1 /*
2 ** ###################################################################
3 **     Processors:          MIMX8QX1AVLFZ
4 **                          MIMX8QX1AVOFZ
5 **
6 **     Compilers:           GNU C Compiler
7 **                          IAR ANSI C/C++ Compiler for ARM
8 **                          Keil ARM C/C++ Compiler
9 **
10 **     Reference manual:    IMX8DQXPRM, Rev. E, 6/2019
11 **     Version:             rev. 4.0, 2020-06-19
12 **     Build:               b200825
13 **
14 **     Abstract:
15 **         CMSIS Peripheral Access Layer for MIMX8QX1_cm4
16 **
17 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
18 **     Copyright 2016-2020 NXP
19 **     All rights reserved.
20 **
21 **     SPDX-License-Identifier: BSD-3-Clause
22 **
23 **     http:                 www.nxp.com
24 **     mail:                 support@nxp.com
25 **
26 **     Revisions:
27 **     - rev. 1.0 (2016-06-02)
28 **         Initial version.
29 **     - rev. 2.0 (2017-08-23)
30 **         RevA Header EAR
31 **     - rev. 3.0 (2018-08-22)
32 **         RevB Header EAR
33 **     - rev. 4.0 (2020-06-19)
34 **         RevC Header RFP
35 **
36 ** ###################################################################
37 */
38 
39 /*!
40  * @file MIMX8QX1_cm4.h
41  * @version 4.0
42  * @date 2020-06-19
43  * @brief CMSIS Peripheral Access Layer for MIMX8QX1_cm4
44  *
45  * CMSIS Peripheral Access Layer for MIMX8QX1_cm4
46  */
47 
48 #ifndef _MIMX8QX1_CM4_H_
49 #define _MIMX8QX1_CM4_H_                         /**< Symbol preventing repeated inclusion */
50 
51 /** Memory map major version (memory maps with equal major version number are
52  * compatible) */
53 #define MCU_MEM_MAP_VERSION 0x0400U
54 /** Memory map minor version */
55 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
56 
57 
58 /* ----------------------------------------------------------------------------
59    -- Interrupt vector numbers
60    ---------------------------------------------------------------------------- */
61 
62 /*!
63  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
64  * @{
65  */
66 
67 /** Interrupt Number Definitions */
68 #define NUMBER_OF_INT_VECTORS 611                /**< Number of interrupts in the Vector table */
69 
70 typedef enum IRQn {
71   /* Auxiliary constants */
72   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
73 
74   /* Core interrupts */
75   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
76   HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
77   MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
78   BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
79   UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
80   SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
81   DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
82   PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
83   SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
84 
85   /* Device specific interrupts */
86   Reserved16_IRQn              = 0,                /**< Reserved */
87   Reserved17_IRQn              = 1,                /**< Reserved */
88   Reserved18_IRQn              = 2,                /**< Reserved */
89   Reserved19_IRQn              = 3,                /**< Reserved */
90   Reserved20_IRQn              = 4,                /**< Reserved */
91   M4_MCM_IRQn                  = 5,                /**< MCM IRQ */
92   Reserved22_IRQn              = 6,                /**< Reserved */
93   Reserved23_IRQn              = 7,                /**< Reserved */
94   Reserved24_IRQn              = 8,                /**< Reserved */
95   Reserved25_IRQn              = 9,                /**< Reserved */
96   Reserved26_IRQn              = 10,               /**< Reserved */
97   Reserved27_IRQn              = 11,               /**< Reserved */
98   Reserved28_IRQn              = 12,               /**< Reserved */
99   Reserved29_IRQn              = 13,               /**< Reserved */
100   Reserved30_IRQn              = 14,               /**< Reserved */
101   Reserved31_IRQn              = 15,               /**< Reserved */
102   Reserved32_IRQn              = 16,               /**< Reserved */
103   Reserved33_IRQn              = 17,               /**< Reserved */
104   Reserved34_IRQn              = 18,               /**< Reserved */
105   M4_TPM_IRQn                  = 19,               /**< Timer PWM Module */
106   Reserved36_IRQn              = 20,               /**< Reserved */
107   Reserved37_IRQn              = 21,               /**< Reserved */
108   M4_LPIT_IRQn                 = 22,               /**< Low-Power Periodic Interrupt Timer */
109   Reserved39_IRQn              = 23,               /**< Reserved */
110   Reserved40_IRQn              = 24,               /**< Reserved */
111   M4_LPUART_IRQn               = 25,               /**< Low Power UART */
112   Reserved42_IRQn              = 26,               /**< Reserved */
113   M4_LPI2C_IRQn                = 27,               /**< Low-Power I2C - Logical OR of master and slave interrupts */
114   Reserved44_IRQn              = 28,               /**< Reserved */
115   M4_MU0_B0_IRQn               = 29,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */
116   Reserved46_IRQn              = 30,               /**< Reserved */
117   Reserved47_IRQn              = 31,               /**< Reserved */
118   IRQSTEER_0_IRQn              = 32,               /**< External interrupt 0 */
119   IRQSTEER_1_IRQn              = 33,               /**< External interrupt 1 */
120   IRQSTEER_2_IRQn              = 34,               /**< External interrupt 2 */
121   IRQSTEER_3_IRQn              = 35,               /**< External interrupt 3 */
122   IRQSTEER_4_IRQn              = 36,               /**< External interrupt 4 */
123   IRQSTEER_5_IRQn              = 37,               /**< External interrupt 5 */
124   IRQSTEER_6_IRQn              = 38,               /**< External interrupt 6 */
125   IRQSTEER_7_IRQn              = 39,               /**< External interrupt 7 */
126   Reserved56_IRQn              = 40,               /**< Reserved */
127   Reserved57_IRQn              = 41,               /**< Reserved */
128   Reserved58_IRQn              = 42,               /**< Reserved */
129   Reserved59_IRQn              = 43,               /**< Reserved */
130   M4_MU0_B1_IRQn               = 44,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */
131   M4_MU0_B2_IRQn               = 45,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */
132   M4_MU0_B3_IRQn               = 46,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */
133   Reserved63_IRQn              = 47,               /**< Reserved */
134   Reserved64_IRQn              = 48,               /**< Reserved */
135   M4_MU1_A_IRQn                = 49,               /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */
136   M4_SW_IRQn                   = 50,               /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */
137   A35_NINTERRIRQ_IRQn          = 83,               /**< Shared Int Source nINTERRIRQ from A35 Sub-System */
138   A35_NEXTERRIRQ_IRQn          = 84,               /**< Shared Int Source nEXTERRIRQ from A35 Sub-System */
139   M4_INT_OUT0_IRQn             = 99,               /**< Shared Int Source INT_OUT[0] from M4 Sub-System */
140   M4_INT_OUT1_IRQn             = 100,              /**< Shared Int Source INT_OUT[1] from M4 Sub-System */
141   M4_INT_OUT2_IRQn             = 101,              /**< Shared Int Source INT_OUT[2] from M4 Sub-System */
142   M4_INT_OUT3_IRQn             = 102,              /**< Shared Int Source INT_OUT[3] from M4 Sub-System */
143   M4_INT_OUT4_IRQn             = 103,              /**< Shared Int Source INT_OUT[4] from M4 Sub-System */
144   M4_INT_OUT5_IRQn             = 104,              /**< Shared Int Source INT_OUT[5] from M4 Sub-System */
145   M4_INT_OUT6_IRQn             = 105,              /**< Shared Int Source INT_OUT[6] from M4 Sub-System */
146   M4_INT_OUT7_IRQn             = 106,              /**< Shared Int Source INT_OUT[7] from M4 Sub-System */
147   DISPLAY0_INT_OUT0_IRQn       = 123,              /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */
148   DISPLAY0_INT_OUT1_IRQn       = 124,              /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */
149   DISPLAY0_INT_OUT2_IRQn       = 125,              /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */
150   DISPLAY0_INT_OUT3_IRQn       = 126,              /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */
151   DISPLAY0_INT_OUT4_IRQn       = 127,              /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */
152   DISPLAY0_INT_OUT5_IRQn       = 128,              /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */
153   DISPLAY0_INT_OUT6_IRQn       = 129,              /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */
154   DISPLAY0_INT_OUT7_IRQn       = 130,              /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */
155   DISPLAY0_RESERVED_IRQn       = 131,              /**< Shared Int Source Reserved from Display0 Sub-System */
156   DISPLAY0_INT_OUT9_IRQn       = 132,              /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */
157   DISPLAY0_INT_OUT10_IRQn      = 133,              /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */
158   DISPLAY0_INT_OUT11_IRQn      = 134,              /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */
159   DISPLAY0_INT_OUT12_IRQn      = 135,              /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */
160   MIPI_DSI0_INT_OUT_IRQn       = 142,              /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */
161   MIPI_DSI1_INT_OUT_IRQn       = 143,              /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */
162   LCD_MOD_INT_IRQn             = 145,              /**< Shared Int Source INT_OUT from ADMA Sub-System */
163   LCD_PWM_INT_IRQn             = 146,              /**< Shared Int Source INT_OUT from ADMA Sub-System */
164   GPU0_XAQ2_INTR_IRQn          = 147,              /**< Shared Int Source xaq2_intr from GPU0 Sub-System */
165   ADMA_EDMA2_INT_IRQn          = 149,              /**< Shared Int Source eDMA2_INT from ADMA Sub-System */
166   ADMA_EDMA2_ERR_INT_IRQn      = 150,              /**< Shared Int Source eDMA2_ERR_INT from ADMA Sub-System */
167   ADMA_EDMA3_INT_IRQn          = 151,              /**< Shared Int Source eDMA3_INT from ADMA Sub-System */
168   ADMA_EDMA3_ERR_INT_IRQn      = 152,              /**< Shared Int Source eDMA3_ERR_INT from ADMA Sub-System */
169   LSIO_GPT0_INT_IRQn           = 163,              /**< Shared Int Source GPT0_INT from LSIO Sub-System */
170   LSIO_GPT1_INT_IRQn           = 164,              /**< Shared Int Source GPT1_INT from LSIO Sub-System */
171   LSIO_GPT2_INT_IRQn           = 165,              /**< Shared Int Source GPT2_INT from LSIO Sub-System */
172   LSIO_GPT3_INT_IRQn           = 166,              /**< Shared Int Source GPT3_INT from LSIO Sub-System */
173   LSIO_GPT4_INT_IRQn           = 167,              /**< Shared Int Source GPT4_INT from LSIO Sub-System */
174   LSIO_KPP_INT_IRQn            = 168,              /**< Shared Int Source KPP_INT from LSIO Sub-System */
175   LSIO_OCTASPI0_INT_IRQn       = 175,              /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */
176   LSIO_OCTASPI1_INT_IRQn       = 176,              /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */
177   LSIO_PWM0_INT_IRQn           = 177,              /**< Shared Int Source PWM0_INT from LSIO Sub-System */
178   LSIO_PWM1_INT_IRQn           = 178,              /**< Shared Int Source PWM1_INT from LSIO Sub-System */
179   LSIO_PWM2_INT_IRQn           = 179,              /**< Shared Int Source PWM2_INT from LSIO Sub-System */
180   LSIO_PWM3_INT_IRQn           = 180,              /**< Shared Int Source PWM3_INT from LSIO Sub-System */
181   LSIO_PWM4_INT_IRQn           = 181,              /**< Shared Int Source PWM4_INT from LSIO Sub-System */
182   LSIO_PWM5_INT_IRQn           = 182,              /**< Shared Int Source PWM5_INT from LSIO Sub-System */
183   LSIO_PWM6_INT_IRQn           = 183,              /**< Shared Int Source PWM6_INT from LSIO Sub-System */
184   LSIO_PWM7_INT_IRQn           = 184,              /**< Shared Int Source PWM7_INT from LSIO Sub-System */
185   HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185,              /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */
186   HSIO_PCIEB_CLK_REQ_INT_IRQn  = 186,              /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */
187   HSIO_PCIEB_DMA_INT_IRQn      = 187,              /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */
188   HSIO_PCIEB_INT_D_IRQn        = 188,              /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */
189   HSIO_PCIEB_INT_C_IRQn        = 189,              /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */
190   HSIO_PCIEB_INT_B_IRQn        = 190,              /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */
191   HSIO_PCIEB_INT_A_IRQn        = 191,              /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */
192   HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192,              /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */
193   HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193,              /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */
194   HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194,              /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */
195   SCU_INT_OUT0_IRQn            = 195,              /**< Shared Int Source INT_OUT[0] from SCU Sub-System */
196   SCU_INT_OUT1_IRQn            = 196,              /**< Shared Int Source INT_OUT[1] from SCU Sub-System */
197   SCU_INT_OUT2_IRQn            = 197,              /**< Shared Int Source INT_OUT[2] from SCU Sub-System */
198   SCU_INT_OUT3_IRQn            = 198,              /**< Shared Int Source INT_OUT[3] from SCU Sub-System */
199   SCU_INT_OUT4_IRQn            = 199,              /**< Shared Int Source INT_OUT[4] from SCU Sub-System */
200   SCU_INT_OUT5_IRQn            = 200,              /**< Shared Int Source INT_OUT[5] from SCU Sub-System */
201   SCU_INT_OUT6_IRQn            = 201,              /**< Shared Int Source INT_OUT[6] from SCU Sub-System */
202   SCU_INT_OUT7_IRQn            = 202,              /**< Shared Int Source INT_OUT[7] from SCU Sub-System */
203   SCU_SYS_COUNT_INT0_IRQn      = 203,              /**< Shared Int Source SYS_COUNT_INT0 from SCU Sub-System */
204   SCU_SYS_COUNT_INT1_IRQn      = 204,              /**< Shared Int Source SYS_COUNT_INT1 from SCU Sub-System */
205   SCU_SYS_COUNT_INT2_IRQn      = 205,              /**< Shared Int Source SYS_COUNT_INT2 from SCU Sub-System */
206   SCU_SYS_COUNT_INT3_IRQn      = 206,              /**< Shared Int Source SYS_COUNT_INT3 from SCU Sub-System */
207   DRC_ECC_CORRECT_INT_IRQn     = 211,              /**< Shared Int Source ECC_CORRECT_INT from DRC Sub-System */
208   DRC_ECC_NCORRECT_INT_IRQn    = 212,              /**< Shared Int Source ECC_NCORRECT_INT from DRC Sub-System */
209   DRC_SBR_DONE_INT_IRQn        = 213,              /**< Shared Int Source SBR_DONE_INT from DRC Sub-System */
210   DRC_PERF_CNT_INT_IRQn        = 214,              /**< Shared Int Source PERF_CNT_INT from DRC Sub-System */
211   LSIO_GPIO_INT0_IRQn          = 219,              /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */
212   LSIO_GPIO_INT1_IRQn          = 220,              /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */
213   LSIO_GPIO_INT2_IRQn          = 221,              /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */
214   LSIO_GPIO_INT3_IRQn          = 222,              /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */
215   LSIO_GPIO_INT4_IRQn          = 223,              /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */
216   LSIO_GPIO_INT5_IRQn          = 224,              /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */
217   LSIO_GPIO_INT6_IRQn          = 225,              /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */
218   LSIO_GPIO_INT7_IRQn          = 226,              /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */
219   LSIO_MU0_INT_IRQn            = 259,              /**< Shared Int Source MU0_INT from LSIO Sub-System */
220   LSIO_MU1_INT_IRQn            = 260,              /**< Shared Int Source MU1_INT from LSIO Sub-System */
221   LSIO_MU2_INT_IRQn            = 261,              /**< Shared Int Source MU2_INT from LSIO Sub-System */
222   LSIO_MU3_INT_IRQn            = 262,              /**< Shared Int Source MU3_INT from LSIO Sub-System */
223   LSIO_MU4_INT_IRQn            = 263,              /**< Shared Int Source MU4_INT from LSIO Sub-System */
224   LSIO_MU5_INT_A_IRQn          = 267,              /**< Shared Int Source MU5_INT_A from LSIO Sub-System */
225   LSIO_MU6_INT_A_IRQn          = 268,              /**< Shared Int Source MU6_INT_A from LSIO Sub-System */
226   LSIO_MU7_INT_A_IRQn          = 269,              /**< Shared Int Source MU7_INT_A from LSIO Sub-System */
227   LSIO_MU8_INT_A_IRQn          = 270,              /**< Shared Int Source MU8_INT_A from LSIO Sub-System */
228   LSIO_MU9_INT_A_IRQn          = 271,              /**< Shared Int Source MU9_INT_A from LSIO Sub-System */
229   LSIO_MU10_INT_A_IRQn         = 272,              /**< Shared Int Source MU10_INT_A from LSIO Sub-System */
230   LSIO_MU11_INT_A_IRQn         = 273,              /**< Shared Int Source MU11_INT_A from LSIO Sub-System */
231   LSIO_MU12_INT_A_IRQn         = 274,              /**< Shared Int Source MU12_INT_A from LSIO Sub-System */
232   LSIO_MU13_INT_A_IRQn         = 275,              /**< Shared Int Source MU13_INT_A from LSIO Sub-System */
233   LSIO_MU5_INT_B_IRQn          = 283,              /**< Shared Int Source MU5_INT_B from LSIO Sub-System */
234   LSIO_MU6_INT_B_IRQn          = 284,              /**< Shared Int Source MU6_INT_B from LSIO Sub-System */
235   LSIO_MU7_INT_B_IRQn          = 285,              /**< Shared Int Source MU7_INT_B from LSIO Sub-System */
236   LSIO_MU8_INT_B_IRQn          = 286,              /**< Shared Int Source MU8_INT_B from LSIO Sub-System */
237   LSIO_MU9_INT_B_IRQn          = 287,              /**< Shared Int Source MU9_INT_B from LSIO Sub-System */
238   LSIO_MU10_INT_B_IRQn         = 288,              /**< Shared Int Source MU10_INT_B from LSIO Sub-System */
239   LSIO_MU11_INT_B_IRQn         = 289,              /**< Shared Int Source MU11_INT_B from LSIO Sub-System */
240   LSIO_MU12_INT_B_IRQn         = 290,              /**< Shared Int Source MU12_INT_B from LSIO Sub-System */
241   LSIO_MU13_INT_B_IRQn         = 291,              /**< Shared Int Source MU13_INT_B from LSIO Sub-System */
242   ADMA_SPI0_INT_IRQn           = 299,              /**< Shared Int Source SPI0_INT from ADMA Sub-System */
243   ADMA_SPI1_INT_IRQn           = 300,              /**< Shared Int Source SPI1_INT from ADMA Sub-System */
244   ADMA_SPI2_INT_IRQn           = 301,              /**< Shared Int Source SPI2_INT from ADMA Sub-System */
245   ADMA_SPI3_INT_IRQn           = 302,              /**< Shared Int Source SPI3_INT from ADMA Sub-System */
246   ADMA_I2C0_INT_IRQn           = 303,              /**< Shared Int Source I2C0_INT from ADMA Sub-System */
247   ADMA_I2C1_INT_IRQn           = 304,              /**< Shared Int Source I2C1_INT from ADMA Sub-System */
248   ADMA_I2C2_INT_IRQn           = 305,              /**< Shared Int Source I2C2_INT from ADMA Sub-System */
249   ADMA_I2C3_INT_IRQn           = 306,              /**< Shared Int Source I2C3_INT from ADMA Sub-System */
250   ADMA_UART0_INT_IRQn          = 308,              /**< Shared Int Source UART0_INT from ADMA Sub-System */
251   ADMA_UART1_INT_IRQn          = 309,              /**< Shared Int Source UART1_INT from ADMA Sub-System */
252   ADMA_UART2_INT_IRQn          = 310,              /**< Shared Int Source UART2_INT from ADMA Sub-System */
253   ADMA_UART3_INT_IRQn          = 311,              /**< Shared Int Source UART3_INT from ADMA Sub-System */
254   CONNECTIVITY_USDHC0_INT_IRQn = 315,              /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */
255   CONNECTIVITY_USDHC1_INT_IRQn = 316,              /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */
256   CONNECTIVITY_USDHC2_INT_IRQn = 317,              /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */
257   ADMA_FLEXCAN0_INT_IRQn       = 318,              /**< Shared Int Source FlexCAN0_INT from ADMA Sub-System */
258   ADMA_FLEXCAN1_INT_IRQn       = 319,              /**< Shared Int Source FlexCAN1_INT from ADMA Sub-System */
259   ADMA_FLEXCAN2_INT_IRQn       = 320,              /**< Shared Int Source FlexCAN2_INT from ADMA Sub-System */
260   ADMA_FTM0_INT_IRQn           = 321,              /**< Shared Int Source FTM0_INT from ADMA Sub-System */
261   ADMA_FTM1_INT_IRQn           = 322,              /**< Shared Int Source FTM1_INT from ADMA Sub-System */
262   ADMA_ADC0_INT_IRQn           = 323,              /**< Shared Int Source ADC0_INT from ADMA Sub-System */
263   ADMA_EXTERNAL_DMA_INT_0_IRQn = 325,              /**< Shared Int Source EXTERNAL_DMA_INT_0 from ADMA Sub-System */
264   ADMA_EXTERNAL_DMA_INT_1_IRQn = 326,              /**< Shared Int Source EXTERNAL_DMA_INT_1 from ADMA Sub-System */
265   ADMA_EXTERNAL_DMA_INT_2_IRQn = 327,              /**< Shared Int Source EXTERNAL_DMA_INT_2 from ADMA Sub-System */
266   ADMA_EXTERNAL_DMA_INT_3_IRQn = 328,              /**< Shared Int Source EXTERNAL_DMA_INT_3 from ADMA Sub-System */
267   ADMA_EXTERNAL_DMA_INT_4_IRQn = 329,              /**< Shared Int Source EXTERNAL_DMA_INT_4 from ADMA Sub-System */
268   ADMA_EXTERNAL_DMA_INT_5_IRQn = 330,              /**< Shared Int Source EXTERNAL_DMA_INT_5 from ADMA Sub-System */
269   CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339,        /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */
270   CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340,        /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */
271   CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341,  /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */
272   CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342,         /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */
273   CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343,        /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */
274   CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344,        /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */
275   CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345,  /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */
276   CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346,         /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */
277   CONNECTIVITY_DTCP_INT_IRQn   = 347,              /**< Shared Int Source DTCP_INT from Connectivity Sub-System */
278   CONNECTIVITY_MLB_INT_IRQn    = 348,              /**< Shared Int Source MLB_INT from Connectivity Sub-System */
279   CONNECTIVITY_MLB_AHB_INT_IRQn = 349,             /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */
280   CONNECTIVITY_USB_OTG_INT_IRQn = 350,             /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */
281   CONNECTIVITY_USB_HOST_INT_IRQn = 351,            /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */
282   CONNECTIVITY_UTMI_INT_IRQn   = 352,              /**< Shared Int Source UTMI_INT from Connectivity Sub-System */
283   CONNECTIVITY_WAKEUP_INT_IRQn = 353,              /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */
284   CONNECTIVITY_USB3_INT_IRQn   = 354,              /**< Shared Int Source USB3_INT from Connectivity Sub-System */
285   CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355,        /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */
286   CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356,       /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */
287   CONNECTIVITY_APBHDMA_IRQn    = 357,              /**< Shared Int Source APBHDMA from Connectivity Sub-System */
288   CONNECTIVITY_DMA_INT_IRQn    = 358,              /**< Shared Int Source DMA_INT from Connectivity Sub-System */
289   CONNECTIVITY_DMA_ERR_INT_IRQn = 359,             /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */
290   IMAGING_MSI_INT_IRQn         = 371,              /**< Shared Int Source MSI_INT from Imaging Sub-System */
291   IMAGING_PDMA_STREAM0_INT_IRQn = 380,             /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */
292   IMAGING_PDMA_STREAM1_INT_IRQn = 381,             /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */
293   IMAGING_PDMA_STREAM2_INT_IRQn = 382,             /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */
294   IMAGING_PDMA_STREAM3_INT_IRQn = 383,             /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */
295   IMAGING_PDMA_STREAM4_INT_IRQn = 384,             /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */
296   IMAGING_PDMA_STREAM5_INT_IRQn = 385,             /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */
297   IMAGING_PDMA_STREAM6_INT_IRQn = 386,             /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */
298   IMAGING_PDMA_STREAM7_INT_IRQn = 387,             /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */
299   IMAGING_MJPEG_ENC0_INT_IRQn  = 388,              /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */
300   IMAGING_MJPEG_ENC1_INT_IRQn  = 389,              /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */
301   IMAGING_MJPEG_ENC2_INT_IRQn  = 390,              /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */
302   IMAGING_MJPEG_ENC3_INT_IRQn  = 391,              /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */
303   IMAGING_MJPEG_DEC0_INT_IRQn  = 392,              /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */
304   IMAGING_MJPEG_DEC1_INT_IRQn  = 393,              /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */
305   IMAGING_MJPEG_DEC2_INT_IRQn  = 394,              /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */
306   IMAGING_MJPEG_DEC3_INT_IRQn  = 395,              /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */
307   ADMA_SAI0_MOD_INT_IRQn       = 397,              /**< Shared Int Source SAI0_MOD_INT from ADMA Sub-System */
308   ADMA_SAI0_DMA_INT_IRQn       = 398,              /**< Shared Int Source SAI0_DMA_INT from ADMA Sub-System */
309   ADMA_SAI1_MOD_INT_IRQn       = 399,              /**< Shared Int Source SAI1_MOD_INT from ADMA Sub-System */
310   ADMA_SAI1_DMA_INT_IRQn       = 400,              /**< Shared Int Source SAI1_DMA_INT from ADMA Sub-System */
311   ADMA_SAI2_MOD_INT_IRQn       = 401,              /**< Shared Int Source SAI2_MOD_INT from ADMA Sub-System */
312   ADMA_SAI2_DMA_INT_IRQn       = 402,              /**< Shared Int Source SAI2_DMA_INT from ADMA Sub-System */
313   MIPI_CSI0_OUT_INT_IRQn       = 403,              /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */
314   ADMA_SAI3_MOD_INT_IRQn       = 406,              /**< Shared Int Source SAI3_MOD_INT from ADMA Sub-System */
315   ADMA_SAI3_DMA_INT_IRQn       = 407,              /**< Shared Int Source SAI3_DMA_INT from ADMA Sub-System */
316   ADMA_SAI4_MOD_INT_IRQn       = 412,              /**< Shared Int Source SAI4_MOD_INT from ADMA Sub-System */
317   ADMA_SAI4_DMA_INT_IRQn       = 413,              /**< Shared Int Source SAI4_DMA_INT from ADMA Sub-System */
318   ADMA_SAI5_MOD_INT_IRQn       = 414,              /**< Shared Int Source SAI5_MOD_INT from ADMA Sub-System */
319   ADMA_SAI5_DMA_INT_IRQn       = 415,              /**< Shared Int Source SAI5_DMA_INT from ADMA Sub-System */
320   ADMA_SPI0_MOD_INT_IRQn       = 419,              /**< Shared Int Source SPI0_MOD_INT from ADMA Sub-System */
321   ADMA_SPI1_MOD_INT_IRQn       = 420,              /**< Shared Int Source SPI1_MOD_INT from ADMA Sub-System */
322   ADMA_SPI2_MOD_INT_IRQn       = 421,              /**< Shared Int Source SPI2_MOD_INT from ADMA Sub-System */
323   ADMA_SPI3_MOD_INT_IRQn       = 422,              /**< Shared Int Source SPI3_MOD_INT from ADMA Sub-System */
324   ADMA_I2C0_MOD_INT_IRQn       = 423,              /**< Shared Int Source I2C0_MOD_INT from ADMA Sub-System */
325   ADMA_I2C1_MOD_INT_IRQn       = 424,              /**< Shared Int Source I2C1_MOD_INT from ADMA Sub-System */
326   ADMA_I2C2_MOD_INT_IRQn       = 425,              /**< Shared Int Source I2C2_MOD_INT from ADMA Sub-System */
327   ADMA_I2C3_MOD_INT_IRQn       = 426,              /**< Shared Int Source I2C3_MOD_INT from ADMA Sub-System */
328   ADMA_UART0_MOD_INT_IRQn      = 428,              /**< Shared Int Source UART0_MOD_INT from ADMA Sub-System */
329   ADMA_UART1_MOD_INT_IRQn      = 429,              /**< Shared Int Source UART1_MOD_INT from ADMA Sub-System */
330   ADMA_UART2_MOD_INT_IRQn      = 430,              /**< Shared Int Source UART2_MOD_INT from ADMA Sub-System */
331   ADMA_UART3_MOD_INT_IRQn      = 431,              /**< Shared Int Source UART3_MOD_INT from ADMA Sub-System */
332   ADMA_FLEXCAN0_MOD_INT_IRQn   = 435,              /**< Shared Int Source FLEXCAN0_MOD_INT from ADMA Sub-System */
333   ADMA_FLEXCAN1_MOD_INT_IRQn   = 436,              /**< Shared Int Source FLEXCAN1_MOD_INT from ADMA Sub-System */
334   ADMA_FLEXCAN2_MOD_INT_IRQn   = 437,              /**< Shared Int Source FLEXCAN2_MOD_INT from ADMA Sub-System */
335   ADMA_FTM0_MOD_INT_IRQn       = 438,              /**< Shared Int Source FTM0_MOD_INT from ADMA Sub-System */
336   ADMA_FTM1_MOD_INT_IRQn       = 439,              /**< Shared Int Source FTM1_MOD_INT from ADMA Sub-System */
337   ADMA_ADC0_MOD_INT_IRQn       = 440,              /**< Shared Int Source ADC0_MOD_INT from ADMA Sub-System */
338   ADMA_FLEXCAN0_DMA_INT_IRQn   = 442,              /**< Shared Int Source FLEXCAN0_DMA_INT from ADMA Sub-System */
339   ADMA_FLEXCAN1_DMA_INT_IRQn   = 443,              /**< Shared Int Source FLEXCAN1_DMA_INT from ADMA Sub-System */
340   ADMA_FLEXCAN2_DMA_INT_IRQn   = 444,              /**< Shared Int Source FLEXCAN2_DMA_INT from ADMA Sub-System */
341   ADMA_FTM0_DMA_INT_IRQn       = 445,              /**< Shared Int Source FTM0_DMA_INT from ADMA Sub-System */
342   ADMA_FTM1_DMA_INT_IRQn       = 446,              /**< Shared Int Source FTM1_DMA_INT from ADMA Sub-System */
343   ADMA_ADC0_DMA_INT_IRQn       = 447,              /**< Shared Int Source ADC0_DMA_INT from ADMA Sub-System */
344   ADMA_EDMA0_INT_IRQn          = 451,              /**< Shared Int Source eDMA0_INT from ADMA Sub-System */
345   ADMA_EDMA0_ERR_INT_IRQn      = 452,              /**< Shared Int Source eDMA0_ERR_INT from ADMA Sub-System */
346   ADMA_EDMA1_INT_IRQn          = 453,              /**< Shared Int Source eDMA1_INT from ADMA Sub-System */
347   ADMA_EDMA1_ERR_INT_IRQn      = 454,              /**< Shared Int Source eDMA1_ERR_INT from ADMA Sub-System */
348   ADMA_ASRC0_INT1_IRQn         = 455,              /**< Shared Int Source ASRC0_INT1 from ADMA Sub-System */
349   ADMA_ASRC0_INT2_IRQn         = 456,              /**< Shared Int Source ASRC0_INT2 from ADMA Sub-System */
350   ADMA_DMA0_CH0_INT_IRQn       = 457,              /**< Shared Int Source DMA0_CH0_INT from ADMA Sub-System */
351   ADMA_DMA0_CH1_INT_IRQn       = 458,              /**< Shared Int Source DMA0_CH1_INT from ADMA Sub-System */
352   ADMA_DMA0_CH2_INT_IRQn       = 459,              /**< Shared Int Source DMA0_CH2_INT from ADMA Sub-System */
353   ADMA_DMA0_CH3_INT_IRQn       = 460,              /**< Shared Int Source DMA0_CH3_INT from ADMA Sub-System */
354   ADMA_DMA0_CH4_INT_IRQn       = 461,              /**< Shared Int Source DMA0_CH4_INT from ADMA Sub-System */
355   ADMA_DMA0_CH5_INT_IRQn       = 462,              /**< Shared Int Source DMA0_CH5_INT from ADMA Sub-System */
356   ADMA_ASRC1_INT1_IRQn         = 463,              /**< Shared Int Source ASRC1_INT1 from ADMA Sub-System */
357   ADMA_ASRC1_INT2_IRQn         = 464,              /**< Shared Int Source ASRC1_INT2 from ADMA Sub-System */
358   ADMA_DMA1_CH0_INT_IRQn       = 465,              /**< Shared Int Source DMA1_CH0_INT from ADMA Sub-System */
359   ADMA_DMA1_CH1_INT_IRQn       = 466,              /**< Shared Int Source DMA1_CH1_INT from ADMA Sub-System */
360   ADMA_DMA1_CH2_INT_IRQn       = 467,              /**< Shared Int Source DMA1_CH2_INT from ADMA Sub-System */
361   ADMA_DMA1_CH3_INT_IRQn       = 468,              /**< Shared Int Source DMA1_CH3_INT from ADMA Sub-System */
362   ADMA_DMA1_CH4_INT_IRQn       = 469,              /**< Shared Int Source DMA1_CH4_INT from ADMA Sub-System */
363   ADMA_DMA1_CH5_INT_IRQn       = 470,              /**< Shared Int Source DMA1_CH5_INT from ADMA Sub-System */
364   ADMA_ESAI0_INT_IRQn          = 471,              /**< Shared Int Source ESAI0_INT from ADMA Sub-System */
365   ADMA_GPT0_INT_IRQn           = 474,              /**< Shared Int Source GPT0_INT from ADMA Sub-System */
366   ADMA_GPT1_INT_IRQn           = 475,              /**< Shared Int Source GPT1_INT from ADMA Sub-System */
367   ADMA_GPT2_INT_IRQn           = 476,              /**< Shared Int Source GPT2_INT from ADMA Sub-System */
368   ADMA_GPT3_INT_IRQn           = 477,              /**< Shared Int Source GPT3_INT from ADMA Sub-System */
369   ADMA_GPT4_INT_IRQn           = 478,              /**< Shared Int Source GPT4_INT from ADMA Sub-System */
370   ADMA_GPT5_INT_IRQn           = 479,              /**< Shared Int Source GPT5_INT from ADMA Sub-System */
371   ADMA_SAI0_INT_IRQn           = 480,              /**< Shared Int Source SAI0_INT from ADMA Sub-System */
372   ADMA_SAI1_INT_IRQn           = 481,              /**< Shared Int Source SAI1_INT from ADMA Sub-System */
373   ADMA_SAI2_INT_IRQn           = 482,              /**< Shared Int Source SAI2_INT from ADMA Sub-System */
374   ADMA_SAI3_INT_IRQn           = 483,              /**< Shared Int Source SAI3_INT from ADMA Sub-System */
375   ADMA_SAI4_INT_IRQn           = 486,              /**< Shared Int Source SAI4_INT from ADMA Sub-System */
376   ADMA_SAI5_INT_IRQn           = 487,              /**< Shared Int Source SAI5_INT from ADMA Sub-System */
377   ADMA_SPDIF0_RX_INT_IRQn      = 488,              /**< Shared Int Source SPDIF0_RX_INT from ADMA Sub-System */
378   ADMA_SPDIF0_TX_INT_IRQn      = 489,              /**< Shared Int Source SPDIF0_TX_INT from ADMA Sub-System */
379   ADMA_ESAI0_MOD_INT_IRQn      = 492,              /**< Shared Int Source ESAI0_MOD_INT from ADMA Sub-System */
380   ADMA_ESAI0_DMA_INT_IRQn      = 493,              /**< Shared Int Source ESAI0_DMA_INT from ADMA Sub-System */
381   ADMA_SPI0_DMA_RX_INT_IRQn    = 499,              /**< Shared Int Source SPI0_DMA_RX_INT from ADMA Sub-System */
382   ADMA_SPI0_DMA_TX_INT_IRQn    = 500,              /**< Shared Int Source SPI0_DMA_TX_INT from ADMA Sub-System */
383   ADMA_SPI1_DMA_RX_INT_IRQn    = 501,              /**< Shared Int Source SPI1_DMA_RX_INT from ADMA Sub-System */
384   ADMA_SPI1_DMA_TX_INT_IRQn    = 502,              /**< Shared Int Source SPI1_DMA_TX_INT from ADMA Sub-System */
385   ADMA_SPI2_DMA_RX_INT_IRQn    = 503,              /**< Shared Int Source SPI2_DMA_RX_INT from ADMA Sub-System */
386   ADMA_SPI2_DMA_TX_INT_IRQn    = 504,              /**< Shared Int Source SPI2_DMA_TX_INT from ADMA Sub-System */
387   ADMA_SPI3_DMA_RX_INT_IRQn    = 505,              /**< Shared Int Source SPI3_DMA_RX_INT from ADMA Sub-System */
388   ADMA_SPI3_DMA_TX_INT_IRQn    = 506,              /**< Shared Int Source SPI3_DMA_TX_INT from ADMA Sub-System */
389   ADMA_I2C0_DMA_RX_INT_IRQn    = 507,              /**< Shared Int Source I2C0_DMA_RX_INT from ADMA Sub-System */
390   ADMA_I2C0_DMA_TX_INT_IRQn    = 508,              /**< Shared Int Source I2C0_DMA_TX_INT from ADMA Sub-System */
391   ADMA_I2C1_DMA_RX_INT_IRQn    = 509,              /**< Shared Int Source I2C1_DMA_RX_INT from ADMA Sub-System */
392   ADMA_I2C1_DMA_TX_INT_IRQn    = 510,              /**< Shared Int Source I2C1_DMA_TX_INT from ADMA Sub-System */
393   ADMA_I2C2_DMA_RX_INT_IRQn    = 511,              /**< Shared Int Source I2C2_DMA_RX_INT from ADMA Sub-System */
394   ADMA_I2C2_DMA_TX_INT_IRQn    = 512,              /**< Shared Int Source I2C2_DMA_TX_INT from ADMA Sub-System */
395   ADMA_I2C3_DMA_RX_INT_IRQn    = 513,              /**< Shared Int Source I2C3_DMA_RX_INT from ADMA Sub-System */
396   ADMA_I2C3_DMA_TX_INT_IRQn    = 514,              /**< Shared Int Source I2C3_DMA_TX_INT from ADMA Sub-System */
397   ADMA_UART0_DMA_RX_INT_IRQn   = 517,              /**< Shared Int Source UART0_DMA_RX_INT from ADMA Sub-System */
398   ADMA_UART0_DMA_TX_INT_IRQn   = 518,              /**< Shared Int Source UART0_DMA_TX_INT from ADMA Sub-System */
399   ADMA_UART1_DMA_RX_INT_IRQn   = 519,              /**< Shared Int Source UART1_DMA_RX_INT from ADMA Sub-System */
400   ADMA_UART1_DMA_TX_INT_IRQn   = 520,              /**< Shared Int Source UART1_DMA_TX_INT from ADMA Sub-System */
401   ADMA_UART2_DMA_RX_INT_IRQn   = 521,              /**< Shared Int Source UART2_DMA_RX_INT from ADMA Sub-System */
402   ADMA_UART2_DMA_TX_INT_IRQn   = 522,              /**< Shared Int Source UART2_DMA_TX_INT from ADMA Sub-System */
403   ADMA_UART3_DMA_RX_INT_IRQn   = 523,              /**< Shared Int Source UART3_DMA_RX_INT from ADMA Sub-System */
404   ADMA_UART3_DMA_TX_INT_IRQn   = 524,              /**< Shared Int Source UART3_DMA_TX_INT from ADMA Sub-System */
405   SECURITY_MU1_A_INT_IRQn      = 531,              /**< Shared Int Source MU1_A_INT from Security Sub-System */
406   SECURITY_MU2_A_INT_IRQn      = 532,              /**< Shared Int Source MU2_A_INT from Security Sub-System */
407   SECURITY_MU3_A_INT_IRQn      = 533,              /**< Shared Int Source MU3_A_INT from Security Sub-System */
408   SECURITY_CAAM_INT0_IRQn      = 534,              /**< Shared Int Source CAAM_INT0 from Security Sub-System */
409   SECURITY_CAAM_INT1_IRQn      = 535,              /**< Shared Int Source CAAM_INT1 from Security Sub-System */
410   SECURITY_CAAM_INT2_IRQn      = 536,              /**< Shared Int Source CAAM_INT2 from Security Sub-System */
411   SECURITY_CAAM_INT3_IRQn      = 537,              /**< Shared Int Source CAAM_INT3 from Security Sub-System */
412   SECURITY_CAAM_RTIC_INT_IRQn  = 538,              /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */
413   ADMA_SPDIF0_RX_MOD_INT_IRQn  = 539,              /**< Shared Int Source SPDIF0_RX_MOD_INT from ADMA Sub-System */
414   ADMA_SPDIF0_RX_DMA_INT_IRQn  = 540,              /**< Shared Int Source SPDIF0_RX_DMA_INT from ADMA Sub-System */
415   ADMA_SPDIF0_TX_MOD_INT_IRQn  = 541,              /**< Shared Int Source SPDIF0_TX_MOD_INT from ADMA Sub-System */
416   ADMA_SPDIF0_TX_DMA_INT_IRQn  = 542,              /**< Shared Int Source SPDIF0_TX_DMA_INT from ADMA Sub-System */
417   VPU_VPU_INT_0_IRQn           = 547,              /**< Shared Int Source VPU_INT_0 from VPU Sub-System */
418   VPU_VPU_INT_1_IRQn           = 548,              /**< Shared Int Source VPU_INT_1 from VPU Sub-System */
419   VPU_VPU_INT_2_IRQn           = 549,              /**< Shared Int Source VPU_INT_2 from VPU Sub-System */
420   VPU_VPU_INT_3_IRQn           = 550,              /**< Shared Int Source VPU_INT_3 from VPU Sub-System */
421   VPU_VPU_INT_4_IRQn           = 551,              /**< Shared Int Source VPU_INT_4 from VPU Sub-System */
422   M4_INTMUX_SOURCE_TPM_IRQn    = 564,              /**< INTMUX Input source: TPM Interrupt */
423   M4_INTMUX_SOURCE_LPIT_IRQn   = 567,              /**< INTMUX Input source: LPIT Interrupt */
424   M4_INTMUX_SOURCE_LPUART_IRQn = 570,              /**< INTMUX Input source: LPUART Interrupt */
425   M4_INTMUX_SOURCE_LPI2C_IRQn  = 572,              /**< INTMUX Input source: LPI2C Interrupt */
426   M4_INTMUX_SOURCE_MU0_A3_IRQn = 591,              /**< INTMUX Input source: MU0_A3 Interrupt */
427   M4_INTMUX_SOURCE_MU0_A2_IRQn = 592,              /**< INTMUX Input source: MU0_A2 Interrupt */
428   M4_INTMUX_SOURCE_MU0_A1_IRQn = 593,              /**< INTMUX Input source: MU0_A1 Interrupt */
429   M4_INTMUX_SOURCE_MU0_A0_IRQn = 594               /**< INTMUX Input source: MU0_A0 Interrupt */
430 } IRQn_Type;
431 
432 /*!
433  * @}
434  */ /* end of group Interrupt_vector_numbers */
435 
436 
437 /* ----------------------------------------------------------------------------
438    -- Configuration of the Cortex-M4 Processor and Core Peripherals
439    ---------------------------------------------------------------------------- */
440 
441 /*!
442  * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
443  * @{
444  */
445 
446 #define __CM4_REV                      0x0001    /**< Core revision r0p1 */
447 #define __MPU_PRESENT                  1         /**< MPU present or not */
448 #define __NVIC_PRIO_BITS               4         /**< Number of Bits used for Priority Levels */
449 #define __Vendor_SysTickConfig         0         /**< Set to 1 if different SysTick Config is used */
450 #define __FPU_PRESENT                  1         /**< FPU present or not */
451 
452 #include "core_cm4.h"                  /* Core Peripheral Access Layer */
453 #include "system_MIMX8QX1_cm4.h"       /* Device specific configuration file */
454 
455 /*!
456  * @}
457  */ /* end of group Cortex_Core_Configuration */
458 
459 
460 /* ----------------------------------------------------------------------------
461    -- Device Peripheral Access Layer
462    ---------------------------------------------------------------------------- */
463 
464 /*!
465  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
466  * @{
467  */
468 
469 
470 /*
471 ** Start of section using anonymous unions
472 */
473 
474 #if defined(__ARMCC_VERSION)
475   #if (__ARMCC_VERSION >= 6010050)
476     #pragma clang diagnostic push
477   #else
478     #pragma push
479     #pragma anon_unions
480   #endif
481 #elif defined(__GNUC__)
482   /* anonymous unions are enabled by default */
483 #elif defined(__IAR_SYSTEMS_ICC__)
484   #pragma language=extended
485 #else
486   #error Not supported compiler type
487 #endif
488 
489 /* ----------------------------------------------------------------------------
490    -- ACM Peripheral Access Layer
491    ---------------------------------------------------------------------------- */
492 
493 /*!
494  * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer
495  * @{
496  */
497 
498 /** ACM - Register Layout Typedef */
499 typedef struct {
500        uint8_t RESERVED_0[14680064];
501   __IO uint32_t AUD_CLK0;                          /**< ACM_AUD_CLK0 Register, offset: 0xE00000 */
502        uint8_t RESERVED_1[65532];
503   __IO uint32_t AUD_CLK1;                          /**< ACM_AUD_CLK1 Register, offset: 0xE10000 */
504        uint8_t RESERVED_2[65532];
505   __IO uint32_t MCLKOUT0;                          /**< ACM_MCLKOUT0 Register, offset: 0xE20000 */
506        uint8_t RESERVED_3[65532];
507   __IO uint32_t MCLKOUT1;                          /**< ACM_MCLKOUT1 Register, offset: 0xE30000 */
508        uint8_t RESERVED_4[196604];
509   __IO uint32_t ESAI0_CLK;                         /**< ACM_ESAI0_CLK Register, offset: 0xE60000 */
510        uint8_t RESERVED_5[131068];
511   struct {                                         /* offset: 0xE80000, array step: 0x10000 */
512     __IO uint32_t GPT_CLK;                           /**< ACM_GPT_CLK Register, array offset: 0xE80000, array step: 0x10000 */
513          uint8_t RESERVED_0[65532];
514   } GPT_CLK[6];
515   struct {                                         /* offset: 0xEE0000, array step: 0x10000 */
516     __IO uint32_t SAI_MCLK;                          /**< ACM_SAI_MCLK Register, array offset: 0xEE0000, array step: 0x10000 */
517          uint8_t RESERVED_0[65532];
518   } SAI_MCLK[8];
519        uint8_t RESERVED_6[262144];
520   __IO uint32_t SPDIF0_TX_CLK;                     /**< ACM_SPDIF0_TX_CLK Register, offset: 0xFA0000 */
521        uint8_t RESERVED_7[131068];
522   __IO uint32_t MQS_HMCLK_CLK;                     /**< ACM_MQS_HMCLK_CLK Register, offset: 0xFC0000 */
523 } ACM_Type;
524 
525 /* ----------------------------------------------------------------------------
526    -- ACM Register Masks
527    ---------------------------------------------------------------------------- */
528 
529 /*!
530  * @addtogroup ACM_Register_Masks ACM Register Masks
531  * @{
532  */
533 
534 /*! @name AUD_CLK0 - ACM_AUD_CLK0 Register */
535 /*! @{ */
536 #define ACM_AUD_CLK0_SEL_MASK                    (0x1FU)
537 #define ACM_AUD_CLK0_SEL_SHIFT                   (0U)
538 /*! SEL - Select
539  *  0b00000..ADMA_SLSLICE2
540  *  0b00001..ADMA_SLSLICE3
541  *  0b00010..EXT_AUD_MCLK0
542  *  0b00011..EXT_AUD_MCLK1
543  *  0b00100..ESAI0_RX_CLK
544  *  0b00101..ESAI0_RX_HF_CLKK
545  *  0b00110..ESAI0_TX_CLK
546  *  0b00111..ESAI0_TX_HF_CLK
547  *  0b01000..SPDIF0_RX
548  *  0b01001..SAI0_RX_BCLK
549  *  0b01010..SAI0_TX_BCLK
550  *  0b01011..SAI1_RX_BCLK
551  *  0b01100..SAI1_TX_BCLK
552  *  0b01101..SAI2_RX_BCLK
553  *  0b01110..SAI3_RX_BCLK
554  */
555 #define ACM_AUD_CLK0_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_MASK)
556 /*! @} */
557 
558 /*! @name AUD_CLK1 - ACM_AUD_CLK1 Register */
559 /*! @{ */
560 #define ACM_AUD_CLK1_SEL_MASK                    (0x1FU)
561 #define ACM_AUD_CLK1_SEL_SHIFT                   (0U)
562 /*! SEL - Select
563  *  0b00000..ADMA_SLSLICE2
564  *  0b00001..ADMA_SLSLICE3
565  *  0b00010..EXT_AUD_MCLK0
566  *  0b00011..EXT_AUD_MCLK1
567  *  0b00100..ESAI0_RX_CLK
568  *  0b00101..ESAI0_RX_HF_CLKK
569  *  0b00110..ESAI0_TX_CLK
570  *  0b00111..ESAI0_TX_HF_CLK
571  *  0b01000..SPDIF0_RX
572  *  0b01001..SAI0_RX_BCLK
573  *  0b01010..SAI0_TX_BCLK
574  *  0b01011..SAI1_RX_BCLK
575  *  0b01100..SAI1_TX_BCLK
576  *  0b01101..SAI2_RX_BCLK
577  *  0b01110..SAI3_RX_BCLK
578  */
579 #define ACM_AUD_CLK1_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_MASK)
580 /*! @} */
581 
582 /*! @name MCLKOUT0 - ACM_MCLKOUT0 Register */
583 /*! @{ */
584 #define ACM_MCLKOUT0_SEL_MASK                    (0x7U)
585 #define ACM_MCLKOUT0_SEL_SHIFT                   (0U)
586 /*! SEL - Select
587  *  0b000..ADMA_SLSLICE2
588  *  0b001..ADMA_SLSLICE3
589  *  0b010..Reserved
590  *  0b011..Reserved
591  *  0b100..SPDIF0_RX
592  *  0b101..Reserved
593  *  0b110..Reserved
594  *  0b111..SAI4_RX_BCLK
595  */
596 #define ACM_MCLKOUT0_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_MASK)
597 /*! @} */
598 
599 /*! @name MCLKOUT1 - ACM_MCLKOUT1 Register */
600 /*! @{ */
601 #define ACM_MCLKOUT1_SEL_MASK                    (0x7U)
602 #define ACM_MCLKOUT1_SEL_SHIFT                   (0U)
603 /*! SEL - Select
604  *  0b000..ADMA_SLSLICE2
605  *  0b001..ADMA_SLSLICE3
606  *  0b010..Reserved
607  *  0b011..Reserved
608  *  0b100..SPDIF0_RX
609  *  0b101..Reserved
610  *  0b110..Reserved
611  *  0b111..SAI4_RX_BCLK
612  */
613 #define ACM_MCLKOUT1_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_MASK)
614 /*! @} */
615 
616 /*! @name ESAI0_CLK - ACM_ESAI0_CLK Register */
617 /*! @{ */
618 #define ACM_ESAI0_CLK_SEL_MASK                   (0x3U)
619 #define ACM_ESAI0_CLK_SEL_SHIFT                  (0U)
620 /*! SEL - Select
621  *  0b00..AUD_PLL_DIV_CLK0
622  *  0b01..AUD_PLL_DIV_CLK1
623  *  0b10..AUD_CLK0
624  *  0b11..AUD_CLK1
625  */
626 #define ACM_ESAI0_CLK_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_MASK)
627 /*! @} */
628 
629 /*! @name GPT_CLK - ACM_GPT_CLK Register */
630 /*! @{ */
631 #define ACM_GPT_CLK_SEL_MASK                     (0x7U)
632 #define ACM_GPT_CLK_SEL_SHIFT                    (0U)
633 /*! SEL - Select
634  *  0b000..AUD_PLL_DIV_CLK0
635  *  0b001..AUD_PLL_DIV_CLK1
636  *  0b010..AUD_CLK0
637  *  0b011..AUD_CLK1
638  *  0b100..24M_REF_CLK
639  */
640 #define ACM_GPT_CLK_SEL(x)                       (((uint32_t)(((uint32_t)(x)) << ACM_GPT_CLK_SEL_SHIFT)) & ACM_GPT_CLK_SEL_MASK)
641 /*! @} */
642 
643 /* The count of ACM_GPT_CLK */
644 #define ACM_GPT_CLK_COUNT                        (6U)
645 
646 /*! @name SAI_MCLK - ACM_SAI_MCLK Register */
647 /*! @{ */
648 #define ACM_SAI_MCLK_SEL_MASK                    (0x3U)
649 #define ACM_SAI_MCLK_SEL_SHIFT                   (0U)
650 /*! SEL - Select
651  *  0b00..AUD_PLL_DIV_CLK0
652  *  0b01..AUD_PLL_DIV_CLK1
653  *  0b10..AUD_CLK0
654  *  0b11..AUD_CLK1
655  */
656 #define ACM_SAI_MCLK_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_SAI_MCLK_SEL_SHIFT)) & ACM_SAI_MCLK_SEL_MASK)
657 /*! @} */
658 
659 /* The count of ACM_SAI_MCLK */
660 #define ACM_SAI_MCLK_COUNT                       (8U)
661 
662 /*! @name SPDIF0_TX_CLK - ACM_SPDIF0_TX_CLK Register */
663 /*! @{ */
664 #define ACM_SPDIF0_TX_CLK_SEL_MASK               (0x3U)
665 #define ACM_SPDIF0_TX_CLK_SEL_SHIFT              (0U)
666 /*! SEL - Select
667  *  0b00..AUD_PLL_DIV_CLK0
668  *  0b01..AUD_PLL_DIV_CLK1
669  *  0b10..AUD_CLK0
670  *  0b11..AUD_CLK1
671  */
672 #define ACM_SPDIF0_TX_CLK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_MASK)
673 /*! @} */
674 
675 /*! @name MQS_HMCLK_CLK - ACM_MQS_HMCLK_CLK Register */
676 /*! @{ */
677 #define ACM_MQS_HMCLK_CLK_SEL_MASK               (0x3U)
678 #define ACM_MQS_HMCLK_CLK_SEL_SHIFT              (0U)
679 /*! SEL - Select
680  *  0b00..AUD_PLL_DIV_CLK0
681  *  0b01..AUD_PLL_DIV_CLK1
682  *  0b10..AUD_CLK0
683  *  0b11..AUD_CLK1
684  */
685 #define ACM_MQS_HMCLK_CLK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_CLK_SEL_SHIFT)) & ACM_MQS_HMCLK_CLK_SEL_MASK)
686 /*! @} */
687 
688 
689 /*!
690  * @}
691  */ /* end of group ACM_Register_Masks */
692 
693 
694 /* ACM - Peripheral instance base addresses */
695 /** Peripheral ADMA__ACM base address */
696 #define ADMA__ACM_BASE                           (0x59000000u)
697 /** Peripheral ADMA__ACM base pointer */
698 #define ADMA__ACM                                ((ACM_Type *)ADMA__ACM_BASE)
699 /** Array initializer of ACM peripheral base addresses */
700 #define ACM_BASE_ADDRS                           { ADMA__ACM_BASE }
701 /** Array initializer of ACM peripheral base pointers */
702 #define ACM_BASE_PTRS                            { ADMA__ACM }
703 
704 /*!
705  * @}
706  */ /* end of group ACM_Peripheral_Access_Layer */
707 
708 
709 /* ----------------------------------------------------------------------------
710    -- ADC Peripheral Access Layer
711    ---------------------------------------------------------------------------- */
712 
713 /*!
714  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
715  * @{
716  */
717 
718 /** ADC - Register Layout Typedef */
719 typedef struct {
720   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
721   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
722        uint8_t RESERVED_0[8];
723   __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
724   __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
725   __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
726   __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
727   __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
728   __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
729        uint8_t RESERVED_1[8];
730   __IO uint32_t FCTRL;                             /**< ADC FIFO Control Register, offset: 0x30 */
731   __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
732        uint8_t RESERVED_2[136];
733   __IO uint32_t TCTRL[8];                          /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
734        uint8_t RESERVED_3[32];
735   struct {                                         /* offset: 0x100, array step: 0x8 */
736     __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
737     __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
738   } CMD[15];
739        uint8_t RESERVED_4[136];
740   __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
741        uint8_t RESERVED_5[240];
742   __I  uint32_t RESFIFO;                           /**< ADC Data Result FIFO Register, offset: 0x300 */
743 } ADC_Type;
744 
745 /* ----------------------------------------------------------------------------
746    -- ADC Register Masks
747    ---------------------------------------------------------------------------- */
748 
749 /*!
750  * @addtogroup ADC_Register_Masks ADC Register Masks
751  * @{
752  */
753 
754 /*! @name VERID - Version ID Register */
755 /*! @{ */
756 #define ADC_VERID_RES_MASK                       (0x1U)
757 #define ADC_VERID_RES_SHIFT                      (0U)
758 /*! RES - Resolution
759  *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
760  *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
761  */
762 #define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
763 #define ADC_VERID_DIFFEN_MASK                    (0x2U)
764 #define ADC_VERID_DIFFEN_SHIFT                   (1U)
765 /*! DIFFEN - Differential Supported
766  *  0b0..Differential operation not supported.
767  *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
768  */
769 #define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
770 #define ADC_VERID_MVI_MASK                       (0x8U)
771 #define ADC_VERID_MVI_SHIFT                      (3U)
772 /*! MVI - Multi Vref Implemented
773  *  0b0..Single voltage reference high (VREFH) input supported.
774  *  0b1..Multiple voltage reference high (VREFH) inputs supported.
775  */
776 #define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
777 #define ADC_VERID_CSW_MASK                       (0x70U)
778 #define ADC_VERID_CSW_SHIFT                      (4U)
779 /*! CSW - Channel Scale Width
780  *  0b000..Channel scaling not supported.
781  *  0b001..Channel scaling supported. 1-bit CSCALE control field.
782  *  0b110..Channel scaling supported. 6-bit CSCALE control field.
783  */
784 #define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
785 #define ADC_VERID_VR1RNGI_MASK                   (0x100U)
786 #define ADC_VERID_VR1RNGI_SHIFT                  (8U)
787 /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
788  *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
789  *  0b1..Range control required. CFG[VREF1RNG] is implemented.
790  */
791 #define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
792 #define ADC_VERID_IADCKI_MASK                    (0x200U)
793 #define ADC_VERID_IADCKI_SHIFT                   (9U)
794 /*! IADCKI - Internal ADC Clock implemented
795  *  0b0..Internal clock source not implemented.
796  *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
797  */
798 #define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
799 #define ADC_VERID_CALOFSI_MASK                   (0x400U)
800 #define ADC_VERID_CALOFSI_SHIFT                  (10U)
801 /*! CALOFSI - Calibration Offset Function Implemented
802  *  0b0..Offset calibration and offset trimming not implemented.
803  *  0b1..Offset calibration and offset trimming implemented.
804  */
805 #define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
806 #define ADC_VERID_MINOR_MASK                     (0xFF0000U)
807 #define ADC_VERID_MINOR_SHIFT                    (16U)
808 /*! MINOR - Minor Version Number
809  */
810 #define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
811 #define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
812 #define ADC_VERID_MAJOR_SHIFT                    (24U)
813 /*! MAJOR - Major Version Number
814  */
815 #define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
816 /*! @} */
817 
818 /*! @name PARAM - Parameter Register */
819 /*! @{ */
820 #define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
821 #define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
822 /*! TRIG_NUM - Trigger Number
823  */
824 #define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
825 #define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
826 #define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
827 /*! FIFOSIZE - Result FIFO Depth
828  *  0b00000001..Result FIFO depth = 1 dataword.
829  *  0b00000100..Result FIFO depth = 4 datawords.
830  *  0b00001000..Result FIFO depth = 8 datawords.
831  *  0b00010000..Result FIFO depth = 16 datawords.
832  *  0b00100000..Result FIFO depth = 32 datawords.
833  *  0b01000000..Result FIFO depth = 64 datawords.
834  */
835 #define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
836 #define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
837 #define ADC_PARAM_CV_NUM_SHIFT                   (16U)
838 /*! CV_NUM - Compare Value Number
839  */
840 #define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
841 #define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
842 #define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
843 /*! CMD_NUM - Command Buffer Number
844  */
845 #define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
846 /*! @} */
847 
848 /*! @name CTRL - ADC Control Register */
849 /*! @{ */
850 #define ADC_CTRL_ADCEN_MASK                      (0x1U)
851 #define ADC_CTRL_ADCEN_SHIFT                     (0U)
852 /*! ADCEN - ADC Enable
853  *  0b0..ADC is disabled.
854  *  0b1..ADC is enabled.
855  */
856 #define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
857 #define ADC_CTRL_RST_MASK                        (0x2U)
858 #define ADC_CTRL_RST_SHIFT                       (1U)
859 /*! RST - Software Reset
860  *  0b0..ADC logic is not reset.
861  *  0b1..ADC logic is reset.
862  */
863 #define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
864 #define ADC_CTRL_DOZEN_MASK                      (0x4U)
865 #define ADC_CTRL_DOZEN_SHIFT                     (2U)
866 /*! DOZEN - Doze Enable
867  *  0b0..ADC is enabled in Doze mode.
868  *  0b1..ADC is disabled in Doze mode.
869  */
870 #define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
871 #define ADC_CTRL_RSTFIFO_MASK                    (0x100U)
872 #define ADC_CTRL_RSTFIFO_SHIFT                   (8U)
873 /*! RSTFIFO - Reset FIFO
874  *  0b0..No effect.
875  *  0b1..FIFO is reset.
876  */
877 #define ADC_CTRL_RSTFIFO(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
878 /*! @} */
879 
880 /*! @name STAT - ADC Status Register */
881 /*! @{ */
882 #define ADC_STAT_RDY_MASK                        (0x1U)
883 #define ADC_STAT_RDY_SHIFT                       (0U)
884 /*! RDY - Result FIFO Ready Flag
885  *  0b0..Result FIFO data level not above watermark level.
886  *  0b1..Result FIFO holding data above watermark level.
887  */
888 #define ADC_STAT_RDY(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
889 #define ADC_STAT_FOF_MASK                        (0x2U)
890 #define ADC_STAT_FOF_SHIFT                       (1U)
891 /*! FOF - Result FIFO Overflow Flag
892  *  0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
893  *  0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
894  */
895 #define ADC_STAT_FOF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
896 #define ADC_STAT_ADC_ACTIVE_MASK                 (0x100U)
897 #define ADC_STAT_ADC_ACTIVE_SHIFT                (8U)
898 /*! ADC_ACTIVE - ADC Active
899  *  0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
900  *  0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
901  */
902 #define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
903 #define ADC_STAT_TRGACT_MASK                     (0x70000U)
904 #define ADC_STAT_TRGACT_SHIFT                    (16U)
905 /*! TRGACT - Trigger Active
906  *  0b000..Command (sequence) associated with Trigger 0 currently being executed.
907  *  0b001..Command (sequence) associated with Trigger 1 currently being executed.
908  *  0b010..Command (sequence) associated with Trigger 2 currently being executed.
909  *  0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
910  */
911 #define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
912 #define ADC_STAT_CMDACT_MASK                     (0xF000000U)
913 #define ADC_STAT_CMDACT_SHIFT                    (24U)
914 /*! CMDACT - Command Active
915  *  0b0000..No command is currently in progress.
916  *  0b0001..Command 1 currently being executed.
917  *  0b0010..Command 2 currently being executed.
918  *  0b0011-0b1111..Associated command number is currently being executed.
919  */
920 #define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
921 /*! @} */
922 
923 /*! @name IE - Interrupt Enable Register */
924 /*! @{ */
925 #define ADC_IE_FWMIE_MASK                        (0x1U)
926 #define ADC_IE_FWMIE_SHIFT                       (0U)
927 /*! FWMIE - FIFO Watermark Interrupt Enable
928  *  0b0..FIFO watermark interrupts are not enabled.
929  *  0b1..FIFO watermark interrupts are enabled.
930  */
931 #define ADC_IE_FWMIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
932 #define ADC_IE_FOFIE_MASK                        (0x2U)
933 #define ADC_IE_FOFIE_SHIFT                       (1U)
934 /*! FOFIE - Result FIFO Overflow Interrupt Enable
935  *  0b0..FIFO overflow interrupts are not enabled.
936  *  0b1..FIFO overflow interrupts are enabled.
937  */
938 #define ADC_IE_FOFIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
939 /*! @} */
940 
941 /*! @name DE - DMA Enable Register */
942 /*! @{ */
943 #define ADC_DE_FWMDE_MASK                        (0x1U)
944 #define ADC_DE_FWMDE_SHIFT                       (0U)
945 /*! FWMDE - FIFO Watermark DMA Enable
946  *  0b0..DMA request disabled.
947  *  0b1..DMA request enabled.
948  */
949 #define ADC_DE_FWMDE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
950 /*! @} */
951 
952 /*! @name CFG - ADC Configuration Register */
953 /*! @{ */
954 #define ADC_CFG_TPRICTRL_MASK                    (0x1U)
955 #define ADC_CFG_TPRICTRL_SHIFT                   (0U)
956 /*! TPRICTRL - ADC trigger priority control
957  *  0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
958  *       the new command specified by the trigger is started.
959  *  0b1..If a higher priority trigger is received during command processing, the current conversion is completed
960  *       (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
961  *       trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
962  *       conversion.
963  */
964 #define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
965 #define ADC_CFG_PWRSEL_MASK                      (0x30U)
966 #define ADC_CFG_PWRSEL_SHIFT                     (4U)
967 /*! PWRSEL - Power Configuration Select
968  *  0b00..Level 1 (Lowest power setting)
969  *  0b01..Level 2
970  *  0b10..Level 3
971  *  0b11..Level 4 (Highest power setting)
972  */
973 #define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
974 #define ADC_CFG_REFSEL_MASK                      (0xC0U)
975 #define ADC_CFG_REFSEL_SHIFT                     (6U)
976 /*! REFSEL - Voltage Reference Selection
977  *  0b00..(Default) Option 1 setting.
978  *  0b01..Option 2 setting.
979  *  0b10..Option 3 setting.
980  *  0b11..Reserved
981  */
982 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
983 #define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
984 #define ADC_CFG_PUDLY_SHIFT                      (16U)
985 /*! PUDLY - Power Up Delay
986  */
987 #define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
988 #define ADC_CFG_PWREN_MASK                       (0x10000000U)
989 #define ADC_CFG_PWREN_SHIFT                      (28U)
990 /*! PWREN - ADC Analog Pre-Enable
991  *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
992  *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
993  *       of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
994  *       detected trigger does not begin ADC operation until the power up delay time has passed.
995  */
996 #define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
997 /*! @} */
998 
999 /*! @name PAUSE - ADC Pause Register */
1000 /*! @{ */
1001 #define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
1002 #define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
1003 /*! PAUSEDLY - Pause Delay
1004  */
1005 #define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
1006 #define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
1007 #define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
1008 /*! PAUSEEN - PAUSE Option Enable
1009  *  0b0..Pause operation disabled
1010  *  0b1..Pause operation enabled
1011  */
1012 #define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
1013 /*! @} */
1014 
1015 /*! @name FCTRL - ADC FIFO Control Register */
1016 /*! @{ */
1017 #define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
1018 #define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
1019 /*! FCOUNT - Result FIFO counter
1020  */
1021 #define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
1022 #define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
1023 #define ADC_FCTRL_FWMARK_SHIFT                   (16U)
1024 /*! FWMARK - Watermark level selection
1025  */
1026 #define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
1027 /*! @} */
1028 
1029 /*! @name SWTRIG - Software Trigger Register */
1030 /*! @{ */
1031 #define ADC_SWTRIG_SWT0_MASK                     (0x1U)
1032 #define ADC_SWTRIG_SWT0_SHIFT                    (0U)
1033 /*! SWT0 - Software trigger 0 event
1034  *  0b0..No trigger 0 event generated.
1035  *  0b1..Trigger 0 event generated.
1036  */
1037 #define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
1038 #define ADC_SWTRIG_SWT1_MASK                     (0x2U)
1039 #define ADC_SWTRIG_SWT1_SHIFT                    (1U)
1040 /*! SWT1 - Software trigger 1 event
1041  *  0b0..No trigger 1 event generated.
1042  *  0b1..Trigger 1 event generated.
1043  */
1044 #define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
1045 #define ADC_SWTRIG_SWT2_MASK                     (0x4U)
1046 #define ADC_SWTRIG_SWT2_SHIFT                    (2U)
1047 /*! SWT2 - Software trigger 2 event
1048  *  0b0..No trigger 2 event generated.
1049  *  0b1..Trigger 2 event generated.
1050  */
1051 #define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
1052 #define ADC_SWTRIG_SWT3_MASK                     (0x8U)
1053 #define ADC_SWTRIG_SWT3_SHIFT                    (3U)
1054 /*! SWT3 - Software trigger 3 event
1055  *  0b0..No trigger 3 event generated.
1056  *  0b1..Trigger 3 event generated.
1057  */
1058 #define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
1059 #define ADC_SWTRIG_SWT4_MASK                     (0x10U)
1060 #define ADC_SWTRIG_SWT4_SHIFT                    (4U)
1061 /*! SWT4 - Software trigger 4 event
1062  *  0b0..No trigger 4 event generated.
1063  *  0b1..Trigger 4 event generated.
1064  */
1065 #define ADC_SWTRIG_SWT4(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
1066 #define ADC_SWTRIG_SWT5_MASK                     (0x20U)
1067 #define ADC_SWTRIG_SWT5_SHIFT                    (5U)
1068 /*! SWT5 - Software trigger 5 event
1069  *  0b0..No trigger 5 event generated.
1070  *  0b1..Trigger 5 event generated.
1071  */
1072 #define ADC_SWTRIG_SWT5(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
1073 #define ADC_SWTRIG_SWT6_MASK                     (0x40U)
1074 #define ADC_SWTRIG_SWT6_SHIFT                    (6U)
1075 /*! SWT6 - Software trigger 6 event
1076  *  0b0..No trigger 6 event generated.
1077  *  0b1..Trigger 6 event generated.
1078  */
1079 #define ADC_SWTRIG_SWT6(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
1080 #define ADC_SWTRIG_SWT7_MASK                     (0x80U)
1081 #define ADC_SWTRIG_SWT7_SHIFT                    (7U)
1082 /*! SWT7 - Software trigger 7 event
1083  *  0b0..No trigger 7 event generated.
1084  *  0b1..Trigger 7 event generated.
1085  */
1086 #define ADC_SWTRIG_SWT7(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
1087 /*! @} */
1088 
1089 /*! @name TCTRL - Trigger Control Register */
1090 /*! @{ */
1091 #define ADC_TCTRL_HTEN_MASK                      (0x1U)
1092 #define ADC_TCTRL_HTEN_SHIFT                     (0U)
1093 /*! HTEN - Trigger enable
1094  *  0b0..Hardware trigger source disabled
1095  *  0b1..Hardware trigger source enabled
1096  */
1097 #define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
1098 #define ADC_TCTRL_TPRI_MASK                      (0x700U)
1099 #define ADC_TCTRL_TPRI_SHIFT                     (8U)
1100 /*! TPRI - Trigger priority setting
1101  *  0b000..Set to highest priority, Level 1
1102  *  0b001-0b110..Set to corresponding priority level
1103  *  0b111..Set to lowest priority, Level 8
1104  */
1105 #define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1106 #define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
1107 #define ADC_TCTRL_TDLY_SHIFT                     (16U)
1108 /*! TDLY - Trigger delay select
1109  */
1110 #define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1111 #define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
1112 #define ADC_TCTRL_TCMD_SHIFT                     (24U)
1113 /*! TCMD - Trigger command select
1114  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1115  *  0b0001..CMD1 is executed
1116  *  0b0010-0b1110..Corresponding CMD is executed
1117  *  0b1111..CMD15 is executed
1118  */
1119 #define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1120 /*! @} */
1121 
1122 /* The count of ADC_TCTRL */
1123 #define ADC_TCTRL_COUNT                          (8U)
1124 
1125 /*! @name CMDL - ADC Command Low Buffer Register */
1126 /*! @{ */
1127 #define ADC_CMDL_ADCH_MASK                       (0x1FU)
1128 #define ADC_CMDL_ADCH_SHIFT                      (0U)
1129 /*! ADCH - Input channel select
1130  *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1131  *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1132  *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1133  *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1134  *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1135  *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1136  *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1137  */
1138 #define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1139 #define ADC_CMDL_ABSEL_MASK                      (0x20U)
1140 #define ADC_CMDL_ABSEL_SHIFT                     (5U)
1141 /*! ABSEL - A-side vs. B-side Select
1142  *  0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
1143  *  0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
1144  */
1145 #define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
1146 #define ADC_CMDL_DIFF_MASK                       (0x40U)
1147 #define ADC_CMDL_DIFF_SHIFT                      (6U)
1148 /*! DIFF - Differential Mode Enable
1149  *  0b0..Single-ended mode.
1150  *  0b1..Differential mode.
1151  */
1152 #define ADC_CMDL_DIFF(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
1153 #define ADC_CMDL_CSCALE_MASK                     (0x2000U)
1154 #define ADC_CMDL_CSCALE_SHIFT                    (13U)
1155 /*! CSCALE - Channel Scale
1156  *  0b0..Scale selected analog channel (Factor of 30/64)
1157  *  0b1..(Default) Full scale (Factor of 1)
1158  */
1159 #define ADC_CMDL_CSCALE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
1160 /*! @} */
1161 
1162 /* The count of ADC_CMDL */
1163 #define ADC_CMDL_COUNT                           (15U)
1164 
1165 /*! @name CMDH - ADC Command High Buffer Register */
1166 /*! @{ */
1167 #define ADC_CMDH_CMPEN_MASK                      (0x3U)
1168 #define ADC_CMDH_CMPEN_SHIFT                     (0U)
1169 /*! CMPEN - Compare Function Enable
1170  *  0b00..Compare disabled.
1171  *  0b01..Reserved
1172  *  0b10..Compare enabled. Store on true.
1173  *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1174  */
1175 #define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1176 #define ADC_CMDH_LWI_MASK                        (0x80U)
1177 #define ADC_CMDH_LWI_SHIFT                       (7U)
1178 /*! LWI - Loop with Increment
1179  *  0b0..Auto channel increment disabled
1180  *  0b1..Auto channel increment enabled
1181  */
1182 #define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1183 #define ADC_CMDH_STS_MASK                        (0x700U)
1184 #define ADC_CMDH_STS_SHIFT                       (8U)
1185 /*! STS - Sample Time Select
1186  *  0b000..Minimum sample time of 3 ADCK cycles.
1187  *  0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1188  *  0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1189  *  0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1190  *  0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1191  *  0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1192  *  0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1193  *  0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1194  */
1195 #define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1196 #define ADC_CMDH_AVGS_MASK                       (0x7000U)
1197 #define ADC_CMDH_AVGS_SHIFT                      (12U)
1198 /*! AVGS - Hardware Average Select
1199  *  0b000..Single conversion.
1200  *  0b001..2 conversions averaged.
1201  *  0b010..4 conversions averaged.
1202  *  0b011..8 conversions averaged.
1203  *  0b100..16 conversions averaged.
1204  *  0b101..32 conversions averaged.
1205  *  0b110..64 conversions averaged.
1206  *  0b111..128 conversions averaged.
1207  */
1208 #define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1209 #define ADC_CMDH_LOOP_MASK                       (0xF0000U)
1210 #define ADC_CMDH_LOOP_SHIFT                      (16U)
1211 /*! LOOP - Loop Count Select
1212  *  0b0000..Looping not enabled. Command executes 1 time.
1213  *  0b0001..Loop 1 time. Command executes 2 times.
1214  *  0b0010..Loop 2 times. Command executes 3 times.
1215  *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1216  *  0b1111..Loop 15 times. Command executes 16 times.
1217  */
1218 #define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1219 #define ADC_CMDH_NEXT_MASK                       (0xF000000U)
1220 #define ADC_CMDH_NEXT_SHIFT                      (24U)
1221 /*! NEXT - Next Command Select
1222  *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1223  *          trigger pending, begin command associated with lower priority trigger.
1224  *  0b0001..Select CMD1 command buffer register as next command.
1225  *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
1226  *  0b1111..Select CMD15 command buffer register as next command.
1227  */
1228 #define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1229 /*! @} */
1230 
1231 /* The count of ADC_CMDH */
1232 #define ADC_CMDH_COUNT                           (15U)
1233 
1234 /*! @name CV - Compare Value Register */
1235 /*! @{ */
1236 #define ADC_CV_CVL_MASK                          (0xFFFFU)
1237 #define ADC_CV_CVL_SHIFT                         (0U)
1238 /*! CVL - Compare Value Low.
1239  */
1240 #define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1241 #define ADC_CV_CVH_MASK                          (0xFFFF0000U)
1242 #define ADC_CV_CVH_SHIFT                         (16U)
1243 /*! CVH - Compare Value High.
1244  */
1245 #define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1246 /*! @} */
1247 
1248 /* The count of ADC_CV */
1249 #define ADC_CV_COUNT                             (4U)
1250 
1251 /*! @name RESFIFO - ADC Data Result FIFO Register */
1252 /*! @{ */
1253 #define ADC_RESFIFO_D_MASK                       (0xFFFFU)
1254 #define ADC_RESFIFO_D_SHIFT                      (0U)
1255 /*! D - Data result
1256  */
1257 #define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1258 #define ADC_RESFIFO_TSRC_MASK                    (0x70000U)
1259 #define ADC_RESFIFO_TSRC_SHIFT                   (16U)
1260 /*! TSRC - Trigger Source
1261  *  0b000..Trigger source 0 initiated this conversion.
1262  *  0b001..Trigger source 1 initiated this conversion.
1263  *  0b010-0b110..Corresponding trigger source initiated this conversion.
1264  *  0b111..Trigger source 7 initiated this conversion.
1265  */
1266 #define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1267 #define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
1268 #define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
1269 /*! LOOPCNT - Loop count value
1270  *  0b0000..Result is from initial conversion in command.
1271  *  0b0001..Result is from second conversion in command.
1272  *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1273  *  0b1111..Result is from 16th conversion in command.
1274  */
1275 #define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1276 #define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
1277 #define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
1278 /*! CMDSRC - Command Buffer Source
1279  *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1280  *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1281  *  0b0001..CMD1 buffer used as control settings for this conversion.
1282  *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1283  *  0b1111..CMD15 buffer used as control settings for this conversion.
1284  */
1285 #define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1286 #define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
1287 #define ADC_RESFIFO_VALID_SHIFT                  (31U)
1288 /*! VALID - FIFO entry is valid
1289  *  0b0..FIFO is empty. Discard any read from RESFIFO.
1290  *  0b1..FIFO record read from RESFIFO is valid.
1291  */
1292 #define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1293 /*! @} */
1294 
1295 
1296 /*!
1297  * @}
1298  */ /* end of group ADC_Register_Masks */
1299 
1300 
1301 /* ADC - Peripheral instance base addresses */
1302 /** Peripheral ADMA__ADC0 base address */
1303 #define ADMA__ADC0_BASE                          (0x5A880000u)
1304 /** Peripheral ADMA__ADC0 base pointer */
1305 #define ADMA__ADC0                               ((ADC_Type *)ADMA__ADC0_BASE)
1306 /** Array initializer of ADC peripheral base addresses */
1307 #define ADC_BASE_ADDRS                           { ADMA__ADC0_BASE }
1308 /** Array initializer of ADC peripheral base pointers */
1309 #define ADC_BASE_PTRS                            { ADMA__ADC0 }
1310 /** Interrupt vectors for the ADC peripheral type */
1311 #define ADC_IRQS                                 { ADMA_ADC0_INT_IRQn }
1312 
1313 /*!
1314  * @}
1315  */ /* end of group ADC_Peripheral_Access_Layer */
1316 
1317 
1318 /* ----------------------------------------------------------------------------
1319    -- APBH Peripheral Access Layer
1320    ---------------------------------------------------------------------------- */
1321 
1322 /*!
1323  * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1324  * @{
1325  */
1326 
1327 /** APBH - Register Layout Typedef */
1328 typedef struct {
1329   struct {                                         /* offset: 0x0 */
1330     __IO uint32_t RW;                                /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1331     __IO uint32_t SET;                               /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1332     __IO uint32_t CLR;                               /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1333     __IO uint32_t TOG;                               /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1334   } CTRL0;
1335   struct {                                         /* offset: 0x10 */
1336     __IO uint32_t RW;                                /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1337     __IO uint32_t SET;                               /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1338     __IO uint32_t CLR;                               /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1339     __IO uint32_t TOG;                               /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1340   } CTRL1;
1341   struct {                                         /* offset: 0x20 */
1342     __IO uint32_t RW;                                /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1343     __IO uint32_t SET;                               /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1344     __IO uint32_t CLR;                               /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1345     __IO uint32_t TOG;                               /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1346   } CTRL2;
1347   struct {                                         /* offset: 0x30 */
1348     __IO uint32_t RW;                                /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1349     __IO uint32_t SET;                               /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1350     __IO uint32_t CLR;                               /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1351     __IO uint32_t TOG;                               /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1352   } CHANNEL_CTRL;
1353        uint32_t DEVSEL;                            /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1354        uint8_t RESERVED_0[12];
1355   __IO uint32_t DMA_BURST_SIZE;                    /**< AHB to APBH DMA burst size, offset: 0x50 */
1356        uint8_t RESERVED_1[12];
1357   __IO uint32_t DEBUGr;                            /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1358        uint8_t RESERVED_2[156];
1359   struct {                                         /* offset: 0x100, array step: 0x70 */
1360     __I  uint32_t CH_CURCMDAR;                       /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
1361          uint8_t RESERVED_0[12];
1362     __IO uint32_t CH_NXTCMDAR;                       /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1363          uint8_t RESERVED_1[12];
1364     __I  uint32_t CH_CMD;                            /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1365          uint8_t RESERVED_2[12];
1366     __I  uint32_t CH_BAR;                            /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1367          uint8_t RESERVED_3[12];
1368     __IO uint32_t CH_SEMA;                           /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1369          uint8_t RESERVED_4[12];
1370     __I  uint32_t CH_DEBUG1;                         /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1371          uint8_t RESERVED_5[12];
1372     __I  uint32_t CH_DEBUG2;                         /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1373          uint8_t RESERVED_6[12];
1374   } CH_CFGn[16];
1375   __I  uint32_t VERSION;                           /**< APBH Bridge Version Register, offset: 0x800 */
1376 } APBH_Type;
1377 
1378 /* ----------------------------------------------------------------------------
1379    -- APBH Register Masks
1380    ---------------------------------------------------------------------------- */
1381 
1382 /*!
1383  * @addtogroup APBH_Register_Masks APBH Register Masks
1384  * @{
1385  */
1386 
1387 /*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1388 /*! @{ */
1389 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK          (0xFFFFU)
1390 #define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT         (0U)
1391 /*! CLKGATE_CHANNEL - CLKGATE_CHANNEL
1392  *  0b0000000000000001..
1393  *  0b0000000000000010..
1394  *  0b0000000000000100..
1395  *  0b0000000000001000..
1396  *  0b0000000000010000..
1397  *  0b0000000000100000..
1398  *  0b0000000001000000..
1399  *  0b0000000010000000..
1400  *  0b0000000100000000..
1401  */
1402 #define APBH_CTRL0_CLKGATE_CHANNEL(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1403 #define APBH_CTRL0_APB_BURST_EN_MASK             (0x10000000U)
1404 #define APBH_CTRL0_APB_BURST_EN_SHIFT            (28U)
1405 /*! APB_BURST_EN - APB_BURST_EN
1406  */
1407 #define APBH_CTRL0_APB_BURST_EN(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1408 #define APBH_CTRL0_AHB_BURST8_EN_MASK            (0x20000000U)
1409 #define APBH_CTRL0_AHB_BURST8_EN_SHIFT           (29U)
1410 /*! AHB_BURST8_EN - AHB_BURST8_EN
1411  */
1412 #define APBH_CTRL0_AHB_BURST8_EN(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1413 #define APBH_CTRL0_CLKGATE_MASK                  (0x40000000U)
1414 #define APBH_CTRL0_CLKGATE_SHIFT                 (30U)
1415 /*! CLKGATE - CLKGATE
1416  */
1417 #define APBH_CTRL0_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1418 #define APBH_CTRL0_SFTRST_MASK                   (0x80000000U)
1419 #define APBH_CTRL0_SFTRST_SHIFT                  (31U)
1420 /*! SFTRST - SFTRST
1421  */
1422 #define APBH_CTRL0_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1423 /*! @} */
1424 
1425 /*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1426 /*! @{ */
1427 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK         (0x1U)
1428 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT        (0U)
1429 /*! CH0_CMDCMPLT_IRQ - CH0_CMDCMPLT_IRQ
1430  */
1431 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1432 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK         (0x2U)
1433 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT        (1U)
1434 /*! CH1_CMDCMPLT_IRQ - CH1_CMDCMPLT_IRQ
1435  */
1436 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1437 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK         (0x4U)
1438 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT        (2U)
1439 /*! CH2_CMDCMPLT_IRQ - CH2_CMDCMPLT_IRQ
1440  */
1441 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1442 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK         (0x8U)
1443 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT        (3U)
1444 /*! CH3_CMDCMPLT_IRQ - CH3_CMDCMPLT_IRQ
1445  */
1446 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1447 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK         (0x10U)
1448 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT        (4U)
1449 /*! CH4_CMDCMPLT_IRQ - CH4_CMDCMPLT_IRQ
1450  */
1451 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1452 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK         (0x20U)
1453 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT        (5U)
1454 /*! CH5_CMDCMPLT_IRQ - CH5_CMDCMPLT_IRQ
1455  */
1456 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1457 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK         (0x40U)
1458 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT        (6U)
1459 /*! CH6_CMDCMPLT_IRQ - CH6_CMDCMPLT_IRQ
1460  */
1461 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1462 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK         (0x80U)
1463 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT        (7U)
1464 /*! CH7_CMDCMPLT_IRQ - CH7_CMDCMPLT_IRQ
1465  */
1466 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1467 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK         (0x100U)
1468 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT        (8U)
1469 /*! CH8_CMDCMPLT_IRQ - CH8_CMDCMPLT_IRQ
1470  */
1471 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1472 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK         (0x200U)
1473 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT        (9U)
1474 /*! CH9_CMDCMPLT_IRQ - CH9_CMDCMPLT_IRQ
1475  */
1476 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1477 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK        (0x400U)
1478 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT       (10U)
1479 /*! CH10_CMDCMPLT_IRQ - CH10_CMDCMPLT_IRQ
1480  */
1481 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1482 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK        (0x800U)
1483 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT       (11U)
1484 /*! CH11_CMDCMPLT_IRQ - CH11_CMDCMPLT_IRQ
1485  */
1486 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1487 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK        (0x1000U)
1488 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT       (12U)
1489 /*! CH12_CMDCMPLT_IRQ - CH12_CMDCMPLT_IRQ
1490  */
1491 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1492 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK        (0x2000U)
1493 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT       (13U)
1494 /*! CH13_CMDCMPLT_IRQ - CH13_CMDCMPLT_IRQ
1495  */
1496 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1497 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK        (0x4000U)
1498 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT       (14U)
1499 /*! CH14_CMDCMPLT_IRQ - CH14_CMDCMPLT_IRQ
1500  */
1501 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1502 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK        (0x8000U)
1503 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT       (15U)
1504 /*! CH15_CMDCMPLT_IRQ - CH15_CMDCMPLT_IRQ
1505  */
1506 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1507 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK      (0x10000U)
1508 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT     (16U)
1509 /*! CH0_CMDCMPLT_IRQ_EN - CH0_CMDCMPLT_IRQ_EN
1510  */
1511 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1512 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK      (0x20000U)
1513 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT     (17U)
1514 /*! CH1_CMDCMPLT_IRQ_EN - CH1_CMDCMPLT_IRQ_EN
1515  */
1516 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1517 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK      (0x40000U)
1518 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT     (18U)
1519 /*! CH2_CMDCMPLT_IRQ_EN - CH2_CMDCMPLT_IRQ_EN
1520  */
1521 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1522 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK      (0x80000U)
1523 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT     (19U)
1524 /*! CH3_CMDCMPLT_IRQ_EN - CH3_CMDCMPLT_IRQ_EN
1525  */
1526 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1527 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK      (0x100000U)
1528 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT     (20U)
1529 /*! CH4_CMDCMPLT_IRQ_EN - CH4_CMDCMPLT_IRQ_EN
1530  */
1531 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1532 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK      (0x200000U)
1533 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT     (21U)
1534 /*! CH5_CMDCMPLT_IRQ_EN - CH5_CMDCMPLT_IRQ_EN
1535  */
1536 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1537 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK      (0x400000U)
1538 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT     (22U)
1539 /*! CH6_CMDCMPLT_IRQ_EN - CH6_CMDCMPLT_IRQ_EN
1540  */
1541 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1542 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK      (0x800000U)
1543 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT     (23U)
1544 /*! CH7_CMDCMPLT_IRQ_EN - CH7_CMDCMPLT_IRQ_EN
1545  */
1546 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1547 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK      (0x1000000U)
1548 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT     (24U)
1549 /*! CH8_CMDCMPLT_IRQ_EN - CH8_CMDCMPLT_IRQ_EN
1550  */
1551 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1552 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK      (0x2000000U)
1553 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT     (25U)
1554 /*! CH9_CMDCMPLT_IRQ_EN - CH9_CMDCMPLT_IRQ_EN
1555  */
1556 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1557 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK     (0x4000000U)
1558 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT    (26U)
1559 /*! CH10_CMDCMPLT_IRQ_EN - CH10_CMDCMPLT_IRQ_EN
1560  */
1561 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1562 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK     (0x8000000U)
1563 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT    (27U)
1564 /*! CH11_CMDCMPLT_IRQ_EN - CH11_CMDCMPLT_IRQ_EN
1565  */
1566 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1567 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK     (0x10000000U)
1568 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT    (28U)
1569 /*! CH12_CMDCMPLT_IRQ_EN - CH12_CMDCMPLT_IRQ_EN
1570  */
1571 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1572 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK     (0x20000000U)
1573 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT    (29U)
1574 /*! CH13_CMDCMPLT_IRQ_EN - CH13_CMDCMPLT_IRQ_EN
1575  */
1576 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1577 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK     (0x40000000U)
1578 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT    (30U)
1579 /*! CH14_CMDCMPLT_IRQ_EN - CH14_CMDCMPLT_IRQ_EN
1580  */
1581 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1582 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK     (0x80000000U)
1583 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT    (31U)
1584 /*! CH15_CMDCMPLT_IRQ_EN - CH15_CMDCMPLT_IRQ_EN
1585  */
1586 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1587 /*! @} */
1588 
1589 /*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
1590 /*! @{ */
1591 #define APBH_CTRL2_CH0_ERROR_IRQ_MASK            (0x1U)
1592 #define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT           (0U)
1593 /*! CH0_ERROR_IRQ - CH0_ERROR_IRQ
1594  */
1595 #define APBH_CTRL2_CH0_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
1596 #define APBH_CTRL2_CH1_ERROR_IRQ_MASK            (0x2U)
1597 #define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT           (1U)
1598 /*! CH1_ERROR_IRQ - CH1_ERROR_IRQ
1599  */
1600 #define APBH_CTRL2_CH1_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
1601 #define APBH_CTRL2_CH2_ERROR_IRQ_MASK            (0x4U)
1602 #define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT           (2U)
1603 /*! CH2_ERROR_IRQ - CH2_ERROR_IRQ
1604  */
1605 #define APBH_CTRL2_CH2_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
1606 #define APBH_CTRL2_CH3_ERROR_IRQ_MASK            (0x8U)
1607 #define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT           (3U)
1608 /*! CH3_ERROR_IRQ - CH3_ERROR_IRQ
1609  */
1610 #define APBH_CTRL2_CH3_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
1611 #define APBH_CTRL2_CH4_ERROR_IRQ_MASK            (0x10U)
1612 #define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT           (4U)
1613 /*! CH4_ERROR_IRQ - CH4_ERROR_IRQ
1614  */
1615 #define APBH_CTRL2_CH4_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
1616 #define APBH_CTRL2_CH5_ERROR_IRQ_MASK            (0x20U)
1617 #define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT           (5U)
1618 /*! CH5_ERROR_IRQ - CH5_ERROR_IRQ
1619  */
1620 #define APBH_CTRL2_CH5_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
1621 #define APBH_CTRL2_CH6_ERROR_IRQ_MASK            (0x40U)
1622 #define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT           (6U)
1623 /*! CH6_ERROR_IRQ - CH6_ERROR_IRQ
1624  */
1625 #define APBH_CTRL2_CH6_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
1626 #define APBH_CTRL2_CH7_ERROR_IRQ_MASK            (0x80U)
1627 #define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT           (7U)
1628 /*! CH7_ERROR_IRQ - CH7_ERROR_IRQ
1629  */
1630 #define APBH_CTRL2_CH7_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
1631 #define APBH_CTRL2_CH8_ERROR_IRQ_MASK            (0x100U)
1632 #define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT           (8U)
1633 /*! CH8_ERROR_IRQ - CH8_ERROR_IRQ
1634  */
1635 #define APBH_CTRL2_CH8_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
1636 #define APBH_CTRL2_CH9_ERROR_IRQ_MASK            (0x200U)
1637 #define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT           (9U)
1638 /*! CH9_ERROR_IRQ - CH9_ERROR_IRQ
1639  */
1640 #define APBH_CTRL2_CH9_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
1641 #define APBH_CTRL2_CH10_ERROR_IRQ_MASK           (0x400U)
1642 #define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT          (10U)
1643 /*! CH10_ERROR_IRQ - CH10_ERROR_IRQ
1644  */
1645 #define APBH_CTRL2_CH10_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
1646 #define APBH_CTRL2_CH11_ERROR_IRQ_MASK           (0x800U)
1647 #define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT          (11U)
1648 /*! CH11_ERROR_IRQ - CH11_ERROR_IRQ
1649  */
1650 #define APBH_CTRL2_CH11_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
1651 #define APBH_CTRL2_CH12_ERROR_IRQ_MASK           (0x1000U)
1652 #define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT          (12U)
1653 /*! CH12_ERROR_IRQ - CH12_ERROR_IRQ
1654  */
1655 #define APBH_CTRL2_CH12_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
1656 #define APBH_CTRL2_CH13_ERROR_IRQ_MASK           (0x2000U)
1657 #define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT          (13U)
1658 /*! CH13_ERROR_IRQ - CH13_ERROR_IRQ
1659  */
1660 #define APBH_CTRL2_CH13_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
1661 #define APBH_CTRL2_CH14_ERROR_IRQ_MASK           (0x4000U)
1662 #define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT          (14U)
1663 /*! CH14_ERROR_IRQ - CH14_ERROR_IRQ
1664  */
1665 #define APBH_CTRL2_CH14_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
1666 #define APBH_CTRL2_CH15_ERROR_IRQ_MASK           (0x8000U)
1667 #define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT          (15U)
1668 /*! CH15_ERROR_IRQ - CH15_ERROR_IRQ
1669  */
1670 #define APBH_CTRL2_CH15_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
1671 #define APBH_CTRL2_CH0_ERROR_STATUS_MASK         (0x10000U)
1672 #define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT        (16U)
1673 /*! CH0_ERROR_STATUS - CH0_ERROR_STATUS
1674  *  0b0..An early termination from the device causes error IRQ.
1675  *  0b1..An AHB bus error causes error IRQ.
1676  */
1677 #define APBH_CTRL2_CH0_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
1678 #define APBH_CTRL2_CH1_ERROR_STATUS_MASK         (0x20000U)
1679 #define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT        (17U)
1680 /*! CH1_ERROR_STATUS - CH1_ERROR_STATUS
1681  *  0b0..An early termination from the device causes error IRQ.
1682  *  0b1..An AHB bus error causes error IRQ.
1683  */
1684 #define APBH_CTRL2_CH1_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
1685 #define APBH_CTRL2_CH2_ERROR_STATUS_MASK         (0x40000U)
1686 #define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT        (18U)
1687 /*! CH2_ERROR_STATUS - CH2_ERROR_STATUS
1688  *  0b0..An early termination from the device causes error IRQ.
1689  *  0b1..An AHB bus error causes error IRQ.
1690  */
1691 #define APBH_CTRL2_CH2_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
1692 #define APBH_CTRL2_CH3_ERROR_STATUS_MASK         (0x80000U)
1693 #define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT        (19U)
1694 /*! CH3_ERROR_STATUS - CH3_ERROR_STATUS
1695  *  0b0..An early termination from the device causes error IRQ.
1696  *  0b1..An AHB bus error causes error IRQ.
1697  */
1698 #define APBH_CTRL2_CH3_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
1699 #define APBH_CTRL2_CH4_ERROR_STATUS_MASK         (0x100000U)
1700 #define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT        (20U)
1701 /*! CH4_ERROR_STATUS - CH4_ERROR_STATUS
1702  *  0b0..An early termination from the device causes error IRQ.
1703  *  0b1..An AHB bus error causes error IRQ.
1704  */
1705 #define APBH_CTRL2_CH4_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
1706 #define APBH_CTRL2_CH5_ERROR_STATUS_MASK         (0x200000U)
1707 #define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT        (21U)
1708 /*! CH5_ERROR_STATUS - CH5_ERROR_STATUS
1709  *  0b0..An early termination from the device causes error IRQ.
1710  *  0b1..An AHB bus error causes error IRQ.
1711  */
1712 #define APBH_CTRL2_CH5_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
1713 #define APBH_CTRL2_CH6_ERROR_STATUS_MASK         (0x400000U)
1714 #define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT        (22U)
1715 /*! CH6_ERROR_STATUS - CH6_ERROR_STATUS
1716  *  0b0..An early termination from the device causes error IRQ.
1717  *  0b1..An AHB bus error causes error IRQ.
1718  */
1719 #define APBH_CTRL2_CH6_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
1720 #define APBH_CTRL2_CH7_ERROR_STATUS_MASK         (0x800000U)
1721 #define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT        (23U)
1722 /*! CH7_ERROR_STATUS - CH7_ERROR_STATUS
1723  *  0b0..An early termination from the device causes error IRQ.
1724  *  0b1..An AHB bus error causes error IRQ.
1725  */
1726 #define APBH_CTRL2_CH7_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
1727 #define APBH_CTRL2_CH8_ERROR_STATUS_MASK         (0x1000000U)
1728 #define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT        (24U)
1729 /*! CH8_ERROR_STATUS - CH8_ERROR_STATUS
1730  *  0b0..An early termination from the device causes error IRQ.
1731  *  0b1..An AHB bus error causes error IRQ.
1732  */
1733 #define APBH_CTRL2_CH8_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
1734 #define APBH_CTRL2_CH9_ERROR_STATUS_MASK         (0x2000000U)
1735 #define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT        (25U)
1736 /*! CH9_ERROR_STATUS - CH9_ERROR_STATUS
1737  *  0b0..An early termination from the device causes error IRQ.
1738  *  0b1..An AHB bus error causes error IRQ.
1739  */
1740 #define APBH_CTRL2_CH9_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
1741 #define APBH_CTRL2_CH10_ERROR_STATUS_MASK        (0x4000000U)
1742 #define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT       (26U)
1743 /*! CH10_ERROR_STATUS - CH10_ERROR_STATUS
1744  *  0b0..An early termination from the device causes error IRQ.
1745  *  0b1..An AHB bus error causes error IRQ.
1746  */
1747 #define APBH_CTRL2_CH10_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
1748 #define APBH_CTRL2_CH11_ERROR_STATUS_MASK        (0x8000000U)
1749 #define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT       (27U)
1750 /*! CH11_ERROR_STATUS - CH11_ERROR_STATUS
1751  *  0b0..An early termination from the device causes error IRQ.
1752  *  0b1..An AHB bus error causes error IRQ.
1753  */
1754 #define APBH_CTRL2_CH11_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
1755 #define APBH_CTRL2_CH12_ERROR_STATUS_MASK        (0x10000000U)
1756 #define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT       (28U)
1757 /*! CH12_ERROR_STATUS - CH12_ERROR_STATUS
1758  *  0b0..An early termination from the device causes error IRQ.
1759  *  0b1..An AHB bus error causes error IRQ.
1760  */
1761 #define APBH_CTRL2_CH12_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
1762 #define APBH_CTRL2_CH13_ERROR_STATUS_MASK        (0x20000000U)
1763 #define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT       (29U)
1764 /*! CH13_ERROR_STATUS - CH13_ERROR_STATUS
1765  *  0b0..An early termination from the device causes error IRQ.
1766  *  0b1..An AHB bus error causes error IRQ.
1767  */
1768 #define APBH_CTRL2_CH13_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
1769 #define APBH_CTRL2_CH14_ERROR_STATUS_MASK        (0x40000000U)
1770 #define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT       (30U)
1771 /*! CH14_ERROR_STATUS - CH14_ERROR_STATUS
1772  *  0b0..An early termination from the device causes error IRQ.
1773  *  0b1..An AHB bus error causes error IRQ.
1774  */
1775 #define APBH_CTRL2_CH14_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
1776 #define APBH_CTRL2_CH15_ERROR_STATUS_MASK        (0x80000000U)
1777 #define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT       (31U)
1778 /*! CH15_ERROR_STATUS - CH15_ERROR_STATUS
1779  *  0b0..An early termination from the device causes error IRQ.
1780  *  0b1..An AHB bus error causes error IRQ.
1781  */
1782 #define APBH_CTRL2_CH15_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
1783 /*! @} */
1784 
1785 /*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
1786 /*! @{ */
1787 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK    (0xFFFFU)
1788 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT   (0U)
1789 /*! FREEZE_CHANNEL - FREEZE_CHANNEL
1790  *  0b0000000000000001..
1791  *  0b0000000000000010..
1792  *  0b0000000000000100..
1793  *  0b0000000000001000..
1794  *  0b0000000000010000..
1795  *  0b0000000000100000..
1796  *  0b0000000001000000..
1797  *  0b0000000010000000..
1798  *  0b0000000100000000..
1799  */
1800 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
1801 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK     (0xFFFF0000U)
1802 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT    (16U)
1803 /*! RESET_CHANNEL - RESET_CHANNEL
1804  *  0b0000000000000001..
1805  *  0b0000000000000010..
1806  *  0b0000000000000100..
1807  *  0b0000000000001000..
1808  *  0b0000000000010000..
1809  *  0b0000000000100000..
1810  *  0b0000000001000000..
1811  *  0b0000000010000000..
1812  *  0b0000000100000000..
1813  */
1814 #define APBH_CHANNEL_CTRL_RESET_CHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
1815 /*! @} */
1816 
1817 /*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
1818 /*! @{ */
1819 #define APBH_DMA_BURST_SIZE_CH0_MASK             (0x3U)
1820 #define APBH_DMA_BURST_SIZE_CH0_SHIFT            (0U)
1821 /*! CH0 - CH0
1822  */
1823 #define APBH_DMA_BURST_SIZE_CH0(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
1824 #define APBH_DMA_BURST_SIZE_CH1_MASK             (0xCU)
1825 #define APBH_DMA_BURST_SIZE_CH1_SHIFT            (2U)
1826 /*! CH1 - CH1
1827  */
1828 #define APBH_DMA_BURST_SIZE_CH1(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
1829 #define APBH_DMA_BURST_SIZE_CH2_MASK             (0x30U)
1830 #define APBH_DMA_BURST_SIZE_CH2_SHIFT            (4U)
1831 /*! CH2 - CH2
1832  */
1833 #define APBH_DMA_BURST_SIZE_CH2(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
1834 #define APBH_DMA_BURST_SIZE_CH3_MASK             (0xC0U)
1835 #define APBH_DMA_BURST_SIZE_CH3_SHIFT            (6U)
1836 /*! CH3 - CH3
1837  */
1838 #define APBH_DMA_BURST_SIZE_CH3(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
1839 #define APBH_DMA_BURST_SIZE_CH4_MASK             (0x300U)
1840 #define APBH_DMA_BURST_SIZE_CH4_SHIFT            (8U)
1841 /*! CH4 - CH4
1842  */
1843 #define APBH_DMA_BURST_SIZE_CH4(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
1844 #define APBH_DMA_BURST_SIZE_CH5_MASK             (0xC00U)
1845 #define APBH_DMA_BURST_SIZE_CH5_SHIFT            (10U)
1846 /*! CH5 - CH5
1847  */
1848 #define APBH_DMA_BURST_SIZE_CH5(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
1849 #define APBH_DMA_BURST_SIZE_CH6_MASK             (0x3000U)
1850 #define APBH_DMA_BURST_SIZE_CH6_SHIFT            (12U)
1851 /*! CH6 - CH6
1852  */
1853 #define APBH_DMA_BURST_SIZE_CH6(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
1854 #define APBH_DMA_BURST_SIZE_CH7_MASK             (0xC000U)
1855 #define APBH_DMA_BURST_SIZE_CH7_SHIFT            (14U)
1856 /*! CH7 - CH7
1857  */
1858 #define APBH_DMA_BURST_SIZE_CH7(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
1859 #define APBH_DMA_BURST_SIZE_CH8_MASK             (0x30000U)
1860 #define APBH_DMA_BURST_SIZE_CH8_SHIFT            (16U)
1861 /*! CH8 - CH8
1862  *  0b00..
1863  *  0b01..
1864  *  0b10..
1865  */
1866 #define APBH_DMA_BURST_SIZE_CH8(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
1867 /*! @} */
1868 
1869 /*! @name DEBUG - AHB to APBH DMA Debug Register */
1870 /*! @{ */
1871 #define APBH_DEBUG_GPMI_ONE_FIFO_MASK            (0x1U)
1872 #define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT           (0U)
1873 /*! GPMI_ONE_FIFO - GPMI_ONE_FIFO
1874  */
1875 #define APBH_DEBUG_GPMI_ONE_FIFO(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
1876 /*! @} */
1877 
1878 /*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
1879 /*! @{ */
1880 #define APBH_CH_CURCMDAR_CMD_ADDR_MASK           (0xFFFFFFFFU)
1881 #define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT          (0U)
1882 /*! CMD_ADDR - CMD_ADDR
1883  */
1884 #define APBH_CH_CURCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
1885 /*! @} */
1886 
1887 /* The count of APBH_CH_CURCMDAR */
1888 #define APBH_CH_CURCMDAR_COUNT                   (16U)
1889 
1890 /*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
1891 /*! @{ */
1892 #define APBH_CH_NXTCMDAR_CMD_ADDR_MASK           (0xFFFFFFFFU)
1893 #define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT          (0U)
1894 /*! CMD_ADDR - CMD_ADDR
1895  */
1896 #define APBH_CH_NXTCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
1897 /*! @} */
1898 
1899 /* The count of APBH_CH_NXTCMDAR */
1900 #define APBH_CH_NXTCMDAR_COUNT                   (16U)
1901 
1902 /*! @name CH_CMD - APBH DMA Channel n Command Register */
1903 /*! @{ */
1904 #define APBH_CH_CMD_COMMAND_MASK                 (0x3U)
1905 #define APBH_CH_CMD_COMMAND_SHIFT                (0U)
1906 /*! COMMAND - COMMAND
1907  *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
1908  *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
1909  *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
1910  *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
1911  *        device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
1912  *        pointer if the peripheral sense line is false.
1913  */
1914 #define APBH_CH_CMD_COMMAND(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
1915 #define APBH_CH_CMD_CHAIN_MASK                   (0x4U)
1916 #define APBH_CH_CMD_CHAIN_SHIFT                  (2U)
1917 /*! CHAIN - CHAIN
1918  */
1919 #define APBH_CH_CMD_CHAIN(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
1920 #define APBH_CH_CMD_IRQONCMPLT_MASK              (0x8U)
1921 #define APBH_CH_CMD_IRQONCMPLT_SHIFT             (3U)
1922 /*! IRQONCMPLT - IRQONCMPLT
1923  */
1924 #define APBH_CH_CMD_IRQONCMPLT(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
1925 #define APBH_CH_CMD_NANDLOCK_MASK                (0x10U)
1926 #define APBH_CH_CMD_NANDLOCK_SHIFT               (4U)
1927 /*! NANDLOCK - NANDLOCK
1928  */
1929 #define APBH_CH_CMD_NANDLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
1930 #define APBH_CH_CMD_NANDWAIT4READY_MASK          (0x20U)
1931 #define APBH_CH_CMD_NANDWAIT4READY_SHIFT         (5U)
1932 /*! NANDWAIT4READY - NANDWAIT4READY
1933  */
1934 #define APBH_CH_CMD_NANDWAIT4READY(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
1935 #define APBH_CH_CMD_SEMAPHORE_MASK               (0x40U)
1936 #define APBH_CH_CMD_SEMAPHORE_SHIFT              (6U)
1937 /*! SEMAPHORE - SEMAPHORE
1938  */
1939 #define APBH_CH_CMD_SEMAPHORE(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
1940 #define APBH_CH_CMD_WAIT4ENDCMD_MASK             (0x80U)
1941 #define APBH_CH_CMD_WAIT4ENDCMD_SHIFT            (7U)
1942 /*! WAIT4ENDCMD - WAIT4ENDCMD
1943  */
1944 #define APBH_CH_CMD_WAIT4ENDCMD(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
1945 #define APBH_CH_CMD_HALTONTERMINATE_MASK         (0x100U)
1946 #define APBH_CH_CMD_HALTONTERMINATE_SHIFT        (8U)
1947 /*! HALTONTERMINATE - HALTONTERMINATE
1948  */
1949 #define APBH_CH_CMD_HALTONTERMINATE(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
1950 #define APBH_CH_CMD_CMDWORDS_MASK                (0xF000U)
1951 #define APBH_CH_CMD_CMDWORDS_SHIFT               (12U)
1952 /*! CMDWORDS - CMDWORDS
1953  */
1954 #define APBH_CH_CMD_CMDWORDS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
1955 #define APBH_CH_CMD_XFER_COUNT_MASK              (0xFFFF0000U)
1956 #define APBH_CH_CMD_XFER_COUNT_SHIFT             (16U)
1957 /*! XFER_COUNT - XFER_COUNT
1958  */
1959 #define APBH_CH_CMD_XFER_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
1960 /*! @} */
1961 
1962 /* The count of APBH_CH_CMD */
1963 #define APBH_CH_CMD_COUNT                        (16U)
1964 
1965 /*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
1966 /*! @{ */
1967 #define APBH_CH_BAR_ADDRESS_MASK                 (0xFFFFFFFFU)
1968 #define APBH_CH_BAR_ADDRESS_SHIFT                (0U)
1969 /*! ADDRESS - ADDRESS
1970  */
1971 #define APBH_CH_BAR_ADDRESS(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
1972 /*! @} */
1973 
1974 /* The count of APBH_CH_BAR */
1975 #define APBH_CH_BAR_COUNT                        (16U)
1976 
1977 /*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
1978 /*! @{ */
1979 #define APBH_CH_SEMA_INCREMENT_SEMA_MASK         (0xFFU)
1980 #define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT        (0U)
1981 /*! INCREMENT_SEMA - INCREMENT_SEMA
1982  */
1983 #define APBH_CH_SEMA_INCREMENT_SEMA(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
1984 #define APBH_CH_SEMA_PHORE_MASK                  (0xFF0000U)
1985 #define APBH_CH_SEMA_PHORE_SHIFT                 (16U)
1986 /*! PHORE - PHORE
1987  */
1988 #define APBH_CH_SEMA_PHORE(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
1989 /*! @} */
1990 
1991 /* The count of APBH_CH_SEMA */
1992 #define APBH_CH_SEMA_COUNT                       (16U)
1993 
1994 /*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
1995 /*! @{ */
1996 #define APBH_CH_DEBUG1_STATEMACHINE_MASK         (0x1FU)
1997 #define APBH_CH_DEBUG1_STATEMACHINE_SHIFT        (0U)
1998 /*! STATEMACHINE - STATEMACHINE
1999  *  0b00000..This is the idle state of the DMA state machine.
2000  *  0b00001..State in which the DMA is waiting to receive the first word of a command.
2001  *  0b00010..State in which the DMA is waiting to receive the third word of a command.
2002  *  0b00011..State in which the DMA is waiting to receive the second word of a command.
2003  *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2004  *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
2005  *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
2006  *           PIO words when PIO count is greater than 1.
2007  *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
2008  *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
2009  *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
2010  *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2011  *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2012  *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
2013  *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
2014  *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
2015  *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
2016  *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
2017  *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
2018  *           effectively halts. A channel reset is required to exit this state
2019  *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
2020  *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
2021  *           indicates that the external device is ready.
2022  */
2023 #define APBH_CH_DEBUG1_STATEMACHINE(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
2024 #define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK         (0x100000U)
2025 #define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT        (20U)
2026 /*! WR_FIFO_FULL - WR_FIFO_FULL
2027  */
2028 #define APBH_CH_DEBUG1_WR_FIFO_FULL(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
2029 #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK        (0x200000U)
2030 #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT       (21U)
2031 /*! WR_FIFO_EMPTY - WR_FIFO_EMPTY
2032  */
2033 #define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
2034 #define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK         (0x400000U)
2035 #define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT        (22U)
2036 /*! RD_FIFO_FULL - RD_FIFO_FULL
2037  */
2038 #define APBH_CH_DEBUG1_RD_FIFO_FULL(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
2039 #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK        (0x800000U)
2040 #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT       (23U)
2041 /*! RD_FIFO_EMPTY - RD_FIFO_EMPTY
2042  */
2043 #define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
2044 #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK     (0x1000000U)
2045 #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT    (24U)
2046 /*! NEXTCMDADDRVALID - NEXTCMDADDRVALID
2047  */
2048 #define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
2049 #define APBH_CH_DEBUG1_READY_MASK                (0x4000000U)
2050 #define APBH_CH_DEBUG1_READY_SHIFT               (26U)
2051 /*! READY - READY
2052  */
2053 #define APBH_CH_DEBUG1_READY(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
2054 #define APBH_CH_DEBUG1_END_MASK                  (0x10000000U)
2055 #define APBH_CH_DEBUG1_END_SHIFT                 (28U)
2056 /*! END - END
2057  */
2058 #define APBH_CH_DEBUG1_END(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
2059 #define APBH_CH_DEBUG1_KICK_MASK                 (0x20000000U)
2060 #define APBH_CH_DEBUG1_KICK_SHIFT                (29U)
2061 /*! KICK - KICK
2062  */
2063 #define APBH_CH_DEBUG1_KICK(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
2064 #define APBH_CH_DEBUG1_BURST_MASK                (0x40000000U)
2065 #define APBH_CH_DEBUG1_BURST_SHIFT               (30U)
2066 /*! BURST - BURST
2067  */
2068 #define APBH_CH_DEBUG1_BURST(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
2069 #define APBH_CH_DEBUG1_REQ_MASK                  (0x80000000U)
2070 #define APBH_CH_DEBUG1_REQ_SHIFT                 (31U)
2071 /*! REQ - REQ
2072  */
2073 #define APBH_CH_DEBUG1_REQ(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
2074 /*! @} */
2075 
2076 /* The count of APBH_CH_DEBUG1 */
2077 #define APBH_CH_DEBUG1_COUNT                     (16U)
2078 
2079 /*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
2080 /*! @{ */
2081 #define APBH_CH_DEBUG2_AHB_BYTES_MASK            (0xFFFFU)
2082 #define APBH_CH_DEBUG2_AHB_BYTES_SHIFT           (0U)
2083 /*! AHB_BYTES - AHB_BYTES
2084  */
2085 #define APBH_CH_DEBUG2_AHB_BYTES(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
2086 #define APBH_CH_DEBUG2_APB_BYTES_MASK            (0xFFFF0000U)
2087 #define APBH_CH_DEBUG2_APB_BYTES_SHIFT           (16U)
2088 /*! APB_BYTES - APB_BYTES
2089  */
2090 #define APBH_CH_DEBUG2_APB_BYTES(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
2091 /*! @} */
2092 
2093 /* The count of APBH_CH_DEBUG2 */
2094 #define APBH_CH_DEBUG2_COUNT                     (16U)
2095 
2096 /*! @name VERSION - APBH Bridge Version Register */
2097 /*! @{ */
2098 #define APBH_VERSION_STEP_MASK                   (0xFFFFU)
2099 #define APBH_VERSION_STEP_SHIFT                  (0U)
2100 /*! STEP - STEP
2101  */
2102 #define APBH_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
2103 #define APBH_VERSION_MINOR_MASK                  (0xFF0000U)
2104 #define APBH_VERSION_MINOR_SHIFT                 (16U)
2105 /*! MINOR - MINOR
2106  */
2107 #define APBH_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
2108 #define APBH_VERSION_MAJOR_MASK                  (0xFF000000U)
2109 #define APBH_VERSION_MAJOR_SHIFT                 (24U)
2110 /*! MAJOR - MAJOR
2111  */
2112 #define APBH_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
2113 /*! @} */
2114 
2115 
2116 /*!
2117  * @}
2118  */ /* end of group APBH_Register_Masks */
2119 
2120 
2121 /* APBH - Peripheral instance base addresses */
2122 /** Peripheral CONNECTIVITY__APBH base address */
2123 #define CONNECTIVITY__APBH_BASE                  (0x5B810000u)
2124 /** Peripheral CONNECTIVITY__APBH base pointer */
2125 #define CONNECTIVITY__APBH                       ((APBH_Type *)CONNECTIVITY__APBH_BASE)
2126 /** Array initializer of APBH peripheral base addresses */
2127 #define APBH_BASE_ADDRS                          { CONNECTIVITY__APBH_BASE }
2128 /** Array initializer of APBH peripheral base pointers */
2129 #define APBH_BASE_PTRS                           { CONNECTIVITY__APBH }
2130 /** Interrupt vectors for the APBH peripheral type */
2131 #define APBH_IRQS                                { CONNECTIVITY_APBHDMA_IRQn }
2132 
2133 /*!
2134  * @}
2135  */ /* end of group APBH_Peripheral_Access_Layer */
2136 
2137 
2138 /* ----------------------------------------------------------------------------
2139    -- ASMC Peripheral Access Layer
2140    ---------------------------------------------------------------------------- */
2141 
2142 /*!
2143  * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer
2144  * @{
2145  */
2146 
2147 /** ASMC - Register Layout Typedef */
2148 typedef struct {
2149   __I  uint32_t SRS;                               /**< System Reset Status Register, offset: 0x0 */
2150        uint8_t RESERVED_0[4];
2151   __IO uint32_t PMPROT;                            /**< Power Mode Protection register, offset: 0x8 */
2152   __IO uint32_t PMCTRL;                            /**< Power Mode Control register, offset: 0xC */
2153   __IO uint32_t STOPCTRL;                          /**< Stop Control Register, offset: 0x10 */
2154   __I  uint32_t PMSTAT;                            /**< Power Mode Status register, offset: 0x14 */
2155 } ASMC_Type;
2156 
2157 /* ----------------------------------------------------------------------------
2158    -- ASMC Register Masks
2159    ---------------------------------------------------------------------------- */
2160 
2161 /*!
2162  * @addtogroup ASMC_Register_Masks ASMC Register Masks
2163  * @{
2164  */
2165 
2166 /*! @name SRS - System Reset Status Register */
2167 /*! @{ */
2168 #define ASMC_SRS_WAKEUP_MASK                     (0x1U)
2169 #define ASMC_SRS_WAKEUP_SHIFT                    (0U)
2170 /*! WAKEUP - Low Leakage Wakeup Reset
2171  *  0b0..Reset not caused by LLWU module wakeup source
2172  *  0b1..Reset caused by LLWU module wakeup source
2173  */
2174 #define ASMC_SRS_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK)
2175 #define ASMC_SRS_WDOG1_MASK                      (0x20U)
2176 #define ASMC_SRS_WDOG1_SHIFT                     (5U)
2177 /*! WDOG1 - Watchdog
2178  *  0b0..Reset not caused by watchdog timeout
2179  *  0b1..Reset caused by watchdog timeout
2180  */
2181 #define ASMC_SRS_WDOG1(x)                        (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK)
2182 #define ASMC_SRS_RES_MASK                        (0x40U)
2183 #define ASMC_SRS_RES_SHIFT                       (6U)
2184 /*! RES - Chip Reset not POR
2185  *  0b0..Chip Reset did not occur
2186  *  0b1..Chip Reset caused by a source other than POR occured
2187  */
2188 #define ASMC_SRS_RES(x)                          (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK)
2189 #define ASMC_SRS_POR_MASK                        (0x80U)
2190 #define ASMC_SRS_POR_SHIFT                       (7U)
2191 /*! POR - Power-On Reset
2192  *  0b0..Reset not caused by POR
2193  *  0b1..Reset caused by POR
2194  */
2195 #define ASMC_SRS_POR(x)                          (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK)
2196 #define ASMC_SRS_LOCKUP_MASK                     (0x200U)
2197 #define ASMC_SRS_LOCKUP_SHIFT                    (9U)
2198 /*! LOCKUP - Core 1 Lockup
2199  *  0b0..Reset not caused by core LOCKUP event
2200  *  0b1..Reset caused by core LOCKUP event
2201  */
2202 #define ASMC_SRS_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK)
2203 #define ASMC_SRS_SW_MASK                         (0x400U)
2204 #define ASMC_SRS_SW_SHIFT                        (10U)
2205 /*! SW - Software
2206  *  0b0..Reset not caused by software setting of SYSRESETREQ bit
2207  *  0b1..Reset caused by software setting of SYSRESETREQ bit
2208  */
2209 #define ASMC_SRS_SW(x)                           (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK)
2210 #define ASMC_SRS_SACKERR_MASK                    (0x1000U)
2211 #define ASMC_SRS_SACKERR_SHIFT                   (12U)
2212 /*! SACKERR - Stop Mode Acknowledge Error Reset
2213  *  0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
2214  *  0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
2215  */
2216 #define ASMC_SRS_SACKERR(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK)
2217 /*! @} */
2218 
2219 /*! @name PMPROT - Power Mode Protection register */
2220 /*! @{ */
2221 #define ASMC_PMPROT_AVLLS_MASK                   (0x2U)
2222 #define ASMC_PMPROT_AVLLS_SHIFT                  (1U)
2223 /*! AVLLS - Allow Very-Low-Leakage Stop Mode
2224  *  0b0..Not Allowed
2225  *  0b1..Allowed
2226  */
2227 #define ASMC_PMPROT_AVLLS(x)                     (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK)
2228 #define ASMC_PMPROT_ALLS_MASK                    (0x8U)
2229 #define ASMC_PMPROT_ALLS_SHIFT                   (3U)
2230 /*! ALLS - Allow Low-Leakage Stop Mode
2231  *  0b0..Not Allowed
2232  *  0b1..Allowed
2233  */
2234 #define ASMC_PMPROT_ALLS(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK)
2235 #define ASMC_PMPROT_AVLP_MASK                    (0x20U)
2236 #define ASMC_PMPROT_AVLP_SHIFT                   (5U)
2237 /*! AVLP - Allow Very-Low-Power Modes
2238  *  0b0..VLPR, VLPW, and VLPS are not allowed.
2239  *  0b1..VLPR, VLPW, and VLPS are allowed.
2240  */
2241 #define ASMC_PMPROT_AVLP(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK)
2242 #define ASMC_PMPROT_AHSRUN_MASK                  (0x80U)
2243 #define ASMC_PMPROT_AHSRUN_SHIFT                 (7U)
2244 /*! AHSRUN - Allow High Speed Run mode
2245  *  0b0..HSRUN is not allowed
2246  *  0b1..HSRUN is allowed
2247  */
2248 #define ASMC_PMPROT_AHSRUN(x)                    (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK)
2249 /*! @} */
2250 
2251 /*! @name PMCTRL - Power Mode Control register */
2252 /*! @{ */
2253 #define ASMC_PMCTRL_STOPM_MASK                   (0x7U)
2254 #define ASMC_PMCTRL_STOPM_SHIFT                  (0U)
2255 /*! STOPM - Stop Mode Control
2256  *  0b000..Normal Stop (STOP)
2257  *  0b001..Reserved
2258  *  0b010..Very-Low-Power Stop (VLPS)
2259  *  0b011..Low-leakage stop
2260  *  0b100..Very-low-leakage stop
2261  *  0b101..Reserved
2262  *  0b110..Reseved
2263  *  0b111..Reserved
2264  */
2265 #define ASMC_PMCTRL_STOPM(x)                     (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK)
2266 #define ASMC_PMCTRL_RUNM_MASK                    (0x60U)
2267 #define ASMC_PMCTRL_RUNM_SHIFT                   (5U)
2268 /*! RUNM - Run Mode Control
2269  *  0b00..Normal Run mode (RUN)
2270  *  0b01..Reserved
2271  *  0b10..Very-Low-Power Run mode (VLPR)
2272  *  0b11..High Speed Run mode (HSRUN)
2273  */
2274 #define ASMC_PMCTRL_RUNM(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK)
2275 /*! @} */
2276 
2277 /*! @name STOPCTRL - Stop Control Register */
2278 /*! @{ */
2279 #define ASMC_STOPCTRL_PSTOPO_MASK                (0xC0U)
2280 #define ASMC_STOPCTRL_PSTOPO_SHIFT               (6U)
2281 /*! PSTOPO - Partial Stop Option
2282  *  0b00..STOP - Normal Stop mode
2283  *  0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
2284  *  0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
2285  *  0b11..Reserved
2286  */
2287 #define ASMC_STOPCTRL_PSTOPO(x)                  (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK)
2288 /*! @} */
2289 
2290 /*! @name PMSTAT - Power Mode Status register */
2291 /*! @{ */
2292 #define ASMC_PMSTAT_PMSTAT_MASK                  (0xFFU)  /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2293 #define ASMC_PMSTAT_PMSTAT_SHIFT                 (0U)
2294 /*! PMSTAT - Power Mode Status
2295  *  0b00000001..Current power mode is RUN.
2296  *  0b00000010..Current power mode is STOP.
2297  *  0b00000100..Current power mode is VLPR.
2298  *  0b00001000..Current power mode is VLPW.
2299  *  0b00010000..Current power mode is VLPS.
2300  *  0b00100000..Current power mode is LLS.
2301  *  0b01000000..Current power mode is VLLS.
2302  *  0b10000000..Current power mode is HSRUN
2303  */
2304 #define ASMC_PMSTAT_PMSTAT(x)                    (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK)  /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2305 /*! @} */
2306 
2307 
2308 /*!
2309  * @}
2310  */ /* end of group ASMC_Register_Masks */
2311 
2312 
2313 /* ASMC - Peripheral instance base addresses */
2314 /** Peripheral CM4__ASMC base address */
2315 #define CM4__ASMC_BASE                           (0x41410000u)
2316 /** Peripheral CM4__ASMC base pointer */
2317 #define CM4__ASMC                                ((ASMC_Type *)CM4__ASMC_BASE)
2318 /** Peripheral SCU__ASMC base address */
2319 #define SCU__ASMC_BASE                           (0x33410000u)
2320 /** Peripheral SCU__ASMC base pointer */
2321 #define SCU__ASMC                                ((ASMC_Type *)SCU__ASMC_BASE)
2322 /** Array initializer of ASMC peripheral base addresses */
2323 #define ASMC_BASE_ADDRS                          { CM4__ASMC_BASE, SCU__ASMC_BASE }
2324 /** Array initializer of ASMC peripheral base pointers */
2325 #define ASMC_BASE_PTRS                           { CM4__ASMC, SCU__ASMC }
2326 
2327 /*!
2328  * @}
2329  */ /* end of group ASMC_Peripheral_Access_Layer */
2330 
2331 
2332 /* ----------------------------------------------------------------------------
2333    -- ASRC Peripheral Access Layer
2334    ---------------------------------------------------------------------------- */
2335 
2336 /*!
2337  * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
2338  * @{
2339  */
2340 
2341 /** ASRC - Register Layout Typedef */
2342 typedef struct {
2343   __IO uint32_t ASRCTR;                            /**< ASRC Control Register, offset: 0x0 */
2344   __IO uint32_t ASRIER;                            /**< ASRC Interrupt Enable Register, offset: 0x4 */
2345        uint8_t RESERVED_0[4];
2346   __IO uint32_t ASRCNCR;                           /**< ASRC Channel Number Configuration Register, offset: 0xC */
2347   __IO uint32_t ASRCFG;                            /**< ASRC Filter Configuration Status Register, offset: 0x10 */
2348   __IO uint32_t ASRCSR;                            /**< ASRC Clock Source Register, offset: 0x14 */
2349   __IO uint32_t ASRCDR1;                           /**< ASRC Clock Divider Register 1, offset: 0x18 */
2350   __IO uint32_t ASRCDR2;                           /**< ASRC Clock Divider Register 2, offset: 0x1C */
2351   __I  uint32_t ASRSTR;                            /**< ASRC Status Register, offset: 0x20 */
2352        uint8_t RESERVED_1[28];
2353   __IO uint32_t ASRPM[5];                          /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
2354   __IO uint32_t ASRTFR1;                           /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
2355        uint8_t RESERVED_2[4];
2356   __IO uint32_t ASRCCR;                            /**< ASRC Channel Counter Register, offset: 0x5C */
2357   __O  uint32_t ASRDIA;                            /**< ASRC Data Input Register for Pair x, offset: 0x60 */
2358   __I  uint32_t ASRDOA;                            /**< ASRC Data Output Register for Pair x, offset: 0x64 */
2359   __O  uint32_t ASRDIB;                            /**< ASRC Data Input Register for Pair x, offset: 0x68 */
2360   __I  uint32_t ASRDOB;                            /**< ASRC Data Output Register for Pair x, offset: 0x6C */
2361   __O  uint32_t ASRDIC;                            /**< ASRC Data Input Register for Pair x, offset: 0x70 */
2362   __I  uint32_t ASRDOC;                            /**< ASRC Data Output Register for Pair x, offset: 0x74 */
2363        uint8_t RESERVED_3[8];
2364   __IO uint32_t ASRIDRHA;                          /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
2365   __IO uint32_t ASRIDRLA;                          /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
2366   __IO uint32_t ASRIDRHB;                          /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
2367   __IO uint32_t ASRIDRLB;                          /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
2368   __IO uint32_t ASRIDRHC;                          /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
2369   __IO uint32_t ASRIDRLC;                          /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
2370   __IO uint32_t ASR76K;                            /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
2371   __IO uint32_t ASR56K;                            /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
2372   __IO uint32_t ASRMCRA;                           /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
2373   __I  uint32_t ASRFSTA;                           /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
2374   __IO uint32_t ASRMCRB;                           /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
2375   __I  uint32_t ASRFSTB;                           /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
2376   __IO uint32_t ASRMCRC;                           /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
2377   __I  uint32_t ASRFSTC;                           /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
2378        uint8_t RESERVED_4[8];
2379   __IO uint32_t ASRMCR1[3];                        /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
2380 } ASRC_Type;
2381 
2382 /* ----------------------------------------------------------------------------
2383    -- ASRC Register Masks
2384    ---------------------------------------------------------------------------- */
2385 
2386 /*!
2387  * @addtogroup ASRC_Register_Masks ASRC Register Masks
2388  * @{
2389  */
2390 
2391 /*! @name ASRCTR - ASRC Control Register */
2392 /*! @{ */
2393 #define ASRC_ASRCTR_ASRCEN_MASK                  (0x1U)
2394 #define ASRC_ASRCTR_ASRCEN_SHIFT                 (0U)
2395 /*! ASRCEN - ASRCEN
2396  */
2397 #define ASRC_ASRCTR_ASRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
2398 #define ASRC_ASRCTR_ASREA_MASK                   (0x2U)
2399 #define ASRC_ASRCTR_ASREA_SHIFT                  (1U)
2400 /*! ASREA - ASREA
2401  */
2402 #define ASRC_ASRCTR_ASREA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
2403 #define ASRC_ASRCTR_ASREB_MASK                   (0x4U)
2404 #define ASRC_ASRCTR_ASREB_SHIFT                  (2U)
2405 /*! ASREB - ASREB
2406  */
2407 #define ASRC_ASRCTR_ASREB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
2408 #define ASRC_ASRCTR_ASREC_MASK                   (0x8U)
2409 #define ASRC_ASRCTR_ASREC_SHIFT                  (3U)
2410 /*! ASREC - ASREC
2411  */
2412 #define ASRC_ASRCTR_ASREC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
2413 #define ASRC_ASRCTR_SRST_MASK                    (0x10U)
2414 #define ASRC_ASRCTR_SRST_SHIFT                   (4U)
2415 /*! SRST - SRST
2416  */
2417 #define ASRC_ASRCTR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
2418 #define ASRC_ASRCTR_IDRA_MASK                    (0x2000U)
2419 #define ASRC_ASRCTR_IDRA_SHIFT                   (13U)
2420 /*! IDRA - IDRA
2421  */
2422 #define ASRC_ASRCTR_IDRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
2423 #define ASRC_ASRCTR_USRA_MASK                    (0x4000U)
2424 #define ASRC_ASRCTR_USRA_SHIFT                   (14U)
2425 /*! USRA - USRA
2426  */
2427 #define ASRC_ASRCTR_USRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
2428 #define ASRC_ASRCTR_IDRB_MASK                    (0x8000U)
2429 #define ASRC_ASRCTR_IDRB_SHIFT                   (15U)
2430 /*! IDRB - IDRB
2431  */
2432 #define ASRC_ASRCTR_IDRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
2433 #define ASRC_ASRCTR_USRB_MASK                    (0x10000U)
2434 #define ASRC_ASRCTR_USRB_SHIFT                   (16U)
2435 /*! USRB - USRB
2436  */
2437 #define ASRC_ASRCTR_USRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
2438 #define ASRC_ASRCTR_IDRC_MASK                    (0x20000U)
2439 #define ASRC_ASRCTR_IDRC_SHIFT                   (17U)
2440 /*! IDRC - IDRC
2441  */
2442 #define ASRC_ASRCTR_IDRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
2443 #define ASRC_ASRCTR_USRC_MASK                    (0x40000U)
2444 #define ASRC_ASRCTR_USRC_SHIFT                   (18U)
2445 /*! USRC - USRC
2446  */
2447 #define ASRC_ASRCTR_USRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
2448 #define ASRC_ASRCTR_ATSA_MASK                    (0x100000U)
2449 #define ASRC_ASRCTR_ATSA_SHIFT                   (20U)
2450 /*! ATSA - ATSA
2451  */
2452 #define ASRC_ASRCTR_ATSA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
2453 #define ASRC_ASRCTR_ATSB_MASK                    (0x200000U)
2454 #define ASRC_ASRCTR_ATSB_SHIFT                   (21U)
2455 /*! ATSB - ATSB
2456  */
2457 #define ASRC_ASRCTR_ATSB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
2458 #define ASRC_ASRCTR_ATSC_MASK                    (0x400000U)
2459 #define ASRC_ASRCTR_ATSC_SHIFT                   (22U)
2460 /*! ATSC - ATSC
2461  */
2462 #define ASRC_ASRCTR_ATSC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
2463 /*! @} */
2464 
2465 /*! @name ASRIER - ASRC Interrupt Enable Register */
2466 /*! @{ */
2467 #define ASRC_ASRIER_ADIEA_MASK                   (0x1U)
2468 #define ASRC_ASRIER_ADIEA_SHIFT                  (0U)
2469 /*! ADIEA - ADIEA
2470  *  0b1..interrupt enabled
2471  *  0b0..interrupt disabled
2472  */
2473 #define ASRC_ASRIER_ADIEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
2474 #define ASRC_ASRIER_ADIEB_MASK                   (0x2U)
2475 #define ASRC_ASRIER_ADIEB_SHIFT                  (1U)
2476 /*! ADIEB - ADIEB
2477  *  0b1..interrupt enabled
2478  *  0b0..interrupt disabled
2479  */
2480 #define ASRC_ASRIER_ADIEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
2481 #define ASRC_ASRIER_ADIEC_MASK                   (0x4U)
2482 #define ASRC_ASRIER_ADIEC_SHIFT                  (2U)
2483 /*! ADIEC - ADIEC
2484  *  0b1..interrupt enabled
2485  *  0b0..interrupt disabled
2486  */
2487 #define ASRC_ASRIER_ADIEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
2488 #define ASRC_ASRIER_ADOEA_MASK                   (0x8U)
2489 #define ASRC_ASRIER_ADOEA_SHIFT                  (3U)
2490 /*! ADOEA - ADOEA
2491  *  0b1..interrupt enabled
2492  *  0b0..interrupt disabled
2493  */
2494 #define ASRC_ASRIER_ADOEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
2495 #define ASRC_ASRIER_ADOEB_MASK                   (0x10U)
2496 #define ASRC_ASRIER_ADOEB_SHIFT                  (4U)
2497 /*! ADOEB - ADOEB
2498  *  0b1..interrupt enabled
2499  *  0b0..interrupt disabled
2500  */
2501 #define ASRC_ASRIER_ADOEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
2502 #define ASRC_ASRIER_ADOEC_MASK                   (0x20U)
2503 #define ASRC_ASRIER_ADOEC_SHIFT                  (5U)
2504 /*! ADOEC - ADOEC
2505  *  0b1..interrupt enabled
2506  *  0b0..interrupt disabled
2507  */
2508 #define ASRC_ASRIER_ADOEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
2509 #define ASRC_ASRIER_AOLIE_MASK                   (0x40U)
2510 #define ASRC_ASRIER_AOLIE_SHIFT                  (6U)
2511 /*! AOLIE - AOLIE
2512  *  0b1..interrupt enabled
2513  *  0b0..interrupt disabled
2514  */
2515 #define ASRC_ASRIER_AOLIE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
2516 #define ASRC_ASRIER_AFPWE_MASK                   (0x80U)
2517 #define ASRC_ASRIER_AFPWE_SHIFT                  (7U)
2518 /*! AFPWE - AFPWE
2519  *  0b1..interrupt enabled
2520  *  0b0..interrupt disabled
2521  */
2522 #define ASRC_ASRIER_AFPWE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
2523 /*! @} */
2524 
2525 /*! @name ASRCNCR - ASRC Channel Number Configuration Register */
2526 /*! @{ */
2527 #define ASRC_ASRCNCR_ANCA_MASK                   (0xFU)
2528 #define ASRC_ASRCNCR_ANCA_SHIFT                  (0U)
2529 /*! ANCA - ANCA
2530  *  0b0000..0 channels in A (Pair A is disabled)
2531  *  0b0001..1 channel in A
2532  *  0b0010..2 channels in A
2533  *  0b0011..3 channels in A
2534  *  0b0100..4 channels in A
2535  *  0b0101..5 channels in A
2536  *  0b0110..6 channels in A
2537  *  0b0111..7 channels in A
2538  *  0b1000..8 channels in A
2539  *  0b1001..9 channels in A
2540  *  0b1010..10 channels in A
2541  *  0b1011-0b1111..Should not be used.
2542  */
2543 #define ASRC_ASRCNCR_ANCA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
2544 #define ASRC_ASRCNCR_ANCB_MASK                   (0xF0U)
2545 #define ASRC_ASRCNCR_ANCB_SHIFT                  (4U)
2546 /*! ANCB - ANCB
2547  *  0b0000..0 channels in B (Pair B is disabled)
2548  *  0b0001..1 channel in B
2549  *  0b0010..2 channels in B
2550  *  0b0011..3 channels in B
2551  *  0b0100..4 channels in B
2552  *  0b0101..5 channels in B
2553  *  0b0110..6 channels in B
2554  *  0b0111..7 channels in B
2555  *  0b1000..8 channels in B
2556  *  0b1001..9 channels in B
2557  *  0b1010..10 channels in B
2558  *  0b1011-0b1111..Should not be used.
2559  */
2560 #define ASRC_ASRCNCR_ANCB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
2561 #define ASRC_ASRCNCR_ANCC_MASK                   (0xF00U)
2562 #define ASRC_ASRCNCR_ANCC_SHIFT                  (8U)
2563 /*! ANCC - ANCC
2564  *  0b0000..0 channels in C (Pair C is disabled)
2565  *  0b0001..1 channel in C
2566  *  0b0010..2 channels in C
2567  *  0b0011..3 channels in C
2568  *  0b0100..4 channels in C
2569  *  0b0101..5 channels in C
2570  *  0b0110..6 channels in C
2571  *  0b0111..7 channels in C
2572  *  0b1000..8 channels in C
2573  *  0b1001..9 channels in C
2574  *  0b1010..10 channels in C
2575  *  0b1011-0b1111..Should not be used.
2576  */
2577 #define ASRC_ASRCNCR_ANCC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
2578 /*! @} */
2579 
2580 /*! @name ASRCFG - ASRC Filter Configuration Status Register */
2581 /*! @{ */
2582 #define ASRC_ASRCFG_PREMODA_MASK                 (0xC0U)
2583 #define ASRC_ASRCFG_PREMODA_SHIFT                (6U)
2584 /*! PREMODA - PREMODA
2585  *  0b00..Select Upsampling-by-2 as defined in
2586  *  0b01..Select Direct-Connection as defined in
2587  *  0b10..Select Downsampling-by-2 as defined in
2588  *  0b11..Select passthrough mode. In this case, POSTMODA[1-0] have no use.
2589  */
2590 #define ASRC_ASRCFG_PREMODA(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
2591 #define ASRC_ASRCFG_POSTMODA_MASK                (0x300U)
2592 #define ASRC_ASRCFG_POSTMODA_SHIFT               (8U)
2593 /*! POSTMODA - POSTMODA
2594  *  0b00..Select Upsampling-by-2 as defined in
2595  *  0b01..Select Direct-Connection as defined in
2596  *  0b10..Select Downsampling-by-2 as defined in
2597  */
2598 #define ASRC_ASRCFG_POSTMODA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
2599 #define ASRC_ASRCFG_PREMODB_MASK                 (0xC00U)
2600 #define ASRC_ASRCFG_PREMODB_SHIFT                (10U)
2601 /*! PREMODB - PREMODB
2602  *  0b00..Select Upsampling-by-2 as defined in
2603  *  0b01..Select Direct-Connection as defined in
2604  *  0b10..Select Downsampling-by-2 as defined in
2605  *  0b11..Select passthrough mode. In this case, POSTMODB[1-0] have no use.
2606  */
2607 #define ASRC_ASRCFG_PREMODB(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
2608 #define ASRC_ASRCFG_POSTMODB_MASK                (0x3000U)
2609 #define ASRC_ASRCFG_POSTMODB_SHIFT               (12U)
2610 /*! POSTMODB - POSTMODB
2611  *  0b00..Select Upsampling-by-2 as defined in
2612  *  0b01..Select Direct-Connection as defined in
2613  *  0b10..Select Downsampling-by-2 as defined in
2614  */
2615 #define ASRC_ASRCFG_POSTMODB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
2616 #define ASRC_ASRCFG_PREMODC_MASK                 (0xC000U)
2617 #define ASRC_ASRCFG_PREMODC_SHIFT                (14U)
2618 /*! PREMODC - PREMODC
2619  *  0b00..Select Upsampling-by-2 as defined in
2620  *  0b01..Select Direct-Connection as defined in
2621  *  0b10..Select Downsampling-by-2 as defined in
2622  *  0b11..Select passthrough mode. In this case, POSTMODC[1-0] have no use.
2623  */
2624 #define ASRC_ASRCFG_PREMODC(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
2625 #define ASRC_ASRCFG_POSTMODC_MASK                (0x30000U)
2626 #define ASRC_ASRCFG_POSTMODC_SHIFT               (16U)
2627 /*! POSTMODC - POSTMODC
2628  *  0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
2629  *  0b01..Select Direct-Connection as defined in Signal Processing Flow.
2630  *  0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
2631  */
2632 #define ASRC_ASRCFG_POSTMODC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
2633 #define ASRC_ASRCFG_NDPRA_MASK                   (0x40000U)
2634 #define ASRC_ASRCFG_NDPRA_SHIFT                  (18U)
2635 /*! NDPRA - NDPRA
2636  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2637  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2638  */
2639 #define ASRC_ASRCFG_NDPRA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
2640 #define ASRC_ASRCFG_NDPRB_MASK                   (0x80000U)
2641 #define ASRC_ASRCFG_NDPRB_SHIFT                  (19U)
2642 /*! NDPRB - NDPRB
2643  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2644  *  0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
2645  */
2646 #define ASRC_ASRCFG_NDPRB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
2647 #define ASRC_ASRCFG_NDPRC_MASK                   (0x100000U)
2648 #define ASRC_ASRCFG_NDPRC_SHIFT                  (20U)
2649 /*! NDPRC - NDPRC
2650  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2651  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2652  */
2653 #define ASRC_ASRCFG_NDPRC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
2654 #define ASRC_ASRCFG_INIRQA_MASK                  (0x200000U)
2655 #define ASRC_ASRCFG_INIRQA_SHIFT                 (21U)
2656 /*! INIRQA - INIRQA
2657  */
2658 #define ASRC_ASRCFG_INIRQA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
2659 #define ASRC_ASRCFG_INIRQB_MASK                  (0x400000U)
2660 #define ASRC_ASRCFG_INIRQB_SHIFT                 (22U)
2661 /*! INIRQB - INIRQB
2662  */
2663 #define ASRC_ASRCFG_INIRQB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
2664 #define ASRC_ASRCFG_INIRQC_MASK                  (0x800000U)
2665 #define ASRC_ASRCFG_INIRQC_SHIFT                 (23U)
2666 /*! INIRQC - INIRQC
2667  */
2668 #define ASRC_ASRCFG_INIRQC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
2669 /*! @} */
2670 
2671 /*! @name ASRCSR - ASRC Clock Source Register */
2672 /*! @{ */
2673 #define ASRC_ASRCSR_AICSA_MASK                   (0xFU)
2674 #define ASRC_ASRCSR_AICSA_SHIFT                  (0U)
2675 /*! AICSA - AICSA
2676  *  0b0000..bit clock 0
2677  *  0b0001..bit clock 1
2678  *  0b0010..bit clock 2
2679  *  0b0011..bit clock 3
2680  *  0b0100..bit clock 4
2681  *  0b0101..bit clock 5
2682  *  0b0110..bit clock 6
2683  *  0b0111..bit clock 7
2684  *  0b1000..bit clock 8
2685  *  0b1001..bit clock 9
2686  *  0b1010..bit clock A
2687  *  0b1011..bit clock B
2688  *  0b1100..bit clock C
2689  *  0b1101..bit clock D
2690  *  0b1110..bit clock E
2691  *  0b1111..clock disabled, connected to zero
2692  */
2693 #define ASRC_ASRCSR_AICSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
2694 #define ASRC_ASRCSR_AICSB_MASK                   (0xF0U)
2695 #define ASRC_ASRCSR_AICSB_SHIFT                  (4U)
2696 /*! AICSB - AICSB
2697  *  0b0000..bit clock 0
2698  *  0b0001..bit clock 1
2699  *  0b0010..bit clock 2
2700  *  0b0011..bit clock 3
2701  *  0b0100..bit clock 4
2702  *  0b0101..bit clock 5
2703  *  0b0110..bit clock 6
2704  *  0b0111..bit clock 7
2705  *  0b1000..bit clock 8
2706  *  0b1001..bit clock 9
2707  *  0b1010..bit clock A
2708  *  0b1011..bit clock B
2709  *  0b1100..bit clock C
2710  *  0b1101..bit clock D
2711  *  0b1110..bit clock E
2712  *  0b1111..clock disabled, connected to zero
2713  */
2714 #define ASRC_ASRCSR_AICSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
2715 #define ASRC_ASRCSR_AICSC_MASK                   (0xF00U)
2716 #define ASRC_ASRCSR_AICSC_SHIFT                  (8U)
2717 /*! AICSC - AICSC
2718  *  0b0000..bit clock 0
2719  *  0b0001..bit clock 1
2720  *  0b0010..bit clock 2
2721  *  0b0011..bit clock 3
2722  *  0b0100..bit clock 4
2723  *  0b0101..bit clock 5
2724  *  0b0110..bit clock 6
2725  *  0b0111..bit clock 7
2726  *  0b1000..bit clock 8
2727  *  0b1001..bit clock 9
2728  *  0b1010..bit clock A
2729  *  0b1011..bit clock B
2730  *  0b1100..bit clock C
2731  *  0b1101..bit clock D
2732  *  0b1110..bit clock E
2733  *  0b1111..clock disabled, connected to zero
2734  */
2735 #define ASRC_ASRCSR_AICSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
2736 #define ASRC_ASRCSR_AOCSA_MASK                   (0xF000U)
2737 #define ASRC_ASRCSR_AOCSA_SHIFT                  (12U)
2738 /*! AOCSA - AOCSA
2739  *  0b0000..bit clock 0
2740  *  0b0001..bit clock 1
2741  *  0b0010..bit clock 2
2742  *  0b0011..bit clock 3
2743  *  0b0100..bit clock 4
2744  *  0b0101..bit clock 5
2745  *  0b0110..bit clock 6
2746  *  0b0111..bit clock 7
2747  *  0b1000..bit clock 8
2748  *  0b1001..bit clock 9
2749  *  0b1010..bit clock A
2750  *  0b1011..bit clock B
2751  *  0b1100..bit clock C
2752  *  0b1101..bit clock D
2753  *  0b1110..bit clock E
2754  *  0b1111..clock disabled, connected to zero
2755  */
2756 #define ASRC_ASRCSR_AOCSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
2757 #define ASRC_ASRCSR_AOCSB_MASK                   (0xF0000U)
2758 #define ASRC_ASRCSR_AOCSB_SHIFT                  (16U)
2759 /*! AOCSB - AOCSB
2760  *  0b0000..bit clock 0
2761  *  0b0001..bit clock 1
2762  *  0b0010..bit clock 2
2763  *  0b0011..bit clock 3
2764  *  0b0100..bit clock 4
2765  *  0b0101..bit clock 5
2766  *  0b0110..bit clock 6
2767  *  0b0111..bit clock 7
2768  *  0b1000..bit clock 8
2769  *  0b1001..bit clock 9
2770  *  0b1010..bit clock A
2771  *  0b1011..bit clock B
2772  *  0b1100..bit clock C
2773  *  0b1101..bit clock D
2774  *  0b1110..bit clock E
2775  *  0b1111..clock disabled, connected to zero
2776  */
2777 #define ASRC_ASRCSR_AOCSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
2778 #define ASRC_ASRCSR_AOCSC_MASK                   (0xF00000U)
2779 #define ASRC_ASRCSR_AOCSC_SHIFT                  (20U)
2780 /*! AOCSC - AOCSC
2781  *  0b0000..bit clock 0
2782  *  0b0001..bit clock 1
2783  *  0b0010..bit clock 2
2784  *  0b0011..bit clock 3
2785  *  0b0100..bit clock 4
2786  *  0b0101..bit clock 5
2787  *  0b0110..bit clock 6
2788  *  0b0111..bit clock 7
2789  *  0b1000..bit clock 8
2790  *  0b1001..bit clock 9
2791  *  0b1010..bit clock A
2792  *  0b1011..bit clock B
2793  *  0b1100..bit clock C
2794  *  0b1101..bit clock D
2795  *  0b1110..bit clock E
2796  *  0b1111..clock disabled, connected to zero
2797  */
2798 #define ASRC_ASRCSR_AOCSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
2799 /*! @} */
2800 
2801 /*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
2802 /*! @{ */
2803 #define ASRC_ASRCDR1_AICPA_MASK                  (0x7U)
2804 #define ASRC_ASRCDR1_AICPA_SHIFT                 (0U)
2805 /*! AICPA - AICPA
2806  */
2807 #define ASRC_ASRCDR1_AICPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
2808 #define ASRC_ASRCDR1_AICDA_MASK                  (0x38U)
2809 #define ASRC_ASRCDR1_AICDA_SHIFT                 (3U)
2810 /*! AICDA - AICDA
2811  */
2812 #define ASRC_ASRCDR1_AICDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
2813 #define ASRC_ASRCDR1_AICPB_MASK                  (0x1C0U)
2814 #define ASRC_ASRCDR1_AICPB_SHIFT                 (6U)
2815 /*! AICPB - AICPB
2816  */
2817 #define ASRC_ASRCDR1_AICPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
2818 #define ASRC_ASRCDR1_AICDB_MASK                  (0xE00U)
2819 #define ASRC_ASRCDR1_AICDB_SHIFT                 (9U)
2820 /*! AICDB - AICDB
2821  */
2822 #define ASRC_ASRCDR1_AICDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
2823 #define ASRC_ASRCDR1_AOCPA_MASK                  (0x7000U)
2824 #define ASRC_ASRCDR1_AOCPA_SHIFT                 (12U)
2825 /*! AOCPA - AOCPA
2826  */
2827 #define ASRC_ASRCDR1_AOCPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
2828 #define ASRC_ASRCDR1_AOCDA_MASK                  (0x38000U)
2829 #define ASRC_ASRCDR1_AOCDA_SHIFT                 (15U)
2830 /*! AOCDA - AOCDA
2831  */
2832 #define ASRC_ASRCDR1_AOCDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
2833 #define ASRC_ASRCDR1_AOCPB_MASK                  (0x1C0000U)
2834 #define ASRC_ASRCDR1_AOCPB_SHIFT                 (18U)
2835 /*! AOCPB - AOCPB
2836  */
2837 #define ASRC_ASRCDR1_AOCPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
2838 #define ASRC_ASRCDR1_AOCDB_MASK                  (0xE00000U)
2839 #define ASRC_ASRCDR1_AOCDB_SHIFT                 (21U)
2840 /*! AOCDB - AOCDB
2841  */
2842 #define ASRC_ASRCDR1_AOCDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
2843 /*! @} */
2844 
2845 /*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
2846 /*! @{ */
2847 #define ASRC_ASRCDR2_AICPC_MASK                  (0x7U)
2848 #define ASRC_ASRCDR2_AICPC_SHIFT                 (0U)
2849 /*! AICPC - AICPC
2850  */
2851 #define ASRC_ASRCDR2_AICPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
2852 #define ASRC_ASRCDR2_AICDC_MASK                  (0x38U)
2853 #define ASRC_ASRCDR2_AICDC_SHIFT                 (3U)
2854 /*! AICDC - AICDC
2855  */
2856 #define ASRC_ASRCDR2_AICDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
2857 #define ASRC_ASRCDR2_AOCPC_MASK                  (0x1C0U)
2858 #define ASRC_ASRCDR2_AOCPC_SHIFT                 (6U)
2859 /*! AOCPC - AOCPC
2860  */
2861 #define ASRC_ASRCDR2_AOCPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
2862 #define ASRC_ASRCDR2_AOCDC_MASK                  (0xE00U)
2863 #define ASRC_ASRCDR2_AOCDC_SHIFT                 (9U)
2864 /*! AOCDC - AOCDC
2865  */
2866 #define ASRC_ASRCDR2_AOCDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
2867 /*! @} */
2868 
2869 /*! @name ASRSTR - ASRC Status Register */
2870 /*! @{ */
2871 #define ASRC_ASRSTR_AIDEA_MASK                   (0x1U)
2872 #define ASRC_ASRSTR_AIDEA_SHIFT                  (0U)
2873 /*! AIDEA - AIDEA
2874  */
2875 #define ASRC_ASRSTR_AIDEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
2876 #define ASRC_ASRSTR_AIDEB_MASK                   (0x2U)
2877 #define ASRC_ASRSTR_AIDEB_SHIFT                  (1U)
2878 /*! AIDEB - AIDEB
2879  */
2880 #define ASRC_ASRSTR_AIDEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
2881 #define ASRC_ASRSTR_AIDEC_MASK                   (0x4U)
2882 #define ASRC_ASRSTR_AIDEC_SHIFT                  (2U)
2883 /*! AIDEC - AIDEC
2884  */
2885 #define ASRC_ASRSTR_AIDEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
2886 #define ASRC_ASRSTR_AODFA_MASK                   (0x8U)
2887 #define ASRC_ASRSTR_AODFA_SHIFT                  (3U)
2888 /*! AODFA - AODFA
2889  */
2890 #define ASRC_ASRSTR_AODFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
2891 #define ASRC_ASRSTR_AODFB_MASK                   (0x10U)
2892 #define ASRC_ASRSTR_AODFB_SHIFT                  (4U)
2893 /*! AODFB - AODFB
2894  */
2895 #define ASRC_ASRSTR_AODFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
2896 #define ASRC_ASRSTR_AODFC_MASK                   (0x20U)
2897 #define ASRC_ASRSTR_AODFC_SHIFT                  (5U)
2898 /*! AODFC - AODFC
2899  */
2900 #define ASRC_ASRSTR_AODFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
2901 #define ASRC_ASRSTR_AOLE_MASK                    (0x40U)
2902 #define ASRC_ASRSTR_AOLE_SHIFT                   (6U)
2903 /*! AOLE - AOLE
2904  */
2905 #define ASRC_ASRSTR_AOLE(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
2906 #define ASRC_ASRSTR_FPWT_MASK                    (0x80U)
2907 #define ASRC_ASRSTR_FPWT_SHIFT                   (7U)
2908 /*! FPWT - FPWT
2909  */
2910 #define ASRC_ASRSTR_FPWT(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
2911 #define ASRC_ASRSTR_AIDUA_MASK                   (0x100U)
2912 #define ASRC_ASRSTR_AIDUA_SHIFT                  (8U)
2913 /*! AIDUA - AIDUA
2914  */
2915 #define ASRC_ASRSTR_AIDUA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
2916 #define ASRC_ASRSTR_AIDUB_MASK                   (0x200U)
2917 #define ASRC_ASRSTR_AIDUB_SHIFT                  (9U)
2918 /*! AIDUB - AIDUB
2919  */
2920 #define ASRC_ASRSTR_AIDUB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
2921 #define ASRC_ASRSTR_AIDUC_MASK                   (0x400U)
2922 #define ASRC_ASRSTR_AIDUC_SHIFT                  (10U)
2923 /*! AIDUC - AIDUC
2924  */
2925 #define ASRC_ASRSTR_AIDUC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
2926 #define ASRC_ASRSTR_AODOA_MASK                   (0x800U)
2927 #define ASRC_ASRSTR_AODOA_SHIFT                  (11U)
2928 /*! AODOA - AODOA
2929  */
2930 #define ASRC_ASRSTR_AODOA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
2931 #define ASRC_ASRSTR_AODOB_MASK                   (0x1000U)
2932 #define ASRC_ASRSTR_AODOB_SHIFT                  (12U)
2933 /*! AODOB - AODOB
2934  */
2935 #define ASRC_ASRSTR_AODOB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
2936 #define ASRC_ASRSTR_AODOC_MASK                   (0x2000U)
2937 #define ASRC_ASRSTR_AODOC_SHIFT                  (13U)
2938 /*! AODOC - AODOC
2939  */
2940 #define ASRC_ASRSTR_AODOC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
2941 #define ASRC_ASRSTR_AIOLA_MASK                   (0x4000U)
2942 #define ASRC_ASRSTR_AIOLA_SHIFT                  (14U)
2943 /*! AIOLA - AIOLA
2944  */
2945 #define ASRC_ASRSTR_AIOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
2946 #define ASRC_ASRSTR_AIOLB_MASK                   (0x8000U)
2947 #define ASRC_ASRSTR_AIOLB_SHIFT                  (15U)
2948 /*! AIOLB - AIOLB
2949  */
2950 #define ASRC_ASRSTR_AIOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
2951 #define ASRC_ASRSTR_AIOLC_MASK                   (0x10000U)
2952 #define ASRC_ASRSTR_AIOLC_SHIFT                  (16U)
2953 /*! AIOLC - AIOLC
2954  */
2955 #define ASRC_ASRSTR_AIOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
2956 #define ASRC_ASRSTR_AOOLA_MASK                   (0x20000U)
2957 #define ASRC_ASRSTR_AOOLA_SHIFT                  (17U)
2958 /*! AOOLA - AOOLA
2959  */
2960 #define ASRC_ASRSTR_AOOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
2961 #define ASRC_ASRSTR_AOOLB_MASK                   (0x40000U)
2962 #define ASRC_ASRSTR_AOOLB_SHIFT                  (18U)
2963 /*! AOOLB - AOOLB
2964  */
2965 #define ASRC_ASRSTR_AOOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
2966 #define ASRC_ASRSTR_AOOLC_MASK                   (0x80000U)
2967 #define ASRC_ASRSTR_AOOLC_SHIFT                  (19U)
2968 /*! AOOLC - AOOLC
2969  */
2970 #define ASRC_ASRSTR_AOOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
2971 #define ASRC_ASRSTR_ATQOL_MASK                   (0x100000U)
2972 #define ASRC_ASRSTR_ATQOL_SHIFT                  (20U)
2973 /*! ATQOL - ATQOL
2974  */
2975 #define ASRC_ASRSTR_ATQOL(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
2976 #define ASRC_ASRSTR_DSLCNT_MASK                  (0x200000U)
2977 #define ASRC_ASRSTR_DSLCNT_SHIFT                 (21U)
2978 /*! DSLCNT - DSLCNT
2979  */
2980 #define ASRC_ASRSTR_DSLCNT(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
2981 /*! @} */
2982 
2983 /*! @name ASRPM - ASRC Parameter Register n */
2984 /*! @{ */
2985 #define ASRC_ASRPM_PARAMETER_VALUE_MASK          (0xFFFFFFU)
2986 #define ASRC_ASRPM_PARAMETER_VALUE_SHIFT         (0U)
2987 /*! PARAMETER_VALUE - PARAMETER_VALUE
2988  */
2989 #define ASRC_ASRPM_PARAMETER_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
2990 /*! @} */
2991 
2992 /* The count of ASRC_ASRPM */
2993 #define ASRC_ASRPM_COUNT                         (5U)
2994 
2995 /*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */
2996 /*! @{ */
2997 #define ASRC_ASRTFR1_TF_BASE_MASK                (0x1FC0U)
2998 #define ASRC_ASRTFR1_TF_BASE_SHIFT               (6U)
2999 /*! TF_BASE - TF_BASE
3000  */
3001 #define ASRC_ASRTFR1_TF_BASE(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
3002 #define ASRC_ASRTFR1_TF_FILL_MASK                (0xFE000U)
3003 #define ASRC_ASRTFR1_TF_FILL_SHIFT               (13U)
3004 /*! TF_FILL - TF_FILL
3005  */
3006 #define ASRC_ASRTFR1_TF_FILL(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
3007 /*! @} */
3008 
3009 /*! @name ASRCCR - ASRC Channel Counter Register */
3010 /*! @{ */
3011 #define ASRC_ASRCCR_ACIA_MASK                    (0xFU)
3012 #define ASRC_ASRCCR_ACIA_SHIFT                   (0U)
3013 /*! ACIA - ACIA
3014  */
3015 #define ASRC_ASRCCR_ACIA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
3016 #define ASRC_ASRCCR_ACIB_MASK                    (0xF0U)
3017 #define ASRC_ASRCCR_ACIB_SHIFT                   (4U)
3018 /*! ACIB - ACIB
3019  */
3020 #define ASRC_ASRCCR_ACIB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
3021 #define ASRC_ASRCCR_ACIC_MASK                    (0xF00U)
3022 #define ASRC_ASRCCR_ACIC_SHIFT                   (8U)
3023 /*! ACIC - ACIC
3024  */
3025 #define ASRC_ASRCCR_ACIC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
3026 #define ASRC_ASRCCR_ACOA_MASK                    (0xF000U)
3027 #define ASRC_ASRCCR_ACOA_SHIFT                   (12U)
3028 /*! ACOA - ACOA
3029  */
3030 #define ASRC_ASRCCR_ACOA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
3031 #define ASRC_ASRCCR_ACOB_MASK                    (0xF0000U)
3032 #define ASRC_ASRCCR_ACOB_SHIFT                   (16U)
3033 /*! ACOB - ACOB
3034  */
3035 #define ASRC_ASRCCR_ACOB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
3036 #define ASRC_ASRCCR_ACOC_MASK                    (0xF00000U)
3037 #define ASRC_ASRCCR_ACOC_SHIFT                   (20U)
3038 /*! ACOC - ACOC
3039  */
3040 #define ASRC_ASRCCR_ACOC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
3041 /*! @} */
3042 
3043 /*! @name ASRDIA - ASRC Data Input Register for Pair x */
3044 /*! @{ */
3045 #define ASRC_ASRDIA_DATA_MASK                    (0xFFFFFFU)
3046 #define ASRC_ASRDIA_DATA_SHIFT                   (0U)
3047 /*! DATA - DATA
3048  */
3049 #define ASRC_ASRDIA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
3050 /*! @} */
3051 
3052 /*! @name ASRDOA - ASRC Data Output Register for Pair x */
3053 /*! @{ */
3054 #define ASRC_ASRDOA_DATA_MASK                    (0xFFFFFFU)
3055 #define ASRC_ASRDOA_DATA_SHIFT                   (0U)
3056 /*! DATA - DATA
3057  */
3058 #define ASRC_ASRDOA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
3059 /*! @} */
3060 
3061 /*! @name ASRDIB - ASRC Data Input Register for Pair x */
3062 /*! @{ */
3063 #define ASRC_ASRDIB_DATA_MASK                    (0xFFFFFFU)
3064 #define ASRC_ASRDIB_DATA_SHIFT                   (0U)
3065 /*! DATA - DATA
3066  */
3067 #define ASRC_ASRDIB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
3068 /*! @} */
3069 
3070 /*! @name ASRDOB - ASRC Data Output Register for Pair x */
3071 /*! @{ */
3072 #define ASRC_ASRDOB_DATA_MASK                    (0xFFFFFFU)
3073 #define ASRC_ASRDOB_DATA_SHIFT                   (0U)
3074 /*! DATA - DATA
3075  */
3076 #define ASRC_ASRDOB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
3077 /*! @} */
3078 
3079 /*! @name ASRDIC - ASRC Data Input Register for Pair x */
3080 /*! @{ */
3081 #define ASRC_ASRDIC_DATA_MASK                    (0xFFFFFFU)
3082 #define ASRC_ASRDIC_DATA_SHIFT                   (0U)
3083 /*! DATA - DATA
3084  */
3085 #define ASRC_ASRDIC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
3086 /*! @} */
3087 
3088 /*! @name ASRDOC - ASRC Data Output Register for Pair x */
3089 /*! @{ */
3090 #define ASRC_ASRDOC_DATA_MASK                    (0xFFFFFFU)
3091 #define ASRC_ASRDOC_DATA_SHIFT                   (0U)
3092 /*! DATA - DATA
3093  */
3094 #define ASRC_ASRDOC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
3095 /*! @} */
3096 
3097 /*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
3098 /*! @{ */
3099 #define ASRC_ASRIDRHA_IDRATIOA_H_MASK            (0xFFU)
3100 #define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT           (0U)
3101 /*! IDRATIOA_H - IDRATIOA_H
3102  */
3103 #define ASRC_ASRIDRHA_IDRATIOA_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
3104 /*! @} */
3105 
3106 /*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
3107 /*! @{ */
3108 #define ASRC_ASRIDRLA_IDRATIOA_L_MASK            (0xFFFFFFU)
3109 #define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT           (0U)
3110 /*! IDRATIOA_L - IDRATIOA_L
3111  */
3112 #define ASRC_ASRIDRLA_IDRATIOA_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
3113 /*! @} */
3114 
3115 /*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
3116 /*! @{ */
3117 #define ASRC_ASRIDRHB_IDRATIOB_H_MASK            (0xFFU)
3118 #define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT           (0U)
3119 /*! IDRATIOB_H - IDRATIOB_H
3120  */
3121 #define ASRC_ASRIDRHB_IDRATIOB_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
3122 /*! @} */
3123 
3124 /*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
3125 /*! @{ */
3126 #define ASRC_ASRIDRLB_IDRATIOB_L_MASK            (0xFFFFFFU)
3127 #define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT           (0U)
3128 /*! IDRATIOB_L - IDRATIOB_L
3129  */
3130 #define ASRC_ASRIDRLB_IDRATIOB_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
3131 /*! @} */
3132 
3133 /*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
3134 /*! @{ */
3135 #define ASRC_ASRIDRHC_IDRATIOC_H_MASK            (0xFFU)
3136 #define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT           (0U)
3137 /*! IDRATIOC_H - IDRATIOC_H
3138  */
3139 #define ASRC_ASRIDRHC_IDRATIOC_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
3140 /*! @} */
3141 
3142 /*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
3143 /*! @{ */
3144 #define ASRC_ASRIDRLC_IDRATIOC_L_MASK            (0xFFFFFFU)
3145 #define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT           (0U)
3146 /*! IDRATIOC_L - IDRATIOC_L
3147  */
3148 #define ASRC_ASRIDRLC_IDRATIOC_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
3149 /*! @} */
3150 
3151 /*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
3152 /*! @{ */
3153 #define ASRC_ASR76K_ASR76K_MASK                  (0x1FFFFU)
3154 #define ASRC_ASR76K_ASR76K_SHIFT                 (0U)
3155 /*! ASR76K - ASR76K
3156  */
3157 #define ASRC_ASR76K_ASR76K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
3158 /*! @} */
3159 
3160 /*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
3161 /*! @{ */
3162 #define ASRC_ASR56K_ASR56K_MASK                  (0x1FFFFU)
3163 #define ASRC_ASR56K_ASR56K_SHIFT                 (0U)
3164 /*! ASR56K - ASR56K
3165  */
3166 #define ASRC_ASR56K_ASR56K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
3167 /*! @} */
3168 
3169 /*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
3170 /*! @{ */
3171 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK      (0x3FU)
3172 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT     (0U)
3173 /*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
3174  */
3175 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
3176 #define ASRC_ASRMCRA_RSYNOFA_MASK                (0x400U)
3177 #define ASRC_ASRMCRA_RSYNOFA_SHIFT               (10U)
3178 /*! RSYNOFA - RSYNOFA
3179  */
3180 #define ASRC_ASRMCRA_RSYNOFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
3181 #define ASRC_ASRMCRA_RSYNIFA_MASK                (0x800U)
3182 #define ASRC_ASRMCRA_RSYNIFA_SHIFT               (11U)
3183 /*! RSYNIFA - RSYNIFA
3184  */
3185 #define ASRC_ASRMCRA_RSYNIFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
3186 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK     (0x3F000U)
3187 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT    (12U)
3188 /*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
3189  */
3190 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
3191 #define ASRC_ASRMCRA_BYPASSPOLYA_MASK            (0x100000U)
3192 #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT           (20U)
3193 /*! BYPASSPOLYA - BYPASSPOLYA
3194  *  0b1..Bypass polyphase filtering.
3195  *  0b0..Don't bypass polyphase filtering.
3196  */
3197 #define ASRC_ASRMCRA_BYPASSPOLYA(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
3198 #define ASRC_ASRMCRA_BUFSTALLA_MASK              (0x200000U)
3199 #define ASRC_ASRMCRA_BUFSTALLA_SHIFT             (21U)
3200 /*! BUFSTALLA - BUFSTALLA
3201  *  0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
3202  *  0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
3203  */
3204 #define ASRC_ASRMCRA_BUFSTALLA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
3205 #define ASRC_ASRMCRA_EXTTHRSHA_MASK              (0x400000U)
3206 #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT             (22U)
3207 /*! EXTTHRSHA - EXTTHRSHA
3208  *  0b1..Use external defined thresholds.
3209  *  0b0..Use default thresholds.
3210  */
3211 #define ASRC_ASRMCRA_EXTTHRSHA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
3212 #define ASRC_ASRMCRA_ZEROBUFA_MASK               (0x800000U)
3213 #define ASRC_ASRMCRA_ZEROBUFA_SHIFT              (23U)
3214 /*! ZEROBUFA - ZEROBUFA
3215  *  0b1..Don't zeroize the buffer
3216  *  0b0..Zeroize the buffer
3217  */
3218 #define ASRC_ASRMCRA_ZEROBUFA(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
3219 /*! @} */
3220 
3221 /*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
3222 /*! @{ */
3223 #define ASRC_ASRFSTA_INFIFO_FILLA_MASK           (0x7FU)
3224 #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT          (0U)
3225 /*! INFIFO_FILLA - INFIFO_FILLA
3226  */
3227 #define ASRC_ASRFSTA_INFIFO_FILLA(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
3228 #define ASRC_ASRFSTA_IAEA_MASK                   (0x800U)
3229 #define ASRC_ASRFSTA_IAEA_SHIFT                  (11U)
3230 /*! IAEA - IAEA
3231  */
3232 #define ASRC_ASRFSTA_IAEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
3233 #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK          (0x7F000U)
3234 #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT         (12U)
3235 /*! OUTFIFO_FILLA - OUTFIFO_FILLA
3236  */
3237 #define ASRC_ASRFSTA_OUTFIFO_FILLA(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
3238 #define ASRC_ASRFSTA_OAFA_MASK                   (0x800000U)
3239 #define ASRC_ASRFSTA_OAFA_SHIFT                  (23U)
3240 /*! OAFA - OAFA
3241  */
3242 #define ASRC_ASRFSTA_OAFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
3243 /*! @} */
3244 
3245 /*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
3246 /*! @{ */
3247 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK      (0x3FU)
3248 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT     (0U)
3249 /*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
3250  */
3251 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
3252 #define ASRC_ASRMCRB_RSYNOFB_MASK                (0x400U)
3253 #define ASRC_ASRMCRB_RSYNOFB_SHIFT               (10U)
3254 /*! RSYNOFB - RSYNOFB
3255  */
3256 #define ASRC_ASRMCRB_RSYNOFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
3257 #define ASRC_ASRMCRB_RSYNIFB_MASK                (0x800U)
3258 #define ASRC_ASRMCRB_RSYNIFB_SHIFT               (11U)
3259 /*! RSYNIFB - RSYNIFB
3260  */
3261 #define ASRC_ASRMCRB_RSYNIFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
3262 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK     (0x3F000U)
3263 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT    (12U)
3264 /*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
3265  */
3266 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
3267 #define ASRC_ASRMCRB_BYPASSPOLYB_MASK            (0x100000U)
3268 #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT           (20U)
3269 /*! BYPASSPOLYB - BYPASSPOLYB
3270  *  0b1..Bypass polyphase filtering.
3271  *  0b0..Don't bypass polyphase filtering.
3272  */
3273 #define ASRC_ASRMCRB_BYPASSPOLYB(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
3274 #define ASRC_ASRMCRB_BUFSTALLB_MASK              (0x200000U)
3275 #define ASRC_ASRMCRB_BUFSTALLB_SHIFT             (21U)
3276 /*! BUFSTALLB - BUFSTALLB
3277  *  0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
3278  *  0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
3279  */
3280 #define ASRC_ASRMCRB_BUFSTALLB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
3281 #define ASRC_ASRMCRB_EXTTHRSHB_MASK              (0x400000U)
3282 #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT             (22U)
3283 /*! EXTTHRSHB - EXTTHRSHB
3284  *  0b1..Use external defined thresholds.
3285  *  0b0..Use default thresholds.
3286  */
3287 #define ASRC_ASRMCRB_EXTTHRSHB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
3288 #define ASRC_ASRMCRB_ZEROBUFB_MASK               (0x800000U)
3289 #define ASRC_ASRMCRB_ZEROBUFB_SHIFT              (23U)
3290 /*! ZEROBUFB - ZEROBUFB
3291  *  0b1..Don't zeroize the buffer
3292  *  0b0..Zeroize the buffer
3293  */
3294 #define ASRC_ASRMCRB_ZEROBUFB(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
3295 /*! @} */
3296 
3297 /*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
3298 /*! @{ */
3299 #define ASRC_ASRFSTB_INFIFO_FILLB_MASK           (0x7FU)
3300 #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT          (0U)
3301 /*! INFIFO_FILLB - INFIFO_FILLB
3302  */
3303 #define ASRC_ASRFSTB_INFIFO_FILLB(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
3304 #define ASRC_ASRFSTB_IAEB_MASK                   (0x800U)
3305 #define ASRC_ASRFSTB_IAEB_SHIFT                  (11U)
3306 /*! IAEB - IAEB
3307  */
3308 #define ASRC_ASRFSTB_IAEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
3309 #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK          (0x7F000U)
3310 #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT         (12U)
3311 /*! OUTFIFO_FILLB - OUTFIFO_FILLB
3312  */
3313 #define ASRC_ASRFSTB_OUTFIFO_FILLB(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
3314 #define ASRC_ASRFSTB_OAFB_MASK                   (0x800000U)
3315 #define ASRC_ASRFSTB_OAFB_SHIFT                  (23U)
3316 /*! OAFB - OAFB
3317  */
3318 #define ASRC_ASRFSTB_OAFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
3319 /*! @} */
3320 
3321 /*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
3322 /*! @{ */
3323 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK      (0x3FU)
3324 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT     (0U)
3325 /*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
3326  */
3327 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
3328 #define ASRC_ASRMCRC_RSYNOFC_MASK                (0x400U)
3329 #define ASRC_ASRMCRC_RSYNOFC_SHIFT               (10U)
3330 /*! RSYNOFC - RSYNOFC
3331  */
3332 #define ASRC_ASRMCRC_RSYNOFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
3333 #define ASRC_ASRMCRC_RSYNIFC_MASK                (0x800U)
3334 #define ASRC_ASRMCRC_RSYNIFC_SHIFT               (11U)
3335 /*! RSYNIFC - RSYNIFC
3336  */
3337 #define ASRC_ASRMCRC_RSYNIFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
3338 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK     (0x3F000U)
3339 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT    (12U)
3340 /*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
3341  */
3342 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
3343 #define ASRC_ASRMCRC_BYPASSPOLYC_MASK            (0x100000U)
3344 #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT           (20U)
3345 /*! BYPASSPOLYC - BYPASSPOLYC
3346  *  0b1..Bypass polyphase filtering.
3347  *  0b0..Don't bypass polyphase filtering.
3348  */
3349 #define ASRC_ASRMCRC_BYPASSPOLYC(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
3350 #define ASRC_ASRMCRC_BUFSTALLC_MASK              (0x200000U)
3351 #define ASRC_ASRMCRC_BUFSTALLC_SHIFT             (21U)
3352 /*! BUFSTALLC - BUFSTALLC
3353  *  0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
3354  *  0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
3355  */
3356 #define ASRC_ASRMCRC_BUFSTALLC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
3357 #define ASRC_ASRMCRC_EXTTHRSHC_MASK              (0x400000U)
3358 #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT             (22U)
3359 /*! EXTTHRSHC - EXTTHRSHC
3360  *  0b1..Use external defined thresholds.
3361  *  0b0..Use default thresholds.
3362  */
3363 #define ASRC_ASRMCRC_EXTTHRSHC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
3364 #define ASRC_ASRMCRC_ZEROBUFC_MASK               (0x800000U)
3365 #define ASRC_ASRMCRC_ZEROBUFC_SHIFT              (23U)
3366 /*! ZEROBUFC - ZEROBUFC
3367  *  0b1..Don't zeroize the buffer
3368  *  0b0..Zeroize the buffer
3369  */
3370 #define ASRC_ASRMCRC_ZEROBUFC(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
3371 /*! @} */
3372 
3373 /*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
3374 /*! @{ */
3375 #define ASRC_ASRFSTC_INFIFO_FILLC_MASK           (0x7FU)
3376 #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT          (0U)
3377 /*! INFIFO_FILLC - INFIFO_FILLC
3378  */
3379 #define ASRC_ASRFSTC_INFIFO_FILLC(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
3380 #define ASRC_ASRFSTC_IAEC_MASK                   (0x800U)
3381 #define ASRC_ASRFSTC_IAEC_SHIFT                  (11U)
3382 /*! IAEC - IAEC
3383  */
3384 #define ASRC_ASRFSTC_IAEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
3385 #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK          (0x7F000U)
3386 #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT         (12U)
3387 /*! OUTFIFO_FILLC - OUTFIFO_FILLC
3388  */
3389 #define ASRC_ASRFSTC_OUTFIFO_FILLC(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
3390 #define ASRC_ASRFSTC_OAFC_MASK                   (0x800000U)
3391 #define ASRC_ASRFSTC_OAFC_SHIFT                  (23U)
3392 /*! OAFC - OAFC
3393  */
3394 #define ASRC_ASRFSTC_OAFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
3395 /*! @} */
3396 
3397 /*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
3398 /*! @{ */
3399 #define ASRC_ASRMCR1_OW16_MASK                   (0x1U)
3400 #define ASRC_ASRMCR1_OW16_SHIFT                  (0U)
3401 /*! OW16 - OW16
3402  *  0b1..16-bit output data
3403  *  0b0..24-bit output data.
3404  */
3405 #define ASRC_ASRMCR1_OW16(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
3406 #define ASRC_ASRMCR1_OSGN_MASK                   (0x2U)
3407 #define ASRC_ASRMCR1_OSGN_SHIFT                  (1U)
3408 /*! OSGN - OSGN
3409  *  0b1..Sign extension.
3410  *  0b0..No sign extension.
3411  */
3412 #define ASRC_ASRMCR1_OSGN(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
3413 #define ASRC_ASRMCR1_OMSB_MASK                   (0x4U)
3414 #define ASRC_ASRMCR1_OMSB_SHIFT                  (2U)
3415 /*! OMSB - OMSB
3416  *  0b1..MSB aligned.
3417  *  0b0..LSB aligned.
3418  */
3419 #define ASRC_ASRMCR1_OMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
3420 #define ASRC_ASRMCR1_IMSB_MASK                   (0x100U)
3421 #define ASRC_ASRMCR1_IMSB_SHIFT                  (8U)
3422 /*! IMSB - IMSB
3423  *  0b1..MSB aligned.
3424  *  0b0..LSB aligned.
3425  */
3426 #define ASRC_ASRMCR1_IMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
3427 #define ASRC_ASRMCR1_IWD_MASK                    (0xE00U)
3428 #define ASRC_ASRMCR1_IWD_SHIFT                   (9U)
3429 /*! IWD - IWD
3430  */
3431 #define ASRC_ASRMCR1_IWD(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
3432 /*! @} */
3433 
3434 /* The count of ASRC_ASRMCR1 */
3435 #define ASRC_ASRMCR1_COUNT                       (3U)
3436 
3437 
3438 /*!
3439  * @}
3440  */ /* end of group ASRC_Register_Masks */
3441 
3442 
3443 /* ASRC - Peripheral instance base addresses */
3444 /** Peripheral ADMA__ASRC0 base address */
3445 #define ADMA__ASRC0_BASE                         (0x59000000u)
3446 /** Peripheral ADMA__ASRC0 base pointer */
3447 #define ADMA__ASRC0                              ((ASRC_Type *)ADMA__ASRC0_BASE)
3448 /** Peripheral ADMA__ASRC1 base address */
3449 #define ADMA__ASRC1_BASE                         (0x59800000u)
3450 /** Peripheral ADMA__ASRC1 base pointer */
3451 #define ADMA__ASRC1                              ((ASRC_Type *)ADMA__ASRC1_BASE)
3452 /** Array initializer of ASRC peripheral base addresses */
3453 #define ASRC_BASE_ADDRS                          { ADMA__ASRC0_BASE, ADMA__ASRC1_BASE }
3454 /** Array initializer of ASRC peripheral base pointers */
3455 #define ASRC_BASE_PTRS                           { ADMA__ASRC0, ADMA__ASRC1 }
3456 
3457 /*!
3458  * @}
3459  */ /* end of group ASRC_Peripheral_Access_Layer */
3460 
3461 
3462 /* ----------------------------------------------------------------------------
3463    -- BCH Peripheral Access Layer
3464    ---------------------------------------------------------------------------- */
3465 
3466 /*!
3467  * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
3468  * @{
3469  */
3470 
3471 /** BCH - Register Layout Typedef */
3472 typedef struct {
3473   struct {                                         /* offset: 0x0 */
3474     __IO uint32_t RW;                                /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
3475     __IO uint32_t SET;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
3476     __IO uint32_t CLR;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
3477     __IO uint32_t TOG;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
3478   } CTRL;
3479   struct {                                         /* offset: 0x10 */
3480     __I  uint32_t RW;                                /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
3481     __I  uint32_t SET;                               /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
3482     __I  uint32_t CLR;                               /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
3483     __I  uint32_t TOG;                               /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
3484   } STATUS0;
3485   struct {                                         /* offset: 0x20 */
3486     __IO uint32_t RW;                                /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
3487     __IO uint32_t SET;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
3488     __IO uint32_t CLR;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
3489     __IO uint32_t TOG;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
3490   } MODE;
3491   struct {                                         /* offset: 0x30 */
3492     __IO uint32_t RW;                                /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
3493     __IO uint32_t SET;                               /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
3494     __IO uint32_t CLR;                               /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
3495     __IO uint32_t TOG;                               /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
3496   } ENCODEPTR;
3497   struct {                                         /* offset: 0x40 */
3498     __IO uint32_t RW;                                /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
3499     __IO uint32_t SET;                               /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
3500     __IO uint32_t CLR;                               /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
3501     __IO uint32_t TOG;                               /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
3502   } DATAPTR;
3503   struct {                                         /* offset: 0x50 */
3504     __IO uint32_t RW;                                /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
3505     __IO uint32_t SET;                               /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
3506     __IO uint32_t CLR;                               /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
3507     __IO uint32_t TOG;                               /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
3508   } METAPTR;
3509        uint8_t RESERVED_0[16];
3510   struct {                                         /* offset: 0x70 */
3511     __IO uint32_t RW;                                /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
3512     __IO uint32_t SET;                               /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
3513     __IO uint32_t CLR;                               /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
3514     __IO uint32_t TOG;                               /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
3515   } LAYOUTSELECT;
3516   struct {                                         /* offset: 0x80 */
3517     __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
3518     __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
3519     __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
3520     __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
3521   } FLASH0LAYOUT0;
3522   struct {                                         /* offset: 0x90 */
3523     __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
3524     __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
3525     __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
3526     __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
3527   } FLASH0LAYOUT1;
3528   struct {                                         /* offset: 0xA0 */
3529     __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
3530     __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
3531     __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
3532     __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
3533   } FLASH1LAYOUT0;
3534   struct {                                         /* offset: 0xB0 */
3535     __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
3536     __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
3537     __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
3538     __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
3539   } FLASH1LAYOUT1;
3540   struct {                                         /* offset: 0xC0 */
3541     __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
3542     __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
3543     __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
3544     __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
3545   } FLASH2LAYOUT0;
3546   struct {                                         /* offset: 0xD0 */
3547     __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
3548     __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
3549     __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
3550     __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
3551   } FLASH2LAYOUT1;
3552   struct {                                         /* offset: 0xE0 */
3553     __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
3554     __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
3555     __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
3556     __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
3557   } FLASH3LAYOUT0;
3558   struct {                                         /* offset: 0xF0 */
3559     __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
3560     __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
3561     __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
3562     __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
3563   } FLASH3LAYOUT1;
3564   struct {                                         /* offset: 0x100 */
3565     __IO uint32_t RW;                                /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
3566     __IO uint32_t SET;                               /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
3567     __IO uint32_t CLR;                               /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
3568     __IO uint32_t TOG;                               /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
3569   } DEBUG0;
3570   struct {                                         /* offset: 0x110 */
3571     __I  uint32_t RW;                                /**< KES Debug Read Register, offset: 0x110 */
3572     __I  uint32_t SET;                               /**< KES Debug Read Register, offset: 0x114 */
3573     __I  uint32_t CLR;                               /**< KES Debug Read Register, offset: 0x118 */
3574     __I  uint32_t TOG;                               /**< KES Debug Read Register, offset: 0x11C */
3575   } DBGKESREAD;
3576   struct {                                         /* offset: 0x120 */
3577     __I  uint32_t RW;                                /**< Chien Search Debug Read Register, offset: 0x120 */
3578     __I  uint32_t SET;                               /**< Chien Search Debug Read Register, offset: 0x124 */
3579     __I  uint32_t CLR;                               /**< Chien Search Debug Read Register, offset: 0x128 */
3580     __I  uint32_t TOG;                               /**< Chien Search Debug Read Register, offset: 0x12C */
3581   } DBGCSFEREAD;
3582   struct {                                         /* offset: 0x130 */
3583     __I  uint32_t RW;                                /**< Syndrome Generator Debug Read Register, offset: 0x130 */
3584     __I  uint32_t SET;                               /**< Syndrome Generator Debug Read Register, offset: 0x134 */
3585     __I  uint32_t CLR;                               /**< Syndrome Generator Debug Read Register, offset: 0x138 */
3586     __I  uint32_t TOG;                               /**< Syndrome Generator Debug Read Register, offset: 0x13C */
3587   } DBGSYNDGENREAD;
3588   struct {                                         /* offset: 0x140 */
3589     __I  uint32_t RW;                                /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
3590     __I  uint32_t SET;                               /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
3591     __I  uint32_t CLR;                               /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
3592     __I  uint32_t TOG;                               /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
3593   } DBGAHBMREAD;
3594   struct {                                         /* offset: 0x150 */
3595     __I  uint32_t RW;                                /**< Block Name Register, offset: 0x150 */
3596     __I  uint32_t SET;                               /**< Block Name Register, offset: 0x154 */
3597     __I  uint32_t CLR;                               /**< Block Name Register, offset: 0x158 */
3598     __I  uint32_t TOG;                               /**< Block Name Register, offset: 0x15C */
3599   } BLOCKNAME;
3600   struct {                                         /* offset: 0x160 */
3601     __I  uint32_t RW;                                /**< BCH Version Register, offset: 0x160 */
3602     __I  uint32_t SET;                               /**< BCH Version Register, offset: 0x164 */
3603     __I  uint32_t CLR;                               /**< BCH Version Register, offset: 0x168 */
3604     __I  uint32_t TOG;                               /**< BCH Version Register, offset: 0x16C */
3605   } VERSION;
3606   struct {                                         /* offset: 0x170 */
3607     __IO uint32_t RW;                                /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
3608     __IO uint32_t SET;                               /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */
3609     __IO uint32_t CLR;                               /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */
3610     __IO uint32_t TOG;                               /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */
3611   } DEBUG1;
3612 } BCH_Type;
3613 
3614 /* ----------------------------------------------------------------------------
3615    -- BCH Register Masks
3616    ---------------------------------------------------------------------------- */
3617 
3618 /*!
3619  * @addtogroup BCH_Register_Masks BCH Register Masks
3620  * @{
3621  */
3622 
3623 /*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
3624 /*! @{ */
3625 #define BCH_CTRL_COMPLETE_IRQ_MASK               (0x1U)
3626 #define BCH_CTRL_COMPLETE_IRQ_SHIFT              (0U)
3627 /*! COMPLETE_IRQ - COMPLETE_IRQ
3628  */
3629 #define BCH_CTRL_COMPLETE_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
3630 #define BCH_CTRL_RSVD0_MASK                      (0x2U)
3631 #define BCH_CTRL_RSVD0_SHIFT                     (1U)
3632 /*! RSVD0 - This field is reserved.
3633  */
3634 #define BCH_CTRL_RSVD0(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
3635 #define BCH_CTRL_DEBUG_STALL_IRQ_MASK            (0x4U)
3636 #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT           (2U)
3637 /*! DEBUG_STALL_IRQ - DEBUG_STALL_IRQ
3638  */
3639 #define BCH_CTRL_DEBUG_STALL_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
3640 #define BCH_CTRL_BM_ERROR_IRQ_MASK               (0x8U)
3641 #define BCH_CTRL_BM_ERROR_IRQ_SHIFT              (3U)
3642 /*! BM_ERROR_IRQ - BM_ERROR_IRQ
3643  */
3644 #define BCH_CTRL_BM_ERROR_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
3645 #define BCH_CTRL_RSVD1_MASK                      (0xF0U)
3646 #define BCH_CTRL_RSVD1_SHIFT                     (4U)
3647 /*! RSVD1 - This field is reserved.
3648  */
3649 #define BCH_CTRL_RSVD1(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
3650 #define BCH_CTRL_COMPLETE_IRQ_EN_MASK            (0x100U)
3651 #define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT           (8U)
3652 /*! COMPLETE_IRQ_EN - COMPLETE_IRQ_EN
3653  */
3654 #define BCH_CTRL_COMPLETE_IRQ_EN(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
3655 #define BCH_CTRL_RSVD2_MASK                      (0x200U)
3656 #define BCH_CTRL_RSVD2_SHIFT                     (9U)
3657 /*! RSVD2 - This field is reserved.
3658  */
3659 #define BCH_CTRL_RSVD2(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
3660 #define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK         (0x400U)
3661 #define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT        (10U)
3662 /*! DEBUG_STALL_IRQ_EN - DEBUG_STALL_IRQ_EN
3663  */
3664 #define BCH_CTRL_DEBUG_STALL_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
3665 #define BCH_CTRL_RSVD3_MASK                      (0xF800U)
3666 #define BCH_CTRL_RSVD3_SHIFT                     (11U)
3667 /*! RSVD3 - This field is reserved.
3668  */
3669 #define BCH_CTRL_RSVD3(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
3670 #define BCH_CTRL_M2M_ENABLE_MASK                 (0x10000U)
3671 #define BCH_CTRL_M2M_ENABLE_SHIFT                (16U)
3672 /*! M2M_ENABLE - M2M_ENABLE
3673  */
3674 #define BCH_CTRL_M2M_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
3675 #define BCH_CTRL_M2M_ENCODE_MASK                 (0x20000U)
3676 #define BCH_CTRL_M2M_ENCODE_SHIFT                (17U)
3677 /*! M2M_ENCODE - M2M_ENCODE
3678  */
3679 #define BCH_CTRL_M2M_ENCODE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
3680 #define BCH_CTRL_M2M_LAYOUT_MASK                 (0xC0000U)
3681 #define BCH_CTRL_M2M_LAYOUT_SHIFT                (18U)
3682 /*! M2M_LAYOUT - M2M_LAYOUT
3683  */
3684 #define BCH_CTRL_M2M_LAYOUT(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
3685 #define BCH_CTRL_RSVD4_MASK                      (0x300000U)
3686 #define BCH_CTRL_RSVD4_SHIFT                     (20U)
3687 /*! RSVD4 - This field is reserved.
3688  */
3689 #define BCH_CTRL_RSVD4(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
3690 #define BCH_CTRL_DEBUGSYNDROME_MASK              (0x400000U)
3691 #define BCH_CTRL_DEBUGSYNDROME_SHIFT             (22U)
3692 /*! DEBUGSYNDROME - DEBUGSYNDROME
3693  */
3694 #define BCH_CTRL_DEBUGSYNDROME(x)                (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
3695 #define BCH_CTRL_RSVD5_MASK                      (0x3F800000U)
3696 #define BCH_CTRL_RSVD5_SHIFT                     (23U)
3697 /*! RSVD5 - This field is reserved.
3698  */
3699 #define BCH_CTRL_RSVD5(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
3700 #define BCH_CTRL_CLKGATE_MASK                    (0x40000000U)
3701 #define BCH_CTRL_CLKGATE_SHIFT                   (30U)
3702 /*! CLKGATE - CLKGATE
3703  *  0b0..Allow BCH to operate normally.
3704  *  0b1..Do not clock BCH gates in order to minimize power consumption.
3705  */
3706 #define BCH_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
3707 #define BCH_CTRL_SFTRST_MASK                     (0x80000000U)
3708 #define BCH_CTRL_SFTRST_SHIFT                    (31U)
3709 /*! SFTRST - SFTRST
3710  *  0b0..Allow BCH to operate normally.
3711  *  0b1..Hold BCH in reset.
3712  */
3713 #define BCH_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
3714 /*! @} */
3715 
3716 /*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
3717 /*! @{ */
3718 #define BCH_STATUS0_RSVD0_MASK                   (0x3U)
3719 #define BCH_STATUS0_RSVD0_SHIFT                  (0U)
3720 /*! RSVD0 - This field is reserved.
3721  */
3722 #define BCH_STATUS0_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
3723 #define BCH_STATUS0_UNCORRECTABLE_MASK           (0x4U)
3724 #define BCH_STATUS0_UNCORRECTABLE_SHIFT          (2U)
3725 /*! UNCORRECTABLE - UNCORRECTABLE
3726  */
3727 #define BCH_STATUS0_UNCORRECTABLE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
3728 #define BCH_STATUS0_CORRECTED_MASK               (0x8U)
3729 #define BCH_STATUS0_CORRECTED_SHIFT              (3U)
3730 /*! CORRECTED - CORRECTED
3731  */
3732 #define BCH_STATUS0_CORRECTED(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
3733 #define BCH_STATUS0_ALLONES_MASK                 (0x10U)
3734 #define BCH_STATUS0_ALLONES_SHIFT                (4U)
3735 /*! ALLONES - ALLONES
3736  */
3737 #define BCH_STATUS0_ALLONES(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
3738 #define BCH_STATUS0_RSVD1_MASK                   (0xE0U)
3739 #define BCH_STATUS0_RSVD1_SHIFT                  (5U)
3740 /*! RSVD1 - This field is reserved.
3741  */
3742 #define BCH_STATUS0_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
3743 #define BCH_STATUS0_STATUS_BLK0_MASK             (0xFF00U)
3744 #define BCH_STATUS0_STATUS_BLK0_SHIFT            (8U)
3745 /*! STATUS_BLK0 - STATUS_BLK0
3746  *  0b00000000..No errors found on block.
3747  *  0b00000001..One error found on block.
3748  *  0b00000010..One errors found on block.
3749  *  0b00000011..One errors found on block.
3750  *  0b00000100..One errors found on block.
3751  *  0b11111110..Block exhibited uncorrectable errors.
3752  *  0b11111111..Page is erased.
3753  */
3754 #define BCH_STATUS0_STATUS_BLK0(x)               (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
3755 #define BCH_STATUS0_COMPLETED_CE_MASK            (0xF0000U)
3756 #define BCH_STATUS0_COMPLETED_CE_SHIFT           (16U)
3757 /*! COMPLETED_CE - COMPLETED_CE
3758  */
3759 #define BCH_STATUS0_COMPLETED_CE(x)              (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
3760 #define BCH_STATUS0_HANDLE_MASK                  (0xFFF00000U)
3761 #define BCH_STATUS0_HANDLE_SHIFT                 (20U)
3762 /*! HANDLE - HANDLE
3763  */
3764 #define BCH_STATUS0_HANDLE(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
3765 /*! @} */
3766 
3767 /*! @name MODE - Hardware ECC Accelerator Mode Register */
3768 /*! @{ */
3769 #define BCH_MODE_ERASE_THRESHOLD_MASK            (0xFFU)
3770 #define BCH_MODE_ERASE_THRESHOLD_SHIFT           (0U)
3771 /*! ERASE_THRESHOLD - ERASE_THRESHOLD
3772  */
3773 #define BCH_MODE_ERASE_THRESHOLD(x)              (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
3774 #define BCH_MODE_RSVD_MASK                       (0xFFFFFF00U)
3775 #define BCH_MODE_RSVD_SHIFT                      (8U)
3776 /*! RSVD - This field is reserved.
3777  */
3778 #define BCH_MODE_RSVD(x)                         (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
3779 /*! @} */
3780 
3781 /*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
3782 /*! @{ */
3783 #define BCH_ENCODEPTR_ADDR_MASK                  (0xFFFFFFFFU)
3784 #define BCH_ENCODEPTR_ADDR_SHIFT                 (0U)
3785 /*! ADDR - ADDR
3786  */
3787 #define BCH_ENCODEPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
3788 /*! @} */
3789 
3790 /*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
3791 /*! @{ */
3792 #define BCH_DATAPTR_ADDR_MASK                    (0xFFFFFFFFU)
3793 #define BCH_DATAPTR_ADDR_SHIFT                   (0U)
3794 /*! ADDR - ADDR
3795  */
3796 #define BCH_DATAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
3797 /*! @} */
3798 
3799 /*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
3800 /*! @{ */
3801 #define BCH_METAPTR_ADDR_MASK                    (0xFFFFFFFFU)
3802 #define BCH_METAPTR_ADDR_SHIFT                   (0U)
3803 /*! ADDR - ADDR
3804  */
3805 #define BCH_METAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
3806 /*! @} */
3807 
3808 /*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
3809 /*! @{ */
3810 #define BCH_LAYOUTSELECT_CS0_SELECT_MASK         (0x3U)
3811 #define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT        (0U)
3812 /*! CS0_SELECT - CS0_SELECT
3813  */
3814 #define BCH_LAYOUTSELECT_CS0_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
3815 #define BCH_LAYOUTSELECT_CS1_SELECT_MASK         (0xCU)
3816 #define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT        (2U)
3817 /*! CS1_SELECT - CS1_SELECT
3818  */
3819 #define BCH_LAYOUTSELECT_CS1_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
3820 #define BCH_LAYOUTSELECT_CS2_SELECT_MASK         (0x30U)
3821 #define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT        (4U)
3822 /*! CS2_SELECT - CS2_SELECT
3823  */
3824 #define BCH_LAYOUTSELECT_CS2_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
3825 #define BCH_LAYOUTSELECT_CS3_SELECT_MASK         (0xC0U)
3826 #define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT        (6U)
3827 /*! CS3_SELECT - CS3_SELECT
3828  */
3829 #define BCH_LAYOUTSELECT_CS3_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
3830 #define BCH_LAYOUTSELECT_CS4_SELECT_MASK         (0x300U)
3831 #define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT        (8U)
3832 /*! CS4_SELECT - CS4_SELECT
3833  */
3834 #define BCH_LAYOUTSELECT_CS4_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
3835 #define BCH_LAYOUTSELECT_CS5_SELECT_MASK         (0xC00U)
3836 #define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT        (10U)
3837 /*! CS5_SELECT - CS5_SELECT
3838  */
3839 #define BCH_LAYOUTSELECT_CS5_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
3840 #define BCH_LAYOUTSELECT_CS6_SELECT_MASK         (0x3000U)
3841 #define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT        (12U)
3842 /*! CS6_SELECT - CS6_SELECT
3843  */
3844 #define BCH_LAYOUTSELECT_CS6_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
3845 #define BCH_LAYOUTSELECT_CS7_SELECT_MASK         (0xC000U)
3846 #define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT        (14U)
3847 /*! CS7_SELECT - CS7_SELECT
3848  */
3849 #define BCH_LAYOUTSELECT_CS7_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
3850 #define BCH_LAYOUTSELECT_CS8_SELECT_MASK         (0x30000U)
3851 #define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT        (16U)
3852 /*! CS8_SELECT - CS8_SELECT
3853  */
3854 #define BCH_LAYOUTSELECT_CS8_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
3855 #define BCH_LAYOUTSELECT_CS9_SELECT_MASK         (0xC0000U)
3856 #define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT        (18U)
3857 /*! CS9_SELECT - CS9_SELECT
3858  */
3859 #define BCH_LAYOUTSELECT_CS9_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
3860 #define BCH_LAYOUTSELECT_CS10_SELECT_MASK        (0x300000U)
3861 #define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT       (20U)
3862 /*! CS10_SELECT - CS10_SELECT
3863  */
3864 #define BCH_LAYOUTSELECT_CS10_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
3865 #define BCH_LAYOUTSELECT_CS11_SELECT_MASK        (0xC00000U)
3866 #define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT       (22U)
3867 /*! CS11_SELECT - CS11_SELECT
3868  */
3869 #define BCH_LAYOUTSELECT_CS11_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
3870 #define BCH_LAYOUTSELECT_CS12_SELECT_MASK        (0x3000000U)
3871 #define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT       (24U)
3872 /*! CS12_SELECT - CS12_SELECT
3873  */
3874 #define BCH_LAYOUTSELECT_CS12_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
3875 #define BCH_LAYOUTSELECT_CS13_SELECT_MASK        (0xC000000U)
3876 #define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT       (26U)
3877 /*! CS13_SELECT - CS13_SELECT
3878  */
3879 #define BCH_LAYOUTSELECT_CS13_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
3880 #define BCH_LAYOUTSELECT_CS14_SELECT_MASK        (0x30000000U)
3881 #define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT       (28U)
3882 /*! CS14_SELECT - CS14_SELECT
3883  */
3884 #define BCH_LAYOUTSELECT_CS14_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
3885 #define BCH_LAYOUTSELECT_CS15_SELECT_MASK        (0xC0000000U)
3886 #define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT       (30U)
3887 /*! CS15_SELECT - CS15_SELECT
3888  */
3889 #define BCH_LAYOUTSELECT_CS15_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
3890 /*! @} */
3891 
3892 /*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
3893 /*! @{ */
3894 #define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
3895 #define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT       (0U)
3896 /*! DATA0_SIZE - DATA0_SIZE
3897  */
3898 #define BCH_FLASH0LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
3899 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
3900 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
3901 /*! GF13_0_GF14_1 - GF13_0_GF14_1
3902  */
3903 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
3904 #define BCH_FLASH0LAYOUT0_ECC0_MASK              (0xF800U)
3905 #define BCH_FLASH0LAYOUT0_ECC0_SHIFT             (11U)
3906 /*! ECC0 - ECC0
3907  *  0b00000..No ECC to be performed
3908  *  0b00001..ECC 2 to be performed
3909  *  0b00010..ECC 4 to be performed
3910  *  0b11110..ECC 60 to be performed
3911  *  0b11111..ECC 62 to be performed
3912  */
3913 #define BCH_FLASH0LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
3914 #define BCH_FLASH0LAYOUT0_META_SIZE_MASK         (0xFF0000U)
3915 #define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT        (16U)
3916 /*! META_SIZE - META_SIZE
3917  */
3918 #define BCH_FLASH0LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
3919 #define BCH_FLASH0LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
3920 #define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT          (24U)
3921 /*! NBLOCKS - NBLOCKS
3922  */
3923 #define BCH_FLASH0LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
3924 /*! @} */
3925 
3926 /*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
3927 /*! @{ */
3928 #define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
3929 #define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT       (0U)
3930 /*! DATAN_SIZE - DATAN_SIZE
3931  */
3932 #define BCH_FLASH0LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
3933 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
3934 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
3935 /*! GF13_0_GF14_1 - GF13_0_GF14_1
3936  */
3937 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
3938 #define BCH_FLASH0LAYOUT1_ECCN_MASK              (0xF800U)
3939 #define BCH_FLASH0LAYOUT1_ECCN_SHIFT             (11U)
3940 /*! ECCN - ECCN
3941  *  0b00000..No ECC to be performed
3942  *  0b00001..ECC 2 to be performed
3943  *  0b00010..ECC 4 to be performed
3944  *  0b11110..ECC 60 to be performed
3945  *  0b11111..ECC 62 to be performed
3946  */
3947 #define BCH_FLASH0LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
3948 #define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
3949 #define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT        (16U)
3950 /*! PAGE_SIZE - PAGE_SIZE
3951  */
3952 #define BCH_FLASH0LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
3953 /*! @} */
3954 
3955 /*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
3956 /*! @{ */
3957 #define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
3958 #define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT       (0U)
3959 /*! DATA0_SIZE - DATA0_SIZE
3960  */
3961 #define BCH_FLASH1LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
3962 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
3963 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
3964 /*! GF13_0_GF14_1 - GF13_0_GF14_1
3965  */
3966 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
3967 #define BCH_FLASH1LAYOUT0_ECC0_MASK              (0xF800U)
3968 #define BCH_FLASH1LAYOUT0_ECC0_SHIFT             (11U)
3969 /*! ECC0 - ECC0
3970  *  0b00000..No ECC to be performed
3971  *  0b00001..ECC 2 to be performed
3972  *  0b00010..ECC 4 to be performed
3973  *  0b11110..ECC 60 to be performed
3974  *  0b11111..ECC 62 to be performed
3975  */
3976 #define BCH_FLASH1LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
3977 #define BCH_FLASH1LAYOUT0_META_SIZE_MASK         (0xFF0000U)
3978 #define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT        (16U)
3979 /*! META_SIZE - META_SIZE
3980  */
3981 #define BCH_FLASH1LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
3982 #define BCH_FLASH1LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
3983 #define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT          (24U)
3984 /*! NBLOCKS - NBLOCKS
3985  */
3986 #define BCH_FLASH1LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
3987 /*! @} */
3988 
3989 /*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
3990 /*! @{ */
3991 #define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
3992 #define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT       (0U)
3993 /*! DATAN_SIZE - DATAN_SIZE
3994  */
3995 #define BCH_FLASH1LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
3996 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
3997 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
3998 /*! GF13_0_GF14_1 - GF13_0_GF14_1
3999  */
4000 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
4001 #define BCH_FLASH1LAYOUT1_ECCN_MASK              (0xF800U)
4002 #define BCH_FLASH1LAYOUT1_ECCN_SHIFT             (11U)
4003 /*! ECCN - ECCN
4004  *  0b00000..No ECC to be performed
4005  *  0b00001..ECC 2 to be performed
4006  *  0b00010..ECC 4 to be performed
4007  *  0b11110..ECC 60 to be performed
4008  *  0b11111..ECC 62 to be performed
4009  */
4010 #define BCH_FLASH1LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
4011 #define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
4012 #define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT        (16U)
4013 /*! PAGE_SIZE - PAGE_SIZE
4014  */
4015 #define BCH_FLASH1LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
4016 /*! @} */
4017 
4018 /*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
4019 /*! @{ */
4020 #define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
4021 #define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT       (0U)
4022 /*! DATA0_SIZE - DATA0_SIZE
4023  */
4024 #define BCH_FLASH2LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
4025 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
4026 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
4027 /*! GF13_0_GF14_1 - GF13_0_GF14_1
4028  */
4029 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
4030 #define BCH_FLASH2LAYOUT0_ECC0_MASK              (0xF800U)
4031 #define BCH_FLASH2LAYOUT0_ECC0_SHIFT             (11U)
4032 /*! ECC0 - ECC0
4033  *  0b00000..No ECC to be performed
4034  *  0b00001..ECC 2 to be performed
4035  *  0b00010..ECC 4 to be performed
4036  *  0b11110..ECC 60 to be performed
4037  *  0b11111..ECC 62 to be performed
4038  */
4039 #define BCH_FLASH2LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
4040 #define BCH_FLASH2LAYOUT0_META_SIZE_MASK         (0xFF0000U)
4041 #define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT        (16U)
4042 /*! META_SIZE - META_SIZE
4043  */
4044 #define BCH_FLASH2LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
4045 #define BCH_FLASH2LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
4046 #define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT          (24U)
4047 /*! NBLOCKS - NBLOCKS
4048  */
4049 #define BCH_FLASH2LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
4050 /*! @} */
4051 
4052 /*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
4053 /*! @{ */
4054 #define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
4055 #define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT       (0U)
4056 /*! DATAN_SIZE - DATAN_SIZE
4057  */
4058 #define BCH_FLASH2LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
4059 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
4060 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
4061 /*! GF13_0_GF14_1 - GF13_0_GF14_1
4062  */
4063 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
4064 #define BCH_FLASH2LAYOUT1_ECCN_MASK              (0xF800U)
4065 #define BCH_FLASH2LAYOUT1_ECCN_SHIFT             (11U)
4066 /*! ECCN - ECCN
4067  *  0b00000..No ECC to be performed
4068  *  0b00001..ECC 2 to be performed
4069  *  0b00010..ECC 4 to be performed
4070  *  0b11110..ECC 60 to be performed
4071  *  0b11111..ECC 62 to be performed
4072  */
4073 #define BCH_FLASH2LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
4074 #define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
4075 #define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT        (16U)
4076 /*! PAGE_SIZE - PAGE_SIZE
4077  */
4078 #define BCH_FLASH2LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
4079 /*! @} */
4080 
4081 /*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
4082 /*! @{ */
4083 #define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
4084 #define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT       (0U)
4085 /*! DATA0_SIZE - DATA0_SIZE
4086  */
4087 #define BCH_FLASH3LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
4088 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
4089 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
4090 /*! GF13_0_GF14_1 - GF13_0_GF14_1
4091  */
4092 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
4093 #define BCH_FLASH3LAYOUT0_ECC0_MASK              (0xF800U)
4094 #define BCH_FLASH3LAYOUT0_ECC0_SHIFT             (11U)
4095 /*! ECC0 - ECC0
4096  *  0b00000..No ECC to be performed
4097  *  0b00001..ECC 2 to be performed
4098  *  0b00010..ECC 4 to be performed
4099  *  0b11110..ECC 60 to be performed
4100  *  0b11111..ECC 62 to be performed
4101  */
4102 #define BCH_FLASH3LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
4103 #define BCH_FLASH3LAYOUT0_META_SIZE_MASK         (0xFF0000U)
4104 #define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT        (16U)
4105 /*! META_SIZE - META_SIZE
4106  */
4107 #define BCH_FLASH3LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
4108 #define BCH_FLASH3LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
4109 #define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT          (24U)
4110 /*! NBLOCKS - NBLOCKS
4111  */
4112 #define BCH_FLASH3LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
4113 /*! @} */
4114 
4115 /*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
4116 /*! @{ */
4117 #define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
4118 #define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT       (0U)
4119 /*! DATAN_SIZE - DATAN_SIZE
4120  */
4121 #define BCH_FLASH3LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
4122 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
4123 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
4124 /*! GF13_0_GF14_1 - GF13_0_GF14_1
4125  */
4126 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
4127 #define BCH_FLASH3LAYOUT1_ECCN_MASK              (0xF800U)
4128 #define BCH_FLASH3LAYOUT1_ECCN_SHIFT             (11U)
4129 /*! ECCN - ECCN
4130  *  0b00000..No ECC to be performed
4131  *  0b00001..ECC 2 to be performed
4132  *  0b00010..ECC 4 to be performed
4133  *  0b11110..ECC 60 to be performed
4134  *  0b11111..ECC 62 to be performed
4135  */
4136 #define BCH_FLASH3LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
4137 #define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
4138 #define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT        (16U)
4139 /*! PAGE_SIZE - PAGE_SIZE
4140  */
4141 #define BCH_FLASH3LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
4142 /*! @} */
4143 
4144 /*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
4145 /*! @{ */
4146 #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK         (0x3FU)
4147 #define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT        (0U)
4148 /*! DEBUG_REG_SELECT - DEBUG_REG_SELECT
4149  */
4150 #define BCH_DEBUG0_DEBUG_REG_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
4151 #define BCH_DEBUG0_RSVD0_MASK                    (0xC0U)
4152 #define BCH_DEBUG0_RSVD0_SHIFT                   (6U)
4153 /*! RSVD0 - This field is reserved.
4154  */
4155 #define BCH_DEBUG0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
4156 #define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK       (0x100U)
4157 #define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT      (8U)
4158 /*! BM_KES_TEST_BYPASS - BM_KES_TEST_BYPASS
4159  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
4160  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4161  */
4162 #define BCH_DEBUG0_BM_KES_TEST_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
4163 #define BCH_DEBUG0_KES_DEBUG_STALL_MASK          (0x200U)
4164 #define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT         (9U)
4165 /*! KES_DEBUG_STALL - KES_DEBUG_STALL
4166  *  0b0..KES FSM proceeds to next block supplied by bus master.
4167  *  0b1..KES FSM waits after current equations are solved and the search engine is started.
4168  */
4169 #define BCH_DEBUG0_KES_DEBUG_STALL(x)            (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
4170 #define BCH_DEBUG0_KES_DEBUG_STEP_MASK           (0x400U)
4171 #define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT          (10U)
4172 /*! KES_DEBUG_STEP - KES_DEBUG_STEP
4173  */
4174 #define BCH_DEBUG0_KES_DEBUG_STEP(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
4175 #define BCH_DEBUG0_KES_STANDALONE_MASK           (0x800U)
4176 #define BCH_DEBUG0_KES_STANDALONE_SHIFT          (11U)
4177 /*! KES_STANDALONE - KES_STANDALONE
4178  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
4179  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4180  */
4181 #define BCH_DEBUG0_KES_STANDALONE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
4182 #define BCH_DEBUG0_KES_DEBUG_KICK_MASK           (0x1000U)
4183 #define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT          (12U)
4184 /*! KES_DEBUG_KICK - KES_DEBUG_KICK
4185  */
4186 #define BCH_DEBUG0_KES_DEBUG_KICK(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
4187 #define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK         (0x2000U)
4188 #define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT        (13U)
4189 /*! KES_DEBUG_MODE4K - KES_DEBUG_MODE4K
4190  *  0b1..Mode is set for 4K NAND pages.
4191  *  0b1..Mode is set for 2K NAND pages.
4192  */
4193 #define BCH_DEBUG0_KES_DEBUG_MODE4K(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
4194 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK   (0x4000U)
4195 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT  (14U)
4196 /*! KES_DEBUG_PAYLOAD_FLAG - KES_DEBUG_PAYLOAD_FLAG
4197  *  0b1..Payload is set for 512 bytes data block.
4198  *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
4199  */
4200 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
4201 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK     (0x8000U)
4202 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT    (15U)
4203 /*! KES_DEBUG_SHIFT_SYND - KES_DEBUG_SHIFT_SYND
4204  */
4205 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
4206 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
4207 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
4208 /*! KES_DEBUG_SYNDROME_SYMBOL - KES_DEBUG_SYNDROME_SYMBOL
4209  *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
4210  *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
4211  */
4212 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x)  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
4213 #define BCH_DEBUG0_RSVD1_MASK                    (0xFE000000U)
4214 #define BCH_DEBUG0_RSVD1_SHIFT                   (25U)
4215 /*! RSVD1 - This field is reserved.
4216  */
4217 #define BCH_DEBUG0_RSVD1(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
4218 /*! @} */
4219 
4220 /*! @name DBGKESREAD - KES Debug Read Register */
4221 /*! @{ */
4222 #define BCH_DBGKESREAD_VALUES_MASK               (0xFFFFFFFFU)
4223 #define BCH_DBGKESREAD_VALUES_SHIFT              (0U)
4224 /*! VALUES - VALUES
4225  */
4226 #define BCH_DBGKESREAD_VALUES(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
4227 /*! @} */
4228 
4229 /*! @name DBGCSFEREAD - Chien Search Debug Read Register */
4230 /*! @{ */
4231 #define BCH_DBGCSFEREAD_VALUES_MASK              (0xFFFFFFFFU)
4232 #define BCH_DBGCSFEREAD_VALUES_SHIFT             (0U)
4233 /*! VALUES - VALUES
4234  */
4235 #define BCH_DBGCSFEREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
4236 /*! @} */
4237 
4238 /*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
4239 /*! @{ */
4240 #define BCH_DBGSYNDGENREAD_VALUES_MASK           (0xFFFFFFFFU)
4241 #define BCH_DBGSYNDGENREAD_VALUES_SHIFT          (0U)
4242 /*! VALUES - VALUES
4243  */
4244 #define BCH_DBGSYNDGENREAD_VALUES(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
4245 /*! @} */
4246 
4247 /*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
4248 /*! @{ */
4249 #define BCH_DBGAHBMREAD_VALUES_MASK              (0xFFFFFFFFU)
4250 #define BCH_DBGAHBMREAD_VALUES_SHIFT             (0U)
4251 /*! VALUES - VALUES
4252  */
4253 #define BCH_DBGAHBMREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
4254 /*! @} */
4255 
4256 /*! @name BLOCKNAME - Block Name Register */
4257 /*! @{ */
4258 #define BCH_BLOCKNAME_NAME_MASK                  (0xFFFFFFFFU)
4259 #define BCH_BLOCKNAME_NAME_SHIFT                 (0U)
4260 /*! NAME - NAME
4261  */
4262 #define BCH_BLOCKNAME_NAME(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
4263 /*! @} */
4264 
4265 /*! @name VERSION - BCH Version Register */
4266 /*! @{ */
4267 #define BCH_VERSION_STEP_MASK                    (0xFFFFU)
4268 #define BCH_VERSION_STEP_SHIFT                   (0U)
4269 /*! STEP - STEP
4270  */
4271 #define BCH_VERSION_STEP(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
4272 #define BCH_VERSION_MINOR_MASK                   (0xFF0000U)
4273 #define BCH_VERSION_MINOR_SHIFT                  (16U)
4274 /*! MINOR - MINOR
4275  */
4276 #define BCH_VERSION_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
4277 #define BCH_VERSION_MAJOR_MASK                   (0xFF000000U)
4278 #define BCH_VERSION_MAJOR_SHIFT                  (24U)
4279 /*! MAJOR - MAJOR
4280  */
4281 #define BCH_VERSION_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
4282 /*! @} */
4283 
4284 /*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
4285 /*! @{ */
4286 #define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK        (0x1FFU)
4287 #define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT       (0U)
4288 /*! ERASED_ZERO_COUNT - ERASED_ZERO_COUNT
4289  */
4290 #define BCH_DEBUG1_ERASED_ZERO_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
4291 #define BCH_DEBUG1_RSVD_MASK                     (0x7FFFFE00U)
4292 #define BCH_DEBUG1_RSVD_SHIFT                    (9U)
4293 /*! RSVD - This field is reserved.
4294  */
4295 #define BCH_DEBUG1_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
4296 #define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK       (0x80000000U)
4297 #define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT      (31U)
4298 /*! DEBUG1_PREERASECHK - DEBUG1_PREERASECHK
4299  *  0b0..Turn off pre-erase check
4300  *  0b1..Turn on pre-erase check
4301  */
4302 #define BCH_DEBUG1_DEBUG1_PREERASECHK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
4303 /*! @} */
4304 
4305 
4306 /*!
4307  * @}
4308  */ /* end of group BCH_Register_Masks */
4309 
4310 
4311 /* BCH - Peripheral instance base addresses */
4312 /** Peripheral CONNECTIVITY__BCH base address */
4313 #define CONNECTIVITY__BCH_BASE                   (0x5B814000u)
4314 /** Peripheral CONNECTIVITY__BCH base pointer */
4315 #define CONNECTIVITY__BCH                        ((BCH_Type *)CONNECTIVITY__BCH_BASE)
4316 /** Array initializer of BCH peripheral base addresses */
4317 #define BCH_BASE_ADDRS                           { CONNECTIVITY__BCH_BASE }
4318 /** Array initializer of BCH peripheral base pointers */
4319 #define BCH_BASE_PTRS                            { CONNECTIVITY__BCH }
4320 
4321 /*!
4322  * @}
4323  */ /* end of group BCH_Peripheral_Access_Layer */
4324 
4325 
4326 /* ----------------------------------------------------------------------------
4327    -- CAN Peripheral Access Layer
4328    ---------------------------------------------------------------------------- */
4329 
4330 /*!
4331  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
4332  * @{
4333  */
4334 
4335 /** CAN - Register Layout Typedef */
4336 typedef struct {
4337   __IO uint32_t MCR;                               /**< Module Configuration register, offset: 0x0 */
4338   __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
4339   __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
4340        uint8_t RESERVED_0[4];
4341   __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask register, offset: 0x10 */
4342   __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
4343   __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
4344   __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
4345   __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
4346   __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 register, offset: 0x24 */
4347   __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
4348   __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 register, offset: 0x2C */
4349   __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
4350   __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
4351   __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
4352        uint8_t RESERVED_1[8];
4353   __I  uint32_t CRCR;                              /**< CRC register, offset: 0x44 */
4354   __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
4355   __I  uint32_t RXFIR;                             /**< Rx FIFO Information register, offset: 0x4C */
4356   __IO uint32_t CBT;                               /**< CAN Bit Timing register, offset: 0x50 */
4357        uint8_t RESERVED_2[4];
4358   __I  uint32_t DBG1;                              /**< Debug 1 register, offset: 0x58 */
4359   __I  uint32_t DBG2;                              /**< Debug 2 register, offset: 0x5C */
4360        uint8_t RESERVED_3[32];
4361   struct {                                         /* offset: 0x80, array step: 0x10 */
4362     __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
4363     __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
4364     __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
4365     __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
4366   } MB[64];
4367        uint8_t RESERVED_4[1024];
4368   __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
4369        uint8_t RESERVED_5[640];
4370   __IO uint32_t FDCTRL;                            /**< CAN FD Control register, offset: 0xC00 */
4371   __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing register, offset: 0xC04 */
4372   __I  uint32_t FDCRC;                             /**< CAN FD CRC register, offset: 0xC08 */
4373 } CAN_Type;
4374 
4375 /* ----------------------------------------------------------------------------
4376    -- CAN Register Masks
4377    ---------------------------------------------------------------------------- */
4378 
4379 /*!
4380  * @addtogroup CAN_Register_Masks CAN Register Masks
4381  * @{
4382  */
4383 
4384 /*! @name MCR - Module Configuration register */
4385 /*! @{ */
4386 #define CAN_MCR_MAXMB_MASK                       (0x7FU)
4387 #define CAN_MCR_MAXMB_SHIFT                      (0U)
4388 /*! MAXMB - Number Of The Last Message Buffer
4389  */
4390 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4391 #define CAN_MCR_IDAM_MASK                        (0x300U)
4392 #define CAN_MCR_IDAM_SHIFT                       (8U)
4393 /*! IDAM - ID Acceptance Mode
4394  *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
4395  *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
4396  *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
4397  *  0b11..Format D: All frames rejected.
4398  */
4399 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4400 #define CAN_MCR_FDEN_MASK                        (0x800U)
4401 #define CAN_MCR_FDEN_SHIFT                       (11U)
4402 /*! FDEN - CAN FD operation enable
4403  *  0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
4404  *  0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
4405  */
4406 #define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
4407 #define CAN_MCR_AEN_MASK                         (0x1000U)
4408 #define CAN_MCR_AEN_SHIFT                        (12U)
4409 /*! AEN - Abort Enable
4410  *  0b0..Abort disabled.
4411  *  0b1..Abort enabled.
4412  */
4413 #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4414 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
4415 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
4416 /*! LPRIOEN - Local Priority Enable
4417  *  0b0..Local Priority disabled.
4418  *  0b1..Local Priority enabled.
4419  */
4420 #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4421 #define CAN_MCR_DMA_MASK                         (0x8000U)
4422 #define CAN_MCR_DMA_SHIFT                        (15U)
4423 /*! DMA - DMA Enable
4424  *  0b0..DMA feature for RX FIFO disabled.
4425  *  0b1..DMA feature for RX FIFO enabled.
4426  */
4427 #define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
4428 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
4429 #define CAN_MCR_IRMQ_SHIFT                       (16U)
4430 /*! IRMQ - Individual Rx Masking And Queue Enable
4431  *  0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
4432  *       applications, the reading of C/S word locks the MB even if it is EMPTY.
4433  *  0b1..Individual Rx masking and queue feature are enabled.
4434  */
4435 #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4436 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
4437 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
4438 /*! SRXDIS - Self Reception Disable
4439  *  0b0..Self-reception enabled.
4440  *  0b1..Self-reception disabled.
4441  */
4442 #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4443 #define CAN_MCR_DOZE_MASK                        (0x40000U)
4444 #define CAN_MCR_DOZE_SHIFT                       (18U)
4445 /*! DOZE - Doze Mode Enable
4446  *  0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
4447  *  0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
4448  */
4449 #define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
4450 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
4451 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
4452 /*! WAKSRC - Wake Up Source
4453  *  0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
4454  *  0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
4455  */
4456 #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4457 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
4458 #define CAN_MCR_LPMACK_SHIFT                     (20U)
4459 /*! LPMACK - Low-Power Mode Acknowledge
4460  *  0b0..FlexCAN is not in a low-power mode.
4461  *  0b1..FlexCAN is in a low-power mode.
4462  */
4463 #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4464 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
4465 #define CAN_MCR_WRNEN_SHIFT                      (21U)
4466 /*! WRNEN - Warning Interrupt Enable
4467  *  0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
4468  *  0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
4469  */
4470 #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4471 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
4472 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
4473 /*! SLFWAK - Self Wake Up
4474  *  0b0..FlexCAN Self Wake Up feature is disabled.
4475  *  0b1..FlexCAN Self Wake Up feature is enabled.
4476  */
4477 #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4478 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
4479 #define CAN_MCR_FRZACK_SHIFT                     (24U)
4480 /*! FRZACK - Freeze Mode Acknowledge
4481  *  0b0..FlexCAN not in Freeze mode, prescaler running.
4482  *  0b1..FlexCAN in Freeze mode, prescaler stopped.
4483  */
4484 #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4485 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
4486 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
4487 /*! SOFTRST - Soft Reset
4488  *  0b0..No reset request.
4489  *  0b1..Resets the registers affected by soft reset.
4490  */
4491 #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4492 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
4493 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
4494 /*! WAKMSK - Wake Up Interrupt Mask
4495  *  0b0..Wake Up interrupt is disabled.
4496  *  0b1..Wake Up interrupt is enabled.
4497  */
4498 #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4499 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
4500 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
4501 /*! NOTRDY - FlexCAN Not Ready
4502  *  0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
4503  *  0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
4504  */
4505 #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4506 #define CAN_MCR_HALT_MASK                        (0x10000000U)
4507 #define CAN_MCR_HALT_SHIFT                       (28U)
4508 /*! HALT - Halt FlexCAN
4509  *  0b0..No Freeze mode request.
4510  *  0b1..Enters Freeze mode if the FRZ bit is asserted.
4511  */
4512 #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4513 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
4514 #define CAN_MCR_RFEN_SHIFT                       (29U)
4515 /*! RFEN - Rx FIFO Enable
4516  *  0b0..Rx FIFO not enabled.
4517  *  0b1..Rx FIFO enabled.
4518  */
4519 #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4520 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
4521 #define CAN_MCR_FRZ_SHIFT                        (30U)
4522 /*! FRZ - Freeze Enable
4523  *  0b0..Not enabled to enter Freeze mode.
4524  *  0b1..Enabled to enter Freeze mode.
4525  */
4526 #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4527 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
4528 #define CAN_MCR_MDIS_SHIFT                       (31U)
4529 /*! MDIS - Module Disable
4530  *  0b0..Enable the FlexCAN module.
4531  *  0b1..Disable the FlexCAN module.
4532  */
4533 #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4534 /*! @} */
4535 
4536 /*! @name CTRL1 - Control 1 register */
4537 /*! @{ */
4538 #define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
4539 #define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
4540 /*! PROPSEG - Propagation Segment
4541  */
4542 #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4543 #define CAN_CTRL1_LOM_MASK                       (0x8U)
4544 #define CAN_CTRL1_LOM_SHIFT                      (3U)
4545 /*! LOM - Listen-Only Mode
4546  *  0b0..Listen-Only mode is deactivated.
4547  *  0b1..FlexCAN module operates in Listen-Only mode.
4548  */
4549 #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4550 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
4551 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
4552 /*! LBUF - Lowest Buffer Transmitted First
4553  *  0b0..Buffer with highest priority is transmitted first.
4554  *  0b1..Lowest number buffer is transmitted first.
4555  */
4556 #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4557 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
4558 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
4559 /*! TSYN - Timer Sync
4560  *  0b0..Timer sync feature disabled
4561  *  0b1..Timer sync feature enabled
4562  */
4563 #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4564 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
4565 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
4566 /*! BOFFREC - Bus Off Recovery
4567  *  0b0..Automatic recovering from Bus Off state enabled.
4568  *  0b1..Automatic recovering from Bus Off state disabled.
4569  */
4570 #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4571 #define CAN_CTRL1_SMP_MASK                       (0x80U)
4572 #define CAN_CTRL1_SMP_SHIFT                      (7U)
4573 /*! SMP - CAN Bit Sampling
4574  *  0b0..Just one sample is used to determine the bit value.
4575  *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
4576  *       preceding samples; a majority rule is used.
4577  */
4578 #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4579 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
4580 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
4581 /*! RWRNMSK - Rx Warning Interrupt Mask
4582  *  0b0..Rx Warning interrupt disabled.
4583  *  0b1..Rx Warning interrupt enabled.
4584  */
4585 #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4586 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
4587 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
4588 /*! TWRNMSK - Tx Warning Interrupt Mask
4589  *  0b0..Tx Warning interrupt disabled.
4590  *  0b1..Tx Warning interrupt enabled.
4591  */
4592 #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4593 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
4594 #define CAN_CTRL1_LPB_SHIFT                      (12U)
4595 /*! LPB - Loop Back Mode
4596  *  0b0..Loop Back disabled.
4597  *  0b1..Loop Back enabled.
4598  */
4599 #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4600 #define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
4601 #define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
4602 /*! CLKSRC - CAN Engine Clock Source
4603  *  0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
4604  *  0b1..The CAN engine clock source is the peripheral clock.
4605  */
4606 #define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4607 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
4608 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
4609 /*! ERRMSK - Error Interrupt Mask
4610  *  0b0..Error interrupt disabled.
4611  *  0b1..Error interrupt enabled.
4612  */
4613 #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4614 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
4615 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
4616 /*! BOFFMSK - Bus Off Interrupt Mask
4617  *  0b0..Bus Off interrupt disabled.
4618  *  0b1..Bus Off interrupt enabled.
4619  */
4620 #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4621 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
4622 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
4623 /*! PSEG2 - Phase Segment 2
4624  */
4625 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4626 #define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
4627 #define CAN_CTRL1_PSEG1_SHIFT                    (19U)
4628 /*! PSEG1 - Phase Segment 1
4629  */
4630 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4631 #define CAN_CTRL1_RJW_MASK                       (0xC00000U)
4632 #define CAN_CTRL1_RJW_SHIFT                      (22U)
4633 /*! RJW - Resync Jump Width
4634  */
4635 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4636 #define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
4637 #define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
4638 /*! PRESDIV - Prescaler Division Factor
4639  */
4640 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4641 /*! @} */
4642 
4643 /*! @name TIMER - Free Running Timer */
4644 /*! @{ */
4645 #define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
4646 #define CAN_TIMER_TIMER_SHIFT                    (0U)
4647 /*! TIMER - Timer Value
4648  */
4649 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4650 /*! @} */
4651 
4652 /*! @name RXMGMASK - Rx Mailboxes Global Mask register */
4653 /*! @{ */
4654 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
4655 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
4656 /*! MG - Rx Mailboxes Global Mask Bits
4657  */
4658 #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4659 /*! @} */
4660 
4661 /*! @name RX14MASK - Rx 14 Mask register */
4662 /*! @{ */
4663 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
4664 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
4665 /*! RX14M - Rx Buffer 14 Mask Bits
4666  */
4667 #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4668 /*! @} */
4669 
4670 /*! @name RX15MASK - Rx 15 Mask register */
4671 /*! @{ */
4672 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
4673 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
4674 /*! RX15M - Rx Buffer 15 Mask Bits
4675  */
4676 #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4677 /*! @} */
4678 
4679 /*! @name ECR - Error Counter */
4680 /*! @{ */
4681 #define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
4682 #define CAN_ECR_TXERRCNT_SHIFT                   (0U)
4683 /*! TXERRCNT - Transmit Error Counter
4684  */
4685 #define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4686 #define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
4687 #define CAN_ECR_RXERRCNT_SHIFT                   (8U)
4688 /*! RXERRCNT - Receive Error Counter
4689  */
4690 #define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4691 #define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
4692 #define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
4693 /*! TXERRCNT_FAST - Transmit Error Counter for fast bits
4694  */
4695 #define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
4696 #define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
4697 #define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
4698 /*! RXERRCNT_FAST - Receive Error Counter for fast bits
4699  */
4700 #define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
4701 /*! @} */
4702 
4703 /*! @name ESR1 - Error and Status 1 register */
4704 /*! @{ */
4705 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
4706 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
4707 /*! WAKINT - Wake-Up Interrupt
4708  *  0b0..No such occurrence.
4709  *  0b1..Indicates a recessive to dominant transition was received on the CAN bus.
4710  */
4711 #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4712 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
4713 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
4714 /*! ERRINT - Error Interrupt
4715  *  0b0..No such occurrence.
4716  *  0b1..Indicates setting of any error bit in the Error and Status register.
4717  */
4718 #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4719 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
4720 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
4721 /*! BOFFINT - Bus Off Interrupt
4722  *  0b0..No such occurrence.
4723  *  0b1..FlexCAN module entered Bus Off state.
4724  */
4725 #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4726 #define CAN_ESR1_RX_MASK                         (0x8U)
4727 #define CAN_ESR1_RX_SHIFT                        (3U)
4728 /*! RX - FlexCAN In Reception
4729  *  0b0..FlexCAN is not receiving a message.
4730  *  0b1..FlexCAN is receiving a message.
4731  */
4732 #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4733 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
4734 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
4735 /*! FLTCONF - Fault Confinement State
4736  *  0b00..Error Active
4737  *  0b01..Error Passive
4738  *  0b1x..Bus Off
4739  */
4740 #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4741 #define CAN_ESR1_TX_MASK                         (0x40U)
4742 #define CAN_ESR1_TX_SHIFT                        (6U)
4743 /*! TX - FlexCAN In Transmission
4744  *  0b0..FlexCAN is not transmitting a message.
4745  *  0b1..FlexCAN is transmitting a message.
4746  */
4747 #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4748 #define CAN_ESR1_IDLE_MASK                       (0x80U)
4749 #define CAN_ESR1_IDLE_SHIFT                      (7U)
4750 /*! IDLE - IDLE
4751  *  0b0..No such occurrence.
4752  *  0b1..CAN bus is now IDLE.
4753  */
4754 #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4755 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
4756 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
4757 /*! RXWRN - Rx Error Warning
4758  *  0b0..No such occurrence.
4759  *  0b1..RXERRCNT is greater than or equal to 96.
4760  */
4761 #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4762 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
4763 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
4764 /*! TXWRN - TX Error Warning
4765  *  0b0..No such occurrence.
4766  *  0b1..TXERRCNT is greater than or equal to 96.
4767  */
4768 #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4769 #define CAN_ESR1_STFERR_MASK                     (0x400U)
4770 #define CAN_ESR1_STFERR_SHIFT                    (10U)
4771 /*! STFERR - Stuffing Error
4772  *  0b0..No such occurrence.
4773  *  0b1..A stuffing error occurred since last read of this register.
4774  */
4775 #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4776 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
4777 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
4778 /*! FRMERR - Form Error
4779  *  0b0..No such occurrence.
4780  *  0b1..A Form Error occurred since last read of this register.
4781  */
4782 #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4783 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
4784 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
4785 /*! CRCERR - Cyclic Redundancy Check Error
4786  *  0b0..No such occurrence.
4787  *  0b1..A CRC error occurred since last read of this register.
4788  */
4789 #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4790 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
4791 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
4792 /*! ACKERR - Acknowledge Error
4793  *  0b0..No such occurrence.
4794  *  0b1..An ACK error occurred since last read of this register.
4795  */
4796 #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4797 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
4798 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
4799 /*! BIT0ERR - Bit0 Error
4800  *  0b0..No such occurrence.
4801  *  0b1..At least one bit sent as dominant is received as recessive.
4802  */
4803 #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4804 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
4805 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
4806 /*! BIT1ERR - Bit1 Error
4807  *  0b0..No such occurrence.
4808  *  0b1..At least one bit sent as recessive is received as dominant.
4809  */
4810 #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4811 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
4812 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
4813 /*! RWRNINT - Rx Warning Interrupt Flag
4814  *  0b0..No such occurrence.
4815  *  0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
4816  */
4817 #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4818 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
4819 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
4820 /*! TWRNINT - Tx Warning Interrupt Flag
4821  *  0b0..No such occurrence.
4822  *  0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
4823  */
4824 #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4825 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
4826 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
4827 /*! SYNCH - CAN Synchronization Status
4828  *  0b0..FlexCAN is not synchronized to the CAN bus.
4829  *  0b1..FlexCAN is synchronized to the CAN bus.
4830  */
4831 #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4832 #define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
4833 #define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
4834 /*! BOFFDONEINT - Bus Off Done Interrupt
4835  *  0b0..No such occurrence.
4836  *  0b1..FlexCAN module has completed Bus Off process.
4837  */
4838 #define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
4839 #define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
4840 #define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
4841 /*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
4842  *  0b0..No such occurrence.
4843  *  0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
4844  */
4845 #define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
4846 #define CAN_ESR1_ERROVR_MASK                     (0x200000U)
4847 #define CAN_ESR1_ERROVR_SHIFT                    (21U)
4848 /*! ERROVR - Error Overrun
4849  *  0b0..Overrun has not occurred.
4850  *  0b1..Overrun has occurred.
4851  */
4852 #define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
4853 #define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
4854 #define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
4855 /*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
4856  *  0b0..No such occurrence.
4857  *  0b1..A stuffing error occurred since last read of this register.
4858  */
4859 #define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
4860 #define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
4861 #define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
4862 /*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
4863  *  0b0..No such occurrence.
4864  *  0b1..A form error occurred since last read of this register.
4865  */
4866 #define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
4867 #define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
4868 #define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
4869 /*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
4870  *  0b0..No such occurrence.
4871  *  0b1..A CRC error occurred since last read of this register.
4872  */
4873 #define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
4874 #define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
4875 #define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
4876 /*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
4877  *  0b0..No such occurrence.
4878  *  0b1..At least one bit sent as dominant is received as recessive.
4879  */
4880 #define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
4881 #define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
4882 #define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
4883 /*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
4884  *  0b0..No such occurrence.
4885  *  0b1..At least one bit sent as recessive is received as dominant.
4886  */
4887 #define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
4888 /*! @} */
4889 
4890 /*! @name IMASK2 - Interrupt Masks 2 register */
4891 /*! @{ */
4892 #define CAN_IMASK2_BUF63TO32M_MASK               (0xFFFFFFFFU)
4893 #define CAN_IMASK2_BUF63TO32M_SHIFT              (0U)
4894 /*! BUF63TO32M - Buffer MBi Mask
4895  */
4896 #define CAN_IMASK2_BUF63TO32M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
4897 /*! @} */
4898 
4899 /*! @name IMASK1 - Interrupt Masks 1 register */
4900 /*! @{ */
4901 #define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
4902 #define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
4903 /*! BUF31TO0M - Buffer MBi Mask
4904  */
4905 #define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
4906 /*! @} */
4907 
4908 /*! @name IFLAG2 - Interrupt Flags 2 register */
4909 /*! @{ */
4910 #define CAN_IFLAG2_BUF63TO32I_MASK               (0xFFFFFFFFU)
4911 #define CAN_IFLAG2_BUF63TO32I_SHIFT              (0U)
4912 /*! BUF63TO32I - Buffer MBi Interrupt
4913  */
4914 #define CAN_IFLAG2_BUF63TO32I(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
4915 /*! @} */
4916 
4917 /*! @name IFLAG1 - Interrupt Flags 1 register */
4918 /*! @{ */
4919 #define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
4920 #define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
4921 /*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
4922  *  0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
4923  *  0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
4924  */
4925 #define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4926 #define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
4927 #define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
4928 /*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
4929  */
4930 #define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4931 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
4932 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
4933 /*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
4934  *  0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
4935  *  0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
4936  *       MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
4937  */
4938 #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4939 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
4940 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
4941 /*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
4942  *  0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
4943  *  0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
4944  */
4945 #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4946 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
4947 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
4948 /*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
4949  *  0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
4950  *  0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
4951  */
4952 #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4953 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
4954 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
4955 /*! BUF31TO8I - Buffer MBi Interrupt
4956  */
4957 #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4958 /*! @} */
4959 
4960 /*! @name CTRL2 - Control 2 register */
4961 /*! @{ */
4962 #define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
4963 #define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
4964 /*! EDFLTDIS - Edge Filter Disable
4965  *  0b0..Edge filter is enabled
4966  *  0b1..Edge filter is disabled
4967  */
4968 #define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
4969 #define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
4970 #define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
4971 /*! ISOCANFDEN - ISO CAN FD Enable
4972  *  0b0..FlexCAN operates using the non-ISO CAN FD protocol.
4973  *  0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
4974  */
4975 #define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
4976 #define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
4977 #define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
4978 /*! PREXCEN - Protocol Exception Enable
4979  *  0b0..Protocol exception is disabled.
4980  *  0b1..Protocol exception is enabled.
4981  */
4982 #define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
4983 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
4984 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
4985 /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
4986  *  0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
4987  *  0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
4988  *       the incoming frame. Mask bits do apply.
4989  */
4990 #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4991 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
4992 #define CAN_CTRL2_RRS_SHIFT                      (17U)
4993 /*! RRS - Remote Request Storing
4994  *  0b0..Remote response frame is generated.
4995  *  0b1..Remote request frame is stored.
4996  */
4997 #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4998 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
4999 #define CAN_CTRL2_MRP_SHIFT                      (18U)
5000 /*! MRP - Mailboxes Reception Priority
5001  *  0b0..Matching starts from Rx FIFO and continues on mailboxes.
5002  *  0b1..Matching starts from mailboxes and continues on Rx FIFO.
5003  */
5004 #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
5005 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
5006 #define CAN_CTRL2_TASD_SHIFT                     (19U)
5007 /*! TASD - Tx Arbitration Start Delay
5008  */
5009 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
5010 #define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
5011 #define CAN_CTRL2_RFFN_SHIFT                     (24U)
5012 /*! RFFN - Number Of Rx FIFO Filters
5013  */
5014 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
5015 #define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
5016 #define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
5017 /*! BOFFDONEMSK - Bus Off Done Interrupt Mask
5018  *  0b0..Bus off done interrupt disabled.
5019  *  0b1..Bus off done interrupt enabled.
5020  */
5021 #define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
5022 #define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
5023 #define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
5024 /*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
5025  *  0b0..ERRINT_FAST error interrupt disabled.
5026  *  0b1..ERRINT_FAST error interrupt enabled.
5027  */
5028 #define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
5029 /*! @} */
5030 
5031 /*! @name ESR2 - Error and Status 2 register */
5032 /*! @{ */
5033 #define CAN_ESR2_IMB_MASK                        (0x2000U)
5034 #define CAN_ESR2_IMB_SHIFT                       (13U)
5035 /*! IMB - Inactive Mailbox
5036  *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
5037  *  0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
5038  */
5039 #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
5040 #define CAN_ESR2_VPS_MASK                        (0x4000U)
5041 #define CAN_ESR2_VPS_SHIFT                       (14U)
5042 /*! VPS - Valid Priority Status
5043  *  0b0..Contents of IMB and LPTM are invalid.
5044  *  0b1..Contents of IMB and LPTM are valid.
5045  */
5046 #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
5047 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
5048 #define CAN_ESR2_LPTM_SHIFT                      (16U)
5049 /*! LPTM - Lowest Priority Tx Mailbox
5050  */
5051 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
5052 /*! @} */
5053 
5054 /*! @name CRCR - CRC register */
5055 /*! @{ */
5056 #define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
5057 #define CAN_CRCR_TXCRC_SHIFT                     (0U)
5058 /*! TXCRC - Transmitted CRC value
5059  */
5060 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
5061 #define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
5062 #define CAN_CRCR_MBCRC_SHIFT                     (16U)
5063 /*! MBCRC - CRC Mailbox
5064  */
5065 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
5066 /*! @} */
5067 
5068 /*! @name RXFGMASK - Rx FIFO Global Mask register */
5069 /*! @{ */
5070 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
5071 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
5072 /*! FGM - Rx FIFO Global Mask Bits
5073  */
5074 #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
5075 /*! @} */
5076 
5077 /*! @name RXFIR - Rx FIFO Information register */
5078 /*! @{ */
5079 #define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
5080 #define CAN_RXFIR_IDHIT_SHIFT                    (0U)
5081 /*! IDHIT - Identifier Acceptance Filter Hit Indicator
5082  */
5083 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
5084 /*! @} */
5085 
5086 /*! @name CBT - CAN Bit Timing register */
5087 /*! @{ */
5088 #define CAN_CBT_EPSEG2_MASK                      (0x1FU)
5089 #define CAN_CBT_EPSEG2_SHIFT                     (0U)
5090 /*! EPSEG2 - Extended Phase Segment 2
5091  */
5092 #define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
5093 #define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
5094 #define CAN_CBT_EPSEG1_SHIFT                     (5U)
5095 /*! EPSEG1 - Extended Phase Segment 1
5096  */
5097 #define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
5098 #define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
5099 #define CAN_CBT_EPROPSEG_SHIFT                   (10U)
5100 /*! EPROPSEG - Extended Propagation Segment
5101  */
5102 #define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
5103 #define CAN_CBT_ERJW_MASK                        (0x1F0000U)
5104 #define CAN_CBT_ERJW_SHIFT                       (16U)
5105 /*! ERJW - Extended Resync Jump Width
5106  */
5107 #define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
5108 #define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
5109 #define CAN_CBT_EPRESDIV_SHIFT                   (21U)
5110 /*! EPRESDIV - Extended Prescaler Division Factor
5111  */
5112 #define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
5113 #define CAN_CBT_BTF_MASK                         (0x80000000U)
5114 #define CAN_CBT_BTF_SHIFT                        (31U)
5115 /*! BTF - Bit Timing Format Enable
5116  *  0b0..Extended bit time definitions disabled.
5117  *  0b1..Extended bit time definitions enabled.
5118  */
5119 #define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
5120 /*! @} */
5121 
5122 /*! @name DBG1 - Debug 1 register */
5123 /*! @{ */
5124 #define CAN_DBG1_CFSM_MASK                       (0x7FU)
5125 #define CAN_DBG1_CFSM_SHIFT                      (0U)
5126 /*! CFSM - CAN Finite State Machine
5127  */
5128 #define CAN_DBG1_CFSM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
5129 #define CAN_DBG1_CBN_MASK                        (0x3FF0000U)
5130 #define CAN_DBG1_CBN_SHIFT                       (16U)
5131 /*! CBN - CAN Bit Number
5132  */
5133 #define CAN_DBG1_CBN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
5134 /*! @} */
5135 
5136 /*! @name DBG2 - Debug 2 register */
5137 /*! @{ */
5138 #define CAN_DBG2_RMP_MASK                        (0x7FU)
5139 #define CAN_DBG2_RMP_SHIFT                       (0U)
5140 /*! RMP - Rx Matching Pointer
5141  */
5142 #define CAN_DBG2_RMP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
5143 #define CAN_DBG2_MPP_MASK                        (0x80U)
5144 #define CAN_DBG2_MPP_SHIFT                       (7U)
5145 /*! MPP - Matching Process in Progress
5146  *  0b0..No matching process ongoing
5147  *  0b1..Matching process is in progress.
5148  */
5149 #define CAN_DBG2_MPP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
5150 #define CAN_DBG2_TAP_MASK                        (0x7F00U)
5151 #define CAN_DBG2_TAP_SHIFT                       (8U)
5152 /*! TAP - Tx Arbitration Pointer
5153  */
5154 #define CAN_DBG2_TAP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
5155 #define CAN_DBG2_APP_MASK                        (0x8000U)
5156 #define CAN_DBG2_APP_SHIFT                       (15U)
5157 /*! APP - Arbitration Process in Progress
5158  *  0b0..No arbitration process ongoing
5159  *  0b1..Arbitration process is in progress.
5160  */
5161 #define CAN_DBG2_APP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
5162 /*! @} */
5163 
5164 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
5165 /*! @{ */
5166 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
5167 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
5168 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
5169  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
5170  *    appears on the CAN bus.
5171  */
5172 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
5173 #define CAN_CS_DLC_MASK                          (0xF0000U)
5174 #define CAN_CS_DLC_SHIFT                         (16U)
5175 /*! DLC - Length of the data to be stored/transmitted.
5176  */
5177 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
5178 #define CAN_CS_RTR_MASK                          (0x100000U)
5179 #define CAN_CS_RTR_SHIFT                         (20U)
5180 /*! RTR - Remote Transmission Request. One/zero for remote/data frame.
5181  */
5182 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
5183 #define CAN_CS_IDE_MASK                          (0x200000U)
5184 #define CAN_CS_IDE_SHIFT                         (21U)
5185 /*! IDE - ID Extended. One/zero for extended/standard format frame.
5186  */
5187 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
5188 #define CAN_CS_SRR_MASK                          (0x400000U)
5189 #define CAN_CS_SRR_SHIFT                         (22U)
5190 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
5191  */
5192 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
5193 #define CAN_CS_CODE_MASK                         (0xF000000U)
5194 #define CAN_CS_CODE_SHIFT                        (24U)
5195 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
5196  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
5197  */
5198 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
5199 #define CAN_CS_ESI_MASK                          (0x20000000U)
5200 #define CAN_CS_ESI_SHIFT                         (29U)
5201 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
5202  */
5203 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
5204 #define CAN_CS_BRS_MASK                          (0x40000000U)
5205 #define CAN_CS_BRS_SHIFT                         (30U)
5206 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
5207  */
5208 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
5209 #define CAN_CS_EDL_MASK                          (0x80000000U)
5210 #define CAN_CS_EDL_SHIFT                         (31U)
5211 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
5212  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
5213  */
5214 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
5215 /*! @} */
5216 
5217 /* The count of CAN_CS */
5218 #define CAN_CS_COUNT                             (64U)
5219 
5220 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
5221 /*! @{ */
5222 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
5223 #define CAN_ID_EXT_SHIFT                         (0U)
5224 /*! EXT - Contains extended (LOW word) identifier of message buffer.
5225  */
5226 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
5227 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
5228 #define CAN_ID_STD_SHIFT                         (18U)
5229 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
5230  */
5231 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
5232 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
5233 #define CAN_ID_PRIO_SHIFT                        (29U)
5234 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
5235  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
5236  *    ID to define the transmission priority.
5237  */
5238 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
5239 /*! @} */
5240 
5241 /* The count of CAN_ID */
5242 #define CAN_ID_COUNT                             (64U)
5243 
5244 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
5245 /*! @{ */
5246 #define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
5247 #define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
5248 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
5249  */
5250 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
5251 #define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
5252 #define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
5253 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
5254  */
5255 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
5256 #define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
5257 #define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
5258 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
5259  */
5260 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
5261 #define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
5262 #define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
5263 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
5264  */
5265 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
5266 /*! @} */
5267 
5268 /* The count of CAN_WORD0 */
5269 #define CAN_WORD0_COUNT                          (64U)
5270 
5271 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
5272 /*! @{ */
5273 #define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
5274 #define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
5275 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
5276  */
5277 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
5278 #define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
5279 #define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
5280 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
5281  */
5282 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
5283 #define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
5284 #define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
5285 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
5286  */
5287 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
5288 #define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
5289 #define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
5290 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
5291  */
5292 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
5293 /*! @} */
5294 
5295 /* The count of CAN_WORD1 */
5296 #define CAN_WORD1_COUNT                          (64U)
5297 
5298 /*! @name RXIMR - Rx Individual Mask registers */
5299 /*! @{ */
5300 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
5301 #define CAN_RXIMR_MI_SHIFT                       (0U)
5302 /*! MI - Individual Mask Bits
5303  */
5304 #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
5305 /*! @} */
5306 
5307 /* The count of CAN_RXIMR */
5308 #define CAN_RXIMR_COUNT                          (64U)
5309 
5310 /*! @name FDCTRL - CAN FD Control register */
5311 /*! @{ */
5312 #define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
5313 #define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
5314 /*! TDCVAL - Transceiver Delay Compensation Value
5315  */
5316 #define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
5317 #define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
5318 #define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
5319 /*! TDCOFF - Transceiver Delay Compensation Offset
5320  */
5321 #define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
5322 #define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
5323 #define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
5324 /*! TDCFAIL - Transceiver Delay Compensation Fail
5325  *  0b0..Measured loop delay is in range.
5326  *  0b1..Measured loop delay is out of range.
5327  */
5328 #define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
5329 #define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
5330 #define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
5331 /*! TDCEN - Transceiver Delay Compensation Enable
5332  *  0b0..TDC is disabled
5333  *  0b1..TDC is enabled
5334  */
5335 #define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
5336 #define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
5337 #define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
5338 /*! MBDSR0 - Message Buffer Data Size for Region 0
5339  *  0b00..Selects 8 bytes per message buffer.
5340  *  0b01..Selects 16 bytes per message buffer.
5341  *  0b10..Selects 32 bytes per message buffer.
5342  *  0b11..Selects 64 bytes per message buffer.
5343  */
5344 #define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
5345 #define CAN_FDCTRL_MBDSR1_MASK                   (0x180000U)
5346 #define CAN_FDCTRL_MBDSR1_SHIFT                  (19U)
5347 /*! MBDSR1 - Message Buffer Data Size for Region 1
5348  *  0b00..Selects 8 bytes per message buffer.
5349  *  0b01..Selects 16 bytes per message buffer.
5350  *  0b10..Selects 32 bytes per message buffer.
5351  *  0b11..Selects 64 bytes per message buffer.
5352  */
5353 #define CAN_FDCTRL_MBDSR1(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
5354 #define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
5355 #define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
5356 /*! FDRATE - Bit Rate Switch Enable
5357  *  0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
5358  *  0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
5359  */
5360 #define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
5361 /*! @} */
5362 
5363 /*! @name FDCBT - CAN FD Bit Timing register */
5364 /*! @{ */
5365 #define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
5366 #define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
5367 /*! FPSEG2 - Fast Phase Segment 2
5368  */
5369 #define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
5370 #define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
5371 #define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
5372 /*! FPSEG1 - Fast Phase Segment 1
5373  */
5374 #define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
5375 #define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
5376 #define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
5377 /*! FPROPSEG - Fast Propagation Segment
5378  */
5379 #define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
5380 #define CAN_FDCBT_FRJW_MASK                      (0x70000U)
5381 #define CAN_FDCBT_FRJW_SHIFT                     (16U)
5382 /*! FRJW - Fast Resync Jump Width
5383  */
5384 #define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
5385 #define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
5386 #define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
5387 /*! FPRESDIV - Fast Prescaler Division Factor
5388  */
5389 #define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
5390 /*! @} */
5391 
5392 /*! @name FDCRC - CAN FD CRC register */
5393 /*! @{ */
5394 #define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
5395 #define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
5396 /*! FD_TXCRC - Extended Transmitted CRC value
5397  */
5398 #define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
5399 #define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
5400 #define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
5401 /*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
5402  */
5403 #define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
5404 /*! @} */
5405 
5406 
5407 /*!
5408  * @}
5409  */ /* end of group CAN_Register_Masks */
5410 
5411 
5412 /* CAN - Peripheral instance base addresses */
5413 /** Peripheral ADMA__CAN0 base address */
5414 #define ADMA__CAN0_BASE                          (0x5A8D0000u)
5415 /** Peripheral ADMA__CAN0 base pointer */
5416 #define ADMA__CAN0                               ((CAN_Type *)ADMA__CAN0_BASE)
5417 /** Peripheral ADMA__CAN1 base address */
5418 #define ADMA__CAN1_BASE                          (0x5A8E0000u)
5419 /** Peripheral ADMA__CAN1 base pointer */
5420 #define ADMA__CAN1                               ((CAN_Type *)ADMA__CAN1_BASE)
5421 /** Peripheral ADMA__CAN2 base address */
5422 #define ADMA__CAN2_BASE                          (0x5A8F0000u)
5423 /** Peripheral ADMA__CAN2 base pointer */
5424 #define ADMA__CAN2                               ((CAN_Type *)ADMA__CAN2_BASE)
5425 /** Array initializer of CAN peripheral base addresses */
5426 #define CAN_BASE_ADDRS                           { ADMA__CAN0_BASE, ADMA__CAN1_BASE, ADMA__CAN2_BASE }
5427 /** Array initializer of CAN peripheral base pointers */
5428 #define CAN_BASE_PTRS                            { ADMA__CAN0, ADMA__CAN1, ADMA__CAN2 }
5429 /** Interrupt vectors for the CAN peripheral type */
5430 #define CAN_Rx_Warning_IRQS                      { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5431 #define CAN_Tx_Warning_IRQS                      { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5432 #define CAN_Wake_Up_IRQS                         { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5433 #define CAN_Error_IRQS                           { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5434 #define CAN_Bus_Off_IRQS                         { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5435 #define CAN_ORed_Message_buffer_IRQS             { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5436 
5437 /*!
5438  * @}
5439  */ /* end of group CAN_Peripheral_Access_Layer */
5440 
5441 
5442 /* ----------------------------------------------------------------------------
5443    -- CI_PI_CSR Peripheral Access Layer
5444    ---------------------------------------------------------------------------- */
5445 
5446 /*!
5447  * @addtogroup CI_PI_CSR_Peripheral_Access_Layer CI_PI_CSR Peripheral Access Layer
5448  * @{
5449  */
5450 
5451 /** CI_PI_CSR - Register Layout Typedef */
5452 typedef struct {
5453   struct {                                         /* offset: 0x0 */
5454     __IO uint32_t RW;                                /**< CI_PI Interface Control Register, offset: 0x0 */
5455     __IO uint32_t SET;                               /**< CI_PI Interface Control Register, offset: 0x4 */
5456     __IO uint32_t CLR;                               /**< CI_PI Interface Control Register, offset: 0x8 */
5457     __IO uint32_t TOG;                               /**< CI_PI Interface Control Register, offset: 0xC */
5458   } IF_CTRL_REG;
5459   struct {                                         /* offset: 0x10 */
5460     __IO uint32_t RW;                                /**< CSI Interface Control Register, offset: 0x10 */
5461     __IO uint32_t SET;                               /**< CSI Interface Control Register, offset: 0x14 */
5462     __IO uint32_t CLR;                               /**< CSI Interface Control Register, offset: 0x18 */
5463     __IO uint32_t TOG;                               /**< CSI Interface Control Register, offset: 0x1C */
5464   } CSI_CTRL_REG;
5465   struct {                                         /* offset: 0x20 */
5466     __I  uint32_t RW;                                /**< CSI Interface Status Register, offset: 0x20 */
5467     __I  uint32_t SET;                               /**< CSI Interface Status Register, offset: 0x24 */
5468     __I  uint32_t CLR;                               /**< CSI Interface Status Register, offset: 0x28 */
5469     __I  uint32_t TOG;                               /**< CSI Interface Status Register, offset: 0x2C */
5470   } CSI_STATUS;
5471   struct {                                         /* offset: 0x30 */
5472     __IO uint32_t RW;                                /**< CSI Interface Control Register1, offset: 0x30 */
5473     __IO uint32_t SET;                               /**< CSI Interface Control Register1, offset: 0x34 */
5474     __IO uint32_t CLR;                               /**< CSI Interface Control Register1, offset: 0x38 */
5475     __IO uint32_t TOG;                               /**< CSI Interface Control Register1, offset: 0x3C */
5476   } CSI_CTRL_REG1;
5477 } CI_PI_CSR_Type;
5478 
5479 /* ----------------------------------------------------------------------------
5480    -- CI_PI_CSR Register Masks
5481    ---------------------------------------------------------------------------- */
5482 
5483 /*!
5484  * @addtogroup CI_PI_CSR_Register_Masks CI_PI_CSR Register Masks
5485  * @{
5486  */
5487 
5488 /*! @name IF_CTRL_REG - CI_PI Interface Control Register */
5489 /*! @{ */
5490 #define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK     (0x1U)
5491 #define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT    (0U)
5492 #define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK)
5493 #define CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK      (0x2U)
5494 #define CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT     (1U)
5495 #define CI_PI_CSR_IF_CTRL_REG_PL_VALID(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK)
5496 #define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK       (0x1CU)
5497 #define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT      (2U)
5498 #define CI_PI_CSR_IF_CTRL_REG_PL_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK)
5499 #define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK      (0xE0U)
5500 #define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT     (5U)
5501 #define CI_PI_CSR_IF_CTRL_REG_IF_FORCE(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK)
5502 #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK (0x100U)
5503 #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT (8U)
5504 /*! DATA_TYPE_SEL - Pixel link data type select
5505  *  0b0..PL data type comes from the csi_interface
5506  *  0b1..PL data type comes from IF_CTRL DATA_TYPE[4:0]
5507  */
5508 #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK)
5509 #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK     (0x3E00U)
5510 #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT    (9U)
5511 /*! DATA_TYPE - Data type
5512  *  0b00000..Null data
5513  *  0b00100..RGB format
5514  *  0b01000..YUV444 Format
5515  *  0b10000..YYU420 odd line
5516  *  0b10010..YYU420 even line
5517  *  0b11000..YYY odd line
5518  *  0b11010..UYVY Even line
5519  *  0b11100..Raw
5520  */
5521 #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE(x)       (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK)
5522 /*! @} */
5523 
5524 /*! @name CSI_CTRL_REG - CSI Interface Control Register */
5525 /*! @{ */
5526 #define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK       (0x1U)
5527 #define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT      (0U)
5528 /*! CSI_EN - CSI interface enable
5529  */
5530 #define CI_PI_CSR_CSI_CTRL_REG_CSI_EN(x)         (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK)
5531 #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK (0x2U)
5532 #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT (1U)
5533 /*! PIXEL_CLK_POL - Pixel Clock polarity control
5534  *  0b0..Pixel Clock input is not inverted
5535  *  0b1..Pixel Clock input is inverted
5536  */
5537 #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL(x)  (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK)
5538 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK    (0x4U)
5539 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT   (2U)
5540 /*! HSYNC_POL - HSYNC polarity control
5541  *  0b0..HSYNC output to Pixel Link is not inverted
5542  *  0b1..HSYNC output to Pixel Link is inverted
5543  */
5544 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL(x)      (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK)
5545 #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK    (0x8U)
5546 #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT   (3U)
5547 /*! VSYNC_POL - VSYNC polarity control
5548  *  0b0..VSYNC output to Pixel Link is not inverted
5549  *  0b1..VSYNC output to Pixel Link is inverted
5550  */
5551 #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL(x)      (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK)
5552 #define CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK       (0x10U)
5553 #define CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT      (4U)
5554 /*! DE_POL - DE polarity control
5555  *  0b0..DE output to Pixel Link is not inverted
5556  *  0b1..DE output to Pixel Link is inverted
5557  */
5558 #define CI_PI_CSR_CSI_CTRL_REG_DE_POL(x)         (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK)
5559 #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK (0x20U)
5560 #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT (5U)
5561 /*! PIXEL_DATA_POL - PIXEL_DATA polarity control
5562  *  0b0..PIXEL_DATA output to Pixel Link is not inverted
5563  *  0b1..PIXEL_DATA output to Pixel Link is inverted
5564  */
5565 #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK)
5566 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK (0x40U)
5567 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT (6U)
5568 /*! CCIR_EXT_VSYNC_EN - External VSYNC enable
5569  */
5570 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK)
5571 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK      (0x80U)
5572 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT     (7U)
5573 /*! CCIR_EN - CCIR mode enable
5574  *  0b0..CCIR mode disable
5575  *  0b1..CCIR mode enable
5576  */
5577 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK)
5578 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK (0x100U)
5579 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT (8U)
5580 /*! CCIR_VIDEO_MODE - CCIR_VIDEO_MODE
5581  *  0b0..Progressive mode
5582  *  0b1..Interlace mode
5583  */
5584 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK)
5585 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK (0x200U)
5586 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT (9U)
5587 /*! CCIR_NTSC_EN - CCIR_NTSC enable
5588  *  0b0..PAL
5589  *  0b1..NTSC
5590  */
5591 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK)
5592 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK (0x400U)
5593 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT (10U)
5594 /*! CCIR_VSYNC_RESET_EN - CCIR_VSYNC_RESET_EN
5595  */
5596 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK)
5597 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK (0x800U)
5598 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT (11U)
5599 /*! CCIR_ECC_ERR_CORRECT_EN - CCIR_ECC_ERR_CORRECT_EN
5600  *  0b0..ECC error correction is disabled.
5601  *  0b1..ECC error correction is enabled.
5602  */
5603 #define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK)
5604 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK (0x1000U)
5605 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT (12U)
5606 /*! HSYNC_FORCE_EN - HSYNC_FORCE_EN
5607  *  0b0..Do not override HSYNC
5608  *  0b1..Override HSYNC
5609  */
5610 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK)
5611 #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK (0x2000U)
5612 #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT (13U)
5613 /*! VSYNC_FORCE_EN - VSYNC_FORCE_EN
5614  *  0b0..Do not override VSYNC
5615  *  0b1..Override VSYNC
5616  */
5617 #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK)
5618 #define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK (0x4000U)
5619 #define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT (14U)
5620 /*! GCLK_MODE_EN - GCLK_MODE_EN
5621  *  0b0..Disable
5622  *  0b1..Enable
5623  */
5624 #define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK)
5625 #define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK    (0x8000U)
5626 #define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT   (15U)
5627 /*! VALID_SEL - VALID_SEL
5628  */
5629 #define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL(x)      (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK)
5630 #define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK  (0x10000U)
5631 #define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT (16U)
5632 /*! RAW_OUT_SEL - RAW_OUT_SEL
5633  *  0b0..Right justified output
5634  *  0b1..Left justified to 14bit output
5635  */
5636 #define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL(x)    (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK)
5637 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK (0x20000U)
5638 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT (17U)
5639 /*! HSYNC_OUT_SEL - HSYNC_OUT_SEL
5640  *  0b0..HSYNC output level
5641  *  0b1..HSYNC output pulse
5642  */
5643 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK)
5644 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK  (0x380000U)
5645 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT (19U)
5646 /*! HSYNC_PULSE - HSYNC_PULSE
5647  */
5648 #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE(x)    (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK)
5649 #define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK   (0x400000U)
5650 #define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT  (22U)
5651 /*! UV_SWAP_EN - UV Swap enable
5652  *  0b0..UV swap disable
5653  *  0b1..UV swap enable
5654  */
5655 #define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN(x)     (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK)
5656 #define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK (0x7800000U)
5657 #define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT (23U)
5658 /*! DATA_TYPE_IN - CSI input data type
5659  *  0b0000..UYVY bt656 8bit
5660  *  0b0001..UYVY bt656 10bit
5661  *  0b0010..RGB 8bit
5662  *  0b0011..BGR 8bit
5663  *  0b0100..RGB 24bit
5664  *  0b0101..YVYU 8bit
5665  *  0b0110..YUV 8bit
5666  *  0b0111..YVYU 16bit
5667  *  0b1000..YUV 24bit
5668  *  0b1001..Bayer 8bit
5669  *  0b1010..Bayer 10bit
5670  *  0b1011..Bayer 12bit
5671  *  0b1100..Bayer 16bit
5672  */
5673 #define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK)
5674 #define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK (0x18000000U)
5675 #define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT (27U)
5676 /*! MASK_VSYNC_COUNTER - CSI mask VSYNC counter
5677  *  0b00..not mask
5678  *  0b01..mask 1 frame
5679  *  0b10..mask 2 frames
5680  *  0b11..mask 3 frames
5681  */
5682 #define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK)
5683 #define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK      (0x80000000U)
5684 #define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT     (31U)
5685 /*! SOFTRST - SOFTRST
5686  */
5687 #define CI_PI_CSR_CSI_CTRL_REG_SOFTRST(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK)
5688 /*! @} */
5689 
5690 /*! @name CSI_STATUS - CSI Interface Status Register */
5691 /*! @{ */
5692 #define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK   (0x1U)
5693 #define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT  (0U)
5694 #define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE(x)     (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT)) & CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK)
5695 #define CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK      (0x2U)
5696 #define CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT     (1U)
5697 #define CI_PI_CSR_CSI_STATUS_ECC_ERROR(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT)) & CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK)
5698 /*! @} */
5699 
5700 /*! @name CSI_CTRL_REG1 - CSI Interface Control Register1 */
5701 /*! @{ */
5702 #define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK (0xFFFFU)
5703 #define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT (0U)
5704 /*! PIXEL_WIDTH - CSI interface enable
5705  */
5706 #define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK)
5707 #define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK (0xFFFF0000U)
5708 #define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT (16U)
5709 /*! VSYNC_PULSE - VSYNC_PULSE
5710  */
5711 #define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK)
5712 /*! @} */
5713 
5714 
5715 /*!
5716  * @}
5717  */ /* end of group CI_PI_CSR_Register_Masks */
5718 
5719 
5720 /* CI_PI_CSR - Peripheral instance base addresses */
5721 /** Peripheral CI_PI_CSR base address */
5722 #define CI_PI_CSR_BASE                           (0x58261000u)
5723 /** Peripheral CI_PI_CSR base pointer */
5724 #define CI_PI_CSR                                ((CI_PI_CSR_Type *)CI_PI_CSR_BASE)
5725 /** Array initializer of CI_PI_CSR peripheral base addresses */
5726 #define CI_PI_CSR_BASE_ADDRS                     { CI_PI_CSR_BASE }
5727 /** Array initializer of CI_PI_CSR peripheral base pointers */
5728 #define CI_PI_CSR_BASE_PTRS                      { CI_PI_CSR }
5729 
5730 /*!
5731  * @}
5732  */ /* end of group CI_PI_CSR_Peripheral_Access_Layer */
5733 
5734 
5735 /* ----------------------------------------------------------------------------
5736    -- CM4_LPCG_LPI2C Peripheral Access Layer
5737    ---------------------------------------------------------------------------- */
5738 
5739 /*!
5740  * @addtogroup CM4_LPCG_LPI2C_Peripheral_Access_Layer CM4_LPCG_LPI2C Peripheral Access Layer
5741  * @{
5742  */
5743 
5744 /** CM4_LPCG_LPI2C - Register Layout Typedef */
5745 typedef struct {
5746   __IO uint32_t LPCG_LPI2C_0;                      /**< na, offset: 0x0 */
5747 } CM4_LPCG_LPI2C_Type;
5748 
5749 /* ----------------------------------------------------------------------------
5750    -- CM4_LPCG_LPI2C Register Masks
5751    ---------------------------------------------------------------------------- */
5752 
5753 /*!
5754  * @addtogroup CM4_LPCG_LPI2C_Register_Masks CM4_LPCG_LPI2C Register Masks
5755  * @{
5756  */
5757 
5758 /*! @name LPCG_LPI2C_0 - na */
5759 /*! @{ */
5760 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
5761 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
5762 /*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable
5763  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5764  *  0b1..Enable HW automatic gating
5765  */
5766 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK)
5767 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
5768 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
5769 /*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable
5770  *  0b0..Disable SW clock regardless of HWEN
5771  *  0b1..Enable SW clock gating
5772  */
5773 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
5774 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U)
5775 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U)
5776 /*! LPCG_LPI2C_0_reserved_2_2 - reserved
5777  */
5778 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK)
5779 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
5780 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
5781 /*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
5782  */
5783 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
5784 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U)
5785 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U)
5786 /*! LPCG_LPI2C_0_reserved_4_4 - reserved
5787  */
5788 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK)
5789 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U)
5790 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U)
5791 /*! lpi2c1_ipg_clk_SWEN - Software Enable
5792  *  0b0..Disable SW clock regardless of HWEN
5793  *  0b1..Enable SW clock gating
5794  */
5795 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK)
5796 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U)
5797 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U)
5798 /*! LPCG_LPI2C_0_reserved_6_6 - reserved
5799  */
5800 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK)
5801 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U)
5802 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U)
5803 /*! lpi2c1_ipg_clk_STOP - show clock root status, 1 means clock stopped
5804  */
5805 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK)
5806 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U)
5807 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U)
5808 /*! LPCG_LPI2C_0_reserved_8_31 - reserved
5809  */
5810 #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK)
5811 /*! @} */
5812 
5813 
5814 /*!
5815  * @}
5816  */ /* end of group CM4_LPCG_LPI2C_Register_Masks */
5817 
5818 
5819 /* CM4_LPCG_LPI2C - Peripheral instance base addresses */
5820 /** Peripheral CM4__LPCG_LPI2C base address */
5821 #define CM4__LPCG_LPI2C_BASE                     (0x41630000u)
5822 /** Peripheral CM4__LPCG_LPI2C base pointer */
5823 #define CM4__LPCG_LPI2C                          ((CM4_LPCG_LPI2C_Type *)CM4__LPCG_LPI2C_BASE)
5824 /** Array initializer of CM4_LPCG_LPI2C peripheral base addresses */
5825 #define CM4_LPCG_LPI2C_BASE_ADDRS                { CM4__LPCG_LPI2C_BASE }
5826 /** Array initializer of CM4_LPCG_LPI2C peripheral base pointers */
5827 #define CM4_LPCG_LPI2C_BASE_PTRS                 { CM4__LPCG_LPI2C }
5828 
5829 /*!
5830  * @}
5831  */ /* end of group CM4_LPCG_LPI2C_Peripheral_Access_Layer */
5832 
5833 
5834 /* ----------------------------------------------------------------------------
5835    -- CM4_LPCG_LPIT Peripheral Access Layer
5836    ---------------------------------------------------------------------------- */
5837 
5838 /*!
5839  * @addtogroup CM4_LPCG_LPIT_Peripheral_Access_Layer CM4_LPCG_LPIT Peripheral Access Layer
5840  * @{
5841  */
5842 
5843 /** CM4_LPCG_LPIT - Register Layout Typedef */
5844 typedef struct {
5845   __IO uint32_t LPCG_LPIT_0;                       /**< na, offset: 0x0 */
5846 } CM4_LPCG_LPIT_Type;
5847 
5848 /* ----------------------------------------------------------------------------
5849    -- CM4_LPCG_LPIT Register Masks
5850    ---------------------------------------------------------------------------- */
5851 
5852 /*!
5853  * @addtogroup CM4_LPCG_LPIT_Register_Masks CM4_LPCG_LPIT Register Masks
5854  * @{
5855  */
5856 
5857 /*! @name LPCG_LPIT_0 - na */
5858 /*! @{ */
5859 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U)
5860 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U)
5861 /*! lpit1_ipg_per_clk_HWEN - Hardware Enable
5862  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5863  *  0b1..Enable HW automatic gating
5864  */
5865 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK)
5866 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U)
5867 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U)
5868 /*! lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN - Software Enable
5869  *  0b0..Disable SW clock regardless of HWEN
5870  *  0b1..Enable SW clock gating
5871  */
5872 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK)
5873 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U)
5874 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U)
5875 /*! LPCG_LPIT_0_reserved_2_2 - reserved
5876  */
5877 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK)
5878 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U)
5879 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U)
5880 /*! lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP - show clock root status, 1 means clock stopped
5881  */
5882 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK)
5883 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U)
5884 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U)
5885 /*! LPCG_LPIT_0_reserved_4_4 - reserved
5886  */
5887 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK)
5888 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U)
5889 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U)
5890 /*! lpit1_ipg_clk_SWEN - Software Enable
5891  *  0b0..Disable SW clock regardless of HWEN
5892  *  0b1..Enable SW clock gating
5893  */
5894 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK)
5895 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U)
5896 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U)
5897 /*! LPCG_LPIT_0_reserved_6_6 - reserved
5898  */
5899 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK)
5900 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U)
5901 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U)
5902 /*! lpit1_ipg_clk_STOP - show clock root status, 1 means clock stopped
5903  */
5904 #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK)
5905 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U)
5906 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U)
5907 /*! LPCG_LPIT_0_reserved_8_31 - reserved
5908  */
5909 #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK)
5910 /*! @} */
5911 
5912 
5913 /*!
5914  * @}
5915  */ /* end of group CM4_LPCG_LPIT_Register_Masks */
5916 
5917 
5918 /* CM4_LPCG_LPIT - Peripheral instance base addresses */
5919 /** Peripheral CM4__LPCG_LPIT base address */
5920 #define CM4__LPCG_LPIT_BASE                      (0x41610000u)
5921 /** Peripheral CM4__LPCG_LPIT base pointer */
5922 #define CM4__LPCG_LPIT                           ((CM4_LPCG_LPIT_Type *)CM4__LPCG_LPIT_BASE)
5923 /** Array initializer of CM4_LPCG_LPIT peripheral base addresses */
5924 #define CM4_LPCG_LPIT_BASE_ADDRS                 { CM4__LPCG_LPIT_BASE }
5925 /** Array initializer of CM4_LPCG_LPIT peripheral base pointers */
5926 #define CM4_LPCG_LPIT_BASE_PTRS                  { CM4__LPCG_LPIT }
5927 
5928 /*!
5929  * @}
5930  */ /* end of group CM4_LPCG_LPIT_Peripheral_Access_Layer */
5931 
5932 
5933 /* ----------------------------------------------------------------------------
5934    -- CM4_LPCG_LPUART Peripheral Access Layer
5935    ---------------------------------------------------------------------------- */
5936 
5937 /*!
5938  * @addtogroup CM4_LPCG_LPUART_Peripheral_Access_Layer CM4_LPCG_LPUART Peripheral Access Layer
5939  * @{
5940  */
5941 
5942 /** CM4_LPCG_LPUART - Register Layout Typedef */
5943 typedef struct {
5944   __IO uint32_t LPCG_LPUART_0;                     /**< na, offset: 0x0 */
5945 } CM4_LPCG_LPUART_Type;
5946 
5947 /* ----------------------------------------------------------------------------
5948    -- CM4_LPCG_LPUART Register Masks
5949    ---------------------------------------------------------------------------- */
5950 
5951 /*!
5952  * @addtogroup CM4_LPCG_LPUART_Register_Masks CM4_LPCG_LPUART Register Masks
5953  * @{
5954  */
5955 
5956 /*! @name LPCG_LPUART_0 - na */
5957 /*! @{ */
5958 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
5959 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
5960 /*! lpuart1_lpuart_baud_gated_clk_HWEN - Hardware Enable
5961  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5962  *  0b1..Enable HW automatic gating
5963  */
5964 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK)
5965 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
5966 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
5967 /*! lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN - Software Enable
5968  *  0b0..Disable SW clock regardless of HWEN
5969  *  0b1..Enable SW clock gating
5970  */
5971 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK)
5972 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U)
5973 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U)
5974 /*! LPCG_LPUART_0_reserved_2_2 - reserved
5975  */
5976 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK)
5977 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
5978 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
5979 /*! lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
5980  */
5981 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK)
5982 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U)
5983 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U)
5984 /*! LPCG_LPUART_0_reserved_4_4 - reserved
5985  */
5986 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK)
5987 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U)
5988 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U)
5989 /*! lpuart1_ipg_clk_SWEN - Software Enable
5990  *  0b0..Disable SW clock regardless of HWEN
5991  *  0b1..Enable SW clock gating
5992  */
5993 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK)
5994 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U)
5995 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U)
5996 /*! LPCG_LPUART_0_reserved_6_6 - reserved
5997  */
5998 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK)
5999 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U)
6000 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U)
6001 /*! lpuart1_ipg_clk_STOP - show clock root status, 1 means clock stopped
6002  */
6003 #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK)
6004 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U)
6005 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U)
6006 /*! LPCG_LPUART_0_reserved_8_31 - reserved
6007  */
6008 #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK)
6009 /*! @} */
6010 
6011 
6012 /*!
6013  * @}
6014  */ /* end of group CM4_LPCG_LPUART_Register_Masks */
6015 
6016 
6017 /* CM4_LPCG_LPUART - Peripheral instance base addresses */
6018 /** Peripheral CM4__LPCG_LPUART base address */
6019 #define CM4__LPCG_LPUART_BASE                    (0x41620000u)
6020 /** Peripheral CM4__LPCG_LPUART base pointer */
6021 #define CM4__LPCG_LPUART                         ((CM4_LPCG_LPUART_Type *)CM4__LPCG_LPUART_BASE)
6022 /** Array initializer of CM4_LPCG_LPUART peripheral base addresses */
6023 #define CM4_LPCG_LPUART_BASE_ADDRS               { CM4__LPCG_LPUART_BASE }
6024 /** Array initializer of CM4_LPCG_LPUART peripheral base pointers */
6025 #define CM4_LPCG_LPUART_BASE_PTRS                { CM4__LPCG_LPUART }
6026 
6027 /*!
6028  * @}
6029  */ /* end of group CM4_LPCG_LPUART_Peripheral_Access_Layer */
6030 
6031 
6032 /* ----------------------------------------------------------------------------
6033    -- CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
6034    ---------------------------------------------------------------------------- */
6035 
6036 /*!
6037  * @addtogroup CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
6038  * @{
6039  */
6040 
6041 /** CM4_LPCG_MMCAU_HCLK - Register Layout Typedef */
6042 typedef struct {
6043   __IO uint32_t LPCG_MMCAU_HCLK_0;                 /**< na, offset: 0x0 */
6044 } CM4_LPCG_MMCAU_HCLK_Type;
6045 
6046 /* ----------------------------------------------------------------------------
6047    -- CM4_LPCG_MMCAU_HCLK Register Masks
6048    ---------------------------------------------------------------------------- */
6049 
6050 /*!
6051  * @addtogroup CM4_LPCG_MMCAU_HCLK_Register_Masks CM4_LPCG_MMCAU_HCLK Register Masks
6052  * @{
6053  */
6054 
6055 /*! @name LPCG_MMCAU_HCLK_0 - na */
6056 /*! @{ */
6057 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U)
6058 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U)
6059 /*! LPCG_MMCAU_HCLK_0_reserved_0_0 - reserved
6060  */
6061 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK)
6062 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U)
6063 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U)
6064 /*! cm4_mmcau_hclk_SWEN - Software Enable
6065  *  0b0..Disable SW clock regardless of HWEN
6066  *  0b1..Enable SW clock gating
6067  */
6068 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK)
6069 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U)
6070 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U)
6071 /*! LPCG_MMCAU_HCLK_0_reserved_2_2 - reserved
6072  */
6073 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK)
6074 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U)
6075 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U)
6076 /*! cm4_mmcau_hclk_STOP - show clock root status, 1 means clock stopped
6077  */
6078 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK)
6079 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
6080 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U)
6081 /*! LPCG_MMCAU_HCLK_0_reserved_4_31 - reserved
6082  */
6083 #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK)
6084 /*! @} */
6085 
6086 
6087 /*!
6088  * @}
6089  */ /* end of group CM4_LPCG_MMCAU_HCLK_Register_Masks */
6090 
6091 
6092 /* CM4_LPCG_MMCAU_HCLK - Peripheral instance base addresses */
6093 /** Peripheral CM4__LPCG_MMCAU_HCLK base address */
6094 #define CM4__LPCG_MMCAU_HCLK_BASE                (0x415F0000u)
6095 /** Peripheral CM4__LPCG_MMCAU_HCLK base pointer */
6096 #define CM4__LPCG_MMCAU_HCLK                     ((CM4_LPCG_MMCAU_HCLK_Type *)CM4__LPCG_MMCAU_HCLK_BASE)
6097 /** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base addresses */
6098 #define CM4_LPCG_MMCAU_HCLK_BASE_ADDRS           { CM4__LPCG_MMCAU_HCLK_BASE }
6099 /** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base pointers */
6100 #define CM4_LPCG_MMCAU_HCLK_BASE_PTRS            { CM4__LPCG_MMCAU_HCLK }
6101 
6102 /*!
6103  * @}
6104  */ /* end of group CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer */
6105 
6106 
6107 /* ----------------------------------------------------------------------------
6108    -- CM4_LPCG_TCMC_HCLK Peripheral Access Layer
6109    ---------------------------------------------------------------------------- */
6110 
6111 /*!
6112  * @addtogroup CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer CM4_LPCG_TCMC_HCLK Peripheral Access Layer
6113  * @{
6114  */
6115 
6116 /** CM4_LPCG_TCMC_HCLK - Register Layout Typedef */
6117 typedef struct {
6118   __IO uint32_t LPCG_TCMC_HCLK_0;                  /**< na, offset: 0x0 */
6119 } CM4_LPCG_TCMC_HCLK_Type;
6120 
6121 /* ----------------------------------------------------------------------------
6122    -- CM4_LPCG_TCMC_HCLK Register Masks
6123    ---------------------------------------------------------------------------- */
6124 
6125 /*!
6126  * @addtogroup CM4_LPCG_TCMC_HCLK_Register_Masks CM4_LPCG_TCMC_HCLK Register Masks
6127  * @{
6128  */
6129 
6130 /*! @name LPCG_TCMC_HCLK_0 - na */
6131 /*! @{ */
6132 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U)
6133 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U)
6134 /*! cm4_tcmc_hclk_HWEN - Hardware Enable
6135  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6136  *  0b1..Enable HW automatic gating
6137  */
6138 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK)
6139 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U)
6140 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U)
6141 /*! cm4_tcmc_hclk_SWEN - Software Enable
6142  *  0b0..Disable SW clock regardless of HWEN
6143  *  0b1..Enable SW clock gating
6144  */
6145 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK)
6146 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U)
6147 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U)
6148 /*! LPCG_TCMC_HCLK_0_reserved_2_2 - reserved
6149  */
6150 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK)
6151 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U)
6152 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U)
6153 /*! cm4_tcmc_hclk_STOP - show clock root status, 1 means clock stopped
6154  */
6155 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK)
6156 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
6157 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U)
6158 /*! LPCG_TCMC_HCLK_0_reserved_4_31 - reserved
6159  */
6160 #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK)
6161 /*! @} */
6162 
6163 
6164 /*!
6165  * @}
6166  */ /* end of group CM4_LPCG_TCMC_HCLK_Register_Masks */
6167 
6168 
6169 /* CM4_LPCG_TCMC_HCLK - Peripheral instance base addresses */
6170 /** Peripheral CM4__LPCG_TCMC_HCLK base address */
6171 #define CM4__LPCG_TCMC_HCLK_BASE                 (0x415E0000u)
6172 /** Peripheral CM4__LPCG_TCMC_HCLK base pointer */
6173 #define CM4__LPCG_TCMC_HCLK                      ((CM4_LPCG_TCMC_HCLK_Type *)CM4__LPCG_TCMC_HCLK_BASE)
6174 /** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base addresses */
6175 #define CM4_LPCG_TCMC_HCLK_BASE_ADDRS            { CM4__LPCG_TCMC_HCLK_BASE }
6176 /** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base pointers */
6177 #define CM4_LPCG_TCMC_HCLK_BASE_PTRS             { CM4__LPCG_TCMC_HCLK }
6178 
6179 /*!
6180  * @}
6181  */ /* end of group CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer */
6182 
6183 
6184 /* ----------------------------------------------------------------------------
6185    -- CM4_LPCG_TPM Peripheral Access Layer
6186    ---------------------------------------------------------------------------- */
6187 
6188 /*!
6189  * @addtogroup CM4_LPCG_TPM_Peripheral_Access_Layer CM4_LPCG_TPM Peripheral Access Layer
6190  * @{
6191  */
6192 
6193 /** CM4_LPCG_TPM - Register Layout Typedef */
6194 typedef struct {
6195   __IO uint32_t LPCG_TPM_0;                        /**< na, offset: 0x0 */
6196 } CM4_LPCG_TPM_Type;
6197 
6198 /* ----------------------------------------------------------------------------
6199    -- CM4_LPCG_TPM Register Masks
6200    ---------------------------------------------------------------------------- */
6201 
6202 /*!
6203  * @addtogroup CM4_LPCG_TPM_Register_Masks CM4_LPCG_TPM Register Masks
6204  * @{
6205  */
6206 
6207 /*! @name LPCG_TPM_0 - na */
6208 /*! @{ */
6209 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U)
6210 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U)
6211 /*! LPCG_TPM_0_reserved_0_0 - reserved
6212  */
6213 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK)
6214 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U)
6215 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U)
6216 /*! tpm1_lptpm_clk_SWEN - Software Enable
6217  *  0b0..Disable SW clock regardless of HWEN
6218  *  0b1..Enable SW clock gating
6219  */
6220 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK)
6221 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U)
6222 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U)
6223 /*! LPCG_TPM_0_reserved_2_2 - reserved
6224  */
6225 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK)
6226 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U)
6227 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U)
6228 /*! tpm1_lptpm_clk_STOP - show clock root status, 1 means clock stopped
6229  */
6230 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK)
6231 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U)
6232 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U)
6233 /*! LPCG_TPM_0_reserved_4_4 - reserved
6234  */
6235 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK)
6236 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U)
6237 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U)
6238 /*! tpm1_ipg_clk_SWEN - Software Enable
6239  *  0b0..Disable SW clock regardless of HWEN
6240  *  0b1..Enable SW clock gating
6241  */
6242 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK)
6243 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U)
6244 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U)
6245 /*! LPCG_TPM_0_reserved_6_6 - reserved
6246  */
6247 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK)
6248 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U)
6249 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U)
6250 /*! tpm1_ipg_clk_STOP - show clock root status, 1 means clock stopped
6251  */
6252 #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK)
6253 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U)
6254 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U)
6255 /*! LPCG_TPM_0_reserved_8_31 - reserved
6256  */
6257 #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK)
6258 /*! @} */
6259 
6260 
6261 /*!
6262  * @}
6263  */ /* end of group CM4_LPCG_TPM_Register_Masks */
6264 
6265 
6266 /* CM4_LPCG_TPM - Peripheral instance base addresses */
6267 /** Peripheral CM4__LPCG_TPM base address */
6268 #define CM4__LPCG_TPM_BASE                       (0x41600000u)
6269 /** Peripheral CM4__LPCG_TPM base pointer */
6270 #define CM4__LPCG_TPM                            ((CM4_LPCG_TPM_Type *)CM4__LPCG_TPM_BASE)
6271 /** Array initializer of CM4_LPCG_TPM peripheral base addresses */
6272 #define CM4_LPCG_TPM_BASE_ADDRS                  { CM4__LPCG_TPM_BASE }
6273 /** Array initializer of CM4_LPCG_TPM peripheral base pointers */
6274 #define CM4_LPCG_TPM_BASE_PTRS                   { CM4__LPCG_TPM }
6275 
6276 /*!
6277  * @}
6278  */ /* end of group CM4_LPCG_TPM_Peripheral_Access_Layer */
6279 
6280 
6281 /* ----------------------------------------------------------------------------
6282    -- CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
6283    ---------------------------------------------------------------------------- */
6284 
6285 /*!
6286  * @addtogroup CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
6287  * @{
6288  */
6289 
6290 /** CONNECTIVITY_LPCG_EDMA - Register Layout Typedef */
6291 typedef struct {
6292   __IO uint32_t LPCG_LPCG_EDMA_0;                  /**< na, offset: 0x0 */
6293 } CONNECTIVITY_LPCG_EDMA_Type;
6294 
6295 /* ----------------------------------------------------------------------------
6296    -- CONNECTIVITY_LPCG_EDMA Register Masks
6297    ---------------------------------------------------------------------------- */
6298 
6299 /*!
6300  * @addtogroup CONNECTIVITY_LPCG_EDMA_Register_Masks CONNECTIVITY_LPCG_EDMA Register Masks
6301  * @{
6302  */
6303 
6304 /*! @name LPCG_LPCG_EDMA_0 - na */
6305 /*! @{ */
6306 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK (0x1U)
6307 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT (0U)
6308 /*! edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN - Hardware Enable
6309  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6310  *  0b1..Enable HW automatic gating
6311  */
6312 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK)
6313 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK (0x2U)
6314 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT (1U)
6315 /*! edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN - Software Enable
6316  *  0b0..Disable SW clock regardless of HWEN
6317  *  0b1..Enable SW clock gating
6318  */
6319 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK)
6320 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK (0x4U)
6321 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT (2U)
6322 /*! LPCG_lpcg_edma_0_reserved_2_2 - reserved
6323  */
6324 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK)
6325 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK (0x8U)
6326 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT (3U)
6327 /*! edma_hclk_STOP_AND_edma_mem_dma_clk_STOP - show clock root status, 1 means clock stopped
6328  */
6329 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK)
6330 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK (0x1FFF0U)
6331 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT (4U)
6332 /*! LPCG_lpcg_edma_0_reserved_4_16 - reserved
6333  */
6334 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK)
6335 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK (0x20000U)
6336 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT (17U)
6337 /*! edma_ipg_clk_SWEN - Software Enable
6338  *  0b0..Disable SW clock regardless of HWEN
6339  *  0b1..Enable SW clock gating
6340  */
6341 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK)
6342 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK (0x40000U)
6343 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT (18U)
6344 /*! LPCG_lpcg_edma_0_reserved_18_18 - reserved
6345  */
6346 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK)
6347 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK (0x80000U)
6348 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT (19U)
6349 /*! edma_ipg_clk_STOP - show clock root status, 1 means clock stopped
6350  */
6351 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK)
6352 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK (0xFFF00000U)
6353 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT (20U)
6354 /*! LPCG_lpcg_edma_0_reserved_20_31 - reserved
6355  */
6356 #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK)
6357 /*! @} */
6358 
6359 
6360 /*!
6361  * @}
6362  */ /* end of group CONNECTIVITY_LPCG_EDMA_Register_Masks */
6363 
6364 
6365 /* CONNECTIVITY_LPCG_EDMA - Peripheral instance base addresses */
6366 /** Peripheral CONNECTIVITY__LPCG_EDMA base address */
6367 #define CONNECTIVITY__LPCG_EDMA_BASE             (0x5B2A0000u)
6368 /** Peripheral CONNECTIVITY__LPCG_EDMA base pointer */
6369 #define CONNECTIVITY__LPCG_EDMA                  ((CONNECTIVITY_LPCG_EDMA_Type *)CONNECTIVITY__LPCG_EDMA_BASE)
6370 /** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base addresses */
6371 #define CONNECTIVITY_LPCG_EDMA_BASE_ADDRS        { CONNECTIVITY__LPCG_EDMA_BASE }
6372 /** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base pointers */
6373 #define CONNECTIVITY_LPCG_EDMA_BASE_PTRS         { CONNECTIVITY__LPCG_EDMA }
6374 
6375 /*!
6376  * @}
6377  */ /* end of group CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer */
6378 
6379 
6380 /* ----------------------------------------------------------------------------
6381    -- CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
6382    ---------------------------------------------------------------------------- */
6383 
6384 /*!
6385  * @addtogroup CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
6386  * @{
6387  */
6388 
6389 /** CONNECTIVITY_LPCG_ENET0 - Register Layout Typedef */
6390 typedef struct {
6391   __IO uint32_t LPCG_LPCG_ENET1_0;                 /**< na, offset: 0x0 */
6392   __IO uint32_t LPCG_LPCG_ENET1_4;                 /**< na, offset: 0x4 */
6393 } CONNECTIVITY_LPCG_ENET0_Type;
6394 
6395 /* ----------------------------------------------------------------------------
6396    -- CONNECTIVITY_LPCG_ENET0 Register Masks
6397    ---------------------------------------------------------------------------- */
6398 
6399 /*!
6400  * @addtogroup CONNECTIVITY_LPCG_ENET0_Register_Masks CONNECTIVITY_LPCG_ENET0 Register Masks
6401  * @{
6402  */
6403 
6404 /*! @name LPCG_LPCG_ENET1_0 - na */
6405 /*! @{ */
6406 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK (0x1U)
6407 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT (0U)
6408 /*! enet1_ipg_clk_time_HWEN - Hardware Enable
6409  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6410  *  0b1..Enable HW automatic gating
6411  */
6412 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK)
6413 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK (0x2U)
6414 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT (1U)
6415 /*! enet1_ipg_clk_time_SWEN - Software Enable
6416  *  0b0..Disable SW clock regardless of HWEN
6417  *  0b1..Enable SW clock gating
6418  */
6419 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK)
6420 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK (0x4U)
6421 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT (2U)
6422 /*! LPCG_lpcg_enet1_0_reserved_2_2 - reserved
6423  */
6424 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK)
6425 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK (0x8U)
6426 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT (3U)
6427 /*! enet1_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
6428  */
6429 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK)
6430 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK (0x10U)
6431 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT (4U)
6432 /*! LPCG_lpcg_enet1_0_reserved_4_4 - reserved
6433  */
6434 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK)
6435 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK (0x20U)
6436 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT (5U)
6437 /*! enet1_2x_txclk_SWEN - Software Enable
6438  *  0b0..Disable SW clock regardless of HWEN
6439  *  0b1..Enable SW clock gating
6440  */
6441 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK)
6442 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK (0x40U)
6443 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT (6U)
6444 /*! LPCG_lpcg_enet1_0_reserved_6_6 - reserved
6445  */
6446 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK)
6447 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK (0x80U)
6448 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT (7U)
6449 /*! enet1_2x_txclk_STOP - show clock root status, 1 means clock stopped
6450  */
6451 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK)
6452 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK (0x100U)
6453 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT (8U)
6454 /*! LPCG_lpcg_enet1_0_reserved_8_8 - reserved
6455  */
6456 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK)
6457 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK (0x200U)
6458 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT (9U)
6459 /*! enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN - Software Enable
6460  *  0b0..Disable SW clock regardless of HWEN
6461  *  0b1..Enable SW clock gating
6462  */
6463 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK)
6464 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK (0x400U)
6465 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT (10U)
6466 /*! LPCG_lpcg_enet1_0_reserved_10_10 - reserved
6467  */
6468 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK)
6469 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK (0x800U)
6470 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT (11U)
6471 /*! enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
6472  */
6473 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK)
6474 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK (0x1000U)
6475 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT (12U)
6476 /*! LPCG_lpcg_enet1_0_reserved_12_12 - reserved
6477  */
6478 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK)
6479 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK (0x2000U)
6480 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT (13U)
6481 /*! enet1_clkdiv_clk_in_SWEN - Software Enable
6482  *  0b0..Disable SW clock regardless of HWEN
6483  *  0b1..Enable SW clock gating
6484  */
6485 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK)
6486 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK (0x4000U)
6487 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT (14U)
6488 /*! LPCG_lpcg_enet1_0_reserved_14_14 - reserved
6489  */
6490 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK)
6491 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK (0x8000U)
6492 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT (15U)
6493 /*! enet1_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
6494  */
6495 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK)
6496 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK (0x10000U)
6497 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT (16U)
6498 /*! enet1_ipg_clk_mac0_HWEN - Hardware Enable
6499  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6500  *  0b1..Enable HW automatic gating
6501  */
6502 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK)
6503 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK (0x20000U)
6504 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT (17U)
6505 /*! enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN - Software Enable
6506  *  0b0..Disable SW clock regardless of HWEN
6507  *  0b1..Enable SW clock gating
6508  */
6509 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK)
6510 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK (0x40000U)
6511 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT (18U)
6512 /*! LPCG_lpcg_enet1_0_reserved_18_18 - reserved
6513  */
6514 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK)
6515 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK (0x80000U)
6516 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT (19U)
6517 /*! enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
6518  */
6519 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK)
6520 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK (0x100000U)
6521 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT (20U)
6522 /*! enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN - Hardware Enable
6523  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6524  *  0b1..Enable HW automatic gating
6525  */
6526 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK)
6527 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK (0x200000U)
6528 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT (21U)
6529 /*! enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN - Software Enable
6530  *  0b0..Disable SW clock regardless of HWEN
6531  *  0b1..Enable SW clock gating
6532  */
6533 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK)
6534 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK (0x400000U)
6535 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT (22U)
6536 /*! LPCG_lpcg_enet1_0_reserved_22_22 - reserved
6537  */
6538 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK)
6539 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK (0x800000U)
6540 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT (23U)
6541 /*! enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6542  */
6543 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK)
6544 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK (0xFF000000U)
6545 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT (24U)
6546 /*! LPCG_lpcg_enet1_0_reserved_24_31 - reserved
6547  */
6548 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK)
6549 /*! @} */
6550 
6551 /*! @name LPCG_LPCG_ENET1_4 - na */
6552 /*! @{ */
6553 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK (0x1U)
6554 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT (0U)
6555 /*! LPCG_lpcg_enet1_4_reserved_0_0 - reserved
6556  */
6557 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK)
6558 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK (0x2U)
6559 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT (1U)
6560 /*! enet1_mac0_rxclk_SWEN - Software Enable
6561  *  0b0..Disable SW clock regardless of HWEN
6562  *  0b1..Enable SW clock gating
6563  */
6564 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK)
6565 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK (0x4U)
6566 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT (2U)
6567 /*! LPCG_lpcg_enet1_4_reserved_2_2 - reserved
6568  */
6569 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK)
6570 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK (0x8U)
6571 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT (3U)
6572 /*! enet1_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
6573  */
6574 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK)
6575 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK (0xFFFFFFF0U)
6576 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT (4U)
6577 /*! LPCG_lpcg_enet1_4_reserved_4_31 - reserved
6578  */
6579 #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK)
6580 /*! @} */
6581 
6582 
6583 /*!
6584  * @}
6585  */ /* end of group CONNECTIVITY_LPCG_ENET0_Register_Masks */
6586 
6587 
6588 /* CONNECTIVITY_LPCG_ENET0 - Peripheral instance base addresses */
6589 /** Peripheral CONNECTIVITY__LPCG_ENET0 base address */
6590 #define CONNECTIVITY__LPCG_ENET0_BASE            (0x5B230000u)
6591 /** Peripheral CONNECTIVITY__LPCG_ENET0 base pointer */
6592 #define CONNECTIVITY__LPCG_ENET0                 ((CONNECTIVITY_LPCG_ENET0_Type *)CONNECTIVITY__LPCG_ENET0_BASE)
6593 /** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base addresses */
6594 #define CONNECTIVITY_LPCG_ENET0_BASE_ADDRS       { CONNECTIVITY__LPCG_ENET0_BASE }
6595 /** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base pointers */
6596 #define CONNECTIVITY_LPCG_ENET0_BASE_PTRS        { CONNECTIVITY__LPCG_ENET0 }
6597 
6598 /*!
6599  * @}
6600  */ /* end of group CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer */
6601 
6602 
6603 /* ----------------------------------------------------------------------------
6604    -- CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
6605    ---------------------------------------------------------------------------- */
6606 
6607 /*!
6608  * @addtogroup CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
6609  * @{
6610  */
6611 
6612 /** CONNECTIVITY_LPCG_ENET1 - Register Layout Typedef */
6613 typedef struct {
6614   __IO uint32_t LPCG_LPCG_ENET2_0;                 /**< na, offset: 0x0 */
6615   __IO uint32_t LPCG_LPCG_ENET2_4;                 /**< na, offset: 0x4 */
6616 } CONNECTIVITY_LPCG_ENET1_Type;
6617 
6618 /* ----------------------------------------------------------------------------
6619    -- CONNECTIVITY_LPCG_ENET1 Register Masks
6620    ---------------------------------------------------------------------------- */
6621 
6622 /*!
6623  * @addtogroup CONNECTIVITY_LPCG_ENET1_Register_Masks CONNECTIVITY_LPCG_ENET1 Register Masks
6624  * @{
6625  */
6626 
6627 /*! @name LPCG_LPCG_ENET2_0 - na */
6628 /*! @{ */
6629 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK (0x1U)
6630 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT (0U)
6631 /*! enet2_ipg_clk_time_HWEN - Hardware Enable
6632  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6633  *  0b1..Enable HW automatic gating
6634  */
6635 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK)
6636 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK (0x2U)
6637 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT (1U)
6638 /*! enet2_ipg_clk_time_SWEN - Software Enable
6639  *  0b0..Disable SW clock regardless of HWEN
6640  *  0b1..Enable SW clock gating
6641  */
6642 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK)
6643 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK (0x4U)
6644 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT (2U)
6645 /*! LPCG_lpcg_enet2_0_reserved_2_2 - reserved
6646  */
6647 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK)
6648 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK (0x8U)
6649 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT (3U)
6650 /*! enet2_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
6651  */
6652 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK)
6653 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK (0x10U)
6654 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT (4U)
6655 /*! LPCG_lpcg_enet2_0_reserved_4_4 - reserved
6656  */
6657 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK)
6658 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK (0x20U)
6659 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT (5U)
6660 /*! enet2_2x_txclk_SWEN - Software Enable
6661  *  0b0..Disable SW clock regardless of HWEN
6662  *  0b1..Enable SW clock gating
6663  */
6664 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK)
6665 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK (0x40U)
6666 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT (6U)
6667 /*! LPCG_lpcg_enet2_0_reserved_6_6 - reserved
6668  */
6669 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK)
6670 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK (0x80U)
6671 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT (7U)
6672 /*! enet2_2x_txclk_STOP - show clock root status, 1 means clock stopped
6673  */
6674 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK)
6675 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK (0x100U)
6676 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT (8U)
6677 /*! LPCG_lpcg_enet2_0_reserved_8_8 - reserved
6678  */
6679 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK)
6680 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK (0x200U)
6681 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT (9U)
6682 /*! enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN - Software Enable
6683  *  0b0..Disable SW clock regardless of HWEN
6684  *  0b1..Enable SW clock gating
6685  */
6686 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK)
6687 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK (0x400U)
6688 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT (10U)
6689 /*! LPCG_lpcg_enet2_0_reserved_10_10 - reserved
6690  */
6691 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK)
6692 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK (0x800U)
6693 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT (11U)
6694 /*! enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
6695  */
6696 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK)
6697 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK (0x1000U)
6698 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT (12U)
6699 /*! LPCG_lpcg_enet2_0_reserved_12_12 - reserved
6700  */
6701 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK)
6702 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK (0x2000U)
6703 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT (13U)
6704 /*! enet2_clkdiv_clk_in_SWEN - Software Enable
6705  *  0b0..Disable SW clock regardless of HWEN
6706  *  0b1..Enable SW clock gating
6707  */
6708 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK)
6709 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK (0x4000U)
6710 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT (14U)
6711 /*! LPCG_lpcg_enet2_0_reserved_14_14 - reserved
6712  */
6713 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK)
6714 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK (0x8000U)
6715 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT (15U)
6716 /*! enet2_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
6717  */
6718 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK)
6719 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK (0x10000U)
6720 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT (16U)
6721 /*! enet2_ipg_clk_mac0_HWEN - Hardware Enable
6722  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6723  *  0b1..Enable HW automatic gating
6724  */
6725 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK)
6726 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK (0x20000U)
6727 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT (17U)
6728 /*! enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN - Software Enable
6729  *  0b0..Disable SW clock regardless of HWEN
6730  *  0b1..Enable SW clock gating
6731  */
6732 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK)
6733 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK (0x40000U)
6734 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT (18U)
6735 /*! LPCG_lpcg_enet2_0_reserved_18_18 - reserved
6736  */
6737 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK)
6738 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK (0x80000U)
6739 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT (19U)
6740 /*! enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
6741  */
6742 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK)
6743 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK (0x100000U)
6744 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT (20U)
6745 /*! enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN - Hardware Enable
6746  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6747  *  0b1..Enable HW automatic gating
6748  */
6749 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK)
6750 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK (0x200000U)
6751 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT (21U)
6752 /*! enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN - Software Enable
6753  *  0b0..Disable SW clock regardless of HWEN
6754  *  0b1..Enable SW clock gating
6755  */
6756 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK)
6757 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK (0x400000U)
6758 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT (22U)
6759 /*! LPCG_lpcg_enet2_0_reserved_22_22 - reserved
6760  */
6761 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK)
6762 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK (0x800000U)
6763 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT (23U)
6764 /*! enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6765  */
6766 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK)
6767 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK (0xFF000000U)
6768 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT (24U)
6769 /*! LPCG_lpcg_enet2_0_reserved_24_31 - reserved
6770  */
6771 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK)
6772 /*! @} */
6773 
6774 /*! @name LPCG_LPCG_ENET2_4 - na */
6775 /*! @{ */
6776 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK (0x1U)
6777 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT (0U)
6778 /*! LPCG_lpcg_enet2_4_reserved_0_0 - reserved
6779  */
6780 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK)
6781 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK (0x2U)
6782 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT (1U)
6783 /*! enet2_mac0_rxclk_SWEN - Software Enable
6784  *  0b0..Disable SW clock regardless of HWEN
6785  *  0b1..Enable SW clock gating
6786  */
6787 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK)
6788 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK (0x4U)
6789 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT (2U)
6790 /*! LPCG_lpcg_enet2_4_reserved_2_2 - reserved
6791  */
6792 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK)
6793 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK (0x8U)
6794 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT (3U)
6795 /*! enet2_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
6796  */
6797 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK)
6798 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK (0xFFFFFFF0U)
6799 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT (4U)
6800 /*! LPCG_lpcg_enet2_4_reserved_4_31 - reserved
6801  */
6802 #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK)
6803 /*! @} */
6804 
6805 
6806 /*!
6807  * @}
6808  */ /* end of group CONNECTIVITY_LPCG_ENET1_Register_Masks */
6809 
6810 
6811 /* CONNECTIVITY_LPCG_ENET1 - Peripheral instance base addresses */
6812 /** Peripheral CONNECTIVITY__LPCG_ENET1 base address */
6813 #define CONNECTIVITY__LPCG_ENET1_BASE            (0x5B240000u)
6814 /** Peripheral CONNECTIVITY__LPCG_ENET1 base pointer */
6815 #define CONNECTIVITY__LPCG_ENET1                 ((CONNECTIVITY_LPCG_ENET1_Type *)CONNECTIVITY__LPCG_ENET1_BASE)
6816 /** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base addresses */
6817 #define CONNECTIVITY_LPCG_ENET1_BASE_ADDRS       { CONNECTIVITY__LPCG_ENET1_BASE }
6818 /** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base pointers */
6819 #define CONNECTIVITY_LPCG_ENET1_BASE_PTRS        { CONNECTIVITY__LPCG_ENET1 }
6820 
6821 /*!
6822  * @}
6823  */ /* end of group CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer */
6824 
6825 
6826 /* ----------------------------------------------------------------------------
6827    -- CONNECTIVITY_LPCG_MLB Peripheral Access Layer
6828    ---------------------------------------------------------------------------- */
6829 
6830 /*!
6831  * @addtogroup CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer CONNECTIVITY_LPCG_MLB Peripheral Access Layer
6832  * @{
6833  */
6834 
6835 /** CONNECTIVITY_LPCG_MLB - Register Layout Typedef */
6836 typedef struct {
6837   __IO uint32_t LPCG_LPCG_MLB_0;                   /**< na, offset: 0x0 */
6838 } CONNECTIVITY_LPCG_MLB_Type;
6839 
6840 /* ----------------------------------------------------------------------------
6841    -- CONNECTIVITY_LPCG_MLB Register Masks
6842    ---------------------------------------------------------------------------- */
6843 
6844 /*!
6845  * @addtogroup CONNECTIVITY_LPCG_MLB_Register_Masks CONNECTIVITY_LPCG_MLB Register Masks
6846  * @{
6847  */
6848 
6849 /*! @name LPCG_LPCG_MLB_0 - na */
6850 /*! @{ */
6851 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK (0x1U)
6852 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT (0U)
6853 /*! LPCG_lpcg_mlb_0_reserved_0_0 - reserved
6854  */
6855 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK)
6856 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK (0x2U)
6857 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT (1U)
6858 /*! mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN - Software Enable
6859  *  0b0..Disable SW clock regardless of HWEN
6860  *  0b1..Enable SW clock gating
6861  */
6862 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK)
6863 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK (0x4U)
6864 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT (2U)
6865 /*! LPCG_lpcg_mlb_0_reserved_2_2 - reserved
6866  */
6867 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK)
6868 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK (0x8U)
6869 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT (3U)
6870 /*! mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP - show clock root status, 1 means clock stopped
6871  */
6872 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK)
6873 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK (0xFFF0U)
6874 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT (4U)
6875 /*! LPCG_lpcg_mlb_0_reserved_4_15 - reserved
6876  */
6877 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK)
6878 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK (0x10000U)
6879 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT (16U)
6880 /*! mlb_ipg_clk_s_HWEN - Hardware Enable
6881  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6882  *  0b1..Enable HW automatic gating
6883  */
6884 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK)
6885 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK (0x20000U)
6886 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT (17U)
6887 /*! mlb_ipg_clk_s_SWEN - Software Enable
6888  *  0b0..Disable SW clock regardless of HWEN
6889  *  0b1..Enable SW clock gating
6890  */
6891 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK)
6892 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK (0x40000U)
6893 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT (18U)
6894 /*! LPCG_lpcg_mlb_0_reserved_18_18 - reserved
6895  */
6896 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK)
6897 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK (0x80000U)
6898 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT (19U)
6899 /*! mlb_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6900  */
6901 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK)
6902 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK (0x100000U)
6903 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT (20U)
6904 /*! LPCG_lpcg_mlb_0_reserved_20_20 - reserved
6905  */
6906 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK)
6907 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK (0x200000U)
6908 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT (21U)
6909 /*! mlb_hclk_SWEN - Software Enable
6910  *  0b0..Disable SW clock regardless of HWEN
6911  *  0b1..Enable SW clock gating
6912  */
6913 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK)
6914 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK (0x400000U)
6915 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT (22U)
6916 /*! LPCG_lpcg_mlb_0_reserved_22_22 - reserved
6917  */
6918 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK)
6919 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK (0x800000U)
6920 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT (23U)
6921 /*! mlb_hclk_STOP - show clock root status, 1 means clock stopped
6922  */
6923 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK)
6924 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK (0xFF000000U)
6925 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT (24U)
6926 /*! LPCG_lpcg_mlb_0_reserved_24_31 - reserved
6927  */
6928 #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK)
6929 /*! @} */
6930 
6931 
6932 /*!
6933  * @}
6934  */ /* end of group CONNECTIVITY_LPCG_MLB_Register_Masks */
6935 
6936 
6937 /* CONNECTIVITY_LPCG_MLB - Peripheral instance base addresses */
6938 /** Peripheral CONNECTIVITY__LPCG_MLB base address */
6939 #define CONNECTIVITY__LPCG_MLB_BASE              (0x5B260000u)
6940 /** Peripheral CONNECTIVITY__LPCG_MLB base pointer */
6941 #define CONNECTIVITY__LPCG_MLB                   ((CONNECTIVITY_LPCG_MLB_Type *)CONNECTIVITY__LPCG_MLB_BASE)
6942 /** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base addresses */
6943 #define CONNECTIVITY_LPCG_MLB_BASE_ADDRS         { CONNECTIVITY__LPCG_MLB_BASE }
6944 /** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base pointers */
6945 #define CONNECTIVITY_LPCG_MLB_BASE_PTRS          { CONNECTIVITY__LPCG_MLB }
6946 
6947 /*!
6948  * @}
6949  */ /* end of group CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer */
6950 
6951 
6952 /* ----------------------------------------------------------------------------
6953    -- CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
6954    ---------------------------------------------------------------------------- */
6955 
6956 /*!
6957  * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
6958  * @{
6959  */
6960 
6961 /** CONNECTIVITY_LPCG_RAWNAND - Register Layout Typedef */
6962 typedef struct {
6963   __IO uint32_t LPCG_LPCG_RAWNAND_0;               /**< na, offset: 0x0 */
6964   __IO uint32_t LPCG_LPCG_RAWNAND_4;               /**< na, offset: 0x4 */
6965 } CONNECTIVITY_LPCG_RAWNAND_Type;
6966 
6967 /* ----------------------------------------------------------------------------
6968    -- CONNECTIVITY_LPCG_RAWNAND Register Masks
6969    ---------------------------------------------------------------------------- */
6970 
6971 /*!
6972  * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Register_Masks CONNECTIVITY_LPCG_RAWNAND Register Masks
6973  * @{
6974  */
6975 
6976 /*! @name LPCG_LPCG_RAWNAND_0 - na */
6977 /*! @{ */
6978 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK (0x1U)
6979 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT (0U)
6980 /*! LPCG_lpcg_rawnand_0_reserved_0_0 - reserved
6981  */
6982 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK)
6983 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK (0x2U)
6984 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT (1U)
6985 /*! rawnand_u_gpmi_bch_input_bch_clk_SWEN - Software Enable
6986  *  0b0..Disable SW clock regardless of HWEN
6987  *  0b1..Enable SW clock gating
6988  */
6989 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK)
6990 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK (0x4U)
6991 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT (2U)
6992 /*! LPCG_lpcg_rawnand_0_reserved_2_2 - reserved
6993  */
6994 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK)
6995 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK (0x8U)
6996 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT (3U)
6997 /*! rawnand_u_gpmi_bch_input_bch_clk_STOP - show clock root status, 1 means clock stopped
6998  */
6999 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK)
7000 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK (0x10U)
7001 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT (4U)
7002 /*! LPCG_lpcg_rawnand_0_reserved_4_4 - reserved
7003  */
7004 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK)
7005 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK (0x20U)
7006 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT (5U)
7007 /*! rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN - Software Enable
7008  *  0b0..Disable SW clock regardless of HWEN
7009  *  0b1..Enable SW clock gating
7010  */
7011 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK)
7012 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK (0x40U)
7013 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT (6U)
7014 /*! LPCG_lpcg_rawnand_0_reserved_6_6 - reserved
7015  */
7016 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK)
7017 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK (0x80U)
7018 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT (7U)
7019 /*! rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP - show clock root status, 1 means clock stopped
7020  */
7021 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK)
7022 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK (0x1FF00U)
7023 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT (8U)
7024 /*! LPCG_lpcg_rawnand_0_reserved_8_16 - reserved
7025  */
7026 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK)
7027 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK (0x20000U)
7028 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT (17U)
7029 /*! rawnand_u_gpmi_input_apb_clk_SWEN - Software Enable
7030  *  0b0..Disable SW clock regardless of HWEN
7031  *  0b1..Enable SW clock gating
7032  */
7033 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK)
7034 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK (0x40000U)
7035 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT (18U)
7036 /*! LPCG_lpcg_rawnand_0_reserved_18_18 - reserved
7037  */
7038 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK)
7039 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK (0x80000U)
7040 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT (19U)
7041 /*! rawnand_u_gpmi_input_apb_clk_STOP - show clock root status, 1 means clock stopped
7042  */
7043 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK)
7044 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK (0x100000U)
7045 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT (20U)
7046 /*! LPCG_lpcg_rawnand_0_reserved_20_20 - reserved
7047  */
7048 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK)
7049 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK (0x200000U)
7050 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT (21U)
7051 /*! rawnand_u_bch_input_apb_clk_SWEN - Software Enable
7052  *  0b0..Disable SW clock regardless of HWEN
7053  *  0b1..Enable SW clock gating
7054  */
7055 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK)
7056 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK (0x400000U)
7057 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT (22U)
7058 /*! LPCG_lpcg_rawnand_0_reserved_22_22 - reserved
7059  */
7060 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK)
7061 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK (0x800000U)
7062 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT (23U)
7063 /*! rawnand_u_bch_input_apb_clk_STOP - show clock root status, 1 means clock stopped
7064  */
7065 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK)
7066 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK (0xFF000000U)
7067 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT (24U)
7068 /*! LPCG_lpcg_rawnand_0_reserved_24_31 - reserved
7069  */
7070 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK)
7071 /*! @} */
7072 
7073 /*! @name LPCG_LPCG_RAWNAND_4 - na */
7074 /*! @{ */
7075 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK (0x1FFFFU)
7076 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT (0U)
7077 /*! LPCG_lpcg_rawnand_4_reserved_0_16 - reserved
7078  */
7079 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK)
7080 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK (0x20000U)
7081 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT (17U)
7082 /*! apbhdma_hclk_SWEN - Software Enable
7083  *  0b0..Disable SW clock regardless of HWEN
7084  *  0b1..Enable SW clock gating
7085  */
7086 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK)
7087 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK (0x40000U)
7088 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT (18U)
7089 /*! LPCG_lpcg_rawnand_4_reserved_18_18 - reserved
7090  */
7091 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK)
7092 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK (0x80000U)
7093 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT (19U)
7094 /*! apbhdma_hclk_STOP - show clock root status, 1 means clock stopped
7095  */
7096 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK)
7097 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK (0xFFF00000U)
7098 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT (20U)
7099 /*! LPCG_lpcg_rawnand_4_reserved_20_31 - reserved
7100  */
7101 #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK)
7102 /*! @} */
7103 
7104 
7105 /*!
7106  * @}
7107  */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Register_Masks */
7108 
7109 
7110 /* CONNECTIVITY_LPCG_RAWNAND - Peripheral instance base addresses */
7111 /** Peripheral CONNECTIVITY__LPCG_RAWNAND base address */
7112 #define CONNECTIVITY__LPCG_RAWNAND_BASE          (0x5B290000u)
7113 /** Peripheral CONNECTIVITY__LPCG_RAWNAND base pointer */
7114 #define CONNECTIVITY__LPCG_RAWNAND               ((CONNECTIVITY_LPCG_RAWNAND_Type *)CONNECTIVITY__LPCG_RAWNAND_BASE)
7115 /** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base addresses */
7116 #define CONNECTIVITY_LPCG_RAWNAND_BASE_ADDRS     { CONNECTIVITY__LPCG_RAWNAND_BASE }
7117 /** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base pointers */
7118 #define CONNECTIVITY_LPCG_RAWNAND_BASE_PTRS      { CONNECTIVITY__LPCG_RAWNAND }
7119 
7120 /*!
7121  * @}
7122  */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer */
7123 
7124 
7125 /* ----------------------------------------------------------------------------
7126    -- CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
7127    ---------------------------------------------------------------------------- */
7128 
7129 /*!
7130  * @addtogroup CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
7131  * @{
7132  */
7133 
7134 /** CONNECTIVITY_LPCG_USB2 - Register Layout Typedef */
7135 typedef struct {
7136   __IO uint32_t LPCG_LPCG_USB2_0;                  /**< na, offset: 0x0 */
7137 } CONNECTIVITY_LPCG_USB2_Type;
7138 
7139 /* ----------------------------------------------------------------------------
7140    -- CONNECTIVITY_LPCG_USB2 Register Masks
7141    ---------------------------------------------------------------------------- */
7142 
7143 /*!
7144  * @addtogroup CONNECTIVITY_LPCG_USB2_Register_Masks CONNECTIVITY_LPCG_USB2 Register Masks
7145  * @{
7146  */
7147 
7148 /*! @name LPCG_LPCG_USB2_0 - na */
7149 /*! @{ */
7150 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK (0x1FFFFU)
7151 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT (0U)
7152 /*! LPCG_lpcg_usb2_0_reserved_0_16 - reserved
7153  */
7154 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK)
7155 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK (0x20000U)
7156 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT (17U)
7157 /*! usboh_ipg_clk_s_SWEN - Software Enable
7158  *  0b0..Disable SW clock regardless of HWEN
7159  *  0b1..Enable SW clock gating
7160  */
7161 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK)
7162 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK (0x40000U)
7163 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT (18U)
7164 /*! LPCG_lpcg_usb2_0_reserved_18_18 - reserved
7165  */
7166 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK)
7167 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK (0x80000U)
7168 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT (19U)
7169 /*! usboh_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
7170  */
7171 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK)
7172 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK (0x100000U)
7173 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT (20U)
7174 /*! LPCG_lpcg_usb2_0_reserved_20_20 - reserved
7175  */
7176 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK)
7177 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK (0x200000U)
7178 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT (21U)
7179 /*! usboh_ipg_clk_s_pl301_SWEN - Software Enable
7180  *  0b0..Disable SW clock regardless of HWEN
7181  *  0b1..Enable SW clock gating
7182  */
7183 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK)
7184 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK (0x400000U)
7185 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT (22U)
7186 /*! LPCG_lpcg_usb2_0_reserved_22_22 - reserved
7187  */
7188 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK)
7189 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK (0x800000U)
7190 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT (23U)
7191 /*! usboh_ipg_clk_s_pl301_STOP - show clock root status, 1 means clock stopped
7192  */
7193 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK)
7194 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK (0x1000000U)
7195 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT (24U)
7196 /*! LPCG_lpcg_usb2_0_reserved_24_24 - reserved
7197  */
7198 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK)
7199 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK (0x2000000U)
7200 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT (25U)
7201 /*! usboh_ipg_ahb_clk_SWEN - Software Enable
7202  *  0b0..Disable SW clock regardless of HWEN
7203  *  0b1..Enable SW clock gating
7204  */
7205 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK)
7206 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK (0x4000000U)
7207 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT (26U)
7208 /*! LPCG_lpcg_usb2_0_reserved_26_26 - reserved
7209  */
7210 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK)
7211 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK (0x8000000U)
7212 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT (27U)
7213 /*! usboh_ipg_ahb_clk_STOP - show clock root status, 1 means clock stopped
7214  */
7215 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK)
7216 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK (0x10000000U)
7217 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT (28U)
7218 /*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN - Hardware Enable
7219  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7220  *  0b1..Enable HW automatic gating
7221  */
7222 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK)
7223 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK (0x20000000U)
7224 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT (29U)
7225 /*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN - Software Enable
7226  *  0b0..Disable SW clock regardless of HWEN
7227  *  0b1..Enable SW clock gating
7228  */
7229 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK)
7230 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK (0x40000000U)
7231 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT (30U)
7232 /*! LPCG_lpcg_usb2_0_reserved_30_30 - reserved
7233  */
7234 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK)
7235 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK (0x80000000U)
7236 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT (31U)
7237 /*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
7238  */
7239 #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK)
7240 /*! @} */
7241 
7242 
7243 /*!
7244  * @}
7245  */ /* end of group CONNECTIVITY_LPCG_USB2_Register_Masks */
7246 
7247 
7248 /* CONNECTIVITY_LPCG_USB2 - Peripheral instance base addresses */
7249 /** Peripheral CONNECTIVITY__LPCG_USB2 base address */
7250 #define CONNECTIVITY__LPCG_USB2_BASE             (0x5B270000u)
7251 /** Peripheral CONNECTIVITY__LPCG_USB2 base pointer */
7252 #define CONNECTIVITY__LPCG_USB2                  ((CONNECTIVITY_LPCG_USB2_Type *)CONNECTIVITY__LPCG_USB2_BASE)
7253 /** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base addresses */
7254 #define CONNECTIVITY_LPCG_USB2_BASE_ADDRS        { CONNECTIVITY__LPCG_USB2_BASE }
7255 /** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base pointers */
7256 #define CONNECTIVITY_LPCG_USB2_BASE_PTRS         { CONNECTIVITY__LPCG_USB2 }
7257 
7258 /*!
7259  * @}
7260  */ /* end of group CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer */
7261 
7262 
7263 /* ----------------------------------------------------------------------------
7264    -- CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
7265    ---------------------------------------------------------------------------- */
7266 
7267 /*!
7268  * @addtogroup CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
7269  * @{
7270  */
7271 
7272 /** CONNECTIVITY_LPCG_USB3 - Register Layout Typedef */
7273 typedef struct {
7274   __IO uint32_t LPCG_LPCG_USB3_0;                  /**< na, offset: 0x0 */
7275 } CONNECTIVITY_LPCG_USB3_Type;
7276 
7277 /* ----------------------------------------------------------------------------
7278    -- CONNECTIVITY_LPCG_USB3 Register Masks
7279    ---------------------------------------------------------------------------- */
7280 
7281 /*!
7282  * @addtogroup CONNECTIVITY_LPCG_USB3_Register_Masks CONNECTIVITY_LPCG_USB3 Register Masks
7283  * @{
7284  */
7285 
7286 /*! @name LPCG_LPCG_USB3_0 - na */
7287 /*! @{ */
7288 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK (0x1U)
7289 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT (0U)
7290 /*! LPCG_lpcg_usb3_0_reserved_0_0 - reserved
7291  */
7292 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK)
7293 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK (0x2U)
7294 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT (1U)
7295 /*! da_ip_usb3_wrap_app_clk_125_predft_SWEN - Software Enable
7296  *  0b0..Disable SW clock regardless of HWEN
7297  *  0b1..Enable SW clock gating
7298  */
7299 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK)
7300 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK (0x4U)
7301 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT (2U)
7302 /*! LPCG_lpcg_usb3_0_reserved_2_2 - reserved
7303  */
7304 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK)
7305 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK (0x8U)
7306 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT (3U)
7307 /*! da_ip_usb3_wrap_app_clk_125_predft_STOP - show clock root status, 1 means clock stopped
7308  */
7309 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK)
7310 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK (0x10U)
7311 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT (4U)
7312 /*! LPCG_lpcg_usb3_0_reserved_4_4 - reserved
7313  */
7314 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK)
7315 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK (0x20U)
7316 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT (5U)
7317 /*! da_ip_usb3_wrap_lpm_clk_predft_SWEN - Software Enable
7318  *  0b0..Disable SW clock regardless of HWEN
7319  *  0b1..Enable SW clock gating
7320  */
7321 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK)
7322 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK (0x40U)
7323 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT (6U)
7324 /*! LPCG_lpcg_usb3_0_reserved_6_6 - reserved
7325  */
7326 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK)
7327 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK (0x80U)
7328 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT (7U)
7329 /*! da_ip_usb3_wrap_lpm_clk_predft_STOP - show clock root status, 1 means clock stopped
7330  */
7331 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK)
7332 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK (0x1FF00U)
7333 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT (8U)
7334 /*! LPCG_lpcg_usb3_0_reserved_8_16 - reserved
7335  */
7336 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK)
7337 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK (0x20000U)
7338 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT (17U)
7339 /*! da_ip_usb3_wrap_ipg_clk_SWEN - Software Enable
7340  *  0b0..Disable SW clock regardless of HWEN
7341  *  0b1..Enable SW clock gating
7342  */
7343 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK)
7344 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK (0x40000U)
7345 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT (18U)
7346 /*! LPCG_lpcg_usb3_0_reserved_18_18 - reserved
7347  */
7348 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK)
7349 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK (0x80000U)
7350 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT (19U)
7351 /*! da_ip_usb3_wrap_ipg_clk_STOP - show clock root status, 1 means clock stopped
7352  */
7353 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK)
7354 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK (0x100000U)
7355 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT (20U)
7356 /*! LPCG_lpcg_usb3_0_reserved_20_20 - reserved
7357  */
7358 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK)
7359 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK (0x200000U)
7360 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT (21U)
7361 /*! da_ip_usb3_wrap_usb3_core_pclk_SWEN - Software Enable
7362  *  0b0..Disable SW clock regardless of HWEN
7363  *  0b1..Enable SW clock gating
7364  */
7365 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK)
7366 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK (0x400000U)
7367 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT (22U)
7368 /*! LPCG_lpcg_usb3_0_reserved_22_22 - reserved
7369  */
7370 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK)
7371 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK (0x800000U)
7372 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT (23U)
7373 /*! da_ip_usb3_wrap_usb3_core_pclk_STOP - show clock root status, 1 means clock stopped
7374  */
7375 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK)
7376 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK (0x1000000U)
7377 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT (24U)
7378 /*! LPCG_lpcg_usb3_0_reserved_24_24 - reserved
7379  */
7380 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK)
7381 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK (0x2000000U)
7382 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT (25U)
7383 /*! da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN - Software Enable
7384  *  0b0..Disable SW clock regardless of HWEN
7385  *  0b1..Enable SW clock gating
7386  */
7387 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK)
7388 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK (0x4000000U)
7389 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT (26U)
7390 /*! LPCG_lpcg_usb3_0_reserved_26_26 - reserved
7391  */
7392 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK)
7393 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK (0x8000000U)
7394 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT (27U)
7395 /*! da_ip_usb3_wrap_usb3_ssphy_pclk_STOP - show clock root status, 1 means clock stopped
7396  */
7397 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK)
7398 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK (0x10000000U)
7399 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT (28U)
7400 /*! LPCG_lpcg_usb3_0_reserved_28_28 - reserved
7401  */
7402 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK)
7403 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK (0x20000000U)
7404 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT (29U)
7405 /*! da_ip_usb3_wrap_usb3_aclk_SWEN - Software Enable
7406  *  0b0..Disable SW clock regardless of HWEN
7407  *  0b1..Enable SW clock gating
7408  */
7409 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK)
7410 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK (0x40000000U)
7411 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT (30U)
7412 /*! LPCG_lpcg_usb3_0_reserved_30_30 - reserved
7413  */
7414 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK)
7415 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK (0x80000000U)
7416 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT (31U)
7417 /*! da_ip_usb3_wrap_usb3_aclk_STOP - show clock root status, 1 means clock stopped
7418  */
7419 #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK)
7420 /*! @} */
7421 
7422 
7423 /*!
7424  * @}
7425  */ /* end of group CONNECTIVITY_LPCG_USB3_Register_Masks */
7426 
7427 
7428 /* CONNECTIVITY_LPCG_USB3 - Peripheral instance base addresses */
7429 /** Peripheral CONNECTIVITY__LPCG_USB3 base address */
7430 #define CONNECTIVITY__LPCG_USB3_BASE             (0x5B280000u)
7431 /** Peripheral CONNECTIVITY__LPCG_USB3 base pointer */
7432 #define CONNECTIVITY__LPCG_USB3                  ((CONNECTIVITY_LPCG_USB3_Type *)CONNECTIVITY__LPCG_USB3_BASE)
7433 /** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base addresses */
7434 #define CONNECTIVITY_LPCG_USB3_BASE_ADDRS        { CONNECTIVITY__LPCG_USB3_BASE }
7435 /** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base pointers */
7436 #define CONNECTIVITY_LPCG_USB3_BASE_PTRS         { CONNECTIVITY__LPCG_USB3 }
7437 
7438 /*!
7439  * @}
7440  */ /* end of group CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer */
7441 
7442 
7443 /* ----------------------------------------------------------------------------
7444    -- CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
7445    ---------------------------------------------------------------------------- */
7446 
7447 /*!
7448  * @addtogroup CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
7449  * @{
7450  */
7451 
7452 /** CONNECTIVITY_LPCG_USDHC0 - Register Layout Typedef */
7453 typedef struct {
7454   __IO uint32_t LPCG_LPCG_USDHC1_0;                /**< na, offset: 0x0 */
7455 } CONNECTIVITY_LPCG_USDHC0_Type;
7456 
7457 /* ----------------------------------------------------------------------------
7458    -- CONNECTIVITY_LPCG_USDHC0 Register Masks
7459    ---------------------------------------------------------------------------- */
7460 
7461 /*!
7462  * @addtogroup CONNECTIVITY_LPCG_USDHC0_Register_Masks CONNECTIVITY_LPCG_USDHC0 Register Masks
7463  * @{
7464  */
7465 
7466 /*! @name LPCG_LPCG_USDHC1_0 - na */
7467 /*! @{ */
7468 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK (0x1U)
7469 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT (0U)
7470 /*! LPCG_lpcg_usdhc1_0_reserved_0_0 - reserved
7471  */
7472 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK)
7473 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK (0x2U)
7474 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT (1U)
7475 /*! usdhc1_ipg_clk_perclk_SWEN - Software Enable
7476  *  0b0..Disable SW clock regardless of HWEN
7477  *  0b1..Enable SW clock gating
7478  */
7479 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK)
7480 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK (0x4U)
7481 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT (2U)
7482 /*! LPCG_lpcg_usdhc1_0_reserved_2_2 - reserved
7483  */
7484 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK)
7485 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK (0x8U)
7486 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT (3U)
7487 /*! usdhc1_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
7488  */
7489 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK)
7490 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK (0xFFF0U)
7491 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT (4U)
7492 /*! LPCG_lpcg_usdhc1_0_reserved_4_15 - reserved
7493  */
7494 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK)
7495 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK (0x10000U)
7496 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT (16U)
7497 /*! usdhc1_ipg_clk_s_HWEN - Hardware Enable
7498  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7499  *  0b1..Enable HW automatic gating
7500  */
7501 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK)
7502 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK (0x20000U)
7503 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT (17U)
7504 /*! usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN - Software Enable
7505  *  0b0..Disable SW clock regardless of HWEN
7506  *  0b1..Enable SW clock gating
7507  */
7508 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK)
7509 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK (0x40000U)
7510 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT (18U)
7511 /*! LPCG_lpcg_usdhc1_0_reserved_18_18 - reserved
7512  */
7513 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK)
7514 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK (0x80000U)
7515 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT (19U)
7516 /*! usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP - show clock root status, 1 means clock stopped
7517  */
7518 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK)
7519 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK (0x100000U)
7520 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT (20U)
7521 /*! LPCG_lpcg_usdhc1_0_reserved_20_20 - reserved
7522  */
7523 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK)
7524 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK (0x200000U)
7525 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT (21U)
7526 /*! usdhc1_hclk_SWEN - Software Enable
7527  *  0b0..Disable SW clock regardless of HWEN
7528  *  0b1..Enable SW clock gating
7529  */
7530 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK)
7531 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK (0x400000U)
7532 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT (22U)
7533 /*! LPCG_lpcg_usdhc1_0_reserved_22_22 - reserved
7534  */
7535 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK)
7536 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK (0x800000U)
7537 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT (23U)
7538 /*! usdhc1_hclk_STOP - show clock root status, 1 means clock stopped
7539  */
7540 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK)
7541 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK (0xFF000000U)
7542 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT (24U)
7543 /*! LPCG_lpcg_usdhc1_0_reserved_24_31 - reserved
7544  */
7545 #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK)
7546 /*! @} */
7547 
7548 
7549 /*!
7550  * @}
7551  */ /* end of group CONNECTIVITY_LPCG_USDHC0_Register_Masks */
7552 
7553 
7554 /* CONNECTIVITY_LPCG_USDHC0 - Peripheral instance base addresses */
7555 /** Peripheral CONNECTIVITY__LPCG_USDHC0 base address */
7556 #define CONNECTIVITY__LPCG_USDHC0_BASE           (0x5B200000u)
7557 /** Peripheral CONNECTIVITY__LPCG_USDHC0 base pointer */
7558 #define CONNECTIVITY__LPCG_USDHC0                ((CONNECTIVITY_LPCG_USDHC0_Type *)CONNECTIVITY__LPCG_USDHC0_BASE)
7559 /** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base addresses */
7560 #define CONNECTIVITY_LPCG_USDHC0_BASE_ADDRS      { CONNECTIVITY__LPCG_USDHC0_BASE }
7561 /** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base pointers */
7562 #define CONNECTIVITY_LPCG_USDHC0_BASE_PTRS       { CONNECTIVITY__LPCG_USDHC0 }
7563 
7564 /*!
7565  * @}
7566  */ /* end of group CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer */
7567 
7568 
7569 /* ----------------------------------------------------------------------------
7570    -- CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
7571    ---------------------------------------------------------------------------- */
7572 
7573 /*!
7574  * @addtogroup CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
7575  * @{
7576  */
7577 
7578 /** CONNECTIVITY_LPCG_USDHC1 - Register Layout Typedef */
7579 typedef struct {
7580   __IO uint32_t LPCG_LPCG_USDHC2_0;                /**< na, offset: 0x0 */
7581 } CONNECTIVITY_LPCG_USDHC1_Type;
7582 
7583 /* ----------------------------------------------------------------------------
7584    -- CONNECTIVITY_LPCG_USDHC1 Register Masks
7585    ---------------------------------------------------------------------------- */
7586 
7587 /*!
7588  * @addtogroup CONNECTIVITY_LPCG_USDHC1_Register_Masks CONNECTIVITY_LPCG_USDHC1 Register Masks
7589  * @{
7590  */
7591 
7592 /*! @name LPCG_LPCG_USDHC2_0 - na */
7593 /*! @{ */
7594 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK (0x1U)
7595 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT (0U)
7596 /*! LPCG_lpcg_usdhc2_0_reserved_0_0 - reserved
7597  */
7598 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK)
7599 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK (0x2U)
7600 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT (1U)
7601 /*! usdhc2_ipg_clk_perclk_SWEN - Software Enable
7602  *  0b0..Disable SW clock regardless of HWEN
7603  *  0b1..Enable SW clock gating
7604  */
7605 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK)
7606 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK (0x4U)
7607 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT (2U)
7608 /*! LPCG_lpcg_usdhc2_0_reserved_2_2 - reserved
7609  */
7610 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK)
7611 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK (0x8U)
7612 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT (3U)
7613 /*! usdhc2_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
7614  */
7615 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK)
7616 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK (0xFFF0U)
7617 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT (4U)
7618 /*! LPCG_lpcg_usdhc2_0_reserved_4_15 - reserved
7619  */
7620 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK)
7621 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK (0x10000U)
7622 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT (16U)
7623 /*! usdhc2_ipg_clk_s_HWEN - Hardware Enable
7624  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7625  *  0b1..Enable HW automatic gating
7626  */
7627 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK)
7628 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK (0x20000U)
7629 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT (17U)
7630 /*! usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN - Software Enable
7631  *  0b0..Disable SW clock regardless of HWEN
7632  *  0b1..Enable SW clock gating
7633  */
7634 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK)
7635 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK (0x40000U)
7636 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT (18U)
7637 /*! LPCG_lpcg_usdhc2_0_reserved_18_18 - reserved
7638  */
7639 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK)
7640 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK (0x80000U)
7641 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT (19U)
7642 /*! usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP - show clock root status, 1 means clock stopped
7643  */
7644 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK)
7645 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK (0x100000U)
7646 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT (20U)
7647 /*! LPCG_lpcg_usdhc2_0_reserved_20_20 - reserved
7648  */
7649 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK)
7650 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK (0x200000U)
7651 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT (21U)
7652 /*! usdhc2_hclk_SWEN - Software Enable
7653  *  0b0..Disable SW clock regardless of HWEN
7654  *  0b1..Enable SW clock gating
7655  */
7656 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK)
7657 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK (0x400000U)
7658 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT (22U)
7659 /*! LPCG_lpcg_usdhc2_0_reserved_22_22 - reserved
7660  */
7661 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK)
7662 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK (0x800000U)
7663 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT (23U)
7664 /*! usdhc2_hclk_STOP - show clock root status, 1 means clock stopped
7665  */
7666 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK)
7667 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK (0xFF000000U)
7668 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT (24U)
7669 /*! LPCG_lpcg_usdhc2_0_reserved_24_31 - reserved
7670  */
7671 #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK)
7672 /*! @} */
7673 
7674 
7675 /*!
7676  * @}
7677  */ /* end of group CONNECTIVITY_LPCG_USDHC1_Register_Masks */
7678 
7679 
7680 /* CONNECTIVITY_LPCG_USDHC1 - Peripheral instance base addresses */
7681 /** Peripheral CONNECTIVITY__LPCG_USDHC1 base address */
7682 #define CONNECTIVITY__LPCG_USDHC1_BASE           (0x5B210000u)
7683 /** Peripheral CONNECTIVITY__LPCG_USDHC1 base pointer */
7684 #define CONNECTIVITY__LPCG_USDHC1                ((CONNECTIVITY_LPCG_USDHC1_Type *)CONNECTIVITY__LPCG_USDHC1_BASE)
7685 /** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base addresses */
7686 #define CONNECTIVITY_LPCG_USDHC1_BASE_ADDRS      { CONNECTIVITY__LPCG_USDHC1_BASE }
7687 /** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base pointers */
7688 #define CONNECTIVITY_LPCG_USDHC1_BASE_PTRS       { CONNECTIVITY__LPCG_USDHC1 }
7689 
7690 /*!
7691  * @}
7692  */ /* end of group CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer */
7693 
7694 
7695 /* ----------------------------------------------------------------------------
7696    -- DC_LPCG Peripheral Access Layer
7697    ---------------------------------------------------------------------------- */
7698 
7699 /*!
7700  * @addtogroup DC_LPCG_Peripheral_Access_Layer DC_LPCG Peripheral Access Layer
7701  * @{
7702  */
7703 
7704 /** DC_LPCG - Register Layout Typedef */
7705 typedef struct {
7706   __IO uint32_t LPCG_DC_LPCG_0;                    /**< na, offset: 0x0 */
7707   __IO uint32_t LPCG_DC_LPCG_4;                    /**< na, offset: 0x4 */
7708   __IO uint32_t LPCG_DC_LPCG_8;                    /**< na, offset: 0x8 */
7709        uint8_t RESERVED_0[4];
7710   __IO uint32_t LPCG_DC_LPCG_16;                   /**< na, offset: 0x10 */
7711   __IO uint32_t LPCG_DC_LPCG_20;                   /**< na, offset: 0x14 */
7712   __IO uint32_t LPCG_DC_LPCG_24;                   /**< na, offset: 0x18 */
7713   __IO uint32_t LPCG_DC_LPCG_28;                   /**< na, offset: 0x1C */
7714   __IO uint32_t LPCG_DC_LPCG_32;                   /**< na, offset: 0x20 */
7715   __IO uint32_t LPCG_DC_LPCG_36;                   /**< na, offset: 0x24 */
7716   __IO uint32_t LPCG_DC_LPCG_40;                   /**< na, offset: 0x28 */
7717   __IO uint32_t LPCG_DC_LPCG_44;                   /**< na, offset: 0x2C */
7718   __IO uint32_t LPCG_DC_LPCG_48;                   /**< na, offset: 0x30 */
7719   __IO uint32_t LPCG_DC_LPCG_52;                   /**< na, offset: 0x34 */
7720   __IO uint32_t LPCG_DC_LPCG_56;                   /**< na, offset: 0x38 */
7721   __IO uint32_t LPCG_DC_LPCG_60;                   /**< na, offset: 0x3C */
7722   __IO uint32_t LPCG_DC_LPCG_64;                   /**< na, offset: 0x40 */
7723   __IO uint32_t LPCG_DC_LPCG_68;                   /**< na, offset: 0x44 */
7724   __IO uint32_t LPCG_DC_LPCG_72;                   /**< na, offset: 0x48 */
7725 } DC_LPCG_Type;
7726 
7727 /* ----------------------------------------------------------------------------
7728    -- DC_LPCG Register Masks
7729    ---------------------------------------------------------------------------- */
7730 
7731 /*!
7732  * @addtogroup DC_LPCG_Register_Masks DC_LPCG Register Masks
7733  * @{
7734  */
7735 
7736 /*! @name LPCG_DC_LPCG_0 - na */
7737 /*! @{ */
7738 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK (0x1U)
7739 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT (0U)
7740 /*! LPCG_dc_lpcg_0_reserved_0_0 - reserved
7741  */
7742 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK)
7743 #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK (0x2U)
7744 #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT (1U)
7745 /*! dsp0_clk_SWEN - Software Enable
7746  *  0b0..Disable SW clock regardless of HWEN
7747  *  0b1..Enable SW clock gating
7748  */
7749 #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK)
7750 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK (0x4U)
7751 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT (2U)
7752 /*! LPCG_dc_lpcg_0_reserved_2_2 - reserved
7753  */
7754 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK)
7755 #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK (0x8U)
7756 #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT (3U)
7757 /*! dsp0_clk_STOP - show clock root status, 1 means clock stopped
7758  */
7759 #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK)
7760 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK (0x10U)
7761 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT (4U)
7762 /*! LPCG_dc_lpcg_0_reserved_4_4 - reserved
7763  */
7764 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK)
7765 #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK (0x20U)
7766 #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT (5U)
7767 /*! dsp1_clk_SWEN - Software Enable
7768  *  0b0..Disable SW clock regardless of HWEN
7769  *  0b1..Enable SW clock gating
7770  */
7771 #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK)
7772 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK (0x40U)
7773 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT (6U)
7774 /*! LPCG_dc_lpcg_0_reserved_6_6 - reserved
7775  */
7776 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK)
7777 #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK (0x80U)
7778 #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT (7U)
7779 /*! dsp1_clk_STOP - show clock root status, 1 means clock stopped
7780  */
7781 #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK)
7782 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK (0xFFFFFF00U)
7783 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT (8U)
7784 /*! LPCG_dc_lpcg_0_reserved_8_31 - reserved
7785  */
7786 #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK)
7787 /*! @} */
7788 
7789 /*! @name LPCG_DC_LPCG_4 - na */
7790 /*! @{ */
7791 #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK (0xFFFFU)
7792 #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT (0U)
7793 /*! LPCG_dc_lpcg_4_reserved_0_15 - reserved
7794  */
7795 #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK)
7796 #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK (0x10000U)
7797 #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT (16U)
7798 /*! lis_ipg_clk_HWEN - Hardware Enable
7799  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7800  *  0b1..Enable HW automatic gating
7801  */
7802 #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK)
7803 #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U)
7804 #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U)
7805 /*! lis_ipg_clk_SWEN - Software Enable
7806  *  0b0..Disable SW clock regardless of HWEN
7807  *  0b1..Enable SW clock gating
7808  */
7809 #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK)
7810 #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK (0x40000U)
7811 #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT (18U)
7812 /*! LPCG_dc_lpcg_4_reserved_18_18 - reserved
7813  */
7814 #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK)
7815 #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U)
7816 #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U)
7817 /*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped
7818  */
7819 #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK)
7820 #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
7821 #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT (20U)
7822 /*! LPCG_dc_lpcg_4_reserved_20_31 - reserved
7823  */
7824 #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK)
7825 /*! @} */
7826 
7827 /*! @name LPCG_DC_LPCG_8 - na */
7828 /*! @{ */
7829 #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK (0xFFFFU)
7830 #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT (0U)
7831 /*! LPCG_dc_lpcg_8_reserved_0_15 - reserved
7832  */
7833 #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK)
7834 #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK (0x10000U)
7835 #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT (16U)
7836 /*! display_ctrl_link_mst0_msi_clk_HWEN - Hardware Enable
7837  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7838  *  0b1..Enable HW automatic gating
7839  */
7840 #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK)
7841 #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK (0x20000U)
7842 #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT (17U)
7843 /*! display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN - Software Enable
7844  *  0b0..Disable SW clock regardless of HWEN
7845  *  0b1..Enable SW clock gating
7846  */
7847 #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK)
7848 #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK (0x40000U)
7849 #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT (18U)
7850 /*! LPCG_dc_lpcg_8_reserved_18_18 - reserved
7851  */
7852 #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK)
7853 #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK (0x80000U)
7854 #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT (19U)
7855 /*! display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP - show clock root status, 1 means clock stopped
7856  */
7857 #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK)
7858 #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
7859 #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT (20U)
7860 /*! LPCG_dc_lpcg_8_reserved_20_31 - reserved
7861  */
7862 #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK)
7863 /*! @} */
7864 
7865 /*! @name LPCG_DC_LPCG_16 - na */
7866 /*! @{ */
7867 #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK (0xFFFFU)
7868 #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT (0U)
7869 /*! LPCG_dc_lpcg_16_reserved_0_15 - reserved
7870  */
7871 #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK)
7872 #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK (0x10000U)
7873 #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT (16U)
7874 /*! pixel_combiner_apb_clk_HWEN - Hardware Enable
7875  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7876  *  0b1..Enable HW automatic gating
7877  */
7878 #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK)
7879 #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK (0x20000U)
7880 #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT (17U)
7881 /*! pixel_combiner_apb_clk_SWEN - Software Enable
7882  *  0b0..Disable SW clock regardless of HWEN
7883  *  0b1..Enable SW clock gating
7884  */
7885 #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK)
7886 #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK (0x40000U)
7887 #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT (18U)
7888 /*! LPCG_dc_lpcg_16_reserved_18_18 - reserved
7889  */
7890 #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK)
7891 #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK (0x80000U)
7892 #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT (19U)
7893 /*! pixel_combiner_apb_clk_STOP - show clock root status, 1 means clock stopped
7894  */
7895 #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK)
7896 #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
7897 #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT (20U)
7898 /*! LPCG_dc_lpcg_16_reserved_20_31 - reserved
7899  */
7900 #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK)
7901 /*! @} */
7902 
7903 /*! @name LPCG_DC_LPCG_20 - na */
7904 /*! @{ */
7905 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK (0xFFFFU)
7906 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT (0U)
7907 /*! LPCG_dc_lpcg_20_reserved_0_15 - reserved
7908  */
7909 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK)
7910 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK (0x10000U)
7911 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT (16U)
7912 /*! iris_mvpl_cfg_clk_HWEN - Hardware Enable
7913  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7914  *  0b1..Enable HW automatic gating
7915  */
7916 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK)
7917 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK (0x20000U)
7918 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT (17U)
7919 /*! iris_mvpl_cfg_clk_SWEN - Software Enable
7920  *  0b0..Disable SW clock regardless of HWEN
7921  *  0b1..Enable SW clock gating
7922  */
7923 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK)
7924 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK (0x40000U)
7925 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT (18U)
7926 /*! LPCG_dc_lpcg_20_reserved_18_18 - reserved
7927  */
7928 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK)
7929 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK (0x80000U)
7930 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT (19U)
7931 /*! iris_mvpl_cfg_clk_STOP - show clock root status, 1 means clock stopped
7932  */
7933 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK)
7934 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK (0x100000U)
7935 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT (20U)
7936 /*! LPCG_dc_lpcg_20_reserved_20_20 - reserved
7937  */
7938 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK)
7939 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK (0x200000U)
7940 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT (21U)
7941 /*! iris_mvpl_axi_clk_SWEN - Software Enable
7942  *  0b0..Disable SW clock regardless of HWEN
7943  *  0b1..Enable SW clock gating
7944  */
7945 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK)
7946 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK (0x400000U)
7947 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT (22U)
7948 /*! LPCG_dc_lpcg_20_reserved_22_22 - reserved
7949  */
7950 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK)
7951 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK (0x800000U)
7952 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT (23U)
7953 /*! iris_mvpl_axi_clk_STOP - show clock root status, 1 means clock stopped
7954  */
7955 #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK)
7956 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK (0xFF000000U)
7957 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT (24U)
7958 /*! LPCG_dc_lpcg_20_reserved_24_31 - reserved
7959  */
7960 #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK)
7961 /*! @} */
7962 
7963 /*! @name LPCG_DC_LPCG_24 - na */
7964 /*! @{ */
7965 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK (0xFFFFU)
7966 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT (0U)
7967 /*! LPCG_dc_lpcg_24_reserved_0_15 - reserved
7968  */
7969 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK)
7970 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK (0x10000U)
7971 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT (16U)
7972 /*! dpr0_dpr_apb_clkg_HWEN - Hardware Enable
7973  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7974  *  0b1..Enable HW automatic gating
7975  */
7976 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK)
7977 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK (0x20000U)
7978 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT (17U)
7979 /*! dpr0_dpr_apb_clkg_SWEN - Software Enable
7980  *  0b0..Disable SW clock regardless of HWEN
7981  *  0b1..Enable SW clock gating
7982  */
7983 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK)
7984 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK (0x40000U)
7985 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT (18U)
7986 /*! LPCG_dc_lpcg_24_reserved_18_18 - reserved
7987  */
7988 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK)
7989 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK (0x80000U)
7990 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT (19U)
7991 /*! dpr0_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped
7992  */
7993 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK)
7994 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK (0x100000U)
7995 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT (20U)
7996 /*! dpr0_dpr_b_clkg_HWEN - Hardware Enable
7997  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7998  *  0b1..Enable HW automatic gating
7999  */
8000 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK)
8001 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK (0x200000U)
8002 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT (21U)
8003 /*! dpr0_dpr_b_clkg_SWEN - Software Enable
8004  *  0b0..Disable SW clock regardless of HWEN
8005  *  0b1..Enable SW clock gating
8006  */
8007 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK)
8008 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK (0x400000U)
8009 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT (22U)
8010 /*! LPCG_dc_lpcg_24_reserved_22_22 - reserved
8011  */
8012 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK)
8013 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK (0x800000U)
8014 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT (23U)
8015 /*! dpr0_dpr_b_clkg_STOP - show clock root status, 1 means clock stopped
8016  */
8017 #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK)
8018 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK (0xFF000000U)
8019 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT (24U)
8020 /*! LPCG_dc_lpcg_24_reserved_24_31 - reserved
8021  */
8022 #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK)
8023 /*! @} */
8024 
8025 /*! @name LPCG_DC_LPCG_28 - na */
8026 /*! @{ */
8027 #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK (0x1U)
8028 #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT (0U)
8029 /*! LPCG_dc_lpcg_28_reserved_0_0 - reserved
8030  */
8031 #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK)
8032 #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK (0x2U)
8033 #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT (1U)
8034 /*! rtram0_rtr_clk_g_SWEN - Software Enable
8035  *  0b0..Disable SW clock regardless of HWEN
8036  *  0b1..Enable SW clock gating
8037  */
8038 #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK)
8039 #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK (0x4U)
8040 #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT (2U)
8041 /*! LPCG_dc_lpcg_28_reserved_2_2 - reserved
8042  */
8043 #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK)
8044 #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK (0x8U)
8045 #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT (3U)
8046 /*! rtram0_rtr_clk_g_STOP - show clock root status, 1 means clock stopped
8047  */
8048 #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK)
8049 #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U)
8050 #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT (4U)
8051 /*! LPCG_dc_lpcg_28_reserved_4_31 - reserved
8052  */
8053 #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK)
8054 /*! @} */
8055 
8056 /*! @name LPCG_DC_LPCG_32 - na */
8057 /*! @{ */
8058 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK (0x1U)
8059 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT (0U)
8060 /*! LPCG_dc_lpcg_32_reserved_0_0 - reserved
8061  */
8062 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK)
8063 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK (0x2U)
8064 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT (1U)
8065 /*! prg0_rtram_clk_SWEN - Software Enable
8066  *  0b0..Disable SW clock regardless of HWEN
8067  *  0b1..Enable SW clock gating
8068  */
8069 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK)
8070 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK (0x4U)
8071 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT (2U)
8072 /*! LPCG_dc_lpcg_32_reserved_2_2 - reserved
8073  */
8074 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK)
8075 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK (0x8U)
8076 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT (3U)
8077 /*! prg0_rtram_clk_STOP - show clock root status, 1 means clock stopped
8078  */
8079 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK)
8080 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK (0xFFF0U)
8081 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT (4U)
8082 /*! LPCG_dc_lpcg_32_reserved_4_15 - reserved
8083  */
8084 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK)
8085 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK (0x10000U)
8086 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT (16U)
8087 /*! prg0_apb_clk_HWEN - Hardware Enable
8088  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8089  *  0b1..Enable HW automatic gating
8090  */
8091 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK)
8092 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK (0x20000U)
8093 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT (17U)
8094 /*! prg0_apb_clk_SWEN - Software Enable
8095  *  0b0..Disable SW clock regardless of HWEN
8096  *  0b1..Enable SW clock gating
8097  */
8098 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK)
8099 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK (0x40000U)
8100 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT (18U)
8101 /*! LPCG_dc_lpcg_32_reserved_18_18 - reserved
8102  */
8103 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK)
8104 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK (0x80000U)
8105 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT (19U)
8106 /*! prg0_apb_clk_STOP - show clock root status, 1 means clock stopped
8107  */
8108 #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK)
8109 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK (0xFFF00000U)
8110 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT (20U)
8111 /*! LPCG_dc_lpcg_32_reserved_20_31 - reserved
8112  */
8113 #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK)
8114 /*! @} */
8115 
8116 /*! @name LPCG_DC_LPCG_36 - na */
8117 /*! @{ */
8118 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK (0x1U)
8119 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT (0U)
8120 /*! LPCG_dc_lpcg_36_reserved_0_0 - reserved
8121  */
8122 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK)
8123 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK (0x2U)
8124 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT (1U)
8125 /*! prg1_rtram_clk_SWEN - Software Enable
8126  *  0b0..Disable SW clock regardless of HWEN
8127  *  0b1..Enable SW clock gating
8128  */
8129 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK)
8130 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK (0x4U)
8131 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT (2U)
8132 /*! LPCG_dc_lpcg_36_reserved_2_2 - reserved
8133  */
8134 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK)
8135 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK (0x8U)
8136 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT (3U)
8137 /*! prg1_rtram_clk_STOP - show clock root status, 1 means clock stopped
8138  */
8139 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK)
8140 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK (0xFFF0U)
8141 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT (4U)
8142 /*! LPCG_dc_lpcg_36_reserved_4_15 - reserved
8143  */
8144 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK)
8145 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK (0x10000U)
8146 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT (16U)
8147 /*! prg1_apb_clk_HWEN - Hardware Enable
8148  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8149  *  0b1..Enable HW automatic gating
8150  */
8151 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK)
8152 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK (0x20000U)
8153 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT (17U)
8154 /*! prg1_apb_clk_SWEN - Software Enable
8155  *  0b0..Disable SW clock regardless of HWEN
8156  *  0b1..Enable SW clock gating
8157  */
8158 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK)
8159 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK (0x40000U)
8160 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT (18U)
8161 /*! LPCG_dc_lpcg_36_reserved_18_18 - reserved
8162  */
8163 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK)
8164 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK (0x80000U)
8165 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT (19U)
8166 /*! prg1_apb_clk_STOP - show clock root status, 1 means clock stopped
8167  */
8168 #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK)
8169 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK (0xFFF00000U)
8170 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT (20U)
8171 /*! LPCG_dc_lpcg_36_reserved_20_31 - reserved
8172  */
8173 #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK)
8174 /*! @} */
8175 
8176 /*! @name LPCG_DC_LPCG_40 - na */
8177 /*! @{ */
8178 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK (0x1U)
8179 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT (0U)
8180 /*! LPCG_dc_lpcg_40_reserved_0_0 - reserved
8181  */
8182 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK)
8183 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK (0x2U)
8184 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT (1U)
8185 /*! prg2_rtram_clk_SWEN - Software Enable
8186  *  0b0..Disable SW clock regardless of HWEN
8187  *  0b1..Enable SW clock gating
8188  */
8189 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK)
8190 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK (0x4U)
8191 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT (2U)
8192 /*! LPCG_dc_lpcg_40_reserved_2_2 - reserved
8193  */
8194 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK)
8195 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK (0x8U)
8196 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT (3U)
8197 /*! prg2_rtram_clk_STOP - show clock root status, 1 means clock stopped
8198  */
8199 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK)
8200 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK (0xFFF0U)
8201 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT (4U)
8202 /*! LPCG_dc_lpcg_40_reserved_4_15 - reserved
8203  */
8204 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK)
8205 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK (0x10000U)
8206 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT (16U)
8207 /*! prg2_apb_clk_HWEN - Hardware Enable
8208  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8209  *  0b1..Enable HW automatic gating
8210  */
8211 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK)
8212 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK (0x20000U)
8213 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT (17U)
8214 /*! prg2_apb_clk_SWEN - Software Enable
8215  *  0b0..Disable SW clock regardless of HWEN
8216  *  0b1..Enable SW clock gating
8217  */
8218 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK)
8219 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK (0x40000U)
8220 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT (18U)
8221 /*! LPCG_dc_lpcg_40_reserved_18_18 - reserved
8222  */
8223 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK)
8224 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK (0x80000U)
8225 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT (19U)
8226 /*! prg2_apb_clk_STOP - show clock root status, 1 means clock stopped
8227  */
8228 #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK)
8229 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK (0xFFF00000U)
8230 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT (20U)
8231 /*! LPCG_dc_lpcg_40_reserved_20_31 - reserved
8232  */
8233 #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK)
8234 /*! @} */
8235 
8236 /*! @name LPCG_DC_LPCG_44 - na */
8237 /*! @{ */
8238 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK (0xFFFFU)
8239 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT (0U)
8240 /*! LPCG_dc_lpcg_44_reserved_0_15 - reserved
8241  */
8242 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK)
8243 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK (0x10000U)
8244 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT (16U)
8245 /*! dpr1_dpr_apb_clkg_HWEN - Hardware Enable
8246  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8247  *  0b1..Enable HW automatic gating
8248  */
8249 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK)
8250 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK (0x20000U)
8251 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT (17U)
8252 /*! dpr1_dpr_apb_clkg_SWEN - Software Enable
8253  *  0b0..Disable SW clock regardless of HWEN
8254  *  0b1..Enable SW clock gating
8255  */
8256 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK)
8257 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK (0x40000U)
8258 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT (18U)
8259 /*! LPCG_dc_lpcg_44_reserved_18_18 - reserved
8260  */
8261 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK)
8262 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK (0x80000U)
8263 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT (19U)
8264 /*! dpr1_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped
8265  */
8266 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK)
8267 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK (0x100000U)
8268 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT (20U)
8269 /*! dpr1_dpr_b_clkg_HWEN - Hardware Enable
8270  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8271  *  0b1..Enable HW automatic gating
8272  */
8273 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK)
8274 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK (0x200000U)
8275 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT (21U)
8276 /*! dpr1_dpr_b_clkg_SWEN - Software Enable
8277  *  0b0..Disable SW clock regardless of HWEN
8278  *  0b1..Enable SW clock gating
8279  */
8280 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK)
8281 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK (0x400000U)
8282 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT (22U)
8283 /*! LPCG_dc_lpcg_44_reserved_22_22 - reserved
8284  */
8285 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK)
8286 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK (0x800000U)
8287 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT (23U)
8288 /*! dpr1_dpr_b_clkg_STOP - show clock root status, 1 means clock stopped
8289  */
8290 #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK)
8291 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK (0xFF000000U)
8292 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT (24U)
8293 /*! LPCG_dc_lpcg_44_reserved_24_31 - reserved
8294  */
8295 #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK)
8296 /*! @} */
8297 
8298 /*! @name LPCG_DC_LPCG_48 - na */
8299 /*! @{ */
8300 #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK (0x1U)
8301 #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT (0U)
8302 /*! LPCG_dc_lpcg_48_reserved_0_0 - reserved
8303  */
8304 #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK)
8305 #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK (0x2U)
8306 #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT (1U)
8307 /*! rtram1_rtr_clk_g_SWEN - Software Enable
8308  *  0b0..Disable SW clock regardless of HWEN
8309  *  0b1..Enable SW clock gating
8310  */
8311 #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK)
8312 #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK (0x4U)
8313 #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT (2U)
8314 /*! LPCG_dc_lpcg_48_reserved_2_2 - reserved
8315  */
8316 #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK)
8317 #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK (0x8U)
8318 #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT (3U)
8319 /*! rtram1_rtr_clk_g_STOP - show clock root status, 1 means clock stopped
8320  */
8321 #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK)
8322 #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK (0xFFFFFFF0U)
8323 #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT (4U)
8324 /*! LPCG_dc_lpcg_48_reserved_4_31 - reserved
8325  */
8326 #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK)
8327 /*! @} */
8328 
8329 /*! @name LPCG_DC_LPCG_52 - na */
8330 /*! @{ */
8331 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK (0x1U)
8332 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT (0U)
8333 /*! LPCG_dc_lpcg_52_reserved_0_0 - reserved
8334  */
8335 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK)
8336 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK (0x2U)
8337 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT (1U)
8338 /*! prg3_rtram_clk_SWEN - Software Enable
8339  *  0b0..Disable SW clock regardless of HWEN
8340  *  0b1..Enable SW clock gating
8341  */
8342 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK)
8343 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK (0x4U)
8344 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT (2U)
8345 /*! LPCG_dc_lpcg_52_reserved_2_2 - reserved
8346  */
8347 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK)
8348 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK (0x8U)
8349 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT (3U)
8350 /*! prg3_rtram_clk_STOP - show clock root status, 1 means clock stopped
8351  */
8352 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK)
8353 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK (0xFFF0U)
8354 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT (4U)
8355 /*! LPCG_dc_lpcg_52_reserved_4_15 - reserved
8356  */
8357 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK)
8358 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK (0x10000U)
8359 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT (16U)
8360 /*! prg3_apb_clk_HWEN - Hardware Enable
8361  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8362  *  0b1..Enable HW automatic gating
8363  */
8364 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK)
8365 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK (0x20000U)
8366 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT (17U)
8367 /*! prg3_apb_clk_SWEN - Software Enable
8368  *  0b0..Disable SW clock regardless of HWEN
8369  *  0b1..Enable SW clock gating
8370  */
8371 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK)
8372 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK (0x40000U)
8373 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT (18U)
8374 /*! LPCG_dc_lpcg_52_reserved_18_18 - reserved
8375  */
8376 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK)
8377 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK (0x80000U)
8378 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT (19U)
8379 /*! prg3_apb_clk_STOP - show clock root status, 1 means clock stopped
8380  */
8381 #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK)
8382 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK (0xFFF00000U)
8383 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT (20U)
8384 /*! LPCG_dc_lpcg_52_reserved_20_31 - reserved
8385  */
8386 #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK)
8387 /*! @} */
8388 
8389 /*! @name LPCG_DC_LPCG_56 - na */
8390 /*! @{ */
8391 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK (0x1U)
8392 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT (0U)
8393 /*! LPCG_dc_lpcg_56_reserved_0_0 - reserved
8394  */
8395 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK)
8396 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK (0x2U)
8397 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT (1U)
8398 /*! prg4_rtram_clk_SWEN - Software Enable
8399  *  0b0..Disable SW clock regardless of HWEN
8400  *  0b1..Enable SW clock gating
8401  */
8402 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK)
8403 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK (0x4U)
8404 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT (2U)
8405 /*! LPCG_dc_lpcg_56_reserved_2_2 - reserved
8406  */
8407 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK)
8408 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK (0x8U)
8409 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT (3U)
8410 /*! prg4_rtram_clk_STOP - show clock root status, 1 means clock stopped
8411  */
8412 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK)
8413 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK (0xFFF0U)
8414 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT (4U)
8415 /*! LPCG_dc_lpcg_56_reserved_4_15 - reserved
8416  */
8417 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK)
8418 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK (0x10000U)
8419 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT (16U)
8420 /*! prg4_apb_clk_HWEN - Hardware Enable
8421  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8422  *  0b1..Enable HW automatic gating
8423  */
8424 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK)
8425 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK (0x20000U)
8426 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT (17U)
8427 /*! prg4_apb_clk_SWEN - Software Enable
8428  *  0b0..Disable SW clock regardless of HWEN
8429  *  0b1..Enable SW clock gating
8430  */
8431 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK)
8432 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK (0x40000U)
8433 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT (18U)
8434 /*! LPCG_dc_lpcg_56_reserved_18_18 - reserved
8435  */
8436 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK)
8437 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK (0x80000U)
8438 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT (19U)
8439 /*! prg4_apb_clk_STOP - show clock root status, 1 means clock stopped
8440  */
8441 #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK)
8442 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK (0xFFF00000U)
8443 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT (20U)
8444 /*! LPCG_dc_lpcg_56_reserved_20_31 - reserved
8445  */
8446 #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK)
8447 /*! @} */
8448 
8449 /*! @name LPCG_DC_LPCG_60 - na */
8450 /*! @{ */
8451 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK (0x1U)
8452 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT (0U)
8453 /*! LPCG_dc_lpcg_60_reserved_0_0 - reserved
8454  */
8455 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK)
8456 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK (0x2U)
8457 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT (1U)
8458 /*! prg5_rtram_clk_SWEN - Software Enable
8459  *  0b0..Disable SW clock regardless of HWEN
8460  *  0b1..Enable SW clock gating
8461  */
8462 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK)
8463 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK (0x4U)
8464 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT (2U)
8465 /*! LPCG_dc_lpcg_60_reserved_2_2 - reserved
8466  */
8467 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK)
8468 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK (0x8U)
8469 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT (3U)
8470 /*! prg5_rtram_clk_STOP - show clock root status, 1 means clock stopped
8471  */
8472 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK)
8473 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK (0xFFF0U)
8474 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT (4U)
8475 /*! LPCG_dc_lpcg_60_reserved_4_15 - reserved
8476  */
8477 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK)
8478 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK (0x10000U)
8479 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT (16U)
8480 /*! prg5_apb_clk_HWEN - Hardware Enable
8481  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8482  *  0b1..Enable HW automatic gating
8483  */
8484 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK)
8485 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK (0x20000U)
8486 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT (17U)
8487 /*! prg5_apb_clk_SWEN - Software Enable
8488  *  0b0..Disable SW clock regardless of HWEN
8489  *  0b1..Enable SW clock gating
8490  */
8491 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK)
8492 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK (0x40000U)
8493 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT (18U)
8494 /*! LPCG_dc_lpcg_60_reserved_18_18 - reserved
8495  */
8496 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK)
8497 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK (0x80000U)
8498 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT (19U)
8499 /*! prg5_apb_clk_STOP - show clock root status, 1 means clock stopped
8500  */
8501 #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK)
8502 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK (0xFFF00000U)
8503 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT (20U)
8504 /*! LPCG_dc_lpcg_60_reserved_20_31 - reserved
8505  */
8506 #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK)
8507 /*! @} */
8508 
8509 /*! @name LPCG_DC_LPCG_64 - na */
8510 /*! @{ */
8511 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK (0x1U)
8512 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT (0U)
8513 /*! LPCG_dc_lpcg_64_reserved_0_0 - reserved
8514  */
8515 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK)
8516 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK (0x2U)
8517 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT (1U)
8518 /*! prg6_rtram_clk_SWEN - Software Enable
8519  *  0b0..Disable SW clock regardless of HWEN
8520  *  0b1..Enable SW clock gating
8521  */
8522 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK)
8523 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK (0x4U)
8524 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT (2U)
8525 /*! LPCG_dc_lpcg_64_reserved_2_2 - reserved
8526  */
8527 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK)
8528 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK (0x8U)
8529 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT (3U)
8530 /*! prg6_rtram_clk_STOP - show clock root status, 1 means clock stopped
8531  */
8532 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK)
8533 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK (0xFFF0U)
8534 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT (4U)
8535 /*! LPCG_dc_lpcg_64_reserved_4_15 - reserved
8536  */
8537 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK)
8538 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK (0x10000U)
8539 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT (16U)
8540 /*! prg6_apb_clk_HWEN - Hardware Enable
8541  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8542  *  0b1..Enable HW automatic gating
8543  */
8544 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK)
8545 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK (0x20000U)
8546 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT (17U)
8547 /*! prg6_apb_clk_SWEN - Software Enable
8548  *  0b0..Disable SW clock regardless of HWEN
8549  *  0b1..Enable SW clock gating
8550  */
8551 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK)
8552 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK (0x40000U)
8553 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT (18U)
8554 /*! LPCG_dc_lpcg_64_reserved_18_18 - reserved
8555  */
8556 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK)
8557 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK (0x80000U)
8558 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT (19U)
8559 /*! prg6_apb_clk_STOP - show clock root status, 1 means clock stopped
8560  */
8561 #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK)
8562 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK (0xFFF00000U)
8563 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT (20U)
8564 /*! LPCG_dc_lpcg_64_reserved_20_31 - reserved
8565  */
8566 #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK)
8567 /*! @} */
8568 
8569 /*! @name LPCG_DC_LPCG_68 - na */
8570 /*! @{ */
8571 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK (0x1U)
8572 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT (0U)
8573 /*! LPCG_dc_lpcg_68_reserved_0_0 - reserved
8574  */
8575 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK)
8576 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK (0x2U)
8577 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT (1U)
8578 /*! prg7_rtram_clk_SWEN - Software Enable
8579  *  0b0..Disable SW clock regardless of HWEN
8580  *  0b1..Enable SW clock gating
8581  */
8582 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK)
8583 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK (0x4U)
8584 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT (2U)
8585 /*! LPCG_dc_lpcg_68_reserved_2_2 - reserved
8586  */
8587 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK)
8588 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK (0x8U)
8589 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT (3U)
8590 /*! prg7_rtram_clk_STOP - show clock root status, 1 means clock stopped
8591  */
8592 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK)
8593 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK (0xFFF0U)
8594 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT (4U)
8595 /*! LPCG_dc_lpcg_68_reserved_4_15 - reserved
8596  */
8597 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK)
8598 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK (0x10000U)
8599 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT (16U)
8600 /*! prg7_apb_clk_HWEN - Hardware Enable
8601  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8602  *  0b1..Enable HW automatic gating
8603  */
8604 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK)
8605 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK (0x20000U)
8606 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT (17U)
8607 /*! prg7_apb_clk_SWEN - Software Enable
8608  *  0b0..Disable SW clock regardless of HWEN
8609  *  0b1..Enable SW clock gating
8610  */
8611 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK)
8612 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK (0x40000U)
8613 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT (18U)
8614 /*! LPCG_dc_lpcg_68_reserved_18_18 - reserved
8615  */
8616 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK)
8617 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK (0x80000U)
8618 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT (19U)
8619 /*! prg7_apb_clk_STOP - show clock root status, 1 means clock stopped
8620  */
8621 #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK)
8622 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK (0xFFF00000U)
8623 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT (20U)
8624 /*! LPCG_dc_lpcg_68_reserved_20_31 - reserved
8625  */
8626 #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK)
8627 /*! @} */
8628 
8629 /*! @name LPCG_DC_LPCG_72 - na */
8630 /*! @{ */
8631 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK (0x1U)
8632 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT (0U)
8633 /*! LPCG_dc_lpcg_72_reserved_0_0 - reserved
8634  */
8635 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK)
8636 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK (0x2U)
8637 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT (1U)
8638 /*! prg8_rtram_clk_SWEN - Software Enable
8639  *  0b0..Disable SW clock regardless of HWEN
8640  *  0b1..Enable SW clock gating
8641  */
8642 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK)
8643 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK (0x4U)
8644 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT (2U)
8645 /*! LPCG_dc_lpcg_72_reserved_2_2 - reserved
8646  */
8647 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK)
8648 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK (0x8U)
8649 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT (3U)
8650 /*! prg8_rtram_clk_STOP - show clock root status, 1 means clock stopped
8651  */
8652 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK)
8653 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK (0xFFF0U)
8654 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT (4U)
8655 /*! LPCG_dc_lpcg_72_reserved_4_15 - reserved
8656  */
8657 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK)
8658 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK (0x10000U)
8659 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT (16U)
8660 /*! prg8_apb_clk_HWEN - Hardware Enable
8661  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8662  *  0b1..Enable HW automatic gating
8663  */
8664 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK)
8665 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK (0x20000U)
8666 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT (17U)
8667 /*! prg8_apb_clk_SWEN - Software Enable
8668  *  0b0..Disable SW clock regardless of HWEN
8669  *  0b1..Enable SW clock gating
8670  */
8671 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK)
8672 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK (0x40000U)
8673 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT (18U)
8674 /*! LPCG_dc_lpcg_72_reserved_18_18 - reserved
8675  */
8676 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK)
8677 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK (0x80000U)
8678 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT (19U)
8679 /*! prg8_apb_clk_STOP - show clock root status, 1 means clock stopped
8680  */
8681 #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK)
8682 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK (0xFFF00000U)
8683 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT (20U)
8684 /*! LPCG_dc_lpcg_72_reserved_20_31 - reserved
8685  */
8686 #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK)
8687 /*! @} */
8688 
8689 
8690 /*!
8691  * @}
8692  */ /* end of group DC_LPCG_Register_Masks */
8693 
8694 
8695 /* DC_LPCG - Peripheral instance base addresses */
8696 /** Peripheral DC__LPCG_DSP0_CLK base address */
8697 #define DC__LPCG_DSP0_CLK_BASE                   (0x56010000u)
8698 /** Peripheral DC__LPCG_DSP0_CLK base pointer */
8699 #define DC__LPCG_DSP0_CLK                        ((DC_LPCG_Type *)DC__LPCG_DSP0_CLK_BASE)
8700 /** Array initializer of DC_LPCG peripheral base addresses */
8701 #define DC_LPCG_BASE_ADDRS                       { DC__LPCG_DSP0_CLK_BASE }
8702 /** Array initializer of DC_LPCG peripheral base pointers */
8703 #define DC_LPCG_BASE_PTRS                        { DC__LPCG_DSP0_CLK }
8704 
8705 /*!
8706  * @}
8707  */ /* end of group DC_LPCG_Peripheral_Access_Layer */
8708 
8709 
8710 /* ----------------------------------------------------------------------------
8711    -- DDRC Peripheral Access Layer
8712    ---------------------------------------------------------------------------- */
8713 
8714 /*!
8715  * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer
8716  * @{
8717  */
8718 
8719 /** DDRC - Register Layout Typedef */
8720 typedef struct {
8721   __IO uint32_t MSTR;                              /**< Master Register0, offset: 0x0 */
8722   __I  uint32_t STAT;                              /**< Operating Mode Status Register, offset: 0x4 */
8723   __IO uint32_t MSTR1;                             /**< Operating Mode Status Register, offset: 0x8 */
8724   __IO uint32_t MRCTRL3;                           /**< Operating Mode Status Register, offset: 0xC */
8725   __IO uint32_t MRCTRL0;                           /**< Mode Register Read/Write Control Register 0., offset: 0x10 */
8726   __IO uint32_t MRCTRL1;                           /**< Mode Register Read/Write Control Register 1, offset: 0x14 */
8727   __I  uint32_t MRSTAT;                            /**< Mode Register Read/Write Status Register, offset: 0x18 */
8728   __IO uint32_t MRCTRL2;                           /**< Mode Register Read/Write Control Register 2, offset: 0x1C */
8729   __IO uint32_t DERATEEN;                          /**< Temperature Derate Enable Register, offset: 0x20 */
8730   __IO uint32_t DERATEINT;                         /**< Temperature Derate Interval Register, offset: 0x24 */
8731        uint8_t RESERVED_0[8];
8732   __IO uint32_t PWRCTL;                            /**< Low Power Control Register, offset: 0x30 */
8733   __IO uint32_t PWRTMG;                            /**< Low Power Timing Register, offset: 0x34 */
8734   __IO uint32_t HWLPCTL;                           /**< Hardware Low Power Control Register, offset: 0x38 */
8735        uint8_t RESERVED_1[20];
8736   __IO uint32_t RFSHCTL0;                          /**< Refresh Control Register 0, offset: 0x50 */
8737   __IO uint32_t RFSHCTL1;                          /**< Refresh Control Register 1, offset: 0x54 */
8738        uint8_t RESERVED_2[8];
8739   __IO uint32_t RFSHCTL3;                          /**< Refresh Control Register 3, offset: 0x60 */
8740   __IO uint32_t RFSHTMG;                           /**< Refresh Timing Register, offset: 0x64 */
8741        uint8_t RESERVED_3[104];
8742   __IO uint32_t INIT0;                             /**< SDRAM Initialization Register 0, offset: 0xD0 */
8743   __IO uint32_t INIT1;                             /**< SDRAM Initialization Register 1, offset: 0xD4 */
8744   __IO uint32_t INIT2;                             /**< SDRAM Initialization Register 2, offset: 0xD8 */
8745   __IO uint32_t INIT3;                             /**< SDRAM Initialization Register 3, offset: 0xDC */
8746   __IO uint32_t INIT4;                             /**< SDRAM Initialization Register 4, offset: 0xE0 */
8747   __IO uint32_t INIT5;                             /**< SDRAM Initialization Register 5, offset: 0xE4 */
8748   __IO uint32_t INIT6;                             /**< SDRAM Initialization Register 6, offset: 0xE8 */
8749   __IO uint32_t INIT7;                             /**< SDRAM Initialization Register 7, offset: 0xEC */
8750   __IO uint32_t DIMMCTL;                           /**< DIMM Control Register, offset: 0xF0 */
8751   __IO uint32_t RANKCTL;                           /**< Rank Control Register, offset: 0xF4 */
8752        uint8_t RESERVED_4[8];
8753   __IO uint32_t DRAMTMG0;                          /**< SDRAM Timing Register 0, offset: 0x100 */
8754   __IO uint32_t DRAMTMG1;                          /**< SDRAM Timing Register 1, offset: 0x104 */
8755   __IO uint32_t DRAMTMG2;                          /**< SDRAM Timing Register 2, offset: 0x108 */
8756   __IO uint32_t DRAMTMG3;                          /**< SDRAM Timing Register 3, offset: 0x10C */
8757   __IO uint32_t DRAMTMG4;                          /**< SDRAM Timing Register 4, offset: 0x110 */
8758   __IO uint32_t DRAMTMG5;                          /**< SDRAM Timing Register 5, offset: 0x114 */
8759   __IO uint32_t DRAMTMG6;                          /**< SDRAM Timing Register 6, offset: 0x118 */
8760   __IO uint32_t DRAMTMG7;                          /**< SDRAM Timing Register 7, offset: 0x11C */
8761   __IO uint32_t DRAMTMG8;                          /**< SDRAM Timing Register 8, offset: 0x120 */
8762   __IO uint32_t DRAMTMG9;                          /**< SDRAM Timing Register 9, offset: 0x124 */
8763   __IO uint32_t DRAMTMG10;                         /**< SDRAM Timing Register 10, offset: 0x128 */
8764   __IO uint32_t DRAMTMG11;                         /**< SDRAM Timing Register 11, offset: 0x12C */
8765   __IO uint32_t DRAMTMG12;                         /**< SDRAM Timing Register 12, offset: 0x130 */
8766   __IO uint32_t DRAMTMG13;                         /**< SDRAM Timing Register 13, offset: 0x134 */
8767   __IO uint32_t DRAMTMG14;                         /**< SDRAM Timing Register 14, offset: 0x138 */
8768   __IO uint32_t DRAMTMG15;                         /**< SDRAM Timing Register 15, offset: 0x13C */
8769        uint8_t RESERVED_5[64];
8770   __IO uint32_t ZQCTL0;                            /**< ZQ Control Register 0, offset: 0x180 */
8771   __IO uint32_t ZQCTL1;                            /**< ZQ Control Register 1, offset: 0x184 */
8772   __IO uint32_t ZQCTL2;                            /**< ZQ Control Register 2, offset: 0x188 */
8773   __I  uint32_t ZQSTAT;                            /**< ZQ Status Register, offset: 0x18C */
8774   __IO uint32_t DFITMG0;                           /**< DFI Timing Register 0, offset: 0x190 */
8775   __IO uint32_t DFITMG1;                           /**< DFI Timing Register 1, offset: 0x194 */
8776   __IO uint32_t DFILPCFG0;                         /**< DFI Low Power Configuration Register 0, offset: 0x198 */
8777   __IO uint32_t DFILPCFG1;                         /**< DFI Low Power Configuration Register 1, offset: 0x19C */
8778   __IO uint32_t DFIUPD0;                           /**< DFI Update Register 0, offset: 0x1A0 */
8779   __IO uint32_t DFIUPD1;                           /**< DFI Update Register 1, offset: 0x1A4 */
8780   __IO uint32_t DFIUPD2;                           /**< DFI Update Register 2, offset: 0x1A8 */
8781        uint8_t RESERVED_6[4];
8782   __IO uint32_t DFIMISC;                           /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
8783   __IO uint32_t DFITMG2;                           /**< DFI Timing Register 2, offset: 0x1B4 */
8784   __IO uint32_t DFITMG3;                           /**< DFI Timing Register 3, offset: 0x1B8 */
8785   __I  uint32_t DFISTAT;                           /**< DFI Status Register, offset: 0x1BC */
8786   __IO uint32_t DBICTL;                            /**< DM/DBI Control Register, offset: 0x1C0 */
8787        uint8_t RESERVED_7[60];
8788   __IO uint32_t ADDRMAP0;                          /**< Address Map Register 0, offset: 0x200 */
8789   __IO uint32_t ADDRMAP1;                          /**< Address Map Register 1, offset: 0x204 */
8790   __IO uint32_t ADDRMAP2;                          /**< Address Map Register 2, offset: 0x208 */
8791   __IO uint32_t ADDRMAP3;                          /**< Address Map Register 3, offset: 0x20C */
8792   __IO uint32_t ADDRMAP4;                          /**< Address Map Register 4, offset: 0x210 */
8793   __IO uint32_t ADDRMAP5;                          /**< Address Map Register 5, offset: 0x214 */
8794   __IO uint32_t ADDRMAP6;                          /**< Address Map Register 6, offset: 0x218 */
8795   __IO uint32_t ADDRMAP7;                          /**< Address Map Register 7, offset: 0x21C */
8796   __IO uint32_t ADDRMAP8;                          /**< Address Map Register 8, offset: 0x220 */
8797   __IO uint32_t ADDRMAP9;                          /**< Address Map Register 9, offset: 0x224 */
8798   __IO uint32_t ADDRMAP10;                         /**< Address Map Register 10, offset: 0x228 */
8799   __IO uint32_t ADDRMAP11;                         /**< Address Map Register 11, offset: 0x22C */
8800        uint8_t RESERVED_8[16];
8801   __IO uint32_t ODTCFG;                            /**< ODT Configuration Register, offset: 0x240 */
8802   __IO uint32_t ODTMAP;                            /**< ODT/Rank Map Register, offset: 0x244 */
8803        uint8_t RESERVED_9[8];
8804   __IO uint32_t SCHED;                             /**< Scheduler Control Register, offset: 0x250 */
8805   __IO uint32_t SCHED1;                            /**< Scheduler Control Register 1, offset: 0x254 */
8806        uint8_t RESERVED_10[4];
8807   __IO uint32_t PERFHPR1;                          /**< High Priority Read CAM Register 1, offset: 0x25C */
8808        uint8_t RESERVED_11[4];
8809   __IO uint32_t PERFLPR1;                          /**< Low Priority Read CAM Register 1, offset: 0x264 */
8810        uint8_t RESERVED_12[4];
8811   __IO uint32_t PERFWR1;                           /**< Write CAM Register 1, offset: 0x26C */
8812        uint8_t RESERVED_13[144];
8813   __IO uint32_t DBG0;                              /**< Debug Register 0, offset: 0x300 */
8814   __IO uint32_t DBG1;                              /**< Debug Register 1, offset: 0x304 */
8815   __I  uint32_t DBGCAM;                            /**< CAM Debug Register, offset: 0x308 */
8816   __IO uint32_t DBGCMD;                            /**< Command Debug Register, offset: 0x30C */
8817   __I  uint32_t DBGSTAT;                           /**< Status Debug Register, offset: 0x310 */
8818        uint8_t RESERVED_14[12];
8819   __IO uint32_t SWCTL;                             /**< Software Register Programming Control Enable, offset: 0x320 */
8820   __I  uint32_t SWSTAT;                            /**< Software Register Programming Control Status, offset: 0x324 */
8821        uint8_t RESERVED_15[68];
8822   __IO uint32_t POISONCFG;                         /**< AXI Poison Configuration Register., offset: 0x36C */
8823   __I  uint32_t POISONSTAT;                        /**< AXI Poison Status Register, offset: 0x370 */
8824        uint8_t RESERVED_16[136];
8825   __I  uint32_t PSTAT;                             /**< Port Status Register, offset: 0x3FC */
8826   __IO uint32_t PCCFG;                             /**< Port Common Configuration Register, offset: 0x400 */
8827   __IO uint32_t PCFGR_0;                           /**< Port n Configuration Read Register, offset: 0x404 */
8828   __IO uint32_t PCFGW_0;                           /**< Port n Configuration Write Register, offset: 0x408 */
8829        uint8_t RESERVED_17[132];
8830   __IO uint32_t PCTRL_0;                           /**< Port n Control Register, offset: 0x490 */
8831   __IO uint32_t PCFGQOS0_0;                        /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
8832   __IO uint32_t PCFGQOS1_0;                        /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
8833   __IO uint32_t PCFGWQOS0_0;                       /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
8834   __IO uint32_t PCFGWQOS1_0;                       /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
8835        uint8_t RESERVED_18[7036];
8836   __IO uint32_t DERATEEN_SHADOW;                   /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */
8837   __IO uint32_t DERATEINT_SHADOW;                  /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */
8838        uint8_t RESERVED_19[40];
8839   __IO uint32_t RFSHCTL0_SHADOW;                   /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */
8840        uint8_t RESERVED_20[16];
8841   __IO uint32_t RFSHTMG_SHADOW;                    /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */
8842        uint8_t RESERVED_21[116];
8843   __IO uint32_t INIT3_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */
8844   __IO uint32_t INIT4_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */
8845        uint8_t RESERVED_22[4];
8846   __IO uint32_t INIT6_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */
8847   __IO uint32_t INIT7_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */
8848        uint8_t RESERVED_23[16];
8849   __IO uint32_t DRAMTMG0_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */
8850   __IO uint32_t DRAMTMG1_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */
8851   __IO uint32_t DRAMTMG2_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */
8852   __IO uint32_t DRAMTMG3_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */
8853   __IO uint32_t DRAMTMG4_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */
8854   __IO uint32_t DRAMTMG5_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */
8855   __IO uint32_t DRAMTMG6_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */
8856   __IO uint32_t DRAMTMG7_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */
8857   __IO uint32_t DRAMTMG8_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */
8858   __IO uint32_t DRAMTMG9_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */
8859   __IO uint32_t DRAMTMG10_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */
8860   __IO uint32_t DRAMTMG11_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */
8861   __IO uint32_t DRAMTMG12_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */
8862   __IO uint32_t DRAMTMG13_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */
8863   __IO uint32_t DRAMTMG14_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */
8864   __IO uint32_t DRAMTMG15_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */
8865        uint8_t RESERVED_24[64];
8866   __IO uint32_t ZQCTL0_SHADOW;                     /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */
8867        uint8_t RESERVED_25[12];
8868   __IO uint32_t DFITMG0_SHADOW;                    /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */
8869   __IO uint32_t DFITMG1_SHADOW;                    /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */
8870        uint8_t RESERVED_26[28];
8871   __IO uint32_t DFITMG2_SHADOW;                    /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */
8872   __IO uint32_t DFITMG3_SHADOW;                    /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */
8873        uint8_t RESERVED_27[132];
8874   __IO uint32_t ODTCFG_SHADOW;                     /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */
8875 } DDRC_Type;
8876 
8877 /* ----------------------------------------------------------------------------
8878    -- DDRC Register Masks
8879    ---------------------------------------------------------------------------- */
8880 
8881 /*!
8882  * @addtogroup DDRC_Register_Masks DDRC Register Masks
8883  * @{
8884  */
8885 
8886 /*! @name MSTR - Master Register0 */
8887 /*! @{ */
8888 #define DDRC_MSTR_ddr3_MASK                      (0x1U)
8889 #define DDRC_MSTR_ddr3_SHIFT                     (0U)
8890 /*! ddr3 - Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only
8891  *    present in designs that support DDR3.
8892  */
8893 #define DDRC_MSTR_ddr3(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr3_SHIFT)) & DDRC_MSTR_ddr3_MASK)
8894 #define DDRC_MSTR_lpddr2_MASK                    (0x4U)
8895 #define DDRC_MSTR_lpddr2_SHIFT                   (2U)
8896 /*! lpddr2 - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use
8897  *    Present only in designs configured to support LPDDR2.
8898  */
8899 #define DDRC_MSTR_lpddr2(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr2_SHIFT)) & DDRC_MSTR_lpddr2_MASK)
8900 #define DDRC_MSTR_lpddr3_MASK                    (0x8U)
8901 #define DDRC_MSTR_lpddr3_SHIFT                   (3U)
8902 /*! lpddr3 - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use
8903  *    Present only in designs configured to support LPDDR3.
8904  */
8905 #define DDRC_MSTR_lpddr3(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr3_SHIFT)) & DDRC_MSTR_lpddr3_MASK)
8906 #define DDRC_MSTR_ddr4_MASK                      (0x10U)
8907 #define DDRC_MSTR_ddr4_SHIFT                     (4U)
8908 /*! ddr4 - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present
8909  *    only in designs configured to support DDR4.
8910  */
8911 #define DDRC_MSTR_ddr4(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr4_SHIFT)) & DDRC_MSTR_ddr4_MASK)
8912 #define DDRC_MSTR_lpddr4_MASK                    (0x20U)
8913 #define DDRC_MSTR_lpddr4_SHIFT                   (5U)
8914 /*! lpddr4 - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use
8915  *    Present only in designs configured to support LPDDR4.
8916  */
8917 #define DDRC_MSTR_lpddr4(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr4_SHIFT)) & DDRC_MSTR_lpddr4_MASK)
8918 #define DDRC_MSTR_burstchop_MASK                 (0x200U)
8919 #define DDRC_MSTR_burstchop_SHIFT                (9U)
8920 /*! burstchop - When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for Reads
8921  *    is exercised only in HIF configurations (DDRC_INCL_ARB not set) and if in full bus width mode
8922  *    (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is
8923  *    exercised only if Partial Writes enabled (DDRC_PARTIAL_WR=1) and if CRC is disabled
8924  *    (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1),
8925  *    burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported.
8926  */
8927 #define DDRC_MSTR_burstchop(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burstchop_SHIFT)) & DDRC_MSTR_burstchop_MASK)
8928 #define DDRC_MSTR_en_2t_timing_mode_MASK         (0x400U)
8929 #define DDRC_MSTR_en_2t_timing_mode_SHIFT        (10U)
8930 /*! en_2t_timing_mode - If 1, then DDRC uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all
8931  *    command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is
8932  *    asserted on the second cycle of the command Note: 2T timing is not supported in
8933  *    LPDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE
8934  *    is set Note: 2T timing is not supported in DDR4 geardown mode. Note: 2T timing is not supported
8935  *    in Shared-AC dual channel mode and the register value is don't care.
8936  */
8937 #define DDRC_MSTR_en_2t_timing_mode(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_MSTR_en_2t_timing_mode_MASK)
8938 #define DDRC_MSTR_geardown_mode_MASK             (0x800U)
8939 #define DDRC_MSTR_geardown_mode_SHIFT            (11U)
8940 /*! geardown_mode - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in
8941  *    normal mode (1N). This register can be changed, only when the Controller is in self-refresh
8942  *    mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported
8943  *    if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported
8944  *    if the configuration parameter DDRC_SHARED_AC is set (in Shared-AC mode) and the register value
8945  *    is don't care
8946  */
8947 #define DDRC_MSTR_geardown_mode(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_geardown_mode_SHIFT)) & DDRC_MSTR_geardown_mode_MASK)
8948 #define DDRC_MSTR_data_bus_width_MASK            (0x3000U)
8949 #define DDRC_MSTR_data_bus_width_SHIFT           (12U)
8950 /*! data_bus_width - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus
8951  *    width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 -
8952  *    Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a
8953  *    multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple
8954  *    of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus
8955  *    width (excluding any ECC width).
8956  */
8957 #define DDRC_MSTR_data_bus_width(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_data_bus_width_SHIFT)) & DDRC_MSTR_data_bus_width_MASK)
8958 #define DDRC_MSTR_dll_off_mode_MASK              (0x8000U)
8959 #define DDRC_MSTR_dll_off_mode_SHIFT             (15U)
8960 /*! dll_off_mode - Set to 1 when the DDRC and DRAM has to be put in DLL-off mode for low frequency
8961  *    operation. Set to 0 to put DDRC and DRAM in DLL-on mode for normal frequency operation. If DDR4
8962  *    CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not
8963  *    supported, and this bit must be set to '0'.
8964  */
8965 #define DDRC_MSTR_dll_off_mode(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_dll_off_mode_SHIFT)) & DDRC_MSTR_dll_off_mode_MASK)
8966 #define DDRC_MSTR_burst_rdwr_MASK                (0xF0000U)
8967 #define DDRC_MSTR_burst_rdwr_SHIFT               (16U)
8968 /*! burst_rdwr - SDRAM burst length used
8969  *  0b0001..Burst length of 2 (only supported for mDDR)
8970  *  0b0010..Burst length of 4
8971  *  0b0100..Burst length of 8
8972  *  0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
8973  */
8974 #define DDRC_MSTR_burst_rdwr(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burst_rdwr_SHIFT)) & DDRC_MSTR_burst_rdwr_MASK)
8975 #define DDRC_MSTR_frequency_ratio_MASK           (0x400000U)
8976 #define DDRC_MSTR_frequency_ratio_SHIFT          (22U)
8977 /*! frequency_ratio - Selects the Frequency Ratio
8978  *  0b0..1:2 Mode
8979  *  0b1..1:1 Mode
8980  */
8981 #define DDRC_MSTR_frequency_ratio(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_ratio_SHIFT)) & DDRC_MSTR_frequency_ratio_MASK)
8982 #define DDRC_MSTR_active_ranks_MASK              (0x3000000U)
8983 #define DDRC_MSTR_active_ranks_SHIFT             (24U)
8984 /*! active_ranks - Only present for multi-rank configurations. Each bit represents one rank. For
8985  *    two-rank configurations, only bits[25:24] are present.
8986  */
8987 #define DDRC_MSTR_active_ranks(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_active_ranks_SHIFT)) & DDRC_MSTR_active_ranks_MASK)
8988 #define DDRC_MSTR_frequency_mode_MASK            (0x20000000U)
8989 #define DDRC_MSTR_frequency_mode_SHIFT           (29U)
8990 /*! frequency_mode - Choose which registers are used.
8991  *  0b0..Original Registers
8992  *  0b1..Shadow Registers
8993  */
8994 #define DDRC_MSTR_frequency_mode(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_mode_SHIFT)) & DDRC_MSTR_frequency_mode_MASK)
8995 #define DDRC_MSTR_device_config_MASK             (0xC0000000U)
8996 #define DDRC_MSTR_device_config_SHIFT            (30U)
8997 /*! device_config - Indicates the configuration of the device used in the system.
8998  *  0b00..x4 device
8999  *  0b01..x8 device
9000  *  0b10..x16 device
9001  *  0b11..x32 device
9002  */
9003 #define DDRC_MSTR_device_config(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_device_config_SHIFT)) & DDRC_MSTR_device_config_MASK)
9004 /*! @} */
9005 
9006 /*! @name STAT - Operating Mode Status Register */
9007 /*! @{ */
9008 #define DDRC_STAT_operating_mode_MASK            (0x7U)
9009 #define DDRC_STAT_operating_mode_SHIFT           (0U)
9010 /*! operating_mode - Operating mode
9011  */
9012 #define DDRC_STAT_operating_mode(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_operating_mode_SHIFT)) & DDRC_STAT_operating_mode_MASK)
9013 #define DDRC_STAT_selfref_type_MASK              (0x30U)
9014 #define DDRC_STAT_selfref_type_SHIFT             (4U)
9015 /*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if
9016  *    it was under Automatic Self Refresh control only or not.
9017  *  0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by
9018  *        CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is
9019  *        in-progress.
9020  *  0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self
9021  *        Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.
9022  *  0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under
9023  *        Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software
9024  *        (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity
9025  */
9026 #define DDRC_STAT_selfref_type(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_type_SHIFT)) & DDRC_STAT_selfref_type_MASK)
9027 #define DDRC_STAT_selfref_state_MASK             (0x300U)
9028 #define DDRC_STAT_selfref_state_SHIFT            (8U)
9029 /*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state
9030  *    for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
9031  *  0b00..SDRAM is not in Self Refresh.
9032  *  0b01..Self refresh 1
9033  *  0b10..Self refresh power down
9034  *  0b11..Self refresh
9035  */
9036 #define DDRC_STAT_selfref_state(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_state_SHIFT)) & DDRC_STAT_selfref_state_MASK)
9037 /*! @} */
9038 
9039 /*! @name MSTR1 - Operating Mode Status Register */
9040 /*! @{ */
9041 #define DDRC_MSTR1_rank_tmgreg_sel_MASK          (0x3U)
9042 #define DDRC_MSTR1_rank_tmgreg_sel_SHIFT         (0U)
9043 /*! rank_tmgreg_sel - rank_tmgreg_sel
9044  *  0b00..USE DRAMTMGx registers for the rank
9045  *  0b01..USE MRAMTMGx registers for the rank
9046  */
9047 #define DDRC_MSTR1_rank_tmgreg_sel(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_rank_tmgreg_sel_SHIFT)) & DDRC_MSTR1_rank_tmgreg_sel_MASK)
9048 #define DDRC_MSTR1_alt_addrmap_en_MASK           (0x10000U)
9049 #define DDRC_MSTR1_alt_addrmap_en_SHIFT          (16U)
9050 /*! alt_addrmap_en - Enable Alternative Address Map
9051  *  0b0..Disable Alternative Address Map
9052  *  0b1..Enable Alternative Address Map
9053  */
9054 #define DDRC_MSTR1_alt_addrmap_en(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_alt_addrmap_en_SHIFT)) & DDRC_MSTR1_alt_addrmap_en_MASK)
9055 /*! @} */
9056 
9057 /*! @name MRCTRL3 - Operating Mode Status Register */
9058 /*! @{ */
9059 #define DDRC_MRCTRL3_mr_rank_sel_MASK            (0x3U)
9060 #define DDRC_MRCTRL3_mr_rank_sel_SHIFT           (0U)
9061 /*! mr_rank_sel - mr_rank_sel
9062  */
9063 #define DDRC_MRCTRL3_mr_rank_sel(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_mr_rank_sel_SHIFT)) & DDRC_MRCTRL3_mr_rank_sel_MASK)
9064 /*! @} */
9065 
9066 /*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */
9067 /*! @{ */
9068 #define DDRC_MRCTRL0_mr_type_MASK                (0x1U)
9069 #define DDRC_MRCTRL0_mr_type_SHIFT               (0U)
9070 /*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
9071  *  0b0..Write
9072  *  0b1..Read
9073  */
9074 #define DDRC_MRCTRL0_mr_type(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_type_SHIFT)) & DDRC_MRCTRL0_mr_type_MASK)
9075 #define DDRC_MRCTRL0_mpr_en_MASK                 (0x2U)
9076 #define DDRC_MRCTRL0_mpr_en_SHIFT                (1U)
9077 /*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
9078  *  0b0..MRS
9079  *  0b1..WR/RD for MPR
9080  */
9081 #define DDRC_MRCTRL0_mpr_en(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mpr_en_SHIFT)) & DDRC_MRCTRL0_mpr_en_MASK)
9082 #define DDRC_MRCTRL0_pda_en_MASK                 (0x4U)
9083 #define DDRC_MRCTRL0_pda_en_SHIFT                (2U)
9084 /*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when
9085  *    pba_mode=1, PBA access is initiated instead of PDA access.
9086  *  0b0..MRS
9087  *  0b1..MRS in Per DRAM Addressability
9088  */
9089 #define DDRC_MRCTRL0_pda_en(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pda_en_SHIFT)) & DDRC_MRCTRL0_pda_en_MASK)
9090 #define DDRC_MRCTRL0_sw_init_int_MASK            (0x8U)
9091 #define DDRC_MRCTRL0_sw_init_int_SHIFT           (3U)
9092 /*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before
9093  *    automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the
9094  *    DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to
9095  *    program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4
9096  *    independent channel mode, note that this must be programmed to both channels beforehand. Note that
9097  *    this must be cleared to 0 after completing Software operation. Otherwise, SDRAM
9098  *    initialization routine will not re-start.
9099  *  0b0..Software intervention is not allowed
9100  *  0b1..Software intervention is allowed
9101  */
9102 #define DDRC_MRCTRL0_sw_init_int(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_sw_init_int_SHIFT)) & DDRC_MRCTRL0_sw_init_int_MASK)
9103 #define DDRC_MRCTRL0_mr_rank_MASK                (0x30U)
9104 #define DDRC_MRCTRL0_mr_rank_SHIFT               (4U)
9105 /*! mr_rank - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access
9106  *    all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which
9107  *    implement address mirroring, it may be necessary to access ranks individually. Examples (assume
9108  *    DDRC is configured for 4 ranks): 0x1 - select rank 0 only 0x2 - select rank 1 only 0x5 -
9109  *    select ranks 0 and 2 0xA - select ranks 1 and 3 0xF - select ranks 0, 1, 2 and 3
9110  */
9111 #define DDRC_MRCTRL0_mr_rank(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_rank_SHIFT)) & DDRC_MRCTRL0_mr_rank_MASK)
9112 #define DDRC_MRCTRL0_mr_addr_MASK                (0xF000U)
9113 #define DDRC_MRCTRL0_mr_addr_SHIFT               (12U)
9114 /*! mr_addr - Address of the mode register that is to be written to.
9115  *  0b0000..MR0
9116  *  0b0001..MR1
9117  *  0b0010..MR2
9118  *  0b0011..MR3
9119  *  0b0100..MR4
9120  *  0b0101..MR5
9121  *  0b0110..MR6
9122  *  0b0111..MR7
9123  */
9124 #define DDRC_MRCTRL0_mr_addr(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_addr_SHIFT)) & DDRC_MRCTRL0_mr_addr_MASK)
9125 #define DDRC_MRCTRL0_pba_mode_MASK               (0x40000000U)
9126 #define DDRC_MRCTRL0_pba_mode_SHIFT              (30U)
9127 /*! pba_mode - Indicates whether PBA access is executed. When setting this bit to 1 along with
9128  *    setting pda_en to 1, DDRC initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability
9129  *    mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by
9130  *    MRSTAT.pda_done in the same way as PDA.
9131  */
9132 #define DDRC_MRCTRL0_pba_mode(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pba_mode_SHIFT)) & DDRC_MRCTRL0_pba_mode_MASK)
9133 #define DDRC_MRCTRL0_mr_wr_MASK                  (0x80000000U)
9134 #define DDRC_MRCTRL0_mr_wr_SHIFT                 (31U)
9135 /*! mr_wr - Setting this register bit to 1 triggers a mode register read or write operation. When
9136  *    the MR operation is complete, the DDRC automatically clears this bit. The other register fields
9137  *    of this register must be written in a separate APB transaction, before setting this mr_wr bit.
9138  *    It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
9139  */
9140 #define DDRC_MRCTRL0_mr_wr(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_wr_SHIFT)) & DDRC_MRCTRL0_mr_wr_MASK)
9141 /*! @} */
9142 
9143 /*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */
9144 /*! @{ */
9145 #define DDRC_MRCTRL1_mr_data_MASK                (0x3FFFFU)
9146 #define DDRC_MRCTRL1_mr_data_SHIFT               (0U)
9147 /*! mr_data - Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For
9148  *    LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes,
9149  *    don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all
9150  *    other configurations.
9151  */
9152 #define DDRC_MRCTRL1_mr_data(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_mr_data_SHIFT)) & DDRC_MRCTRL1_mr_data_MASK)
9153 /*! @} */
9154 
9155 /*! @name MRSTAT - Mode Register Read/Write Status Register */
9156 /*! @{ */
9157 #define DDRC_MRSTAT_mr_wr_busy_MASK              (0x1U)
9158 #define DDRC_MRSTAT_mr_wr_busy_SHIFT             (0U)
9159 /*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This
9160  *    signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the
9161  *    MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when
9162  *    'MRSTAT.mr_wr_busy' is high.
9163  *  0b0..Indicates that the SoC core can initiate a mode register write operation
9164  *  0b1..Indicates that mode register write operation is in progress
9165  */
9166 #define DDRC_MRSTAT_mr_wr_busy(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_MRSTAT_mr_wr_busy_MASK)
9167 #define DDRC_MRSTAT_pda_done_MASK                (0x100U)
9168 #define DDRC_MRSTAT_pda_done_SHIFT               (8U)
9169 /*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is
9170  *    low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode
9171  *    are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is
9172  *    recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to
9173  *    perform PDA operation next time
9174  *  0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.
9175  *  0b1..Indicates that mode register write operation related to PDA/PBA has competed.
9176  */
9177 #define DDRC_MRSTAT_pda_done(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_pda_done_SHIFT)) & DDRC_MRSTAT_pda_done_MASK)
9178 /*! @} */
9179 
9180 /*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */
9181 /*! @{ */
9182 #define DDRC_MRCTRL2_mr_device_sel_MASK          (0xFFFFFFFFU)
9183 #define DDRC_MRCTRL2_mr_device_sel_SHIFT         (0U)
9184 /*! mr_device_sel - Indicates the device(s) to be selected during the MRS that happens in PDA mode.
9185  *    Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to
9186  *    Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied
9187  *    to that device. A '0' indicates that the MRS commands should be skipped for that device.
9188  */
9189 #define DDRC_MRCTRL2_mr_device_sel(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_MRCTRL2_mr_device_sel_MASK)
9190 /*! @} */
9191 
9192 /*! @name DERATEEN - Temperature Derate Enable Register */
9193 /*! @{ */
9194 #define DDRC_DERATEEN_derate_enable_MASK         (0x1U)
9195 #define DDRC_DERATEEN_derate_enable_SHIFT        (0U)
9196 /*! derate_enable - Enables derating. Present only in designs configured to support
9197  *    LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
9198  *  0b0..Timing parameter derating is disabled
9199  *  0b1..Timing parameter derating is enabled using MR4 read value.
9200  */
9201 #define DDRC_DERATEEN_derate_enable(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_enable_SHIFT)) & DDRC_DERATEEN_derate_enable_MASK)
9202 #define DDRC_DERATEEN_derate_value_MASK          (0x2U)
9203 #define DDRC_DERATEEN_derate_value_SHIFT         (1U)
9204 /*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9205  *    Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a
9206  *    core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this
9207  *    register field should be set to 1; otherwise it should be set to 0.
9208  *  0b0..Derating uses +1
9209  *  0b1..Derating uses +2
9210  */
9211 #define DDRC_DERATEEN_derate_value(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_value_SHIFT)) & DDRC_DERATEEN_derate_value_MASK)
9212 #define DDRC_DERATEEN_derate_byte_MASK           (0xF0U)
9213 #define DDRC_DERATEEN_derate_byte_SHIFT          (4U)
9214 /*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9215  *    Indicates which byte of the MRR data is used for derating. The maximum valid value depends on
9216  *    MEMC_DRAM_TOTAL_DATA_WIDTH.
9217  */
9218 #define DDRC_DERATEEN_derate_byte(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_byte_SHIFT)) & DDRC_DERATEEN_derate_byte_MASK)
9219 #define DDRC_DERATEEN_rc_derate_value_MASK       (0x300U)
9220 #define DDRC_DERATEEN_rc_derate_value_SHIFT      (8U)
9221 /*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support
9222  *    LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the
9223  *    core_ddrc_core_clk period, and rounding up the next integer.
9224  *  0b00..Derating uses +1
9225  *  0b01..Derating uses +2
9226  *  0b10..Derating uses +3
9227  *  0b11..Derating uses +4
9228  */
9229 #define DDRC_DERATEEN_rc_derate_value(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_rc_derate_value_SHIFT)) & DDRC_DERATEEN_rc_derate_value_MASK)
9230 /*! @} */
9231 
9232 /*! @name DERATEINT - Temperature Derate Interval Register */
9233 /*! @{ */
9234 #define DDRC_DERATEINT_mr4_read_interval_MASK    (0xFFFFFFFFU)
9235 #define DDRC_DERATEINT_mr4_read_interval_SHIFT   (0U)
9236 /*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters.
9237  *    Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to
9238  *    zero. Unit: DFI clock cycle.
9239  */
9240 #define DDRC_DERATEINT_mr4_read_interval(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_mr4_read_interval_MASK)
9241 /*! @} */
9242 
9243 /*! @name PWRCTL - Low Power Control Register */
9244 /*! @{ */
9245 #define DDRC_PWRCTL_selfref_en_MASK              (0x1U)
9246 #define DDRC_PWRCTL_selfref_en_SHIFT             (0U)
9247 /*! selfref_en - If true then the DDRC puts the SDRAM into Self Refresh after a programmable number
9248  *    of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit
9249  *    may be re-programmed during the course of normal operation.
9250  */
9251 #define DDRC_PWRCTL_selfref_en(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_en_SHIFT)) & DDRC_PWRCTL_selfref_en_MASK)
9252 #define DDRC_PWRCTL_powerdown_en_MASK            (0x2U)
9253 #define DDRC_PWRCTL_powerdown_en_SHIFT           (1U)
9254 /*! powerdown_en - If true then the DDRC goes into power-down after a programmable number of cycles
9255  *    "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be
9256  *    re-programmed during the course of normal operation.
9257  */
9258 #define DDRC_PWRCTL_powerdown_en(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_powerdown_en_SHIFT)) & DDRC_PWRCTL_powerdown_en_MASK)
9259 #define DDRC_PWRCTL_deeppowerdown_en_MASK        (0x4U)
9260 #define DDRC_PWRCTL_deeppowerdown_en_SHIFT       (2U)
9261 /*! deeppowerdown_en - When this is 1, DDRC puts the SDRAM into deep power-down mode when the
9262  *    transaction store is empty. This register must be reset to '0' to bring DDRC out of deep power-down
9263  *    mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only
9264  *    in designs configured to support mDDR or LPDDR2 or LPDDR3. For
9265  *    non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
9266  */
9267 #define DDRC_PWRCTL_deeppowerdown_en(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_PWRCTL_deeppowerdown_en_MASK)
9268 #define DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U)
9269 #define DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U)
9270 /*! en_dfi_dram_clk_disable - Enable the assertion of dfi_dram_clk_disable whenever a clock is not
9271  *    required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of
9272  *    dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can
9273  *    be asserted in following: in Self Refresh in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3,
9274  *    can be asserted in following: in Self Refresh in Power Down in Deep Power Down during Normal
9275  *    operation (Clock Stop) In LPDDR4, can be asserted in following: in Self Refresh Power Down in
9276  *    Power Down during Normal operation (Clock Stop)
9277  */
9278 #define DDRC_PWRCTL_en_dfi_dram_clk_disable(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK)
9279 #define DDRC_PWRCTL_mpsm_en_MASK                 (0x10U)
9280 #define DDRC_PWRCTL_mpsm_en_SHIFT                (4U)
9281 /*! mpsm_en - When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the
9282  *    transaction store is empty. This register must be reset to '0' to bring DDRC out of maximum power
9283  *    saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register
9284  *    should not be set to 1. Note that MPSM is not supported when using a DDR PHY, if the PHY
9285  *    parameter DDRC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to
9286  *    toggle. FOR PERFORMANCE ONLY.
9287  */
9288 #define DDRC_PWRCTL_mpsm_en(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_mpsm_en_SHIFT)) & DDRC_PWRCTL_mpsm_en_MASK)
9289 #define DDRC_PWRCTL_selfref_sw_MASK              (0x20U)
9290 #define DDRC_PWRCTL_selfref_sw_SHIFT             (5U)
9291 /*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state
9292  *    immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software
9293  *    Entry/Exit to Self Refresh.
9294  *  0b0..Software Exit from Self Refresh
9295  *  0b1..Software Entry to Self Refresh
9296  */
9297 #define DDRC_PWRCTL_selfref_sw(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_sw_SHIFT)) & DDRC_PWRCTL_selfref_sw_MASK)
9298 #define DDRC_PWRCTL_stay_in_selfref_MASK         (0x40U)
9299 #define DDRC_PWRCTL_stay_in_selfref_SHIFT        (6U)
9300 /*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power
9301  *    down state or exit Self refresh power down state for LPDDR4. This register controls transition
9302  *    from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow
9303  *    transition from Self refresh state
9304  *  0b0..
9305  *  0b1..
9306  */
9307 #define DDRC_PWRCTL_stay_in_selfref(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_PWRCTL_stay_in_selfref_MASK)
9308 /*! @} */
9309 
9310 /*! @name PWRTMG - Low Power Timing Register */
9311 /*! @{ */
9312 #define DDRC_PWRTMG_powerdown_to_x32_MASK        (0x1FU)
9313 #define DDRC_PWRTMG_powerdown_to_x32_SHIFT       (0U)
9314 /*! powerdown_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
9315  *    automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there
9316  *    are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. Unit:
9317  *    Multiples of 32 DFI clocks FOR PERFORMANCE ONLY.
9318  */
9319 #define DDRC_PWRTMG_powerdown_to_x32(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_PWRTMG_powerdown_to_x32_MASK)
9320 #define DDRC_PWRTMG_t_dpd_x4096_MASK             (0xFF00U)
9321 #define DDRC_PWRTMG_t_dpd_x4096_SHIFT            (8U)
9322 /*! t_dpd_x4096 - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as
9323  *    mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is
9324  *    de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI
9325  *    clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
9326  *    ONLY.
9327  */
9328 #define DDRC_PWRTMG_t_dpd_x4096(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_PWRTMG_t_dpd_x4096_MASK)
9329 #define DDRC_PWRTMG_selfref_to_x32_MASK          (0xFF0000U)
9330 #define DDRC_PWRTMG_selfref_to_x32_SHIFT         (16U)
9331 /*! selfref_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
9332  *    automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there
9333  *    are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. Unit:
9334  *    Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY.
9335  */
9336 #define DDRC_PWRTMG_selfref_to_x32(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_PWRTMG_selfref_to_x32_MASK)
9337 /*! @} */
9338 
9339 /*! @name HWLPCTL - Hardware Low Power Control Register */
9340 /*! @{ */
9341 #define DDRC_HWLPCTL_hw_lp_en_MASK               (0x1U)
9342 #define DDRC_HWLPCTL_hw_lp_en_SHIFT              (0U)
9343 /*! hw_lp_en - Enable for Hardware Low Power Interface.
9344  */
9345 #define DDRC_HWLPCTL_hw_lp_en(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_en_MASK)
9346 #define DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK     (0x2U)
9347 #define DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT    (1U)
9348 /*! hw_lp_exit_idle_en - When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be
9349  *    used to exit from the automatic clock stop, automatic power down or automatic self-refresh
9350  *    modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power
9351  *    Interface and/or Software (PWRCTL.selfref_sw).
9352  */
9353 #define DDRC_HWLPCTL_hw_lp_exit_idle_en(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK)
9354 #define DDRC_HWLPCTL_hw_lp_idle_x32_MASK         (0xFFF0000U)
9355 #define DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT        (16U)
9356 /*! hw_lp_idle_x32 - Hardware idle period. The cactive_ddrc output is driven low if the DDRC command
9357  *    channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The
9358  *    DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware
9359  *    idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR
9360  *    PERFORMANCE ONLY.
9361  */
9362 #define DDRC_HWLPCTL_hw_lp_idle_x32(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_HWLPCTL_hw_lp_idle_x32_MASK)
9363 /*! @} */
9364 
9365 /*! @name RFSHCTL0 - Refresh Control Register 0 */
9366 /*! @{ */
9367 #define DDRC_RFSHCTL0_per_bank_refresh_MASK      (0x4U)
9368 #define DDRC_RFSHCTL0_per_bank_refresh_SHIFT     (2U)
9369 /*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is
9370  *    not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices.
9371  *    Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9372  *  0b1..Per bank refresh
9373  *  0b0..All bank refresh
9374  */
9375 #define DDRC_RFSHCTL0_per_bank_refresh(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_per_bank_refresh_MASK)
9376 #define DDRC_RFSHCTL0_refresh_burst_MASK         (0x1F0U)
9377 #define DDRC_RFSHCTL0_refresh_burst_SHIFT        (4U)
9378 /*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to
9379  *    accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to
9380  *    perform a refresh is a one-time penalty that must be paid for each group of refreshes.
9381  *    Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
9382  *    Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases
9383  *    the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2
9384  *    refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of
9385  *    DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not
9386  *    per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh
9387  *    feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
9388  *    mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care
9389  *    must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated
9390  *    due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
9391  *    situation, the refresh burst will be delayed until the PHY-initiated update is complete.
9392  */
9393 #define DDRC_RFSHCTL0_refresh_burst(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_refresh_burst_MASK)
9394 #define DDRC_RFSHCTL0_refresh_to_x32_MASK        (0x1F000U)
9395 #define DDRC_RFSHCTL0_refresh_to_x32_SHIFT       (12U)
9396 /*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once,
9397  *    but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be
9398  *    performed. A speculative refresh is a refresh performed at a time when refresh would be
9399  *    useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time
9400  *    determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since
9401  *    the last refresh, then a speculative refresh is performed. Speculative refreshes continues
9402  *    successively until there are no refreshes pending or until new reads or writes are issued to the
9403  *    DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
9404  */
9405 #define DDRC_RFSHCTL0_refresh_to_x32(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_refresh_to_x32_MASK)
9406 #define DDRC_RFSHCTL0_refresh_margin_MASK        (0xF00000U)
9407 #define DDRC_RFSHCTL0_refresh_margin_SHIFT       (20U)
9408 /*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or
9409  *    page timer expires. A critical refresh is to be issued before this threshold is reached. It is
9410  *    recommended that this not be changed from the default value, currently shown as 0x2. It must
9411  *    always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4,
9412  *    internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled
9413  *    (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to
9414  *    RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
9415  */
9416 #define DDRC_RFSHCTL0_refresh_margin(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_refresh_margin_MASK)
9417 /*! @} */
9418 
9419 /*! @name RFSHCTL1 - Refresh Control Register 1 */
9420 /*! @{ */
9421 #define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU)
9422 #define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U)
9423 /*! refresh_timer0_start_value_x32 - Refresh timer start for rank 0 (only present in multi-rank
9424  *    configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
9425  *    proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
9426  *    of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
9427  */
9428 #define DDRC_RFSHCTL1_refresh_timer0_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK)
9429 #define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U)
9430 #define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U)
9431 /*! refresh_timer1_start_value_x32 - Refresh timer start for rank 1 (only present in multi-rank
9432  *    configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
9433  *    proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
9434  *    of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
9435  */
9436 #define DDRC_RFSHCTL1_refresh_timer1_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK)
9437 /*! @} */
9438 
9439 /*! @name RFSHCTL3 - Refresh Control Register 3 */
9440 /*! @{ */
9441 #define DDRC_RFSHCTL3_dis_auto_refresh_MASK      (0x1U)
9442 #define DDRC_RFSHCTL3_dis_auto_refresh_SHIFT     (0U)
9443 /*! dis_auto_refresh - When '1', disable auto-refresh generated by the DDRC. When auto-refresh is
9444  *    disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh,
9445  *    reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh
9446  *    transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4
9447  *    CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is
9448  *    not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled
9449  *    (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This
9450  *    register field is changeable on the fly.
9451  */
9452 #define DDRC_RFSHCTL3_dis_auto_refresh(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_RFSHCTL3_dis_auto_refresh_MASK)
9453 #define DDRC_RFSHCTL3_refresh_update_level_MASK  (0x2U)
9454 #define DDRC_RFSHCTL3_refresh_update_level_SHIFT (1U)
9455 /*! refresh_update_level - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
9456  *    the refresh register(s) have been updated. refresh_update_level must not be toggled when the
9457  *    DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when
9458  *    exiting reset.
9459  */
9460 #define DDRC_RFSHCTL3_refresh_update_level(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_update_level_SHIFT)) & DDRC_RFSHCTL3_refresh_update_level_MASK)
9461 #define DDRC_RFSHCTL3_refresh_mode_MASK          (0x70U)
9462 #define DDRC_RFSHCTL3_refresh_mode_SHIFT         (4U)
9463 /*! refresh_mode - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x -
9464  *    010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not
9465  *    supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if
9466  *    RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the DDRC.
9467  *    Note: This must be set up while the Controller is in reset or while the Controller is in
9468  *    self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic
9469  *    register will be supported in future version of the DDRC. Note: This register field has effect only
9470  *    if a DDR4 SDRAM device is in use (MSTR.ddr4 = 1).
9471  */
9472 #define DDRC_RFSHCTL3_refresh_mode(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_RFSHCTL3_refresh_mode_MASK)
9473 /*! @} */
9474 
9475 /*! @name RFSHTMG - Refresh Timing Register */
9476 /*! @{ */
9477 #define DDRC_RFSHTMG_t_rfc_min_MASK              (0x3FFU)
9478 #define DDRC_RFSHTMG_t_rfc_min_SHIFT             (0U)
9479 /*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is
9480  *    operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller
9481  *    is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In
9482  *    LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations
9483  *    is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is
9484  *    equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending
9485  *    on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the
9486  *    appropriate value from the spec based on the 'refresh_mode' and the device density that is used.
9487  *    Unit: Clocks.
9488  */
9489 #define DDRC_RFSHTMG_t_rfc_min(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_t_rfc_min_MASK)
9490 #define DDRC_RFSHTMG_lpddr3_trefbw_en_MASK       (0x8000U)
9491 #define DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT      (15U)
9492 /*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when
9493  *    DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3
9494  *    devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW
9495  *    parameter not used - 1 - tREFBW parameter used
9496  */
9497 #define DDRC_RFSHTMG_lpddr3_trefbw_en(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_lpddr3_trefbw_en_MASK)
9498 #define DDRC_RFSHTMG_t_rfc_nom_x32_MASK          (0xFFF0000U)
9499 #define DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT         (16U)
9500 /*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us
9501  *    for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For
9502  *    LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register
9503  *    should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
9504  *    register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode,
9505  *    program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending
9506  *    on the refresh mode. The user should program the appropriate value from the spec based on the
9507  *    value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be
9508  *    greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or
9509  *    DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed
9510  *    2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode:
9511  *    RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
9512  */
9513 #define DDRC_RFSHTMG_t_rfc_nom_x32(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_t_rfc_nom_x32_MASK)
9514 /*! @} */
9515 
9516 /*! @name INIT0 - SDRAM Initialization Register 0 */
9517 /*! @{ */
9518 #define DDRC_INIT0_pre_cke_x1024_MASK            (0xFFFU)
9519 #define DDRC_INIT0_pre_cke_x1024_SHIFT           (0U)
9520 /*! pre_cke_x1024 - Cycles to wait after reset before driving CKE high to start the SDRAM
9521  *    initialization sequence. Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be
9522  *    programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2
9523  *    ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC
9524  *    spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this
9525  *    should include the time needed to satisfy tSTAB
9526  */
9527 #define DDRC_INIT0_pre_cke_x1024(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_pre_cke_x1024_SHIFT)) & DDRC_INIT0_pre_cke_x1024_MASK)
9528 #define DDRC_INIT0_post_cke_x1024_MASK           (0x3FF0000U)
9529 #define DDRC_INIT0_post_cke_x1024_SHIFT          (16U)
9530 /*! post_cke_x1024 - Cycles to wait after driving CKE high to start the SDRAM initialization
9531  *    sequence. Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value
9532  *    to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be
9533  *    programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us.
9534  *    When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
9535  *    value divided by 2, and round it up to the next integer value.
9536  */
9537 #define DDRC_INIT0_post_cke_x1024(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_post_cke_x1024_SHIFT)) & DDRC_INIT0_post_cke_x1024_MASK)
9538 #define DDRC_INIT0_skip_dram_init_MASK           (0xC0000000U)
9539 #define DDRC_INIT0_skip_dram_init_SHIFT          (30U)
9540 /*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper
9541  *    bit decides what state the controller starts up in when reset is removed - 00 - SDRAM
9542  *    Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after
9543  *    power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after
9544  *    power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run
9545  *    after power-up.
9546  *  0b00..SDRAM Initialization routine is run after power-up
9547  *  0b01..SDRAM Initialization routine is skipped after power-up
9548  *  0b10..SDRAM Initialization routine is run after power-up
9549  *  0b11..SDRAM Initialization routine is skipped after power-up
9550  */
9551 #define DDRC_INIT0_skip_dram_init(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_skip_dram_init_SHIFT)) & DDRC_INIT0_skip_dram_init_MASK)
9552 /*! @} */
9553 
9554 /*! @name INIT1 - SDRAM Initialization Register 1 */
9555 /*! @{ */
9556 #define DDRC_INIT1_pre_ocd_x32_MASK              (0xFU)
9557 #define DDRC_INIT1_pre_ocd_x32_SHIFT             (0U)
9558 /*! pre_ocd_x32 - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a
9559  *    global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for
9560  *    this; it may be set to zero.
9561  */
9562 #define DDRC_INIT1_pre_ocd_x32(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_pre_ocd_x32_SHIFT)) & DDRC_INIT1_pre_ocd_x32_MASK)
9563 #define DDRC_INIT1_dram_rstn_x1024_MASK          (0x1FF0000U)
9564 #define DDRC_INIT1_dram_rstn_x1024_SHIFT         (16U)
9565 /*! dram_rstn_x1024 - Number of cycles to assert SDRAM reset signal during init sequence. This is
9566  *    only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this
9567  *    should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode,
9568  *    program this to JEDEC spec value divided by 2, and round it up to the next integer value.
9569  *    Unit: 1024 DFI clock cycles.
9570  */
9571 #define DDRC_INIT1_dram_rstn_x1024(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_INIT1_dram_rstn_x1024_MASK)
9572 /*! @} */
9573 
9574 /*! @name INIT2 - SDRAM Initialization Register 2 */
9575 /*! @{ */
9576 #define DDRC_INIT2_min_stable_clock_x1_MASK      (0xFU)
9577 #define DDRC_INIT2_min_stable_clock_x1_SHIFT     (0U)
9578 /*! min_stable_clock_x1 - Time to wait after the first CKE high, tINIT2. Present only in designs
9579  *    configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the
9580  *    controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by
9581  *    2, and round it up to the next integer value. Unit: DFI clock cycles.
9582  */
9583 #define DDRC_INIT2_min_stable_clock_x1(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_INIT2_min_stable_clock_x1_MASK)
9584 #define DDRC_INIT2_idle_after_reset_x32_MASK     (0xFF00U)
9585 #define DDRC_INIT2_idle_after_reset_x32_SHIFT    (8U)
9586 /*! idle_after_reset_x32 - Idle time after the reset command, tINIT4. Present only in designs
9587  *    configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program
9588  *    this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI
9589  *    clock cycles.
9590  */
9591 #define DDRC_INIT2_idle_after_reset_x32(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_INIT2_idle_after_reset_x32_MASK)
9592 /*! @} */
9593 
9594 /*! @name INIT3 - SDRAM Initialization Register 3 */
9595 /*! @{ */
9596 #define DDRC_INIT3_emr_MASK                      (0xFFFFU)
9597 #define DDRC_INIT3_emr_SHIFT                     (0U)
9598 /*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
9599  *    register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1
9600  *    register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by
9601  *    the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 -
9602  *    Value to write to MR2 register
9603  */
9604 #define DDRC_INIT3_emr(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_emr_SHIFT)) & DDRC_INIT3_emr_MASK)
9605 #define DDRC_INIT3_mr_MASK                       (0xFFFF0000U)
9606 #define DDRC_INIT3_mr_SHIFT                      (16U)
9607 /*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The
9608  *    DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to
9609  *    write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
9610  */
9611 #define DDRC_INIT3_mr(x)                         (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_mr_SHIFT)) & DDRC_INIT3_mr_MASK)
9612 /*! @} */
9613 
9614 /*! @name INIT4 - SDRAM Initialization Register 4 */
9615 /*! @{ */
9616 #define DDRC_INIT4_emr3_MASK                     (0xFFFFU)
9617 #define DDRC_INIT4_emr3_SHIFT                    (0U)
9618 /*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register
9619  *    mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
9620  */
9621 #define DDRC_INIT4_emr3(x)                       (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr3_SHIFT)) & DDRC_INIT4_emr3_MASK)
9622 #define DDRC_INIT4_emr2_MASK                     (0xFFFF0000U)
9623 #define DDRC_INIT4_emr2_SHIFT                    (16U)
9624 /*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register
9625  *    LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
9626  */
9627 #define DDRC_INIT4_emr2(x)                       (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr2_SHIFT)) & DDRC_INIT4_emr2_MASK)
9628 /*! @} */
9629 
9630 /*! @name INIT5 - SDRAM Initialization Register 5 */
9631 /*! @{ */
9632 #define DDRC_INIT5_max_auto_init_x1024_MASK      (0x3FFU)
9633 #define DDRC_INIT5_max_auto_init_x1024_SHIFT     (0U)
9634 /*! max_auto_init_x1024 - Maximum duration of the auto initialization, tINIT5. Present only in
9635  *    designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI
9636  *    clock cycles.
9637  */
9638 #define DDRC_INIT5_max_auto_init_x1024(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_INIT5_max_auto_init_x1024_MASK)
9639 #define DDRC_INIT5_dev_zqinit_x32_MASK           (0xFF0000U)
9640 #define DDRC_INIT5_dev_zqinit_x32_SHIFT          (16U)
9641 /*! dev_zqinit_x32 - ZQ initial calibration, tZQINIT. Present only in designs configured to support
9642  *    DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires
9643  *    1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2
9644  *    frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the
9645  *    next integer value. Unit: 32 DFI clock cycles.
9646  */
9647 #define DDRC_INIT5_dev_zqinit_x32(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_INIT5_dev_zqinit_x32_MASK)
9648 /*! @} */
9649 
9650 /*! @name INIT6 - SDRAM Initialization Register 6 */
9651 /*! @{ */
9652 #define DDRC_INIT6_mr5_MASK                      (0xFFFFU)
9653 #define DDRC_INIT6_mr5_SHIFT                     (0U)
9654 /*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
9655  */
9656 #define DDRC_INIT6_mr5(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr5_SHIFT)) & DDRC_INIT6_mr5_MASK)
9657 #define DDRC_INIT6_mr4_MASK                      (0xFFFF0000U)
9658 #define DDRC_INIT6_mr4_SHIFT                     (16U)
9659 /*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
9660  */
9661 #define DDRC_INIT6_mr4(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr4_SHIFT)) & DDRC_INIT6_mr4_MASK)
9662 /*! @} */
9663 
9664 /*! @name INIT7 - SDRAM Initialization Register 7 */
9665 /*! @{ */
9666 #define DDRC_INIT7_mr6_MASK                      (0xFFFF0000U)
9667 #define DDRC_INIT7_mr6_SHIFT                     (16U)
9668 /*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
9669  */
9670 #define DDRC_INIT7_mr6(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_mr6_SHIFT)) & DDRC_INIT7_mr6_MASK)
9671 /*! @} */
9672 
9673 /*! @name DIMMCTL - DIMM Control Register */
9674 /*! @{ */
9675 #define DDRC_DIMMCTL_dimm_stagger_cs_en_MASK     (0x1U)
9676 #define DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT    (0U)
9677 /*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and
9678  *    LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.
9679  *    Even if this bit is set it does not take care of software driven MR commands (via
9680  *    MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
9681  *  0b0..Do not stagger accesses
9682  *  0b1..(non-DDR4) Send all commands to even and odd ranks separately
9683  *  0b1..(DDR4) Send MRS commands to each ranks separately
9684  */
9685 #define DDRC_DIMMCTL_dimm_stagger_cs_en(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_DIMMCTL_dimm_stagger_cs_en_MASK)
9686 #define DDRC_DIMMCTL_dimm_addr_mirr_en_MASK      (0x2U)
9687 #define DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT     (1U)
9688 /*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and
9689  *    multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address
9690  *    mirroring for odd ranks, which means that the following address, bank address and bank group
9691  *    bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for
9692  *    the DDR4. Setting this bit ensures that, for mode register accesses during the automatic
9693  *    initialization routine, these bits are swapped within the DDRC to compensate for this
9694  *    UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4
9695  *    UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular
9696  *    DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of
9697  *    software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4
9698  *    SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0
9699  *    because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
9700  *  0b0..Do not implement address mirroring
9701  *  0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any
9702  *       automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)
9703  */
9704 #define DDRC_DIMMCTL_dimm_addr_mirr_en(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_DIMMCTL_dimm_addr_mirr_en_MASK)
9705 #define DDRC_DIMMCTL_dimm_output_inv_en_MASK     (0x4U)
9706 #define DDRC_DIMMCTL_dimm_output_inv_en_SHIFT    (2U)
9707 /*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4
9708  *    RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the
9709  *    following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13,
9710  *    A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the
9711  *    DDRC during the automatic initialization routine and enabling of a particular DDR4 feature,
9712  *    separate A-side and B-side mode register accesses are generated. For B-side mode register
9713  *    accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It
9714  *    is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect
9715  *    on the address of any other memory accesses, or of software-driven mode register accesses.
9716  *  0b0..Do not implement output inversion for B-side DRAMs.
9717  *  0b1..Implement output inversion for B-side DRAMs.
9718  */
9719 #define DDRC_DIMMCTL_dimm_output_inv_en(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_DIMMCTL_dimm_output_inv_en_MASK)
9720 #define DDRC_DIMMCTL_mrs_a17_en_MASK             (0x8U)
9721 #define DDRC_DIMMCTL_mrs_a17_en_SHIFT            (3U)
9722 /*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is
9723  *    specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
9724  *    which do not have A17 are attached and the Output Inversion are enabled, this must be set to
9725  *    0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on
9726  *    the address of any other memory accesses, or of software-driven mode register accesses.
9727  *  0b0..Disabled
9728  *  0b1..Enabled
9729  */
9730 #define DDRC_DIMMCTL_mrs_a17_en(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_DIMMCTL_mrs_a17_en_MASK)
9731 #define DDRC_DIMMCTL_mrs_bg1_en_MASK             (0x10U)
9732 #define DDRC_DIMMCTL_mrs_bg1_en_SHIFT            (4U)
9733 /*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is
9734  *    specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
9735  *    which do not have BG1 are attached and both the CA parity and the Output Inversion are
9736  *    enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note:
9737  *    This has no effect on the address of any other memory accesses, or of software-driven mode
9738  *    register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0
9739  *    of odd ranks.
9740  *  0b0..Disabled
9741  *  0b1..Enabled
9742  */
9743 #define DDRC_DIMMCTL_mrs_bg1_en(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_DIMMCTL_mrs_bg1_en_MASK)
9744 #define DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK  (0x20U)
9745 #define DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U)
9746 /*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
9747  *    BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs
9748  *    with x16 devices.
9749  *  0b0..BG0 and BG1 are swapped if address mirroring is enabled.
9750  *  0b1..BG0 and BG1 are NOT swapped.
9751  */
9752 #define DDRC_DIMMCTL_dimm_dis_bg_mirroring(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK)
9753 #define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK   (0x40U)
9754 #define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT  (6U)
9755 /*! lrdimm_bcom_cmd_prot - Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM
9756  *    commands defined in the Data Buffer specification. When using DDR4 LRDIMM, this bit must be set
9757  *    to 1. Otherwise, this bit must be set to 0.
9758  */
9759 #define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK)
9760 /*! @} */
9761 
9762 /*! @name RANKCTL - Rank Control Register */
9763 /*! @{ */
9764 #define DDRC_RANKCTL_max_rank_rd_MASK            (0xFU)
9765 #define DDRC_RANKCTL_max_rank_rd_SHIFT           (0U)
9766 /*! max_rank_rd - Only present for multi-rank configurations. Background: Reads to the same rank can
9767  *    be performed back-to-back. Reads to different ranks require additional gap dictated by the
9768  *    register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to
9769  *    give PHY enough time to switch the delay when changing ranks. The DDRC arbitrates for bus
9770  *    access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles
9771  *    (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the
9772  *    same rank are eligible to be scheduled. This prevents reads from other ranks from having fair
9773  *    access to the data bus. This parameter represents the maximum number of reads that can be
9774  *    scheduled consecutively to the same rank. After this number is reached, a delay equal to
9775  *    RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be
9776  *    scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This
9777  *    feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on
9778  *    the same rank as long as commands are available for it. Minimum programmable value is 0 (feature
9779  *    disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
9780  */
9781 #define DDRC_RANKCTL_max_rank_rd(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_max_rank_rd_SHIFT)) & DDRC_RANKCTL_max_rank_rd_MASK)
9782 #define DDRC_RANKCTL_diff_rank_rd_gap_MASK       (0xF0U)
9783 #define DDRC_RANKCTL_diff_rank_rd_gap_SHIFT      (4U)
9784 /*! diff_rank_rd_gap - Only present for multi-rank configurations. Indicates the number of clocks of
9785  *    gap in data responses when performing consecutive reads to different ranks. This is used to
9786  *    switch the delays in the PHY to match the rank requirements. This value should consider both
9787  *    PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for
9788  *    value of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased
9789  *    by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT
9790  *    requirement: The value programmed in this register takes care of the ODT switch off timing requirement
9791  *    when switching ranks during reads. When the controller is operating in 1:1 mode, program this
9792  *    to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2
9793  *    mode, program this to the larger value divided by two and round it up to the next integer.
9794  *    Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer
9795  *    (DDR4DB01) Specification.
9796  */
9797 #define DDRC_RANKCTL_diff_rank_rd_gap(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_rd_gap_MASK)
9798 #define DDRC_RANKCTL_diff_rank_wr_gap_MASK       (0xF00U)
9799 #define DDRC_RANKCTL_diff_rank_wr_gap_SHIFT      (8U)
9800 /*! diff_rank_wr_gap - Only present for multi-rank configurations. Indicates the number of clocks of
9801  *    gap in data responses when performing consecutive writes to different ranks. This is used to
9802  *    switch the delays in the PHY to match the rank requirements. This value should consider both
9803  *    PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for
9804  *    value of tphy_wrcsgap) If CRC feature is enabled, should be increased by 1. If write preamble
9805  *    is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If write postamble is set to
9806  *    1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this
9807  *    register takes care of the ODT switch off timing requirement when switching ranks during writes.
9808  *    For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in
9809  *    1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the
9810  *    controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to
9811  *    the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in
9812  *    JEDEC DDR4 Data Buffer (DDR4DB01) Specification.
9813  */
9814 #define DDRC_RANKCTL_diff_rank_wr_gap(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_wr_gap_MASK)
9815 /*! @} */
9816 
9817 /*! @name DRAMTMG0 - SDRAM Timing Register 0 */
9818 /*! @{ */
9819 #define DDRC_DRAMTMG0_t_ras_min_MASK             (0x3FU)
9820 #define DDRC_DRAMTMG0_t_ras_min_SHIFT            (0U)
9821 /*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the
9822  *    controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding
9823  *    up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
9824  *    program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
9825  */
9826 #define DDRC_DRAMTMG0_t_ras_min(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_t_ras_min_MASK)
9827 #define DDRC_DRAMTMG0_t_ras_max_MASK             (0x7F00U)
9828 #define DDRC_DRAMTMG0_t_ras_max_SHIFT            (8U)
9829 /*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the
9830  *    maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid.
9831  *    When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
9832  *    No rounding up. Unit: Multiples of 1024 clocks.
9833  */
9834 #define DDRC_DRAMTMG0_t_ras_max(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_t_ras_max_MASK)
9835 #define DDRC_DRAMTMG0_t_faw_MASK                 (0x3F0000U)
9836 #define DDRC_DRAMTMG0_t_faw_SHIFT                (16U)
9837 /*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank
9838  *    design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller
9839  *    is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next
9840  *    integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency
9841  *    mode. Unit: Clocks
9842  */
9843 #define DDRC_DRAMTMG0_t_faw(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_faw_SHIFT)) & DDRC_DRAMTMG0_t_faw_MASK)
9844 #define DDRC_DRAMTMG0_wr2pre_MASK                (0x7F000000U)
9845 #define DDRC_DRAMTMG0_wr2pre_SHIFT               (24U)
9846 /*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL
9847  *    + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower
9848  *    frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in
9849  *    the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
9850  *    - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra
9851  *    cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2
9852  *    frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller
9853  *    is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2
9854  *    and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it
9855  *    may be necessary to adjust the value of this parameter to compensate for the extra cycle of
9856  *    latency through the LRDIMM.
9857  */
9858 #define DDRC_DRAMTMG0_wr2pre(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_wr2pre_SHIFT)) & DDRC_DRAMTMG0_wr2pre_MASK)
9859 /*! @} */
9860 
9861 /*! @name DRAMTMG1 - SDRAM Timing Register 1 */
9862 /*! @{ */
9863 #define DDRC_DRAMTMG1_t_rc_MASK                  (0x7FU)
9864 #define DDRC_DRAMTMG1_t_rc_SHIFT                 (0U)
9865 /*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2
9866  *    frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit:
9867  *    Clocks.
9868  */
9869 #define DDRC_DRAMTMG1_t_rc(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_rc_SHIFT)) & DDRC_DRAMTMG1_t_rc_MASK)
9870 #define DDRC_DRAMTMG1_rd2pre_MASK                (0x3F00U)
9871 #define DDRC_DRAMTMG1_rd2pre_SHIFT               (8U)
9872 /*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP,
9873  *    2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4)
9874  *    or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
9875  *    LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4
9876  *    - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously,
9877  *    use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode,
9878  *    divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T
9879  *    mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
9880  *    Unit: Clocks.
9881  */
9882 #define DDRC_DRAMTMG1_rd2pre(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_rd2pre_SHIFT)) & DDRC_DRAMTMG1_rd2pre_MASK)
9883 #define DDRC_DRAMTMG1_t_xp_MASK                  (0x1F0000U)
9884 #define DDRC_DRAMTMG1_t_xp_SHIFT                 (16U)
9885 /*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be
9886  *    programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used,
9887  *    set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program
9888  *    this to (tXP/2) and round it up to the next integer value. Units: Clocks
9889  */
9890 #define DDRC_DRAMTMG1_t_xp(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_xp_SHIFT)) & DDRC_DRAMTMG1_t_xp_MASK)
9891 /*! @} */
9892 
9893 /*! @name DRAMTMG2 - SDRAM Timing Register 2 */
9894 /*! @{ */
9895 #define DDRC_DRAMTMG2_wr2rd_MASK                 (0x3FU)
9896 #define DDRC_DRAMTMG2_wr2rd_SHIFT                (0U)
9897 /*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from
9898  *    write command to read command for same bank group. In others, minimum time from write command to
9899  *    read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
9900  *    global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL
9901  *    = burst length. This must match the value programmed in the BL bit of the mode register to
9902  *    the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes
9903  *    directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes
9904  *    directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
9905  *    When the controller is operating in 1:2 mode, divide the value calculated using the above
9906  *    equation by 2, and round it up to next integer.
9907  */
9908 #define DDRC_DRAMTMG2_wr2rd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_wr2rd_SHIFT)) & DDRC_DRAMTMG2_wr2rd_MASK)
9909 #define DDRC_DRAMTMG2_rd2wr_MASK                 (0x3F00U)
9910 #define DDRC_DRAMTMG2_rd2wr_SHIFT                (8U)
9911 /*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL
9912  *    + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK)
9913  *    + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) +
9914  *    RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command.
9915  *    Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see
9916  *    the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: -
9917  *    WL = write latency - BL = burst length. This must match the value programmed in the BL bit of
9918  *    the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write
9919  *    preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to
9920  *    LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
9921  *    tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the
9922  *    value calculated using the above equation by 2, and round it up to next integer. Note that,
9923  *    depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter
9924  *    to compensate for the extra cycle of latency through the LRDIMM.
9925  */
9926 #define DDRC_DRAMTMG2_rd2wr(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_rd2wr_SHIFT)) & DDRC_DRAMTMG2_rd2wr_MASK)
9927 #define DDRC_DRAMTMG2_read_latency_MASK          (0x3F0000U)
9928 #define DDRC_DRAMTMG2_read_latency_SHIFT         (16U)
9929 /*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be
9930  *    set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust
9931  *    the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When
9932  *    the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the
9933  *    above equation by 2, and round it up to next integer. This register field is not required for
9934  *    DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in
9935  *    DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
9936  */
9937 #define DDRC_DRAMTMG2_read_latency(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_read_latency_SHIFT)) & DDRC_DRAMTMG2_read_latency_MASK)
9938 #define DDRC_DRAMTMG2_write_latency_MASK         (0x3F000000U)
9939 #define DDRC_DRAMTMG2_write_latency_SHIFT        (24U)
9940 /*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be
9941  *    set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if
9942  *    using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra
9943  *    cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio
9944  *    mode, divide the value calculated using the above equation by 2, and round it up to next
9945  *    integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set),
9946  *    as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
9947  *    protocols Unit: clocks
9948  */
9949 #define DDRC_DRAMTMG2_write_latency(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_write_latency_SHIFT)) & DDRC_DRAMTMG2_write_latency_MASK)
9950 /*! @} */
9951 
9952 /*! @name DRAMTMG3 - SDRAM Timing Register 3 */
9953 /*! @{ */
9954 #define DDRC_DRAMTMG3_t_mod_MASK                 (0x3FFU)
9955 #define DDRC_DRAMTMG3_t_mod_SHIFT                (0U)
9956 /*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and
9957  *    following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
9958  *    Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
9959  *    next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
9960  *    RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to
9961  *    compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
9962  *    Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller
9963  *    is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if
9964  *    controller is operating in 1:2 frequency ratio mode.
9965  */
9966 #define DDRC_DRAMTMG3_t_mod(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mod_SHIFT)) & DDRC_DRAMTMG3_t_mod_MASK)
9967 #define DDRC_DRAMTMG3_t_mrd_MASK                 (0x3F000U)
9968 #define DDRC_DRAMTMG3_t_mrd_SHIFT                (12U)
9969 /*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected
9970  *    SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS
9971  *    command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is
9972  *    operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer
9973  *    value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
9974  */
9975 #define DDRC_DRAMTMG3_t_mrd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrd_SHIFT)) & DDRC_DRAMTMG3_t_mrd_MASK)
9976 #define DDRC_DRAMTMG3_t_mrw_MASK                 (0x3FF00000U)
9977 #define DDRC_DRAMTMG3_t_mrw_SHIFT                (20U)
9978 /*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs
9979  *    configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3
9980  *    typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2,
9981  *    this register is used for the time from a MRW/MRR to all other commands. When the controller
9982  *    is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and
9983  *    round it up to the next integer value. For LDPDR3, this register is used for the time from a
9984  *    MRW/MRR to a MRW/MRR.
9985  */
9986 #define DDRC_DRAMTMG3_t_mrw(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrw_SHIFT)) & DDRC_DRAMTMG3_t_mrw_MASK)
9987 /*! @} */
9988 
9989 /*! @name DRAMTMG4 - SDRAM Timing Register 4 */
9990 /*! @{ */
9991 #define DDRC_DRAMTMG4_t_rp_MASK                  (0x1FU)
9992 #define DDRC_DRAMTMG4_t_rp_SHIFT                 (0U)
9993 /*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is
9994  *    operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is
9995  *    operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) +
9996  *    1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
9997  *    to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
9998  */
9999 #define DDRC_DRAMTMG4_t_rp(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rp_SHIFT)) & DDRC_DRAMTMG4_t_rp_MASK)
10000 #define DDRC_DRAMTMG4_t_rrd_MASK                 (0xF00U)
10001 #define DDRC_DRAMTMG4_t_rrd_SHIFT                (8U)
10002 /*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank
10003  *    group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller
10004  *    is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it
10005  *    up to the next integer value. Unit: Clocks.
10006  */
10007 #define DDRC_DRAMTMG4_t_rrd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rrd_SHIFT)) & DDRC_DRAMTMG4_t_rrd_MASK)
10008 #define DDRC_DRAMTMG4_t_ccd_MASK                 (0xF0000U)
10009 #define DDRC_DRAMTMG4_t_ccd_SHIFT                (16U)
10010 /*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank
10011  *    group. Others: tCCD: This is the minimum time between two reads or two writes. When the
10012  *    controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it
10013  *    up to the next integer value. Unit: clocks.
10014  */
10015 #define DDRC_DRAMTMG4_t_ccd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_ccd_SHIFT)) & DDRC_DRAMTMG4_t_ccd_MASK)
10016 #define DDRC_DRAMTMG4_t_rcd_MASK                 (0x1F000000U)
10017 #define DDRC_DRAMTMG4_t_rcd_SHIFT                (24U)
10018 /*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the
10019  *    controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round
10020  *    it up to the next integer value. Minimum value allowed for this register is 1, which implies
10021  *    minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio
10022  *    mode. Unit: Clocks.
10023  */
10024 #define DDRC_DRAMTMG4_t_rcd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rcd_SHIFT)) & DDRC_DRAMTMG4_t_rcd_MASK)
10025 /*! @} */
10026 
10027 /*! @name DRAMTMG5 - SDRAM Timing Register 5 */
10028 /*! @{ */
10029 #define DDRC_DRAMTMG5_t_cke_MASK                 (0x1FU)
10030 #define DDRC_DRAMTMG5_t_cke_SHIFT                (0U)
10031 /*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -
10032  *    LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of
10033  *    tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When
10034  *    the controller is operating in 1:2 frequency ratio mode, program this to (value described
10035  *    above)/2 and round it up to the next integer value. Unit: Clocks.
10036  */
10037 #define DDRC_DRAMTMG5_t_cke(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cke_SHIFT)) & DDRC_DRAMTMG5_t_cke_MASK)
10038 #define DDRC_DRAMTMG5_t_ckesr_MASK               (0x3F00U)
10039 #define DDRC_DRAMTMG5_t_ckesr_SHIFT              (8U)
10040 /*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing
10041  *    in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR
10042  *    - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity
10043  *    latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased
10044  *    by PL. When the controller is operating in 1:2 frequency ratio mode, program this to
10045  *    recommended value divided by two and round it up to next integer.
10046  */
10047 #define DDRC_DRAMTMG5_t_ckesr(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_t_ckesr_MASK)
10048 #define DDRC_DRAMTMG5_t_cksre_MASK               (0xF0000U)
10049 #define DDRC_DRAMTMG5_t_cksre_SHIFT              (16U)
10050 /*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.
10051  *    Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
10052  *    LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+
10053  *    PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should
10054  *    be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program
10055  *    this to recommended value divided by two and round it up to next integer.
10056  */
10057 #define DDRC_DRAMTMG5_t_cksre(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksre_SHIFT)) & DDRC_DRAMTMG5_t_cksre_MASK)
10058 #define DDRC_DRAMTMG5_t_cksrx_MASK               (0xF000000U)
10059 #define DDRC_DRAMTMG5_t_cksrx_SHIFT              (24U)
10060 /*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock
10061  *    before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 -
10062  *    LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the
10063  *    controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by
10064  *    two and round it up to next integer.
10065  */
10066 #define DDRC_DRAMTMG5_t_cksrx(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_t_cksrx_MASK)
10067 /*! @} */
10068 
10069 /*! @name DRAMTMG6 - SDRAM Timing Register 6 */
10070 /*! @{ */
10071 #define DDRC_DRAMTMG6_t_ckcsx_MASK               (0xFU)
10072 #define DDRC_DRAMTMG6_t_ckcsx_SHIFT              (0U)
10073 /*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before
10074  *    issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop
10075  *    Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2
10076  *    When the controller is operating in 1:2 frequency ratio mode, program this to recommended value
10077  *    divided by two and round it up to next integer. This is only present for designs supporting
10078  *    mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
10079  */
10080 #define DDRC_DRAMTMG6_t_ckcsx(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_t_ckcsx_MASK)
10081 #define DDRC_DRAMTMG6_t_ckdpdx_MASK              (0xF0000U)
10082 #define DDRC_DRAMTMG6_t_ckdpdx_SHIFT             (16U)
10083 /*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock
10084  *    before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR:
10085  *    1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode,
10086  *    program this to recommended value divided by two and round it up to next integer. This is only
10087  *    present for designs supporting mDDR or LPDDR2 devices.
10088  */
10089 #define DDRC_DRAMTMG6_t_ckdpdx(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_t_ckdpdx_MASK)
10090 #define DDRC_DRAMTMG6_t_ckdpde_MASK              (0xF000000U)
10091 #define DDRC_DRAMTMG6_t_ckdpde_SHIFT             (24U)
10092 /*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock.
10093  *    Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
10094  *    LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to
10095  *    recommended value divided by two and round it up to next integer. This is only present for designs
10096  *    supporting mDDR or LPDDR2/LPDDR3 devices.
10097  */
10098 #define DDRC_DRAMTMG6_t_ckdpde(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_t_ckdpde_MASK)
10099 /*! @} */
10100 
10101 /*! @name DRAMTMG7 - SDRAM Timing Register 7 */
10102 /*! @{ */
10103 #define DDRC_DRAMTMG7_t_ckpdx_MASK               (0xFU)
10104 #define DDRC_DRAMTMG7_t_ckpdx_SHIFT              (0U)
10105 /*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before
10106  *    issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 -
10107  *    LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the
10108  *    same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode,
10109  *    program this to recommended value divided by two and round it up to next integer. This is only
10110  *    present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
10111  */
10112 #define DDRC_DRAMTMG7_t_ckpdx(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_t_ckpdx_MASK)
10113 #define DDRC_DRAMTMG7_t_ckpde_MASK               (0xF00U)
10114 #define DDRC_DRAMTMG7_t_ckpde_SHIFT              (8U)
10115 /*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock.
10116  *    Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2
10117  *    - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as
10118  *    DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this
10119  *    to recommended value divided by two and round it up to next integer. This is only present for
10120  *    designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
10121  */
10122 #define DDRC_DRAMTMG7_t_ckpde(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_t_ckpde_MASK)
10123 /*! @} */
10124 
10125 /*! @name DRAMTMG8 - SDRAM Timing Register 8 */
10126 /*! @{ */
10127 #define DDRC_DRAMTMG8_t_xs_x32_MASK              (0x7FU)
10128 #define DDRC_DRAMTMG8_t_xs_x32_SHIFT             (0U)
10129 /*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is
10130  *    operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round
10131  *    up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
10132  *    DDR4 SDRAMs.
10133  */
10134 #define DDRC_DRAMTMG8_t_xs_x32(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_x32_MASK)
10135 #define DDRC_DRAMTMG8_t_xs_dll_x32_MASK          (0x7F00U)
10136 #define DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT         (8U)
10137 /*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller
10138  *    is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and
10139  *    round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
10140  *    DDR4 SDRAMs.
10141  */
10142 #define DDRC_DRAMTMG8_t_xs_dll_x32(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_dll_x32_MASK)
10143 #define DDRC_DRAMTMG8_t_xs_abort_x32_MASK        (0x7F0000U)
10144 #define DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT       (16U)
10145 /*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self
10146  *    Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the
10147  *    above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
10148  *    Note: Ensure this is less than or equal to t_xs_x32.
10149  */
10150 #define DDRC_DRAMTMG8_t_xs_abort_x32(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_abort_x32_MASK)
10151 #define DDRC_DRAMTMG8_t_xs_fast_x32_MASK         (0x7F000000U)
10152 #define DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT        (24U)
10153 /*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown
10154  *    mode). When the controller is operating in 1:2 frequency ratio mode, program this to the
10155  *    above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
10156  *    This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to
10157  *    t_xs_x32.
10158  */
10159 #define DDRC_DRAMTMG8_t_xs_fast_x32(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_fast_x32_MASK)
10160 /*! @} */
10161 
10162 /*! @name DRAMTMG9 - SDRAM Timing Register 9 */
10163 /*! @{ */
10164 #define DDRC_DRAMTMG9_wr2rd_s_MASK               (0x3FU)
10165 #define DDRC_DRAMTMG9_wr2rd_s_SHIFT              (0U)
10166 /*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different
10167  *    bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
10168  *    global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where:
10169  *    - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value
10170  *    programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read
10171  *    command delay for different bank group. This comes directly from the SDRAM specification. When
10172  *    the controller is operating in 1:2 mode, divide the value calculated using the above equation
10173  *    by 2, and round it up to next integer.
10174  */
10175 #define DDRC_DRAMTMG9_wr2rd_s(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_wr2rd_s_MASK)
10176 #define DDRC_DRAMTMG9_t_rrd_s_MASK               (0xF00U)
10177 #define DDRC_DRAMTMG9_t_rrd_s_SHIFT              (8U)
10178 /*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank
10179  *    group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2)
10180  *    and round it up to the next integer value. Present only in designs configured to support DDR4.
10181  *    Unit: Clocks.
10182  */
10183 #define DDRC_DRAMTMG9_t_rrd_s(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_t_rrd_s_MASK)
10184 #define DDRC_DRAMTMG9_t_ccd_s_MASK               (0x70000U)
10185 #define DDRC_DRAMTMG9_t_ccd_s_SHIFT              (16U)
10186 /*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank
10187  *    group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When
10188  *    the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round
10189  *    it up to the next integer value. Present only in designs configured to support DDR4. Unit:
10190  *    clocks.
10191  */
10192 #define DDRC_DRAMTMG9_t_ccd_s(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_t_ccd_s_MASK)
10193 #define DDRC_DRAMTMG9_ddr4_wr_preamble_MASK      (0x40000000U)
10194 #define DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT     (30U)
10195 /*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
10196  */
10197 #define DDRC_DRAMTMG9_ddr4_wr_preamble(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_ddr4_wr_preamble_MASK)
10198 /*! @} */
10199 
10200 /*! @name DRAMTMG10 - SDRAM Timing Register 10 */
10201 /*! @{ */
10202 #define DDRC_DRAMTMG10_t_gear_hold_MASK          (0x3U)
10203 #define DDRC_DRAMTMG10_t_gear_hold_SHIFT         (0U)
10204 /*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For
10205  *    DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
10206  *    1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer
10207  *    value. Unit: Clocks
10208  */
10209 #define DDRC_DRAMTMG10_t_gear_hold(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_t_gear_hold_MASK)
10210 #define DDRC_DRAMTMG10_t_gear_setup_MASK         (0xCU)
10211 #define DDRC_DRAMTMG10_t_gear_setup_SHIFT        (2U)
10212 /*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For
10213  *    DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
10214  *    1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer
10215  *    value. Unit: Clocks
10216  */
10217 #define DDRC_DRAMTMG10_t_gear_setup(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_t_gear_setup_MASK)
10218 #define DDRC_DRAMTMG10_t_cmd_gear_MASK           (0x1F00U)
10219 #define DDRC_DRAMTMG10_t_cmd_gear_SHIFT          (8U)
10220 /*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is
10221  *    defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for
10222  *    this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2)
10223  *    and round it up to the next integer value. Unit: Clocks
10224  */
10225 #define DDRC_DRAMTMG10_t_cmd_gear(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_t_cmd_gear_MASK)
10226 #define DDRC_DRAMTMG10_t_sync_gear_MASK          (0x1F0000U)
10227 #define DDRC_DRAMTMG10_t_sync_gear_SHIFT         (16U)
10228 /*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even
10229  *    number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK
10230  *    tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28
10231  *    When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up
10232  *    to the next integer value. Unit: Clocks
10233  */
10234 #define DDRC_DRAMTMG10_t_sync_gear(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_t_sync_gear_MASK)
10235 /*! @} */
10236 
10237 /*! @name DRAMTMG11 - SDRAM Timing Register 11 */
10238 /*! @{ */
10239 #define DDRC_DRAMTMG11_t_ckmpe_MASK              (0x1FU)
10240 #define DDRC_DRAMTMG11_t_ckmpe_SHIFT             (0U)
10241 /*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs
10242  *    configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio
10243  *    mode, divide the value calculated using the above equation by 2, and round it up to next
10244  *    integer.
10245  */
10246 #define DDRC_DRAMTMG11_t_ckmpe(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_t_ckmpe_MASK)
10247 #define DDRC_DRAMTMG11_t_mpx_s_MASK              (0x300U)
10248 #define DDRC_DRAMTMG11_t_mpx_s_SHIFT             (8U)
10249 /*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2
10250  *    frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value.
10251  *    Present only in designs configured to support DDR4. Unit: Clocks.
10252  */
10253 #define DDRC_DRAMTMG11_t_mpx_s(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_t_mpx_s_MASK)
10254 #define DDRC_DRAMTMG11_t_mpx_lh_MASK             (0x1F0000U)
10255 #define DDRC_DRAMTMG11_t_mpx_lh_SHIFT            (16U)
10256 /*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the
10257  *    controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present
10258  *    only in designs configured to support DDR4. Unit: clocks.
10259  */
10260 #define DDRC_DRAMTMG11_t_mpx_lh(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_t_mpx_lh_MASK)
10261 #define DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK    (0x7F000000U)
10262 #define DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT   (24U)
10263 /*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.
10264  *    When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and
10265  *    round it up to the next integer value. Present only in designs configured to support DDR4.
10266  *    Unit: Multiples of 32 clocks.
10267  */
10268 #define DDRC_DRAMTMG11_post_mpsm_gap_x32(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK)
10269 /*! @} */
10270 
10271 /*! @name DRAMTMG12 - SDRAM Timing Register 12 */
10272 /*! @{ */
10273 #define DDRC_DRAMTMG12_t_mrd_pda_MASK            (0x1FU)
10274 #define DDRC_DRAMTMG12_t_mrd_pda_SHIFT           (0U)
10275 /*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the
10276  *    controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up
10277  *    to the next integer value.
10278  */
10279 #define DDRC_DRAMTMG12_t_mrd_pda(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_t_mrd_pda_MASK)
10280 #define DDRC_DRAMTMG12_t_ckehcmd_MASK            (0xF00U)
10281 #define DDRC_DRAMTMG12_t_ckehcmd_SHIFT           (8U)
10282 /*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is
10283  *    operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next
10284  *    integer value.
10285  */
10286 #define DDRC_DRAMTMG12_t_ckehcmd(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_t_ckehcmd_MASK)
10287 #define DDRC_DRAMTMG12_t_cmdcke_MASK             (0x30000U)
10288 #define DDRC_DRAMTMG12_t_cmdcke_SHIFT            (16U)
10289 /*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE
10290  *    or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to
10291  *    (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
10292  */
10293 #define DDRC_DRAMTMG12_t_cmdcke(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_t_cmdcke_MASK)
10294 /*! @} */
10295 
10296 /*! @name DRAMTMG13 - SDRAM Timing Register 13 */
10297 /*! @{ */
10298 #define DDRC_DRAMTMG13_t_ppd_MASK                (0x7U)
10299 #define DDRC_DRAMTMG13_t_ppd_SHIFT               (0U)
10300 /*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the
10301  *    controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to
10302  *    the next integer value. Unit: Clocks.
10303  */
10304 #define DDRC_DRAMTMG13_t_ppd(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ppd_SHIFT)) & DDRC_DRAMTMG13_t_ppd_MASK)
10305 #define DDRC_DRAMTMG13_t_ccd_mw_MASK             (0x3F0000U)
10306 #define DDRC_DRAMTMG13_t_ccd_mw_SHIFT            (16U)
10307 /*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write
10308  *    command for same bank. When the controller is operating in 1:2 frequency ratio mode, program
10309  *    this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
10310  */
10311 #define DDRC_DRAMTMG13_t_ccd_mw(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_t_ccd_mw_MASK)
10312 #define DDRC_DRAMTMG13_odtloff_MASK              (0x7F000000U)
10313 #define DDRC_DRAMTMG13_odtloff_SHIFT             (24U)
10314 /*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When
10315  *    the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round
10316  *    it up to the next integer value. Unit: Clocks.
10317  */
10318 #define DDRC_DRAMTMG13_odtloff(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_odtloff_SHIFT)) & DDRC_DRAMTMG13_odtloff_MASK)
10319 /*! @} */
10320 
10321 /*! @name DRAMTMG14 - SDRAM Timing Register 14 */
10322 /*! @{ */
10323 #define DDRC_DRAMTMG14_t_xsr_MASK                (0xFFFU)
10324 #define DDRC_DRAMTMG14_t_xsr_SHIFT               (0U)
10325 /*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2
10326  *    frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
10327  *    Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
10328  */
10329 #define DDRC_DRAMTMG14_t_xsr(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_t_xsr_SHIFT)) & DDRC_DRAMTMG14_t_xsr_MASK)
10330 /*! @} */
10331 
10332 /*! @name DRAMTMG15 - SDRAM Timing Register 15 */
10333 /*! @{ */
10334 #define DDRC_DRAMTMG15_t_stab_x32_MASK           (0xFFU)
10335 #define DDRC_DRAMTMG15_t_stab_x32_SHIFT          (0U)
10336 /*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4
10337  *    RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the
10338  *    clock must be stable for a time specified by tSTAB - in the case of input clock frequency
10339  *    change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for
10340  *    DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to
10341  *    recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock
10342  *    cycles.
10343  */
10344 #define DDRC_DRAMTMG15_t_stab_x32(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_t_stab_x32_MASK)
10345 #define DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK     (0x80000000U)
10346 #define DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT    (31U)
10347 /*! en_dfi_lp_t_stab - Enable DFI tSTAB
10348  *  0b0..Disable using tSTAB when exiting DFI LP
10349  *  0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power.
10350  */
10351 #define DDRC_DRAMTMG15_en_dfi_lp_t_stab(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK)
10352 /*! @} */
10353 
10354 /*! @name ZQCTL0 - ZQ Control Register 0 */
10355 /*! @{ */
10356 #define DDRC_ZQCTL0_t_zq_short_nop_MASK          (0x3FFU)
10357 #define DDRC_ZQCTL0_t_zq_short_nop_SHIFT         (0U)
10358 /*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles
10359  *    of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
10360  *    When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
10361  *    round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
10362  *    LPDDR2/LPDDR3/LPDDR4 devices.
10363  */
10364 #define DDRC_ZQCTL0_t_zq_short_nop(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_short_nop_MASK)
10365 #define DDRC_ZQCTL0_t_zq_long_nop_MASK           (0x7FF0000U)
10366 #define DDRC_ZQCTL0_t_zq_long_nop_SHIFT          (16U)
10367 /*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI
10368  *    clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is
10369  *    issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program
10370  *    this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to
10371  *    tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it
10372  *    up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
10373  *    LPDDR2/LPDDR3/LPDDR4 devices.
10374  */
10375 #define DDRC_ZQCTL0_t_zq_long_nop(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_long_nop_MASK)
10376 #define DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK          (0x10000000U)
10377 #define DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT         (28U)
10378 /*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC
10379  *    configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting
10380  *    MPSM mode.
10381  *  0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
10382  *       This is only present for designs supporting DDR4 devices.
10383  *  0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
10384  */
10385 #define DDRC_ZQCTL0_dis_mpsmx_zqcl(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK)
10386 #define DDRC_ZQCTL0_zq_resistor_shared_MASK      (0x20000000U)
10387 #define DDRC_ZQCTL0_zq_resistor_shared_SHIFT     (29U)
10388 /*! zq_resistor_shared - ZQ resistor sharing
10389  *  0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10390  *  0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are
10391  *       sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that
10392  *       commands to different ranks do not overlap.
10393  */
10394 #define DDRC_ZQCTL0_zq_resistor_shared(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_zq_resistor_shared_MASK)
10395 #define DDRC_ZQCTL0_dis_srx_zqcl_MASK            (0x40000000U)
10396 #define DDRC_ZQCTL0_dis_srx_zqcl_SHIFT           (30U)
10397 /*! dis_srx_zqcl - Disable ZQCL/MPC
10398  *  0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
10399  *       when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting
10400  *       DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10401  *  0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
10402  *       when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
10403  */
10404 #define DDRC_ZQCTL0_dis_srx_zqcl(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_srx_zqcl_MASK)
10405 #define DDRC_ZQCTL0_dis_auto_zq_MASK             (0x80000000U)
10406 #define DDRC_ZQCTL0_dis_auto_zq_SHIFT            (31U)
10407 /*! dis_auto_zq - Disable Auto ZQCS/MPC
10408  *  0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
10409  *  0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used
10410  *       instead to issue ZQ calibration request from APB module.
10411  */
10412 #define DDRC_ZQCTL0_dis_auto_zq(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_dis_auto_zq_MASK)
10413 /*! @} */
10414 
10415 /*! @name ZQCTL1 - ZQ Control Register 1 */
10416 /*! @{ */
10417 #define DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU)
10418 #define DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U)
10419 /*! t_zq_short_interval_x1024 - Average interval to wait between automatically issuing ZQCS (ZQ
10420  *    calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices.
10421  *    Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs
10422  *    supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10423  */
10424 #define DDRC_ZQCTL1_t_zq_short_interval_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK)
10425 #define DDRC_ZQCTL1_t_zq_reset_nop_MASK          (0x3FF00000U)
10426 #define DDRC_ZQCTL1_t_zq_reset_nop_SHIFT         (20U)
10427 /*! t_zq_reset_nop - tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ
10428  *    calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency
10429  *    ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only
10430  *    present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
10431  */
10432 #define DDRC_ZQCTL1_t_zq_reset_nop(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_ZQCTL1_t_zq_reset_nop_MASK)
10433 /*! @} */
10434 
10435 /*! @name ZQCTL2 - ZQ Control Register 2 */
10436 /*! @{ */
10437 #define DDRC_ZQCTL2_zq_reset_MASK                (0x1U)
10438 #define DDRC_ZQCTL2_zq_reset_SHIFT               (0U)
10439 /*! zq_reset - Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset
10440  *    operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this
10441  *    signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down
10442  *    operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
10443  */
10444 #define DDRC_ZQCTL2_zq_reset(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_zq_reset_SHIFT)) & DDRC_ZQCTL2_zq_reset_MASK)
10445 /*! @} */
10446 
10447 /*! @name ZQSTAT - ZQ Status Register */
10448 /*! @{ */
10449 #define DDRC_ZQSTAT_zq_reset_busy_MASK           (0x1U)
10450 #define DDRC_ZQSTAT_zq_reset_busy_SHIFT          (0U)
10451 /*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This
10452  *    signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ
10453  *    Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended
10454  *    not to perform ZQ Reset commands when this signal is high.
10455  *  0b0..Indicates that the SoC core can initiate a ZQ Reset operation
10456  *  0b1..Indicates that ZQ Reset operation is in progress
10457  */
10458 #define DDRC_ZQSTAT_zq_reset_busy(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_ZQSTAT_zq_reset_busy_MASK)
10459 /*! @} */
10460 
10461 /*! @name DFITMG0 - DFI Timing Register 0 */
10462 /*! @{ */
10463 #define DDRC_DFITMG0_dfi_tphy_wrlat_MASK         (0x3FU)
10464 #define DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT        (0U)
10465 /*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable
10466  *    (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY
10467  *    specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be
10468  *    necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for
10469  *    the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY
10470  *    clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
10471  */
10472 #define DDRC_DFITMG0_dfi_tphy_wrlat(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrlat_MASK)
10473 #define DDRC_DFITMG0_dfi_tphy_wrdata_MASK        (0x3F00U)
10474 #define DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT       (8U)
10475 /*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to
10476  *    when the associated write data is driven on the dfi_wrdata signal. This corresponds to the
10477  *    DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max
10478  *    supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on
10479  *    DFITMG0.dfi_wrdata_use_sdr.
10480  */
10481 #define DDRC_DFITMG0_dfi_tphy_wrdata(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrdata_MASK)
10482 #define DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK     (0x8000U)
10483 #define DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT    (15U)
10484 /*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using
10485  *    HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat
10486  *    is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in
10487  *    DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of
10488  *    HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification
10489  *    for correct value.
10490  */
10491 #define DDRC_DFITMG0_dfi_wrdata_use_sdr(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK)
10492 #define DDRC_DFITMG0_dfi_t_rddata_en_MASK        (0x7F0000U)
10493 #define DDRC_DFITMG0_dfi_t_rddata_en_SHIFT       (16U)
10494 /*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the
10495  *    assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds
10496  *    to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it
10497  *    may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to
10498  *    compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or
10499  *    DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
10500  */
10501 #define DDRC_DFITMG0_dfi_t_rddata_en(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_dfi_t_rddata_en_MASK)
10502 #define DDRC_DFITMG0_dfi_rddata_use_sdr_MASK     (0x800000U)
10503 #define DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT    (23U)
10504 /*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated
10505  *    using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in
10506  *    DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI
10507  *    clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct
10508  *    value.
10509  */
10510 #define DDRC_DFITMG0_dfi_rddata_use_sdr(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_rddata_use_sdr_MASK)
10511 #define DDRC_DFITMG0_dfi_t_ctrl_delay_MASK       (0x1F000000U)
10512 #define DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT      (24U)
10513 /*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion
10514  *    of the DFI control signals that the control signals at the PHY-DRAM interface reflect the
10515  *    assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing
10516  *    parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it
10517  *    is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms
10518  *    of DFI clock.
10519  */
10520 #define DDRC_DFITMG0_dfi_t_ctrl_delay(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_dfi_t_ctrl_delay_MASK)
10521 /*! @} */
10522 
10523 /*! @name DFITMG1 - DFI Timing Register 1 */
10524 /*! @{ */
10525 #define DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK  (0x1FU)
10526 #define DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U)
10527 /*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the
10528  *    dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the
10529  *    DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not
10530  *    phase aligned, this timing parameter should be rounded up to the next integer value.
10531  */
10532 #define DDRC_DFITMG1_dfi_t_dram_clk_enable(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK)
10533 #define DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U)
10534 #define DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U)
10535 /*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the
10536  *    dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM
10537  *    boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned,
10538  *    this timing parameter should be rounded up to the next integer value.
10539  */
10540 #define DDRC_DFITMG1_dfi_t_dram_clk_disable(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK)
10541 #define DDRC_DFITMG1_dfi_t_wrdata_delay_MASK     (0x1F0000U)
10542 #define DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT    (16U)
10543 /*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en
10544  *    signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.
10545  *    This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
10546  *    correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI
10547  *    3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be
10548  *    programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2
10549  *    and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit:
10550  *    Clocks
10551  */
10552 #define DDRC_DFITMG1_dfi_t_wrdata_delay(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_dfi_t_wrdata_delay_MASK)
10553 #define DDRC_DFITMG1_dfi_t_parin_lat_MASK        (0x3000000U)
10554 #define DDRC_DFITMG1_dfi_t_parin_lat_SHIFT       (24U)
10555 /*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
10556  *    asserted and when the associated dfi_parity_in signal is driven.
10557  */
10558 #define DDRC_DFITMG1_dfi_t_parin_lat(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_parin_lat_MASK)
10559 #define DDRC_DFITMG1_dfi_t_cmd_lat_MASK          (0xF0000000U)
10560 #define DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT         (28U)
10561 /*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
10562  *    asserted and when the associated command is driven. This field is used for CAL mode, should be
10563  *    set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY
10564  *    can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
10565  */
10566 #define DDRC_DFITMG1_dfi_t_cmd_lat(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_cmd_lat_MASK)
10567 /*! @} */
10568 
10569 /*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */
10570 /*! @{ */
10571 #define DDRC_DFILPCFG0_dfi_lp_en_pd_MASK         (0x1U)
10572 #define DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT        (0U)
10573 /*! dfi_lp_en_pd - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
10574  */
10575 #define DDRC_DFILPCFG0_dfi_lp_en_pd(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_pd_MASK)
10576 #define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK     (0xF0U)
10577 #define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT    (4U)
10578 /*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down
10579  *    mode is entered. Determines the DFI's tlp_wakeup time:
10580  *  0b0000..16 cycles
10581  *  0b0001..32 cycles
10582  *  0b0010..64 cycles
10583  *  0b0011..128 cycles
10584  *  0b0100..256 cycles
10585  *  0b0101..512 cycles
10586  *  0b0110..1024 cycles
10587  *  0b0111..2048 cycles
10588  *  0b1000..4096 cycles
10589  *  0b1001..8192 cycles
10590  *  0b1010..16384 cycles
10591  *  0b1011..32768 cycles
10592  *  0b1100..65536 cycles
10593  *  0b1101..131072 cycles
10594  *  0b1110..262144 cycles
10595  *  0b1111..Unlimited cycles
10596  */
10597 #define DDRC_DFILPCFG0_dfi_lp_wakeup_pd(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK)
10598 #define DDRC_DFILPCFG0_dfi_lp_en_sr_MASK         (0x100U)
10599 #define DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT        (8U)
10600 /*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
10601  *  0b0..Disabled
10602  *  0b1..Enabled
10603  */
10604 #define DDRC_DFILPCFG0_dfi_lp_en_sr(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_sr_MASK)
10605 #define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK     (0xF000U)
10606 #define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT    (12U)
10607 /*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh
10608  *    mode is entered. Determines the DFI's tlp_wakeup time:
10609  *  0b0000..16 cycles
10610  *  0b0001..32 cycles
10611  *  0b0010..64 cycles
10612  *  0b0011..128 cycles
10613  *  0b0100..256 cycles
10614  *  0b0101..512 cycles
10615  *  0b0110..1024 cycles
10616  *  0b0111..2048 cycles
10617  *  0b1000..4096 cycles
10618  *  0b1001..8192 cycles
10619  *  0b1010..16384 cycles
10620  *  0b1011..32768 cycles
10621  *  0b1100..65536 cycles
10622  *  0b1101..131072 cycles
10623  *  0b1110..262144 cycles
10624  *  0b1111..Unlimited cycles
10625  */
10626 #define DDRC_DFILPCFG0_dfi_lp_wakeup_sr(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK)
10627 #define DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK        (0x10000U)
10628 #define DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT       (16U)
10629 /*! dfi_lp_en_dpd - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. -
10630  *    0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3
10631  *    devices.
10632  */
10633 #define DDRC_DFILPCFG0_dfi_lp_en_dpd(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK)
10634 #define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK    (0xF00000U)
10635 #define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT   (20U)
10636 /*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power
10637  *    Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs
10638  *    supporting mDDR or LPDDR2/LPDDR3 devices.
10639  *  0b0000..16 cycles
10640  *  0b0001..32 cycles
10641  *  0b0010..64 cycles
10642  *  0b0011..128 cycles
10643  *  0b0100..256 cycles
10644  *  0b0101..512 cycles
10645  *  0b0110..1024 cycles
10646  *  0b0111..2048 cycles
10647  *  0b1000..4096 cycles
10648  *  0b1001..8192 cycles
10649  *  0b1010..16384 cycles
10650  *  0b1011..32768 cycles
10651  *  0b1100..65536 cycles
10652  *  0b1101..131072 cycles
10653  *  0b1110..262144 cycles
10654  *  0b1111..Unlimited cycles
10655  */
10656 #define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK)
10657 #define DDRC_DFILPCFG0_dfi_tlp_resp_MASK         (0x1F000000U)
10658 #define DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT        (24U)
10659 /*! dfi_tlp_resp - Setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both
10660  *    Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1
10661  *    specification onwards, recommends using a fixed value of 7 always.
10662  */
10663 #define DDRC_DFILPCFG0_dfi_tlp_resp(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_DFILPCFG0_dfi_tlp_resp_MASK)
10664 /*! @} */
10665 
10666 /*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */
10667 /*! @{ */
10668 #define DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK       (0x1U)
10669 #define DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT      (0U)
10670 /*! dfi_lp_en_mpsm - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode
10671  *    Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4
10672  *    devices.
10673  */
10674 #define DDRC_DFILPCFG1_dfi_lp_en_mpsm(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK)
10675 #define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK   (0xF0U)
10676 #define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT  (4U)
10677 /*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum
10678  *    Power Saving Mode is entered. Determines the DFI's tlp_wakeup time:
10679  *  0b0000..16 cycles
10680  *  0b0001..32 cycles
10681  *  0b0010..64 cycles
10682  *  0b0011..128 cycles
10683  *  0b0100..256 cycles
10684  *  0b0101..512 cycles
10685  *  0b0110..1024 cycles
10686  *  0b0111..2048 cycles
10687  *  0b1000..4096 cycles
10688  *  0b1001..8192 cycles
10689  *  0b1010..16384 cycles
10690  *  0b1011..32768 cycles
10691  *  0b1100..65536 cycles
10692  *  0b1101..131072 cycles
10693  *  0b1110..262144 cycles
10694  *  0b1111..Unlimited cycles
10695  */
10696 #define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK)
10697 /*! @} */
10698 
10699 /*! @name DFIUPD0 - DFI Update Register 0 */
10700 /*! @{ */
10701 #define DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK       (0x3FFU)
10702 #define DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT      (0U)
10703 /*! dfi_t_ctrlup_min - Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req
10704  *    signal must be asserted. The DDRC expects the PHY to respond within this time. If the PHY does
10705  *    not respond, the DDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest
10706  *    value to assign to this variable is 0x3.
10707  */
10708 #define DDRC_DFIUPD0_dfi_t_ctrlup_min(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK)
10709 #define DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK       (0x3FF0000U)
10710 #define DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT      (16U)
10711 /*! dfi_t_ctrlup_max - Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req
10712  *    signal can assert. Lowest value to assign to this variable is 0x40.
10713  */
10714 #define DDRC_DFIUPD0_dfi_t_ctrlup_max(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK)
10715 #define DDRC_DFIUPD0_ctrlupd_pre_srx_MASK        (0x20000000U)
10716 #define DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT       (29U)
10717 /*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1
10718  *    : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact,
10719  *    because no dfi_ctrlupd_req will be issued when SRX.
10720  *  0b0..send ctrlupd after SRX
10721  *  0b1..send ctrlupd before SRX
10722  */
10723 #define DDRC_DFIUPD0_ctrlupd_pre_srx(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_DFIUPD0_ctrlupd_pre_srx_MASK)
10724 #define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK   (0x40000000U)
10725 #define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT  (30U)
10726 /*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation
10727  *  0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit.
10728  *  0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.
10729  */
10730 #define DDRC_DFIUPD0_dis_auto_ctrlupd_srx(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK)
10731 #define DDRC_DFIUPD0_dis_auto_ctrlupd_MASK       (0x80000000U)
10732 #define DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT      (31U)
10733 /*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC
10734  *  0b0..DDRC issues dfi_ctrlupd_req periodically.
10735  *  0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req
10736  *       signal using register reg_ddrc_ctrlupd.
10737  */
10738 #define DDRC_DFIUPD0_dis_auto_ctrlupd(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_MASK)
10739 /*! @} */
10740 
10741 /*! @name DFIUPD1 - DFI Update Register 1 */
10742 /*! @{ */
10743 #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU)
10744 #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U)
10745 /*! dfi_t_ctrlupd_interval_max_x1024 - This is the maximum amount of time between DDRC initiated DFI
10746  *    update requests. This timer resets with each update request; when the timer expires
10747  *    dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
10748  *    idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used
10749  *    to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain
10750  *    calibration over PVT, but frequent updates may impact performance. Minimum allowed value for
10751  *    this field is 1. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be
10752  *    greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 DFI clock cycles
10753  */
10754 #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK)
10755 #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U)
10756 #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U)
10757 /*! dfi_t_ctrlupd_interval_min_x1024 - This is the minimum amount of time between DDRC initiated DFI
10758  *    update requests (which is executed whenever the DDRC is idle). Set this number higher to
10759  *    reduce the frequency of update requests, which can have a small impact on the latency of the first
10760  *    read request when the DDRC is idle. Minimum allowed value for this field is 1. Unit: 1024 DFI
10761  *    clock cycles
10762  */
10763 #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK)
10764 /*! @} */
10765 
10766 /*! @name DFIUPD2 - DFI Update Register 2 */
10767 /*! @{ */
10768 #define DDRC_DFIUPD2_dfi_phyupd_en_MASK          (0x80000000U)
10769 #define DDRC_DFIUPD2_dfi_phyupd_en_SHIFT         (31U)
10770 /*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates:
10771  *  0b0..Disabled
10772  *  0b1..Enabled
10773  */
10774 #define DDRC_DFIUPD2_dfi_phyupd_en(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_DFIUPD2_dfi_phyupd_en_MASK)
10775 /*! @} */
10776 
10777 /*! @name DFIMISC - DFI Miscellaneous Control Register */
10778 /*! @{ */
10779 #define DDRC_DFIMISC_dfi_init_complete_en_MASK   (0x1U)
10780 #define DDRC_DFIMISC_dfi_init_complete_en_SHIFT  (0U)
10781 /*! dfi_init_complete_en - PHY initialization complete enable signal. When asserted the
10782  *    dfi_init_complete signal can be used to trigger SDRAM initialisation
10783  */
10784 #define DDRC_DFIMISC_dfi_init_complete_en(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_DFIMISC_dfi_init_complete_en_MASK)
10785 #define DDRC_DFIMISC_phy_dbi_mode_MASK           (0x2U)
10786 #define DDRC_DFIMISC_phy_dbi_mode_SHIFT          (1U)
10787 /*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4.
10788  *  0b0..DDRC implements DBI functionality.
10789  *  0b1..PHY implements DBI functionality.
10790  */
10791 #define DDRC_DFIMISC_phy_dbi_mode(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_DFIMISC_phy_dbi_mode_MASK)
10792 #define DDRC_DFIMISC_dfi_data_cs_polarity_MASK   (0x4U)
10793 #define DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT  (2U)
10794 /*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.
10795  *  0b0..Signals are active low
10796  *  0b1..Signals are active high
10797  */
10798 #define DDRC_DFIMISC_dfi_data_cs_polarity(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_DFIMISC_dfi_data_cs_polarity_MASK)
10799 #define DDRC_DFIMISC_ctl_idle_en_MASK            (0x10U)
10800 #define DDRC_DFIMISC_ctl_idle_en_SHIFT           (4U)
10801 /*! ctl_idle_en - Enables support of ctl_idle signal, which is non-DFI related pin specific to
10802  *    certain PHYs. See signal description of ctl_idle signal for further details of ctl_idle
10803  *    functionality.
10804  */
10805 #define DDRC_DFIMISC_ctl_idle_en(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_DFIMISC_ctl_idle_en_MASK)
10806 #define DDRC_DFIMISC_dfi_init_start_MASK         (0x20U)
10807 #define DDRC_DFIMISC_dfi_init_start_SHIFT        (5U)
10808 /*! dfi_init_start - PHY init start request signal.When asserted it triggers the PHY init start request
10809  */
10810 #define DDRC_DFIMISC_dfi_init_start(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_start_SHIFT)) & DDRC_DFIMISC_dfi_init_start_MASK)
10811 #define DDRC_DFIMISC_dfi_frequency_MASK          (0x1F00U)
10812 #define DDRC_DFIMISC_dfi_frequency_SHIFT         (8U)
10813 /*! dfi_frequency - Indicates the operating frequency of the system. The number of supported
10814  *    frequencies and the mapping of signal values to clock frequencies are defined by the PHY.
10815  */
10816 #define DDRC_DFIMISC_dfi_frequency(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_frequency_SHIFT)) & DDRC_DFIMISC_dfi_frequency_MASK)
10817 /*! @} */
10818 
10819 /*! @name DFITMG2 - DFI Timing Register 2 */
10820 /*! @{ */
10821 #define DDRC_DFITMG2_dfi_tphy_wrcslat_MASK       (0x3FU)
10822 #define DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT      (0U)
10823 /*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the
10824  *    DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds
10825  *    to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
10826  */
10827 #define DDRC_DFITMG2_dfi_tphy_wrcslat(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_wrcslat_MASK)
10828 #define DDRC_DFITMG2_dfi_tphy_rdcslat_MASK       (0x7F00U)
10829 #define DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT      (8U)
10830 /*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI
10831  *    control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds
10832  *    to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
10833  */
10834 #define DDRC_DFITMG2_dfi_tphy_rdcslat(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_rdcslat_MASK)
10835 /*! @} */
10836 
10837 /*! @name DFITMG3 - DFI Timing Register 3 */
10838 /*! @{ */
10839 #define DDRC_DFITMG3_dfi_t_geardown_delay_MASK   (0x1FU)
10840 #define DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT  (0U)
10841 /*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being
10842  *    ready to receive commands. Refer to PHY specification for correct value. When the controller is
10843  *    operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to
10844  *    the next integer value. Unit: Clocks
10845  */
10846 #define DDRC_DFITMG3_dfi_t_geardown_delay(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_dfi_t_geardown_delay_MASK)
10847 /*! @} */
10848 
10849 /*! @name DFISTAT - DFI Status Register */
10850 /*! @{ */
10851 #define DDRC_DFISTAT_dfi_init_complete_MASK      (0x1U)
10852 #define DDRC_DFISTAT_dfi_init_complete_SHIFT     (0U)
10853 /*! dfi_init_complete - The status flag register which announces when the DFI initialization has
10854  *    been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete
10855  *    flag is polled to know when the initialization is done.
10856  */
10857 #define DDRC_DFISTAT_dfi_init_complete(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_DFISTAT_dfi_init_complete_MASK)
10858 #define DDRC_DFISTAT_dfi_lp_ack_MASK             (0x2U)
10859 #define DDRC_DFISTAT_dfi_lp_ack_SHIFT            (1U)
10860 /*! dfi_lp_ack - Stores the value of the dfi_lp_ack input to the controller.
10861  */
10862 #define DDRC_DFISTAT_dfi_lp_ack(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_DFISTAT_dfi_lp_ack_MASK)
10863 /*! @} */
10864 
10865 /*! @name DBICTL - DM/DBI Control Register */
10866 /*! @{ */
10867 #define DDRC_DBICTL_dm_en_MASK                   (0x1U)
10868 #define DDRC_DBICTL_dm_en_SHIFT                  (0U)
10869 /*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode
10870  *    register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal
10871  *    must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity
10872  *    from this signal
10873  *  0b0..DM is disabled
10874  *  0b1..DM is enabled
10875  */
10876 #define DDRC_DBICTL_dm_en(x)                     (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_dm_en_SHIFT)) & DDRC_DBICTL_dm_en_MASK)
10877 #define DDRC_DBICTL_wr_dbi_en_MASK               (0x2U)
10878 #define DDRC_DBICTL_wr_dbi_en_SHIFT              (1U)
10879 /*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11.
10880  *    When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
10881  *  0b0..Write DBI is disabled
10882  *  0b1..Write DBI is enabled.
10883  */
10884 #define DDRC_DBICTL_wr_dbi_en(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_wr_dbi_en_SHIFT)) & DDRC_DBICTL_wr_dbi_en_MASK)
10885 #define DDRC_DBICTL_rd_dbi_en_MASK               (0x4U)
10886 #define DDRC_DBICTL_rd_dbi_en_SHIFT              (2U)
10887 /*! rd_dbi_en - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is
10888  *    enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A12. When
10889  *    x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
10890  */
10891 #define DDRC_DBICTL_rd_dbi_en(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_rd_dbi_en_SHIFT)) & DDRC_DBICTL_rd_dbi_en_MASK)
10892 /*! @} */
10893 
10894 /*! @name ADDRMAP0 - Address Map Register 0 */
10895 /*! @{ */
10896 #define DDRC_ADDRMAP0_addrmap_cs_bit0_MASK       (0x1FU)
10897 #define DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT      (0U)
10898 /*! addrmap_cs_bit0 - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 28,
10899  *    and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base
10900  *    to the value of this field. If set to 31, rank address bit 0 is set to 0.
10901  */
10902 #define DDRC_ADDRMAP0_addrmap_cs_bit0(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_ADDRMAP0_addrmap_cs_bit0_MASK)
10903 /*! @} */
10904 
10905 /*! @name ADDRMAP1 - Address Map Register 1 */
10906 /*! @{ */
10907 #define DDRC_ADDRMAP1_addrmap_bank_b0_MASK       (0x1FU)
10908 #define DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT      (0U)
10909 /*! addrmap_bank_b0 - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 31
10910  *    Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined
10911  *    by adding the internal base to the value of this field.
10912  */
10913 #define DDRC_ADDRMAP1_addrmap_bank_b0(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b0_MASK)
10914 #define DDRC_ADDRMAP1_addrmap_bank_b1_MASK       (0x1F00U)
10915 #define DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT      (8U)
10916 /*! addrmap_bank_b1 - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 31
10917  *    Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined
10918  *    by adding the internal base to the value of this field.
10919  */
10920 #define DDRC_ADDRMAP1_addrmap_bank_b1(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b1_MASK)
10921 #define DDRC_ADDRMAP1_addrmap_bank_b2_MASK       (0x1F0000U)
10922 #define DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT      (16U)
10923 /*! addrmap_bank_b2 - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 30
10924  *    and 31 Internal Base: 4 The selected HIF address bit is determined by adding the internal base
10925  *    to the value of this field. If set to 31, bank address bit 2 is set to 0.
10926  */
10927 #define DDRC_ADDRMAP1_addrmap_bank_b2(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b2_MASK)
10928 /*! @} */
10929 
10930 /*! @name ADDRMAP2 - Address Map Register 2 */
10931 /*! @{ */
10932 #define DDRC_ADDRMAP2_addrmap_col_b2_MASK        (0xFU)
10933 #define DDRC_ADDRMAP2_addrmap_col_b2_SHIFT       (0U)
10934 /*! addrmap_col_b2 - - Full bus width mode: Selects the HIF address bit used as column address bit
10935  *    2. - Half bus width mode: Selects the HIF address bit used as column address bit 3. - Quarter
10936  *    bus width mode: Selects the HIF address bit used as column address bit 4. Valid Range: 0 to 7
10937  *    Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the
10938  *    value of this field. Note, if DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to
10939  *    program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and -
10940  *    PCCFG.bl_exp_mode==1 and either - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or - In LPDDR4 and
10941  *    ADDRMAP1.addrmap_bank_b0==0 If DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to
10942  *    0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1
10943  *    and - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus
10944  *    Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to
10945  *    column address bit 2. If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it
10946  *    is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If
10947  *    MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is recommended to program this to 0
10948  *    so that HIF[2] maps to column address bit 3.
10949  */
10950 #define DDRC_ADDRMAP2_addrmap_col_b2(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b2_MASK)
10951 #define DDRC_ADDRMAP2_addrmap_col_b3_MASK        (0xF00U)
10952 #define DDRC_ADDRMAP2_addrmap_col_b3_SHIFT       (8U)
10953 /*! addrmap_col_b3 - - Full bus width mode: Selects the HIF address bit used as column address bit
10954  *    3. - Half bus width mode: Selects the HIF address bit used as column address bit 4. - Quarter
10955  *    bus width mode: Selects the HIF address bit used as column address bit 5. Valid Range: 0 to 7
10956  *    Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the
10957  *    value of this field. Note, if DDRC_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width
10958  *    (MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to program this to 0.
10959  */
10960 #define DDRC_ADDRMAP2_addrmap_col_b3(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b3_MASK)
10961 #define DDRC_ADDRMAP2_addrmap_col_b4_MASK        (0xF0000U)
10962 #define DDRC_ADDRMAP2_addrmap_col_b4_SHIFT       (16U)
10963 /*! addrmap_col_b4 - - Full bus width mode: Selects the HIF address bit used as column address bit
10964  *    4. - Half bus width mode: Selects the HIF address bit used as column address bit 5. - Quarter
10965  *    bus width mode: Selects the HIF address bit used as column address bit 6. Valid Range: 0 to 7,
10966  *    and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base
10967  *    to the value of this field. If set to 15, this column address bit is set to 0.
10968  */
10969 #define DDRC_ADDRMAP2_addrmap_col_b4(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b4_MASK)
10970 #define DDRC_ADDRMAP2_addrmap_col_b5_MASK        (0xF000000U)
10971 #define DDRC_ADDRMAP2_addrmap_col_b5_SHIFT       (24U)
10972 /*! addrmap_col_b5 - - Full bus width mode: Selects the HIF address bit used as column address bit
10973  *    5. - Half bus width mode: Selects the HIF address bit used as column address bit 6. - Quarter
10974  *    bus width mode: Selects the HIF address bit used as column address bit 7 . Valid Range: 0 to 7,
10975  *    and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal
10976  *    base to the value of this field. If set to 15, this column address bit is set to 0.
10977  */
10978 #define DDRC_ADDRMAP2_addrmap_col_b5(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b5_MASK)
10979 /*! @} */
10980 
10981 /*! @name ADDRMAP3 - Address Map Register 3 */
10982 /*! @{ */
10983 #define DDRC_ADDRMAP3_addrmap_col_b6_MASK        (0xFU)
10984 #define DDRC_ADDRMAP3_addrmap_col_b6_SHIFT       (0U)
10985 /*! addrmap_col_b6 - - Full bus width mode: Selects the HIF address bit used as column address bit
10986  *    6. - Half bus width mode: Selects the HIF address bit used as column address bit 7. - Quarter
10987  *    bus width mode: Selects the HIF address bit used as column address bit 8. Valid Range: 0 to 7,
10988  *    and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base
10989  *    to the value of this field. If set to 15, this column address bit is set to 0.
10990  */
10991 #define DDRC_ADDRMAP3_addrmap_col_b6(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b6_MASK)
10992 #define DDRC_ADDRMAP3_addrmap_col_b7_MASK        (0xF00U)
10993 #define DDRC_ADDRMAP3_addrmap_col_b7_SHIFT       (8U)
10994 /*! addrmap_col_b7 - - Full bus width mode: Selects the HIF address bit used as column address bit
10995  *    7. - Half bus width mode: Selects the HIF address bit used as column address bit 8. - Quarter
10996  *    bus width mode: Selects the HIF address bit used as column address bit 9. Valid Range: 0 to 7,
10997  *    and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base
10998  *    to the value of this field. If set to 15, this column address bit is set to 0.
10999  */
11000 #define DDRC_ADDRMAP3_addrmap_col_b7(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b7_MASK)
11001 #define DDRC_ADDRMAP3_addrmap_col_b8_MASK        (0xF0000U)
11002 #define DDRC_ADDRMAP3_addrmap_col_b8_SHIFT       (16U)
11003 /*! addrmap_col_b8 - - Full bus width mode: Selects the HIF address bit used as column address bit
11004  *    8. - Half bus width mode: Selects the HIF address bit used as column address bit 9. - Quarter
11005  *    bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3
11006  *    mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined
11007  *    by adding the internal base to the value of this field. If set to 15, this column address bit
11008  *    is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for
11009  *    indicating auto-precharge, and hence no source address bit can be mapped to column address
11010  *    bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence
11011  *    column bit 10 is used.
11012  */
11013 #define DDRC_ADDRMAP3_addrmap_col_b8(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b8_MASK)
11014 #define DDRC_ADDRMAP3_addrmap_col_b9_MASK        (0xF000000U)
11015 #define DDRC_ADDRMAP3_addrmap_col_b9_SHIFT       (24U)
11016 /*! addrmap_col_b9 - - Full bus width mode: Selects the HIF address bit used as column address bit
11017  *    9. - Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in
11018  *    LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as column address
11019  *    bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
11020  *    HIF address bit is determined by adding the internal base to the value of this field. If set to
11021  *    15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column
11022  *    address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be
11023  *    mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
11024  *    auto-precharge in the CA bus and hence column bit 10 is used.
11025  */
11026 #define DDRC_ADDRMAP3_addrmap_col_b9(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b9_MASK)
11027 /*! @} */
11028 
11029 /*! @name ADDRMAP4 - Address Map Register 4 */
11030 /*! @{ */
11031 #define DDRC_ADDRMAP4_addrmap_col_b10_MASK       (0xFU)
11032 #define DDRC_ADDRMAP4_addrmap_col_b10_SHIFT      (0U)
11033 /*! addrmap_col_b10 - - Full bus width mode: Selects the HIF address bit used as column address bit
11034  *    11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the HIF address bit used as
11035  *    column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. To make it
11036  *    unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
11037  *    address bit is determined by adding the internal base to the value of this field. If set to
11038  *    15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column
11039  *    address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be
11040  *    mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge
11041  *    in the CA bus and hence column bit 10 is used.
11042  */
11043 #define DDRC_ADDRMAP4_addrmap_col_b10(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b10_MASK)
11044 #define DDRC_ADDRMAP4_addrmap_col_b11_MASK       (0xF00U)
11045 #define DDRC_ADDRMAP4_addrmap_col_b11_SHIFT      (8U)
11046 /*! addrmap_col_b11 - - Full bus width mode: Selects the HIF address bit used as column address bit
11047  *    13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To make it unused, this should
11048  *    be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must be tied to
11049  *    4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by
11050  *    adding the internal base to the value of this field. If set to 15, this column address bit is
11051  *    set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for
11052  *    indicating auto-precharge, and hence no source address bit can be mapped to column address bit
11053  *    10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column
11054  *    bit 10 is used.
11055  */
11056 #define DDRC_ADDRMAP4_addrmap_col_b11(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b11_MASK)
11057 /*! @} */
11058 
11059 /*! @name ADDRMAP5 - Address Map Register 5 */
11060 /*! @{ */
11061 #define DDRC_ADDRMAP5_addrmap_row_b0_MASK        (0xFU)
11062 #define DDRC_ADDRMAP5_addrmap_row_b0_SHIFT       (0U)
11063 /*! addrmap_row_b0 - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11
11064  *    Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by
11065  *    adding the internal base to the value of this field.
11066  */
11067 #define DDRC_ADDRMAP5_addrmap_row_b0(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b0_MASK)
11068 #define DDRC_ADDRMAP5_addrmap_row_b1_MASK        (0xF00U)
11069 #define DDRC_ADDRMAP5_addrmap_row_b1_SHIFT       (8U)
11070 /*! addrmap_row_b1 - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11
11071  *    Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by
11072  *    adding the internal base to the value of this field.
11073  */
11074 #define DDRC_ADDRMAP5_addrmap_row_b1(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b1_MASK)
11075 #define DDRC_ADDRMAP5_addrmap_row_b2_10_MASK     (0xF0000U)
11076 #define DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT    (16U)
11077 /*! addrmap_row_b2_10 - Selects the HIF address bits used as row address bits 2 to 10. Valid Range:
11078  *    0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for
11079  *    row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit
11080  *    for each of the row address bits is determined by adding the internal base to the value of this
11081  *    field. When value 15 is used the values of row address bits 2 to 10 are defined by registers
11082  *    ADDRMAP9, ADDRMAP10, ADDRMAP11.
11083  */
11084 #define DDRC_ADDRMAP5_addrmap_row_b2_10(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b2_10_MASK)
11085 #define DDRC_ADDRMAP5_addrmap_row_b11_MASK       (0xF000000U)
11086 #define DDRC_ADDRMAP5_addrmap_row_b11_SHIFT      (24U)
11087 /*! addrmap_row_b11 - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11,
11088  *    and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal
11089  *    base to the value of this field. If set to 15, row address bit 11 is set to 0.
11090  */
11091 #define DDRC_ADDRMAP5_addrmap_row_b11(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b11_MASK)
11092 /*! @} */
11093 
11094 /*! @name ADDRMAP6 - Address Map Register 6 */
11095 /*! @{ */
11096 #define DDRC_ADDRMAP6_addrmap_row_b12_MASK       (0xFU)
11097 #define DDRC_ADDRMAP6_addrmap_row_b12_SHIFT      (0U)
11098 /*! addrmap_row_b12 - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11,
11099  *    and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal
11100  *    base to the value of this field. If set to 15, row address bit 12 is set to 0.
11101  */
11102 #define DDRC_ADDRMAP6_addrmap_row_b12(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b12_MASK)
11103 #define DDRC_ADDRMAP6_addrmap_row_b13_MASK       (0xF00U)
11104 #define DDRC_ADDRMAP6_addrmap_row_b13_SHIFT      (8U)
11105 /*! addrmap_row_b13 - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11,
11106  *    and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal
11107  *    base to the value of this field. If set to 15, row address bit 13 is set to 0.
11108  */
11109 #define DDRC_ADDRMAP6_addrmap_row_b13(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b13_MASK)
11110 #define DDRC_ADDRMAP6_addrmap_row_b14_MASK       (0xF0000U)
11111 #define DDRC_ADDRMAP6_addrmap_row_b14_SHIFT      (16U)
11112 /*! addrmap_row_b14 - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11,
11113  *    and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal
11114  *    base to the value of this field. If set to 15, row address bit 14 is set to 0.
11115  */
11116 #define DDRC_ADDRMAP6_addrmap_row_b14(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b14_MASK)
11117 #define DDRC_ADDRMAP6_addrmap_row_b15_MASK       (0xF000000U)
11118 #define DDRC_ADDRMAP6_addrmap_row_b15_SHIFT      (24U)
11119 /*! addrmap_row_b15 - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11,
11120  *    and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal
11121  *    base to the value of this field. If set to 15, row address bit 15 is set to 0.
11122  */
11123 #define DDRC_ADDRMAP6_addrmap_row_b15(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b15_MASK)
11124 #define DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK       (0x80000000U)
11125 #define DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT      (31U)
11126 /*! lpddr3_6gb_12gb - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 -
11127  *    LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as
11128  *    invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present only in designs
11129  *    configured to support LPDDR3.
11130  */
11131 #define DDRC_ADDRMAP6_lpddr3_6gb_12gb(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK)
11132 /*! @} */
11133 
11134 /*! @name ADDRMAP7 - Address Map Register 7 */
11135 /*! @{ */
11136 #define DDRC_ADDRMAP7_addrmap_row_b16_MASK       (0xFU)
11137 #define DDRC_ADDRMAP7_addrmap_row_b16_SHIFT      (0U)
11138 /*! addrmap_row_b16 - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11,
11139  *    and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal
11140  *    base to the value of this field. If set to 15, row address bit 16 is set to 0.
11141  */
11142 #define DDRC_ADDRMAP7_addrmap_row_b16(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b16_MASK)
11143 #define DDRC_ADDRMAP7_addrmap_row_b17_MASK       (0xF00U)
11144 #define DDRC_ADDRMAP7_addrmap_row_b17_SHIFT      (8U)
11145 /*! addrmap_row_b17 - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11,
11146  *    and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal
11147  *    base to the value of this field. If set to 15, row address bit 17 is set to 0.
11148  */
11149 #define DDRC_ADDRMAP7_addrmap_row_b17(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b17_MASK)
11150 /*! @} */
11151 
11152 /*! @name ADDRMAP8 - Address Map Register 8 */
11153 /*! @{ */
11154 #define DDRC_ADDRMAP8_addrmap_bg_b0_MASK         (0x1FU)
11155 #define DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT        (0U)
11156 /*! addrmap_bg_b0 - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to
11157  *    31 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is
11158  *    determined by adding the internal base to the value of this field.
11159  */
11160 #define DDRC_ADDRMAP8_addrmap_bg_b0(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b0_MASK)
11161 #define DDRC_ADDRMAP8_addrmap_bg_b1_MASK         (0x3F00U)
11162 #define DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT        (8U)
11163 /*! addrmap_bg_b1 - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to
11164  *    31, and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address
11165  *    bits is determined by adding the internal base to the value of this field. If set to 63, bank
11166  *    group address bit 1 is set to 0.
11167  */
11168 #define DDRC_ADDRMAP8_addrmap_bg_b1(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b1_MASK)
11169 /*! @} */
11170 
11171 /*! @name ADDRMAP9 - Address Map Register 9 */
11172 /*! @{ */
11173 #define DDRC_ADDRMAP9_addrmap_row_b2_MASK        (0xFU)
11174 #define DDRC_ADDRMAP9_addrmap_row_b2_SHIFT       (0U)
11175 /*! addrmap_row_b2 - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11
11176  *    Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by
11177  *    adding the internal base to the value of this field. This register field is used only when
11178  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11179  */
11180 #define DDRC_ADDRMAP9_addrmap_row_b2(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b2_MASK)
11181 #define DDRC_ADDRMAP9_addrmap_row_b3_MASK        (0xF00U)
11182 #define DDRC_ADDRMAP9_addrmap_row_b3_SHIFT       (8U)
11183 /*! addrmap_row_b3 - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11
11184  *    Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by
11185  *    adding the internal base to the value of this field. This register field is used only when
11186  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11187  */
11188 #define DDRC_ADDRMAP9_addrmap_row_b3(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b3_MASK)
11189 #define DDRC_ADDRMAP9_addrmap_row_b4_MASK        (0xF0000U)
11190 #define DDRC_ADDRMAP9_addrmap_row_b4_SHIFT       (16U)
11191 /*! addrmap_row_b4 - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11
11192  *    Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by
11193  *    adding the internal base to the value of this field. This register field is used only when
11194  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11195  */
11196 #define DDRC_ADDRMAP9_addrmap_row_b4(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b4_MASK)
11197 #define DDRC_ADDRMAP9_addrmap_row_b5_MASK        (0xF000000U)
11198 #define DDRC_ADDRMAP9_addrmap_row_b5_SHIFT       (24U)
11199 /*! addrmap_row_b5 - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11
11200  *    Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by
11201  *    adding the internal base to the value of this field. This register field is used only when
11202  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11203  */
11204 #define DDRC_ADDRMAP9_addrmap_row_b5(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b5_MASK)
11205 /*! @} */
11206 
11207 /*! @name ADDRMAP10 - Address Map Register 10 */
11208 /*! @{ */
11209 #define DDRC_ADDRMAP10_addrmap_row_b6_MASK       (0xFU)
11210 #define DDRC_ADDRMAP10_addrmap_row_b6_SHIFT      (0U)
11211 /*! addrmap_row_b6 - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11
11212  *    Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by
11213  *    adding the internal base to the value of this field. This register field is used only when
11214  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11215  */
11216 #define DDRC_ADDRMAP10_addrmap_row_b6(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b6_MASK)
11217 #define DDRC_ADDRMAP10_addrmap_row_b7_MASK       (0xF00U)
11218 #define DDRC_ADDRMAP10_addrmap_row_b7_SHIFT      (8U)
11219 /*! addrmap_row_b7 - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11
11220  *    Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by
11221  *    adding the internal base to the value of this field. This register field is used only when
11222  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11223  */
11224 #define DDRC_ADDRMAP10_addrmap_row_b7(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b7_MASK)
11225 #define DDRC_ADDRMAP10_addrmap_row_b8_MASK       (0xF0000U)
11226 #define DDRC_ADDRMAP10_addrmap_row_b8_SHIFT      (16U)
11227 /*! addrmap_row_b8 - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11
11228  *    Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by
11229  *    adding the internal base to the value of this field. This register field is used only when
11230  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11231  */
11232 #define DDRC_ADDRMAP10_addrmap_row_b8(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b8_MASK)
11233 #define DDRC_ADDRMAP10_addrmap_row_b9_MASK       (0xF000000U)
11234 #define DDRC_ADDRMAP10_addrmap_row_b9_SHIFT      (24U)
11235 /*! addrmap_row_b9 - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11
11236  *    Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by
11237  *    adding the internal base to the value of this field. This register field is used only when
11238  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11239  */
11240 #define DDRC_ADDRMAP10_addrmap_row_b9(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b9_MASK)
11241 /*! @} */
11242 
11243 /*! @name ADDRMAP11 - Address Map Register 11 */
11244 /*! @{ */
11245 #define DDRC_ADDRMAP11_addrmap_row_b10_MASK      (0xFU)
11246 #define DDRC_ADDRMAP11_addrmap_row_b10_SHIFT     (0U)
11247 /*! addrmap_row_b10 - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11
11248  *    Internal Base: 16 The selected HIF address bit for each of the row address bits is determined
11249  *    by adding the internal base to the value of this field. This register field is used only when
11250  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11251  */
11252 #define DDRC_ADDRMAP11_addrmap_row_b10(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_ADDRMAP11_addrmap_row_b10_MASK)
11253 /*! @} */
11254 
11255 /*! @name ODTCFG - ODT Configuration Register */
11256 /*! @{ */
11257 #define DDRC_ODTCFG_rd_odt_delay_MASK            (0x7CU)
11258 #define DDRC_ODTCFG_rd_odt_delay_SHIFT           (2U)
11259 /*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT
11260  *    values associated with that command. ODT setting must remain constant for the entire time that
11261  *    DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5
11262  *    (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL -
11263  *    CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL
11264  *    mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write
11265  *    preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does
11266  *    not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
11267  */
11268 #define DDRC_ODTCFG_rd_odt_delay(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_rd_odt_delay_MASK)
11269 #define DDRC_ODTCFG_rd_odt_hold_MASK             (0xF00U)
11270 #define DDRC_ODTCFG_rd_odt_hold_SHIFT            (8U)
11271 /*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value
11272  *    is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not
11273  *    DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK
11274  *    write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) -
11275  *    RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
11276  */
11277 #define DDRC_ODTCFG_rd_odt_hold(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_rd_odt_hold_MASK)
11278 #define DDRC_ODTCFG_wr_odt_delay_MASK            (0x1F0000U)
11279 #define DDRC_ODTCFG_wr_odt_delay_SHIFT           (16U)
11280 /*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT
11281  *    values associated with that command. ODT setting must remain constant for the entire time that
11282  *    DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL +
11283  *    AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT
11284  *    for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3:
11285  *    - WL - 1 - RU(tODTon(max)/tCK))
11286  */
11287 #define DDRC_ODTCFG_wr_odt_delay(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_wr_odt_delay_MASK)
11288 #define DDRC_ODTCFG_wr_odt_hold_MASK             (0xF000000U)
11289 #define DDRC_ODTCFG_wr_odt_hold_SHIFT            (24U)
11290 /*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value
11291  *    is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
11292  *    - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8:
11293  *    5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
11294  *    CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
11295  */
11296 #define DDRC_ODTCFG_wr_odt_hold(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_wr_odt_hold_MASK)
11297 /*! @} */
11298 
11299 /*! @name ODTMAP - ODT/Rank Map Register */
11300 /*! @{ */
11301 #define DDRC_ODTMAP_rank0_wr_odt_MASK            (0x3U)
11302 #define DDRC_ODTMAP_rank0_wr_odt_SHIFT           (0U)
11303 /*! rank0_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank
11304  *    has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
11305  *    Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
11306  *    rank, set its bit to 1 to enable its ODT.
11307  */
11308 #define DDRC_ODTMAP_rank0_wr_odt(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_ODTMAP_rank0_wr_odt_MASK)
11309 #define DDRC_ODTMAP_rank0_rd_odt_MASK            (0x30U)
11310 #define DDRC_ODTMAP_rank0_rd_odt_SHIFT           (4U)
11311 /*! rank0_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 0. Each
11312  *    rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
11313  *    Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
11314  *    rank, set its bit to 1 to enable its ODT.
11315  */
11316 #define DDRC_ODTMAP_rank0_rd_odt(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_ODTMAP_rank0_rd_odt_MASK)
11317 #define DDRC_ODTMAP_rank1_wr_odt_MASK            (0x300U)
11318 #define DDRC_ODTMAP_rank1_wr_odt_SHIFT           (8U)
11319 /*! rank1_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank
11320  *    has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
11321  *    Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
11322  *    rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
11323  */
11324 #define DDRC_ODTMAP_rank1_wr_odt(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_ODTMAP_rank1_wr_odt_MASK)
11325 #define DDRC_ODTMAP_rank1_rd_odt_MASK            (0x3000U)
11326 #define DDRC_ODTMAP_rank1_rd_odt_SHIFT           (12U)
11327 /*! rank1_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 1. Each
11328  *    rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
11329  *    Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
11330  *    rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more
11331  *    ranks
11332  */
11333 #define DDRC_ODTMAP_rank1_rd_odt(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_ODTMAP_rank1_rd_odt_MASK)
11334 /*! @} */
11335 
11336 /*! @name SCHED - Scheduler Control Register */
11337 /*! @{ */
11338 #define DDRC_SCHED_force_low_pri_n_MASK          (0x1U)
11339 #define DDRC_SCHED_force_low_pri_n_SHIFT         (0U)
11340 /*! force_low_pri_n - Active low signal. When asserted ('0'), all incoming transactions are forced
11341  *    to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read
11342  *    commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all
11343  *    Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands.
11344  *    Forcing the incoming transactions to low priority implicitly turns off Bypass path for read
11345  *    commands. FOR PERFORMANCE ONLY.
11346  */
11347 #define DDRC_SCHED_force_low_pri_n(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_force_low_pri_n_SHIFT)) & DDRC_SCHED_force_low_pri_n_MASK)
11348 #define DDRC_SCHED_prefer_write_MASK             (0x2U)
11349 #define DDRC_SCHED_prefer_write_SHIFT            (1U)
11350 /*! prefer_write - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
11351  */
11352 #define DDRC_SCHED_prefer_write(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_prefer_write_SHIFT)) & DDRC_SCHED_prefer_write_MASK)
11353 #define DDRC_SCHED_pageclose_MASK                (0x4U)
11354 #define DDRC_SCHED_pageclose_SHIFT               (2U)
11355 /*! pageclose - If true, bank is kept open only while there are page hit transactions available in
11356  *    the CAM to that bank. The last read or write command in the CAM with a bank and page hit will
11357  *    be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and
11358  *    SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued
11359  *    in some cases where there is a mode switch between Write and Read or between LPR and HPR. The
11360  *    Read and Write commands that are executed as part of the ECC scrub requests are also executed
11361  *    without auto-precharge. If false, the bank remains open until there is a need to close it (to
11362  *    open a different page, or for page timeout or refresh timeout) - also known as open page
11363  *    policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF
11364  *    interface (hif_cmd_autopre). The pageclose feature provids a midway between Open and Close page
11365  *    policies. FOR PERFORMANCE ONLY.
11366  */
11367 #define DDRC_SCHED_pageclose(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_pageclose_SHIFT)) & DDRC_SCHED_pageclose_MASK)
11368 #define DDRC_SCHED_lpr_num_entries_MASK          (0x1F00U)
11369 #define DDRC_SCHED_lpr_num_entries_SHIFT         (8U)
11370 /*! lpr_num_entries - Number of entries in the low priority transaction store is this value + 1.
11371  *    (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high
11372  *    priority transaction store. Setting this to maximum value allocates all entries to low
11373  *    priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and
11374  *    the rest to high priority transaction store. Note: In ECC configurations, the numbers of
11375  *    write and low priority read credits issued is one less than in the non-ECC case. One entry each is
11376  *    reserved in the write and low-priority read CAMs for storing the RMW requests arising out of
11377  *    single bit error correction RMW operation.
11378  */
11379 #define DDRC_SCHED_lpr_num_entries(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_lpr_num_entries_SHIFT)) & DDRC_SCHED_lpr_num_entries_MASK)
11380 #define DDRC_SCHED_go2critical_hysteresis_MASK   (0xFF0000U)
11381 #define DDRC_SCHED_go2critical_hysteresis_SHIFT  (16U)
11382 /*! go2critical_hysteresis - UNUSED
11383  */
11384 #define DDRC_SCHED_go2critical_hysteresis(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_SCHED_go2critical_hysteresis_MASK)
11385 #define DDRC_SCHED_rdwr_idle_gap_MASK            (0x7F000000U)
11386 #define DDRC_SCHED_rdwr_idle_gap_SHIFT           (24U)
11387 /*! rdwr_idle_gap - When the preferred transaction store is empty for these many clock cycles,
11388  *    switch to the alternate transaction store if it is non-empty. The read transaction store (both high
11389  *    and low priority) is the default preferred transaction store and the write transaction store
11390  *    is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal
11391  *    value for this register. When set to 0x0, the transaction store switching will happen
11392  *    immediately when the switching conditions become true. FOR PERFORMANCE ONLY
11393  */
11394 #define DDRC_SCHED_rdwr_idle_gap(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_SCHED_rdwr_idle_gap_MASK)
11395 /*! @} */
11396 
11397 /*! @name SCHED1 - Scheduler Control Register 1 */
11398 /*! @{ */
11399 #define DDRC_SCHED1_pageclose_timer_MASK         (0xFFU)
11400 #define DDRC_SCHED1_pageclose_timer_SHIFT        (0U)
11401 /*! pageclose_timer - This field works in conjunction with SCHED.pageclose. It only has meaning if
11402  *    SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be
11403  *    scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes
11404  *    an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for
11405  *    details of when this may happen. If SCHED.pageclose==1 and pageclose_timer>0, then an
11406  *    auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit.
11407  *    Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per
11408  *    bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page
11409  *    hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a
11410  *    page hit. Once the timer has reached zero, an explcit precharge will be attempted to be
11411  *    scheduled.
11412  */
11413 #define DDRC_SCHED1_pageclose_timer(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_pageclose_timer_SHIFT)) & DDRC_SCHED1_pageclose_timer_MASK)
11414 /*! @} */
11415 
11416 /*! @name PERFHPR1 - High Priority Read CAM Register 1 */
11417 /*! @{ */
11418 #define DDRC_PERFHPR1_hpr_max_starve_MASK        (0xFFFFU)
11419 #define DDRC_PERFHPR1_hpr_max_starve_SHIFT       (0U)
11420 /*! hpr_max_starve - Number of DFI clocks that the HPR queue can be starved before it goes critical.
11421  *    The minimum valid functional value for this register is 0x1. Programming it to 0x0 will
11422  *    disable the starvation functionality; during normal operation, this function should not be disabled
11423  *    as it will cause excessive latencies. FOR PERFORMANCE ONLY.
11424  */
11425 #define DDRC_PERFHPR1_hpr_max_starve(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_PERFHPR1_hpr_max_starve_MASK)
11426 #define DDRC_PERFHPR1_hpr_xact_run_length_MASK   (0xFF000000U)
11427 #define DDRC_PERFHPR1_hpr_xact_run_length_SHIFT  (24U)
11428 /*! hpr_xact_run_length - Number of transactions that are serviced once the HPR queue goes critical
11429  *    is the smaller of: - (a) This number - (b) Number of transactions available. Unit:
11430  *    Transaction. FOR PERFORMANCE ONLY.
11431  */
11432 #define DDRC_PERFHPR1_hpr_xact_run_length(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_PERFHPR1_hpr_xact_run_length_MASK)
11433 /*! @} */
11434 
11435 /*! @name PERFLPR1 - Low Priority Read CAM Register 1 */
11436 /*! @{ */
11437 #define DDRC_PERFLPR1_lpr_max_starve_MASK        (0xFFFFU)
11438 #define DDRC_PERFLPR1_lpr_max_starve_SHIFT       (0U)
11439 /*! lpr_max_starve - Number of DFI clocks that the LPR queue can be starved before it goes critical.
11440  *    The minimum valid functional value for this register is 0x1. Programming it to 0x0 will
11441  *    disable the starvation functionality; during normal operation, this function should not be disabled
11442  *    as it will cause excessive latencies. FOR PERFORMANCE ONLY.
11443  */
11444 #define DDRC_PERFLPR1_lpr_max_starve(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_PERFLPR1_lpr_max_starve_MASK)
11445 #define DDRC_PERFLPR1_lpr_xact_run_length_MASK   (0xFF000000U)
11446 #define DDRC_PERFLPR1_lpr_xact_run_length_SHIFT  (24U)
11447 /*! lpr_xact_run_length - Number of transactions that are serviced once the LPR queue goes critical
11448  *    is the smaller of: - (a) This number - (b) Number of transactions available. Unit:
11449  *    Transaction. FOR PERFORMANCE ONLY.
11450  */
11451 #define DDRC_PERFLPR1_lpr_xact_run_length(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_PERFLPR1_lpr_xact_run_length_MASK)
11452 /*! @} */
11453 
11454 /*! @name PERFWR1 - Write CAM Register 1 */
11455 /*! @{ */
11456 #define DDRC_PERFWR1_w_max_starve_MASK           (0xFFFFU)
11457 #define DDRC_PERFWR1_w_max_starve_SHIFT          (0U)
11458 /*! w_max_starve - Number of DFI clocks that the WR queue can be starved before it goes critical.
11459  *    The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable
11460  *    the starvation functionality; during normal operation, this function should not be disabled as
11461  *    it will cause excessive latencies. FOR PERFORMANCE ONLY.
11462  */
11463 #define DDRC_PERFWR1_w_max_starve(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_max_starve_SHIFT)) & DDRC_PERFWR1_w_max_starve_MASK)
11464 #define DDRC_PERFWR1_w_xact_run_length_MASK      (0xFF000000U)
11465 #define DDRC_PERFWR1_w_xact_run_length_SHIFT     (24U)
11466 /*! w_xact_run_length - Number of transactions that are serviced once the WR queue goes critical is
11467  *    the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction.
11468  *    FOR PERFORMANCE ONLY.
11469  */
11470 #define DDRC_PERFWR1_w_xact_run_length(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_PERFWR1_w_xact_run_length_MASK)
11471 /*! @} */
11472 
11473 /*! @name DBG0 - Debug Register 0 */
11474 /*! @{ */
11475 #define DDRC_DBG0_dis_wc_MASK                    (0x1U)
11476 #define DDRC_DBG0_dis_wc_SHIFT                   (0U)
11477 /*! dis_wc - When 1, disable write combine. FOR DEBUG ONLY
11478  */
11479 #define DDRC_DBG0_dis_wc(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_wc_SHIFT)) & DDRC_DBG0_dis_wc_MASK)
11480 #define DDRC_DBG0_dis_rd_bypass_MASK             (0x2U)
11481 #define DDRC_DBG0_dis_rd_bypass_SHIFT            (1U)
11482 /*! dis_rd_bypass - Only present in designs supporting read bypass. When 1, disable bypass path for
11483  *    high priority read page hits FOR DEBUG ONLY.
11484  */
11485 #define DDRC_DBG0_dis_rd_bypass(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_rd_bypass_SHIFT)) & DDRC_DBG0_dis_rd_bypass_MASK)
11486 #define DDRC_DBG0_dis_act_bypass_MASK            (0x4U)
11487 #define DDRC_DBG0_dis_act_bypass_SHIFT           (2U)
11488 /*! dis_act_bypass - Only present in designs supporting activate bypass. When 1, disable bypass path
11489  *    for high priority read activates FOR DEBUG ONLY.
11490  */
11491 #define DDRC_DBG0_dis_act_bypass(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_act_bypass_SHIFT)) & DDRC_DBG0_dis_act_bypass_MASK)
11492 #define DDRC_DBG0_dis_collision_page_opt_MASK    (0x10U)
11493 #define DDRC_DBG0_dis_collision_page_opt_SHIFT   (4U)
11494 /*! dis_collision_page_opt - When this is set to '0', auto-precharge is disabled for the flushed
11495  *    command in a collision case. Collision cases are write followed by read to same address, read
11496  *    followed by write to same address, or write followed by write to same address with DBG0.dis_wc
11497  *    bit = 1 (where same address comparisons exclude the two address bits representing critical
11498  *    word). FOR DEBUG ONLY.
11499  */
11500 #define DDRC_DBG0_dis_collision_page_opt(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_collision_page_opt_SHIFT)) & DDRC_DBG0_dis_collision_page_opt_MASK)
11501 /*! @} */
11502 
11503 /*! @name DBG1 - Debug Register 1 */
11504 /*! @{ */
11505 #define DDRC_DBG1_dis_dq_MASK                    (0x1U)
11506 #define DDRC_DBG1_dis_dq_SHIFT                   (0U)
11507 /*! dis_dq - When 1, DDRC will not de-queue any transactions from the CAM. Bypass is also disabled.
11508  *    All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this
11509  *    is asserted. This bit may be used to prevent reads or writes being issued by the DDRC, which
11510  *    makes it safe to modify certain register fields associated with reads and writes (see User
11511  *    Guide for details). After setting this bit, it is strongly recommended to poll
11512  *    DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which
11513  *    affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit
11514  *    is intended to be switched on-the-fly.
11515  */
11516 #define DDRC_DBG1_dis_dq(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_dq_SHIFT)) & DDRC_DBG1_dis_dq_MASK)
11517 #define DDRC_DBG1_dis_hif_MASK                   (0x2U)
11518 #define DDRC_DBG1_dis_hif_SHIFT                  (1U)
11519 /*! dis_hif - When 1, DDRC asserts the HIF command signal hif_cmd_stall. DDRC will ignore the
11520  *    hif_cmd_valid and all other associated request signals. This bit is intended to be switched
11521  *    on-the-fly.
11522  */
11523 #define DDRC_DBG1_dis_hif(x)                     (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_hif_SHIFT)) & DDRC_DBG1_dis_hif_MASK)
11524 /*! @} */
11525 
11526 /*! @name DBGCAM - CAM Debug Register */
11527 /*! @{ */
11528 #define DDRC_DBGCAM_dbg_hpr_q_depth_MASK         (0x3FU)
11529 #define DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT        (0U)
11530 /*! dbg_hpr_q_depth - High priority read queue depth FOR DEBUG ONLY
11531  */
11532 #define DDRC_DBGCAM_dbg_hpr_q_depth(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_hpr_q_depth_MASK)
11533 #define DDRC_DBGCAM_dbg_lpr_q_depth_MASK         (0x3F00U)
11534 #define DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT        (8U)
11535 /*! dbg_lpr_q_depth - Low priority read queue depth The last entry of Lpr queue is reserved for ECC
11536  *    SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG
11537  *    ONLY
11538  */
11539 #define DDRC_DBGCAM_dbg_lpr_q_depth(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_lpr_q_depth_MASK)
11540 #define DDRC_DBGCAM_dbg_w_q_depth_MASK           (0x3F0000U)
11541 #define DDRC_DBGCAM_dbg_w_q_depth_SHIFT          (16U)
11542 /*! dbg_w_q_depth - Write queue depth The last entry of WR queue is reserved for ECC SCRUB
11543  *    operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY
11544  */
11545 #define DDRC_DBGCAM_dbg_w_q_depth(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_w_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_w_q_depth_MASK)
11546 #define DDRC_DBGCAM_dbg_stall_MASK               (0x1000000U)
11547 #define DDRC_DBGCAM_dbg_stall_SHIFT              (24U)
11548 /*! dbg_stall - Stall FOR DEBUG ONLY
11549  */
11550 #define DDRC_DBGCAM_dbg_stall(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_SHIFT)) & DDRC_DBGCAM_dbg_stall_MASK)
11551 #define DDRC_DBGCAM_dbg_rd_q_empty_MASK          (0x2000000U)
11552 #define DDRC_DBGCAM_dbg_rd_q_empty_SHIFT         (25U)
11553 /*! dbg_rd_q_empty - When 1, all the Read command queues and Read data buffers inside DDRC are
11554  *    empty. This register is to be used for debug purpose. An example use-case scenario: When Controller
11555  *    enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have
11556  *    executed all the commands in its queues and the write and read data drained. Hence this register
11557  *    should be 1 at that time. FOR DEBUG ONLY
11558  */
11559 #define DDRC_DBGCAM_dbg_rd_q_empty(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_rd_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_rd_q_empty_MASK)
11560 #define DDRC_DBGCAM_dbg_wr_q_empty_MASK          (0x4000000U)
11561 #define DDRC_DBGCAM_dbg_wr_q_empty_SHIFT         (26U)
11562 /*! dbg_wr_q_empty - When 1, all the Write command queues and Write data buffers inside DDRC are
11563  *    empty. This register is to be used for debug purpose. An example use-case scenario: When
11564  *    Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have
11565  *    executed all the commands in its queues and the write and read data drained. Hence this register
11566  *    should be 1 at that time. FOR DEBUG ONLY
11567  */
11568 #define DDRC_DBGCAM_dbg_wr_q_empty(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_wr_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_wr_q_empty_MASK)
11569 #define DDRC_DBGCAM_rd_data_pipeline_empty_MASK  (0x10000000U)
11570 #define DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT (28U)
11571 /*! rd_data_pipeline_empty - This bit indicates that the read data pipeline on the DFI interface is
11572  *    empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to
11573  *    ensure that all remaining commands/data have completed.
11574  */
11575 #define DDRC_DBGCAM_rd_data_pipeline_empty(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_rd_data_pipeline_empty_MASK)
11576 #define DDRC_DBGCAM_wr_data_pipeline_empty_MASK  (0x20000000U)
11577 #define DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT (29U)
11578 /*! wr_data_pipeline_empty - This bit indicates that the write data pipeline on the DFI interface is
11579  *    empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to
11580  *    ensure that all remaining commands/data have completed.
11581  */
11582 #define DDRC_DBGCAM_wr_data_pipeline_empty(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_wr_data_pipeline_empty_MASK)
11583 #define DDRC_DBGCAM_dbg_stall_wr_MASK            (0x40000000U)
11584 #define DDRC_DBGCAM_dbg_stall_wr_SHIFT           (30U)
11585 /*! dbg_stall_wr - Stall for Write channel FOR DEBUG ONLY
11586  */
11587 #define DDRC_DBGCAM_dbg_stall_wr(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_wr_SHIFT)) & DDRC_DBGCAM_dbg_stall_wr_MASK)
11588 #define DDRC_DBGCAM_dbg_stall_rd_MASK            (0x80000000U)
11589 #define DDRC_DBGCAM_dbg_stall_rd_SHIFT           (31U)
11590 /*! dbg_stall_rd - Stall for Read channel FOR DEBUG ONLY
11591  */
11592 #define DDRC_DBGCAM_dbg_stall_rd(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_rd_SHIFT)) & DDRC_DBGCAM_dbg_stall_rd_MASK)
11593 /*! @} */
11594 
11595 /*! @name DBGCMD - Command Debug Register */
11596 /*! @{ */
11597 #define DDRC_DBGCMD_rank0_refresh_MASK           (0x1U)
11598 #define DDRC_DBGCMD_rank0_refresh_SHIFT          (0U)
11599 /*! rank0_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank
11600  *    0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When
11601  *    DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent
11602  *    to rank index 0. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is
11603  *    recommended NOT to set this register bit if in Init or Deep power-down operating modes or
11604  *    Maximum Power Saving Mode.
11605  */
11606 #define DDRC_DBGCMD_rank0_refresh(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank0_refresh_SHIFT)) & DDRC_DBGCMD_rank0_refresh_MASK)
11607 #define DDRC_DBGCMD_rank1_refresh_MASK           (0x2U)
11608 #define DDRC_DBGCMD_rank1_refresh_SHIFT          (1U)
11609 /*! rank1_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank
11610  *    1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When
11611  *    DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent
11612  *    to rank index 1. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is
11613  *    recommended NOT to set this register bit if in Init or Deep power-down operating modes or
11614  *    Maximum Power Saving Mode.
11615  */
11616 #define DDRC_DBGCMD_rank1_refresh(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank1_refresh_SHIFT)) & DDRC_DBGCMD_rank1_refresh_MASK)
11617 #define DDRC_DBGCMD_zq_calib_short_MASK          (0x10U)
11618 #define DDRC_DBGCMD_zq_calib_short_SHIFT         (4U)
11619 /*! zq_calib_short - Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ
11620  *    calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the
11621  *    DDRC, the bit is automatically cleared. This operation can be performed only when
11622  *    ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register
11623  *    bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep
11624  *    power-down operating modes and Maximum Power Saving Mode.
11625  */
11626 #define DDRC_DBGCMD_zq_calib_short(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_zq_calib_short_SHIFT)) & DDRC_DBGCMD_zq_calib_short_MASK)
11627 #define DDRC_DBGCMD_ctrlupd_MASK                 (0x20U)
11628 #define DDRC_DBGCMD_ctrlupd_SHIFT                (5U)
11629 /*! ctrlupd - Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the
11630  *    PHY. When this request is stored in the DDRC, the bit is automatically cleared. This
11631  *    operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
11632  */
11633 #define DDRC_DBGCMD_ctrlupd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_ctrlupd_SHIFT)) & DDRC_DBGCMD_ctrlupd_MASK)
11634 /*! @} */
11635 
11636 /*! @name DBGSTAT - Status Debug Register */
11637 /*! @{ */
11638 #define DDRC_DBGSTAT_rank0_refresh_busy_MASK     (0x1U)
11639 #define DDRC_DBGSTAT_rank0_refresh_busy_SHIFT    (0U)
11640 /*! rank0_refresh_busy - SoC core may initiate a rank0_refresh operation (refresh operation to rank
11641  *    0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh
11642  *    is set to one. It goes low when the rank0_refresh operation is stored in the DDRC. It is
11643  *    recommended not to perform rank0_refresh operations when this signal is high. - 0 - Indicates that
11644  *    the SoC core can initiate a rank0_refresh operation - 1 - Indicates that rank0_refresh
11645  *    operation has not been stored yet in the DDRC
11646  */
11647 #define DDRC_DBGSTAT_rank0_refresh_busy(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank0_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank0_refresh_busy_MASK)
11648 #define DDRC_DBGSTAT_rank1_refresh_busy_MASK     (0x2U)
11649 #define DDRC_DBGSTAT_rank1_refresh_busy_SHIFT    (1U)
11650 /*! rank1_refresh_busy - SoC core may initiate a rank1_refresh operation (refresh operation to rank
11651  *    1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh
11652  *    is set to one. It goes low when the rank1_refresh operation is stored in the DDRC. It is
11653  *    recommended not to perform rank1_refresh operations when this signal is high. - 0 - Indicates that
11654  *    the SoC core can initiate a rank1_refresh operation - 1 - Indicates that rank1_refresh
11655  *    operation has not been stored yet in the DDRC
11656  */
11657 #define DDRC_DBGSTAT_rank1_refresh_busy(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank1_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank1_refresh_busy_MASK)
11658 #define DDRC_DBGSTAT_zq_calib_short_busy_MASK    (0x10U)
11659 #define DDRC_DBGSTAT_zq_calib_short_busy_SHIFT   (4U)
11660 /*! zq_calib_short_busy - SoC core may initiate a ZQCS (ZQ calibration short) operation only if this
11661  *    signal is low. This signal goes high in the clock after the DDRC accepts the ZQCS request. It
11662  *    goes low when the ZQCS operation is initiated in the DDRC. It is recommended not to perform
11663  *    ZQCS operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQCS
11664  *    operation - 1 - Indicates that ZQCS operation has not been initiated yet in the DDRC
11665  */
11666 #define DDRC_DBGSTAT_zq_calib_short_busy(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_zq_calib_short_busy_SHIFT)) & DDRC_DBGSTAT_zq_calib_short_busy_MASK)
11667 #define DDRC_DBGSTAT_ctrlupd_busy_MASK           (0x20U)
11668 #define DDRC_DBGSTAT_ctrlupd_busy_SHIFT          (5U)
11669 /*! ctrlupd_busy - SoC core may initiate a ctrlupd operation only if this signal is low. This signal
11670  *    goes high in the clock after the DDRC accepts the ctrlupd request. It goes low when the
11671  *    ctrlupd operation is initiated in the DDRC. It is recommended not to perform ctrlupd operations
11672  *    when this signal is high. - 0 - Indicates that the SoC core can initiate a ctrlupd operation - 1
11673  *    - Indicates that ctrlupd operation has not been initiated yet in the DDRC
11674  */
11675 #define DDRC_DBGSTAT_ctrlupd_busy(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_ctrlupd_busy_SHIFT)) & DDRC_DBGSTAT_ctrlupd_busy_MASK)
11676 /*! @} */
11677 
11678 /*! @name SWCTL - Software Register Programming Control Enable */
11679 /*! @{ */
11680 #define DDRC_SWCTL_sw_done_MASK                  (0x1U)
11681 #define DDRC_SWCTL_sw_done_SHIFT                 (0U)
11682 /*! sw_done - Enable quasi-dynamic register programming outside reset. Program register to 0 to
11683  *    enable quasi-dynamic programming. Set back register to 1 once programming is done.
11684  */
11685 #define DDRC_SWCTL_sw_done(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_SWCTL_sw_done_SHIFT)) & DDRC_SWCTL_sw_done_MASK)
11686 /*! @} */
11687 
11688 /*! @name SWSTAT - Software Register Programming Control Status */
11689 /*! @{ */
11690 #define DDRC_SWSTAT_sw_done_ack_MASK             (0x1U)
11691 #define DDRC_SWSTAT_sw_done_ack_SHIFT            (0U)
11692 /*! sw_done_ack - Register programming done. This register is the echo of SWCTL.sw_done. Wait for
11693  *    sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure
11694  *    that the correct registers values are propagated to the destination clock domains.
11695  */
11696 #define DDRC_SWSTAT_sw_done_ack(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_SWSTAT_sw_done_ack_SHIFT)) & DDRC_SWSTAT_sw_done_ack_MASK)
11697 /*! @} */
11698 
11699 /*! @name POISONCFG - AXI Poison Configuration Register. */
11700 /*! @{ */
11701 #define DDRC_POISONCFG_wr_poison_slverr_en_MASK  (0x1U)
11702 #define DDRC_POISONCFG_wr_poison_slverr_en_SHIFT (0U)
11703 /*! wr_poison_slverr_en - If set to 1, enables SLVERR response for write transaction poisoning
11704  */
11705 #define DDRC_POISONCFG_wr_poison_slverr_en(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_slverr_en_MASK)
11706 #define DDRC_POISONCFG_wr_poison_intr_en_MASK    (0x10U)
11707 #define DDRC_POISONCFG_wr_poison_intr_en_SHIFT   (4U)
11708 /*! wr_poison_intr_en - If set to 1, enables interrupts for write transaction poisoning
11709  */
11710 #define DDRC_POISONCFG_wr_poison_intr_en(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_en_MASK)
11711 #define DDRC_POISONCFG_wr_poison_intr_clr_MASK   (0x100U)
11712 #define DDRC_POISONCFG_wr_poison_intr_clr_SHIFT  (8U)
11713 /*! wr_poison_intr_clr - Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for
11714  *    correct value to propagate to core logic and clear the interrupts.
11715  */
11716 #define DDRC_POISONCFG_wr_poison_intr_clr(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_clr_MASK)
11717 #define DDRC_POISONCFG_rd_poison_slverr_en_MASK  (0x10000U)
11718 #define DDRC_POISONCFG_rd_poison_slverr_en_SHIFT (16U)
11719 /*! rd_poison_slverr_en - If set to 1, enables SLVERR response for read transaction poisoning
11720  */
11721 #define DDRC_POISONCFG_rd_poison_slverr_en(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_slverr_en_MASK)
11722 #define DDRC_POISONCFG_rd_poison_intr_en_MASK    (0x100000U)
11723 #define DDRC_POISONCFG_rd_poison_intr_en_SHIFT   (20U)
11724 /*! rd_poison_intr_en - If set to 1, enables interrupts for read transaction poisoning
11725  */
11726 #define DDRC_POISONCFG_rd_poison_intr_en(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_en_MASK)
11727 #define DDRC_POISONCFG_rd_poison_intr_clr_MASK   (0x1000000U)
11728 #define DDRC_POISONCFG_rd_poison_intr_clr_SHIFT  (24U)
11729 /*! rd_poison_intr_clr - Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for
11730  *    correct value to propagate to core logic and clear the interrupts.
11731  */
11732 #define DDRC_POISONCFG_rd_poison_intr_clr(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_clr_MASK)
11733 /*! @} */
11734 
11735 /*! @name POISONSTAT - AXI Poison Status Register */
11736 /*! @{ */
11737 #define DDRC_POISONSTAT_wr_poison_intr_0_MASK    (0x1U)
11738 #define DDRC_POISONSTAT_wr_poison_intr_0_SHIFT   (0U)
11739 /*! wr_poison_intr_0 - Write transaction poisoning error interrupt for port 0. This register is a
11740  *    APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is
11741  *    poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0, and
11742  *    so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB
11743  *    clock.
11744  */
11745 #define DDRC_POISONSTAT_wr_poison_intr_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_wr_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_wr_poison_intr_0_MASK)
11746 #define DDRC_POISONSTAT_rd_poison_intr_0_MASK    (0x10000U)
11747 #define DDRC_POISONSTAT_rd_poison_intr_0_SHIFT   (16U)
11748 /*! rd_poison_intr_0 - Read transaction poisoning error interrupt for port 0. This register is a APB
11749  *    clock copy (double register synchronizer) of the interrupt asserted when a transaction is
11750  *    poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0, and
11751  *    so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock.
11752  */
11753 #define DDRC_POISONSTAT_rd_poison_intr_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_rd_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_rd_poison_intr_0_MASK)
11754 /*! @} */
11755 
11756 /*! @name PSTAT - Port Status Register */
11757 /*! @{ */
11758 #define DDRC_PSTAT_rd_port_busy_0_MASK           (0x1U)
11759 #define DDRC_PSTAT_rd_port_busy_0_SHIFT          (0U)
11760 /*! rd_port_busy_0 - Indicates if there are outstanding reads for AXI port 0.
11761  */
11762 #define DDRC_PSTAT_rd_port_busy_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_rd_port_busy_0_SHIFT)) & DDRC_PSTAT_rd_port_busy_0_MASK)
11763 #define DDRC_PSTAT_wr_port_busy_0_MASK           (0x10000U)
11764 #define DDRC_PSTAT_wr_port_busy_0_SHIFT          (16U)
11765 /*! wr_port_busy_0 - Indicates if there are outstanding writes for AXI port 0.
11766  */
11767 #define DDRC_PSTAT_wr_port_busy_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_wr_port_busy_0_SHIFT)) & DDRC_PSTAT_wr_port_busy_0_MASK)
11768 /*! @} */
11769 
11770 /*! @name PCCFG - Port Common Configuration Register */
11771 /*! @{ */
11772 #define DDRC_PCCFG_go2critical_en_MASK           (0x1U)
11773 #define DDRC_PCCFG_go2critical_en_SHIFT          (0U)
11774 /*! go2critical_en - If set to 1 (enabled), sets co_gs_go2critical_wr and
11775  *    co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from
11776  *    AXI master. If set to 0 (disabled), co_gs_go2critical_wr and
11777  *    co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
11778  */
11779 #define DDRC_PCCFG_go2critical_en(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_go2critical_en_SHIFT)) & DDRC_PCCFG_go2critical_en_MASK)
11780 #define DDRC_PCCFG_pagematch_limit_MASK          (0x10U)
11781 #define DDRC_PCCFG_pagematch_limit_SHIFT         (4U)
11782 /*! pagematch_limit - Page match four limit. If set to 1, limits the number of consecutive same page
11783  *    DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is
11784  *    enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC
11785  *    transactions.
11786  */
11787 #define DDRC_PCCFG_pagematch_limit(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_pagematch_limit_SHIFT)) & DDRC_PCCFG_pagematch_limit_MASK)
11788 #define DDRC_PCCFG_bl_exp_mode_MASK              (0x100U)
11789 #define DDRC_PCCFG_bl_exp_mode_SHIFT             (8U)
11790 /*! bl_exp_mode - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every
11791  *    AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then
11792  *    XPI will use half of the memory burst length as a unit. This applies to both reads and
11793  *    writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in
11794  *    cases where Partial Writes is enabled (DDRC_PARTIAL_WR=1), in order to avoid or minimize t_ccd_l
11795  *    penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence, bl_exp_mode=1 is only recommended if
11796  *    DDR4 or LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the
11797  *    following cases: - DDRC_PARTIAL_WR=0 - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01,
11798  *    MEMC_BURST_LENGTH=8 and MSTR.burst_rdwr=1000 (LPDDR4 only) - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01,
11799  *    MEMC_BURST_LENGTH=4 and MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or
11800  *    CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Data Channel
11801  *    Interleave is enabled
11802  */
11803 #define DDRC_PCCFG_bl_exp_mode(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_bl_exp_mode_SHIFT)) & DDRC_PCCFG_bl_exp_mode_MASK)
11804 /*! @} */
11805 
11806 /*! @name PCFGR_0 - Port n Configuration Read Register */
11807 /*! @{ */
11808 #define DDRC_PCFGR_0_rd_port_priority_MASK       (0x3FFU)
11809 #define DDRC_PCFGR_0_rd_port_priority_SHIFT      (0U)
11810 /*! rd_port_priority - Determines the initial load value of read aging counters. These counters will
11811  *    be parallel loaded after reset, or after each grant to the corresponding port. The aging
11812  *    counters down-count every clock cycle where the port is requesting but not granted. The higher
11813  *    significant 5-bits of the read aging counter sets the priority of the read channel of a given
11814  *    port. Port's priority will increase as the higher significant 5-bits of the counter starts to
11815  *    decrease. When the aging counter becomes 0, the corresponding port channel will have the highest
11816  *    priority level (timeout condition - Priority0). For multi-port configurations, the aging
11817  *    counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are
11818  *    enabled (timeout is still applicable). For single port configurations, the aging counters are
11819  *    only used when they timeout (become 0) to force read-write direction switching. In this case,
11820  *    external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read
11821  *    priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by
11822  *    command basis. Note: The two LSBs of this register field are tied internally to 2'b00.
11823  */
11824 #define DDRC_PCFGR_0_rd_port_priority(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_priority_SHIFT)) & DDRC_PCFGR_0_rd_port_priority_MASK)
11825 #define DDRC_PCFGR_0_rd_port_aging_en_MASK       (0x1000U)
11826 #define DDRC_PCFGR_0_rd_port_aging_en_SHIFT      (12U)
11827 /*! rd_port_aging_en - If set to 1, enables aging function for the read channel of the port.
11828  */
11829 #define DDRC_PCFGR_0_rd_port_aging_en(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_aging_en_SHIFT)) & DDRC_PCFGR_0_rd_port_aging_en_MASK)
11830 #define DDRC_PCFGR_0_rd_port_urgent_en_MASK      (0x2000U)
11831 #define DDRC_PCFGR_0_rd_port_urgent_en_SHIFT     (13U)
11832 /*! rd_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled
11833  *    and arurgent is asserted by the master, that port becomes the highest priority and
11834  *    co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in
11835  *    PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is
11836  *    independent of address handshaking (it is not associated with any particular command).
11837  */
11838 #define DDRC_PCFGR_0_rd_port_urgent_en(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_urgent_en_SHIFT)) & DDRC_PCFGR_0_rd_port_urgent_en_MASK)
11839 #define DDRC_PCFGR_0_rd_port_pagematch_en_MASK   (0x4000U)
11840 #define DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT  (14U)
11841 /*! rd_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a
11842  *    requesting port is granted, the port is continued to be granted if the following immediate commands are
11843  *    to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit
11844  *    register.
11845  */
11846 #define DDRC_PCFGR_0_rd_port_pagematch_en(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT)) & DDRC_PCFGR_0_rd_port_pagematch_en_MASK)
11847 #define DDRC_PCFGR_0_rdwr_ordered_en_MASK        (0x10000U)
11848 #define DDRC_PCFGR_0_rdwr_ordered_en_SHIFT       (16U)
11849 /*! rdwr_ordered_en - Enable ordered read/writes. If set to 1, preserves the ordering between read
11850  *    transaction and write transaction issued to the same address, on a given port. In other words,
11851  *    the controller ensures that all same address read and write commands from the application port
11852  *    interface are transported to the DFI interface in the order of acceptance. This feature is
11853  *    useful in cases where software coherency is desired for masters issuing back-to-back read/write
11854  *    transactions without waiting for write/read responses. Note that this register has an effect
11855  *    only if necessary logic is instantiated via the DDRC_RDWR_ORDERED_n parameter.
11856  */
11857 #define DDRC_PCFGR_0_rdwr_ordered_en(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rdwr_ordered_en_SHIFT)) & DDRC_PCFGR_0_rdwr_ordered_en_MASK)
11858 /*! @} */
11859 
11860 /*! @name PCFGW_0 - Port n Configuration Write Register */
11861 /*! @{ */
11862 #define DDRC_PCFGW_0_wr_port_priority_MASK       (0x3FFU)
11863 #define DDRC_PCFGW_0_wr_port_priority_SHIFT      (0U)
11864 /*! wr_port_priority - Determines the initial load value of write aging counters. These counters
11865  *    will be parallel loaded after reset, or after each grant to the corresponding port. The aging
11866  *    counters down-count every clock cycle where the port is requesting but not granted. The higher
11867  *    significant 5-bits of the write aging counter sets the initial priority of the write channel of
11868  *    a given port. Port's priority will increase as the higher significant 5-bits of the counter
11869  *    starts to decrease. When the aging counter becomes 0, the corresponding port channel will have
11870  *    the highest priority level. For multi-port configurations, the aging counters cannot be used to
11871  *    set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is
11872  *    still applicable). For single port configurations, the aging counters are only used when they
11873  *    timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register
11874  *    field are tied internally to 2'b00.
11875  */
11876 #define DDRC_PCFGW_0_wr_port_priority(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_priority_SHIFT)) & DDRC_PCFGW_0_wr_port_priority_MASK)
11877 #define DDRC_PCFGW_0_wr_port_aging_en_MASK       (0x1000U)
11878 #define DDRC_PCFGW_0_wr_port_aging_en_SHIFT      (12U)
11879 /*! wr_port_aging_en - If set to 1, enables aging function for the write channel of the port.
11880  */
11881 #define DDRC_PCFGW_0_wr_port_aging_en(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_aging_en_SHIFT)) & DDRC_PCFGW_0_wr_port_aging_en_MASK)
11882 #define DDRC_PCFGW_0_wr_port_urgent_en_MASK      (0x2000U)
11883 #define DDRC_PCFGW_0_wr_port_urgent_en_SHIFT     (13U)
11884 /*! wr_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled
11885  *    and awurgent is asserted by the master, that port becomes the highest priority and
11886  *    co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that
11887  *    awurgent signal can be asserted anytime and as long as required which is independent of address
11888  *    handshaking (it is not associated with any particular command).
11889  */
11890 #define DDRC_PCFGW_0_wr_port_urgent_en(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_urgent_en_SHIFT)) & DDRC_PCFGW_0_wr_port_urgent_en_MASK)
11891 #define DDRC_PCFGW_0_wr_port_pagematch_en_MASK   (0x4000U)
11892 #define DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT  (14U)
11893 /*! wr_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a
11894  *    requesting port is granted, the port is continued to be granted if the following immediate commands are
11895  *    to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit
11896  *    register.
11897  */
11898 #define DDRC_PCFGW_0_wr_port_pagematch_en(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT)) & DDRC_PCFGW_0_wr_port_pagematch_en_MASK)
11899 /*! @} */
11900 
11901 /*! @name PCTRL_0 - Port n Control Register */
11902 /*! @{ */
11903 #define DDRC_PCTRL_0_port_en_MASK                (0x1U)
11904 #define DDRC_PCTRL_0_port_en_SHIFT               (0U)
11905 /*! port_en - Enables AXI port n.
11906  */
11907 #define DDRC_PCTRL_0_port_en(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_PCTRL_0_port_en_SHIFT)) & DDRC_PCTRL_0_port_en_MASK)
11908 /*! @} */
11909 
11910 /*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */
11911 /*! @{ */
11912 #define DDRC_PCFGQOS0_0_rqos_map_level1_MASK     (0xFU)
11913 #define DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT    (0U)
11914 /*! rqos_map_level1 - Separation level1 indicating the end of region0 mapping; start of region0 is
11915  *    0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which
11916  *    corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where
11917  *    the higher the value corresponds to higher port priority. All of the map_level* registers must
11918  *    be set to distinct values.
11919  */
11920 #define DDRC_PCFGQOS0_0_rqos_map_level1(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_level1_MASK)
11921 #define DDRC_PCFGQOS0_0_rqos_map_region0_MASK    (0x30000U)
11922 #define DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT   (16U)
11923 /*! rqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0:
11924  *    LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address
11925  *    queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support is disabled
11926  *    (DDRC_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
11927  *    traffic.
11928  */
11929 #define DDRC_PCFGQOS0_0_rqos_map_region0(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region0_MASK)
11930 #define DDRC_PCFGQOS0_0_rqos_map_region1_MASK    (0x300000U)
11931 #define DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT   (20U)
11932 /*! rqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0 :
11933  *    LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address
11934  *    queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled
11935  *    (DDRC_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
11936  *    traffic.
11937  */
11938 #define DDRC_PCFGQOS0_0_rqos_map_region1(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region1_MASK)
11939 /*! @} */
11940 
11941 /*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */
11942 /*! @{ */
11943 #define DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK   (0x7FFU)
11944 #define DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT  (0U)
11945 /*! rqos_map_timeoutb - Specifies the timeout value for transactions mapped to the blue address queue.
11946  */
11947 #define DDRC_PCFGQOS1_0_rqos_map_timeoutb(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK)
11948 #define DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK   (0x7FF0000U)
11949 #define DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT  (16U)
11950 /*! rqos_map_timeoutr - Specifies the timeout value for transactions mapped to the red address queue.
11951  */
11952 #define DDRC_PCFGQOS1_0_rqos_map_timeoutr(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK)
11953 /*! @} */
11954 
11955 /*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */
11956 /*! @{ */
11957 #define DDRC_PCFGWQOS0_0_wqos_map_level_MASK     (0xFU)
11958 #define DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT    (0U)
11959 /*! wqos_map_level - Separation level indicating the end of region0 mapping; start of region0 is 0.
11960  *    Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos
11961  *    values are used directly as port priorities, where the higher the value corresponds to higher
11962  *    port priority.
11963  */
11964 #define DDRC_PCFGWQOS0_0_wqos_map_level(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_level_MASK)
11965 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK   (0x30000U)
11966 #define DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT  (16U)
11967 /*! wqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0:
11968  *    NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region0 is set
11969  *    to 1 (VPW), VPW traffic is aliased to NPW traffic.
11970  */
11971 #define DDRC_PCFGWQOS0_0_wqos_map_region0(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
11972 #define DDRC_PCFGWQOS0_0_wqos_map_region1_MASK   (0x300000U)
11973 #define DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT  (20U)
11974 /*! wqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0:
11975  *    NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region 1 is
11976  *    set to 1 (VPW), VPW traffic is aliased to LPW traffic.
11977  */
11978 #define DDRC_PCFGWQOS0_0_wqos_map_region1(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region1_MASK)
11979 /*! @} */
11980 
11981 /*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */
11982 /*! @{ */
11983 #define DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK   (0x7FFU)
11984 #define DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT  (0U)
11985 /*! wqos_map_timeout - Specifies the timeout value for write transactions.
11986  */
11987 #define DDRC_PCFGWQOS1_0_wqos_map_timeout(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT)) & DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK)
11988 /*! @} */
11989 
11990 /*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */
11991 /*! @{ */
11992 #define DDRC_DERATEEN_SHADOW_derate_enable_MASK  (0x1U)
11993 #define DDRC_DERATEEN_SHADOW_derate_enable_SHIFT (0U)
11994 /*! derate_enable - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing
11995  *    parameter derating is enabled using MR4 read value. Present only in designs configured to support
11996  *    LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
11997  */
11998 #define DDRC_DERATEEN_SHADOW_derate_enable(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_enable_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_enable_MASK)
11999 #define DDRC_DERATEEN_SHADOW_derate_value_MASK   (0x2U)
12000 #define DDRC_DERATEEN_SHADOW_derate_value_SHIFT  (1U)
12001 /*! derate_value - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in
12002  *    designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as
12003  *    derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of
12004  *    core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it
12005  *    should be set to 0.
12006  */
12007 #define DDRC_DERATEEN_SHADOW_derate_value(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_value_MASK)
12008 #define DDRC_DERATEEN_SHADOW_derate_byte_MASK    (0xF0U)
12009 #define DDRC_DERATEEN_SHADOW_derate_byte_SHIFT   (4U)
12010 /*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
12011  *    Indicates which byte of the MRR data is used for derating. The maximum valid value depends on
12012  *    MEMC_DRAM_TOTAL_DATA_WIDTH.
12013  */
12014 #define DDRC_DERATEEN_SHADOW_derate_byte(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_byte_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_byte_MASK)
12015 #define DDRC_DERATEEN_SHADOW_rc_derate_value_MASK (0x300U)
12016 #define DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT (8U)
12017 /*! rc_derate_value - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2.
12018  *    - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support
12019  *    LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by
12020  *    the core_ddrc_core_clk period, and rounding up the next integer.
12021  */
12022 #define DDRC_DERATEEN_SHADOW_rc_derate_value(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_rc_derate_value_MASK)
12023 /*! @} */
12024 
12025 /*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */
12026 /*! @{ */
12027 #define DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK (0xFFFFFFFFU)
12028 #define DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT (0U)
12029 /*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters.
12030  *    Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to
12031  *    zero. Unit: DFI clock cycle.
12032  */
12033 #define DDRC_DERATEINT_SHADOW_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK)
12034 /*! @} */
12035 
12036 /*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */
12037 /*! @{ */
12038 #define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK (0x4U)
12039 #define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT (2U)
12040 /*! per_bank_refresh - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
12041  *    traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should
12042  *    be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support
12043  *    LPDDR2/LPDDR3/LPDDR4
12044  */
12045 #define DDRC_RFSHCTL0_SHADOW_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK)
12046 #define DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK  (0x1F0U)
12047 #define DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT (4U)
12048 /*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to
12049  *    accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to
12050  *    perform a refresh is a one-time penalty that must be paid for each group of refreshes.
12051  *    Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
12052  *    Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases
12053  *    the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2
12054  *    refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of
12055  *    DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not
12056  *    per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh
12057  *    feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
12058  *    mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care
12059  *    must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated
12060  *    due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
12061  *    situation, the refresh burst will be delayed until the PHY-initiated update is complete.
12062  */
12063 #define DDRC_RFSHCTL0_SHADOW_refresh_burst(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK)
12064 #define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK (0x1F000U)
12065 #define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT (12U)
12066 /*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once,
12067  *    but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be
12068  *    performed. A speculative refresh is a refresh performed at a time when refresh would be
12069  *    useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time
12070  *    determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since
12071  *    the last refresh, then a speculative refresh is performed. Speculative refreshes continues
12072  *    successively until there are no refreshes pending or until new reads or writes are issued to the
12073  *    DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
12074  */
12075 #define DDRC_RFSHCTL0_SHADOW_refresh_to_x32(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK)
12076 #define DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK (0xF00000U)
12077 #define DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT (20U)
12078 /*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or
12079  *    page timer expires. A critical refresh is to be issued before this threshold is reached. It is
12080  *    recommended that this not be changed from the default value, currently shown as 0x2. It must
12081  *    always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4,
12082  *    internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled
12083  *    (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to
12084  *    RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
12085  */
12086 #define DDRC_RFSHCTL0_SHADOW_refresh_margin(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK)
12087 /*! @} */
12088 
12089 /*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */
12090 /*! @{ */
12091 #define DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK       (0x3FFU)
12092 #define DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT      (0U)
12093 /*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is
12094  *    operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller
12095  *    is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In
12096  *    LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations
12097  *    is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is
12098  *    equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending
12099  *    on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the
12100  *    appropriate value from the spec based on the 'refresh_mode' and the device density that is used.
12101  *    Unit: Clocks.
12102  */
12103 #define DDRC_RFSHTMG_SHADOW_t_rfc_min(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK)
12104 #define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK (0x8000U)
12105 #define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT (15U)
12106 /*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when
12107  *    DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3
12108  *    devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW
12109  *    parameter not used - 1 - tREFBW parameter used
12110  */
12111 #define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK)
12112 #define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK   (0xFFF0000U)
12113 #define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT  (16U)
12114 /*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us
12115  *    for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For
12116  *    LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register
12117  *    should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
12118  *    register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode,
12119  *    program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending
12120  *    on the refresh mode. The user should program the appropriate value from the spec based on the
12121  *    value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be
12122  *    greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or
12123  *    DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed
12124  *    2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode:
12125  *    RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
12126  */
12127 #define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK)
12128 /*! @} */
12129 
12130 /*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */
12131 /*! @{ */
12132 #define DDRC_INIT3_SHADOW_emr_MASK               (0xFFFFU)
12133 #define DDRC_INIT3_SHADOW_emr_SHIFT              (0U)
12134 /*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
12135  *    register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1
12136  *    register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by
12137  *    the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 -
12138  *    Value to write to MR2 register
12139  */
12140 #define DDRC_INIT3_SHADOW_emr(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_emr_SHIFT)) & DDRC_INIT3_SHADOW_emr_MASK)
12141 #define DDRC_INIT3_SHADOW_mr_MASK                (0xFFFF0000U)
12142 #define DDRC_INIT3_SHADOW_mr_SHIFT               (16U)
12143 /*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The
12144  *    DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to
12145  *    write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
12146  */
12147 #define DDRC_INIT3_SHADOW_mr(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_mr_SHIFT)) & DDRC_INIT3_SHADOW_mr_MASK)
12148 /*! @} */
12149 
12150 /*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */
12151 /*! @{ */
12152 #define DDRC_INIT4_SHADOW_emr3_MASK              (0xFFFFU)
12153 #define DDRC_INIT4_SHADOW_emr3_SHIFT             (0U)
12154 /*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register
12155  *    mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
12156  */
12157 #define DDRC_INIT4_SHADOW_emr3(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr3_SHIFT)) & DDRC_INIT4_SHADOW_emr3_MASK)
12158 #define DDRC_INIT4_SHADOW_emr2_MASK              (0xFFFF0000U)
12159 #define DDRC_INIT4_SHADOW_emr2_SHIFT             (16U)
12160 /*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register
12161  *    LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
12162  */
12163 #define DDRC_INIT4_SHADOW_emr2(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr2_SHIFT)) & DDRC_INIT4_SHADOW_emr2_MASK)
12164 /*! @} */
12165 
12166 /*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */
12167 /*! @{ */
12168 #define DDRC_INIT6_SHADOW_mr5_MASK               (0xFFFFU)
12169 #define DDRC_INIT6_SHADOW_mr5_SHIFT              (0U)
12170 /*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
12171  */
12172 #define DDRC_INIT6_SHADOW_mr5(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr5_SHIFT)) & DDRC_INIT6_SHADOW_mr5_MASK)
12173 #define DDRC_INIT6_SHADOW_mr4_MASK               (0xFFFF0000U)
12174 #define DDRC_INIT6_SHADOW_mr4_SHIFT              (16U)
12175 /*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
12176  */
12177 #define DDRC_INIT6_SHADOW_mr4(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr4_SHIFT)) & DDRC_INIT6_SHADOW_mr4_MASK)
12178 /*! @} */
12179 
12180 /*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */
12181 /*! @{ */
12182 #define DDRC_INIT7_SHADOW_mr6_MASK               (0xFFFF0000U)
12183 #define DDRC_INIT7_SHADOW_mr6_SHIFT              (16U)
12184 /*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
12185  */
12186 #define DDRC_INIT7_SHADOW_mr6(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_SHADOW_mr6_SHIFT)) & DDRC_INIT7_SHADOW_mr6_MASK)
12187 /*! @} */
12188 
12189 /*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */
12190 /*! @{ */
12191 #define DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK      (0x3FU)
12192 #define DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT     (0U)
12193 /*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the
12194  *    controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding
12195  *    up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
12196  *    program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
12197  */
12198 #define DDRC_DRAMTMG0_SHADOW_t_ras_min(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK)
12199 #define DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK      (0x7F00U)
12200 #define DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT     (8U)
12201 /*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the
12202  *    maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid.
12203  *    When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
12204  *    No rounding up. Unit: Multiples of 1024 clocks.
12205  */
12206 #define DDRC_DRAMTMG0_SHADOW_t_ras_max(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK)
12207 #define DDRC_DRAMTMG0_SHADOW_t_faw_MASK          (0x3F0000U)
12208 #define DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT         (16U)
12209 /*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank
12210  *    design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller
12211  *    is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next
12212  *    integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency
12213  *    mode. Unit: Clocks
12214  */
12215 #define DDRC_DRAMTMG0_SHADOW_t_faw(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_faw_MASK)
12216 #define DDRC_DRAMTMG0_SHADOW_wr2pre_MASK         (0x7F000000U)
12217 #define DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT        (24U)
12218 /*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL
12219  *    + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower
12220  *    frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in
12221  *    the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
12222  *    - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra
12223  *    cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2
12224  *    frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller
12225  *    is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2
12226  *    and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it
12227  *    may be necessary to adjust the value of this parameter to compensate for the extra cycle of
12228  *    latency through the LRDIMM.
12229  */
12230 #define DDRC_DRAMTMG0_SHADOW_wr2pre(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT)) & DDRC_DRAMTMG0_SHADOW_wr2pre_MASK)
12231 /*! @} */
12232 
12233 /*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */
12234 /*! @{ */
12235 #define DDRC_DRAMTMG1_SHADOW_t_rc_MASK           (0x7FU)
12236 #define DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT          (0U)
12237 /*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2
12238  *    frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit:
12239  *    Clocks.
12240  */
12241 #define DDRC_DRAMTMG1_SHADOW_t_rc(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_rc_MASK)
12242 #define DDRC_DRAMTMG1_SHADOW_rd2pre_MASK         (0x3F00U)
12243 #define DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT        (8U)
12244 /*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP,
12245  *    2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4)
12246  *    or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
12247  *    LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4
12248  *    - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously,
12249  *    use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode,
12250  *    divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T
12251  *    mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
12252  *    Unit: Clocks.
12253  */
12254 #define DDRC_DRAMTMG1_SHADOW_rd2pre(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT)) & DDRC_DRAMTMG1_SHADOW_rd2pre_MASK)
12255 #define DDRC_DRAMTMG1_SHADOW_t_xp_MASK           (0x1F0000U)
12256 #define DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT          (16U)
12257 /*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be
12258  *    programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used,
12259  *    set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program
12260  *    this to (tXP/2) and round it up to the next integer value. Units: Clocks
12261  */
12262 #define DDRC_DRAMTMG1_SHADOW_t_xp(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_xp_MASK)
12263 /*! @} */
12264 
12265 /*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */
12266 /*! @{ */
12267 #define DDRC_DRAMTMG2_SHADOW_wr2rd_MASK          (0x3FU)
12268 #define DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT         (0U)
12269 /*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from
12270  *    write command to read command for same bank group. In others, minimum time from write command to
12271  *    read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
12272  *    global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL
12273  *    = burst length. This must match the value programmed in the BL bit of the mode register to
12274  *    the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes
12275  *    directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes
12276  *    directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
12277  *    When the controller is operating in 1:2 mode, divide the value calculated using the above
12278  *    equation by 2, and round it up to next integer.
12279  */
12280 #define DDRC_DRAMTMG2_SHADOW_wr2rd(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT)) & DDRC_DRAMTMG2_SHADOW_wr2rd_MASK)
12281 #define DDRC_DRAMTMG2_SHADOW_rd2wr_MASK          (0x3F00U)
12282 #define DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT         (8U)
12283 /*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL
12284  *    + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK)
12285  *    + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) +
12286  *    RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command.
12287  *    Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see
12288  *    the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: -
12289  *    WL = write latency - BL = burst length. This must match the value programmed in the BL bit of
12290  *    the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write
12291  *    preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to
12292  *    LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
12293  *    tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the
12294  *    value calculated using the above equation by 2, and round it up to next integer. Note that,
12295  *    depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter
12296  *    to compensate for the extra cycle of latency through the LRDIMM.
12297  */
12298 #define DDRC_DRAMTMG2_SHADOW_rd2wr(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT)) & DDRC_DRAMTMG2_SHADOW_rd2wr_MASK)
12299 #define DDRC_DRAMTMG2_SHADOW_read_latency_MASK   (0x3F0000U)
12300 #define DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT  (16U)
12301 /*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be
12302  *    set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust
12303  *    the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When
12304  *    the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the
12305  *    above equation by 2, and round it up to next integer. This register field is not required for
12306  *    DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in
12307  *    DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
12308  */
12309 #define DDRC_DRAMTMG2_SHADOW_read_latency(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_read_latency_MASK)
12310 #define DDRC_DRAMTMG2_SHADOW_write_latency_MASK  (0x3F000000U)
12311 #define DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT (24U)
12312 /*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be
12313  *    set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if
12314  *    using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra
12315  *    cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio
12316  *    mode, divide the value calculated using the above equation by 2, and round it up to next
12317  *    integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set),
12318  *    as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
12319  *    protocols Unit: clocks
12320  */
12321 #define DDRC_DRAMTMG2_SHADOW_write_latency(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_write_latency_MASK)
12322 /*! @} */
12323 
12324 /*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */
12325 /*! @{ */
12326 #define DDRC_DRAMTMG3_SHADOW_t_mod_MASK          (0x3FFU)
12327 #define DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT         (0U)
12328 /*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and
12329  *    following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
12330  *    Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
12331  *    next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
12332  *    RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to
12333  *    compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
12334  *    Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller
12335  *    is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if
12336  *    controller is operating in 1:2 frequency ratio mode.
12337  */
12338 #define DDRC_DRAMTMG3_SHADOW_t_mod(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mod_MASK)
12339 #define DDRC_DRAMTMG3_SHADOW_t_mrd_MASK          (0x3F000U)
12340 #define DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT         (12U)
12341 /*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected
12342  *    SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS
12343  *    command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is
12344  *    operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer
12345  *    value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
12346  */
12347 #define DDRC_DRAMTMG3_SHADOW_t_mrd(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrd_MASK)
12348 #define DDRC_DRAMTMG3_SHADOW_t_mrw_MASK          (0x3FF00000U)
12349 #define DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT         (20U)
12350 /*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs
12351  *    configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3
12352  *    typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2,
12353  *    this register is used for the time from a MRW/MRR to all other commands. When the controller
12354  *    is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and
12355  *    round it up to the next integer value. For LDPDR3, this register is used for the time from a
12356  *    MRW/MRR to a MRW/MRR.
12357  */
12358 #define DDRC_DRAMTMG3_SHADOW_t_mrw(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrw_MASK)
12359 /*! @} */
12360 
12361 /*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */
12362 /*! @{ */
12363 #define DDRC_DRAMTMG4_SHADOW_t_rp_MASK           (0x1FU)
12364 #define DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT          (0U)
12365 /*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is
12366  *    operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is
12367  *    operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) +
12368  *    1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
12369  *    to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
12370  */
12371 #define DDRC_DRAMTMG4_SHADOW_t_rp(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rp_MASK)
12372 #define DDRC_DRAMTMG4_SHADOW_t_rrd_MASK          (0xF00U)
12373 #define DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT         (8U)
12374 /*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank
12375  *    group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller
12376  *    is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it
12377  *    up to the next integer value. Unit: Clocks.
12378  */
12379 #define DDRC_DRAMTMG4_SHADOW_t_rrd(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rrd_MASK)
12380 #define DDRC_DRAMTMG4_SHADOW_t_ccd_MASK          (0xF0000U)
12381 #define DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT         (16U)
12382 /*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank
12383  *    group. Others: tCCD: This is the minimum time between two reads or two writes. When the
12384  *    controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it
12385  *    up to the next integer value. Unit: clocks.
12386  */
12387 #define DDRC_DRAMTMG4_SHADOW_t_ccd(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_ccd_MASK)
12388 #define DDRC_DRAMTMG4_SHADOW_t_rcd_MASK          (0x1F000000U)
12389 #define DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT         (24U)
12390 /*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the
12391  *    controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round
12392  *    it up to the next integer value. Minimum value allowed for this register is 1, which implies
12393  *    minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio
12394  *    mode. Unit: Clocks.
12395  */
12396 #define DDRC_DRAMTMG4_SHADOW_t_rcd(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rcd_MASK)
12397 /*! @} */
12398 
12399 /*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */
12400 /*! @{ */
12401 #define DDRC_DRAMTMG5_SHADOW_t_cke_MASK          (0x1FU)
12402 #define DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT         (0U)
12403 /*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -
12404  *    LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of
12405  *    tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When
12406  *    the controller is operating in 1:2 frequency ratio mode, program this to (value described
12407  *    above)/2 and round it up to the next integer value. Unit: Clocks.
12408  */
12409 #define DDRC_DRAMTMG5_SHADOW_t_cke(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cke_MASK)
12410 #define DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK        (0x3F00U)
12411 #define DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT       (8U)
12412 /*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing
12413  *    in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR
12414  *    - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity
12415  *    latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased
12416  *    by PL. When the controller is operating in 1:2 frequency ratio mode, program this to
12417  *    recommended value divided by two and round it up to next integer.
12418  */
12419 #define DDRC_DRAMTMG5_SHADOW_t_ckesr(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK)
12420 #define DDRC_DRAMTMG5_SHADOW_t_cksre_MASK        (0xF0000U)
12421 #define DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT       (16U)
12422 /*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.
12423  *    Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
12424  *    LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+
12425  *    PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should
12426  *    be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program
12427  *    this to recommended value divided by two and round it up to next integer.
12428  */
12429 #define DDRC_DRAMTMG5_SHADOW_t_cksre(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksre_MASK)
12430 #define DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK        (0xF000000U)
12431 #define DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT       (24U)
12432 /*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock
12433  *    before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 -
12434  *    LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the
12435  *    controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by
12436  *    two and round it up to next integer.
12437  */
12438 #define DDRC_DRAMTMG5_SHADOW_t_cksrx(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK)
12439 /*! @} */
12440 
12441 /*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */
12442 /*! @{ */
12443 #define DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK        (0xFU)
12444 #define DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT       (0U)
12445 /*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before
12446  *    issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop
12447  *    Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2
12448  *    When the controller is operating in 1:2 frequency ratio mode, program this to recommended value
12449  *    divided by two and round it up to next integer. This is only present for designs supporting
12450  *    mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
12451  */
12452 #define DDRC_DRAMTMG6_SHADOW_t_ckcsx(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK)
12453 #define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK       (0xF0000U)
12454 #define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT      (16U)
12455 /*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock
12456  *    before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR:
12457  *    1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode,
12458  *    program this to recommended value divided by two and round it up to next integer. This is only
12459  *    present for designs supporting mDDR or LPDDR2 devices.
12460  */
12461 #define DDRC_DRAMTMG6_SHADOW_t_ckdpdx(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK)
12462 #define DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK       (0xF000000U)
12463 #define DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT      (24U)
12464 /*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock.
12465  *    Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
12466  *    LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to
12467  *    recommended value divided by two and round it up to next integer. This is only present for designs
12468  *    supporting mDDR or LPDDR2/LPDDR3 devices.
12469  */
12470 #define DDRC_DRAMTMG6_SHADOW_t_ckdpde(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK)
12471 /*! @} */
12472 
12473 /*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */
12474 /*! @{ */
12475 #define DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK        (0xFU)
12476 #define DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT       (0U)
12477 /*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before
12478  *    issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 -
12479  *    LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the
12480  *    same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode,
12481  *    program this to recommended value divided by two and round it up to next integer. This is only
12482  *    present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
12483  */
12484 #define DDRC_DRAMTMG7_SHADOW_t_ckpdx(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK)
12485 #define DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK        (0xF00U)
12486 #define DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT       (8U)
12487 /*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock.
12488  *    Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2
12489  *    - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as
12490  *    DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this
12491  *    to recommended value divided by two and round it up to next integer. This is only present for
12492  *    designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
12493  */
12494 #define DDRC_DRAMTMG7_SHADOW_t_ckpde(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK)
12495 /*! @} */
12496 
12497 /*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */
12498 /*! @{ */
12499 #define DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK       (0x7FU)
12500 #define DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT      (0U)
12501 /*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is
12502  *    operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round
12503  *    up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
12504  *    DDR4 SDRAMs.
12505  */
12506 #define DDRC_DRAMTMG8_SHADOW_t_xs_x32(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK)
12507 #define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK   (0x7F00U)
12508 #define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT  (8U)
12509 /*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller
12510  *    is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and
12511  *    round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
12512  *    DDR4 SDRAMs.
12513  */
12514 #define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK)
12515 #define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK (0x7F0000U)
12516 #define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT (16U)
12517 /*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self
12518  *    Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the
12519  *    above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
12520  *    Note: Ensure this is less than or equal to t_xs_x32.
12521  */
12522 #define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK)
12523 #define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK  (0x7F000000U)
12524 #define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT (24U)
12525 /*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown
12526  *    mode). When the controller is operating in 1:2 frequency ratio mode, program this to the
12527  *    above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
12528  *    This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to
12529  *    t_xs_x32.
12530  */
12531 #define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK)
12532 /*! @} */
12533 
12534 /*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */
12535 /*! @{ */
12536 #define DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK        (0x3FU)
12537 #define DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT       (0U)
12538 /*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different
12539  *    bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
12540  *    global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where:
12541  *    - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value
12542  *    programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read
12543  *    command delay for different bank group. This comes directly from the SDRAM specification. When
12544  *    the controller is operating in 1:2 mode, divide the value calculated using the above equation
12545  *    by 2, and round it up to next integer.
12546  */
12547 #define DDRC_DRAMTMG9_SHADOW_wr2rd_s(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK)
12548 #define DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK        (0xF00U)
12549 #define DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT       (8U)
12550 /*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank
12551  *    group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2)
12552  *    and round it up to the next integer value. Present only in designs configured to support DDR4.
12553  *    Unit: Clocks.
12554  */
12555 #define DDRC_DRAMTMG9_SHADOW_t_rrd_s(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK)
12556 #define DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK        (0x70000U)
12557 #define DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT       (16U)
12558 /*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank
12559  *    group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When
12560  *    the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round
12561  *    it up to the next integer value. Present only in designs configured to support DDR4. Unit:
12562  *    clocks.
12563  */
12564 #define DDRC_DRAMTMG9_SHADOW_t_ccd_s(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK)
12565 #define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK (0x40000000U)
12566 #define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT (30U)
12567 /*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
12568  */
12569 #define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK)
12570 /*! @} */
12571 
12572 /*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */
12573 /*! @{ */
12574 #define DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK   (0x3U)
12575 #define DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT  (0U)
12576 /*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For
12577  *    DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
12578  *    1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer
12579  *    value. Unit: Clocks
12580  */
12581 #define DDRC_DRAMTMG10_SHADOW_t_gear_hold(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK)
12582 #define DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK  (0xCU)
12583 #define DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT (2U)
12584 /*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For
12585  *    DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
12586  *    1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer
12587  *    value. Unit: Clocks
12588  */
12589 #define DDRC_DRAMTMG10_SHADOW_t_gear_setup(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK)
12590 #define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK    (0x1F00U)
12591 #define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT   (8U)
12592 /*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is
12593  *    defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for
12594  *    this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2)
12595  *    and round it up to the next integer value. Unit: Clocks
12596  */
12597 #define DDRC_DRAMTMG10_SHADOW_t_cmd_gear(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK)
12598 #define DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK   (0x1F0000U)
12599 #define DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT  (16U)
12600 /*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even
12601  *    number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK
12602  *    tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28
12603  *    When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up
12604  *    to the next integer value. Unit: Clocks
12605  */
12606 #define DDRC_DRAMTMG10_SHADOW_t_sync_gear(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK)
12607 /*! @} */
12608 
12609 /*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */
12610 /*! @{ */
12611 #define DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK       (0x1FU)
12612 #define DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT      (0U)
12613 /*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs
12614  *    configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio
12615  *    mode, divide the value calculated using the above equation by 2, and round it up to next
12616  *    integer.
12617  */
12618 #define DDRC_DRAMTMG11_SHADOW_t_ckmpe(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK)
12619 #define DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK       (0x300U)
12620 #define DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT      (8U)
12621 /*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2
12622  *    frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value.
12623  *    Present only in designs configured to support DDR4. Unit: Clocks.
12624  */
12625 #define DDRC_DRAMTMG11_SHADOW_t_mpx_s(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK)
12626 #define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK      (0x1F0000U)
12627 #define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT     (16U)
12628 /*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the
12629  *    controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present
12630  *    only in designs configured to support DDR4. Unit: clocks.
12631  */
12632 #define DDRC_DRAMTMG11_SHADOW_t_mpx_lh(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK)
12633 #define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK (0x7F000000U)
12634 #define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT (24U)
12635 /*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.
12636  *    When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and
12637  *    round it up to the next integer value. Present only in designs configured to support DDR4.
12638  *    Unit: Multiples of 32 clocks.
12639  */
12640 #define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK)
12641 /*! @} */
12642 
12643 /*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */
12644 /*! @{ */
12645 #define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK     (0x1FU)
12646 #define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT    (0U)
12647 /*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the
12648  *    controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up
12649  *    to the next integer value.
12650  */
12651 #define DDRC_DRAMTMG12_SHADOW_t_mrd_pda(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK)
12652 #define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK     (0xF00U)
12653 #define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT    (8U)
12654 /*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is
12655  *    operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next
12656  *    integer value.
12657  */
12658 #define DDRC_DRAMTMG12_SHADOW_t_ckehcmd(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK)
12659 #define DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK      (0x30000U)
12660 #define DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT     (16U)
12661 /*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE
12662  *    or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to
12663  *    (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
12664  */
12665 #define DDRC_DRAMTMG12_SHADOW_t_cmdcke(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK)
12666 /*! @} */
12667 
12668 /*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */
12669 /*! @{ */
12670 #define DDRC_DRAMTMG13_SHADOW_t_ppd_MASK         (0x7U)
12671 #define DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT        (0U)
12672 /*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the
12673  *    controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to
12674  *    the next integer value. Unit: Clocks.
12675  */
12676 #define DDRC_DRAMTMG13_SHADOW_t_ppd(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ppd_MASK)
12677 #define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK      (0x3F0000U)
12678 #define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT     (16U)
12679 /*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write
12680  *    command for same bank. When the controller is operating in 1:2 frequency ratio mode, program
12681  *    this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
12682  */
12683 #define DDRC_DRAMTMG13_SHADOW_t_ccd_mw(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK)
12684 #define DDRC_DRAMTMG13_SHADOW_odtloff_MASK       (0x7F000000U)
12685 #define DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT      (24U)
12686 /*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When
12687  *    the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round
12688  *    it up to the next integer value. Unit: Clocks.
12689  */
12690 #define DDRC_DRAMTMG13_SHADOW_odtloff(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT)) & DDRC_DRAMTMG13_SHADOW_odtloff_MASK)
12691 /*! @} */
12692 
12693 /*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */
12694 /*! @{ */
12695 #define DDRC_DRAMTMG14_SHADOW_t_xsr_MASK         (0xFFFU)
12696 #define DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT        (0U)
12697 /*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2
12698  *    frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
12699  *    Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
12700  */
12701 #define DDRC_DRAMTMG14_SHADOW_t_xsr(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT)) & DDRC_DRAMTMG14_SHADOW_t_xsr_MASK)
12702 /*! @} */
12703 
12704 /*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */
12705 /*! @{ */
12706 #define DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK    (0xFFU)
12707 #define DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT   (0U)
12708 /*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4
12709  *    RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the
12710  *    clock must be stable for a time specified by tSTAB - in the case of input clock frequency
12711  *    change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for
12712  *    DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to
12713  *    recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock
12714  *    cycles.
12715  */
12716 #define DDRC_DRAMTMG15_SHADOW_t_stab_x32(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK)
12717 #define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK (0x80000000U)
12718 #define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT (31U)
12719 /*! en_dfi_lp_t_stab - - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is
12720  *    stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when
12721  *    exiting DFI LP
12722  */
12723 #define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK)
12724 /*! @} */
12725 
12726 /*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */
12727 /*! @{ */
12728 #define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK   (0x3FFU)
12729 #define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT  (0U)
12730 /*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles
12731  *    of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
12732  *    When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
12733  *    round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
12734  *    LPDDR2/LPDDR3/LPDDR4 devices.
12735  */
12736 #define DDRC_ZQCTL0_SHADOW_t_zq_short_nop(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK)
12737 #define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK    (0x7FF0000U)
12738 #define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT   (16U)
12739 /*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI
12740  *    clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is
12741  *    issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program
12742  *    this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to
12743  *    tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it
12744  *    up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
12745  *    LPDDR2/LPDDR3/LPDDR4 devices.
12746  */
12747 #define DDRC_ZQCTL0_SHADOW_t_zq_long_nop(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK)
12748 #define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK   (0x10000000U)
12749 #define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT  (28U)
12750 /*! dis_mpsmx_zqcl - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only
12751  *    applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving
12752  *    Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting
12753  *    DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the
12754  *    DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after
12755  *    exiting MPSM mode.
12756  */
12757 #define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK)
12758 #define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK (0x20000000U)
12759 #define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT (29U)
12760 /*! zq_resistor_shared - - 1 - Denotes that ZQ resistor is shared between ranks. Means
12761  *    ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
12762  *    tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 -
12763  *    ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or
12764  *    LPDDR2/LPDDR3/LPDDR4 devices.
12765  */
12766 #define DDRC_ZQCTL0_SHADOW_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK)
12767 #define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK     (0x40000000U)
12768 #define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT    (30U)
12769 /*! dis_srx_zqcl - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at
12770  *    Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 -
12771  *    Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only
12772  *    applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for
12773  *    designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
12774  */
12775 #define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK)
12776 #define DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK      (0x80000000U)
12777 #define DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT     (31U)
12778 /*! dis_auto_zq - - 1 - Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register
12779  *    DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 -
12780  *    Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
12781  *    This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
12782  */
12783 #define DDRC_ZQCTL0_SHADOW_dis_auto_zq(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK)
12784 /*! @} */
12785 
12786 /*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */
12787 /*! @{ */
12788 #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK  (0x3FU)
12789 #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT (0U)
12790 /*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable
12791  *    (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY
12792  *    specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be
12793  *    necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for
12794  *    the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY
12795  *    clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
12796  */
12797 #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK)
12798 #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK (0x3F00U)
12799 #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT (8U)
12800 /*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to
12801  *    when the associated write data is driven on the dfi_wrdata signal. This corresponds to the
12802  *    DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max
12803  *    supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on
12804  *    DFITMG0.dfi_wrdata_use_sdr.
12805  */
12806 #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK)
12807 #define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK (0x8000U)
12808 #define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT (15U)
12809 /*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using
12810  *    HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat
12811  *    is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in
12812  *    DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of
12813  *    HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification
12814  *    for correct value.
12815  */
12816 #define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK)
12817 #define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK (0x7F0000U)
12818 #define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT (16U)
12819 /*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the
12820  *    assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds
12821  *    to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it
12822  *    may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to
12823  *    compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or
12824  *    DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
12825  */
12826 #define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK)
12827 #define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK (0x800000U)
12828 #define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT (23U)
12829 /*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated
12830  *    using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in
12831  *    DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI
12832  *    clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct
12833  *    value.
12834  */
12835 #define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK)
12836 #define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK (0x1F000000U)
12837 #define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT (24U)
12838 /*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion
12839  *    of the DFI control signals that the control signals at the PHY-DRAM interface reflect the
12840  *    assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing
12841  *    parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it
12842  *    is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms
12843  *    of DFI clock.
12844  */
12845 #define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK)
12846 /*! @} */
12847 
12848 /*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */
12849 /*! @{ */
12850 #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK (0x1FU)
12851 #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT (0U)
12852 /*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the
12853  *    dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the
12854  *    DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not
12855  *    phase aligned, this timing parameter should be rounded up to the next integer value.
12856  */
12857 #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK)
12858 #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK (0x1F00U)
12859 #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT (8U)
12860 /*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the
12861  *    dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM
12862  *    boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned,
12863  *    this timing parameter should be rounded up to the next integer value.
12864  */
12865 #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK)
12866 #define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK (0x1F0000U)
12867 #define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT (16U)
12868 /*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en
12869  *    signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.
12870  *    This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
12871  *    correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI
12872  *    3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be
12873  *    programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2
12874  *    and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit:
12875  *    Clocks
12876  */
12877 #define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK)
12878 #define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK (0x3000000U)
12879 #define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT (24U)
12880 /*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
12881  *    asserted and when the associated dfi_parity_in signal is driven.
12882  */
12883 #define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK)
12884 #define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK   (0xF0000000U)
12885 #define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT  (28U)
12886 /*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
12887  *    asserted and when the associated command is driven. This field is used for CAL mode, should be
12888  *    set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY
12889  *    can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
12890  */
12891 #define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK)
12892 /*! @} */
12893 
12894 /*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */
12895 /*! @{ */
12896 #define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK (0x3FU)
12897 #define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT (0U)
12898 /*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the
12899  *    DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds
12900  *    to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
12901  */
12902 #define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK)
12903 #define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK (0x7F00U)
12904 #define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT (8U)
12905 /*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI
12906  *    control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds
12907  *    to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
12908  */
12909 #define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK)
12910 /*! @} */
12911 
12912 /*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */
12913 /*! @{ */
12914 #define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK (0x1FU)
12915 #define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT (0U)
12916 /*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being
12917  *    ready to receive commands. Refer to PHY specification for correct value. When the controller is
12918  *    operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to
12919  *    the next integer value. Unit: Clocks
12920  */
12921 #define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK)
12922 /*! @} */
12923 
12924 /*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */
12925 /*! @{ */
12926 #define DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK     (0x7CU)
12927 #define DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT    (2U)
12928 /*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT
12929  *    values associated with that command. ODT setting must remain constant for the entire time that
12930  *    DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5
12931  *    (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL -
12932  *    CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL
12933  *    mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write
12934  *    preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does
12935  *    not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
12936  */
12937 #define DDRC_ODTCFG_SHADOW_rd_odt_delay(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK)
12938 #define DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK      (0xF00U)
12939 #define DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT     (8U)
12940 /*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value
12941  *    is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not
12942  *    DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK
12943  *    write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) -
12944  *    RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
12945  */
12946 #define DDRC_ODTCFG_SHADOW_rd_odt_hold(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK)
12947 #define DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK     (0x1F0000U)
12948 #define DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT    (16U)
12949 /*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT
12950  *    values associated with that command. ODT setting must remain constant for the entire time that
12951  *    DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL +
12952  *    AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT
12953  *    for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3:
12954  *    - WL - 1 - RU(tODTon(max)/tCK))
12955  */
12956 #define DDRC_ODTCFG_SHADOW_wr_odt_delay(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK)
12957 #define DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK      (0xF000000U)
12958 #define DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT     (24U)
12959 /*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value
12960  *    is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
12961  *    - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8:
12962  *    5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
12963  *    CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
12964  */
12965 #define DDRC_ODTCFG_SHADOW_wr_odt_hold(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK)
12966 /*! @} */
12967 
12968 
12969 /*!
12970  * @}
12971  */ /* end of group DDRC_Register_Masks */
12972 
12973 
12974 /* DDRC - Peripheral instance base addresses */
12975 /** Peripheral DRC__DDRC base address */
12976 #define DRC__DDRC_BASE                           (0x5C000000u)
12977 /** Peripheral DRC__DDRC base pointer */
12978 #define DRC__DDRC                                ((DDRC_Type *)DRC__DDRC_BASE)
12979 /** Array initializer of DDRC peripheral base addresses */
12980 #define DDRC_BASE_ADDRS                          { DRC__DDRC_BASE }
12981 /** Array initializer of DDRC peripheral base pointers */
12982 #define DDRC_BASE_PTRS                           { DRC__DDRC }
12983 
12984 /*!
12985  * @}
12986  */ /* end of group DDRC_Peripheral_Access_Layer */
12987 
12988 
12989 /* ----------------------------------------------------------------------------
12990    -- DDRPHY Peripheral Access Layer
12991    ---------------------------------------------------------------------------- */
12992 
12993 /*!
12994  * @addtogroup DDRPHY_Peripheral_Access_Layer DDRPHY Peripheral Access Layer
12995  * @{
12996  */
12997 
12998 /** DDRPHY - Register Layout Typedef */
12999 typedef struct {
13000   __I  uint32_t RIDR;                              /**< Revision Identification Register, offset: 0x0 */
13001   __IO uint32_t PIR;                               /**< PHY Initialization Register, offset: 0x4 */
13002        uint8_t RESERVED_0[8];
13003   __IO uint32_t PGCR0;                             /**< PHY General Configuration Register 0, offset: 0x10 */
13004   __IO uint32_t PGCR1;                             /**< PHY General Configuration Register 1, offset: 0x14 */
13005   __IO uint32_t PGCR2;                             /**< PHY General Configuration Register 2, offset: 0x18 */
13006   __IO uint32_t PGCR3;                             /**< PHY General Configuration Register 3, offset: 0x1C */
13007   __IO uint32_t PGCR4;                             /**< PHY General Configuration Register 4, offset: 0x20 */
13008   __IO uint32_t PGCR5;                             /**< PHY General Configuration Register 5, offset: 0x24 */
13009   __IO uint32_t PGCR6;                             /**< PHY General Configuration Register 6, offset: 0x28 */
13010   __IO uint32_t PGCR7;                             /**< PHY General Configuration Register 7, offset: 0x2C */
13011   __I  uint32_t PGSR0;                             /**< PHY General Status Register 0, offset: 0x30 */
13012   __I  uint32_t PGSR1;                             /**< PHY General Status Register 1, offset: 0x34 */
13013   __I  uint32_t PGSR2;                             /**< PHY General Status Register 2, offset: 0x38 */
13014        uint8_t RESERVED_1[4];
13015   __IO uint32_t PTR0;                              /**< PHY Timing Register 0, offset: 0x40 */
13016   __IO uint32_t PTR1;                              /**< PHY Timing Register 1, offset: 0x44 */
13017   __IO uint32_t PTR2;                              /**< PHY Timing Register 2, offset: 0x48 */
13018   __IO uint32_t PTR3;                              /**< PHY Timing Register 3, offset: 0x4C */
13019   __IO uint32_t PTR4;                              /**< PHY Timing Register 4, offset: 0x50 */
13020   __IO uint32_t PTR5;                              /**< PHY Timing Register 5, offset: 0x54 */
13021   __IO uint32_t PTR6;                              /**< PHY Timing Register 6, offset: 0x58 */
13022        uint8_t RESERVED_2[12];
13023   __IO uint32_t PLLCR0;                            /**< PLL Control Register 0 (Type B PLL Only), offset: 0x68 */
13024   __IO uint32_t PLLCR1;                            /**< PLL Control Register 1 (Type B PLL Only), offset: 0x6C */
13025   __IO uint32_t PLLCR2;                            /**< PLL Control Register 2 (Type B PLL Only), offset: 0x70 */
13026   __IO uint32_t PLLCR3;                            /**< PLL Control Register 3 (Type B PLL Only), offset: 0x74 */
13027   __IO uint32_t PLLCR4;                            /**< PLL Control Register 4 (Type B PLL Only), offset: 0x78 */
13028   __IO uint32_t PLLCR5;                            /**< PLL Control Register 5 (Type B PLL Only), offset: 0x7C */
13029        uint8_t RESERVED_3[8];
13030   __IO uint32_t DXCCR;                             /**< DATX8 Common Configuration Register, offset: 0x88 */
13031        uint8_t RESERVED_4[4];
13032   __IO uint32_t DSGCR;                             /**< DDR System General Configuration Register, offset: 0x90 */
13033        uint8_t RESERVED_5[4];
13034   __IO uint32_t ODTCR;                             /**< ODT Configuration Register, offset: 0x98 */
13035        uint8_t RESERVED_6[4];
13036   __IO uint32_t AACR;                              /**< Anti-Aging Control Register, offset: 0xA0 */
13037        uint8_t RESERVED_7[28];
13038   __IO uint32_t GPR0;                              /**< General Purpose Register 0, offset: 0xC0 */
13039   __IO uint32_t GPR1;                              /**< General Purpose Register 1, offset: 0xC4 */
13040        uint8_t RESERVED_8[56];
13041   __IO uint32_t DCR;                               /**< DRAM Configuration Register, offset: 0x100 */
13042        uint8_t RESERVED_9[12];
13043   __IO uint32_t DTPR0;                             /**< DRAM Timing Parameters Register 0, offset: 0x110 */
13044   __IO uint32_t DTPR1;                             /**< DRAM Timing Parameters Register 1, offset: 0x114 */
13045   __IO uint32_t DTPR2;                             /**< DRAM Timing Parameters Register 2, offset: 0x118 */
13046   __IO uint32_t DTPR3;                             /**< DRAM Timing Parameters Register 3, offset: 0x11C */
13047   __IO uint32_t DTPR4;                             /**< DRAM Timing Parameters Register 4, offset: 0x120 */
13048   __IO uint32_t DTPR5;                             /**< DRAM Timing Parameters Register 5, offset: 0x124 */
13049   __IO uint32_t DTPR6;                             /**< DRAM Timing Parameters Register 6, offset: 0x128 */
13050        uint8_t RESERVED_10[20];
13051   __IO uint32_t RDIMMGCR0;                         /**< RDIMM General Configuration Register 0, offset: 0x140 */
13052   __IO uint32_t RDIMMGCR1;                         /**< RDIMM General Configuration Register 1, offset: 0x144 */
13053   __IO uint32_t RDIMMGCR2;                         /**< RDIMM General Configuration Register 2, offset: 0x148 */
13054        uint8_t RESERVED_11[4];
13055   __IO uint32_t RDIMMCR0;                          /**< RDIMM Control Register 0, offset: 0x150 */
13056   __IO uint32_t RDIMMCR1;                          /**< RDIMM Control Register 1, offset: 0x154 */
13057   __IO uint32_t RDIMMCR2;                          /**< RDIMM Control Register 2, offset: 0x158 */
13058   __IO uint32_t RDIMMCR3;                          /**< RDIMM Control Register 3, offset: 0x15C */
13059   __IO uint32_t RDIMMCR4;                          /**< RDIMM Control Register 4, offset: 0x160 */
13060        uint8_t RESERVED_12[4];
13061   __IO uint32_t SCHCR0;                            /**< Scheduler Command Register 0, offset: 0x168 */
13062   __IO uint32_t SCHCR1;                            /**< Scheduler Command Register 1, offset: 0x16C */
13063        uint8_t RESERVED_13[16];
13064   __IO uint32_t MR0;                               /**< LPDDR4 Mode Register 0, offset: 0x180 */
13065   __IO uint32_t MR1;                               /**< LPDDR4 Mode Register 1, offset: 0x184 */
13066   __IO uint32_t MR2;                               /**< LPDDR4 Mode Register 2, offset: 0x188 */
13067   __IO uint32_t MR3;                               /**< LPDDR4 Mode Register 3, offset: 0x18C */
13068   __IO uint32_t MR4;                               /**< LPDDR4 Mode Register 4, offset: 0x190 */
13069   __IO uint32_t MR5;                               /**< LPDDR4 Mode Register 5, offset: 0x194 */
13070   __IO uint32_t MR6;                               /**< LPDDR4 Mode Register 6, offset: 0x198 */
13071   __IO uint32_t MR7;                               /**< LPDDR4 Mode Register 7, offset: 0x19C */
13072        uint8_t RESERVED_14[12];
13073   __IO uint32_t MR11;                              /**< LPDDR4 Mode Register 11, offset: 0x1AC */
13074   __IO uint32_t MR12;                              /**< LPDDR4 Mode Register 12, offset: 0x1B0 */
13075   __IO uint32_t MR13;                              /**< LPDDR4 Mode Register 13, offset: 0x1B4 */
13076   __IO uint32_t MR14;                              /**< LPDDR4 Mode Register 14, offset: 0x1B8 */
13077        uint8_t RESERVED_15[28];
13078   __IO uint32_t MR22;                              /**< LPDDR4 Mode Register 22, offset: 0x1D8 */
13079        uint8_t RESERVED_16[36];
13080   __IO uint32_t DTCR0;                             /**< Data Training Configuration Register 0, offset: 0x200 */
13081   __IO uint32_t DTCR1;                             /**< Data Training Configuration Register 1, offset: 0x204 */
13082   __IO uint32_t DTAR0;                             /**< Data Training Address Register 0, offset: 0x208 */
13083   __IO uint32_t DTAR1;                             /**< Data Training Address Register 1, offset: 0x20C */
13084   __IO uint32_t DTAR2;                             /**< Data Training Address Register 2, offset: 0x210 */
13085        uint8_t RESERVED_17[4];
13086   __IO uint32_t DTDR0;                             /**< Data Training Data Register 0, offset: 0x218 */
13087   __IO uint32_t DTDR1;                             /**< Data Training Data Register 1, offset: 0x21C */
13088        uint8_t RESERVED_18[16];
13089   __I  uint32_t DTEDR0;                            /**< Data Training Eye Data Register 0, offset: 0x230 */
13090   __I  uint32_t DTEDR1;                            /**< Data Training Eye Data Register 1, offset: 0x234 */
13091   __I  uint32_t DTEDR2;                            /**< Data Training Eye Data Register 2, offset: 0x238 */
13092   __I  uint32_t VTDR;                              /**< VREF Training Data Register, offset: 0x23C */
13093   __IO uint32_t CATR0;                             /**< CA Training Register 0, offset: 0x240 */
13094   __IO uint32_t CATR1;                             /**< CA Training Register 1, offset: 0x244 */
13095   __IO uint32_t PGCR8;                             /**< PHY General Configuration Register 8, offset: 0x248 */
13096        uint8_t RESERVED_19[4];
13097   __IO uint32_t DQSDR0;                            /**< DQS Drift Register 0, offset: 0x250 */
13098   __IO uint32_t DQSDR1;                            /**< DQS Drift Register 1, offset: 0x254 */
13099   __IO uint32_t DQSDR2;                            /**< DQS Drift Register 2, offset: 0x258 */
13100        uint8_t RESERVED_20[164];
13101   __IO uint32_t DCUAR;                             /**< DCU Address Register, offset: 0x300 */
13102   __IO uint32_t DCUDR;                             /**< DCU Data Register, offset: 0x304 */
13103   __IO uint32_t DCURR;                             /**< DCU Run Register, offset: 0x308 */
13104   __IO uint32_t DCULR;                             /**< DCU Loop Register, offset: 0x30C */
13105   __IO uint32_t DCUGCR;                            /**< DCU General Configuration Register, offset: 0x310 */
13106   __IO uint32_t DCUTPR;                            /**< DCU Timing Parameters Register, offset: 0x314 */
13107   __I  uint32_t DCUSR0;                            /**< DCU Status Register 0, offset: 0x318 */
13108   __I  uint32_t DCUSR1;                            /**< DCU Status Register 1, offset: 0x31C */
13109        uint8_t RESERVED_21[224];
13110   __IO uint32_t BISTRR;                            /**< BIST Run Register, offset: 0x400 */
13111   __IO uint32_t BISTWCR;                           /**< BIST Word Count Register, offset: 0x404 */
13112   __IO uint32_t BISTMSKR0;                         /**< BIST Mask Register 0, offset: 0x408 */
13113   __IO uint32_t BISTMSKR1;                         /**< BIST Mask Register 1, offset: 0x40C */
13114   __IO uint32_t BISTMSKR2;                         /**< BIST Mask Register 2, offset: 0x410 */
13115   __IO uint32_t BISTLSR;                           /**< BIST LFSR Seed Register, offset: 0x414 */
13116   __IO uint32_t BISTAR0;                           /**< BIST Address Register 0, offset: 0x418 */
13117   __IO uint32_t BISTAR1;                           /**< BIST Address Register 1, offset: 0x41C */
13118   __IO uint32_t BISTAR2;                           /**< BIST Address Register 2, offset: 0x420 */
13119   __IO uint32_t BISTAR3;                           /**< BIST Address Register 3, offset: 0x424 */
13120   __IO uint32_t BISTAR4;                           /**< BIST Address Register 4, offset: 0x428 */
13121   __IO uint32_t BISTUDPR;                          /**< BIST User Data Pattern Register, offset: 0x42C */
13122   __I  uint32_t BISTGSR;                           /**< BIST General Status Register, offset: 0x430 */
13123   __I  uint32_t BISTWER0;                          /**< BIST Word Error Register 0, offset: 0x434 */
13124   __I  uint32_t BISTWER1;                          /**< BIST Word Error Register 1, offset: 0x438 */
13125   __I  uint32_t BISTBER0;                          /**< BIST Bit Error Register 0, offset: 0x43C */
13126   __I  uint32_t BISTBER1;                          /**< BIST Bit Error Register 1, offset: 0x440 */
13127   __I  uint32_t BISTBER2;                          /**< BIST Bit Error Register 2, offset: 0x444 */
13128   __I  uint32_t BISTBER3;                          /**< BIST Bit Error Register 3, offset: 0x448 */
13129   __I  uint32_t BISTBER4;                          /**< BIST Bit Error Register 4, offset: 0x44C */
13130   __I  uint32_t BISTWCSR;                          /**< BIST Word Count Status Register, offset: 0x450 */
13131   __I  uint32_t BISTFWR0;                          /**< BIST Fail Word Register 0, offset: 0x454 */
13132   __I  uint32_t BISTFWR1;                          /**< BIST Fail Word Register 1, offset: 0x458 */
13133   __I  uint32_t BISTFWR2;                          /**< BIST Fail Word Register 2, offset: 0x45C */
13134   __I  uint32_t BISTBER5;                          /**< BIST Bit Error Register 5, offset: 0x460 */
13135        uint8_t RESERVED_22[120];
13136   __IO uint32_t RANKIDR;                           /**< Rank ID Register, offset: 0x4DC */
13137   __I  uint32_t RIOCR0;                            /**< Rank I/O Configuration Register 0, offset: 0x4E0 */
13138   __I  uint32_t RIOCR1;                            /**< Rank I/O Configuration Register 1, offset: 0x4E4 */
13139   __IO uint32_t RIOCR2;                            /**< Rank I/O Configuration Register 2, offset: 0x4E8 */
13140   __I  uint32_t RIOCR3;                            /**< Rank I/O Configuration Register 3, offset: 0x4EC */
13141   __IO uint32_t RIOCR4;                            /**< Rank I/O Configuration Register 4, offset: 0x4F0 */
13142   __IO uint32_t RIOCR5;                            /**< Rank I/O Configuration Register 5, offset: 0x4F4 */
13143        uint8_t RESERVED_23[8];
13144   __IO uint32_t ACIOCR0;                           /**< AC I/O Configuration Register 0, offset: 0x500 */
13145   __IO uint32_t ACIOCR1;                           /**< AC I/O Configuration Register 1, offset: 0x504 */
13146   __IO uint32_t ACIOCR2;                           /**< AC I/O Configuration Register 2, offset: 0x508 */
13147   __IO uint32_t ACIOCR3;                           /**< AC I/O Configuration Register 3, offset: 0x50C */
13148   __IO uint32_t ACIOCR4;                           /**< AC I/O Configuration Register 4, offset: 0x510 */
13149   __IO uint32_t ACIOCR5;                           /**< AC I/O Configuration Register 5, offset: 0x514 */
13150        uint8_t RESERVED_24[8];
13151   __IO uint32_t IOVCR0;                            /**< IO VREF Control Register 0, offset: 0x520 */
13152   __I  uint32_t IOVCR1;                            /**< IO VREF Control Register 1, offset: 0x524 */
13153   __IO uint32_t VTCR0;                             /**< VREF Training Control Register 0, offset: 0x528 */
13154   __IO uint32_t VTCR1;                             /**< VREF Training Control Register 1, offset: 0x52C */
13155        uint8_t RESERVED_25[16];
13156   __IO uint32_t ACBDLR0;                           /**< AC Bit Delay Line Register 0, offset: 0x540 */
13157   __IO uint32_t ACBDLR1;                           /**< AC Bit Delay Line Register 1, offset: 0x544 */
13158   __IO uint32_t ACBDLR2;                           /**< AC Bit Delay Line Register 2, offset: 0x548 */
13159   __IO uint32_t ACBDLR3;                           /**< AC Bit Delay Line Register 3, offset: 0x54C */
13160   __IO uint32_t ACBDLR4;                           /**< AC Bit Delay Line Register 4, offset: 0x550 */
13161   __IO uint32_t ACBDLR5;                           /**< AC Bit Delay Line Register 5, offset: 0x554 */
13162   __IO uint32_t ACBDLR6;                           /**< AC Bit Delay Line Register 6, offset: 0x558 */
13163   __IO uint32_t ACBDLR7;                           /**< AC Bit Delay Line Register 7, offset: 0x55C */
13164   __IO uint32_t ACBDLR8;                           /**< AC Bit Delay Line Register 8, offset: 0x560 */
13165   __IO uint32_t ACBDLR9;                           /**< AC Bit Delay Line Register 9, offset: 0x564 */
13166   __IO uint32_t ACBDLR10;                          /**< AC Bit Delay Line Register 10, offset: 0x568 */
13167   __I  uint32_t ACBDLR11;                          /**< AC Bit Delay Line Register 11, offset: 0x56C */
13168   __I  uint32_t ACBDLR12;                          /**< AC Bit Delay Line Register 12, offset: 0x570 */
13169   __I  uint32_t ACBDLR13;                          /**< AC Bit Delay Line Register 13, offset: 0x574 */
13170   __I  uint32_t ACBDLR14;                          /**< AC Bit Delay Line Register 14, offset: 0x578 */
13171   __IO uint32_t ACBDLR15;                          /**< AC Bit Delay Line Register 15, offset: 0x57C */
13172   __IO uint32_t ACBDLR16;                          /**< AC Bit Delay Line Register 16, offset: 0x580 */
13173   __IO uint32_t ACLCDLR;                           /**< AC Local Calibrated Delay Line Register, offset: 0x584 */
13174        uint8_t RESERVED_26[24];
13175   __IO uint32_t ACMDLR0;                           /**< AC Master Delay Line Register 0, offset: 0x5A0 */
13176   __IO uint32_t ACMDLR1;                           /**< AC Master Delay Line Register 1, offset: 0x5A4 */
13177        uint8_t RESERVED_27[216];
13178   __IO uint32_t ZQCR;                              /**< ZQ Impedance Control Register, offset: 0x680 */
13179   __IO uint32_t ZQ0PR0;                            /**< ZQ n Impedance Control Program Register 0, offset: 0x684 */
13180   __IO uint32_t ZQ0PR1;                            /**< ZQ n Impedance Control Program Register 1, offset: 0x688 */
13181   __I  uint32_t ZQ0DR0;                            /**< ZQ n Impedance Control Data Register 0, offset: 0x68C */
13182   __I  uint32_t ZQ0DR1;                            /**< ZQ n Impedance Control Data Register 1, offset: 0x690 */
13183   __IO uint32_t ZQ0OR0;                            /**< ZQ n Impedance Control Override Data Register 0, offset: 0x694 */
13184   __IO uint32_t ZQ0OR1;                            /**< ZQ n Impedance Control Override Data Register 1, offset: 0x698 */
13185   __I  uint32_t ZQ0SR;                             /**< ZQ n Impedance Control Status Register, offset: 0x69C */
13186        uint8_t RESERVED_28[4];
13187   __IO uint32_t ZQ1PR0;                            /**< ZQ n Impedance Control Program Register 0, offset: 0x6A4 */
13188   __IO uint32_t ZQ1PR1;                            /**< ZQ n Impedance Control Program Register 1, offset: 0x6A8 */
13189   __I  uint32_t ZQ1DR0;                            /**< ZQ n Impedance Control Data Register 0, offset: 0x6AC */
13190   __I  uint32_t ZQ1DR1;                            /**< ZQ n Impedance Control Data Register 1, offset: 0x6B0 */
13191   __IO uint32_t ZQ1OR0;                            /**< ZQ n Impedance Control Override Data Register 0, offset: 0x6B4 */
13192   __IO uint32_t ZQ1OR1;                            /**< ZQ n Impedance Control Override Data Register 1, offset: 0x6B8 */
13193   __I  uint32_t ZQ1SR;                             /**< ZQ n Impedance Control Status Register, offset: 0x6BC */
13194        uint8_t RESERVED_29[4];
13195   __IO uint32_t ZQ2PR0;                            /**< ZQ n Impedance Control Program Register 0, offset: 0x6C4 */
13196   __IO uint32_t ZQ2PR1;                            /**< ZQ n Impedance Control Program Register 1, offset: 0x6C8 */
13197   __I  uint32_t ZQ2DR0;                            /**< ZQ n Impedance Control Data Register 0, offset: 0x6CC */
13198   __I  uint32_t ZQ2DR1;                            /**< ZQ n Impedance Control Data Register 1, offset: 0x6D0 */
13199   __IO uint32_t ZQ2OR0;                            /**< ZQ n Impedance Control Override Data Register 0, offset: 0x6D4 */
13200   __IO uint32_t ZQ2OR1;                            /**< ZQ n Impedance Control Override Data Register 1, offset: 0x6D8 */
13201   __I  uint32_t ZQ2SR;                             /**< ZQ n Impedance Control Status Register, offset: 0x6DC */
13202        uint8_t RESERVED_30[4];
13203   __I  uint32_t ZQ3PR0;                            /**< ZQ n Impedance Control Program Register 0, offset: 0x6E4 */
13204   __I  uint32_t ZQ3PR1;                            /**< ZQ n Impedance Control Program Register 1, offset: 0x6E8 */
13205   __I  uint32_t ZQ3DR0;                            /**< ZQ n Impedance Control Data Register 0, offset: 0x6EC */
13206   __I  uint32_t ZQ3DR1;                            /**< ZQ n Impedance Control Data Register 1, offset: 0x6F0 */
13207   __I  uint32_t ZQ3OR0;                            /**< ZQ n Impedance Control Override Data Register 0, offset: 0x6F4 */
13208   __I  uint32_t ZQ3OR1;                            /**< ZQ n Impedance Control Override Data Register 1, offset: 0x6F8 */
13209   __I  uint32_t ZQ3SR;                             /**< ZQ n Impedance Control Status Register, offset: 0x6FC */
13210   __IO uint32_t DX0GCR0;                           /**< DATX8 n General Configuration Register 0, offset: 0x700 */
13211   __IO uint32_t DX0GCR1;                           /**< DATX8 n General Configuration Register 1, offset: 0x704 */
13212   __IO uint32_t DX0GCR2;                           /**< DATX8 n General Configuration Register 2, offset: 0x708 */
13213   __IO uint32_t DX0GCR3;                           /**< DATX8 n General Configuration Register 3, offset: 0x70C */
13214   __IO uint32_t DX0GCR4;                           /**< DATX8 n General Configuration Register 4, offset: 0x710 */
13215   __IO uint32_t DX0GCR5;                           /**< DATX8 n General Configuration Register 5, offset: 0x714 */
13216   __IO uint32_t DX0GCR6;                           /**< DATX8 n General Configuration Register 6, offset: 0x718 */
13217   __IO uint32_t DX0GCR7;                           /**< DATX8 n General Configuration Register 7, offset: 0x71C */
13218   __I  uint32_t DX0GCR8;                           /**< DATX8 n General Configuration Register 8, offset: 0x720 */
13219   __I  uint32_t DX0GCR9;                           /**< DATX8 n General Configuration Register 9, offset: 0x724 */
13220   __IO uint32_t DX0DQMAP0;                         /**< DATX8 n DQ/DM Mapping Register 0, offset: 0x728 */
13221   __IO uint32_t DX0DQMAP1;                         /**< DATX8 n DQ/DM Mapping Register 1, offset: 0x72C */
13222        uint8_t RESERVED_31[16];
13223   __IO uint32_t DX0BDLR0;                          /**< DATX8 n Bit Delay Line Register 0, offset: 0x740 */
13224   __IO uint32_t DX0BDLR1;                          /**< DATX8 n Bit Delay Line Register 1, offset: 0x744 */
13225   __IO uint32_t DX0BDLR2;                          /**< DATX8 n Bit Delay Line Register 2, offset: 0x748 */
13226        uint8_t RESERVED_32[4];
13227   __IO uint32_t DX0BDLR3;                          /**< DATX8 n Bit Delay Line Register 3, offset: 0x750 */
13228   __IO uint32_t DX0BDLR4;                          /**< DATX8 n Bit Delay Line Register 4, offset: 0x754 */
13229   __IO uint32_t DX0BDLR5;                          /**< DATX8 n Bit Delay Line Register 5, offset: 0x758 */
13230        uint8_t RESERVED_33[4];
13231   __IO uint32_t DX0BDLR6;                          /**< DATX8 n Bit Delay Line Register 6, offset: 0x760 */
13232   __I  uint32_t DX0BDLR7;                          /**< DATX8 n Bit Delay Line Register 7, offset: 0x764 */
13233   __I  uint32_t DX0BDLR8;                          /**< DATX8 n Bit Delay Line Register 8, offset: 0x768 */
13234   __I  uint32_t DX0BDLR9;                          /**< DATX8 n Bit Delay Line Register 9, offset: 0x76C */
13235        uint8_t RESERVED_34[16];
13236   __IO uint32_t DX0LCDLR0;                         /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0x780 */
13237   __IO uint32_t DX0LCDLR1;                         /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0x784 */
13238   __IO uint32_t DX0LCDLR2;                         /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0x788 */
13239   __IO uint32_t DX0LCDLR3;                         /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0x78C */
13240   __IO uint32_t DX0LCDLR4;                         /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0x790 */
13241   __IO uint32_t DX0LCDLR5;                         /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0x794 */
13242        uint8_t RESERVED_35[8];
13243   __IO uint32_t DX0MDLR0;                          /**< DATX8 n Master Delay Line Register 0, offset: 0x7A0 */
13244   __IO uint32_t DX0MDLR1;                          /**< DATX8 n Master Delay Line Register 1, offset: 0x7A4 */
13245        uint8_t RESERVED_36[24];
13246   __IO uint32_t DX0GTR0;                           /**< DATX8 n General Timing Register 0, offset: 0x7C0 */
13247        uint8_t RESERVED_37[12];
13248   __I  uint32_t DX0RSR0;                           /**< DATX8 n Rank Status Register 0, offset: 0x7D0 */
13249   __I  uint32_t DX0RSR1;                           /**< DATX8 n Rank Status Register 1, offset: 0x7D4 */
13250   __I  uint32_t DX0RSR2;                           /**< DATX8 n Rank Status Register 2, offset: 0x7D8 */
13251   __I  uint32_t DX0RSR3;                           /**< DATX8 n Rank Status Register 3, offset: 0x7DC */
13252   __I  uint32_t DX0GSR0;                           /**< DATX8 n General Status Register 0, offset: 0x7E0 */
13253   __I  uint32_t DX0GSR1;                           /**< DATX8 n General Status Register 1, offset: 0x7E4 */
13254   __I  uint32_t DX0GSR2;                           /**< DATX8 n General Status Register 2, offset: 0x7E8 */
13255   __I  uint32_t DX0GSR3;                           /**< DATX8 n General Status Register 3, offset: 0x7EC */
13256   __I  uint32_t DX0GSR4;                           /**< DATX8 n General Status Register 4, offset: 0x7F0 */
13257   __I  uint32_t DX0GSR5;                           /**< DATX8 n General Status Register 5, offset: 0x7F4 */
13258   __I  uint32_t DX0GSR6;                           /**< DATX8 n General Status Register 6, offset: 0x7F8 */
13259        uint8_t RESERVED_38[4];
13260   __IO uint32_t DX1GCR0;                           /**< DATX8 n General Configuration Register 0, offset: 0x800 */
13261   __IO uint32_t DX1GCR1;                           /**< DATX8 n General Configuration Register 1, offset: 0x804 */
13262   __IO uint32_t DX1GCR2;                           /**< DATX8 n General Configuration Register 2, offset: 0x808 */
13263   __IO uint32_t DX1GCR3;                           /**< DATX8 n General Configuration Register 3, offset: 0x80C */
13264   __IO uint32_t DX1GCR4;                           /**< DATX8 n General Configuration Register 4, offset: 0x810 */
13265   __IO uint32_t DX1GCR5;                           /**< DATX8 n General Configuration Register 5, offset: 0x814 */
13266   __IO uint32_t DX1GCR6;                           /**< DATX8 n General Configuration Register 6, offset: 0x818 */
13267   __IO uint32_t DX1GCR7;                           /**< DATX8 n General Configuration Register 7, offset: 0x81C */
13268   __I  uint32_t DX1GCR8;                           /**< DATX8 n General Configuration Register 8, offset: 0x820 */
13269   __I  uint32_t DX1GCR9;                           /**< DATX8 n General Configuration Register 9, offset: 0x824 */
13270   __IO uint32_t DX1DQMAP0;                         /**< DATX8 n DQ/DM Mapping Register 0, offset: 0x828 */
13271   __IO uint32_t DX1DQMAP1;                         /**< DATX8 n DQ/DM Mapping Register 1, offset: 0x82C */
13272        uint8_t RESERVED_39[16];
13273   __IO uint32_t DX1BDLR0;                          /**< DATX8 n Bit Delay Line Register 0, offset: 0x840 */
13274   __IO uint32_t DX1BDLR1;                          /**< DATX8 n Bit Delay Line Register 1, offset: 0x844 */
13275   __IO uint32_t DX1BDLR2;                          /**< DATX8 n Bit Delay Line Register 2, offset: 0x848 */
13276        uint8_t RESERVED_40[4];
13277   __IO uint32_t DX1BDLR3;                          /**< DATX8 n Bit Delay Line Register 3, offset: 0x850 */
13278   __IO uint32_t DX1BDLR4;                          /**< DATX8 n Bit Delay Line Register 4, offset: 0x854 */
13279   __IO uint32_t DX1BDLR5;                          /**< DATX8 n Bit Delay Line Register 5, offset: 0x858 */
13280        uint8_t RESERVED_41[4];
13281   __IO uint32_t DX1BDLR6;                          /**< DATX8 n Bit Delay Line Register 6, offset: 0x860 */
13282   __I  uint32_t DX1BDLR7;                          /**< DATX8 n Bit Delay Line Register 7, offset: 0x864 */
13283   __I  uint32_t DX1BDLR8;                          /**< DATX8 n Bit Delay Line Register 8, offset: 0x868 */
13284   __I  uint32_t DX1BDLR9;                          /**< DATX8 n Bit Delay Line Register 9, offset: 0x86C */
13285        uint8_t RESERVED_42[16];
13286   __IO uint32_t DX1LCDLR0;                         /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0x880 */
13287   __IO uint32_t DX1LCDLR1;                         /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0x884 */
13288   __IO uint32_t DX1LCDLR2;                         /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0x888 */
13289   __IO uint32_t DX1LCDLR3;                         /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0x88C */
13290   __IO uint32_t DX1LCDLR4;                         /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0x890 */
13291   __IO uint32_t DX1LCDLR5;                         /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0x894 */
13292        uint8_t RESERVED_43[8];
13293   __IO uint32_t DX1MDLR0;                          /**< DATX8 n Master Delay Line Register 0, offset: 0x8A0 */
13294   __IO uint32_t DX1MDLR1;                          /**< DATX8 n Master Delay Line Register 1, offset: 0x8A4 */
13295        uint8_t RESERVED_44[24];
13296   __IO uint32_t DX1GTR0;                           /**< DATX8 n General Timing Register 0, offset: 0x8C0 */
13297        uint8_t RESERVED_45[12];
13298   __I  uint32_t DX1RSR0;                           /**< DATX8 n Rank Status Register 0, offset: 0x8D0 */
13299   __I  uint32_t DX1RSR1;                           /**< DATX8 n Rank Status Register 1, offset: 0x8D4 */
13300   __I  uint32_t DX1RSR2;                           /**< DATX8 n Rank Status Register 2, offset: 0x8D8 */
13301   __I  uint32_t DX1RSR3;                           /**< DATX8 n Rank Status Register 3, offset: 0x8DC */
13302   __I  uint32_t DX1GSR0;                           /**< DATX8 n General Status Register 0, offset: 0x8E0 */
13303   __I  uint32_t DX1GSR1;                           /**< DATX8 n General Status Register 1, offset: 0x8E4 */
13304   __I  uint32_t DX1GSR2;                           /**< DATX8 n General Status Register 2, offset: 0x8E8 */
13305   __I  uint32_t DX1GSR3;                           /**< DATX8 n General Status Register 3, offset: 0x8EC */
13306   __I  uint32_t DX1GSR4;                           /**< DATX8 n General Status Register 4, offset: 0x8F0 */
13307   __I  uint32_t DX1GSR5;                           /**< DATX8 n General Status Register 5, offset: 0x8F4 */
13308   __I  uint32_t DX1GSR6;                           /**< DATX8 n General Status Register 6, offset: 0x8F8 */
13309        uint8_t RESERVED_46[4];
13310   __IO uint32_t DX2GCR0;                           /**< DATX8 n General Configuration Register 0, offset: 0x900 */
13311   __IO uint32_t DX2GCR1;                           /**< DATX8 n General Configuration Register 1, offset: 0x904 */
13312   __IO uint32_t DX2GCR2;                           /**< DATX8 n General Configuration Register 2, offset: 0x908 */
13313   __IO uint32_t DX2GCR3;                           /**< DATX8 n General Configuration Register 3, offset: 0x90C */
13314   __IO uint32_t DX2GCR4;                           /**< DATX8 n General Configuration Register 4, offset: 0x910 */
13315   __IO uint32_t DX2GCR5;                           /**< DATX8 n General Configuration Register 5, offset: 0x914 */
13316   __IO uint32_t DX2GCR6;                           /**< DATX8 n General Configuration Register 6, offset: 0x918 */
13317   __IO uint32_t DX2GCR7;                           /**< DATX8 n General Configuration Register 7, offset: 0x91C */
13318   __I  uint32_t DX2GCR8;                           /**< DATX8 n General Configuration Register 8, offset: 0x920 */
13319   __I  uint32_t DX2GCR9;                           /**< DATX8 n General Configuration Register 9, offset: 0x924 */
13320   __IO uint32_t DX2DQMAP0;                         /**< DATX8 n DQ/DM Mapping Register 0, offset: 0x928 */
13321   __IO uint32_t DX2DQMAP1;                         /**< DATX8 n DQ/DM Mapping Register 1, offset: 0x92C */
13322        uint8_t RESERVED_47[16];
13323   __IO uint32_t DX2BDLR0;                          /**< DATX8 n Bit Delay Line Register 0, offset: 0x940 */
13324   __IO uint32_t DX2BDLR1;                          /**< DATX8 n Bit Delay Line Register 1, offset: 0x944 */
13325   __IO uint32_t DX2BDLR2;                          /**< DATX8 n Bit Delay Line Register 2, offset: 0x948 */
13326        uint8_t RESERVED_48[4];
13327   __IO uint32_t DX2BDLR3;                          /**< DATX8 n Bit Delay Line Register 3, offset: 0x950 */
13328   __IO uint32_t DX2BDLR4;                          /**< DATX8 n Bit Delay Line Register 4, offset: 0x954 */
13329   __IO uint32_t DX2BDLR5;                          /**< DATX8 n Bit Delay Line Register 5, offset: 0x958 */
13330        uint8_t RESERVED_49[4];
13331   __IO uint32_t DX2BDLR6;                          /**< DATX8 n Bit Delay Line Register 6, offset: 0x960 */
13332   __I  uint32_t DX2BDLR7;                          /**< DATX8 n Bit Delay Line Register 7, offset: 0x964 */
13333   __I  uint32_t DX2BDLR8;                          /**< DATX8 n Bit Delay Line Register 8, offset: 0x968 */
13334   __I  uint32_t DX2BDLR9;                          /**< DATX8 n Bit Delay Line Register 9, offset: 0x96C */
13335        uint8_t RESERVED_50[16];
13336   __IO uint32_t DX2LCDLR0;                         /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0x980 */
13337   __IO uint32_t DX2LCDLR1;                         /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0x984 */
13338   __IO uint32_t DX2LCDLR2;                         /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0x988 */
13339   __IO uint32_t DX2LCDLR3;                         /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0x98C */
13340   __IO uint32_t DX2LCDLR4;                         /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0x990 */
13341   __IO uint32_t DX2LCDLR5;                         /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0x994 */
13342        uint8_t RESERVED_51[8];
13343   __IO uint32_t DX2MDLR0;                          /**< DATX8 n Master Delay Line Register 0, offset: 0x9A0 */
13344   __IO uint32_t DX2MDLR1;                          /**< DATX8 n Master Delay Line Register 1, offset: 0x9A4 */
13345        uint8_t RESERVED_52[24];
13346   __IO uint32_t DX2GTR0;                           /**< DATX8 n General Timing Register 0, offset: 0x9C0 */
13347        uint8_t RESERVED_53[12];
13348   __I  uint32_t DX2RSR0;                           /**< DATX8 n Rank Status Register 0, offset: 0x9D0 */
13349   __I  uint32_t DX2RSR1;                           /**< DATX8 n Rank Status Register 1, offset: 0x9D4 */
13350   __I  uint32_t DX2RSR2;                           /**< DATX8 n Rank Status Register 2, offset: 0x9D8 */
13351   __I  uint32_t DX2RSR3;                           /**< DATX8 n Rank Status Register 3, offset: 0x9DC */
13352   __I  uint32_t DX2GSR0;                           /**< DATX8 n General Status Register 0, offset: 0x9E0 */
13353   __I  uint32_t DX2GSR1;                           /**< DATX8 n General Status Register 1, offset: 0x9E4 */
13354   __I  uint32_t DX2GSR2;                           /**< DATX8 n General Status Register 2, offset: 0x9E8 */
13355   __I  uint32_t DX2GSR3;                           /**< DATX8 n General Status Register 3, offset: 0x9EC */
13356   __I  uint32_t DX2GSR4;                           /**< DATX8 n General Status Register 4, offset: 0x9F0 */
13357   __I  uint32_t DX2GSR5;                           /**< DATX8 n General Status Register 5, offset: 0x9F4 */
13358   __I  uint32_t DX2GSR6;                           /**< DATX8 n General Status Register 6, offset: 0x9F8 */
13359        uint8_t RESERVED_54[4];
13360   __IO uint32_t DX3GCR0;                           /**< DATX8 n General Configuration Register 0, offset: 0xA00 */
13361   __IO uint32_t DX3GCR1;                           /**< DATX8 n General Configuration Register 1, offset: 0xA04 */
13362   __IO uint32_t DX3GCR2;                           /**< DATX8 n General Configuration Register 2, offset: 0xA08 */
13363   __IO uint32_t DX3GCR3;                           /**< DATX8 n General Configuration Register 3, offset: 0xA0C */
13364   __IO uint32_t DX3GCR4;                           /**< DATX8 n General Configuration Register 4, offset: 0xA10 */
13365   __IO uint32_t DX3GCR5;                           /**< DATX8 n General Configuration Register 5, offset: 0xA14 */
13366   __IO uint32_t DX3GCR6;                           /**< DATX8 n General Configuration Register 6, offset: 0xA18 */
13367   __IO uint32_t DX3GCR7;                           /**< DATX8 n General Configuration Register 7, offset: 0xA1C */
13368   __I  uint32_t DX3GCR8;                           /**< DATX8 n General Configuration Register 8, offset: 0xA20 */
13369   __I  uint32_t DX3GCR9;                           /**< DATX8 n General Configuration Register 9, offset: 0xA24 */
13370   __IO uint32_t DX3DQMAP0;                         /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xA28 */
13371   __IO uint32_t DX3DQMAP1;                         /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xA2C */
13372        uint8_t RESERVED_55[16];
13373   __IO uint32_t DX3BDLR0;                          /**< DATX8 n Bit Delay Line Register 0, offset: 0xA40 */
13374   __IO uint32_t DX3BDLR1;                          /**< DATX8 n Bit Delay Line Register 1, offset: 0xA44 */
13375   __IO uint32_t DX3BDLR2;                          /**< DATX8 n Bit Delay Line Register 2, offset: 0xA48 */
13376        uint8_t RESERVED_56[4];
13377   __IO uint32_t DX3BDLR3;                          /**< DATX8 n Bit Delay Line Register 3, offset: 0xA50 */
13378   __IO uint32_t DX3BDLR4;                          /**< DATX8 n Bit Delay Line Register 4, offset: 0xA54 */
13379   __IO uint32_t DX3BDLR5;                          /**< DATX8 n Bit Delay Line Register 5, offset: 0xA58 */
13380        uint8_t RESERVED_57[4];
13381   __IO uint32_t DX3BDLR6;                          /**< DATX8 n Bit Delay Line Register 6, offset: 0xA60 */
13382   __I  uint32_t DX3BDLR7;                          /**< DATX8 n Bit Delay Line Register 7, offset: 0xA64 */
13383   __I  uint32_t DX3BDLR8;                          /**< DATX8 n Bit Delay Line Register 8, offset: 0xA68 */
13384   __I  uint32_t DX3BDLR9;                          /**< DATX8 n Bit Delay Line Register 9, offset: 0xA6C */
13385        uint8_t RESERVED_58[16];
13386   __IO uint32_t DX3LCDLR0;                         /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xA80 */
13387   __IO uint32_t DX3LCDLR1;                         /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xA84 */
13388   __IO uint32_t DX3LCDLR2;                         /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xA88 */
13389   __IO uint32_t DX3LCDLR3;                         /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xA8C */
13390   __IO uint32_t DX3LCDLR4;                         /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xA90 */
13391   __IO uint32_t DX3LCDLR5;                         /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xA94 */
13392        uint8_t RESERVED_59[8];
13393   __IO uint32_t DX3MDLR0;                          /**< DATX8 n Master Delay Line Register 0, offset: 0xAA0 */
13394   __IO uint32_t DX3MDLR1;                          /**< DATX8 n Master Delay Line Register 1, offset: 0xAA4 */
13395        uint8_t RESERVED_60[24];
13396   __IO uint32_t DX3GTR0;                           /**< DATX8 n General Timing Register 0, offset: 0xAC0 */
13397        uint8_t RESERVED_61[12];
13398   __I  uint32_t DX3RSR0;                           /**< DATX8 n Rank Status Register 0, offset: 0xAD0 */
13399   __I  uint32_t DX3RSR1;                           /**< DATX8 n Rank Status Register 1, offset: 0xAD4 */
13400   __I  uint32_t DX3RSR2;                           /**< DATX8 n Rank Status Register 2, offset: 0xAD8 */
13401   __I  uint32_t DX3RSR3;                           /**< DATX8 n Rank Status Register 3, offset: 0xADC */
13402   __I  uint32_t DX3GSR0;                           /**< DATX8 n General Status Register 0, offset: 0xAE0 */
13403   __I  uint32_t DX3GSR1;                           /**< DATX8 n General Status Register 1, offset: 0xAE4 */
13404   __I  uint32_t DX3GSR2;                           /**< DATX8 n General Status Register 2, offset: 0xAE8 */
13405   __I  uint32_t DX3GSR3;                           /**< DATX8 n General Status Register 3, offset: 0xAEC */
13406   __I  uint32_t DX3GSR4;                           /**< DATX8 n General Status Register 4, offset: 0xAF0 */
13407   __I  uint32_t DX3GSR5;                           /**< DATX8 n General Status Register 5, offset: 0xAF4 */
13408   __I  uint32_t DX3GSR6;                           /**< DATX8 n General Status Register 6, offset: 0xAF8 */
13409        uint8_t RESERVED_62[4];
13410   __I  uint32_t DX4GCR0;                           /**< DATX8 n General Configuration Register 0, offset: 0xB00 */
13411   __I  uint32_t DX4GCR1;                           /**< DATX8 n General Configuration Register 1, offset: 0xB04 */
13412   __I  uint32_t DX4GCR2;                           /**< DATX8 n General Configuration Register 2, offset: 0xB08 */
13413   __I  uint32_t DX4GCR3;                           /**< DATX8 n General Configuration Register 3, offset: 0xB0C */
13414   __I  uint32_t DX4GCR4;                           /**< DATX8 n General Configuration Register 4, offset: 0xB10 */
13415   __I  uint32_t DX4GCR5;                           /**< DATX8 n General Configuration Register 5, offset: 0xB14 */
13416   __I  uint32_t DX4GCR6;                           /**< DATX8 n General Configuration Register 6, offset: 0xB18 */
13417   __I  uint32_t DX4GCR7;                           /**< DATX8 n General Configuration Register 7, offset: 0xB1C */
13418   __I  uint32_t DX4GCR8;                           /**< DATX8 n General Configuration Register 8, offset: 0xB20 */
13419   __I  uint32_t DX4GCR9;                           /**< DATX8 n General Configuration Register 9, offset: 0xB24 */
13420   __I  uint32_t DX4DQMAP0;                         /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xB28 */
13421   __I  uint32_t DX4DQMAP1;                         /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xB2C */
13422        uint8_t RESERVED_63[16];
13423   __I  uint32_t DX4BDLR0;                          /**< DATX8 n Bit Delay Line Register 0, offset: 0xB40 */
13424   __I  uint32_t DX4BDLR1;                          /**< DATX8 n Bit Delay Line Register 1, offset: 0xB44 */
13425   __I  uint32_t DX4BDLR2;                          /**< DATX8 n Bit Delay Line Register 2, offset: 0xB48 */
13426        uint8_t RESERVED_64[4];
13427   __I  uint32_t DX4BDLR3;                          /**< DATX8 n Bit Delay Line Register 3, offset: 0xB50 */
13428   __I  uint32_t DX4BDLR4;                          /**< DATX8 n Bit Delay Line Register 4, offset: 0xB54 */
13429   __I  uint32_t DX4BDLR5;                          /**< DATX8 n Bit Delay Line Register 5, offset: 0xB58 */
13430        uint8_t RESERVED_65[4];
13431   __I  uint32_t DX4BDLR6;                          /**< DATX8 n Bit Delay Line Register 6, offset: 0xB60 */
13432   __I  uint32_t DX4BDLR7;                          /**< DATX8 n Bit Delay Line Register 7, offset: 0xB64 */
13433   __I  uint32_t DX4BDLR8;                          /**< DATX8 n Bit Delay Line Register 8, offset: 0xB68 */
13434   __I  uint32_t DX4BDLR9;                          /**< DATX8 n Bit Delay Line Register 9, offset: 0xB6C */
13435        uint8_t RESERVED_66[16];
13436   __I  uint32_t DX4LCDLR0;                         /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xB80 */
13437   __I  uint32_t DX4LCDLR1;                         /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xB84 */
13438   __I  uint32_t DX4LCDLR2;                         /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xB88 */
13439   __I  uint32_t DX4LCDLR3;                         /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xB8C */
13440   __I  uint32_t DX4LCDLR4;                         /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xB90 */
13441   __I  uint32_t DX4LCDLR5;                         /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xB94 */
13442        uint8_t RESERVED_67[8];
13443   __I  uint32_t DX4MDLR0;                          /**< DATX8 n Master Delay Line Register 0, offset: 0xBA0 */
13444   __I  uint32_t DX4MDLR1;                          /**< DATX8 n Master Delay Line Register 1, offset: 0xBA4 */
13445        uint8_t RESERVED_68[24];
13446   __I  uint32_t DX4GTR0;                           /**< DATX8 n General Timing Register 0, offset: 0xBC0 */
13447        uint8_t RESERVED_69[12];
13448   __I  uint32_t DX4RSR0;                           /**< DATX8 n Rank Status Register 0, offset: 0xBD0 */
13449   __I  uint32_t DX4RSR1;                           /**< DATX8 n Rank Status Register 1, offset: 0xBD4 */
13450   __I  uint32_t DX4RSR2;                           /**< DATX8 n Rank Status Register 2, offset: 0xBD8 */
13451   __I  uint32_t DX4RSR3;                           /**< DATX8 n Rank Status Register 3, offset: 0xBDC */
13452   __I  uint32_t DX4GSR0;                           /**< DATX8 n General Status Register 0, offset: 0xBE0 */
13453   __I  uint32_t DX4GSR1;                           /**< DATX8 n General Status Register 1, offset: 0xBE4 */
13454   __I  uint32_t DX4GSR2;                           /**< DATX8 n General Status Register 2, offset: 0xBE8 */
13455   __I  uint32_t DX4GSR3;                           /**< DATX8 n General Status Register 3, offset: 0xBEC */
13456   __I  uint32_t DX4GSR4;                           /**< DATX8 n General Status Register 4, offset: 0xBF0 */
13457   __I  uint32_t DX4GSR5;                           /**< DATX8 n General Status Register 5, offset: 0xBF4 */
13458   __I  uint32_t DX4GSR6;                           /**< DATX8 n General Status Register 6, offset: 0xBF8 */
13459        uint8_t RESERVED_70[4];
13460   __I  uint32_t DX5GCR0;                           /**< DATX8 n General Configuration Register 0, offset: 0xC00 */
13461   __I  uint32_t DX5GCR1;                           /**< DATX8 n General Configuration Register 1, offset: 0xC04 */
13462   __I  uint32_t DX5GCR2;                           /**< DATX8 n General Configuration Register 2, offset: 0xC08 */
13463   __I  uint32_t DX5GCR3;                           /**< DATX8 n General Configuration Register 3, offset: 0xC0C */
13464   __I  uint32_t DX5GCR4;                           /**< DATX8 n General Configuration Register 4, offset: 0xC10 */
13465   __I  uint32_t DX5GCR5;                           /**< DATX8 n General Configuration Register 5, offset: 0xC14 */
13466   __I  uint32_t DX5GCR6;                           /**< DATX8 n General Configuration Register 6, offset: 0xC18 */
13467   __I  uint32_t DX5GCR7;                           /**< DATX8 n General Configuration Register 7, offset: 0xC1C */
13468   __I  uint32_t DX5GCR8;                           /**< DATX8 n General Configuration Register 8, offset: 0xC20 */
13469   __I  uint32_t DX5GCR9;                           /**< DATX8 n General Configuration Register 9, offset: 0xC24 */
13470   __I  uint32_t DX5DQMAP0;                         /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xC28 */
13471   __I  uint32_t DX5DQMAP1;                         /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xC2C */
13472        uint8_t RESERVED_71[16];
13473   __I  uint32_t DX5BDLR0;                          /**< DATX8 n Bit Delay Line Register 0, offset: 0xC40 */
13474   __I  uint32_t DX5BDLR1;                          /**< DATX8 n Bit Delay Line Register 1, offset: 0xC44 */
13475   __I  uint32_t DX5BDLR2;                          /**< DATX8 n Bit Delay Line Register 2, offset: 0xC48 */
13476        uint8_t RESERVED_72[4];
13477   __I  uint32_t DX5BDLR3;                          /**< DATX8 n Bit Delay Line Register 3, offset: 0xC50 */
13478   __I  uint32_t DX5BDLR4;                          /**< DATX8 n Bit Delay Line Register 4, offset: 0xC54 */
13479   __I  uint32_t DX5BDLR5;                          /**< DATX8 n Bit Delay Line Register 5, offset: 0xC58 */
13480        uint8_t RESERVED_73[4];
13481   __I  uint32_t DX5BDLR6;                          /**< DATX8 n Bit Delay Line Register 6, offset: 0xC60 */
13482   __I  uint32_t DX5BDLR7;                          /**< DATX8 n Bit Delay Line Register 7, offset: 0xC64 */
13483   __I  uint32_t DX5BDLR8;                          /**< DATX8 n Bit Delay Line Register 8, offset: 0xC68 */
13484   __I  uint32_t DX5BDLR9;                          /**< DATX8 n Bit Delay Line Register 9, offset: 0xC6C */
13485        uint8_t RESERVED_74[16];
13486   __I  uint32_t DX5LCDLR0;                         /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xC80 */
13487   __I  uint32_t DX5LCDLR1;                         /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xC84 */
13488   __I  uint32_t DX5LCDLR2;                         /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xC88 */
13489   __I  uint32_t DX5LCDLR3;                         /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xC8C */
13490   __I  uint32_t DX5LCDLR4;                         /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xC90 */
13491   __I  uint32_t DX5LCDLR5;                         /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xC94 */
13492        uint8_t RESERVED_75[8];
13493   __I  uint32_t DX5MDLR0;                          /**< DATX8 n Master Delay Line Register 0, offset: 0xCA0 */
13494   __I  uint32_t DX5MDLR1;                          /**< DATX8 n Master Delay Line Register 1, offset: 0xCA4 */
13495        uint8_t RESERVED_76[24];
13496   __I  uint32_t DX5GTR0;                           /**< DATX8 n General Timing Register 0, offset: 0xCC0 */
13497        uint8_t RESERVED_77[12];
13498   __I  uint32_t DX5RSR0;                           /**< DATX8 n Rank Status Register 0, offset: 0xCD0 */
13499   __I  uint32_t DX5RSR1;                           /**< DATX8 n Rank Status Register 1, offset: 0xCD4 */
13500   __I  uint32_t DX5RSR2;                           /**< DATX8 n Rank Status Register 2, offset: 0xCD8 */
13501   __I  uint32_t DX5RSR3;                           /**< DATX8 n Rank Status Register 3, offset: 0xCDC */
13502   __I  uint32_t DX5GSR0;                           /**< DATX8 n General Status Register 0, offset: 0xCE0 */
13503   __I  uint32_t DX5GSR1;                           /**< DATX8 n General Status Register 1, offset: 0xCE4 */
13504   __I  uint32_t DX5GSR2;                           /**< DATX8 n General Status Register 2, offset: 0xCE8 */
13505   __I  uint32_t DX5GSR3;                           /**< DATX8 n General Status Register 3, offset: 0xCEC */
13506   __I  uint32_t DX5GSR4;                           /**< DATX8 n General Status Register 4, offset: 0xCF0 */
13507   __I  uint32_t DX5GSR5;                           /**< DATX8 n General Status Register 5, offset: 0xCF4 */
13508   __I  uint32_t DX5GSR6;                           /**< DATX8 n General Status Register 6, offset: 0xCF8 */
13509        uint8_t RESERVED_78[4];
13510   __I  uint32_t DX6GCR0;                           /**< DATX8 n General Configuration Register 0, offset: 0xD00 */
13511   __I  uint32_t DX6GCR1;                           /**< DATX8 n General Configuration Register 1, offset: 0xD04 */
13512   __I  uint32_t DX6GCR2;                           /**< DATX8 n General Configuration Register 2, offset: 0xD08 */
13513   __I  uint32_t DX6GCR3;                           /**< DATX8 n General Configuration Register 3, offset: 0xD0C */
13514   __I  uint32_t DX6GCR4;                           /**< DATX8 n General Configuration Register 4, offset: 0xD10 */
13515   __I  uint32_t DX6GCR5;                           /**< DATX8 n General Configuration Register 5, offset: 0xD14 */
13516   __I  uint32_t DX6GCR6;                           /**< DATX8 n General Configuration Register 6, offset: 0xD18 */
13517   __I  uint32_t DX6GCR7;                           /**< DATX8 n General Configuration Register 7, offset: 0xD1C */
13518   __I  uint32_t DX6GCR8;                           /**< DATX8 n General Configuration Register 8, offset: 0xD20 */
13519   __I  uint32_t DX6GCR9;                           /**< DATX8 n General Configuration Register 9, offset: 0xD24 */
13520   __I  uint32_t DX6DQMAP0;                         /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xD28 */
13521   __I  uint32_t DX6DQMAP1;                         /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xD2C */
13522        uint8_t RESERVED_79[16];
13523   __I  uint32_t DX6BDLR0;                          /**< DATX8 n Bit Delay Line Register 0, offset: 0xD40 */
13524   __I  uint32_t DX6BDLR1;                          /**< DATX8 n Bit Delay Line Register 1, offset: 0xD44 */
13525   __I  uint32_t DX6BDLR2;                          /**< DATX8 n Bit Delay Line Register 2, offset: 0xD48 */
13526        uint8_t RESERVED_80[4];
13527   __I  uint32_t DX6BDLR3;                          /**< DATX8 n Bit Delay Line Register 3, offset: 0xD50 */
13528   __I  uint32_t DX6BDLR4;                          /**< DATX8 n Bit Delay Line Register 4, offset: 0xD54 */
13529   __I  uint32_t DX6BDLR5;                          /**< DATX8 n Bit Delay Line Register 5, offset: 0xD58 */
13530        uint8_t RESERVED_81[4];
13531   __I  uint32_t DX6BDLR6;                          /**< DATX8 n Bit Delay Line Register 6, offset: 0xD60 */
13532   __I  uint32_t DX6BDLR7;                          /**< DATX8 n Bit Delay Line Register 7, offset: 0xD64 */
13533   __I  uint32_t DX6BDLR8;                          /**< DATX8 n Bit Delay Line Register 8, offset: 0xD68 */
13534   __I  uint32_t DX6BDLR9;                          /**< DATX8 n Bit Delay Line Register 9, offset: 0xD6C */
13535        uint8_t RESERVED_82[16];
13536   __I  uint32_t DX6LCDLR0;                         /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xD80 */
13537   __I  uint32_t DX6LCDLR1;                         /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xD84 */
13538   __I  uint32_t DX6LCDLR2;                         /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xD88 */
13539   __I  uint32_t DX6LCDLR3;                         /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xD8C */
13540   __I  uint32_t DX6LCDLR4;                         /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xD90 */
13541   __I  uint32_t DX6LCDLR5;                         /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xD94 */
13542        uint8_t RESERVED_83[8];
13543   __I  uint32_t DX6MDLR0;                          /**< DATX8 n Master Delay Line Register 0, offset: 0xDA0 */
13544   __I  uint32_t DX6MDLR1;                          /**< DATX8 n Master Delay Line Register 1, offset: 0xDA4 */
13545        uint8_t RESERVED_84[24];
13546   __I  uint32_t DX6GTR0;                           /**< DATX8 n General Timing Register 0, offset: 0xDC0 */
13547        uint8_t RESERVED_85[12];
13548   __I  uint32_t DX6RSR0;                           /**< DATX8 n Rank Status Register 0, offset: 0xDD0 */
13549   __I  uint32_t DX6RSR1;                           /**< DATX8 n Rank Status Register 1, offset: 0xDD4 */
13550   __I  uint32_t DX6RSR2;                           /**< DATX8 n Rank Status Register 2, offset: 0xDD8 */
13551   __I  uint32_t DX6RSR3;                           /**< DATX8 n Rank Status Register 3, offset: 0xDDC */
13552   __I  uint32_t DX6GSR0;                           /**< DATX8 n General Status Register 0, offset: 0xDE0 */
13553   __I  uint32_t DX6GSR1;                           /**< DATX8 n General Status Register 1, offset: 0xDE4 */
13554   __I  uint32_t DX6GSR2;                           /**< DATX8 n General Status Register 2, offset: 0xDE8 */
13555   __I  uint32_t DX6GSR3;                           /**< DATX8 n General Status Register 3, offset: 0xDEC */
13556   __I  uint32_t DX6GSR4;                           /**< DATX8 n General Status Register 4, offset: 0xDF0 */
13557   __I  uint32_t DX6GSR5;                           /**< DATX8 n General Status Register 5, offset: 0xDF4 */
13558   __I  uint32_t DX6GSR6;                           /**< DATX8 n General Status Register 6, offset: 0xDF8 */
13559        uint8_t RESERVED_86[4];
13560   __I  uint32_t DX7GCR0;                           /**< DATX8 n General Configuration Register 0, offset: 0xE00 */
13561   __I  uint32_t DX7GCR1;                           /**< DATX8 n General Configuration Register 1, offset: 0xE04 */
13562   __I  uint32_t DX7GCR2;                           /**< DATX8 n General Configuration Register 2, offset: 0xE08 */
13563   __I  uint32_t DX7GCR3;                           /**< DATX8 n General Configuration Register 3, offset: 0xE0C */
13564   __I  uint32_t DX7GCR4;                           /**< DATX8 n General Configuration Register 4, offset: 0xE10 */
13565   __I  uint32_t DX7GCR5;                           /**< DATX8 n General Configuration Register 5, offset: 0xE14 */
13566   __I  uint32_t DX7GCR6;                           /**< DATX8 n General Configuration Register 6, offset: 0xE18 */
13567   __I  uint32_t DX7GCR7;                           /**< DATX8 n General Configuration Register 7, offset: 0xE1C */
13568   __I  uint32_t DX7GCR8;                           /**< DATX8 n General Configuration Register 8, offset: 0xE20 */
13569   __I  uint32_t DX7GCR9;                           /**< DATX8 n General Configuration Register 9, offset: 0xE24 */
13570   __I  uint32_t DX7DQMAP0;                         /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xE28 */
13571   __I  uint32_t DX7DQMAP1;                         /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xE2C */
13572        uint8_t RESERVED_87[16];
13573   __I  uint32_t DX7BDLR0;                          /**< DATX8 n Bit Delay Line Register 0, offset: 0xE40 */
13574   __I  uint32_t DX7BDLR1;                          /**< DATX8 n Bit Delay Line Register 1, offset: 0xE44 */
13575   __I  uint32_t DX7BDLR2;                          /**< DATX8 n Bit Delay Line Register 2, offset: 0xE48 */
13576        uint8_t RESERVED_88[4];
13577   __I  uint32_t DX7BDLR3;                          /**< DATX8 n Bit Delay Line Register 3, offset: 0xE50 */
13578   __I  uint32_t DX7BDLR4;                          /**< DATX8 n Bit Delay Line Register 4, offset: 0xE54 */
13579   __I  uint32_t DX7BDLR5;                          /**< DATX8 n Bit Delay Line Register 5, offset: 0xE58 */
13580        uint8_t RESERVED_89[4];
13581   __I  uint32_t DX7BDLR6;                          /**< DATX8 n Bit Delay Line Register 6, offset: 0xE60 */
13582   __I  uint32_t DX7BDLR7;                          /**< DATX8 n Bit Delay Line Register 7, offset: 0xE64 */
13583   __I  uint32_t DX7BDLR8;                          /**< DATX8 n Bit Delay Line Register 8, offset: 0xE68 */
13584   __I  uint32_t DX7BDLR9;                          /**< DATX8 n Bit Delay Line Register 9, offset: 0xE6C */
13585        uint8_t RESERVED_90[16];
13586   __I  uint32_t DX7LCDLR0;                         /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xE80 */
13587   __I  uint32_t DX7LCDLR1;                         /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xE84 */
13588   __I  uint32_t DX7LCDLR2;                         /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xE88 */
13589   __I  uint32_t DX7LCDLR3;                         /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xE8C */
13590   __I  uint32_t DX7LCDLR4;                         /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xE90 */
13591   __I  uint32_t DX7LCDLR5;                         /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xE94 */
13592        uint8_t RESERVED_91[8];
13593   __I  uint32_t DX7MDLR0;                          /**< DATX8 n Master Delay Line Register 0, offset: 0xEA0 */
13594   __I  uint32_t DX7MDLR1;                          /**< DATX8 n Master Delay Line Register 1, offset: 0xEA4 */
13595        uint8_t RESERVED_92[24];
13596   __I  uint32_t DX7GTR0;                           /**< DATX8 n General Timing Register 0, offset: 0xEC0 */
13597        uint8_t RESERVED_93[12];
13598   __I  uint32_t DX7RSR0;                           /**< DATX8 n Rank Status Register 0, offset: 0xED0 */
13599   __I  uint32_t DX7RSR1;                           /**< DATX8 n Rank Status Register 1, offset: 0xED4 */
13600   __I  uint32_t DX7RSR2;                           /**< DATX8 n Rank Status Register 2, offset: 0xED8 */
13601   __I  uint32_t DX7RSR3;                           /**< DATX8 n Rank Status Register 3, offset: 0xEDC */
13602   __I  uint32_t DX7GSR0;                           /**< DATX8 n General Status Register 0, offset: 0xEE0 */
13603   __I  uint32_t DX7GSR1;                           /**< DATX8 n General Status Register 1, offset: 0xEE4 */
13604   __I  uint32_t DX7GSR2;                           /**< DATX8 n General Status Register 2, offset: 0xEE8 */
13605   __I  uint32_t DX7GSR3;                           /**< DATX8 n General Status Register 3, offset: 0xEEC */
13606   __I  uint32_t DX7GSR4;                           /**< DATX8 n General Status Register 4, offset: 0xEF0 */
13607   __I  uint32_t DX7GSR5;                           /**< DATX8 n General Status Register 5, offset: 0xEF4 */
13608   __I  uint32_t DX7GSR6;                           /**< DATX8 n General Status Register 6, offset: 0xEF8 */
13609        uint8_t RESERVED_94[4];
13610   __I  uint32_t DX8GCR0;                           /**< DATX8 n General Configuration Register 0, offset: 0xF00 */
13611   __I  uint32_t DX8GCR1;                           /**< DATX8 n General Configuration Register 1, offset: 0xF04 */
13612   __I  uint32_t DX8GCR2;                           /**< DATX8 n General Configuration Register 2, offset: 0xF08 */
13613   __I  uint32_t DX8GCR3;                           /**< DATX8 n General Configuration Register 3, offset: 0xF0C */
13614   __I  uint32_t DX8GCR4;                           /**< DATX8 n General Configuration Register 4, offset: 0xF10 */
13615   __I  uint32_t DX8GCR5;                           /**< DATX8 n General Configuration Register 5, offset: 0xF14 */
13616   __I  uint32_t DX8GCR6;                           /**< DATX8 n General Configuration Register 6, offset: 0xF18 */
13617   __I  uint32_t DX8GCR7;                           /**< DATX8 n General Configuration Register 7, offset: 0xF1C */
13618   __I  uint32_t DX8GCR8;                           /**< DATX8 n General Configuration Register 8, offset: 0xF20 */
13619   __I  uint32_t DX8GCR9;                           /**< DATX8 n General Configuration Register 9, offset: 0xF24 */
13620   __I  uint32_t DX8DQMAP0;                         /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xF28 */
13621   __I  uint32_t DX8DQMAP1;                         /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xF2C */
13622        uint8_t RESERVED_95[16];
13623   __I  uint32_t DX8BDLR0;                          /**< DATX8 n Bit Delay Line Register 0, offset: 0xF40 */
13624   __I  uint32_t DX8BDLR1;                          /**< DATX8 n Bit Delay Line Register 1, offset: 0xF44 */
13625   __I  uint32_t DX8BDLR2;                          /**< DATX8 n Bit Delay Line Register 2, offset: 0xF48 */
13626        uint8_t RESERVED_96[4];
13627   __I  uint32_t DX8BDLR3;                          /**< DATX8 n Bit Delay Line Register 3, offset: 0xF50 */
13628   __I  uint32_t DX8BDLR4;                          /**< DATX8 n Bit Delay Line Register 4, offset: 0xF54 */
13629   __I  uint32_t DX8BDLR5;                          /**< DATX8 n Bit Delay Line Register 5, offset: 0xF58 */
13630        uint8_t RESERVED_97[4];
13631   __I  uint32_t DX8BDLR6;                          /**< DATX8 n Bit Delay Line Register 6, offset: 0xF60 */
13632   __I  uint32_t DX8BDLR7;                          /**< DATX8 n Bit Delay Line Register 7, offset: 0xF64 */
13633   __I  uint32_t DX8BDLR8;                          /**< DATX8 n Bit Delay Line Register 8, offset: 0xF68 */
13634   __I  uint32_t DX8BDLR9;                          /**< DATX8 n Bit Delay Line Register 9, offset: 0xF6C */
13635        uint8_t RESERVED_98[16];
13636   __I  uint32_t DX8LCDLR0;                         /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xF80 */
13637   __I  uint32_t DX8LCDLR1;                         /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xF84 */
13638   __I  uint32_t DX8LCDLR2;                         /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xF88 */
13639   __I  uint32_t DX8LCDLR3;                         /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xF8C */
13640   __I  uint32_t DX8LCDLR4;                         /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xF90 */
13641   __I  uint32_t DX8LCDLR5;                         /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xF94 */
13642        uint8_t RESERVED_99[8];
13643   __I  uint32_t DX8MDLR0;                          /**< DATX8 n Master Delay Line Register 0, offset: 0xFA0 */
13644   __I  uint32_t DX8MDLR1;                          /**< DATX8 n Master Delay Line Register 1, offset: 0xFA4 */
13645        uint8_t RESERVED_100[24];
13646   __I  uint32_t DX8GTR0;                           /**< DATX8 n General Timing Register 0, offset: 0xFC0 */
13647        uint8_t RESERVED_101[12];
13648   __I  uint32_t DX8RSR0;                           /**< DATX8 n Rank Status Register 0, offset: 0xFD0 */
13649   __I  uint32_t DX8RSR1;                           /**< DATX8 n Rank Status Register 1, offset: 0xFD4 */
13650   __I  uint32_t DX8RSR2;                           /**< DATX8 n Rank Status Register 2, offset: 0xFD8 */
13651   __I  uint32_t DX8RSR3;                           /**< DATX8 n Rank Status Register 3, offset: 0xFDC */
13652   __I  uint32_t DX8GSR0;                           /**< DATX8 n General Status Register 0, offset: 0xFE0 */
13653   __I  uint32_t DX8GSR1;                           /**< DATX8 n General Status Register 1, offset: 0xFE4 */
13654   __I  uint32_t DX8GSR2;                           /**< DATX8 n General Status Register 2, offset: 0xFE8 */
13655   __I  uint32_t DX8GSR3;                           /**< DATX8 n General Status Register 3, offset: 0xFEC */
13656   __I  uint32_t DX8GSR4;                           /**< DATX8 n General Status Register 4, offset: 0xFF0 */
13657   __I  uint32_t DX8GSR5;                           /**< DATX8 n General Status Register 5, offset: 0xFF4 */
13658   __I  uint32_t DX8GSR6;                           /**< DATX8 n General Status Register 6, offset: 0xFF8 */
13659        uint8_t RESERVED_102[1028];
13660   __IO uint32_t DX8SL0OSC;                         /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1400 */
13661   __IO uint32_t DX8SL0PLLCR0;                      /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1404 */
13662   __IO uint32_t DX8SL0PLLCR1;                      /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1408 */
13663   __IO uint32_t DX8SL0PLLCR2;                      /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x140C */
13664   __IO uint32_t DX8SL0PLLCR3;                      /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1410 */
13665   __IO uint32_t DX8SL0PLLCR4;                      /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1414 */
13666   __IO uint32_t DX8SL0PLLCR5;                      /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1418 */
13667   __IO uint32_t DX8SL0DQSCTL;                      /**< DATX8 0-1 DQS Control Register, offset: 0x141C */
13668   __I  uint32_t DX8SL0TRNCTL;                      /**< DATX8 0-1 Training Control Register, offset: 0x1420 */
13669   __IO uint32_t DX8SL0DDLCTL;                      /**< DATX8 0-1 DDL Control Register, offset: 0x1424 */
13670   __IO uint32_t DX8SL0DXCTL1;                      /**< DATX8 0-1 DX Control Register 1, offset: 0x1428 */
13671   __IO uint32_t DX8SL0DXCTL2;                      /**< DATX8 0-1 DX Control Register 2, offset: 0x142C */
13672   __IO uint32_t DX8SL0IOCR;                        /**< DATX8 0-1 I/O Configuration Register, offset: 0x1430 */
13673   __I  uint32_t DX4SL0IOCR;                        /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1434 */
13674        uint8_t RESERVED_103[8];
13675   __IO uint32_t DX8SL1OSC;                         /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1440 */
13676   __IO uint32_t DX8SL1PLLCR0;                      /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1444 */
13677   __IO uint32_t DX8SL1PLLCR1;                      /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1448 */
13678   __IO uint32_t DX8SL1PLLCR2;                      /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x144C */
13679   __IO uint32_t DX8SL1PLLCR3;                      /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1450 */
13680   __IO uint32_t DX8SL1PLLCR4;                      /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1454 */
13681   __IO uint32_t DX8SL1PLLCR5;                      /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1458 */
13682   __IO uint32_t DX8SL1DQSCTL;                      /**< DATX8 0-1 DQS Control Register, offset: 0x145C */
13683   __I  uint32_t DX8SL1TRNCTL;                      /**< DATX8 0-1 Training Control Register, offset: 0x1460 */
13684   __IO uint32_t DX8SL1DDLCTL;                      /**< DATX8 0-1 DDL Control Register, offset: 0x1464 */
13685   __IO uint32_t DX8SL1DXCTL1;                      /**< DATX8 0-1 DX Control Register 1, offset: 0x1468 */
13686   __IO uint32_t DX8SL1DXCTL2;                      /**< DATX8 0-1 DX Control Register 2, offset: 0x146C */
13687   __IO uint32_t DX8SL1IOCR;                        /**< DATX8 0-1 I/O Configuration Register, offset: 0x1470 */
13688   __I  uint32_t DX4SL1IOCR;                        /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1474 */
13689        uint8_t RESERVED_104[8];
13690   __IO uint32_t DX8SL2OSC;                         /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1480 */
13691   __IO uint32_t DX8SL2PLLCR0;                      /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1484 */
13692   __IO uint32_t DX8SL2PLLCR1;                      /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1488 */
13693   __IO uint32_t DX8SL2PLLCR2;                      /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x148C */
13694   __IO uint32_t DX8SL2PLLCR3;                      /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1490 */
13695   __IO uint32_t DX8SL2PLLCR4;                      /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1494 */
13696   __IO uint32_t DX8SL2PLLCR5;                      /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1498 */
13697   __IO uint32_t DX8SL2DQSCTL;                      /**< DATX8 0-1 DQS Control Register, offset: 0x149C */
13698   __I  uint32_t DX8SL2TRNCTL;                      /**< DATX8 0-1 Training Control Register, offset: 0x14A0 */
13699   __IO uint32_t DX8SL2DDLCTL;                      /**< DATX8 0-1 DDL Control Register, offset: 0x14A4 */
13700   __IO uint32_t DX8SL2DXCTL1;                      /**< DATX8 0-1 DX Control Register 1, offset: 0x14A8 */
13701   __IO uint32_t DX8SL2DXCTL2;                      /**< DATX8 0-1 DX Control Register 2, offset: 0x14AC */
13702   __IO uint32_t DX8SL2IOCR;                        /**< DATX8 0-1 I/O Configuration Register, offset: 0x14B0 */
13703   __I  uint32_t DX4SL2IOCR;                        /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x14B4 */
13704        uint8_t RESERVED_105[8];
13705   __I  uint32_t DX8SL3OSC;                         /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x14C0 */
13706   __I  uint32_t DX8SL3PLLCR0;                      /**< DAXT8 0-1 PLL Control Register 0, offset: 0x14C4 */
13707   __I  uint32_t DX8SL3PLLCR1;                      /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x14C8 */
13708   __I  uint32_t DX8SL3PLLCR2;                      /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x14CC */
13709   __I  uint32_t DX8SL3PLLCR3;                      /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x14D0 */
13710   __I  uint32_t DX8SL3PLLCR4;                      /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x14D4 */
13711   __I  uint32_t DX8SL3PLLCR5;                      /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x14D8 */
13712   __I  uint32_t DX8SL3DQSCTL;                      /**< DATX8 0-1 DQS Control Register, offset: 0x14DC */
13713   __I  uint32_t DX8SL3TRNCTL;                      /**< DATX8 0-1 Training Control Register, offset: 0x14E0 */
13714   __I  uint32_t DX8SL3DDLCTL;                      /**< DATX8 0-1 DDL Control Register, offset: 0x14E4 */
13715   __I  uint32_t DX8SL3DXCTL1;                      /**< DATX8 0-1 DX Control Register 1, offset: 0x14E8 */
13716   __I  uint32_t DX8SL3DXCTL2;                      /**< DATX8 0-1 DX Control Register 2, offset: 0x14EC */
13717   __I  uint32_t DX8SL3IOCR;                        /**< DATX8 0-1 I/O Configuration Register, offset: 0x14F0 */
13718   __I  uint32_t DX4SL3IOCR;                        /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x14F4 */
13719        uint8_t RESERVED_106[8];
13720   __I  uint32_t DX8SL4OSC;                         /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1500 */
13721   __I  uint32_t DX8SL4PLLCR0;                      /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1504 */
13722   __I  uint32_t DX8SL4PLLCR1;                      /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1508 */
13723   __I  uint32_t DX8SL4PLLCR2;                      /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x150C */
13724   __I  uint32_t DX8SL4PLLCR3;                      /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1510 */
13725   __I  uint32_t DX8SL4PLLCR4;                      /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1514 */
13726   __I  uint32_t DX8SL4PLLCR5;                      /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1518 */
13727   __I  uint32_t DX8SL4DQSCTL;                      /**< DATX8 0-1 DQS Control Register, offset: 0x151C */
13728   __I  uint32_t DX8SL4TRNCTL;                      /**< DATX8 0-1 Training Control Register, offset: 0x1520 */
13729   __I  uint32_t DX8SL4DDLCTL;                      /**< DATX8 0-1 DDL Control Register, offset: 0x1524 */
13730   __I  uint32_t DX8SL4DXCTL1;                      /**< DATX8 0-1 DX Control Register 1, offset: 0x1528 */
13731   __I  uint32_t DX8SL4DXCTL2;                      /**< DATX8 0-1 DX Control Register 2, offset: 0x152C */
13732   __I  uint32_t DX8SL4IOCR;                        /**< DATX8 0-1 I/O Configuration Register, offset: 0x1530 */
13733   __I  uint32_t DX4SL4IOCR;                        /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1534 */
13734        uint8_t RESERVED_107[8];
13735   __I  uint32_t DX8SL5OSC;                         /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1540 */
13736   __I  uint32_t DX8SL5PLLCR0;                      /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1544 */
13737   __I  uint32_t DX8SL5PLLCR1;                      /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1548 */
13738   __I  uint32_t DX8SL5PLLCR2;                      /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x154C */
13739   __I  uint32_t DX8SL5PLLCR3;                      /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1550 */
13740   __I  uint32_t DX8SL5PLLCR4;                      /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1554 */
13741   __I  uint32_t DX8SL5PLLCR5;                      /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1558 */
13742   __I  uint32_t DX8SL5DQSCTL;                      /**< DATX8 0-1 DQS Control Register, offset: 0x155C */
13743   __I  uint32_t DX8SL5TRNCTL;                      /**< DATX8 0-1 Training Control Register, offset: 0x1560 */
13744   __I  uint32_t DX8SL5DDLCTL;                      /**< DATX8 0-1 DDL Control Register, offset: 0x1564 */
13745   __I  uint32_t DX8SL5DXCTL1;                      /**< DATX8 0-1 DX Control Register 1, offset: 0x1568 */
13746   __I  uint32_t DX8SL5DXCTL2;                      /**< DATX8 0-1 DX Control Register 2, offset: 0x156C */
13747   __I  uint32_t DX8SL5IOCR;                        /**< DATX8 0-1 I/O Configuration Register, offset: 0x1570 */
13748   __I  uint32_t DX4SL5IOCR;                        /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1574 */
13749        uint8_t RESERVED_108[8];
13750   __I  uint32_t DX8SL6OSC;                         /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1580 */
13751   __I  uint32_t DX8SL6PLLCR0;                      /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1584 */
13752   __I  uint32_t DX8SL6PLLCR1;                      /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1588 */
13753   __I  uint32_t DX8SL6PLLCR2;                      /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x158C */
13754   __I  uint32_t DX8SL6PLLCR3;                      /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1590 */
13755   __I  uint32_t DX8SL6PLLCR4;                      /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1594 */
13756   __I  uint32_t DX8SL6PLLCR5;                      /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1598 */
13757   __I  uint32_t DX8SL6DQSCTL;                      /**< DATX8 0-1 DQS Control Register, offset: 0x159C */
13758   __I  uint32_t DX8SL6TRNCTL;                      /**< DATX8 0-1 Training Control Register, offset: 0x15A0 */
13759   __I  uint32_t DX8SL6DDLCTL;                      /**< DATX8 0-1 DDL Control Register, offset: 0x15A4 */
13760   __I  uint32_t DX8SL6DXCTL1;                      /**< DATX8 0-1 DX Control Register 1, offset: 0x15A8 */
13761   __I  uint32_t DX8SL6DXCTL2;                      /**< DATX8 0-1 DX Control Register 2, offset: 0x15AC */
13762   __I  uint32_t DX8SL6IOCR;                        /**< DATX8 0-1 I/O Configuration Register, offset: 0x15B0 */
13763   __I  uint32_t DX4SL6IOCR;                        /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x15B4 */
13764        uint8_t RESERVED_109[8];
13765   __I  uint32_t DX8SL7OSC;                         /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x15C0 */
13766   __I  uint32_t DX8SL7PLLCR0;                      /**< DAXT8 0-1 PLL Control Register 0, offset: 0x15C4 */
13767   __I  uint32_t DX8SL7PLLCR1;                      /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x15C8 */
13768   __I  uint32_t DX8SL7PLLCR2;                      /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x15CC */
13769   __I  uint32_t DX8SL7PLLCR3;                      /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x15D0 */
13770   __I  uint32_t DX8SL7PLLCR4;                      /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x15D4 */
13771   __I  uint32_t DX8SL7PLLCR5;                      /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x15D8 */
13772   __I  uint32_t DX8SL7DQSCTL;                      /**< DATX8 0-1 DQS Control Register, offset: 0x15DC */
13773   __I  uint32_t DX8SL7TRNCTL;                      /**< DATX8 0-1 Training Control Register, offset: 0x15E0 */
13774   __I  uint32_t DX8SL7DDLCTL;                      /**< DATX8 0-1 DDL Control Register, offset: 0x15E4 */
13775   __I  uint32_t DX8SL7DXCTL1;                      /**< DATX8 0-1 DX Control Register 1, offset: 0x15E8 */
13776   __I  uint32_t DX8SL7DXCTL2;                      /**< DATX8 0-1 DX Control Register 2, offset: 0x15EC */
13777   __I  uint32_t DX8SL7IOCR;                        /**< DATX8 0-1 I/O Configuration Register, offset: 0x15F0 */
13778   __I  uint32_t DX4SL7IOCR;                        /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x15F4 */
13779        uint8_t RESERVED_110[8];
13780   __I  uint32_t DX8SL8OSC;                         /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1600 */
13781   __I  uint32_t DX8SL8PLLCR0;                      /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1604 */
13782   __I  uint32_t DX8SL8PLLCR1;                      /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1608 */
13783   __I  uint32_t DX8SL8PLLCR2;                      /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x160C */
13784   __I  uint32_t DX8SL8PLLCR3;                      /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1610 */
13785   __I  uint32_t DX8SL8PLLCR4;                      /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1614 */
13786   __I  uint32_t DX8SL8PLLCR5;                      /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1618 */
13787   __I  uint32_t DX8SL8DQSCTL;                      /**< DATX8 0-1 DQS Control Register, offset: 0x161C */
13788   __I  uint32_t DX8SL8TRNCTL;                      /**< DATX8 0-1 Training Control Register, offset: 0x1620 */
13789   __I  uint32_t DX8SL8DDLCTL;                      /**< DATX8 0-1 DDL Control Register, offset: 0x1624 */
13790   __I  uint32_t DX8SL8DXCTL1;                      /**< DATX8 0-1 DX Control Register 1, offset: 0x1628 */
13791   __I  uint32_t DX8SL8DXCTL2;                      /**< DATX8 0-1 DX Control Register 2, offset: 0x162C */
13792   __I  uint32_t DX8SL8IOCR;                        /**< DATX8 0-1 I/O Configuration Register, offset: 0x1630 */
13793   __I  uint32_t DX4SL8IOCR;                        /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1634 */
13794        uint8_t RESERVED_111[392];
13795   __O  uint32_t DX8SLBOSC;                         /**< DATX8 0-8 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x17C0 */
13796   __O  uint32_t DX8SLBPLLCR0;                      /**< DAXT8 0-8 PLL Control Register 0, offset: 0x17C4 */
13797   __O  uint32_t DX8SLBPLLCR1;                      /**< DAXT8 0-8 PLL Control Register 1 (Type B PLL Only), offset: 0x17C8 */
13798   __O  uint32_t DX8SLBPLLCR2;                      /**< DAXT8 0-8 PLL Control Register 2 (Type B PLL Only), offset: 0x17CC */
13799   __O  uint32_t DX8SLBPLLCR3;                      /**< DAXT8 0-8 PLL Control Register 3 (Type B PLL Only), offset: 0x17D0 */
13800   __O  uint32_t DX8SLBPLLCR4;                      /**< DAXT8 0-8 PLL Control Register 4 (Type B PLL Only), offset: 0x17D4 */
13801   __O  uint32_t DX8SLBPLLCR5;                      /**< DAXT8 0-8 PLL Control Register 5 (Type B PLL Only), offset: 0x17D8 */
13802   __O  uint32_t DX8SLBDQSCTL;                      /**< DATX8 0-8 DQS Control Register, offset: 0x17DC */
13803   __O  uint32_t DX8SLBTRNCTL;                      /**< DATX8 0-8 Training Control Register, offset: 0x17E0 */
13804   __O  uint32_t DX8SLBDDLCTL;                      /**< DATX8 0-8 DDL Control Register, offset: 0x17E4 */
13805   __O  uint32_t DX8SLBDXCTL1;                      /**< DATX8 0-8 DX Control Register 1, offset: 0x17E8 */
13806   __O  uint32_t DX8SLBDXCTL2;                      /**< DATX8 0-8 DX Control Register 2, offset: 0x17EC */
13807   __O  uint32_t DX8SLBIOCR;                        /**< DATX8 0-8 I/O Configuration Register, offset: 0x17F0 */
13808   __O  uint32_t DX4SLBIOCR;                        /**< DATX4 0-8 I/O Configuration Register, offset: 0x17F4 */
13809 } DDRPHY_Type;
13810 
13811 /* ----------------------------------------------------------------------------
13812    -- DDRPHY Register Masks
13813    ---------------------------------------------------------------------------- */
13814 
13815 /*!
13816  * @addtogroup DDRPHY_Register_Masks DDRPHY Register Masks
13817  * @{
13818  */
13819 
13820 /*! @name RIDR - Revision Identification Register */
13821 /*! @{ */
13822 #define DDRPHY_RIDR_PUBMNR_MASK                  (0xFU)
13823 #define DDRPHY_RIDR_PUBMNR_SHIFT                 (0U)
13824 /*! PUBMNR - PUB Minor Revision
13825  */
13826 #define DDRPHY_RIDR_PUBMNR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PUBMNR_SHIFT)) & DDRPHY_RIDR_PUBMNR_MASK)
13827 #define DDRPHY_RIDR_PUBMDR_MASK                  (0xF0U)
13828 #define DDRPHY_RIDR_PUBMDR_SHIFT                 (4U)
13829 /*! PUBMDR - PUB Moderate Revision
13830  */
13831 #define DDRPHY_RIDR_PUBMDR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PUBMDR_SHIFT)) & DDRPHY_RIDR_PUBMDR_MASK)
13832 #define DDRPHY_RIDR_PUBMJR_MASK                  (0xF00U)
13833 #define DDRPHY_RIDR_PUBMJR_SHIFT                 (8U)
13834 /*! PUBMJR - PUB Major Revision
13835  */
13836 #define DDRPHY_RIDR_PUBMJR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PUBMJR_SHIFT)) & DDRPHY_RIDR_PUBMJR_MASK)
13837 #define DDRPHY_RIDR_PHYMNR_MASK                  (0xF000U)
13838 #define DDRPHY_RIDR_PHYMNR_SHIFT                 (12U)
13839 /*! PHYMNR - PHY Minor Revision
13840  */
13841 #define DDRPHY_RIDR_PHYMNR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PHYMNR_SHIFT)) & DDRPHY_RIDR_PHYMNR_MASK)
13842 #define DDRPHY_RIDR_PHYMDR_MASK                  (0xF0000U)
13843 #define DDRPHY_RIDR_PHYMDR_SHIFT                 (16U)
13844 /*! PHYMDR - PHY Moderate Revision
13845  */
13846 #define DDRPHY_RIDR_PHYMDR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PHYMDR_SHIFT)) & DDRPHY_RIDR_PHYMDR_MASK)
13847 #define DDRPHY_RIDR_PHYMJR_MASK                  (0xF00000U)
13848 #define DDRPHY_RIDR_PHYMJR_SHIFT                 (20U)
13849 /*! PHYMJR - PHY Major Revision
13850  */
13851 #define DDRPHY_RIDR_PHYMJR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PHYMJR_SHIFT)) & DDRPHY_RIDR_PHYMJR_MASK)
13852 #define DDRPHY_RIDR_UDRID_MASK                   (0xFF000000U)
13853 #define DDRPHY_RIDR_UDRID_SHIFT                  (24U)
13854 /*! UDRID - User-Defined Revision ID
13855  */
13856 #define DDRPHY_RIDR_UDRID(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_UDRID_SHIFT)) & DDRPHY_RIDR_UDRID_MASK)
13857 /*! @} */
13858 
13859 /*! @name PIR - PHY Initialization Register */
13860 /*! @{ */
13861 #define DDRPHY_PIR_INIT_MASK                     (0x1U)
13862 #define DDRPHY_PIR_INIT_SHIFT                    (0U)
13863 /*! INIT - Initialization Trigger
13864  */
13865 #define DDRPHY_PIR_INIT(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_INIT_SHIFT)) & DDRPHY_PIR_INIT_MASK)
13866 #define DDRPHY_PIR_ZCAL_MASK                     (0x2U)
13867 #define DDRPHY_PIR_ZCAL_SHIFT                    (1U)
13868 /*! ZCAL - Impedance Calibration
13869  */
13870 #define DDRPHY_PIR_ZCAL(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_ZCAL_SHIFT)) & DDRPHY_PIR_ZCAL_MASK)
13871 #define DDRPHY_PIR_CA_MASK                       (0x4U)
13872 #define DDRPHY_PIR_CA_SHIFT                      (2U)
13873 /*! CA - CA Training
13874  */
13875 #define DDRPHY_PIR_CA(x)                         (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_CA_SHIFT)) & DDRPHY_PIR_CA_MASK)
13876 #define DDRPHY_PIR_RESERVED_3_MASK               (0x8U)
13877 #define DDRPHY_PIR_RESERVED_3_SHIFT              (3U)
13878 /*! RESERVED_3 - Reserved. Return zeroes on reads.
13879  */
13880 #define DDRPHY_PIR_RESERVED_3(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RESERVED_3_SHIFT)) & DDRPHY_PIR_RESERVED_3_MASK)
13881 #define DDRPHY_PIR_PLLINIT_MASK                  (0x10U)
13882 #define DDRPHY_PIR_PLLINIT_SHIFT                 (4U)
13883 /*! PLLINIT - PLL Initialiazation
13884  */
13885 #define DDRPHY_PIR_PLLINIT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_PLLINIT_SHIFT)) & DDRPHY_PIR_PLLINIT_MASK)
13886 #define DDRPHY_PIR_DCAL_MASK                     (0x20U)
13887 #define DDRPHY_PIR_DCAL_SHIFT                    (5U)
13888 /*! DCAL - Digital Delay Line (DDL) Calibration
13889  */
13890 #define DDRPHY_PIR_DCAL(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DCAL_SHIFT)) & DDRPHY_PIR_DCAL_MASK)
13891 #define DDRPHY_PIR_PHYRST_MASK                   (0x40U)
13892 #define DDRPHY_PIR_PHYRST_SHIFT                  (6U)
13893 /*! PHYRST - PHY Reset
13894  */
13895 #define DDRPHY_PIR_PHYRST(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_PHYRST_SHIFT)) & DDRPHY_PIR_PHYRST_MASK)
13896 #define DDRPHY_PIR_DRAMRST_MASK                  (0x80U)
13897 #define DDRPHY_PIR_DRAMRST_SHIFT                 (7U)
13898 /*! DRAMRST - DRAM Reset (DDR3/DDR4/LPDDR4 Only)
13899  */
13900 #define DDRPHY_PIR_DRAMRST(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DRAMRST_SHIFT)) & DDRPHY_PIR_DRAMRST_MASK)
13901 #define DDRPHY_PIR_DRAMINIT_MASK                 (0x100U)
13902 #define DDRPHY_PIR_DRAMINIT_SHIFT                (8U)
13903 /*! DRAMINIT - DRAM Initialization
13904  */
13905 #define DDRPHY_PIR_DRAMINIT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DRAMINIT_SHIFT)) & DDRPHY_PIR_DRAMINIT_MASK)
13906 #define DDRPHY_PIR_WL_MASK                       (0x200U)
13907 #define DDRPHY_PIR_WL_SHIFT                      (9U)
13908 /*! WL - Write Leveling
13909  */
13910 #define DDRPHY_PIR_WL(x)                         (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WL_SHIFT)) & DDRPHY_PIR_WL_MASK)
13911 #define DDRPHY_PIR_QSGATE_MASK                   (0x400U)
13912 #define DDRPHY_PIR_QSGATE_SHIFT                  (10U)
13913 /*! QSGATE - Read DQS Gate Training
13914  */
13915 #define DDRPHY_PIR_QSGATE(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_QSGATE_SHIFT)) & DDRPHY_PIR_QSGATE_MASK)
13916 #define DDRPHY_PIR_WLADJ_MASK                    (0x800U)
13917 #define DDRPHY_PIR_WLADJ_SHIFT                   (11U)
13918 /*! WLADJ - Write Leveling Adjust
13919  */
13920 #define DDRPHY_PIR_WLADJ(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WLADJ_SHIFT)) & DDRPHY_PIR_WLADJ_MASK)
13921 #define DDRPHY_PIR_RDDSKW_MASK                   (0x1000U)
13922 #define DDRPHY_PIR_RDDSKW_SHIFT                  (12U)
13923 /*! RDDSKW - Read Data Bit Deskew
13924  */
13925 #define DDRPHY_PIR_RDDSKW(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RDDSKW_SHIFT)) & DDRPHY_PIR_RDDSKW_MASK)
13926 #define DDRPHY_PIR_WRDSKW_MASK                   (0x2000U)
13927 #define DDRPHY_PIR_WRDSKW_SHIFT                  (13U)
13928 /*! WRDSKW - Write Data Bit Deskew
13929  */
13930 #define DDRPHY_PIR_WRDSKW(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WRDSKW_SHIFT)) & DDRPHY_PIR_WRDSKW_MASK)
13931 #define DDRPHY_PIR_RDEYE_MASK                    (0x4000U)
13932 #define DDRPHY_PIR_RDEYE_SHIFT                   (14U)
13933 /*! RDEYE - Read Data Eye Training
13934  */
13935 #define DDRPHY_PIR_RDEYE(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RDEYE_SHIFT)) & DDRPHY_PIR_RDEYE_MASK)
13936 #define DDRPHY_PIR_WREYE_MASK                    (0x8000U)
13937 #define DDRPHY_PIR_WREYE_SHIFT                   (15U)
13938 /*! WREYE - Write Data Eye Training
13939  */
13940 #define DDRPHY_PIR_WREYE(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WREYE_SHIFT)) & DDRPHY_PIR_WREYE_MASK)
13941 #define DDRPHY_PIR_SRD_MASK                      (0x10000U)
13942 #define DDRPHY_PIR_SRD_SHIFT                     (16U)
13943 /*! SRD - Static Read Training
13944  */
13945 #define DDRPHY_PIR_SRD(x)                        (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_SRD_SHIFT)) & DDRPHY_PIR_SRD_MASK)
13946 #define DDRPHY_PIR_VREF_MASK                     (0x20000U)
13947 #define DDRPHY_PIR_VREF_SHIFT                    (17U)
13948 /*! VREF - VREF Training
13949  */
13950 #define DDRPHY_PIR_VREF(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_VREF_SHIFT)) & DDRPHY_PIR_VREF_MASK)
13951 #define DDRPHY_PIR_CTLDINIT_MASK                 (0x40000U)
13952 #define DDRPHY_PIR_CTLDINIT_SHIFT                (18U)
13953 /*! CTLDINIT - Controller DRAM Initialization
13954  */
13955 #define DDRPHY_PIR_CTLDINIT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_CTLDINIT_SHIFT)) & DDRPHY_PIR_CTLDINIT_MASK)
13956 #define DDRPHY_PIR_RDIMMINIT_MASK                (0x80000U)
13957 #define DDRPHY_PIR_RDIMMINIT_SHIFT               (19U)
13958 /*! RDIMMINIT - RDIMM Initialization
13959  */
13960 #define DDRPHY_PIR_RDIMMINIT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RDIMMINIT_SHIFT)) & DDRPHY_PIR_RDIMMINIT_MASK)
13961 #define DDRPHY_PIR_DQS2DQ_MASK                   (0x100000U)
13962 #define DDRPHY_PIR_DQS2DQ_SHIFT                  (20U)
13963 /*! DQS2DQ - Write DQS2DQ Training
13964  */
13965 #define DDRPHY_PIR_DQS2DQ(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DQS2DQ_SHIFT)) & DDRPHY_PIR_DQS2DQ_MASK)
13966 #define DDRPHY_PIR_RESERVED_28_21_MASK           (0x1FE00000U)
13967 #define DDRPHY_PIR_RESERVED_28_21_SHIFT          (21U)
13968 /*! RESERVED_28_21 - Reserved. Return zeroes on reads.
13969  */
13970 #define DDRPHY_PIR_RESERVED_28_21(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RESERVED_28_21_SHIFT)) & DDRPHY_PIR_RESERVED_28_21_MASK)
13971 #define DDRPHY_PIR_DCALPSE_MASK                  (0x20000000U)
13972 #define DDRPHY_PIR_DCALPSE_SHIFT                 (29U)
13973 /*! DCALPSE - Digital Delay Line (DDL) Calibration Pause
13974  */
13975 #define DDRPHY_PIR_DCALPSE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DCALPSE_SHIFT)) & DDRPHY_PIR_DCALPSE_MASK)
13976 #define DDRPHY_PIR_ZCALBYP_MASK                  (0x40000000U)
13977 #define DDRPHY_PIR_ZCALBYP_SHIFT                 (30U)
13978 /*! ZCALBYP - Impedance Calibration Bypass
13979  */
13980 #define DDRPHY_PIR_ZCALBYP(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_ZCALBYP_SHIFT)) & DDRPHY_PIR_ZCALBYP_MASK)
13981 #define DDRPHY_PIR_RESERVED_31_MASK              (0x80000000U)
13982 #define DDRPHY_PIR_RESERVED_31_SHIFT             (31U)
13983 /*! RESERVED_31 - Reserved. Return zeroes on reads.
13984  */
13985 #define DDRPHY_PIR_RESERVED_31(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RESERVED_31_SHIFT)) & DDRPHY_PIR_RESERVED_31_MASK)
13986 /*! @} */
13987 
13988 /*! @name PGCR0 - PHY General Configuration Register 0 */
13989 /*! @{ */
13990 #define DDRPHY_PGCR0_RESERVED_7_0_MASK           (0xFFU)
13991 #define DDRPHY_PGCR0_RESERVED_7_0_SHIFT          (0U)
13992 /*! RESERVED_7_0 - Reserved. Returns zeroes on reads.
13993  */
13994 #define DDRPHY_PGCR0_RESERVED_7_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_7_0_SHIFT)) & DDRPHY_PGCR0_RESERVED_7_0_MASK)
13995 #define DDRPHY_PGCR0_OSCEN_MASK                  (0x100U)
13996 #define DDRPHY_PGCR0_OSCEN_SHIFT                 (8U)
13997 /*! OSCEN - Oscillator Enable
13998  */
13999 #define DDRPHY_PGCR0_OSCEN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_OSCEN_SHIFT)) & DDRPHY_PGCR0_OSCEN_MASK)
14000 #define DDRPHY_PGCR0_OSCDIV_MASK                 (0x1E00U)
14001 #define DDRPHY_PGCR0_OSCDIV_SHIFT                (9U)
14002 /*! OSCDIV - Oscillator Mode Division
14003  */
14004 #define DDRPHY_PGCR0_OSCDIV(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_OSCDIV_SHIFT)) & DDRPHY_PGCR0_OSCDIV_MASK)
14005 #define DDRPHY_PGCR0_RESERVED_13_MASK            (0x2000U)
14006 #define DDRPHY_PGCR0_RESERVED_13_SHIFT           (13U)
14007 /*! RESERVED_13 - Reserved. Returns zeroes on reads.
14008  */
14009 #define DDRPHY_PGCR0_RESERVED_13(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_13_SHIFT)) & DDRPHY_PGCR0_RESERVED_13_MASK)
14010 #define DDRPHY_PGCR0_DTOSEL_MASK                 (0x7C000U)
14011 #define DDRPHY_PGCR0_DTOSEL_SHIFT                (14U)
14012 /*! DTOSEL - Digital Test Output Select
14013  */
14014 #define DDRPHY_PGCR0_DTOSEL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_DTOSEL_SHIFT)) & DDRPHY_PGCR0_DTOSEL_MASK)
14015 #define DDRPHY_PGCR0_RESERVED_23_19_MASK         (0xF80000U)
14016 #define DDRPHY_PGCR0_RESERVED_23_19_SHIFT        (19U)
14017 /*! RESERVED_23_19 - Reserved. Returns zeroes on reads.
14018  */
14019 #define DDRPHY_PGCR0_RESERVED_23_19(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_23_19_SHIFT)) & DDRPHY_PGCR0_RESERVED_23_19_MASK)
14020 #define DDRPHY_PGCR0_OSCACDL_MASK                (0x3000000U)
14021 #define DDRPHY_PGCR0_OSCACDL_SHIFT               (24U)
14022 /*! OSCACDL - Oscillator Mode Address/Command Delay Line Select
14023  */
14024 #define DDRPHY_PGCR0_OSCACDL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_OSCACDL_SHIFT)) & DDRPHY_PGCR0_OSCACDL_MASK)
14025 #define DDRPHY_PGCR0_PHYFRST_MASK                (0x4000000U)
14026 #define DDRPHY_PGCR0_PHYFRST_SHIFT               (26U)
14027 /*! PHYFRST - PHY FIFO Reset
14028  */
14029 #define DDRPHY_PGCR0_PHYFRST(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_PHYFRST_SHIFT)) & DDRPHY_PGCR0_PHYFRST_MASK)
14030 #define DDRPHY_PGCR0_RESERVED_30_27_MASK         (0x78000000U)
14031 #define DDRPHY_PGCR0_RESERVED_30_27_SHIFT        (27U)
14032 /*! RESERVED_30_27 - Reserved. Returns zeroes on reads.
14033  */
14034 #define DDRPHY_PGCR0_RESERVED_30_27(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_30_27_SHIFT)) & DDRPHY_PGCR0_RESERVED_30_27_MASK)
14035 #define DDRPHY_PGCR0_ADCP_MASK                   (0x80000000U)
14036 #define DDRPHY_PGCR0_ADCP_SHIFT                  (31U)
14037 /*! ADCP - Address Copy
14038  */
14039 #define DDRPHY_PGCR0_ADCP(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_ADCP_SHIFT)) & DDRPHY_PGCR0_ADCP_MASK)
14040 /*! @} */
14041 
14042 /*! @name PGCR1 - PHY General Configuration Register 1 */
14043 /*! @{ */
14044 #define DDRPHY_PGCR1_DTOMODE_MASK                (0x1U)
14045 #define DDRPHY_PGCR1_DTOMODE_SHIFT               (0U)
14046 /*! DTOMODE - Digital Test Output Mode
14047  */
14048 #define DDRPHY_PGCR1_DTOMODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DTOMODE_SHIFT)) & DDRPHY_PGCR1_DTOMODE_MASK)
14049 #define DDRPHY_PGCR1_WLMODE_MASK                 (0x2U)
14050 #define DDRPHY_PGCR1_WLMODE_SHIFT                (1U)
14051 /*! WLMODE - Write Leveling (Software) Mode
14052  */
14053 #define DDRPHY_PGCR1_WLMODE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_WLMODE_SHIFT)) & DDRPHY_PGCR1_WLMODE_MASK)
14054 #define DDRPHY_PGCR1_WLSTEP_MASK                 (0x4U)
14055 #define DDRPHY_PGCR1_WLSTEP_SHIFT                (2U)
14056 /*! WLSTEP - Write Leveling Step
14057  */
14058 #define DDRPHY_PGCR1_WLSTEP(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_WLSTEP_SHIFT)) & DDRPHY_PGCR1_WLSTEP_MASK)
14059 #define DDRPHY_PGCR1_AC_CKOUT_DIFF_MASK          (0x8U)
14060 #define DDRPHY_PGCR1_AC_CKOUT_DIFF_SHIFT         (3U)
14061 /*! AC_CKOUT_DIFF - Selects PDIFF cell for CK generation
14062  */
14063 #define DDRPHY_PGCR1_AC_CKOUT_DIFF(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_AC_CKOUT_DIFF_SHIFT)) & DDRPHY_PGCR1_AC_CKOUT_DIFF_MASK)
14064 #define DDRPHY_PGCR1_DX_DQSOUT_DIFF_MASK         (0x10U)
14065 #define DDRPHY_PGCR1_DX_DQSOUT_DIFF_SHIFT        (4U)
14066 /*! DX_DQSOUT_DIFF - Selects PDIFF cell for DQS generation
14067  */
14068 #define DDRPHY_PGCR1_DX_DQSOUT_DIFF(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DX_DQSOUT_DIFF_SHIFT)) & DDRPHY_PGCR1_DX_DQSOUT_DIFF_MASK)
14069 #define DDRPHY_PGCR1_CAST_MASK                   (0x20U)
14070 #define DDRPHY_PGCR1_CAST_SHIFT                  (5U)
14071 /*! CAST - CA Software Training.
14072  */
14073 #define DDRPHY_PGCR1_CAST(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_CAST_SHIFT)) & DDRPHY_PGCR1_CAST_MASK)
14074 #define DDRPHY_PGCR1_PUBMODE_MASK                (0x40U)
14075 #define DDRPHY_PGCR1_PUBMODE_SHIFT               (6U)
14076 /*! PUBMODE - Enables, if set, the PUB to control the interface to the PHY and SDRAM.
14077  */
14078 #define DDRPHY_PGCR1_PUBMODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_PUBMODE_SHIFT)) & DDRPHY_PGCR1_PUBMODE_MASK)
14079 #define DDRPHY_PGCR1_RESERVED_8_7_MASK           (0x180U)
14080 #define DDRPHY_PGCR1_RESERVED_8_7_SHIFT          (7U)
14081 /*! RESERVED_8_7 - Reserved. Returns zeroes on reads.
14082  */
14083 #define DDRPHY_PGCR1_RESERVED_8_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_RESERVED_8_7_SHIFT)) & DDRPHY_PGCR1_RESERVED_8_7_MASK)
14084 #define DDRPHY_PGCR1_MDLEN_MASK                  (0x200U)
14085 #define DDRPHY_PGCR1_MDLEN_SHIFT                 (9U)
14086 /*! MDLEN - Master Delay Line Enable
14087  */
14088 #define DDRPHY_PGCR1_MDLEN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_MDLEN_SHIFT)) & DDRPHY_PGCR1_MDLEN_MASK)
14089 #define DDRPHY_PGCR1_LPFEN_MASK                  (0x400U)
14090 #define DDRPHY_PGCR1_LPFEN_SHIFT                 (10U)
14091 /*! LPFEN - Low-Pass Filter Enable
14092  */
14093 #define DDRPHY_PGCR1_LPFEN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LPFEN_SHIFT)) & DDRPHY_PGCR1_LPFEN_MASK)
14094 #define DDRPHY_PGCR1_LPFDEPTH_MASK               (0x1800U)
14095 #define DDRPHY_PGCR1_LPFDEPTH_SHIFT              (11U)
14096 /*! LPFDEPTH - Low-Pass Filter Depth
14097  */
14098 #define DDRPHY_PGCR1_LPFDEPTH(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LPFDEPTH_SHIFT)) & DDRPHY_PGCR1_LPFDEPTH_MASK)
14099 #define DDRPHY_PGCR1_FDEPTH_MASK                 (0x6000U)
14100 #define DDRPHY_PGCR1_FDEPTH_SHIFT                (13U)
14101 /*! FDEPTH - Filter Depth
14102  */
14103 #define DDRPHY_PGCR1_FDEPTH(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_FDEPTH_SHIFT)) & DDRPHY_PGCR1_FDEPTH_MASK)
14104 #define DDRPHY_PGCR1_DUALCHN_MASK                (0x8000U)
14105 #define DDRPHY_PGCR1_DUALCHN_SHIFT               (15U)
14106 /*! DUALCHN - Dual Channel Configuration
14107  */
14108 #define DDRPHY_PGCR1_DUALCHN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DUALCHN_SHIFT)) & DDRPHY_PGCR1_DUALCHN_MASK)
14109 #define DDRPHY_PGCR1_ACPDDC_MASK                 (0x10000U)
14110 #define DDRPHY_PGCR1_ACPDDC_SHIFT                (16U)
14111 /*! ACPDDC - AC Power-Down with Dual Channels
14112  */
14113 #define DDRPHY_PGCR1_ACPDDC(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_ACPDDC_SHIFT)) & DDRPHY_PGCR1_ACPDDC_MASK)
14114 #define DDRPHY_PGCR1_DISDIC_MASK                 (0x20000U)
14115 #define DDRPHY_PGCR1_DISDIC_SHIFT                (17U)
14116 /*! DISDIC - Enable/Disable control for dfi_init_complete.
14117  */
14118 #define DDRPHY_PGCR1_DISDIC(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DISDIC_SHIFT)) & DDRPHY_PGCR1_DISDIC_MASK)
14119 #define DDRPHY_PGCR1_UPDMSTRC0_MASK              (0x40000U)
14120 #define DDRPHY_PGCR1_UPDMSTRC0_SHIFT             (18U)
14121 /*! UPDMSTRC0 - DFI Update Master Channel 0
14122  */
14123 #define DDRPHY_PGCR1_UPDMSTRC0(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_UPDMSTRC0_SHIFT)) & DDRPHY_PGCR1_UPDMSTRC0_MASK)
14124 #define DDRPHY_PGCR1_RESERVED_19_MASK            (0x80000U)
14125 #define DDRPHY_PGCR1_RESERVED_19_SHIFT           (19U)
14126 /*! RESERVED_19 - Reserved. Returns zeroes on reads.
14127  */
14128 #define DDRPHY_PGCR1_RESERVED_19(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_RESERVED_19_SHIFT)) & DDRPHY_PGCR1_RESERVED_19_MASK)
14129 #define DDRPHY_PGCR1_LRDIMMST_MASK               (0x100000U)
14130 #define DDRPHY_PGCR1_LRDIMMST_SHIFT              (20U)
14131 /*! LRDIMMST - LRDIMM Software Training
14132  */
14133 #define DDRPHY_PGCR1_LRDIMMST(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LRDIMMST_SHIFT)) & DDRPHY_PGCR1_LRDIMMST_MASK)
14134 #define DDRPHY_PGCR1_ACVLDDLY_MASK               (0xE00000U)
14135 #define DDRPHY_PGCR1_ACVLDDLY_SHIFT              (21U)
14136 /*! ACVLDDLY - AC Loopback Valid Delay
14137  */
14138 #define DDRPHY_PGCR1_ACVLDDLY(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_ACVLDDLY_SHIFT)) & DDRPHY_PGCR1_ACVLDDLY_MASK)
14139 #define DDRPHY_PGCR1_ACVLDTRN_MASK               (0x1000000U)
14140 #define DDRPHY_PGCR1_ACVLDTRN_SHIFT              (24U)
14141 /*! ACVLDTRN - AC Loopback Valid Train
14142  */
14143 #define DDRPHY_PGCR1_ACVLDTRN(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_ACVLDTRN_SHIFT)) & DDRPHY_PGCR1_ACVLDTRN_MASK)
14144 #define DDRPHY_PGCR1_PHYHRST_MASK                (0x2000000U)
14145 #define DDRPHY_PGCR1_PHYHRST_SHIFT               (25U)
14146 /*! PHYHRST - PHY High-Speed Reset
14147  */
14148 #define DDRPHY_PGCR1_PHYHRST(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_PHYHRST_SHIFT)) & DDRPHY_PGCR1_PHYHRST_MASK)
14149 #define DDRPHY_PGCR1_DLTMODE_MASK                (0x4000000U)
14150 #define DDRPHY_PGCR1_DLTMODE_SHIFT               (26U)
14151 /*! DLTMODE - Delay Line Test Mode
14152  */
14153 #define DDRPHY_PGCR1_DLTMODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DLTMODE_SHIFT)) & DDRPHY_PGCR1_DLTMODE_MASK)
14154 #define DDRPHY_PGCR1_DLTST_MASK                  (0x8000000U)
14155 #define DDRPHY_PGCR1_DLTST_SHIFT                 (27U)
14156 /*! DLTST - Delay Line Test Start
14157  */
14158 #define DDRPHY_PGCR1_DLTST(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DLTST_SHIFT)) & DDRPHY_PGCR1_DLTST_MASK)
14159 #define DDRPHY_PGCR1_LBGSDQS_MASK                (0x10000000U)
14160 #define DDRPHY_PGCR1_LBGSDQS_SHIFT               (28U)
14161 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value (equivalent to one CK period)
14162  */
14163 #define DDRPHY_PGCR1_LBGSDQS(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LBGSDQS_SHIFT)) & DDRPHY_PGCR1_LBGSDQS_MASK)
14164 #define DDRPHY_PGCR1_RESERVED_30_29_MASK         (0x60000000U)
14165 #define DDRPHY_PGCR1_RESERVED_30_29_SHIFT        (29U)
14166 /*! RESERVED_30_29 - Reserved. Returns zeroes on reads.
14167  */
14168 #define DDRPHY_PGCR1_RESERVED_30_29(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_RESERVED_30_29_SHIFT)) & DDRPHY_PGCR1_RESERVED_30_29_MASK)
14169 #define DDRPHY_PGCR1_LBMODE_MASK                 (0x80000000U)
14170 #define DDRPHY_PGCR1_LBMODE_SHIFT                (31U)
14171 /*! LBMODE - Loopback Mode
14172  */
14173 #define DDRPHY_PGCR1_LBMODE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LBMODE_SHIFT)) & DDRPHY_PGCR1_LBMODE_MASK)
14174 /*! @} */
14175 
14176 /*! @name PGCR2 - PHY General Configuration Register 2 */
14177 /*! @{ */
14178 #define DDRPHY_PGCR2_tREFPRD_MASK                (0x3FFFFU)
14179 #define DDRPHY_PGCR2_tREFPRD_SHIFT               (0U)
14180 /*! tREFPRD - Refresh Period
14181  */
14182 #define DDRPHY_PGCR2_tREFPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_tREFPRD_SHIFT)) & DDRPHY_PGCR2_tREFPRD_MASK)
14183 #define DDRPHY_PGCR2_PLLFSMBYP_MASK              (0x40000U)
14184 #define DDRPHY_PGCR2_PLLFSMBYP_SHIFT             (18U)
14185 /*! PLLFSMBYP - PLL FSM Bypass
14186  */
14187 #define DDRPHY_PGCR2_PLLFSMBYP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_PLLFSMBYP_SHIFT)) & DDRPHY_PGCR2_PLLFSMBYP_MASK)
14188 #define DDRPHY_PGCR2_INITFSMBYP_MASK             (0x80000U)
14189 #define DDRPHY_PGCR2_INITFSMBYP_SHIFT            (19U)
14190 /*! INITFSMBYP - Initialization Bypass
14191  */
14192 #define DDRPHY_PGCR2_INITFSMBYP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_INITFSMBYP_SHIFT)) & DDRPHY_PGCR2_INITFSMBYP_MASK)
14193 #define DDRPHY_PGCR2_DTPMXTMR_MASK               (0xFF00000U)
14194 #define DDRPHY_PGCR2_DTPMXTMR_SHIFT              (20U)
14195 /*! DTPMXTMR - Data Training PUB Mode Exit Timer
14196  */
14197 #define DDRPHY_PGCR2_DTPMXTMR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_DTPMXTMR_SHIFT)) & DDRPHY_PGCR2_DTPMXTMR_MASK)
14198 #define DDRPHY_PGCR2_ICPC_MASK                   (0x10000000U)
14199 #define DDRPHY_PGCR2_ICPC_SHIFT                  (28U)
14200 /*! ICPC - Initialization Complete Pin Configuration
14201  */
14202 #define DDRPHY_PGCR2_ICPC(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_ICPC_SHIFT)) & DDRPHY_PGCR2_ICPC_MASK)
14203 #define DDRPHY_PGCR2_CLRPERR_MASK                (0x20000000U)
14204 #define DDRPHY_PGCR2_CLRPERR_SHIFT               (29U)
14205 /*! CLRPERR - Clear Parity Error
14206  */
14207 #define DDRPHY_PGCR2_CLRPERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_CLRPERR_SHIFT)) & DDRPHY_PGCR2_CLRPERR_MASK)
14208 #define DDRPHY_PGCR2_CLRZCAL_MASK                (0x40000000U)
14209 #define DDRPHY_PGCR2_CLRZCAL_SHIFT               (30U)
14210 /*! CLRZCAL - Clear Impedance Calibration
14211  */
14212 #define DDRPHY_PGCR2_CLRZCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_CLRZCAL_SHIFT)) & DDRPHY_PGCR2_CLRZCAL_MASK)
14213 #define DDRPHY_PGCR2_CLRTSTAT_MASK               (0x80000000U)
14214 #define DDRPHY_PGCR2_CLRTSTAT_SHIFT              (31U)
14215 /*! CLRTSTAT - Clear Training Status Registers
14216  */
14217 #define DDRPHY_PGCR2_CLRTSTAT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_CLRTSTAT_SHIFT)) & DDRPHY_PGCR2_CLRTSTAT_MASK)
14218 /*! @} */
14219 
14220 /*! @name PGCR3 - PHY General Configuration Register 3 */
14221 /*! @{ */
14222 #define DDRPHY_PGCR3_CLKLEVEL_MASK               (0x3U)
14223 #define DDRPHY_PGCR3_CLKLEVEL_SHIFT              (0U)
14224 /*! CLKLEVEL - Clock Level when Clock Gating
14225  */
14226 #define DDRPHY_PGCR3_CLKLEVEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_CLKLEVEL_SHIFT)) & DDRPHY_PGCR3_CLKLEVEL_MASK)
14227 #define DDRPHY_PGCR3_DISRST_MASK                 (0x4U)
14228 #define DDRPHY_PGCR3_DISRST_SHIFT                (2U)
14229 /*! DISRST - Read FIFO Reset Disable
14230  */
14231 #define DDRPHY_PGCR3_DISRST(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_DISRST_SHIFT)) & DDRPHY_PGCR3_DISRST_MASK)
14232 #define DDRPHY_PGCR3_RDMODE_MASK                 (0x18U)
14233 #define DDRPHY_PGCR3_RDMODE_SHIFT                (3U)
14234 /*! RDMODE - AC Receive FIFO Read Mode
14235  */
14236 #define DDRPHY_PGCR3_RDMODE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_RDMODE_SHIFT)) & DDRPHY_PGCR3_RDMODE_MASK)
14237 #define DDRPHY_PGCR3_IOLB_MASK                   (0x20U)
14238 #define DDRPHY_PGCR3_IOLB_SHIFT                  (5U)
14239 /*! IOLB - IO Loop-Back Select
14240  */
14241 #define DDRPHY_PGCR3_IOLB(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_IOLB_SHIFT)) & DDRPHY_PGCR3_IOLB_MASK)
14242 #define DDRPHY_PGCR3_DDLBYPMODE_MASK             (0xC0U)
14243 #define DDRPHY_PGCR3_DDLBYPMODE_SHIFT            (6U)
14244 /*! DDLBYPMODE - Controls DDL Bypass Modes
14245  */
14246 #define DDRPHY_PGCR3_DDLBYPMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_DDLBYPMODE_SHIFT)) & DDRPHY_PGCR3_DDLBYPMODE_MASK)
14247 #define DDRPHY_PGCR3_RESERVED_8_MASK             (0x100U)
14248 #define DDRPHY_PGCR3_RESERVED_8_SHIFT            (8U)
14249 /*! RESERVED_8 - Reserved. Return zeroes on reads.
14250  */
14251 #define DDRPHY_PGCR3_RESERVED_8(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_RESERVED_8_SHIFT)) & DDRPHY_PGCR3_RESERVED_8_MASK)
14252 #define DDRPHY_PGCR3_GATEACCTLCLK_MASK           (0x600U)
14253 #define DDRPHY_PGCR3_GATEACCTLCLK_SHIFT          (9U)
14254 /*! GATEACCTLCLK - Enable Clock Gating for AC [0] ctl_clk
14255  */
14256 #define DDRPHY_PGCR3_GATEACCTLCLK(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_GATEACCTLCLK_SHIFT)) & DDRPHY_PGCR3_GATEACCTLCLK_MASK)
14257 #define DDRPHY_PGCR3_GATEACDDRCLK_MASK           (0x1800U)
14258 #define DDRPHY_PGCR3_GATEACDDRCLK_SHIFT          (11U)
14259 /*! GATEACDDRCLK - Enable Clock Gating for AC [0] ddr_clk
14260  */
14261 #define DDRPHY_PGCR3_GATEACDDRCLK(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_GATEACDDRCLK_SHIFT)) & DDRPHY_PGCR3_GATEACDDRCLK_MASK)
14262 #define DDRPHY_PGCR3_GATEACRDCLK_MASK            (0x6000U)
14263 #define DDRPHY_PGCR3_GATEACRDCLK_SHIFT           (13U)
14264 /*! GATEACRDCLK - Enable Clock Gating for AC [0] ctl_rd_clk
14265  */
14266 #define DDRPHY_PGCR3_GATEACRDCLK(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_GATEACRDCLK_SHIFT)) & DDRPHY_PGCR3_GATEACRDCLK_MASK)
14267 #define DDRPHY_PGCR3_RESERVED_15_MASK            (0x8000U)
14268 #define DDRPHY_PGCR3_RESERVED_15_SHIFT           (15U)
14269 /*! RESERVED_15 - Reserved. Return zeroes on reads.
14270  */
14271 #define DDRPHY_PGCR3_RESERVED_15(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_RESERVED_15_SHIFT)) & DDRPHY_PGCR3_RESERVED_15_MASK)
14272 #define DDRPHY_PGCR3_CKEN_MASK                   (0xFF0000U)
14273 #define DDRPHY_PGCR3_CKEN_SHIFT                  (16U)
14274 /*! CKEN - CK Enable
14275  */
14276 #define DDRPHY_PGCR3_CKEN(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_CKEN_SHIFT)) & DDRPHY_PGCR3_CKEN_MASK)
14277 #define DDRPHY_PGCR3_CKNEN_MASK                  (0xFF000000U)
14278 #define DDRPHY_PGCR3_CKNEN_SHIFT                 (24U)
14279 /*! CKNEN - CKN Enable
14280  */
14281 #define DDRPHY_PGCR3_CKNEN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_CKNEN_SHIFT)) & DDRPHY_PGCR3_CKNEN_MASK)
14282 /*! @} */
14283 
14284 /*! @name PGCR4 - PHY General Configuration Register 4 */
14285 /*! @{ */
14286 #define DDRPHY_PGCR4_LPIOPD_MASK                 (0x1U)
14287 #define DDRPHY_PGCR4_LPIOPD_SHIFT                (0U)
14288 /*! LPIOPD - AC Low Power IO Power Down
14289  */
14290 #define DDRPHY_PGCR4_LPIOPD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_LPIOPD_SHIFT)) & DDRPHY_PGCR4_LPIOPD_MASK)
14291 #define DDRPHY_PGCR4_LPPLLPD_MASK                (0x2U)
14292 #define DDRPHY_PGCR4_LPPLLPD_SHIFT               (1U)
14293 /*! LPPLLPD - AC Low Power PLL Power Down
14294  */
14295 #define DDRPHY_PGCR4_LPPLLPD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_LPPLLPD_SHIFT)) & DDRPHY_PGCR4_LPPLLPD_MASK)
14296 #define DDRPHY_PGCR4_RESERVED_3_2_MASK           (0xCU)
14297 #define DDRPHY_PGCR4_RESERVED_3_2_SHIFT          (2U)
14298 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
14299  */
14300 #define DDRPHY_PGCR4_RESERVED_3_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RESERVED_3_2_SHIFT)) & DDRPHY_PGCR4_RESERVED_3_2_MASK)
14301 #define DDRPHY_PGCR4_LPWAKEUP_THRSH_MASK         (0xF0U)
14302 #define DDRPHY_PGCR4_LPWAKEUP_THRSH_SHIFT        (4U)
14303 /*! LPWAKEUP_THRSH - AC Low Power Wakeup Threshold
14304  */
14305 #define DDRPHY_PGCR4_LPWAKEUP_THRSH(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_PGCR4_LPWAKEUP_THRSH_MASK)
14306 #define DDRPHY_PGCR4_DCALSVAL_MASK               (0x1FF00U)
14307 #define DDRPHY_PGCR4_DCALSVAL_SHIFT              (8U)
14308 /*! DCALSVAL - DDL Calibration Starting Value
14309  */
14310 #define DDRPHY_PGCR4_DCALSVAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_DCALSVAL_SHIFT)) & DDRPHY_PGCR4_DCALSVAL_MASK)
14311 #define DDRPHY_PGCR4_DCALTYPE_MASK               (0x20000U)
14312 #define DDRPHY_PGCR4_DCALTYPE_SHIFT              (17U)
14313 /*! DCALTYPE - DDL Calibration Type
14314  */
14315 #define DDRPHY_PGCR4_DCALTYPE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_DCALTYPE_SHIFT)) & DDRPHY_PGCR4_DCALTYPE_MASK)
14316 #define DDRPHY_PGCR4_RESERVED_18_MASK            (0x40000U)
14317 #define DDRPHY_PGCR4_RESERVED_18_SHIFT           (18U)
14318 /*! RESERVED_18 - Reserved. Return zeroes on reads.
14319  */
14320 #define DDRPHY_PGCR4_RESERVED_18(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RESERVED_18_SHIFT)) & DDRPHY_PGCR4_RESERVED_18_MASK)
14321 #define DDRPHY_PGCR4_WRRMODE_MASK                (0x80000U)
14322 #define DDRPHY_PGCR4_WRRMODE_SHIFT               (19U)
14323 /*! WRRMODE - AC Macro Write Path Rise-to-Rise Mode
14324  */
14325 #define DDRPHY_PGCR4_WRRMODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_WRRMODE_SHIFT)) & DDRPHY_PGCR4_WRRMODE_MASK)
14326 #define DDRPHY_PGCR4_RRRMODE_MASK                (0x100000U)
14327 #define DDRPHY_PGCR4_RRRMODE_SHIFT               (20U)
14328 /*! RRRMODE - AC Macro Read Path Rise-to-Rise Mode
14329  */
14330 #define DDRPHY_PGCR4_RRRMODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RRRMODE_SHIFT)) & DDRPHY_PGCR4_RRRMODE_MASK)
14331 #define DDRPHY_PGCR4_PDRDDLBYP_MASK              (0x200000U)
14332 #define DDRPHY_PGCR4_PDRDDLBYP_SHIFT             (21U)
14333 /*! PDRDDLBYP - AC PDR DDL Bypass
14334  */
14335 #define DDRPHY_PGCR4_PDRDDLBYP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_PDRDDLBYP_SHIFT)) & DDRPHY_PGCR4_PDRDDLBYP_MASK)
14336 #define DDRPHY_PGCR4_TEDDLBYP_MASK               (0x400000U)
14337 #define DDRPHY_PGCR4_TEDDLBYP_SHIFT              (22U)
14338 /*! TEDDLBYP - AC ODT DDL Bypass
14339  */
14340 #define DDRPHY_PGCR4_TEDDLBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_TEDDLBYP_SHIFT)) & DDRPHY_PGCR4_TEDDLBYP_MASK)
14341 #define DDRPHY_PGCR4_OEDDLBYP_MASK               (0x800000U)
14342 #define DDRPHY_PGCR4_OEDDLBYP_SHIFT              (23U)
14343 /*! OEDDLBYP - AC OE DDL Bypass
14344  */
14345 #define DDRPHY_PGCR4_OEDDLBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_OEDDLBYP_SHIFT)) & DDRPHY_PGCR4_OEDDLBYP_MASK)
14346 #define DDRPHY_PGCR4_ACDDLBYP_MASK               (0x1F000000U)
14347 #define DDRPHY_PGCR4_ACDDLBYP_SHIFT              (24U)
14348 /*! ACDDLBYP - AC DDL Bypass
14349  */
14350 #define DDRPHY_PGCR4_ACDDLBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_ACDDLBYP_SHIFT)) & DDRPHY_PGCR4_ACDDLBYP_MASK)
14351 #define DDRPHY_PGCR4_ACDDLLD_MASK                (0x20000000U)
14352 #define DDRPHY_PGCR4_ACDDLLD_SHIFT               (29U)
14353 /*! ACDDLLD - AC DDL Delay Select Dymainc Load
14354  */
14355 #define DDRPHY_PGCR4_ACDDLLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_ACDDLLD_SHIFT)) & DDRPHY_PGCR4_ACDDLLD_MASK)
14356 #define DDRPHY_PGCR4_RESERVED_31_30_MASK         (0xC0000000U)
14357 #define DDRPHY_PGCR4_RESERVED_31_30_SHIFT        (30U)
14358 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
14359  */
14360 #define DDRPHY_PGCR4_RESERVED_31_30(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RESERVED_31_30_SHIFT)) & DDRPHY_PGCR4_RESERVED_31_30_MASK)
14361 /*! @} */
14362 
14363 /*! @name PGCR5 - PHY General Configuration Register 5 */
14364 /*! @{ */
14365 #define DDRPHY_PGCR5_DDLPGRW_MASK                (0x1U)
14366 #define DDRPHY_PGCR5_DDLPGRW_SHIFT               (0U)
14367 /*! DDLPGRW - DDL Page Read Write select
14368  */
14369 #define DDRPHY_PGCR5_DDLPGRW(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DDLPGRW_SHIFT)) & DDRPHY_PGCR5_DDLPGRW_MASK)
14370 #define DDRPHY_PGCR5_DDLPGACT_MASK               (0x2U)
14371 #define DDRPHY_PGCR5_DDLPGACT_SHIFT              (1U)
14372 /*! DDLPGACT - DDL Page Read Write select
14373  */
14374 #define DDRPHY_PGCR5_DDLPGACT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DDLPGACT_SHIFT)) & DDRPHY_PGCR5_DDLPGACT_MASK)
14375 #define DDRPHY_PGCR5_DXREFISELRANGE_MASK         (0x4U)
14376 #define DDRPHY_PGCR5_DXREFISELRANGE_SHIFT        (2U)
14377 /*! DXREFISELRANGE - Internal VREF generator REFSEL ragne select
14378  */
14379 #define DDRPHY_PGCR5_DXREFISELRANGE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DXREFISELRANGE_SHIFT)) & DDRPHY_PGCR5_DXREFISELRANGE_MASK)
14380 #define DDRPHY_PGCR5_RESERVED_3_MASK             (0x8U)
14381 #define DDRPHY_PGCR5_RESERVED_3_SHIFT            (3U)
14382 /*! RESERVED_3 - Reserved. Return zeroes on reads.
14383  */
14384 #define DDRPHY_PGCR5_RESERVED_3(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_RESERVED_3_SHIFT)) & DDRPHY_PGCR5_RESERVED_3_MASK)
14385 #define DDRPHY_PGCR5_VREF_RBCTRL_MASK            (0xF0U)
14386 #define DDRPHY_PGCR5_VREF_RBCTRL_SHIFT           (4U)
14387 /*! VREF_RBCTRL - Receiver bias core side control
14388  */
14389 #define DDRPHY_PGCR5_VREF_RBCTRL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_VREF_RBCTRL_SHIFT)) & DDRPHY_PGCR5_VREF_RBCTRL_MASK)
14390 #define DDRPHY_PGCR5_DISCNPERIOD_MASK            (0xFF00U)
14391 #define DDRPHY_PGCR5_DISCNPERIOD_SHIFT           (8U)
14392 /*! DISCNPERIOD - DFI Disconnect Time Period
14393  */
14394 #define DDRPHY_PGCR5_DISCNPERIOD(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DISCNPERIOD_SHIFT)) & DDRPHY_PGCR5_DISCNPERIOD_MASK)
14395 #define DDRPHY_PGCR5_FRQAT_MASK                  (0xFF0000U)
14396 #define DDRPHY_PGCR5_FRQAT_SHIFT                 (16U)
14397 /*! FRQAT - Frequency A Ratio Term
14398  */
14399 #define DDRPHY_PGCR5_FRQAT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_FRQAT_SHIFT)) & DDRPHY_PGCR5_FRQAT_MASK)
14400 #define DDRPHY_PGCR5_FRQBT_MASK                  (0xFF000000U)
14401 #define DDRPHY_PGCR5_FRQBT_SHIFT                 (24U)
14402 /*! FRQBT - Frequency B Ratio Term
14403  */
14404 #define DDRPHY_PGCR5_FRQBT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_FRQBT_SHIFT)) & DDRPHY_PGCR5_FRQBT_MASK)
14405 /*! @} */
14406 
14407 /*! @name PGCR6 - PHY General Configuration Register 6 */
14408 /*! @{ */
14409 #define DDRPHY_PGCR6_INHVT_MASK                  (0x1U)
14410 #define DDRPHY_PGCR6_INHVT_SHIFT                 (0U)
14411 /*! INHVT - VT Calculation Inhibit
14412  */
14413 #define DDRPHY_PGCR6_INHVT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_INHVT_SHIFT)) & DDRPHY_PGCR6_INHVT_MASK)
14414 #define DDRPHY_PGCR6_FVT_MASK                    (0x2U)
14415 #define DDRPHY_PGCR6_FVT_SHIFT                   (1U)
14416 /*! FVT - Forced VT Compensation Trigger
14417  */
14418 #define DDRPHY_PGCR6_FVT(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_FVT_SHIFT)) & DDRPHY_PGCR6_FVT_MASK)
14419 #define DDRPHY_PGCR6_RESERVED_7_2_MASK           (0xFCU)
14420 #define DDRPHY_PGCR6_RESERVED_7_2_SHIFT          (2U)
14421 /*! RESERVED_7_2 - Reserved. Returns zeroes on reads.
14422  */
14423 #define DDRPHY_PGCR6_RESERVED_7_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_RESERVED_7_2_SHIFT)) & DDRPHY_PGCR6_RESERVED_7_2_MASK)
14424 #define DDRPHY_PGCR6_CKBVT_MASK                  (0x100U)
14425 #define DDRPHY_PGCR6_CKBVT_SHIFT                 (8U)
14426 /*! CKBVT - CK Bit Delay VT Compensation
14427  */
14428 #define DDRPHY_PGCR6_CKBVT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_CKBVT_SHIFT)) & DDRPHY_PGCR6_CKBVT_MASK)
14429 #define DDRPHY_PGCR6_CSNBVT_MASK                 (0x200U)
14430 #define DDRPHY_PGCR6_CSNBVT_SHIFT                (9U)
14431 /*! CSNBVT - CSN Bit Delay VT Compensation
14432  */
14433 #define DDRPHY_PGCR6_CSNBVT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_CSNBVT_SHIFT)) & DDRPHY_PGCR6_CSNBVT_MASK)
14434 #define DDRPHY_PGCR6_CKEBVT_MASK                 (0x400U)
14435 #define DDRPHY_PGCR6_CKEBVT_SHIFT                (10U)
14436 /*! CKEBVT - CKE Bit Delay VT Compensation
14437  */
14438 #define DDRPHY_PGCR6_CKEBVT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_CKEBVT_SHIFT)) & DDRPHY_PGCR6_CKEBVT_MASK)
14439 #define DDRPHY_PGCR6_ODTBVT_MASK                 (0x800U)
14440 #define DDRPHY_PGCR6_ODTBVT_SHIFT                (11U)
14441 /*! ODTBVT - ODT Bit Delay VT Compensation
14442  */
14443 #define DDRPHY_PGCR6_ODTBVT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_ODTBVT_SHIFT)) & DDRPHY_PGCR6_ODTBVT_MASK)
14444 #define DDRPHY_PGCR6_ACBVT_MASK                  (0x1000U)
14445 #define DDRPHY_PGCR6_ACBVT_SHIFT                 (12U)
14446 /*! ACBVT - Address/Command Bit Delay VT Compensation
14447  */
14448 #define DDRPHY_PGCR6_ACBVT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_ACBVT_SHIFT)) & DDRPHY_PGCR6_ACBVT_MASK)
14449 #define DDRPHY_PGCR6_ACDLVT_MASK                 (0x2000U)
14450 #define DDRPHY_PGCR6_ACDLVT_SHIFT                (13U)
14451 /*! ACDLVT - AC Address/Command Delay LCDL VT Compensation
14452  */
14453 #define DDRPHY_PGCR6_ACDLVT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_ACDLVT_SHIFT)) & DDRPHY_PGCR6_ACDLVT_MASK)
14454 #define DDRPHY_PGCR6_RESERVED_15_14_MASK         (0xC000U)
14455 #define DDRPHY_PGCR6_RESERVED_15_14_SHIFT        (14U)
14456 /*! RESERVED_15_14 - Reserved. Returns zeroes on reads.
14457  */
14458 #define DDRPHY_PGCR6_RESERVED_15_14(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_RESERVED_15_14_SHIFT)) & DDRPHY_PGCR6_RESERVED_15_14_MASK)
14459 #define DDRPHY_PGCR6_DLDLMT_MASK                 (0xFF0000U)
14460 #define DDRPHY_PGCR6_DLDLMT_SHIFT                (16U)
14461 /*! DLDLMT - Delay Line VT Drift Limit
14462  */
14463 #define DDRPHY_PGCR6_DLDLMT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_DLDLMT_SHIFT)) & DDRPHY_PGCR6_DLDLMT_MASK)
14464 #define DDRPHY_PGCR6_RESERVED_31_24_MASK         (0xFF000000U)
14465 #define DDRPHY_PGCR6_RESERVED_31_24_SHIFT        (24U)
14466 /*! RESERVED_31_24 - Reserved. Returns zeroes on reads.
14467  */
14468 #define DDRPHY_PGCR6_RESERVED_31_24(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_RESERVED_31_24_SHIFT)) & DDRPHY_PGCR6_RESERVED_31_24_MASK)
14469 /*! @} */
14470 
14471 /*! @name PGCR7 - PHY General Configuration Register 7 */
14472 /*! @{ */
14473 #define DDRPHY_PGCR7_ACTMODE_MASK                (0x1U)
14474 #define DDRPHY_PGCR7_ACTMODE_SHIFT               (0U)
14475 /*! ACTMODE - AC Test Mode
14476  */
14477 #define DDRPHY_PGCR7_ACTMODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACTMODE_SHIFT)) & DDRPHY_PGCR7_ACTMODE_MASK)
14478 #define DDRPHY_PGCR7_ACDTOSEL_MASK               (0x2U)
14479 #define DDRPHY_PGCR7_ACDTOSEL_SHIFT              (1U)
14480 /*! ACDTOSEL - AC Digital Test Output Select
14481  */
14482 #define DDRPHY_PGCR7_ACDTOSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACDTOSEL_SHIFT)) & DDRPHY_PGCR7_ACDTOSEL_MASK)
14483 #define DDRPHY_PGCR7_ACRSVD_2_MASK               (0x4U)
14484 #define DDRPHY_PGCR7_ACRSVD_2_SHIFT              (2U)
14485 /*! ACRSVD_2 - This bit is reserved for future AC special PHY modes but the register is already
14486  *    connected to existing (unused) AC phy_mode bits.
14487  */
14488 #define DDRPHY_PGCR7_ACRSVD_2(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACRSVD_2_SHIFT)) & DDRPHY_PGCR7_ACRSVD_2_MASK)
14489 #define DDRPHY_PGCR7_ACDLDT_MASK                 (0x8U)
14490 #define DDRPHY_PGCR7_ACDLDT_SHIFT                (3U)
14491 /*! ACDLDT - AC DDL Load Type
14492  */
14493 #define DDRPHY_PGCR7_ACDLDT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACDLDT_SHIFT)) & DDRPHY_PGCR7_ACDLDT_MASK)
14494 #define DDRPHY_PGCR7_ACRCLKMD_MASK               (0x10U)
14495 #define DDRPHY_PGCR7_ACRCLKMD_SHIFT              (4U)
14496 /*! ACRCLKMD - AC Read Clock Mode
14497  */
14498 #define DDRPHY_PGCR7_ACRCLKMD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACRCLKMD_SHIFT)) & DDRPHY_PGCR7_ACRCLKMD_MASK)
14499 #define DDRPHY_PGCR7_ACCALCLK_MASK               (0x20U)
14500 #define DDRPHY_PGCR7_ACCALCLK_SHIFT              (5U)
14501 /*! ACCALCLK - AC Calibration Clock Select
14502  */
14503 #define DDRPHY_PGCR7_ACCALCLK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACCALCLK_SHIFT)) & DDRPHY_PGCR7_ACCALCLK_MASK)
14504 #define DDRPHY_PGCR7_ACRSVD_7_6_MASK             (0xC0U)
14505 #define DDRPHY_PGCR7_ACRSVD_7_6_SHIFT            (6U)
14506 /*! ACRSVD_7_6 - These bits are reserved for future AC special PHY modes but the registers are
14507  *    already connected to existing (unused) AC phy_mode bits.
14508  */
14509 #define DDRPHY_PGCR7_ACRSVD_7_6(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACRSVD_7_6_SHIFT)) & DDRPHY_PGCR7_ACRSVD_7_6_MASK)
14510 #define DDRPHY_PGCR7_RESERVED_31_8_MASK          (0xFFFFFF00U)
14511 #define DDRPHY_PGCR7_RESERVED_31_8_SHIFT         (8U)
14512 /*! RESERVED_31_8 - Reserved. Returns zeroes on reads.
14513  */
14514 #define DDRPHY_PGCR7_RESERVED_31_8(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_RESERVED_31_8_SHIFT)) & DDRPHY_PGCR7_RESERVED_31_8_MASK)
14515 /*! @} */
14516 
14517 /*! @name PGSR0 - PHY General Status Register 0 */
14518 /*! @{ */
14519 #define DDRPHY_PGSR0_IDONE_MASK                  (0x1U)
14520 #define DDRPHY_PGSR0_IDONE_SHIFT                 (0U)
14521 /*! IDONE - Initialization Done
14522  */
14523 #define DDRPHY_PGSR0_IDONE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_IDONE_SHIFT)) & DDRPHY_PGSR0_IDONE_MASK)
14524 #define DDRPHY_PGSR0_PLDONE_MASK                 (0x2U)
14525 #define DDRPHY_PGSR0_PLDONE_SHIFT                (1U)
14526 /*! PLDONE - PLL Lock Done
14527  */
14528 #define DDRPHY_PGSR0_PLDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_PLDONE_SHIFT)) & DDRPHY_PGSR0_PLDONE_MASK)
14529 #define DDRPHY_PGSR0_DCDONE_MASK                 (0x4U)
14530 #define DDRPHY_PGSR0_DCDONE_SHIFT                (2U)
14531 /*! DCDONE - Digital Delay Line (DDL) Calibration Done
14532  */
14533 #define DDRPHY_PGSR0_DCDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DCDONE_SHIFT)) & DDRPHY_PGSR0_DCDONE_MASK)
14534 #define DDRPHY_PGSR0_ZCDONE_MASK                 (0x8U)
14535 #define DDRPHY_PGSR0_ZCDONE_SHIFT                (3U)
14536 /*! ZCDONE - Impedance Calibration Done
14537  */
14538 #define DDRPHY_PGSR0_ZCDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_ZCDONE_SHIFT)) & DDRPHY_PGSR0_ZCDONE_MASK)
14539 #define DDRPHY_PGSR0_DIDONE_MASK                 (0x10U)
14540 #define DDRPHY_PGSR0_DIDONE_SHIFT                (4U)
14541 /*! DIDONE - DRAM Initialization Done
14542  */
14543 #define DDRPHY_PGSR0_DIDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DIDONE_SHIFT)) & DDRPHY_PGSR0_DIDONE_MASK)
14544 #define DDRPHY_PGSR0_WLDONE_MASK                 (0x20U)
14545 #define DDRPHY_PGSR0_WLDONE_SHIFT                (5U)
14546 /*! WLDONE - Write Leveling Done
14547  */
14548 #define DDRPHY_PGSR0_WLDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLDONE_SHIFT)) & DDRPHY_PGSR0_WLDONE_MASK)
14549 #define DDRPHY_PGSR0_QSGDONE_MASK                (0x40U)
14550 #define DDRPHY_PGSR0_QSGDONE_SHIFT               (6U)
14551 /*! QSGDONE - DQS Gate Training Done
14552  */
14553 #define DDRPHY_PGSR0_QSGDONE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_QSGDONE_SHIFT)) & DDRPHY_PGSR0_QSGDONE_MASK)
14554 #define DDRPHY_PGSR0_WLADONE_MASK                (0x80U)
14555 #define DDRPHY_PGSR0_WLADONE_SHIFT               (7U)
14556 /*! WLADONE - Write Leveling Adjustment Done
14557  */
14558 #define DDRPHY_PGSR0_WLADONE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLADONE_SHIFT)) & DDRPHY_PGSR0_WLADONE_MASK)
14559 #define DDRPHY_PGSR0_RDDONE_MASK                 (0x100U)
14560 #define DDRPHY_PGSR0_RDDONE_SHIFT                (8U)
14561 /*! RDDONE - Read Bit Deskew Done
14562  */
14563 #define DDRPHY_PGSR0_RDDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_RDDONE_SHIFT)) & DDRPHY_PGSR0_RDDONE_MASK)
14564 #define DDRPHY_PGSR0_WDDONE_MASK                 (0x200U)
14565 #define DDRPHY_PGSR0_WDDONE_SHIFT                (9U)
14566 /*! WDDONE - Write Bit Deskew Done
14567  */
14568 #define DDRPHY_PGSR0_WDDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WDDONE_SHIFT)) & DDRPHY_PGSR0_WDDONE_MASK)
14569 #define DDRPHY_PGSR0_REDONE_MASK                 (0x400U)
14570 #define DDRPHY_PGSR0_REDONE_SHIFT                (10U)
14571 /*! REDONE - Read Eye Training Done
14572  */
14573 #define DDRPHY_PGSR0_REDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_REDONE_SHIFT)) & DDRPHY_PGSR0_REDONE_MASK)
14574 #define DDRPHY_PGSR0_WEDONE_MASK                 (0x800U)
14575 #define DDRPHY_PGSR0_WEDONE_SHIFT                (11U)
14576 /*! WEDONE - Write Eye Training Done
14577  */
14578 #define DDRPHY_PGSR0_WEDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WEDONE_SHIFT)) & DDRPHY_PGSR0_WEDONE_MASK)
14579 #define DDRPHY_PGSR0_CADONE_MASK                 (0x1000U)
14580 #define DDRPHY_PGSR0_CADONE_SHIFT                (12U)
14581 /*! CADONE - CA Training Done
14582  */
14583 #define DDRPHY_PGSR0_CADONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_CADONE_SHIFT)) & DDRPHY_PGSR0_CADONE_MASK)
14584 #define DDRPHY_PGSR0_SRDDONE_MASK                (0x2000U)
14585 #define DDRPHY_PGSR0_SRDDONE_SHIFT               (13U)
14586 /*! SRDDONE - Static Read Done
14587  */
14588 #define DDRPHY_PGSR0_SRDDONE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_SRDDONE_SHIFT)) & DDRPHY_PGSR0_SRDDONE_MASK)
14589 #define DDRPHY_PGSR0_VDONE_MASK                  (0x4000U)
14590 #define DDRPHY_PGSR0_VDONE_SHIFT                 (14U)
14591 /*! VDONE - VREF Training Done
14592  */
14593 #define DDRPHY_PGSR0_VDONE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_VDONE_SHIFT)) & DDRPHY_PGSR0_VDONE_MASK)
14594 #define DDRPHY_PGSR0_DQS2DQDONE_MASK             (0x8000U)
14595 #define DDRPHY_PGSR0_DQS2DQDONE_SHIFT            (15U)
14596 /*! DQS2DQDONE - Write DQS2DQ Training Done
14597  */
14598 #define DDRPHY_PGSR0_DQS2DQDONE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DQS2DQDONE_SHIFT)) & DDRPHY_PGSR0_DQS2DQDONE_MASK)
14599 #define DDRPHY_PGSR0_RESERVED_17_16_MASK         (0x30000U)
14600 #define DDRPHY_PGSR0_RESERVED_17_16_SHIFT        (16U)
14601 /*! RESERVED_17_16 - Reserved. Returns zeroes on reads.
14602  */
14603 #define DDRPHY_PGSR0_RESERVED_17_16(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_RESERVED_17_16_SHIFT)) & DDRPHY_PGSR0_RESERVED_17_16_MASK)
14604 #define DDRPHY_PGSR0_DQS2DQERR_MASK              (0x40000U)
14605 #define DDRPHY_PGSR0_DQS2DQERR_SHIFT             (18U)
14606 /*! DQS2DQERR - Write DQS2DQ Training Error
14607  */
14608 #define DDRPHY_PGSR0_DQS2DQERR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DQS2DQERR_SHIFT)) & DDRPHY_PGSR0_DQS2DQERR_MASK)
14609 #define DDRPHY_PGSR0_VERR_MASK                   (0x80000U)
14610 #define DDRPHY_PGSR0_VERR_SHIFT                  (19U)
14611 /*! VERR - VREF Training Error
14612  */
14613 #define DDRPHY_PGSR0_VERR(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_VERR_SHIFT)) & DDRPHY_PGSR0_VERR_MASK)
14614 #define DDRPHY_PGSR0_ZCERR_MASK                  (0x100000U)
14615 #define DDRPHY_PGSR0_ZCERR_SHIFT                 (20U)
14616 /*! ZCERR - Impedance Calibration Error
14617  */
14618 #define DDRPHY_PGSR0_ZCERR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_ZCERR_SHIFT)) & DDRPHY_PGSR0_ZCERR_MASK)
14619 #define DDRPHY_PGSR0_WLERR_MASK                  (0x200000U)
14620 #define DDRPHY_PGSR0_WLERR_SHIFT                 (21U)
14621 /*! WLERR - Write Leveling Error
14622  */
14623 #define DDRPHY_PGSR0_WLERR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLERR_SHIFT)) & DDRPHY_PGSR0_WLERR_MASK)
14624 #define DDRPHY_PGSR0_QSGERR_MASK                 (0x400000U)
14625 #define DDRPHY_PGSR0_QSGERR_SHIFT                (22U)
14626 /*! QSGERR - DQS Gate Training Error
14627  */
14628 #define DDRPHY_PGSR0_QSGERR(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_QSGERR_SHIFT)) & DDRPHY_PGSR0_QSGERR_MASK)
14629 #define DDRPHY_PGSR0_WLAERR_MASK                 (0x800000U)
14630 #define DDRPHY_PGSR0_WLAERR_SHIFT                (23U)
14631 /*! WLAERR - Write Leveling Adjustment Error
14632  */
14633 #define DDRPHY_PGSR0_WLAERR(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLAERR_SHIFT)) & DDRPHY_PGSR0_WLAERR_MASK)
14634 #define DDRPHY_PGSR0_RDERR_MASK                  (0x1000000U)
14635 #define DDRPHY_PGSR0_RDERR_SHIFT                 (24U)
14636 /*! RDERR - Read Bit Deskew Error
14637  */
14638 #define DDRPHY_PGSR0_RDERR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_RDERR_SHIFT)) & DDRPHY_PGSR0_RDERR_MASK)
14639 #define DDRPHY_PGSR0_WDERR_MASK                  (0x2000000U)
14640 #define DDRPHY_PGSR0_WDERR_SHIFT                 (25U)
14641 /*! WDERR - Write Bit Deskew Error
14642  */
14643 #define DDRPHY_PGSR0_WDERR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WDERR_SHIFT)) & DDRPHY_PGSR0_WDERR_MASK)
14644 #define DDRPHY_PGSR0_REERR_MASK                  (0x4000000U)
14645 #define DDRPHY_PGSR0_REERR_SHIFT                 (26U)
14646 /*! REERR - Read Eye Training Error
14647  */
14648 #define DDRPHY_PGSR0_REERR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_REERR_SHIFT)) & DDRPHY_PGSR0_REERR_MASK)
14649 #define DDRPHY_PGSR0_WEERR_MASK                  (0x8000000U)
14650 #define DDRPHY_PGSR0_WEERR_SHIFT                 (27U)
14651 /*! WEERR - Write Eye Training Error
14652  */
14653 #define DDRPHY_PGSR0_WEERR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WEERR_SHIFT)) & DDRPHY_PGSR0_WEERR_MASK)
14654 #define DDRPHY_PGSR0_CAERR_MASK                  (0x10000000U)
14655 #define DDRPHY_PGSR0_CAERR_SHIFT                 (28U)
14656 /*! CAERR - CA Training Error
14657  */
14658 #define DDRPHY_PGSR0_CAERR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_CAERR_SHIFT)) & DDRPHY_PGSR0_CAERR_MASK)
14659 #define DDRPHY_PGSR0_CAWRN_MASK                  (0x20000000U)
14660 #define DDRPHY_PGSR0_CAWRN_SHIFT                 (29U)
14661 /*! CAWRN - CA Training Warning
14662  */
14663 #define DDRPHY_PGSR0_CAWRN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_CAWRN_SHIFT)) & DDRPHY_PGSR0_CAWRN_MASK)
14664 #define DDRPHY_PGSR0_SRDERR_MASK                 (0x40000000U)
14665 #define DDRPHY_PGSR0_SRDERR_SHIFT                (30U)
14666 /*! SRDERR - Static Read Error
14667  */
14668 #define DDRPHY_PGSR0_SRDERR(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_SRDERR_SHIFT)) & DDRPHY_PGSR0_SRDERR_MASK)
14669 #define DDRPHY_PGSR0_APLOCK_MASK                 (0x80000000U)
14670 #define DDRPHY_PGSR0_APLOCK_SHIFT                (31U)
14671 /*! APLOCK - AC PLL Lock
14672  */
14673 #define DDRPHY_PGSR0_APLOCK(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_APLOCK_SHIFT)) & DDRPHY_PGSR0_APLOCK_MASK)
14674 /*! @} */
14675 
14676 /*! @name PGSR1 - PHY General Status Register 1 */
14677 /*! @{ */
14678 #define DDRPHY_PGSR1_DLTDONE_MASK                (0x1U)
14679 #define DDRPHY_PGSR1_DLTDONE_SHIFT               (0U)
14680 /*! DLTDONE - Delay Line Test Done for AC macro 0
14681  */
14682 #define DDRPHY_PGSR1_DLTDONE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_DLTDONE_SHIFT)) & DDRPHY_PGSR1_DLTDONE_MASK)
14683 #define DDRPHY_PGSR1_DLTCODE_MASK                (0x1FFFFFEU)
14684 #define DDRPHY_PGSR1_DLTCODE_SHIFT               (1U)
14685 /*! DLTCODE - Delay Line Test Code for AC macro 0
14686  */
14687 #define DDRPHY_PGSR1_DLTCODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_DLTCODE_SHIFT)) & DDRPHY_PGSR1_DLTCODE_MASK)
14688 #define DDRPHY_PGSR1_RESERVED_29_25_MASK         (0x3E000000U)
14689 #define DDRPHY_PGSR1_RESERVED_29_25_SHIFT        (25U)
14690 /*! RESERVED_29_25 - Reserved. Returns zeroes on reads.
14691  */
14692 #define DDRPHY_PGSR1_RESERVED_29_25(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_RESERVED_29_25_SHIFT)) & DDRPHY_PGSR1_RESERVED_29_25_MASK)
14693 #define DDRPHY_PGSR1_VTSTOP_MASK                 (0x40000000U)
14694 #define DDRPHY_PGSR1_VTSTOP_SHIFT                (30U)
14695 /*! VTSTOP - VT Stop
14696  */
14697 #define DDRPHY_PGSR1_VTSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_VTSTOP_SHIFT)) & DDRPHY_PGSR1_VTSTOP_MASK)
14698 #define DDRPHY_PGSR1_PARERR_MASK                 (0x80000000U)
14699 #define DDRPHY_PGSR1_PARERR_SHIFT                (31U)
14700 /*! PARERR - RDIMM Parity Error
14701  */
14702 #define DDRPHY_PGSR1_PARERR(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_PARERR_SHIFT)) & DDRPHY_PGSR1_PARERR_MASK)
14703 /*! @} */
14704 
14705 /*! @name PGSR2 - PHY General Status Register 2 */
14706 /*! @{ */
14707 #define DDRPHY_PGSR2_DLTDONE_MASK                (0x1U)
14708 #define DDRPHY_PGSR2_DLTDONE_SHIFT               (0U)
14709 /*! DLTDONE - Delay Line Test Done for AC macro 1
14710  */
14711 #define DDRPHY_PGSR2_DLTDONE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR2_DLTDONE_SHIFT)) & DDRPHY_PGSR2_DLTDONE_MASK)
14712 #define DDRPHY_PGSR2_DLTCODE_MASK                (0x1FFFFFEU)
14713 #define DDRPHY_PGSR2_DLTCODE_SHIFT               (1U)
14714 /*! DLTCODE - Delay Line Test Code for AC macro 1
14715  */
14716 #define DDRPHY_PGSR2_DLTCODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR2_DLTCODE_SHIFT)) & DDRPHY_PGSR2_DLTCODE_MASK)
14717 #define DDRPHY_PGSR2_RESERVED_31_25_MASK         (0xFE000000U)
14718 #define DDRPHY_PGSR2_RESERVED_31_25_SHIFT        (25U)
14719 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
14720  */
14721 #define DDRPHY_PGSR2_RESERVED_31_25(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR2_RESERVED_31_25_SHIFT)) & DDRPHY_PGSR2_RESERVED_31_25_MASK)
14722 /*! @} */
14723 
14724 /*! @name PTR0 - PHY Timing Register 0 */
14725 /*! @{ */
14726 #define DDRPHY_PTR0_tPHYRST_MASK                 (0x3FU)
14727 #define DDRPHY_PTR0_tPHYRST_SHIFT                (0U)
14728 /*! tPHYRST - PHY Reset Time
14729  */
14730 #define DDRPHY_PTR0_tPHYRST(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR0_tPHYRST_SHIFT)) & DDRPHY_PTR0_tPHYRST_MASK)
14731 #define DDRPHY_PTR0_tPLLGS_MASK                  (0x1FFFC0U)
14732 #define DDRPHY_PTR0_tPLLGS_SHIFT                 (6U)
14733 /*! tPLLGS - PLL Gear Shift Time
14734  */
14735 #define DDRPHY_PTR0_tPLLGS(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR0_tPLLGS_SHIFT)) & DDRPHY_PTR0_tPLLGS_MASK)
14736 #define DDRPHY_PTR0_tPLLPD_MASK                  (0xFFE00000U)
14737 #define DDRPHY_PTR0_tPLLPD_SHIFT                 (21U)
14738 /*! tPLLPD - PLL Power-Down Time
14739  */
14740 #define DDRPHY_PTR0_tPLLPD(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR0_tPLLPD_SHIFT)) & DDRPHY_PTR0_tPLLPD_MASK)
14741 /*! @} */
14742 
14743 /*! @name PTR1 - PHY Timing Register 1 */
14744 /*! @{ */
14745 #define DDRPHY_PTR1_tPLLRST_MASK                 (0x1FFFU)
14746 #define DDRPHY_PTR1_tPLLRST_SHIFT                (0U)
14747 /*! tPLLRST - PLL Reset Time
14748  */
14749 #define DDRPHY_PTR1_tPLLRST(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR1_tPLLRST_SHIFT)) & DDRPHY_PTR1_tPLLRST_MASK)
14750 #define DDRPHY_PTR1_RESERVED_15_13_MASK          (0xE000U)
14751 #define DDRPHY_PTR1_RESERVED_15_13_SHIFT         (13U)
14752 /*! RESERVED_15_13 - Reserved. Returns zeroes on reads.
14753  */
14754 #define DDRPHY_PTR1_RESERVED_15_13(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR1_RESERVED_15_13_SHIFT)) & DDRPHY_PTR1_RESERVED_15_13_MASK)
14755 #define DDRPHY_PTR1_tPLLLOCK_MASK                (0xFFFF0000U)
14756 #define DDRPHY_PTR1_tPLLLOCK_SHIFT               (16U)
14757 /*! tPLLLOCK - PLL Lock Time
14758  */
14759 #define DDRPHY_PTR1_tPLLLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR1_tPLLLOCK_SHIFT)) & DDRPHY_PTR1_tPLLLOCK_MASK)
14760 /*! @} */
14761 
14762 /*! @name PTR2 - PHY Timing Register 2 */
14763 /*! @{ */
14764 #define DDRPHY_PTR2_tCALON_MASK                  (0x1FU)
14765 #define DDRPHY_PTR2_tCALON_SHIFT                 (0U)
14766 /*! tCALON - Calibration On Time
14767  */
14768 #define DDRPHY_PTR2_tCALON(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tCALON_SHIFT)) & DDRPHY_PTR2_tCALON_MASK)
14769 #define DDRPHY_PTR2_tCALS_MASK                   (0x3E0U)
14770 #define DDRPHY_PTR2_tCALS_SHIFT                  (5U)
14771 /*! tCALS - Calibration Setup Time
14772  */
14773 #define DDRPHY_PTR2_tCALS(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tCALS_SHIFT)) & DDRPHY_PTR2_tCALS_MASK)
14774 #define DDRPHY_PTR2_tCALH_MASK                   (0x7C00U)
14775 #define DDRPHY_PTR2_tCALH_SHIFT                  (10U)
14776 /*! tCALH - Calibration Hold Time
14777  */
14778 #define DDRPHY_PTR2_tCALH(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tCALH_SHIFT)) & DDRPHY_PTR2_tCALH_MASK)
14779 #define DDRPHY_PTR2_tWLDLYS_MASK                 (0xF8000U)
14780 #define DDRPHY_PTR2_tWLDLYS_SHIFT                (15U)
14781 /*! tWLDLYS - Write Leveling Delay Settling Time
14782  */
14783 #define DDRPHY_PTR2_tWLDLYS(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tWLDLYS_SHIFT)) & DDRPHY_PTR2_tWLDLYS_MASK)
14784 #define DDRPHY_PTR2_RESERVED_31_20_MASK          (0xFFF00000U)
14785 #define DDRPHY_PTR2_RESERVED_31_20_SHIFT         (20U)
14786 /*! RESERVED_31_20 - Reserved. Return zeroes on reads.
14787  */
14788 #define DDRPHY_PTR2_RESERVED_31_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_RESERVED_31_20_SHIFT)) & DDRPHY_PTR2_RESERVED_31_20_MASK)
14789 /*! @} */
14790 
14791 /*! @name PTR3 - PHY Timing Register 3 */
14792 /*! @{ */
14793 #define DDRPHY_PTR3_tDINIT0_MASK                 (0x7FFFFFU)
14794 #define DDRPHY_PTR3_tDINIT0_SHIFT                (0U)
14795 /*! tDINIT0 - DRAM Initialization Time 0
14796  */
14797 #define DDRPHY_PTR3_tDINIT0(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR3_tDINIT0_SHIFT)) & DDRPHY_PTR3_tDINIT0_MASK)
14798 #define DDRPHY_PTR3_RESERVED_31_23_MASK          (0xFF800000U)
14799 #define DDRPHY_PTR3_RESERVED_31_23_SHIFT         (23U)
14800 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
14801  */
14802 #define DDRPHY_PTR3_RESERVED_31_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR3_RESERVED_31_23_SHIFT)) & DDRPHY_PTR3_RESERVED_31_23_MASK)
14803 /*! @} */
14804 
14805 /*! @name PTR4 - PHY Timing Register 4 */
14806 /*! @{ */
14807 #define DDRPHY_PTR4_tDINIT1_MASK                 (0x1FFFU)
14808 #define DDRPHY_PTR4_tDINIT1_SHIFT                (0U)
14809 /*! tDINIT1 - DRAM Initialization Time 1
14810  */
14811 #define DDRPHY_PTR4_tDINIT1(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR4_tDINIT1_SHIFT)) & DDRPHY_PTR4_tDINIT1_MASK)
14812 #define DDRPHY_PTR4_RESERVED_31_13_MASK          (0xFFFFE000U)
14813 #define DDRPHY_PTR4_RESERVED_31_13_SHIFT         (13U)
14814 /*! RESERVED_31_13 - Reserved. Return zeroes on reads.
14815  */
14816 #define DDRPHY_PTR4_RESERVED_31_13(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR4_RESERVED_31_13_SHIFT)) & DDRPHY_PTR4_RESERVED_31_13_MASK)
14817 /*! @} */
14818 
14819 /*! @name PTR5 - PHY Timing Register 5 */
14820 /*! @{ */
14821 #define DDRPHY_PTR5_tDINIT2_MASK                 (0x7FFFFU)
14822 #define DDRPHY_PTR5_tDINIT2_SHIFT                (0U)
14823 /*! tDINIT2 - DRAM Initialization Time 1
14824  */
14825 #define DDRPHY_PTR5_tDINIT2(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR5_tDINIT2_SHIFT)) & DDRPHY_PTR5_tDINIT2_MASK)
14826 #define DDRPHY_PTR5_RESERVED_31_19_MASK          (0xFFF80000U)
14827 #define DDRPHY_PTR5_RESERVED_31_19_SHIFT         (19U)
14828 /*! RESERVED_31_19 - Reserved. Return zeroes on reads.
14829  */
14830 #define DDRPHY_PTR5_RESERVED_31_19(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR5_RESERVED_31_19_SHIFT)) & DDRPHY_PTR5_RESERVED_31_19_MASK)
14831 /*! @} */
14832 
14833 /*! @name PTR6 - PHY Timing Register 6 */
14834 /*! @{ */
14835 #define DDRPHY_PTR6_tDINIT3_MASK                 (0xFFFU)
14836 #define DDRPHY_PTR6_tDINIT3_SHIFT                (0U)
14837 /*! tDINIT3 - DRAM Initialization Time 3
14838  */
14839 #define DDRPHY_PTR6_tDINIT3(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_tDINIT3_SHIFT)) & DDRPHY_PTR6_tDINIT3_MASK)
14840 #define DDRPHY_PTR6_RESERVED_19_12_MASK          (0xFF000U)
14841 #define DDRPHY_PTR6_RESERVED_19_12_SHIFT         (12U)
14842 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
14843  */
14844 #define DDRPHY_PTR6_RESERVED_19_12(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_RESERVED_19_12_SHIFT)) & DDRPHY_PTR6_RESERVED_19_12_MASK)
14845 #define DDRPHY_PTR6_tDINIT4_MASK                 (0x7F00000U)
14846 #define DDRPHY_PTR6_tDINIT4_SHIFT                (20U)
14847 /*! tDINIT4 - DRAM Initialization Time 4
14848  */
14849 #define DDRPHY_PTR6_tDINIT4(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_tDINIT4_SHIFT)) & DDRPHY_PTR6_tDINIT4_MASK)
14850 #define DDRPHY_PTR6_RESERVED_31_27_MASK          (0xF8000000U)
14851 #define DDRPHY_PTR6_RESERVED_31_27_SHIFT         (27U)
14852 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
14853  */
14854 #define DDRPHY_PTR6_RESERVED_31_27(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_RESERVED_31_27_SHIFT)) & DDRPHY_PTR6_RESERVED_31_27_MASK)
14855 /*! @} */
14856 
14857 /*! @name PLLCR0 - PLL Control Register 0 (Type B PLL Only) */
14858 /*! @{ */
14859 #define DDRPHY_PLLCR0_DTC_MASK                   (0xFU)
14860 #define DDRPHY_PLLCR0_DTC_SHIFT                  (0U)
14861 /*! DTC - Digital Test Control
14862  */
14863 #define DDRPHY_PLLCR0_DTC(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_DTC_SHIFT)) & DDRPHY_PLLCR0_DTC_MASK)
14864 #define DDRPHY_PLLCR0_ATC_MASK                   (0xF0U)
14865 #define DDRPHY_PLLCR0_ATC_SHIFT                  (4U)
14866 /*! ATC - Analog Test Control
14867  */
14868 #define DDRPHY_PLLCR0_ATC(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_ATC_SHIFT)) & DDRPHY_PLLCR0_ATC_MASK)
14869 #define DDRPHY_PLLCR0_ATOEN_MASK                 (0x100U)
14870 #define DDRPHY_PLLCR0_ATOEN_SHIFT                (8U)
14871 /*! ATOEN - Analog Test Enable
14872  */
14873 #define DDRPHY_PLLCR0_ATOEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_ATOEN_SHIFT)) & DDRPHY_PLLCR0_ATOEN_MASK)
14874 #define DDRPHY_PLLCR0_RESERVED_11_9_MASK         (0xE00U)
14875 #define DDRPHY_PLLCR0_RESERVED_11_9_SHIFT        (9U)
14876 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
14877  */
14878 #define DDRPHY_PLLCR0_RESERVED_11_9(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_PLLCR0_RESERVED_11_9_MASK)
14879 #define DDRPHY_PLLCR0_GSHIFT_MASK                (0x1000U)
14880 #define DDRPHY_PLLCR0_GSHIFT_SHIFT               (12U)
14881 /*! GSHIFT - Gear Shift
14882  */
14883 #define DDRPHY_PLLCR0_GSHIFT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_GSHIFT_SHIFT)) & DDRPHY_PLLCR0_GSHIFT_MASK)
14884 #define DDRPHY_PLLCR0_CPIC_MASK                  (0x1E000U)
14885 #define DDRPHY_PLLCR0_CPIC_SHIFT                 (13U)
14886 /*! CPIC - Charge Pump Integrating Current Control
14887  */
14888 #define DDRPHY_PLLCR0_CPIC(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_CPIC_SHIFT)) & DDRPHY_PLLCR0_CPIC_MASK)
14889 #define DDRPHY_PLLCR0_CPPC_MASK                  (0x7E0000U)
14890 #define DDRPHY_PLLCR0_CPPC_SHIFT                 (17U)
14891 /*! CPPC - Charge Pump Proportional Current Control
14892  */
14893 #define DDRPHY_PLLCR0_CPPC(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_CPPC_SHIFT)) & DDRPHY_PLLCR0_CPPC_MASK)
14894 #define DDRPHY_PLLCR0_RLOCKM_MASK                (0x800000U)
14895 #define DDRPHY_PLLCR0_RLOCKM_SHIFT               (23U)
14896 /*! RLOCKM - Relock Mode
14897  */
14898 #define DDRPHY_PLLCR0_RLOCKM(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_RLOCKM_SHIFT)) & DDRPHY_PLLCR0_RLOCKM_MASK)
14899 #define DDRPHY_PLLCR0_FRQSEL_MASK                (0xF000000U)
14900 #define DDRPHY_PLLCR0_FRQSEL_SHIFT               (24U)
14901 /*! FRQSEL - PLL Frequency Select
14902  */
14903 #define DDRPHY_PLLCR0_FRQSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_FRQSEL_SHIFT)) & DDRPHY_PLLCR0_FRQSEL_MASK)
14904 #define DDRPHY_PLLCR0_RSTOPM_MASK                (0x10000000U)
14905 #define DDRPHY_PLLCR0_RSTOPM_SHIFT               (28U)
14906 /*! RSTOPM - Reference Stop Mode
14907  */
14908 #define DDRPHY_PLLCR0_RSTOPM(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_RSTOPM_SHIFT)) & DDRPHY_PLLCR0_RSTOPM_MASK)
14909 #define DDRPHY_PLLCR0_PLLPD_MASK                 (0x20000000U)
14910 #define DDRPHY_PLLCR0_PLLPD_SHIFT                (29U)
14911 /*! PLLPD - PLL Power Down
14912  */
14913 #define DDRPHY_PLLCR0_PLLPD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_PLLPD_SHIFT)) & DDRPHY_PLLCR0_PLLPD_MASK)
14914 #define DDRPHY_PLLCR0_PLLRST_MASK                (0x40000000U)
14915 #define DDRPHY_PLLCR0_PLLRST_SHIFT               (30U)
14916 /*! PLLRST - PLL Reset
14917  */
14918 #define DDRPHY_PLLCR0_PLLRST(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_PLLRST_SHIFT)) & DDRPHY_PLLCR0_PLLRST_MASK)
14919 #define DDRPHY_PLLCR0_PLLBYP_MASK                (0x80000000U)
14920 #define DDRPHY_PLLCR0_PLLBYP_SHIFT               (31U)
14921 /*! PLLBYP - PLL Bypass
14922  */
14923 #define DDRPHY_PLLCR0_PLLBYP(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_PLLBYP_SHIFT)) & DDRPHY_PLLCR0_PLLBYP_MASK)
14924 /*! @} */
14925 
14926 /*! @name PLLCR1 - PLL Control Register 1 (Type B PLL Only) */
14927 /*! @{ */
14928 #define DDRPHY_PLLCR1_LOCKDS_MASK                (0x1U)
14929 #define DDRPHY_PLLCR1_LOCKDS_SHIFT               (0U)
14930 /*! LOCKDS - Lock Detector Select
14931  */
14932 #define DDRPHY_PLLCR1_LOCKDS(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_LOCKDS_SHIFT)) & DDRPHY_PLLCR1_LOCKDS_MASK)
14933 #define DDRPHY_PLLCR1_LOCKCS_MASK                (0x2U)
14934 #define DDRPHY_PLLCR1_LOCKCS_SHIFT               (1U)
14935 /*! LOCKCS - Lock Detector Counter Select
14936  */
14937 #define DDRPHY_PLLCR1_LOCKCS(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_LOCKCS_SHIFT)) & DDRPHY_PLLCR1_LOCKCS_MASK)
14938 #define DDRPHY_PLLCR1_LOCKPS_MASK                (0x4U)
14939 #define DDRPHY_PLLCR1_LOCKPS_SHIFT               (2U)
14940 /*! LOCKPS - Lock Detector Phase Select
14941  */
14942 #define DDRPHY_PLLCR1_LOCKPS(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_LOCKPS_SHIFT)) & DDRPHY_PLLCR1_LOCKPS_MASK)
14943 #define DDRPHY_PLLCR1_BYPVDD_MASK                (0x8U)
14944 #define DDRPHY_PLLCR1_BYPVDD_SHIFT               (3U)
14945 /*! BYPVDD - PLL VDD voltage level control
14946  */
14947 #define DDRPHY_PLLCR1_BYPVDD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_BYPVDD_SHIFT)) & DDRPHY_PLLCR1_BYPVDD_MASK)
14948 #define DDRPHY_PLLCR1_BYPVREGDIG_MASK            (0x10U)
14949 #define DDRPHY_PLLCR1_BYPVREGDIG_SHIFT           (4U)
14950 /*! BYPVREGDIG - Bypass PLL vreg_dig
14951  */
14952 #define DDRPHY_PLLCR1_BYPVREGDIG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_PLLCR1_BYPVREGDIG_MASK)
14953 #define DDRPHY_PLLCR1_BYPVREGCP_MASK             (0x20U)
14954 #define DDRPHY_PLLCR1_BYPVREGCP_SHIFT            (5U)
14955 /*! BYPVREGCP - Bypass PLL vreg_cp
14956  */
14957 #define DDRPHY_PLLCR1_BYPVREGCP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_PLLCR1_BYPVREGCP_MASK)
14958 #define DDRPHY_PLLCR1_RESERVED_15_6_MASK         (0xFFC0U)
14959 #define DDRPHY_PLLCR1_RESERVED_15_6_SHIFT        (6U)
14960 /*! RESERVED_15_6 - Reserved. Return zeroes on reads.
14961  */
14962 #define DDRPHY_PLLCR1_RESERVED_15_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_RESERVED_15_6_SHIFT)) & DDRPHY_PLLCR1_RESERVED_15_6_MASK)
14963 #define DDRPHY_PLLCR1_PLLPROG_MASK               (0xFFFF0000U)
14964 #define DDRPHY_PLLCR1_PLLPROG_SHIFT              (16U)
14965 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
14966  */
14967 #define DDRPHY_PLLCR1_PLLPROG(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_PLLPROG_SHIFT)) & DDRPHY_PLLCR1_PLLPROG_MASK)
14968 /*! @} */
14969 
14970 /*! @name PLLCR2 - PLL Control Register 2 (Type B PLL Only) */
14971 /*! @{ */
14972 #define DDRPHY_PLLCR2_PLLCTRL_31_0_MASK          (0xFFFFFFFFU)
14973 #define DDRPHY_PLLCR2_PLLCTRL_31_0_SHIFT         (0U)
14974 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
14975  */
14976 #define DDRPHY_PLLCR2_PLLCTRL_31_0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_PLLCR2_PLLCTRL_31_0_MASK)
14977 /*! @} */
14978 
14979 /*! @name PLLCR3 - PLL Control Register 3 (Type B PLL Only) */
14980 /*! @{ */
14981 #define DDRPHY_PLLCR3_PLLCTRL_63_32_MASK         (0xFFFFFFFFU)
14982 #define DDRPHY_PLLCR3_PLLCTRL_63_32_SHIFT        (0U)
14983 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
14984  */
14985 #define DDRPHY_PLLCR3_PLLCTRL_63_32(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_PLLCR3_PLLCTRL_63_32_MASK)
14986 /*! @} */
14987 
14988 /*! @name PLLCR4 - PLL Control Register 4 (Type B PLL Only) */
14989 /*! @{ */
14990 #define DDRPHY_PLLCR4_PLLCTRL_95_64_MASK         (0xFFFFFFFFU)
14991 #define DDRPHY_PLLCR4_PLLCTRL_95_64_SHIFT        (0U)
14992 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
14993  */
14994 #define DDRPHY_PLLCR4_PLLCTRL_95_64(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_PLLCR4_PLLCTRL_95_64_MASK)
14995 /*! @} */
14996 
14997 /*! @name PLLCR5 - PLL Control Register 5 (Type B PLL Only) */
14998 /*! @{ */
14999 #define DDRPHY_PLLCR5_PLLCTRL_103_96_MASK        (0xFFU)
15000 #define DDRPHY_PLLCR5_PLLCTRL_103_96_SHIFT       (0U)
15001 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
15002  */
15003 #define DDRPHY_PLLCR5_PLLCTRL_103_96(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_PLLCR5_PLLCTRL_103_96_MASK)
15004 #define DDRPHY_PLLCR5_RESERVED_31_8_MASK         (0xFFFFFF00U)
15005 #define DDRPHY_PLLCR5_RESERVED_31_8_SHIFT        (8U)
15006 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
15007  */
15008 #define DDRPHY_PLLCR5_RESERVED_31_8(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_PLLCR5_RESERVED_31_8_MASK)
15009 /*! @} */
15010 
15011 /*! @name DXCCR - DATX8 Common Configuration Register */
15012 /*! @{ */
15013 #define DDRPHY_DXCCR_RESERVED_2_0_MASK           (0x7U)
15014 #define DDRPHY_DXCCR_RESERVED_2_0_SHIFT          (0U)
15015 /*! RESERVED_2_0 - Reserved. Return zeroes on reads
15016  */
15017 #define DDRPHY_DXCCR_RESERVED_2_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RESERVED_2_0_SHIFT)) & DDRPHY_DXCCR_RESERVED_2_0_MASK)
15018 #define DDRPHY_DXCCR_DQS2DQMPER_MASK             (0x78U)
15019 #define DDRPHY_DXCCR_DQS2DQMPER_SHIFT            (3U)
15020 /*! DQS2DQMPER - Write DQS2DQ Training Measurement Period
15021  */
15022 #define DDRPHY_DXCCR_DQS2DQMPER(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_DQS2DQMPER_SHIFT)) & DDRPHY_DXCCR_DQS2DQMPER_MASK)
15023 #define DDRPHY_DXCCR_RESERVED_28_7_MASK          (0x1FFFFF80U)
15024 #define DDRPHY_DXCCR_RESERVED_28_7_SHIFT         (7U)
15025 /*! RESERVED_28_7 - Reserved. Return zeroes on reads
15026  */
15027 #define DDRPHY_DXCCR_RESERVED_28_7(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RESERVED_28_7_SHIFT)) & DDRPHY_DXCCR_RESERVED_28_7_MASK)
15028 #define DDRPHY_DXCCR_RKLOOP_MASK                 (0x20000000U)
15029 #define DDRPHY_DXCCR_RKLOOP_SHIFT                (29U)
15030 /*! RKLOOP - Rank looping (per-rank eye centering) enable
15031  */
15032 #define DDRPHY_DXCCR_RKLOOP(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RKLOOP_SHIFT)) & DDRPHY_DXCCR_RKLOOP_MASK)
15033 #define DDRPHY_DXCCR_RESERVED_31_30_MASK         (0xC0000000U)
15034 #define DDRPHY_DXCCR_RESERVED_31_30_SHIFT        (30U)
15035 /*! RESERVED_31_30 - Reserved. Return zeroes on reads
15036  */
15037 #define DDRPHY_DXCCR_RESERVED_31_30(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RESERVED_31_30_SHIFT)) & DDRPHY_DXCCR_RESERVED_31_30_MASK)
15038 /*! @} */
15039 
15040 /*! @name DSGCR - DDR System General Configuration Register */
15041 /*! @{ */
15042 #define DDRPHY_DSGCR_PUREN_MASK                  (0x1U)
15043 #define DDRPHY_DSGCR_PUREN_SHIFT                 (0U)
15044 /*! PUREN - PHY Update Request Enable
15045  */
15046 #define DDRPHY_DSGCR_PUREN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_PUREN_SHIFT)) & DDRPHY_DSGCR_PUREN_MASK)
15047 #define DDRPHY_DSGCR_MREN_MASK                   (0x2U)
15048 #define DDRPHY_DSGCR_MREN_SHIFT                  (1U)
15049 /*! MREN - Master Request Enable
15050  */
15051 #define DDRPHY_DSGCR_MREN(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_MREN_SHIFT)) & DDRPHY_DSGCR_MREN_MASK)
15052 #define DDRPHY_DSGCR_CTLZUEN_MASK                (0x4U)
15053 #define DDRPHY_DSGCR_CTLZUEN_SHIFT               (2U)
15054 /*! CTLZUEN - Controller Impedance Update Enable
15055  */
15056 #define DDRPHY_DSGCR_CTLZUEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_CTLZUEN_SHIFT)) & DDRPHY_DSGCR_CTLZUEN_MASK)
15057 #define DDRPHY_DSGCR_MSTRVER_MASK                (0x8U)
15058 #define DDRPHY_DSGCR_MSTRVER_SHIFT               (3U)
15059 /*! MSTRVER - Master Version
15060  */
15061 #define DDRPHY_DSGCR_MSTRVER(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_MSTRVER_SHIFT)) & DDRPHY_DSGCR_MSTRVER_MASK)
15062 #define DDRPHY_DSGCR_RESERVED_4_MASK             (0x10U)
15063 #define DDRPHY_DSGCR_RESERVED_4_SHIFT            (4U)
15064 /*! RESERVED_4 - Reserved. Return zeroes on reads
15065  */
15066 #define DDRPHY_DSGCR_RESERVED_4(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_4_SHIFT)) & DDRPHY_DSGCR_RESERVED_4_MASK)
15067 #define DDRPHY_DSGCR_CUAEN_MASK                  (0x20U)
15068 #define DDRPHY_DSGCR_CUAEN_SHIFT                 (5U)
15069 /*! CUAEN - Controller Update Acknowledge Enable
15070  */
15071 #define DDRPHY_DSGCR_CUAEN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_CUAEN_SHIFT)) & DDRPHY_DSGCR_CUAEN_MASK)
15072 #define DDRPHY_DSGCR_PUAD_MASK                   (0xFC0U)
15073 #define DDRPHY_DSGCR_PUAD_SHIFT                  (6U)
15074 /*! PUAD - PHY Update Acknowledge Delay
15075  */
15076 #define DDRPHY_DSGCR_PUAD(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_PUAD_SHIFT)) & DDRPHY_DSGCR_PUAD_MASK)
15077 #define DDRPHY_DSGCR_DTOODT_MASK                 (0x1000U)
15078 #define DDRPHY_DSGCR_DTOODT_SHIFT                (12U)
15079 /*! DTOODT - DTO On-Die Termination
15080  */
15081 #define DDRPHY_DSGCR_DTOODT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOODT_SHIFT)) & DDRPHY_DSGCR_DTOODT_MASK)
15082 #define DDRPHY_DSGCR_RESERVED_13_MASK            (0x2000U)
15083 #define DDRPHY_DSGCR_RESERVED_13_SHIFT           (13U)
15084 /*! RESERVED_13 - Reserved. Return zeroes on reads
15085  */
15086 #define DDRPHY_DSGCR_RESERVED_13(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_13_SHIFT)) & DDRPHY_DSGCR_RESERVED_13_MASK)
15087 #define DDRPHY_DSGCR_DTOPDR_MASK                 (0x4000U)
15088 #define DDRPHY_DSGCR_DTOPDR_SHIFT                (14U)
15089 /*! DTOPDR - DTO Power Down Receiver
15090  */
15091 #define DDRPHY_DSGCR_DTOPDR(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOPDR_SHIFT)) & DDRPHY_DSGCR_DTOPDR_MASK)
15092 #define DDRPHY_DSGCR_DTOIOM_MASK                 (0x8000U)
15093 #define DDRPHY_DSGCR_DTOIOM_SHIFT                (15U)
15094 /*! DTOIOM - DTO I/O Mode
15095  */
15096 #define DDRPHY_DSGCR_DTOIOM(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOIOM_SHIFT)) & DDRPHY_DSGCR_DTOIOM_MASK)
15097 #define DDRPHY_DSGCR_DTOOE_MASK                  (0x10000U)
15098 #define DDRPHY_DSGCR_DTOOE_SHIFT                 (16U)
15099 /*! DTOOE - DTO Output Enable
15100  */
15101 #define DDRPHY_DSGCR_DTOOE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOOE_SHIFT)) & DDRPHY_DSGCR_DTOOE_MASK)
15102 #define DDRPHY_DSGCR_ATOAE_MASK                  (0x20000U)
15103 #define DDRPHY_DSGCR_ATOAE_SHIFT                 (17U)
15104 /*! ATOAE - ATO Analog Test Enable
15105  */
15106 #define DDRPHY_DSGCR_ATOAE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_ATOAE_SHIFT)) & DDRPHY_DSGCR_ATOAE_MASK)
15107 #define DDRPHY_DSGCR_RESERVED_18_MASK            (0x40000U)
15108 #define DDRPHY_DSGCR_RESERVED_18_SHIFT           (18U)
15109 /*! RESERVED_18 - Reserved. Return zeroes on reads.
15110  */
15111 #define DDRPHY_DSGCR_RESERVED_18(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_18_SHIFT)) & DDRPHY_DSGCR_RESERVED_18_MASK)
15112 #define DDRPHY_DSGCR_SDRMODE_MASK                (0x180000U)
15113 #define DDRPHY_DSGCR_SDRMODE_SHIFT               (19U)
15114 /*! SDRMODE - Single Data Rate Mode
15115  */
15116 #define DDRPHY_DSGCR_SDRMODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_SDRMODE_SHIFT)) & DDRPHY_DSGCR_SDRMODE_MASK)
15117 #define DDRPHY_DSGCR_RSTOE_MASK                  (0x200000U)
15118 #define DDRPHY_DSGCR_RSTOE_SHIFT                 (21U)
15119 /*! RSTOE - SDRAM Reset Output Enable
15120  */
15121 #define DDRPHY_DSGCR_RSTOE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RSTOE_SHIFT)) & DDRPHY_DSGCR_RSTOE_MASK)
15122 #define DDRPHY_DSGCR_RESERVED_22_MASK            (0x400000U)
15123 #define DDRPHY_DSGCR_RESERVED_22_SHIFT           (22U)
15124 /*! RESERVED_22 - Reserved. Return zeroes on reads.
15125  */
15126 #define DDRPHY_DSGCR_RESERVED_22(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_22_SHIFT)) & DDRPHY_DSGCR_RESERVED_22_MASK)
15127 #define DDRPHY_DSGCR_PHYZUEN_MASK                (0x800000U)
15128 #define DDRPHY_DSGCR_PHYZUEN_SHIFT               (23U)
15129 /*! PHYZUEN - PHY Impedance Update Enable
15130  */
15131 #define DDRPHY_DSGCR_PHYZUEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_PHYZUEN_SHIFT)) & DDRPHY_DSGCR_PHYZUEN_MASK)
15132 #define DDRPHY_DSGCR_RDBICL_MASK                 (0x7000000U)
15133 #define DDRPHY_DSGCR_RDBICL_SHIFT                (24U)
15134 /*! RDBICL - When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.
15135  */
15136 #define DDRPHY_DSGCR_RDBICL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RDBICL_SHIFT)) & DDRPHY_DSGCR_RDBICL_MASK)
15137 #define DDRPHY_DSGCR_RDBICLSEL_MASK              (0x8000000U)
15138 #define DDRPHY_DSGCR_RDBICLSEL_SHIFT             (27U)
15139 /*! RDBICLSEL - When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1,
15140  *    calculation will use RDBICL, otherwise use default calculation.
15141  */
15142 #define DDRPHY_DSGCR_RDBICLSEL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RDBICLSEL_SHIFT)) & DDRPHY_DSGCR_RDBICLSEL_MASK)
15143 #define DDRPHY_DSGCR_RESERVED_31_28_MASK         (0xF0000000U)
15144 #define DDRPHY_DSGCR_RESERVED_31_28_SHIFT        (28U)
15145 /*! RESERVED_31_28 - Reserved. Return zeroes on reads.
15146  */
15147 #define DDRPHY_DSGCR_RESERVED_31_28(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_31_28_SHIFT)) & DDRPHY_DSGCR_RESERVED_31_28_MASK)
15148 /*! @} */
15149 
15150 /*! @name ODTCR - ODT Configuration Register */
15151 /*! @{ */
15152 #define DDRPHY_ODTCR_RDODT_MASK                  (0x1U)
15153 #define DDRPHY_ODTCR_RDODT_SHIFT                 (0U)
15154 /*! RDODT - Read ODT.
15155  */
15156 #define DDRPHY_ODTCR_RDODT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RDODT_SHIFT)) & DDRPHY_ODTCR_RDODT_MASK)
15157 #define DDRPHY_ODTCR_RDODT_RSVD_MASK             (0xFFEU)
15158 #define DDRPHY_ODTCR_RDODT_RSVD_SHIFT            (1U)
15159 /*! RDODT_RSVD - Reserved. Return zeroes on reads.
15160  */
15161 #define DDRPHY_ODTCR_RDODT_RSVD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RDODT_RSVD_SHIFT)) & DDRPHY_ODTCR_RDODT_RSVD_MASK)
15162 #define DDRPHY_ODTCR_RESERVED_15_12_MASK         (0xF000U)
15163 #define DDRPHY_ODTCR_RESERVED_15_12_SHIFT        (12U)
15164 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
15165  */
15166 #define DDRPHY_ODTCR_RESERVED_15_12(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RESERVED_15_12_SHIFT)) & DDRPHY_ODTCR_RESERVED_15_12_MASK)
15167 #define DDRPHY_ODTCR_WRODT_MASK                  (0x10000U)
15168 #define DDRPHY_ODTCR_WRODT_SHIFT                 (16U)
15169 /*! WRODT - Write ODT.
15170  */
15171 #define DDRPHY_ODTCR_WRODT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_WRODT_SHIFT)) & DDRPHY_ODTCR_WRODT_MASK)
15172 #define DDRPHY_ODTCR_WRODT_RSVD_MASK             (0xFFE0000U)
15173 #define DDRPHY_ODTCR_WRODT_RSVD_SHIFT            (17U)
15174 /*! WRODT_RSVD - Reserved. Return zeroes on reads.
15175  */
15176 #define DDRPHY_ODTCR_WRODT_RSVD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_WRODT_RSVD_SHIFT)) & DDRPHY_ODTCR_WRODT_RSVD_MASK)
15177 #define DDRPHY_ODTCR_RESERVED_31_28_MASK         (0xF0000000U)
15178 #define DDRPHY_ODTCR_RESERVED_31_28_SHIFT        (28U)
15179 /*! RESERVED_31_28 - Reserved. Return zeroes on reads.
15180  */
15181 #define DDRPHY_ODTCR_RESERVED_31_28(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RESERVED_31_28_SHIFT)) & DDRPHY_ODTCR_RESERVED_31_28_MASK)
15182 /*! @} */
15183 
15184 /*! @name AACR - Anti-Aging Control Register */
15185 /*! @{ */
15186 #define DDRPHY_AACR_AATR_MASK                    (0x3FFFFFFFU)
15187 #define DDRPHY_AACR_AATR_SHIFT                   (0U)
15188 /*! AATR - Anti-Aging Toggle Rate
15189  */
15190 #define DDRPHY_AACR_AATR(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_AACR_AATR_SHIFT)) & DDRPHY_AACR_AATR_MASK)
15191 #define DDRPHY_AACR_AAENC_MASK                   (0x40000000U)
15192 #define DDRPHY_AACR_AAENC_SHIFT                  (30U)
15193 /*! AAENC - Anti-Aging Enable Control
15194  */
15195 #define DDRPHY_AACR_AAENC(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_AACR_AAENC_SHIFT)) & DDRPHY_AACR_AAENC_MASK)
15196 #define DDRPHY_AACR_AAOENC_MASK                  (0x80000000U)
15197 #define DDRPHY_AACR_AAOENC_SHIFT                 (31U)
15198 /*! AAOENC - Anti-Aging PAD Output Enable Control
15199  */
15200 #define DDRPHY_AACR_AAOENC(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_AACR_AAOENC_SHIFT)) & DDRPHY_AACR_AAOENC_MASK)
15201 /*! @} */
15202 
15203 /*! @name GPR0 - General Purpose Register 0 */
15204 /*! @{ */
15205 #define DDRPHY_GPR0_GPR0_MASK                    (0xFFFFFFFFU)
15206 #define DDRPHY_GPR0_GPR0_SHIFT                   (0U)
15207 /*! GPR0 - General Purpose Register 0
15208  */
15209 #define DDRPHY_GPR0_GPR0(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_GPR0_GPR0_SHIFT)) & DDRPHY_GPR0_GPR0_MASK)
15210 /*! @} */
15211 
15212 /*! @name GPR1 - General Purpose Register 1 */
15213 /*! @{ */
15214 #define DDRPHY_GPR1_GPR1_MASK                    (0xFFFFFFFFU)
15215 #define DDRPHY_GPR1_GPR1_SHIFT                   (0U)
15216 /*! GPR1 - General Purpose Register 1
15217  */
15218 #define DDRPHY_GPR1_GPR1(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_GPR1_GPR1_SHIFT)) & DDRPHY_GPR1_GPR1_MASK)
15219 /*! @} */
15220 
15221 /*! @name DCR - DRAM Configuration Register */
15222 /*! @{ */
15223 #define DDRPHY_DCR_DDRMD_MASK                    (0x7U)
15224 #define DDRPHY_DCR_DDRMD_SHIFT                   (0U)
15225 /*! DDRMD - DDR Mode
15226  */
15227 #define DDRPHY_DCR_DDRMD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDRMD_SHIFT)) & DDRPHY_DCR_DDRMD_MASK)
15228 #define DDRPHY_DCR_DDR8BNK_MASK                  (0x8U)
15229 #define DDRPHY_DCR_DDR8BNK_SHIFT                 (3U)
15230 /*! DDR8BNK - DDR 8-Bank
15231  */
15232 #define DDRPHY_DCR_DDR8BNK(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDR8BNK_SHIFT)) & DDRPHY_DCR_DDR8BNK_MASK)
15233 #define DDRPHY_DCR_PDQ_MASK                      (0x70U)
15234 #define DDRPHY_DCR_PDQ_SHIFT                     (4U)
15235 /*! PDQ - Primary DQ (DDR3 Only)
15236  */
15237 #define DDRPHY_DCR_PDQ(x)                        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_PDQ_SHIFT)) & DDRPHY_DCR_PDQ_MASK)
15238 #define DDRPHY_DCR_MPRDQ_MASK                    (0x80U)
15239 #define DDRPHY_DCR_MPRDQ_SHIFT                   (7U)
15240 /*! MPRDQ - Multi-Purpose Register (MPR) DQ (DDR3 Only)
15241  */
15242 #define DDRPHY_DCR_MPRDQ(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_MPRDQ_SHIFT)) & DDRPHY_DCR_MPRDQ_MASK)
15243 #define DDRPHY_DCR_DDRTYPE_MASK                  (0x300U)
15244 #define DDRPHY_DCR_DDRTYPE_SHIFT                 (8U)
15245 /*! DDRTYPE - DDR Type
15246  */
15247 #define DDRPHY_DCR_DDRTYPE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDRTYPE_SHIFT)) & DDRPHY_DCR_DDRTYPE_MASK)
15248 #define DDRPHY_DCR_BYTEMASK_MASK                 (0x3FC00U)
15249 #define DDRPHY_DCR_BYTEMASK_SHIFT                (10U)
15250 /*! BYTEMASK - Byte Mask
15251  */
15252 #define DDRPHY_DCR_BYTEMASK(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_BYTEMASK_SHIFT)) & DDRPHY_DCR_BYTEMASK_MASK)
15253 #define DDRPHY_DCR_RESERVED_26_18_MASK           (0x7FC0000U)
15254 #define DDRPHY_DCR_RESERVED_26_18_SHIFT          (18U)
15255 /*! RESERVED_26_18 - Reserved. Return zeroes on reads.
15256  */
15257 #define DDRPHY_DCR_RESERVED_26_18(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_RESERVED_26_18_SHIFT)) & DDRPHY_DCR_RESERVED_26_18_MASK)
15258 #define DDRPHY_DCR_NOSRA_MASK                    (0x8000000U)
15259 #define DDRPHY_DCR_NOSRA_SHIFT                   (27U)
15260 /*! NOSRA - No Simultaneous Rank Access
15261  */
15262 #define DDRPHY_DCR_NOSRA(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_NOSRA_SHIFT)) & DDRPHY_DCR_NOSRA_MASK)
15263 #define DDRPHY_DCR_DDR2T_MASK                    (0x10000000U)
15264 #define DDRPHY_DCR_DDR2T_SHIFT                   (28U)
15265 /*! DDR2T - DDR 2T Timing
15266  */
15267 #define DDRPHY_DCR_DDR2T(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDR2T_SHIFT)) & DDRPHY_DCR_DDR2T_MASK)
15268 #define DDRPHY_DCR_UDIMM_MASK                    (0x20000000U)
15269 #define DDRPHY_DCR_UDIMM_SHIFT                   (29U)
15270 /*! UDIMM - Un-buffered DIMM Address Mirroring
15271  */
15272 #define DDRPHY_DCR_UDIMM(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_UDIMM_SHIFT)) & DDRPHY_DCR_UDIMM_MASK)
15273 #define DDRPHY_DCR_UBG_MASK                      (0x40000000U)
15274 #define DDRPHY_DCR_UBG_SHIFT                     (30U)
15275 /*! UBG - Un-used Bank Group
15276  */
15277 #define DDRPHY_DCR_UBG(x)                        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_UBG_SHIFT)) & DDRPHY_DCR_UBG_MASK)
15278 #define DDRPHY_DCR_GEARDN_MASK                   (0x80000000U)
15279 #define DDRPHY_DCR_GEARDN_SHIFT                  (31U)
15280 /*! GEARDN - DDR4 Gear Down Timing.
15281  */
15282 #define DDRPHY_DCR_GEARDN(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_GEARDN_SHIFT)) & DDRPHY_DCR_GEARDN_MASK)
15283 /*! @} */
15284 
15285 /*! @name DTPR0 - DRAM Timing Parameters Register 0 */
15286 /*! @{ */
15287 #define DDRPHY_DTPR0_tRTP_MASK                   (0x1FU)
15288 #define DDRPHY_DTPR0_tRTP_SHIFT                  (0U)
15289 /*! tRTP - Internal read to precharge command delay
15290  */
15291 #define DDRPHY_DTPR0_tRTP(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRTP_SHIFT)) & DDRPHY_DTPR0_tRTP_MASK)
15292 #define DDRPHY_DTPR0_RESERVED_7_5_MASK           (0xE0U)
15293 #define DDRPHY_DTPR0_RESERVED_7_5_SHIFT          (5U)
15294 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
15295  */
15296 #define DDRPHY_DTPR0_RESERVED_7_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR0_RESERVED_7_5_MASK)
15297 #define DDRPHY_DTPR0_tRP_MASK                    (0x7F00U)
15298 #define DDRPHY_DTPR0_tRP_SHIFT                   (8U)
15299 /*! tRP - Precharge command period
15300  */
15301 #define DDRPHY_DTPR0_tRP(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRP_SHIFT)) & DDRPHY_DTPR0_tRP_MASK)
15302 #define DDRPHY_DTPR0_RESERVED_15_MASK            (0x8000U)
15303 #define DDRPHY_DTPR0_RESERVED_15_SHIFT           (15U)
15304 /*! RESERVED_15 - Reserved. Return zeroes on reads.
15305  */
15306 #define DDRPHY_DTPR0_RESERVED_15(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_15_SHIFT)) & DDRPHY_DTPR0_RESERVED_15_MASK)
15307 #define DDRPHY_DTPR0_tRAS_MASK                   (0x7F0000U)
15308 #define DDRPHY_DTPR0_tRAS_SHIFT                  (16U)
15309 /*! tRAS - Activate to precharge command delay
15310  */
15311 #define DDRPHY_DTPR0_tRAS(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRAS_SHIFT)) & DDRPHY_DTPR0_tRAS_MASK)
15312 #define DDRPHY_DTPR0_RESERVED_23_MASK            (0x800000U)
15313 #define DDRPHY_DTPR0_RESERVED_23_SHIFT           (23U)
15314 /*! RESERVED_23 - Reserved. Return zeroes on reads.
15315  */
15316 #define DDRPHY_DTPR0_RESERVED_23(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_23_SHIFT)) & DDRPHY_DTPR0_RESERVED_23_MASK)
15317 #define DDRPHY_DTPR0_tRRD_MASK                   (0x1F000000U)
15318 #define DDRPHY_DTPR0_tRRD_SHIFT                  (24U)
15319 /*! tRRD - Activate to activate command delay (different banks)
15320  */
15321 #define DDRPHY_DTPR0_tRRD(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRRD_SHIFT)) & DDRPHY_DTPR0_tRRD_MASK)
15322 #define DDRPHY_DTPR0_RESERVED_31_29_MASK         (0xE0000000U)
15323 #define DDRPHY_DTPR0_RESERVED_31_29_SHIFT        (29U)
15324 /*! RESERVED_31_29 - Reserved. Return zeroes on reads.
15325  */
15326 #define DDRPHY_DTPR0_RESERVED_31_29(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_31_29_SHIFT)) & DDRPHY_DTPR0_RESERVED_31_29_MASK)
15327 /*! @} */
15328 
15329 /*! @name DTPR1 - DRAM Timing Parameters Register 1 */
15330 /*! @{ */
15331 #define DDRPHY_DTPR1_tMRD_MASK                   (0x1FU)
15332 #define DDRPHY_DTPR1_tMRD_SHIFT                  (0U)
15333 /*! tMRD - Load mode cycle time
15334  */
15335 #define DDRPHY_DTPR1_tMRD(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tMRD_SHIFT)) & DDRPHY_DTPR1_tMRD_MASK)
15336 #define DDRPHY_DTPR1_RESERVED_7_5_MASK           (0xE0U)
15337 #define DDRPHY_DTPR1_RESERVED_7_5_SHIFT          (5U)
15338 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
15339  */
15340 #define DDRPHY_DTPR1_RESERVED_7_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR1_RESERVED_7_5_MASK)
15341 #define DDRPHY_DTPR1_tMOD_MASK                   (0x700U)
15342 #define DDRPHY_DTPR1_tMOD_SHIFT                  (8U)
15343 /*! tMOD - Load mode update delay (DDR4 and DDR3 only)
15344  */
15345 #define DDRPHY_DTPR1_tMOD(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tMOD_SHIFT)) & DDRPHY_DTPR1_tMOD_MASK)
15346 #define DDRPHY_DTPR1_RESERVED_15_11_MASK         (0xF800U)
15347 #define DDRPHY_DTPR1_RESERVED_15_11_SHIFT        (11U)
15348 /*! RESERVED_15_11 - Reserved. Return zeroes on reads.
15349  */
15350 #define DDRPHY_DTPR1_RESERVED_15_11(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_15_11_SHIFT)) & DDRPHY_DTPR1_RESERVED_15_11_MASK)
15351 #define DDRPHY_DTPR1_tFAW_MASK                   (0x7F0000U)
15352 #define DDRPHY_DTPR1_tFAW_SHIFT                  (16U)
15353 /*! tFAW - 4-bank activate period
15354  */
15355 #define DDRPHY_DTPR1_tFAW(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tFAW_SHIFT)) & DDRPHY_DTPR1_tFAW_MASK)
15356 #define DDRPHY_DTPR1_RESERVED_23_MASK            (0x800000U)
15357 #define DDRPHY_DTPR1_RESERVED_23_SHIFT           (23U)
15358 /*! RESERVED_23 - Reserved. Return zeroes on reads.
15359  */
15360 #define DDRPHY_DTPR1_RESERVED_23(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_23_SHIFT)) & DDRPHY_DTPR1_RESERVED_23_MASK)
15361 #define DDRPHY_DTPR1_tWLMRD_MASK                 (0x7F000000U)
15362 #define DDRPHY_DTPR1_tWLMRD_SHIFT                (24U)
15363 /*! tWLMRD - Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
15364  */
15365 #define DDRPHY_DTPR1_tWLMRD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tWLMRD_SHIFT)) & DDRPHY_DTPR1_tWLMRD_MASK)
15366 #define DDRPHY_DTPR1_RESERVED_31_MASK            (0x80000000U)
15367 #define DDRPHY_DTPR1_RESERVED_31_SHIFT           (31U)
15368 /*! RESERVED_31 - Reserved. Return zeroes on reads.
15369  */
15370 #define DDRPHY_DTPR1_RESERVED_31(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_31_SHIFT)) & DDRPHY_DTPR1_RESERVED_31_MASK)
15371 /*! @} */
15372 
15373 /*! @name DTPR2 - DRAM Timing Parameters Register 2 */
15374 /*! @{ */
15375 #define DDRPHY_DTPR2_tXS_MASK                    (0x3FFU)
15376 #define DDRPHY_DTPR2_tXS_SHIFT                   (0U)
15377 /*! tXS - Self refresh exit delay
15378  */
15379 #define DDRPHY_DTPR2_tXS(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tXS_SHIFT)) & DDRPHY_DTPR2_tXS_MASK)
15380 #define DDRPHY_DTPR2_RESERVED_15_10_MASK         (0xFC00U)
15381 #define DDRPHY_DTPR2_RESERVED_15_10_SHIFT        (10U)
15382 /*! RESERVED_15_10 - Reserved. Return zeroes on reads.
15383  */
15384 #define DDRPHY_DTPR2_RESERVED_15_10(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_RESERVED_15_10_SHIFT)) & DDRPHY_DTPR2_RESERVED_15_10_MASK)
15385 #define DDRPHY_DTPR2_tCKE_MASK                   (0xF0000U)
15386 #define DDRPHY_DTPR2_tCKE_SHIFT                  (16U)
15387 /*! tCKE - CKE minimum pulse width
15388  */
15389 #define DDRPHY_DTPR2_tCKE(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tCKE_SHIFT)) & DDRPHY_DTPR2_tCKE_MASK)
15390 #define DDRPHY_DTPR2_tCMDCKE_MASK                (0xF00000U)
15391 #define DDRPHY_DTPR2_tCMDCKE_SHIFT               (20U)
15392 /*! tCMDCKE - Delay from Valid command to CKE Input low (LPDDR4 mode only)
15393  */
15394 #define DDRPHY_DTPR2_tCMDCKE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tCMDCKE_SHIFT)) & DDRPHY_DTPR2_tCMDCKE_MASK)
15395 #define DDRPHY_DTPR2_tRTODT_MASK                 (0x1000000U)
15396 #define DDRPHY_DTPR2_tRTODT_SHIFT                (24U)
15397 /*! tRTODT - Read to ODT delay (DDR3 only)
15398  */
15399 #define DDRPHY_DTPR2_tRTODT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tRTODT_SHIFT)) & DDRPHY_DTPR2_tRTODT_MASK)
15400 #define DDRPHY_DTPR2_RESERVED_27_25_MASK         (0xE000000U)
15401 #define DDRPHY_DTPR2_RESERVED_27_25_SHIFT        (25U)
15402 /*! RESERVED_27_25 - Reserved. Return zeroes on reads.
15403  */
15404 #define DDRPHY_DTPR2_RESERVED_27_25(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_RESERVED_27_25_SHIFT)) & DDRPHY_DTPR2_RESERVED_27_25_MASK)
15405 #define DDRPHY_DTPR2_tRTW_MASK                   (0x10000000U)
15406 #define DDRPHY_DTPR2_tRTW_SHIFT                  (28U)
15407 /*! tRTW - Read to Write command delay. Valid values are
15408  */
15409 #define DDRPHY_DTPR2_tRTW(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tRTW_SHIFT)) & DDRPHY_DTPR2_tRTW_MASK)
15410 #define DDRPHY_DTPR2_RESERVED_31_29_MASK         (0xE0000000U)
15411 #define DDRPHY_DTPR2_RESERVED_31_29_SHIFT        (29U)
15412 /*! RESERVED_31_29 - Reserved. Return zeroes on reads.
15413  */
15414 #define DDRPHY_DTPR2_RESERVED_31_29(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_RESERVED_31_29_SHIFT)) & DDRPHY_DTPR2_RESERVED_31_29_MASK)
15415 /*! @} */
15416 
15417 /*! @name DTPR3 - DRAM Timing Parameters Register 3 */
15418 /*! @{ */
15419 #define DDRPHY_DTPR3_TDQSCK_MASK                 (0x7U)
15420 #define DDRPHY_DTPR3_TDQSCK_SHIFT                (0U)
15421 /*! TDQSCK - DQS output access time from CK/CK# (LPDDR2/3 only)
15422  */
15423 #define DDRPHY_DTPR3_TDQSCK(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_TDQSCK_SHIFT)) & DDRPHY_DTPR3_TDQSCK_MASK)
15424 #define DDRPHY_DTPR3_RESERVED_7_3_MASK           (0xF8U)
15425 #define DDRPHY_DTPR3_RESERVED_7_3_SHIFT          (3U)
15426 /*! RESERVED_7_3 - Reserved. Return zeroes on reads.
15427  */
15428 #define DDRPHY_DTPR3_RESERVED_7_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_RESERVED_7_3_SHIFT)) & DDRPHY_DTPR3_RESERVED_7_3_MASK)
15429 #define DDRPHY_DTPR3_tDQSCKmax_MASK              (0xF00U)
15430 #define DDRPHY_DTPR3_tDQSCKmax_SHIFT             (8U)
15431 /*! tDQSCKmax - Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
15432  */
15433 #define DDRPHY_DTPR3_tDQSCKmax(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tDQSCKmax_SHIFT)) & DDRPHY_DTPR3_tDQSCKmax_MASK)
15434 #define DDRPHY_DTPR3_RESERVED_15_12_MASK         (0xF000U)
15435 #define DDRPHY_DTPR3_RESERVED_15_12_SHIFT        (12U)
15436 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
15437  */
15438 #define DDRPHY_DTPR3_RESERVED_15_12(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_RESERVED_15_12_SHIFT)) & DDRPHY_DTPR3_RESERVED_15_12_MASK)
15439 #define DDRPHY_DTPR3_tDLLK_MASK                  (0x3FF0000U)
15440 #define DDRPHY_DTPR3_tDLLK_SHIFT                 (16U)
15441 /*! tDLLK - DLL locking time
15442  */
15443 #define DDRPHY_DTPR3_tDLLK(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tDLLK_SHIFT)) & DDRPHY_DTPR3_tDLLK_MASK)
15444 #define DDRPHY_DTPR3_tCCD_MASK                   (0x1C000000U)
15445 #define DDRPHY_DTPR3_tCCD_SHIFT                  (26U)
15446 /*! tCCD - Read to read and write to write command delay
15447  */
15448 #define DDRPHY_DTPR3_tCCD(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tCCD_SHIFT)) & DDRPHY_DTPR3_tCCD_MASK)
15449 #define DDRPHY_DTPR3_tOFDx_MASK                  (0xE0000000U)
15450 #define DDRPHY_DTPR3_tOFDx_SHIFT                 (29U)
15451 /*! tOFDx - ODT turn-off delay extension
15452  */
15453 #define DDRPHY_DTPR3_tOFDx(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tOFDx_SHIFT)) & DDRPHY_DTPR3_tOFDx_MASK)
15454 /*! @} */
15455 
15456 /*! @name DTPR4 - DRAM Timing Parameters Register 4 */
15457 /*! @{ */
15458 #define DDRPHY_DTPR4_tXP_MASK                    (0x1FU)
15459 #define DDRPHY_DTPR4_tXP_SHIFT                   (0U)
15460 /*! tXP - Power down exit delay
15461  */
15462 #define DDRPHY_DTPR4_tXP(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tXP_SHIFT)) & DDRPHY_DTPR4_tXP_MASK)
15463 #define DDRPHY_DTPR4_RESERVED_7_5_MASK           (0xE0U)
15464 #define DDRPHY_DTPR4_RESERVED_7_5_SHIFT          (5U)
15465 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
15466  */
15467 #define DDRPHY_DTPR4_RESERVED_7_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR4_RESERVED_7_5_MASK)
15468 #define DDRPHY_DTPR4_tWLO_MASK                   (0x3F00U)
15469 #define DDRPHY_DTPR4_tWLO_SHIFT                  (8U)
15470 /*! tWLO - Write leveling output delay
15471  */
15472 #define DDRPHY_DTPR4_tWLO(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tWLO_SHIFT)) & DDRPHY_DTPR4_tWLO_MASK)
15473 #define DDRPHY_DTPR4_RESERVED_15_14_MASK         (0xC000U)
15474 #define DDRPHY_DTPR4_RESERVED_15_14_SHIFT        (14U)
15475 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
15476  */
15477 #define DDRPHY_DTPR4_RESERVED_15_14(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_15_14_SHIFT)) & DDRPHY_DTPR4_RESERVED_15_14_MASK)
15478 #define DDRPHY_DTPR4_tRFC_MASK                   (0x3FF0000U)
15479 #define DDRPHY_DTPR4_tRFC_SHIFT                  (16U)
15480 /*! tRFC - Refresh-to-Refresh
15481  */
15482 #define DDRPHY_DTPR4_tRFC(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tRFC_SHIFT)) & DDRPHY_DTPR4_tRFC_MASK)
15483 #define DDRPHY_DTPR4_RESERVED_27_26_MASK         (0xC000000U)
15484 #define DDRPHY_DTPR4_RESERVED_27_26_SHIFT        (26U)
15485 /*! RESERVED_27_26 - Reserved. Return zeroes on reads.
15486  */
15487 #define DDRPHY_DTPR4_RESERVED_27_26(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_27_26_SHIFT)) & DDRPHY_DTPR4_RESERVED_27_26_MASK)
15488 #define DDRPHY_DTPR4_tAOND_tAOFD_MASK            (0x30000000U)
15489 #define DDRPHY_DTPR4_tAOND_tAOFD_SHIFT           (28U)
15490 /*! tAOND_tAOFD - ODT turn-on/turn-off delays (DDR2 only)
15491  */
15492 #define DDRPHY_DTPR4_tAOND_tAOFD(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tAOND_tAOFD_SHIFT)) & DDRPHY_DTPR4_tAOND_tAOFD_MASK)
15493 #define DDRPHY_DTPR4_RESERVED_31_30_MASK         (0xC0000000U)
15494 #define DDRPHY_DTPR4_RESERVED_31_30_SHIFT        (30U)
15495 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
15496  */
15497 #define DDRPHY_DTPR4_RESERVED_31_30(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_31_30_SHIFT)) & DDRPHY_DTPR4_RESERVED_31_30_MASK)
15498 /*! @} */
15499 
15500 /*! @name DTPR5 - DRAM Timing Parameters Register 5 */
15501 /*! @{ */
15502 #define DDRPHY_DTPR5_tWTR_MASK                   (0x1FU)
15503 #define DDRPHY_DTPR5_tWTR_SHIFT                  (0U)
15504 /*! tWTR - Internal write to read command delay
15505  */
15506 #define DDRPHY_DTPR5_tWTR(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_tWTR_SHIFT)) & DDRPHY_DTPR5_tWTR_MASK)
15507 #define DDRPHY_DTPR5_RESERVED_7_5_MASK           (0xE0U)
15508 #define DDRPHY_DTPR5_RESERVED_7_5_SHIFT          (5U)
15509 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
15510  */
15511 #define DDRPHY_DTPR5_RESERVED_7_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR5_RESERVED_7_5_MASK)
15512 #define DDRPHY_DTPR5_tRCD_MASK                   (0x7F00U)
15513 #define DDRPHY_DTPR5_tRCD_SHIFT                  (8U)
15514 /*! tRCD - Activate to read or write delay
15515  */
15516 #define DDRPHY_DTPR5_tRCD(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_tRCD_SHIFT)) & DDRPHY_DTPR5_tRCD_MASK)
15517 #define DDRPHY_DTPR5_RESERVED_15_MASK            (0x8000U)
15518 #define DDRPHY_DTPR5_RESERVED_15_SHIFT           (15U)
15519 /*! RESERVED_15 - Reserved. Return zeroes on reads.
15520  */
15521 #define DDRPHY_DTPR5_RESERVED_15(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_RESERVED_15_SHIFT)) & DDRPHY_DTPR5_RESERVED_15_MASK)
15522 #define DDRPHY_DTPR5_tRC_MASK                    (0xFF0000U)
15523 #define DDRPHY_DTPR5_tRC_SHIFT                   (16U)
15524 /*! tRC - Activate to activate command delay (same bank)
15525  */
15526 #define DDRPHY_DTPR5_tRC(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_tRC_SHIFT)) & DDRPHY_DTPR5_tRC_MASK)
15527 #define DDRPHY_DTPR5_RESERVED_31_24_MASK         (0xFF000000U)
15528 #define DDRPHY_DTPR5_RESERVED_31_24_SHIFT        (24U)
15529 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
15530  */
15531 #define DDRPHY_DTPR5_RESERVED_31_24(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_RESERVED_31_24_SHIFT)) & DDRPHY_DTPR5_RESERVED_31_24_MASK)
15532 /*! @} */
15533 
15534 /*! @name DTPR6 - DRAM Timing Parameters Register 6 */
15535 /*! @{ */
15536 #define DDRPHY_DTPR6_PUBRL_MASK                  (0x3FU)
15537 #define DDRPHY_DTPR6_PUBRL_SHIFT                 (0U)
15538 /*! PUBRL - Read Latency
15539  */
15540 #define DDRPHY_DTPR6_PUBRL(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBRL_SHIFT)) & DDRPHY_DTPR6_PUBRL_MASK)
15541 #define DDRPHY_DTPR6_RESERVED_7_6_MASK           (0xC0U)
15542 #define DDRPHY_DTPR6_RESERVED_7_6_SHIFT          (6U)
15543 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
15544  */
15545 #define DDRPHY_DTPR6_RESERVED_7_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_RESERVED_7_6_SHIFT)) & DDRPHY_DTPR6_RESERVED_7_6_MASK)
15546 #define DDRPHY_DTPR6_PUBWL_MASK                  (0x3F00U)
15547 #define DDRPHY_DTPR6_PUBWL_SHIFT                 (8U)
15548 /*! PUBWL - Write Latency
15549  */
15550 #define DDRPHY_DTPR6_PUBWL(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBWL_SHIFT)) & DDRPHY_DTPR6_PUBWL_MASK)
15551 #define DDRPHY_DTPR6_RESERVED_29_14_MASK         (0x3FFFC000U)
15552 #define DDRPHY_DTPR6_RESERVED_29_14_SHIFT        (14U)
15553 /*! RESERVED_29_14 - Reserved. Return zeroes on reads.
15554  */
15555 #define DDRPHY_DTPR6_RESERVED_29_14(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_RESERVED_29_14_SHIFT)) & DDRPHY_DTPR6_RESERVED_29_14_MASK)
15556 #define DDRPHY_DTPR6_PUBRLEN_MASK                (0x40000000U)
15557 #define DDRPHY_DTPR6_PUBRLEN_SHIFT               (30U)
15558 /*! PUBRLEN - PUB Read Latency Enable
15559  */
15560 #define DDRPHY_DTPR6_PUBRLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBRLEN_SHIFT)) & DDRPHY_DTPR6_PUBRLEN_MASK)
15561 #define DDRPHY_DTPR6_PUBWLEN_MASK                (0x80000000U)
15562 #define DDRPHY_DTPR6_PUBWLEN_SHIFT               (31U)
15563 /*! PUBWLEN - PUB Write Latency Enable
15564  */
15565 #define DDRPHY_DTPR6_PUBWLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBWLEN_SHIFT)) & DDRPHY_DTPR6_PUBWLEN_MASK)
15566 /*! @} */
15567 
15568 /*! @name RDIMMGCR0 - RDIMM General Configuration Register 0 */
15569 /*! @{ */
15570 #define DDRPHY_RDIMMGCR0_RDIMM_MASK              (0x1U)
15571 #define DDRPHY_RDIMMGCR0_RDIMM_SHIFT             (0U)
15572 /*! RDIMM - Registered DIMM
15573  */
15574 #define DDRPHY_RDIMMGCR0_RDIMM(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RDIMM_SHIFT)) & DDRPHY_RDIMMGCR0_RDIMM_MASK)
15575 #define DDRPHY_RDIMMGCR0_ERRNOREG_MASK           (0x2U)
15576 #define DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT          (1U)
15577 /*! ERRNOREG - Parity Error No Registering
15578  */
15579 #define DDRPHY_RDIMMGCR0_ERRNOREG(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT)) & DDRPHY_RDIMMGCR0_ERRNOREG_MASK)
15580 #define DDRPHY_RDIMMGCR0_SOPERR_MASK             (0x4U)
15581 #define DDRPHY_RDIMMGCR0_SOPERR_SHIFT            (2U)
15582 /*! SOPERR - Stop on Parity Error
15583  */
15584 #define DDRPHY_RDIMMGCR0_SOPERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_SOPERR_SHIFT)) & DDRPHY_RDIMMGCR0_SOPERR_MASK)
15585 #define DDRPHY_RDIMMGCR0_RESERVED_3_MASK         (0x8U)
15586 #define DDRPHY_RDIMMGCR0_RESERVED_3_SHIFT        (3U)
15587 /*! RESERVED_3 - Reserved. Return zeroes on reads.
15588  */
15589 #define DDRPHY_RDIMMGCR0_RESERVED_3(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_3_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_3_MASK)
15590 #define DDRPHY_RDIMMGCR0_RNKMRREN_MASK           (0x10U)
15591 #define DDRPHY_RDIMMGCR0_RNKMRREN_SHIFT          (4U)
15592 /*! RNKMRREN - Rank Mirror Enable.
15593  */
15594 #define DDRPHY_RDIMMGCR0_RNKMRREN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RNKMRREN_SHIFT)) & DDRPHY_RDIMMGCR0_RNKMRREN_MASK)
15595 #define DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_MASK      (0xE0U)
15596 #define DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT     (5U)
15597 /*! RNKMRREN_RSVD - Reserved. Return zeroes on reads.
15598  */
15599 #define DDRPHY_RDIMMGCR0_RNKMRREN_RSVD(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT)) & DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_MASK)
15600 #define DDRPHY_RDIMMGCR0_RESERVED_16_8_MASK      (0x1FF00U)
15601 #define DDRPHY_RDIMMGCR0_RESERVED_16_8_SHIFT     (8U)
15602 /*! RESERVED_16_8 - Reserved. Return zeroes on reads.
15603  */
15604 #define DDRPHY_RDIMMGCR0_RESERVED_16_8(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_16_8_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_16_8_MASK)
15605 #define DDRPHY_RDIMMGCR0_PARINIOM_MASK           (0x20000U)
15606 #define DDRPHY_RDIMMGCR0_PARINIOM_SHIFT          (17U)
15607 /*! PARINIOM - PAR_IN I/O Mode
15608  */
15609 #define DDRPHY_RDIMMGCR0_PARINIOM(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_PARINIOM_SHIFT)) & DDRPHY_RDIMMGCR0_PARINIOM_MASK)
15610 #define DDRPHY_RDIMMGCR0_LRDIMM_MASK             (0x40000U)
15611 #define DDRPHY_RDIMMGCR0_LRDIMM_SHIFT            (18U)
15612 /*! LRDIMM - Load Reduced DIMM
15613  */
15614 #define DDRPHY_RDIMMGCR0_LRDIMM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_LRDIMM_SHIFT)) & DDRPHY_RDIMMGCR0_LRDIMM_MASK)
15615 #define DDRPHY_RDIMMGCR0_ERROUTODT_MASK          (0x80000U)
15616 #define DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT         (19U)
15617 /*! ERROUTODT - ERROUT# On-Die Termination
15618  */
15619 #define DDRPHY_RDIMMGCR0_ERROUTODT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTODT_MASK)
15620 #define DDRPHY_RDIMMGCR0_RESERVED_20_MASK        (0x100000U)
15621 #define DDRPHY_RDIMMGCR0_RESERVED_20_SHIFT       (20U)
15622 /*! RESERVED_20 - Reserved. Return zeroes on reads.
15623  */
15624 #define DDRPHY_RDIMMGCR0_RESERVED_20(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_20_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_20_MASK)
15625 #define DDRPHY_RDIMMGCR0_ERROUTPDR_MASK          (0x200000U)
15626 #define DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT         (21U)
15627 /*! ERROUTPDR - ERROUT# Power Down Receiver
15628  */
15629 #define DDRPHY_RDIMMGCR0_ERROUTPDR(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTPDR_MASK)
15630 #define DDRPHY_RDIMMGCR0_ERROUTIOM_MASK          (0x400000U)
15631 #define DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT         (22U)
15632 /*! ERROUTIOM - ERROUT# I/O Mode
15633  */
15634 #define DDRPHY_RDIMMGCR0_ERROUTIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTIOM_MASK)
15635 #define DDRPHY_RDIMMGCR0_ERROUTOE_MASK           (0x800000U)
15636 #define DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT          (23U)
15637 /*! ERROUTOE - ERROUT# Output Enable
15638  */
15639 #define DDRPHY_RDIMMGCR0_ERROUTOE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTOE_MASK)
15640 #define DDRPHY_RDIMMGCR0_RESERVED_26_24_MASK     (0x7000000U)
15641 #define DDRPHY_RDIMMGCR0_RESERVED_26_24_SHIFT    (24U)
15642 /*! RESERVED_26_24 - Reserved. Return zeroes on reads.
15643  */
15644 #define DDRPHY_RDIMMGCR0_RESERVED_26_24(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_26_24_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_26_24_MASK)
15645 #define DDRPHY_RDIMMGCR0_RDIMMIOM_MASK           (0x8000000U)
15646 #define DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT          (27U)
15647 /*! RDIMMIOM - RDIMM Outputs I/O Mode
15648  */
15649 #define DDRPHY_RDIMMGCR0_RDIMMIOM(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT)) & DDRPHY_RDIMMGCR0_RDIMMIOM_MASK)
15650 #define DDRPHY_RDIMMGCR0_RESERVED_29_28_MASK     (0x30000000U)
15651 #define DDRPHY_RDIMMGCR0_RESERVED_29_28_SHIFT    (28U)
15652 /*! RESERVED_29_28 - Reserved. Return zeroes on reads.
15653  */
15654 #define DDRPHY_RDIMMGCR0_RESERVED_29_28(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_29_28_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_29_28_MASK)
15655 #define DDRPHY_RDIMMGCR0_QCSEN_MASK              (0x40000000U)
15656 #define DDRPHY_RDIMMGCR0_QCSEN_SHIFT             (30U)
15657 /*! QCSEN - RDMIMM Quad CS Enable
15658  */
15659 #define DDRPHY_RDIMMGCR0_QCSEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_QCSEN_SHIFT)) & DDRPHY_RDIMMGCR0_QCSEN_MASK)
15660 #define DDRPHY_RDIMMGCR0_RESERVED_31_MASK        (0x80000000U)
15661 #define DDRPHY_RDIMMGCR0_RESERVED_31_SHIFT       (31U)
15662 /*! RESERVED_31 - Reserved. Return zeroes on reads.
15663  */
15664 #define DDRPHY_RDIMMGCR0_RESERVED_31(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_31_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_31_MASK)
15665 /*! @} */
15666 
15667 /*! @name RDIMMGCR1 - RDIMM General Configuration Register 1 */
15668 /*! @{ */
15669 #define DDRPHY_RDIMMGCR1_tBCSTAB_MASK            (0x3FFFU)
15670 #define DDRPHY_RDIMMGCR1_tBCSTAB_SHIFT           (0U)
15671 /*! tBCSTAB - Stabilization time
15672  */
15673 #define DDRPHY_RDIMMGCR1_tBCSTAB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCSTAB_SHIFT)) & DDRPHY_RDIMMGCR1_tBCSTAB_MASK)
15674 #define DDRPHY_RDIMMGCR1_RESERVED_15_14_MASK     (0xC000U)
15675 #define DDRPHY_RDIMMGCR1_RESERVED_15_14_SHIFT    (14U)
15676 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
15677  */
15678 #define DDRPHY_RDIMMGCR1_RESERVED_15_14(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_15_14_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_15_14_MASK)
15679 #define DDRPHY_RDIMMGCR1_tBCMRD_MASK             (0x70000U)
15680 #define DDRPHY_RDIMMGCR1_tBCMRD_SHIFT            (16U)
15681 /*! tBCMRD - Command word to command word programming delay
15682  */
15683 #define DDRPHY_RDIMMGCR1_tBCMRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCMRD_SHIFT)) & DDRPHY_RDIMMGCR1_tBCMRD_MASK)
15684 #define DDRPHY_RDIMMGCR1_RESERVED_19_MASK        (0x80000U)
15685 #define DDRPHY_RDIMMGCR1_RESERVED_19_SHIFT       (19U)
15686 /*! RESERVED_19 - Reserved. Return zeroes on reads.
15687  */
15688 #define DDRPHY_RDIMMGCR1_RESERVED_19(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_19_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_19_MASK)
15689 #define DDRPHY_RDIMMGCR1_tBCMRD_L_MASK           (0x700000U)
15690 #define DDRPHY_RDIMMGCR1_tBCMRD_L_SHIFT          (20U)
15691 /*! tBCMRD_L - Command word to command word programming delay
15692  */
15693 #define DDRPHY_RDIMMGCR1_tBCMRD_L(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCMRD_L_SHIFT)) & DDRPHY_RDIMMGCR1_tBCMRD_L_MASK)
15694 #define DDRPHY_RDIMMGCR1_RESERVED_23_MASK        (0x800000U)
15695 #define DDRPHY_RDIMMGCR1_RESERVED_23_SHIFT       (23U)
15696 /*! RESERVED_23 - Reserved. Return zeroes on reads.
15697  */
15698 #define DDRPHY_RDIMMGCR1_RESERVED_23(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_23_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_23_MASK)
15699 #define DDRPHY_RDIMMGCR1_tBCMRD_L2_MASK          (0x7000000U)
15700 #define DDRPHY_RDIMMGCR1_tBCMRD_L2_SHIFT         (24U)
15701 /*! tBCMRD_L2 - Command word to command word programming delay
15702  */
15703 #define DDRPHY_RDIMMGCR1_tBCMRD_L2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCMRD_L2_SHIFT)) & DDRPHY_RDIMMGCR1_tBCMRD_L2_MASK)
15704 #define DDRPHY_RDIMMGCR1_RESERVED_27_MASK        (0x8000000U)
15705 #define DDRPHY_RDIMMGCR1_RESERVED_27_SHIFT       (27U)
15706 /*! RESERVED_27 - Reserved. Return zeroes on reads.
15707  */
15708 #define DDRPHY_RDIMMGCR1_RESERVED_27(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_27_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_27_MASK)
15709 #define DDRPHY_RDIMMGCR1_A17BID_MASK             (0x10000000U)
15710 #define DDRPHY_RDIMMGCR1_A17BID_SHIFT            (28U)
15711 /*! A17BID - Address [17] B-side Inversion Disable
15712  */
15713 #define DDRPHY_RDIMMGCR1_A17BID(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_A17BID_SHIFT)) & DDRPHY_RDIMMGCR1_A17BID_MASK)
15714 #define DDRPHY_RDIMMGCR1_RESERVED_31_29_MASK     (0xE0000000U)
15715 #define DDRPHY_RDIMMGCR1_RESERVED_31_29_SHIFT    (29U)
15716 /*! RESERVED_31_29 - Reserved. Return zeroes on reads.
15717  */
15718 #define DDRPHY_RDIMMGCR1_RESERVED_31_29(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_31_29_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_31_29_MASK)
15719 /*! @} */
15720 
15721 /*! @name RDIMMGCR2 - RDIMM General Configuration Register 2 */
15722 /*! @{ */
15723 #define DDRPHY_RDIMMGCR2_CRINIT_MASK             (0xFFFFFFFFU)
15724 #define DDRPHY_RDIMMGCR2_CRINIT_SHIFT            (0U)
15725 /*! CRINIT - Control Registers Initialization Enable
15726  */
15727 #define DDRPHY_RDIMMGCR2_CRINIT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR2_CRINIT_SHIFT)) & DDRPHY_RDIMMGCR2_CRINIT_MASK)
15728 /*! @} */
15729 
15730 /*! @name RDIMMCR0 - RDIMM Control Register 0 */
15731 /*! @{ */
15732 #define DDRPHY_RDIMMCR0_RC0_MASK                 (0xFU)
15733 #define DDRPHY_RDIMMCR0_RC0_SHIFT                (0U)
15734 /*! RC0 - DDR4/DDR3 Control Word 0 (Global Features Control Word)
15735  */
15736 #define DDRPHY_RDIMMCR0_RC0(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC0_SHIFT)) & DDRPHY_RDIMMCR0_RC0_MASK)
15737 #define DDRPHY_RDIMMCR0_RC1_MASK                 (0xF0U)
15738 #define DDRPHY_RDIMMCR0_RC1_SHIFT                (4U)
15739 /*! RC1 - DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
15740  */
15741 #define DDRPHY_RDIMMCR0_RC1(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC1_SHIFT)) & DDRPHY_RDIMMCR0_RC1_MASK)
15742 #define DDRPHY_RDIMMCR0_RC2_MASK                 (0xF00U)
15743 #define DDRPHY_RDIMMCR0_RC2_SHIFT                (8U)
15744 /*! RC2 - DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)
15745  */
15746 #define DDRPHY_RDIMMCR0_RC2(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC2_SHIFT)) & DDRPHY_RDIMMCR0_RC2_MASK)
15747 #define DDRPHY_RDIMMCR0_RC3_MASK                 (0xF000U)
15748 #define DDRPHY_RDIMMCR0_RC3_SHIFT                (12U)
15749 /*! RC3 - DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control
15750  *    Word 3 (Command/Address Signals Driver Characteristrics Control Word)
15751  */
15752 #define DDRPHY_RDIMMCR0_RC3(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC3_SHIFT)) & DDRPHY_RDIMMCR0_RC3_MASK)
15753 #define DDRPHY_RDIMMCR0_RC4_MASK                 (0xF0000U)
15754 #define DDRPHY_RDIMMCR0_RC4_SHIFT                (16U)
15755 /*! RC4 - DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3
15756  *    Control Word 4 (Control Signals Driver Characteristics Control Word)
15757  */
15758 #define DDRPHY_RDIMMCR0_RC4(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC4_SHIFT)) & DDRPHY_RDIMMCR0_RC4_MASK)
15759 #define DDRPHY_RDIMMCR0_RC5_MASK                 (0xF00000U)
15760 #define DDRPHY_RDIMMCR0_RC5_SHIFT                (20U)
15761 /*! RC5 - DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
15762  */
15763 #define DDRPHY_RDIMMCR0_RC5(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC5_SHIFT)) & DDRPHY_RDIMMCR0_RC5_MASK)
15764 #define DDRPHY_RDIMMCR0_RC6_MASK                 (0xF000000U)
15765 #define DDRPHY_RDIMMCR0_RC6_SHIFT                (24U)
15766 /*! RC6 - DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
15767  */
15768 #define DDRPHY_RDIMMCR0_RC6(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC6_SHIFT)) & DDRPHY_RDIMMCR0_RC6_MASK)
15769 #define DDRPHY_RDIMMCR0_RC7_MASK                 (0xF0000000U)
15770 #define DDRPHY_RDIMMCR0_RC7_SHIFT                (28U)
15771 /*! RC7 - DDR4/DDR3 Control Word 7
15772  */
15773 #define DDRPHY_RDIMMCR0_RC7(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC7_SHIFT)) & DDRPHY_RDIMMCR0_RC7_MASK)
15774 /*! @} */
15775 
15776 /*! @name RDIMMCR1 - RDIMM Control Register 1 */
15777 /*! @{ */
15778 #define DDRPHY_RDIMMCR1_RC8_MASK                 (0xFU)
15779 #define DDRPHY_RDIMMCR1_RC8_SHIFT                (0U)
15780 /*! RC8 - DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8
15781  *    (Additional Input Bus Termination Setting Control Word)
15782  */
15783 #define DDRPHY_RDIMMCR1_RC8(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC8_SHIFT)) & DDRPHY_RDIMMCR1_RC8_MASK)
15784 #define DDRPHY_RDIMMCR1_RC9_MASK                 (0xF0U)
15785 #define DDRPHY_RDIMMCR1_RC9_SHIFT                (4U)
15786 /*! RC9 - DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
15787  */
15788 #define DDRPHY_RDIMMCR1_RC9(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC9_SHIFT)) & DDRPHY_RDIMMCR1_RC9_MASK)
15789 #define DDRPHY_RDIMMCR1_RC10_MASK                (0xF00U)
15790 #define DDRPHY_RDIMMCR1_RC10_SHIFT               (8U)
15791 /*! RC10 - DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
15792  */
15793 #define DDRPHY_RDIMMCR1_RC10(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC10_SHIFT)) & DDRPHY_RDIMMCR1_RC10_MASK)
15794 #define DDRPHY_RDIMMCR1_RC11_MASK                (0xF000U)
15795 #define DDRPHY_RDIMMCR1_RC11_SHIFT               (12U)
15796 /*! RC11 - DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3
15797  *    Control Word 11 (Operation Voltage VDD Control Word)
15798  */
15799 #define DDRPHY_RDIMMCR1_RC11(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC11_SHIFT)) & DDRPHY_RDIMMCR1_RC11_MASK)
15800 #define DDRPHY_RDIMMCR1_RC12_MASK                (0xF0000U)
15801 #define DDRPHY_RDIMMCR1_RC12_SHIFT               (16U)
15802 /*! RC12 - DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
15803  */
15804 #define DDRPHY_RDIMMCR1_RC12(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC12_SHIFT)) & DDRPHY_RDIMMCR1_RC12_MASK)
15805 #define DDRPHY_RDIMMCR1_RC13_MASK                (0xF00000U)
15806 #define DDRPHY_RDIMMCR1_RC13_SHIFT               (20U)
15807 /*! RC13 - DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
15808  */
15809 #define DDRPHY_RDIMMCR1_RC13(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC13_SHIFT)) & DDRPHY_RDIMMCR1_RC13_MASK)
15810 #define DDRPHY_RDIMMCR1_RC14_MASK                (0xF000000U)
15811 #define DDRPHY_RDIMMCR1_RC14_SHIFT               (24U)
15812 /*! RC14 - DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
15813  */
15814 #define DDRPHY_RDIMMCR1_RC14(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC14_SHIFT)) & DDRPHY_RDIMMCR1_RC14_MASK)
15815 #define DDRPHY_RDIMMCR1_RC15_MASK                (0xF0000000U)
15816 #define DDRPHY_RDIMMCR1_RC15_SHIFT               (28U)
15817 /*! RC15 - Control Word 15
15818  */
15819 #define DDRPHY_RDIMMCR1_RC15(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC15_SHIFT)) & DDRPHY_RDIMMCR1_RC15_MASK)
15820 /*! @} */
15821 
15822 /*! @name RDIMMCR2 - RDIMM Control Register 2 */
15823 /*! @{ */
15824 #define DDRPHY_RDIMMCR2_RC1X_MASK                (0xFFU)
15825 #define DDRPHY_RDIMMCR2_RC1X_SHIFT               (0U)
15826 /*! RC1X - Control Word RC1X
15827  */
15828 #define DDRPHY_RDIMMCR2_RC1X(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC1X_SHIFT)) & DDRPHY_RDIMMCR2_RC1X_MASK)
15829 #define DDRPHY_RDIMMCR2_RC2X_MASK                (0xFF00U)
15830 #define DDRPHY_RDIMMCR2_RC2X_SHIFT               (8U)
15831 /*! RC2X - Control Word RC2X
15832  */
15833 #define DDRPHY_RDIMMCR2_RC2X(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC2X_SHIFT)) & DDRPHY_RDIMMCR2_RC2X_MASK)
15834 #define DDRPHY_RDIMMCR2_RC3X_MASK                (0xFF0000U)
15835 #define DDRPHY_RDIMMCR2_RC3X_SHIFT               (16U)
15836 /*! RC3X - Control Word RC3X
15837  */
15838 #define DDRPHY_RDIMMCR2_RC3X(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC3X_SHIFT)) & DDRPHY_RDIMMCR2_RC3X_MASK)
15839 #define DDRPHY_RDIMMCR2_RC4X_MASK                (0xFF000000U)
15840 #define DDRPHY_RDIMMCR2_RC4X_SHIFT               (24U)
15841 /*! RC4X - Control Word RC4X
15842  */
15843 #define DDRPHY_RDIMMCR2_RC4X(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC4X_SHIFT)) & DDRPHY_RDIMMCR2_RC4X_MASK)
15844 /*! @} */
15845 
15846 /*! @name RDIMMCR3 - RDIMM Control Register 3 */
15847 /*! @{ */
15848 #define DDRPHY_RDIMMCR3_RC5X_MASK                (0xFFU)
15849 #define DDRPHY_RDIMMCR3_RC5X_SHIFT               (0U)
15850 /*! RC5X - Control Word RC5X
15851  */
15852 #define DDRPHY_RDIMMCR3_RC5X(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC5X_SHIFT)) & DDRPHY_RDIMMCR3_RC5X_MASK)
15853 #define DDRPHY_RDIMMCR3_RC6X_MASK                (0xFF00U)
15854 #define DDRPHY_RDIMMCR3_RC6X_SHIFT               (8U)
15855 /*! RC6X - Control Word RC6X
15856  */
15857 #define DDRPHY_RDIMMCR3_RC6X(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC6X_SHIFT)) & DDRPHY_RDIMMCR3_RC6X_MASK)
15858 #define DDRPHY_RDIMMCR3_RC7X_MASK                (0xFF0000U)
15859 #define DDRPHY_RDIMMCR3_RC7X_SHIFT               (16U)
15860 /*! RC7X - Control Word RC7X
15861  */
15862 #define DDRPHY_RDIMMCR3_RC7X(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC7X_SHIFT)) & DDRPHY_RDIMMCR3_RC7X_MASK)
15863 #define DDRPHY_RDIMMCR3_RC8X_MASK                (0xFF000000U)
15864 #define DDRPHY_RDIMMCR3_RC8X_SHIFT               (24U)
15865 /*! RC8X - Control Word RC8X
15866  */
15867 #define DDRPHY_RDIMMCR3_RC8X(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC8X_SHIFT)) & DDRPHY_RDIMMCR3_RC8X_MASK)
15868 /*! @} */
15869 
15870 /*! @name RDIMMCR4 - RDIMM Control Register 4 */
15871 /*! @{ */
15872 #define DDRPHY_RDIMMCR4_RC9X_MASK                (0xFFU)
15873 #define DDRPHY_RDIMMCR4_RC9X_SHIFT               (0U)
15874 /*! RC9X - Control Word RC9X
15875  */
15876 #define DDRPHY_RDIMMCR4_RC9X(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RC9X_SHIFT)) & DDRPHY_RDIMMCR4_RC9X_MASK)
15877 #define DDRPHY_RDIMMCR4_RCAX_MASK                (0xFF00U)
15878 #define DDRPHY_RDIMMCR4_RCAX_SHIFT               (8U)
15879 /*! RCAX - Control Word RC10X
15880  */
15881 #define DDRPHY_RDIMMCR4_RCAX(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RCAX_SHIFT)) & DDRPHY_RDIMMCR4_RCAX_MASK)
15882 #define DDRPHY_RDIMMCR4_RCBX_MASK                (0xFF0000U)
15883 #define DDRPHY_RDIMMCR4_RCBX_SHIFT               (16U)
15884 /*! RCBX - Control Word RC11X
15885  */
15886 #define DDRPHY_RDIMMCR4_RCBX(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RCBX_SHIFT)) & DDRPHY_RDIMMCR4_RCBX_MASK)
15887 #define DDRPHY_RDIMMCR4_RCXX_MASK                (0xFF000000U)
15888 #define DDRPHY_RDIMMCR4_RCXX_SHIFT               (24U)
15889 /*! RCXX - Reserved for future use.
15890  */
15891 #define DDRPHY_RDIMMCR4_RCXX(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RCXX_SHIFT)) & DDRPHY_RDIMMCR4_RCXX_MASK)
15892 /*! @} */
15893 
15894 /*! @name SCHCR0 - Scheduler Command Register 0 */
15895 /*! @{ */
15896 #define DDRPHY_SCHCR0_SCHTRIG_MASK               (0xFU)
15897 #define DDRPHY_SCHCR0_SCHTRIG_SHIFT              (0U)
15898 /*! SCHTRIG - Mode Register Command Trigger
15899  */
15900 #define DDRPHY_SCHCR0_SCHTRIG(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_SCHTRIG_SHIFT)) & DDRPHY_SCHCR0_SCHTRIG_MASK)
15901 #define DDRPHY_SCHCR0_CMD_MASK                   (0xF0U)
15902 #define DDRPHY_SCHCR0_CMD_SHIFT                  (4U)
15903 /*! CMD - Specifies the Command to be issued
15904  */
15905 #define DDRPHY_SCHCR0_CMD(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_CMD_SHIFT)) & DDRPHY_SCHCR0_CMD_MASK)
15906 #define DDRPHY_SCHCR0_SP_CMD_MASK                (0xF00U)
15907 #define DDRPHY_SCHCR0_SP_CMD_SHIFT               (8U)
15908 /*! SP_CMD - Special Command codes
15909  */
15910 #define DDRPHY_SCHCR0_SP_CMD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_SP_CMD_SHIFT)) & DDRPHY_SCHCR0_SP_CMD_MASK)
15911 #define DDRPHY_SCHCR0_RESERVED_15_12_MASK        (0xF000U)
15912 #define DDRPHY_SCHCR0_RESERVED_15_12_SHIFT       (12U)
15913 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
15914  */
15915 #define DDRPHY_SCHCR0_RESERVED_15_12(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_RESERVED_15_12_SHIFT)) & DDRPHY_SCHCR0_RESERVED_15_12_MASK)
15916 #define DDRPHY_SCHCR0_SCHDQV_MASK                (0x1FF0000U)
15917 #define DDRPHY_SCHCR0_SCHDQV_SHIFT               (16U)
15918 /*! SCHDQV - Scheduler Command DQ Value
15919  */
15920 #define DDRPHY_SCHCR0_SCHDQV(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_SCHDQV_SHIFT)) & DDRPHY_SCHCR0_SCHDQV_MASK)
15921 #define DDRPHY_SCHCR0_RESERVED_31_25_MASK        (0xFE000000U)
15922 #define DDRPHY_SCHCR0_RESERVED_31_25_SHIFT       (25U)
15923 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
15924  */
15925 #define DDRPHY_SCHCR0_RESERVED_31_25(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_RESERVED_31_25_SHIFT)) & DDRPHY_SCHCR0_RESERVED_31_25_MASK)
15926 /*! @} */
15927 
15928 /*! @name SCHCR1 - Scheduler Command Register 1 */
15929 /*! @{ */
15930 #define DDRPHY_SCHCR1_RESERVED_1_0_MASK          (0x3U)
15931 #define DDRPHY_SCHCR1_RESERVED_1_0_SHIFT         (0U)
15932 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
15933  */
15934 #define DDRPHY_SCHCR1_RESERVED_1_0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_RESERVED_1_0_SHIFT)) & DDRPHY_SCHCR1_RESERVED_1_0_MASK)
15935 #define DDRPHY_SCHCR1_ALLRANK_MASK               (0x4U)
15936 #define DDRPHY_SCHCR1_ALLRANK_SHIFT              (2U)
15937 /*! ALLRANK - All Ranks enabled
15938  */
15939 #define DDRPHY_SCHCR1_ALLRANK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_ALLRANK_SHIFT)) & DDRPHY_SCHCR1_ALLRANK_MASK)
15940 #define DDRPHY_SCHCR1_RESERVED_3_MASK            (0x8U)
15941 #define DDRPHY_SCHCR1_RESERVED_3_SHIFT           (3U)
15942 /*! RESERVED_3 - Reserved. Return zeroes on reads.
15943  */
15944 #define DDRPHY_SCHCR1_RESERVED_3(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_RESERVED_3_SHIFT)) & DDRPHY_SCHCR1_RESERVED_3_MASK)
15945 #define DDRPHY_SCHCR1_SCBK_MASK                  (0x30U)
15946 #define DDRPHY_SCHCR1_SCBK_SHIFT                 (4U)
15947 /*! SCBK - Scheduler Command Bank Address
15948  */
15949 #define DDRPHY_SCHCR1_SCBK(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCBK_SHIFT)) & DDRPHY_SCHCR1_SCBK_MASK)
15950 #define DDRPHY_SCHCR1_SCBG_MASK                  (0xC0U)
15951 #define DDRPHY_SCHCR1_SCBG_SHIFT                 (6U)
15952 /*! SCBG - Scheduler Command Bank Group
15953  */
15954 #define DDRPHY_SCHCR1_SCBG(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCBG_SHIFT)) & DDRPHY_SCHCR1_SCBG_MASK)
15955 #define DDRPHY_SCHCR1_SCADDR_MASK                (0xFFFFF00U)
15956 #define DDRPHY_SCHCR1_SCADDR_SHIFT               (8U)
15957 /*! SCADDR - Scheduler Command Address Specifies the value to be driven on the address bus.
15958  */
15959 #define DDRPHY_SCHCR1_SCADDR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCADDR_SHIFT)) & DDRPHY_SCHCR1_SCADDR_MASK)
15960 #define DDRPHY_SCHCR1_SCRNK_MASK                 (0xF0000000U)
15961 #define DDRPHY_SCHCR1_SCRNK_SHIFT                (28U)
15962 /*! SCRNK - Scheduler Rank Address
15963  */
15964 #define DDRPHY_SCHCR1_SCRNK(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCRNK_SHIFT)) & DDRPHY_SCHCR1_SCRNK_MASK)
15965 /*! @} */
15966 
15967 /*! @name MR0 - LPDDR4 Mode Register 0 */
15968 /*! @{ */
15969 #define DDRPHY_MR0_RSVD_2_0_MASK                 (0x7U)
15970 #define DDRPHY_MR0_RSVD_2_0_SHIFT                (0U)
15971 /*! RSVD_2_0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
15972  */
15973 #define DDRPHY_MR0_RSVD_2_0(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RSVD_2_0_SHIFT)) & DDRPHY_MR0_RSVD_2_0_MASK)
15974 #define DDRPHY_MR0_RZQI_MASK                     (0x18U)
15975 #define DDRPHY_MR0_RZQI_SHIFT                    (3U)
15976 /*! RZQI - Built-in Self-Test for RZQ
15977  */
15978 #define DDRPHY_MR0_RZQI(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RZQI_SHIFT)) & DDRPHY_MR0_RZQI_MASK)
15979 #define DDRPHY_MR0_RSVD_6_5_MASK                 (0x60U)
15980 #define DDRPHY_MR0_RSVD_6_5_SHIFT                (5U)
15981 /*! RSVD_6_5 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
15982  */
15983 #define DDRPHY_MR0_RSVD_6_5(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RSVD_6_5_SHIFT)) & DDRPHY_MR0_RSVD_6_5_MASK)
15984 #define DDRPHY_MR0_CATR_MASK                     (0x80U)
15985 #define DDRPHY_MR0_CATR_SHIFT                    (7U)
15986 /*! CATR - CA Terminating Rank
15987  */
15988 #define DDRPHY_MR0_CATR(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_CATR_SHIFT)) & DDRPHY_MR0_CATR_MASK)
15989 #define DDRPHY_MR0_RSVD_15_8_MASK                (0xFF00U)
15990 #define DDRPHY_MR0_RSVD_15_8_SHIFT               (8U)
15991 /*! RSVD_15_8 - Reserved. Return zeroes on reads.
15992  */
15993 #define DDRPHY_MR0_RSVD_15_8(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RSVD_15_8_SHIFT)) & DDRPHY_MR0_RSVD_15_8_MASK)
15994 #define DDRPHY_MR0_RESERVED_31_16_MASK           (0xFFFF0000U)
15995 #define DDRPHY_MR0_RESERVED_31_16_SHIFT          (16U)
15996 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
15997  */
15998 #define DDRPHY_MR0_RESERVED_31_16(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RESERVED_31_16_SHIFT)) & DDRPHY_MR0_RESERVED_31_16_MASK)
15999 /*! @} */
16000 
16001 /*! @name MR1 - LPDDR4 Mode Register 1 */
16002 /*! @{ */
16003 #define DDRPHY_MR1_BL_MASK                       (0x3U)
16004 #define DDRPHY_MR1_BL_SHIFT                      (0U)
16005 /*! BL - Burst Length
16006  */
16007 #define DDRPHY_MR1_BL(x)                         (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_BL_SHIFT)) & DDRPHY_MR1_BL_MASK)
16008 #define DDRPHY_MR1_WRPRE_MASK                    (0x4U)
16009 #define DDRPHY_MR1_WRPRE_SHIFT                   (2U)
16010 /*! WRPRE - Write Preamble Length
16011  */
16012 #define DDRPHY_MR1_WRPRE(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_WRPRE_SHIFT)) & DDRPHY_MR1_WRPRE_MASK)
16013 #define DDRPHY_MR1_RDPRE_MASK                    (0x8U)
16014 #define DDRPHY_MR1_RDPRE_SHIFT                   (3U)
16015 /*! RDPRE - Read Preamble Length
16016  */
16017 #define DDRPHY_MR1_RDPRE(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RDPRE_SHIFT)) & DDRPHY_MR1_RDPRE_MASK)
16018 #define DDRPHY_MR1_nWR_MASK                      (0x70U)
16019 #define DDRPHY_MR1_nWR_SHIFT                     (4U)
16020 /*! nWR - Write-recovery for auto-precharge command
16021  */
16022 #define DDRPHY_MR1_nWR(x)                        (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_nWR_SHIFT)) & DDRPHY_MR1_nWR_MASK)
16023 #define DDRPHY_MR1_RDPST_MASK                    (0x80U)
16024 #define DDRPHY_MR1_RDPST_SHIFT                   (7U)
16025 /*! RDPST - Read Postamble Length
16026  */
16027 #define DDRPHY_MR1_RDPST(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RDPST_SHIFT)) & DDRPHY_MR1_RDPST_MASK)
16028 #define DDRPHY_MR1_RSVD_MASK                     (0xFF00U)
16029 #define DDRPHY_MR1_RSVD_SHIFT                    (8U)
16030 /*! RSVD - Reserved. Return zeroes on reads.
16031  */
16032 #define DDRPHY_MR1_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RSVD_SHIFT)) & DDRPHY_MR1_RSVD_MASK)
16033 #define DDRPHY_MR1_RESERVED_31_16_MASK           (0xFFFF0000U)
16034 #define DDRPHY_MR1_RESERVED_31_16_SHIFT          (16U)
16035 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
16036  */
16037 #define DDRPHY_MR1_RESERVED_31_16(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RESERVED_31_16_SHIFT)) & DDRPHY_MR1_RESERVED_31_16_MASK)
16038 /*! @} */
16039 
16040 /*! @name MR2 - LPDDR4 Mode Register 2 */
16041 /*! @{ */
16042 #define DDRPHY_MR2_RL_MASK                       (0x7U)
16043 #define DDRPHY_MR2_RL_SHIFT                      (0U)
16044 /*! RL - Read Latency
16045  */
16046 #define DDRPHY_MR2_RL(x)                         (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_RL_SHIFT)) & DDRPHY_MR2_RL_MASK)
16047 #define DDRPHY_MR2_WL_MASK                       (0x38U)
16048 #define DDRPHY_MR2_WL_SHIFT                      (3U)
16049 /*! WL - Write Latency
16050  */
16051 #define DDRPHY_MR2_WL(x)                         (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_WL_SHIFT)) & DDRPHY_MR2_WL_MASK)
16052 #define DDRPHY_MR2_WLS_MASK                      (0x40U)
16053 #define DDRPHY_MR2_WLS_SHIFT                     (6U)
16054 /*! WLS - Write Latency Set
16055  */
16056 #define DDRPHY_MR2_WLS(x)                        (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_WLS_SHIFT)) & DDRPHY_MR2_WLS_MASK)
16057 #define DDRPHY_MR2_WRL_MASK                      (0x80U)
16058 #define DDRPHY_MR2_WRL_SHIFT                     (7U)
16059 /*! WRL - Write Leveling
16060  */
16061 #define DDRPHY_MR2_WRL(x)                        (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_WRL_SHIFT)) & DDRPHY_MR2_WRL_MASK)
16062 #define DDRPHY_MR2_RSVD_MASK                     (0xFF00U)
16063 #define DDRPHY_MR2_RSVD_SHIFT                    (8U)
16064 /*! RSVD - Reserved. Return zeroes on reads.
16065  */
16066 #define DDRPHY_MR2_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_RSVD_SHIFT)) & DDRPHY_MR2_RSVD_MASK)
16067 #define DDRPHY_MR2_RESERVED_31_16_MASK           (0xFFFF0000U)
16068 #define DDRPHY_MR2_RESERVED_31_16_SHIFT          (16U)
16069 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
16070  */
16071 #define DDRPHY_MR2_RESERVED_31_16(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_RESERVED_31_16_SHIFT)) & DDRPHY_MR2_RESERVED_31_16_MASK)
16072 /*! @} */
16073 
16074 /*! @name MR3 - LPDDR4 Mode Register 3 */
16075 /*! @{ */
16076 #define DDRPHY_MR3_PUCAL_MASK                    (0x1U)
16077 #define DDRPHY_MR3_PUCAL_SHIFT                   (0U)
16078 /*! PUCAL - Pull-up Calibration Point
16079  */
16080 #define DDRPHY_MR3_PUCAL(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_PUCAL_SHIFT)) & DDRPHY_MR3_PUCAL_MASK)
16081 #define DDRPHY_MR3_WRPST_MASK                    (0x2U)
16082 #define DDRPHY_MR3_WRPST_SHIFT                   (1U)
16083 /*! WRPST - Write Postamble Length
16084  */
16085 #define DDRPHY_MR3_WRPST(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_WRPST_SHIFT)) & DDRPHY_MR3_WRPST_MASK)
16086 #define DDRPHY_MR3_RSVD_MASK                     (0x4U)
16087 #define DDRPHY_MR3_RSVD_SHIFT                    (2U)
16088 /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16089  */
16090 #define DDRPHY_MR3_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_RSVD_SHIFT)) & DDRPHY_MR3_RSVD_MASK)
16091 #define DDRPHY_MR3_PDDS_MASK                     (0x38U)
16092 #define DDRPHY_MR3_PDDS_SHIFT                    (3U)
16093 /*! PDDS - Pull-down Drive Strength
16094  */
16095 #define DDRPHY_MR3_PDDS(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_PDDS_SHIFT)) & DDRPHY_MR3_PDDS_MASK)
16096 #define DDRPHY_MR3_DBIRD_MASK                    (0x40U)
16097 #define DDRPHY_MR3_DBIRD_SHIFT                   (6U)
16098 /*! DBIRD - DBI-Read Enable
16099  */
16100 #define DDRPHY_MR3_DBIRD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_DBIRD_SHIFT)) & DDRPHY_MR3_DBIRD_MASK)
16101 #define DDRPHY_MR3_DBIWR_MASK                    (0x80U)
16102 #define DDRPHY_MR3_DBIWR_SHIFT                   (7U)
16103 /*! DBIWR - DBI-Write Enable
16104  */
16105 #define DDRPHY_MR3_DBIWR(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_DBIWR_SHIFT)) & DDRPHY_MR3_DBIWR_MASK)
16106 #define DDRPHY_MR3_RESERVED_31_8_MASK            (0xFFFFFF00U)
16107 #define DDRPHY_MR3_RESERVED_31_8_SHIFT           (8U)
16108 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16109  */
16110 #define DDRPHY_MR3_RESERVED_31_8(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_RESERVED_31_8_SHIFT)) & DDRPHY_MR3_RESERVED_31_8_MASK)
16111 /*! @} */
16112 
16113 /*! @name MR4 - LPDDR4 Mode Register 4 */
16114 /*! @{ */
16115 #define DDRPHY_MR4_RSVD_MASK                     (0xFFU)
16116 #define DDRPHY_MR4_RSVD_SHIFT                    (0U)
16117 /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16118  */
16119 #define DDRPHY_MR4_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR4_RSVD_SHIFT)) & DDRPHY_MR4_RSVD_MASK)
16120 #define DDRPHY_MR4_RESERVED_31_8_MASK            (0xFFFFFF00U)
16121 #define DDRPHY_MR4_RESERVED_31_8_SHIFT           (8U)
16122 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16123  */
16124 #define DDRPHY_MR4_RESERVED_31_8(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR4_RESERVED_31_8_SHIFT)) & DDRPHY_MR4_RESERVED_31_8_MASK)
16125 /*! @} */
16126 
16127 /*! @name MR5 - LPDDR4 Mode Register 5 */
16128 /*! @{ */
16129 #define DDRPHY_MR5_RSVD_MASK                     (0xFFU)
16130 #define DDRPHY_MR5_RSVD_SHIFT                    (0U)
16131 /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16132  */
16133 #define DDRPHY_MR5_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR5_RSVD_SHIFT)) & DDRPHY_MR5_RSVD_MASK)
16134 #define DDRPHY_MR5_RESERVED_31_8_MASK            (0xFFFFFF00U)
16135 #define DDRPHY_MR5_RESERVED_31_8_SHIFT           (8U)
16136 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16137  */
16138 #define DDRPHY_MR5_RESERVED_31_8(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR5_RESERVED_31_8_SHIFT)) & DDRPHY_MR5_RESERVED_31_8_MASK)
16139 /*! @} */
16140 
16141 /*! @name MR6 - LPDDR4 Mode Register 6 */
16142 /*! @{ */
16143 #define DDRPHY_MR6_RSVD_MASK                     (0xFFU)
16144 #define DDRPHY_MR6_RSVD_SHIFT                    (0U)
16145 /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16146  */
16147 #define DDRPHY_MR6_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR6_RSVD_SHIFT)) & DDRPHY_MR6_RSVD_MASK)
16148 #define DDRPHY_MR6_RESERVED_31_8_MASK            (0xFFFFFF00U)
16149 #define DDRPHY_MR6_RESERVED_31_8_SHIFT           (8U)
16150 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16151  */
16152 #define DDRPHY_MR6_RESERVED_31_8(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR6_RESERVED_31_8_SHIFT)) & DDRPHY_MR6_RESERVED_31_8_MASK)
16153 /*! @} */
16154 
16155 /*! @name MR7 - LPDDR4 Mode Register 7 */
16156 /*! @{ */
16157 #define DDRPHY_MR7_RSVD_MASK                     (0xFFU)
16158 #define DDRPHY_MR7_RSVD_SHIFT                    (0U)
16159 /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16160  */
16161 #define DDRPHY_MR7_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR7_RSVD_SHIFT)) & DDRPHY_MR7_RSVD_MASK)
16162 #define DDRPHY_MR7_RESERVED_31_8_MASK            (0xFFFFFF00U)
16163 #define DDRPHY_MR7_RESERVED_31_8_SHIFT           (8U)
16164 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16165  */
16166 #define DDRPHY_MR7_RESERVED_31_8(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR7_RESERVED_31_8_SHIFT)) & DDRPHY_MR7_RESERVED_31_8_MASK)
16167 /*! @} */
16168 
16169 /*! @name MR11 - LPDDR4 Mode Register 11 */
16170 /*! @{ */
16171 #define DDRPHY_MR11_DQODT_MASK                   (0x7U)
16172 #define DDRPHY_MR11_DQODT_SHIFT                  (0U)
16173 /*! DQODT - DQ Bus Receiver On-Die-Termination
16174  */
16175 #define DDRPHY_MR11_DQODT(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_DQODT_SHIFT)) & DDRPHY_MR11_DQODT_MASK)
16176 #define DDRPHY_MR11_RSVD_3_MASK                  (0x8U)
16177 #define DDRPHY_MR11_RSVD_3_SHIFT                 (3U)
16178 /*! RSVD_3 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16179  */
16180 #define DDRPHY_MR11_RSVD_3(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RSVD_3_SHIFT)) & DDRPHY_MR11_RSVD_3_MASK)
16181 #define DDRPHY_MR11_CAODT_MASK                   (0x70U)
16182 #define DDRPHY_MR11_CAODT_SHIFT                  (4U)
16183 /*! CAODT - CA Bus Receiver On-Die-Termination
16184  */
16185 #define DDRPHY_MR11_CAODT(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_CAODT_SHIFT)) & DDRPHY_MR11_CAODT_MASK)
16186 #define DDRPHY_MR11_RSVD_7_MASK                  (0x80U)
16187 #define DDRPHY_MR11_RSVD_7_SHIFT                 (7U)
16188 /*! RSVD_7 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16189  */
16190 #define DDRPHY_MR11_RSVD_7(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RSVD_7_SHIFT)) & DDRPHY_MR11_RSVD_7_MASK)
16191 #define DDRPHY_MR11_RSVD_15_8_MASK               (0xFF00U)
16192 #define DDRPHY_MR11_RSVD_15_8_SHIFT              (8U)
16193 /*! RSVD_15_8 - Reserved. Return zeroes on reads.
16194  */
16195 #define DDRPHY_MR11_RSVD_15_8(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RSVD_15_8_SHIFT)) & DDRPHY_MR11_RSVD_15_8_MASK)
16196 #define DDRPHY_MR11_RESERVED_31_16_MASK          (0xFFFF0000U)
16197 #define DDRPHY_MR11_RESERVED_31_16_SHIFT         (16U)
16198 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
16199  */
16200 #define DDRPHY_MR11_RESERVED_31_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RESERVED_31_16_SHIFT)) & DDRPHY_MR11_RESERVED_31_16_MASK)
16201 /*! @} */
16202 
16203 /*! @name MR12 - LPDDR4 Mode Register 12 */
16204 /*! @{ */
16205 #define DDRPHY_MR12_VREF_CA_MASK                 (0x3FU)
16206 #define DDRPHY_MR12_VREF_CA_SHIFT                (0U)
16207 /*! VREF_CA - Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
16208  */
16209 #define DDRPHY_MR12_VREF_CA(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_VREF_CA_SHIFT)) & DDRPHY_MR12_VREF_CA_MASK)
16210 #define DDRPHY_MR12_VR_CA_MASK                   (0x40U)
16211 #define DDRPHY_MR12_VR_CA_SHIFT                  (6U)
16212 /*! VR_CA - VREF_CA Range Select.
16213  */
16214 #define DDRPHY_MR12_VR_CA(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_VR_CA_SHIFT)) & DDRPHY_MR12_VR_CA_MASK)
16215 #define DDRPHY_MR12_RSVD_MASK                    (0x80U)
16216 #define DDRPHY_MR12_RSVD_SHIFT                   (7U)
16217 /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16218  */
16219 #define DDRPHY_MR12_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_RSVD_SHIFT)) & DDRPHY_MR12_RSVD_MASK)
16220 #define DDRPHY_MR12_RESERVED_31_8_MASK           (0xFFFFFF00U)
16221 #define DDRPHY_MR12_RESERVED_31_8_SHIFT          (8U)
16222 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16223  */
16224 #define DDRPHY_MR12_RESERVED_31_8(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_RESERVED_31_8_SHIFT)) & DDRPHY_MR12_RESERVED_31_8_MASK)
16225 /*! @} */
16226 
16227 /*! @name MR13 - LPDDR4 Mode Register 13 */
16228 /*! @{ */
16229 #define DDRPHY_MR13_CBT_MASK                     (0x1U)
16230 #define DDRPHY_MR13_CBT_SHIFT                    (0U)
16231 /*! CBT - Command Bus Training
16232  */
16233 #define DDRPHY_MR13_CBT(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_CBT_SHIFT)) & DDRPHY_MR13_CBT_MASK)
16234 #define DDRPHY_MR13_RPT_MASK                     (0x2U)
16235 #define DDRPHY_MR13_RPT_SHIFT                    (1U)
16236 /*! RPT - Read Preamble Training Mode
16237  */
16238 #define DDRPHY_MR13_RPT(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_RPT_SHIFT)) & DDRPHY_MR13_RPT_MASK)
16239 #define DDRPHY_MR13_VRO_MASK                     (0x4U)
16240 #define DDRPHY_MR13_VRO_SHIFT                    (2U)
16241 /*! VRO - VREF Output
16242  */
16243 #define DDRPHY_MR13_VRO(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_VRO_SHIFT)) & DDRPHY_MR13_VRO_MASK)
16244 #define DDRPHY_MR13_VRCG_MASK                    (0x8U)
16245 #define DDRPHY_MR13_VRCG_SHIFT                   (3U)
16246 /*! VRCG - VREF Current Generator
16247  */
16248 #define DDRPHY_MR13_VRCG(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_VRCG_SHIFT)) & DDRPHY_MR13_VRCG_MASK)
16249 #define DDRPHY_MR13_RRO_MASK                     (0x10U)
16250 #define DDRPHY_MR13_RRO_SHIFT                    (4U)
16251 /*! RRO - Refresh Rate Option
16252  */
16253 #define DDRPHY_MR13_RRO(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_RRO_SHIFT)) & DDRPHY_MR13_RRO_MASK)
16254 #define DDRPHY_MR13_DMD_MASK                     (0x20U)
16255 #define DDRPHY_MR13_DMD_SHIFT                    (5U)
16256 /*! DMD - Data Mask Enable
16257  */
16258 #define DDRPHY_MR13_DMD(x)                       (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_DMD_SHIFT)) & DDRPHY_MR13_DMD_MASK)
16259 #define DDRPHY_MR13_FSPWR_MASK                   (0x40U)
16260 #define DDRPHY_MR13_FSPWR_SHIFT                  (6U)
16261 /*! FSPWR - Frequency Set Point Write Enable
16262  */
16263 #define DDRPHY_MR13_FSPWR(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_FSPWR_SHIFT)) & DDRPHY_MR13_FSPWR_MASK)
16264 #define DDRPHY_MR13_FSPOP_MASK                   (0x80U)
16265 #define DDRPHY_MR13_FSPOP_SHIFT                  (7U)
16266 /*! FSPOP - Frequency Set Point Operation Mode
16267  */
16268 #define DDRPHY_MR13_FSPOP(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_FSPOP_SHIFT)) & DDRPHY_MR13_FSPOP_MASK)
16269 #define DDRPHY_MR13_RESERVED_31_8_MASK           (0xFFFFFF00U)
16270 #define DDRPHY_MR13_RESERVED_31_8_SHIFT          (8U)
16271 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16272  */
16273 #define DDRPHY_MR13_RESERVED_31_8(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_RESERVED_31_8_SHIFT)) & DDRPHY_MR13_RESERVED_31_8_MASK)
16274 /*! @} */
16275 
16276 /*! @name MR14 - LPDDR4 Mode Register 14 */
16277 /*! @{ */
16278 #define DDRPHY_MR14_VREF_DQ_MASK                 (0x3FU)
16279 #define DDRPHY_MR14_VREF_DQ_SHIFT                (0U)
16280 /*! VREF_DQ - Reserved. Return zeroes on reads.
16281  */
16282 #define DDRPHY_MR14_VREF_DQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_VREF_DQ_SHIFT)) & DDRPHY_MR14_VREF_DQ_MASK)
16283 #define DDRPHY_MR14_VR_DQ_MASK                   (0x40U)
16284 #define DDRPHY_MR14_VR_DQ_SHIFT                  (6U)
16285 /*! VR_DQ - VREFDQ Range Selects.
16286  */
16287 #define DDRPHY_MR14_VR_DQ(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_VR_DQ_SHIFT)) & DDRPHY_MR14_VR_DQ_MASK)
16288 #define DDRPHY_MR14_RSVD_MASK                    (0x80U)
16289 #define DDRPHY_MR14_RSVD_SHIFT                   (7U)
16290 /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16291  */
16292 #define DDRPHY_MR14_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_RSVD_SHIFT)) & DDRPHY_MR14_RSVD_MASK)
16293 #define DDRPHY_MR14_RESERVED_31_8_MASK           (0xFFFFFF00U)
16294 #define DDRPHY_MR14_RESERVED_31_8_SHIFT          (8U)
16295 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16296  */
16297 #define DDRPHY_MR14_RESERVED_31_8(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_RESERVED_31_8_SHIFT)) & DDRPHY_MR14_RESERVED_31_8_MASK)
16298 /*! @} */
16299 
16300 /*! @name MR22 - LPDDR4 Mode Register 22 */
16301 /*! @{ */
16302 #define DDRPHY_MR22_CODT_MASK                    (0x7U)
16303 #define DDRPHY_MR22_CODT_SHIFT                   (0U)
16304 /*! CODT - Controller ODT value for VOH calibration.
16305  */
16306 #define DDRPHY_MR22_CODT(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_CODT_SHIFT)) & DDRPHY_MR22_CODT_MASK)
16307 #define DDRPHY_MR22_ODTE_CK_MASK                 (0x8U)
16308 #define DDRPHY_MR22_ODTE_CK_SHIFT                (3U)
16309 /*! ODTE_CK - ODT CK override.
16310  */
16311 #define DDRPHY_MR22_ODTE_CK(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_ODTE_CK_SHIFT)) & DDRPHY_MR22_ODTE_CK_MASK)
16312 #define DDRPHY_MR22_ODTE_CS_MASK                 (0x10U)
16313 #define DDRPHY_MR22_ODTE_CS_SHIFT                (4U)
16314 /*! ODTE_CS - ODT CS override.
16315  */
16316 #define DDRPHY_MR22_ODTE_CS(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_ODTE_CS_SHIFT)) & DDRPHY_MR22_ODTE_CS_MASK)
16317 #define DDRPHY_MR22_ODTD_CA_MASK                 (0x20U)
16318 #define DDRPHY_MR22_ODTD_CA_SHIFT                (5U)
16319 /*! ODTD_CA - CA ODT termination disable.
16320  */
16321 #define DDRPHY_MR22_ODTD_CA(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_ODTD_CA_SHIFT)) & DDRPHY_MR22_ODTD_CA_MASK)
16322 #define DDRPHY_MR22_RSVD_MASK                    (0xC0U)
16323 #define DDRPHY_MR22_RSVD_SHIFT                   (6U)
16324 /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16325  */
16326 #define DDRPHY_MR22_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_RSVD_SHIFT)) & DDRPHY_MR22_RSVD_MASK)
16327 #define DDRPHY_MR22_RESERVED_31_8_MASK           (0xFFFFFF00U)
16328 #define DDRPHY_MR22_RESERVED_31_8_SHIFT          (8U)
16329 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16330  */
16331 #define DDRPHY_MR22_RESERVED_31_8(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_RESERVED_31_8_SHIFT)) & DDRPHY_MR22_RESERVED_31_8_MASK)
16332 /*! @} */
16333 
16334 /*! @name DTCR0 - Data Training Configuration Register 0 */
16335 /*! @{ */
16336 #define DDRPHY_DTCR0_DTRPTN_MASK                 (0xFU)
16337 #define DDRPHY_DTCR0_DTRPTN_SHIFT                (0U)
16338 /*! DTRPTN - Data Training Repeat Number
16339  */
16340 #define DDRPHY_DTCR0_DTRPTN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTRPTN_SHIFT)) & DDRPHY_DTCR0_DTRPTN_MASK)
16341 #define DDRPHY_DTCR0_MPCWEYE_MASK                (0x10U)
16342 #define DDRPHY_DTCR0_MPCWEYE_SHIFT               (4U)
16343 /*! MPCWEYE - WEYE Training using MPC FIFO Commands
16344  */
16345 #define DDRPHY_DTCR0_MPCWEYE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_MPCWEYE_SHIFT)) & DDRPHY_DTCR0_MPCWEYE_MASK)
16346 #define DDRPHY_DTCR0_RESERVED_5_MASK             (0x20U)
16347 #define DDRPHY_DTCR0_RESERVED_5_SHIFT            (5U)
16348 /*! RESERVED_5 - Reserved. Return zeroes on reads.
16349  */
16350 #define DDRPHY_DTCR0_RESERVED_5(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RESERVED_5_SHIFT)) & DDRPHY_DTCR0_RESERVED_5_MASK)
16351 #define DDRPHY_DTCR0_DTMPR_MASK                  (0x40U)
16352 #define DDRPHY_DTCR0_DTMPR_SHIFT                 (6U)
16353 /*! DTMPR - Data Training Using MPR
16354  */
16355 #define DDRPHY_DTCR0_DTMPR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTMPR_SHIFT)) & DDRPHY_DTCR0_DTMPR_MASK)
16356 #define DDRPHY_DTCR0_DTCMPD_MASK                 (0x80U)
16357 #define DDRPHY_DTCR0_DTCMPD_SHIFT                (7U)
16358 /*! DTCMPD - Data Training Compare Data
16359  */
16360 #define DDRPHY_DTCR0_DTCMPD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTCMPD_SHIFT)) & DDRPHY_DTCR0_DTCMPD_MASK)
16361 #define DDRPHY_DTCR0_RFSHEN_MASK                 (0xF00U)
16362 #define DDRPHY_DTCR0_RFSHEN_SHIFT                (8U)
16363 /*! RFSHEN - Refreshes Issued During Entry to Training
16364  */
16365 #define DDRPHY_DTCR0_RFSHEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RFSHEN_SHIFT)) & DDRPHY_DTCR0_RFSHEN_MASK)
16366 #define DDRPHY_DTCR0_DTWBDDM_MASK                (0x1000U)
16367 #define DDRPHY_DTCR0_DTWBDDM_SHIFT               (12U)
16368 /*! DTWBDDM - Data Training Write Bit Deskew Data Mask
16369  */
16370 #define DDRPHY_DTCR0_DTWBDDM(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTWBDDM_SHIFT)) & DDRPHY_DTCR0_DTWBDDM_MASK)
16371 #define DDRPHY_DTCR0_DTBDC_MASK                  (0x2000U)
16372 #define DDRPHY_DTCR0_DTBDC_SHIFT                 (13U)
16373 /*! DTBDC - Data Training Bit Deskew Centering
16374  */
16375 #define DDRPHY_DTCR0_DTBDC(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTBDC_SHIFT)) & DDRPHY_DTCR0_DTBDC_MASK)
16376 #define DDRPHY_DTCR0_DTRDBITR_MASK               (0xC000U)
16377 #define DDRPHY_DTCR0_DTRDBITR_SHIFT              (14U)
16378 /*! DTRDBITR - Data Training read DBI deskewing configuration
16379  */
16380 #define DDRPHY_DTCR0_DTRDBITR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTRDBITR_SHIFT)) & DDRPHY_DTCR0_DTRDBITR_MASK)
16381 #define DDRPHY_DTCR0_DTDBS_MASK                  (0xF0000U)
16382 #define DDRPHY_DTCR0_DTDBS_SHIFT                 (16U)
16383 /*! DTDBS - Data Training Debug Byte Select
16384  */
16385 #define DDRPHY_DTCR0_DTDBS(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDBS_SHIFT)) & DDRPHY_DTCR0_DTDBS_MASK)
16386 #define DDRPHY_DTCR0_DTDEN_MASK                  (0x100000U)
16387 #define DDRPHY_DTCR0_DTDEN_SHIFT                 (20U)
16388 /*! DTDEN - Data Training Debug Enable
16389  */
16390 #define DDRPHY_DTCR0_DTDEN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDEN_SHIFT)) & DDRPHY_DTCR0_DTDEN_MASK)
16391 #define DDRPHY_DTCR0_DTDSTP_MASK                 (0x200000U)
16392 #define DDRPHY_DTCR0_DTDSTP_SHIFT                (21U)
16393 /*! DTDSTP - Data Training Debug Step
16394  */
16395 #define DDRPHY_DTCR0_DTDSTP(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDSTP_SHIFT)) & DDRPHY_DTCR0_DTDSTP_MASK)
16396 #define DDRPHY_DTCR0_DTEXD_MASK                  (0x400000U)
16397 #define DDRPHY_DTCR0_DTEXD_SHIFT                 (22U)
16398 /*! DTEXD - Data Training Extended Write DQS
16399  */
16400 #define DDRPHY_DTCR0_DTEXD(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTEXD_SHIFT)) & DDRPHY_DTCR0_DTEXD_MASK)
16401 #define DDRPHY_DTCR0_DTEXG_MASK                  (0x800000U)
16402 #define DDRPHY_DTCR0_DTEXG_SHIFT                 (23U)
16403 /*! DTEXG - Data Training with Early/Extended Gate
16404  */
16405 #define DDRPHY_DTCR0_DTEXG(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTEXG_SHIFT)) & DDRPHY_DTCR0_DTEXG_MASK)
16406 #define DDRPHY_DTCR0_DTDRS_MASK                  (0x3000000U)
16407 #define DDRPHY_DTCR0_DTDRS_SHIFT                 (24U)
16408 /*! DTDRS - Data Training Debug Rank Select
16409  */
16410 #define DDRPHY_DTCR0_DTDRS(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDRS_SHIFT)) & DDRPHY_DTCR0_DTDRS_MASK)
16411 #define DDRPHY_DTCR0_RESERVED_27_26_MASK         (0xC000000U)
16412 #define DDRPHY_DTCR0_RESERVED_27_26_SHIFT        (26U)
16413 /*! RESERVED_27_26 - Reserved. Return zeroes on reads.
16414  */
16415 #define DDRPHY_DTCR0_RESERVED_27_26(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RESERVED_27_26_SHIFT)) & DDRPHY_DTCR0_RESERVED_27_26_MASK)
16416 #define DDRPHY_DTCR0_RFSHDT_MASK                 (0xF0000000U)
16417 #define DDRPHY_DTCR0_RFSHDT_SHIFT                (28U)
16418 /*! RFSHDT - Refresh During Training
16419  */
16420 #define DDRPHY_DTCR0_RFSHDT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RFSHDT_SHIFT)) & DDRPHY_DTCR0_RFSHDT_MASK)
16421 /*! @} */
16422 
16423 /*! @name DTCR1 - Data Training Configuration Register 1 */
16424 /*! @{ */
16425 #define DDRPHY_DTCR1_BSTEN_MASK                  (0x1U)
16426 #define DDRPHY_DTCR1_BSTEN_SHIFT                 (0U)
16427 /*! BSTEN - Basic Gate Training Enable
16428  */
16429 #define DDRPHY_DTCR1_BSTEN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_BSTEN_SHIFT)) & DDRPHY_DTCR1_BSTEN_MASK)
16430 #define DDRPHY_DTCR1_RDLVLEN_MASK                (0x2U)
16431 #define DDRPHY_DTCR1_RDLVLEN_SHIFT               (1U)
16432 /*! RDLVLEN - Read Leveling Enable
16433  */
16434 #define DDRPHY_DTCR1_RDLVLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDLVLEN_SHIFT)) & DDRPHY_DTCR1_RDLVLEN_MASK)
16435 #define DDRPHY_DTCR1_RDPRMVL_TRN_MASK            (0x4U)
16436 #define DDRPHY_DTCR1_RDPRMVL_TRN_SHIFT           (2U)
16437 /*! RDPRMVL_TRN - Read Preamble Training enable
16438  */
16439 #define DDRPHY_DTCR1_RDPRMVL_TRN(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDPRMVL_TRN_SHIFT)) & DDRPHY_DTCR1_RDPRMVL_TRN_MASK)
16440 #define DDRPHY_DTCR1_RESERVED_3_MASK             (0x8U)
16441 #define DDRPHY_DTCR1_RESERVED_3_SHIFT            (3U)
16442 /*! RESERVED_3 - Reserved. Return zeroes on reads.
16443  */
16444 #define DDRPHY_DTCR1_RESERVED_3(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_3_SHIFT)) & DDRPHY_DTCR1_RESERVED_3_MASK)
16445 #define DDRPHY_DTCR1_RDLVLGS_MASK                (0x70U)
16446 #define DDRPHY_DTCR1_RDLVLGS_SHIFT               (4U)
16447 /*! RDLVLGS - Read Leveling Gate Shift
16448  */
16449 #define DDRPHY_DTCR1_RDLVLGS(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDLVLGS_SHIFT)) & DDRPHY_DTCR1_RDLVLGS_MASK)
16450 #define DDRPHY_DTCR1_RESERVED_7_MASK             (0x80U)
16451 #define DDRPHY_DTCR1_RESERVED_7_SHIFT            (7U)
16452 /*! RESERVED_7 - Reserved. Return zeroes on reads.
16453  */
16454 #define DDRPHY_DTCR1_RESERVED_7(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_7_SHIFT)) & DDRPHY_DTCR1_RESERVED_7_MASK)
16455 #define DDRPHY_DTCR1_RDLVLGDIFF_MASK             (0x700U)
16456 #define DDRPHY_DTCR1_RDLVLGDIFF_SHIFT            (8U)
16457 /*! RDLVLGDIFF - Read Leveling Gate Sampling Difference
16458  */
16459 #define DDRPHY_DTCR1_RDLVLGDIFF(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDLVLGDIFF_SHIFT)) & DDRPHY_DTCR1_RDLVLGDIFF_MASK)
16460 #define DDRPHY_DTCR1_RESERVED_11_MASK            (0x800U)
16461 #define DDRPHY_DTCR1_RESERVED_11_SHIFT           (11U)
16462 /*! RESERVED_11 - Reserved. Return zeroes on reads.
16463  */
16464 #define DDRPHY_DTCR1_RESERVED_11(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_11_SHIFT)) & DDRPHY_DTCR1_RESERVED_11_MASK)
16465 #define DDRPHY_DTCR1_DTRANK_MASK                 (0x3000U)
16466 #define DDRPHY_DTCR1_DTRANK_SHIFT                (12U)
16467 /*! DTRANK - Data Training Rank
16468  */
16469 #define DDRPHY_DTCR1_DTRANK(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_DTRANK_SHIFT)) & DDRPHY_DTCR1_DTRANK_MASK)
16470 #define DDRPHY_DTCR1_RESERVED_15_14_MASK         (0xC000U)
16471 #define DDRPHY_DTCR1_RESERVED_15_14_SHIFT        (14U)
16472 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
16473  */
16474 #define DDRPHY_DTCR1_RESERVED_15_14(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_15_14_SHIFT)) & DDRPHY_DTCR1_RESERVED_15_14_MASK)
16475 #define DDRPHY_DTCR1_RANKEN_MASK                 (0x10000U)
16476 #define DDRPHY_DTCR1_RANKEN_SHIFT                (16U)
16477 /*! RANKEN - Rank Enable.
16478  */
16479 #define DDRPHY_DTCR1_RANKEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RANKEN_SHIFT)) & DDRPHY_DTCR1_RANKEN_MASK)
16480 #define DDRPHY_DTCR1_RANKEN_RSVD_MASK            (0xFFFE0000U)
16481 #define DDRPHY_DTCR1_RANKEN_RSVD_SHIFT           (17U)
16482 /*! RANKEN_RSVD - Rank Enable.
16483  */
16484 #define DDRPHY_DTCR1_RANKEN_RSVD(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RANKEN_RSVD_SHIFT)) & DDRPHY_DTCR1_RANKEN_RSVD_MASK)
16485 /*! @} */
16486 
16487 /*! @name DTAR0 - Data Training Address Register 0 */
16488 /*! @{ */
16489 #define DDRPHY_DTAR0_DTROW_MASK                  (0x3FFFFU)
16490 #define DDRPHY_DTAR0_DTROW_SHIFT                 (0U)
16491 /*! DTROW - Data Training Row Address
16492  */
16493 #define DDRPHY_DTAR0_DTROW(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_DTROW_SHIFT)) & DDRPHY_DTAR0_DTROW_MASK)
16494 #define DDRPHY_DTAR0_RESERVED_19_18_MASK         (0xC0000U)
16495 #define DDRPHY_DTAR0_RESERVED_19_18_SHIFT        (18U)
16496 /*! RESERVED_19_18 - Reserved. Return zeroes on reads.
16497  */
16498 #define DDRPHY_DTAR0_RESERVED_19_18(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_RESERVED_19_18_SHIFT)) & DDRPHY_DTAR0_RESERVED_19_18_MASK)
16499 #define DDRPHY_DTAR0_DTBGBK0_MASK                (0xF00000U)
16500 #define DDRPHY_DTAR0_DTBGBK0_SHIFT               (20U)
16501 /*! DTBGBK0 - Data Training Bank Group and Bank Address
16502  */
16503 #define DDRPHY_DTAR0_DTBGBK0(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_DTBGBK0_SHIFT)) & DDRPHY_DTAR0_DTBGBK0_MASK)
16504 #define DDRPHY_DTAR0_DTBGBK1_MASK                (0xF000000U)
16505 #define DDRPHY_DTAR0_DTBGBK1_SHIFT               (24U)
16506 /*! DTBGBK1 - Data Training Bank Group and Bank Address
16507  */
16508 #define DDRPHY_DTAR0_DTBGBK1(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_DTBGBK1_SHIFT)) & DDRPHY_DTAR0_DTBGBK1_MASK)
16509 #define DDRPHY_DTAR0_MPRLOC_MASK                 (0x30000000U)
16510 #define DDRPHY_DTAR0_MPRLOC_SHIFT                (28U)
16511 /*! MPRLOC - Multi-Purpose Register (MPR) Location
16512  */
16513 #define DDRPHY_DTAR0_MPRLOC(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_MPRLOC_SHIFT)) & DDRPHY_DTAR0_MPRLOC_MASK)
16514 #define DDRPHY_DTAR0_RESERVED_31_30_MASK         (0xC0000000U)
16515 #define DDRPHY_DTAR0_RESERVED_31_30_SHIFT        (30U)
16516 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
16517  */
16518 #define DDRPHY_DTAR0_RESERVED_31_30(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_RESERVED_31_30_SHIFT)) & DDRPHY_DTAR0_RESERVED_31_30_MASK)
16519 /*! @} */
16520 
16521 /*! @name DTAR1 - Data Training Address Register 1 */
16522 /*! @{ */
16523 #define DDRPHY_DTAR1_DTCOL0_MASK                 (0x1FFU)
16524 #define DDRPHY_DTAR1_DTCOL0_SHIFT                (0U)
16525 /*! DTCOL0 - Data Training Column Address
16526  */
16527 #define DDRPHY_DTAR1_DTCOL0(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_DTCOL0_SHIFT)) & DDRPHY_DTAR1_DTCOL0_MASK)
16528 #define DDRPHY_DTAR1_RESERVED_15_9_MASK          (0xFE00U)
16529 #define DDRPHY_DTAR1_RESERVED_15_9_SHIFT         (9U)
16530 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
16531  */
16532 #define DDRPHY_DTAR1_RESERVED_15_9(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_RESERVED_15_9_SHIFT)) & DDRPHY_DTAR1_RESERVED_15_9_MASK)
16533 #define DDRPHY_DTAR1_DTCOL1_MASK                 (0x1FF0000U)
16534 #define DDRPHY_DTAR1_DTCOL1_SHIFT                (16U)
16535 /*! DTCOL1 - Data Training Column Address
16536  */
16537 #define DDRPHY_DTAR1_DTCOL1(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_DTCOL1_SHIFT)) & DDRPHY_DTAR1_DTCOL1_MASK)
16538 #define DDRPHY_DTAR1_RESERVED_31_25_MASK         (0xFE000000U)
16539 #define DDRPHY_DTAR1_RESERVED_31_25_SHIFT        (25U)
16540 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
16541  */
16542 #define DDRPHY_DTAR1_RESERVED_31_25(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_RESERVED_31_25_SHIFT)) & DDRPHY_DTAR1_RESERVED_31_25_MASK)
16543 /*! @} */
16544 
16545 /*! @name DTAR2 - Data Training Address Register 2 */
16546 /*! @{ */
16547 #define DDRPHY_DTAR2_DTCOL2_MASK                 (0x1FFU)
16548 #define DDRPHY_DTAR2_DTCOL2_SHIFT                (0U)
16549 /*! DTCOL2 - Data Training Column Address
16550  */
16551 #define DDRPHY_DTAR2_DTCOL2(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_DTCOL2_SHIFT)) & DDRPHY_DTAR2_DTCOL2_MASK)
16552 #define DDRPHY_DTAR2_RESERVED_15_9_MASK          (0xFE00U)
16553 #define DDRPHY_DTAR2_RESERVED_15_9_SHIFT         (9U)
16554 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
16555  */
16556 #define DDRPHY_DTAR2_RESERVED_15_9(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_RESERVED_15_9_SHIFT)) & DDRPHY_DTAR2_RESERVED_15_9_MASK)
16557 #define DDRPHY_DTAR2_DTCOL3_MASK                 (0x1FF0000U)
16558 #define DDRPHY_DTAR2_DTCOL3_SHIFT                (16U)
16559 /*! DTCOL3 - Data Training Column Address
16560  */
16561 #define DDRPHY_DTAR2_DTCOL3(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_DTCOL3_SHIFT)) & DDRPHY_DTAR2_DTCOL3_MASK)
16562 #define DDRPHY_DTAR2_RESERVED_31_25_MASK         (0xFE000000U)
16563 #define DDRPHY_DTAR2_RESERVED_31_25_SHIFT        (25U)
16564 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
16565  */
16566 #define DDRPHY_DTAR2_RESERVED_31_25(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_RESERVED_31_25_SHIFT)) & DDRPHY_DTAR2_RESERVED_31_25_MASK)
16567 /*! @} */
16568 
16569 /*! @name DTDR0 - Data Training Data Register 0 */
16570 /*! @{ */
16571 #define DDRPHY_DTDR0_DTBYTE0_MASK                (0xFFU)
16572 #define DDRPHY_DTDR0_DTBYTE0_SHIFT               (0U)
16573 /*! DTBYTE0 - Data Training Data
16574  */
16575 #define DDRPHY_DTDR0_DTBYTE0(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE0_SHIFT)) & DDRPHY_DTDR0_DTBYTE0_MASK)
16576 #define DDRPHY_DTDR0_DTBYTE1_MASK                (0xFF00U)
16577 #define DDRPHY_DTDR0_DTBYTE1_SHIFT               (8U)
16578 /*! DTBYTE1 - Data Training Data
16579  */
16580 #define DDRPHY_DTDR0_DTBYTE1(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE1_SHIFT)) & DDRPHY_DTDR0_DTBYTE1_MASK)
16581 #define DDRPHY_DTDR0_DTBYTE2_MASK                (0xFF0000U)
16582 #define DDRPHY_DTDR0_DTBYTE2_SHIFT               (16U)
16583 /*! DTBYTE2 - Data Training Data
16584  */
16585 #define DDRPHY_DTDR0_DTBYTE2(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE2_SHIFT)) & DDRPHY_DTDR0_DTBYTE2_MASK)
16586 #define DDRPHY_DTDR0_DTBYTE3_MASK                (0xFF000000U)
16587 #define DDRPHY_DTDR0_DTBYTE3_SHIFT               (24U)
16588 /*! DTBYTE3 - Data Training Data
16589  */
16590 #define DDRPHY_DTDR0_DTBYTE3(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE3_SHIFT)) & DDRPHY_DTDR0_DTBYTE3_MASK)
16591 /*! @} */
16592 
16593 /*! @name DTDR1 - Data Training Data Register 1 */
16594 /*! @{ */
16595 #define DDRPHY_DTDR1_DTBYTE4_MASK                (0xFFU)
16596 #define DDRPHY_DTDR1_DTBYTE4_SHIFT               (0U)
16597 /*! DTBYTE4 - Data Training Data
16598  */
16599 #define DDRPHY_DTDR1_DTBYTE4(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE4_SHIFT)) & DDRPHY_DTDR1_DTBYTE4_MASK)
16600 #define DDRPHY_DTDR1_DTBYTE5_MASK                (0xFF00U)
16601 #define DDRPHY_DTDR1_DTBYTE5_SHIFT               (8U)
16602 /*! DTBYTE5 - Data Training Data
16603  */
16604 #define DDRPHY_DTDR1_DTBYTE5(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE5_SHIFT)) & DDRPHY_DTDR1_DTBYTE5_MASK)
16605 #define DDRPHY_DTDR1_DTBYTE6_MASK                (0xFF0000U)
16606 #define DDRPHY_DTDR1_DTBYTE6_SHIFT               (16U)
16607 /*! DTBYTE6 - Data Training Data
16608  */
16609 #define DDRPHY_DTDR1_DTBYTE6(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE6_SHIFT)) & DDRPHY_DTDR1_DTBYTE6_MASK)
16610 #define DDRPHY_DTDR1_DTBYTE7_MASK                (0xFF000000U)
16611 #define DDRPHY_DTDR1_DTBYTE7_SHIFT               (24U)
16612 /*! DTBYTE7 - Data Training Data
16613  */
16614 #define DDRPHY_DTDR1_DTBYTE7(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE7_SHIFT)) & DDRPHY_DTDR1_DTBYTE7_MASK)
16615 /*! @} */
16616 
16617 /*! @name DTEDR0 - Data Training Eye Data Register 0 */
16618 /*! @{ */
16619 #define DDRPHY_DTEDR0_WDQLMN_MASK                (0x1FFU)
16620 #define DDRPHY_DTEDR0_WDQLMN_SHIFT               (0U)
16621 /*! WDQLMN - Data Training WDQ LCDL Minimum.
16622  */
16623 #define DDRPHY_DTEDR0_WDQLMN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQLMN_SHIFT)) & DDRPHY_DTEDR0_WDQLMN_MASK)
16624 #define DDRPHY_DTEDR0_WDQLMX_MASK                (0x3FE00U)
16625 #define DDRPHY_DTEDR0_WDQLMX_SHIFT               (9U)
16626 /*! WDQLMX - Data Training WDQ LCDL Maximum.
16627  */
16628 #define DDRPHY_DTEDR0_WDQLMX(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQLMX_SHIFT)) & DDRPHY_DTEDR0_WDQLMX_MASK)
16629 #define DDRPHY_DTEDR0_WDQBMN_MASK                (0xFC0000U)
16630 #define DDRPHY_DTEDR0_WDQBMN_SHIFT               (18U)
16631 /*! WDQBMN - Data Training Write BDL Shift Minimum.
16632  */
16633 #define DDRPHY_DTEDR0_WDQBMN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQBMN_SHIFT)) & DDRPHY_DTEDR0_WDQBMN_MASK)
16634 #define DDRPHY_DTEDR0_WDQBMX_MASK                (0xFF000000U)
16635 #define DDRPHY_DTEDR0_WDQBMX_SHIFT               (24U)
16636 /*! WDQBMX - Data Training Write BDL Shift Maximum.
16637  */
16638 #define DDRPHY_DTEDR0_WDQBMX(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQBMX_SHIFT)) & DDRPHY_DTEDR0_WDQBMX_MASK)
16639 /*! @} */
16640 
16641 /*! @name DTEDR1 - Data Training Eye Data Register 1 */
16642 /*! @{ */
16643 #define DDRPHY_DTEDR1_RDQSLMN_MASK               (0x1FFU)
16644 #define DDRPHY_DTEDR1_RDQSLMN_SHIFT              (0U)
16645 /*! RDQSLMN - Data Training RDQS LCDL Minimum.
16646  */
16647 #define DDRPHY_DTEDR1_RDQSLMN(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSLMN_SHIFT)) & DDRPHY_DTEDR1_RDQSLMN_MASK)
16648 #define DDRPHY_DTEDR1_RDQSLMX_MASK               (0x3FE00U)
16649 #define DDRPHY_DTEDR1_RDQSLMX_SHIFT              (9U)
16650 /*! RDQSLMX - Data Training RDQS LCDL Maximum.
16651  */
16652 #define DDRPHY_DTEDR1_RDQSLMX(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSLMX_SHIFT)) & DDRPHY_DTEDR1_RDQSLMX_MASK)
16653 #define DDRPHY_DTEDR1_RDQSBMN_MASK               (0xFC0000U)
16654 #define DDRPHY_DTEDR1_RDQSBMN_SHIFT              (18U)
16655 /*! RDQSBMN - Data Training Read BDL Shift Minimum.
16656  */
16657 #define DDRPHY_DTEDR1_RDQSBMN(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSBMN_SHIFT)) & DDRPHY_DTEDR1_RDQSBMN_MASK)
16658 #define DDRPHY_DTEDR1_RDQSBMX_MASK               (0xFF000000U)
16659 #define DDRPHY_DTEDR1_RDQSBMX_SHIFT              (24U)
16660 /*! RDQSBMX - Data Training Read BDL Shift Maximum.
16661  */
16662 #define DDRPHY_DTEDR1_RDQSBMX(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSBMX_SHIFT)) & DDRPHY_DTEDR1_RDQSBMX_MASK)
16663 /*! @} */
16664 
16665 /*! @name DTEDR2 - Data Training Eye Data Register 2 */
16666 /*! @{ */
16667 #define DDRPHY_DTEDR2_RDQSNLMN_MASK              (0x1FFU)
16668 #define DDRPHY_DTEDR2_RDQSNLMN_SHIFT             (0U)
16669 /*! RDQSNLMN - Data Training RDQSN LCDL Minimum.
16670  */
16671 #define DDRPHY_DTEDR2_RDQSNLMN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNLMN_SHIFT)) & DDRPHY_DTEDR2_RDQSNLMN_MASK)
16672 #define DDRPHY_DTEDR2_RDQSNLMX_MASK              (0x3FE00U)
16673 #define DDRPHY_DTEDR2_RDQSNLMX_SHIFT             (9U)
16674 /*! RDQSNLMX - Data Training RDQSN LCDL Maximum.
16675  */
16676 #define DDRPHY_DTEDR2_RDQSNLMX(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNLMX_SHIFT)) & DDRPHY_DTEDR2_RDQSNLMX_MASK)
16677 #define DDRPHY_DTEDR2_RDQSNBMN_MASK              (0xFC0000U)
16678 #define DDRPHY_DTEDR2_RDQSNBMN_SHIFT             (18U)
16679 /*! RDQSNBMN - Data Training Read BDL Shift Minimum.
16680  */
16681 #define DDRPHY_DTEDR2_RDQSNBMN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNBMN_SHIFT)) & DDRPHY_DTEDR2_RDQSNBMN_MASK)
16682 #define DDRPHY_DTEDR2_RDQSNBMX_MASK              (0xFF000000U)
16683 #define DDRPHY_DTEDR2_RDQSNBMX_SHIFT             (24U)
16684 /*! RDQSNBMX - Data Training Read BDL Shift Maximum.
16685  */
16686 #define DDRPHY_DTEDR2_RDQSNBMX(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNBMX_SHIFT)) & DDRPHY_DTEDR2_RDQSNBMX_MASK)
16687 /*! @} */
16688 
16689 /*! @name VTDR - VREF Training Data Register */
16690 /*! @{ */
16691 #define DDRPHY_VTDR_DVREFMN_MASK                 (0x3FU)
16692 #define DDRPHY_VTDR_DVREFMN_SHIFT                (0U)
16693 /*! DVREFMN - DRAM DQ VREF Minimum.
16694  */
16695 #define DDRPHY_VTDR_DVREFMN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_DVREFMN_SHIFT)) & DDRPHY_VTDR_DVREFMN_MASK)
16696 #define DDRPHY_VTDR_RESERVED_7_6_MASK            (0xC0U)
16697 #define DDRPHY_VTDR_RESERVED_7_6_SHIFT           (6U)
16698 /*! RESERVED_7_6 - Reserved. Returns zeroes on reads.
16699  */
16700 #define DDRPHY_VTDR_RESERVED_7_6(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_7_6_SHIFT)) & DDRPHY_VTDR_RESERVED_7_6_MASK)
16701 #define DDRPHY_VTDR_DVREFMX_MASK                 (0x3F00U)
16702 #define DDRPHY_VTDR_DVREFMX_SHIFT                (8U)
16703 /*! DVREFMX - DRAM DQ VREF Maximum.
16704  */
16705 #define DDRPHY_VTDR_DVREFMX(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_DVREFMX_SHIFT)) & DDRPHY_VTDR_DVREFMX_MASK)
16706 #define DDRPHY_VTDR_RESERVED_15_14_MASK          (0xC000U)
16707 #define DDRPHY_VTDR_RESERVED_15_14_SHIFT         (14U)
16708 /*! RESERVED_15_14 - Reserved. Returns zeroes on reads.
16709  */
16710 #define DDRPHY_VTDR_RESERVED_15_14(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_15_14_SHIFT)) & DDRPHY_VTDR_RESERVED_15_14_MASK)
16711 #define DDRPHY_VTDR_HVREFMN_MASK                 (0x7F0000U)
16712 #define DDRPHY_VTDR_HVREFMN_SHIFT                (16U)
16713 /*! HVREFMN - DRAM DQ VREF Minimum.
16714  */
16715 #define DDRPHY_VTDR_HVREFMN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_HVREFMN_SHIFT)) & DDRPHY_VTDR_HVREFMN_MASK)
16716 #define DDRPHY_VTDR_RESERVED_23_MASK             (0x800000U)
16717 #define DDRPHY_VTDR_RESERVED_23_SHIFT            (23U)
16718 /*! RESERVED_23 - Reserved. Returns zeroes on reads.
16719  */
16720 #define DDRPHY_VTDR_RESERVED_23(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_23_SHIFT)) & DDRPHY_VTDR_RESERVED_23_MASK)
16721 #define DDRPHY_VTDR_HVREFMX_MASK                 (0x7F000000U)
16722 #define DDRPHY_VTDR_HVREFMX_SHIFT                (24U)
16723 /*! HVREFMX - DRAM DQ VREF Maximum.
16724  */
16725 #define DDRPHY_VTDR_HVREFMX(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_HVREFMX_SHIFT)) & DDRPHY_VTDR_HVREFMX_MASK)
16726 #define DDRPHY_VTDR_RESERVED_31_MASK             (0x80000000U)
16727 #define DDRPHY_VTDR_RESERVED_31_SHIFT            (31U)
16728 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
16729  */
16730 #define DDRPHY_VTDR_RESERVED_31(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_31_SHIFT)) & DDRPHY_VTDR_RESERVED_31_MASK)
16731 /*! @} */
16732 
16733 /*! @name CATR0 - CA Training Register 0 */
16734 /*! @{ */
16735 #define DDRPHY_CATR0_CA1BYTE0_MASK               (0xFU)
16736 #define DDRPHY_CATR0_CA1BYTE0_SHIFT              (0U)
16737 /*! CA1BYTE0 - CA_1 Response Byte Lane 0
16738  */
16739 #define DDRPHY_CATR0_CA1BYTE0(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CA1BYTE0_SHIFT)) & DDRPHY_CATR0_CA1BYTE0_MASK)
16740 #define DDRPHY_CATR0_CA1BYTE1_MASK               (0xF0U)
16741 #define DDRPHY_CATR0_CA1BYTE1_SHIFT              (4U)
16742 /*! CA1BYTE1 - CA_1 Response Byte Lane 1
16743  */
16744 #define DDRPHY_CATR0_CA1BYTE1(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CA1BYTE1_SHIFT)) & DDRPHY_CATR0_CA1BYTE1_MASK)
16745 #define DDRPHY_CATR0_CAADR_MASK                  (0x1F00U)
16746 #define DDRPHY_CATR0_CAADR_SHIFT                 (8U)
16747 /*! CAADR - Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA
16748  *    response after Calibration command has been sent to the memory
16749  */
16750 #define DDRPHY_CATR0_CAADR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CAADR_SHIFT)) & DDRPHY_CATR0_CAADR_MASK)
16751 #define DDRPHY_CATR0_RESERVED_15_13_MASK         (0xE000U)
16752 #define DDRPHY_CATR0_RESERVED_15_13_SHIFT        (13U)
16753 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
16754  */
16755 #define DDRPHY_CATR0_RESERVED_15_13(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_RESERVED_15_13_SHIFT)) & DDRPHY_CATR0_RESERVED_15_13_MASK)
16756 #define DDRPHY_CATR0_CACD_MASK                   (0x1F0000U)
16757 #define DDRPHY_CATR0_CACD_SHIFT                  (16U)
16758 /*! CACD - Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command
16759  */
16760 #define DDRPHY_CATR0_CACD(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CACD_SHIFT)) & DDRPHY_CATR0_CACD_MASK)
16761 #define DDRPHY_CATR0_RESERVED_31_21_MASK         (0xFFE00000U)
16762 #define DDRPHY_CATR0_RESERVED_31_21_SHIFT        (21U)
16763 /*! RESERVED_31_21 - Reserved. Return zeroes on reads.
16764  */
16765 #define DDRPHY_CATR0_RESERVED_31_21(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_RESERVED_31_21_SHIFT)) & DDRPHY_CATR0_RESERVED_31_21_MASK)
16766 /*! @} */
16767 
16768 /*! @name CATR1 - CA Training Register 1 */
16769 /*! @{ */
16770 #define DDRPHY_CATR1_CAENT_MASK                  (0xFU)
16771 #define DDRPHY_CATR1_CAENT_SHIFT                 (0U)
16772 /*! CAENT - Minimum time (in terms of number of dram clocks) for first CA calibration command after CKE is low
16773  */
16774 #define DDRPHY_CATR1_CAENT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CAENT_SHIFT)) & DDRPHY_CATR1_CAENT_MASK)
16775 #define DDRPHY_CATR1_CAEXT_MASK                  (0xF0U)
16776 #define DDRPHY_CATR1_CAEXT_SHIFT                 (4U)
16777 /*! CAEXT - Minimum time (in terms of number of dram clocks) for CA calibration exit command after CKE is high
16778  */
16779 #define DDRPHY_CATR1_CAEXT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CAEXT_SHIFT)) & DDRPHY_CATR1_CAEXT_MASK)
16780 #define DDRPHY_CATR1_CACKEL_MASK                 (0xF00U)
16781 #define DDRPHY_CATR1_CACKEL_SHIFT                (8U)
16782 /*! CACKEL - Minimum time (in terms of number of dram clocks) for CKE going low after CA calibration mode is programmed
16783  */
16784 #define DDRPHY_CATR1_CACKEL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CACKEL_SHIFT)) & DDRPHY_CATR1_CACKEL_MASK)
16785 #define DDRPHY_CATR1_CACKEH_MASK                 (0xF000U)
16786 #define DDRPHY_CATR1_CACKEH_SHIFT                (12U)
16787 /*! CACKEH - Minimum time (in terms of number of dram clocks) for CKE high after last CA calibration response is driven by memory
16788  */
16789 #define DDRPHY_CATR1_CACKEH(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CACKEH_SHIFT)) & DDRPHY_CATR1_CACKEH_MASK)
16790 #define DDRPHY_CATR1_CAMRZ_MASK                  (0xF0000U)
16791 #define DDRPHY_CATR1_CAMRZ_SHIFT                 (16U)
16792 /*! CAMRZ - Minimum time (in terms of number of dram clocks) for DRAM DQ going tristate after MRW CA exit calibration command
16793  */
16794 #define DDRPHY_CATR1_CAMRZ(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CAMRZ_SHIFT)) & DDRPHY_CATR1_CAMRZ_MASK)
16795 #define DDRPHY_CATR1_CA0BYTE0_MASK               (0xF00000U)
16796 #define DDRPHY_CATR1_CA0BYTE0_SHIFT              (20U)
16797 /*! CA0BYTE0 - CA_0 Response Byte Lane 0
16798  */
16799 #define DDRPHY_CATR1_CA0BYTE0(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CA0BYTE0_SHIFT)) & DDRPHY_CATR1_CA0BYTE0_MASK)
16800 #define DDRPHY_CATR1_CA0BYTE1_MASK               (0xF000000U)
16801 #define DDRPHY_CATR1_CA0BYTE1_SHIFT              (24U)
16802 /*! CA0BYTE1 - CA_0 Response Byte Lane 1
16803  */
16804 #define DDRPHY_CATR1_CA0BYTE1(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CA0BYTE1_SHIFT)) & DDRPHY_CATR1_CA0BYTE1_MASK)
16805 #define DDRPHY_CATR1_RESERVED_31_28_MASK         (0xF0000000U)
16806 #define DDRPHY_CATR1_RESERVED_31_28_SHIFT        (28U)
16807 /*! RESERVED_31_28 - Reserved. Return zeroes on reads.
16808  */
16809 #define DDRPHY_CATR1_RESERVED_31_28(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_RESERVED_31_28_SHIFT)) & DDRPHY_CATR1_RESERVED_31_28_MASK)
16810 /*! @} */
16811 
16812 /*! @name PGCR8 - PHY General Configuration Register 8 */
16813 /*! @{ */
16814 #define DDRPHY_PGCR8_BSWAPMSB_MASK               (0x1FFU)
16815 #define DDRPHY_PGCR8_BSWAPMSB_SHIFT              (0U)
16816 /*! BSWAPMSB - When a bit is set, it indicates that the corresponding PHY byte lane is connected to
16817  *    MSByte of the LPDDR4 DRAM 16 bit instance it is connected to.
16818  */
16819 #define DDRPHY_PGCR8_BSWAPMSB(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_BSWAPMSB_SHIFT)) & DDRPHY_PGCR8_BSWAPMSB_MASK)
16820 #define DDRPHY_PGCR8_RESERVED_13_9_MASK          (0x3E00U)
16821 #define DDRPHY_PGCR8_RESERVED_13_9_SHIFT         (9U)
16822 /*! RESERVED_13_9 - Reserved. Return zeroes on reads.
16823  */
16824 #define DDRPHY_PGCR8_RESERVED_13_9(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_RESERVED_13_9_SHIFT)) & DDRPHY_PGCR8_RESERVED_13_9_MASK)
16825 #define DDRPHY_PGCR8_INC_DQS2DQ_EN_MASK          (0x4000U)
16826 #define DDRPHY_PGCR8_INC_DQS2DQ_EN_SHIFT         (14U)
16827 /*! INC_DQS2DQ_EN - Incremental DQS2DQ Training
16828  */
16829 #define DDRPHY_PGCR8_INC_DQS2DQ_EN(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_EN_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_EN_MASK)
16830 #define DDRPHY_PGCR8_INC_DQS2DQ_MODE_MASK        (0x8000U)
16831 #define DDRPHY_PGCR8_INC_DQS2DQ_MODE_SHIFT       (15U)
16832 /*! INC_DQS2DQ_MODE - Self Incremental DQS2DQ Training
16833  */
16834 #define DDRPHY_PGCR8_INC_DQS2DQ_MODE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_MODE_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_MODE_MASK)
16835 #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_MASK      (0x10000U)
16836 #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_SHIFT     (16U)
16837 /*! INC_DQS2DQ_RANKEN - Rank Enable
16838  */
16839 #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_MASK)
16840 #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_MASK (0xE0000U)
16841 #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_SHIFT (17U)
16842 /*! INC_DQS2DQ_RANKEN_RSVD - Rank Enable
16843  */
16844 #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD(x)   (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_MASK)
16845 #define DDRPHY_PGCR8_INC_DQS2DQ_CM_MASK          (0xFF00000U)
16846 #define DDRPHY_PGCR8_INC_DQS2DQ_CM_SHIFT         (20U)
16847 /*! INC_DQS2DQ_CM - Counter Cycle Multiplier
16848  */
16849 #define DDRPHY_PGCR8_INC_DQS2DQ_CM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_CM_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_CM_MASK)
16850 #define DDRPHY_PGCR8_INC_DQS2DQ_CF_MASK          (0xF0000000U)
16851 #define DDRPHY_PGCR8_INC_DQS2DQ_CF_SHIFT         (28U)
16852 /*! INC_DQS2DQ_CF - Counter Cycles Factor
16853  */
16854 #define DDRPHY_PGCR8_INC_DQS2DQ_CF(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_CF_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_CF_MASK)
16855 /*! @} */
16856 
16857 /*! @name DQSDR0 - DQS Drift Register 0 */
16858 /*! @{ */
16859 #define DDRPHY_DQSDR0_DFTDTEN_MASK               (0x1U)
16860 #define DDRPHY_DQSDR0_DFTDTEN_SHIFT              (0U)
16861 /*! DFTDTEN - DQS Drift Detection Enable
16862  */
16863 #define DDRPHY_DQSDR0_DFTDTEN(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDTEN_SHIFT)) & DDRPHY_DQSDR0_DFTDTEN_MASK)
16864 #define DDRPHY_DQSDR0_DFTDTMODE_MASK             (0x2U)
16865 #define DDRPHY_DQSDR0_DFTDTMODE_SHIFT            (1U)
16866 /*! DFTDTMODE - DQS Drift Detection Mode
16867  */
16868 #define DDRPHY_DQSDR0_DFTDTMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDTMODE_SHIFT)) & DDRPHY_DQSDR0_DFTDTMODE_MASK)
16869 #define DDRPHY_DQSDR0_DFTUPMODE_MASK             (0xCU)
16870 #define DDRPHY_DQSDR0_DFTUPMODE_SHIFT            (2U)
16871 /*! DFTUPMODE - DQS Drift Update Mode
16872  */
16873 #define DDRPHY_DQSDR0_DFTUPMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTUPMODE_SHIFT)) & DDRPHY_DQSDR0_DFTUPMODE_MASK)
16874 #define DDRPHY_DQSDR0_DFTGPULSE_MASK             (0xF0U)
16875 #define DDRPHY_DQSDR0_DFTGPULSE_SHIFT            (4U)
16876 /*! DFTGPULSE - Gate Pulse Enable
16877  */
16878 #define DDRPHY_DQSDR0_DFTGPULSE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTGPULSE_SHIFT)) & DDRPHY_DQSDR0_DFTGPULSE_MASK)
16879 #define DDRPHY_DQSDR0_RESERVED_11_8_MASK         (0xF00U)
16880 #define DDRPHY_DQSDR0_RESERVED_11_8_SHIFT        (8U)
16881 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
16882  */
16883 #define DDRPHY_DQSDR0_RESERVED_11_8(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_RESERVED_11_8_SHIFT)) & DDRPHY_DQSDR0_RESERVED_11_8_MASK)
16884 #define DDRPHY_DQSDR0_DFTIDLRD_MASK              (0xF000U)
16885 #define DDRPHY_DQSDR0_DFTIDLRD_SHIFT             (12U)
16886 /*! DFTIDLRD - Drift Idle Reads
16887  */
16888 #define DDRPHY_DQSDR0_DFTIDLRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTIDLRD_SHIFT)) & DDRPHY_DQSDR0_DFTIDLRD_MASK)
16889 #define DDRPHY_DQSDR0_DFTB2BRD_MASK              (0xF0000U)
16890 #define DDRPHY_DQSDR0_DFTB2BRD_SHIFT             (16U)
16891 /*! DFTB2BRD - Drift Back-to-Back Reads
16892  */
16893 #define DDRPHY_DQSDR0_DFTB2BRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTB2BRD_SHIFT)) & DDRPHY_DQSDR0_DFTB2BRD_MASK)
16894 #define DDRPHY_DQSDR0_DFTRDSPC_MASK              (0x300000U)
16895 #define DDRPHY_DQSDR0_DFTRDSPC_SHIFT             (20U)
16896 /*! DFTRDSPC - Drift Read Spacing
16897  */
16898 #define DDRPHY_DQSDR0_DFTRDSPC(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTRDSPC_SHIFT)) & DDRPHY_DQSDR0_DFTRDSPC_MASK)
16899 #define DDRPHY_DQSDR0_RESERVED_25_22_MASK        (0x3C00000U)
16900 #define DDRPHY_DQSDR0_RESERVED_25_22_SHIFT       (22U)
16901 /*! RESERVED_25_22 - Reserved. Return zeroes on reads.
16902  */
16903 #define DDRPHY_DQSDR0_RESERVED_25_22(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_RESERVED_25_22_SHIFT)) & DDRPHY_DQSDR0_RESERVED_25_22_MASK)
16904 #define DDRPHY_DQSDR0_DFTDDLUP_MASK              (0x4000000U)
16905 #define DDRPHY_DQSDR0_DFTDDLUP_SHIFT             (26U)
16906 /*! DFTDDLUP - Drift DDL Update
16907  */
16908 #define DDRPHY_DQSDR0_DFTDDLUP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDDLUP_SHIFT)) & DDRPHY_DQSDR0_DFTDDLUP_MASK)
16909 #define DDRPHY_DQSDR0_DFTZQUP_MASK               (0x8000000U)
16910 #define DDRPHY_DQSDR0_DFTZQUP_SHIFT              (27U)
16911 /*! DFTZQUP - Drift Impedance Update
16912  */
16913 #define DDRPHY_DQSDR0_DFTZQUP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTZQUP_SHIFT)) & DDRPHY_DQSDR0_DFTZQUP_MASK)
16914 #define DDRPHY_DQSDR0_DFTDLY_MASK                (0xF0000000U)
16915 #define DDRPHY_DQSDR0_DFTDLY_SHIFT               (28U)
16916 /*! DFTDLY - Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected
16917  */
16918 #define DDRPHY_DQSDR0_DFTDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDLY_SHIFT)) & DDRPHY_DQSDR0_DFTDLY_MASK)
16919 /*! @} */
16920 
16921 /*! @name DQSDR1 - DQS Drift Register 1 */
16922 /*! @{ */
16923 #define DDRPHY_DQSDR1_DFTRDIDLC_MASK             (0xFFU)
16924 #define DDRPHY_DQSDR1_DFTRDIDLC_SHIFT            (0U)
16925 /*! DFTRDIDLC - Drift Idle Read Cycles
16926  */
16927 #define DDRPHY_DQSDR1_DFTRDIDLC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDIDLC_SHIFT)) & DDRPHY_DQSDR1_DFTRDIDLC_MASK)
16928 #define DDRPHY_DQSDR1_DFTRDB2BC_MASK             (0xFF00U)
16929 #define DDRPHY_DQSDR1_DFTRDB2BC_SHIFT            (8U)
16930 /*! DFTRDB2BC - Drift Back-to-Back Read Cycles
16931  */
16932 #define DDRPHY_DQSDR1_DFTRDB2BC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDB2BC_SHIFT)) & DDRPHY_DQSDR1_DFTRDB2BC_MASK)
16933 #define DDRPHY_DQSDR1_DFTRDIDLF_MASK             (0xF0000U)
16934 #define DDRPHY_DQSDR1_DFTRDIDLF_SHIFT            (16U)
16935 /*! DFTRDIDLF - Drift Idle Read Cycles Factor
16936  */
16937 #define DDRPHY_DQSDR1_DFTRDIDLF(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDIDLF_SHIFT)) & DDRPHY_DQSDR1_DFTRDIDLF_MASK)
16938 #define DDRPHY_DQSDR1_DFTRDB2BF_MASK             (0xF00000U)
16939 #define DDRPHY_DQSDR1_DFTRDB2BF_SHIFT            (20U)
16940 /*! DFTRDB2BF - Drift Back-to-Back Read Cycles Factor
16941  */
16942 #define DDRPHY_DQSDR1_DFTRDB2BF(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDB2BF_SHIFT)) & DDRPHY_DQSDR1_DFTRDB2BF_MASK)
16943 #define DDRPHY_DQSDR1_DFTUPDACKC_MASK            (0x1F000000U)
16944 #define DDRPHY_DQSDR1_DFTUPDACKC_SHIFT           (24U)
16945 /*! DFTUPDACKC - Drift DFI Update ACK to DQS Drift FSM issuing IDLE Read Cycles
16946  */
16947 #define DDRPHY_DQSDR1_DFTUPDACKC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTUPDACKC_SHIFT)) & DDRPHY_DQSDR1_DFTUPDACKC_MASK)
16948 #define DDRPHY_DQSDR1_DFTUPDACKF_MASK            (0xE0000000U)
16949 #define DDRPHY_DQSDR1_DFTUPDACKF_SHIFT           (29U)
16950 /*! DFTUPDACKF - Drift DFI Update Request ACK to DQS Drift FSM issing IDLE REad Cycles Factor
16951  */
16952 #define DDRPHY_DQSDR1_DFTUPDACKF(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTUPDACKF_SHIFT)) & DDRPHY_DQSDR1_DFTUPDACKF_MASK)
16953 /*! @} */
16954 
16955 /*! @name DQSDR2 - DQS Drift Register 2 */
16956 /*! @{ */
16957 #define DDRPHY_DQSDR2_DFTMNTPRD_MASK             (0xFFFFU)
16958 #define DDRPHY_DQSDR2_DFTMNTPRD_SHIFT            (0U)
16959 /*! DFTMNTPRD - Drift Monitor Period
16960  */
16961 #define DDRPHY_DQSDR2_DFTMNTPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR2_DFTMNTPRD_SHIFT)) & DDRPHY_DQSDR2_DFTMNTPRD_MASK)
16962 #define DDRPHY_DQSDR2_DFTTHRSH_MASK              (0xFF0000U)
16963 #define DDRPHY_DQSDR2_DFTTHRSH_SHIFT             (16U)
16964 /*! DFTTHRSH - Drift Threshold
16965  */
16966 #define DDRPHY_DQSDR2_DFTTHRSH(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR2_DFTTHRSH_SHIFT)) & DDRPHY_DQSDR2_DFTTHRSH_MASK)
16967 #define DDRPHY_DQSDR2_RESERVED_31_24_MASK        (0xFF000000U)
16968 #define DDRPHY_DQSDR2_RESERVED_31_24_SHIFT       (24U)
16969 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
16970  */
16971 #define DDRPHY_DQSDR2_RESERVED_31_24(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR2_RESERVED_31_24_SHIFT)) & DDRPHY_DQSDR2_RESERVED_31_24_MASK)
16972 /*! @} */
16973 
16974 /*! @name DCUAR - DCU Address Register */
16975 /*! @{ */
16976 #define DDRPHY_DCUAR_CWADDR_W_MASK               (0xFU)
16977 #define DDRPHY_DCUAR_CWADDR_W_SHIFT              (0U)
16978 /*! CWADDR_W - Cache Word Address
16979  */
16980 #define DDRPHY_DCUAR_CWADDR_W(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CWADDR_W_SHIFT)) & DDRPHY_DCUAR_CWADDR_W_MASK)
16981 #define DDRPHY_DCUAR_CSADDR_W_MASK               (0xF0U)
16982 #define DDRPHY_DCUAR_CSADDR_W_SHIFT              (4U)
16983 /*! CSADDR_W - Cache Slice Address
16984  */
16985 #define DDRPHY_DCUAR_CSADDR_W(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CSADDR_W_SHIFT)) & DDRPHY_DCUAR_CSADDR_W_MASK)
16986 #define DDRPHY_DCUAR_CSEL_MASK                   (0x300U)
16987 #define DDRPHY_DCUAR_CSEL_SHIFT                  (8U)
16988 /*! CSEL - Cache Select
16989  */
16990 #define DDRPHY_DCUAR_CSEL(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CSEL_SHIFT)) & DDRPHY_DCUAR_CSEL_MASK)
16991 #define DDRPHY_DCUAR_INCA_MASK                   (0x400U)
16992 #define DDRPHY_DCUAR_INCA_SHIFT                  (10U)
16993 /*! INCA - Increment Address
16994  */
16995 #define DDRPHY_DCUAR_INCA(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_INCA_SHIFT)) & DDRPHY_DCUAR_INCA_MASK)
16996 #define DDRPHY_DCUAR_ATYPE_MASK                  (0x800U)
16997 #define DDRPHY_DCUAR_ATYPE_SHIFT                 (11U)
16998 /*! ATYPE - Access Type
16999  */
17000 #define DDRPHY_DCUAR_ATYPE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_ATYPE_SHIFT)) & DDRPHY_DCUAR_ATYPE_MASK)
17001 #define DDRPHY_DCUAR_CWADDR_R_MASK               (0xF000U)
17002 #define DDRPHY_DCUAR_CWADDR_R_SHIFT              (12U)
17003 /*! CWADDR_R - Cache Word Address
17004  */
17005 #define DDRPHY_DCUAR_CWADDR_R(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CWADDR_R_SHIFT)) & DDRPHY_DCUAR_CWADDR_R_MASK)
17006 #define DDRPHY_DCUAR_CSADDR_R_MASK               (0xF0000U)
17007 #define DDRPHY_DCUAR_CSADDR_R_SHIFT              (16U)
17008 /*! CSADDR_R - Cache Slice Address
17009  */
17010 #define DDRPHY_DCUAR_CSADDR_R(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CSADDR_R_SHIFT)) & DDRPHY_DCUAR_CSADDR_R_MASK)
17011 #define DDRPHY_DCUAR_RESERVED_31_20_MASK         (0xFFF00000U)
17012 #define DDRPHY_DCUAR_RESERVED_31_20_SHIFT        (20U)
17013 /*! RESERVED_31_20 - Reserved. Return zeroes on reads.
17014  */
17015 #define DDRPHY_DCUAR_RESERVED_31_20(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_RESERVED_31_20_SHIFT)) & DDRPHY_DCUAR_RESERVED_31_20_MASK)
17016 /*! @} */
17017 
17018 /*! @name DCUDR - DCU Data Register */
17019 /*! @{ */
17020 #define DDRPHY_DCUDR_CDATA_MASK                  (0xFFFFFFFFU)
17021 #define DDRPHY_DCUDR_CDATA_SHIFT                 (0U)
17022 /*! CDATA - Cache Data
17023  */
17024 #define DDRPHY_DCUDR_CDATA(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUDR_CDATA_SHIFT)) & DDRPHY_DCUDR_CDATA_MASK)
17025 /*! @} */
17026 
17027 /*! @name DCURR - DCU Run Register */
17028 /*! @{ */
17029 #define DDRPHY_DCURR_DINST_MASK                  (0xFU)
17030 #define DDRPHY_DCURR_DINST_SHIFT                 (0U)
17031 /*! DINST - DCU Instruction
17032  */
17033 #define DDRPHY_DCURR_DINST(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_DINST_SHIFT)) & DDRPHY_DCURR_DINST_MASK)
17034 #define DDRPHY_DCURR_SADDR_MASK                  (0xF0U)
17035 #define DDRPHY_DCURR_SADDR_SHIFT                 (4U)
17036 /*! SADDR - Start Address
17037  */
17038 #define DDRPHY_DCURR_SADDR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_SADDR_SHIFT)) & DDRPHY_DCURR_SADDR_MASK)
17039 #define DDRPHY_DCURR_EADDR_MASK                  (0xF00U)
17040 #define DDRPHY_DCURR_EADDR_SHIFT                 (8U)
17041 /*! EADDR - End Address
17042  */
17043 #define DDRPHY_DCURR_EADDR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_EADDR_SHIFT)) & DDRPHY_DCURR_EADDR_MASK)
17044 #define DDRPHY_DCURR_NFAIL_MASK                  (0xFF000U)
17045 #define DDRPHY_DCURR_NFAIL_SHIFT                 (12U)
17046 /*! NFAIL - Number of Failures
17047  */
17048 #define DDRPHY_DCURR_NFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_NFAIL_SHIFT)) & DDRPHY_DCURR_NFAIL_MASK)
17049 #define DDRPHY_DCURR_SONF_MASK                   (0x100000U)
17050 #define DDRPHY_DCURR_SONF_SHIFT                  (20U)
17051 /*! SONF - Stop On Nth Fail
17052  */
17053 #define DDRPHY_DCURR_SONF(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_SONF_SHIFT)) & DDRPHY_DCURR_SONF_MASK)
17054 #define DDRPHY_DCURR_SCOF_MASK                   (0x200000U)
17055 #define DDRPHY_DCURR_SCOF_SHIFT                  (21U)
17056 /*! SCOF - Stop Capture On Full
17057  */
17058 #define DDRPHY_DCURR_SCOF(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_SCOF_SHIFT)) & DDRPHY_DCURR_SCOF_MASK)
17059 #define DDRPHY_DCURR_RCEN_MASK                   (0x400000U)
17060 #define DDRPHY_DCURR_RCEN_SHIFT                  (22U)
17061 /*! RCEN - Read Capture Enable
17062  */
17063 #define DDRPHY_DCURR_RCEN(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_RCEN_SHIFT)) & DDRPHY_DCURR_RCEN_MASK)
17064 #define DDRPHY_DCURR_XCEN_MASK                   (0x800000U)
17065 #define DDRPHY_DCURR_XCEN_SHIFT                  (23U)
17066 /*! XCEN - Expected Compare Enable
17067  */
17068 #define DDRPHY_DCURR_XCEN(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_XCEN_SHIFT)) & DDRPHY_DCURR_XCEN_MASK)
17069 #define DDRPHY_DCURR_RESERVED_31_24_MASK         (0xFF000000U)
17070 #define DDRPHY_DCURR_RESERVED_31_24_SHIFT        (24U)
17071 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
17072  */
17073 #define DDRPHY_DCURR_RESERVED_31_24(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_RESERVED_31_24_SHIFT)) & DDRPHY_DCURR_RESERVED_31_24_MASK)
17074 /*! @} */
17075 
17076 /*! @name DCULR - DCU Loop Register */
17077 /*! @{ */
17078 #define DDRPHY_DCULR_LSADDR_MASK                 (0xFU)
17079 #define DDRPHY_DCULR_LSADDR_SHIFT                (0U)
17080 /*! LSADDR - Loop Start Address
17081  */
17082 #define DDRPHY_DCULR_LSADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LSADDR_SHIFT)) & DDRPHY_DCULR_LSADDR_MASK)
17083 #define DDRPHY_DCULR_LEADDR_MASK                 (0xF0U)
17084 #define DDRPHY_DCULR_LEADDR_SHIFT                (4U)
17085 /*! LEADDR - Loop End Address
17086  */
17087 #define DDRPHY_DCULR_LEADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LEADDR_SHIFT)) & DDRPHY_DCULR_LEADDR_MASK)
17088 #define DDRPHY_DCULR_LCNT_MASK                   (0xFF00U)
17089 #define DDRPHY_DCULR_LCNT_SHIFT                  (8U)
17090 /*! LCNT - Loop Count
17091  */
17092 #define DDRPHY_DCULR_LCNT(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LCNT_SHIFT)) & DDRPHY_DCULR_LCNT_MASK)
17093 #define DDRPHY_DCULR_LINF_MASK                   (0x10000U)
17094 #define DDRPHY_DCULR_LINF_SHIFT                  (16U)
17095 /*! LINF - Loop Infinite
17096  */
17097 #define DDRPHY_DCULR_LINF(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LINF_SHIFT)) & DDRPHY_DCULR_LINF_MASK)
17098 #define DDRPHY_DCULR_IDA_MASK                    (0x20000U)
17099 #define DDRPHY_DCULR_IDA_SHIFT                   (17U)
17100 /*! IDA - Increment DRAM Address
17101  */
17102 #define DDRPHY_DCULR_IDA(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_IDA_SHIFT)) & DDRPHY_DCULR_IDA_MASK)
17103 #define DDRPHY_DCULR_RESERVED_27_18_MASK         (0xFFC0000U)
17104 #define DDRPHY_DCULR_RESERVED_27_18_SHIFT        (18U)
17105 /*! RESERVED_27_18 - Reserved. Return zeroes on reads.
17106  */
17107 #define DDRPHY_DCULR_RESERVED_27_18(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_RESERVED_27_18_SHIFT)) & DDRPHY_DCULR_RESERVED_27_18_MASK)
17108 #define DDRPHY_DCULR_XLEADDR_MASK                (0xF0000000U)
17109 #define DDRPHY_DCULR_XLEADDR_SHIFT               (28U)
17110 /*! XLEADDR - Expected Data Loop End Address
17111  */
17112 #define DDRPHY_DCULR_XLEADDR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_XLEADDR_SHIFT)) & DDRPHY_DCULR_XLEADDR_MASK)
17113 /*! @} */
17114 
17115 /*! @name DCUGCR - DCU General Configuration Register */
17116 /*! @{ */
17117 #define DDRPHY_DCUGCR_RCSW_MASK                  (0xFFFFU)
17118 #define DDRPHY_DCUGCR_RCSW_SHIFT                 (0U)
17119 /*! RCSW - Read Capture Start Word
17120  */
17121 #define DDRPHY_DCUGCR_RCSW(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUGCR_RCSW_SHIFT)) & DDRPHY_DCUGCR_RCSW_MASK)
17122 #define DDRPHY_DCUGCR_RESERVED_31_16_MASK        (0xFFFF0000U)
17123 #define DDRPHY_DCUGCR_RESERVED_31_16_SHIFT       (16U)
17124 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
17125  */
17126 #define DDRPHY_DCUGCR_RESERVED_31_16(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUGCR_RESERVED_31_16_SHIFT)) & DDRPHY_DCUGCR_RESERVED_31_16_MASK)
17127 /*! @} */
17128 
17129 /*! @name DCUTPR - DCU Timing Parameters Register */
17130 /*! @{ */
17131 #define DDRPHY_DCUTPR_tDCUT0_MASK                (0xFFU)
17132 #define DDRPHY_DCUTPR_tDCUT0_SHIFT               (0U)
17133 /*! tDCUT0 - DCU Generic Timing Parameter 0
17134  */
17135 #define DDRPHY_DCUTPR_tDCUT0(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUTPR_tDCUT0_SHIFT)) & DDRPHY_DCUTPR_tDCUT0_MASK)
17136 #define DDRPHY_DCUTPR_tDCUT1_MASK                (0xFF00U)
17137 #define DDRPHY_DCUTPR_tDCUT1_SHIFT               (8U)
17138 /*! tDCUT1 - DCU Generic Timing Parameter 1
17139  */
17140 #define DDRPHY_DCUTPR_tDCUT1(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUTPR_tDCUT1_SHIFT)) & DDRPHY_DCUTPR_tDCUT1_MASK)
17141 #define DDRPHY_DCUTPR_tDCUT2_MASK                (0xFFFF0000U)
17142 #define DDRPHY_DCUTPR_tDCUT2_SHIFT               (16U)
17143 /*! tDCUT2 - DCU Generic Timing Parameter 2
17144  */
17145 #define DDRPHY_DCUTPR_tDCUT2(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUTPR_tDCUT2_SHIFT)) & DDRPHY_DCUTPR_tDCUT2_MASK)
17146 /*! @} */
17147 
17148 /*! @name DCUSR0 - DCU Status Register 0 */
17149 /*! @{ */
17150 #define DDRPHY_DCUSR0_RDONE_MASK                 (0x1U)
17151 #define DDRPHY_DCUSR0_RDONE_SHIFT                (0U)
17152 /*! RDONE - Run Done
17153  */
17154 #define DDRPHY_DCUSR0_RDONE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_RDONE_SHIFT)) & DDRPHY_DCUSR0_RDONE_MASK)
17155 #define DDRPHY_DCUSR0_CFAIL_MASK                 (0x2U)
17156 #define DDRPHY_DCUSR0_CFAIL_SHIFT                (1U)
17157 /*! CFAIL - Capture Fail
17158  */
17159 #define DDRPHY_DCUSR0_CFAIL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_CFAIL_SHIFT)) & DDRPHY_DCUSR0_CFAIL_MASK)
17160 #define DDRPHY_DCUSR0_CFULL_MASK                 (0x4U)
17161 #define DDRPHY_DCUSR0_CFULL_SHIFT                (2U)
17162 /*! CFULL - Capture Full
17163  */
17164 #define DDRPHY_DCUSR0_CFULL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_CFULL_SHIFT)) & DDRPHY_DCUSR0_CFULL_MASK)
17165 #define DDRPHY_DCUSR0_RESERVED_31_3_MASK         (0xFFFFFFF8U)
17166 #define DDRPHY_DCUSR0_RESERVED_31_3_SHIFT        (3U)
17167 /*! RESERVED_31_3 - Reserved. Return zeroes on reads.
17168  */
17169 #define DDRPHY_DCUSR0_RESERVED_31_3(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_RESERVED_31_3_SHIFT)) & DDRPHY_DCUSR0_RESERVED_31_3_MASK)
17170 /*! @} */
17171 
17172 /*! @name DCUSR1 - DCU Status Register 1 */
17173 /*! @{ */
17174 #define DDRPHY_DCUSR1_RDCNT_MASK                 (0xFFFFU)
17175 #define DDRPHY_DCUSR1_RDCNT_SHIFT                (0U)
17176 /*! RDCNT - Read Count
17177  */
17178 #define DDRPHY_DCUSR1_RDCNT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR1_RDCNT_SHIFT)) & DDRPHY_DCUSR1_RDCNT_MASK)
17179 #define DDRPHY_DCUSR1_FLCNT_MASK                 (0xFF0000U)
17180 #define DDRPHY_DCUSR1_FLCNT_SHIFT                (16U)
17181 /*! FLCNT - Fail Count
17182  */
17183 #define DDRPHY_DCUSR1_FLCNT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR1_FLCNT_SHIFT)) & DDRPHY_DCUSR1_FLCNT_MASK)
17184 #define DDRPHY_DCUSR1_LPCNT_MASK                 (0xFF000000U)
17185 #define DDRPHY_DCUSR1_LPCNT_SHIFT                (24U)
17186 /*! LPCNT - Loop Count
17187  */
17188 #define DDRPHY_DCUSR1_LPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR1_LPCNT_SHIFT)) & DDRPHY_DCUSR1_LPCNT_MASK)
17189 /*! @} */
17190 
17191 /*! @name BISTRR - BIST Run Register */
17192 /*! @{ */
17193 #define DDRPHY_BISTRR_BINST_MASK                 (0x7U)
17194 #define DDRPHY_BISTRR_BINST_SHIFT                (0U)
17195 /*! BINST - BIST Instruction
17196  */
17197 #define DDRPHY_BISTRR_BINST(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BINST_SHIFT)) & DDRPHY_BISTRR_BINST_MASK)
17198 #define DDRPHY_BISTRR_BMODE_MASK                 (0x8U)
17199 #define DDRPHY_BISTRR_BMODE_SHIFT                (3U)
17200 /*! BMODE - BIST Mode
17201  */
17202 #define DDRPHY_BISTRR_BMODE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BMODE_SHIFT)) & DDRPHY_BISTRR_BMODE_MASK)
17203 #define DDRPHY_BISTRR_BINF_MASK                  (0x10U)
17204 #define DDRPHY_BISTRR_BINF_SHIFT                 (4U)
17205 /*! BINF - BIST Infinite Run
17206  */
17207 #define DDRPHY_BISTRR_BINF(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BINF_SHIFT)) & DDRPHY_BISTRR_BINF_MASK)
17208 #define DDRPHY_BISTRR_NFAIL_MASK                 (0x1FE0U)
17209 #define DDRPHY_BISTRR_NFAIL_SHIFT                (5U)
17210 /*! NFAIL - Number of Failures
17211  */
17212 #define DDRPHY_BISTRR_NFAIL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_NFAIL_SHIFT)) & DDRPHY_BISTRR_NFAIL_MASK)
17213 #define DDRPHY_BISTRR_BSONF_MASK                 (0x2000U)
17214 #define DDRPHY_BISTRR_BSONF_SHIFT                (13U)
17215 /*! BSONF - BIST Stop On Nth Fail
17216  */
17217 #define DDRPHY_BISTRR_BSONF(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BSONF_SHIFT)) & DDRPHY_BISTRR_BSONF_MASK)
17218 #define DDRPHY_BISTRR_BDXEN_MASK                 (0x4000U)
17219 #define DDRPHY_BISTRR_BDXEN_SHIFT                (14U)
17220 /*! BDXEN - BIST DATX8 Enable
17221  */
17222 #define DDRPHY_BISTRR_BDXEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDXEN_SHIFT)) & DDRPHY_BISTRR_BDXEN_MASK)
17223 #define DDRPHY_BISTRR_BACEN_MASK                 (0x8000U)
17224 #define DDRPHY_BISTRR_BACEN_SHIFT                (15U)
17225 /*! BACEN - BIST AC Enable
17226  */
17227 #define DDRPHY_BISTRR_BACEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BACEN_SHIFT)) & DDRPHY_BISTRR_BACEN_MASK)
17228 #define DDRPHY_BISTRR_BDMEN_MASK                 (0x10000U)
17229 #define DDRPHY_BISTRR_BDMEN_SHIFT                (16U)
17230 /*! BDMEN - BIST Data Mask Enable
17231  */
17232 #define DDRPHY_BISTRR_BDMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDMEN_SHIFT)) & DDRPHY_BISTRR_BDMEN_MASK)
17233 #define DDRPHY_BISTRR_BDXDPAT_MASK               (0x60000U)
17234 #define DDRPHY_BISTRR_BDXDPAT_SHIFT              (17U)
17235 /*! BDXDPAT - BIST Data Pattern
17236  */
17237 #define DDRPHY_BISTRR_BDXDPAT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDXDPAT_SHIFT)) & DDRPHY_BISTRR_BDXDPAT_MASK)
17238 #define DDRPHY_BISTRR_BDXSEL_MASK                (0x780000U)
17239 #define DDRPHY_BISTRR_BDXSEL_SHIFT               (19U)
17240 /*! BDXSEL - BIST DATX8 Select
17241  */
17242 #define DDRPHY_BISTRR_BDXSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDXSEL_SHIFT)) & DDRPHY_BISTRR_BDXSEL_MASK)
17243 #define DDRPHY_BISTRR_BCKSEL_MASK                (0x1800000U)
17244 #define DDRPHY_BISTRR_BCKSEL_SHIFT               (23U)
17245 /*! BCKSEL - BIST CK Select
17246  */
17247 #define DDRPHY_BISTRR_BCKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BCKSEL_SHIFT)) & DDRPHY_BISTRR_BCKSEL_MASK)
17248 #define DDRPHY_BISTRR_BCCSEL_MASK                (0x2000000U)
17249 #define DDRPHY_BISTRR_BCCSEL_SHIFT               (25U)
17250 /*! BCCSEL - BIST Clock Cycle Select
17251  */
17252 #define DDRPHY_BISTRR_BCCSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BCCSEL_SHIFT)) & DDRPHY_BISTRR_BCCSEL_MASK)
17253 #define DDRPHY_BISTRR_BACDPAT_MASK               (0xC000000U)
17254 #define DDRPHY_BISTRR_BACDPAT_SHIFT              (26U)
17255 /*! BACDPAT - BIST AC Data Pattern
17256  */
17257 #define DDRPHY_BISTRR_BACDPAT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BACDPAT_SHIFT)) & DDRPHY_BISTRR_BACDPAT_MASK)
17258 #define DDRPHY_BISTRR_BSOMA_MASK                 (0x10000000U)
17259 #define DDRPHY_BISTRR_BSOMA_SHIFT                (28U)
17260 /*! BSOMA - BIST Stop on Maximum Address
17261  */
17262 #define DDRPHY_BISTRR_BSOMA(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BSOMA_SHIFT)) & DDRPHY_BISTRR_BSOMA_MASK)
17263 #define DDRPHY_BISTRR_BPRBST_MASK                (0x20000000U)
17264 #define DDRPHY_BISTRR_BPRBST_SHIFT               (29U)
17265 /*! BPRBST - BIST PRBS Type.
17266  */
17267 #define DDRPHY_BISTRR_BPRBST(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BPRBST_SHIFT)) & DDRPHY_BISTRR_BPRBST_MASK)
17268 #define DDRPHY_BISTRR_RESERVED_31_30_MASK        (0xC0000000U)
17269 #define DDRPHY_BISTRR_RESERVED_31_30_SHIFT       (30U)
17270 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
17271  */
17272 #define DDRPHY_BISTRR_RESERVED_31_30(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_RESERVED_31_30_SHIFT)) & DDRPHY_BISTRR_RESERVED_31_30_MASK)
17273 /*! @} */
17274 
17275 /*! @name BISTWCR - BIST Word Count Register */
17276 /*! @{ */
17277 #define DDRPHY_BISTWCR_BDXWCNT_MASK              (0xFFFFU)
17278 #define DDRPHY_BISTWCR_BDXWCNT_SHIFT             (0U)
17279 /*! BDXWCNT - BIST DX Word Count
17280  */
17281 #define DDRPHY_BISTWCR_BDXWCNT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCR_BDXWCNT_SHIFT)) & DDRPHY_BISTWCR_BDXWCNT_MASK)
17282 #define DDRPHY_BISTWCR_BACWCNT_MASK              (0xFFFF0000U)
17283 #define DDRPHY_BISTWCR_BACWCNT_SHIFT             (16U)
17284 /*! BACWCNT - BIST AC Word Count
17285  */
17286 #define DDRPHY_BISTWCR_BACWCNT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCR_BACWCNT_SHIFT)) & DDRPHY_BISTWCR_BACWCNT_MASK)
17287 /*! @} */
17288 
17289 /*! @name BISTMSKR0 - BIST Mask Register 0 */
17290 /*! @{ */
17291 #define DDRPHY_BISTMSKR0_AMSK_MASK               (0x3FFFFU)
17292 #define DDRPHY_BISTMSKR0_AMSK_SHIFT              (0U)
17293 /*! AMSK - Mask bit for each of the up to 16 address bits.
17294  */
17295 #define DDRPHY_BISTMSKR0_AMSK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_AMSK_SHIFT)) & DDRPHY_BISTMSKR0_AMSK_MASK)
17296 #define DDRPHY_BISTMSKR0_RESERVED_18_MASK        (0x40000U)
17297 #define DDRPHY_BISTMSKR0_RESERVED_18_SHIFT       (18U)
17298 /*! RESERVED_18 - Reserved. Return zeros on reads.
17299  */
17300 #define DDRPHY_BISTMSKR0_RESERVED_18(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_RESERVED_18_SHIFT)) & DDRPHY_BISTMSKR0_RESERVED_18_MASK)
17301 #define DDRPHY_BISTMSKR0_ACTMSK_MASK             (0x80000U)
17302 #define DDRPHY_BISTMSKR0_ACTMSK_SHIFT            (19U)
17303 /*! ACTMSK - Mask bit for the RAS.
17304  */
17305 #define DDRPHY_BISTMSKR0_ACTMSK(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_ACTMSK_SHIFT)) & DDRPHY_BISTMSKR0_ACTMSK_MASK)
17306 #define DDRPHY_BISTMSKR0_CSMSK_MASK              (0x100000U)
17307 #define DDRPHY_BISTMSKR0_CSMSK_SHIFT             (20U)
17308 /*! CSMSK - Mask bit for each of the up to 12 CS_N bits.
17309  */
17310 #define DDRPHY_BISTMSKR0_CSMSK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_CSMSK_SHIFT)) & DDRPHY_BISTMSKR0_CSMSK_MASK)
17311 #define DDRPHY_BISTMSKR0_CSMSK_RSVD_MASK         (0xFFE00000U)
17312 #define DDRPHY_BISTMSKR0_CSMSK_RSVD_SHIFT        (21U)
17313 /*! CSMSK_RSVD - Reserved. Return zeros on reads.
17314  */
17315 #define DDRPHY_BISTMSKR0_CSMSK_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_CSMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR0_CSMSK_RSVD_MASK)
17316 /*! @} */
17317 
17318 /*! @name BISTMSKR1 - BIST Mask Register 1 */
17319 /*! @{ */
17320 #define DDRPHY_BISTMSKR1_RESERVED_3_0_MASK       (0xFU)
17321 #define DDRPHY_BISTMSKR1_RESERVED_3_0_SHIFT      (0U)
17322 /*! RESERVED_3_0 - Reserved. Return zeros on reads.
17323  */
17324 #define DDRPHY_BISTMSKR1_RESERVED_3_0(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_RESERVED_3_0_SHIFT)) & DDRPHY_BISTMSKR1_RESERVED_3_0_MASK)
17325 #define DDRPHY_BISTMSKR1_BAMSK_MASK              (0xF0U)
17326 #define DDRPHY_BISTMSKR1_BAMSK_SHIFT             (4U)
17327 /*! BAMSK - Mask bit for each of the up to 4 bank address bits.
17328  */
17329 #define DDRPHY_BISTMSKR1_BAMSK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_BAMSK_SHIFT)) & DDRPHY_BISTMSKR1_BAMSK_MASK)
17330 #define DDRPHY_BISTMSKR1_CKEMSK_MASK             (0x100U)
17331 #define DDRPHY_BISTMSKR1_CKEMSK_SHIFT            (8U)
17332 /*! CKEMSK - Mask bit for each of the up to 8 CKE bits.
17333  */
17334 #define DDRPHY_BISTMSKR1_CKEMSK(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CKEMSK_SHIFT)) & DDRPHY_BISTMSKR1_CKEMSK_MASK)
17335 #define DDRPHY_BISTMSKR1_CKEMSK_RSVD_MASK        (0xFE00U)
17336 #define DDRPHY_BISTMSKR1_CKEMSK_RSVD_SHIFT       (9U)
17337 /*! CKEMSK_RSVD - Reserved. Return zeros on reads.
17338  */
17339 #define DDRPHY_BISTMSKR1_CKEMSK_RSVD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CKEMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR1_CKEMSK_RSVD_MASK)
17340 #define DDRPHY_BISTMSKR1_ODTMSK_MASK             (0x10000U)
17341 #define DDRPHY_BISTMSKR1_ODTMSK_SHIFT            (16U)
17342 /*! ODTMSK - Mask bit for each of the up to 8 ODT bits.
17343  */
17344 #define DDRPHY_BISTMSKR1_ODTMSK(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_ODTMSK_SHIFT)) & DDRPHY_BISTMSKR1_ODTMSK_MASK)
17345 #define DDRPHY_BISTMSKR1_ODTMSK_RSVD_MASK        (0xFE0000U)
17346 #define DDRPHY_BISTMSKR1_ODTMSK_RSVD_SHIFT       (17U)
17347 /*! ODTMSK_RSVD - Reserved. Return zeros on reads.
17348  */
17349 #define DDRPHY_BISTMSKR1_ODTMSK_RSVD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_ODTMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR1_ODTMSK_RSVD_MASK)
17350 #define DDRPHY_BISTMSKR1_CIDMSK_MASK             (0x1000000U)
17351 #define DDRPHY_BISTMSKR1_CIDMSK_SHIFT            (24U)
17352 /*! CIDMSK - Mask bits for each of the up to 3 Chip IP bits.
17353  */
17354 #define DDRPHY_BISTMSKR1_CIDMSK(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CIDMSK_SHIFT)) & DDRPHY_BISTMSKR1_CIDMSK_MASK)
17355 #define DDRPHY_BISTMSKR1_CIDMSK_RSVD_MASK        (0x6000000U)
17356 #define DDRPHY_BISTMSKR1_CIDMSK_RSVD_SHIFT       (25U)
17357 /*! CIDMSK_RSVD - Reserved. Return zeros on reads.
17358  */
17359 #define DDRPHY_BISTMSKR1_CIDMSK_RSVD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CIDMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR1_CIDMSK_RSVD_MASK)
17360 #define DDRPHY_BISTMSKR1_PARINMSK_MASK           (0x8000000U)
17361 #define DDRPHY_BISTMSKR1_PARINMSK_SHIFT          (27U)
17362 /*! PARINMSK - Mask bit for the PAR_IN.
17363  */
17364 #define DDRPHY_BISTMSKR1_PARINMSK(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_PARINMSK_SHIFT)) & DDRPHY_BISTMSKR1_PARINMSK_MASK)
17365 #define DDRPHY_BISTMSKR1_DMMSK_MASK              (0xF0000000U)
17366 #define DDRPHY_BISTMSKR1_DMMSK_SHIFT             (28U)
17367 /*! DMMSK - Mask bit for the data mask (DM) bit.
17368  */
17369 #define DDRPHY_BISTMSKR1_DMMSK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_DMMSK_SHIFT)) & DDRPHY_BISTMSKR1_DMMSK_MASK)
17370 /*! @} */
17371 
17372 /*! @name BISTMSKR2 - BIST Mask Register 2 */
17373 /*! @{ */
17374 #define DDRPHY_BISTMSKR2_DQMSK_MASK              (0xFFFFFFFFU)
17375 #define DDRPHY_BISTMSKR2_DQMSK_SHIFT             (0U)
17376 /*! DQMSK - Mask bit for each of the 8 data (DQ) bits
17377  */
17378 #define DDRPHY_BISTMSKR2_DQMSK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR2_DQMSK_SHIFT)) & DDRPHY_BISTMSKR2_DQMSK_MASK)
17379 /*! @} */
17380 
17381 /*! @name BISTLSR - BIST LFSR Seed Register */
17382 /*! @{ */
17383 #define DDRPHY_BISTLSR_SEED_MASK                 (0xFFFFFFFFU)
17384 #define DDRPHY_BISTLSR_SEED_SHIFT                (0U)
17385 /*! SEED - LFSR seed for pseudo-random BIST patterns
17386  */
17387 #define DDRPHY_BISTLSR_SEED(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTLSR_SEED_SHIFT)) & DDRPHY_BISTLSR_SEED_MASK)
17388 /*! @} */
17389 
17390 /*! @name BISTAR0 - BIST Address Register 0 */
17391 /*! @{ */
17392 #define DDRPHY_BISTAR0_BCOL_MASK                 (0xFFFU)
17393 #define DDRPHY_BISTAR0_BCOL_SHIFT                (0U)
17394 /*! BCOL - BIST Column Address
17395  */
17396 #define DDRPHY_BISTAR0_BCOL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR0_BCOL_SHIFT)) & DDRPHY_BISTAR0_BCOL_MASK)
17397 #define DDRPHY_BISTAR0_RESERVED_27_12_MASK       (0xFFFF000U)
17398 #define DDRPHY_BISTAR0_RESERVED_27_12_SHIFT      (12U)
17399 /*! RESERVED_27_12 - Reserved. Return zeroes on reads.
17400  */
17401 #define DDRPHY_BISTAR0_RESERVED_27_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR0_RESERVED_27_12_SHIFT)) & DDRPHY_BISTAR0_RESERVED_27_12_MASK)
17402 #define DDRPHY_BISTAR0_BBANK_MASK                (0xF0000000U)
17403 #define DDRPHY_BISTAR0_BBANK_SHIFT               (28U)
17404 /*! BBANK - BIST Bank Address
17405  */
17406 #define DDRPHY_BISTAR0_BBANK(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR0_BBANK_SHIFT)) & DDRPHY_BISTAR0_BBANK_MASK)
17407 /*! @} */
17408 
17409 /*! @name BISTAR1 - BIST Address Register 1 */
17410 /*! @{ */
17411 #define DDRPHY_BISTAR1_BRANK_MASK                (0xFU)
17412 #define DDRPHY_BISTAR1_BRANK_SHIFT               (0U)
17413 /*! BRANK - BIST Rank
17414  */
17415 #define DDRPHY_BISTAR1_BRANK(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_BRANK_SHIFT)) & DDRPHY_BISTAR1_BRANK_MASK)
17416 #define DDRPHY_BISTAR1_BAINC_MASK                (0xFFF0U)
17417 #define DDRPHY_BISTAR1_BAINC_SHIFT               (4U)
17418 /*! BAINC - BIST Address Increment
17419  */
17420 #define DDRPHY_BISTAR1_BAINC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_BAINC_SHIFT)) & DDRPHY_BISTAR1_BAINC_MASK)
17421 #define DDRPHY_BISTAR1_BMRANK_MASK               (0xF0000U)
17422 #define DDRPHY_BISTAR1_BMRANK_SHIFT              (16U)
17423 /*! BMRANK - BIST Maximum Rank
17424  */
17425 #define DDRPHY_BISTAR1_BMRANK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_BMRANK_SHIFT)) & DDRPHY_BISTAR1_BMRANK_MASK)
17426 #define DDRPHY_BISTAR1_RESERVED_31_20_MASK       (0xFFF00000U)
17427 #define DDRPHY_BISTAR1_RESERVED_31_20_SHIFT      (20U)
17428 /*! RESERVED_31_20 - Reserved. Return zeroes on reads.
17429  */
17430 #define DDRPHY_BISTAR1_RESERVED_31_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_RESERVED_31_20_SHIFT)) & DDRPHY_BISTAR1_RESERVED_31_20_MASK)
17431 /*! @} */
17432 
17433 /*! @name BISTAR2 - BIST Address Register 2 */
17434 /*! @{ */
17435 #define DDRPHY_BISTAR2_BMCOL_MASK                (0xFFFU)
17436 #define DDRPHY_BISTAR2_BMCOL_SHIFT               (0U)
17437 /*! BMCOL - BIST Maximum Column Address
17438  */
17439 #define DDRPHY_BISTAR2_BMCOL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR2_BMCOL_SHIFT)) & DDRPHY_BISTAR2_BMCOL_MASK)
17440 #define DDRPHY_BISTAR2_RESERVED_27_12_MASK       (0xFFFF000U)
17441 #define DDRPHY_BISTAR2_RESERVED_27_12_SHIFT      (12U)
17442 /*! RESERVED_27_12 - Reserved. Return zeroes on reads.
17443  */
17444 #define DDRPHY_BISTAR2_RESERVED_27_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR2_RESERVED_27_12_SHIFT)) & DDRPHY_BISTAR2_RESERVED_27_12_MASK)
17445 #define DDRPHY_BISTAR2_BMBANK_MASK               (0xF0000000U)
17446 #define DDRPHY_BISTAR2_BMBANK_SHIFT              (28U)
17447 /*! BMBANK - BIST Maximum Bank Address
17448  */
17449 #define DDRPHY_BISTAR2_BMBANK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR2_BMBANK_SHIFT)) & DDRPHY_BISTAR2_BMBANK_MASK)
17450 /*! @} */
17451 
17452 /*! @name BISTAR3 - BIST Address Register 3 */
17453 /*! @{ */
17454 #define DDRPHY_BISTAR3_BROW_MASK                 (0x3FFFFU)
17455 #define DDRPHY_BISTAR3_BROW_SHIFT                (0U)
17456 /*! BROW - BIST Row Address
17457  */
17458 #define DDRPHY_BISTAR3_BROW(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR3_BROW_SHIFT)) & DDRPHY_BISTAR3_BROW_MASK)
17459 #define DDRPHY_BISTAR3_RESERVED_31_18_MASK       (0xFFFC0000U)
17460 #define DDRPHY_BISTAR3_RESERVED_31_18_SHIFT      (18U)
17461 /*! RESERVED_31_18 - Reserved. Return zeroes on reads.
17462  */
17463 #define DDRPHY_BISTAR3_RESERVED_31_18(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR3_RESERVED_31_18_SHIFT)) & DDRPHY_BISTAR3_RESERVED_31_18_MASK)
17464 /*! @} */
17465 
17466 /*! @name BISTAR4 - BIST Address Register 4 */
17467 /*! @{ */
17468 #define DDRPHY_BISTAR4_BMROW_MASK                (0x3FFFFU)
17469 #define DDRPHY_BISTAR4_BMROW_SHIFT               (0U)
17470 /*! BMROW - BIST Maximum Row Address
17471  */
17472 #define DDRPHY_BISTAR4_BMROW(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR4_BMROW_SHIFT)) & DDRPHY_BISTAR4_BMROW_MASK)
17473 #define DDRPHY_BISTAR4_RESERVED_31_18_MASK       (0xFFFC0000U)
17474 #define DDRPHY_BISTAR4_RESERVED_31_18_SHIFT      (18U)
17475 /*! RESERVED_31_18 - Reserved. Return zeroes on reads.
17476  */
17477 #define DDRPHY_BISTAR4_RESERVED_31_18(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR4_RESERVED_31_18_SHIFT)) & DDRPHY_BISTAR4_RESERVED_31_18_MASK)
17478 /*! @} */
17479 
17480 /*! @name BISTUDPR - BIST User Data Pattern Register */
17481 /*! @{ */
17482 #define DDRPHY_BISTUDPR_BUDP0_MASK               (0xFFFFU)
17483 #define DDRPHY_BISTUDPR_BUDP0_SHIFT              (0U)
17484 /*! BUDP0 - BIST User Data Pattern 0
17485  */
17486 #define DDRPHY_BISTUDPR_BUDP0(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTUDPR_BUDP0_SHIFT)) & DDRPHY_BISTUDPR_BUDP0_MASK)
17487 #define DDRPHY_BISTUDPR_BUDP1_MASK               (0xFFFF0000U)
17488 #define DDRPHY_BISTUDPR_BUDP1_SHIFT              (16U)
17489 /*! BUDP1 - BIST User Data Pattern 1
17490  */
17491 #define DDRPHY_BISTUDPR_BUDP1(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTUDPR_BUDP1_SHIFT)) & DDRPHY_BISTUDPR_BUDP1_MASK)
17492 /*! @} */
17493 
17494 /*! @name BISTGSR - BIST General Status Register */
17495 /*! @{ */
17496 #define DDRPHY_BISTGSR_BDONE_MASK                (0x1U)
17497 #define DDRPHY_BISTGSR_BDONE_SHIFT               (0U)
17498 /*! BDONE - BIST Done
17499  */
17500 #define DDRPHY_BISTGSR_BDONE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_BDONE_SHIFT)) & DDRPHY_BISTGSR_BDONE_MASK)
17501 #define DDRPHY_BISTGSR_BACERR_MASK               (0x2U)
17502 #define DDRPHY_BISTGSR_BACERR_SHIFT              (1U)
17503 /*! BACERR - BIST Address/Command Error
17504  */
17505 #define DDRPHY_BISTGSR_BACERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_BACERR_SHIFT)) & DDRPHY_BISTGSR_BACERR_MASK)
17506 #define DDRPHY_BISTGSR_BDXERR_MASK               (0x7FCU)
17507 #define DDRPHY_BISTGSR_BDXERR_SHIFT              (2U)
17508 /*! BDXERR - BIST Data Error
17509  */
17510 #define DDRPHY_BISTGSR_BDXERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_BDXERR_SHIFT)) & DDRPHY_BISTGSR_BDXERR_MASK)
17511 #define DDRPHY_BISTGSR_RESERVED_11_MASK          (0x800U)
17512 #define DDRPHY_BISTGSR_RESERVED_11_SHIFT         (11U)
17513 /*! RESERVED_11 - Reserved. Return zeros on reads.
17514  */
17515 #define DDRPHY_BISTGSR_RESERVED_11(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RESERVED_11_SHIFT)) & DDRPHY_BISTGSR_RESERVED_11_MASK)
17516 #define DDRPHY_BISTGSR_RESERVED_19_12_MASK       (0xFF000U)
17517 #define DDRPHY_BISTGSR_RESERVED_19_12_SHIFT      (12U)
17518 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
17519  */
17520 #define DDRPHY_BISTGSR_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RESERVED_19_12_SHIFT)) & DDRPHY_BISTGSR_RESERVED_19_12_MASK)
17521 #define DDRPHY_BISTGSR_DMBER_MASK                (0xFF00000U)
17522 #define DDRPHY_BISTGSR_DMBER_SHIFT               (20U)
17523 /*! DMBER - DM Bit Error
17524  */
17525 #define DDRPHY_BISTGSR_DMBER(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_DMBER_SHIFT)) & DDRPHY_BISTGSR_DMBER_MASK)
17526 #define DDRPHY_BISTGSR_RASBER_MASK               (0x30000000U)
17527 #define DDRPHY_BISTGSR_RASBER_SHIFT              (28U)
17528 /*! RASBER - RAS_n/ACT_n Bit Error
17529  */
17530 #define DDRPHY_BISTGSR_RASBER(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RASBER_SHIFT)) & DDRPHY_BISTGSR_RASBER_MASK)
17531 #define DDRPHY_BISTGSR_RESERVED_31_30_MASK       (0xC0000000U)
17532 #define DDRPHY_BISTGSR_RESERVED_31_30_SHIFT      (30U)
17533 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
17534  */
17535 #define DDRPHY_BISTGSR_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RESERVED_31_30_SHIFT)) & DDRPHY_BISTGSR_RESERVED_31_30_MASK)
17536 /*! @} */
17537 
17538 /*! @name BISTWER0 - BIST Word Error Register 0 */
17539 /*! @{ */
17540 #define DDRPHY_BISTWER0_ACWER_MASK               (0x3FFFFU)
17541 #define DDRPHY_BISTWER0_ACWER_SHIFT              (0U)
17542 /*! ACWER - Address/Command Word Error
17543  */
17544 #define DDRPHY_BISTWER0_ACWER(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER0_ACWER_SHIFT)) & DDRPHY_BISTWER0_ACWER_MASK)
17545 #define DDRPHY_BISTWER0_RESERVED_31_18_MASK      (0xFFFC0000U)
17546 #define DDRPHY_BISTWER0_RESERVED_31_18_SHIFT     (18U)
17547 /*! RESERVED_31_18 - Reserved. Return zeroes on reads.
17548  */
17549 #define DDRPHY_BISTWER0_RESERVED_31_18(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER0_RESERVED_31_18_SHIFT)) & DDRPHY_BISTWER0_RESERVED_31_18_MASK)
17550 /*! @} */
17551 
17552 /*! @name BISTWER1 - BIST Word Error Register 1 */
17553 /*! @{ */
17554 #define DDRPHY_BISTWER1_DXWER_MASK               (0xFFFFU)
17555 #define DDRPHY_BISTWER1_DXWER_SHIFT              (0U)
17556 /*! DXWER - Byte Word Error
17557  */
17558 #define DDRPHY_BISTWER1_DXWER(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER1_DXWER_SHIFT)) & DDRPHY_BISTWER1_DXWER_MASK)
17559 #define DDRPHY_BISTWER1_RESERVED_31_16_MASK      (0xFFFF0000U)
17560 #define DDRPHY_BISTWER1_RESERVED_31_16_SHIFT     (16U)
17561 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
17562  */
17563 #define DDRPHY_BISTWER1_RESERVED_31_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER1_RESERVED_31_16_SHIFT)) & DDRPHY_BISTWER1_RESERVED_31_16_MASK)
17564 /*! @} */
17565 
17566 /*! @name BISTBER0 - BIST Bit Error Register 0 */
17567 /*! @{ */
17568 #define DDRPHY_BISTBER0_ABER_MASK                (0xFFFFFFFFU)
17569 #define DDRPHY_BISTBER0_ABER_SHIFT               (0U)
17570 /*! ABER - Address Bit Error
17571  */
17572 #define DDRPHY_BISTBER0_ABER(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER0_ABER_SHIFT)) & DDRPHY_BISTBER0_ABER_MASK)
17573 /*! @} */
17574 
17575 /*! @name BISTBER1 - BIST Bit Error Register 1 */
17576 /*! @{ */
17577 #define DDRPHY_BISTBER1_BABER_MASK               (0xFFU)
17578 #define DDRPHY_BISTBER1_BABER_SHIFT              (0U)
17579 /*! BABER - Bank Address Bit Error
17580  */
17581 #define DDRPHY_BISTBER1_BABER(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER1_BABER_SHIFT)) & DDRPHY_BISTBER1_BABER_MASK)
17582 #define DDRPHY_BISTBER1_CSBER_MASK               (0x300U)
17583 #define DDRPHY_BISTBER1_CSBER_SHIFT              (8U)
17584 /*! CSBER - CS_N Bit Error.
17585  */
17586 #define DDRPHY_BISTBER1_CSBER(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER1_CSBER_SHIFT)) & DDRPHY_BISTBER1_CSBER_MASK)
17587 #define DDRPHY_BISTBER1_CSBER_RSVD_MASK          (0xFFFFFC00U)
17588 #define DDRPHY_BISTBER1_CSBER_RSVD_SHIFT         (10U)
17589 /*! CSBER_RSVD - Reserved. Return zeros on reads.
17590  */
17591 #define DDRPHY_BISTBER1_CSBER_RSVD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER1_CSBER_RSVD_SHIFT)) & DDRPHY_BISTBER1_CSBER_RSVD_MASK)
17592 /*! @} */
17593 
17594 /*! @name BISTBER2 - BIST Bit Error Register 2 */
17595 /*! @{ */
17596 #define DDRPHY_BISTBER2_DQBER0_MASK              (0xFFFFFFFFU)
17597 #define DDRPHY_BISTBER2_DQBER0_SHIFT             (0U)
17598 /*! DQBER0 - Data Bit Error
17599  */
17600 #define DDRPHY_BISTBER2_DQBER0(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER2_DQBER0_SHIFT)) & DDRPHY_BISTBER2_DQBER0_MASK)
17601 /*! @} */
17602 
17603 /*! @name BISTBER3 - BIST Bit Error Register 3 */
17604 /*! @{ */
17605 #define DDRPHY_BISTBER3_DQBER1_MASK              (0xFFFFFFFFU)
17606 #define DDRPHY_BISTBER3_DQBER1_SHIFT             (0U)
17607 /*! DQBER1 - Data Bit Error
17608  */
17609 #define DDRPHY_BISTBER3_DQBER1(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER3_DQBER1_SHIFT)) & DDRPHY_BISTBER3_DQBER1_MASK)
17610 /*! @} */
17611 
17612 /*! @name BISTBER4 - BIST Bit Error Register 4 */
17613 /*! @{ */
17614 #define DDRPHY_BISTBER4_ABER_MASK                (0xFU)
17615 #define DDRPHY_BISTBER4_ABER_SHIFT               (0U)
17616 /*! ABER - Address Bit Error
17617  */
17618 #define DDRPHY_BISTBER4_ABER(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_ABER_SHIFT)) & DDRPHY_BISTBER4_ABER_MASK)
17619 #define DDRPHY_BISTBER4_RESERVED_7_4_MASK        (0xF0U)
17620 #define DDRPHY_BISTBER4_RESERVED_7_4_SHIFT       (4U)
17621 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
17622  */
17623 #define DDRPHY_BISTBER4_RESERVED_7_4(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_RESERVED_7_4_SHIFT)) & DDRPHY_BISTBER4_RESERVED_7_4_MASK)
17624 #define DDRPHY_BISTBER4_CIDBER_MASK              (0x300U)
17625 #define DDRPHY_BISTBER4_CIDBER_SHIFT             (8U)
17626 /*! CIDBER - Chip ID Bit Error.
17627  */
17628 #define DDRPHY_BISTBER4_CIDBER(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_CIDBER_SHIFT)) & DDRPHY_BISTBER4_CIDBER_MASK)
17629 #define DDRPHY_BISTBER4_CIDBER_RSVD_MASK         (0x3C00U)
17630 #define DDRPHY_BISTBER4_CIDBER_RSVD_SHIFT        (10U)
17631 /*! CIDBER_RSVD - Reserved. Return zeros on reads.
17632  */
17633 #define DDRPHY_BISTBER4_CIDBER_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_CIDBER_RSVD_SHIFT)) & DDRPHY_BISTBER4_CIDBER_RSVD_MASK)
17634 #define DDRPHY_BISTBER4_RESERVED_31_14_MASK      (0xFFFFC000U)
17635 #define DDRPHY_BISTBER4_RESERVED_31_14_SHIFT     (14U)
17636 /*! RESERVED_31_14 - Reserved. Return zeroes on reads.
17637  */
17638 #define DDRPHY_BISTBER4_RESERVED_31_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_RESERVED_31_14_SHIFT)) & DDRPHY_BISTBER4_RESERVED_31_14_MASK)
17639 /*! @} */
17640 
17641 /*! @name BISTWCSR - BIST Word Count Status Register */
17642 /*! @{ */
17643 #define DDRPHY_BISTWCSR_ACWCNT_MASK              (0xFFFFU)
17644 #define DDRPHY_BISTWCSR_ACWCNT_SHIFT             (0U)
17645 /*! ACWCNT - Address/Command Word Count
17646  */
17647 #define DDRPHY_BISTWCSR_ACWCNT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCSR_ACWCNT_SHIFT)) & DDRPHY_BISTWCSR_ACWCNT_MASK)
17648 #define DDRPHY_BISTWCSR_DXWCNT_MASK              (0xFFFF0000U)
17649 #define DDRPHY_BISTWCSR_DXWCNT_SHIFT             (16U)
17650 /*! DXWCNT - Byte Word Count
17651  */
17652 #define DDRPHY_BISTWCSR_DXWCNT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCSR_DXWCNT_SHIFT)) & DDRPHY_BISTWCSR_DXWCNT_MASK)
17653 /*! @} */
17654 
17655 /*! @name BISTFWR0 - BIST Fail Word Register 0 */
17656 /*! @{ */
17657 #define DDRPHY_BISTFWR0_AWEBS_MASK               (0x3FFFFU)
17658 #define DDRPHY_BISTFWR0_AWEBS_SHIFT              (0U)
17659 /*! AWEBS - Bit status during a word error for each of the up to 16 address bits
17660  */
17661 #define DDRPHY_BISTFWR0_AWEBS(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_AWEBS_SHIFT)) & DDRPHY_BISTFWR0_AWEBS_MASK)
17662 #define DDRPHY_BISTFWR0_ACTWEBS_MASK             (0x40000U)
17663 #define DDRPHY_BISTFWR0_ACTWEBS_SHIFT            (18U)
17664 /*! ACTWEBS - Bit status during a word error for the RAS.
17665  */
17666 #define DDRPHY_BISTFWR0_ACTWEBS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_ACTWEBS_SHIFT)) & DDRPHY_BISTFWR0_ACTWEBS_MASK)
17667 #define DDRPHY_BISTFWR0_RESERVED_19_MASK         (0x80000U)
17668 #define DDRPHY_BISTFWR0_RESERVED_19_SHIFT        (19U)
17669 /*! RESERVED_19 - Reserved. Return zeroes on reads.
17670  */
17671 #define DDRPHY_BISTFWR0_RESERVED_19(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_RESERVED_19_SHIFT)) & DDRPHY_BISTFWR0_RESERVED_19_MASK)
17672 #define DDRPHY_BISTFWR0_CSWEBS_MASK              (0x100000U)
17673 #define DDRPHY_BISTFWR0_CSWEBS_SHIFT             (20U)
17674 /*! CSWEBS - Bit status during a word error for each of the up to 12 CS# bits.
17675  */
17676 #define DDRPHY_BISTFWR0_CSWEBS(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_CSWEBS_SHIFT)) & DDRPHY_BISTFWR0_CSWEBS_MASK)
17677 #define DDRPHY_BISTFWR0_CSWEBS_RSVD_MASK         (0xFFE00000U)
17678 #define DDRPHY_BISTFWR0_CSWEBS_RSVD_SHIFT        (21U)
17679 /*! CSWEBS_RSVD - Reserved. Return zeros on reads.
17680  */
17681 #define DDRPHY_BISTFWR0_CSWEBS_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_CSWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR0_CSWEBS_RSVD_MASK)
17682 /*! @} */
17683 
17684 /*! @name BISTFWR1 - BIST Fail Word Register 1 */
17685 /*! @{ */
17686 #define DDRPHY_BISTFWR1_CKEWEBS_MASK             (0x1U)
17687 #define DDRPHY_BISTFWR1_CKEWEBS_SHIFT            (0U)
17688 /*! CKEWEBS - Bit status during a word error for each of the up to 8 CKE bits.
17689  */
17690 #define DDRPHY_BISTFWR1_CKEWEBS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CKEWEBS_SHIFT)) & DDRPHY_BISTFWR1_CKEWEBS_MASK)
17691 #define DDRPHY_BISTFWR1_CKEWEBS_RSVD_MASK        (0xFEU)
17692 #define DDRPHY_BISTFWR1_CKEWEBS_RSVD_SHIFT       (1U)
17693 /*! CKEWEBS_RSVD - Reserved. Return zeros on reads.
17694  */
17695 #define DDRPHY_BISTFWR1_CKEWEBS_RSVD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CKEWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR1_CKEWEBS_RSVD_MASK)
17696 #define DDRPHY_BISTFWR1_ODTWEBS_MASK             (0x100U)
17697 #define DDRPHY_BISTFWR1_ODTWEBS_SHIFT            (8U)
17698 /*! ODTWEBS - Bit status during a word error for each of the up to 8 ODT bits.
17699  */
17700 #define DDRPHY_BISTFWR1_ODTWEBS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_ODTWEBS_SHIFT)) & DDRPHY_BISTFWR1_ODTWEBS_MASK)
17701 #define DDRPHY_BISTFWR1_ODTWEBS_RSVD_MASK        (0xFE00U)
17702 #define DDRPHY_BISTFWR1_ODTWEBS_RSVD_SHIFT       (9U)
17703 /*! ODTWEBS_RSVD - Reserved. Return zeros on reads.
17704  */
17705 #define DDRPHY_BISTFWR1_ODTWEBS_RSVD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_ODTWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR1_ODTWEBS_RSVD_MASK)
17706 #define DDRPHY_BISTFWR1_BAWEBS_MASK              (0xF0000U)
17707 #define DDRPHY_BISTFWR1_BAWEBS_SHIFT             (16U)
17708 /*! BAWEBS - Bit status during a word error for each of the bank address bits
17709  */
17710 #define DDRPHY_BISTFWR1_BAWEBS(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_BAWEBS_SHIFT)) & DDRPHY_BISTFWR1_BAWEBS_MASK)
17711 #define DDRPHY_BISTFWR1_CIDWEBS_MASK             (0x100000U)
17712 #define DDRPHY_BISTFWR1_CIDWEBS_SHIFT            (20U)
17713 /*! CIDWEBS - Bit status during a word error for each of the up to 3 chip ID bits.
17714  */
17715 #define DDRPHY_BISTFWR1_CIDWEBS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CIDWEBS_SHIFT)) & DDRPHY_BISTFWR1_CIDWEBS_MASK)
17716 #define DDRPHY_BISTFWR1_CIDWEBS_RSVD_MASK        (0x600000U)
17717 #define DDRPHY_BISTFWR1_CIDWEBS_RSVD_SHIFT       (21U)
17718 /*! CIDWEBS_RSVD - Reserved. Return zeros on reads.
17719  */
17720 #define DDRPHY_BISTFWR1_CIDWEBS_RSVD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CIDWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR1_CIDWEBS_RSVD_MASK)
17721 #define DDRPHY_BISTFWR1_RESERVED_23_22_MASK      (0x800000U)
17722 #define DDRPHY_BISTFWR1_RESERVED_23_22_SHIFT     (23U)
17723 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
17724  */
17725 #define DDRPHY_BISTFWR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_RESERVED_23_22_SHIFT)) & DDRPHY_BISTFWR1_RESERVED_23_22_MASK)
17726 #define DDRPHY_BISTFWR1_RESERVED_27_24_MASK      (0xF000000U)
17727 #define DDRPHY_BISTFWR1_RESERVED_27_24_SHIFT     (24U)
17728 /*! RESERVED_27_24 - Reserved. Return zeroes on reads.
17729  */
17730 #define DDRPHY_BISTFWR1_RESERVED_27_24(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_RESERVED_27_24_SHIFT)) & DDRPHY_BISTFWR1_RESERVED_27_24_MASK)
17731 #define DDRPHY_BISTFWR1_DMWEBS_MASK              (0xF0000000U)
17732 #define DDRPHY_BISTFWR1_DMWEBS_SHIFT             (28U)
17733 /*! DMWEBS - Bit status during a word error for the data mask (DM) bit
17734  */
17735 #define DDRPHY_BISTFWR1_DMWEBS(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_DMWEBS_SHIFT)) & DDRPHY_BISTFWR1_DMWEBS_MASK)
17736 /*! @} */
17737 
17738 /*! @name BISTFWR2 - BIST Fail Word Register 2 */
17739 /*! @{ */
17740 #define DDRPHY_BISTFWR2_DQWEBS_MASK              (0xFFFFFFFFU)
17741 #define DDRPHY_BISTFWR2_DQWEBS_SHIFT             (0U)
17742 /*! DQWEBS - Bit status during a word error for each of the 8 data (DQ) bits
17743  */
17744 #define DDRPHY_BISTFWR2_DQWEBS(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR2_DQWEBS_SHIFT)) & DDRPHY_BISTFWR2_DQWEBS_MASK)
17745 /*! @} */
17746 
17747 /*! @name BISTBER5 - BIST Bit Error Register 5 */
17748 /*! @{ */
17749 #define DDRPHY_BISTBER5_CKEBER_MASK              (0x3U)
17750 #define DDRPHY_BISTBER5_CKEBER_SHIFT             (0U)
17751 /*! CKEBER - CKE Bit Error.
17752  */
17753 #define DDRPHY_BISTBER5_CKEBER(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_CKEBER_SHIFT)) & DDRPHY_BISTBER5_CKEBER_MASK)
17754 #define DDRPHY_BISTBER5_CKEBER_RSVD_MASK         (0xFFFCU)
17755 #define DDRPHY_BISTBER5_CKEBER_RSVD_SHIFT        (2U)
17756 /*! CKEBER_RSVD - Reserved. Return zeros on reads.
17757  */
17758 #define DDRPHY_BISTBER5_CKEBER_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_CKEBER_RSVD_SHIFT)) & DDRPHY_BISTBER5_CKEBER_RSVD_MASK)
17759 #define DDRPHY_BISTBER5_ODTBER_MASK              (0x30000U)
17760 #define DDRPHY_BISTBER5_ODTBER_SHIFT             (16U)
17761 /*! ODTBER - ODT Bit Error.
17762  */
17763 #define DDRPHY_BISTBER5_ODTBER(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_ODTBER_SHIFT)) & DDRPHY_BISTBER5_ODTBER_MASK)
17764 #define DDRPHY_BISTBER5_ODTBER_RSVD_MASK         (0xFFFC0000U)
17765 #define DDRPHY_BISTBER5_ODTBER_RSVD_SHIFT        (18U)
17766 /*! ODTBER_RSVD - Reserved. Return zeros on reads.
17767  */
17768 #define DDRPHY_BISTBER5_ODTBER_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_ODTBER_RSVD_SHIFT)) & DDRPHY_BISTBER5_ODTBER_RSVD_MASK)
17769 /*! @} */
17770 
17771 /*! @name RANKIDR - Rank ID Register */
17772 /*! @{ */
17773 #define DDRPHY_RANKIDR_RANKWID_MASK              (0xFU)
17774 #define DDRPHY_RANKIDR_RANKWID_SHIFT             (0U)
17775 /*! RANKWID - Rank Write ID
17776  */
17777 #define DDRPHY_RANKIDR_RANKWID(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RANKWID_SHIFT)) & DDRPHY_RANKIDR_RANKWID_MASK)
17778 #define DDRPHY_RANKIDR_RESERVED_15_4_MASK        (0xFFF0U)
17779 #define DDRPHY_RANKIDR_RESERVED_15_4_SHIFT       (4U)
17780 /*! RESERVED_15_4 - Reserved. Return zeroes on reads.
17781  */
17782 #define DDRPHY_RANKIDR_RESERVED_15_4(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RESERVED_15_4_SHIFT)) & DDRPHY_RANKIDR_RESERVED_15_4_MASK)
17783 #define DDRPHY_RANKIDR_RANKRID_MASK              (0xF0000U)
17784 #define DDRPHY_RANKIDR_RANKRID_SHIFT             (16U)
17785 /*! RANKRID - Rank Read ID
17786  */
17787 #define DDRPHY_RANKIDR_RANKRID(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RANKRID_SHIFT)) & DDRPHY_RANKIDR_RANKRID_MASK)
17788 #define DDRPHY_RANKIDR_RESERVED_31_20_MASK       (0xFFF00000U)
17789 #define DDRPHY_RANKIDR_RESERVED_31_20_SHIFT      (20U)
17790 /*! RESERVED_31_20 - Reserved. Return zeroes on reads.
17791  */
17792 #define DDRPHY_RANKIDR_RESERVED_31_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RESERVED_31_20_SHIFT)) & DDRPHY_RANKIDR_RESERVED_31_20_MASK)
17793 /*! @} */
17794 
17795 /*! @name RIOCR0 - Rank I/O Configuration Register 0 */
17796 /*! @{ */
17797 #define DDRPHY_RIOCR0_RESERVED_31_0_MASK         (0xFFFFFFFFU)
17798 #define DDRPHY_RIOCR0_RESERVED_31_0_SHIFT        (0U)
17799 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
17800  */
17801 #define DDRPHY_RIOCR0_RESERVED_31_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR0_RESERVED_31_0_SHIFT)) & DDRPHY_RIOCR0_RESERVED_31_0_MASK)
17802 /*! @} */
17803 
17804 /*! @name RIOCR1 - Rank I/O Configuration Register 1 */
17805 /*! @{ */
17806 #define DDRPHY_RIOCR1_RESERVED_31_0_MASK         (0xFFFFFFFFU)
17807 #define DDRPHY_RIOCR1_RESERVED_31_0_SHIFT        (0U)
17808 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
17809  */
17810 #define DDRPHY_RIOCR1_RESERVED_31_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR1_RESERVED_31_0_SHIFT)) & DDRPHY_RIOCR1_RESERVED_31_0_MASK)
17811 /*! @} */
17812 
17813 /*! @name RIOCR2 - Rank I/O Configuration Register 2 */
17814 /*! @{ */
17815 #define DDRPHY_RIOCR2_CSOEMODE_MASK              (0x3U)
17816 #define DDRPHY_RIOCR2_CSOEMODE_SHIFT             (0U)
17817 /*! CSOEMODE - SDRAM CS_n Output Enable (OE) Mode Selection.
17818  */
17819 #define DDRPHY_RIOCR2_CSOEMODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_CSOEMODE_SHIFT)) & DDRPHY_RIOCR2_CSOEMODE_MASK)
17820 #define DDRPHY_RIOCR2_CSOEMODE_RSVD_MASK         (0xFFFFFCU)
17821 #define DDRPHY_RIOCR2_CSOEMODE_RSVD_SHIFT        (2U)
17822 /*! CSOEMODE_RSVD - Reserved. Return zeros on reads.
17823  */
17824 #define DDRPHY_RIOCR2_CSOEMODE_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_CSOEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR2_CSOEMODE_RSVD_MASK)
17825 #define DDRPHY_RIOCR2_COEMODE_MASK               (0x3000000U)
17826 #define DDRPHY_RIOCR2_COEMODE_SHIFT              (24U)
17827 /*! COEMODE - SDRAM C Output Enable (OE) Mode Selection.
17828  */
17829 #define DDRPHY_RIOCR2_COEMODE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_COEMODE_SHIFT)) & DDRPHY_RIOCR2_COEMODE_MASK)
17830 #define DDRPHY_RIOCR2_COEMODE_RSVD_MASK          (0x3C000000U)
17831 #define DDRPHY_RIOCR2_COEMODE_RSVD_SHIFT         (26U)
17832 /*! COEMODE_RSVD - Reserved. Return zeros on reads.
17833  */
17834 #define DDRPHY_RIOCR2_COEMODE_RSVD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_COEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR2_COEMODE_RSVD_MASK)
17835 #define DDRPHY_RIOCR2_RESERVED_31_30_MASK        (0xC0000000U)
17836 #define DDRPHY_RIOCR2_RESERVED_31_30_SHIFT       (30U)
17837 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
17838  */
17839 #define DDRPHY_RIOCR2_RESERVED_31_30(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_RESERVED_31_30_SHIFT)) & DDRPHY_RIOCR2_RESERVED_31_30_MASK)
17840 /*! @} */
17841 
17842 /*! @name RIOCR3 - Rank I/O Configuration Register 3 */
17843 /*! @{ */
17844 #define DDRPHY_RIOCR3_RESERVED_31_0_MASK         (0xFFFFFFFFU)
17845 #define DDRPHY_RIOCR3_RESERVED_31_0_SHIFT        (0U)
17846 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
17847  */
17848 #define DDRPHY_RIOCR3_RESERVED_31_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR3_RESERVED_31_0_SHIFT)) & DDRPHY_RIOCR3_RESERVED_31_0_MASK)
17849 /*! @} */
17850 
17851 /*! @name RIOCR4 - Rank I/O Configuration Register 4 */
17852 /*! @{ */
17853 #define DDRPHY_RIOCR4_CKEOEMODE_MASK             (0x3U)
17854 #define DDRPHY_RIOCR4_CKEOEMODE_SHIFT            (0U)
17855 /*! CKEOEMODE - SDRAM CKE Output Enable (OE) Mode Selection.
17856  */
17857 #define DDRPHY_RIOCR4_CKEOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR4_CKEOEMODE_SHIFT)) & DDRPHY_RIOCR4_CKEOEMODE_MASK)
17858 #define DDRPHY_RIOCR4_CKEOEMODE_RSVD_MASK        (0xFFFCU)
17859 #define DDRPHY_RIOCR4_CKEOEMODE_RSVD_SHIFT       (2U)
17860 /*! CKEOEMODE_RSVD - Reserved. Return zeros on reads.
17861  */
17862 #define DDRPHY_RIOCR4_CKEOEMODE_RSVD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR4_CKEOEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR4_CKEOEMODE_RSVD_MASK)
17863 #define DDRPHY_RIOCR4_RESERVED_31_16_MASK        (0xFFFF0000U)
17864 #define DDRPHY_RIOCR4_RESERVED_31_16_SHIFT       (16U)
17865 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
17866  */
17867 #define DDRPHY_RIOCR4_RESERVED_31_16(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR4_RESERVED_31_16_SHIFT)) & DDRPHY_RIOCR4_RESERVED_31_16_MASK)
17868 /*! @} */
17869 
17870 /*! @name RIOCR5 - Rank I/O Configuration Register 5 */
17871 /*! @{ */
17872 #define DDRPHY_RIOCR5_ODTOEMODE_MASK             (0x3U)
17873 #define DDRPHY_RIOCR5_ODTOEMODE_SHIFT            (0U)
17874 /*! ODTOEMODE - SDRAM On-die Termination Output Enable (OE) Mode Selection.
17875  */
17876 #define DDRPHY_RIOCR5_ODTOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR5_ODTOEMODE_SHIFT)) & DDRPHY_RIOCR5_ODTOEMODE_MASK)
17877 #define DDRPHY_RIOCR5_ODTOEMODE_RSVD_MASK        (0xFFFCU)
17878 #define DDRPHY_RIOCR5_ODTOEMODE_RSVD_SHIFT       (2U)
17879 /*! ODTOEMODE_RSVD - Reserved. Return zeros on reads.
17880  */
17881 #define DDRPHY_RIOCR5_ODTOEMODE_RSVD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR5_ODTOEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR5_ODTOEMODE_RSVD_MASK)
17882 #define DDRPHY_RIOCR5_RESERVED_31_16_MASK        (0xFFFF0000U)
17883 #define DDRPHY_RIOCR5_RESERVED_31_16_SHIFT       (16U)
17884 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
17885  */
17886 #define DDRPHY_RIOCR5_RESERVED_31_16(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR5_RESERVED_31_16_SHIFT)) & DDRPHY_RIOCR5_RESERVED_31_16_MASK)
17887 /*! @} */
17888 
17889 /*! @name ACIOCR0 - AC I/O Configuration Register 0 */
17890 /*! @{ */
17891 #define DDRPHY_ACIOCR0_ACRANKCLKSEL_MASK         (0x1U)
17892 #define DDRPHY_ACIOCR0_ACRANKCLKSEL_SHIFT        (0U)
17893 /*! ACRANKCLKSEL - Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
17894  */
17895 #define DDRPHY_ACIOCR0_ACRANKCLKSEL(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACRANKCLKSEL_SHIFT)) & DDRPHY_ACIOCR0_ACRANKCLKSEL_MASK)
17896 #define DDRPHY_ACIOCR0_RESERVED_1_MASK           (0x2U)
17897 #define DDRPHY_ACIOCR0_RESERVED_1_SHIFT          (1U)
17898 /*! RESERVED_1 - Reserved. Return zeroes on reads.
17899  */
17900 #define DDRPHY_ACIOCR0_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_1_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_1_MASK)
17901 #define DDRPHY_ACIOCR0_ACODTMODE_MASK            (0xCU)
17902 #define DDRPHY_ACIOCR0_ACODTMODE_SHIFT           (2U)
17903 /*! ACODTMODE - AC On-die Termination Mode
17904  */
17905 #define DDRPHY_ACIOCR0_ACODTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACODTMODE_SHIFT)) & DDRPHY_ACIOCR0_ACODTMODE_MASK)
17906 #define DDRPHY_ACIOCR0_ACPDRMODE_MASK            (0x30U)
17907 #define DDRPHY_ACIOCR0_ACPDRMODE_SHIFT           (4U)
17908 /*! ACPDRMODE - AC Power Down Receiver Mode
17909  */
17910 #define DDRPHY_ACIOCR0_ACPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACPDRMODE_SHIFT)) & DDRPHY_ACIOCR0_ACPDRMODE_MASK)
17911 #define DDRPHY_ACIOCR0_CKDCC_MASK                (0x3C0U)
17912 #define DDRPHY_ACIOCR0_CKDCC_SHIFT               (6U)
17913 /*! CKDCC - CK Duty Cycle Correction
17914  */
17915 #define DDRPHY_ACIOCR0_CKDCC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_CKDCC_SHIFT)) & DDRPHY_ACIOCR0_CKDCC_MASK)
17916 #define DDRPHY_ACIOCR0_ACPNUMSEL_MASK            (0xC00U)
17917 #define DDRPHY_ACIOCR0_ACPNUMSEL_SHIFT           (10U)
17918 /*! ACPNUMSEL - Address/Command custom pin mapping configuration
17919  */
17920 #define DDRPHY_ACIOCR0_ACPNUMSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACPNUMSEL_SHIFT)) & DDRPHY_ACIOCR0_ACPNUMSEL_MASK)
17921 #define DDRPHY_ACIOCR0_RESERVED_15_12_MASK       (0xF000U)
17922 #define DDRPHY_ACIOCR0_RESERVED_15_12_SHIFT      (12U)
17923 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
17924  */
17925 #define DDRPHY_ACIOCR0_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_15_12_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_15_12_MASK)
17926 #define DDRPHY_ACIOCR0_ESR_MASK                  (0xFF0000U)
17927 #define DDRPHY_ACIOCR0_ESR_SHIFT                 (16U)
17928 /*! ESR - Decoupling Capacitance ESR Control in D5M I/O ring
17929  */
17930 #define DDRPHY_ACIOCR0_ESR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ESR_SHIFT)) & DDRPHY_ACIOCR0_ESR_MASK)
17931 #define DDRPHY_ACIOCR0_RESERVED_25_24_MASK       (0x3000000U)
17932 #define DDRPHY_ACIOCR0_RESERVED_25_24_SHIFT      (24U)
17933 /*! RESERVED_25_24 - Reserved. Return zeroes on reads.
17934  */
17935 #define DDRPHY_ACIOCR0_RESERVED_25_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_25_24_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_25_24_MASK)
17936 #define DDRPHY_ACIOCR0_RSTODT_MASK               (0x4000000U)
17937 #define DDRPHY_ACIOCR0_RSTODT_SHIFT              (26U)
17938 /*! RSTODT - SDRAM Reset On-Die Termination
17939  */
17940 #define DDRPHY_ACIOCR0_RSTODT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RSTODT_SHIFT)) & DDRPHY_ACIOCR0_RSTODT_MASK)
17941 #define DDRPHY_ACIOCR0_RESERVED_27_MASK          (0x8000000U)
17942 #define DDRPHY_ACIOCR0_RESERVED_27_SHIFT         (27U)
17943 /*! RESERVED_27 - Reserved. Return zeroes on reads.
17944  */
17945 #define DDRPHY_ACIOCR0_RESERVED_27(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_27_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_27_MASK)
17946 #define DDRPHY_ACIOCR0_RSTPDR_MASK               (0x10000000U)
17947 #define DDRPHY_ACIOCR0_RSTPDR_SHIFT              (28U)
17948 /*! RSTPDR - SDRAM Reset Power Down Receiver
17949  */
17950 #define DDRPHY_ACIOCR0_RSTPDR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RSTPDR_SHIFT)) & DDRPHY_ACIOCR0_RSTPDR_MASK)
17951 #define DDRPHY_ACIOCR0_RSTIOM_MASK               (0x20000000U)
17952 #define DDRPHY_ACIOCR0_RSTIOM_SHIFT              (29U)
17953 /*! RSTIOM - SDRAM Reset I/O Mode
17954  */
17955 #define DDRPHY_ACIOCR0_RSTIOM(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RSTIOM_SHIFT)) & DDRPHY_ACIOCR0_RSTIOM_MASK)
17956 #define DDRPHY_ACIOCR0_ACSR_MASK                 (0xC0000000U)
17957 #define DDRPHY_ACIOCR0_ACSR_SHIFT                (30U)
17958 /*! ACSR - Address/Command Slew Rate (D3F I/O Only)
17959  */
17960 #define DDRPHY_ACIOCR0_ACSR(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACSR_SHIFT)) & DDRPHY_ACIOCR0_ACSR_MASK)
17961 /*! @} */
17962 
17963 /*! @name ACIOCR1 - AC I/O Configuration Register 1 */
17964 /*! @{ */
17965 #define DDRPHY_ACIOCR1_AOEMODE_MASK              (0xFFFFFFFFU)
17966 #define DDRPHY_ACIOCR1_AOEMODE_SHIFT             (0U)
17967 /*! AOEMODE - SDRAM Address Output Enable (OE) Mode Selection
17968  */
17969 #define DDRPHY_ACIOCR1_AOEMODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR1_AOEMODE_SHIFT)) & DDRPHY_ACIOCR1_AOEMODE_MASK)
17970 /*! @} */
17971 
17972 /*! @name ACIOCR2 - AC I/O Configuration Register 2 */
17973 /*! @{ */
17974 #define DDRPHY_ACIOCR2_ACCLKGATE0_MASK           (0xFFFFFFU)
17975 #define DDRPHY_ACIOCR2_ACCLKGATE0_SHIFT          (0U)
17976 /*! ACCLKGATE0 - Clock gating for AC D slices [23:0]
17977  */
17978 #define DDRPHY_ACIOCR2_ACCLKGATE0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACCLKGATE0_MASK)
17979 #define DDRPHY_ACIOCR2_CKCLKGATE0_MASK           (0x3000000U)
17980 #define DDRPHY_ACIOCR2_CKCLKGATE0_SHIFT          (24U)
17981 /*! CKCLKGATE0 - Clock gating for CK D slices [1:0]
17982  */
17983 #define DDRPHY_ACIOCR2_CKCLKGATE0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_CKCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_CKCLKGATE0_MASK)
17984 #define DDRPHY_ACIOCR2_CKNCLKGATE0_MASK          (0xC000000U)
17985 #define DDRPHY_ACIOCR2_CKNCLKGATE0_SHIFT         (26U)
17986 /*! CKNCLKGATE0 - Clock gating for CK# D slices [1:0]
17987  */
17988 #define DDRPHY_ACIOCR2_CKNCLKGATE0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_CKNCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_CKNCLKGATE0_MASK)
17989 #define DDRPHY_ACIOCR2_ACTECLKGATE0_MASK         (0x10000000U)
17990 #define DDRPHY_ACIOCR2_ACTECLKGATE0_SHIFT        (28U)
17991 /*! ACTECLKGATE0 - Clock gating for Termination Enable D slices [0]
17992  */
17993 #define DDRPHY_ACIOCR2_ACTECLKGATE0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACTECLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACTECLKGATE0_MASK)
17994 #define DDRPHY_ACIOCR2_ACPDRCLKGATE0_MASK        (0x20000000U)
17995 #define DDRPHY_ACIOCR2_ACPDRCLKGATE0_SHIFT       (29U)
17996 /*! ACPDRCLKGATE0 - Clock gating for Power Down Receiver D slices [0]
17997  */
17998 #define DDRPHY_ACIOCR2_ACPDRCLKGATE0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACPDRCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACPDRCLKGATE0_MASK)
17999 #define DDRPHY_ACIOCR2_ACOECLKGATE0_MASK         (0x40000000U)
18000 #define DDRPHY_ACIOCR2_ACOECLKGATE0_SHIFT        (30U)
18001 /*! ACOECLKGATE0 - Clock gating for Output Enable D slices [0]
18002  */
18003 #define DDRPHY_ACIOCR2_ACOECLKGATE0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACOECLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACOECLKGATE0_MASK)
18004 #define DDRPHY_ACIOCR2_CLKGENCLKGATE_MASK        (0x80000000U)
18005 #define DDRPHY_ACIOCR2_CLKGENCLKGATE_SHIFT       (31U)
18006 /*! CLKGENCLKGATE - Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice
18007  */
18008 #define DDRPHY_ACIOCR2_CLKGENCLKGATE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_CLKGENCLKGATE_SHIFT)) & DDRPHY_ACIOCR2_CLKGENCLKGATE_MASK)
18009 /*! @} */
18010 
18011 /*! @name ACIOCR3 - AC I/O Configuration Register 3 */
18012 /*! @{ */
18013 #define DDRPHY_ACIOCR3_CKOEMODE_MASK             (0xFU)
18014 #define DDRPHY_ACIOCR3_CKOEMODE_SHIFT            (0U)
18015 /*! CKOEMODE - SDRAM CK Output Enable (OE) Mode Selection.
18016  */
18017 #define DDRPHY_ACIOCR3_CKOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_CKOEMODE_SHIFT)) & DDRPHY_ACIOCR3_CKOEMODE_MASK)
18018 #define DDRPHY_ACIOCR3_CKOEMODE_RSVD_MASK        (0xF0U)
18019 #define DDRPHY_ACIOCR3_CKOEMODE_RSVD_SHIFT       (4U)
18020 /*! CKOEMODE_RSVD - Reserved. Return zeros on reads.
18021  */
18022 #define DDRPHY_ACIOCR3_CKOEMODE_RSVD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_CKOEMODE_RSVD_SHIFT)) & DDRPHY_ACIOCR3_CKOEMODE_RSVD_MASK)
18023 #define DDRPHY_ACIOCR3_RESERVED_15_8_MASK        (0xFF00U)
18024 #define DDRPHY_ACIOCR3_RESERVED_15_8_SHIFT       (8U)
18025 /*! RESERVED_15_8 - Reserved. Return zeroes on reads.
18026  */
18027 #define DDRPHY_ACIOCR3_RESERVED_15_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_RESERVED_15_8_SHIFT)) & DDRPHY_ACIOCR3_RESERVED_15_8_MASK)
18028 #define DDRPHY_ACIOCR3_ACTOEMODE_MASK            (0x30000U)
18029 #define DDRPHY_ACIOCR3_ACTOEMODE_SHIFT           (16U)
18030 /*! ACTOEMODE - SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
18031  */
18032 #define DDRPHY_ACIOCR3_ACTOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_ACTOEMODE_SHIFT)) & DDRPHY_ACIOCR3_ACTOEMODE_MASK)
18033 #define DDRPHY_ACIOCR3_A16OEMODE_MASK            (0xC0000U)
18034 #define DDRPHY_ACIOCR3_A16OEMODE_SHIFT           (18U)
18035 /*! A16OEMODE - SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
18036  */
18037 #define DDRPHY_ACIOCR3_A16OEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_A16OEMODE_SHIFT)) & DDRPHY_ACIOCR3_A16OEMODE_MASK)
18038 #define DDRPHY_ACIOCR3_A17OEMODE_MASK            (0x300000U)
18039 #define DDRPHY_ACIOCR3_A17OEMODE_SHIFT           (20U)
18040 /*! A17OEMODE - SDRAM A[17] Output Enable (OE) Mode Selection
18041  */
18042 #define DDRPHY_ACIOCR3_A17OEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_A17OEMODE_SHIFT)) & DDRPHY_ACIOCR3_A17OEMODE_MASK)
18043 #define DDRPHY_ACIOCR3_BAOEMODE_MASK             (0x3C00000U)
18044 #define DDRPHY_ACIOCR3_BAOEMODE_SHIFT            (22U)
18045 /*! BAOEMODE - SDRAM Bank Address Output Enable (OE) Mode Selection
18046  */
18047 #define DDRPHY_ACIOCR3_BAOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_BAOEMODE_SHIFT)) & DDRPHY_ACIOCR3_BAOEMODE_MASK)
18048 #define DDRPHY_ACIOCR3_BGOEMODE_MASK             (0x3C000000U)
18049 #define DDRPHY_ACIOCR3_BGOEMODE_SHIFT            (26U)
18050 /*! BGOEMODE - SDRAM Bank Group Output Enable (OE) Mode Selection
18051  */
18052 #define DDRPHY_ACIOCR3_BGOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_BGOEMODE_SHIFT)) & DDRPHY_ACIOCR3_BGOEMODE_MASK)
18053 #define DDRPHY_ACIOCR3_PAROEMODE_MASK            (0xC0000000U)
18054 #define DDRPHY_ACIOCR3_PAROEMODE_SHIFT           (30U)
18055 /*! PAROEMODE - SDRAM Parity Output Enable (OE) Mode Selection
18056  */
18057 #define DDRPHY_ACIOCR3_PAROEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_PAROEMODE_SHIFT)) & DDRPHY_ACIOCR3_PAROEMODE_MASK)
18058 /*! @} */
18059 
18060 /*! @name ACIOCR4 - AC I/O Configuration Register 4 */
18061 /*! @{ */
18062 #define DDRPHY_ACIOCR4_ACCLKGATE1_MASK           (0xFFFFFFU)
18063 #define DDRPHY_ACIOCR4_ACCLKGATE1_SHIFT          (0U)
18064 /*! ACCLKGATE1 - Clock gating for AC D slices [47:24]
18065  */
18066 #define DDRPHY_ACIOCR4_ACCLKGATE1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACCLKGATE1_MASK)
18067 #define DDRPHY_ACIOCR4_CKCLKGATE1_MASK           (0x3000000U)
18068 #define DDRPHY_ACIOCR4_CKCLKGATE1_SHIFT          (24U)
18069 /*! CKCLKGATE1 - Clock gating for CK D slices [3:2]
18070  */
18071 #define DDRPHY_ACIOCR4_CKCLKGATE1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_CKCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_CKCLKGATE1_MASK)
18072 #define DDRPHY_ACIOCR4_CKNCLKGATE1_MASK          (0xC000000U)
18073 #define DDRPHY_ACIOCR4_CKNCLKGATE1_SHIFT         (26U)
18074 /*! CKNCLKGATE1 - Clock gating for CK# D slices [3:2]
18075  */
18076 #define DDRPHY_ACIOCR4_CKNCLKGATE1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_CKNCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_CKNCLKGATE1_MASK)
18077 #define DDRPHY_ACIOCR4_ACTECLKGATE1_MASK         (0x10000000U)
18078 #define DDRPHY_ACIOCR4_ACTECLKGATE1_SHIFT        (28U)
18079 /*! ACTECLKGATE1 - Clock gating for Termination Enable D slices [1]
18080  */
18081 #define DDRPHY_ACIOCR4_ACTECLKGATE1(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACTECLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACTECLKGATE1_MASK)
18082 #define DDRPHY_ACIOCR4_ACPDRCLKGATE1_MASK        (0x20000000U)
18083 #define DDRPHY_ACIOCR4_ACPDRCLKGATE1_SHIFT       (29U)
18084 /*! ACPDRCLKGATE1 - Clock gating for Power Down Receiver D slices [1]
18085  */
18086 #define DDRPHY_ACIOCR4_ACPDRCLKGATE1(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACPDRCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACPDRCLKGATE1_MASK)
18087 #define DDRPHY_ACIOCR4_ACOECLKGATE1_MASK         (0x40000000U)
18088 #define DDRPHY_ACIOCR4_ACOECLKGATE1_SHIFT        (30U)
18089 /*! ACOECLKGATE1 - Clock gating for Output Enable D slices [1]
18090  */
18091 #define DDRPHY_ACIOCR4_ACOECLKGATE1(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACOECLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACOECLKGATE1_MASK)
18092 #define DDRPHY_ACIOCR4_LBCLKGATE_MASK            (0x80000000U)
18093 #define DDRPHY_ACIOCR4_LBCLKGATE_SHIFT           (31U)
18094 /*! LBCLKGATE - Clock gating for AC LB slices and loopback read valid slices
18095  */
18096 #define DDRPHY_ACIOCR4_LBCLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_LBCLKGATE_SHIFT)) & DDRPHY_ACIOCR4_LBCLKGATE_MASK)
18097 /*! @} */
18098 
18099 /*! @name ACIOCR5 - AC I/O Configuration Register 5 */
18100 /*! @{ */
18101 #define DDRPHY_ACIOCR5_ACRXM_MASK                (0x7FFU)
18102 #define DDRPHY_ACIOCR5_ACRXM_SHIFT               (0U)
18103 /*! ACRXM - AC IO Receiver Mode
18104  */
18105 #define DDRPHY_ACIOCR5_ACRXM(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACRXM_SHIFT)) & DDRPHY_ACIOCR5_ACRXM_MASK)
18106 #define DDRPHY_ACIOCR5_ACTXM_MASK                (0x3FF800U)
18107 #define DDRPHY_ACIOCR5_ACTXM_SHIFT               (11U)
18108 /*! ACTXM - AC IO Transmitter Mode
18109  */
18110 #define DDRPHY_ACIOCR5_ACTXM(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACTXM_SHIFT)) & DDRPHY_ACIOCR5_ACTXM_MASK)
18111 #define DDRPHY_ACIOCR5_ACXIOM_MASK               (0x1C00000U)
18112 #define DDRPHY_ACIOCR5_ACXIOM_SHIFT              (22U)
18113 /*! ACXIOM - AC IO Mode
18114  */
18115 #define DDRPHY_ACIOCR5_ACXIOM(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACXIOM_SHIFT)) & DDRPHY_ACIOCR5_ACXIOM_MASK)
18116 #define DDRPHY_ACIOCR5_ACVREFIOM_MASK            (0xE000000U)
18117 #define DDRPHY_ACIOCR5_ACVREFIOM_SHIFT           (25U)
18118 /*! ACVREFIOM - IOM bits for PVREF and PVREFE cells in AC IO ring
18119  */
18120 #define DDRPHY_ACIOCR5_ACVREFIOM(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACVREFIOM_SHIFT)) & DDRPHY_ACIOCR5_ACVREFIOM_MASK)
18121 #define DDRPHY_ACIOCR5_RESERVED_31_28_MASK       (0xF0000000U)
18122 #define DDRPHY_ACIOCR5_RESERVED_31_28_SHIFT      (28U)
18123 /*! RESERVED_31_28 - Reserved. Return zeroes on reads.
18124  */
18125 #define DDRPHY_ACIOCR5_RESERVED_31_28(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_RESERVED_31_28_SHIFT)) & DDRPHY_ACIOCR5_RESERVED_31_28_MASK)
18126 /*! @} */
18127 
18128 /*! @name IOVCR0 - IO VREF Control Register 0 */
18129 /*! @{ */
18130 #define DDRPHY_IOVCR0_ACVREFISEL_MASK            (0x7FU)
18131 #define DDRPHY_IOVCR0_ACVREFISEL_SHIFT           (0U)
18132 /*! ACVREFISEL - REFSEL Control for internal AC IOs
18133  */
18134 #define DDRPHY_IOVCR0_ACVREFISEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACVREFISEL_SHIFT)) & DDRPHY_IOVCR0_ACVREFISEL_MASK)
18135 #define DDRPHY_IOVCR0_ACVREFISELRANGE_MASK       (0x80U)
18136 #define DDRPHY_IOVCR0_ACVREFISELRANGE_SHIFT      (7U)
18137 /*! ACVREFISELRANGE - Internal VREF generator REFSEL ragne select
18138  */
18139 #define DDRPHY_IOVCR0_ACVREFISELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACVREFISELRANGE_SHIFT)) & DDRPHY_IOVCR0_ACVREFISELRANGE_MASK)
18140 #define DDRPHY_IOVCR0_ACREFSSEL_MASK             (0x7F00U)
18141 #define DDRPHY_IOVCR0_ACREFSSEL_SHIFT            (8U)
18142 /*! ACREFSSEL - Address/command lane Single-End VREF Select
18143  */
18144 #define DDRPHY_IOVCR0_ACREFSSEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFSSEL_SHIFT)) & DDRPHY_IOVCR0_ACREFSSEL_MASK)
18145 #define DDRPHY_IOVCR0_ACREFSSELRANGE_MASK        (0x8000U)
18146 #define DDRPHY_IOVCR0_ACREFSSELRANGE_SHIFT       (15U)
18147 /*! ACREFSSELRANGE - Single ended VREF generator REFSEL range select
18148  */
18149 #define DDRPHY_IOVCR0_ACREFSSELRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFSSELRANGE_SHIFT)) & DDRPHY_IOVCR0_ACREFSSELRANGE_MASK)
18150 #define DDRPHY_IOVCR0_ACREFESEL_MASK             (0x7F0000U)
18151 #define DDRPHY_IOVCR0_ACREFESEL_SHIFT            (16U)
18152 /*! ACREFESEL - Address/command lane External VREF Select
18153  */
18154 #define DDRPHY_IOVCR0_ACREFESEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFESEL_SHIFT)) & DDRPHY_IOVCR0_ACREFESEL_MASK)
18155 #define DDRPHY_IOVCR0_ACREFESELRANGE_MASK        (0x800000U)
18156 #define DDRPHY_IOVCR0_ACREFESELRANGE_SHIFT       (23U)
18157 /*! ACREFESELRANGE - External VREF generato REFSEL range select
18158  */
18159 #define DDRPHY_IOVCR0_ACREFESELRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFESELRANGE_SHIFT)) & DDRPHY_IOVCR0_ACREFESELRANGE_MASK)
18160 #define DDRPHY_IOVCR0_ACREFIEN_MASK              (0x1000000U)
18161 #define DDRPHY_IOVCR0_ACREFIEN_SHIFT             (24U)
18162 /*! ACREFIEN - Address/command lane Internal VREF Enable
18163  */
18164 #define DDRPHY_IOVCR0_ACREFIEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFIEN_SHIFT)) & DDRPHY_IOVCR0_ACREFIEN_MASK)
18165 #define DDRPHY_IOVCR0_ACREFSEN_MASK              (0x2000000U)
18166 #define DDRPHY_IOVCR0_ACREFSEN_SHIFT             (25U)
18167 /*! ACREFSEN - Address/command lane Single-End VREF Enable
18168  */
18169 #define DDRPHY_IOVCR0_ACREFSEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFSEN_SHIFT)) & DDRPHY_IOVCR0_ACREFSEN_MASK)
18170 #define DDRPHY_IOVCR0_ACREFEEN_MASK              (0xC000000U)
18171 #define DDRPHY_IOVCR0_ACREFEEN_SHIFT             (26U)
18172 /*! ACREFEEN - Address/command lane Internal VREF Enable
18173  */
18174 #define DDRPHY_IOVCR0_ACREFEEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFEEN_SHIFT)) & DDRPHY_IOVCR0_ACREFEEN_MASK)
18175 #define DDRPHY_IOVCR0_ACREFPEN_MASK              (0x10000000U)
18176 #define DDRPHY_IOVCR0_ACREFPEN_SHIFT             (28U)
18177 /*! ACREFPEN - Address/command lane VREF Pad Enable
18178  */
18179 #define DDRPHY_IOVCR0_ACREFPEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFPEN_SHIFT)) & DDRPHY_IOVCR0_ACREFPEN_MASK)
18180 #define DDRPHY_IOVCR0_RESERVED_31_29_MASK        (0xE0000000U)
18181 #define DDRPHY_IOVCR0_RESERVED_31_29_SHIFT       (29U)
18182 /*! RESERVED_31_29 - Reserved. Return zeroes on reads.
18183  */
18184 #define DDRPHY_IOVCR0_RESERVED_31_29(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_RESERVED_31_29_SHIFT)) & DDRPHY_IOVCR0_RESERVED_31_29_MASK)
18185 /*! @} */
18186 
18187 /*! @name IOVCR1 - IO VREF Control Register 1 */
18188 /*! @{ */
18189 #define DDRPHY_IOVCR1_RESERVED_31_0_MASK         (0xFFFFFFFFU)
18190 #define DDRPHY_IOVCR1_RESERVED_31_0_SHIFT        (0U)
18191 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
18192  */
18193 #define DDRPHY_IOVCR1_RESERVED_31_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR1_RESERVED_31_0_SHIFT)) & DDRPHY_IOVCR1_RESERVED_31_0_MASK)
18194 /*! @} */
18195 
18196 /*! @name VTCR0 - VREF Training Control Register 0 */
18197 /*! @{ */
18198 #define DDRPHY_VTCR0_DVINIT_MASK                 (0x3FU)
18199 #define DDRPHY_VTCR0_DVINIT_SHIFT                (0U)
18200 /*! DVINIT - Initial DRAM DQ VREF value used during DRAM VREF training
18201  */
18202 #define DDRPHY_VTCR0_DVINIT(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVINIT_SHIFT)) & DDRPHY_VTCR0_DVINIT_MASK)
18203 #define DDRPHY_VTCR0_DVMIN_MASK                  (0xFC0U)
18204 #define DDRPHY_VTCR0_DVMIN_SHIFT                 (6U)
18205 /*! DVMIN - Minimum VREF limit value used during DRAM VREF training
18206  */
18207 #define DDRPHY_VTCR0_DVMIN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVMIN_SHIFT)) & DDRPHY_VTCR0_DVMIN_MASK)
18208 #define DDRPHY_VTCR0_DVMAX_MASK                  (0x3F000U)
18209 #define DDRPHY_VTCR0_DVMAX_SHIFT                 (12U)
18210 /*! DVMAX - Maximum VREF limit value used during DRAM VREF training
18211  */
18212 #define DDRPHY_VTCR0_DVMAX(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVMAX_SHIFT)) & DDRPHY_VTCR0_DVMAX_MASK)
18213 #define DDRPHY_VTCR0_DVSS_MASK                   (0x3C0000U)
18214 #define DDRPHY_VTCR0_DVSS_SHIFT                  (18U)
18215 /*! DVSS - DRAM DQ VREF step size used during DRAM VREF training
18216  */
18217 #define DDRPHY_VTCR0_DVSS(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVSS_SHIFT)) & DDRPHY_VTCR0_DVSS_MASK)
18218 #define DDRPHY_VTCR0_VWCR_MASK                   (0x3C00000U)
18219 #define DDRPHY_VTCR0_VWCR_SHIFT                  (22U)
18220 /*! VWCR - VREF Word Count
18221  */
18222 #define DDRPHY_VTCR0_VWCR(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_VWCR_SHIFT)) & DDRPHY_VTCR0_VWCR_MASK)
18223 #define DDRPHY_VTCR0_RESERVED_26_MASK            (0x4000000U)
18224 #define DDRPHY_VTCR0_RESERVED_26_SHIFT           (26U)
18225 /*! RESERVED_26 - Reserved. Returns zeroes on reads.
18226  */
18227 #define DDRPHY_VTCR0_RESERVED_26(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_RESERVED_26_SHIFT)) & DDRPHY_VTCR0_RESERVED_26_MASK)
18228 #define DDRPHY_VTCR0_PDAEN_MASK                  (0x8000000U)
18229 #define DDRPHY_VTCR0_PDAEN_SHIFT                 (27U)
18230 /*! PDAEN - Per Device Addressability Enable
18231  */
18232 #define DDRPHY_VTCR0_PDAEN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_PDAEN_SHIFT)) & DDRPHY_VTCR0_PDAEN_MASK)
18233 #define DDRPHY_VTCR0_DVEN_MASK                   (0x10000000U)
18234 #define DDRPHY_VTCR0_DVEN_SHIFT                  (28U)
18235 /*! DVEN - DRM DQ VREF training Enable
18236  */
18237 #define DDRPHY_VTCR0_DVEN(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVEN_SHIFT)) & DDRPHY_VTCR0_DVEN_MASK)
18238 #define DDRPHY_VTCR0_tVREF_MASK                  (0xE0000000U)
18239 #define DDRPHY_VTCR0_tVREF_SHIFT                 (29U)
18240 /*! tVREF - Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training
18241  */
18242 #define DDRPHY_VTCR0_tVREF(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_tVREF_SHIFT)) & DDRPHY_VTCR0_tVREF_MASK)
18243 /*! @} */
18244 
18245 /*! @name VTCR1 - VREF Training Control Register 1 */
18246 /*! @{ */
18247 #define DDRPHY_VTCR1_HVIO_MASK                   (0x1U)
18248 #define DDRPHY_VTCR1_HVIO_SHIFT                  (0U)
18249 /*! HVIO - Host IO Type Control
18250  */
18251 #define DDRPHY_VTCR1_HVIO(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVIO_SHIFT)) & DDRPHY_VTCR1_HVIO_MASK)
18252 #define DDRPHY_VTCR1_HVEN_MASK                   (0x2U)
18253 #define DDRPHY_VTCR1_HVEN_SHIFT                  (1U)
18254 /*! HVEN - HOST (IO) internal VREF training Enable
18255  */
18256 #define DDRPHY_VTCR1_HVEN(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVEN_SHIFT)) & DDRPHY_VTCR1_HVEN_MASK)
18257 #define DDRPHY_VTCR1_ENUM_MASK                   (0x4U)
18258 #define DDRPHY_VTCR1_ENUM_SHIFT                  (2U)
18259 /*! ENUM - Number of LCDL Eye points for which VREF training is repeated
18260  */
18261 #define DDRPHY_VTCR1_ENUM(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_ENUM_SHIFT)) & DDRPHY_VTCR1_ENUM_MASK)
18262 #define DDRPHY_VTCR1_EOFF_MASK                   (0x18U)
18263 #define DDRPHY_VTCR1_EOFF_SHIFT                  (3U)
18264 /*! EOFF - Eye LCDL Offset value for VREF training
18265  */
18266 #define DDRPHY_VTCR1_EOFF(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_EOFF_SHIFT)) & DDRPHY_VTCR1_EOFF_MASK)
18267 #define DDRPHY_VTCR1_tVREFIO_MASK                (0xE0U)
18268 #define DDRPHY_VTCR1_tVREFIO_SHIFT               (5U)
18269 /*! tVREFIO - Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
18270  */
18271 #define DDRPHY_VTCR1_tVREFIO(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_tVREFIO_SHIFT)) & DDRPHY_VTCR1_tVREFIO_MASK)
18272 #define DDRPHY_VTCR1_SHREN_MASK                  (0x100U)
18273 #define DDRPHY_VTCR1_SHREN_SHIFT                 (8U)
18274 /*! SHREN - Static Host Vref Rank Enable
18275  */
18276 #define DDRPHY_VTCR1_SHREN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_SHREN_SHIFT)) & DDRPHY_VTCR1_SHREN_MASK)
18277 #define DDRPHY_VTCR1_SHRNK_MASK                  (0x600U)
18278 #define DDRPHY_VTCR1_SHRNK_SHIFT                 (9U)
18279 /*! SHRNK - Static Host Vref Rank Value
18280  */
18281 #define DDRPHY_VTCR1_SHRNK(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_SHRNK_SHIFT)) & DDRPHY_VTCR1_SHRNK_MASK)
18282 #define DDRPHY_VTCR1_RESERVED_11_MASK            (0x800U)
18283 #define DDRPHY_VTCR1_RESERVED_11_SHIFT           (11U)
18284 /*! RESERVED_11 - Reserved. Returns zeroes on reads.
18285  */
18286 #define DDRPHY_VTCR1_RESERVED_11(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_11_SHIFT)) & DDRPHY_VTCR1_RESERVED_11_MASK)
18287 #define DDRPHY_VTCR1_HVMIN_MASK                  (0x7F000U)
18288 #define DDRPHY_VTCR1_HVMIN_SHIFT                 (12U)
18289 /*! HVMIN - Minimum VREF limit value used during DRAM VREF training.
18290  */
18291 #define DDRPHY_VTCR1_HVMIN(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVMIN_SHIFT)) & DDRPHY_VTCR1_HVMIN_MASK)
18292 #define DDRPHY_VTCR1_RESERVED_19_MASK            (0x80000U)
18293 #define DDRPHY_VTCR1_RESERVED_19_SHIFT           (19U)
18294 /*! RESERVED_19 - Reserved. Returns zeroes on reads.
18295  */
18296 #define DDRPHY_VTCR1_RESERVED_19(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_19_SHIFT)) & DDRPHY_VTCR1_RESERVED_19_MASK)
18297 #define DDRPHY_VTCR1_HVMAX_MASK                  (0x7F00000U)
18298 #define DDRPHY_VTCR1_HVMAX_SHIFT                 (20U)
18299 /*! HVMAX - Maximum VREF limit value used during DRAM VREF training.
18300  */
18301 #define DDRPHY_VTCR1_HVMAX(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVMAX_SHIFT)) & DDRPHY_VTCR1_HVMAX_MASK)
18302 #define DDRPHY_VTCR1_RESERVED_27_MASK            (0x8000000U)
18303 #define DDRPHY_VTCR1_RESERVED_27_SHIFT           (27U)
18304 /*! RESERVED_27 - Reserved. Returns zeroes on reads.
18305  */
18306 #define DDRPHY_VTCR1_RESERVED_27(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
18307 #define DDRPHY_VTCR1_HVSS_MASK                   (0xF0000000U)
18308 #define DDRPHY_VTCR1_HVSS_SHIFT                  (28U)
18309 /*! HVSS - Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)
18310  */
18311 #define DDRPHY_VTCR1_HVSS(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVSS_SHIFT)) & DDRPHY_VTCR1_HVSS_MASK)
18312 /*! @} */
18313 
18314 /*! @name ACBDLR0 - AC Bit Delay Line Register 0 */
18315 /*! @{ */
18316 #define DDRPHY_ACBDLR0_CK0BD_MASK                (0x3FU)
18317 #define DDRPHY_ACBDLR0_CK0BD_SHIFT               (0U)
18318 /*! CK0BD - CK0 Bit Delay
18319  */
18320 #define DDRPHY_ACBDLR0_CK0BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK0BD_SHIFT)) & DDRPHY_ACBDLR0_CK0BD_MASK)
18321 #define DDRPHY_ACBDLR0_RESERVED_7_6_MASK         (0xC0U)
18322 #define DDRPHY_ACBDLR0_RESERVED_7_6_SHIFT        (6U)
18323 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18324  */
18325 #define DDRPHY_ACBDLR0_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_7_6_MASK)
18326 #define DDRPHY_ACBDLR0_CK1BD_MASK                (0x3F00U)
18327 #define DDRPHY_ACBDLR0_CK1BD_SHIFT               (8U)
18328 /*! CK1BD - CK1 Bit Delay
18329  */
18330 #define DDRPHY_ACBDLR0_CK1BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK1BD_SHIFT)) & DDRPHY_ACBDLR0_CK1BD_MASK)
18331 #define DDRPHY_ACBDLR0_RESERVED_15_14_MASK       (0xC000U)
18332 #define DDRPHY_ACBDLR0_RESERVED_15_14_SHIFT      (14U)
18333 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18334  */
18335 #define DDRPHY_ACBDLR0_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_15_14_MASK)
18336 #define DDRPHY_ACBDLR0_CK2BD_MASK                (0x3F0000U)
18337 #define DDRPHY_ACBDLR0_CK2BD_SHIFT               (16U)
18338 /*! CK2BD - CK2 Bit Delay
18339  */
18340 #define DDRPHY_ACBDLR0_CK2BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK2BD_SHIFT)) & DDRPHY_ACBDLR0_CK2BD_MASK)
18341 #define DDRPHY_ACBDLR0_RESERVED_23_22_MASK       (0xC00000U)
18342 #define DDRPHY_ACBDLR0_RESERVED_23_22_SHIFT      (22U)
18343 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18344  */
18345 #define DDRPHY_ACBDLR0_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_23_22_MASK)
18346 #define DDRPHY_ACBDLR0_CK3BD_MASK                (0x3F000000U)
18347 #define DDRPHY_ACBDLR0_CK3BD_SHIFT               (24U)
18348 /*! CK3BD - CK3 Bit Delay
18349  */
18350 #define DDRPHY_ACBDLR0_CK3BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK3BD_SHIFT)) & DDRPHY_ACBDLR0_CK3BD_MASK)
18351 #define DDRPHY_ACBDLR0_RESERVED_31_30_MASK       (0xC0000000U)
18352 #define DDRPHY_ACBDLR0_RESERVED_31_30_SHIFT      (30U)
18353 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18354  */
18355 #define DDRPHY_ACBDLR0_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_31_30_MASK)
18356 /*! @} */
18357 
18358 /*! @name ACBDLR1 - AC Bit Delay Line Register 1 */
18359 /*! @{ */
18360 #define DDRPHY_ACBDLR1_ACTBD_MASK                (0x3FU)
18361 #define DDRPHY_ACBDLR1_ACTBD_SHIFT               (0U)
18362 /*! ACTBD - Delay select for the BDL on ACTN.
18363  */
18364 #define DDRPHY_ACBDLR1_ACTBD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_ACTBD_SHIFT)) & DDRPHY_ACBDLR1_ACTBD_MASK)
18365 #define DDRPHY_ACBDLR1_RESERVED_7_6_MASK         (0xC0U)
18366 #define DDRPHY_ACBDLR1_RESERVED_7_6_SHIFT        (6U)
18367 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18368  */
18369 #define DDRPHY_ACBDLR1_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_7_6_MASK)
18370 #define DDRPHY_ACBDLR1_A17BD_MASK                (0x3F00U)
18371 #define DDRPHY_ACBDLR1_A17BD_SHIFT               (8U)
18372 /*! A17BD - Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.
18373  */
18374 #define DDRPHY_ACBDLR1_A17BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_A17BD_SHIFT)) & DDRPHY_ACBDLR1_A17BD_MASK)
18375 #define DDRPHY_ACBDLR1_RESERVED_15_14_MASK       (0xC000U)
18376 #define DDRPHY_ACBDLR1_RESERVED_15_14_SHIFT      (14U)
18377 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18378  */
18379 #define DDRPHY_ACBDLR1_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_15_14_MASK)
18380 #define DDRPHY_ACBDLR1_A16BD_MASK                (0x3F0000U)
18381 #define DDRPHY_ACBDLR1_A16BD_SHIFT               (16U)
18382 /*! A16BD - Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.
18383  */
18384 #define DDRPHY_ACBDLR1_A16BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_A16BD_SHIFT)) & DDRPHY_ACBDLR1_A16BD_MASK)
18385 #define DDRPHY_ACBDLR1_RESERVED_23_22_MASK       (0xC00000U)
18386 #define DDRPHY_ACBDLR1_RESERVED_23_22_SHIFT      (22U)
18387 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18388  */
18389 #define DDRPHY_ACBDLR1_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_23_22_MASK)
18390 #define DDRPHY_ACBDLR1_PARBD_MASK                (0x3F000000U)
18391 #define DDRPHY_ACBDLR1_PARBD_SHIFT               (24U)
18392 /*! PARBD - Delay select for the BDL on Parity.
18393  */
18394 #define DDRPHY_ACBDLR1_PARBD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_PARBD_SHIFT)) & DDRPHY_ACBDLR1_PARBD_MASK)
18395 #define DDRPHY_ACBDLR1_RESERVED_31_30_MASK       (0xC0000000U)
18396 #define DDRPHY_ACBDLR1_RESERVED_31_30_SHIFT      (30U)
18397 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18398  */
18399 #define DDRPHY_ACBDLR1_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_31_30_MASK)
18400 /*! @} */
18401 
18402 /*! @name ACBDLR2 - AC Bit Delay Line Register 2 */
18403 /*! @{ */
18404 #define DDRPHY_ACBDLR2_BA0BD_MASK                (0x3FU)
18405 #define DDRPHY_ACBDLR2_BA0BD_SHIFT               (0U)
18406 /*! BA0BD - Delay select for the BDL on BA[0].
18407  */
18408 #define DDRPHY_ACBDLR2_BA0BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BA0BD_SHIFT)) & DDRPHY_ACBDLR2_BA0BD_MASK)
18409 #define DDRPHY_ACBDLR2_RESERVED_7_6_MASK         (0xC0U)
18410 #define DDRPHY_ACBDLR2_RESERVED_7_6_SHIFT        (6U)
18411 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18412  */
18413 #define DDRPHY_ACBDLR2_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_7_6_MASK)
18414 #define DDRPHY_ACBDLR2_BA1BD_MASK                (0x3F00U)
18415 #define DDRPHY_ACBDLR2_BA1BD_SHIFT               (8U)
18416 /*! BA1BD - Delay select for the BDL on BA[1].
18417  */
18418 #define DDRPHY_ACBDLR2_BA1BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BA1BD_SHIFT)) & DDRPHY_ACBDLR2_BA1BD_MASK)
18419 #define DDRPHY_ACBDLR2_RESERVED_15_14_MASK       (0xC000U)
18420 #define DDRPHY_ACBDLR2_RESERVED_15_14_SHIFT      (14U)
18421 /*! RESERVED_15_14 - Reser.ved Return zeroes on reads.
18422  */
18423 #define DDRPHY_ACBDLR2_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_15_14_MASK)
18424 #define DDRPHY_ACBDLR2_BG0BD_MASK                (0x3F0000U)
18425 #define DDRPHY_ACBDLR2_BG0BD_SHIFT               (16U)
18426 /*! BG0BD - Delay select for the BDL on BG[0].
18427  */
18428 #define DDRPHY_ACBDLR2_BG0BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BG0BD_SHIFT)) & DDRPHY_ACBDLR2_BG0BD_MASK)
18429 #define DDRPHY_ACBDLR2_RESERVED_23_22_MASK       (0xC00000U)
18430 #define DDRPHY_ACBDLR2_RESERVED_23_22_SHIFT      (22U)
18431 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18432  */
18433 #define DDRPHY_ACBDLR2_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_23_22_MASK)
18434 #define DDRPHY_ACBDLR2_BG1BD_MASK                (0x3F000000U)
18435 #define DDRPHY_ACBDLR2_BG1BD_SHIFT               (24U)
18436 /*! BG1BD - Delay select for the BDL on BG[1].
18437  */
18438 #define DDRPHY_ACBDLR2_BG1BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BG1BD_SHIFT)) & DDRPHY_ACBDLR2_BG1BD_MASK)
18439 #define DDRPHY_ACBDLR2_RESERVED_31_30_MASK       (0xC0000000U)
18440 #define DDRPHY_ACBDLR2_RESERVED_31_30_SHIFT      (30U)
18441 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18442  */
18443 #define DDRPHY_ACBDLR2_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_31_30_MASK)
18444 /*! @} */
18445 
18446 /*! @name ACBDLR3 - AC Bit Delay Line Register 3 */
18447 /*! @{ */
18448 #define DDRPHY_ACBDLR3_CS0BD_MASK                (0x3FU)
18449 #define DDRPHY_ACBDLR3_CS0BD_SHIFT               (0U)
18450 /*! CS0BD - Delay select for the BDL on CS[0].
18451  */
18452 #define DDRPHY_ACBDLR3_CS0BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS0BD_SHIFT)) & DDRPHY_ACBDLR3_CS0BD_MASK)
18453 #define DDRPHY_ACBDLR3_RESERVED_7_6_MASK         (0xC0U)
18454 #define DDRPHY_ACBDLR3_RESERVED_7_6_SHIFT        (6U)
18455 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18456  */
18457 #define DDRPHY_ACBDLR3_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_7_6_MASK)
18458 #define DDRPHY_ACBDLR3_CS1BD_MASK                (0x3F00U)
18459 #define DDRPHY_ACBDLR3_CS1BD_SHIFT               (8U)
18460 /*! CS1BD - Delay select for the BDL on CS[1].
18461  */
18462 #define DDRPHY_ACBDLR3_CS1BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS1BD_SHIFT)) & DDRPHY_ACBDLR3_CS1BD_MASK)
18463 #define DDRPHY_ACBDLR3_RESERVED_15_14_MASK       (0xC000U)
18464 #define DDRPHY_ACBDLR3_RESERVED_15_14_SHIFT      (14U)
18465 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18466  */
18467 #define DDRPHY_ACBDLR3_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_15_14_MASK)
18468 #define DDRPHY_ACBDLR3_CS2BD_MASK                (0x3F0000U)
18469 #define DDRPHY_ACBDLR3_CS2BD_SHIFT               (16U)
18470 /*! CS2BD - Delay select for the BDL on CS[2].
18471  */
18472 #define DDRPHY_ACBDLR3_CS2BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS2BD_SHIFT)) & DDRPHY_ACBDLR3_CS2BD_MASK)
18473 #define DDRPHY_ACBDLR3_RESERVED_23_22_MASK       (0xC00000U)
18474 #define DDRPHY_ACBDLR3_RESERVED_23_22_SHIFT      (22U)
18475 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18476  */
18477 #define DDRPHY_ACBDLR3_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_23_22_MASK)
18478 #define DDRPHY_ACBDLR3_CS3BD_MASK                (0x3F000000U)
18479 #define DDRPHY_ACBDLR3_CS3BD_SHIFT               (24U)
18480 /*! CS3BD - Delay select for the BDL on CS[3].
18481  */
18482 #define DDRPHY_ACBDLR3_CS3BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS3BD_SHIFT)) & DDRPHY_ACBDLR3_CS3BD_MASK)
18483 #define DDRPHY_ACBDLR3_RESERVED_31_30_MASK       (0xC0000000U)
18484 #define DDRPHY_ACBDLR3_RESERVED_31_30_SHIFT      (30U)
18485 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18486  */
18487 #define DDRPHY_ACBDLR3_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_31_30_MASK)
18488 /*! @} */
18489 
18490 /*! @name ACBDLR4 - AC Bit Delay Line Register 4 */
18491 /*! @{ */
18492 #define DDRPHY_ACBDLR4_ODT0BD_MASK               (0x3FU)
18493 #define DDRPHY_ACBDLR4_ODT0BD_SHIFT              (0U)
18494 /*! ODT0BD - Delay select for the BDL on ODT[0].
18495  */
18496 #define DDRPHY_ACBDLR4_ODT0BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT0BD_SHIFT)) & DDRPHY_ACBDLR4_ODT0BD_MASK)
18497 #define DDRPHY_ACBDLR4_RESERVED_7_6_MASK         (0xC0U)
18498 #define DDRPHY_ACBDLR4_RESERVED_7_6_SHIFT        (6U)
18499 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18500  */
18501 #define DDRPHY_ACBDLR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_7_6_MASK)
18502 #define DDRPHY_ACBDLR4_ODT1BD_MASK               (0x3F00U)
18503 #define DDRPHY_ACBDLR4_ODT1BD_SHIFT              (8U)
18504 /*! ODT1BD - Delay select for the BDL on ODT[1].
18505  */
18506 #define DDRPHY_ACBDLR4_ODT1BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT1BD_SHIFT)) & DDRPHY_ACBDLR4_ODT1BD_MASK)
18507 #define DDRPHY_ACBDLR4_RESERVED_15_14_MASK       (0xC000U)
18508 #define DDRPHY_ACBDLR4_RESERVED_15_14_SHIFT      (14U)
18509 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18510  */
18511 #define DDRPHY_ACBDLR4_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_15_14_MASK)
18512 #define DDRPHY_ACBDLR4_ODT2BD_MASK               (0x3F0000U)
18513 #define DDRPHY_ACBDLR4_ODT2BD_SHIFT              (16U)
18514 /*! ODT2BD - Delay select for the BDL on ODT[2].
18515  */
18516 #define DDRPHY_ACBDLR4_ODT2BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT2BD_SHIFT)) & DDRPHY_ACBDLR4_ODT2BD_MASK)
18517 #define DDRPHY_ACBDLR4_RESERVED_23_22_MASK       (0xC00000U)
18518 #define DDRPHY_ACBDLR4_RESERVED_23_22_SHIFT      (22U)
18519 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18520  */
18521 #define DDRPHY_ACBDLR4_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_23_22_MASK)
18522 #define DDRPHY_ACBDLR4_ODT3BD_MASK               (0x3F000000U)
18523 #define DDRPHY_ACBDLR4_ODT3BD_SHIFT              (24U)
18524 /*! ODT3BD - Delay select for the BDL on ODT[3].
18525  */
18526 #define DDRPHY_ACBDLR4_ODT3BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT3BD_SHIFT)) & DDRPHY_ACBDLR4_ODT3BD_MASK)
18527 #define DDRPHY_ACBDLR4_RESERVED_31_30_MASK       (0xC0000000U)
18528 #define DDRPHY_ACBDLR4_RESERVED_31_30_SHIFT      (30U)
18529 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18530  */
18531 #define DDRPHY_ACBDLR4_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_31_30_MASK)
18532 /*! @} */
18533 
18534 /*! @name ACBDLR5 - AC Bit Delay Line Register 5 */
18535 /*! @{ */
18536 #define DDRPHY_ACBDLR5_CKE0BD_MASK               (0x3FU)
18537 #define DDRPHY_ACBDLR5_CKE0BD_SHIFT              (0U)
18538 /*! CKE0BD - Delay select for the BDL on CKE[0].
18539  */
18540 #define DDRPHY_ACBDLR5_CKE0BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE0BD_SHIFT)) & DDRPHY_ACBDLR5_CKE0BD_MASK)
18541 #define DDRPHY_ACBDLR5_RESERVED_7_6_MASK         (0xC0U)
18542 #define DDRPHY_ACBDLR5_RESERVED_7_6_SHIFT        (6U)
18543 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18544  */
18545 #define DDRPHY_ACBDLR5_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_7_6_MASK)
18546 #define DDRPHY_ACBDLR5_CKE1BD_MASK               (0x3F00U)
18547 #define DDRPHY_ACBDLR5_CKE1BD_SHIFT              (8U)
18548 /*! CKE1BD - Delay select for the BDL on CKE[1].
18549  */
18550 #define DDRPHY_ACBDLR5_CKE1BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE1BD_SHIFT)) & DDRPHY_ACBDLR5_CKE1BD_MASK)
18551 #define DDRPHY_ACBDLR5_RESERVED_15_14_MASK       (0xC000U)
18552 #define DDRPHY_ACBDLR5_RESERVED_15_14_SHIFT      (14U)
18553 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18554  */
18555 #define DDRPHY_ACBDLR5_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_15_14_MASK)
18556 #define DDRPHY_ACBDLR5_CKE2BD_MASK               (0x3F0000U)
18557 #define DDRPHY_ACBDLR5_CKE2BD_SHIFT              (16U)
18558 /*! CKE2BD - Delay select for the BDL on CKE[2].
18559  */
18560 #define DDRPHY_ACBDLR5_CKE2BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE2BD_SHIFT)) & DDRPHY_ACBDLR5_CKE2BD_MASK)
18561 #define DDRPHY_ACBDLR5_RESERVED_23_22_MASK       (0xC00000U)
18562 #define DDRPHY_ACBDLR5_RESERVED_23_22_SHIFT      (22U)
18563 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18564  */
18565 #define DDRPHY_ACBDLR5_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_23_22_MASK)
18566 #define DDRPHY_ACBDLR5_CKE3BD_MASK               (0x3F000000U)
18567 #define DDRPHY_ACBDLR5_CKE3BD_SHIFT              (24U)
18568 /*! CKE3BD - Delay select for the BDL on CKE[3].
18569  */
18570 #define DDRPHY_ACBDLR5_CKE3BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE3BD_SHIFT)) & DDRPHY_ACBDLR5_CKE3BD_MASK)
18571 #define DDRPHY_ACBDLR5_RESERVED_31_30_MASK       (0xC0000000U)
18572 #define DDRPHY_ACBDLR5_RESERVED_31_30_SHIFT      (30U)
18573 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18574  */
18575 #define DDRPHY_ACBDLR5_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_31_30_MASK)
18576 /*! @} */
18577 
18578 /*! @name ACBDLR6 - AC Bit Delay Line Register 6 */
18579 /*! @{ */
18580 #define DDRPHY_ACBDLR6_A00BD_MASK                (0x3FU)
18581 #define DDRPHY_ACBDLR6_A00BD_SHIFT               (0U)
18582 /*! A00BD - Delay select for the BDL on Address A[0].
18583  */
18584 #define DDRPHY_ACBDLR6_A00BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A00BD_SHIFT)) & DDRPHY_ACBDLR6_A00BD_MASK)
18585 #define DDRPHY_ACBDLR6_RESERVED_7_6_MASK         (0xC0U)
18586 #define DDRPHY_ACBDLR6_RESERVED_7_6_SHIFT        (6U)
18587 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18588  */
18589 #define DDRPHY_ACBDLR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_7_6_MASK)
18590 #define DDRPHY_ACBDLR6_A01BD_MASK                (0x3F00U)
18591 #define DDRPHY_ACBDLR6_A01BD_SHIFT               (8U)
18592 /*! A01BD - Delay select for the BDL on Address A[1].
18593  */
18594 #define DDRPHY_ACBDLR6_A01BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A01BD_SHIFT)) & DDRPHY_ACBDLR6_A01BD_MASK)
18595 #define DDRPHY_ACBDLR6_RESERVED_15_14_MASK       (0xC000U)
18596 #define DDRPHY_ACBDLR6_RESERVED_15_14_SHIFT      (14U)
18597 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18598  */
18599 #define DDRPHY_ACBDLR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_15_14_MASK)
18600 #define DDRPHY_ACBDLR6_A02BD_MASK                (0x3F0000U)
18601 #define DDRPHY_ACBDLR6_A02BD_SHIFT               (16U)
18602 /*! A02BD - Delay select for the BDL on Address A[2].
18603  */
18604 #define DDRPHY_ACBDLR6_A02BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A02BD_SHIFT)) & DDRPHY_ACBDLR6_A02BD_MASK)
18605 #define DDRPHY_ACBDLR6_RESERVED_23_22_MASK       (0xC00000U)
18606 #define DDRPHY_ACBDLR6_RESERVED_23_22_SHIFT      (22U)
18607 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18608  */
18609 #define DDRPHY_ACBDLR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_23_22_MASK)
18610 #define DDRPHY_ACBDLR6_A03BD_MASK                (0x3F000000U)
18611 #define DDRPHY_ACBDLR6_A03BD_SHIFT               (24U)
18612 /*! A03BD - Delay select for the BDL on Address A[3].
18613  */
18614 #define DDRPHY_ACBDLR6_A03BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A03BD_SHIFT)) & DDRPHY_ACBDLR6_A03BD_MASK)
18615 #define DDRPHY_ACBDLR6_RESERVED_31_30_MASK       (0xC0000000U)
18616 #define DDRPHY_ACBDLR6_RESERVED_31_30_SHIFT      (30U)
18617 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18618  */
18619 #define DDRPHY_ACBDLR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_31_30_MASK)
18620 /*! @} */
18621 
18622 /*! @name ACBDLR7 - AC Bit Delay Line Register 7 */
18623 /*! @{ */
18624 #define DDRPHY_ACBDLR7_A04BD_MASK                (0x3FU)
18625 #define DDRPHY_ACBDLR7_A04BD_SHIFT               (0U)
18626 /*! A04BD - Delay select for the BDL on Address A[4].
18627  */
18628 #define DDRPHY_ACBDLR7_A04BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A04BD_SHIFT)) & DDRPHY_ACBDLR7_A04BD_MASK)
18629 #define DDRPHY_ACBDLR7_RESERVED_7_6_MASK         (0xC0U)
18630 #define DDRPHY_ACBDLR7_RESERVED_7_6_SHIFT        (6U)
18631 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18632  */
18633 #define DDRPHY_ACBDLR7_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_7_6_MASK)
18634 #define DDRPHY_ACBDLR7_A05BD_MASK                (0x3F00U)
18635 #define DDRPHY_ACBDLR7_A05BD_SHIFT               (8U)
18636 /*! A05BD - Delay select for the BDL on Address A[5].
18637  */
18638 #define DDRPHY_ACBDLR7_A05BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A05BD_SHIFT)) & DDRPHY_ACBDLR7_A05BD_MASK)
18639 #define DDRPHY_ACBDLR7_RESERVED_15_14_MASK       (0xC000U)
18640 #define DDRPHY_ACBDLR7_RESERVED_15_14_SHIFT      (14U)
18641 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18642  */
18643 #define DDRPHY_ACBDLR7_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_15_14_MASK)
18644 #define DDRPHY_ACBDLR7_A06BD_MASK                (0x3F0000U)
18645 #define DDRPHY_ACBDLR7_A06BD_SHIFT               (16U)
18646 /*! A06BD - Delay select for the BDL on Address A[6].
18647  */
18648 #define DDRPHY_ACBDLR7_A06BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A06BD_SHIFT)) & DDRPHY_ACBDLR7_A06BD_MASK)
18649 #define DDRPHY_ACBDLR7_RESERVED_23_22_MASK       (0xC00000U)
18650 #define DDRPHY_ACBDLR7_RESERVED_23_22_SHIFT      (22U)
18651 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18652  */
18653 #define DDRPHY_ACBDLR7_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_23_22_MASK)
18654 #define DDRPHY_ACBDLR7_A07BD_MASK                (0x3F000000U)
18655 #define DDRPHY_ACBDLR7_A07BD_SHIFT               (24U)
18656 /*! A07BD - Delay select for the BDL on Address A[7].
18657  */
18658 #define DDRPHY_ACBDLR7_A07BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A07BD_SHIFT)) & DDRPHY_ACBDLR7_A07BD_MASK)
18659 #define DDRPHY_ACBDLR7_RESERVED_31_30_MASK       (0xC0000000U)
18660 #define DDRPHY_ACBDLR7_RESERVED_31_30_SHIFT      (30U)
18661 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18662  */
18663 #define DDRPHY_ACBDLR7_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_31_30_MASK)
18664 /*! @} */
18665 
18666 /*! @name ACBDLR8 - AC Bit Delay Line Register 8 */
18667 /*! @{ */
18668 #define DDRPHY_ACBDLR8_A08BD_MASK                (0x3FU)
18669 #define DDRPHY_ACBDLR8_A08BD_SHIFT               (0U)
18670 /*! A08BD - Delay select for the BDL on Address A[8].
18671  */
18672 #define DDRPHY_ACBDLR8_A08BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A08BD_SHIFT)) & DDRPHY_ACBDLR8_A08BD_MASK)
18673 #define DDRPHY_ACBDLR8_RESERVED_7_6_MASK         (0xC0U)
18674 #define DDRPHY_ACBDLR8_RESERVED_7_6_SHIFT        (6U)
18675 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18676  */
18677 #define DDRPHY_ACBDLR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_7_6_MASK)
18678 #define DDRPHY_ACBDLR8_A09BD_MASK                (0x3F00U)
18679 #define DDRPHY_ACBDLR8_A09BD_SHIFT               (8U)
18680 /*! A09BD - Delay select for the BDL on Address A[9].
18681  */
18682 #define DDRPHY_ACBDLR8_A09BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A09BD_SHIFT)) & DDRPHY_ACBDLR8_A09BD_MASK)
18683 #define DDRPHY_ACBDLR8_RESERVED_15_14_MASK       (0xC000U)
18684 #define DDRPHY_ACBDLR8_RESERVED_15_14_SHIFT      (14U)
18685 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18686  */
18687 #define DDRPHY_ACBDLR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_15_14_MASK)
18688 #define DDRPHY_ACBDLR8_A10BD_MASK                (0x3F0000U)
18689 #define DDRPHY_ACBDLR8_A10BD_SHIFT               (16U)
18690 /*! A10BD - Delay select for the BDL on Address A[10].
18691  */
18692 #define DDRPHY_ACBDLR8_A10BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A10BD_SHIFT)) & DDRPHY_ACBDLR8_A10BD_MASK)
18693 #define DDRPHY_ACBDLR8_RESERVED_23_22_MASK       (0xC00000U)
18694 #define DDRPHY_ACBDLR8_RESERVED_23_22_SHIFT      (22U)
18695 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18696  */
18697 #define DDRPHY_ACBDLR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_23_22_MASK)
18698 #define DDRPHY_ACBDLR8_A11BD_MASK                (0x3F000000U)
18699 #define DDRPHY_ACBDLR8_A11BD_SHIFT               (24U)
18700 /*! A11BD - Delay select for the BDL on Address A[11].
18701  */
18702 #define DDRPHY_ACBDLR8_A11BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A11BD_SHIFT)) & DDRPHY_ACBDLR8_A11BD_MASK)
18703 #define DDRPHY_ACBDLR8_RESERVED_31_30_MASK       (0xC0000000U)
18704 #define DDRPHY_ACBDLR8_RESERVED_31_30_SHIFT      (30U)
18705 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18706  */
18707 #define DDRPHY_ACBDLR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_31_30_MASK)
18708 /*! @} */
18709 
18710 /*! @name ACBDLR9 - AC Bit Delay Line Register 9 */
18711 /*! @{ */
18712 #define DDRPHY_ACBDLR9_A12BD_MASK                (0x3FU)
18713 #define DDRPHY_ACBDLR9_A12BD_SHIFT               (0U)
18714 /*! A12BD - Delay select for the BDL on Address A[12].
18715  */
18716 #define DDRPHY_ACBDLR9_A12BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A12BD_SHIFT)) & DDRPHY_ACBDLR9_A12BD_MASK)
18717 #define DDRPHY_ACBDLR9_RESERVED_7_6_MASK         (0xC0U)
18718 #define DDRPHY_ACBDLR9_RESERVED_7_6_SHIFT        (6U)
18719 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18720  */
18721 #define DDRPHY_ACBDLR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_7_6_MASK)
18722 #define DDRPHY_ACBDLR9_A13BD_MASK                (0x3F00U)
18723 #define DDRPHY_ACBDLR9_A13BD_SHIFT               (8U)
18724 /*! A13BD - Delay select for the BDL on Address A[13].
18725  */
18726 #define DDRPHY_ACBDLR9_A13BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A13BD_SHIFT)) & DDRPHY_ACBDLR9_A13BD_MASK)
18727 #define DDRPHY_ACBDLR9_RESERVED_15_14_MASK       (0xC000U)
18728 #define DDRPHY_ACBDLR9_RESERVED_15_14_SHIFT      (14U)
18729 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18730  */
18731 #define DDRPHY_ACBDLR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_15_14_MASK)
18732 #define DDRPHY_ACBDLR9_A14BD_MASK                (0x3F0000U)
18733 #define DDRPHY_ACBDLR9_A14BD_SHIFT               (16U)
18734 /*! A14BD - Delay select for the BDL on Address A[14].
18735  */
18736 #define DDRPHY_ACBDLR9_A14BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A14BD_SHIFT)) & DDRPHY_ACBDLR9_A14BD_MASK)
18737 #define DDRPHY_ACBDLR9_RESERVED_23_22_MASK       (0xC00000U)
18738 #define DDRPHY_ACBDLR9_RESERVED_23_22_SHIFT      (22U)
18739 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18740  */
18741 #define DDRPHY_ACBDLR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_23_22_MASK)
18742 #define DDRPHY_ACBDLR9_A15BD_MASK                (0x3F000000U)
18743 #define DDRPHY_ACBDLR9_A15BD_SHIFT               (24U)
18744 /*! A15BD - Delay select for the BDL on Address A[15].
18745  */
18746 #define DDRPHY_ACBDLR9_A15BD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A15BD_SHIFT)) & DDRPHY_ACBDLR9_A15BD_MASK)
18747 #define DDRPHY_ACBDLR9_RESERVED_31_30_MASK       (0xC0000000U)
18748 #define DDRPHY_ACBDLR9_RESERVED_31_30_SHIFT      (30U)
18749 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18750  */
18751 #define DDRPHY_ACBDLR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_31_30_MASK)
18752 /*! @} */
18753 
18754 /*! @name ACBDLR10 - AC Bit Delay Line Register 10 */
18755 /*! @{ */
18756 #define DDRPHY_ACBDLR10_RESERVED_7_0_MASK        (0xFFU)
18757 #define DDRPHY_ACBDLR10_RESERVED_7_0_SHIFT       (0U)
18758 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
18759  */
18760 #define DDRPHY_ACBDLR10_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_7_0_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_7_0_MASK)
18761 #define DDRPHY_ACBDLR10_CID0BD_MASK              (0x3F00U)
18762 #define DDRPHY_ACBDLR10_CID0BD_SHIFT             (8U)
18763 /*! CID0BD - Delay select for the BDL on Chip ID CID[0]
18764  */
18765 #define DDRPHY_ACBDLR10_CID0BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_CID0BD_SHIFT)) & DDRPHY_ACBDLR10_CID0BD_MASK)
18766 #define DDRPHY_ACBDLR10_RESERVED_15_14_MASK      (0xC000U)
18767 #define DDRPHY_ACBDLR10_RESERVED_15_14_SHIFT     (14U)
18768 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18769  */
18770 #define DDRPHY_ACBDLR10_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_15_14_MASK)
18771 #define DDRPHY_ACBDLR10_CID1BD_MASK              (0x3F0000U)
18772 #define DDRPHY_ACBDLR10_CID1BD_SHIFT             (16U)
18773 /*! CID1BD - Delay select for the BDL on Chip ID CID[1]
18774  */
18775 #define DDRPHY_ACBDLR10_CID1BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_CID1BD_SHIFT)) & DDRPHY_ACBDLR10_CID1BD_MASK)
18776 #define DDRPHY_ACBDLR10_RESERVED_23_22_MASK      (0xC00000U)
18777 #define DDRPHY_ACBDLR10_RESERVED_23_22_SHIFT     (22U)
18778 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18779  */
18780 #define DDRPHY_ACBDLR10_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_23_22_MASK)
18781 #define DDRPHY_ACBDLR10_CID2BD_MASK              (0x3F000000U)
18782 #define DDRPHY_ACBDLR10_CID2BD_SHIFT             (24U)
18783 /*! CID2BD - Delay select for the BDL on Chip ID CID[2]
18784  */
18785 #define DDRPHY_ACBDLR10_CID2BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_CID2BD_SHIFT)) & DDRPHY_ACBDLR10_CID2BD_MASK)
18786 #define DDRPHY_ACBDLR10_RESERVED_31_30_MASK      (0xC0000000U)
18787 #define DDRPHY_ACBDLR10_RESERVED_31_30_SHIFT     (30U)
18788 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18789  */
18790 #define DDRPHY_ACBDLR10_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_31_30_MASK)
18791 /*! @} */
18792 
18793 /*! @name ACBDLR11 - AC Bit Delay Line Register 11 */
18794 /*! @{ */
18795 #define DDRPHY_ACBDLR11_CS4BD_MASK               (0x3FU)
18796 #define DDRPHY_ACBDLR11_CS4BD_SHIFT              (0U)
18797 /*! CS4BD - Delay select for the BDL on CS[4]
18798  */
18799 #define DDRPHY_ACBDLR11_CS4BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS4BD_SHIFT)) & DDRPHY_ACBDLR11_CS4BD_MASK)
18800 #define DDRPHY_ACBDLR11_RESERVED_7_6_MASK        (0xC0U)
18801 #define DDRPHY_ACBDLR11_RESERVED_7_6_SHIFT       (6U)
18802 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18803  */
18804 #define DDRPHY_ACBDLR11_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_7_6_MASK)
18805 #define DDRPHY_ACBDLR11_CS5BD_MASK               (0x3F00U)
18806 #define DDRPHY_ACBDLR11_CS5BD_SHIFT              (8U)
18807 /*! CS5BD - Delay select for the BDL on CS[5]
18808  */
18809 #define DDRPHY_ACBDLR11_CS5BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS5BD_SHIFT)) & DDRPHY_ACBDLR11_CS5BD_MASK)
18810 #define DDRPHY_ACBDLR11_RESERVED_15_14_MASK      (0xC000U)
18811 #define DDRPHY_ACBDLR11_RESERVED_15_14_SHIFT     (14U)
18812 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18813  */
18814 #define DDRPHY_ACBDLR11_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_15_14_MASK)
18815 #define DDRPHY_ACBDLR11_CS6BD_MASK               (0x3F0000U)
18816 #define DDRPHY_ACBDLR11_CS6BD_SHIFT              (16U)
18817 /*! CS6BD - Delay select for the BDL on CS[6]
18818  */
18819 #define DDRPHY_ACBDLR11_CS6BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS6BD_SHIFT)) & DDRPHY_ACBDLR11_CS6BD_MASK)
18820 #define DDRPHY_ACBDLR11_RESERVED_23_22_MASK      (0xC00000U)
18821 #define DDRPHY_ACBDLR11_RESERVED_23_22_SHIFT     (22U)
18822 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18823  */
18824 #define DDRPHY_ACBDLR11_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_23_22_MASK)
18825 #define DDRPHY_ACBDLR11_CS7BD_MASK               (0x3F000000U)
18826 #define DDRPHY_ACBDLR11_CS7BD_SHIFT              (24U)
18827 /*! CS7BD - Delay select for the BDL on CS[7]
18828  */
18829 #define DDRPHY_ACBDLR11_CS7BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS7BD_SHIFT)) & DDRPHY_ACBDLR11_CS7BD_MASK)
18830 #define DDRPHY_ACBDLR11_RESERVED_31_30_MASK      (0xC0000000U)
18831 #define DDRPHY_ACBDLR11_RESERVED_31_30_SHIFT     (30U)
18832 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18833  */
18834 #define DDRPHY_ACBDLR11_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_31_30_MASK)
18835 /*! @} */
18836 
18837 /*! @name ACBDLR12 - AC Bit Delay Line Register 12 */
18838 /*! @{ */
18839 #define DDRPHY_ACBDLR12_CS8BD_MASK               (0x3FU)
18840 #define DDRPHY_ACBDLR12_CS8BD_SHIFT              (0U)
18841 /*! CS8BD - Delay select for the BDL on CS[8]
18842  */
18843 #define DDRPHY_ACBDLR12_CS8BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS8BD_SHIFT)) & DDRPHY_ACBDLR12_CS8BD_MASK)
18844 #define DDRPHY_ACBDLR12_RESERVED_7_6_MASK        (0xC0U)
18845 #define DDRPHY_ACBDLR12_RESERVED_7_6_SHIFT       (6U)
18846 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18847  */
18848 #define DDRPHY_ACBDLR12_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_7_6_MASK)
18849 #define DDRPHY_ACBDLR12_CS9BD_MASK               (0x3F00U)
18850 #define DDRPHY_ACBDLR12_CS9BD_SHIFT              (8U)
18851 /*! CS9BD - Delay select for the BDL on CS[9]
18852  */
18853 #define DDRPHY_ACBDLR12_CS9BD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS9BD_SHIFT)) & DDRPHY_ACBDLR12_CS9BD_MASK)
18854 #define DDRPHY_ACBDLR12_RESERVED_15_14_MASK      (0xC000U)
18855 #define DDRPHY_ACBDLR12_RESERVED_15_14_SHIFT     (14U)
18856 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18857  */
18858 #define DDRPHY_ACBDLR12_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_15_14_MASK)
18859 #define DDRPHY_ACBDLR12_CS10BD_MASK              (0x3F0000U)
18860 #define DDRPHY_ACBDLR12_CS10BD_SHIFT             (16U)
18861 /*! CS10BD - Delay select for the BDL on CS[10]
18862  */
18863 #define DDRPHY_ACBDLR12_CS10BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS10BD_SHIFT)) & DDRPHY_ACBDLR12_CS10BD_MASK)
18864 #define DDRPHY_ACBDLR12_RESERVED_23_22_MASK      (0xC00000U)
18865 #define DDRPHY_ACBDLR12_RESERVED_23_22_SHIFT     (22U)
18866 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18867  */
18868 #define DDRPHY_ACBDLR12_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_23_22_MASK)
18869 #define DDRPHY_ACBDLR12_CS11BD_MASK              (0x3F000000U)
18870 #define DDRPHY_ACBDLR12_CS11BD_SHIFT             (24U)
18871 /*! CS11BD - Delay select for the BDL on CS[11]
18872  */
18873 #define DDRPHY_ACBDLR12_CS11BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS11BD_SHIFT)) & DDRPHY_ACBDLR12_CS11BD_MASK)
18874 #define DDRPHY_ACBDLR12_RESERVED_31_30_MASK      (0xC0000000U)
18875 #define DDRPHY_ACBDLR12_RESERVED_31_30_SHIFT     (30U)
18876 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18877  */
18878 #define DDRPHY_ACBDLR12_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_31_30_MASK)
18879 /*! @} */
18880 
18881 /*! @name ACBDLR13 - AC Bit Delay Line Register 13 */
18882 /*! @{ */
18883 #define DDRPHY_ACBDLR13_ODT4BD_MASK              (0x3FU)
18884 #define DDRPHY_ACBDLR13_ODT4BD_SHIFT             (0U)
18885 /*! ODT4BD - Delay select for the BDL on ODT[4]
18886  */
18887 #define DDRPHY_ACBDLR13_ODT4BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT4BD_SHIFT)) & DDRPHY_ACBDLR13_ODT4BD_MASK)
18888 #define DDRPHY_ACBDLR13_RESERVED_7_6_MASK        (0xC0U)
18889 #define DDRPHY_ACBDLR13_RESERVED_7_6_SHIFT       (6U)
18890 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18891  */
18892 #define DDRPHY_ACBDLR13_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_7_6_MASK)
18893 #define DDRPHY_ACBDLR13_ODT5BD_MASK              (0x3F00U)
18894 #define DDRPHY_ACBDLR13_ODT5BD_SHIFT             (8U)
18895 /*! ODT5BD - Delay select for the BDL on ODT[5]
18896  */
18897 #define DDRPHY_ACBDLR13_ODT5BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT5BD_SHIFT)) & DDRPHY_ACBDLR13_ODT5BD_MASK)
18898 #define DDRPHY_ACBDLR13_RESERVED_15_14_MASK      (0xC000U)
18899 #define DDRPHY_ACBDLR13_RESERVED_15_14_SHIFT     (14U)
18900 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18901  */
18902 #define DDRPHY_ACBDLR13_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_15_14_MASK)
18903 #define DDRPHY_ACBDLR13_ODT6BD_MASK              (0x3F0000U)
18904 #define DDRPHY_ACBDLR13_ODT6BD_SHIFT             (16U)
18905 /*! ODT6BD - Delay select for the BDL on ODT[6]
18906  */
18907 #define DDRPHY_ACBDLR13_ODT6BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT6BD_SHIFT)) & DDRPHY_ACBDLR13_ODT6BD_MASK)
18908 #define DDRPHY_ACBDLR13_RESERVED_23_22_MASK      (0xC00000U)
18909 #define DDRPHY_ACBDLR13_RESERVED_23_22_SHIFT     (22U)
18910 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18911  */
18912 #define DDRPHY_ACBDLR13_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_23_22_MASK)
18913 #define DDRPHY_ACBDLR13_ODT7BD_MASK              (0x3F000000U)
18914 #define DDRPHY_ACBDLR13_ODT7BD_SHIFT             (24U)
18915 /*! ODT7BD - Delay select for the BDL on ODT[7]
18916  */
18917 #define DDRPHY_ACBDLR13_ODT7BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT7BD_SHIFT)) & DDRPHY_ACBDLR13_ODT7BD_MASK)
18918 #define DDRPHY_ACBDLR13_RESERVED_31_30_MASK      (0xC0000000U)
18919 #define DDRPHY_ACBDLR13_RESERVED_31_30_SHIFT     (30U)
18920 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18921  */
18922 #define DDRPHY_ACBDLR13_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_31_30_MASK)
18923 /*! @} */
18924 
18925 /*! @name ACBDLR14 - AC Bit Delay Line Register 14 */
18926 /*! @{ */
18927 #define DDRPHY_ACBDLR14_CKE4BD_MASK              (0x3FU)
18928 #define DDRPHY_ACBDLR14_CKE4BD_SHIFT             (0U)
18929 /*! CKE4BD - Delay select for the BDL on CKE[4]
18930  */
18931 #define DDRPHY_ACBDLR14_CKE4BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE4BD_SHIFT)) & DDRPHY_ACBDLR14_CKE4BD_MASK)
18932 #define DDRPHY_ACBDLR14_RESERVED_7_6_MASK        (0xC0U)
18933 #define DDRPHY_ACBDLR14_RESERVED_7_6_SHIFT       (6U)
18934 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18935  */
18936 #define DDRPHY_ACBDLR14_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_7_6_MASK)
18937 #define DDRPHY_ACBDLR14_CKE5BD_MASK              (0x3F00U)
18938 #define DDRPHY_ACBDLR14_CKE5BD_SHIFT             (8U)
18939 /*! CKE5BD - Delay select for the BDL on CKE[5]
18940  */
18941 #define DDRPHY_ACBDLR14_CKE5BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE5BD_SHIFT)) & DDRPHY_ACBDLR14_CKE5BD_MASK)
18942 #define DDRPHY_ACBDLR14_RESERVED_15_14_MASK      (0xC000U)
18943 #define DDRPHY_ACBDLR14_RESERVED_15_14_SHIFT     (14U)
18944 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18945  */
18946 #define DDRPHY_ACBDLR14_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_15_14_MASK)
18947 #define DDRPHY_ACBDLR14_CKE6BD_MASK              (0x3F0000U)
18948 #define DDRPHY_ACBDLR14_CKE6BD_SHIFT             (16U)
18949 /*! CKE6BD - Delay select for the BDL on CKE[6]
18950  */
18951 #define DDRPHY_ACBDLR14_CKE6BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE6BD_SHIFT)) & DDRPHY_ACBDLR14_CKE6BD_MASK)
18952 #define DDRPHY_ACBDLR14_RESERVED_23_22_MASK      (0xC00000U)
18953 #define DDRPHY_ACBDLR14_RESERVED_23_22_SHIFT     (22U)
18954 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18955  */
18956 #define DDRPHY_ACBDLR14_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_23_22_MASK)
18957 #define DDRPHY_ACBDLR14_CKE7BD_MASK              (0x3F000000U)
18958 #define DDRPHY_ACBDLR14_CKE7BD_SHIFT             (24U)
18959 /*! CKE7BD - Delay select for the BDL on CKE[7]
18960  */
18961 #define DDRPHY_ACBDLR14_CKE7BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE7BD_SHIFT)) & DDRPHY_ACBDLR14_CKE7BD_MASK)
18962 #define DDRPHY_ACBDLR14_RESERVED_31_30_MASK      (0xC0000000U)
18963 #define DDRPHY_ACBDLR14_RESERVED_31_30_SHIFT     (30U)
18964 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18965  */
18966 #define DDRPHY_ACBDLR14_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_31_30_MASK)
18967 /*! @} */
18968 
18969 /*! @name ACBDLR15 - AC Bit Delay Line Register 15 */
18970 /*! @{ */
18971 #define DDRPHY_ACBDLR15_PDRBD_MASK               (0x3FU)
18972 #define DDRPHY_ACBDLR15_PDRBD_SHIFT              (0U)
18973 /*! PDRBD - Delay select for the BDL on PDR
18974  */
18975 #define DDRPHY_ACBDLR15_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_PDRBD_SHIFT)) & DDRPHY_ACBDLR15_PDRBD_MASK)
18976 #define DDRPHY_ACBDLR15_RESERVED_7_6_MASK        (0xC0U)
18977 #define DDRPHY_ACBDLR15_RESERVED_7_6_SHIFT       (6U)
18978 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18979  */
18980 #define DDRPHY_ACBDLR15_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR15_RESERVED_7_6_MASK)
18981 #define DDRPHY_ACBDLR15_TEBD_MASK                (0x3F00U)
18982 #define DDRPHY_ACBDLR15_TEBD_SHIFT               (8U)
18983 /*! TEBD - Delay select for the BDL on TE
18984  */
18985 #define DDRPHY_ACBDLR15_TEBD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_TEBD_SHIFT)) & DDRPHY_ACBDLR15_TEBD_MASK)
18986 #define DDRPHY_ACBDLR15_RESERVED_15_14_MASK      (0xC000U)
18987 #define DDRPHY_ACBDLR15_RESERVED_15_14_SHIFT     (14U)
18988 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18989  */
18990 #define DDRPHY_ACBDLR15_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR15_RESERVED_15_14_MASK)
18991 #define DDRPHY_ACBDLR15_OEBD_MASK                (0x3F0000U)
18992 #define DDRPHY_ACBDLR15_OEBD_SHIFT               (16U)
18993 /*! OEBD - Delay select for the BDL on OE
18994  */
18995 #define DDRPHY_ACBDLR15_OEBD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_OEBD_SHIFT)) & DDRPHY_ACBDLR15_OEBD_MASK)
18996 #define DDRPHY_ACBDLR15_RESERVED_31_22_MASK      (0xFFC00000U)
18997 #define DDRPHY_ACBDLR15_RESERVED_31_22_SHIFT     (22U)
18998 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
18999  */
19000 #define DDRPHY_ACBDLR15_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_RESERVED_31_22_SHIFT)) & DDRPHY_ACBDLR15_RESERVED_31_22_MASK)
19001 /*! @} */
19002 
19003 /*! @name ACBDLR16 - AC Bit Delay Line Register 16 */
19004 /*! @{ */
19005 #define DDRPHY_ACBDLR16_CKN0BD_MASK              (0x3FU)
19006 #define DDRPHY_ACBDLR16_CKN0BD_SHIFT             (0U)
19007 /*! CKN0BD - Delay select for the BDL on CKN[0]
19008  */
19009 #define DDRPHY_ACBDLR16_CKN0BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN0BD_SHIFT)) & DDRPHY_ACBDLR16_CKN0BD_MASK)
19010 #define DDRPHY_ACBDLR16_RESERVED_7_6_MASK        (0xC0U)
19011 #define DDRPHY_ACBDLR16_RESERVED_7_6_SHIFT       (6U)
19012 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
19013  */
19014 #define DDRPHY_ACBDLR16_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_7_6_MASK)
19015 #define DDRPHY_ACBDLR16_CKN1BD_MASK              (0x3F00U)
19016 #define DDRPHY_ACBDLR16_CKN1BD_SHIFT             (8U)
19017 /*! CKN1BD - Delay select for the BDL on CKN[1]
19018  */
19019 #define DDRPHY_ACBDLR16_CKN1BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN1BD_SHIFT)) & DDRPHY_ACBDLR16_CKN1BD_MASK)
19020 #define DDRPHY_ACBDLR16_RESERVED_15_14_MASK      (0xC000U)
19021 #define DDRPHY_ACBDLR16_RESERVED_15_14_SHIFT     (14U)
19022 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
19023  */
19024 #define DDRPHY_ACBDLR16_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_15_14_MASK)
19025 #define DDRPHY_ACBDLR16_CKN2BD_MASK              (0x3F0000U)
19026 #define DDRPHY_ACBDLR16_CKN2BD_SHIFT             (16U)
19027 /*! CKN2BD - Delay select for the BDL on CKN[2]
19028  */
19029 #define DDRPHY_ACBDLR16_CKN2BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN2BD_SHIFT)) & DDRPHY_ACBDLR16_CKN2BD_MASK)
19030 #define DDRPHY_ACBDLR16_RESERVED_23_22_MASK      (0xC00000U)
19031 #define DDRPHY_ACBDLR16_RESERVED_23_22_SHIFT     (22U)
19032 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
19033  */
19034 #define DDRPHY_ACBDLR16_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_23_22_MASK)
19035 #define DDRPHY_ACBDLR16_CKN3BD_MASK              (0x3F000000U)
19036 #define DDRPHY_ACBDLR16_CKN3BD_SHIFT             (24U)
19037 /*! CKN3BD - Delay select for the BDL on CKN[3]
19038  */
19039 #define DDRPHY_ACBDLR16_CKN3BD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN3BD_SHIFT)) & DDRPHY_ACBDLR16_CKN3BD_MASK)
19040 #define DDRPHY_ACBDLR16_RESERVED_31_30_MASK      (0xC0000000U)
19041 #define DDRPHY_ACBDLR16_RESERVED_31_30_SHIFT     (30U)
19042 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
19043  */
19044 #define DDRPHY_ACBDLR16_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_31_30_MASK)
19045 /*! @} */
19046 
19047 /*! @name ACLCDLR - AC Local Calibrated Delay Line Register */
19048 /*! @{ */
19049 #define DDRPHY_ACLCDLR_ACD_MASK                  (0x1FFU)
19050 #define DDRPHY_ACLCDLR_ACD_SHIFT                 (0U)
19051 /*! ACD - Address/Command Delay for AC Macro 0
19052  */
19053 #define DDRPHY_ACLCDLR_ACD(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_ACD_SHIFT)) & DDRPHY_ACLCDLR_ACD_MASK)
19054 #define DDRPHY_ACLCDLR_RESERVED_15_9_MASK        (0xFE00U)
19055 #define DDRPHY_ACLCDLR_RESERVED_15_9_SHIFT       (9U)
19056 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
19057  */
19058 #define DDRPHY_ACLCDLR_RESERVED_15_9(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_RESERVED_15_9_SHIFT)) & DDRPHY_ACLCDLR_RESERVED_15_9_MASK)
19059 #define DDRPHY_ACLCDLR_ACD1_MASK                 (0x1FF0000U)
19060 #define DDRPHY_ACLCDLR_ACD1_SHIFT                (16U)
19061 /*! ACD1 - Address/Command Delay for AC Macro 1
19062  */
19063 #define DDRPHY_ACLCDLR_ACD1(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_ACD1_SHIFT)) & DDRPHY_ACLCDLR_ACD1_MASK)
19064 #define DDRPHY_ACLCDLR_RESERVED_31_25_MASK       (0xFE000000U)
19065 #define DDRPHY_ACLCDLR_RESERVED_31_25_SHIFT      (25U)
19066 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
19067  */
19068 #define DDRPHY_ACLCDLR_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_RESERVED_31_25_SHIFT)) & DDRPHY_ACLCDLR_RESERVED_31_25_MASK)
19069 /*! @} */
19070 
19071 /*! @name ACMDLR0 - AC Master Delay Line Register 0 */
19072 /*! @{ */
19073 #define DDRPHY_ACMDLR0_IPRD_MASK                 (0x1FFU)
19074 #define DDRPHY_ACMDLR0_IPRD_SHIFT                (0U)
19075 /*! IPRD - Initial Period
19076  */
19077 #define DDRPHY_ACMDLR0_IPRD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_IPRD_SHIFT)) & DDRPHY_ACMDLR0_IPRD_MASK)
19078 #define DDRPHY_ACMDLR0_RESERVED_15_9_MASK        (0xFE00U)
19079 #define DDRPHY_ACMDLR0_RESERVED_15_9_SHIFT       (9U)
19080 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
19081  */
19082 #define DDRPHY_ACMDLR0_RESERVED_15_9(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_ACMDLR0_RESERVED_15_9_MASK)
19083 #define DDRPHY_ACMDLR0_TPRD_MASK                 (0x1FF0000U)
19084 #define DDRPHY_ACMDLR0_TPRD_SHIFT                (16U)
19085 /*! TPRD - Target Period
19086  */
19087 #define DDRPHY_ACMDLR0_TPRD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_TPRD_SHIFT)) & DDRPHY_ACMDLR0_TPRD_MASK)
19088 #define DDRPHY_ACMDLR0_RESERVED_31_25_MASK       (0xFE000000U)
19089 #define DDRPHY_ACMDLR0_RESERVED_31_25_SHIFT      (25U)
19090 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
19091  */
19092 #define DDRPHY_ACMDLR0_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_ACMDLR0_RESERVED_31_25_MASK)
19093 /*! @} */
19094 
19095 /*! @name ACMDLR1 - AC Master Delay Line Register 1 */
19096 /*! @{ */
19097 #define DDRPHY_ACMDLR1_MDLD_MASK                 (0x1FFU)
19098 #define DDRPHY_ACMDLR1_MDLD_SHIFT                (0U)
19099 /*! MDLD - MDL Delay for AC Macro 0
19100  */
19101 #define DDRPHY_ACMDLR1_MDLD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_MDLD_SHIFT)) & DDRPHY_ACMDLR1_MDLD_MASK)
19102 #define DDRPHY_ACMDLR1_RESERVED_15_9_MASK        (0xFE00U)
19103 #define DDRPHY_ACMDLR1_RESERVED_15_9_SHIFT       (9U)
19104 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
19105  */
19106 #define DDRPHY_ACMDLR1_RESERVED_15_9(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_ACMDLR1_RESERVED_15_9_MASK)
19107 #define DDRPHY_ACMDLR1_MDLD1_MASK                (0x1FF0000U)
19108 #define DDRPHY_ACMDLR1_MDLD1_SHIFT               (16U)
19109 /*! MDLD1 - MDL Delay for AC Macro 1
19110  */
19111 #define DDRPHY_ACMDLR1_MDLD1(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_MDLD1_SHIFT)) & DDRPHY_ACMDLR1_MDLD1_MASK)
19112 #define DDRPHY_ACMDLR1_RESERVED_31_25_MASK       (0xFE000000U)
19113 #define DDRPHY_ACMDLR1_RESERVED_31_25_SHIFT      (25U)
19114 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
19115  */
19116 #define DDRPHY_ACMDLR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_ACMDLR1_RESERVED_31_25_MASK)
19117 /*! @} */
19118 
19119 /*! @name ZQCR - ZQ Impedance Control Register */
19120 /*! @{ */
19121 #define DDRPHY_ZQCR_ZQPD_MASK                    (0x1U)
19122 #define DDRPHY_ZQCR_ZQPD_SHIFT                   (0U)
19123 /*! ZQPD - ZQ Power Down
19124  */
19125 #define DDRPHY_ZQCR_ZQPD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQPD_SHIFT)) & DDRPHY_ZQCR_ZQPD_MASK)
19126 #define DDRPHY_ZQCR_ZCALT_MASK                   (0x2U)
19127 #define DDRPHY_ZQCR_ZCALT_SHIFT                  (1U)
19128 /*! ZCALT - ZQ Calibration Type
19129  */
19130 #define DDRPHY_ZQCR_ZCALT(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZCALT_SHIFT)) & DDRPHY_ZQCR_ZCALT_MASK)
19131 #define DDRPHY_ZQCR_AVGMAX_MASK                  (0xCU)
19132 #define DDRPHY_ZQCR_AVGMAX_SHIFT                 (2U)
19133 /*! AVGMAX - Maximum number of averaging rounds to be used by averaging algorithm
19134  */
19135 #define DDRPHY_ZQCR_AVGMAX(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_AVGMAX_SHIFT)) & DDRPHY_ZQCR_AVGMAX_MASK)
19136 #define DDRPHY_ZQCR_AVGEN_MASK                   (0x10U)
19137 #define DDRPHY_ZQCR_AVGEN_SHIFT                  (4U)
19138 /*! AVGEN - Averaging algorithm enable, if set, enables averaging algorithm
19139  */
19140 #define DDRPHY_ZQCR_AVGEN(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_AVGEN_SHIFT)) & DDRPHY_ZQCR_AVGEN_MASK)
19141 #define DDRPHY_ZQCR_IODLMT_MASK                  (0xE0U)
19142 #define DDRPHY_ZQCR_IODLMT_SHIFT                 (5U)
19143 /*! IODLMT - IO VT Drift Limit
19144  */
19145 #define DDRPHY_ZQCR_IODLMT(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_IODLMT_SHIFT)) & DDRPHY_ZQCR_IODLMT_MASK)
19146 #define DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK    (0x100U)
19147 #define DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT   (8U)
19148 /*! FORCE_ZCAL_VT_UPDATE - Force ZCAL VT update
19149  */
19150 #define DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT)) & DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK)
19151 #define DDRPHY_ZQCR_ODT_MODE_MASK                (0x600U)
19152 #define DDRPHY_ZQCR_ODT_MODE_SHIFT               (9U)
19153 /*! ODT_MODE - Choice of termination mode
19154  */
19155 #define DDRPHY_ZQCR_ODT_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ODT_MODE_SHIFT)) & DDRPHY_ZQCR_ODT_MODE_MASK)
19156 #define DDRPHY_ZQCR_ZQREFIEN_MASK                (0x800U)
19157 #define DDRPHY_ZQCR_ZQREFIEN_SHIFT               (11U)
19158 /*! ZQREFIEN - ZQ Internal VREF Enable
19159  */
19160 #define DDRPHY_ZQCR_ZQREFIEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQREFIEN_SHIFT)) & DDRPHY_ZQCR_ZQREFIEN_MASK)
19161 #define DDRPHY_ZQCR_ZQREFPEN_MASK                (0x1000U)
19162 #define DDRPHY_ZQCR_ZQREFPEN_SHIFT               (12U)
19163 /*! ZQREFPEN - ZQ VREF Pad Enable
19164  */
19165 #define DDRPHY_ZQCR_ZQREFPEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQREFPEN_SHIFT)) & DDRPHY_ZQCR_ZQREFPEN_MASK)
19166 #define DDRPHY_ZQCR_PGWAIT_FRQA_MASK             (0x7E000U)
19167 #define DDRPHY_ZQCR_PGWAIT_FRQA_SHIFT            (13U)
19168 /*! PGWAIT_FRQA - Programmable Wait for Frequency A
19169  */
19170 #define DDRPHY_ZQCR_PGWAIT_FRQA(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_PGWAIT_FRQA_SHIFT)) & DDRPHY_ZQCR_PGWAIT_FRQA_MASK)
19171 #define DDRPHY_ZQCR_PGWAIT_FRQB_MASK             (0x1F80000U)
19172 #define DDRPHY_ZQCR_PGWAIT_FRQB_SHIFT            (19U)
19173 /*! PGWAIT_FRQB - Programmable Wait for Frequency B
19174  */
19175 #define DDRPHY_ZQCR_PGWAIT_FRQB(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_PGWAIT_FRQB_SHIFT)) & DDRPHY_ZQCR_PGWAIT_FRQB_MASK)
19176 #define DDRPHY_ZQCR_ZQREFISELRANGE_MASK          (0x2000000U)
19177 #define DDRPHY_ZQCR_ZQREFISELRANGE_SHIFT         (25U)
19178 /*! ZQREFISELRANGE - ZQ VREF Range
19179  */
19180 #define DDRPHY_ZQCR_ZQREFISELRANGE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQREFISELRANGE_SHIFT)) & DDRPHY_ZQCR_ZQREFISELRANGE_MASK)
19181 #define DDRPHY_ZQCR_RESERVED_31_26_MASK          (0xFC000000U)
19182 #define DDRPHY_ZQCR_RESERVED_31_26_SHIFT         (26U)
19183 /*! RESERVED_31_26 - Reserved. Return zeroes on reads.
19184  */
19185 #define DDRPHY_ZQCR_RESERVED_31_26(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_RESERVED_31_26_SHIFT)) & DDRPHY_ZQCR_RESERVED_31_26_MASK)
19186 /*! @} */
19187 
19188 /*! @name ZQ0PR0 - ZQ n Impedance Control Program Register 0 */
19189 /*! @{ */
19190 #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK     (0xFU)
19191 #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT    (0U)
19192 /*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
19193  */
19194 #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK)
19195 #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK     (0xF0U)
19196 #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT    (4U)
19197 /*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
19198  */
19199 #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK)
19200 #define DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_MASK        (0xF00U)
19201 #define DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT       (8U)
19202 /*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio
19203  */
19204 #define DDRPHY_ZQ0PR0_ZPROG_HOST_ODT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_MASK)
19205 #define DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK        (0xF000U)
19206 #define DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT       (12U)
19207 /*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio
19208  */
19209 #define DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK)
19210 #define DDRPHY_ZQ0PR0_PU_DRV_ADJUST_MASK         (0x70000U)
19211 #define DDRPHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT        (16U)
19212 /*! PU_DRV_ADJUST - Pullup drive strength adjustment
19213  */
19214 #define DDRPHY_ZQ0PR0_PU_DRV_ADJUST(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ0PR0_PU_DRV_ADJUST_MASK)
19215 #define DDRPHY_ZQ0PR0_PD_DRV_ADJUST_MASK         (0x380000U)
19216 #define DDRPHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT        (19U)
19217 /*! PD_DRV_ADJUST - Pulldown drive strength adjustment
19218  */
19219 #define DDRPHY_ZQ0PR0_PD_DRV_ADJUST(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ0PR0_PD_DRV_ADJUST_MASK)
19220 #define DDRPHY_ZQ0PR0_ODT_ADJUST_MASK            (0x1C00000U)
19221 #define DDRPHY_ZQ0PR0_ODT_ADJUST_SHIFT           (22U)
19222 /*! ODT_ADJUST - Termination adjustment
19223  */
19224 #define DDRPHY_ZQ0PR0_ODT_ADJUST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ0PR0_ODT_ADJUST_MASK)
19225 #define DDRPHY_ZQ0PR0_ZLE_MODE_MASK              (0x6000000U)
19226 #define DDRPHY_ZQ0PR0_ZLE_MODE_SHIFT             (25U)
19227 /*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
19228  */
19229 #define DDRPHY_ZQ0PR0_ZLE_MODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ0PR0_ZLE_MODE_MASK)
19230 #define DDRPHY_ZQ0PR0_ZSEGBYP_MASK               (0x8000000U)
19231 #define DDRPHY_ZQ0PR0_ZSEGBYP_SHIFT              (27U)
19232 /*! ZSEGBYP - Calibration segment bypass
19233  */
19234 #define DDRPHY_ZQ0PR0_ZSEGBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ0PR0_ZSEGBYP_MASK)
19235 #define DDRPHY_ZQ0PR0_PU_ODT_ZDEN_MASK           (0x10000000U)
19236 #define DDRPHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT          (28U)
19237 /*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable
19238  */
19239 #define DDRPHY_ZQ0PR0_PU_ODT_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PU_ODT_ZDEN_MASK)
19240 #define DDRPHY_ZQ0PR0_PD_ODT_ZDEN_MASK           (0x20000000U)
19241 #define DDRPHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT          (29U)
19242 /*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable
19243  */
19244 #define DDRPHY_ZQ0PR0_PD_ODT_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PD_ODT_ZDEN_MASK)
19245 #define DDRPHY_ZQ0PR0_PU_DRV_ZDEN_MASK           (0x40000000U)
19246 #define DDRPHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT          (30U)
19247 /*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable
19248  */
19249 #define DDRPHY_ZQ0PR0_PU_DRV_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PU_DRV_ZDEN_MASK)
19250 #define DDRPHY_ZQ0PR0_PD_DRV_ZDEN_MASK           (0x80000000U)
19251 #define DDRPHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT          (31U)
19252 /*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable
19253  */
19254 #define DDRPHY_ZQ0PR0_PD_DRV_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PD_DRV_ZDEN_MASK)
19255 /*! @} */
19256 
19257 /*! @name ZQ0PR1 - ZQ n Impedance Control Program Register 1 */
19258 /*! @{ */
19259 #define DDRPHY_ZQ0PR1_PD_REFSEL_MASK             (0x7FU)
19260 #define DDRPHY_ZQ0PR1_PD_REFSEL_SHIFT            (0U)
19261 /*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell
19262  */
19263 #define DDRPHY_ZQ0PR1_PD_REFSEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ0PR1_PD_REFSEL_MASK)
19264 #define DDRPHY_ZQ0PR1_RESERVED_7_MASK            (0x80U)
19265 #define DDRPHY_ZQ0PR1_RESERVED_7_SHIFT           (7U)
19266 /*! RESERVED_7 - Reserved. Return zeros on reads.
19267  */
19268 #define DDRPHY_ZQ0PR1_RESERVED_7(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ0PR1_RESERVED_7_MASK)
19269 #define DDRPHY_ZQ0PR1_PU_REFSEL_MASK             (0x7F00U)
19270 #define DDRPHY_ZQ0PR1_PU_REFSEL_SHIFT            (8U)
19271 /*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell
19272  */
19273 #define DDRPHY_ZQ0PR1_PU_REFSEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ0PR1_PU_REFSEL_MASK)
19274 #define DDRPHY_ZQ0PR1_RESERVED_31_15_MASK        (0xFFFF8000U)
19275 #define DDRPHY_ZQ0PR1_RESERVED_31_15_SHIFT       (15U)
19276 /*! RESERVED_31_15 - Reserved. Return zeros on reads.
19277  */
19278 #define DDRPHY_ZQ0PR1_RESERVED_31_15(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ0PR1_RESERVED_31_15_MASK)
19279 /*! @} */
19280 
19281 /*! @name ZQ0DR0 - ZQ n Impedance Control Data Register 0 */
19282 /*! @{ */
19283 #define DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_MASK   (0x3FFU)
19284 #define DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_SHIFT  (0U)
19285 /*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result
19286  */
19287 #define DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_MASK)
19288 #define DDRPHY_ZQ0DR0_RESERVED_15_10_MASK        (0xFC00U)
19289 #define DDRPHY_ZQ0DR0_RESERVED_15_10_SHIFT       (10U)
19290 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19291  */
19292 #define DDRPHY_ZQ0DR0_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0DR0_RESERVED_15_10_MASK)
19293 #define DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_MASK   (0x3FF0000U)
19294 #define DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_SHIFT  (16U)
19295 /*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result
19296  */
19297 #define DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_MASK)
19298 #define DDRPHY_ZQ0DR0_RESERVED_31_26_MASK        (0xFC000000U)
19299 #define DDRPHY_ZQ0DR0_RESERVED_31_26_SHIFT       (26U)
19300 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19301  */
19302 #define DDRPHY_ZQ0DR0_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0DR0_RESERVED_31_26_MASK)
19303 /*! @} */
19304 
19305 /*! @name ZQ0DR1 - ZQ n Impedance Control Data Register 1 */
19306 /*! @{ */
19307 #define DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_MASK   (0x3FFU)
19308 #define DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_SHIFT  (0U)
19309 /*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result
19310  */
19311 #define DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_MASK)
19312 #define DDRPHY_ZQ0DR1_RESERVED_15_10_MASK        (0xFC00U)
19313 #define DDRPHY_ZQ0DR1_RESERVED_15_10_SHIFT       (10U)
19314 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19315  */
19316 #define DDRPHY_ZQ0DR1_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0DR1_RESERVED_15_10_MASK)
19317 #define DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_MASK   (0x3FF0000U)
19318 #define DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_SHIFT  (16U)
19319 /*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result
19320  */
19321 #define DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_MASK)
19322 #define DDRPHY_ZQ0DR1_RESERVED_31_26_MASK        (0xFC000000U)
19323 #define DDRPHY_ZQ0DR1_RESERVED_31_26_SHIFT       (26U)
19324 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19325  */
19326 #define DDRPHY_ZQ0DR1_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0DR1_RESERVED_31_26_MASK)
19327 /*! @} */
19328 
19329 /*! @name ZQ0OR0 - ZQ n Impedance Control Override Data Register 0 */
19330 /*! @{ */
19331 #define DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK     (0x3FFU)
19332 #define DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT    (0U)
19333 /*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance
19334  */
19335 #define DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK)
19336 #define DDRPHY_ZQ0OR0_RESERVED_15_10_MASK        (0xFC00U)
19337 #define DDRPHY_ZQ0OR0_RESERVED_15_10_SHIFT       (10U)
19338 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19339  */
19340 #define DDRPHY_ZQ0OR0_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0OR0_RESERVED_15_10_MASK)
19341 #define DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK     (0x3FF0000U)
19342 #define DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT    (16U)
19343 /*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance
19344  */
19345 #define DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK)
19346 #define DDRPHY_ZQ0OR0_RESERVED_31_26_MASK        (0xFC000000U)
19347 #define DDRPHY_ZQ0OR0_RESERVED_31_26_SHIFT       (26U)
19348 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19349  */
19350 #define DDRPHY_ZQ0OR0_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0OR0_RESERVED_31_26_MASK)
19351 /*! @} */
19352 
19353 /*! @name ZQ0OR1 - ZQ n Impedance Control Override Data Register 1 */
19354 /*! @{ */
19355 #define DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK     (0x3FFU)
19356 #define DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT    (0U)
19357 /*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination
19358  */
19359 #define DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK)
19360 #define DDRPHY_ZQ0OR1_RESERVED_15_10_MASK        (0xFC00U)
19361 #define DDRPHY_ZQ0OR1_RESERVED_15_10_SHIFT       (10U)
19362 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19363  */
19364 #define DDRPHY_ZQ0OR1_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0OR1_RESERVED_15_10_MASK)
19365 #define DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK     (0x3FF0000U)
19366 #define DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT    (16U)
19367 /*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination
19368  */
19369 #define DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK)
19370 #define DDRPHY_ZQ0OR1_RESERVED_31_26_MASK        (0xFC000000U)
19371 #define DDRPHY_ZQ0OR1_RESERVED_31_26_SHIFT       (26U)
19372 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19373  */
19374 #define DDRPHY_ZQ0OR1_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0OR1_RESERVED_31_26_MASK)
19375 /*! @} */
19376 
19377 /*! @name ZQ0SR - ZQ n Impedance Control Status Register */
19378 /*! @{ */
19379 #define DDRPHY_ZQ0SR_ZPD_MASK                    (0x3U)
19380 #define DDRPHY_ZQ0SR_ZPD_SHIFT                   (0U)
19381 /*! ZPD - Output impedance pull-down calibration status
19382  */
19383 #define DDRPHY_ZQ0SR_ZPD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZPD_SHIFT)) & DDRPHY_ZQ0SR_ZPD_MASK)
19384 #define DDRPHY_ZQ0SR_ZPU_MASK                    (0xCU)
19385 #define DDRPHY_ZQ0SR_ZPU_SHIFT                   (2U)
19386 /*! ZPU - Output impedance pull-up calibration status
19387  */
19388 #define DDRPHY_ZQ0SR_ZPU(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZPU_SHIFT)) & DDRPHY_ZQ0SR_ZPU_MASK)
19389 #define DDRPHY_ZQ0SR_OPD_MASK                    (0x30U)
19390 #define DDRPHY_ZQ0SR_OPD_SHIFT                   (4U)
19391 /*! OPD - On-die termination (ODT) pull-down calibration status
19392  */
19393 #define DDRPHY_ZQ0SR_OPD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_OPD_SHIFT)) & DDRPHY_ZQ0SR_OPD_MASK)
19394 #define DDRPHY_ZQ0SR_OPU_MASK                    (0xC0U)
19395 #define DDRPHY_ZQ0SR_OPU_SHIFT                   (6U)
19396 /*! OPU - On-die termination (ODT) pull-up calibration status
19397  */
19398 #define DDRPHY_ZQ0SR_OPU(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_OPU_SHIFT)) & DDRPHY_ZQ0SR_OPU_MASK)
19399 #define DDRPHY_ZQ0SR_ZERR_MASK                   (0x100U)
19400 #define DDRPHY_ZQ0SR_ZERR_SHIFT                  (8U)
19401 /*! ZERR - Impedance Calibration Error
19402  */
19403 #define DDRPHY_ZQ0SR_ZERR(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZERR_SHIFT)) & DDRPHY_ZQ0SR_ZERR_MASK)
19404 #define DDRPHY_ZQ0SR_ZDONE_MASK                  (0x200U)
19405 #define DDRPHY_ZQ0SR_ZDONE_SHIFT                 (9U)
19406 /*! ZDONE - Impedance Calibration Done
19407  */
19408 #define DDRPHY_ZQ0SR_ZDONE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZDONE_SHIFT)) & DDRPHY_ZQ0SR_ZDONE_MASK)
19409 #define DDRPHY_ZQ0SR_PU_DRV_SAT_MASK             (0x400U)
19410 #define DDRPHY_ZQ0SR_PU_DRV_SAT_SHIFT            (10U)
19411 /*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19412  */
19413 #define DDRPHY_ZQ0SR_PU_DRV_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ0SR_PU_DRV_SAT_MASK)
19414 #define DDRPHY_ZQ0SR_PD_DRV_SAT_MASK             (0x800U)
19415 #define DDRPHY_ZQ0SR_PD_DRV_SAT_SHIFT            (11U)
19416 /*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19417  */
19418 #define DDRPHY_ZQ0SR_PD_DRV_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ0SR_PD_DRV_SAT_MASK)
19419 #define DDRPHY_ZQ0SR_PU_ODT_SAT_MASK             (0x1000U)
19420 #define DDRPHY_ZQ0SR_PU_ODT_SAT_SHIFT            (12U)
19421 /*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19422  */
19423 #define DDRPHY_ZQ0SR_PU_ODT_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ0SR_PU_ODT_SAT_MASK)
19424 #define DDRPHY_ZQ0SR_PD_ODT_SAT_MASK             (0x2000U)
19425 #define DDRPHY_ZQ0SR_PD_ODT_SAT_SHIFT            (13U)
19426 /*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19427  */
19428 #define DDRPHY_ZQ0SR_PD_ODT_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ0SR_PD_ODT_SAT_MASK)
19429 #define DDRPHY_ZQ0SR_RESERVED_31_14_MASK         (0xFFFFC000U)
19430 #define DDRPHY_ZQ0SR_RESERVED_31_14_SHIFT        (14U)
19431 /*! RESERVED_31_14 - Reserved. Return zeros on reads.
19432  */
19433 #define DDRPHY_ZQ0SR_RESERVED_31_14(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ0SR_RESERVED_31_14_MASK)
19434 /*! @} */
19435 
19436 /*! @name ZQ1PR0 - ZQ n Impedance Control Program Register 0 */
19437 /*! @{ */
19438 #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK     (0xFU)
19439 #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT    (0U)
19440 /*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
19441  */
19442 #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK)
19443 #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK     (0xF0U)
19444 #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT    (4U)
19445 /*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
19446  */
19447 #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK)
19448 #define DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_MASK        (0xF00U)
19449 #define DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT       (8U)
19450 /*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio
19451  */
19452 #define DDRPHY_ZQ1PR0_ZPROG_HOST_ODT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_MASK)
19453 #define DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK        (0xF000U)
19454 #define DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT       (12U)
19455 /*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio
19456  */
19457 #define DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK)
19458 #define DDRPHY_ZQ1PR0_PU_DRV_ADJUST_MASK         (0x70000U)
19459 #define DDRPHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT        (16U)
19460 /*! PU_DRV_ADJUST - Pullup drive strength adjustment
19461  */
19462 #define DDRPHY_ZQ1PR0_PU_DRV_ADJUST(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ1PR0_PU_DRV_ADJUST_MASK)
19463 #define DDRPHY_ZQ1PR0_PD_DRV_ADJUST_MASK         (0x380000U)
19464 #define DDRPHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT        (19U)
19465 /*! PD_DRV_ADJUST - Pulldown drive strength adjustment
19466  */
19467 #define DDRPHY_ZQ1PR0_PD_DRV_ADJUST(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ1PR0_PD_DRV_ADJUST_MASK)
19468 #define DDRPHY_ZQ1PR0_ODT_ADJUST_MASK            (0x1C00000U)
19469 #define DDRPHY_ZQ1PR0_ODT_ADJUST_SHIFT           (22U)
19470 /*! ODT_ADJUST - Termination adjustment
19471  */
19472 #define DDRPHY_ZQ1PR0_ODT_ADJUST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ1PR0_ODT_ADJUST_MASK)
19473 #define DDRPHY_ZQ1PR0_ZLE_MODE_MASK              (0x6000000U)
19474 #define DDRPHY_ZQ1PR0_ZLE_MODE_SHIFT             (25U)
19475 /*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
19476  */
19477 #define DDRPHY_ZQ1PR0_ZLE_MODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ1PR0_ZLE_MODE_MASK)
19478 #define DDRPHY_ZQ1PR0_ZSEGBYP_MASK               (0x8000000U)
19479 #define DDRPHY_ZQ1PR0_ZSEGBYP_SHIFT              (27U)
19480 /*! ZSEGBYP - Calibration segment bypass
19481  */
19482 #define DDRPHY_ZQ1PR0_ZSEGBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ1PR0_ZSEGBYP_MASK)
19483 #define DDRPHY_ZQ1PR0_PU_ODT_ZDEN_MASK           (0x10000000U)
19484 #define DDRPHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT          (28U)
19485 /*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable
19486  */
19487 #define DDRPHY_ZQ1PR0_PU_ODT_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PU_ODT_ZDEN_MASK)
19488 #define DDRPHY_ZQ1PR0_PD_ODT_ZDEN_MASK           (0x20000000U)
19489 #define DDRPHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT          (29U)
19490 /*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable
19491  */
19492 #define DDRPHY_ZQ1PR0_PD_ODT_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PD_ODT_ZDEN_MASK)
19493 #define DDRPHY_ZQ1PR0_PU_DRV_ZDEN_MASK           (0x40000000U)
19494 #define DDRPHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT          (30U)
19495 /*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable
19496  */
19497 #define DDRPHY_ZQ1PR0_PU_DRV_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PU_DRV_ZDEN_MASK)
19498 #define DDRPHY_ZQ1PR0_PD_DRV_ZDEN_MASK           (0x80000000U)
19499 #define DDRPHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT          (31U)
19500 /*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable
19501  */
19502 #define DDRPHY_ZQ1PR0_PD_DRV_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PD_DRV_ZDEN_MASK)
19503 /*! @} */
19504 
19505 /*! @name ZQ1PR1 - ZQ n Impedance Control Program Register 1 */
19506 /*! @{ */
19507 #define DDRPHY_ZQ1PR1_PD_REFSEL_MASK             (0x7FU)
19508 #define DDRPHY_ZQ1PR1_PD_REFSEL_SHIFT            (0U)
19509 /*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell
19510  */
19511 #define DDRPHY_ZQ1PR1_PD_REFSEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ1PR1_PD_REFSEL_MASK)
19512 #define DDRPHY_ZQ1PR1_RESERVED_7_MASK            (0x80U)
19513 #define DDRPHY_ZQ1PR1_RESERVED_7_SHIFT           (7U)
19514 /*! RESERVED_7 - Reserved. Return zeros on reads.
19515  */
19516 #define DDRPHY_ZQ1PR1_RESERVED_7(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ1PR1_RESERVED_7_MASK)
19517 #define DDRPHY_ZQ1PR1_PU_REFSEL_MASK             (0x7F00U)
19518 #define DDRPHY_ZQ1PR1_PU_REFSEL_SHIFT            (8U)
19519 /*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell
19520  */
19521 #define DDRPHY_ZQ1PR1_PU_REFSEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ1PR1_PU_REFSEL_MASK)
19522 #define DDRPHY_ZQ1PR1_RESERVED_31_15_MASK        (0xFFFF8000U)
19523 #define DDRPHY_ZQ1PR1_RESERVED_31_15_SHIFT       (15U)
19524 /*! RESERVED_31_15 - Reserved. Return zeros on reads.
19525  */
19526 #define DDRPHY_ZQ1PR1_RESERVED_31_15(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ1PR1_RESERVED_31_15_MASK)
19527 /*! @} */
19528 
19529 /*! @name ZQ1DR0 - ZQ n Impedance Control Data Register 0 */
19530 /*! @{ */
19531 #define DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_MASK   (0x3FFU)
19532 #define DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_SHIFT  (0U)
19533 /*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result
19534  */
19535 #define DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_MASK)
19536 #define DDRPHY_ZQ1DR0_RESERVED_15_10_MASK        (0xFC00U)
19537 #define DDRPHY_ZQ1DR0_RESERVED_15_10_SHIFT       (10U)
19538 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19539  */
19540 #define DDRPHY_ZQ1DR0_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1DR0_RESERVED_15_10_MASK)
19541 #define DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_MASK   (0x3FF0000U)
19542 #define DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_SHIFT  (16U)
19543 /*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result
19544  */
19545 #define DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_MASK)
19546 #define DDRPHY_ZQ1DR0_RESERVED_31_26_MASK        (0xFC000000U)
19547 #define DDRPHY_ZQ1DR0_RESERVED_31_26_SHIFT       (26U)
19548 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19549  */
19550 #define DDRPHY_ZQ1DR0_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1DR0_RESERVED_31_26_MASK)
19551 /*! @} */
19552 
19553 /*! @name ZQ1DR1 - ZQ n Impedance Control Data Register 1 */
19554 /*! @{ */
19555 #define DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_MASK   (0x3FFU)
19556 #define DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_SHIFT  (0U)
19557 /*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result
19558  */
19559 #define DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_MASK)
19560 #define DDRPHY_ZQ1DR1_RESERVED_15_10_MASK        (0xFC00U)
19561 #define DDRPHY_ZQ1DR1_RESERVED_15_10_SHIFT       (10U)
19562 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19563  */
19564 #define DDRPHY_ZQ1DR1_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1DR1_RESERVED_15_10_MASK)
19565 #define DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_MASK   (0x3FF0000U)
19566 #define DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_SHIFT  (16U)
19567 /*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result
19568  */
19569 #define DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_MASK)
19570 #define DDRPHY_ZQ1DR1_RESERVED_31_26_MASK        (0xFC000000U)
19571 #define DDRPHY_ZQ1DR1_RESERVED_31_26_SHIFT       (26U)
19572 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19573  */
19574 #define DDRPHY_ZQ1DR1_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1DR1_RESERVED_31_26_MASK)
19575 /*! @} */
19576 
19577 /*! @name ZQ1OR0 - ZQ n Impedance Control Override Data Register 0 */
19578 /*! @{ */
19579 #define DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_MASK     (0x3FFU)
19580 #define DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_SHIFT    (0U)
19581 /*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance
19582  */
19583 #define DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_MASK)
19584 #define DDRPHY_ZQ1OR0_RESERVED_15_10_MASK        (0xFC00U)
19585 #define DDRPHY_ZQ1OR0_RESERVED_15_10_SHIFT       (10U)
19586 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19587  */
19588 #define DDRPHY_ZQ1OR0_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1OR0_RESERVED_15_10_MASK)
19589 #define DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_MASK     (0x3FF0000U)
19590 #define DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_SHIFT    (16U)
19591 /*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance
19592  */
19593 #define DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_MASK)
19594 #define DDRPHY_ZQ1OR0_RESERVED_31_26_MASK        (0xFC000000U)
19595 #define DDRPHY_ZQ1OR0_RESERVED_31_26_SHIFT       (26U)
19596 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19597  */
19598 #define DDRPHY_ZQ1OR0_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1OR0_RESERVED_31_26_MASK)
19599 /*! @} */
19600 
19601 /*! @name ZQ1OR1 - ZQ n Impedance Control Override Data Register 1 */
19602 /*! @{ */
19603 #define DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_MASK     (0x3FFU)
19604 #define DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_SHIFT    (0U)
19605 /*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination
19606  */
19607 #define DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_MASK)
19608 #define DDRPHY_ZQ1OR1_RESERVED_15_10_MASK        (0xFC00U)
19609 #define DDRPHY_ZQ1OR1_RESERVED_15_10_SHIFT       (10U)
19610 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19611  */
19612 #define DDRPHY_ZQ1OR1_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1OR1_RESERVED_15_10_MASK)
19613 #define DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_MASK     (0x3FF0000U)
19614 #define DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_SHIFT    (16U)
19615 /*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination
19616  */
19617 #define DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_MASK)
19618 #define DDRPHY_ZQ1OR1_RESERVED_31_26_MASK        (0xFC000000U)
19619 #define DDRPHY_ZQ1OR1_RESERVED_31_26_SHIFT       (26U)
19620 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19621  */
19622 #define DDRPHY_ZQ1OR1_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1OR1_RESERVED_31_26_MASK)
19623 /*! @} */
19624 
19625 /*! @name ZQ1SR - ZQ n Impedance Control Status Register */
19626 /*! @{ */
19627 #define DDRPHY_ZQ1SR_ZPD_MASK                    (0x3U)
19628 #define DDRPHY_ZQ1SR_ZPD_SHIFT                   (0U)
19629 /*! ZPD - Output impedance pull-down calibration status
19630  */
19631 #define DDRPHY_ZQ1SR_ZPD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZPD_SHIFT)) & DDRPHY_ZQ1SR_ZPD_MASK)
19632 #define DDRPHY_ZQ1SR_ZPU_MASK                    (0xCU)
19633 #define DDRPHY_ZQ1SR_ZPU_SHIFT                   (2U)
19634 /*! ZPU - Output impedance pull-up calibration status
19635  */
19636 #define DDRPHY_ZQ1SR_ZPU(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZPU_SHIFT)) & DDRPHY_ZQ1SR_ZPU_MASK)
19637 #define DDRPHY_ZQ1SR_OPD_MASK                    (0x30U)
19638 #define DDRPHY_ZQ1SR_OPD_SHIFT                   (4U)
19639 /*! OPD - On-die termination (ODT) pull-down calibration status
19640  */
19641 #define DDRPHY_ZQ1SR_OPD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_OPD_SHIFT)) & DDRPHY_ZQ1SR_OPD_MASK)
19642 #define DDRPHY_ZQ1SR_OPU_MASK                    (0xC0U)
19643 #define DDRPHY_ZQ1SR_OPU_SHIFT                   (6U)
19644 /*! OPU - On-die termination (ODT) pull-up calibration status
19645  */
19646 #define DDRPHY_ZQ1SR_OPU(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_OPU_SHIFT)) & DDRPHY_ZQ1SR_OPU_MASK)
19647 #define DDRPHY_ZQ1SR_ZERR_MASK                   (0x100U)
19648 #define DDRPHY_ZQ1SR_ZERR_SHIFT                  (8U)
19649 /*! ZERR - Impedance Calibration Error
19650  */
19651 #define DDRPHY_ZQ1SR_ZERR(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZERR_SHIFT)) & DDRPHY_ZQ1SR_ZERR_MASK)
19652 #define DDRPHY_ZQ1SR_ZDONE_MASK                  (0x200U)
19653 #define DDRPHY_ZQ1SR_ZDONE_SHIFT                 (9U)
19654 /*! ZDONE - Impedance Calibration Done
19655  */
19656 #define DDRPHY_ZQ1SR_ZDONE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZDONE_SHIFT)) & DDRPHY_ZQ1SR_ZDONE_MASK)
19657 #define DDRPHY_ZQ1SR_PU_DRV_SAT_MASK             (0x400U)
19658 #define DDRPHY_ZQ1SR_PU_DRV_SAT_SHIFT            (10U)
19659 /*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19660  */
19661 #define DDRPHY_ZQ1SR_PU_DRV_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ1SR_PU_DRV_SAT_MASK)
19662 #define DDRPHY_ZQ1SR_PD_DRV_SAT_MASK             (0x800U)
19663 #define DDRPHY_ZQ1SR_PD_DRV_SAT_SHIFT            (11U)
19664 /*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19665  */
19666 #define DDRPHY_ZQ1SR_PD_DRV_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ1SR_PD_DRV_SAT_MASK)
19667 #define DDRPHY_ZQ1SR_PU_ODT_SAT_MASK             (0x1000U)
19668 #define DDRPHY_ZQ1SR_PU_ODT_SAT_SHIFT            (12U)
19669 /*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19670  */
19671 #define DDRPHY_ZQ1SR_PU_ODT_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ1SR_PU_ODT_SAT_MASK)
19672 #define DDRPHY_ZQ1SR_PD_ODT_SAT_MASK             (0x2000U)
19673 #define DDRPHY_ZQ1SR_PD_ODT_SAT_SHIFT            (13U)
19674 /*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19675  */
19676 #define DDRPHY_ZQ1SR_PD_ODT_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ1SR_PD_ODT_SAT_MASK)
19677 #define DDRPHY_ZQ1SR_RESERVED_31_14_MASK         (0xFFFFC000U)
19678 #define DDRPHY_ZQ1SR_RESERVED_31_14_SHIFT        (14U)
19679 /*! RESERVED_31_14 - Reserved. Return zeros on reads.
19680  */
19681 #define DDRPHY_ZQ1SR_RESERVED_31_14(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ1SR_RESERVED_31_14_MASK)
19682 /*! @} */
19683 
19684 /*! @name ZQ2PR0 - ZQ n Impedance Control Program Register 0 */
19685 /*! @{ */
19686 #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_MASK     (0xFU)
19687 #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_SHIFT    (0U)
19688 /*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
19689  */
19690 #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_MASK)
19691 #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_MASK     (0xF0U)
19692 #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_SHIFT    (4U)
19693 /*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
19694  */
19695 #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_MASK)
19696 #define DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_MASK        (0xF00U)
19697 #define DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_SHIFT       (8U)
19698 /*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio
19699  */
19700 #define DDRPHY_ZQ2PR0_ZPROG_HOST_ODT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_MASK)
19701 #define DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_MASK        (0xF000U)
19702 #define DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_SHIFT       (12U)
19703 /*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio
19704  */
19705 #define DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_MASK)
19706 #define DDRPHY_ZQ2PR0_PU_DRV_ADJUST_MASK         (0x70000U)
19707 #define DDRPHY_ZQ2PR0_PU_DRV_ADJUST_SHIFT        (16U)
19708 /*! PU_DRV_ADJUST - Pullup drive strength adjustment
19709  */
19710 #define DDRPHY_ZQ2PR0_PU_DRV_ADJUST(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ2PR0_PU_DRV_ADJUST_MASK)
19711 #define DDRPHY_ZQ2PR0_PD_DRV_ADJUST_MASK         (0x380000U)
19712 #define DDRPHY_ZQ2PR0_PD_DRV_ADJUST_SHIFT        (19U)
19713 /*! PD_DRV_ADJUST - Pulldown drive strength adjustment
19714  */
19715 #define DDRPHY_ZQ2PR0_PD_DRV_ADJUST(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ2PR0_PD_DRV_ADJUST_MASK)
19716 #define DDRPHY_ZQ2PR0_ODT_ADJUST_MASK            (0x1C00000U)
19717 #define DDRPHY_ZQ2PR0_ODT_ADJUST_SHIFT           (22U)
19718 /*! ODT_ADJUST - Termination adjustment
19719  */
19720 #define DDRPHY_ZQ2PR0_ODT_ADJUST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ2PR0_ODT_ADJUST_MASK)
19721 #define DDRPHY_ZQ2PR0_ZLE_MODE_MASK              (0x6000000U)
19722 #define DDRPHY_ZQ2PR0_ZLE_MODE_SHIFT             (25U)
19723 /*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
19724  */
19725 #define DDRPHY_ZQ2PR0_ZLE_MODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ2PR0_ZLE_MODE_MASK)
19726 #define DDRPHY_ZQ2PR0_ZSEGBYP_MASK               (0x8000000U)
19727 #define DDRPHY_ZQ2PR0_ZSEGBYP_SHIFT              (27U)
19728 /*! ZSEGBYP - Calibration segment bypass
19729  */
19730 #define DDRPHY_ZQ2PR0_ZSEGBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ2PR0_ZSEGBYP_MASK)
19731 #define DDRPHY_ZQ2PR0_PU_ODT_ZDEN_MASK           (0x10000000U)
19732 #define DDRPHY_ZQ2PR0_PU_ODT_ZDEN_SHIFT          (28U)
19733 /*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable
19734  */
19735 #define DDRPHY_ZQ2PR0_PU_ODT_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PU_ODT_ZDEN_MASK)
19736 #define DDRPHY_ZQ2PR0_PD_ODT_ZDEN_MASK           (0x20000000U)
19737 #define DDRPHY_ZQ2PR0_PD_ODT_ZDEN_SHIFT          (29U)
19738 /*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable
19739  */
19740 #define DDRPHY_ZQ2PR0_PD_ODT_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PD_ODT_ZDEN_MASK)
19741 #define DDRPHY_ZQ2PR0_PU_DRV_ZDEN_MASK           (0x40000000U)
19742 #define DDRPHY_ZQ2PR0_PU_DRV_ZDEN_SHIFT          (30U)
19743 /*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable
19744  */
19745 #define DDRPHY_ZQ2PR0_PU_DRV_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PU_DRV_ZDEN_MASK)
19746 #define DDRPHY_ZQ2PR0_PD_DRV_ZDEN_MASK           (0x80000000U)
19747 #define DDRPHY_ZQ2PR0_PD_DRV_ZDEN_SHIFT          (31U)
19748 /*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable
19749  */
19750 #define DDRPHY_ZQ2PR0_PD_DRV_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PD_DRV_ZDEN_MASK)
19751 /*! @} */
19752 
19753 /*! @name ZQ2PR1 - ZQ n Impedance Control Program Register 1 */
19754 /*! @{ */
19755 #define DDRPHY_ZQ2PR1_PD_REFSEL_MASK             (0x7FU)
19756 #define DDRPHY_ZQ2PR1_PD_REFSEL_SHIFT            (0U)
19757 /*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell
19758  */
19759 #define DDRPHY_ZQ2PR1_PD_REFSEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ2PR1_PD_REFSEL_MASK)
19760 #define DDRPHY_ZQ2PR1_RESERVED_7_MASK            (0x80U)
19761 #define DDRPHY_ZQ2PR1_RESERVED_7_SHIFT           (7U)
19762 /*! RESERVED_7 - Reserved. Return zeros on reads.
19763  */
19764 #define DDRPHY_ZQ2PR1_RESERVED_7(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ2PR1_RESERVED_7_MASK)
19765 #define DDRPHY_ZQ2PR1_PU_REFSEL_MASK             (0x7F00U)
19766 #define DDRPHY_ZQ2PR1_PU_REFSEL_SHIFT            (8U)
19767 /*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell
19768  */
19769 #define DDRPHY_ZQ2PR1_PU_REFSEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ2PR1_PU_REFSEL_MASK)
19770 #define DDRPHY_ZQ2PR1_RESERVED_31_15_MASK        (0xFFFF8000U)
19771 #define DDRPHY_ZQ2PR1_RESERVED_31_15_SHIFT       (15U)
19772 /*! RESERVED_31_15 - Reserved. Return zeros on reads.
19773  */
19774 #define DDRPHY_ZQ2PR1_RESERVED_31_15(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ2PR1_RESERVED_31_15_MASK)
19775 /*! @} */
19776 
19777 /*! @name ZQ2DR0 - ZQ n Impedance Control Data Register 0 */
19778 /*! @{ */
19779 #define DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_MASK   (0x3FFU)
19780 #define DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_SHIFT  (0U)
19781 /*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result
19782  */
19783 #define DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_MASK)
19784 #define DDRPHY_ZQ2DR0_RESERVED_15_10_MASK        (0xFC00U)
19785 #define DDRPHY_ZQ2DR0_RESERVED_15_10_SHIFT       (10U)
19786 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19787  */
19788 #define DDRPHY_ZQ2DR0_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2DR0_RESERVED_15_10_MASK)
19789 #define DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_MASK   (0x3FF0000U)
19790 #define DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_SHIFT  (16U)
19791 /*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result
19792  */
19793 #define DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_MASK)
19794 #define DDRPHY_ZQ2DR0_RESERVED_31_26_MASK        (0xFC000000U)
19795 #define DDRPHY_ZQ2DR0_RESERVED_31_26_SHIFT       (26U)
19796 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19797  */
19798 #define DDRPHY_ZQ2DR0_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2DR0_RESERVED_31_26_MASK)
19799 /*! @} */
19800 
19801 /*! @name ZQ2DR1 - ZQ n Impedance Control Data Register 1 */
19802 /*! @{ */
19803 #define DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_MASK   (0x3FFU)
19804 #define DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_SHIFT  (0U)
19805 /*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result
19806  */
19807 #define DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_MASK)
19808 #define DDRPHY_ZQ2DR1_RESERVED_15_10_MASK        (0xFC00U)
19809 #define DDRPHY_ZQ2DR1_RESERVED_15_10_SHIFT       (10U)
19810 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19811  */
19812 #define DDRPHY_ZQ2DR1_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2DR1_RESERVED_15_10_MASK)
19813 #define DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_MASK   (0x3FF0000U)
19814 #define DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_SHIFT  (16U)
19815 /*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result
19816  */
19817 #define DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_MASK)
19818 #define DDRPHY_ZQ2DR1_RESERVED_31_26_MASK        (0xFC000000U)
19819 #define DDRPHY_ZQ2DR1_RESERVED_31_26_SHIFT       (26U)
19820 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19821  */
19822 #define DDRPHY_ZQ2DR1_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2DR1_RESERVED_31_26_MASK)
19823 /*! @} */
19824 
19825 /*! @name ZQ2OR0 - ZQ n Impedance Control Override Data Register 0 */
19826 /*! @{ */
19827 #define DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_MASK     (0x3FFU)
19828 #define DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_SHIFT    (0U)
19829 /*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance
19830  */
19831 #define DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_MASK)
19832 #define DDRPHY_ZQ2OR0_RESERVED_15_10_MASK        (0xFC00U)
19833 #define DDRPHY_ZQ2OR0_RESERVED_15_10_SHIFT       (10U)
19834 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19835  */
19836 #define DDRPHY_ZQ2OR0_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2OR0_RESERVED_15_10_MASK)
19837 #define DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_MASK     (0x3FF0000U)
19838 #define DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_SHIFT    (16U)
19839 /*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance
19840  */
19841 #define DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_MASK)
19842 #define DDRPHY_ZQ2OR0_RESERVED_31_26_MASK        (0xFC000000U)
19843 #define DDRPHY_ZQ2OR0_RESERVED_31_26_SHIFT       (26U)
19844 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19845  */
19846 #define DDRPHY_ZQ2OR0_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2OR0_RESERVED_31_26_MASK)
19847 /*! @} */
19848 
19849 /*! @name ZQ2OR1 - ZQ n Impedance Control Override Data Register 1 */
19850 /*! @{ */
19851 #define DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_MASK     (0x3FFU)
19852 #define DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_SHIFT    (0U)
19853 /*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination
19854  */
19855 #define DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_MASK)
19856 #define DDRPHY_ZQ2OR1_RESERVED_15_10_MASK        (0xFC00U)
19857 #define DDRPHY_ZQ2OR1_RESERVED_15_10_SHIFT       (10U)
19858 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
19859  */
19860 #define DDRPHY_ZQ2OR1_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2OR1_RESERVED_15_10_MASK)
19861 #define DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_MASK     (0x3FF0000U)
19862 #define DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_SHIFT    (16U)
19863 /*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination
19864  */
19865 #define DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_MASK)
19866 #define DDRPHY_ZQ2OR1_RESERVED_31_26_MASK        (0xFC000000U)
19867 #define DDRPHY_ZQ2OR1_RESERVED_31_26_SHIFT       (26U)
19868 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
19869  */
19870 #define DDRPHY_ZQ2OR1_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2OR1_RESERVED_31_26_MASK)
19871 /*! @} */
19872 
19873 /*! @name ZQ2SR - ZQ n Impedance Control Status Register */
19874 /*! @{ */
19875 #define DDRPHY_ZQ2SR_ZPD_MASK                    (0x3U)
19876 #define DDRPHY_ZQ2SR_ZPD_SHIFT                   (0U)
19877 /*! ZPD - Output impedance pull-down calibration status
19878  */
19879 #define DDRPHY_ZQ2SR_ZPD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZPD_SHIFT)) & DDRPHY_ZQ2SR_ZPD_MASK)
19880 #define DDRPHY_ZQ2SR_ZPU_MASK                    (0xCU)
19881 #define DDRPHY_ZQ2SR_ZPU_SHIFT                   (2U)
19882 /*! ZPU - Output impedance pull-up calibration status
19883  */
19884 #define DDRPHY_ZQ2SR_ZPU(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZPU_SHIFT)) & DDRPHY_ZQ2SR_ZPU_MASK)
19885 #define DDRPHY_ZQ2SR_OPD_MASK                    (0x30U)
19886 #define DDRPHY_ZQ2SR_OPD_SHIFT                   (4U)
19887 /*! OPD - On-die termination (ODT) pull-down calibration status
19888  */
19889 #define DDRPHY_ZQ2SR_OPD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_OPD_SHIFT)) & DDRPHY_ZQ2SR_OPD_MASK)
19890 #define DDRPHY_ZQ2SR_OPU_MASK                    (0xC0U)
19891 #define DDRPHY_ZQ2SR_OPU_SHIFT                   (6U)
19892 /*! OPU - On-die termination (ODT) pull-up calibration status
19893  */
19894 #define DDRPHY_ZQ2SR_OPU(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_OPU_SHIFT)) & DDRPHY_ZQ2SR_OPU_MASK)
19895 #define DDRPHY_ZQ2SR_ZERR_MASK                   (0x100U)
19896 #define DDRPHY_ZQ2SR_ZERR_SHIFT                  (8U)
19897 /*! ZERR - Impedance Calibration Error
19898  */
19899 #define DDRPHY_ZQ2SR_ZERR(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZERR_SHIFT)) & DDRPHY_ZQ2SR_ZERR_MASK)
19900 #define DDRPHY_ZQ2SR_ZDONE_MASK                  (0x200U)
19901 #define DDRPHY_ZQ2SR_ZDONE_SHIFT                 (9U)
19902 /*! ZDONE - Impedance Calibration Done
19903  */
19904 #define DDRPHY_ZQ2SR_ZDONE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZDONE_SHIFT)) & DDRPHY_ZQ2SR_ZDONE_MASK)
19905 #define DDRPHY_ZQ2SR_PU_DRV_SAT_MASK             (0x400U)
19906 #define DDRPHY_ZQ2SR_PU_DRV_SAT_SHIFT            (10U)
19907 /*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19908  */
19909 #define DDRPHY_ZQ2SR_PU_DRV_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ2SR_PU_DRV_SAT_MASK)
19910 #define DDRPHY_ZQ2SR_PD_DRV_SAT_MASK             (0x800U)
19911 #define DDRPHY_ZQ2SR_PD_DRV_SAT_SHIFT            (11U)
19912 /*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19913  */
19914 #define DDRPHY_ZQ2SR_PD_DRV_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ2SR_PD_DRV_SAT_MASK)
19915 #define DDRPHY_ZQ2SR_PU_ODT_SAT_MASK             (0x1000U)
19916 #define DDRPHY_ZQ2SR_PU_ODT_SAT_SHIFT            (12U)
19917 /*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19918  */
19919 #define DDRPHY_ZQ2SR_PU_ODT_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ2SR_PU_ODT_SAT_MASK)
19920 #define DDRPHY_ZQ2SR_PD_ODT_SAT_MASK             (0x2000U)
19921 #define DDRPHY_ZQ2SR_PD_ODT_SAT_SHIFT            (13U)
19922 /*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19923  */
19924 #define DDRPHY_ZQ2SR_PD_ODT_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ2SR_PD_ODT_SAT_MASK)
19925 #define DDRPHY_ZQ2SR_RESERVED_31_14_MASK         (0xFFFFC000U)
19926 #define DDRPHY_ZQ2SR_RESERVED_31_14_SHIFT        (14U)
19927 /*! RESERVED_31_14 - Reserved. Return zeros on reads.
19928  */
19929 #define DDRPHY_ZQ2SR_RESERVED_31_14(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ2SR_RESERVED_31_14_MASK)
19930 /*! @} */
19931 
19932 /*! @name ZQ3PR0 - ZQ n Impedance Control Program Register 0 */
19933 /*! @{ */
19934 #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_MASK     (0xFU)
19935 #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_SHIFT    (0U)
19936 /*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
19937  */
19938 #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_MASK)
19939 #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_MASK     (0xF0U)
19940 #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_SHIFT    (4U)
19941 /*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
19942  */
19943 #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_MASK)
19944 #define DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_MASK        (0xF00U)
19945 #define DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_SHIFT       (8U)
19946 /*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio
19947  */
19948 #define DDRPHY_ZQ3PR0_ZPROG_HOST_ODT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_MASK)
19949 #define DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_MASK        (0xF000U)
19950 #define DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_SHIFT       (12U)
19951 /*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio
19952  */
19953 #define DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_MASK)
19954 #define DDRPHY_ZQ3PR0_PU_DRV_ADJUST_MASK         (0x70000U)
19955 #define DDRPHY_ZQ3PR0_PU_DRV_ADJUST_SHIFT        (16U)
19956 /*! PU_DRV_ADJUST - Pullup drive strength adjustment
19957  */
19958 #define DDRPHY_ZQ3PR0_PU_DRV_ADJUST(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ3PR0_PU_DRV_ADJUST_MASK)
19959 #define DDRPHY_ZQ3PR0_PD_DRV_ADJUST_MASK         (0x380000U)
19960 #define DDRPHY_ZQ3PR0_PD_DRV_ADJUST_SHIFT        (19U)
19961 /*! PD_DRV_ADJUST - Pulldown drive strength adjustment
19962  */
19963 #define DDRPHY_ZQ3PR0_PD_DRV_ADJUST(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ3PR0_PD_DRV_ADJUST_MASK)
19964 #define DDRPHY_ZQ3PR0_ODT_ADJUST_MASK            (0x1C00000U)
19965 #define DDRPHY_ZQ3PR0_ODT_ADJUST_SHIFT           (22U)
19966 /*! ODT_ADJUST - Termination adjustment
19967  */
19968 #define DDRPHY_ZQ3PR0_ODT_ADJUST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ3PR0_ODT_ADJUST_MASK)
19969 #define DDRPHY_ZQ3PR0_ZLE_MODE_MASK              (0x6000000U)
19970 #define DDRPHY_ZQ3PR0_ZLE_MODE_SHIFT             (25U)
19971 /*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
19972  */
19973 #define DDRPHY_ZQ3PR0_ZLE_MODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ3PR0_ZLE_MODE_MASK)
19974 #define DDRPHY_ZQ3PR0_ZSEGBYP_MASK               (0x8000000U)
19975 #define DDRPHY_ZQ3PR0_ZSEGBYP_SHIFT              (27U)
19976 /*! ZSEGBYP - Calibration segment bypass
19977  */
19978 #define DDRPHY_ZQ3PR0_ZSEGBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ3PR0_ZSEGBYP_MASK)
19979 #define DDRPHY_ZQ3PR0_PU_ODT_ZDEN_MASK           (0x10000000U)
19980 #define DDRPHY_ZQ3PR0_PU_ODT_ZDEN_SHIFT          (28U)
19981 /*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable
19982  */
19983 #define DDRPHY_ZQ3PR0_PU_ODT_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PU_ODT_ZDEN_MASK)
19984 #define DDRPHY_ZQ3PR0_PD_ODT_ZDEN_MASK           (0x20000000U)
19985 #define DDRPHY_ZQ3PR0_PD_ODT_ZDEN_SHIFT          (29U)
19986 /*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable
19987  */
19988 #define DDRPHY_ZQ3PR0_PD_ODT_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PD_ODT_ZDEN_MASK)
19989 #define DDRPHY_ZQ3PR0_PU_DRV_ZDEN_MASK           (0x40000000U)
19990 #define DDRPHY_ZQ3PR0_PU_DRV_ZDEN_SHIFT          (30U)
19991 /*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable
19992  */
19993 #define DDRPHY_ZQ3PR0_PU_DRV_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PU_DRV_ZDEN_MASK)
19994 #define DDRPHY_ZQ3PR0_PD_DRV_ZDEN_MASK           (0x80000000U)
19995 #define DDRPHY_ZQ3PR0_PD_DRV_ZDEN_SHIFT          (31U)
19996 /*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable
19997  */
19998 #define DDRPHY_ZQ3PR0_PD_DRV_ZDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PD_DRV_ZDEN_MASK)
19999 /*! @} */
20000 
20001 /*! @name ZQ3PR1 - ZQ n Impedance Control Program Register 1 */
20002 /*! @{ */
20003 #define DDRPHY_ZQ3PR1_PD_REFSEL_MASK             (0x7FU)
20004 #define DDRPHY_ZQ3PR1_PD_REFSEL_SHIFT            (0U)
20005 /*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell
20006  */
20007 #define DDRPHY_ZQ3PR1_PD_REFSEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ3PR1_PD_REFSEL_MASK)
20008 #define DDRPHY_ZQ3PR1_RESERVED_7_MASK            (0x80U)
20009 #define DDRPHY_ZQ3PR1_RESERVED_7_SHIFT           (7U)
20010 /*! RESERVED_7 - Reserved. Return zeros on reads.
20011  */
20012 #define DDRPHY_ZQ3PR1_RESERVED_7(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ3PR1_RESERVED_7_MASK)
20013 #define DDRPHY_ZQ3PR1_PU_REFSEL_MASK             (0x7F00U)
20014 #define DDRPHY_ZQ3PR1_PU_REFSEL_SHIFT            (8U)
20015 /*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell
20016  */
20017 #define DDRPHY_ZQ3PR1_PU_REFSEL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ3PR1_PU_REFSEL_MASK)
20018 #define DDRPHY_ZQ3PR1_RESERVED_31_15_MASK        (0xFFFF8000U)
20019 #define DDRPHY_ZQ3PR1_RESERVED_31_15_SHIFT       (15U)
20020 /*! RESERVED_31_15 - Reserved. Return zeros on reads.
20021  */
20022 #define DDRPHY_ZQ3PR1_RESERVED_31_15(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ3PR1_RESERVED_31_15_MASK)
20023 /*! @} */
20024 
20025 /*! @name ZQ3DR0 - ZQ n Impedance Control Data Register 0 */
20026 /*! @{ */
20027 #define DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_MASK   (0x3FFU)
20028 #define DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_SHIFT  (0U)
20029 /*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result
20030  */
20031 #define DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_MASK)
20032 #define DDRPHY_ZQ3DR0_RESERVED_15_10_MASK        (0xFC00U)
20033 #define DDRPHY_ZQ3DR0_RESERVED_15_10_SHIFT       (10U)
20034 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
20035  */
20036 #define DDRPHY_ZQ3DR0_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3DR0_RESERVED_15_10_MASK)
20037 #define DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_MASK   (0x3FF0000U)
20038 #define DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_SHIFT  (16U)
20039 /*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result
20040  */
20041 #define DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_MASK)
20042 #define DDRPHY_ZQ3DR0_RESERVED_31_26_MASK        (0xFC000000U)
20043 #define DDRPHY_ZQ3DR0_RESERVED_31_26_SHIFT       (26U)
20044 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
20045  */
20046 #define DDRPHY_ZQ3DR0_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3DR0_RESERVED_31_26_MASK)
20047 /*! @} */
20048 
20049 /*! @name ZQ3DR1 - ZQ n Impedance Control Data Register 1 */
20050 /*! @{ */
20051 #define DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_MASK   (0x3FFU)
20052 #define DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_SHIFT  (0U)
20053 /*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result
20054  */
20055 #define DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_MASK)
20056 #define DDRPHY_ZQ3DR1_RESERVED_15_10_MASK        (0xFC00U)
20057 #define DDRPHY_ZQ3DR1_RESERVED_15_10_SHIFT       (10U)
20058 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
20059  */
20060 #define DDRPHY_ZQ3DR1_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3DR1_RESERVED_15_10_MASK)
20061 #define DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_MASK   (0x3FF0000U)
20062 #define DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_SHIFT  (16U)
20063 /*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result
20064  */
20065 #define DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_MASK)
20066 #define DDRPHY_ZQ3DR1_RESERVED_31_26_MASK        (0xFC000000U)
20067 #define DDRPHY_ZQ3DR1_RESERVED_31_26_SHIFT       (26U)
20068 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
20069  */
20070 #define DDRPHY_ZQ3DR1_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3DR1_RESERVED_31_26_MASK)
20071 /*! @} */
20072 
20073 /*! @name ZQ3OR0 - ZQ n Impedance Control Override Data Register 0 */
20074 /*! @{ */
20075 #define DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_MASK     (0x3FFU)
20076 #define DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_SHIFT    (0U)
20077 /*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance
20078  */
20079 #define DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_MASK)
20080 #define DDRPHY_ZQ3OR0_RESERVED_15_10_MASK        (0xFC00U)
20081 #define DDRPHY_ZQ3OR0_RESERVED_15_10_SHIFT       (10U)
20082 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
20083  */
20084 #define DDRPHY_ZQ3OR0_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3OR0_RESERVED_15_10_MASK)
20085 #define DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_MASK     (0x3FF0000U)
20086 #define DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_SHIFT    (16U)
20087 /*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance
20088  */
20089 #define DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_MASK)
20090 #define DDRPHY_ZQ3OR0_RESERVED_31_26_MASK        (0xFC000000U)
20091 #define DDRPHY_ZQ3OR0_RESERVED_31_26_SHIFT       (26U)
20092 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
20093  */
20094 #define DDRPHY_ZQ3OR0_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3OR0_RESERVED_31_26_MASK)
20095 /*! @} */
20096 
20097 /*! @name ZQ3OR1 - ZQ n Impedance Control Override Data Register 1 */
20098 /*! @{ */
20099 #define DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_MASK     (0x3FFU)
20100 #define DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_SHIFT    (0U)
20101 /*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination
20102  */
20103 #define DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_MASK)
20104 #define DDRPHY_ZQ3OR1_RESERVED_15_10_MASK        (0xFC00U)
20105 #define DDRPHY_ZQ3OR1_RESERVED_15_10_SHIFT       (10U)
20106 /*! RESERVED_15_10 - Reserved. Return zeros on reads.
20107  */
20108 #define DDRPHY_ZQ3OR1_RESERVED_15_10(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3OR1_RESERVED_15_10_MASK)
20109 #define DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_MASK     (0x3FF0000U)
20110 #define DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_SHIFT    (16U)
20111 /*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination
20112  */
20113 #define DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_MASK)
20114 #define DDRPHY_ZQ3OR1_RESERVED_31_26_MASK        (0xFC000000U)
20115 #define DDRPHY_ZQ3OR1_RESERVED_31_26_SHIFT       (26U)
20116 /*! RESERVED_31_26 - Reserved. Return zeros on reads.
20117  */
20118 #define DDRPHY_ZQ3OR1_RESERVED_31_26(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3OR1_RESERVED_31_26_MASK)
20119 /*! @} */
20120 
20121 /*! @name ZQ3SR - ZQ n Impedance Control Status Register */
20122 /*! @{ */
20123 #define DDRPHY_ZQ3SR_ZPD_MASK                    (0x3U)
20124 #define DDRPHY_ZQ3SR_ZPD_SHIFT                   (0U)
20125 /*! ZPD - Output impedance pull-down calibration status
20126  */
20127 #define DDRPHY_ZQ3SR_ZPD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZPD_SHIFT)) & DDRPHY_ZQ3SR_ZPD_MASK)
20128 #define DDRPHY_ZQ3SR_ZPU_MASK                    (0xCU)
20129 #define DDRPHY_ZQ3SR_ZPU_SHIFT                   (2U)
20130 /*! ZPU - Output impedance pull-up calibration status
20131  */
20132 #define DDRPHY_ZQ3SR_ZPU(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZPU_SHIFT)) & DDRPHY_ZQ3SR_ZPU_MASK)
20133 #define DDRPHY_ZQ3SR_OPD_MASK                    (0x30U)
20134 #define DDRPHY_ZQ3SR_OPD_SHIFT                   (4U)
20135 /*! OPD - On-die termination (ODT) pull-down calibration status
20136  */
20137 #define DDRPHY_ZQ3SR_OPD(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_OPD_SHIFT)) & DDRPHY_ZQ3SR_OPD_MASK)
20138 #define DDRPHY_ZQ3SR_OPU_MASK                    (0xC0U)
20139 #define DDRPHY_ZQ3SR_OPU_SHIFT                   (6U)
20140 /*! OPU - On-die termination (ODT) pull-up calibration status
20141  */
20142 #define DDRPHY_ZQ3SR_OPU(x)                      (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_OPU_SHIFT)) & DDRPHY_ZQ3SR_OPU_MASK)
20143 #define DDRPHY_ZQ3SR_ZERR_MASK                   (0x100U)
20144 #define DDRPHY_ZQ3SR_ZERR_SHIFT                  (8U)
20145 /*! ZERR - Impedance Calibration Error
20146  */
20147 #define DDRPHY_ZQ3SR_ZERR(x)                     (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZERR_SHIFT)) & DDRPHY_ZQ3SR_ZERR_MASK)
20148 #define DDRPHY_ZQ3SR_ZDONE_MASK                  (0x200U)
20149 #define DDRPHY_ZQ3SR_ZDONE_SHIFT                 (9U)
20150 /*! ZDONE - Impedance Calibration Done
20151  */
20152 #define DDRPHY_ZQ3SR_ZDONE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZDONE_SHIFT)) & DDRPHY_ZQ3SR_ZDONE_MASK)
20153 #define DDRPHY_ZQ3SR_PU_DRV_SAT_MASK             (0x400U)
20154 #define DDRPHY_ZQ3SR_PU_DRV_SAT_SHIFT            (10U)
20155 /*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register
20156  */
20157 #define DDRPHY_ZQ3SR_PU_DRV_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ3SR_PU_DRV_SAT_MASK)
20158 #define DDRPHY_ZQ3SR_PD_DRV_SAT_MASK             (0x800U)
20159 #define DDRPHY_ZQ3SR_PD_DRV_SAT_SHIFT            (11U)
20160 /*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register
20161  */
20162 #define DDRPHY_ZQ3SR_PD_DRV_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ3SR_PD_DRV_SAT_MASK)
20163 #define DDRPHY_ZQ3SR_PU_ODT_SAT_MASK             (0x1000U)
20164 #define DDRPHY_ZQ3SR_PU_ODT_SAT_SHIFT            (12U)
20165 /*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register
20166  */
20167 #define DDRPHY_ZQ3SR_PU_ODT_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ3SR_PU_ODT_SAT_MASK)
20168 #define DDRPHY_ZQ3SR_PD_ODT_SAT_MASK             (0x2000U)
20169 #define DDRPHY_ZQ3SR_PD_ODT_SAT_SHIFT            (13U)
20170 /*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register
20171  */
20172 #define DDRPHY_ZQ3SR_PD_ODT_SAT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ3SR_PD_ODT_SAT_MASK)
20173 #define DDRPHY_ZQ3SR_RESERVED_31_14_MASK         (0xFFFFC000U)
20174 #define DDRPHY_ZQ3SR_RESERVED_31_14_SHIFT        (14U)
20175 /*! RESERVED_31_14 - Reserved. Return zeros on reads.
20176  */
20177 #define DDRPHY_ZQ3SR_RESERVED_31_14(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ3SR_RESERVED_31_14_MASK)
20178 /*! @} */
20179 
20180 /*! @name DX0GCR0 - DATX8 n General Configuration Register 0 */
20181 /*! @{ */
20182 #define DDRPHY_DX0GCR0_RESERVED_1_0_MASK         (0x3U)
20183 #define DDRPHY_DX0GCR0_RESERVED_1_0_SHIFT        (0U)
20184 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
20185  */
20186 #define DDRPHY_DX0GCR0_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX0GCR0_RESERVED_1_0_MASK)
20187 #define DDRPHY_DX0GCR0_DQSGOE_MASK               (0x4U)
20188 #define DDRPHY_DX0GCR0_DQSGOE_SHIFT              (2U)
20189 /*! DQSGOE - DQSG Output Enable
20190  */
20191 #define DDRPHY_DX0GCR0_DQSGOE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSGOE_SHIFT)) & DDRPHY_DX0GCR0_DQSGOE_MASK)
20192 #define DDRPHY_DX0GCR0_DQSGODT_MASK              (0x8U)
20193 #define DDRPHY_DX0GCR0_DQSGODT_SHIFT             (3U)
20194 /*! DQSGODT - DQSG On-Die Termination
20195  */
20196 #define DDRPHY_DX0GCR0_DQSGODT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSGODT_SHIFT)) & DDRPHY_DX0GCR0_DQSGODT_MASK)
20197 #define DDRPHY_DX0GCR0_RESERVED_4_MASK           (0x10U)
20198 #define DDRPHY_DX0GCR0_RESERVED_4_SHIFT          (4U)
20199 /*! RESERVED_4 - Reserved. Return zeroes on reads.
20200  */
20201 #define DDRPHY_DX0GCR0_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX0GCR0_RESERVED_4_MASK)
20202 #define DDRPHY_DX0GCR0_DQSGPDR_MASK              (0x20U)
20203 #define DDRPHY_DX0GCR0_DQSGPDR_SHIFT             (5U)
20204 /*! DQSGPDR - DQSG Power Down Receiver
20205  */
20206 #define DDRPHY_DX0GCR0_DQSGPDR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX0GCR0_DQSGPDR_MASK)
20207 #define DDRPHY_DX0GCR0_DQSRPD_MASK               (0x40U)
20208 #define DDRPHY_DX0GCR0_DQSRPD_SHIFT              (6U)
20209 /*! DQSRPD - DQSR Power Down
20210  */
20211 #define DDRPHY_DX0GCR0_DQSRPD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSRPD_SHIFT)) & DDRPHY_DX0GCR0_DQSRPD_MASK)
20212 #define DDRPHY_DX0GCR0_CPDRSHFT_MASK             (0x180U)
20213 #define DDRPHY_DX0GCR0_CPDRSHFT_SHIFT            (7U)
20214 /*! CPDRSHFT - Configurable PDR Phase Shift
20215  */
20216 #define DDRPHY_DX0GCR0_CPDRSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX0GCR0_CPDRSHFT_MASK)
20217 #define DDRPHY_DX0GCR0_RTTOH_MASK                (0x600U)
20218 #define DDRPHY_DX0GCR0_RTTOH_SHIFT               (9U)
20219 /*! RTTOH - RTT Output Hold
20220  */
20221 #define DDRPHY_DX0GCR0_RTTOH(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RTTOH_SHIFT)) & DDRPHY_DX0GCR0_RTTOH_MASK)
20222 #define DDRPHY_DX0GCR0_RTTOAL_MASK               (0x800U)
20223 #define DDRPHY_DX0GCR0_RTTOAL_SHIFT              (11U)
20224 /*! RTTOAL - RTT On Additive Latency
20225  */
20226 #define DDRPHY_DX0GCR0_RTTOAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RTTOAL_SHIFT)) & DDRPHY_DX0GCR0_RTTOAL_MASK)
20227 #define DDRPHY_DX0GCR0_DQSSEPDR_MASK             (0x1000U)
20228 #define DDRPHY_DX0GCR0_DQSSEPDR_SHIFT            (12U)
20229 /*! DQSSEPDR - DQSSE Power Down Receiver
20230  */
20231 #define DDRPHY_DX0GCR0_DQSSEPDR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX0GCR0_DQSSEPDR_MASK)
20232 #define DDRPHY_DX0GCR0_DQSNSEPDR_MASK            (0x2000U)
20233 #define DDRPHY_DX0GCR0_DQSNSEPDR_SHIFT           (13U)
20234 /*! DQSNSEPDR - DQSNSE Power Down Receiver
20235  */
20236 #define DDRPHY_DX0GCR0_DQSNSEPDR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX0GCR0_DQSNSEPDR_MASK)
20237 #define DDRPHY_DX0GCR0_RESERVED_19_14_MASK       (0xFC000U)
20238 #define DDRPHY_DX0GCR0_RESERVED_19_14_SHIFT      (14U)
20239 /*! RESERVED_19_14 - Reserved. Return zeroes on reads.
20240  */
20241 #define DDRPHY_DX0GCR0_RESERVED_19_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX0GCR0_RESERVED_19_14_MASK)
20242 #define DDRPHY_DX0GCR0_RDDLY_MASK                (0xF00000U)
20243 #define DDRPHY_DX0GCR0_RDDLY_SHIFT               (20U)
20244 /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
20245  */
20246 #define DDRPHY_DX0GCR0_RDDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RDDLY_SHIFT)) & DDRPHY_DX0GCR0_RDDLY_MASK)
20247 #define DDRPHY_DX0GCR0_DQSDCC_MASK               (0xF000000U)
20248 #define DDRPHY_DX0GCR0_DQSDCC_SHIFT              (24U)
20249 /*! DQSDCC - DQS Duty Cycle Correction
20250  */
20251 #define DDRPHY_DX0GCR0_DQSDCC(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSDCC_SHIFT)) & DDRPHY_DX0GCR0_DQSDCC_MASK)
20252 #define DDRPHY_DX0GCR0_CODTSHFT_MASK             (0x30000000U)
20253 #define DDRPHY_DX0GCR0_CODTSHFT_SHIFT            (28U)
20254 /*! CODTSHFT - Configurable ODT(TE) Phase Shift
20255  */
20256 #define DDRPHY_DX0GCR0_CODTSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX0GCR0_CODTSHFT_MASK)
20257 #define DDRPHY_DX0GCR0_MDLEN_MASK                (0x40000000U)
20258 #define DDRPHY_DX0GCR0_MDLEN_SHIFT               (30U)
20259 /*! MDLEN - Master Delay Line Enable
20260  */
20261 #define DDRPHY_DX0GCR0_MDLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_MDLEN_SHIFT)) & DDRPHY_DX0GCR0_MDLEN_MASK)
20262 #define DDRPHY_DX0GCR0_CALBYP_MASK               (0x80000000U)
20263 #define DDRPHY_DX0GCR0_CALBYP_SHIFT              (31U)
20264 /*! CALBYP - Calibration Bypass
20265  */
20266 #define DDRPHY_DX0GCR0_CALBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_CALBYP_SHIFT)) & DDRPHY_DX0GCR0_CALBYP_MASK)
20267 /*! @} */
20268 
20269 /*! @name DX0GCR1 - DATX8 n General Configuration Register 1 */
20270 /*! @{ */
20271 #define DDRPHY_DX0GCR1_DQEN_MASK                 (0xFFU)
20272 #define DDRPHY_DX0GCR1_DQEN_SHIFT                (0U)
20273 /*! DQEN - Enables DQ corresponding to each bit in a byte
20274  */
20275 #define DDRPHY_DX0GCR1_DQEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DQEN_SHIFT)) & DDRPHY_DX0GCR1_DQEN_MASK)
20276 #define DDRPHY_DX0GCR1_DMEN_MASK                 (0x100U)
20277 #define DDRPHY_DX0GCR1_DMEN_SHIFT                (8U)
20278 /*! DMEN - Enables DM pin in a byte lane
20279  */
20280 #define DDRPHY_DX0GCR1_DMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DMEN_SHIFT)) & DDRPHY_DX0GCR1_DMEN_MASK)
20281 #define DDRPHY_DX0GCR1_DSEN_MASK                 (0x200U)
20282 #define DDRPHY_DX0GCR1_DSEN_SHIFT                (9U)
20283 /*! DSEN - Enables Write Data strobe in a byte lane
20284  */
20285 #define DDRPHY_DX0GCR1_DSEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DSEN_SHIFT)) & DDRPHY_DX0GCR1_DSEN_MASK)
20286 #define DDRPHY_DX0GCR1_TEEN_MASK                 (0x400U)
20287 #define DDRPHY_DX0GCR1_TEEN_SHIFT                (10U)
20288 /*! TEEN - Enables ODT/TE in a byte lane
20289  */
20290 #define DDRPHY_DX0GCR1_TEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_TEEN_SHIFT)) & DDRPHY_DX0GCR1_TEEN_MASK)
20291 #define DDRPHY_DX0GCR1_PDREN_MASK                (0x800U)
20292 #define DDRPHY_DX0GCR1_PDREN_SHIFT               (11U)
20293 /*! PDREN - Enables PDR in a byte lane
20294  */
20295 #define DDRPHY_DX0GCR1_PDREN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_PDREN_SHIFT)) & DDRPHY_DX0GCR1_PDREN_MASK)
20296 #define DDRPHY_DX0GCR1_OEEN_MASK                 (0x1000U)
20297 #define DDRPHY_DX0GCR1_OEEN_SHIFT                (12U)
20298 /*! OEEN - Enables Read Data Strobe in a byte lane
20299  */
20300 #define DDRPHY_DX0GCR1_OEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_OEEN_SHIFT)) & DDRPHY_DX0GCR1_OEEN_MASK)
20301 #define DDRPHY_DX0GCR1_QSSEL_MASK                (0x2000U)
20302 #define DDRPHY_DX0GCR1_QSSEL_SHIFT               (13U)
20303 /*! QSSEL - Select the delayed or non-delayed read data strobe
20304  */
20305 #define DDRPHY_DX0GCR1_QSSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_QSSEL_SHIFT)) & DDRPHY_DX0GCR1_QSSEL_MASK)
20306 #define DDRPHY_DX0GCR1_QSNSEL_MASK               (0x4000U)
20307 #define DDRPHY_DX0GCR1_QSNSEL_SHIFT              (14U)
20308 /*! QSNSEL - Select the delayed or non-delayed read data strobe #
20309  */
20310 #define DDRPHY_DX0GCR1_QSNSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_QSNSEL_SHIFT)) & DDRPHY_DX0GCR1_QSNSEL_MASK)
20311 #define DDRPHY_DX0GCR1_RESERVED_15_MASK          (0x8000U)
20312 #define DDRPHY_DX0GCR1_RESERVED_15_SHIFT         (15U)
20313 /*! RESERVED_15 - Reserved. Returns zeroes on reads.
20314  */
20315 #define DDRPHY_DX0GCR1_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX0GCR1_RESERVED_15_MASK)
20316 #define DDRPHY_DX0GCR1_DXPDRMODE_MASK            (0xFFFF0000U)
20317 #define DDRPHY_DX0GCR1_DXPDRMODE_SHIFT           (16U)
20318 /*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
20319  */
20320 #define DDRPHY_DX0GCR1_DXPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX0GCR1_DXPDRMODE_MASK)
20321 /*! @} */
20322 
20323 /*! @name DX0GCR2 - DATX8 n General Configuration Register 2 */
20324 /*! @{ */
20325 #define DDRPHY_DX0GCR2_DXTEMODE_MASK             (0xFFFFU)
20326 #define DDRPHY_DX0GCR2_DXTEMODE_SHIFT            (0U)
20327 /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
20328  */
20329 #define DDRPHY_DX0GCR2_DXTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX0GCR2_DXTEMODE_MASK)
20330 #define DDRPHY_DX0GCR2_DXOEMODE_MASK             (0xFFFF0000U)
20331 #define DDRPHY_DX0GCR2_DXOEMODE_SHIFT            (16U)
20332 /*! DXOEMODE - Enables the OE mode values for DQ[7:0]
20333  */
20334 #define DDRPHY_DX0GCR2_DXOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX0GCR2_DXOEMODE_MASK)
20335 /*! @} */
20336 
20337 /*! @name DX0GCR3 - DATX8 n General Configuration Register 3 */
20338 /*! @{ */
20339 #define DDRPHY_DX0GCR3_WDMBVT_MASK               (0x1U)
20340 #define DDRPHY_DX0GCR3_WDMBVT_SHIFT              (0U)
20341 /*! WDMBVT - Write Data Mask BDL VT Compensation
20342  */
20343 #define DDRPHY_DX0GCR3_WDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDMBVT_SHIFT)) & DDRPHY_DX0GCR3_WDMBVT_MASK)
20344 #define DDRPHY_DX0GCR3_RDMBVT_MASK               (0x2U)
20345 #define DDRPHY_DX0GCR3_RDMBVT_SHIFT              (1U)
20346 /*! RDMBVT - Read Data Mask BDL VT Compensation
20347  */
20348 #define DDRPHY_DX0GCR3_RDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RDMBVT_SHIFT)) & DDRPHY_DX0GCR3_RDMBVT_MASK)
20349 #define DDRPHY_DX0GCR3_DSPDRMODE_MASK            (0xCU)
20350 #define DDRPHY_DX0GCR3_DSPDRMODE_SHIFT           (2U)
20351 /*! DSPDRMODE - Enables the PDR mode values for DQS.
20352  */
20353 #define DDRPHY_DX0GCR3_DSPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX0GCR3_DSPDRMODE_MASK)
20354 #define DDRPHY_DX0GCR3_DSTEMODE_MASK             (0x30U)
20355 #define DDRPHY_DX0GCR3_DSTEMODE_SHIFT            (4U)
20356 /*! DSTEMODE - Enables the TE mode values for DQS.
20357  */
20358 #define DDRPHY_DX0GCR3_DSTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSTEMODE_MASK)
20359 #define DDRPHY_DX0GCR3_DSOEMODE_MASK             (0xC0U)
20360 #define DDRPHY_DX0GCR3_DSOEMODE_SHIFT            (6U)
20361 /*! DSOEMODE - Enables the OE mode values for DQS.
20362  */
20363 #define DDRPHY_DX0GCR3_DSOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSOEMODE_MASK)
20364 #define DDRPHY_DX0GCR3_WDSBVT_MASK               (0x100U)
20365 #define DDRPHY_DX0GCR3_WDSBVT_SHIFT              (8U)
20366 /*! WDSBVT - Write Data Strobe BDL VT Compensation
20367  */
20368 #define DDRPHY_DX0GCR3_WDSBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDSBVT_SHIFT)) & DDRPHY_DX0GCR3_WDSBVT_MASK)
20369 #define DDRPHY_DX0GCR3_RESERVED_9_MASK           (0x200U)
20370 #define DDRPHY_DX0GCR3_RESERVED_9_SHIFT          (9U)
20371 /*! RESERVED_9 - Reserved. Returns zeroes on reads.
20372  */
20373 #define DDRPHY_DX0GCR3_RESERVED_9(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX0GCR3_RESERVED_9_MASK)
20374 #define DDRPHY_DX0GCR3_DMPDRMODE_MASK            (0xC00U)
20375 #define DDRPHY_DX0GCR3_DMPDRMODE_SHIFT           (10U)
20376 /*! DMPDRMODE - Enables the PDR mode values for DM.
20377  */
20378 #define DDRPHY_DX0GCR3_DMPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX0GCR3_DMPDRMODE_MASK)
20379 #define DDRPHY_DX0GCR3_DMTEMODE_MASK             (0x3000U)
20380 #define DDRPHY_DX0GCR3_DMTEMODE_SHIFT            (12U)
20381 /*! DMTEMODE - Enables the TE mode values for DM.
20382  */
20383 #define DDRPHY_DX0GCR3_DMTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX0GCR3_DMTEMODE_MASK)
20384 #define DDRPHY_DX0GCR3_DMOEMODE_MASK             (0xC000U)
20385 #define DDRPHY_DX0GCR3_DMOEMODE_SHIFT            (14U)
20386 /*! DMOEMODE - Enables the OE mode values for DM.
20387  */
20388 #define DDRPHY_DX0GCR3_DMOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX0GCR3_DMOEMODE_MASK)
20389 #define DDRPHY_DX0GCR3_DSNPDRMODE_MASK           (0x30000U)
20390 #define DDRPHY_DX0GCR3_DSNPDRMODE_SHIFT          (16U)
20391 /*! DSNPDRMODE - Enables the PDR mode for DQS
20392  */
20393 #define DDRPHY_DX0GCR3_DSNPDRMODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX0GCR3_DSNPDRMODE_MASK)
20394 #define DDRPHY_DX0GCR3_DSNTEMODE_MASK            (0xC0000U)
20395 #define DDRPHY_DX0GCR3_DSNTEMODE_SHIFT           (18U)
20396 /*! DSNTEMODE - Enables the TE mode for DQS
20397  */
20398 #define DDRPHY_DX0GCR3_DSNTEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSNTEMODE_MASK)
20399 #define DDRPHY_DX0GCR3_DSNOEMODE_MASK            (0x300000U)
20400 #define DDRPHY_DX0GCR3_DSNOEMODE_SHIFT           (20U)
20401 /*! DSNOEMODE - Enables the OE mode for DQs
20402  */
20403 #define DDRPHY_DX0GCR3_DSNOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSNOEMODE_MASK)
20404 #define DDRPHY_DX0GCR3_PDRBVT_MASK               (0x400000U)
20405 #define DDRPHY_DX0GCR3_PDRBVT_SHIFT              (22U)
20406 /*! PDRBVT - Power Down Receiver BDL VT Compensation
20407  */
20408 #define DDRPHY_DX0GCR3_PDRBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_PDRBVT_SHIFT)) & DDRPHY_DX0GCR3_PDRBVT_MASK)
20409 #define DDRPHY_DX0GCR3_RGSLVT_MASK               (0x800000U)
20410 #define DDRPHY_DX0GCR3_RGSLVT_SHIFT              (23U)
20411 /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
20412  */
20413 #define DDRPHY_DX0GCR3_RGSLVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RGSLVT_SHIFT)) & DDRPHY_DX0GCR3_RGSLVT_MASK)
20414 #define DDRPHY_DX0GCR3_WLLVT_MASK                (0x1000000U)
20415 #define DDRPHY_DX0GCR3_WLLVT_SHIFT               (24U)
20416 /*! WLLVT - Write Leveling LCDL Delay VT Compensation
20417  */
20418 #define DDRPHY_DX0GCR3_WLLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WLLVT_SHIFT)) & DDRPHY_DX0GCR3_WLLVT_MASK)
20419 #define DDRPHY_DX0GCR3_WDLVT_MASK                (0x2000000U)
20420 #define DDRPHY_DX0GCR3_WDLVT_SHIFT               (25U)
20421 /*! WDLVT - Write DQ LCDL Delay VT Compensation
20422  */
20423 #define DDRPHY_DX0GCR3_WDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDLVT_SHIFT)) & DDRPHY_DX0GCR3_WDLVT_MASK)
20424 #define DDRPHY_DX0GCR3_RDLVT_MASK                (0x4000000U)
20425 #define DDRPHY_DX0GCR3_RDLVT_SHIFT               (26U)
20426 /*! RDLVT - Read DQS LCDL Delay VT Compensation
20427  */
20428 #define DDRPHY_DX0GCR3_RDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RDLVT_SHIFT)) & DDRPHY_DX0GCR3_RDLVT_MASK)
20429 #define DDRPHY_DX0GCR3_RGLVT_MASK                (0x8000000U)
20430 #define DDRPHY_DX0GCR3_RGLVT_SHIFT               (27U)
20431 /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
20432  */
20433 #define DDRPHY_DX0GCR3_RGLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RGLVT_SHIFT)) & DDRPHY_DX0GCR3_RGLVT_MASK)
20434 #define DDRPHY_DX0GCR3_WDBVT_MASK                (0x10000000U)
20435 #define DDRPHY_DX0GCR3_WDBVT_SHIFT               (28U)
20436 /*! WDBVT - Write Data BDL VT Compensation
20437  */
20438 #define DDRPHY_DX0GCR3_WDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDBVT_SHIFT)) & DDRPHY_DX0GCR3_WDBVT_MASK)
20439 #define DDRPHY_DX0GCR3_RDBVT_MASK                (0x20000000U)
20440 #define DDRPHY_DX0GCR3_RDBVT_SHIFT               (29U)
20441 /*! RDBVT - Read Data BDL VT Compensation
20442  */
20443 #define DDRPHY_DX0GCR3_RDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RDBVT_SHIFT)) & DDRPHY_DX0GCR3_RDBVT_MASK)
20444 #define DDRPHY_DX0GCR3_TEBVT_MASK                (0x40000000U)
20445 #define DDRPHY_DX0GCR3_TEBVT_SHIFT               (30U)
20446 /*! TEBVT - Termination Enable BDL VT Compensation
20447  */
20448 #define DDRPHY_DX0GCR3_TEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_TEBVT_SHIFT)) & DDRPHY_DX0GCR3_TEBVT_MASK)
20449 #define DDRPHY_DX0GCR3_OEBVT_MASK                (0x80000000U)
20450 #define DDRPHY_DX0GCR3_OEBVT_SHIFT               (31U)
20451 /*! OEBVT - Output Enable BDL VT Compensation
20452  */
20453 #define DDRPHY_DX0GCR3_OEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_OEBVT_SHIFT)) & DDRPHY_DX0GCR3_OEBVT_MASK)
20454 /*! @} */
20455 
20456 /*! @name DX0GCR4 - DATX8 n General Configuration Register 4 */
20457 /*! @{ */
20458 #define DDRPHY_DX0GCR4_DXREFIMON_MASK            (0x3U)
20459 #define DDRPHY_DX0GCR4_DXREFIMON_SHIFT           (0U)
20460 /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
20461  */
20462 #define DDRPHY_DX0GCR4_DXREFIMON(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX0GCR4_DXREFIMON_MASK)
20463 #define DDRPHY_DX0GCR4_DXREFIEN_MASK             (0x3CU)
20464 #define DDRPHY_DX0GCR4_DXREFIEN_SHIFT            (2U)
20465 /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
20466  */
20467 #define DDRPHY_DX0GCR4_DXREFIEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFIEN_MASK)
20468 #define DDRPHY_DX0GCR4_RESERVED_7_6_MASK         (0xC0U)
20469 #define DDRPHY_DX0GCR4_RESERVED_7_6_SHIFT        (6U)
20470 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
20471  */
20472 #define DDRPHY_DX0GCR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR4_RESERVED_7_6_MASK)
20473 #define DDRPHY_DX0GCR4_DXREFSSEL_MASK            (0x7F00U)
20474 #define DDRPHY_DX0GCR4_DXREFSSEL_SHIFT           (8U)
20475 /*! DXREFSSEL - Byte Lane Single-End VREF Select
20476  */
20477 #define DDRPHY_DX0GCR4_DXREFSSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX0GCR4_DXREFSSEL_MASK)
20478 #define DDRPHY_DX0GCR4_DXREFSSELRANGE_MASK       (0x8000U)
20479 #define DDRPHY_DX0GCR4_DXREFSSELRANGE_SHIFT      (15U)
20480 /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
20481  */
20482 #define DDRPHY_DX0GCR4_DXREFSSELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX0GCR4_DXREFSSELRANGE_MASK)
20483 #define DDRPHY_DX0GCR4_DXREFESEL_MASK            (0x7F0000U)
20484 #define DDRPHY_DX0GCR4_DXREFESEL_SHIFT           (16U)
20485 /*! DXREFESEL - Byte Lane External VREF Select
20486  */
20487 #define DDRPHY_DX0GCR4_DXREFESEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX0GCR4_DXREFESEL_MASK)
20488 #define DDRPHY_DX0GCR4_DXREFESELRANGE_MASK       (0x800000U)
20489 #define DDRPHY_DX0GCR4_DXREFESELRANGE_SHIFT      (23U)
20490 /*! DXREFESELRANGE - External VREF generator REFSEL range select
20491  */
20492 #define DDRPHY_DX0GCR4_DXREFESELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX0GCR4_DXREFESELRANGE_MASK)
20493 #define DDRPHY_DX0GCR4_RESERVED_24_MASK          (0x1000000U)
20494 #define DDRPHY_DX0GCR4_RESERVED_24_SHIFT         (24U)
20495 /*! RESERVED_24 - Reserved. Returns zeros on reads.
20496  */
20497 #define DDRPHY_DX0GCR4_RESERVED_24(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX0GCR4_RESERVED_24_MASK)
20498 #define DDRPHY_DX0GCR4_DXREFSEN_MASK             (0x2000000U)
20499 #define DDRPHY_DX0GCR4_DXREFSEN_SHIFT            (25U)
20500 /*! DXREFSEN - Byte Lane Single-End VREF Enable
20501  */
20502 #define DDRPHY_DX0GCR4_DXREFSEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFSEN_MASK)
20503 #define DDRPHY_DX0GCR4_DXREFEEN_MASK             (0xC000000U)
20504 #define DDRPHY_DX0GCR4_DXREFEEN_SHIFT            (26U)
20505 /*! DXREFEEN - Byte Lane Internal VREF Enable
20506  */
20507 #define DDRPHY_DX0GCR4_DXREFEEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFEEN_MASK)
20508 #define DDRPHY_DX0GCR4_DXREFPEN_MASK             (0x10000000U)
20509 #define DDRPHY_DX0GCR4_DXREFPEN_SHIFT            (28U)
20510 /*! DXREFPEN - Byte Lane VREF Pad Enable
20511  */
20512 #define DDRPHY_DX0GCR4_DXREFPEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFPEN_MASK)
20513 #define DDRPHY_DX0GCR4_RESERVED_31_29_MASK       (0xE0000000U)
20514 #define DDRPHY_DX0GCR4_RESERVED_31_29_SHIFT      (29U)
20515 /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
20516  */
20517 #define DDRPHY_DX0GCR4_RESERVED_31_29(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX0GCR4_RESERVED_31_29_MASK)
20518 /*! @} */
20519 
20520 /*! @name DX0GCR5 - DATX8 n General Configuration Register 5 */
20521 /*! @{ */
20522 #define DDRPHY_DX0GCR5_DXREFISELR0_MASK          (0x7FU)
20523 #define DDRPHY_DX0GCR5_DXREFISELR0_SHIFT         (0U)
20524 /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
20525  */
20526 #define DDRPHY_DX0GCR5_DXREFISELR0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR0_MASK)
20527 #define DDRPHY_DX0GCR5_RESERVED_7_MASK           (0x80U)
20528 #define DDRPHY_DX0GCR5_RESERVED_7_SHIFT          (7U)
20529 /*! RESERVED_7 - Reserved. Returns zeros on reads.
20530  */
20531 #define DDRPHY_DX0GCR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_7_MASK)
20532 #define DDRPHY_DX0GCR5_DXREFISELR1_MASK          (0x7F00U)
20533 #define DDRPHY_DX0GCR5_DXREFISELR1_SHIFT         (8U)
20534 /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
20535  */
20536 #define DDRPHY_DX0GCR5_DXREFISELR1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR1_MASK)
20537 #define DDRPHY_DX0GCR5_RESERVED_15_MASK          (0x8000U)
20538 #define DDRPHY_DX0GCR5_RESERVED_15_SHIFT         (15U)
20539 /*! RESERVED_15 - Reserved. Returns zeros on reads.
20540  */
20541 #define DDRPHY_DX0GCR5_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_15_MASK)
20542 #define DDRPHY_DX0GCR5_DXREFISELR2_MASK          (0x7F0000U)
20543 #define DDRPHY_DX0GCR5_DXREFISELR2_SHIFT         (16U)
20544 /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
20545  */
20546 #define DDRPHY_DX0GCR5_DXREFISELR2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR2_MASK)
20547 #define DDRPHY_DX0GCR5_RESERVED_23_MASK          (0x800000U)
20548 #define DDRPHY_DX0GCR5_RESERVED_23_SHIFT         (23U)
20549 /*! RESERVED_23 - Reserved. Returns zeros on reads.
20550  */
20551 #define DDRPHY_DX0GCR5_RESERVED_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_23_MASK)
20552 #define DDRPHY_DX0GCR5_DXREFISELR3_MASK          (0x7F000000U)
20553 #define DDRPHY_DX0GCR5_DXREFISELR3_SHIFT         (24U)
20554 /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
20555  */
20556 #define DDRPHY_DX0GCR5_DXREFISELR3(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR3_MASK)
20557 #define DDRPHY_DX0GCR5_RESERVED_31_MASK          (0x80000000U)
20558 #define DDRPHY_DX0GCR5_RESERVED_31_SHIFT         (31U)
20559 /*! RESERVED_31 - Reserved. Returns zeros on reads.
20560  */
20561 #define DDRPHY_DX0GCR5_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_31_MASK)
20562 /*! @} */
20563 
20564 /*! @name DX0GCR6 - DATX8 n General Configuration Register 6 */
20565 /*! @{ */
20566 #define DDRPHY_DX0GCR6_DXDQVREFR0_MASK           (0x3FU)
20567 #define DDRPHY_DX0GCR6_DXDQVREFR0_SHIFT          (0U)
20568 /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
20569  */
20570 #define DDRPHY_DX0GCR6_DXDQVREFR0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR0_MASK)
20571 #define DDRPHY_DX0GCR6_RESERVED_7_6_MASK         (0xC0U)
20572 #define DDRPHY_DX0GCR6_RESERVED_7_6_SHIFT        (6U)
20573 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
20574  */
20575 #define DDRPHY_DX0GCR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_7_6_MASK)
20576 #define DDRPHY_DX0GCR6_DXDQVREFR1_MASK           (0x3F00U)
20577 #define DDRPHY_DX0GCR6_DXDQVREFR1_SHIFT          (8U)
20578 /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
20579  */
20580 #define DDRPHY_DX0GCR6_DXDQVREFR1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR1_MASK)
20581 #define DDRPHY_DX0GCR6_RESERVED_15_14_MASK       (0xC000U)
20582 #define DDRPHY_DX0GCR6_RESERVED_15_14_SHIFT      (14U)
20583 /*! RESERVED_15_14 - Reserved. Returns zeros on reads.
20584  */
20585 #define DDRPHY_DX0GCR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_15_14_MASK)
20586 #define DDRPHY_DX0GCR6_DXDQVREFR2_MASK           (0x3F0000U)
20587 #define DDRPHY_DX0GCR6_DXDQVREFR2_SHIFT          (16U)
20588 /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
20589  */
20590 #define DDRPHY_DX0GCR6_DXDQVREFR2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR2_MASK)
20591 #define DDRPHY_DX0GCR6_RESERVED_23_22_MASK       (0xC00000U)
20592 #define DDRPHY_DX0GCR6_RESERVED_23_22_SHIFT      (22U)
20593 /*! RESERVED_23_22 - Reserved. Returns zeros on reads.
20594  */
20595 #define DDRPHY_DX0GCR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_23_22_MASK)
20596 #define DDRPHY_DX0GCR6_DXDQVREFR3_MASK           (0x3F000000U)
20597 #define DDRPHY_DX0GCR6_DXDQVREFR3_SHIFT          (24U)
20598 /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
20599  */
20600 #define DDRPHY_DX0GCR6_DXDQVREFR3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR3_MASK)
20601 #define DDRPHY_DX0GCR6_RESERVED_31_30_MASK       (0xC0000000U)
20602 #define DDRPHY_DX0GCR6_RESERVED_31_30_SHIFT      (30U)
20603 /*! RESERVED_31_30 - Reserved. Returns zeros on reads.
20604  */
20605 #define DDRPHY_DX0GCR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_31_30_MASK)
20606 /*! @} */
20607 
20608 /*! @name DX0GCR7 - DATX8 n General Configuration Register 7 */
20609 /*! @{ */
20610 #define DDRPHY_DX0GCR7_DCALSVAL_MASK             (0x1FFU)
20611 #define DDRPHY_DX0GCR7_DCALSVAL_SHIFT            (0U)
20612 /*! DCALSVAL - DDL Calibration Starting Value
20613  */
20614 #define DDRPHY_DX0GCR7_DCALSVAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX0GCR7_DCALSVAL_MASK)
20615 #define DDRPHY_DX0GCR7_DCALTYPE_MASK             (0x200U)
20616 #define DDRPHY_DX0GCR7_DCALTYPE_SHIFT            (9U)
20617 /*! DCALTYPE - DDL Calibration Type
20618  */
20619 #define DDRPHY_DX0GCR7_DCALTYPE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX0GCR7_DCALTYPE_MASK)
20620 #define DDRPHY_DX0GCR7_RESERVED_17_10_MASK       (0x3FC00U)
20621 #define DDRPHY_DX0GCR7_RESERVED_17_10_SHIFT      (10U)
20622 /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
20623  */
20624 #define DDRPHY_DX0GCR7_RESERVED_17_10(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX0GCR7_RESERVED_17_10_MASK)
20625 #define DDRPHY_DX0GCR7_RESERVED_18_MASK          (0x40000U)
20626 #define DDRPHY_DX0GCR7_RESERVED_18_SHIFT         (18U)
20627 /*! RESERVED_18 - Reserved. Caution, do not write to this register field.
20628  */
20629 #define DDRPHY_DX0GCR7_RESERVED_18(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX0GCR7_RESERVED_18_MASK)
20630 #define DDRPHY_DX0GCR7_RESERVED_31_19_MASK       (0xFFF80000U)
20631 #define DDRPHY_DX0GCR7_RESERVED_31_19_SHIFT      (19U)
20632 /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
20633  */
20634 #define DDRPHY_DX0GCR7_RESERVED_31_19(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX0GCR7_RESERVED_31_19_MASK)
20635 /*! @} */
20636 
20637 /*! @name DX0GCR8 - DATX8 n General Configuration Register 8 */
20638 /*! @{ */
20639 #define DDRPHY_DX0GCR8_RESERVED_5_0_MASK         (0x3FU)
20640 #define DDRPHY_DX0GCR8_RESERVED_5_0_SHIFT        (0U)
20641 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
20642  */
20643 #define DDRPHY_DX0GCR8_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_5_0_MASK)
20644 #define DDRPHY_DX0GCR8_RESERVED_7_6_MASK         (0xC0U)
20645 #define DDRPHY_DX0GCR8_RESERVED_7_6_SHIFT        (6U)
20646 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20647  */
20648 #define DDRPHY_DX0GCR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_7_6_MASK)
20649 #define DDRPHY_DX0GCR8_RESERVED_13_8_MASK        (0x3F00U)
20650 #define DDRPHY_DX0GCR8_RESERVED_13_8_SHIFT       (8U)
20651 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
20652  */
20653 #define DDRPHY_DX0GCR8_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_13_8_MASK)
20654 #define DDRPHY_DX0GCR8_RESERVED_15_14_MASK       (0xC000U)
20655 #define DDRPHY_DX0GCR8_RESERVED_15_14_SHIFT      (14U)
20656 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20657  */
20658 #define DDRPHY_DX0GCR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_15_14_MASK)
20659 #define DDRPHY_DX0GCR8_RESERVED_21_16_MASK       (0x3F0000U)
20660 #define DDRPHY_DX0GCR8_RESERVED_21_16_SHIFT      (16U)
20661 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
20662  */
20663 #define DDRPHY_DX0GCR8_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_21_16_MASK)
20664 #define DDRPHY_DX0GCR8_RESERVED_23_22_MASK       (0xC00000U)
20665 #define DDRPHY_DX0GCR8_RESERVED_23_22_SHIFT      (22U)
20666 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20667  */
20668 #define DDRPHY_DX0GCR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_23_22_MASK)
20669 #define DDRPHY_DX0GCR8_RESERVED_29_24_MASK       (0x3F000000U)
20670 #define DDRPHY_DX0GCR8_RESERVED_29_24_SHIFT      (24U)
20671 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
20672  */
20673 #define DDRPHY_DX0GCR8_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_29_24_MASK)
20674 #define DDRPHY_DX0GCR8_RESERVED_31_30_MASK       (0xC0000000U)
20675 #define DDRPHY_DX0GCR8_RESERVED_31_30_SHIFT      (30U)
20676 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20677  */
20678 #define DDRPHY_DX0GCR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_31_30_MASK)
20679 /*! @} */
20680 
20681 /*! @name DX0GCR9 - DATX8 n General Configuration Register 9 */
20682 /*! @{ */
20683 #define DDRPHY_DX0GCR9_RESERVED_5_0_MASK         (0x3FU)
20684 #define DDRPHY_DX0GCR9_RESERVED_5_0_SHIFT        (0U)
20685 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
20686  */
20687 #define DDRPHY_DX0GCR9_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_5_0_MASK)
20688 #define DDRPHY_DX0GCR9_RESERVED_7_6_MASK         (0xC0U)
20689 #define DDRPHY_DX0GCR9_RESERVED_7_6_SHIFT        (6U)
20690 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20691  */
20692 #define DDRPHY_DX0GCR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_7_6_MASK)
20693 #define DDRPHY_DX0GCR9_RESERVED_13_8_MASK        (0x3F00U)
20694 #define DDRPHY_DX0GCR9_RESERVED_13_8_SHIFT       (8U)
20695 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
20696  */
20697 #define DDRPHY_DX0GCR9_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_13_8_MASK)
20698 #define DDRPHY_DX0GCR9_RESERVED_15_14_MASK       (0xC000U)
20699 #define DDRPHY_DX0GCR9_RESERVED_15_14_SHIFT      (14U)
20700 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20701  */
20702 #define DDRPHY_DX0GCR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_15_14_MASK)
20703 #define DDRPHY_DX0GCR9_RESERVED_21_16_MASK       (0x3F0000U)
20704 #define DDRPHY_DX0GCR9_RESERVED_21_16_SHIFT      (16U)
20705 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
20706  */
20707 #define DDRPHY_DX0GCR9_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_21_16_MASK)
20708 #define DDRPHY_DX0GCR9_RESERVED_23_22_MASK       (0xC00000U)
20709 #define DDRPHY_DX0GCR9_RESERVED_23_22_SHIFT      (22U)
20710 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20711  */
20712 #define DDRPHY_DX0GCR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_23_22_MASK)
20713 #define DDRPHY_DX0GCR9_RESERVED_29_24_MASK       (0x3F000000U)
20714 #define DDRPHY_DX0GCR9_RESERVED_29_24_SHIFT      (24U)
20715 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
20716  */
20717 #define DDRPHY_DX0GCR9_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_29_24_MASK)
20718 #define DDRPHY_DX0GCR9_RESERVED_31_30_MASK       (0xC0000000U)
20719 #define DDRPHY_DX0GCR9_RESERVED_31_30_SHIFT      (30U)
20720 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20721  */
20722 #define DDRPHY_DX0GCR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_31_30_MASK)
20723 /*! @} */
20724 
20725 /*! @name DX0DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
20726 /*! @{ */
20727 #define DDRPHY_DX0DQMAP0_DQ0MAP_MASK             (0xFU)
20728 #define DDRPHY_DX0DQMAP0_DQ0MAP_SHIFT            (0U)
20729 /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
20730  */
20731 #define DDRPHY_DX0DQMAP0_DQ0MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ0MAP_MASK)
20732 #define DDRPHY_DX0DQMAP0_DQ1MAP_MASK             (0xF0U)
20733 #define DDRPHY_DX0DQMAP0_DQ1MAP_SHIFT            (4U)
20734 /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
20735  */
20736 #define DDRPHY_DX0DQMAP0_DQ1MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ1MAP_MASK)
20737 #define DDRPHY_DX0DQMAP0_DQ2MAP_MASK             (0xF00U)
20738 #define DDRPHY_DX0DQMAP0_DQ2MAP_SHIFT            (8U)
20739 /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
20740  */
20741 #define DDRPHY_DX0DQMAP0_DQ2MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ2MAP_MASK)
20742 #define DDRPHY_DX0DQMAP0_DQ3MAP_MASK             (0xF000U)
20743 #define DDRPHY_DX0DQMAP0_DQ3MAP_SHIFT            (12U)
20744 /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
20745  */
20746 #define DDRPHY_DX0DQMAP0_DQ3MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ3MAP_MASK)
20747 #define DDRPHY_DX0DQMAP0_DQ4MAP_MASK             (0xF0000U)
20748 #define DDRPHY_DX0DQMAP0_DQ4MAP_SHIFT            (16U)
20749 /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
20750  */
20751 #define DDRPHY_DX0DQMAP0_DQ4MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ4MAP_MASK)
20752 #define DDRPHY_DX0DQMAP0_RESERVED_30_20_MASK     (0x7FF00000U)
20753 #define DDRPHY_DX0DQMAP0_RESERVED_30_20_SHIFT    (20U)
20754 /*! RESERVED_30_20 - Reserved. Return zeroes on reads.
20755  */
20756 #define DDRPHY_DX0DQMAP0_RESERVED_30_20(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX0DQMAP0_RESERVED_30_20_MASK)
20757 #define DDRPHY_DX0DQMAP0_MAPOK_MASK              (0x80000000U)
20758 #define DDRPHY_DX0DQMAP0_MAPOK_SHIFT             (31U)
20759 /*! MAPOK - Checksum bit
20760  */
20761 #define DDRPHY_DX0DQMAP0_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX0DQMAP0_MAPOK_MASK)
20762 /*! @} */
20763 
20764 /*! @name DX0DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
20765 /*! @{ */
20766 #define DDRPHY_DX0DQMAP1_DQ5MAP_MASK             (0xFU)
20767 #define DDRPHY_DX0DQMAP1_DQ5MAP_SHIFT            (0U)
20768 /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
20769  */
20770 #define DDRPHY_DX0DQMAP1_DQ5MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX0DQMAP1_DQ5MAP_MASK)
20771 #define DDRPHY_DX0DQMAP1_DQ6MAP_MASK             (0xF0U)
20772 #define DDRPHY_DX0DQMAP1_DQ6MAP_SHIFT            (4U)
20773 /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
20774  */
20775 #define DDRPHY_DX0DQMAP1_DQ6MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX0DQMAP1_DQ6MAP_MASK)
20776 #define DDRPHY_DX0DQMAP1_DQ7MAP_MASK             (0xF00U)
20777 #define DDRPHY_DX0DQMAP1_DQ7MAP_SHIFT            (8U)
20778 /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
20779  */
20780 #define DDRPHY_DX0DQMAP1_DQ7MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX0DQMAP1_DQ7MAP_MASK)
20781 #define DDRPHY_DX0DQMAP1_DMMAP_MASK              (0xF000U)
20782 #define DDRPHY_DX0DQMAP1_DMMAP_SHIFT             (12U)
20783 /*! DMMAP - DM bit DATX8 slice mapping index
20784  */
20785 #define DDRPHY_DX0DQMAP1_DMMAP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX0DQMAP1_DMMAP_MASK)
20786 #define DDRPHY_DX0DQMAP1_RESERVED_30_16_MASK     (0x7FFF0000U)
20787 #define DDRPHY_DX0DQMAP1_RESERVED_30_16_SHIFT    (16U)
20788 /*! RESERVED_30_16 - Reserved. Return zeroes on reads.
20789  */
20790 #define DDRPHY_DX0DQMAP1_RESERVED_30_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX0DQMAP1_RESERVED_30_16_MASK)
20791 #define DDRPHY_DX0DQMAP1_MAPOK_MASK              (0x80000000U)
20792 #define DDRPHY_DX0DQMAP1_MAPOK_SHIFT             (31U)
20793 /*! MAPOK - Checksum bit
20794  */
20795 #define DDRPHY_DX0DQMAP1_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX0DQMAP1_MAPOK_MASK)
20796 /*! @} */
20797 
20798 /*! @name DX0BDLR0 - DATX8 n Bit Delay Line Register 0 */
20799 /*! @{ */
20800 #define DDRPHY_DX0BDLR0_DQ0WBD_MASK              (0x3FU)
20801 #define DDRPHY_DX0BDLR0_DQ0WBD_SHIFT             (0U)
20802 /*! DQ0WBD - DQ0 Write Bit Delay
20803  */
20804 #define DDRPHY_DX0BDLR0_DQ0WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ0WBD_MASK)
20805 #define DDRPHY_DX0BDLR0_RESERVED_7_6_MASK        (0xC0U)
20806 #define DDRPHY_DX0BDLR0_RESERVED_7_6_SHIFT       (6U)
20807 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20808  */
20809 #define DDRPHY_DX0BDLR0_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_7_6_MASK)
20810 #define DDRPHY_DX0BDLR0_DQ1WBD_MASK              (0x3F00U)
20811 #define DDRPHY_DX0BDLR0_DQ1WBD_SHIFT             (8U)
20812 /*! DQ1WBD - DQ1 Write Bit Delay
20813  */
20814 #define DDRPHY_DX0BDLR0_DQ1WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ1WBD_MASK)
20815 #define DDRPHY_DX0BDLR0_RESERVED_15_14_MASK      (0xC000U)
20816 #define DDRPHY_DX0BDLR0_RESERVED_15_14_SHIFT     (14U)
20817 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20818  */
20819 #define DDRPHY_DX0BDLR0_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_15_14_MASK)
20820 #define DDRPHY_DX0BDLR0_DQ2WBD_MASK              (0x3F0000U)
20821 #define DDRPHY_DX0BDLR0_DQ2WBD_SHIFT             (16U)
20822 /*! DQ2WBD - DQ2 Write Bit Delay
20823  */
20824 #define DDRPHY_DX0BDLR0_DQ2WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ2WBD_MASK)
20825 #define DDRPHY_DX0BDLR0_RESERVED_23_22_MASK      (0xC00000U)
20826 #define DDRPHY_DX0BDLR0_RESERVED_23_22_SHIFT     (22U)
20827 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20828  */
20829 #define DDRPHY_DX0BDLR0_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_23_22_MASK)
20830 #define DDRPHY_DX0BDLR0_DQ3WBD_MASK              (0x3F000000U)
20831 #define DDRPHY_DX0BDLR0_DQ3WBD_SHIFT             (24U)
20832 /*! DQ3WBD - DQ3 Write Bit Delay
20833  */
20834 #define DDRPHY_DX0BDLR0_DQ3WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ3WBD_MASK)
20835 #define DDRPHY_DX0BDLR0_RESERVED_31_30_MASK      (0xC0000000U)
20836 #define DDRPHY_DX0BDLR0_RESERVED_31_30_SHIFT     (30U)
20837 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20838  */
20839 #define DDRPHY_DX0BDLR0_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_31_30_MASK)
20840 /*! @} */
20841 
20842 /*! @name DX0BDLR1 - DATX8 n Bit Delay Line Register 1 */
20843 /*! @{ */
20844 #define DDRPHY_DX0BDLR1_DQ4WBD_MASK              (0x3FU)
20845 #define DDRPHY_DX0BDLR1_DQ4WBD_SHIFT             (0U)
20846 /*! DQ4WBD - DQ4 Write Bit Delay
20847  */
20848 #define DDRPHY_DX0BDLR1_DQ4WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ4WBD_MASK)
20849 #define DDRPHY_DX0BDLR1_RESERVED_7_6_MASK        (0xC0U)
20850 #define DDRPHY_DX0BDLR1_RESERVED_7_6_SHIFT       (6U)
20851 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20852  */
20853 #define DDRPHY_DX0BDLR1_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_7_6_MASK)
20854 #define DDRPHY_DX0BDLR1_DQ5WBD_MASK              (0x3F00U)
20855 #define DDRPHY_DX0BDLR1_DQ5WBD_SHIFT             (8U)
20856 /*! DQ5WBD - DQ5 Write Bit Delay
20857  */
20858 #define DDRPHY_DX0BDLR1_DQ5WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ5WBD_MASK)
20859 #define DDRPHY_DX0BDLR1_RESERVED_15_14_MASK      (0xC000U)
20860 #define DDRPHY_DX0BDLR1_RESERVED_15_14_SHIFT     (14U)
20861 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20862  */
20863 #define DDRPHY_DX0BDLR1_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_15_14_MASK)
20864 #define DDRPHY_DX0BDLR1_DQ6WBD_MASK              (0x3F0000U)
20865 #define DDRPHY_DX0BDLR1_DQ6WBD_SHIFT             (16U)
20866 /*! DQ6WBD - DQ6 Write Bit Delay
20867  */
20868 #define DDRPHY_DX0BDLR1_DQ6WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ6WBD_MASK)
20869 #define DDRPHY_DX0BDLR1_RESERVED_23_22_MASK      (0xC00000U)
20870 #define DDRPHY_DX0BDLR1_RESERVED_23_22_SHIFT     (22U)
20871 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20872  */
20873 #define DDRPHY_DX0BDLR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_23_22_MASK)
20874 #define DDRPHY_DX0BDLR1_DQ7WBD_MASK              (0x3F000000U)
20875 #define DDRPHY_DX0BDLR1_DQ7WBD_SHIFT             (24U)
20876 /*! DQ7WBD - DQ7 Write Bit Delay
20877  */
20878 #define DDRPHY_DX0BDLR1_DQ7WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ7WBD_MASK)
20879 #define DDRPHY_DX0BDLR1_RESERVED_31_30_MASK      (0xC0000000U)
20880 #define DDRPHY_DX0BDLR1_RESERVED_31_30_SHIFT     (30U)
20881 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20882  */
20883 #define DDRPHY_DX0BDLR1_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_31_30_MASK)
20884 /*! @} */
20885 
20886 /*! @name DX0BDLR2 - DATX8 n Bit Delay Line Register 2 */
20887 /*! @{ */
20888 #define DDRPHY_DX0BDLR2_DMWBD_MASK               (0x3FU)
20889 #define DDRPHY_DX0BDLR2_DMWBD_SHIFT              (0U)
20890 /*! DMWBD - DM Write Bit Delay
20891  */
20892 #define DDRPHY_DX0BDLR2_DMWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DMWBD_SHIFT)) & DDRPHY_DX0BDLR2_DMWBD_MASK)
20893 #define DDRPHY_DX0BDLR2_RESERVED_7_6_MASK        (0xC0U)
20894 #define DDRPHY_DX0BDLR2_RESERVED_7_6_SHIFT       (6U)
20895 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20896  */
20897 #define DDRPHY_DX0BDLR2_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_7_6_MASK)
20898 #define DDRPHY_DX0BDLR2_DSWBD_MASK               (0x3F00U)
20899 #define DDRPHY_DX0BDLR2_DSWBD_SHIFT              (8U)
20900 /*! DSWBD - DQS Write Bit Delay
20901  */
20902 #define DDRPHY_DX0BDLR2_DSWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DSWBD_SHIFT)) & DDRPHY_DX0BDLR2_DSWBD_MASK)
20903 #define DDRPHY_DX0BDLR2_RESERVED_15_14_MASK      (0xC000U)
20904 #define DDRPHY_DX0BDLR2_RESERVED_15_14_SHIFT     (14U)
20905 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20906  */
20907 #define DDRPHY_DX0BDLR2_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_15_14_MASK)
20908 #define DDRPHY_DX0BDLR2_DSOEBD_MASK              (0x3F0000U)
20909 #define DDRPHY_DX0BDLR2_DSOEBD_SHIFT             (16U)
20910 /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
20911  */
20912 #define DDRPHY_DX0BDLR2_DSOEBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX0BDLR2_DSOEBD_MASK)
20913 #define DDRPHY_DX0BDLR2_RESERVED_23_22_MASK      (0xC00000U)
20914 #define DDRPHY_DX0BDLR2_RESERVED_23_22_SHIFT     (22U)
20915 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20916  */
20917 #define DDRPHY_DX0BDLR2_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_23_22_MASK)
20918 #define DDRPHY_DX0BDLR2_DSNWBD_MASK              (0x3F000000U)
20919 #define DDRPHY_DX0BDLR2_DSNWBD_SHIFT             (24U)
20920 /*! DSNWBD - DQSN Write Bit Delay
20921  */
20922 #define DDRPHY_DX0BDLR2_DSNWBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX0BDLR2_DSNWBD_MASK)
20923 #define DDRPHY_DX0BDLR2_RESERVED_31_30_MASK      (0xC0000000U)
20924 #define DDRPHY_DX0BDLR2_RESERVED_31_30_SHIFT     (30U)
20925 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20926  */
20927 #define DDRPHY_DX0BDLR2_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_31_30_MASK)
20928 /*! @} */
20929 
20930 /*! @name DX0BDLR3 - DATX8 n Bit Delay Line Register 3 */
20931 /*! @{ */
20932 #define DDRPHY_DX0BDLR3_DQ0RBD_MASK              (0x3FU)
20933 #define DDRPHY_DX0BDLR3_DQ0RBD_SHIFT             (0U)
20934 /*! DQ0RBD - DQ0 Read Bit Delay
20935  */
20936 #define DDRPHY_DX0BDLR3_DQ0RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ0RBD_MASK)
20937 #define DDRPHY_DX0BDLR3_RESERVED_7_6_MASK        (0xC0U)
20938 #define DDRPHY_DX0BDLR3_RESERVED_7_6_SHIFT       (6U)
20939 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20940  */
20941 #define DDRPHY_DX0BDLR3_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_7_6_MASK)
20942 #define DDRPHY_DX0BDLR3_DQ1RBD_MASK              (0x3F00U)
20943 #define DDRPHY_DX0BDLR3_DQ1RBD_SHIFT             (8U)
20944 /*! DQ1RBD - DQ1 Read Bit Delay
20945  */
20946 #define DDRPHY_DX0BDLR3_DQ1RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ1RBD_MASK)
20947 #define DDRPHY_DX0BDLR3_RESERVED_15_14_MASK      (0xC000U)
20948 #define DDRPHY_DX0BDLR3_RESERVED_15_14_SHIFT     (14U)
20949 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20950  */
20951 #define DDRPHY_DX0BDLR3_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_15_14_MASK)
20952 #define DDRPHY_DX0BDLR3_DQ2RBD_MASK              (0x3F0000U)
20953 #define DDRPHY_DX0BDLR3_DQ2RBD_SHIFT             (16U)
20954 /*! DQ2RBD - DQ2 Read Bit Delay
20955  */
20956 #define DDRPHY_DX0BDLR3_DQ2RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ2RBD_MASK)
20957 #define DDRPHY_DX0BDLR3_RESERVED_23_22_MASK      (0xC00000U)
20958 #define DDRPHY_DX0BDLR3_RESERVED_23_22_SHIFT     (22U)
20959 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20960  */
20961 #define DDRPHY_DX0BDLR3_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_23_22_MASK)
20962 #define DDRPHY_DX0BDLR3_DQ3RBD_MASK              (0x3F000000U)
20963 #define DDRPHY_DX0BDLR3_DQ3RBD_SHIFT             (24U)
20964 /*! DQ3RBD - DQ3 Read Bit Delay
20965  */
20966 #define DDRPHY_DX0BDLR3_DQ3RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ3RBD_MASK)
20967 #define DDRPHY_DX0BDLR3_RESERVED_31_30_MASK      (0xC0000000U)
20968 #define DDRPHY_DX0BDLR3_RESERVED_31_30_SHIFT     (30U)
20969 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20970  */
20971 #define DDRPHY_DX0BDLR3_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_31_30_MASK)
20972 /*! @} */
20973 
20974 /*! @name DX0BDLR4 - DATX8 n Bit Delay Line Register 4 */
20975 /*! @{ */
20976 #define DDRPHY_DX0BDLR4_DQ4RBD_MASK              (0x3FU)
20977 #define DDRPHY_DX0BDLR4_DQ4RBD_SHIFT             (0U)
20978 /*! DQ4RBD - DQ4 Read Bit Delay
20979  */
20980 #define DDRPHY_DX0BDLR4_DQ4RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ4RBD_MASK)
20981 #define DDRPHY_DX0BDLR4_RESERVED_7_6_MASK        (0xC0U)
20982 #define DDRPHY_DX0BDLR4_RESERVED_7_6_SHIFT       (6U)
20983 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20984  */
20985 #define DDRPHY_DX0BDLR4_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_7_6_MASK)
20986 #define DDRPHY_DX0BDLR4_DQ5RBD_MASK              (0x3F00U)
20987 #define DDRPHY_DX0BDLR4_DQ5RBD_SHIFT             (8U)
20988 /*! DQ5RBD - DQ5 Read Bit Delay
20989  */
20990 #define DDRPHY_DX0BDLR4_DQ5RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ5RBD_MASK)
20991 #define DDRPHY_DX0BDLR4_RESERVED_15_14_MASK      (0xC000U)
20992 #define DDRPHY_DX0BDLR4_RESERVED_15_14_SHIFT     (14U)
20993 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20994  */
20995 #define DDRPHY_DX0BDLR4_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_15_14_MASK)
20996 #define DDRPHY_DX0BDLR4_DQ6RBD_MASK              (0x3F0000U)
20997 #define DDRPHY_DX0BDLR4_DQ6RBD_SHIFT             (16U)
20998 /*! DQ6RBD - DQ6 Read Bit Delay
20999  */
21000 #define DDRPHY_DX0BDLR4_DQ6RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ6RBD_MASK)
21001 #define DDRPHY_DX0BDLR4_RESERVED_23_22_MASK      (0xC00000U)
21002 #define DDRPHY_DX0BDLR4_RESERVED_23_22_SHIFT     (22U)
21003 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
21004  */
21005 #define DDRPHY_DX0BDLR4_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_23_22_MASK)
21006 #define DDRPHY_DX0BDLR4_DQ7RBD_MASK              (0x3F000000U)
21007 #define DDRPHY_DX0BDLR4_DQ7RBD_SHIFT             (24U)
21008 /*! DQ7RBD - DQ7 Read Bit Delay
21009  */
21010 #define DDRPHY_DX0BDLR4_DQ7RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ7RBD_MASK)
21011 #define DDRPHY_DX0BDLR4_RESERVED_31_30_MASK      (0xC0000000U)
21012 #define DDRPHY_DX0BDLR4_RESERVED_31_30_SHIFT     (30U)
21013 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
21014  */
21015 #define DDRPHY_DX0BDLR4_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_31_30_MASK)
21016 /*! @} */
21017 
21018 /*! @name DX0BDLR5 - DATX8 n Bit Delay Line Register 5 */
21019 /*! @{ */
21020 #define DDRPHY_DX0BDLR5_DMRBD_MASK               (0x3FU)
21021 #define DDRPHY_DX0BDLR5_DMRBD_SHIFT              (0U)
21022 /*! DMRBD - DM Read Bit Delay
21023  */
21024 #define DDRPHY_DX0BDLR5_DMRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR5_DMRBD_SHIFT)) & DDRPHY_DX0BDLR5_DMRBD_MASK)
21025 #define DDRPHY_DX0BDLR5_RESERVED_31_6_MASK       (0xFFFFFFC0U)
21026 #define DDRPHY_DX0BDLR5_RESERVED_31_6_SHIFT      (6U)
21027 /*! RESERVED_31_6 - Reserved. Return zeroes on reads.
21028  */
21029 #define DDRPHY_DX0BDLR5_RESERVED_31_6(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX0BDLR5_RESERVED_31_6_MASK)
21030 /*! @} */
21031 
21032 /*! @name DX0BDLR6 - DATX8 n Bit Delay Line Register 6 */
21033 /*! @{ */
21034 #define DDRPHY_DX0BDLR6_RESERVED_7_0_MASK        (0xFFU)
21035 #define DDRPHY_DX0BDLR6_RESERVED_7_0_SHIFT       (0U)
21036 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
21037  */
21038 #define DDRPHY_DX0BDLR6_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX0BDLR6_RESERVED_7_0_MASK)
21039 #define DDRPHY_DX0BDLR6_PDRBD_MASK               (0x3F00U)
21040 #define DDRPHY_DX0BDLR6_PDRBD_SHIFT              (8U)
21041 /*! PDRBD - Power down receiver Bit Delay
21042  */
21043 #define DDRPHY_DX0BDLR6_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_PDRBD_SHIFT)) & DDRPHY_DX0BDLR6_PDRBD_MASK)
21044 #define DDRPHY_DX0BDLR6_RESERVED_15_14_MASK      (0xC000U)
21045 #define DDRPHY_DX0BDLR6_RESERVED_15_14_SHIFT     (14U)
21046 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
21047  */
21048 #define DDRPHY_DX0BDLR6_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR6_RESERVED_15_14_MASK)
21049 #define DDRPHY_DX0BDLR6_TERBD_MASK               (0x3F0000U)
21050 #define DDRPHY_DX0BDLR6_TERBD_SHIFT              (16U)
21051 /*! TERBD - Termination Enable Bit Delay
21052  */
21053 #define DDRPHY_DX0BDLR6_TERBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_TERBD_SHIFT)) & DDRPHY_DX0BDLR6_TERBD_MASK)
21054 #define DDRPHY_DX0BDLR6_RESERVED_31_22_MASK      (0xFFC00000U)
21055 #define DDRPHY_DX0BDLR6_RESERVED_31_22_SHIFT     (22U)
21056 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
21057  */
21058 #define DDRPHY_DX0BDLR6_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR6_RESERVED_31_22_MASK)
21059 /*! @} */
21060 
21061 /*! @name DX0BDLR7 - DATX8 n Bit Delay Line Register 7 */
21062 /*! @{ */
21063 #define DDRPHY_DX0BDLR7_RESERVED_5_0_MASK        (0x3FU)
21064 #define DDRPHY_DX0BDLR7_RESERVED_5_0_SHIFT       (0U)
21065 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
21066  */
21067 #define DDRPHY_DX0BDLR7_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_5_0_MASK)
21068 #define DDRPHY_DX0BDLR7_RESERVED_7_6_MASK        (0xC0U)
21069 #define DDRPHY_DX0BDLR7_RESERVED_7_6_SHIFT       (6U)
21070 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
21071  */
21072 #define DDRPHY_DX0BDLR7_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_7_6_MASK)
21073 #define DDRPHY_DX0BDLR7_RESERVED_13_8_MASK       (0x3F00U)
21074 #define DDRPHY_DX0BDLR7_RESERVED_13_8_SHIFT      (8U)
21075 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
21076  */
21077 #define DDRPHY_DX0BDLR7_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_13_8_MASK)
21078 #define DDRPHY_DX0BDLR7_RESERVED_15_14_MASK      (0xC000U)
21079 #define DDRPHY_DX0BDLR7_RESERVED_15_14_SHIFT     (14U)
21080 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
21081  */
21082 #define DDRPHY_DX0BDLR7_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_15_14_MASK)
21083 #define DDRPHY_DX0BDLR7_RESERVED_21_16_MASK      (0x3F0000U)
21084 #define DDRPHY_DX0BDLR7_RESERVED_21_16_SHIFT     (16U)
21085 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
21086  */
21087 #define DDRPHY_DX0BDLR7_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_21_16_MASK)
21088 #define DDRPHY_DX0BDLR7_RESERVED_31_22_MASK      (0xFFC00000U)
21089 #define DDRPHY_DX0BDLR7_RESERVED_31_22_SHIFT     (22U)
21090 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
21091  */
21092 #define DDRPHY_DX0BDLR7_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_31_22_MASK)
21093 /*! @} */
21094 
21095 /*! @name DX0BDLR8 - DATX8 n Bit Delay Line Register 8 */
21096 /*! @{ */
21097 #define DDRPHY_DX0BDLR8_RESERVED_5_0_MASK        (0x3FU)
21098 #define DDRPHY_DX0BDLR8_RESERVED_5_0_SHIFT       (0U)
21099 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
21100  */
21101 #define DDRPHY_DX0BDLR8_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_5_0_MASK)
21102 #define DDRPHY_DX0BDLR8_RESERVED_7_6_MASK        (0xC0U)
21103 #define DDRPHY_DX0BDLR8_RESERVED_7_6_SHIFT       (6U)
21104 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
21105  */
21106 #define DDRPHY_DX0BDLR8_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_7_6_MASK)
21107 #define DDRPHY_DX0BDLR8_RESERVED_13_8_MASK       (0x3F00U)
21108 #define DDRPHY_DX0BDLR8_RESERVED_13_8_SHIFT      (8U)
21109 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
21110  */
21111 #define DDRPHY_DX0BDLR8_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_13_8_MASK)
21112 #define DDRPHY_DX0BDLR8_RESERVED_15_14_MASK      (0xC000U)
21113 #define DDRPHY_DX0BDLR8_RESERVED_15_14_SHIFT     (14U)
21114 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
21115  */
21116 #define DDRPHY_DX0BDLR8_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_15_14_MASK)
21117 #define DDRPHY_DX0BDLR8_RESERVED_21_16_MASK      (0x3F0000U)
21118 #define DDRPHY_DX0BDLR8_RESERVED_21_16_SHIFT     (16U)
21119 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
21120  */
21121 #define DDRPHY_DX0BDLR8_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_21_16_MASK)
21122 #define DDRPHY_DX0BDLR8_RESERVED_31_22_MASK      (0xFFC00000U)
21123 #define DDRPHY_DX0BDLR8_RESERVED_31_22_SHIFT     (22U)
21124 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
21125  */
21126 #define DDRPHY_DX0BDLR8_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_31_22_MASK)
21127 /*! @} */
21128 
21129 /*! @name DX0BDLR9 - DATX8 n Bit Delay Line Register 9 */
21130 /*! @{ */
21131 #define DDRPHY_DX0BDLR9_RESERVED_5_0_MASK        (0x3FU)
21132 #define DDRPHY_DX0BDLR9_RESERVED_5_0_SHIFT       (0U)
21133 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
21134  */
21135 #define DDRPHY_DX0BDLR9_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_5_0_MASK)
21136 #define DDRPHY_DX0BDLR9_RESERVED_7_6_MASK        (0xC0U)
21137 #define DDRPHY_DX0BDLR9_RESERVED_7_6_SHIFT       (6U)
21138 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
21139  */
21140 #define DDRPHY_DX0BDLR9_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_7_6_MASK)
21141 #define DDRPHY_DX0BDLR9_RESERVED_13_8_MASK       (0x3F00U)
21142 #define DDRPHY_DX0BDLR9_RESERVED_13_8_SHIFT      (8U)
21143 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
21144  */
21145 #define DDRPHY_DX0BDLR9_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_13_8_MASK)
21146 #define DDRPHY_DX0BDLR9_RESERVED_15_14_MASK      (0xC000U)
21147 #define DDRPHY_DX0BDLR9_RESERVED_15_14_SHIFT     (14U)
21148 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
21149  */
21150 #define DDRPHY_DX0BDLR9_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_15_14_MASK)
21151 #define DDRPHY_DX0BDLR9_RESERVED_21_16_MASK      (0x3F0000U)
21152 #define DDRPHY_DX0BDLR9_RESERVED_21_16_SHIFT     (16U)
21153 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
21154  */
21155 #define DDRPHY_DX0BDLR9_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_21_16_MASK)
21156 #define DDRPHY_DX0BDLR9_RESERVED_31_22_MASK      (0xFFC00000U)
21157 #define DDRPHY_DX0BDLR9_RESERVED_31_22_SHIFT     (22U)
21158 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
21159  */
21160 #define DDRPHY_DX0BDLR9_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_31_22_MASK)
21161 /*! @} */
21162 
21163 /*! @name DX0LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
21164 /*! @{ */
21165 #define DDRPHY_DX0LCDLR0_WLD_MASK                (0x1FFU)
21166 #define DDRPHY_DX0LCDLR0_WLD_SHIFT               (0U)
21167 /*! WLD - Write Leveling Delay
21168  */
21169 #define DDRPHY_DX0LCDLR0_WLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_WLD_SHIFT)) & DDRPHY_DX0LCDLR0_WLD_MASK)
21170 #define DDRPHY_DX0LCDLR0_RESERVED_15_9_MASK      (0xFE00U)
21171 #define DDRPHY_DX0LCDLR0_RESERVED_15_9_SHIFT     (9U)
21172 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21173  */
21174 #define DDRPHY_DX0LCDLR0_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR0_RESERVED_15_9_MASK)
21175 #define DDRPHY_DX0LCDLR0_RESERVED_24_16_MASK     (0x1FF0000U)
21176 #define DDRPHY_DX0LCDLR0_RESERVED_24_16_SHIFT    (16U)
21177 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21178  */
21179 #define DDRPHY_DX0LCDLR0_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR0_RESERVED_24_16_MASK)
21180 #define DDRPHY_DX0LCDLR0_RESERVED_31_25_MASK     (0xFE000000U)
21181 #define DDRPHY_DX0LCDLR0_RESERVED_31_25_SHIFT    (25U)
21182 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21183  */
21184 #define DDRPHY_DX0LCDLR0_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR0_RESERVED_31_25_MASK)
21185 /*! @} */
21186 
21187 /*! @name DX0LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
21188 /*! @{ */
21189 #define DDRPHY_DX0LCDLR1_WDQD_MASK               (0x1FFU)
21190 #define DDRPHY_DX0LCDLR1_WDQD_SHIFT              (0U)
21191 /*! WDQD - Write Data Delay
21192  */
21193 #define DDRPHY_DX0LCDLR1_WDQD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_WDQD_SHIFT)) & DDRPHY_DX0LCDLR1_WDQD_MASK)
21194 #define DDRPHY_DX0LCDLR1_RESERVED_15_9_MASK      (0xFE00U)
21195 #define DDRPHY_DX0LCDLR1_RESERVED_15_9_SHIFT     (9U)
21196 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21197  */
21198 #define DDRPHY_DX0LCDLR1_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR1_RESERVED_15_9_MASK)
21199 #define DDRPHY_DX0LCDLR1_RESERVED_24_16_MASK     (0x1FF0000U)
21200 #define DDRPHY_DX0LCDLR1_RESERVED_24_16_SHIFT    (16U)
21201 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21202  */
21203 #define DDRPHY_DX0LCDLR1_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR1_RESERVED_24_16_MASK)
21204 #define DDRPHY_DX0LCDLR1_RESERVED_31_25_MASK     (0xFE000000U)
21205 #define DDRPHY_DX0LCDLR1_RESERVED_31_25_SHIFT    (25U)
21206 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21207  */
21208 #define DDRPHY_DX0LCDLR1_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR1_RESERVED_31_25_MASK)
21209 /*! @} */
21210 
21211 /*! @name DX0LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
21212 /*! @{ */
21213 #define DDRPHY_DX0LCDLR2_DQSGD_MASK              (0x1FFU)
21214 #define DDRPHY_DX0LCDLR2_DQSGD_SHIFT             (0U)
21215 /*! DQSGD - Read DQS Gating Delay
21216  */
21217 #define DDRPHY_DX0LCDLR2_DQSGD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX0LCDLR2_DQSGD_MASK)
21218 #define DDRPHY_DX0LCDLR2_RESERVED_15_9_MASK      (0xFE00U)
21219 #define DDRPHY_DX0LCDLR2_RESERVED_15_9_SHIFT     (9U)
21220 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21221  */
21222 #define DDRPHY_DX0LCDLR2_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR2_RESERVED_15_9_MASK)
21223 #define DDRPHY_DX0LCDLR2_RESERVED_24_16_MASK     (0x1FF0000U)
21224 #define DDRPHY_DX0LCDLR2_RESERVED_24_16_SHIFT    (16U)
21225 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21226  */
21227 #define DDRPHY_DX0LCDLR2_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR2_RESERVED_24_16_MASK)
21228 #define DDRPHY_DX0LCDLR2_RESERVED_31_25_MASK     (0xFE000000U)
21229 #define DDRPHY_DX0LCDLR2_RESERVED_31_25_SHIFT    (25U)
21230 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21231  */
21232 #define DDRPHY_DX0LCDLR2_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR2_RESERVED_31_25_MASK)
21233 /*! @} */
21234 
21235 /*! @name DX0LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
21236 /*! @{ */
21237 #define DDRPHY_DX0LCDLR3_RDQSD_MASK              (0x1FFU)
21238 #define DDRPHY_DX0LCDLR3_RDQSD_SHIFT             (0U)
21239 /*! RDQSD - Read DQS Delay
21240  */
21241 #define DDRPHY_DX0LCDLR3_RDQSD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX0LCDLR3_RDQSD_MASK)
21242 #define DDRPHY_DX0LCDLR3_RESERVED_15_9_MASK      (0xFE00U)
21243 #define DDRPHY_DX0LCDLR3_RESERVED_15_9_SHIFT     (9U)
21244 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21245  */
21246 #define DDRPHY_DX0LCDLR3_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR3_RESERVED_15_9_MASK)
21247 #define DDRPHY_DX0LCDLR3_RESERVED_24_16_MASK     (0x1FF0000U)
21248 #define DDRPHY_DX0LCDLR3_RESERVED_24_16_SHIFT    (16U)
21249 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21250  */
21251 #define DDRPHY_DX0LCDLR3_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR3_RESERVED_24_16_MASK)
21252 #define DDRPHY_DX0LCDLR3_RESERVED_31_25_MASK     (0xFE000000U)
21253 #define DDRPHY_DX0LCDLR3_RESERVED_31_25_SHIFT    (25U)
21254 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21255  */
21256 #define DDRPHY_DX0LCDLR3_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR3_RESERVED_31_25_MASK)
21257 /*! @} */
21258 
21259 /*! @name DX0LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
21260 /*! @{ */
21261 #define DDRPHY_DX0LCDLR4_RDQSND_MASK             (0x1FFU)
21262 #define DDRPHY_DX0LCDLR4_RDQSND_SHIFT            (0U)
21263 /*! RDQSND - Read DQSN Delay
21264  */
21265 #define DDRPHY_DX0LCDLR4_RDQSND(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX0LCDLR4_RDQSND_MASK)
21266 #define DDRPHY_DX0LCDLR4_RESERVED_15_9_MASK      (0xFE00U)
21267 #define DDRPHY_DX0LCDLR4_RESERVED_15_9_SHIFT     (9U)
21268 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21269  */
21270 #define DDRPHY_DX0LCDLR4_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR4_RESERVED_15_9_MASK)
21271 #define DDRPHY_DX0LCDLR4_RESERVED_24_16_MASK     (0x1FF0000U)
21272 #define DDRPHY_DX0LCDLR4_RESERVED_24_16_SHIFT    (16U)
21273 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21274  */
21275 #define DDRPHY_DX0LCDLR4_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR4_RESERVED_24_16_MASK)
21276 #define DDRPHY_DX0LCDLR4_RESERVED_31_25_MASK     (0xFE000000U)
21277 #define DDRPHY_DX0LCDLR4_RESERVED_31_25_SHIFT    (25U)
21278 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21279  */
21280 #define DDRPHY_DX0LCDLR4_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR4_RESERVED_31_25_MASK)
21281 /*! @} */
21282 
21283 /*! @name DX0LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
21284 /*! @{ */
21285 #define DDRPHY_DX0LCDLR5_DQSGSD_MASK             (0x1FFU)
21286 #define DDRPHY_DX0LCDLR5_DQSGSD_SHIFT            (0U)
21287 /*! DQSGSD - DQS Gating Status Delay
21288  */
21289 #define DDRPHY_DX0LCDLR5_DQSGSD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX0LCDLR5_DQSGSD_MASK)
21290 #define DDRPHY_DX0LCDLR5_RESERVED_15_9_MASK      (0xFE00U)
21291 #define DDRPHY_DX0LCDLR5_RESERVED_15_9_SHIFT     (9U)
21292 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21293  */
21294 #define DDRPHY_DX0LCDLR5_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR5_RESERVED_15_9_MASK)
21295 #define DDRPHY_DX0LCDLR5_RESERVED_24_16_MASK     (0x1FF0000U)
21296 #define DDRPHY_DX0LCDLR5_RESERVED_24_16_SHIFT    (16U)
21297 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21298  */
21299 #define DDRPHY_DX0LCDLR5_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR5_RESERVED_24_16_MASK)
21300 #define DDRPHY_DX0LCDLR5_RESERVED_31_25_MASK     (0xFE000000U)
21301 #define DDRPHY_DX0LCDLR5_RESERVED_31_25_SHIFT    (25U)
21302 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21303  */
21304 #define DDRPHY_DX0LCDLR5_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR5_RESERVED_31_25_MASK)
21305 /*! @} */
21306 
21307 /*! @name DX0MDLR0 - DATX8 n Master Delay Line Register 0 */
21308 /*! @{ */
21309 #define DDRPHY_DX0MDLR0_IPRD_MASK                (0x1FFU)
21310 #define DDRPHY_DX0MDLR0_IPRD_SHIFT               (0U)
21311 /*! IPRD - Initial Period
21312  */
21313 #define DDRPHY_DX0MDLR0_IPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_IPRD_SHIFT)) & DDRPHY_DX0MDLR0_IPRD_MASK)
21314 #define DDRPHY_DX0MDLR0_RESERVED_15_9_MASK       (0xFE00U)
21315 #define DDRPHY_DX0MDLR0_RESERVED_15_9_SHIFT      (9U)
21316 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21317  */
21318 #define DDRPHY_DX0MDLR0_RESERVED_15_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX0MDLR0_RESERVED_15_9_MASK)
21319 #define DDRPHY_DX0MDLR0_TPRD_MASK                (0x1FF0000U)
21320 #define DDRPHY_DX0MDLR0_TPRD_SHIFT               (16U)
21321 /*! TPRD - Target Period
21322  */
21323 #define DDRPHY_DX0MDLR0_TPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_TPRD_SHIFT)) & DDRPHY_DX0MDLR0_TPRD_MASK)
21324 #define DDRPHY_DX0MDLR0_RESERVED_31_25_MASK      (0xFE000000U)
21325 #define DDRPHY_DX0MDLR0_RESERVED_31_25_SHIFT     (25U)
21326 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21327  */
21328 #define DDRPHY_DX0MDLR0_RESERVED_31_25(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX0MDLR0_RESERVED_31_25_MASK)
21329 /*! @} */
21330 
21331 /*! @name DX0MDLR1 - DATX8 n Master Delay Line Register 1 */
21332 /*! @{ */
21333 #define DDRPHY_DX0MDLR1_MDLD_MASK                (0x1FFU)
21334 #define DDRPHY_DX0MDLR1_MDLD_SHIFT               (0U)
21335 /*! MDLD - MDL Delay
21336  */
21337 #define DDRPHY_DX0MDLR1_MDLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR1_MDLD_SHIFT)) & DDRPHY_DX0MDLR1_MDLD_MASK)
21338 #define DDRPHY_DX0MDLR1_RESERVED_31_9_MASK       (0xFFFFFE00U)
21339 #define DDRPHY_DX0MDLR1_RESERVED_31_9_SHIFT      (9U)
21340 /*! RESERVED_31_9 - Reserved. Return zeroes on reads.
21341  */
21342 #define DDRPHY_DX0MDLR1_RESERVED_31_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX0MDLR1_RESERVED_31_9_MASK)
21343 /*! @} */
21344 
21345 /*! @name DX0GTR0 - DATX8 n General Timing Register 0 */
21346 /*! @{ */
21347 #define DDRPHY_DX0GTR0_DGSL_MASK                 (0x1FU)
21348 #define DDRPHY_DX0GTR0_DGSL_SHIFT                (0U)
21349 /*! DGSL - DQS Gating System Latency
21350  */
21351 #define DDRPHY_DX0GTR0_DGSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_DGSL_SHIFT)) & DDRPHY_DX0GTR0_DGSL_MASK)
21352 #define DDRPHY_DX0GTR0_RESERVED_7_5_MASK         (0xE0U)
21353 #define DDRPHY_DX0GTR0_RESERVED_7_5_SHIFT        (5U)
21354 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
21355  */
21356 #define DDRPHY_DX0GTR0_RESERVED_7_5(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_7_5_MASK)
21357 #define DDRPHY_DX0GTR0_RESERVED_12_8_MASK        (0x1F00U)
21358 #define DDRPHY_DX0GTR0_RESERVED_12_8_SHIFT       (8U)
21359 /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
21360  */
21361 #define DDRPHY_DX0GTR0_RESERVED_12_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_12_8_MASK)
21362 #define DDRPHY_DX0GTR0_RESERVED_15_13_MASK       (0xE000U)
21363 #define DDRPHY_DX0GTR0_RESERVED_15_13_SHIFT      (13U)
21364 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
21365  */
21366 #define DDRPHY_DX0GTR0_RESERVED_15_13(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_15_13_MASK)
21367 #define DDRPHY_DX0GTR0_WLSL_MASK                 (0xF0000U)
21368 #define DDRPHY_DX0GTR0_WLSL_SHIFT                (16U)
21369 /*! WLSL - Write Leveling System Latency
21370  */
21371 #define DDRPHY_DX0GTR0_WLSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_WLSL_SHIFT)) & DDRPHY_DX0GTR0_WLSL_MASK)
21372 #define DDRPHY_DX0GTR0_RESERVED_23_20_MASK       (0xF00000U)
21373 #define DDRPHY_DX0GTR0_RESERVED_23_20_SHIFT      (20U)
21374 /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
21375  */
21376 #define DDRPHY_DX0GTR0_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_23_20_MASK)
21377 #define DDRPHY_DX0GTR0_WDQSL_MASK                (0x7000000U)
21378 #define DDRPHY_DX0GTR0_WDQSL_SHIFT               (24U)
21379 /*! WDQSL - DQ Write Path Latency Pipeline
21380  */
21381 #define DDRPHY_DX0GTR0_WDQSL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_WDQSL_SHIFT)) & DDRPHY_DX0GTR0_WDQSL_MASK)
21382 #define DDRPHY_DX0GTR0_RESERVED_31_24_MASK       (0xF8000000U)
21383 #define DDRPHY_DX0GTR0_RESERVED_31_24_SHIFT      (27U)
21384 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
21385  */
21386 #define DDRPHY_DX0GTR0_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_31_24_MASK)
21387 /*! @} */
21388 
21389 /*! @name DX0RSR0 - DATX8 n Rank Status Register 0 */
21390 /*! @{ */
21391 #define DDRPHY_DX0RSR0_QSGERR_MASK               (0xFFFFU)
21392 #define DDRPHY_DX0RSR0_QSGERR_SHIFT              (0U)
21393 /*! QSGERR - DQS Gate Training Error
21394  */
21395 #define DDRPHY_DX0RSR0_QSGERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR0_QSGERR_SHIFT)) & DDRPHY_DX0RSR0_QSGERR_MASK)
21396 #define DDRPHY_DX0RSR0_RESERVED_31_16_MASK       (0xFFFF0000U)
21397 #define DDRPHY_DX0RSR0_RESERVED_31_16_SHIFT      (16U)
21398 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
21399  */
21400 #define DDRPHY_DX0RSR0_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR0_RESERVED_31_16_MASK)
21401 /*! @} */
21402 
21403 /*! @name DX0RSR1 - DATX8 n Rank Status Register 1 */
21404 /*! @{ */
21405 #define DDRPHY_DX0RSR1_RDLVLERR_MASK             (0xFFFFU)
21406 #define DDRPHY_DX0RSR1_RDLVLERR_SHIFT            (0U)
21407 /*! RDLVLERR - Read Leveling Error
21408  */
21409 #define DDRPHY_DX0RSR1_RDLVLERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX0RSR1_RDLVLERR_MASK)
21410 #define DDRPHY_DX0RSR1_RESERVED_31_16_MASK       (0xFFFF0000U)
21411 #define DDRPHY_DX0RSR1_RESERVED_31_16_SHIFT      (16U)
21412 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
21413  */
21414 #define DDRPHY_DX0RSR1_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR1_RESERVED_31_16_MASK)
21415 /*! @} */
21416 
21417 /*! @name DX0RSR2 - DATX8 n Rank Status Register 2 */
21418 /*! @{ */
21419 #define DDRPHY_DX0RSR2_WLAWN_MASK                (0xFFFFU)
21420 #define DDRPHY_DX0RSR2_WLAWN_SHIFT               (0U)
21421 /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
21422  */
21423 #define DDRPHY_DX0RSR2_WLAWN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR2_WLAWN_SHIFT)) & DDRPHY_DX0RSR2_WLAWN_MASK)
21424 #define DDRPHY_DX0RSR2_RESERVED_31_16_MASK       (0xFFFF0000U)
21425 #define DDRPHY_DX0RSR2_RESERVED_31_16_SHIFT      (16U)
21426 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
21427  */
21428 #define DDRPHY_DX0RSR2_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR2_RESERVED_31_16_MASK)
21429 /*! @} */
21430 
21431 /*! @name DX0RSR3 - DATX8 n Rank Status Register 3 */
21432 /*! @{ */
21433 #define DDRPHY_DX0RSR3_WLAERR_MASK               (0xFFFFU)
21434 #define DDRPHY_DX0RSR3_WLAERR_SHIFT              (0U)
21435 /*! WLAERR - Write Leveling Adjustment Error
21436  */
21437 #define DDRPHY_DX0RSR3_WLAERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR3_WLAERR_SHIFT)) & DDRPHY_DX0RSR3_WLAERR_MASK)
21438 #define DDRPHY_DX0RSR3_RESERVED_31_16_MASK       (0xFFFF0000U)
21439 #define DDRPHY_DX0RSR3_RESERVED_31_16_SHIFT      (16U)
21440 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
21441  */
21442 #define DDRPHY_DX0RSR3_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR3_RESERVED_31_16_MASK)
21443 /*! @} */
21444 
21445 /*! @name DX0GSR0 - DATX8 n General Status Register 0 */
21446 /*! @{ */
21447 #define DDRPHY_DX0GSR0_WDQCAL_MASK               (0x1U)
21448 #define DDRPHY_DX0GSR0_WDQCAL_SHIFT              (0U)
21449 /*! WDQCAL - Write DQ Calibration
21450  */
21451 #define DDRPHY_DX0GSR0_WDQCAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WDQCAL_SHIFT)) & DDRPHY_DX0GSR0_WDQCAL_MASK)
21452 #define DDRPHY_DX0GSR0_RDQSCAL_MASK              (0x2U)
21453 #define DDRPHY_DX0GSR0_RDQSCAL_SHIFT             (1U)
21454 /*! RDQSCAL - Read DQS Calibration
21455  */
21456 #define DDRPHY_DX0GSR0_RDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX0GSR0_RDQSCAL_MASK)
21457 #define DDRPHY_DX0GSR0_RDQSNCAL_MASK             (0x4U)
21458 #define DDRPHY_DX0GSR0_RDQSNCAL_SHIFT            (2U)
21459 /*! RDQSNCAL - Read DQS# Calibration
21460  */
21461 #define DDRPHY_DX0GSR0_RDQSNCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX0GSR0_RDQSNCAL_MASK)
21462 #define DDRPHY_DX0GSR0_GDQSCAL_MASK              (0x8U)
21463 #define DDRPHY_DX0GSR0_GDQSCAL_SHIFT             (3U)
21464 /*! GDQSCAL - Read DQS gating Calibration
21465  */
21466 #define DDRPHY_DX0GSR0_GDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX0GSR0_GDQSCAL_MASK)
21467 #define DDRPHY_DX0GSR0_WLCAL_MASK                (0x10U)
21468 #define DDRPHY_DX0GSR0_WLCAL_SHIFT               (4U)
21469 /*! WLCAL - Write Leveling Calibration
21470  */
21471 #define DDRPHY_DX0GSR0_WLCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLCAL_SHIFT)) & DDRPHY_DX0GSR0_WLCAL_MASK)
21472 #define DDRPHY_DX0GSR0_WLDONE_MASK               (0x20U)
21473 #define DDRPHY_DX0GSR0_WLDONE_SHIFT              (5U)
21474 /*! WLDONE - Write Leveling Done
21475  */
21476 #define DDRPHY_DX0GSR0_WLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLDONE_SHIFT)) & DDRPHY_DX0GSR0_WLDONE_MASK)
21477 #define DDRPHY_DX0GSR0_WLERR_MASK                (0x40U)
21478 #define DDRPHY_DX0GSR0_WLERR_SHIFT               (6U)
21479 /*! WLERR - Write Leveling Error
21480  */
21481 #define DDRPHY_DX0GSR0_WLERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLERR_SHIFT)) & DDRPHY_DX0GSR0_WLERR_MASK)
21482 #define DDRPHY_DX0GSR0_WLPRD_MASK                (0xFF80U)
21483 #define DDRPHY_DX0GSR0_WLPRD_SHIFT               (7U)
21484 /*! WLPRD - Write Leveling Period
21485  */
21486 #define DDRPHY_DX0GSR0_WLPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLPRD_SHIFT)) & DDRPHY_DX0GSR0_WLPRD_MASK)
21487 #define DDRPHY_DX0GSR0_DPLOCK_MASK               (0x10000U)
21488 #define DDRPHY_DX0GSR0_DPLOCK_SHIFT              (16U)
21489 /*! DPLOCK - DATX8 PLL Lock
21490  */
21491 #define DDRPHY_DX0GSR0_DPLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_DPLOCK_SHIFT)) & DDRPHY_DX0GSR0_DPLOCK_MASK)
21492 #define DDRPHY_DX0GSR0_GDQSPRD_MASK              (0x3FE0000U)
21493 #define DDRPHY_DX0GSR0_GDQSPRD_SHIFT             (17U)
21494 /*! GDQSPRD - Read DQS gating Period
21495  */
21496 #define DDRPHY_DX0GSR0_GDQSPRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX0GSR0_GDQSPRD_MASK)
21497 #define DDRPHY_DX0GSR0_RESERVED_29_26_MASK       (0x3C000000U)
21498 #define DDRPHY_DX0GSR0_RESERVED_29_26_SHIFT      (26U)
21499 /*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
21500  */
21501 #define DDRPHY_DX0GSR0_RESERVED_29_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX0GSR0_RESERVED_29_26_MASK)
21502 #define DDRPHY_DX0GSR0_WLDQ_MASK                 (0x40000000U)
21503 #define DDRPHY_DX0GSR0_WLDQ_SHIFT                (30U)
21504 /*! WLDQ - Write Leveling DQ Status
21505  */
21506 #define DDRPHY_DX0GSR0_WLDQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLDQ_SHIFT)) & DDRPHY_DX0GSR0_WLDQ_MASK)
21507 #define DDRPHY_DX0GSR0_RESERVED_31_MASK          (0x80000000U)
21508 #define DDRPHY_DX0GSR0_RESERVED_31_SHIFT         (31U)
21509 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
21510  */
21511 #define DDRPHY_DX0GSR0_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX0GSR0_RESERVED_31_MASK)
21512 /*! @} */
21513 
21514 /*! @name DX0GSR1 - DATX8 n General Status Register 1 */
21515 /*! @{ */
21516 #define DDRPHY_DX0GSR1_DLTDONE_MASK              (0x1U)
21517 #define DDRPHY_DX0GSR1_DLTDONE_SHIFT             (0U)
21518 /*! DLTDONE - Delay Line Test Done
21519  */
21520 #define DDRPHY_DX0GSR1_DLTDONE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR1_DLTDONE_SHIFT)) & DDRPHY_DX0GSR1_DLTDONE_MASK)
21521 #define DDRPHY_DX0GSR1_DLTCODE_MASK              (0x1FFFFFEU)
21522 #define DDRPHY_DX0GSR1_DLTCODE_SHIFT             (1U)
21523 /*! DLTCODE - Delay Line Test Code
21524  */
21525 #define DDRPHY_DX0GSR1_DLTCODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR1_DLTCODE_SHIFT)) & DDRPHY_DX0GSR1_DLTCODE_MASK)
21526 #define DDRPHY_DX0GSR1_RESERVED_31_25_MASK       (0xFE000000U)
21527 #define DDRPHY_DX0GSR1_RESERVED_31_25_SHIFT      (25U)
21528 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
21529  */
21530 #define DDRPHY_DX0GSR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX0GSR1_RESERVED_31_25_MASK)
21531 /*! @} */
21532 
21533 /*! @name DX0GSR2 - DATX8 n General Status Register 2 */
21534 /*! @{ */
21535 #define DDRPHY_DX0GSR2_RDERR_MASK                (0x1U)
21536 #define DDRPHY_DX0GSR2_RDERR_SHIFT               (0U)
21537 /*! RDERR - Read Bit Deskew Error
21538  */
21539 #define DDRPHY_DX0GSR2_RDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_RDERR_SHIFT)) & DDRPHY_DX0GSR2_RDERR_MASK)
21540 #define DDRPHY_DX0GSR2_RDWN_MASK                 (0x2U)
21541 #define DDRPHY_DX0GSR2_RDWN_SHIFT                (1U)
21542 /*! RDWN - Read Bit Deskew Warning
21543  */
21544 #define DDRPHY_DX0GSR2_RDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_RDWN_SHIFT)) & DDRPHY_DX0GSR2_RDWN_MASK)
21545 #define DDRPHY_DX0GSR2_WDERR_MASK                (0x4U)
21546 #define DDRPHY_DX0GSR2_WDERR_SHIFT               (2U)
21547 /*! WDERR - Write Bit Deskew Error
21548  */
21549 #define DDRPHY_DX0GSR2_WDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WDERR_SHIFT)) & DDRPHY_DX0GSR2_WDERR_MASK)
21550 #define DDRPHY_DX0GSR2_WDWN_MASK                 (0x8U)
21551 #define DDRPHY_DX0GSR2_WDWN_SHIFT                (3U)
21552 /*! WDWN - Write Bit Deskew Warning
21553  */
21554 #define DDRPHY_DX0GSR2_WDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WDWN_SHIFT)) & DDRPHY_DX0GSR2_WDWN_MASK)
21555 #define DDRPHY_DX0GSR2_REERR_MASK                (0x10U)
21556 #define DDRPHY_DX0GSR2_REERR_SHIFT               (4U)
21557 /*! REERR - Read Eye Centering Error
21558  */
21559 #define DDRPHY_DX0GSR2_REERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_REERR_SHIFT)) & DDRPHY_DX0GSR2_REERR_MASK)
21560 #define DDRPHY_DX0GSR2_REWN_MASK                 (0x20U)
21561 #define DDRPHY_DX0GSR2_REWN_SHIFT                (5U)
21562 /*! REWN - Read Eye Centering Warning
21563  */
21564 #define DDRPHY_DX0GSR2_REWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_REWN_SHIFT)) & DDRPHY_DX0GSR2_REWN_MASK)
21565 #define DDRPHY_DX0GSR2_WEERR_MASK                (0x40U)
21566 #define DDRPHY_DX0GSR2_WEERR_SHIFT               (6U)
21567 /*! WEERR - Write Eye Centering Error
21568  */
21569 #define DDRPHY_DX0GSR2_WEERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WEERR_SHIFT)) & DDRPHY_DX0GSR2_WEERR_MASK)
21570 #define DDRPHY_DX0GSR2_WEWN_MASK                 (0x80U)
21571 #define DDRPHY_DX0GSR2_WEWN_SHIFT                (7U)
21572 /*! WEWN - Write Eye Centering Warning
21573  */
21574 #define DDRPHY_DX0GSR2_WEWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WEWN_SHIFT)) & DDRPHY_DX0GSR2_WEWN_MASK)
21575 #define DDRPHY_DX0GSR2_ESTAT_MASK                (0xF00U)
21576 #define DDRPHY_DX0GSR2_ESTAT_SHIFT               (8U)
21577 /*! ESTAT - Error Status
21578  */
21579 #define DDRPHY_DX0GSR2_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_ESTAT_SHIFT)) & DDRPHY_DX0GSR2_ESTAT_MASK)
21580 #define DDRPHY_DX0GSR2_DQS2DQERR_MASK            (0xFF000U)
21581 #define DDRPHY_DX0GSR2_DQS2DQERR_SHIFT           (12U)
21582 /*! DQS2DQERR - Write DQS2DQ Training Error
21583  */
21584 #define DDRPHY_DX0GSR2_DQS2DQERR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX0GSR2_DQS2DQERR_MASK)
21585 #define DDRPHY_DX0GSR2_SRDERR_MASK               (0x100000U)
21586 #define DDRPHY_DX0GSR2_SRDERR_SHIFT              (20U)
21587 /*! SRDERR - Static Read Error
21588  */
21589 #define DDRPHY_DX0GSR2_SRDERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_SRDERR_SHIFT)) & DDRPHY_DX0GSR2_SRDERR_MASK)
21590 #define DDRPHY_DX0GSR2_RESERVED_21_MASK          (0x200000U)
21591 #define DDRPHY_DX0GSR2_RESERVED_21_SHIFT         (21U)
21592 /*! RESERVED_21 - Reserved. Return zeroes on reads.
21593  */
21594 #define DDRPHY_DX0GSR2_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX0GSR2_RESERVED_21_MASK)
21595 #define DDRPHY_DX0GSR2_GSDQSCAL_MASK             (0x400000U)
21596 #define DDRPHY_DX0GSR2_GSDQSCAL_SHIFT            (22U)
21597 /*! GSDQSCAL - Read DQS Gating Status Calibration
21598  */
21599 #define DDRPHY_DX0GSR2_GSDQSCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX0GSR2_GSDQSCAL_MASK)
21600 #define DDRPHY_DX0GSR2_GSDQSPRD_MASK             (0xFF800000U)
21601 #define DDRPHY_DX0GSR2_GSDQSPRD_SHIFT            (23U)
21602 /*! GSDQSPRD - Read DQS gating Status Period
21603  */
21604 #define DDRPHY_DX0GSR2_GSDQSPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX0GSR2_GSDQSPRD_MASK)
21605 /*! @} */
21606 
21607 /*! @name DX0GSR3 - DATX8 n General Status Register 3 */
21608 /*! @{ */
21609 #define DDRPHY_DX0GSR3_SRDPC_MASK                (0x3U)
21610 #define DDRPHY_DX0GSR3_SRDPC_SHIFT               (0U)
21611 /*! SRDPC - Static Read Delay Pass Count
21612  */
21613 #define DDRPHY_DX0GSR3_SRDPC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_SRDPC_SHIFT)) & DDRPHY_DX0GSR3_SRDPC_MASK)
21614 #define DDRPHY_DX0GSR3_RESERVED_7_2_MASK         (0xFCU)
21615 #define DDRPHY_DX0GSR3_RESERVED_7_2_SHIFT        (2U)
21616 /*! RESERVED_7_2 - Reserved. Return zeroes on reads.
21617  */
21618 #define DDRPHY_DX0GSR3_RESERVED_7_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX0GSR3_RESERVED_7_2_MASK)
21619 #define DDRPHY_DX0GSR3_HVERR_MASK                (0xF00U)
21620 #define DDRPHY_DX0GSR3_HVERR_SHIFT               (8U)
21621 /*! HVERR - Host VREF Training Error
21622  */
21623 #define DDRPHY_DX0GSR3_HVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_HVERR_SHIFT)) & DDRPHY_DX0GSR3_HVERR_MASK)
21624 #define DDRPHY_DX0GSR3_HVWRN_MASK                (0xF000U)
21625 #define DDRPHY_DX0GSR3_HVWRN_SHIFT               (12U)
21626 /*! HVWRN - Host VREF Training Warning
21627  */
21628 #define DDRPHY_DX0GSR3_HVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_HVWRN_SHIFT)) & DDRPHY_DX0GSR3_HVWRN_MASK)
21629 #define DDRPHY_DX0GSR3_DVERR_MASK                (0xF0000U)
21630 #define DDRPHY_DX0GSR3_DVERR_SHIFT               (16U)
21631 /*! DVERR - DRAM VREF Training Error
21632  */
21633 #define DDRPHY_DX0GSR3_DVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_DVERR_SHIFT)) & DDRPHY_DX0GSR3_DVERR_MASK)
21634 #define DDRPHY_DX0GSR3_DVWRN_MASK                (0xF00000U)
21635 #define DDRPHY_DX0GSR3_DVWRN_SHIFT               (20U)
21636 /*! DVWRN - DRAM VREF Training Warning
21637  */
21638 #define DDRPHY_DX0GSR3_DVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_DVWRN_SHIFT)) & DDRPHY_DX0GSR3_DVWRN_MASK)
21639 #define DDRPHY_DX0GSR3_ESTAT_MASK                (0x7000000U)
21640 #define DDRPHY_DX0GSR3_ESTAT_SHIFT               (24U)
21641 /*! ESTAT - VREF Training Error Status Code
21642  */
21643 #define DDRPHY_DX0GSR3_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_ESTAT_SHIFT)) & DDRPHY_DX0GSR3_ESTAT_MASK)
21644 #define DDRPHY_DX0GSR3_RESERVED_31_27_MASK       (0xF8000000U)
21645 #define DDRPHY_DX0GSR3_RESERVED_31_27_SHIFT      (27U)
21646 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
21647  */
21648 #define DDRPHY_DX0GSR3_RESERVED_31_27(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX0GSR3_RESERVED_31_27_MASK)
21649 /*! @} */
21650 
21651 /*! @name DX0GSR4 - DATX8 n General Status Register 4 */
21652 /*! @{ */
21653 #define DDRPHY_DX0GSR4_RESERVED_0_MASK           (0x1U)
21654 #define DDRPHY_DX0GSR4_RESERVED_0_SHIFT          (0U)
21655 /*! RESERVED_0 - Reserved. Return zeroes on reads.
21656  */
21657 #define DDRPHY_DX0GSR4_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_0_MASK)
21658 #define DDRPHY_DX0GSR4_RESERVED_1_MASK           (0x2U)
21659 #define DDRPHY_DX0GSR4_RESERVED_1_SHIFT          (1U)
21660 /*! RESERVED_1 - Reserved. Return zeroes on reads.
21661  */
21662 #define DDRPHY_DX0GSR4_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_1_MASK)
21663 #define DDRPHY_DX0GSR4_RESERVED_2_MASK           (0x4U)
21664 #define DDRPHY_DX0GSR4_RESERVED_2_SHIFT          (2U)
21665 /*! RESERVED_2 - Reserved. Return zeroes on reads.
21666  */
21667 #define DDRPHY_DX0GSR4_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_2_MASK)
21668 #define DDRPHY_DX0GSR4_RESERVED_3_MASK           (0x8U)
21669 #define DDRPHY_DX0GSR4_RESERVED_3_SHIFT          (3U)
21670 /*! RESERVED_3 - Reserved. Return zeroes on reads.
21671  */
21672 #define DDRPHY_DX0GSR4_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_3_MASK)
21673 #define DDRPHY_DX0GSR4_RESERVED_4_MASK           (0x10U)
21674 #define DDRPHY_DX0GSR4_RESERVED_4_SHIFT          (4U)
21675 /*! RESERVED_4 - Reserved. Return zeroes on reads.
21676  */
21677 #define DDRPHY_DX0GSR4_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_4_MASK)
21678 #define DDRPHY_DX0GSR4_RESERVED_5_MASK           (0x20U)
21679 #define DDRPHY_DX0GSR4_RESERVED_5_SHIFT          (5U)
21680 /*! RESERVED_5 - Reserved. Return zeroes on reads.
21681  */
21682 #define DDRPHY_DX0GSR4_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_5_MASK)
21683 #define DDRPHY_DX0GSR4_RESERVED_6_MASK           (0x40U)
21684 #define DDRPHY_DX0GSR4_RESERVED_6_SHIFT          (6U)
21685 /*! RESERVED_6 - Reserved. Return zeroes on reads.
21686  */
21687 #define DDRPHY_DX0GSR4_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_6_MASK)
21688 #define DDRPHY_DX0GSR4_RESERVED_15_7_MASK        (0xFF80U)
21689 #define DDRPHY_DX0GSR4_RESERVED_15_7_SHIFT       (7U)
21690 /*! RESERVED_15_7 - Reserved. Return zeroes on reads.
21691  */
21692 #define DDRPHY_DX0GSR4_RESERVED_15_7(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_15_7_MASK)
21693 #define DDRPHY_DX0GSR4_RESERVED_16_MASK          (0x10000U)
21694 #define DDRPHY_DX0GSR4_RESERVED_16_SHIFT         (16U)
21695 /*! RESERVED_16 - Reserved. Return zeroes on reads.
21696  */
21697 #define DDRPHY_DX0GSR4_RESERVED_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_16_MASK)
21698 #define DDRPHY_DX0GSR4_RESERVED_25_17_MASK       (0x3FE0000U)
21699 #define DDRPHY_DX0GSR4_RESERVED_25_17_SHIFT      (17U)
21700 /*! RESERVED_25_17 - Reserved. Return zeroes on reads.
21701  */
21702 #define DDRPHY_DX0GSR4_RESERVED_25_17(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_25_17_MASK)
21703 #define DDRPHY_DX0GSR4_RESERVED_31_26_MASK       (0xFC000000U)
21704 #define DDRPHY_DX0GSR4_RESERVED_31_26_SHIFT      (26U)
21705 /*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
21706  */
21707 #define DDRPHY_DX0GSR4_RESERVED_31_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_31_26_MASK)
21708 /*! @} */
21709 
21710 /*! @name DX0GSR5 - DATX8 n General Status Register 5 */
21711 /*! @{ */
21712 #define DDRPHY_DX0GSR5_RESERVED_0_MASK           (0x1U)
21713 #define DDRPHY_DX0GSR5_RESERVED_0_SHIFT          (0U)
21714 /*! RESERVED_0 - Reserved. Return zeroes on reads.
21715  */
21716 #define DDRPHY_DX0GSR5_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_0_MASK)
21717 #define DDRPHY_DX0GSR5_RESERVED_1_MASK           (0x2U)
21718 #define DDRPHY_DX0GSR5_RESERVED_1_SHIFT          (1U)
21719 /*! RESERVED_1 - Reserved. Return zeroes on reads.
21720  */
21721 #define DDRPHY_DX0GSR5_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_1_MASK)
21722 #define DDRPHY_DX0GSR5_RESERVED_2_MASK           (0x4U)
21723 #define DDRPHY_DX0GSR5_RESERVED_2_SHIFT          (2U)
21724 /*! RESERVED_2 - Reserved. Return zeroes on reads.
21725  */
21726 #define DDRPHY_DX0GSR5_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_2_MASK)
21727 #define DDRPHY_DX0GSR5_RESERVED_3_MASK           (0x8U)
21728 #define DDRPHY_DX0GSR5_RESERVED_3_SHIFT          (3U)
21729 /*! RESERVED_3 - Reserved. Return zeroes on reads.
21730  */
21731 #define DDRPHY_DX0GSR5_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_3_MASK)
21732 #define DDRPHY_DX0GSR5_RESERVED_4_MASK           (0x10U)
21733 #define DDRPHY_DX0GSR5_RESERVED_4_SHIFT          (4U)
21734 /*! RESERVED_4 - Reserved. Return zeroes on reads.
21735  */
21736 #define DDRPHY_DX0GSR5_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_4_MASK)
21737 #define DDRPHY_DX0GSR5_RESERVED_5_MASK           (0x20U)
21738 #define DDRPHY_DX0GSR5_RESERVED_5_SHIFT          (5U)
21739 /*! RESERVED_5 - Reserved. Return zeroes on reads.
21740  */
21741 #define DDRPHY_DX0GSR5_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_5_MASK)
21742 #define DDRPHY_DX0GSR5_RESERVED_6_MASK           (0x40U)
21743 #define DDRPHY_DX0GSR5_RESERVED_6_SHIFT          (6U)
21744 /*! RESERVED_6 - Reserved. Return zeroes on reads.
21745  */
21746 #define DDRPHY_DX0GSR5_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_6_MASK)
21747 #define DDRPHY_DX0GSR5_RESERVED_7_MASK           (0x80U)
21748 #define DDRPHY_DX0GSR5_RESERVED_7_SHIFT          (7U)
21749 /*! RESERVED_7 - Reserved. Return zeroes on reads.
21750  */
21751 #define DDRPHY_DX0GSR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_7_MASK)
21752 #define DDRPHY_DX0GSR5_RESERVED_11_8_MASK        (0xF00U)
21753 #define DDRPHY_DX0GSR5_RESERVED_11_8_SHIFT       (8U)
21754 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
21755  */
21756 #define DDRPHY_DX0GSR5_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_11_8_MASK)
21757 #define DDRPHY_DX0GSR5_RESERVED_19_12_MASK       (0xFF000U)
21758 #define DDRPHY_DX0GSR5_RESERVED_19_12_SHIFT      (12U)
21759 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
21760  */
21761 #define DDRPHY_DX0GSR5_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_19_12_MASK)
21762 #define DDRPHY_DX0GSR5_RESERVED_20_MASK          (0x100000U)
21763 #define DDRPHY_DX0GSR5_RESERVED_20_SHIFT         (20U)
21764 /*! RESERVED_20 - Reserved. Return zeroes on reads.
21765  */
21766 #define DDRPHY_DX0GSR5_RESERVED_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_20_MASK)
21767 #define DDRPHY_DX0GSR5_RESERVED_21_MASK          (0x200000U)
21768 #define DDRPHY_DX0GSR5_RESERVED_21_SHIFT         (21U)
21769 /*! RESERVED_21 - Reserved. Return zeroes on reads.
21770  */
21771 #define DDRPHY_DX0GSR5_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_21_MASK)
21772 #define DDRPHY_DX0GSR5_RESERVED_22_MASK          (0x400000U)
21773 #define DDRPHY_DX0GSR5_RESERVED_22_SHIFT         (22U)
21774 /*! RESERVED_22 - Reserved. Return zeroes on reads.
21775  */
21776 #define DDRPHY_DX0GSR5_RESERVED_22(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_22_MASK)
21777 #define DDRPHY_DX0GSR5_RESERVED_31_23_MASK       (0xFF800000U)
21778 #define DDRPHY_DX0GSR5_RESERVED_31_23_SHIFT      (23U)
21779 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
21780  */
21781 #define DDRPHY_DX0GSR5_RESERVED_31_23(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_31_23_MASK)
21782 /*! @} */
21783 
21784 /*! @name DX0GSR6 - DATX8 n General Status Register 6 */
21785 /*! @{ */
21786 #define DDRPHY_DX0GSR6_RESERVED_1_0_MASK         (0x3U)
21787 #define DDRPHY_DX0GSR6_RESERVED_1_0_SHIFT        (0U)
21788 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
21789  */
21790 #define DDRPHY_DX0GSR6_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_1_0_MASK)
21791 #define DDRPHY_DX0GSR6_RESERVED_3_2_MASK         (0xCU)
21792 #define DDRPHY_DX0GSR6_RESERVED_3_2_SHIFT        (2U)
21793 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
21794  */
21795 #define DDRPHY_DX0GSR6_RESERVED_3_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_3_2_MASK)
21796 #define DDRPHY_DX0GSR6_RESERVED_7_4_MASK         (0xF0U)
21797 #define DDRPHY_DX0GSR6_RESERVED_7_4_SHIFT        (4U)
21798 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
21799  */
21800 #define DDRPHY_DX0GSR6_RESERVED_7_4(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_7_4_MASK)
21801 #define DDRPHY_DX0GSR6_RESERVED_11_8_MASK        (0xF00U)
21802 #define DDRPHY_DX0GSR6_RESERVED_11_8_SHIFT       (8U)
21803 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
21804  */
21805 #define DDRPHY_DX0GSR6_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_11_8_MASK)
21806 #define DDRPHY_DX0GSR6_RESERVED_15_12_MASK       (0xF000U)
21807 #define DDRPHY_DX0GSR6_RESERVED_15_12_SHIFT      (12U)
21808 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
21809  */
21810 #define DDRPHY_DX0GSR6_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_15_12_MASK)
21811 #define DDRPHY_DX0GSR6_RESERVED_19_15_MASK       (0xF0000U)
21812 #define DDRPHY_DX0GSR6_RESERVED_19_15_SHIFT      (16U)
21813 /*! RESERVED_19_15 - Reserved. Return zeroes on reads.
21814  */
21815 #define DDRPHY_DX0GSR6_RESERVED_19_15(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_19_15_MASK)
21816 #define DDRPHY_DX0GSR6_RESERVED_23_20_MASK       (0xF00000U)
21817 #define DDRPHY_DX0GSR6_RESERVED_23_20_SHIFT      (20U)
21818 /*! RESERVED_23_20 - Reserved. Return zeroes on reads.
21819  */
21820 #define DDRPHY_DX0GSR6_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_23_20_MASK)
21821 #define DDRPHY_DX0GSR6_RESERVED_31_24_MASK       (0xFF000000U)
21822 #define DDRPHY_DX0GSR6_RESERVED_31_24_SHIFT      (24U)
21823 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
21824  */
21825 #define DDRPHY_DX0GSR6_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_31_24_MASK)
21826 /*! @} */
21827 
21828 /*! @name DX1GCR0 - DATX8 n General Configuration Register 0 */
21829 /*! @{ */
21830 #define DDRPHY_DX1GCR0_RESERVED_1_0_MASK         (0x3U)
21831 #define DDRPHY_DX1GCR0_RESERVED_1_0_SHIFT        (0U)
21832 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
21833  */
21834 #define DDRPHY_DX1GCR0_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX1GCR0_RESERVED_1_0_MASK)
21835 #define DDRPHY_DX1GCR0_DQSGOE_MASK               (0x4U)
21836 #define DDRPHY_DX1GCR0_DQSGOE_SHIFT              (2U)
21837 /*! DQSGOE - DQSG Output Enable
21838  */
21839 #define DDRPHY_DX1GCR0_DQSGOE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSGOE_SHIFT)) & DDRPHY_DX1GCR0_DQSGOE_MASK)
21840 #define DDRPHY_DX1GCR0_DQSGODT_MASK              (0x8U)
21841 #define DDRPHY_DX1GCR0_DQSGODT_SHIFT             (3U)
21842 /*! DQSGODT - DQSG On-Die Termination
21843  */
21844 #define DDRPHY_DX1GCR0_DQSGODT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSGODT_SHIFT)) & DDRPHY_DX1GCR0_DQSGODT_MASK)
21845 #define DDRPHY_DX1GCR0_RESERVED_4_MASK           (0x10U)
21846 #define DDRPHY_DX1GCR0_RESERVED_4_SHIFT          (4U)
21847 /*! RESERVED_4 - Reserved. Return zeroes on reads.
21848  */
21849 #define DDRPHY_DX1GCR0_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX1GCR0_RESERVED_4_MASK)
21850 #define DDRPHY_DX1GCR0_DQSGPDR_MASK              (0x20U)
21851 #define DDRPHY_DX1GCR0_DQSGPDR_SHIFT             (5U)
21852 /*! DQSGPDR - DQSG Power Down Receiver
21853  */
21854 #define DDRPHY_DX1GCR0_DQSGPDR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX1GCR0_DQSGPDR_MASK)
21855 #define DDRPHY_DX1GCR0_DQSRPD_MASK               (0x40U)
21856 #define DDRPHY_DX1GCR0_DQSRPD_SHIFT              (6U)
21857 /*! DQSRPD - DQSR Power Down
21858  */
21859 #define DDRPHY_DX1GCR0_DQSRPD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSRPD_SHIFT)) & DDRPHY_DX1GCR0_DQSRPD_MASK)
21860 #define DDRPHY_DX1GCR0_CPDRSHFT_MASK             (0x180U)
21861 #define DDRPHY_DX1GCR0_CPDRSHFT_SHIFT            (7U)
21862 /*! CPDRSHFT - Configurable PDR Phase Shift
21863  */
21864 #define DDRPHY_DX1GCR0_CPDRSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX1GCR0_CPDRSHFT_MASK)
21865 #define DDRPHY_DX1GCR0_RTTOH_MASK                (0x600U)
21866 #define DDRPHY_DX1GCR0_RTTOH_SHIFT               (9U)
21867 /*! RTTOH - RTT Output Hold
21868  */
21869 #define DDRPHY_DX1GCR0_RTTOH(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RTTOH_SHIFT)) & DDRPHY_DX1GCR0_RTTOH_MASK)
21870 #define DDRPHY_DX1GCR0_RTTOAL_MASK               (0x800U)
21871 #define DDRPHY_DX1GCR0_RTTOAL_SHIFT              (11U)
21872 /*! RTTOAL - RTT On Additive Latency
21873  */
21874 #define DDRPHY_DX1GCR0_RTTOAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RTTOAL_SHIFT)) & DDRPHY_DX1GCR0_RTTOAL_MASK)
21875 #define DDRPHY_DX1GCR0_DQSSEPDR_MASK             (0x1000U)
21876 #define DDRPHY_DX1GCR0_DQSSEPDR_SHIFT            (12U)
21877 /*! DQSSEPDR - DQSSE Power Down Receiver
21878  */
21879 #define DDRPHY_DX1GCR0_DQSSEPDR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX1GCR0_DQSSEPDR_MASK)
21880 #define DDRPHY_DX1GCR0_DQSNSEPDR_MASK            (0x2000U)
21881 #define DDRPHY_DX1GCR0_DQSNSEPDR_SHIFT           (13U)
21882 /*! DQSNSEPDR - DQSNSE Power Down Receiver
21883  */
21884 #define DDRPHY_DX1GCR0_DQSNSEPDR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX1GCR0_DQSNSEPDR_MASK)
21885 #define DDRPHY_DX1GCR0_RESERVED_19_14_MASK       (0xFC000U)
21886 #define DDRPHY_DX1GCR0_RESERVED_19_14_SHIFT      (14U)
21887 /*! RESERVED_19_14 - Reserved. Return zeroes on reads.
21888  */
21889 #define DDRPHY_DX1GCR0_RESERVED_19_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX1GCR0_RESERVED_19_14_MASK)
21890 #define DDRPHY_DX1GCR0_RDDLY_MASK                (0xF00000U)
21891 #define DDRPHY_DX1GCR0_RDDLY_SHIFT               (20U)
21892 /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
21893  */
21894 #define DDRPHY_DX1GCR0_RDDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RDDLY_SHIFT)) & DDRPHY_DX1GCR0_RDDLY_MASK)
21895 #define DDRPHY_DX1GCR0_DQSDCC_MASK               (0xF000000U)
21896 #define DDRPHY_DX1GCR0_DQSDCC_SHIFT              (24U)
21897 /*! DQSDCC - DQS Duty Cycle Correction
21898  */
21899 #define DDRPHY_DX1GCR0_DQSDCC(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSDCC_SHIFT)) & DDRPHY_DX1GCR0_DQSDCC_MASK)
21900 #define DDRPHY_DX1GCR0_CODTSHFT_MASK             (0x30000000U)
21901 #define DDRPHY_DX1GCR0_CODTSHFT_SHIFT            (28U)
21902 /*! CODTSHFT - Configurable ODT(TE) Phase Shift
21903  */
21904 #define DDRPHY_DX1GCR0_CODTSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX1GCR0_CODTSHFT_MASK)
21905 #define DDRPHY_DX1GCR0_MDLEN_MASK                (0x40000000U)
21906 #define DDRPHY_DX1GCR0_MDLEN_SHIFT               (30U)
21907 /*! MDLEN - Master Delay Line Enable
21908  */
21909 #define DDRPHY_DX1GCR0_MDLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_MDLEN_SHIFT)) & DDRPHY_DX1GCR0_MDLEN_MASK)
21910 #define DDRPHY_DX1GCR0_CALBYP_MASK               (0x80000000U)
21911 #define DDRPHY_DX1GCR0_CALBYP_SHIFT              (31U)
21912 /*! CALBYP - Calibration Bypass
21913  */
21914 #define DDRPHY_DX1GCR0_CALBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_CALBYP_SHIFT)) & DDRPHY_DX1GCR0_CALBYP_MASK)
21915 /*! @} */
21916 
21917 /*! @name DX1GCR1 - DATX8 n General Configuration Register 1 */
21918 /*! @{ */
21919 #define DDRPHY_DX1GCR1_DQEN_MASK                 (0xFFU)
21920 #define DDRPHY_DX1GCR1_DQEN_SHIFT                (0U)
21921 /*! DQEN - Enables DQ corresponding to each bit in a byte
21922  */
21923 #define DDRPHY_DX1GCR1_DQEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DQEN_SHIFT)) & DDRPHY_DX1GCR1_DQEN_MASK)
21924 #define DDRPHY_DX1GCR1_DMEN_MASK                 (0x100U)
21925 #define DDRPHY_DX1GCR1_DMEN_SHIFT                (8U)
21926 /*! DMEN - Enables DM pin in a byte lane
21927  */
21928 #define DDRPHY_DX1GCR1_DMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DMEN_SHIFT)) & DDRPHY_DX1GCR1_DMEN_MASK)
21929 #define DDRPHY_DX1GCR1_DSEN_MASK                 (0x200U)
21930 #define DDRPHY_DX1GCR1_DSEN_SHIFT                (9U)
21931 /*! DSEN - Enables Write Data strobe in a byte lane
21932  */
21933 #define DDRPHY_DX1GCR1_DSEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DSEN_SHIFT)) & DDRPHY_DX1GCR1_DSEN_MASK)
21934 #define DDRPHY_DX1GCR1_TEEN_MASK                 (0x400U)
21935 #define DDRPHY_DX1GCR1_TEEN_SHIFT                (10U)
21936 /*! TEEN - Enables ODT/TE in a byte lane
21937  */
21938 #define DDRPHY_DX1GCR1_TEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_TEEN_SHIFT)) & DDRPHY_DX1GCR1_TEEN_MASK)
21939 #define DDRPHY_DX1GCR1_PDREN_MASK                (0x800U)
21940 #define DDRPHY_DX1GCR1_PDREN_SHIFT               (11U)
21941 /*! PDREN - Enables PDR in a byte lane
21942  */
21943 #define DDRPHY_DX1GCR1_PDREN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_PDREN_SHIFT)) & DDRPHY_DX1GCR1_PDREN_MASK)
21944 #define DDRPHY_DX1GCR1_OEEN_MASK                 (0x1000U)
21945 #define DDRPHY_DX1GCR1_OEEN_SHIFT                (12U)
21946 /*! OEEN - Enables Read Data Strobe in a byte lane
21947  */
21948 #define DDRPHY_DX1GCR1_OEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_OEEN_SHIFT)) & DDRPHY_DX1GCR1_OEEN_MASK)
21949 #define DDRPHY_DX1GCR1_QSSEL_MASK                (0x2000U)
21950 #define DDRPHY_DX1GCR1_QSSEL_SHIFT               (13U)
21951 /*! QSSEL - Select the delayed or non-delayed read data strobe
21952  */
21953 #define DDRPHY_DX1GCR1_QSSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_QSSEL_SHIFT)) & DDRPHY_DX1GCR1_QSSEL_MASK)
21954 #define DDRPHY_DX1GCR1_QSNSEL_MASK               (0x4000U)
21955 #define DDRPHY_DX1GCR1_QSNSEL_SHIFT              (14U)
21956 /*! QSNSEL - Select the delayed or non-delayed read data strobe #
21957  */
21958 #define DDRPHY_DX1GCR1_QSNSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_QSNSEL_SHIFT)) & DDRPHY_DX1GCR1_QSNSEL_MASK)
21959 #define DDRPHY_DX1GCR1_RESERVED_15_MASK          (0x8000U)
21960 #define DDRPHY_DX1GCR1_RESERVED_15_SHIFT         (15U)
21961 /*! RESERVED_15 - Reserved. Returns zeroes on reads.
21962  */
21963 #define DDRPHY_DX1GCR1_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX1GCR1_RESERVED_15_MASK)
21964 #define DDRPHY_DX1GCR1_DXPDRMODE_MASK            (0xFFFF0000U)
21965 #define DDRPHY_DX1GCR1_DXPDRMODE_SHIFT           (16U)
21966 /*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
21967  */
21968 #define DDRPHY_DX1GCR1_DXPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX1GCR1_DXPDRMODE_MASK)
21969 /*! @} */
21970 
21971 /*! @name DX1GCR2 - DATX8 n General Configuration Register 2 */
21972 /*! @{ */
21973 #define DDRPHY_DX1GCR2_DXTEMODE_MASK             (0xFFFFU)
21974 #define DDRPHY_DX1GCR2_DXTEMODE_SHIFT            (0U)
21975 /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
21976  */
21977 #define DDRPHY_DX1GCR2_DXTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX1GCR2_DXTEMODE_MASK)
21978 #define DDRPHY_DX1GCR2_DXOEMODE_MASK             (0xFFFF0000U)
21979 #define DDRPHY_DX1GCR2_DXOEMODE_SHIFT            (16U)
21980 /*! DXOEMODE - Enables the OE mode values for DQ[7:0]
21981  */
21982 #define DDRPHY_DX1GCR2_DXOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX1GCR2_DXOEMODE_MASK)
21983 /*! @} */
21984 
21985 /*! @name DX1GCR3 - DATX8 n General Configuration Register 3 */
21986 /*! @{ */
21987 #define DDRPHY_DX1GCR3_WDMBVT_MASK               (0x1U)
21988 #define DDRPHY_DX1GCR3_WDMBVT_SHIFT              (0U)
21989 /*! WDMBVT - Write Data Mask BDL VT Compensation
21990  */
21991 #define DDRPHY_DX1GCR3_WDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDMBVT_SHIFT)) & DDRPHY_DX1GCR3_WDMBVT_MASK)
21992 #define DDRPHY_DX1GCR3_RDMBVT_MASK               (0x2U)
21993 #define DDRPHY_DX1GCR3_RDMBVT_SHIFT              (1U)
21994 /*! RDMBVT - Read Data Mask BDL VT Compensation
21995  */
21996 #define DDRPHY_DX1GCR3_RDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RDMBVT_SHIFT)) & DDRPHY_DX1GCR3_RDMBVT_MASK)
21997 #define DDRPHY_DX1GCR3_DSPDRMODE_MASK            (0xCU)
21998 #define DDRPHY_DX1GCR3_DSPDRMODE_SHIFT           (2U)
21999 /*! DSPDRMODE - Enables the PDR mode values for DQS.
22000  */
22001 #define DDRPHY_DX1GCR3_DSPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX1GCR3_DSPDRMODE_MASK)
22002 #define DDRPHY_DX1GCR3_DSTEMODE_MASK             (0x30U)
22003 #define DDRPHY_DX1GCR3_DSTEMODE_SHIFT            (4U)
22004 /*! DSTEMODE - Enables the TE mode values for DQS.
22005  */
22006 #define DDRPHY_DX1GCR3_DSTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSTEMODE_MASK)
22007 #define DDRPHY_DX1GCR3_DSOEMODE_MASK             (0xC0U)
22008 #define DDRPHY_DX1GCR3_DSOEMODE_SHIFT            (6U)
22009 /*! DSOEMODE - Enables the OE mode values for DQS.
22010  */
22011 #define DDRPHY_DX1GCR3_DSOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSOEMODE_MASK)
22012 #define DDRPHY_DX1GCR3_WDSBVT_MASK               (0x100U)
22013 #define DDRPHY_DX1GCR3_WDSBVT_SHIFT              (8U)
22014 /*! WDSBVT - Write Data Strobe BDL VT Compensation
22015  */
22016 #define DDRPHY_DX1GCR3_WDSBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDSBVT_SHIFT)) & DDRPHY_DX1GCR3_WDSBVT_MASK)
22017 #define DDRPHY_DX1GCR3_RESERVED_9_MASK           (0x200U)
22018 #define DDRPHY_DX1GCR3_RESERVED_9_SHIFT          (9U)
22019 /*! RESERVED_9 - Reserved. Returns zeroes on reads.
22020  */
22021 #define DDRPHY_DX1GCR3_RESERVED_9(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX1GCR3_RESERVED_9_MASK)
22022 #define DDRPHY_DX1GCR3_DMPDRMODE_MASK            (0xC00U)
22023 #define DDRPHY_DX1GCR3_DMPDRMODE_SHIFT           (10U)
22024 /*! DMPDRMODE - Enables the PDR mode values for DM.
22025  */
22026 #define DDRPHY_DX1GCR3_DMPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX1GCR3_DMPDRMODE_MASK)
22027 #define DDRPHY_DX1GCR3_DMTEMODE_MASK             (0x3000U)
22028 #define DDRPHY_DX1GCR3_DMTEMODE_SHIFT            (12U)
22029 /*! DMTEMODE - Enables the TE mode values for DM.
22030  */
22031 #define DDRPHY_DX1GCR3_DMTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX1GCR3_DMTEMODE_MASK)
22032 #define DDRPHY_DX1GCR3_DMOEMODE_MASK             (0xC000U)
22033 #define DDRPHY_DX1GCR3_DMOEMODE_SHIFT            (14U)
22034 /*! DMOEMODE - Enables the OE mode values for DM.
22035  */
22036 #define DDRPHY_DX1GCR3_DMOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX1GCR3_DMOEMODE_MASK)
22037 #define DDRPHY_DX1GCR3_DSNPDRMODE_MASK           (0x30000U)
22038 #define DDRPHY_DX1GCR3_DSNPDRMODE_SHIFT          (16U)
22039 /*! DSNPDRMODE - Enables the PDR mode for DQS
22040  */
22041 #define DDRPHY_DX1GCR3_DSNPDRMODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX1GCR3_DSNPDRMODE_MASK)
22042 #define DDRPHY_DX1GCR3_DSNTEMODE_MASK            (0xC0000U)
22043 #define DDRPHY_DX1GCR3_DSNTEMODE_SHIFT           (18U)
22044 /*! DSNTEMODE - Enables the TE mode for DQS
22045  */
22046 #define DDRPHY_DX1GCR3_DSNTEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSNTEMODE_MASK)
22047 #define DDRPHY_DX1GCR3_DSNOEMODE_MASK            (0x300000U)
22048 #define DDRPHY_DX1GCR3_DSNOEMODE_SHIFT           (20U)
22049 /*! DSNOEMODE - Enables the OE mode for DQs
22050  */
22051 #define DDRPHY_DX1GCR3_DSNOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSNOEMODE_MASK)
22052 #define DDRPHY_DX1GCR3_PDRBVT_MASK               (0x400000U)
22053 #define DDRPHY_DX1GCR3_PDRBVT_SHIFT              (22U)
22054 /*! PDRBVT - Power Down Receiver BDL VT Compensation
22055  */
22056 #define DDRPHY_DX1GCR3_PDRBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_PDRBVT_SHIFT)) & DDRPHY_DX1GCR3_PDRBVT_MASK)
22057 #define DDRPHY_DX1GCR3_RGSLVT_MASK               (0x800000U)
22058 #define DDRPHY_DX1GCR3_RGSLVT_SHIFT              (23U)
22059 /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
22060  */
22061 #define DDRPHY_DX1GCR3_RGSLVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RGSLVT_SHIFT)) & DDRPHY_DX1GCR3_RGSLVT_MASK)
22062 #define DDRPHY_DX1GCR3_WLLVT_MASK                (0x1000000U)
22063 #define DDRPHY_DX1GCR3_WLLVT_SHIFT               (24U)
22064 /*! WLLVT - Write Leveling LCDL Delay VT Compensation
22065  */
22066 #define DDRPHY_DX1GCR3_WLLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WLLVT_SHIFT)) & DDRPHY_DX1GCR3_WLLVT_MASK)
22067 #define DDRPHY_DX1GCR3_WDLVT_MASK                (0x2000000U)
22068 #define DDRPHY_DX1GCR3_WDLVT_SHIFT               (25U)
22069 /*! WDLVT - Write DQ LCDL Delay VT Compensation
22070  */
22071 #define DDRPHY_DX1GCR3_WDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDLVT_SHIFT)) & DDRPHY_DX1GCR3_WDLVT_MASK)
22072 #define DDRPHY_DX1GCR3_RDLVT_MASK                (0x4000000U)
22073 #define DDRPHY_DX1GCR3_RDLVT_SHIFT               (26U)
22074 /*! RDLVT - Read DQS LCDL Delay VT Compensation
22075  */
22076 #define DDRPHY_DX1GCR3_RDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RDLVT_SHIFT)) & DDRPHY_DX1GCR3_RDLVT_MASK)
22077 #define DDRPHY_DX1GCR3_RGLVT_MASK                (0x8000000U)
22078 #define DDRPHY_DX1GCR3_RGLVT_SHIFT               (27U)
22079 /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
22080  */
22081 #define DDRPHY_DX1GCR3_RGLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RGLVT_SHIFT)) & DDRPHY_DX1GCR3_RGLVT_MASK)
22082 #define DDRPHY_DX1GCR3_WDBVT_MASK                (0x10000000U)
22083 #define DDRPHY_DX1GCR3_WDBVT_SHIFT               (28U)
22084 /*! WDBVT - Write Data BDL VT Compensation
22085  */
22086 #define DDRPHY_DX1GCR3_WDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDBVT_SHIFT)) & DDRPHY_DX1GCR3_WDBVT_MASK)
22087 #define DDRPHY_DX1GCR3_RDBVT_MASK                (0x20000000U)
22088 #define DDRPHY_DX1GCR3_RDBVT_SHIFT               (29U)
22089 /*! RDBVT - Read Data BDL VT Compensation
22090  */
22091 #define DDRPHY_DX1GCR3_RDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RDBVT_SHIFT)) & DDRPHY_DX1GCR3_RDBVT_MASK)
22092 #define DDRPHY_DX1GCR3_TEBVT_MASK                (0x40000000U)
22093 #define DDRPHY_DX1GCR3_TEBVT_SHIFT               (30U)
22094 /*! TEBVT - Termination Enable BDL VT Compensation
22095  */
22096 #define DDRPHY_DX1GCR3_TEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_TEBVT_SHIFT)) & DDRPHY_DX1GCR3_TEBVT_MASK)
22097 #define DDRPHY_DX1GCR3_OEBVT_MASK                (0x80000000U)
22098 #define DDRPHY_DX1GCR3_OEBVT_SHIFT               (31U)
22099 /*! OEBVT - Output Enable BDL VT Compensation
22100  */
22101 #define DDRPHY_DX1GCR3_OEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_OEBVT_SHIFT)) & DDRPHY_DX1GCR3_OEBVT_MASK)
22102 /*! @} */
22103 
22104 /*! @name DX1GCR4 - DATX8 n General Configuration Register 4 */
22105 /*! @{ */
22106 #define DDRPHY_DX1GCR4_DXREFIMON_MASK            (0x3U)
22107 #define DDRPHY_DX1GCR4_DXREFIMON_SHIFT           (0U)
22108 /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
22109  */
22110 #define DDRPHY_DX1GCR4_DXREFIMON(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX1GCR4_DXREFIMON_MASK)
22111 #define DDRPHY_DX1GCR4_DXREFIEN_MASK             (0x3CU)
22112 #define DDRPHY_DX1GCR4_DXREFIEN_SHIFT            (2U)
22113 /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
22114  */
22115 #define DDRPHY_DX1GCR4_DXREFIEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFIEN_MASK)
22116 #define DDRPHY_DX1GCR4_RESERVED_7_6_MASK         (0xC0U)
22117 #define DDRPHY_DX1GCR4_RESERVED_7_6_SHIFT        (6U)
22118 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
22119  */
22120 #define DDRPHY_DX1GCR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR4_RESERVED_7_6_MASK)
22121 #define DDRPHY_DX1GCR4_DXREFSSEL_MASK            (0x7F00U)
22122 #define DDRPHY_DX1GCR4_DXREFSSEL_SHIFT           (8U)
22123 /*! DXREFSSEL - Byte Lane Single-End VREF Select
22124  */
22125 #define DDRPHY_DX1GCR4_DXREFSSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX1GCR4_DXREFSSEL_MASK)
22126 #define DDRPHY_DX1GCR4_DXREFSSELRANGE_MASK       (0x8000U)
22127 #define DDRPHY_DX1GCR4_DXREFSSELRANGE_SHIFT      (15U)
22128 /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
22129  */
22130 #define DDRPHY_DX1GCR4_DXREFSSELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX1GCR4_DXREFSSELRANGE_MASK)
22131 #define DDRPHY_DX1GCR4_DXREFESEL_MASK            (0x7F0000U)
22132 #define DDRPHY_DX1GCR4_DXREFESEL_SHIFT           (16U)
22133 /*! DXREFESEL - Byte Lane External VREF Select
22134  */
22135 #define DDRPHY_DX1GCR4_DXREFESEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX1GCR4_DXREFESEL_MASK)
22136 #define DDRPHY_DX1GCR4_DXREFESELRANGE_MASK       (0x800000U)
22137 #define DDRPHY_DX1GCR4_DXREFESELRANGE_SHIFT      (23U)
22138 /*! DXREFESELRANGE - External VREF generator REFSEL range select
22139  */
22140 #define DDRPHY_DX1GCR4_DXREFESELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX1GCR4_DXREFESELRANGE_MASK)
22141 #define DDRPHY_DX1GCR4_RESERVED_24_MASK          (0x1000000U)
22142 #define DDRPHY_DX1GCR4_RESERVED_24_SHIFT         (24U)
22143 /*! RESERVED_24 - Reserved. Returns zeros on reads.
22144  */
22145 #define DDRPHY_DX1GCR4_RESERVED_24(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX1GCR4_RESERVED_24_MASK)
22146 #define DDRPHY_DX1GCR4_DXREFSEN_MASK             (0x2000000U)
22147 #define DDRPHY_DX1GCR4_DXREFSEN_SHIFT            (25U)
22148 /*! DXREFSEN - Byte Lane Single-End VREF Enable
22149  */
22150 #define DDRPHY_DX1GCR4_DXREFSEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFSEN_MASK)
22151 #define DDRPHY_DX1GCR4_DXREFEEN_MASK             (0xC000000U)
22152 #define DDRPHY_DX1GCR4_DXREFEEN_SHIFT            (26U)
22153 /*! DXREFEEN - Byte Lane Internal VREF Enable
22154  */
22155 #define DDRPHY_DX1GCR4_DXREFEEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFEEN_MASK)
22156 #define DDRPHY_DX1GCR4_DXREFPEN_MASK             (0x10000000U)
22157 #define DDRPHY_DX1GCR4_DXREFPEN_SHIFT            (28U)
22158 /*! DXREFPEN - Byte Lane VREF Pad Enable
22159  */
22160 #define DDRPHY_DX1GCR4_DXREFPEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFPEN_MASK)
22161 #define DDRPHY_DX1GCR4_RESERVED_31_29_MASK       (0xE0000000U)
22162 #define DDRPHY_DX1GCR4_RESERVED_31_29_SHIFT      (29U)
22163 /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
22164  */
22165 #define DDRPHY_DX1GCR4_RESERVED_31_29(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX1GCR4_RESERVED_31_29_MASK)
22166 /*! @} */
22167 
22168 /*! @name DX1GCR5 - DATX8 n General Configuration Register 5 */
22169 /*! @{ */
22170 #define DDRPHY_DX1GCR5_DXREFISELR0_MASK          (0x7FU)
22171 #define DDRPHY_DX1GCR5_DXREFISELR0_SHIFT         (0U)
22172 /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
22173  */
22174 #define DDRPHY_DX1GCR5_DXREFISELR0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR0_MASK)
22175 #define DDRPHY_DX1GCR5_RESERVED_7_MASK           (0x80U)
22176 #define DDRPHY_DX1GCR5_RESERVED_7_SHIFT          (7U)
22177 /*! RESERVED_7 - Reserved. Returns zeros on reads.
22178  */
22179 #define DDRPHY_DX1GCR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_7_MASK)
22180 #define DDRPHY_DX1GCR5_DXREFISELR1_MASK          (0x7F00U)
22181 #define DDRPHY_DX1GCR5_DXREFISELR1_SHIFT         (8U)
22182 /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
22183  */
22184 #define DDRPHY_DX1GCR5_DXREFISELR1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR1_MASK)
22185 #define DDRPHY_DX1GCR5_RESERVED_15_MASK          (0x8000U)
22186 #define DDRPHY_DX1GCR5_RESERVED_15_SHIFT         (15U)
22187 /*! RESERVED_15 - Reserved. Returns zeros on reads.
22188  */
22189 #define DDRPHY_DX1GCR5_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_15_MASK)
22190 #define DDRPHY_DX1GCR5_DXREFISELR2_MASK          (0x7F0000U)
22191 #define DDRPHY_DX1GCR5_DXREFISELR2_SHIFT         (16U)
22192 /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
22193  */
22194 #define DDRPHY_DX1GCR5_DXREFISELR2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR2_MASK)
22195 #define DDRPHY_DX1GCR5_RESERVED_23_MASK          (0x800000U)
22196 #define DDRPHY_DX1GCR5_RESERVED_23_SHIFT         (23U)
22197 /*! RESERVED_23 - Reserved. Returns zeros on reads.
22198  */
22199 #define DDRPHY_DX1GCR5_RESERVED_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_23_MASK)
22200 #define DDRPHY_DX1GCR5_DXREFISELR3_MASK          (0x7F000000U)
22201 #define DDRPHY_DX1GCR5_DXREFISELR3_SHIFT         (24U)
22202 /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
22203  */
22204 #define DDRPHY_DX1GCR5_DXREFISELR3(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR3_MASK)
22205 #define DDRPHY_DX1GCR5_RESERVED_31_MASK          (0x80000000U)
22206 #define DDRPHY_DX1GCR5_RESERVED_31_SHIFT         (31U)
22207 /*! RESERVED_31 - Reserved. Returns zeros on reads.
22208  */
22209 #define DDRPHY_DX1GCR5_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_31_MASK)
22210 /*! @} */
22211 
22212 /*! @name DX1GCR6 - DATX8 n General Configuration Register 6 */
22213 /*! @{ */
22214 #define DDRPHY_DX1GCR6_DXDQVREFR0_MASK           (0x3FU)
22215 #define DDRPHY_DX1GCR6_DXDQVREFR0_SHIFT          (0U)
22216 /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
22217  */
22218 #define DDRPHY_DX1GCR6_DXDQVREFR0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR0_MASK)
22219 #define DDRPHY_DX1GCR6_RESERVED_7_6_MASK         (0xC0U)
22220 #define DDRPHY_DX1GCR6_RESERVED_7_6_SHIFT        (6U)
22221 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
22222  */
22223 #define DDRPHY_DX1GCR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_7_6_MASK)
22224 #define DDRPHY_DX1GCR6_DXDQVREFR1_MASK           (0x3F00U)
22225 #define DDRPHY_DX1GCR6_DXDQVREFR1_SHIFT          (8U)
22226 /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
22227  */
22228 #define DDRPHY_DX1GCR6_DXDQVREFR1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR1_MASK)
22229 #define DDRPHY_DX1GCR6_RESERVED_15_14_MASK       (0xC000U)
22230 #define DDRPHY_DX1GCR6_RESERVED_15_14_SHIFT      (14U)
22231 /*! RESERVED_15_14 - Reserved. Returns zeros on reads.
22232  */
22233 #define DDRPHY_DX1GCR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_15_14_MASK)
22234 #define DDRPHY_DX1GCR6_DXDQVREFR2_MASK           (0x3F0000U)
22235 #define DDRPHY_DX1GCR6_DXDQVREFR2_SHIFT          (16U)
22236 /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
22237  */
22238 #define DDRPHY_DX1GCR6_DXDQVREFR2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR2_MASK)
22239 #define DDRPHY_DX1GCR6_RESERVED_23_22_MASK       (0xC00000U)
22240 #define DDRPHY_DX1GCR6_RESERVED_23_22_SHIFT      (22U)
22241 /*! RESERVED_23_22 - Reserved. Returns zeros on reads.
22242  */
22243 #define DDRPHY_DX1GCR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_23_22_MASK)
22244 #define DDRPHY_DX1GCR6_DXDQVREFR3_MASK           (0x3F000000U)
22245 #define DDRPHY_DX1GCR6_DXDQVREFR3_SHIFT          (24U)
22246 /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
22247  */
22248 #define DDRPHY_DX1GCR6_DXDQVREFR3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR3_MASK)
22249 #define DDRPHY_DX1GCR6_RESERVED_31_30_MASK       (0xC0000000U)
22250 #define DDRPHY_DX1GCR6_RESERVED_31_30_SHIFT      (30U)
22251 /*! RESERVED_31_30 - Reserved. Returns zeros on reads.
22252  */
22253 #define DDRPHY_DX1GCR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_31_30_MASK)
22254 /*! @} */
22255 
22256 /*! @name DX1GCR7 - DATX8 n General Configuration Register 7 */
22257 /*! @{ */
22258 #define DDRPHY_DX1GCR7_DCALSVAL_MASK             (0x1FFU)
22259 #define DDRPHY_DX1GCR7_DCALSVAL_SHIFT            (0U)
22260 /*! DCALSVAL - DDL Calibration Starting Value
22261  */
22262 #define DDRPHY_DX1GCR7_DCALSVAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX1GCR7_DCALSVAL_MASK)
22263 #define DDRPHY_DX1GCR7_DCALTYPE_MASK             (0x200U)
22264 #define DDRPHY_DX1GCR7_DCALTYPE_SHIFT            (9U)
22265 /*! DCALTYPE - DDL Calibration Type
22266  */
22267 #define DDRPHY_DX1GCR7_DCALTYPE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX1GCR7_DCALTYPE_MASK)
22268 #define DDRPHY_DX1GCR7_RESERVED_17_10_MASK       (0x3FC00U)
22269 #define DDRPHY_DX1GCR7_RESERVED_17_10_SHIFT      (10U)
22270 /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
22271  */
22272 #define DDRPHY_DX1GCR7_RESERVED_17_10(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX1GCR7_RESERVED_17_10_MASK)
22273 #define DDRPHY_DX1GCR7_RESERVED_18_MASK          (0x40000U)
22274 #define DDRPHY_DX1GCR7_RESERVED_18_SHIFT         (18U)
22275 /*! RESERVED_18 - Reserved. Caution, do not write to this register field.
22276  */
22277 #define DDRPHY_DX1GCR7_RESERVED_18(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX1GCR7_RESERVED_18_MASK)
22278 #define DDRPHY_DX1GCR7_RESERVED_31_19_MASK       (0xFFF80000U)
22279 #define DDRPHY_DX1GCR7_RESERVED_31_19_SHIFT      (19U)
22280 /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
22281  */
22282 #define DDRPHY_DX1GCR7_RESERVED_31_19(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX1GCR7_RESERVED_31_19_MASK)
22283 /*! @} */
22284 
22285 /*! @name DX1GCR8 - DATX8 n General Configuration Register 8 */
22286 /*! @{ */
22287 #define DDRPHY_DX1GCR8_RESERVED_5_0_MASK         (0x3FU)
22288 #define DDRPHY_DX1GCR8_RESERVED_5_0_SHIFT        (0U)
22289 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22290  */
22291 #define DDRPHY_DX1GCR8_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_5_0_MASK)
22292 #define DDRPHY_DX1GCR8_RESERVED_7_6_MASK         (0xC0U)
22293 #define DDRPHY_DX1GCR8_RESERVED_7_6_SHIFT        (6U)
22294 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22295  */
22296 #define DDRPHY_DX1GCR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_7_6_MASK)
22297 #define DDRPHY_DX1GCR8_RESERVED_13_8_MASK        (0x3F00U)
22298 #define DDRPHY_DX1GCR8_RESERVED_13_8_SHIFT       (8U)
22299 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22300  */
22301 #define DDRPHY_DX1GCR8_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_13_8_MASK)
22302 #define DDRPHY_DX1GCR8_RESERVED_15_14_MASK       (0xC000U)
22303 #define DDRPHY_DX1GCR8_RESERVED_15_14_SHIFT      (14U)
22304 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22305  */
22306 #define DDRPHY_DX1GCR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_15_14_MASK)
22307 #define DDRPHY_DX1GCR8_RESERVED_21_16_MASK       (0x3F0000U)
22308 #define DDRPHY_DX1GCR8_RESERVED_21_16_SHIFT      (16U)
22309 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22310  */
22311 #define DDRPHY_DX1GCR8_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_21_16_MASK)
22312 #define DDRPHY_DX1GCR8_RESERVED_23_22_MASK       (0xC00000U)
22313 #define DDRPHY_DX1GCR8_RESERVED_23_22_SHIFT      (22U)
22314 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22315  */
22316 #define DDRPHY_DX1GCR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_23_22_MASK)
22317 #define DDRPHY_DX1GCR8_RESERVED_29_24_MASK       (0x3F000000U)
22318 #define DDRPHY_DX1GCR8_RESERVED_29_24_SHIFT      (24U)
22319 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
22320  */
22321 #define DDRPHY_DX1GCR8_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_29_24_MASK)
22322 #define DDRPHY_DX1GCR8_RESERVED_31_30_MASK       (0xC0000000U)
22323 #define DDRPHY_DX1GCR8_RESERVED_31_30_SHIFT      (30U)
22324 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22325  */
22326 #define DDRPHY_DX1GCR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_31_30_MASK)
22327 /*! @} */
22328 
22329 /*! @name DX1GCR9 - DATX8 n General Configuration Register 9 */
22330 /*! @{ */
22331 #define DDRPHY_DX1GCR9_RESERVED_5_0_MASK         (0x3FU)
22332 #define DDRPHY_DX1GCR9_RESERVED_5_0_SHIFT        (0U)
22333 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22334  */
22335 #define DDRPHY_DX1GCR9_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_5_0_MASK)
22336 #define DDRPHY_DX1GCR9_RESERVED_7_6_MASK         (0xC0U)
22337 #define DDRPHY_DX1GCR9_RESERVED_7_6_SHIFT        (6U)
22338 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22339  */
22340 #define DDRPHY_DX1GCR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_7_6_MASK)
22341 #define DDRPHY_DX1GCR9_RESERVED_13_8_MASK        (0x3F00U)
22342 #define DDRPHY_DX1GCR9_RESERVED_13_8_SHIFT       (8U)
22343 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22344  */
22345 #define DDRPHY_DX1GCR9_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_13_8_MASK)
22346 #define DDRPHY_DX1GCR9_RESERVED_15_14_MASK       (0xC000U)
22347 #define DDRPHY_DX1GCR9_RESERVED_15_14_SHIFT      (14U)
22348 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22349  */
22350 #define DDRPHY_DX1GCR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_15_14_MASK)
22351 #define DDRPHY_DX1GCR9_RESERVED_21_16_MASK       (0x3F0000U)
22352 #define DDRPHY_DX1GCR9_RESERVED_21_16_SHIFT      (16U)
22353 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22354  */
22355 #define DDRPHY_DX1GCR9_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_21_16_MASK)
22356 #define DDRPHY_DX1GCR9_RESERVED_23_22_MASK       (0xC00000U)
22357 #define DDRPHY_DX1GCR9_RESERVED_23_22_SHIFT      (22U)
22358 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22359  */
22360 #define DDRPHY_DX1GCR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_23_22_MASK)
22361 #define DDRPHY_DX1GCR9_RESERVED_29_24_MASK       (0x3F000000U)
22362 #define DDRPHY_DX1GCR9_RESERVED_29_24_SHIFT      (24U)
22363 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
22364  */
22365 #define DDRPHY_DX1GCR9_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_29_24_MASK)
22366 #define DDRPHY_DX1GCR9_RESERVED_31_30_MASK       (0xC0000000U)
22367 #define DDRPHY_DX1GCR9_RESERVED_31_30_SHIFT      (30U)
22368 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22369  */
22370 #define DDRPHY_DX1GCR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_31_30_MASK)
22371 /*! @} */
22372 
22373 /*! @name DX1DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
22374 /*! @{ */
22375 #define DDRPHY_DX1DQMAP0_DQ0MAP_MASK             (0xFU)
22376 #define DDRPHY_DX1DQMAP0_DQ0MAP_SHIFT            (0U)
22377 /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
22378  */
22379 #define DDRPHY_DX1DQMAP0_DQ0MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ0MAP_MASK)
22380 #define DDRPHY_DX1DQMAP0_DQ1MAP_MASK             (0xF0U)
22381 #define DDRPHY_DX1DQMAP0_DQ1MAP_SHIFT            (4U)
22382 /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
22383  */
22384 #define DDRPHY_DX1DQMAP0_DQ1MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ1MAP_MASK)
22385 #define DDRPHY_DX1DQMAP0_DQ2MAP_MASK             (0xF00U)
22386 #define DDRPHY_DX1DQMAP0_DQ2MAP_SHIFT            (8U)
22387 /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
22388  */
22389 #define DDRPHY_DX1DQMAP0_DQ2MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ2MAP_MASK)
22390 #define DDRPHY_DX1DQMAP0_DQ3MAP_MASK             (0xF000U)
22391 #define DDRPHY_DX1DQMAP0_DQ3MAP_SHIFT            (12U)
22392 /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
22393  */
22394 #define DDRPHY_DX1DQMAP0_DQ3MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ3MAP_MASK)
22395 #define DDRPHY_DX1DQMAP0_DQ4MAP_MASK             (0xF0000U)
22396 #define DDRPHY_DX1DQMAP0_DQ4MAP_SHIFT            (16U)
22397 /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
22398  */
22399 #define DDRPHY_DX1DQMAP0_DQ4MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ4MAP_MASK)
22400 #define DDRPHY_DX1DQMAP0_RESERVED_30_20_MASK     (0x7FF00000U)
22401 #define DDRPHY_DX1DQMAP0_RESERVED_30_20_SHIFT    (20U)
22402 /*! RESERVED_30_20 - Reserved. Return zeroes on reads.
22403  */
22404 #define DDRPHY_DX1DQMAP0_RESERVED_30_20(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX1DQMAP0_RESERVED_30_20_MASK)
22405 #define DDRPHY_DX1DQMAP0_MAPOK_MASK              (0x80000000U)
22406 #define DDRPHY_DX1DQMAP0_MAPOK_SHIFT             (31U)
22407 /*! MAPOK - Checksum bit
22408  */
22409 #define DDRPHY_DX1DQMAP0_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX1DQMAP0_MAPOK_MASK)
22410 /*! @} */
22411 
22412 /*! @name DX1DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
22413 /*! @{ */
22414 #define DDRPHY_DX1DQMAP1_DQ5MAP_MASK             (0xFU)
22415 #define DDRPHY_DX1DQMAP1_DQ5MAP_SHIFT            (0U)
22416 /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
22417  */
22418 #define DDRPHY_DX1DQMAP1_DQ5MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX1DQMAP1_DQ5MAP_MASK)
22419 #define DDRPHY_DX1DQMAP1_DQ6MAP_MASK             (0xF0U)
22420 #define DDRPHY_DX1DQMAP1_DQ6MAP_SHIFT            (4U)
22421 /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
22422  */
22423 #define DDRPHY_DX1DQMAP1_DQ6MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX1DQMAP1_DQ6MAP_MASK)
22424 #define DDRPHY_DX1DQMAP1_DQ7MAP_MASK             (0xF00U)
22425 #define DDRPHY_DX1DQMAP1_DQ7MAP_SHIFT            (8U)
22426 /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
22427  */
22428 #define DDRPHY_DX1DQMAP1_DQ7MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX1DQMAP1_DQ7MAP_MASK)
22429 #define DDRPHY_DX1DQMAP1_DMMAP_MASK              (0xF000U)
22430 #define DDRPHY_DX1DQMAP1_DMMAP_SHIFT             (12U)
22431 /*! DMMAP - DM bit DATX8 slice mapping index
22432  */
22433 #define DDRPHY_DX1DQMAP1_DMMAP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX1DQMAP1_DMMAP_MASK)
22434 #define DDRPHY_DX1DQMAP1_RESERVED_30_16_MASK     (0x7FFF0000U)
22435 #define DDRPHY_DX1DQMAP1_RESERVED_30_16_SHIFT    (16U)
22436 /*! RESERVED_30_16 - Reserved. Return zeroes on reads.
22437  */
22438 #define DDRPHY_DX1DQMAP1_RESERVED_30_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX1DQMAP1_RESERVED_30_16_MASK)
22439 #define DDRPHY_DX1DQMAP1_MAPOK_MASK              (0x80000000U)
22440 #define DDRPHY_DX1DQMAP1_MAPOK_SHIFT             (31U)
22441 /*! MAPOK - Checksum bit
22442  */
22443 #define DDRPHY_DX1DQMAP1_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX1DQMAP1_MAPOK_MASK)
22444 /*! @} */
22445 
22446 /*! @name DX1BDLR0 - DATX8 n Bit Delay Line Register 0 */
22447 /*! @{ */
22448 #define DDRPHY_DX1BDLR0_DQ0WBD_MASK              (0x3FU)
22449 #define DDRPHY_DX1BDLR0_DQ0WBD_SHIFT             (0U)
22450 /*! DQ0WBD - DQ0 Write Bit Delay
22451  */
22452 #define DDRPHY_DX1BDLR0_DQ0WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ0WBD_MASK)
22453 #define DDRPHY_DX1BDLR0_RESERVED_7_6_MASK        (0xC0U)
22454 #define DDRPHY_DX1BDLR0_RESERVED_7_6_SHIFT       (6U)
22455 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22456  */
22457 #define DDRPHY_DX1BDLR0_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_7_6_MASK)
22458 #define DDRPHY_DX1BDLR0_DQ1WBD_MASK              (0x3F00U)
22459 #define DDRPHY_DX1BDLR0_DQ1WBD_SHIFT             (8U)
22460 /*! DQ1WBD - DQ1 Write Bit Delay
22461  */
22462 #define DDRPHY_DX1BDLR0_DQ1WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ1WBD_MASK)
22463 #define DDRPHY_DX1BDLR0_RESERVED_15_14_MASK      (0xC000U)
22464 #define DDRPHY_DX1BDLR0_RESERVED_15_14_SHIFT     (14U)
22465 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22466  */
22467 #define DDRPHY_DX1BDLR0_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_15_14_MASK)
22468 #define DDRPHY_DX1BDLR0_DQ2WBD_MASK              (0x3F0000U)
22469 #define DDRPHY_DX1BDLR0_DQ2WBD_SHIFT             (16U)
22470 /*! DQ2WBD - DQ2 Write Bit Delay
22471  */
22472 #define DDRPHY_DX1BDLR0_DQ2WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ2WBD_MASK)
22473 #define DDRPHY_DX1BDLR0_RESERVED_23_22_MASK      (0xC00000U)
22474 #define DDRPHY_DX1BDLR0_RESERVED_23_22_SHIFT     (22U)
22475 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22476  */
22477 #define DDRPHY_DX1BDLR0_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_23_22_MASK)
22478 #define DDRPHY_DX1BDLR0_DQ3WBD_MASK              (0x3F000000U)
22479 #define DDRPHY_DX1BDLR0_DQ3WBD_SHIFT             (24U)
22480 /*! DQ3WBD - DQ3 Write Bit Delay
22481  */
22482 #define DDRPHY_DX1BDLR0_DQ3WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ3WBD_MASK)
22483 #define DDRPHY_DX1BDLR0_RESERVED_31_30_MASK      (0xC0000000U)
22484 #define DDRPHY_DX1BDLR0_RESERVED_31_30_SHIFT     (30U)
22485 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22486  */
22487 #define DDRPHY_DX1BDLR0_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_31_30_MASK)
22488 /*! @} */
22489 
22490 /*! @name DX1BDLR1 - DATX8 n Bit Delay Line Register 1 */
22491 /*! @{ */
22492 #define DDRPHY_DX1BDLR1_DQ4WBD_MASK              (0x3FU)
22493 #define DDRPHY_DX1BDLR1_DQ4WBD_SHIFT             (0U)
22494 /*! DQ4WBD - DQ4 Write Bit Delay
22495  */
22496 #define DDRPHY_DX1BDLR1_DQ4WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ4WBD_MASK)
22497 #define DDRPHY_DX1BDLR1_RESERVED_7_6_MASK        (0xC0U)
22498 #define DDRPHY_DX1BDLR1_RESERVED_7_6_SHIFT       (6U)
22499 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22500  */
22501 #define DDRPHY_DX1BDLR1_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_7_6_MASK)
22502 #define DDRPHY_DX1BDLR1_DQ5WBD_MASK              (0x3F00U)
22503 #define DDRPHY_DX1BDLR1_DQ5WBD_SHIFT             (8U)
22504 /*! DQ5WBD - DQ5 Write Bit Delay
22505  */
22506 #define DDRPHY_DX1BDLR1_DQ5WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ5WBD_MASK)
22507 #define DDRPHY_DX1BDLR1_RESERVED_15_14_MASK      (0xC000U)
22508 #define DDRPHY_DX1BDLR1_RESERVED_15_14_SHIFT     (14U)
22509 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22510  */
22511 #define DDRPHY_DX1BDLR1_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_15_14_MASK)
22512 #define DDRPHY_DX1BDLR1_DQ6WBD_MASK              (0x3F0000U)
22513 #define DDRPHY_DX1BDLR1_DQ6WBD_SHIFT             (16U)
22514 /*! DQ6WBD - DQ6 Write Bit Delay
22515  */
22516 #define DDRPHY_DX1BDLR1_DQ6WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ6WBD_MASK)
22517 #define DDRPHY_DX1BDLR1_RESERVED_23_22_MASK      (0xC00000U)
22518 #define DDRPHY_DX1BDLR1_RESERVED_23_22_SHIFT     (22U)
22519 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22520  */
22521 #define DDRPHY_DX1BDLR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_23_22_MASK)
22522 #define DDRPHY_DX1BDLR1_DQ7WBD_MASK              (0x3F000000U)
22523 #define DDRPHY_DX1BDLR1_DQ7WBD_SHIFT             (24U)
22524 /*! DQ7WBD - DQ7 Write Bit Delay
22525  */
22526 #define DDRPHY_DX1BDLR1_DQ7WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ7WBD_MASK)
22527 #define DDRPHY_DX1BDLR1_RESERVED_31_30_MASK      (0xC0000000U)
22528 #define DDRPHY_DX1BDLR1_RESERVED_31_30_SHIFT     (30U)
22529 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22530  */
22531 #define DDRPHY_DX1BDLR1_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_31_30_MASK)
22532 /*! @} */
22533 
22534 /*! @name DX1BDLR2 - DATX8 n Bit Delay Line Register 2 */
22535 /*! @{ */
22536 #define DDRPHY_DX1BDLR2_DMWBD_MASK               (0x3FU)
22537 #define DDRPHY_DX1BDLR2_DMWBD_SHIFT              (0U)
22538 /*! DMWBD - DM Write Bit Delay
22539  */
22540 #define DDRPHY_DX1BDLR2_DMWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DMWBD_SHIFT)) & DDRPHY_DX1BDLR2_DMWBD_MASK)
22541 #define DDRPHY_DX1BDLR2_RESERVED_7_6_MASK        (0xC0U)
22542 #define DDRPHY_DX1BDLR2_RESERVED_7_6_SHIFT       (6U)
22543 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22544  */
22545 #define DDRPHY_DX1BDLR2_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_7_6_MASK)
22546 #define DDRPHY_DX1BDLR2_DSWBD_MASK               (0x3F00U)
22547 #define DDRPHY_DX1BDLR2_DSWBD_SHIFT              (8U)
22548 /*! DSWBD - DQS Write Bit Delay
22549  */
22550 #define DDRPHY_DX1BDLR2_DSWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DSWBD_SHIFT)) & DDRPHY_DX1BDLR2_DSWBD_MASK)
22551 #define DDRPHY_DX1BDLR2_RESERVED_15_14_MASK      (0xC000U)
22552 #define DDRPHY_DX1BDLR2_RESERVED_15_14_SHIFT     (14U)
22553 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22554  */
22555 #define DDRPHY_DX1BDLR2_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_15_14_MASK)
22556 #define DDRPHY_DX1BDLR2_DSOEBD_MASK              (0x3F0000U)
22557 #define DDRPHY_DX1BDLR2_DSOEBD_SHIFT             (16U)
22558 /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
22559  */
22560 #define DDRPHY_DX1BDLR2_DSOEBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX1BDLR2_DSOEBD_MASK)
22561 #define DDRPHY_DX1BDLR2_RESERVED_23_22_MASK      (0xC00000U)
22562 #define DDRPHY_DX1BDLR2_RESERVED_23_22_SHIFT     (22U)
22563 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22564  */
22565 #define DDRPHY_DX1BDLR2_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_23_22_MASK)
22566 #define DDRPHY_DX1BDLR2_DSNWBD_MASK              (0x3F000000U)
22567 #define DDRPHY_DX1BDLR2_DSNWBD_SHIFT             (24U)
22568 /*! DSNWBD - DQSN Write Bit Delay
22569  */
22570 #define DDRPHY_DX1BDLR2_DSNWBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX1BDLR2_DSNWBD_MASK)
22571 #define DDRPHY_DX1BDLR2_RESERVED_31_30_MASK      (0xC0000000U)
22572 #define DDRPHY_DX1BDLR2_RESERVED_31_30_SHIFT     (30U)
22573 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22574  */
22575 #define DDRPHY_DX1BDLR2_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_31_30_MASK)
22576 /*! @} */
22577 
22578 /*! @name DX1BDLR3 - DATX8 n Bit Delay Line Register 3 */
22579 /*! @{ */
22580 #define DDRPHY_DX1BDLR3_DQ0RBD_MASK              (0x3FU)
22581 #define DDRPHY_DX1BDLR3_DQ0RBD_SHIFT             (0U)
22582 /*! DQ0RBD - DQ0 Read Bit Delay
22583  */
22584 #define DDRPHY_DX1BDLR3_DQ0RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ0RBD_MASK)
22585 #define DDRPHY_DX1BDLR3_RESERVED_7_6_MASK        (0xC0U)
22586 #define DDRPHY_DX1BDLR3_RESERVED_7_6_SHIFT       (6U)
22587 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22588  */
22589 #define DDRPHY_DX1BDLR3_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_7_6_MASK)
22590 #define DDRPHY_DX1BDLR3_DQ1RBD_MASK              (0x3F00U)
22591 #define DDRPHY_DX1BDLR3_DQ1RBD_SHIFT             (8U)
22592 /*! DQ1RBD - DQ1 Read Bit Delay
22593  */
22594 #define DDRPHY_DX1BDLR3_DQ1RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ1RBD_MASK)
22595 #define DDRPHY_DX1BDLR3_RESERVED_15_14_MASK      (0xC000U)
22596 #define DDRPHY_DX1BDLR3_RESERVED_15_14_SHIFT     (14U)
22597 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22598  */
22599 #define DDRPHY_DX1BDLR3_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_15_14_MASK)
22600 #define DDRPHY_DX1BDLR3_DQ2RBD_MASK              (0x3F0000U)
22601 #define DDRPHY_DX1BDLR3_DQ2RBD_SHIFT             (16U)
22602 /*! DQ2RBD - DQ2 Read Bit Delay
22603  */
22604 #define DDRPHY_DX1BDLR3_DQ2RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ2RBD_MASK)
22605 #define DDRPHY_DX1BDLR3_RESERVED_23_22_MASK      (0xC00000U)
22606 #define DDRPHY_DX1BDLR3_RESERVED_23_22_SHIFT     (22U)
22607 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22608  */
22609 #define DDRPHY_DX1BDLR3_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_23_22_MASK)
22610 #define DDRPHY_DX1BDLR3_DQ3RBD_MASK              (0x3F000000U)
22611 #define DDRPHY_DX1BDLR3_DQ3RBD_SHIFT             (24U)
22612 /*! DQ3RBD - DQ3 Read Bit Delay
22613  */
22614 #define DDRPHY_DX1BDLR3_DQ3RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ3RBD_MASK)
22615 #define DDRPHY_DX1BDLR3_RESERVED_31_30_MASK      (0xC0000000U)
22616 #define DDRPHY_DX1BDLR3_RESERVED_31_30_SHIFT     (30U)
22617 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22618  */
22619 #define DDRPHY_DX1BDLR3_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_31_30_MASK)
22620 /*! @} */
22621 
22622 /*! @name DX1BDLR4 - DATX8 n Bit Delay Line Register 4 */
22623 /*! @{ */
22624 #define DDRPHY_DX1BDLR4_DQ4RBD_MASK              (0x3FU)
22625 #define DDRPHY_DX1BDLR4_DQ4RBD_SHIFT             (0U)
22626 /*! DQ4RBD - DQ4 Read Bit Delay
22627  */
22628 #define DDRPHY_DX1BDLR4_DQ4RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ4RBD_MASK)
22629 #define DDRPHY_DX1BDLR4_RESERVED_7_6_MASK        (0xC0U)
22630 #define DDRPHY_DX1BDLR4_RESERVED_7_6_SHIFT       (6U)
22631 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22632  */
22633 #define DDRPHY_DX1BDLR4_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_7_6_MASK)
22634 #define DDRPHY_DX1BDLR4_DQ5RBD_MASK              (0x3F00U)
22635 #define DDRPHY_DX1BDLR4_DQ5RBD_SHIFT             (8U)
22636 /*! DQ5RBD - DQ5 Read Bit Delay
22637  */
22638 #define DDRPHY_DX1BDLR4_DQ5RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ5RBD_MASK)
22639 #define DDRPHY_DX1BDLR4_RESERVED_15_14_MASK      (0xC000U)
22640 #define DDRPHY_DX1BDLR4_RESERVED_15_14_SHIFT     (14U)
22641 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22642  */
22643 #define DDRPHY_DX1BDLR4_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_15_14_MASK)
22644 #define DDRPHY_DX1BDLR4_DQ6RBD_MASK              (0x3F0000U)
22645 #define DDRPHY_DX1BDLR4_DQ6RBD_SHIFT             (16U)
22646 /*! DQ6RBD - DQ6 Read Bit Delay
22647  */
22648 #define DDRPHY_DX1BDLR4_DQ6RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ6RBD_MASK)
22649 #define DDRPHY_DX1BDLR4_RESERVED_23_22_MASK      (0xC00000U)
22650 #define DDRPHY_DX1BDLR4_RESERVED_23_22_SHIFT     (22U)
22651 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22652  */
22653 #define DDRPHY_DX1BDLR4_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_23_22_MASK)
22654 #define DDRPHY_DX1BDLR4_DQ7RBD_MASK              (0x3F000000U)
22655 #define DDRPHY_DX1BDLR4_DQ7RBD_SHIFT             (24U)
22656 /*! DQ7RBD - DQ7 Read Bit Delay
22657  */
22658 #define DDRPHY_DX1BDLR4_DQ7RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ7RBD_MASK)
22659 #define DDRPHY_DX1BDLR4_RESERVED_31_30_MASK      (0xC0000000U)
22660 #define DDRPHY_DX1BDLR4_RESERVED_31_30_SHIFT     (30U)
22661 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22662  */
22663 #define DDRPHY_DX1BDLR4_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_31_30_MASK)
22664 /*! @} */
22665 
22666 /*! @name DX1BDLR5 - DATX8 n Bit Delay Line Register 5 */
22667 /*! @{ */
22668 #define DDRPHY_DX1BDLR5_DMRBD_MASK               (0x3FU)
22669 #define DDRPHY_DX1BDLR5_DMRBD_SHIFT              (0U)
22670 /*! DMRBD - DM Read Bit Delay
22671  */
22672 #define DDRPHY_DX1BDLR5_DMRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR5_DMRBD_SHIFT)) & DDRPHY_DX1BDLR5_DMRBD_MASK)
22673 #define DDRPHY_DX1BDLR5_RESERVED_31_6_MASK       (0xFFFFFFC0U)
22674 #define DDRPHY_DX1BDLR5_RESERVED_31_6_SHIFT      (6U)
22675 /*! RESERVED_31_6 - Reserved. Return zeroes on reads.
22676  */
22677 #define DDRPHY_DX1BDLR5_RESERVED_31_6(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX1BDLR5_RESERVED_31_6_MASK)
22678 /*! @} */
22679 
22680 /*! @name DX1BDLR6 - DATX8 n Bit Delay Line Register 6 */
22681 /*! @{ */
22682 #define DDRPHY_DX1BDLR6_RESERVED_7_0_MASK        (0xFFU)
22683 #define DDRPHY_DX1BDLR6_RESERVED_7_0_SHIFT       (0U)
22684 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
22685  */
22686 #define DDRPHY_DX1BDLR6_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX1BDLR6_RESERVED_7_0_MASK)
22687 #define DDRPHY_DX1BDLR6_PDRBD_MASK               (0x3F00U)
22688 #define DDRPHY_DX1BDLR6_PDRBD_SHIFT              (8U)
22689 /*! PDRBD - Power down receiver Bit Delay
22690  */
22691 #define DDRPHY_DX1BDLR6_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_PDRBD_SHIFT)) & DDRPHY_DX1BDLR6_PDRBD_MASK)
22692 #define DDRPHY_DX1BDLR6_RESERVED_15_14_MASK      (0xC000U)
22693 #define DDRPHY_DX1BDLR6_RESERVED_15_14_SHIFT     (14U)
22694 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22695  */
22696 #define DDRPHY_DX1BDLR6_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR6_RESERVED_15_14_MASK)
22697 #define DDRPHY_DX1BDLR6_TERBD_MASK               (0x3F0000U)
22698 #define DDRPHY_DX1BDLR6_TERBD_SHIFT              (16U)
22699 /*! TERBD - Termination Enable Bit Delay
22700  */
22701 #define DDRPHY_DX1BDLR6_TERBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_TERBD_SHIFT)) & DDRPHY_DX1BDLR6_TERBD_MASK)
22702 #define DDRPHY_DX1BDLR6_RESERVED_31_22_MASK      (0xFFC00000U)
22703 #define DDRPHY_DX1BDLR6_RESERVED_31_22_SHIFT     (22U)
22704 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
22705  */
22706 #define DDRPHY_DX1BDLR6_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR6_RESERVED_31_22_MASK)
22707 /*! @} */
22708 
22709 /*! @name DX1BDLR7 - DATX8 n Bit Delay Line Register 7 */
22710 /*! @{ */
22711 #define DDRPHY_DX1BDLR7_RESERVED_5_0_MASK        (0x3FU)
22712 #define DDRPHY_DX1BDLR7_RESERVED_5_0_SHIFT       (0U)
22713 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22714  */
22715 #define DDRPHY_DX1BDLR7_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_5_0_MASK)
22716 #define DDRPHY_DX1BDLR7_RESERVED_7_6_MASK        (0xC0U)
22717 #define DDRPHY_DX1BDLR7_RESERVED_7_6_SHIFT       (6U)
22718 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22719  */
22720 #define DDRPHY_DX1BDLR7_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_7_6_MASK)
22721 #define DDRPHY_DX1BDLR7_RESERVED_13_8_MASK       (0x3F00U)
22722 #define DDRPHY_DX1BDLR7_RESERVED_13_8_SHIFT      (8U)
22723 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22724  */
22725 #define DDRPHY_DX1BDLR7_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_13_8_MASK)
22726 #define DDRPHY_DX1BDLR7_RESERVED_15_14_MASK      (0xC000U)
22727 #define DDRPHY_DX1BDLR7_RESERVED_15_14_SHIFT     (14U)
22728 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22729  */
22730 #define DDRPHY_DX1BDLR7_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_15_14_MASK)
22731 #define DDRPHY_DX1BDLR7_RESERVED_21_16_MASK      (0x3F0000U)
22732 #define DDRPHY_DX1BDLR7_RESERVED_21_16_SHIFT     (16U)
22733 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22734  */
22735 #define DDRPHY_DX1BDLR7_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_21_16_MASK)
22736 #define DDRPHY_DX1BDLR7_RESERVED_31_22_MASK      (0xFFC00000U)
22737 #define DDRPHY_DX1BDLR7_RESERVED_31_22_SHIFT     (22U)
22738 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
22739  */
22740 #define DDRPHY_DX1BDLR7_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_31_22_MASK)
22741 /*! @} */
22742 
22743 /*! @name DX1BDLR8 - DATX8 n Bit Delay Line Register 8 */
22744 /*! @{ */
22745 #define DDRPHY_DX1BDLR8_RESERVED_5_0_MASK        (0x3FU)
22746 #define DDRPHY_DX1BDLR8_RESERVED_5_0_SHIFT       (0U)
22747 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22748  */
22749 #define DDRPHY_DX1BDLR8_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_5_0_MASK)
22750 #define DDRPHY_DX1BDLR8_RESERVED_7_6_MASK        (0xC0U)
22751 #define DDRPHY_DX1BDLR8_RESERVED_7_6_SHIFT       (6U)
22752 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22753  */
22754 #define DDRPHY_DX1BDLR8_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_7_6_MASK)
22755 #define DDRPHY_DX1BDLR8_RESERVED_13_8_MASK       (0x3F00U)
22756 #define DDRPHY_DX1BDLR8_RESERVED_13_8_SHIFT      (8U)
22757 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22758  */
22759 #define DDRPHY_DX1BDLR8_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_13_8_MASK)
22760 #define DDRPHY_DX1BDLR8_RESERVED_15_14_MASK      (0xC000U)
22761 #define DDRPHY_DX1BDLR8_RESERVED_15_14_SHIFT     (14U)
22762 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22763  */
22764 #define DDRPHY_DX1BDLR8_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_15_14_MASK)
22765 #define DDRPHY_DX1BDLR8_RESERVED_21_16_MASK      (0x3F0000U)
22766 #define DDRPHY_DX1BDLR8_RESERVED_21_16_SHIFT     (16U)
22767 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22768  */
22769 #define DDRPHY_DX1BDLR8_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_21_16_MASK)
22770 #define DDRPHY_DX1BDLR8_RESERVED_31_22_MASK      (0xFFC00000U)
22771 #define DDRPHY_DX1BDLR8_RESERVED_31_22_SHIFT     (22U)
22772 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
22773  */
22774 #define DDRPHY_DX1BDLR8_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_31_22_MASK)
22775 /*! @} */
22776 
22777 /*! @name DX1BDLR9 - DATX8 n Bit Delay Line Register 9 */
22778 /*! @{ */
22779 #define DDRPHY_DX1BDLR9_RESERVED_5_0_MASK        (0x3FU)
22780 #define DDRPHY_DX1BDLR9_RESERVED_5_0_SHIFT       (0U)
22781 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22782  */
22783 #define DDRPHY_DX1BDLR9_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_5_0_MASK)
22784 #define DDRPHY_DX1BDLR9_RESERVED_7_6_MASK        (0xC0U)
22785 #define DDRPHY_DX1BDLR9_RESERVED_7_6_SHIFT       (6U)
22786 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22787  */
22788 #define DDRPHY_DX1BDLR9_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_7_6_MASK)
22789 #define DDRPHY_DX1BDLR9_RESERVED_13_8_MASK       (0x3F00U)
22790 #define DDRPHY_DX1BDLR9_RESERVED_13_8_SHIFT      (8U)
22791 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22792  */
22793 #define DDRPHY_DX1BDLR9_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_13_8_MASK)
22794 #define DDRPHY_DX1BDLR9_RESERVED_15_14_MASK      (0xC000U)
22795 #define DDRPHY_DX1BDLR9_RESERVED_15_14_SHIFT     (14U)
22796 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22797  */
22798 #define DDRPHY_DX1BDLR9_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_15_14_MASK)
22799 #define DDRPHY_DX1BDLR9_RESERVED_21_16_MASK      (0x3F0000U)
22800 #define DDRPHY_DX1BDLR9_RESERVED_21_16_SHIFT     (16U)
22801 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22802  */
22803 #define DDRPHY_DX1BDLR9_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_21_16_MASK)
22804 #define DDRPHY_DX1BDLR9_RESERVED_31_22_MASK      (0xFFC00000U)
22805 #define DDRPHY_DX1BDLR9_RESERVED_31_22_SHIFT     (22U)
22806 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
22807  */
22808 #define DDRPHY_DX1BDLR9_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_31_22_MASK)
22809 /*! @} */
22810 
22811 /*! @name DX1LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
22812 /*! @{ */
22813 #define DDRPHY_DX1LCDLR0_WLD_MASK                (0x1FFU)
22814 #define DDRPHY_DX1LCDLR0_WLD_SHIFT               (0U)
22815 /*! WLD - Write Leveling Delay
22816  */
22817 #define DDRPHY_DX1LCDLR0_WLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_WLD_SHIFT)) & DDRPHY_DX1LCDLR0_WLD_MASK)
22818 #define DDRPHY_DX1LCDLR0_RESERVED_15_9_MASK      (0xFE00U)
22819 #define DDRPHY_DX1LCDLR0_RESERVED_15_9_SHIFT     (9U)
22820 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22821  */
22822 #define DDRPHY_DX1LCDLR0_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR0_RESERVED_15_9_MASK)
22823 #define DDRPHY_DX1LCDLR0_RESERVED_24_16_MASK     (0x1FF0000U)
22824 #define DDRPHY_DX1LCDLR0_RESERVED_24_16_SHIFT    (16U)
22825 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22826  */
22827 #define DDRPHY_DX1LCDLR0_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR0_RESERVED_24_16_MASK)
22828 #define DDRPHY_DX1LCDLR0_RESERVED_31_25_MASK     (0xFE000000U)
22829 #define DDRPHY_DX1LCDLR0_RESERVED_31_25_SHIFT    (25U)
22830 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22831  */
22832 #define DDRPHY_DX1LCDLR0_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR0_RESERVED_31_25_MASK)
22833 /*! @} */
22834 
22835 /*! @name DX1LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
22836 /*! @{ */
22837 #define DDRPHY_DX1LCDLR1_WDQD_MASK               (0x1FFU)
22838 #define DDRPHY_DX1LCDLR1_WDQD_SHIFT              (0U)
22839 /*! WDQD - Write Data Delay
22840  */
22841 #define DDRPHY_DX1LCDLR1_WDQD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_WDQD_SHIFT)) & DDRPHY_DX1LCDLR1_WDQD_MASK)
22842 #define DDRPHY_DX1LCDLR1_RESERVED_15_9_MASK      (0xFE00U)
22843 #define DDRPHY_DX1LCDLR1_RESERVED_15_9_SHIFT     (9U)
22844 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22845  */
22846 #define DDRPHY_DX1LCDLR1_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR1_RESERVED_15_9_MASK)
22847 #define DDRPHY_DX1LCDLR1_RESERVED_24_16_MASK     (0x1FF0000U)
22848 #define DDRPHY_DX1LCDLR1_RESERVED_24_16_SHIFT    (16U)
22849 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22850  */
22851 #define DDRPHY_DX1LCDLR1_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR1_RESERVED_24_16_MASK)
22852 #define DDRPHY_DX1LCDLR1_RESERVED_31_25_MASK     (0xFE000000U)
22853 #define DDRPHY_DX1LCDLR1_RESERVED_31_25_SHIFT    (25U)
22854 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22855  */
22856 #define DDRPHY_DX1LCDLR1_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR1_RESERVED_31_25_MASK)
22857 /*! @} */
22858 
22859 /*! @name DX1LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
22860 /*! @{ */
22861 #define DDRPHY_DX1LCDLR2_DQSGD_MASK              (0x1FFU)
22862 #define DDRPHY_DX1LCDLR2_DQSGD_SHIFT             (0U)
22863 /*! DQSGD - Read DQS Gating Delay
22864  */
22865 #define DDRPHY_DX1LCDLR2_DQSGD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX1LCDLR2_DQSGD_MASK)
22866 #define DDRPHY_DX1LCDLR2_RESERVED_15_9_MASK      (0xFE00U)
22867 #define DDRPHY_DX1LCDLR2_RESERVED_15_9_SHIFT     (9U)
22868 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22869  */
22870 #define DDRPHY_DX1LCDLR2_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR2_RESERVED_15_9_MASK)
22871 #define DDRPHY_DX1LCDLR2_RESERVED_24_16_MASK     (0x1FF0000U)
22872 #define DDRPHY_DX1LCDLR2_RESERVED_24_16_SHIFT    (16U)
22873 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22874  */
22875 #define DDRPHY_DX1LCDLR2_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR2_RESERVED_24_16_MASK)
22876 #define DDRPHY_DX1LCDLR2_RESERVED_31_25_MASK     (0xFE000000U)
22877 #define DDRPHY_DX1LCDLR2_RESERVED_31_25_SHIFT    (25U)
22878 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22879  */
22880 #define DDRPHY_DX1LCDLR2_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR2_RESERVED_31_25_MASK)
22881 /*! @} */
22882 
22883 /*! @name DX1LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
22884 /*! @{ */
22885 #define DDRPHY_DX1LCDLR3_RDQSD_MASK              (0x1FFU)
22886 #define DDRPHY_DX1LCDLR3_RDQSD_SHIFT             (0U)
22887 /*! RDQSD - Read DQS Delay
22888  */
22889 #define DDRPHY_DX1LCDLR3_RDQSD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX1LCDLR3_RDQSD_MASK)
22890 #define DDRPHY_DX1LCDLR3_RESERVED_15_9_MASK      (0xFE00U)
22891 #define DDRPHY_DX1LCDLR3_RESERVED_15_9_SHIFT     (9U)
22892 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22893  */
22894 #define DDRPHY_DX1LCDLR3_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR3_RESERVED_15_9_MASK)
22895 #define DDRPHY_DX1LCDLR3_RESERVED_24_16_MASK     (0x1FF0000U)
22896 #define DDRPHY_DX1LCDLR3_RESERVED_24_16_SHIFT    (16U)
22897 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22898  */
22899 #define DDRPHY_DX1LCDLR3_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR3_RESERVED_24_16_MASK)
22900 #define DDRPHY_DX1LCDLR3_RESERVED_31_25_MASK     (0xFE000000U)
22901 #define DDRPHY_DX1LCDLR3_RESERVED_31_25_SHIFT    (25U)
22902 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22903  */
22904 #define DDRPHY_DX1LCDLR3_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR3_RESERVED_31_25_MASK)
22905 /*! @} */
22906 
22907 /*! @name DX1LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
22908 /*! @{ */
22909 #define DDRPHY_DX1LCDLR4_RDQSND_MASK             (0x1FFU)
22910 #define DDRPHY_DX1LCDLR4_RDQSND_SHIFT            (0U)
22911 /*! RDQSND - Read DQSN Delay
22912  */
22913 #define DDRPHY_DX1LCDLR4_RDQSND(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX1LCDLR4_RDQSND_MASK)
22914 #define DDRPHY_DX1LCDLR4_RESERVED_15_9_MASK      (0xFE00U)
22915 #define DDRPHY_DX1LCDLR4_RESERVED_15_9_SHIFT     (9U)
22916 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22917  */
22918 #define DDRPHY_DX1LCDLR4_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR4_RESERVED_15_9_MASK)
22919 #define DDRPHY_DX1LCDLR4_RESERVED_24_16_MASK     (0x1FF0000U)
22920 #define DDRPHY_DX1LCDLR4_RESERVED_24_16_SHIFT    (16U)
22921 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22922  */
22923 #define DDRPHY_DX1LCDLR4_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR4_RESERVED_24_16_MASK)
22924 #define DDRPHY_DX1LCDLR4_RESERVED_31_25_MASK     (0xFE000000U)
22925 #define DDRPHY_DX1LCDLR4_RESERVED_31_25_SHIFT    (25U)
22926 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22927  */
22928 #define DDRPHY_DX1LCDLR4_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR4_RESERVED_31_25_MASK)
22929 /*! @} */
22930 
22931 /*! @name DX1LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
22932 /*! @{ */
22933 #define DDRPHY_DX1LCDLR5_DQSGSD_MASK             (0x1FFU)
22934 #define DDRPHY_DX1LCDLR5_DQSGSD_SHIFT            (0U)
22935 /*! DQSGSD - DQS Gating Status Delay
22936  */
22937 #define DDRPHY_DX1LCDLR5_DQSGSD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX1LCDLR5_DQSGSD_MASK)
22938 #define DDRPHY_DX1LCDLR5_RESERVED_15_9_MASK      (0xFE00U)
22939 #define DDRPHY_DX1LCDLR5_RESERVED_15_9_SHIFT     (9U)
22940 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22941  */
22942 #define DDRPHY_DX1LCDLR5_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR5_RESERVED_15_9_MASK)
22943 #define DDRPHY_DX1LCDLR5_RESERVED_24_16_MASK     (0x1FF0000U)
22944 #define DDRPHY_DX1LCDLR5_RESERVED_24_16_SHIFT    (16U)
22945 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22946  */
22947 #define DDRPHY_DX1LCDLR5_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR5_RESERVED_24_16_MASK)
22948 #define DDRPHY_DX1LCDLR5_RESERVED_31_25_MASK     (0xFE000000U)
22949 #define DDRPHY_DX1LCDLR5_RESERVED_31_25_SHIFT    (25U)
22950 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22951  */
22952 #define DDRPHY_DX1LCDLR5_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR5_RESERVED_31_25_MASK)
22953 /*! @} */
22954 
22955 /*! @name DX1MDLR0 - DATX8 n Master Delay Line Register 0 */
22956 /*! @{ */
22957 #define DDRPHY_DX1MDLR0_IPRD_MASK                (0x1FFU)
22958 #define DDRPHY_DX1MDLR0_IPRD_SHIFT               (0U)
22959 /*! IPRD - Initial Period
22960  */
22961 #define DDRPHY_DX1MDLR0_IPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_IPRD_SHIFT)) & DDRPHY_DX1MDLR0_IPRD_MASK)
22962 #define DDRPHY_DX1MDLR0_RESERVED_15_9_MASK       (0xFE00U)
22963 #define DDRPHY_DX1MDLR0_RESERVED_15_9_SHIFT      (9U)
22964 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22965  */
22966 #define DDRPHY_DX1MDLR0_RESERVED_15_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX1MDLR0_RESERVED_15_9_MASK)
22967 #define DDRPHY_DX1MDLR0_TPRD_MASK                (0x1FF0000U)
22968 #define DDRPHY_DX1MDLR0_TPRD_SHIFT               (16U)
22969 /*! TPRD - Target Period
22970  */
22971 #define DDRPHY_DX1MDLR0_TPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_TPRD_SHIFT)) & DDRPHY_DX1MDLR0_TPRD_MASK)
22972 #define DDRPHY_DX1MDLR0_RESERVED_31_25_MASK      (0xFE000000U)
22973 #define DDRPHY_DX1MDLR0_RESERVED_31_25_SHIFT     (25U)
22974 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22975  */
22976 #define DDRPHY_DX1MDLR0_RESERVED_31_25(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX1MDLR0_RESERVED_31_25_MASK)
22977 /*! @} */
22978 
22979 /*! @name DX1MDLR1 - DATX8 n Master Delay Line Register 1 */
22980 /*! @{ */
22981 #define DDRPHY_DX1MDLR1_MDLD_MASK                (0x1FFU)
22982 #define DDRPHY_DX1MDLR1_MDLD_SHIFT               (0U)
22983 /*! MDLD - MDL Delay
22984  */
22985 #define DDRPHY_DX1MDLR1_MDLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR1_MDLD_SHIFT)) & DDRPHY_DX1MDLR1_MDLD_MASK)
22986 #define DDRPHY_DX1MDLR1_RESERVED_31_9_MASK       (0xFFFFFE00U)
22987 #define DDRPHY_DX1MDLR1_RESERVED_31_9_SHIFT      (9U)
22988 /*! RESERVED_31_9 - Reserved. Return zeroes on reads.
22989  */
22990 #define DDRPHY_DX1MDLR1_RESERVED_31_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX1MDLR1_RESERVED_31_9_MASK)
22991 /*! @} */
22992 
22993 /*! @name DX1GTR0 - DATX8 n General Timing Register 0 */
22994 /*! @{ */
22995 #define DDRPHY_DX1GTR0_DGSL_MASK                 (0x1FU)
22996 #define DDRPHY_DX1GTR0_DGSL_SHIFT                (0U)
22997 /*! DGSL - DQS Gating System Latency
22998  */
22999 #define DDRPHY_DX1GTR0_DGSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_DGSL_SHIFT)) & DDRPHY_DX1GTR0_DGSL_MASK)
23000 #define DDRPHY_DX1GTR0_RESERVED_7_5_MASK         (0xE0U)
23001 #define DDRPHY_DX1GTR0_RESERVED_7_5_SHIFT        (5U)
23002 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
23003  */
23004 #define DDRPHY_DX1GTR0_RESERVED_7_5(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_7_5_MASK)
23005 #define DDRPHY_DX1GTR0_RESERVED_12_8_MASK        (0x1F00U)
23006 #define DDRPHY_DX1GTR0_RESERVED_12_8_SHIFT       (8U)
23007 /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
23008  */
23009 #define DDRPHY_DX1GTR0_RESERVED_12_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_12_8_MASK)
23010 #define DDRPHY_DX1GTR0_RESERVED_15_13_MASK       (0xE000U)
23011 #define DDRPHY_DX1GTR0_RESERVED_15_13_SHIFT      (13U)
23012 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
23013  */
23014 #define DDRPHY_DX1GTR0_RESERVED_15_13(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_15_13_MASK)
23015 #define DDRPHY_DX1GTR0_WLSL_MASK                 (0xF0000U)
23016 #define DDRPHY_DX1GTR0_WLSL_SHIFT                (16U)
23017 /*! WLSL - Write Leveling System Latency
23018  */
23019 #define DDRPHY_DX1GTR0_WLSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_WLSL_SHIFT)) & DDRPHY_DX1GTR0_WLSL_MASK)
23020 #define DDRPHY_DX1GTR0_RESERVED_23_20_MASK       (0xF00000U)
23021 #define DDRPHY_DX1GTR0_RESERVED_23_20_SHIFT      (20U)
23022 /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
23023  */
23024 #define DDRPHY_DX1GTR0_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_23_20_MASK)
23025 #define DDRPHY_DX1GTR0_WDQSL_MASK                (0x7000000U)
23026 #define DDRPHY_DX1GTR0_WDQSL_SHIFT               (24U)
23027 /*! WDQSL - DQ Write Path Latency Pipeline
23028  */
23029 #define DDRPHY_DX1GTR0_WDQSL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_WDQSL_SHIFT)) & DDRPHY_DX1GTR0_WDQSL_MASK)
23030 #define DDRPHY_DX1GTR0_RESERVED_31_24_MASK       (0xF8000000U)
23031 #define DDRPHY_DX1GTR0_RESERVED_31_24_SHIFT      (27U)
23032 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
23033  */
23034 #define DDRPHY_DX1GTR0_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_31_24_MASK)
23035 /*! @} */
23036 
23037 /*! @name DX1RSR0 - DATX8 n Rank Status Register 0 */
23038 /*! @{ */
23039 #define DDRPHY_DX1RSR0_QSGERR_MASK               (0xFFFFU)
23040 #define DDRPHY_DX1RSR0_QSGERR_SHIFT              (0U)
23041 /*! QSGERR - DQS Gate Training Error
23042  */
23043 #define DDRPHY_DX1RSR0_QSGERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR0_QSGERR_SHIFT)) & DDRPHY_DX1RSR0_QSGERR_MASK)
23044 #define DDRPHY_DX1RSR0_RESERVED_31_16_MASK       (0xFFFF0000U)
23045 #define DDRPHY_DX1RSR0_RESERVED_31_16_SHIFT      (16U)
23046 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
23047  */
23048 #define DDRPHY_DX1RSR0_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR0_RESERVED_31_16_MASK)
23049 /*! @} */
23050 
23051 /*! @name DX1RSR1 - DATX8 n Rank Status Register 1 */
23052 /*! @{ */
23053 #define DDRPHY_DX1RSR1_RDLVLERR_MASK             (0xFFFFU)
23054 #define DDRPHY_DX1RSR1_RDLVLERR_SHIFT            (0U)
23055 /*! RDLVLERR - Read Leveling Error
23056  */
23057 #define DDRPHY_DX1RSR1_RDLVLERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX1RSR1_RDLVLERR_MASK)
23058 #define DDRPHY_DX1RSR1_RESERVED_31_16_MASK       (0xFFFF0000U)
23059 #define DDRPHY_DX1RSR1_RESERVED_31_16_SHIFT      (16U)
23060 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
23061  */
23062 #define DDRPHY_DX1RSR1_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR1_RESERVED_31_16_MASK)
23063 /*! @} */
23064 
23065 /*! @name DX1RSR2 - DATX8 n Rank Status Register 2 */
23066 /*! @{ */
23067 #define DDRPHY_DX1RSR2_WLAWN_MASK                (0xFFFFU)
23068 #define DDRPHY_DX1RSR2_WLAWN_SHIFT               (0U)
23069 /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
23070  */
23071 #define DDRPHY_DX1RSR2_WLAWN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR2_WLAWN_SHIFT)) & DDRPHY_DX1RSR2_WLAWN_MASK)
23072 #define DDRPHY_DX1RSR2_RESERVED_31_16_MASK       (0xFFFF0000U)
23073 #define DDRPHY_DX1RSR2_RESERVED_31_16_SHIFT      (16U)
23074 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
23075  */
23076 #define DDRPHY_DX1RSR2_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR2_RESERVED_31_16_MASK)
23077 /*! @} */
23078 
23079 /*! @name DX1RSR3 - DATX8 n Rank Status Register 3 */
23080 /*! @{ */
23081 #define DDRPHY_DX1RSR3_WLAERR_MASK               (0xFFFFU)
23082 #define DDRPHY_DX1RSR3_WLAERR_SHIFT              (0U)
23083 /*! WLAERR - Write Leveling Adjustment Error
23084  */
23085 #define DDRPHY_DX1RSR3_WLAERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR3_WLAERR_SHIFT)) & DDRPHY_DX1RSR3_WLAERR_MASK)
23086 #define DDRPHY_DX1RSR3_RESERVED_31_16_MASK       (0xFFFF0000U)
23087 #define DDRPHY_DX1RSR3_RESERVED_31_16_SHIFT      (16U)
23088 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
23089  */
23090 #define DDRPHY_DX1RSR3_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR3_RESERVED_31_16_MASK)
23091 /*! @} */
23092 
23093 /*! @name DX1GSR0 - DATX8 n General Status Register 0 */
23094 /*! @{ */
23095 #define DDRPHY_DX1GSR0_WDQCAL_MASK               (0x1U)
23096 #define DDRPHY_DX1GSR0_WDQCAL_SHIFT              (0U)
23097 /*! WDQCAL - Write DQ Calibration
23098  */
23099 #define DDRPHY_DX1GSR0_WDQCAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WDQCAL_SHIFT)) & DDRPHY_DX1GSR0_WDQCAL_MASK)
23100 #define DDRPHY_DX1GSR0_RDQSCAL_MASK              (0x2U)
23101 #define DDRPHY_DX1GSR0_RDQSCAL_SHIFT             (1U)
23102 /*! RDQSCAL - Read DQS Calibration
23103  */
23104 #define DDRPHY_DX1GSR0_RDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX1GSR0_RDQSCAL_MASK)
23105 #define DDRPHY_DX1GSR0_RDQSNCAL_MASK             (0x4U)
23106 #define DDRPHY_DX1GSR0_RDQSNCAL_SHIFT            (2U)
23107 /*! RDQSNCAL - Read DQS# Calibration
23108  */
23109 #define DDRPHY_DX1GSR0_RDQSNCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX1GSR0_RDQSNCAL_MASK)
23110 #define DDRPHY_DX1GSR0_GDQSCAL_MASK              (0x8U)
23111 #define DDRPHY_DX1GSR0_GDQSCAL_SHIFT             (3U)
23112 /*! GDQSCAL - Read DQS gating Calibration
23113  */
23114 #define DDRPHY_DX1GSR0_GDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX1GSR0_GDQSCAL_MASK)
23115 #define DDRPHY_DX1GSR0_WLCAL_MASK                (0x10U)
23116 #define DDRPHY_DX1GSR0_WLCAL_SHIFT               (4U)
23117 /*! WLCAL - Write Leveling Calibration
23118  */
23119 #define DDRPHY_DX1GSR0_WLCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLCAL_SHIFT)) & DDRPHY_DX1GSR0_WLCAL_MASK)
23120 #define DDRPHY_DX1GSR0_WLDONE_MASK               (0x20U)
23121 #define DDRPHY_DX1GSR0_WLDONE_SHIFT              (5U)
23122 /*! WLDONE - Write Leveling Done
23123  */
23124 #define DDRPHY_DX1GSR0_WLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLDONE_SHIFT)) & DDRPHY_DX1GSR0_WLDONE_MASK)
23125 #define DDRPHY_DX1GSR0_WLERR_MASK                (0x40U)
23126 #define DDRPHY_DX1GSR0_WLERR_SHIFT               (6U)
23127 /*! WLERR - Write Leveling Error
23128  */
23129 #define DDRPHY_DX1GSR0_WLERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLERR_SHIFT)) & DDRPHY_DX1GSR0_WLERR_MASK)
23130 #define DDRPHY_DX1GSR0_WLPRD_MASK                (0xFF80U)
23131 #define DDRPHY_DX1GSR0_WLPRD_SHIFT               (7U)
23132 /*! WLPRD - Write Leveling Period
23133  */
23134 #define DDRPHY_DX1GSR0_WLPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLPRD_SHIFT)) & DDRPHY_DX1GSR0_WLPRD_MASK)
23135 #define DDRPHY_DX1GSR0_DPLOCK_MASK               (0x10000U)
23136 #define DDRPHY_DX1GSR0_DPLOCK_SHIFT              (16U)
23137 /*! DPLOCK - DATX8 PLL Lock
23138  */
23139 #define DDRPHY_DX1GSR0_DPLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_DPLOCK_SHIFT)) & DDRPHY_DX1GSR0_DPLOCK_MASK)
23140 #define DDRPHY_DX1GSR0_GDQSPRD_MASK              (0x3FE0000U)
23141 #define DDRPHY_DX1GSR0_GDQSPRD_SHIFT             (17U)
23142 /*! GDQSPRD - Read DQS gating Period
23143  */
23144 #define DDRPHY_DX1GSR0_GDQSPRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX1GSR0_GDQSPRD_MASK)
23145 #define DDRPHY_DX1GSR0_RESERVED_29_26_MASK       (0x3C000000U)
23146 #define DDRPHY_DX1GSR0_RESERVED_29_26_SHIFT      (26U)
23147 /*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
23148  */
23149 #define DDRPHY_DX1GSR0_RESERVED_29_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX1GSR0_RESERVED_29_26_MASK)
23150 #define DDRPHY_DX1GSR0_WLDQ_MASK                 (0x40000000U)
23151 #define DDRPHY_DX1GSR0_WLDQ_SHIFT                (30U)
23152 /*! WLDQ - Write Leveling DQ Status
23153  */
23154 #define DDRPHY_DX1GSR0_WLDQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLDQ_SHIFT)) & DDRPHY_DX1GSR0_WLDQ_MASK)
23155 #define DDRPHY_DX1GSR0_RESERVED_31_MASK          (0x80000000U)
23156 #define DDRPHY_DX1GSR0_RESERVED_31_SHIFT         (31U)
23157 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
23158  */
23159 #define DDRPHY_DX1GSR0_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX1GSR0_RESERVED_31_MASK)
23160 /*! @} */
23161 
23162 /*! @name DX1GSR1 - DATX8 n General Status Register 1 */
23163 /*! @{ */
23164 #define DDRPHY_DX1GSR1_DLTDONE_MASK              (0x1U)
23165 #define DDRPHY_DX1GSR1_DLTDONE_SHIFT             (0U)
23166 /*! DLTDONE - Delay Line Test Done
23167  */
23168 #define DDRPHY_DX1GSR1_DLTDONE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR1_DLTDONE_SHIFT)) & DDRPHY_DX1GSR1_DLTDONE_MASK)
23169 #define DDRPHY_DX1GSR1_DLTCODE_MASK              (0x1FFFFFEU)
23170 #define DDRPHY_DX1GSR1_DLTCODE_SHIFT             (1U)
23171 /*! DLTCODE - Delay Line Test Code
23172  */
23173 #define DDRPHY_DX1GSR1_DLTCODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR1_DLTCODE_SHIFT)) & DDRPHY_DX1GSR1_DLTCODE_MASK)
23174 #define DDRPHY_DX1GSR1_RESERVED_31_25_MASK       (0xFE000000U)
23175 #define DDRPHY_DX1GSR1_RESERVED_31_25_SHIFT      (25U)
23176 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
23177  */
23178 #define DDRPHY_DX1GSR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX1GSR1_RESERVED_31_25_MASK)
23179 /*! @} */
23180 
23181 /*! @name DX1GSR2 - DATX8 n General Status Register 2 */
23182 /*! @{ */
23183 #define DDRPHY_DX1GSR2_RDERR_MASK                (0x1U)
23184 #define DDRPHY_DX1GSR2_RDERR_SHIFT               (0U)
23185 /*! RDERR - Read Bit Deskew Error
23186  */
23187 #define DDRPHY_DX1GSR2_RDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_RDERR_SHIFT)) & DDRPHY_DX1GSR2_RDERR_MASK)
23188 #define DDRPHY_DX1GSR2_RDWN_MASK                 (0x2U)
23189 #define DDRPHY_DX1GSR2_RDWN_SHIFT                (1U)
23190 /*! RDWN - Read Bit Deskew Warning
23191  */
23192 #define DDRPHY_DX1GSR2_RDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_RDWN_SHIFT)) & DDRPHY_DX1GSR2_RDWN_MASK)
23193 #define DDRPHY_DX1GSR2_WDERR_MASK                (0x4U)
23194 #define DDRPHY_DX1GSR2_WDERR_SHIFT               (2U)
23195 /*! WDERR - Write Bit Deskew Error
23196  */
23197 #define DDRPHY_DX1GSR2_WDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WDERR_SHIFT)) & DDRPHY_DX1GSR2_WDERR_MASK)
23198 #define DDRPHY_DX1GSR2_WDWN_MASK                 (0x8U)
23199 #define DDRPHY_DX1GSR2_WDWN_SHIFT                (3U)
23200 /*! WDWN - Write Bit Deskew Warning
23201  */
23202 #define DDRPHY_DX1GSR2_WDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WDWN_SHIFT)) & DDRPHY_DX1GSR2_WDWN_MASK)
23203 #define DDRPHY_DX1GSR2_REERR_MASK                (0x10U)
23204 #define DDRPHY_DX1GSR2_REERR_SHIFT               (4U)
23205 /*! REERR - Read Eye Centering Error
23206  */
23207 #define DDRPHY_DX1GSR2_REERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_REERR_SHIFT)) & DDRPHY_DX1GSR2_REERR_MASK)
23208 #define DDRPHY_DX1GSR2_REWN_MASK                 (0x20U)
23209 #define DDRPHY_DX1GSR2_REWN_SHIFT                (5U)
23210 /*! REWN - Read Eye Centering Warning
23211  */
23212 #define DDRPHY_DX1GSR2_REWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_REWN_SHIFT)) & DDRPHY_DX1GSR2_REWN_MASK)
23213 #define DDRPHY_DX1GSR2_WEERR_MASK                (0x40U)
23214 #define DDRPHY_DX1GSR2_WEERR_SHIFT               (6U)
23215 /*! WEERR - Write Eye Centering Error
23216  */
23217 #define DDRPHY_DX1GSR2_WEERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WEERR_SHIFT)) & DDRPHY_DX1GSR2_WEERR_MASK)
23218 #define DDRPHY_DX1GSR2_WEWN_MASK                 (0x80U)
23219 #define DDRPHY_DX1GSR2_WEWN_SHIFT                (7U)
23220 /*! WEWN - Write Eye Centering Warning
23221  */
23222 #define DDRPHY_DX1GSR2_WEWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WEWN_SHIFT)) & DDRPHY_DX1GSR2_WEWN_MASK)
23223 #define DDRPHY_DX1GSR2_ESTAT_MASK                (0xF00U)
23224 #define DDRPHY_DX1GSR2_ESTAT_SHIFT               (8U)
23225 /*! ESTAT - Error Status
23226  */
23227 #define DDRPHY_DX1GSR2_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_ESTAT_SHIFT)) & DDRPHY_DX1GSR2_ESTAT_MASK)
23228 #define DDRPHY_DX1GSR2_DQS2DQERR_MASK            (0xFF000U)
23229 #define DDRPHY_DX1GSR2_DQS2DQERR_SHIFT           (12U)
23230 /*! DQS2DQERR - Write DQS2DQ Training Error
23231  */
23232 #define DDRPHY_DX1GSR2_DQS2DQERR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX1GSR2_DQS2DQERR_MASK)
23233 #define DDRPHY_DX1GSR2_SRDERR_MASK               (0x100000U)
23234 #define DDRPHY_DX1GSR2_SRDERR_SHIFT              (20U)
23235 /*! SRDERR - Static Read Error
23236  */
23237 #define DDRPHY_DX1GSR2_SRDERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_SRDERR_SHIFT)) & DDRPHY_DX1GSR2_SRDERR_MASK)
23238 #define DDRPHY_DX1GSR2_RESERVED_21_MASK          (0x200000U)
23239 #define DDRPHY_DX1GSR2_RESERVED_21_SHIFT         (21U)
23240 /*! RESERVED_21 - Reserved. Return zeroes on reads.
23241  */
23242 #define DDRPHY_DX1GSR2_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX1GSR2_RESERVED_21_MASK)
23243 #define DDRPHY_DX1GSR2_GSDQSCAL_MASK             (0x400000U)
23244 #define DDRPHY_DX1GSR2_GSDQSCAL_SHIFT            (22U)
23245 /*! GSDQSCAL - Read DQS Gating Status Calibration
23246  */
23247 #define DDRPHY_DX1GSR2_GSDQSCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX1GSR2_GSDQSCAL_MASK)
23248 #define DDRPHY_DX1GSR2_GSDQSPRD_MASK             (0xFF800000U)
23249 #define DDRPHY_DX1GSR2_GSDQSPRD_SHIFT            (23U)
23250 /*! GSDQSPRD - Read DQS gating Status Period
23251  */
23252 #define DDRPHY_DX1GSR2_GSDQSPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX1GSR2_GSDQSPRD_MASK)
23253 /*! @} */
23254 
23255 /*! @name DX1GSR3 - DATX8 n General Status Register 3 */
23256 /*! @{ */
23257 #define DDRPHY_DX1GSR3_SRDPC_MASK                (0x3U)
23258 #define DDRPHY_DX1GSR3_SRDPC_SHIFT               (0U)
23259 /*! SRDPC - Static Read Delay Pass Count
23260  */
23261 #define DDRPHY_DX1GSR3_SRDPC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_SRDPC_SHIFT)) & DDRPHY_DX1GSR3_SRDPC_MASK)
23262 #define DDRPHY_DX1GSR3_RESERVED_7_2_MASK         (0xFCU)
23263 #define DDRPHY_DX1GSR3_RESERVED_7_2_SHIFT        (2U)
23264 /*! RESERVED_7_2 - Reserved. Return zeroes on reads.
23265  */
23266 #define DDRPHY_DX1GSR3_RESERVED_7_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX1GSR3_RESERVED_7_2_MASK)
23267 #define DDRPHY_DX1GSR3_HVERR_MASK                (0xF00U)
23268 #define DDRPHY_DX1GSR3_HVERR_SHIFT               (8U)
23269 /*! HVERR - Host VREF Training Error
23270  */
23271 #define DDRPHY_DX1GSR3_HVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_HVERR_SHIFT)) & DDRPHY_DX1GSR3_HVERR_MASK)
23272 #define DDRPHY_DX1GSR3_HVWRN_MASK                (0xF000U)
23273 #define DDRPHY_DX1GSR3_HVWRN_SHIFT               (12U)
23274 /*! HVWRN - Host VREF Training Warning
23275  */
23276 #define DDRPHY_DX1GSR3_HVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_HVWRN_SHIFT)) & DDRPHY_DX1GSR3_HVWRN_MASK)
23277 #define DDRPHY_DX1GSR3_DVERR_MASK                (0xF0000U)
23278 #define DDRPHY_DX1GSR3_DVERR_SHIFT               (16U)
23279 /*! DVERR - DRAM VREF Training Error
23280  */
23281 #define DDRPHY_DX1GSR3_DVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_DVERR_SHIFT)) & DDRPHY_DX1GSR3_DVERR_MASK)
23282 #define DDRPHY_DX1GSR3_DVWRN_MASK                (0xF00000U)
23283 #define DDRPHY_DX1GSR3_DVWRN_SHIFT               (20U)
23284 /*! DVWRN - DRAM VREF Training Warning
23285  */
23286 #define DDRPHY_DX1GSR3_DVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_DVWRN_SHIFT)) & DDRPHY_DX1GSR3_DVWRN_MASK)
23287 #define DDRPHY_DX1GSR3_ESTAT_MASK                (0x7000000U)
23288 #define DDRPHY_DX1GSR3_ESTAT_SHIFT               (24U)
23289 /*! ESTAT - VREF Training Error Status Code
23290  */
23291 #define DDRPHY_DX1GSR3_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_ESTAT_SHIFT)) & DDRPHY_DX1GSR3_ESTAT_MASK)
23292 #define DDRPHY_DX1GSR3_RESERVED_31_27_MASK       (0xF8000000U)
23293 #define DDRPHY_DX1GSR3_RESERVED_31_27_SHIFT      (27U)
23294 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
23295  */
23296 #define DDRPHY_DX1GSR3_RESERVED_31_27(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX1GSR3_RESERVED_31_27_MASK)
23297 /*! @} */
23298 
23299 /*! @name DX1GSR4 - DATX8 n General Status Register 4 */
23300 /*! @{ */
23301 #define DDRPHY_DX1GSR4_RESERVED_0_MASK           (0x1U)
23302 #define DDRPHY_DX1GSR4_RESERVED_0_SHIFT          (0U)
23303 /*! RESERVED_0 - Reserved. Return zeroes on reads.
23304  */
23305 #define DDRPHY_DX1GSR4_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_0_MASK)
23306 #define DDRPHY_DX1GSR4_RESERVED_1_MASK           (0x2U)
23307 #define DDRPHY_DX1GSR4_RESERVED_1_SHIFT          (1U)
23308 /*! RESERVED_1 - Reserved. Return zeroes on reads.
23309  */
23310 #define DDRPHY_DX1GSR4_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_1_MASK)
23311 #define DDRPHY_DX1GSR4_RESERVED_2_MASK           (0x4U)
23312 #define DDRPHY_DX1GSR4_RESERVED_2_SHIFT          (2U)
23313 /*! RESERVED_2 - Reserved. Return zeroes on reads.
23314  */
23315 #define DDRPHY_DX1GSR4_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_2_MASK)
23316 #define DDRPHY_DX1GSR4_RESERVED_3_MASK           (0x8U)
23317 #define DDRPHY_DX1GSR4_RESERVED_3_SHIFT          (3U)
23318 /*! RESERVED_3 - Reserved. Return zeroes on reads.
23319  */
23320 #define DDRPHY_DX1GSR4_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_3_MASK)
23321 #define DDRPHY_DX1GSR4_RESERVED_4_MASK           (0x10U)
23322 #define DDRPHY_DX1GSR4_RESERVED_4_SHIFT          (4U)
23323 /*! RESERVED_4 - Reserved. Return zeroes on reads.
23324  */
23325 #define DDRPHY_DX1GSR4_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_4_MASK)
23326 #define DDRPHY_DX1GSR4_RESERVED_5_MASK           (0x20U)
23327 #define DDRPHY_DX1GSR4_RESERVED_5_SHIFT          (5U)
23328 /*! RESERVED_5 - Reserved. Return zeroes on reads.
23329  */
23330 #define DDRPHY_DX1GSR4_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_5_MASK)
23331 #define DDRPHY_DX1GSR4_RESERVED_6_MASK           (0x40U)
23332 #define DDRPHY_DX1GSR4_RESERVED_6_SHIFT          (6U)
23333 /*! RESERVED_6 - Reserved. Return zeroes on reads.
23334  */
23335 #define DDRPHY_DX1GSR4_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_6_MASK)
23336 #define DDRPHY_DX1GSR4_RESERVED_15_7_MASK        (0xFF80U)
23337 #define DDRPHY_DX1GSR4_RESERVED_15_7_SHIFT       (7U)
23338 /*! RESERVED_15_7 - Reserved. Return zeroes on reads.
23339  */
23340 #define DDRPHY_DX1GSR4_RESERVED_15_7(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_15_7_MASK)
23341 #define DDRPHY_DX1GSR4_RESERVED_16_MASK          (0x10000U)
23342 #define DDRPHY_DX1GSR4_RESERVED_16_SHIFT         (16U)
23343 /*! RESERVED_16 - Reserved. Return zeroes on reads.
23344  */
23345 #define DDRPHY_DX1GSR4_RESERVED_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_16_MASK)
23346 #define DDRPHY_DX1GSR4_RESERVED_25_17_MASK       (0x3FE0000U)
23347 #define DDRPHY_DX1GSR4_RESERVED_25_17_SHIFT      (17U)
23348 /*! RESERVED_25_17 - Reserved. Return zeroes on reads.
23349  */
23350 #define DDRPHY_DX1GSR4_RESERVED_25_17(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_25_17_MASK)
23351 #define DDRPHY_DX1GSR4_RESERVED_31_26_MASK       (0xFC000000U)
23352 #define DDRPHY_DX1GSR4_RESERVED_31_26_SHIFT      (26U)
23353 /*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
23354  */
23355 #define DDRPHY_DX1GSR4_RESERVED_31_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_31_26_MASK)
23356 /*! @} */
23357 
23358 /*! @name DX1GSR5 - DATX8 n General Status Register 5 */
23359 /*! @{ */
23360 #define DDRPHY_DX1GSR5_RESERVED_0_MASK           (0x1U)
23361 #define DDRPHY_DX1GSR5_RESERVED_0_SHIFT          (0U)
23362 /*! RESERVED_0 - Reserved. Return zeroes on reads.
23363  */
23364 #define DDRPHY_DX1GSR5_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_0_MASK)
23365 #define DDRPHY_DX1GSR5_RESERVED_1_MASK           (0x2U)
23366 #define DDRPHY_DX1GSR5_RESERVED_1_SHIFT          (1U)
23367 /*! RESERVED_1 - Reserved. Return zeroes on reads.
23368  */
23369 #define DDRPHY_DX1GSR5_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_1_MASK)
23370 #define DDRPHY_DX1GSR5_RESERVED_2_MASK           (0x4U)
23371 #define DDRPHY_DX1GSR5_RESERVED_2_SHIFT          (2U)
23372 /*! RESERVED_2 - Reserved. Return zeroes on reads.
23373  */
23374 #define DDRPHY_DX1GSR5_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_2_MASK)
23375 #define DDRPHY_DX1GSR5_RESERVED_3_MASK           (0x8U)
23376 #define DDRPHY_DX1GSR5_RESERVED_3_SHIFT          (3U)
23377 /*! RESERVED_3 - Reserved. Return zeroes on reads.
23378  */
23379 #define DDRPHY_DX1GSR5_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_3_MASK)
23380 #define DDRPHY_DX1GSR5_RESERVED_4_MASK           (0x10U)
23381 #define DDRPHY_DX1GSR5_RESERVED_4_SHIFT          (4U)
23382 /*! RESERVED_4 - Reserved. Return zeroes on reads.
23383  */
23384 #define DDRPHY_DX1GSR5_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_4_MASK)
23385 #define DDRPHY_DX1GSR5_RESERVED_5_MASK           (0x20U)
23386 #define DDRPHY_DX1GSR5_RESERVED_5_SHIFT          (5U)
23387 /*! RESERVED_5 - Reserved. Return zeroes on reads.
23388  */
23389 #define DDRPHY_DX1GSR5_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_5_MASK)
23390 #define DDRPHY_DX1GSR5_RESERVED_6_MASK           (0x40U)
23391 #define DDRPHY_DX1GSR5_RESERVED_6_SHIFT          (6U)
23392 /*! RESERVED_6 - Reserved. Return zeroes on reads.
23393  */
23394 #define DDRPHY_DX1GSR5_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_6_MASK)
23395 #define DDRPHY_DX1GSR5_RESERVED_7_MASK           (0x80U)
23396 #define DDRPHY_DX1GSR5_RESERVED_7_SHIFT          (7U)
23397 /*! RESERVED_7 - Reserved. Return zeroes on reads.
23398  */
23399 #define DDRPHY_DX1GSR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_7_MASK)
23400 #define DDRPHY_DX1GSR5_RESERVED_11_8_MASK        (0xF00U)
23401 #define DDRPHY_DX1GSR5_RESERVED_11_8_SHIFT       (8U)
23402 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
23403  */
23404 #define DDRPHY_DX1GSR5_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_11_8_MASK)
23405 #define DDRPHY_DX1GSR5_RESERVED_19_12_MASK       (0xFF000U)
23406 #define DDRPHY_DX1GSR5_RESERVED_19_12_SHIFT      (12U)
23407 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
23408  */
23409 #define DDRPHY_DX1GSR5_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_19_12_MASK)
23410 #define DDRPHY_DX1GSR5_RESERVED_20_MASK          (0x100000U)
23411 #define DDRPHY_DX1GSR5_RESERVED_20_SHIFT         (20U)
23412 /*! RESERVED_20 - Reserved. Return zeroes on reads.
23413  */
23414 #define DDRPHY_DX1GSR5_RESERVED_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_20_MASK)
23415 #define DDRPHY_DX1GSR5_RESERVED_21_MASK          (0x200000U)
23416 #define DDRPHY_DX1GSR5_RESERVED_21_SHIFT         (21U)
23417 /*! RESERVED_21 - Reserved. Return zeroes on reads.
23418  */
23419 #define DDRPHY_DX1GSR5_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_21_MASK)
23420 #define DDRPHY_DX1GSR5_RESERVED_22_MASK          (0x400000U)
23421 #define DDRPHY_DX1GSR5_RESERVED_22_SHIFT         (22U)
23422 /*! RESERVED_22 - Reserved. Return zeroes on reads.
23423  */
23424 #define DDRPHY_DX1GSR5_RESERVED_22(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_22_MASK)
23425 #define DDRPHY_DX1GSR5_RESERVED_31_23_MASK       (0xFF800000U)
23426 #define DDRPHY_DX1GSR5_RESERVED_31_23_SHIFT      (23U)
23427 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
23428  */
23429 #define DDRPHY_DX1GSR5_RESERVED_31_23(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_31_23_MASK)
23430 /*! @} */
23431 
23432 /*! @name DX1GSR6 - DATX8 n General Status Register 6 */
23433 /*! @{ */
23434 #define DDRPHY_DX1GSR6_RESERVED_1_0_MASK         (0x3U)
23435 #define DDRPHY_DX1GSR6_RESERVED_1_0_SHIFT        (0U)
23436 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
23437  */
23438 #define DDRPHY_DX1GSR6_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_1_0_MASK)
23439 #define DDRPHY_DX1GSR6_RESERVED_3_2_MASK         (0xCU)
23440 #define DDRPHY_DX1GSR6_RESERVED_3_2_SHIFT        (2U)
23441 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
23442  */
23443 #define DDRPHY_DX1GSR6_RESERVED_3_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_3_2_MASK)
23444 #define DDRPHY_DX1GSR6_RESERVED_7_4_MASK         (0xF0U)
23445 #define DDRPHY_DX1GSR6_RESERVED_7_4_SHIFT        (4U)
23446 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
23447  */
23448 #define DDRPHY_DX1GSR6_RESERVED_7_4(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_7_4_MASK)
23449 #define DDRPHY_DX1GSR6_RESERVED_11_8_MASK        (0xF00U)
23450 #define DDRPHY_DX1GSR6_RESERVED_11_8_SHIFT       (8U)
23451 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
23452  */
23453 #define DDRPHY_DX1GSR6_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_11_8_MASK)
23454 #define DDRPHY_DX1GSR6_RESERVED_15_12_MASK       (0xF000U)
23455 #define DDRPHY_DX1GSR6_RESERVED_15_12_SHIFT      (12U)
23456 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
23457  */
23458 #define DDRPHY_DX1GSR6_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_15_12_MASK)
23459 #define DDRPHY_DX1GSR6_RESERVED_19_15_MASK       (0xF0000U)
23460 #define DDRPHY_DX1GSR6_RESERVED_19_15_SHIFT      (16U)
23461 /*! RESERVED_19_15 - Reserved. Return zeroes on reads.
23462  */
23463 #define DDRPHY_DX1GSR6_RESERVED_19_15(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_19_15_MASK)
23464 #define DDRPHY_DX1GSR6_RESERVED_23_20_MASK       (0xF00000U)
23465 #define DDRPHY_DX1GSR6_RESERVED_23_20_SHIFT      (20U)
23466 /*! RESERVED_23_20 - Reserved. Return zeroes on reads.
23467  */
23468 #define DDRPHY_DX1GSR6_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_23_20_MASK)
23469 #define DDRPHY_DX1GSR6_RESERVED_31_24_MASK       (0xFF000000U)
23470 #define DDRPHY_DX1GSR6_RESERVED_31_24_SHIFT      (24U)
23471 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
23472  */
23473 #define DDRPHY_DX1GSR6_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_31_24_MASK)
23474 /*! @} */
23475 
23476 /*! @name DX2GCR0 - DATX8 n General Configuration Register 0 */
23477 /*! @{ */
23478 #define DDRPHY_DX2GCR0_RESERVED_1_0_MASK         (0x3U)
23479 #define DDRPHY_DX2GCR0_RESERVED_1_0_SHIFT        (0U)
23480 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
23481  */
23482 #define DDRPHY_DX2GCR0_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX2GCR0_RESERVED_1_0_MASK)
23483 #define DDRPHY_DX2GCR0_DQSGOE_MASK               (0x4U)
23484 #define DDRPHY_DX2GCR0_DQSGOE_SHIFT              (2U)
23485 /*! DQSGOE - DQSG Output Enable
23486  */
23487 #define DDRPHY_DX2GCR0_DQSGOE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSGOE_SHIFT)) & DDRPHY_DX2GCR0_DQSGOE_MASK)
23488 #define DDRPHY_DX2GCR0_DQSGODT_MASK              (0x8U)
23489 #define DDRPHY_DX2GCR0_DQSGODT_SHIFT             (3U)
23490 /*! DQSGODT - DQSG On-Die Termination
23491  */
23492 #define DDRPHY_DX2GCR0_DQSGODT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSGODT_SHIFT)) & DDRPHY_DX2GCR0_DQSGODT_MASK)
23493 #define DDRPHY_DX2GCR0_RESERVED_4_MASK           (0x10U)
23494 #define DDRPHY_DX2GCR0_RESERVED_4_SHIFT          (4U)
23495 /*! RESERVED_4 - Reserved. Return zeroes on reads.
23496  */
23497 #define DDRPHY_DX2GCR0_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX2GCR0_RESERVED_4_MASK)
23498 #define DDRPHY_DX2GCR0_DQSGPDR_MASK              (0x20U)
23499 #define DDRPHY_DX2GCR0_DQSGPDR_SHIFT             (5U)
23500 /*! DQSGPDR - DQSG Power Down Receiver
23501  */
23502 #define DDRPHY_DX2GCR0_DQSGPDR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX2GCR0_DQSGPDR_MASK)
23503 #define DDRPHY_DX2GCR0_DQSRPD_MASK               (0x40U)
23504 #define DDRPHY_DX2GCR0_DQSRPD_SHIFT              (6U)
23505 /*! DQSRPD - DQSR Power Down
23506  */
23507 #define DDRPHY_DX2GCR0_DQSRPD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSRPD_SHIFT)) & DDRPHY_DX2GCR0_DQSRPD_MASK)
23508 #define DDRPHY_DX2GCR0_CPDRSHFT_MASK             (0x180U)
23509 #define DDRPHY_DX2GCR0_CPDRSHFT_SHIFT            (7U)
23510 /*! CPDRSHFT - Configurable PDR Phase Shift
23511  */
23512 #define DDRPHY_DX2GCR0_CPDRSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX2GCR0_CPDRSHFT_MASK)
23513 #define DDRPHY_DX2GCR0_RTTOH_MASK                (0x600U)
23514 #define DDRPHY_DX2GCR0_RTTOH_SHIFT               (9U)
23515 /*! RTTOH - RTT Output Hold
23516  */
23517 #define DDRPHY_DX2GCR0_RTTOH(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RTTOH_SHIFT)) & DDRPHY_DX2GCR0_RTTOH_MASK)
23518 #define DDRPHY_DX2GCR0_RTTOAL_MASK               (0x800U)
23519 #define DDRPHY_DX2GCR0_RTTOAL_SHIFT              (11U)
23520 /*! RTTOAL - RTT On Additive Latency
23521  */
23522 #define DDRPHY_DX2GCR0_RTTOAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RTTOAL_SHIFT)) & DDRPHY_DX2GCR0_RTTOAL_MASK)
23523 #define DDRPHY_DX2GCR0_DQSSEPDR_MASK             (0x1000U)
23524 #define DDRPHY_DX2GCR0_DQSSEPDR_SHIFT            (12U)
23525 /*! DQSSEPDR - DQSSE Power Down Receiver
23526  */
23527 #define DDRPHY_DX2GCR0_DQSSEPDR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX2GCR0_DQSSEPDR_MASK)
23528 #define DDRPHY_DX2GCR0_DQSNSEPDR_MASK            (0x2000U)
23529 #define DDRPHY_DX2GCR0_DQSNSEPDR_SHIFT           (13U)
23530 /*! DQSNSEPDR - DQSNSE Power Down Receiver
23531  */
23532 #define DDRPHY_DX2GCR0_DQSNSEPDR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX2GCR0_DQSNSEPDR_MASK)
23533 #define DDRPHY_DX2GCR0_RESERVED_19_14_MASK       (0xFC000U)
23534 #define DDRPHY_DX2GCR0_RESERVED_19_14_SHIFT      (14U)
23535 /*! RESERVED_19_14 - Reserved. Return zeroes on reads.
23536  */
23537 #define DDRPHY_DX2GCR0_RESERVED_19_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX2GCR0_RESERVED_19_14_MASK)
23538 #define DDRPHY_DX2GCR0_RDDLY_MASK                (0xF00000U)
23539 #define DDRPHY_DX2GCR0_RDDLY_SHIFT               (20U)
23540 /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
23541  */
23542 #define DDRPHY_DX2GCR0_RDDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RDDLY_SHIFT)) & DDRPHY_DX2GCR0_RDDLY_MASK)
23543 #define DDRPHY_DX2GCR0_DQSDCC_MASK               (0xF000000U)
23544 #define DDRPHY_DX2GCR0_DQSDCC_SHIFT              (24U)
23545 /*! DQSDCC - DQS Duty Cycle Correction
23546  */
23547 #define DDRPHY_DX2GCR0_DQSDCC(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSDCC_SHIFT)) & DDRPHY_DX2GCR0_DQSDCC_MASK)
23548 #define DDRPHY_DX2GCR0_CODTSHFT_MASK             (0x30000000U)
23549 #define DDRPHY_DX2GCR0_CODTSHFT_SHIFT            (28U)
23550 /*! CODTSHFT - Configurable ODT(TE) Phase Shift
23551  */
23552 #define DDRPHY_DX2GCR0_CODTSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX2GCR0_CODTSHFT_MASK)
23553 #define DDRPHY_DX2GCR0_MDLEN_MASK                (0x40000000U)
23554 #define DDRPHY_DX2GCR0_MDLEN_SHIFT               (30U)
23555 /*! MDLEN - Master Delay Line Enable
23556  */
23557 #define DDRPHY_DX2GCR0_MDLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_MDLEN_SHIFT)) & DDRPHY_DX2GCR0_MDLEN_MASK)
23558 #define DDRPHY_DX2GCR0_CALBYP_MASK               (0x80000000U)
23559 #define DDRPHY_DX2GCR0_CALBYP_SHIFT              (31U)
23560 /*! CALBYP - Calibration Bypass
23561  */
23562 #define DDRPHY_DX2GCR0_CALBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_CALBYP_SHIFT)) & DDRPHY_DX2GCR0_CALBYP_MASK)
23563 /*! @} */
23564 
23565 /*! @name DX2GCR1 - DATX8 n General Configuration Register 1 */
23566 /*! @{ */
23567 #define DDRPHY_DX2GCR1_DQEN_MASK                 (0xFFU)
23568 #define DDRPHY_DX2GCR1_DQEN_SHIFT                (0U)
23569 /*! DQEN - Enables DQ corresponding to each bit in a byte
23570  */
23571 #define DDRPHY_DX2GCR1_DQEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DQEN_SHIFT)) & DDRPHY_DX2GCR1_DQEN_MASK)
23572 #define DDRPHY_DX2GCR1_DMEN_MASK                 (0x100U)
23573 #define DDRPHY_DX2GCR1_DMEN_SHIFT                (8U)
23574 /*! DMEN - Enables DM pin in a byte lane
23575  */
23576 #define DDRPHY_DX2GCR1_DMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DMEN_SHIFT)) & DDRPHY_DX2GCR1_DMEN_MASK)
23577 #define DDRPHY_DX2GCR1_DSEN_MASK                 (0x200U)
23578 #define DDRPHY_DX2GCR1_DSEN_SHIFT                (9U)
23579 /*! DSEN - Enables Write Data strobe in a byte lane
23580  */
23581 #define DDRPHY_DX2GCR1_DSEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DSEN_SHIFT)) & DDRPHY_DX2GCR1_DSEN_MASK)
23582 #define DDRPHY_DX2GCR1_TEEN_MASK                 (0x400U)
23583 #define DDRPHY_DX2GCR1_TEEN_SHIFT                (10U)
23584 /*! TEEN - Enables ODT/TE in a byte lane
23585  */
23586 #define DDRPHY_DX2GCR1_TEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_TEEN_SHIFT)) & DDRPHY_DX2GCR1_TEEN_MASK)
23587 #define DDRPHY_DX2GCR1_PDREN_MASK                (0x800U)
23588 #define DDRPHY_DX2GCR1_PDREN_SHIFT               (11U)
23589 /*! PDREN - Enables PDR in a byte lane
23590  */
23591 #define DDRPHY_DX2GCR1_PDREN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_PDREN_SHIFT)) & DDRPHY_DX2GCR1_PDREN_MASK)
23592 #define DDRPHY_DX2GCR1_OEEN_MASK                 (0x1000U)
23593 #define DDRPHY_DX2GCR1_OEEN_SHIFT                (12U)
23594 /*! OEEN - Enables Read Data Strobe in a byte lane
23595  */
23596 #define DDRPHY_DX2GCR1_OEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_OEEN_SHIFT)) & DDRPHY_DX2GCR1_OEEN_MASK)
23597 #define DDRPHY_DX2GCR1_QSSEL_MASK                (0x2000U)
23598 #define DDRPHY_DX2GCR1_QSSEL_SHIFT               (13U)
23599 /*! QSSEL - Select the delayed or non-delayed read data strobe
23600  */
23601 #define DDRPHY_DX2GCR1_QSSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_QSSEL_SHIFT)) & DDRPHY_DX2GCR1_QSSEL_MASK)
23602 #define DDRPHY_DX2GCR1_QSNSEL_MASK               (0x4000U)
23603 #define DDRPHY_DX2GCR1_QSNSEL_SHIFT              (14U)
23604 /*! QSNSEL - Select the delayed or non-delayed read data strobe #
23605  */
23606 #define DDRPHY_DX2GCR1_QSNSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_QSNSEL_SHIFT)) & DDRPHY_DX2GCR1_QSNSEL_MASK)
23607 #define DDRPHY_DX2GCR1_RESERVED_15_MASK          (0x8000U)
23608 #define DDRPHY_DX2GCR1_RESERVED_15_SHIFT         (15U)
23609 /*! RESERVED_15 - Reserved. Returns zeroes on reads.
23610  */
23611 #define DDRPHY_DX2GCR1_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX2GCR1_RESERVED_15_MASK)
23612 #define DDRPHY_DX2GCR1_DXPDRMODE_MASK            (0xFFFF0000U)
23613 #define DDRPHY_DX2GCR1_DXPDRMODE_SHIFT           (16U)
23614 /*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
23615  */
23616 #define DDRPHY_DX2GCR1_DXPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX2GCR1_DXPDRMODE_MASK)
23617 /*! @} */
23618 
23619 /*! @name DX2GCR2 - DATX8 n General Configuration Register 2 */
23620 /*! @{ */
23621 #define DDRPHY_DX2GCR2_DXTEMODE_MASK             (0xFFFFU)
23622 #define DDRPHY_DX2GCR2_DXTEMODE_SHIFT            (0U)
23623 /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
23624  */
23625 #define DDRPHY_DX2GCR2_DXTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX2GCR2_DXTEMODE_MASK)
23626 #define DDRPHY_DX2GCR2_DXOEMODE_MASK             (0xFFFF0000U)
23627 #define DDRPHY_DX2GCR2_DXOEMODE_SHIFT            (16U)
23628 /*! DXOEMODE - Enables the OE mode values for DQ[7:0]
23629  */
23630 #define DDRPHY_DX2GCR2_DXOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX2GCR2_DXOEMODE_MASK)
23631 /*! @} */
23632 
23633 /*! @name DX2GCR3 - DATX8 n General Configuration Register 3 */
23634 /*! @{ */
23635 #define DDRPHY_DX2GCR3_WDMBVT_MASK               (0x1U)
23636 #define DDRPHY_DX2GCR3_WDMBVT_SHIFT              (0U)
23637 /*! WDMBVT - Write Data Mask BDL VT Compensation
23638  */
23639 #define DDRPHY_DX2GCR3_WDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDMBVT_SHIFT)) & DDRPHY_DX2GCR3_WDMBVT_MASK)
23640 #define DDRPHY_DX2GCR3_RDMBVT_MASK               (0x2U)
23641 #define DDRPHY_DX2GCR3_RDMBVT_SHIFT              (1U)
23642 /*! RDMBVT - Read Data Mask BDL VT Compensation
23643  */
23644 #define DDRPHY_DX2GCR3_RDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RDMBVT_SHIFT)) & DDRPHY_DX2GCR3_RDMBVT_MASK)
23645 #define DDRPHY_DX2GCR3_DSPDRMODE_MASK            (0xCU)
23646 #define DDRPHY_DX2GCR3_DSPDRMODE_SHIFT           (2U)
23647 /*! DSPDRMODE - Enables the PDR mode values for DQS.
23648  */
23649 #define DDRPHY_DX2GCR3_DSPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX2GCR3_DSPDRMODE_MASK)
23650 #define DDRPHY_DX2GCR3_DSTEMODE_MASK             (0x30U)
23651 #define DDRPHY_DX2GCR3_DSTEMODE_SHIFT            (4U)
23652 /*! DSTEMODE - Enables the TE mode values for DQS.
23653  */
23654 #define DDRPHY_DX2GCR3_DSTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSTEMODE_MASK)
23655 #define DDRPHY_DX2GCR3_DSOEMODE_MASK             (0xC0U)
23656 #define DDRPHY_DX2GCR3_DSOEMODE_SHIFT            (6U)
23657 /*! DSOEMODE - Enables the OE mode values for DQS.
23658  */
23659 #define DDRPHY_DX2GCR3_DSOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSOEMODE_MASK)
23660 #define DDRPHY_DX2GCR3_WDSBVT_MASK               (0x100U)
23661 #define DDRPHY_DX2GCR3_WDSBVT_SHIFT              (8U)
23662 /*! WDSBVT - Write Data Strobe BDL VT Compensation
23663  */
23664 #define DDRPHY_DX2GCR3_WDSBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDSBVT_SHIFT)) & DDRPHY_DX2GCR3_WDSBVT_MASK)
23665 #define DDRPHY_DX2GCR3_RESERVED_9_MASK           (0x200U)
23666 #define DDRPHY_DX2GCR3_RESERVED_9_SHIFT          (9U)
23667 /*! RESERVED_9 - Reserved. Returns zeroes on reads.
23668  */
23669 #define DDRPHY_DX2GCR3_RESERVED_9(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX2GCR3_RESERVED_9_MASK)
23670 #define DDRPHY_DX2GCR3_DMPDRMODE_MASK            (0xC00U)
23671 #define DDRPHY_DX2GCR3_DMPDRMODE_SHIFT           (10U)
23672 /*! DMPDRMODE - Enables the PDR mode values for DM.
23673  */
23674 #define DDRPHY_DX2GCR3_DMPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX2GCR3_DMPDRMODE_MASK)
23675 #define DDRPHY_DX2GCR3_DMTEMODE_MASK             (0x3000U)
23676 #define DDRPHY_DX2GCR3_DMTEMODE_SHIFT            (12U)
23677 /*! DMTEMODE - Enables the TE mode values for DM.
23678  */
23679 #define DDRPHY_DX2GCR3_DMTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX2GCR3_DMTEMODE_MASK)
23680 #define DDRPHY_DX2GCR3_DMOEMODE_MASK             (0xC000U)
23681 #define DDRPHY_DX2GCR3_DMOEMODE_SHIFT            (14U)
23682 /*! DMOEMODE - Enables the OE mode values for DM.
23683  */
23684 #define DDRPHY_DX2GCR3_DMOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX2GCR3_DMOEMODE_MASK)
23685 #define DDRPHY_DX2GCR3_DSNPDRMODE_MASK           (0x30000U)
23686 #define DDRPHY_DX2GCR3_DSNPDRMODE_SHIFT          (16U)
23687 /*! DSNPDRMODE - Enables the PDR mode for DQS
23688  */
23689 #define DDRPHY_DX2GCR3_DSNPDRMODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX2GCR3_DSNPDRMODE_MASK)
23690 #define DDRPHY_DX2GCR3_DSNTEMODE_MASK            (0xC0000U)
23691 #define DDRPHY_DX2GCR3_DSNTEMODE_SHIFT           (18U)
23692 /*! DSNTEMODE - Enables the TE mode for DQS
23693  */
23694 #define DDRPHY_DX2GCR3_DSNTEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSNTEMODE_MASK)
23695 #define DDRPHY_DX2GCR3_DSNOEMODE_MASK            (0x300000U)
23696 #define DDRPHY_DX2GCR3_DSNOEMODE_SHIFT           (20U)
23697 /*! DSNOEMODE - Enables the OE mode for DQs
23698  */
23699 #define DDRPHY_DX2GCR3_DSNOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSNOEMODE_MASK)
23700 #define DDRPHY_DX2GCR3_PDRBVT_MASK               (0x400000U)
23701 #define DDRPHY_DX2GCR3_PDRBVT_SHIFT              (22U)
23702 /*! PDRBVT - Power Down Receiver BDL VT Compensation
23703  */
23704 #define DDRPHY_DX2GCR3_PDRBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_PDRBVT_SHIFT)) & DDRPHY_DX2GCR3_PDRBVT_MASK)
23705 #define DDRPHY_DX2GCR3_RGSLVT_MASK               (0x800000U)
23706 #define DDRPHY_DX2GCR3_RGSLVT_SHIFT              (23U)
23707 /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
23708  */
23709 #define DDRPHY_DX2GCR3_RGSLVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RGSLVT_SHIFT)) & DDRPHY_DX2GCR3_RGSLVT_MASK)
23710 #define DDRPHY_DX2GCR3_WLLVT_MASK                (0x1000000U)
23711 #define DDRPHY_DX2GCR3_WLLVT_SHIFT               (24U)
23712 /*! WLLVT - Write Leveling LCDL Delay VT Compensation
23713  */
23714 #define DDRPHY_DX2GCR3_WLLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WLLVT_SHIFT)) & DDRPHY_DX2GCR3_WLLVT_MASK)
23715 #define DDRPHY_DX2GCR3_WDLVT_MASK                (0x2000000U)
23716 #define DDRPHY_DX2GCR3_WDLVT_SHIFT               (25U)
23717 /*! WDLVT - Write DQ LCDL Delay VT Compensation
23718  */
23719 #define DDRPHY_DX2GCR3_WDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDLVT_SHIFT)) & DDRPHY_DX2GCR3_WDLVT_MASK)
23720 #define DDRPHY_DX2GCR3_RDLVT_MASK                (0x4000000U)
23721 #define DDRPHY_DX2GCR3_RDLVT_SHIFT               (26U)
23722 /*! RDLVT - Read DQS LCDL Delay VT Compensation
23723  */
23724 #define DDRPHY_DX2GCR3_RDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RDLVT_SHIFT)) & DDRPHY_DX2GCR3_RDLVT_MASK)
23725 #define DDRPHY_DX2GCR3_RGLVT_MASK                (0x8000000U)
23726 #define DDRPHY_DX2GCR3_RGLVT_SHIFT               (27U)
23727 /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
23728  */
23729 #define DDRPHY_DX2GCR3_RGLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RGLVT_SHIFT)) & DDRPHY_DX2GCR3_RGLVT_MASK)
23730 #define DDRPHY_DX2GCR3_WDBVT_MASK                (0x10000000U)
23731 #define DDRPHY_DX2GCR3_WDBVT_SHIFT               (28U)
23732 /*! WDBVT - Write Data BDL VT Compensation
23733  */
23734 #define DDRPHY_DX2GCR3_WDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDBVT_SHIFT)) & DDRPHY_DX2GCR3_WDBVT_MASK)
23735 #define DDRPHY_DX2GCR3_RDBVT_MASK                (0x20000000U)
23736 #define DDRPHY_DX2GCR3_RDBVT_SHIFT               (29U)
23737 /*! RDBVT - Read Data BDL VT Compensation
23738  */
23739 #define DDRPHY_DX2GCR3_RDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RDBVT_SHIFT)) & DDRPHY_DX2GCR3_RDBVT_MASK)
23740 #define DDRPHY_DX2GCR3_TEBVT_MASK                (0x40000000U)
23741 #define DDRPHY_DX2GCR3_TEBVT_SHIFT               (30U)
23742 /*! TEBVT - Termination Enable BDL VT Compensation
23743  */
23744 #define DDRPHY_DX2GCR3_TEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_TEBVT_SHIFT)) & DDRPHY_DX2GCR3_TEBVT_MASK)
23745 #define DDRPHY_DX2GCR3_OEBVT_MASK                (0x80000000U)
23746 #define DDRPHY_DX2GCR3_OEBVT_SHIFT               (31U)
23747 /*! OEBVT - Output Enable BDL VT Compensation
23748  */
23749 #define DDRPHY_DX2GCR3_OEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_OEBVT_SHIFT)) & DDRPHY_DX2GCR3_OEBVT_MASK)
23750 /*! @} */
23751 
23752 /*! @name DX2GCR4 - DATX8 n General Configuration Register 4 */
23753 /*! @{ */
23754 #define DDRPHY_DX2GCR4_DXREFIMON_MASK            (0x3U)
23755 #define DDRPHY_DX2GCR4_DXREFIMON_SHIFT           (0U)
23756 /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
23757  */
23758 #define DDRPHY_DX2GCR4_DXREFIMON(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX2GCR4_DXREFIMON_MASK)
23759 #define DDRPHY_DX2GCR4_DXREFIEN_MASK             (0x3CU)
23760 #define DDRPHY_DX2GCR4_DXREFIEN_SHIFT            (2U)
23761 /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
23762  */
23763 #define DDRPHY_DX2GCR4_DXREFIEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFIEN_MASK)
23764 #define DDRPHY_DX2GCR4_RESERVED_7_6_MASK         (0xC0U)
23765 #define DDRPHY_DX2GCR4_RESERVED_7_6_SHIFT        (6U)
23766 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
23767  */
23768 #define DDRPHY_DX2GCR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR4_RESERVED_7_6_MASK)
23769 #define DDRPHY_DX2GCR4_DXREFSSEL_MASK            (0x7F00U)
23770 #define DDRPHY_DX2GCR4_DXREFSSEL_SHIFT           (8U)
23771 /*! DXREFSSEL - Byte Lane Single-End VREF Select
23772  */
23773 #define DDRPHY_DX2GCR4_DXREFSSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX2GCR4_DXREFSSEL_MASK)
23774 #define DDRPHY_DX2GCR4_DXREFSSELRANGE_MASK       (0x8000U)
23775 #define DDRPHY_DX2GCR4_DXREFSSELRANGE_SHIFT      (15U)
23776 /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
23777  */
23778 #define DDRPHY_DX2GCR4_DXREFSSELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX2GCR4_DXREFSSELRANGE_MASK)
23779 #define DDRPHY_DX2GCR4_DXREFESEL_MASK            (0x7F0000U)
23780 #define DDRPHY_DX2GCR4_DXREFESEL_SHIFT           (16U)
23781 /*! DXREFESEL - Byte Lane External VREF Select
23782  */
23783 #define DDRPHY_DX2GCR4_DXREFESEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX2GCR4_DXREFESEL_MASK)
23784 #define DDRPHY_DX2GCR4_DXREFESELRANGE_MASK       (0x800000U)
23785 #define DDRPHY_DX2GCR4_DXREFESELRANGE_SHIFT      (23U)
23786 /*! DXREFESELRANGE - External VREF generator REFSEL range select
23787  */
23788 #define DDRPHY_DX2GCR4_DXREFESELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX2GCR4_DXREFESELRANGE_MASK)
23789 #define DDRPHY_DX2GCR4_RESERVED_24_MASK          (0x1000000U)
23790 #define DDRPHY_DX2GCR4_RESERVED_24_SHIFT         (24U)
23791 /*! RESERVED_24 - Reserved. Returns zeros on reads.
23792  */
23793 #define DDRPHY_DX2GCR4_RESERVED_24(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX2GCR4_RESERVED_24_MASK)
23794 #define DDRPHY_DX2GCR4_DXREFSEN_MASK             (0x2000000U)
23795 #define DDRPHY_DX2GCR4_DXREFSEN_SHIFT            (25U)
23796 /*! DXREFSEN - Byte Lane Single-End VREF Enable
23797  */
23798 #define DDRPHY_DX2GCR4_DXREFSEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFSEN_MASK)
23799 #define DDRPHY_DX2GCR4_DXREFEEN_MASK             (0xC000000U)
23800 #define DDRPHY_DX2GCR4_DXREFEEN_SHIFT            (26U)
23801 /*! DXREFEEN - Byte Lane Internal VREF Enable
23802  */
23803 #define DDRPHY_DX2GCR4_DXREFEEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFEEN_MASK)
23804 #define DDRPHY_DX2GCR4_DXREFPEN_MASK             (0x10000000U)
23805 #define DDRPHY_DX2GCR4_DXREFPEN_SHIFT            (28U)
23806 /*! DXREFPEN - Byte Lane VREF Pad Enable
23807  */
23808 #define DDRPHY_DX2GCR4_DXREFPEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFPEN_MASK)
23809 #define DDRPHY_DX2GCR4_RESERVED_31_29_MASK       (0xE0000000U)
23810 #define DDRPHY_DX2GCR4_RESERVED_31_29_SHIFT      (29U)
23811 /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
23812  */
23813 #define DDRPHY_DX2GCR4_RESERVED_31_29(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX2GCR4_RESERVED_31_29_MASK)
23814 /*! @} */
23815 
23816 /*! @name DX2GCR5 - DATX8 n General Configuration Register 5 */
23817 /*! @{ */
23818 #define DDRPHY_DX2GCR5_DXREFISELR0_MASK          (0x7FU)
23819 #define DDRPHY_DX2GCR5_DXREFISELR0_SHIFT         (0U)
23820 /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
23821  */
23822 #define DDRPHY_DX2GCR5_DXREFISELR0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR0_MASK)
23823 #define DDRPHY_DX2GCR5_RESERVED_7_MASK           (0x80U)
23824 #define DDRPHY_DX2GCR5_RESERVED_7_SHIFT          (7U)
23825 /*! RESERVED_7 - Reserved. Returns zeros on reads.
23826  */
23827 #define DDRPHY_DX2GCR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_7_MASK)
23828 #define DDRPHY_DX2GCR5_DXREFISELR1_MASK          (0x7F00U)
23829 #define DDRPHY_DX2GCR5_DXREFISELR1_SHIFT         (8U)
23830 /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
23831  */
23832 #define DDRPHY_DX2GCR5_DXREFISELR1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR1_MASK)
23833 #define DDRPHY_DX2GCR5_RESERVED_15_MASK          (0x8000U)
23834 #define DDRPHY_DX2GCR5_RESERVED_15_SHIFT         (15U)
23835 /*! RESERVED_15 - Reserved. Returns zeros on reads.
23836  */
23837 #define DDRPHY_DX2GCR5_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_15_MASK)
23838 #define DDRPHY_DX2GCR5_DXREFISELR2_MASK          (0x7F0000U)
23839 #define DDRPHY_DX2GCR5_DXREFISELR2_SHIFT         (16U)
23840 /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
23841  */
23842 #define DDRPHY_DX2GCR5_DXREFISELR2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR2_MASK)
23843 #define DDRPHY_DX2GCR5_RESERVED_23_MASK          (0x800000U)
23844 #define DDRPHY_DX2GCR5_RESERVED_23_SHIFT         (23U)
23845 /*! RESERVED_23 - Reserved. Returns zeros on reads.
23846  */
23847 #define DDRPHY_DX2GCR5_RESERVED_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_23_MASK)
23848 #define DDRPHY_DX2GCR5_DXREFISELR3_MASK          (0x7F000000U)
23849 #define DDRPHY_DX2GCR5_DXREFISELR3_SHIFT         (24U)
23850 /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
23851  */
23852 #define DDRPHY_DX2GCR5_DXREFISELR3(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR3_MASK)
23853 #define DDRPHY_DX2GCR5_RESERVED_31_MASK          (0x80000000U)
23854 #define DDRPHY_DX2GCR5_RESERVED_31_SHIFT         (31U)
23855 /*! RESERVED_31 - Reserved. Returns zeros on reads.
23856  */
23857 #define DDRPHY_DX2GCR5_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_31_MASK)
23858 /*! @} */
23859 
23860 /*! @name DX2GCR6 - DATX8 n General Configuration Register 6 */
23861 /*! @{ */
23862 #define DDRPHY_DX2GCR6_DXDQVREFR0_MASK           (0x3FU)
23863 #define DDRPHY_DX2GCR6_DXDQVREFR0_SHIFT          (0U)
23864 /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
23865  */
23866 #define DDRPHY_DX2GCR6_DXDQVREFR0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR0_MASK)
23867 #define DDRPHY_DX2GCR6_RESERVED_7_6_MASK         (0xC0U)
23868 #define DDRPHY_DX2GCR6_RESERVED_7_6_SHIFT        (6U)
23869 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
23870  */
23871 #define DDRPHY_DX2GCR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_7_6_MASK)
23872 #define DDRPHY_DX2GCR6_DXDQVREFR1_MASK           (0x3F00U)
23873 #define DDRPHY_DX2GCR6_DXDQVREFR1_SHIFT          (8U)
23874 /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
23875  */
23876 #define DDRPHY_DX2GCR6_DXDQVREFR1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR1_MASK)
23877 #define DDRPHY_DX2GCR6_RESERVED_15_14_MASK       (0xC000U)
23878 #define DDRPHY_DX2GCR6_RESERVED_15_14_SHIFT      (14U)
23879 /*! RESERVED_15_14 - Reserved. Returns zeros on reads.
23880  */
23881 #define DDRPHY_DX2GCR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_15_14_MASK)
23882 #define DDRPHY_DX2GCR6_DXDQVREFR2_MASK           (0x3F0000U)
23883 #define DDRPHY_DX2GCR6_DXDQVREFR2_SHIFT          (16U)
23884 /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
23885  */
23886 #define DDRPHY_DX2GCR6_DXDQVREFR2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR2_MASK)
23887 #define DDRPHY_DX2GCR6_RESERVED_23_22_MASK       (0xC00000U)
23888 #define DDRPHY_DX2GCR6_RESERVED_23_22_SHIFT      (22U)
23889 /*! RESERVED_23_22 - Reserved. Returns zeros on reads.
23890  */
23891 #define DDRPHY_DX2GCR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_23_22_MASK)
23892 #define DDRPHY_DX2GCR6_DXDQVREFR3_MASK           (0x3F000000U)
23893 #define DDRPHY_DX2GCR6_DXDQVREFR3_SHIFT          (24U)
23894 /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
23895  */
23896 #define DDRPHY_DX2GCR6_DXDQVREFR3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR3_MASK)
23897 #define DDRPHY_DX2GCR6_RESERVED_31_30_MASK       (0xC0000000U)
23898 #define DDRPHY_DX2GCR6_RESERVED_31_30_SHIFT      (30U)
23899 /*! RESERVED_31_30 - Reserved. Returns zeros on reads.
23900  */
23901 #define DDRPHY_DX2GCR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_31_30_MASK)
23902 /*! @} */
23903 
23904 /*! @name DX2GCR7 - DATX8 n General Configuration Register 7 */
23905 /*! @{ */
23906 #define DDRPHY_DX2GCR7_DCALSVAL_MASK             (0x1FFU)
23907 #define DDRPHY_DX2GCR7_DCALSVAL_SHIFT            (0U)
23908 /*! DCALSVAL - DDL Calibration Starting Value
23909  */
23910 #define DDRPHY_DX2GCR7_DCALSVAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX2GCR7_DCALSVAL_MASK)
23911 #define DDRPHY_DX2GCR7_DCALTYPE_MASK             (0x200U)
23912 #define DDRPHY_DX2GCR7_DCALTYPE_SHIFT            (9U)
23913 /*! DCALTYPE - DDL Calibration Type
23914  */
23915 #define DDRPHY_DX2GCR7_DCALTYPE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX2GCR7_DCALTYPE_MASK)
23916 #define DDRPHY_DX2GCR7_RESERVED_17_10_MASK       (0x3FC00U)
23917 #define DDRPHY_DX2GCR7_RESERVED_17_10_SHIFT      (10U)
23918 /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
23919  */
23920 #define DDRPHY_DX2GCR7_RESERVED_17_10(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX2GCR7_RESERVED_17_10_MASK)
23921 #define DDRPHY_DX2GCR7_RESERVED_18_MASK          (0x40000U)
23922 #define DDRPHY_DX2GCR7_RESERVED_18_SHIFT         (18U)
23923 /*! RESERVED_18 - Reserved. Caution, do not write to this register field.
23924  */
23925 #define DDRPHY_DX2GCR7_RESERVED_18(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX2GCR7_RESERVED_18_MASK)
23926 #define DDRPHY_DX2GCR7_RESERVED_31_19_MASK       (0xFFF80000U)
23927 #define DDRPHY_DX2GCR7_RESERVED_31_19_SHIFT      (19U)
23928 /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
23929  */
23930 #define DDRPHY_DX2GCR7_RESERVED_31_19(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX2GCR7_RESERVED_31_19_MASK)
23931 /*! @} */
23932 
23933 /*! @name DX2GCR8 - DATX8 n General Configuration Register 8 */
23934 /*! @{ */
23935 #define DDRPHY_DX2GCR8_RESERVED_5_0_MASK         (0x3FU)
23936 #define DDRPHY_DX2GCR8_RESERVED_5_0_SHIFT        (0U)
23937 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
23938  */
23939 #define DDRPHY_DX2GCR8_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_5_0_MASK)
23940 #define DDRPHY_DX2GCR8_RESERVED_7_6_MASK         (0xC0U)
23941 #define DDRPHY_DX2GCR8_RESERVED_7_6_SHIFT        (6U)
23942 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
23943  */
23944 #define DDRPHY_DX2GCR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_7_6_MASK)
23945 #define DDRPHY_DX2GCR8_RESERVED_13_8_MASK        (0x3F00U)
23946 #define DDRPHY_DX2GCR8_RESERVED_13_8_SHIFT       (8U)
23947 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
23948  */
23949 #define DDRPHY_DX2GCR8_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_13_8_MASK)
23950 #define DDRPHY_DX2GCR8_RESERVED_15_14_MASK       (0xC000U)
23951 #define DDRPHY_DX2GCR8_RESERVED_15_14_SHIFT      (14U)
23952 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
23953  */
23954 #define DDRPHY_DX2GCR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_15_14_MASK)
23955 #define DDRPHY_DX2GCR8_RESERVED_21_16_MASK       (0x3F0000U)
23956 #define DDRPHY_DX2GCR8_RESERVED_21_16_SHIFT      (16U)
23957 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
23958  */
23959 #define DDRPHY_DX2GCR8_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_21_16_MASK)
23960 #define DDRPHY_DX2GCR8_RESERVED_23_22_MASK       (0xC00000U)
23961 #define DDRPHY_DX2GCR8_RESERVED_23_22_SHIFT      (22U)
23962 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
23963  */
23964 #define DDRPHY_DX2GCR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_23_22_MASK)
23965 #define DDRPHY_DX2GCR8_RESERVED_29_24_MASK       (0x3F000000U)
23966 #define DDRPHY_DX2GCR8_RESERVED_29_24_SHIFT      (24U)
23967 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
23968  */
23969 #define DDRPHY_DX2GCR8_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_29_24_MASK)
23970 #define DDRPHY_DX2GCR8_RESERVED_31_30_MASK       (0xC0000000U)
23971 #define DDRPHY_DX2GCR8_RESERVED_31_30_SHIFT      (30U)
23972 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
23973  */
23974 #define DDRPHY_DX2GCR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_31_30_MASK)
23975 /*! @} */
23976 
23977 /*! @name DX2GCR9 - DATX8 n General Configuration Register 9 */
23978 /*! @{ */
23979 #define DDRPHY_DX2GCR9_RESERVED_5_0_MASK         (0x3FU)
23980 #define DDRPHY_DX2GCR9_RESERVED_5_0_SHIFT        (0U)
23981 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
23982  */
23983 #define DDRPHY_DX2GCR9_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_5_0_MASK)
23984 #define DDRPHY_DX2GCR9_RESERVED_7_6_MASK         (0xC0U)
23985 #define DDRPHY_DX2GCR9_RESERVED_7_6_SHIFT        (6U)
23986 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
23987  */
23988 #define DDRPHY_DX2GCR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_7_6_MASK)
23989 #define DDRPHY_DX2GCR9_RESERVED_13_8_MASK        (0x3F00U)
23990 #define DDRPHY_DX2GCR9_RESERVED_13_8_SHIFT       (8U)
23991 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
23992  */
23993 #define DDRPHY_DX2GCR9_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_13_8_MASK)
23994 #define DDRPHY_DX2GCR9_RESERVED_15_14_MASK       (0xC000U)
23995 #define DDRPHY_DX2GCR9_RESERVED_15_14_SHIFT      (14U)
23996 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
23997  */
23998 #define DDRPHY_DX2GCR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_15_14_MASK)
23999 #define DDRPHY_DX2GCR9_RESERVED_21_16_MASK       (0x3F0000U)
24000 #define DDRPHY_DX2GCR9_RESERVED_21_16_SHIFT      (16U)
24001 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
24002  */
24003 #define DDRPHY_DX2GCR9_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_21_16_MASK)
24004 #define DDRPHY_DX2GCR9_RESERVED_23_22_MASK       (0xC00000U)
24005 #define DDRPHY_DX2GCR9_RESERVED_23_22_SHIFT      (22U)
24006 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24007  */
24008 #define DDRPHY_DX2GCR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_23_22_MASK)
24009 #define DDRPHY_DX2GCR9_RESERVED_29_24_MASK       (0x3F000000U)
24010 #define DDRPHY_DX2GCR9_RESERVED_29_24_SHIFT      (24U)
24011 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
24012  */
24013 #define DDRPHY_DX2GCR9_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_29_24_MASK)
24014 #define DDRPHY_DX2GCR9_RESERVED_31_30_MASK       (0xC0000000U)
24015 #define DDRPHY_DX2GCR9_RESERVED_31_30_SHIFT      (30U)
24016 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24017  */
24018 #define DDRPHY_DX2GCR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_31_30_MASK)
24019 /*! @} */
24020 
24021 /*! @name DX2DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
24022 /*! @{ */
24023 #define DDRPHY_DX2DQMAP0_DQ0MAP_MASK             (0xFU)
24024 #define DDRPHY_DX2DQMAP0_DQ0MAP_SHIFT            (0U)
24025 /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
24026  */
24027 #define DDRPHY_DX2DQMAP0_DQ0MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ0MAP_MASK)
24028 #define DDRPHY_DX2DQMAP0_DQ1MAP_MASK             (0xF0U)
24029 #define DDRPHY_DX2DQMAP0_DQ1MAP_SHIFT            (4U)
24030 /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
24031  */
24032 #define DDRPHY_DX2DQMAP0_DQ1MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ1MAP_MASK)
24033 #define DDRPHY_DX2DQMAP0_DQ2MAP_MASK             (0xF00U)
24034 #define DDRPHY_DX2DQMAP0_DQ2MAP_SHIFT            (8U)
24035 /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
24036  */
24037 #define DDRPHY_DX2DQMAP0_DQ2MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ2MAP_MASK)
24038 #define DDRPHY_DX2DQMAP0_DQ3MAP_MASK             (0xF000U)
24039 #define DDRPHY_DX2DQMAP0_DQ3MAP_SHIFT            (12U)
24040 /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
24041  */
24042 #define DDRPHY_DX2DQMAP0_DQ3MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ3MAP_MASK)
24043 #define DDRPHY_DX2DQMAP0_DQ4MAP_MASK             (0xF0000U)
24044 #define DDRPHY_DX2DQMAP0_DQ4MAP_SHIFT            (16U)
24045 /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
24046  */
24047 #define DDRPHY_DX2DQMAP0_DQ4MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ4MAP_MASK)
24048 #define DDRPHY_DX2DQMAP0_RESERVED_30_20_MASK     (0x7FF00000U)
24049 #define DDRPHY_DX2DQMAP0_RESERVED_30_20_SHIFT    (20U)
24050 /*! RESERVED_30_20 - Reserved. Return zeroes on reads.
24051  */
24052 #define DDRPHY_DX2DQMAP0_RESERVED_30_20(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX2DQMAP0_RESERVED_30_20_MASK)
24053 #define DDRPHY_DX2DQMAP0_MAPOK_MASK              (0x80000000U)
24054 #define DDRPHY_DX2DQMAP0_MAPOK_SHIFT             (31U)
24055 /*! MAPOK - Checksum bit
24056  */
24057 #define DDRPHY_DX2DQMAP0_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX2DQMAP0_MAPOK_MASK)
24058 /*! @} */
24059 
24060 /*! @name DX2DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
24061 /*! @{ */
24062 #define DDRPHY_DX2DQMAP1_DQ5MAP_MASK             (0xFU)
24063 #define DDRPHY_DX2DQMAP1_DQ5MAP_SHIFT            (0U)
24064 /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
24065  */
24066 #define DDRPHY_DX2DQMAP1_DQ5MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX2DQMAP1_DQ5MAP_MASK)
24067 #define DDRPHY_DX2DQMAP1_DQ6MAP_MASK             (0xF0U)
24068 #define DDRPHY_DX2DQMAP1_DQ6MAP_SHIFT            (4U)
24069 /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
24070  */
24071 #define DDRPHY_DX2DQMAP1_DQ6MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX2DQMAP1_DQ6MAP_MASK)
24072 #define DDRPHY_DX2DQMAP1_DQ7MAP_MASK             (0xF00U)
24073 #define DDRPHY_DX2DQMAP1_DQ7MAP_SHIFT            (8U)
24074 /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
24075  */
24076 #define DDRPHY_DX2DQMAP1_DQ7MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX2DQMAP1_DQ7MAP_MASK)
24077 #define DDRPHY_DX2DQMAP1_DMMAP_MASK              (0xF000U)
24078 #define DDRPHY_DX2DQMAP1_DMMAP_SHIFT             (12U)
24079 /*! DMMAP - DM bit DATX8 slice mapping index
24080  */
24081 #define DDRPHY_DX2DQMAP1_DMMAP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX2DQMAP1_DMMAP_MASK)
24082 #define DDRPHY_DX2DQMAP1_RESERVED_30_16_MASK     (0x7FFF0000U)
24083 #define DDRPHY_DX2DQMAP1_RESERVED_30_16_SHIFT    (16U)
24084 /*! RESERVED_30_16 - Reserved. Return zeroes on reads.
24085  */
24086 #define DDRPHY_DX2DQMAP1_RESERVED_30_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX2DQMAP1_RESERVED_30_16_MASK)
24087 #define DDRPHY_DX2DQMAP1_MAPOK_MASK              (0x80000000U)
24088 #define DDRPHY_DX2DQMAP1_MAPOK_SHIFT             (31U)
24089 /*! MAPOK - Checksum bit
24090  */
24091 #define DDRPHY_DX2DQMAP1_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX2DQMAP1_MAPOK_MASK)
24092 /*! @} */
24093 
24094 /*! @name DX2BDLR0 - DATX8 n Bit Delay Line Register 0 */
24095 /*! @{ */
24096 #define DDRPHY_DX2BDLR0_DQ0WBD_MASK              (0x3FU)
24097 #define DDRPHY_DX2BDLR0_DQ0WBD_SHIFT             (0U)
24098 /*! DQ0WBD - DQ0 Write Bit Delay
24099  */
24100 #define DDRPHY_DX2BDLR0_DQ0WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ0WBD_MASK)
24101 #define DDRPHY_DX2BDLR0_RESERVED_7_6_MASK        (0xC0U)
24102 #define DDRPHY_DX2BDLR0_RESERVED_7_6_SHIFT       (6U)
24103 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24104  */
24105 #define DDRPHY_DX2BDLR0_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_7_6_MASK)
24106 #define DDRPHY_DX2BDLR0_DQ1WBD_MASK              (0x3F00U)
24107 #define DDRPHY_DX2BDLR0_DQ1WBD_SHIFT             (8U)
24108 /*! DQ1WBD - DQ1 Write Bit Delay
24109  */
24110 #define DDRPHY_DX2BDLR0_DQ1WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ1WBD_MASK)
24111 #define DDRPHY_DX2BDLR0_RESERVED_15_14_MASK      (0xC000U)
24112 #define DDRPHY_DX2BDLR0_RESERVED_15_14_SHIFT     (14U)
24113 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24114  */
24115 #define DDRPHY_DX2BDLR0_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_15_14_MASK)
24116 #define DDRPHY_DX2BDLR0_DQ2WBD_MASK              (0x3F0000U)
24117 #define DDRPHY_DX2BDLR0_DQ2WBD_SHIFT             (16U)
24118 /*! DQ2WBD - DQ2 Write Bit Delay
24119  */
24120 #define DDRPHY_DX2BDLR0_DQ2WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ2WBD_MASK)
24121 #define DDRPHY_DX2BDLR0_RESERVED_23_22_MASK      (0xC00000U)
24122 #define DDRPHY_DX2BDLR0_RESERVED_23_22_SHIFT     (22U)
24123 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24124  */
24125 #define DDRPHY_DX2BDLR0_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_23_22_MASK)
24126 #define DDRPHY_DX2BDLR0_DQ3WBD_MASK              (0x3F000000U)
24127 #define DDRPHY_DX2BDLR0_DQ3WBD_SHIFT             (24U)
24128 /*! DQ3WBD - DQ3 Write Bit Delay
24129  */
24130 #define DDRPHY_DX2BDLR0_DQ3WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ3WBD_MASK)
24131 #define DDRPHY_DX2BDLR0_RESERVED_31_30_MASK      (0xC0000000U)
24132 #define DDRPHY_DX2BDLR0_RESERVED_31_30_SHIFT     (30U)
24133 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24134  */
24135 #define DDRPHY_DX2BDLR0_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_31_30_MASK)
24136 /*! @} */
24137 
24138 /*! @name DX2BDLR1 - DATX8 n Bit Delay Line Register 1 */
24139 /*! @{ */
24140 #define DDRPHY_DX2BDLR1_DQ4WBD_MASK              (0x3FU)
24141 #define DDRPHY_DX2BDLR1_DQ4WBD_SHIFT             (0U)
24142 /*! DQ4WBD - DQ4 Write Bit Delay
24143  */
24144 #define DDRPHY_DX2BDLR1_DQ4WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ4WBD_MASK)
24145 #define DDRPHY_DX2BDLR1_RESERVED_7_6_MASK        (0xC0U)
24146 #define DDRPHY_DX2BDLR1_RESERVED_7_6_SHIFT       (6U)
24147 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24148  */
24149 #define DDRPHY_DX2BDLR1_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_7_6_MASK)
24150 #define DDRPHY_DX2BDLR1_DQ5WBD_MASK              (0x3F00U)
24151 #define DDRPHY_DX2BDLR1_DQ5WBD_SHIFT             (8U)
24152 /*! DQ5WBD - DQ5 Write Bit Delay
24153  */
24154 #define DDRPHY_DX2BDLR1_DQ5WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ5WBD_MASK)
24155 #define DDRPHY_DX2BDLR1_RESERVED_15_14_MASK      (0xC000U)
24156 #define DDRPHY_DX2BDLR1_RESERVED_15_14_SHIFT     (14U)
24157 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24158  */
24159 #define DDRPHY_DX2BDLR1_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_15_14_MASK)
24160 #define DDRPHY_DX2BDLR1_DQ6WBD_MASK              (0x3F0000U)
24161 #define DDRPHY_DX2BDLR1_DQ6WBD_SHIFT             (16U)
24162 /*! DQ6WBD - DQ6 Write Bit Delay
24163  */
24164 #define DDRPHY_DX2BDLR1_DQ6WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ6WBD_MASK)
24165 #define DDRPHY_DX2BDLR1_RESERVED_23_22_MASK      (0xC00000U)
24166 #define DDRPHY_DX2BDLR1_RESERVED_23_22_SHIFT     (22U)
24167 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24168  */
24169 #define DDRPHY_DX2BDLR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_23_22_MASK)
24170 #define DDRPHY_DX2BDLR1_DQ7WBD_MASK              (0x3F000000U)
24171 #define DDRPHY_DX2BDLR1_DQ7WBD_SHIFT             (24U)
24172 /*! DQ7WBD - DQ7 Write Bit Delay
24173  */
24174 #define DDRPHY_DX2BDLR1_DQ7WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ7WBD_MASK)
24175 #define DDRPHY_DX2BDLR1_RESERVED_31_30_MASK      (0xC0000000U)
24176 #define DDRPHY_DX2BDLR1_RESERVED_31_30_SHIFT     (30U)
24177 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24178  */
24179 #define DDRPHY_DX2BDLR1_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_31_30_MASK)
24180 /*! @} */
24181 
24182 /*! @name DX2BDLR2 - DATX8 n Bit Delay Line Register 2 */
24183 /*! @{ */
24184 #define DDRPHY_DX2BDLR2_DMWBD_MASK               (0x3FU)
24185 #define DDRPHY_DX2BDLR2_DMWBD_SHIFT              (0U)
24186 /*! DMWBD - DM Write Bit Delay
24187  */
24188 #define DDRPHY_DX2BDLR2_DMWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DMWBD_SHIFT)) & DDRPHY_DX2BDLR2_DMWBD_MASK)
24189 #define DDRPHY_DX2BDLR2_RESERVED_7_6_MASK        (0xC0U)
24190 #define DDRPHY_DX2BDLR2_RESERVED_7_6_SHIFT       (6U)
24191 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24192  */
24193 #define DDRPHY_DX2BDLR2_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_7_6_MASK)
24194 #define DDRPHY_DX2BDLR2_DSWBD_MASK               (0x3F00U)
24195 #define DDRPHY_DX2BDLR2_DSWBD_SHIFT              (8U)
24196 /*! DSWBD - DQS Write Bit Delay
24197  */
24198 #define DDRPHY_DX2BDLR2_DSWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DSWBD_SHIFT)) & DDRPHY_DX2BDLR2_DSWBD_MASK)
24199 #define DDRPHY_DX2BDLR2_RESERVED_15_14_MASK      (0xC000U)
24200 #define DDRPHY_DX2BDLR2_RESERVED_15_14_SHIFT     (14U)
24201 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24202  */
24203 #define DDRPHY_DX2BDLR2_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_15_14_MASK)
24204 #define DDRPHY_DX2BDLR2_DSOEBD_MASK              (0x3F0000U)
24205 #define DDRPHY_DX2BDLR2_DSOEBD_SHIFT             (16U)
24206 /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
24207  */
24208 #define DDRPHY_DX2BDLR2_DSOEBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX2BDLR2_DSOEBD_MASK)
24209 #define DDRPHY_DX2BDLR2_RESERVED_23_22_MASK      (0xC00000U)
24210 #define DDRPHY_DX2BDLR2_RESERVED_23_22_SHIFT     (22U)
24211 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24212  */
24213 #define DDRPHY_DX2BDLR2_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_23_22_MASK)
24214 #define DDRPHY_DX2BDLR2_DSNWBD_MASK              (0x3F000000U)
24215 #define DDRPHY_DX2BDLR2_DSNWBD_SHIFT             (24U)
24216 /*! DSNWBD - DQSN Write Bit Delay
24217  */
24218 #define DDRPHY_DX2BDLR2_DSNWBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX2BDLR2_DSNWBD_MASK)
24219 #define DDRPHY_DX2BDLR2_RESERVED_31_30_MASK      (0xC0000000U)
24220 #define DDRPHY_DX2BDLR2_RESERVED_31_30_SHIFT     (30U)
24221 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24222  */
24223 #define DDRPHY_DX2BDLR2_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_31_30_MASK)
24224 /*! @} */
24225 
24226 /*! @name DX2BDLR3 - DATX8 n Bit Delay Line Register 3 */
24227 /*! @{ */
24228 #define DDRPHY_DX2BDLR3_DQ0RBD_MASK              (0x3FU)
24229 #define DDRPHY_DX2BDLR3_DQ0RBD_SHIFT             (0U)
24230 /*! DQ0RBD - DQ0 Read Bit Delay
24231  */
24232 #define DDRPHY_DX2BDLR3_DQ0RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ0RBD_MASK)
24233 #define DDRPHY_DX2BDLR3_RESERVED_7_6_MASK        (0xC0U)
24234 #define DDRPHY_DX2BDLR3_RESERVED_7_6_SHIFT       (6U)
24235 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24236  */
24237 #define DDRPHY_DX2BDLR3_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_7_6_MASK)
24238 #define DDRPHY_DX2BDLR3_DQ1RBD_MASK              (0x3F00U)
24239 #define DDRPHY_DX2BDLR3_DQ1RBD_SHIFT             (8U)
24240 /*! DQ1RBD - DQ1 Read Bit Delay
24241  */
24242 #define DDRPHY_DX2BDLR3_DQ1RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ1RBD_MASK)
24243 #define DDRPHY_DX2BDLR3_RESERVED_15_14_MASK      (0xC000U)
24244 #define DDRPHY_DX2BDLR3_RESERVED_15_14_SHIFT     (14U)
24245 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24246  */
24247 #define DDRPHY_DX2BDLR3_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_15_14_MASK)
24248 #define DDRPHY_DX2BDLR3_DQ2RBD_MASK              (0x3F0000U)
24249 #define DDRPHY_DX2BDLR3_DQ2RBD_SHIFT             (16U)
24250 /*! DQ2RBD - DQ2 Read Bit Delay
24251  */
24252 #define DDRPHY_DX2BDLR3_DQ2RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ2RBD_MASK)
24253 #define DDRPHY_DX2BDLR3_RESERVED_23_22_MASK      (0xC00000U)
24254 #define DDRPHY_DX2BDLR3_RESERVED_23_22_SHIFT     (22U)
24255 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24256  */
24257 #define DDRPHY_DX2BDLR3_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_23_22_MASK)
24258 #define DDRPHY_DX2BDLR3_DQ3RBD_MASK              (0x3F000000U)
24259 #define DDRPHY_DX2BDLR3_DQ3RBD_SHIFT             (24U)
24260 /*! DQ3RBD - DQ3 Read Bit Delay
24261  */
24262 #define DDRPHY_DX2BDLR3_DQ3RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ3RBD_MASK)
24263 #define DDRPHY_DX2BDLR3_RESERVED_31_30_MASK      (0xC0000000U)
24264 #define DDRPHY_DX2BDLR3_RESERVED_31_30_SHIFT     (30U)
24265 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24266  */
24267 #define DDRPHY_DX2BDLR3_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_31_30_MASK)
24268 /*! @} */
24269 
24270 /*! @name DX2BDLR4 - DATX8 n Bit Delay Line Register 4 */
24271 /*! @{ */
24272 #define DDRPHY_DX2BDLR4_DQ4RBD_MASK              (0x3FU)
24273 #define DDRPHY_DX2BDLR4_DQ4RBD_SHIFT             (0U)
24274 /*! DQ4RBD - DQ4 Read Bit Delay
24275  */
24276 #define DDRPHY_DX2BDLR4_DQ4RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ4RBD_MASK)
24277 #define DDRPHY_DX2BDLR4_RESERVED_7_6_MASK        (0xC0U)
24278 #define DDRPHY_DX2BDLR4_RESERVED_7_6_SHIFT       (6U)
24279 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24280  */
24281 #define DDRPHY_DX2BDLR4_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_7_6_MASK)
24282 #define DDRPHY_DX2BDLR4_DQ5RBD_MASK              (0x3F00U)
24283 #define DDRPHY_DX2BDLR4_DQ5RBD_SHIFT             (8U)
24284 /*! DQ5RBD - DQ5 Read Bit Delay
24285  */
24286 #define DDRPHY_DX2BDLR4_DQ5RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ5RBD_MASK)
24287 #define DDRPHY_DX2BDLR4_RESERVED_15_14_MASK      (0xC000U)
24288 #define DDRPHY_DX2BDLR4_RESERVED_15_14_SHIFT     (14U)
24289 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24290  */
24291 #define DDRPHY_DX2BDLR4_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_15_14_MASK)
24292 #define DDRPHY_DX2BDLR4_DQ6RBD_MASK              (0x3F0000U)
24293 #define DDRPHY_DX2BDLR4_DQ6RBD_SHIFT             (16U)
24294 /*! DQ6RBD - DQ6 Read Bit Delay
24295  */
24296 #define DDRPHY_DX2BDLR4_DQ6RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ6RBD_MASK)
24297 #define DDRPHY_DX2BDLR4_RESERVED_23_22_MASK      (0xC00000U)
24298 #define DDRPHY_DX2BDLR4_RESERVED_23_22_SHIFT     (22U)
24299 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24300  */
24301 #define DDRPHY_DX2BDLR4_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_23_22_MASK)
24302 #define DDRPHY_DX2BDLR4_DQ7RBD_MASK              (0x3F000000U)
24303 #define DDRPHY_DX2BDLR4_DQ7RBD_SHIFT             (24U)
24304 /*! DQ7RBD - DQ7 Read Bit Delay
24305  */
24306 #define DDRPHY_DX2BDLR4_DQ7RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ7RBD_MASK)
24307 #define DDRPHY_DX2BDLR4_RESERVED_31_30_MASK      (0xC0000000U)
24308 #define DDRPHY_DX2BDLR4_RESERVED_31_30_SHIFT     (30U)
24309 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24310  */
24311 #define DDRPHY_DX2BDLR4_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_31_30_MASK)
24312 /*! @} */
24313 
24314 /*! @name DX2BDLR5 - DATX8 n Bit Delay Line Register 5 */
24315 /*! @{ */
24316 #define DDRPHY_DX2BDLR5_DMRBD_MASK               (0x3FU)
24317 #define DDRPHY_DX2BDLR5_DMRBD_SHIFT              (0U)
24318 /*! DMRBD - DM Read Bit Delay
24319  */
24320 #define DDRPHY_DX2BDLR5_DMRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR5_DMRBD_SHIFT)) & DDRPHY_DX2BDLR5_DMRBD_MASK)
24321 #define DDRPHY_DX2BDLR5_RESERVED_31_6_MASK       (0xFFFFFFC0U)
24322 #define DDRPHY_DX2BDLR5_RESERVED_31_6_SHIFT      (6U)
24323 /*! RESERVED_31_6 - Reserved. Return zeroes on reads.
24324  */
24325 #define DDRPHY_DX2BDLR5_RESERVED_31_6(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX2BDLR5_RESERVED_31_6_MASK)
24326 /*! @} */
24327 
24328 /*! @name DX2BDLR6 - DATX8 n Bit Delay Line Register 6 */
24329 /*! @{ */
24330 #define DDRPHY_DX2BDLR6_RESERVED_7_0_MASK        (0xFFU)
24331 #define DDRPHY_DX2BDLR6_RESERVED_7_0_SHIFT       (0U)
24332 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
24333  */
24334 #define DDRPHY_DX2BDLR6_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX2BDLR6_RESERVED_7_0_MASK)
24335 #define DDRPHY_DX2BDLR6_PDRBD_MASK               (0x3F00U)
24336 #define DDRPHY_DX2BDLR6_PDRBD_SHIFT              (8U)
24337 /*! PDRBD - Power down receiver Bit Delay
24338  */
24339 #define DDRPHY_DX2BDLR6_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_PDRBD_SHIFT)) & DDRPHY_DX2BDLR6_PDRBD_MASK)
24340 #define DDRPHY_DX2BDLR6_RESERVED_15_14_MASK      (0xC000U)
24341 #define DDRPHY_DX2BDLR6_RESERVED_15_14_SHIFT     (14U)
24342 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24343  */
24344 #define DDRPHY_DX2BDLR6_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR6_RESERVED_15_14_MASK)
24345 #define DDRPHY_DX2BDLR6_TERBD_MASK               (0x3F0000U)
24346 #define DDRPHY_DX2BDLR6_TERBD_SHIFT              (16U)
24347 /*! TERBD - Termination Enable Bit Delay
24348  */
24349 #define DDRPHY_DX2BDLR6_TERBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_TERBD_SHIFT)) & DDRPHY_DX2BDLR6_TERBD_MASK)
24350 #define DDRPHY_DX2BDLR6_RESERVED_31_22_MASK      (0xFFC00000U)
24351 #define DDRPHY_DX2BDLR6_RESERVED_31_22_SHIFT     (22U)
24352 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
24353  */
24354 #define DDRPHY_DX2BDLR6_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR6_RESERVED_31_22_MASK)
24355 /*! @} */
24356 
24357 /*! @name DX2BDLR7 - DATX8 n Bit Delay Line Register 7 */
24358 /*! @{ */
24359 #define DDRPHY_DX2BDLR7_RESERVED_5_0_MASK        (0x3FU)
24360 #define DDRPHY_DX2BDLR7_RESERVED_5_0_SHIFT       (0U)
24361 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
24362  */
24363 #define DDRPHY_DX2BDLR7_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_5_0_MASK)
24364 #define DDRPHY_DX2BDLR7_RESERVED_7_6_MASK        (0xC0U)
24365 #define DDRPHY_DX2BDLR7_RESERVED_7_6_SHIFT       (6U)
24366 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24367  */
24368 #define DDRPHY_DX2BDLR7_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_7_6_MASK)
24369 #define DDRPHY_DX2BDLR7_RESERVED_13_8_MASK       (0x3F00U)
24370 #define DDRPHY_DX2BDLR7_RESERVED_13_8_SHIFT      (8U)
24371 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
24372  */
24373 #define DDRPHY_DX2BDLR7_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_13_8_MASK)
24374 #define DDRPHY_DX2BDLR7_RESERVED_15_14_MASK      (0xC000U)
24375 #define DDRPHY_DX2BDLR7_RESERVED_15_14_SHIFT     (14U)
24376 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24377  */
24378 #define DDRPHY_DX2BDLR7_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_15_14_MASK)
24379 #define DDRPHY_DX2BDLR7_RESERVED_21_16_MASK      (0x3F0000U)
24380 #define DDRPHY_DX2BDLR7_RESERVED_21_16_SHIFT     (16U)
24381 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
24382  */
24383 #define DDRPHY_DX2BDLR7_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_21_16_MASK)
24384 #define DDRPHY_DX2BDLR7_RESERVED_31_22_MASK      (0xFFC00000U)
24385 #define DDRPHY_DX2BDLR7_RESERVED_31_22_SHIFT     (22U)
24386 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
24387  */
24388 #define DDRPHY_DX2BDLR7_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_31_22_MASK)
24389 /*! @} */
24390 
24391 /*! @name DX2BDLR8 - DATX8 n Bit Delay Line Register 8 */
24392 /*! @{ */
24393 #define DDRPHY_DX2BDLR8_RESERVED_5_0_MASK        (0x3FU)
24394 #define DDRPHY_DX2BDLR8_RESERVED_5_0_SHIFT       (0U)
24395 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
24396  */
24397 #define DDRPHY_DX2BDLR8_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_5_0_MASK)
24398 #define DDRPHY_DX2BDLR8_RESERVED_7_6_MASK        (0xC0U)
24399 #define DDRPHY_DX2BDLR8_RESERVED_7_6_SHIFT       (6U)
24400 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24401  */
24402 #define DDRPHY_DX2BDLR8_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_7_6_MASK)
24403 #define DDRPHY_DX2BDLR8_RESERVED_13_8_MASK       (0x3F00U)
24404 #define DDRPHY_DX2BDLR8_RESERVED_13_8_SHIFT      (8U)
24405 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
24406  */
24407 #define DDRPHY_DX2BDLR8_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_13_8_MASK)
24408 #define DDRPHY_DX2BDLR8_RESERVED_15_14_MASK      (0xC000U)
24409 #define DDRPHY_DX2BDLR8_RESERVED_15_14_SHIFT     (14U)
24410 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24411  */
24412 #define DDRPHY_DX2BDLR8_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_15_14_MASK)
24413 #define DDRPHY_DX2BDLR8_RESERVED_21_16_MASK      (0x3F0000U)
24414 #define DDRPHY_DX2BDLR8_RESERVED_21_16_SHIFT     (16U)
24415 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
24416  */
24417 #define DDRPHY_DX2BDLR8_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_21_16_MASK)
24418 #define DDRPHY_DX2BDLR8_RESERVED_31_22_MASK      (0xFFC00000U)
24419 #define DDRPHY_DX2BDLR8_RESERVED_31_22_SHIFT     (22U)
24420 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
24421  */
24422 #define DDRPHY_DX2BDLR8_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_31_22_MASK)
24423 /*! @} */
24424 
24425 /*! @name DX2BDLR9 - DATX8 n Bit Delay Line Register 9 */
24426 /*! @{ */
24427 #define DDRPHY_DX2BDLR9_RESERVED_5_0_MASK        (0x3FU)
24428 #define DDRPHY_DX2BDLR9_RESERVED_5_0_SHIFT       (0U)
24429 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
24430  */
24431 #define DDRPHY_DX2BDLR9_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_5_0_MASK)
24432 #define DDRPHY_DX2BDLR9_RESERVED_7_6_MASK        (0xC0U)
24433 #define DDRPHY_DX2BDLR9_RESERVED_7_6_SHIFT       (6U)
24434 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24435  */
24436 #define DDRPHY_DX2BDLR9_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_7_6_MASK)
24437 #define DDRPHY_DX2BDLR9_RESERVED_13_8_MASK       (0x3F00U)
24438 #define DDRPHY_DX2BDLR9_RESERVED_13_8_SHIFT      (8U)
24439 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
24440  */
24441 #define DDRPHY_DX2BDLR9_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_13_8_MASK)
24442 #define DDRPHY_DX2BDLR9_RESERVED_15_14_MASK      (0xC000U)
24443 #define DDRPHY_DX2BDLR9_RESERVED_15_14_SHIFT     (14U)
24444 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24445  */
24446 #define DDRPHY_DX2BDLR9_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_15_14_MASK)
24447 #define DDRPHY_DX2BDLR9_RESERVED_21_16_MASK      (0x3F0000U)
24448 #define DDRPHY_DX2BDLR9_RESERVED_21_16_SHIFT     (16U)
24449 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
24450  */
24451 #define DDRPHY_DX2BDLR9_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_21_16_MASK)
24452 #define DDRPHY_DX2BDLR9_RESERVED_31_22_MASK      (0xFFC00000U)
24453 #define DDRPHY_DX2BDLR9_RESERVED_31_22_SHIFT     (22U)
24454 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
24455  */
24456 #define DDRPHY_DX2BDLR9_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_31_22_MASK)
24457 /*! @} */
24458 
24459 /*! @name DX2LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
24460 /*! @{ */
24461 #define DDRPHY_DX2LCDLR0_WLD_MASK                (0x1FFU)
24462 #define DDRPHY_DX2LCDLR0_WLD_SHIFT               (0U)
24463 /*! WLD - Write Leveling Delay
24464  */
24465 #define DDRPHY_DX2LCDLR0_WLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_WLD_SHIFT)) & DDRPHY_DX2LCDLR0_WLD_MASK)
24466 #define DDRPHY_DX2LCDLR0_RESERVED_15_9_MASK      (0xFE00U)
24467 #define DDRPHY_DX2LCDLR0_RESERVED_15_9_SHIFT     (9U)
24468 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24469  */
24470 #define DDRPHY_DX2LCDLR0_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR0_RESERVED_15_9_MASK)
24471 #define DDRPHY_DX2LCDLR0_RESERVED_24_16_MASK     (0x1FF0000U)
24472 #define DDRPHY_DX2LCDLR0_RESERVED_24_16_SHIFT    (16U)
24473 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24474  */
24475 #define DDRPHY_DX2LCDLR0_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR0_RESERVED_24_16_MASK)
24476 #define DDRPHY_DX2LCDLR0_RESERVED_31_25_MASK     (0xFE000000U)
24477 #define DDRPHY_DX2LCDLR0_RESERVED_31_25_SHIFT    (25U)
24478 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24479  */
24480 #define DDRPHY_DX2LCDLR0_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR0_RESERVED_31_25_MASK)
24481 /*! @} */
24482 
24483 /*! @name DX2LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
24484 /*! @{ */
24485 #define DDRPHY_DX2LCDLR1_WDQD_MASK               (0x1FFU)
24486 #define DDRPHY_DX2LCDLR1_WDQD_SHIFT              (0U)
24487 /*! WDQD - Write Data Delay
24488  */
24489 #define DDRPHY_DX2LCDLR1_WDQD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_WDQD_SHIFT)) & DDRPHY_DX2LCDLR1_WDQD_MASK)
24490 #define DDRPHY_DX2LCDLR1_RESERVED_15_9_MASK      (0xFE00U)
24491 #define DDRPHY_DX2LCDLR1_RESERVED_15_9_SHIFT     (9U)
24492 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24493  */
24494 #define DDRPHY_DX2LCDLR1_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR1_RESERVED_15_9_MASK)
24495 #define DDRPHY_DX2LCDLR1_RESERVED_24_16_MASK     (0x1FF0000U)
24496 #define DDRPHY_DX2LCDLR1_RESERVED_24_16_SHIFT    (16U)
24497 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24498  */
24499 #define DDRPHY_DX2LCDLR1_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR1_RESERVED_24_16_MASK)
24500 #define DDRPHY_DX2LCDLR1_RESERVED_31_25_MASK     (0xFE000000U)
24501 #define DDRPHY_DX2LCDLR1_RESERVED_31_25_SHIFT    (25U)
24502 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24503  */
24504 #define DDRPHY_DX2LCDLR1_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR1_RESERVED_31_25_MASK)
24505 /*! @} */
24506 
24507 /*! @name DX2LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
24508 /*! @{ */
24509 #define DDRPHY_DX2LCDLR2_DQSGD_MASK              (0x1FFU)
24510 #define DDRPHY_DX2LCDLR2_DQSGD_SHIFT             (0U)
24511 /*! DQSGD - Read DQS Gating Delay
24512  */
24513 #define DDRPHY_DX2LCDLR2_DQSGD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX2LCDLR2_DQSGD_MASK)
24514 #define DDRPHY_DX2LCDLR2_RESERVED_15_9_MASK      (0xFE00U)
24515 #define DDRPHY_DX2LCDLR2_RESERVED_15_9_SHIFT     (9U)
24516 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24517  */
24518 #define DDRPHY_DX2LCDLR2_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR2_RESERVED_15_9_MASK)
24519 #define DDRPHY_DX2LCDLR2_RESERVED_24_16_MASK     (0x1FF0000U)
24520 #define DDRPHY_DX2LCDLR2_RESERVED_24_16_SHIFT    (16U)
24521 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24522  */
24523 #define DDRPHY_DX2LCDLR2_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR2_RESERVED_24_16_MASK)
24524 #define DDRPHY_DX2LCDLR2_RESERVED_31_25_MASK     (0xFE000000U)
24525 #define DDRPHY_DX2LCDLR2_RESERVED_31_25_SHIFT    (25U)
24526 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24527  */
24528 #define DDRPHY_DX2LCDLR2_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR2_RESERVED_31_25_MASK)
24529 /*! @} */
24530 
24531 /*! @name DX2LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
24532 /*! @{ */
24533 #define DDRPHY_DX2LCDLR3_RDQSD_MASK              (0x1FFU)
24534 #define DDRPHY_DX2LCDLR3_RDQSD_SHIFT             (0U)
24535 /*! RDQSD - Read DQS Delay
24536  */
24537 #define DDRPHY_DX2LCDLR3_RDQSD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX2LCDLR3_RDQSD_MASK)
24538 #define DDRPHY_DX2LCDLR3_RESERVED_15_9_MASK      (0xFE00U)
24539 #define DDRPHY_DX2LCDLR3_RESERVED_15_9_SHIFT     (9U)
24540 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24541  */
24542 #define DDRPHY_DX2LCDLR3_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR3_RESERVED_15_9_MASK)
24543 #define DDRPHY_DX2LCDLR3_RESERVED_24_16_MASK     (0x1FF0000U)
24544 #define DDRPHY_DX2LCDLR3_RESERVED_24_16_SHIFT    (16U)
24545 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24546  */
24547 #define DDRPHY_DX2LCDLR3_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR3_RESERVED_24_16_MASK)
24548 #define DDRPHY_DX2LCDLR3_RESERVED_31_25_MASK     (0xFE000000U)
24549 #define DDRPHY_DX2LCDLR3_RESERVED_31_25_SHIFT    (25U)
24550 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24551  */
24552 #define DDRPHY_DX2LCDLR3_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR3_RESERVED_31_25_MASK)
24553 /*! @} */
24554 
24555 /*! @name DX2LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
24556 /*! @{ */
24557 #define DDRPHY_DX2LCDLR4_RDQSND_MASK             (0x1FFU)
24558 #define DDRPHY_DX2LCDLR4_RDQSND_SHIFT            (0U)
24559 /*! RDQSND - Read DQSN Delay
24560  */
24561 #define DDRPHY_DX2LCDLR4_RDQSND(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX2LCDLR4_RDQSND_MASK)
24562 #define DDRPHY_DX2LCDLR4_RESERVED_15_9_MASK      (0xFE00U)
24563 #define DDRPHY_DX2LCDLR4_RESERVED_15_9_SHIFT     (9U)
24564 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24565  */
24566 #define DDRPHY_DX2LCDLR4_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR4_RESERVED_15_9_MASK)
24567 #define DDRPHY_DX2LCDLR4_RESERVED_24_16_MASK     (0x1FF0000U)
24568 #define DDRPHY_DX2LCDLR4_RESERVED_24_16_SHIFT    (16U)
24569 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24570  */
24571 #define DDRPHY_DX2LCDLR4_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR4_RESERVED_24_16_MASK)
24572 #define DDRPHY_DX2LCDLR4_RESERVED_31_25_MASK     (0xFE000000U)
24573 #define DDRPHY_DX2LCDLR4_RESERVED_31_25_SHIFT    (25U)
24574 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24575  */
24576 #define DDRPHY_DX2LCDLR4_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR4_RESERVED_31_25_MASK)
24577 /*! @} */
24578 
24579 /*! @name DX2LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
24580 /*! @{ */
24581 #define DDRPHY_DX2LCDLR5_DQSGSD_MASK             (0x1FFU)
24582 #define DDRPHY_DX2LCDLR5_DQSGSD_SHIFT            (0U)
24583 /*! DQSGSD - DQS Gating Status Delay
24584  */
24585 #define DDRPHY_DX2LCDLR5_DQSGSD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX2LCDLR5_DQSGSD_MASK)
24586 #define DDRPHY_DX2LCDLR5_RESERVED_15_9_MASK      (0xFE00U)
24587 #define DDRPHY_DX2LCDLR5_RESERVED_15_9_SHIFT     (9U)
24588 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24589  */
24590 #define DDRPHY_DX2LCDLR5_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR5_RESERVED_15_9_MASK)
24591 #define DDRPHY_DX2LCDLR5_RESERVED_24_16_MASK     (0x1FF0000U)
24592 #define DDRPHY_DX2LCDLR5_RESERVED_24_16_SHIFT    (16U)
24593 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24594  */
24595 #define DDRPHY_DX2LCDLR5_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR5_RESERVED_24_16_MASK)
24596 #define DDRPHY_DX2LCDLR5_RESERVED_31_25_MASK     (0xFE000000U)
24597 #define DDRPHY_DX2LCDLR5_RESERVED_31_25_SHIFT    (25U)
24598 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24599  */
24600 #define DDRPHY_DX2LCDLR5_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR5_RESERVED_31_25_MASK)
24601 /*! @} */
24602 
24603 /*! @name DX2MDLR0 - DATX8 n Master Delay Line Register 0 */
24604 /*! @{ */
24605 #define DDRPHY_DX2MDLR0_IPRD_MASK                (0x1FFU)
24606 #define DDRPHY_DX2MDLR0_IPRD_SHIFT               (0U)
24607 /*! IPRD - Initial Period
24608  */
24609 #define DDRPHY_DX2MDLR0_IPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_IPRD_SHIFT)) & DDRPHY_DX2MDLR0_IPRD_MASK)
24610 #define DDRPHY_DX2MDLR0_RESERVED_15_9_MASK       (0xFE00U)
24611 #define DDRPHY_DX2MDLR0_RESERVED_15_9_SHIFT      (9U)
24612 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24613  */
24614 #define DDRPHY_DX2MDLR0_RESERVED_15_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX2MDLR0_RESERVED_15_9_MASK)
24615 #define DDRPHY_DX2MDLR0_TPRD_MASK                (0x1FF0000U)
24616 #define DDRPHY_DX2MDLR0_TPRD_SHIFT               (16U)
24617 /*! TPRD - Target Period
24618  */
24619 #define DDRPHY_DX2MDLR0_TPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_TPRD_SHIFT)) & DDRPHY_DX2MDLR0_TPRD_MASK)
24620 #define DDRPHY_DX2MDLR0_RESERVED_31_25_MASK      (0xFE000000U)
24621 #define DDRPHY_DX2MDLR0_RESERVED_31_25_SHIFT     (25U)
24622 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24623  */
24624 #define DDRPHY_DX2MDLR0_RESERVED_31_25(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX2MDLR0_RESERVED_31_25_MASK)
24625 /*! @} */
24626 
24627 /*! @name DX2MDLR1 - DATX8 n Master Delay Line Register 1 */
24628 /*! @{ */
24629 #define DDRPHY_DX2MDLR1_MDLD_MASK                (0x1FFU)
24630 #define DDRPHY_DX2MDLR1_MDLD_SHIFT               (0U)
24631 /*! MDLD - MDL Delay
24632  */
24633 #define DDRPHY_DX2MDLR1_MDLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR1_MDLD_SHIFT)) & DDRPHY_DX2MDLR1_MDLD_MASK)
24634 #define DDRPHY_DX2MDLR1_RESERVED_31_9_MASK       (0xFFFFFE00U)
24635 #define DDRPHY_DX2MDLR1_RESERVED_31_9_SHIFT      (9U)
24636 /*! RESERVED_31_9 - Reserved. Return zeroes on reads.
24637  */
24638 #define DDRPHY_DX2MDLR1_RESERVED_31_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX2MDLR1_RESERVED_31_9_MASK)
24639 /*! @} */
24640 
24641 /*! @name DX2GTR0 - DATX8 n General Timing Register 0 */
24642 /*! @{ */
24643 #define DDRPHY_DX2GTR0_DGSL_MASK                 (0x1FU)
24644 #define DDRPHY_DX2GTR0_DGSL_SHIFT                (0U)
24645 /*! DGSL - DQS Gating System Latency
24646  */
24647 #define DDRPHY_DX2GTR0_DGSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_DGSL_SHIFT)) & DDRPHY_DX2GTR0_DGSL_MASK)
24648 #define DDRPHY_DX2GTR0_RESERVED_7_5_MASK         (0xE0U)
24649 #define DDRPHY_DX2GTR0_RESERVED_7_5_SHIFT        (5U)
24650 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
24651  */
24652 #define DDRPHY_DX2GTR0_RESERVED_7_5(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_7_5_MASK)
24653 #define DDRPHY_DX2GTR0_RESERVED_12_8_MASK        (0x1F00U)
24654 #define DDRPHY_DX2GTR0_RESERVED_12_8_SHIFT       (8U)
24655 /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
24656  */
24657 #define DDRPHY_DX2GTR0_RESERVED_12_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_12_8_MASK)
24658 #define DDRPHY_DX2GTR0_RESERVED_15_13_MASK       (0xE000U)
24659 #define DDRPHY_DX2GTR0_RESERVED_15_13_SHIFT      (13U)
24660 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
24661  */
24662 #define DDRPHY_DX2GTR0_RESERVED_15_13(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_15_13_MASK)
24663 #define DDRPHY_DX2GTR0_WLSL_MASK                 (0xF0000U)
24664 #define DDRPHY_DX2GTR0_WLSL_SHIFT                (16U)
24665 /*! WLSL - Write Leveling System Latency
24666  */
24667 #define DDRPHY_DX2GTR0_WLSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_WLSL_SHIFT)) & DDRPHY_DX2GTR0_WLSL_MASK)
24668 #define DDRPHY_DX2GTR0_RESERVED_23_20_MASK       (0xF00000U)
24669 #define DDRPHY_DX2GTR0_RESERVED_23_20_SHIFT      (20U)
24670 /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
24671  */
24672 #define DDRPHY_DX2GTR0_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_23_20_MASK)
24673 #define DDRPHY_DX2GTR0_WDQSL_MASK                (0x7000000U)
24674 #define DDRPHY_DX2GTR0_WDQSL_SHIFT               (24U)
24675 /*! WDQSL - DQ Write Path Latency Pipeline
24676  */
24677 #define DDRPHY_DX2GTR0_WDQSL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_WDQSL_SHIFT)) & DDRPHY_DX2GTR0_WDQSL_MASK)
24678 #define DDRPHY_DX2GTR0_RESERVED_31_24_MASK       (0xF8000000U)
24679 #define DDRPHY_DX2GTR0_RESERVED_31_24_SHIFT      (27U)
24680 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
24681  */
24682 #define DDRPHY_DX2GTR0_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_31_24_MASK)
24683 /*! @} */
24684 
24685 /*! @name DX2RSR0 - DATX8 n Rank Status Register 0 */
24686 /*! @{ */
24687 #define DDRPHY_DX2RSR0_QSGERR_MASK               (0xFFFFU)
24688 #define DDRPHY_DX2RSR0_QSGERR_SHIFT              (0U)
24689 /*! QSGERR - DQS Gate Training Error
24690  */
24691 #define DDRPHY_DX2RSR0_QSGERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR0_QSGERR_SHIFT)) & DDRPHY_DX2RSR0_QSGERR_MASK)
24692 #define DDRPHY_DX2RSR0_RESERVED_31_16_MASK       (0xFFFF0000U)
24693 #define DDRPHY_DX2RSR0_RESERVED_31_16_SHIFT      (16U)
24694 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
24695  */
24696 #define DDRPHY_DX2RSR0_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR0_RESERVED_31_16_MASK)
24697 /*! @} */
24698 
24699 /*! @name DX2RSR1 - DATX8 n Rank Status Register 1 */
24700 /*! @{ */
24701 #define DDRPHY_DX2RSR1_RDLVLERR_MASK             (0xFFFFU)
24702 #define DDRPHY_DX2RSR1_RDLVLERR_SHIFT            (0U)
24703 /*! RDLVLERR - Read Leveling Error
24704  */
24705 #define DDRPHY_DX2RSR1_RDLVLERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX2RSR1_RDLVLERR_MASK)
24706 #define DDRPHY_DX2RSR1_RESERVED_31_16_MASK       (0xFFFF0000U)
24707 #define DDRPHY_DX2RSR1_RESERVED_31_16_SHIFT      (16U)
24708 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
24709  */
24710 #define DDRPHY_DX2RSR1_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR1_RESERVED_31_16_MASK)
24711 /*! @} */
24712 
24713 /*! @name DX2RSR2 - DATX8 n Rank Status Register 2 */
24714 /*! @{ */
24715 #define DDRPHY_DX2RSR2_WLAWN_MASK                (0xFFFFU)
24716 #define DDRPHY_DX2RSR2_WLAWN_SHIFT               (0U)
24717 /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
24718  */
24719 #define DDRPHY_DX2RSR2_WLAWN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR2_WLAWN_SHIFT)) & DDRPHY_DX2RSR2_WLAWN_MASK)
24720 #define DDRPHY_DX2RSR2_RESERVED_31_16_MASK       (0xFFFF0000U)
24721 #define DDRPHY_DX2RSR2_RESERVED_31_16_SHIFT      (16U)
24722 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
24723  */
24724 #define DDRPHY_DX2RSR2_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR2_RESERVED_31_16_MASK)
24725 /*! @} */
24726 
24727 /*! @name DX2RSR3 - DATX8 n Rank Status Register 3 */
24728 /*! @{ */
24729 #define DDRPHY_DX2RSR3_WLAERR_MASK               (0xFFFFU)
24730 #define DDRPHY_DX2RSR3_WLAERR_SHIFT              (0U)
24731 /*! WLAERR - Write Leveling Adjustment Error
24732  */
24733 #define DDRPHY_DX2RSR3_WLAERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR3_WLAERR_SHIFT)) & DDRPHY_DX2RSR3_WLAERR_MASK)
24734 #define DDRPHY_DX2RSR3_RESERVED_31_16_MASK       (0xFFFF0000U)
24735 #define DDRPHY_DX2RSR3_RESERVED_31_16_SHIFT      (16U)
24736 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
24737  */
24738 #define DDRPHY_DX2RSR3_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR3_RESERVED_31_16_MASK)
24739 /*! @} */
24740 
24741 /*! @name DX2GSR0 - DATX8 n General Status Register 0 */
24742 /*! @{ */
24743 #define DDRPHY_DX2GSR0_WDQCAL_MASK               (0x1U)
24744 #define DDRPHY_DX2GSR0_WDQCAL_SHIFT              (0U)
24745 /*! WDQCAL - Write DQ Calibration
24746  */
24747 #define DDRPHY_DX2GSR0_WDQCAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WDQCAL_SHIFT)) & DDRPHY_DX2GSR0_WDQCAL_MASK)
24748 #define DDRPHY_DX2GSR0_RDQSCAL_MASK              (0x2U)
24749 #define DDRPHY_DX2GSR0_RDQSCAL_SHIFT             (1U)
24750 /*! RDQSCAL - Read DQS Calibration
24751  */
24752 #define DDRPHY_DX2GSR0_RDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX2GSR0_RDQSCAL_MASK)
24753 #define DDRPHY_DX2GSR0_RDQSNCAL_MASK             (0x4U)
24754 #define DDRPHY_DX2GSR0_RDQSNCAL_SHIFT            (2U)
24755 /*! RDQSNCAL - Read DQS# Calibration
24756  */
24757 #define DDRPHY_DX2GSR0_RDQSNCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX2GSR0_RDQSNCAL_MASK)
24758 #define DDRPHY_DX2GSR0_GDQSCAL_MASK              (0x8U)
24759 #define DDRPHY_DX2GSR0_GDQSCAL_SHIFT             (3U)
24760 /*! GDQSCAL - Read DQS gating Calibration
24761  */
24762 #define DDRPHY_DX2GSR0_GDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX2GSR0_GDQSCAL_MASK)
24763 #define DDRPHY_DX2GSR0_WLCAL_MASK                (0x10U)
24764 #define DDRPHY_DX2GSR0_WLCAL_SHIFT               (4U)
24765 /*! WLCAL - Write Leveling Calibration
24766  */
24767 #define DDRPHY_DX2GSR0_WLCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLCAL_SHIFT)) & DDRPHY_DX2GSR0_WLCAL_MASK)
24768 #define DDRPHY_DX2GSR0_WLDONE_MASK               (0x20U)
24769 #define DDRPHY_DX2GSR0_WLDONE_SHIFT              (5U)
24770 /*! WLDONE - Write Leveling Done
24771  */
24772 #define DDRPHY_DX2GSR0_WLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLDONE_SHIFT)) & DDRPHY_DX2GSR0_WLDONE_MASK)
24773 #define DDRPHY_DX2GSR0_WLERR_MASK                (0x40U)
24774 #define DDRPHY_DX2GSR0_WLERR_SHIFT               (6U)
24775 /*! WLERR - Write Leveling Error
24776  */
24777 #define DDRPHY_DX2GSR0_WLERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLERR_SHIFT)) & DDRPHY_DX2GSR0_WLERR_MASK)
24778 #define DDRPHY_DX2GSR0_WLPRD_MASK                (0xFF80U)
24779 #define DDRPHY_DX2GSR0_WLPRD_SHIFT               (7U)
24780 /*! WLPRD - Write Leveling Period
24781  */
24782 #define DDRPHY_DX2GSR0_WLPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLPRD_SHIFT)) & DDRPHY_DX2GSR0_WLPRD_MASK)
24783 #define DDRPHY_DX2GSR0_DPLOCK_MASK               (0x10000U)
24784 #define DDRPHY_DX2GSR0_DPLOCK_SHIFT              (16U)
24785 /*! DPLOCK - DATX8 PLL Lock
24786  */
24787 #define DDRPHY_DX2GSR0_DPLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_DPLOCK_SHIFT)) & DDRPHY_DX2GSR0_DPLOCK_MASK)
24788 #define DDRPHY_DX2GSR0_GDQSPRD_MASK              (0x3FE0000U)
24789 #define DDRPHY_DX2GSR0_GDQSPRD_SHIFT             (17U)
24790 /*! GDQSPRD - Read DQS gating Period
24791  */
24792 #define DDRPHY_DX2GSR0_GDQSPRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX2GSR0_GDQSPRD_MASK)
24793 #define DDRPHY_DX2GSR0_RESERVED_29_26_MASK       (0x3C000000U)
24794 #define DDRPHY_DX2GSR0_RESERVED_29_26_SHIFT      (26U)
24795 /*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
24796  */
24797 #define DDRPHY_DX2GSR0_RESERVED_29_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX2GSR0_RESERVED_29_26_MASK)
24798 #define DDRPHY_DX2GSR0_WLDQ_MASK                 (0x40000000U)
24799 #define DDRPHY_DX2GSR0_WLDQ_SHIFT                (30U)
24800 /*! WLDQ - Write Leveling DQ Status
24801  */
24802 #define DDRPHY_DX2GSR0_WLDQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLDQ_SHIFT)) & DDRPHY_DX2GSR0_WLDQ_MASK)
24803 #define DDRPHY_DX2GSR0_RESERVED_31_MASK          (0x80000000U)
24804 #define DDRPHY_DX2GSR0_RESERVED_31_SHIFT         (31U)
24805 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
24806  */
24807 #define DDRPHY_DX2GSR0_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX2GSR0_RESERVED_31_MASK)
24808 /*! @} */
24809 
24810 /*! @name DX2GSR1 - DATX8 n General Status Register 1 */
24811 /*! @{ */
24812 #define DDRPHY_DX2GSR1_DLTDONE_MASK              (0x1U)
24813 #define DDRPHY_DX2GSR1_DLTDONE_SHIFT             (0U)
24814 /*! DLTDONE - Delay Line Test Done
24815  */
24816 #define DDRPHY_DX2GSR1_DLTDONE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR1_DLTDONE_SHIFT)) & DDRPHY_DX2GSR1_DLTDONE_MASK)
24817 #define DDRPHY_DX2GSR1_DLTCODE_MASK              (0x1FFFFFEU)
24818 #define DDRPHY_DX2GSR1_DLTCODE_SHIFT             (1U)
24819 /*! DLTCODE - Delay Line Test Code
24820  */
24821 #define DDRPHY_DX2GSR1_DLTCODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR1_DLTCODE_SHIFT)) & DDRPHY_DX2GSR1_DLTCODE_MASK)
24822 #define DDRPHY_DX2GSR1_RESERVED_31_25_MASK       (0xFE000000U)
24823 #define DDRPHY_DX2GSR1_RESERVED_31_25_SHIFT      (25U)
24824 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
24825  */
24826 #define DDRPHY_DX2GSR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX2GSR1_RESERVED_31_25_MASK)
24827 /*! @} */
24828 
24829 /*! @name DX2GSR2 - DATX8 n General Status Register 2 */
24830 /*! @{ */
24831 #define DDRPHY_DX2GSR2_RDERR_MASK                (0x1U)
24832 #define DDRPHY_DX2GSR2_RDERR_SHIFT               (0U)
24833 /*! RDERR - Read Bit Deskew Error
24834  */
24835 #define DDRPHY_DX2GSR2_RDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_RDERR_SHIFT)) & DDRPHY_DX2GSR2_RDERR_MASK)
24836 #define DDRPHY_DX2GSR2_RDWN_MASK                 (0x2U)
24837 #define DDRPHY_DX2GSR2_RDWN_SHIFT                (1U)
24838 /*! RDWN - Read Bit Deskew Warning
24839  */
24840 #define DDRPHY_DX2GSR2_RDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_RDWN_SHIFT)) & DDRPHY_DX2GSR2_RDWN_MASK)
24841 #define DDRPHY_DX2GSR2_WDERR_MASK                (0x4U)
24842 #define DDRPHY_DX2GSR2_WDERR_SHIFT               (2U)
24843 /*! WDERR - Write Bit Deskew Error
24844  */
24845 #define DDRPHY_DX2GSR2_WDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WDERR_SHIFT)) & DDRPHY_DX2GSR2_WDERR_MASK)
24846 #define DDRPHY_DX2GSR2_WDWN_MASK                 (0x8U)
24847 #define DDRPHY_DX2GSR2_WDWN_SHIFT                (3U)
24848 /*! WDWN - Write Bit Deskew Warning
24849  */
24850 #define DDRPHY_DX2GSR2_WDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WDWN_SHIFT)) & DDRPHY_DX2GSR2_WDWN_MASK)
24851 #define DDRPHY_DX2GSR2_REERR_MASK                (0x10U)
24852 #define DDRPHY_DX2GSR2_REERR_SHIFT               (4U)
24853 /*! REERR - Read Eye Centering Error
24854  */
24855 #define DDRPHY_DX2GSR2_REERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_REERR_SHIFT)) & DDRPHY_DX2GSR2_REERR_MASK)
24856 #define DDRPHY_DX2GSR2_REWN_MASK                 (0x20U)
24857 #define DDRPHY_DX2GSR2_REWN_SHIFT                (5U)
24858 /*! REWN - Read Eye Centering Warning
24859  */
24860 #define DDRPHY_DX2GSR2_REWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_REWN_SHIFT)) & DDRPHY_DX2GSR2_REWN_MASK)
24861 #define DDRPHY_DX2GSR2_WEERR_MASK                (0x40U)
24862 #define DDRPHY_DX2GSR2_WEERR_SHIFT               (6U)
24863 /*! WEERR - Write Eye Centering Error
24864  */
24865 #define DDRPHY_DX2GSR2_WEERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WEERR_SHIFT)) & DDRPHY_DX2GSR2_WEERR_MASK)
24866 #define DDRPHY_DX2GSR2_WEWN_MASK                 (0x80U)
24867 #define DDRPHY_DX2GSR2_WEWN_SHIFT                (7U)
24868 /*! WEWN - Write Eye Centering Warning
24869  */
24870 #define DDRPHY_DX2GSR2_WEWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WEWN_SHIFT)) & DDRPHY_DX2GSR2_WEWN_MASK)
24871 #define DDRPHY_DX2GSR2_ESTAT_MASK                (0xF00U)
24872 #define DDRPHY_DX2GSR2_ESTAT_SHIFT               (8U)
24873 /*! ESTAT - Error Status
24874  */
24875 #define DDRPHY_DX2GSR2_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_ESTAT_SHIFT)) & DDRPHY_DX2GSR2_ESTAT_MASK)
24876 #define DDRPHY_DX2GSR2_DQS2DQERR_MASK            (0xFF000U)
24877 #define DDRPHY_DX2GSR2_DQS2DQERR_SHIFT           (12U)
24878 /*! DQS2DQERR - Write DQS2DQ Training Error
24879  */
24880 #define DDRPHY_DX2GSR2_DQS2DQERR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX2GSR2_DQS2DQERR_MASK)
24881 #define DDRPHY_DX2GSR2_SRDERR_MASK               (0x100000U)
24882 #define DDRPHY_DX2GSR2_SRDERR_SHIFT              (20U)
24883 /*! SRDERR - Static Read Error
24884  */
24885 #define DDRPHY_DX2GSR2_SRDERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_SRDERR_SHIFT)) & DDRPHY_DX2GSR2_SRDERR_MASK)
24886 #define DDRPHY_DX2GSR2_RESERVED_21_MASK          (0x200000U)
24887 #define DDRPHY_DX2GSR2_RESERVED_21_SHIFT         (21U)
24888 /*! RESERVED_21 - Reserved. Return zeroes on reads.
24889  */
24890 #define DDRPHY_DX2GSR2_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX2GSR2_RESERVED_21_MASK)
24891 #define DDRPHY_DX2GSR2_GSDQSCAL_MASK             (0x400000U)
24892 #define DDRPHY_DX2GSR2_GSDQSCAL_SHIFT            (22U)
24893 /*! GSDQSCAL - Read DQS Gating Status Calibration
24894  */
24895 #define DDRPHY_DX2GSR2_GSDQSCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX2GSR2_GSDQSCAL_MASK)
24896 #define DDRPHY_DX2GSR2_GSDQSPRD_MASK             (0xFF800000U)
24897 #define DDRPHY_DX2GSR2_GSDQSPRD_SHIFT            (23U)
24898 /*! GSDQSPRD - Read DQS gating Status Period
24899  */
24900 #define DDRPHY_DX2GSR2_GSDQSPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX2GSR2_GSDQSPRD_MASK)
24901 /*! @} */
24902 
24903 /*! @name DX2GSR3 - DATX8 n General Status Register 3 */
24904 /*! @{ */
24905 #define DDRPHY_DX2GSR3_SRDPC_MASK                (0x3U)
24906 #define DDRPHY_DX2GSR3_SRDPC_SHIFT               (0U)
24907 /*! SRDPC - Static Read Delay Pass Count
24908  */
24909 #define DDRPHY_DX2GSR3_SRDPC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_SRDPC_SHIFT)) & DDRPHY_DX2GSR3_SRDPC_MASK)
24910 #define DDRPHY_DX2GSR3_RESERVED_7_2_MASK         (0xFCU)
24911 #define DDRPHY_DX2GSR3_RESERVED_7_2_SHIFT        (2U)
24912 /*! RESERVED_7_2 - Reserved. Return zeroes on reads.
24913  */
24914 #define DDRPHY_DX2GSR3_RESERVED_7_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX2GSR3_RESERVED_7_2_MASK)
24915 #define DDRPHY_DX2GSR3_HVERR_MASK                (0xF00U)
24916 #define DDRPHY_DX2GSR3_HVERR_SHIFT               (8U)
24917 /*! HVERR - Host VREF Training Error
24918  */
24919 #define DDRPHY_DX2GSR3_HVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_HVERR_SHIFT)) & DDRPHY_DX2GSR3_HVERR_MASK)
24920 #define DDRPHY_DX2GSR3_HVWRN_MASK                (0xF000U)
24921 #define DDRPHY_DX2GSR3_HVWRN_SHIFT               (12U)
24922 /*! HVWRN - Host VREF Training Warning
24923  */
24924 #define DDRPHY_DX2GSR3_HVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_HVWRN_SHIFT)) & DDRPHY_DX2GSR3_HVWRN_MASK)
24925 #define DDRPHY_DX2GSR3_DVERR_MASK                (0xF0000U)
24926 #define DDRPHY_DX2GSR3_DVERR_SHIFT               (16U)
24927 /*! DVERR - DRAM VREF Training Error
24928  */
24929 #define DDRPHY_DX2GSR3_DVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_DVERR_SHIFT)) & DDRPHY_DX2GSR3_DVERR_MASK)
24930 #define DDRPHY_DX2GSR3_DVWRN_MASK                (0xF00000U)
24931 #define DDRPHY_DX2GSR3_DVWRN_SHIFT               (20U)
24932 /*! DVWRN - DRAM VREF Training Warning
24933  */
24934 #define DDRPHY_DX2GSR3_DVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_DVWRN_SHIFT)) & DDRPHY_DX2GSR3_DVWRN_MASK)
24935 #define DDRPHY_DX2GSR3_ESTAT_MASK                (0x7000000U)
24936 #define DDRPHY_DX2GSR3_ESTAT_SHIFT               (24U)
24937 /*! ESTAT - VREF Training Error Status Code
24938  */
24939 #define DDRPHY_DX2GSR3_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_ESTAT_SHIFT)) & DDRPHY_DX2GSR3_ESTAT_MASK)
24940 #define DDRPHY_DX2GSR3_RESERVED_31_27_MASK       (0xF8000000U)
24941 #define DDRPHY_DX2GSR3_RESERVED_31_27_SHIFT      (27U)
24942 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
24943  */
24944 #define DDRPHY_DX2GSR3_RESERVED_31_27(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX2GSR3_RESERVED_31_27_MASK)
24945 /*! @} */
24946 
24947 /*! @name DX2GSR4 - DATX8 n General Status Register 4 */
24948 /*! @{ */
24949 #define DDRPHY_DX2GSR4_RESERVED_0_MASK           (0x1U)
24950 #define DDRPHY_DX2GSR4_RESERVED_0_SHIFT          (0U)
24951 /*! RESERVED_0 - Reserved. Return zeroes on reads.
24952  */
24953 #define DDRPHY_DX2GSR4_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_0_MASK)
24954 #define DDRPHY_DX2GSR4_RESERVED_1_MASK           (0x2U)
24955 #define DDRPHY_DX2GSR4_RESERVED_1_SHIFT          (1U)
24956 /*! RESERVED_1 - Reserved. Return zeroes on reads.
24957  */
24958 #define DDRPHY_DX2GSR4_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_1_MASK)
24959 #define DDRPHY_DX2GSR4_RESERVED_2_MASK           (0x4U)
24960 #define DDRPHY_DX2GSR4_RESERVED_2_SHIFT          (2U)
24961 /*! RESERVED_2 - Reserved. Return zeroes on reads.
24962  */
24963 #define DDRPHY_DX2GSR4_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_2_MASK)
24964 #define DDRPHY_DX2GSR4_RESERVED_3_MASK           (0x8U)
24965 #define DDRPHY_DX2GSR4_RESERVED_3_SHIFT          (3U)
24966 /*! RESERVED_3 - Reserved. Return zeroes on reads.
24967  */
24968 #define DDRPHY_DX2GSR4_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_3_MASK)
24969 #define DDRPHY_DX2GSR4_RESERVED_4_MASK           (0x10U)
24970 #define DDRPHY_DX2GSR4_RESERVED_4_SHIFT          (4U)
24971 /*! RESERVED_4 - Reserved. Return zeroes on reads.
24972  */
24973 #define DDRPHY_DX2GSR4_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_4_MASK)
24974 #define DDRPHY_DX2GSR4_RESERVED_5_MASK           (0x20U)
24975 #define DDRPHY_DX2GSR4_RESERVED_5_SHIFT          (5U)
24976 /*! RESERVED_5 - Reserved. Return zeroes on reads.
24977  */
24978 #define DDRPHY_DX2GSR4_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_5_MASK)
24979 #define DDRPHY_DX2GSR4_RESERVED_6_MASK           (0x40U)
24980 #define DDRPHY_DX2GSR4_RESERVED_6_SHIFT          (6U)
24981 /*! RESERVED_6 - Reserved. Return zeroes on reads.
24982  */
24983 #define DDRPHY_DX2GSR4_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_6_MASK)
24984 #define DDRPHY_DX2GSR4_RESERVED_15_7_MASK        (0xFF80U)
24985 #define DDRPHY_DX2GSR4_RESERVED_15_7_SHIFT       (7U)
24986 /*! RESERVED_15_7 - Reserved. Return zeroes on reads.
24987  */
24988 #define DDRPHY_DX2GSR4_RESERVED_15_7(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_15_7_MASK)
24989 #define DDRPHY_DX2GSR4_RESERVED_16_MASK          (0x10000U)
24990 #define DDRPHY_DX2GSR4_RESERVED_16_SHIFT         (16U)
24991 /*! RESERVED_16 - Reserved. Return zeroes on reads.
24992  */
24993 #define DDRPHY_DX2GSR4_RESERVED_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_16_MASK)
24994 #define DDRPHY_DX2GSR4_RESERVED_25_17_MASK       (0x3FE0000U)
24995 #define DDRPHY_DX2GSR4_RESERVED_25_17_SHIFT      (17U)
24996 /*! RESERVED_25_17 - Reserved. Return zeroes on reads.
24997  */
24998 #define DDRPHY_DX2GSR4_RESERVED_25_17(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_25_17_MASK)
24999 #define DDRPHY_DX2GSR4_RESERVED_31_26_MASK       (0xFC000000U)
25000 #define DDRPHY_DX2GSR4_RESERVED_31_26_SHIFT      (26U)
25001 /*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
25002  */
25003 #define DDRPHY_DX2GSR4_RESERVED_31_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_31_26_MASK)
25004 /*! @} */
25005 
25006 /*! @name DX2GSR5 - DATX8 n General Status Register 5 */
25007 /*! @{ */
25008 #define DDRPHY_DX2GSR5_RESERVED_0_MASK           (0x1U)
25009 #define DDRPHY_DX2GSR5_RESERVED_0_SHIFT          (0U)
25010 /*! RESERVED_0 - Reserved. Return zeroes on reads.
25011  */
25012 #define DDRPHY_DX2GSR5_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_0_MASK)
25013 #define DDRPHY_DX2GSR5_RESERVED_1_MASK           (0x2U)
25014 #define DDRPHY_DX2GSR5_RESERVED_1_SHIFT          (1U)
25015 /*! RESERVED_1 - Reserved. Return zeroes on reads.
25016  */
25017 #define DDRPHY_DX2GSR5_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_1_MASK)
25018 #define DDRPHY_DX2GSR5_RESERVED_2_MASK           (0x4U)
25019 #define DDRPHY_DX2GSR5_RESERVED_2_SHIFT          (2U)
25020 /*! RESERVED_2 - Reserved. Return zeroes on reads.
25021  */
25022 #define DDRPHY_DX2GSR5_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_2_MASK)
25023 #define DDRPHY_DX2GSR5_RESERVED_3_MASK           (0x8U)
25024 #define DDRPHY_DX2GSR5_RESERVED_3_SHIFT          (3U)
25025 /*! RESERVED_3 - Reserved. Return zeroes on reads.
25026  */
25027 #define DDRPHY_DX2GSR5_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_3_MASK)
25028 #define DDRPHY_DX2GSR5_RESERVED_4_MASK           (0x10U)
25029 #define DDRPHY_DX2GSR5_RESERVED_4_SHIFT          (4U)
25030 /*! RESERVED_4 - Reserved. Return zeroes on reads.
25031  */
25032 #define DDRPHY_DX2GSR5_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_4_MASK)
25033 #define DDRPHY_DX2GSR5_RESERVED_5_MASK           (0x20U)
25034 #define DDRPHY_DX2GSR5_RESERVED_5_SHIFT          (5U)
25035 /*! RESERVED_5 - Reserved. Return zeroes on reads.
25036  */
25037 #define DDRPHY_DX2GSR5_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_5_MASK)
25038 #define DDRPHY_DX2GSR5_RESERVED_6_MASK           (0x40U)
25039 #define DDRPHY_DX2GSR5_RESERVED_6_SHIFT          (6U)
25040 /*! RESERVED_6 - Reserved. Return zeroes on reads.
25041  */
25042 #define DDRPHY_DX2GSR5_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_6_MASK)
25043 #define DDRPHY_DX2GSR5_RESERVED_7_MASK           (0x80U)
25044 #define DDRPHY_DX2GSR5_RESERVED_7_SHIFT          (7U)
25045 /*! RESERVED_7 - Reserved. Return zeroes on reads.
25046  */
25047 #define DDRPHY_DX2GSR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_7_MASK)
25048 #define DDRPHY_DX2GSR5_RESERVED_11_8_MASK        (0xF00U)
25049 #define DDRPHY_DX2GSR5_RESERVED_11_8_SHIFT       (8U)
25050 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
25051  */
25052 #define DDRPHY_DX2GSR5_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_11_8_MASK)
25053 #define DDRPHY_DX2GSR5_RESERVED_19_12_MASK       (0xFF000U)
25054 #define DDRPHY_DX2GSR5_RESERVED_19_12_SHIFT      (12U)
25055 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
25056  */
25057 #define DDRPHY_DX2GSR5_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_19_12_MASK)
25058 #define DDRPHY_DX2GSR5_RESERVED_20_MASK          (0x100000U)
25059 #define DDRPHY_DX2GSR5_RESERVED_20_SHIFT         (20U)
25060 /*! RESERVED_20 - Reserved. Return zeroes on reads.
25061  */
25062 #define DDRPHY_DX2GSR5_RESERVED_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_20_MASK)
25063 #define DDRPHY_DX2GSR5_RESERVED_21_MASK          (0x200000U)
25064 #define DDRPHY_DX2GSR5_RESERVED_21_SHIFT         (21U)
25065 /*! RESERVED_21 - Reserved. Return zeroes on reads.
25066  */
25067 #define DDRPHY_DX2GSR5_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_21_MASK)
25068 #define DDRPHY_DX2GSR5_RESERVED_22_MASK          (0x400000U)
25069 #define DDRPHY_DX2GSR5_RESERVED_22_SHIFT         (22U)
25070 /*! RESERVED_22 - Reserved. Return zeroes on reads.
25071  */
25072 #define DDRPHY_DX2GSR5_RESERVED_22(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_22_MASK)
25073 #define DDRPHY_DX2GSR5_RESERVED_31_23_MASK       (0xFF800000U)
25074 #define DDRPHY_DX2GSR5_RESERVED_31_23_SHIFT      (23U)
25075 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
25076  */
25077 #define DDRPHY_DX2GSR5_RESERVED_31_23(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_31_23_MASK)
25078 /*! @} */
25079 
25080 /*! @name DX2GSR6 - DATX8 n General Status Register 6 */
25081 /*! @{ */
25082 #define DDRPHY_DX2GSR6_RESERVED_1_0_MASK         (0x3U)
25083 #define DDRPHY_DX2GSR6_RESERVED_1_0_SHIFT        (0U)
25084 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
25085  */
25086 #define DDRPHY_DX2GSR6_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_1_0_MASK)
25087 #define DDRPHY_DX2GSR6_RESERVED_3_2_MASK         (0xCU)
25088 #define DDRPHY_DX2GSR6_RESERVED_3_2_SHIFT        (2U)
25089 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
25090  */
25091 #define DDRPHY_DX2GSR6_RESERVED_3_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_3_2_MASK)
25092 #define DDRPHY_DX2GSR6_RESERVED_7_4_MASK         (0xF0U)
25093 #define DDRPHY_DX2GSR6_RESERVED_7_4_SHIFT        (4U)
25094 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
25095  */
25096 #define DDRPHY_DX2GSR6_RESERVED_7_4(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_7_4_MASK)
25097 #define DDRPHY_DX2GSR6_RESERVED_11_8_MASK        (0xF00U)
25098 #define DDRPHY_DX2GSR6_RESERVED_11_8_SHIFT       (8U)
25099 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
25100  */
25101 #define DDRPHY_DX2GSR6_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_11_8_MASK)
25102 #define DDRPHY_DX2GSR6_RESERVED_15_12_MASK       (0xF000U)
25103 #define DDRPHY_DX2GSR6_RESERVED_15_12_SHIFT      (12U)
25104 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
25105  */
25106 #define DDRPHY_DX2GSR6_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_15_12_MASK)
25107 #define DDRPHY_DX2GSR6_RESERVED_19_15_MASK       (0xF0000U)
25108 #define DDRPHY_DX2GSR6_RESERVED_19_15_SHIFT      (16U)
25109 /*! RESERVED_19_15 - Reserved. Return zeroes on reads.
25110  */
25111 #define DDRPHY_DX2GSR6_RESERVED_19_15(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_19_15_MASK)
25112 #define DDRPHY_DX2GSR6_RESERVED_23_20_MASK       (0xF00000U)
25113 #define DDRPHY_DX2GSR6_RESERVED_23_20_SHIFT      (20U)
25114 /*! RESERVED_23_20 - Reserved. Return zeroes on reads.
25115  */
25116 #define DDRPHY_DX2GSR6_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_23_20_MASK)
25117 #define DDRPHY_DX2GSR6_RESERVED_31_24_MASK       (0xFF000000U)
25118 #define DDRPHY_DX2GSR6_RESERVED_31_24_SHIFT      (24U)
25119 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
25120  */
25121 #define DDRPHY_DX2GSR6_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_31_24_MASK)
25122 /*! @} */
25123 
25124 /*! @name DX3GCR0 - DATX8 n General Configuration Register 0 */
25125 /*! @{ */
25126 #define DDRPHY_DX3GCR0_RESERVED_1_0_MASK         (0x3U)
25127 #define DDRPHY_DX3GCR0_RESERVED_1_0_SHIFT        (0U)
25128 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
25129  */
25130 #define DDRPHY_DX3GCR0_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX3GCR0_RESERVED_1_0_MASK)
25131 #define DDRPHY_DX3GCR0_DQSGOE_MASK               (0x4U)
25132 #define DDRPHY_DX3GCR0_DQSGOE_SHIFT              (2U)
25133 /*! DQSGOE - DQSG Output Enable
25134  */
25135 #define DDRPHY_DX3GCR0_DQSGOE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSGOE_SHIFT)) & DDRPHY_DX3GCR0_DQSGOE_MASK)
25136 #define DDRPHY_DX3GCR0_DQSGODT_MASK              (0x8U)
25137 #define DDRPHY_DX3GCR0_DQSGODT_SHIFT             (3U)
25138 /*! DQSGODT - DQSG On-Die Termination
25139  */
25140 #define DDRPHY_DX3GCR0_DQSGODT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSGODT_SHIFT)) & DDRPHY_DX3GCR0_DQSGODT_MASK)
25141 #define DDRPHY_DX3GCR0_RESERVED_4_MASK           (0x10U)
25142 #define DDRPHY_DX3GCR0_RESERVED_4_SHIFT          (4U)
25143 /*! RESERVED_4 - Reserved. Return zeroes on reads.
25144  */
25145 #define DDRPHY_DX3GCR0_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX3GCR0_RESERVED_4_MASK)
25146 #define DDRPHY_DX3GCR0_DQSGPDR_MASK              (0x20U)
25147 #define DDRPHY_DX3GCR0_DQSGPDR_SHIFT             (5U)
25148 /*! DQSGPDR - DQSG Power Down Receiver
25149  */
25150 #define DDRPHY_DX3GCR0_DQSGPDR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX3GCR0_DQSGPDR_MASK)
25151 #define DDRPHY_DX3GCR0_DQSRPD_MASK               (0x40U)
25152 #define DDRPHY_DX3GCR0_DQSRPD_SHIFT              (6U)
25153 /*! DQSRPD - DQSR Power Down
25154  */
25155 #define DDRPHY_DX3GCR0_DQSRPD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSRPD_SHIFT)) & DDRPHY_DX3GCR0_DQSRPD_MASK)
25156 #define DDRPHY_DX3GCR0_CPDRSHFT_MASK             (0x180U)
25157 #define DDRPHY_DX3GCR0_CPDRSHFT_SHIFT            (7U)
25158 /*! CPDRSHFT - Configurable PDR Phase Shift
25159  */
25160 #define DDRPHY_DX3GCR0_CPDRSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX3GCR0_CPDRSHFT_MASK)
25161 #define DDRPHY_DX3GCR0_RTTOH_MASK                (0x600U)
25162 #define DDRPHY_DX3GCR0_RTTOH_SHIFT               (9U)
25163 /*! RTTOH - RTT Output Hold
25164  */
25165 #define DDRPHY_DX3GCR0_RTTOH(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RTTOH_SHIFT)) & DDRPHY_DX3GCR0_RTTOH_MASK)
25166 #define DDRPHY_DX3GCR0_RTTOAL_MASK               (0x800U)
25167 #define DDRPHY_DX3GCR0_RTTOAL_SHIFT              (11U)
25168 /*! RTTOAL - RTT On Additive Latency
25169  */
25170 #define DDRPHY_DX3GCR0_RTTOAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RTTOAL_SHIFT)) & DDRPHY_DX3GCR0_RTTOAL_MASK)
25171 #define DDRPHY_DX3GCR0_DQSSEPDR_MASK             (0x1000U)
25172 #define DDRPHY_DX3GCR0_DQSSEPDR_SHIFT            (12U)
25173 /*! DQSSEPDR - DQSSE Power Down Receiver
25174  */
25175 #define DDRPHY_DX3GCR0_DQSSEPDR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX3GCR0_DQSSEPDR_MASK)
25176 #define DDRPHY_DX3GCR0_DQSNSEPDR_MASK            (0x2000U)
25177 #define DDRPHY_DX3GCR0_DQSNSEPDR_SHIFT           (13U)
25178 /*! DQSNSEPDR - DQSNSE Power Down Receiver
25179  */
25180 #define DDRPHY_DX3GCR0_DQSNSEPDR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX3GCR0_DQSNSEPDR_MASK)
25181 #define DDRPHY_DX3GCR0_RESERVED_19_14_MASK       (0xFC000U)
25182 #define DDRPHY_DX3GCR0_RESERVED_19_14_SHIFT      (14U)
25183 /*! RESERVED_19_14 - Reserved. Return zeroes on reads.
25184  */
25185 #define DDRPHY_DX3GCR0_RESERVED_19_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX3GCR0_RESERVED_19_14_MASK)
25186 #define DDRPHY_DX3GCR0_RDDLY_MASK                (0xF00000U)
25187 #define DDRPHY_DX3GCR0_RDDLY_SHIFT               (20U)
25188 /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
25189  */
25190 #define DDRPHY_DX3GCR0_RDDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RDDLY_SHIFT)) & DDRPHY_DX3GCR0_RDDLY_MASK)
25191 #define DDRPHY_DX3GCR0_DQSDCC_MASK               (0xF000000U)
25192 #define DDRPHY_DX3GCR0_DQSDCC_SHIFT              (24U)
25193 /*! DQSDCC - DQS Duty Cycle Correction
25194  */
25195 #define DDRPHY_DX3GCR0_DQSDCC(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSDCC_SHIFT)) & DDRPHY_DX3GCR0_DQSDCC_MASK)
25196 #define DDRPHY_DX3GCR0_CODTSHFT_MASK             (0x30000000U)
25197 #define DDRPHY_DX3GCR0_CODTSHFT_SHIFT            (28U)
25198 /*! CODTSHFT - Configurable ODT(TE) Phase Shift
25199  */
25200 #define DDRPHY_DX3GCR0_CODTSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX3GCR0_CODTSHFT_MASK)
25201 #define DDRPHY_DX3GCR0_MDLEN_MASK                (0x40000000U)
25202 #define DDRPHY_DX3GCR0_MDLEN_SHIFT               (30U)
25203 /*! MDLEN - Master Delay Line Enable
25204  */
25205 #define DDRPHY_DX3GCR0_MDLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_MDLEN_SHIFT)) & DDRPHY_DX3GCR0_MDLEN_MASK)
25206 #define DDRPHY_DX3GCR0_CALBYP_MASK               (0x80000000U)
25207 #define DDRPHY_DX3GCR0_CALBYP_SHIFT              (31U)
25208 /*! CALBYP - Calibration Bypass
25209  */
25210 #define DDRPHY_DX3GCR0_CALBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_CALBYP_SHIFT)) & DDRPHY_DX3GCR0_CALBYP_MASK)
25211 /*! @} */
25212 
25213 /*! @name DX3GCR1 - DATX8 n General Configuration Register 1 */
25214 /*! @{ */
25215 #define DDRPHY_DX3GCR1_DQEN_MASK                 (0xFFU)
25216 #define DDRPHY_DX3GCR1_DQEN_SHIFT                (0U)
25217 /*! DQEN - Enables DQ corresponding to each bit in a byte
25218  */
25219 #define DDRPHY_DX3GCR1_DQEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DQEN_SHIFT)) & DDRPHY_DX3GCR1_DQEN_MASK)
25220 #define DDRPHY_DX3GCR1_DMEN_MASK                 (0x100U)
25221 #define DDRPHY_DX3GCR1_DMEN_SHIFT                (8U)
25222 /*! DMEN - Enables DM pin in a byte lane
25223  */
25224 #define DDRPHY_DX3GCR1_DMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DMEN_SHIFT)) & DDRPHY_DX3GCR1_DMEN_MASK)
25225 #define DDRPHY_DX3GCR1_DSEN_MASK                 (0x200U)
25226 #define DDRPHY_DX3GCR1_DSEN_SHIFT                (9U)
25227 /*! DSEN - Enables Write Data strobe in a byte lane
25228  */
25229 #define DDRPHY_DX3GCR1_DSEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DSEN_SHIFT)) & DDRPHY_DX3GCR1_DSEN_MASK)
25230 #define DDRPHY_DX3GCR1_TEEN_MASK                 (0x400U)
25231 #define DDRPHY_DX3GCR1_TEEN_SHIFT                (10U)
25232 /*! TEEN - Enables ODT/TE in a byte lane
25233  */
25234 #define DDRPHY_DX3GCR1_TEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_TEEN_SHIFT)) & DDRPHY_DX3GCR1_TEEN_MASK)
25235 #define DDRPHY_DX3GCR1_PDREN_MASK                (0x800U)
25236 #define DDRPHY_DX3GCR1_PDREN_SHIFT               (11U)
25237 /*! PDREN - Enables PDR in a byte lane
25238  */
25239 #define DDRPHY_DX3GCR1_PDREN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_PDREN_SHIFT)) & DDRPHY_DX3GCR1_PDREN_MASK)
25240 #define DDRPHY_DX3GCR1_OEEN_MASK                 (0x1000U)
25241 #define DDRPHY_DX3GCR1_OEEN_SHIFT                (12U)
25242 /*! OEEN - Enables Read Data Strobe in a byte lane
25243  */
25244 #define DDRPHY_DX3GCR1_OEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_OEEN_SHIFT)) & DDRPHY_DX3GCR1_OEEN_MASK)
25245 #define DDRPHY_DX3GCR1_QSSEL_MASK                (0x2000U)
25246 #define DDRPHY_DX3GCR1_QSSEL_SHIFT               (13U)
25247 /*! QSSEL - Select the delayed or non-delayed read data strobe
25248  */
25249 #define DDRPHY_DX3GCR1_QSSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_QSSEL_SHIFT)) & DDRPHY_DX3GCR1_QSSEL_MASK)
25250 #define DDRPHY_DX3GCR1_QSNSEL_MASK               (0x4000U)
25251 #define DDRPHY_DX3GCR1_QSNSEL_SHIFT              (14U)
25252 /*! QSNSEL - Select the delayed or non-delayed read data strobe #
25253  */
25254 #define DDRPHY_DX3GCR1_QSNSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_QSNSEL_SHIFT)) & DDRPHY_DX3GCR1_QSNSEL_MASK)
25255 #define DDRPHY_DX3GCR1_RESERVED_15_MASK          (0x8000U)
25256 #define DDRPHY_DX3GCR1_RESERVED_15_SHIFT         (15U)
25257 /*! RESERVED_15 - Reserved. Returns zeroes on reads.
25258  */
25259 #define DDRPHY_DX3GCR1_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX3GCR1_RESERVED_15_MASK)
25260 #define DDRPHY_DX3GCR1_DXPDRMODE_MASK            (0xFFFF0000U)
25261 #define DDRPHY_DX3GCR1_DXPDRMODE_SHIFT           (16U)
25262 /*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
25263  */
25264 #define DDRPHY_DX3GCR1_DXPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX3GCR1_DXPDRMODE_MASK)
25265 /*! @} */
25266 
25267 /*! @name DX3GCR2 - DATX8 n General Configuration Register 2 */
25268 /*! @{ */
25269 #define DDRPHY_DX3GCR2_DXTEMODE_MASK             (0xFFFFU)
25270 #define DDRPHY_DX3GCR2_DXTEMODE_SHIFT            (0U)
25271 /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
25272  */
25273 #define DDRPHY_DX3GCR2_DXTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX3GCR2_DXTEMODE_MASK)
25274 #define DDRPHY_DX3GCR2_DXOEMODE_MASK             (0xFFFF0000U)
25275 #define DDRPHY_DX3GCR2_DXOEMODE_SHIFT            (16U)
25276 /*! DXOEMODE - Enables the OE mode values for DQ[7:0]
25277  */
25278 #define DDRPHY_DX3GCR2_DXOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX3GCR2_DXOEMODE_MASK)
25279 /*! @} */
25280 
25281 /*! @name DX3GCR3 - DATX8 n General Configuration Register 3 */
25282 /*! @{ */
25283 #define DDRPHY_DX3GCR3_WDMBVT_MASK               (0x1U)
25284 #define DDRPHY_DX3GCR3_WDMBVT_SHIFT              (0U)
25285 /*! WDMBVT - Write Data Mask BDL VT Compensation
25286  */
25287 #define DDRPHY_DX3GCR3_WDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDMBVT_SHIFT)) & DDRPHY_DX3GCR3_WDMBVT_MASK)
25288 #define DDRPHY_DX3GCR3_RDMBVT_MASK               (0x2U)
25289 #define DDRPHY_DX3GCR3_RDMBVT_SHIFT              (1U)
25290 /*! RDMBVT - Read Data Mask BDL VT Compensation
25291  */
25292 #define DDRPHY_DX3GCR3_RDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RDMBVT_SHIFT)) & DDRPHY_DX3GCR3_RDMBVT_MASK)
25293 #define DDRPHY_DX3GCR3_DSPDRMODE_MASK            (0xCU)
25294 #define DDRPHY_DX3GCR3_DSPDRMODE_SHIFT           (2U)
25295 /*! DSPDRMODE - Enables the PDR mode values for DQS.
25296  */
25297 #define DDRPHY_DX3GCR3_DSPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX3GCR3_DSPDRMODE_MASK)
25298 #define DDRPHY_DX3GCR3_DSTEMODE_MASK             (0x30U)
25299 #define DDRPHY_DX3GCR3_DSTEMODE_SHIFT            (4U)
25300 /*! DSTEMODE - Enables the TE mode values for DQS.
25301  */
25302 #define DDRPHY_DX3GCR3_DSTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSTEMODE_MASK)
25303 #define DDRPHY_DX3GCR3_DSOEMODE_MASK             (0xC0U)
25304 #define DDRPHY_DX3GCR3_DSOEMODE_SHIFT            (6U)
25305 /*! DSOEMODE - Enables the OE mode values for DQS.
25306  */
25307 #define DDRPHY_DX3GCR3_DSOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSOEMODE_MASK)
25308 #define DDRPHY_DX3GCR3_WDSBVT_MASK               (0x100U)
25309 #define DDRPHY_DX3GCR3_WDSBVT_SHIFT              (8U)
25310 /*! WDSBVT - Write Data Strobe BDL VT Compensation
25311  */
25312 #define DDRPHY_DX3GCR3_WDSBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDSBVT_SHIFT)) & DDRPHY_DX3GCR3_WDSBVT_MASK)
25313 #define DDRPHY_DX3GCR3_RESERVED_9_MASK           (0x200U)
25314 #define DDRPHY_DX3GCR3_RESERVED_9_SHIFT          (9U)
25315 /*! RESERVED_9 - Reserved. Returns zeroes on reads.
25316  */
25317 #define DDRPHY_DX3GCR3_RESERVED_9(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX3GCR3_RESERVED_9_MASK)
25318 #define DDRPHY_DX3GCR3_DMPDRMODE_MASK            (0xC00U)
25319 #define DDRPHY_DX3GCR3_DMPDRMODE_SHIFT           (10U)
25320 /*! DMPDRMODE - Enables the PDR mode values for DM.
25321  */
25322 #define DDRPHY_DX3GCR3_DMPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX3GCR3_DMPDRMODE_MASK)
25323 #define DDRPHY_DX3GCR3_DMTEMODE_MASK             (0x3000U)
25324 #define DDRPHY_DX3GCR3_DMTEMODE_SHIFT            (12U)
25325 /*! DMTEMODE - Enables the TE mode values for DM.
25326  */
25327 #define DDRPHY_DX3GCR3_DMTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX3GCR3_DMTEMODE_MASK)
25328 #define DDRPHY_DX3GCR3_DMOEMODE_MASK             (0xC000U)
25329 #define DDRPHY_DX3GCR3_DMOEMODE_SHIFT            (14U)
25330 /*! DMOEMODE - Enables the OE mode values for DM.
25331  */
25332 #define DDRPHY_DX3GCR3_DMOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX3GCR3_DMOEMODE_MASK)
25333 #define DDRPHY_DX3GCR3_DSNPDRMODE_MASK           (0x30000U)
25334 #define DDRPHY_DX3GCR3_DSNPDRMODE_SHIFT          (16U)
25335 /*! DSNPDRMODE - Enables the PDR mode for DQS
25336  */
25337 #define DDRPHY_DX3GCR3_DSNPDRMODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX3GCR3_DSNPDRMODE_MASK)
25338 #define DDRPHY_DX3GCR3_DSNTEMODE_MASK            (0xC0000U)
25339 #define DDRPHY_DX3GCR3_DSNTEMODE_SHIFT           (18U)
25340 /*! DSNTEMODE - Enables the TE mode for DQS
25341  */
25342 #define DDRPHY_DX3GCR3_DSNTEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSNTEMODE_MASK)
25343 #define DDRPHY_DX3GCR3_DSNOEMODE_MASK            (0x300000U)
25344 #define DDRPHY_DX3GCR3_DSNOEMODE_SHIFT           (20U)
25345 /*! DSNOEMODE - Enables the OE mode for DQs
25346  */
25347 #define DDRPHY_DX3GCR3_DSNOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSNOEMODE_MASK)
25348 #define DDRPHY_DX3GCR3_PDRBVT_MASK               (0x400000U)
25349 #define DDRPHY_DX3GCR3_PDRBVT_SHIFT              (22U)
25350 /*! PDRBVT - Power Down Receiver BDL VT Compensation
25351  */
25352 #define DDRPHY_DX3GCR3_PDRBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_PDRBVT_SHIFT)) & DDRPHY_DX3GCR3_PDRBVT_MASK)
25353 #define DDRPHY_DX3GCR3_RGSLVT_MASK               (0x800000U)
25354 #define DDRPHY_DX3GCR3_RGSLVT_SHIFT              (23U)
25355 /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
25356  */
25357 #define DDRPHY_DX3GCR3_RGSLVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RGSLVT_SHIFT)) & DDRPHY_DX3GCR3_RGSLVT_MASK)
25358 #define DDRPHY_DX3GCR3_WLLVT_MASK                (0x1000000U)
25359 #define DDRPHY_DX3GCR3_WLLVT_SHIFT               (24U)
25360 /*! WLLVT - Write Leveling LCDL Delay VT Compensation
25361  */
25362 #define DDRPHY_DX3GCR3_WLLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WLLVT_SHIFT)) & DDRPHY_DX3GCR3_WLLVT_MASK)
25363 #define DDRPHY_DX3GCR3_WDLVT_MASK                (0x2000000U)
25364 #define DDRPHY_DX3GCR3_WDLVT_SHIFT               (25U)
25365 /*! WDLVT - Write DQ LCDL Delay VT Compensation
25366  */
25367 #define DDRPHY_DX3GCR3_WDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDLVT_SHIFT)) & DDRPHY_DX3GCR3_WDLVT_MASK)
25368 #define DDRPHY_DX3GCR3_RDLVT_MASK                (0x4000000U)
25369 #define DDRPHY_DX3GCR3_RDLVT_SHIFT               (26U)
25370 /*! RDLVT - Read DQS LCDL Delay VT Compensation
25371  */
25372 #define DDRPHY_DX3GCR3_RDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RDLVT_SHIFT)) & DDRPHY_DX3GCR3_RDLVT_MASK)
25373 #define DDRPHY_DX3GCR3_RGLVT_MASK                (0x8000000U)
25374 #define DDRPHY_DX3GCR3_RGLVT_SHIFT               (27U)
25375 /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
25376  */
25377 #define DDRPHY_DX3GCR3_RGLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RGLVT_SHIFT)) & DDRPHY_DX3GCR3_RGLVT_MASK)
25378 #define DDRPHY_DX3GCR3_WDBVT_MASK                (0x10000000U)
25379 #define DDRPHY_DX3GCR3_WDBVT_SHIFT               (28U)
25380 /*! WDBVT - Write Data BDL VT Compensation
25381  */
25382 #define DDRPHY_DX3GCR3_WDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDBVT_SHIFT)) & DDRPHY_DX3GCR3_WDBVT_MASK)
25383 #define DDRPHY_DX3GCR3_RDBVT_MASK                (0x20000000U)
25384 #define DDRPHY_DX3GCR3_RDBVT_SHIFT               (29U)
25385 /*! RDBVT - Read Data BDL VT Compensation
25386  */
25387 #define DDRPHY_DX3GCR3_RDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RDBVT_SHIFT)) & DDRPHY_DX3GCR3_RDBVT_MASK)
25388 #define DDRPHY_DX3GCR3_TEBVT_MASK                (0x40000000U)
25389 #define DDRPHY_DX3GCR3_TEBVT_SHIFT               (30U)
25390 /*! TEBVT - Termination Enable BDL VT Compensation
25391  */
25392 #define DDRPHY_DX3GCR3_TEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_TEBVT_SHIFT)) & DDRPHY_DX3GCR3_TEBVT_MASK)
25393 #define DDRPHY_DX3GCR3_OEBVT_MASK                (0x80000000U)
25394 #define DDRPHY_DX3GCR3_OEBVT_SHIFT               (31U)
25395 /*! OEBVT - Output Enable BDL VT Compensation
25396  */
25397 #define DDRPHY_DX3GCR3_OEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_OEBVT_SHIFT)) & DDRPHY_DX3GCR3_OEBVT_MASK)
25398 /*! @} */
25399 
25400 /*! @name DX3GCR4 - DATX8 n General Configuration Register 4 */
25401 /*! @{ */
25402 #define DDRPHY_DX3GCR4_DXREFIMON_MASK            (0x3U)
25403 #define DDRPHY_DX3GCR4_DXREFIMON_SHIFT           (0U)
25404 /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
25405  */
25406 #define DDRPHY_DX3GCR4_DXREFIMON(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX3GCR4_DXREFIMON_MASK)
25407 #define DDRPHY_DX3GCR4_DXREFIEN_MASK             (0x3CU)
25408 #define DDRPHY_DX3GCR4_DXREFIEN_SHIFT            (2U)
25409 /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
25410  */
25411 #define DDRPHY_DX3GCR4_DXREFIEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFIEN_MASK)
25412 #define DDRPHY_DX3GCR4_RESERVED_7_6_MASK         (0xC0U)
25413 #define DDRPHY_DX3GCR4_RESERVED_7_6_SHIFT        (6U)
25414 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
25415  */
25416 #define DDRPHY_DX3GCR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR4_RESERVED_7_6_MASK)
25417 #define DDRPHY_DX3GCR4_DXREFSSEL_MASK            (0x7F00U)
25418 #define DDRPHY_DX3GCR4_DXREFSSEL_SHIFT           (8U)
25419 /*! DXREFSSEL - Byte Lane Single-End VREF Select
25420  */
25421 #define DDRPHY_DX3GCR4_DXREFSSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX3GCR4_DXREFSSEL_MASK)
25422 #define DDRPHY_DX3GCR4_DXREFSSELRANGE_MASK       (0x8000U)
25423 #define DDRPHY_DX3GCR4_DXREFSSELRANGE_SHIFT      (15U)
25424 /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
25425  */
25426 #define DDRPHY_DX3GCR4_DXREFSSELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX3GCR4_DXREFSSELRANGE_MASK)
25427 #define DDRPHY_DX3GCR4_DXREFESEL_MASK            (0x7F0000U)
25428 #define DDRPHY_DX3GCR4_DXREFESEL_SHIFT           (16U)
25429 /*! DXREFESEL - Byte Lane External VREF Select
25430  */
25431 #define DDRPHY_DX3GCR4_DXREFESEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX3GCR4_DXREFESEL_MASK)
25432 #define DDRPHY_DX3GCR4_DXREFESELRANGE_MASK       (0x800000U)
25433 #define DDRPHY_DX3GCR4_DXREFESELRANGE_SHIFT      (23U)
25434 /*! DXREFESELRANGE - External VREF generator REFSEL range select
25435  */
25436 #define DDRPHY_DX3GCR4_DXREFESELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX3GCR4_DXREFESELRANGE_MASK)
25437 #define DDRPHY_DX3GCR4_RESERVED_24_MASK          (0x1000000U)
25438 #define DDRPHY_DX3GCR4_RESERVED_24_SHIFT         (24U)
25439 /*! RESERVED_24 - Reserved. Returns zeros on reads.
25440  */
25441 #define DDRPHY_DX3GCR4_RESERVED_24(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX3GCR4_RESERVED_24_MASK)
25442 #define DDRPHY_DX3GCR4_DXREFSEN_MASK             (0x2000000U)
25443 #define DDRPHY_DX3GCR4_DXREFSEN_SHIFT            (25U)
25444 /*! DXREFSEN - Byte Lane Single-End VREF Enable
25445  */
25446 #define DDRPHY_DX3GCR4_DXREFSEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFSEN_MASK)
25447 #define DDRPHY_DX3GCR4_DXREFEEN_MASK             (0xC000000U)
25448 #define DDRPHY_DX3GCR4_DXREFEEN_SHIFT            (26U)
25449 /*! DXREFEEN - Byte Lane Internal VREF Enable
25450  */
25451 #define DDRPHY_DX3GCR4_DXREFEEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFEEN_MASK)
25452 #define DDRPHY_DX3GCR4_DXREFPEN_MASK             (0x10000000U)
25453 #define DDRPHY_DX3GCR4_DXREFPEN_SHIFT            (28U)
25454 /*! DXREFPEN - Byte Lane VREF Pad Enable
25455  */
25456 #define DDRPHY_DX3GCR4_DXREFPEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFPEN_MASK)
25457 #define DDRPHY_DX3GCR4_RESERVED_31_29_MASK       (0xE0000000U)
25458 #define DDRPHY_DX3GCR4_RESERVED_31_29_SHIFT      (29U)
25459 /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
25460  */
25461 #define DDRPHY_DX3GCR4_RESERVED_31_29(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX3GCR4_RESERVED_31_29_MASK)
25462 /*! @} */
25463 
25464 /*! @name DX3GCR5 - DATX8 n General Configuration Register 5 */
25465 /*! @{ */
25466 #define DDRPHY_DX3GCR5_DXREFISELR0_MASK          (0x7FU)
25467 #define DDRPHY_DX3GCR5_DXREFISELR0_SHIFT         (0U)
25468 /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
25469  */
25470 #define DDRPHY_DX3GCR5_DXREFISELR0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR0_MASK)
25471 #define DDRPHY_DX3GCR5_RESERVED_7_MASK           (0x80U)
25472 #define DDRPHY_DX3GCR5_RESERVED_7_SHIFT          (7U)
25473 /*! RESERVED_7 - Reserved. Returns zeros on reads.
25474  */
25475 #define DDRPHY_DX3GCR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_7_MASK)
25476 #define DDRPHY_DX3GCR5_DXREFISELR1_MASK          (0x7F00U)
25477 #define DDRPHY_DX3GCR5_DXREFISELR1_SHIFT         (8U)
25478 /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
25479  */
25480 #define DDRPHY_DX3GCR5_DXREFISELR1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR1_MASK)
25481 #define DDRPHY_DX3GCR5_RESERVED_15_MASK          (0x8000U)
25482 #define DDRPHY_DX3GCR5_RESERVED_15_SHIFT         (15U)
25483 /*! RESERVED_15 - Reserved. Returns zeros on reads.
25484  */
25485 #define DDRPHY_DX3GCR5_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_15_MASK)
25486 #define DDRPHY_DX3GCR5_DXREFISELR2_MASK          (0x7F0000U)
25487 #define DDRPHY_DX3GCR5_DXREFISELR2_SHIFT         (16U)
25488 /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
25489  */
25490 #define DDRPHY_DX3GCR5_DXREFISELR2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR2_MASK)
25491 #define DDRPHY_DX3GCR5_RESERVED_23_MASK          (0x800000U)
25492 #define DDRPHY_DX3GCR5_RESERVED_23_SHIFT         (23U)
25493 /*! RESERVED_23 - Reserved. Returns zeros on reads.
25494  */
25495 #define DDRPHY_DX3GCR5_RESERVED_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_23_MASK)
25496 #define DDRPHY_DX3GCR5_DXREFISELR3_MASK          (0x7F000000U)
25497 #define DDRPHY_DX3GCR5_DXREFISELR3_SHIFT         (24U)
25498 /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
25499  */
25500 #define DDRPHY_DX3GCR5_DXREFISELR3(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR3_MASK)
25501 #define DDRPHY_DX3GCR5_RESERVED_31_MASK          (0x80000000U)
25502 #define DDRPHY_DX3GCR5_RESERVED_31_SHIFT         (31U)
25503 /*! RESERVED_31 - Reserved. Returns zeros on reads.
25504  */
25505 #define DDRPHY_DX3GCR5_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_31_MASK)
25506 /*! @} */
25507 
25508 /*! @name DX3GCR6 - DATX8 n General Configuration Register 6 */
25509 /*! @{ */
25510 #define DDRPHY_DX3GCR6_DXDQVREFR0_MASK           (0x3FU)
25511 #define DDRPHY_DX3GCR6_DXDQVREFR0_SHIFT          (0U)
25512 /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
25513  */
25514 #define DDRPHY_DX3GCR6_DXDQVREFR0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR0_MASK)
25515 #define DDRPHY_DX3GCR6_RESERVED_7_6_MASK         (0xC0U)
25516 #define DDRPHY_DX3GCR6_RESERVED_7_6_SHIFT        (6U)
25517 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
25518  */
25519 #define DDRPHY_DX3GCR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_7_6_MASK)
25520 #define DDRPHY_DX3GCR6_DXDQVREFR1_MASK           (0x3F00U)
25521 #define DDRPHY_DX3GCR6_DXDQVREFR1_SHIFT          (8U)
25522 /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
25523  */
25524 #define DDRPHY_DX3GCR6_DXDQVREFR1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR1_MASK)
25525 #define DDRPHY_DX3GCR6_RESERVED_15_14_MASK       (0xC000U)
25526 #define DDRPHY_DX3GCR6_RESERVED_15_14_SHIFT      (14U)
25527 /*! RESERVED_15_14 - Reserved. Returns zeros on reads.
25528  */
25529 #define DDRPHY_DX3GCR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_15_14_MASK)
25530 #define DDRPHY_DX3GCR6_DXDQVREFR2_MASK           (0x3F0000U)
25531 #define DDRPHY_DX3GCR6_DXDQVREFR2_SHIFT          (16U)
25532 /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
25533  */
25534 #define DDRPHY_DX3GCR6_DXDQVREFR2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR2_MASK)
25535 #define DDRPHY_DX3GCR6_RESERVED_23_22_MASK       (0xC00000U)
25536 #define DDRPHY_DX3GCR6_RESERVED_23_22_SHIFT      (22U)
25537 /*! RESERVED_23_22 - Reserved. Returns zeros on reads.
25538  */
25539 #define DDRPHY_DX3GCR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_23_22_MASK)
25540 #define DDRPHY_DX3GCR6_DXDQVREFR3_MASK           (0x3F000000U)
25541 #define DDRPHY_DX3GCR6_DXDQVREFR3_SHIFT          (24U)
25542 /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
25543  */
25544 #define DDRPHY_DX3GCR6_DXDQVREFR3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR3_MASK)
25545 #define DDRPHY_DX3GCR6_RESERVED_31_30_MASK       (0xC0000000U)
25546 #define DDRPHY_DX3GCR6_RESERVED_31_30_SHIFT      (30U)
25547 /*! RESERVED_31_30 - Reserved. Returns zeros on reads.
25548  */
25549 #define DDRPHY_DX3GCR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_31_30_MASK)
25550 /*! @} */
25551 
25552 /*! @name DX3GCR7 - DATX8 n General Configuration Register 7 */
25553 /*! @{ */
25554 #define DDRPHY_DX3GCR7_DCALSVAL_MASK             (0x1FFU)
25555 #define DDRPHY_DX3GCR7_DCALSVAL_SHIFT            (0U)
25556 /*! DCALSVAL - DDL Calibration Starting Value
25557  */
25558 #define DDRPHY_DX3GCR7_DCALSVAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX3GCR7_DCALSVAL_MASK)
25559 #define DDRPHY_DX3GCR7_DCALTYPE_MASK             (0x200U)
25560 #define DDRPHY_DX3GCR7_DCALTYPE_SHIFT            (9U)
25561 /*! DCALTYPE - DDL Calibration Type
25562  */
25563 #define DDRPHY_DX3GCR7_DCALTYPE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX3GCR7_DCALTYPE_MASK)
25564 #define DDRPHY_DX3GCR7_RESERVED_17_10_MASK       (0x3FC00U)
25565 #define DDRPHY_DX3GCR7_RESERVED_17_10_SHIFT      (10U)
25566 /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
25567  */
25568 #define DDRPHY_DX3GCR7_RESERVED_17_10(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX3GCR7_RESERVED_17_10_MASK)
25569 #define DDRPHY_DX3GCR7_RESERVED_18_MASK          (0x40000U)
25570 #define DDRPHY_DX3GCR7_RESERVED_18_SHIFT         (18U)
25571 /*! RESERVED_18 - Reserved. Caution, do not write to this register field.
25572  */
25573 #define DDRPHY_DX3GCR7_RESERVED_18(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX3GCR7_RESERVED_18_MASK)
25574 #define DDRPHY_DX3GCR7_RESERVED_31_19_MASK       (0xFFF80000U)
25575 #define DDRPHY_DX3GCR7_RESERVED_31_19_SHIFT      (19U)
25576 /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
25577  */
25578 #define DDRPHY_DX3GCR7_RESERVED_31_19(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX3GCR7_RESERVED_31_19_MASK)
25579 /*! @} */
25580 
25581 /*! @name DX3GCR8 - DATX8 n General Configuration Register 8 */
25582 /*! @{ */
25583 #define DDRPHY_DX3GCR8_RESERVED_5_0_MASK         (0x3FU)
25584 #define DDRPHY_DX3GCR8_RESERVED_5_0_SHIFT        (0U)
25585 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
25586  */
25587 #define DDRPHY_DX3GCR8_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_5_0_MASK)
25588 #define DDRPHY_DX3GCR8_RESERVED_7_6_MASK         (0xC0U)
25589 #define DDRPHY_DX3GCR8_RESERVED_7_6_SHIFT        (6U)
25590 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25591  */
25592 #define DDRPHY_DX3GCR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_7_6_MASK)
25593 #define DDRPHY_DX3GCR8_RESERVED_13_8_MASK        (0x3F00U)
25594 #define DDRPHY_DX3GCR8_RESERVED_13_8_SHIFT       (8U)
25595 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
25596  */
25597 #define DDRPHY_DX3GCR8_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_13_8_MASK)
25598 #define DDRPHY_DX3GCR8_RESERVED_15_14_MASK       (0xC000U)
25599 #define DDRPHY_DX3GCR8_RESERVED_15_14_SHIFT      (14U)
25600 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25601  */
25602 #define DDRPHY_DX3GCR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_15_14_MASK)
25603 #define DDRPHY_DX3GCR8_RESERVED_21_16_MASK       (0x3F0000U)
25604 #define DDRPHY_DX3GCR8_RESERVED_21_16_SHIFT      (16U)
25605 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
25606  */
25607 #define DDRPHY_DX3GCR8_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_21_16_MASK)
25608 #define DDRPHY_DX3GCR8_RESERVED_23_22_MASK       (0xC00000U)
25609 #define DDRPHY_DX3GCR8_RESERVED_23_22_SHIFT      (22U)
25610 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25611  */
25612 #define DDRPHY_DX3GCR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_23_22_MASK)
25613 #define DDRPHY_DX3GCR8_RESERVED_29_24_MASK       (0x3F000000U)
25614 #define DDRPHY_DX3GCR8_RESERVED_29_24_SHIFT      (24U)
25615 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
25616  */
25617 #define DDRPHY_DX3GCR8_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_29_24_MASK)
25618 #define DDRPHY_DX3GCR8_RESERVED_31_30_MASK       (0xC0000000U)
25619 #define DDRPHY_DX3GCR8_RESERVED_31_30_SHIFT      (30U)
25620 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25621  */
25622 #define DDRPHY_DX3GCR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_31_30_MASK)
25623 /*! @} */
25624 
25625 /*! @name DX3GCR9 - DATX8 n General Configuration Register 9 */
25626 /*! @{ */
25627 #define DDRPHY_DX3GCR9_RESERVED_5_0_MASK         (0x3FU)
25628 #define DDRPHY_DX3GCR9_RESERVED_5_0_SHIFT        (0U)
25629 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
25630  */
25631 #define DDRPHY_DX3GCR9_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_5_0_MASK)
25632 #define DDRPHY_DX3GCR9_RESERVED_7_6_MASK         (0xC0U)
25633 #define DDRPHY_DX3GCR9_RESERVED_7_6_SHIFT        (6U)
25634 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25635  */
25636 #define DDRPHY_DX3GCR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_7_6_MASK)
25637 #define DDRPHY_DX3GCR9_RESERVED_13_8_MASK        (0x3F00U)
25638 #define DDRPHY_DX3GCR9_RESERVED_13_8_SHIFT       (8U)
25639 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
25640  */
25641 #define DDRPHY_DX3GCR9_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_13_8_MASK)
25642 #define DDRPHY_DX3GCR9_RESERVED_15_14_MASK       (0xC000U)
25643 #define DDRPHY_DX3GCR9_RESERVED_15_14_SHIFT      (14U)
25644 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25645  */
25646 #define DDRPHY_DX3GCR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_15_14_MASK)
25647 #define DDRPHY_DX3GCR9_RESERVED_21_16_MASK       (0x3F0000U)
25648 #define DDRPHY_DX3GCR9_RESERVED_21_16_SHIFT      (16U)
25649 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
25650  */
25651 #define DDRPHY_DX3GCR9_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_21_16_MASK)
25652 #define DDRPHY_DX3GCR9_RESERVED_23_22_MASK       (0xC00000U)
25653 #define DDRPHY_DX3GCR9_RESERVED_23_22_SHIFT      (22U)
25654 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25655  */
25656 #define DDRPHY_DX3GCR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_23_22_MASK)
25657 #define DDRPHY_DX3GCR9_RESERVED_29_24_MASK       (0x3F000000U)
25658 #define DDRPHY_DX3GCR9_RESERVED_29_24_SHIFT      (24U)
25659 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
25660  */
25661 #define DDRPHY_DX3GCR9_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_29_24_MASK)
25662 #define DDRPHY_DX3GCR9_RESERVED_31_30_MASK       (0xC0000000U)
25663 #define DDRPHY_DX3GCR9_RESERVED_31_30_SHIFT      (30U)
25664 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25665  */
25666 #define DDRPHY_DX3GCR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_31_30_MASK)
25667 /*! @} */
25668 
25669 /*! @name DX3DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
25670 /*! @{ */
25671 #define DDRPHY_DX3DQMAP0_DQ0MAP_MASK             (0xFU)
25672 #define DDRPHY_DX3DQMAP0_DQ0MAP_SHIFT            (0U)
25673 /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
25674  */
25675 #define DDRPHY_DX3DQMAP0_DQ0MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ0MAP_MASK)
25676 #define DDRPHY_DX3DQMAP0_DQ1MAP_MASK             (0xF0U)
25677 #define DDRPHY_DX3DQMAP0_DQ1MAP_SHIFT            (4U)
25678 /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
25679  */
25680 #define DDRPHY_DX3DQMAP0_DQ1MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ1MAP_MASK)
25681 #define DDRPHY_DX3DQMAP0_DQ2MAP_MASK             (0xF00U)
25682 #define DDRPHY_DX3DQMAP0_DQ2MAP_SHIFT            (8U)
25683 /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
25684  */
25685 #define DDRPHY_DX3DQMAP0_DQ2MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ2MAP_MASK)
25686 #define DDRPHY_DX3DQMAP0_DQ3MAP_MASK             (0xF000U)
25687 #define DDRPHY_DX3DQMAP0_DQ3MAP_SHIFT            (12U)
25688 /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
25689  */
25690 #define DDRPHY_DX3DQMAP0_DQ3MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ3MAP_MASK)
25691 #define DDRPHY_DX3DQMAP0_DQ4MAP_MASK             (0xF0000U)
25692 #define DDRPHY_DX3DQMAP0_DQ4MAP_SHIFT            (16U)
25693 /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
25694  */
25695 #define DDRPHY_DX3DQMAP0_DQ4MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ4MAP_MASK)
25696 #define DDRPHY_DX3DQMAP0_RESERVED_30_20_MASK     (0x7FF00000U)
25697 #define DDRPHY_DX3DQMAP0_RESERVED_30_20_SHIFT    (20U)
25698 /*! RESERVED_30_20 - Reserved. Return zeroes on reads.
25699  */
25700 #define DDRPHY_DX3DQMAP0_RESERVED_30_20(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX3DQMAP0_RESERVED_30_20_MASK)
25701 #define DDRPHY_DX3DQMAP0_MAPOK_MASK              (0x80000000U)
25702 #define DDRPHY_DX3DQMAP0_MAPOK_SHIFT             (31U)
25703 /*! MAPOK - Checksum bit
25704  */
25705 #define DDRPHY_DX3DQMAP0_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX3DQMAP0_MAPOK_MASK)
25706 /*! @} */
25707 
25708 /*! @name DX3DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
25709 /*! @{ */
25710 #define DDRPHY_DX3DQMAP1_DQ5MAP_MASK             (0xFU)
25711 #define DDRPHY_DX3DQMAP1_DQ5MAP_SHIFT            (0U)
25712 /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
25713  */
25714 #define DDRPHY_DX3DQMAP1_DQ5MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX3DQMAP1_DQ5MAP_MASK)
25715 #define DDRPHY_DX3DQMAP1_DQ6MAP_MASK             (0xF0U)
25716 #define DDRPHY_DX3DQMAP1_DQ6MAP_SHIFT            (4U)
25717 /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
25718  */
25719 #define DDRPHY_DX3DQMAP1_DQ6MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX3DQMAP1_DQ6MAP_MASK)
25720 #define DDRPHY_DX3DQMAP1_DQ7MAP_MASK             (0xF00U)
25721 #define DDRPHY_DX3DQMAP1_DQ7MAP_SHIFT            (8U)
25722 /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
25723  */
25724 #define DDRPHY_DX3DQMAP1_DQ7MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX3DQMAP1_DQ7MAP_MASK)
25725 #define DDRPHY_DX3DQMAP1_DMMAP_MASK              (0xF000U)
25726 #define DDRPHY_DX3DQMAP1_DMMAP_SHIFT             (12U)
25727 /*! DMMAP - DM bit DATX8 slice mapping index
25728  */
25729 #define DDRPHY_DX3DQMAP1_DMMAP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX3DQMAP1_DMMAP_MASK)
25730 #define DDRPHY_DX3DQMAP1_RESERVED_30_16_MASK     (0x7FFF0000U)
25731 #define DDRPHY_DX3DQMAP1_RESERVED_30_16_SHIFT    (16U)
25732 /*! RESERVED_30_16 - Reserved. Return zeroes on reads.
25733  */
25734 #define DDRPHY_DX3DQMAP1_RESERVED_30_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX3DQMAP1_RESERVED_30_16_MASK)
25735 #define DDRPHY_DX3DQMAP1_MAPOK_MASK              (0x80000000U)
25736 #define DDRPHY_DX3DQMAP1_MAPOK_SHIFT             (31U)
25737 /*! MAPOK - Checksum bit
25738  */
25739 #define DDRPHY_DX3DQMAP1_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX3DQMAP1_MAPOK_MASK)
25740 /*! @} */
25741 
25742 /*! @name DX3BDLR0 - DATX8 n Bit Delay Line Register 0 */
25743 /*! @{ */
25744 #define DDRPHY_DX3BDLR0_DQ0WBD_MASK              (0x3FU)
25745 #define DDRPHY_DX3BDLR0_DQ0WBD_SHIFT             (0U)
25746 /*! DQ0WBD - DQ0 Write Bit Delay
25747  */
25748 #define DDRPHY_DX3BDLR0_DQ0WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ0WBD_MASK)
25749 #define DDRPHY_DX3BDLR0_RESERVED_7_6_MASK        (0xC0U)
25750 #define DDRPHY_DX3BDLR0_RESERVED_7_6_SHIFT       (6U)
25751 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25752  */
25753 #define DDRPHY_DX3BDLR0_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_7_6_MASK)
25754 #define DDRPHY_DX3BDLR0_DQ1WBD_MASK              (0x3F00U)
25755 #define DDRPHY_DX3BDLR0_DQ1WBD_SHIFT             (8U)
25756 /*! DQ1WBD - DQ1 Write Bit Delay
25757  */
25758 #define DDRPHY_DX3BDLR0_DQ1WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ1WBD_MASK)
25759 #define DDRPHY_DX3BDLR0_RESERVED_15_14_MASK      (0xC000U)
25760 #define DDRPHY_DX3BDLR0_RESERVED_15_14_SHIFT     (14U)
25761 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25762  */
25763 #define DDRPHY_DX3BDLR0_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_15_14_MASK)
25764 #define DDRPHY_DX3BDLR0_DQ2WBD_MASK              (0x3F0000U)
25765 #define DDRPHY_DX3BDLR0_DQ2WBD_SHIFT             (16U)
25766 /*! DQ2WBD - DQ2 Write Bit Delay
25767  */
25768 #define DDRPHY_DX3BDLR0_DQ2WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ2WBD_MASK)
25769 #define DDRPHY_DX3BDLR0_RESERVED_23_22_MASK      (0xC00000U)
25770 #define DDRPHY_DX3BDLR0_RESERVED_23_22_SHIFT     (22U)
25771 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25772  */
25773 #define DDRPHY_DX3BDLR0_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_23_22_MASK)
25774 #define DDRPHY_DX3BDLR0_DQ3WBD_MASK              (0x3F000000U)
25775 #define DDRPHY_DX3BDLR0_DQ3WBD_SHIFT             (24U)
25776 /*! DQ3WBD - DQ3 Write Bit Delay
25777  */
25778 #define DDRPHY_DX3BDLR0_DQ3WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ3WBD_MASK)
25779 #define DDRPHY_DX3BDLR0_RESERVED_31_30_MASK      (0xC0000000U)
25780 #define DDRPHY_DX3BDLR0_RESERVED_31_30_SHIFT     (30U)
25781 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25782  */
25783 #define DDRPHY_DX3BDLR0_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_31_30_MASK)
25784 /*! @} */
25785 
25786 /*! @name DX3BDLR1 - DATX8 n Bit Delay Line Register 1 */
25787 /*! @{ */
25788 #define DDRPHY_DX3BDLR1_DQ4WBD_MASK              (0x3FU)
25789 #define DDRPHY_DX3BDLR1_DQ4WBD_SHIFT             (0U)
25790 /*! DQ4WBD - DQ4 Write Bit Delay
25791  */
25792 #define DDRPHY_DX3BDLR1_DQ4WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ4WBD_MASK)
25793 #define DDRPHY_DX3BDLR1_RESERVED_7_6_MASK        (0xC0U)
25794 #define DDRPHY_DX3BDLR1_RESERVED_7_6_SHIFT       (6U)
25795 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25796  */
25797 #define DDRPHY_DX3BDLR1_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_7_6_MASK)
25798 #define DDRPHY_DX3BDLR1_DQ5WBD_MASK              (0x3F00U)
25799 #define DDRPHY_DX3BDLR1_DQ5WBD_SHIFT             (8U)
25800 /*! DQ5WBD - DQ5 Write Bit Delay
25801  */
25802 #define DDRPHY_DX3BDLR1_DQ5WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ5WBD_MASK)
25803 #define DDRPHY_DX3BDLR1_RESERVED_15_14_MASK      (0xC000U)
25804 #define DDRPHY_DX3BDLR1_RESERVED_15_14_SHIFT     (14U)
25805 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25806  */
25807 #define DDRPHY_DX3BDLR1_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_15_14_MASK)
25808 #define DDRPHY_DX3BDLR1_DQ6WBD_MASK              (0x3F0000U)
25809 #define DDRPHY_DX3BDLR1_DQ6WBD_SHIFT             (16U)
25810 /*! DQ6WBD - DQ6 Write Bit Delay
25811  */
25812 #define DDRPHY_DX3BDLR1_DQ6WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ6WBD_MASK)
25813 #define DDRPHY_DX3BDLR1_RESERVED_23_22_MASK      (0xC00000U)
25814 #define DDRPHY_DX3BDLR1_RESERVED_23_22_SHIFT     (22U)
25815 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25816  */
25817 #define DDRPHY_DX3BDLR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_23_22_MASK)
25818 #define DDRPHY_DX3BDLR1_DQ7WBD_MASK              (0x3F000000U)
25819 #define DDRPHY_DX3BDLR1_DQ7WBD_SHIFT             (24U)
25820 /*! DQ7WBD - DQ7 Write Bit Delay
25821  */
25822 #define DDRPHY_DX3BDLR1_DQ7WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ7WBD_MASK)
25823 #define DDRPHY_DX3BDLR1_RESERVED_31_30_MASK      (0xC0000000U)
25824 #define DDRPHY_DX3BDLR1_RESERVED_31_30_SHIFT     (30U)
25825 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25826  */
25827 #define DDRPHY_DX3BDLR1_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_31_30_MASK)
25828 /*! @} */
25829 
25830 /*! @name DX3BDLR2 - DATX8 n Bit Delay Line Register 2 */
25831 /*! @{ */
25832 #define DDRPHY_DX3BDLR2_DMWBD_MASK               (0x3FU)
25833 #define DDRPHY_DX3BDLR2_DMWBD_SHIFT              (0U)
25834 /*! DMWBD - DM Write Bit Delay
25835  */
25836 #define DDRPHY_DX3BDLR2_DMWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DMWBD_SHIFT)) & DDRPHY_DX3BDLR2_DMWBD_MASK)
25837 #define DDRPHY_DX3BDLR2_RESERVED_7_6_MASK        (0xC0U)
25838 #define DDRPHY_DX3BDLR2_RESERVED_7_6_SHIFT       (6U)
25839 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25840  */
25841 #define DDRPHY_DX3BDLR2_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_7_6_MASK)
25842 #define DDRPHY_DX3BDLR2_DSWBD_MASK               (0x3F00U)
25843 #define DDRPHY_DX3BDLR2_DSWBD_SHIFT              (8U)
25844 /*! DSWBD - DQS Write Bit Delay
25845  */
25846 #define DDRPHY_DX3BDLR2_DSWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DSWBD_SHIFT)) & DDRPHY_DX3BDLR2_DSWBD_MASK)
25847 #define DDRPHY_DX3BDLR2_RESERVED_15_14_MASK      (0xC000U)
25848 #define DDRPHY_DX3BDLR2_RESERVED_15_14_SHIFT     (14U)
25849 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25850  */
25851 #define DDRPHY_DX3BDLR2_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_15_14_MASK)
25852 #define DDRPHY_DX3BDLR2_DSOEBD_MASK              (0x3F0000U)
25853 #define DDRPHY_DX3BDLR2_DSOEBD_SHIFT             (16U)
25854 /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
25855  */
25856 #define DDRPHY_DX3BDLR2_DSOEBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX3BDLR2_DSOEBD_MASK)
25857 #define DDRPHY_DX3BDLR2_RESERVED_23_22_MASK      (0xC00000U)
25858 #define DDRPHY_DX3BDLR2_RESERVED_23_22_SHIFT     (22U)
25859 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25860  */
25861 #define DDRPHY_DX3BDLR2_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_23_22_MASK)
25862 #define DDRPHY_DX3BDLR2_DSNWBD_MASK              (0x3F000000U)
25863 #define DDRPHY_DX3BDLR2_DSNWBD_SHIFT             (24U)
25864 /*! DSNWBD - DQSN Write Bit Delay
25865  */
25866 #define DDRPHY_DX3BDLR2_DSNWBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX3BDLR2_DSNWBD_MASK)
25867 #define DDRPHY_DX3BDLR2_RESERVED_31_30_MASK      (0xC0000000U)
25868 #define DDRPHY_DX3BDLR2_RESERVED_31_30_SHIFT     (30U)
25869 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25870  */
25871 #define DDRPHY_DX3BDLR2_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_31_30_MASK)
25872 /*! @} */
25873 
25874 /*! @name DX3BDLR3 - DATX8 n Bit Delay Line Register 3 */
25875 /*! @{ */
25876 #define DDRPHY_DX3BDLR3_DQ0RBD_MASK              (0x3FU)
25877 #define DDRPHY_DX3BDLR3_DQ0RBD_SHIFT             (0U)
25878 /*! DQ0RBD - DQ0 Read Bit Delay
25879  */
25880 #define DDRPHY_DX3BDLR3_DQ0RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ0RBD_MASK)
25881 #define DDRPHY_DX3BDLR3_RESERVED_7_6_MASK        (0xC0U)
25882 #define DDRPHY_DX3BDLR3_RESERVED_7_6_SHIFT       (6U)
25883 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25884  */
25885 #define DDRPHY_DX3BDLR3_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_7_6_MASK)
25886 #define DDRPHY_DX3BDLR3_DQ1RBD_MASK              (0x3F00U)
25887 #define DDRPHY_DX3BDLR3_DQ1RBD_SHIFT             (8U)
25888 /*! DQ1RBD - DQ1 Read Bit Delay
25889  */
25890 #define DDRPHY_DX3BDLR3_DQ1RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ1RBD_MASK)
25891 #define DDRPHY_DX3BDLR3_RESERVED_15_14_MASK      (0xC000U)
25892 #define DDRPHY_DX3BDLR3_RESERVED_15_14_SHIFT     (14U)
25893 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25894  */
25895 #define DDRPHY_DX3BDLR3_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_15_14_MASK)
25896 #define DDRPHY_DX3BDLR3_DQ2RBD_MASK              (0x3F0000U)
25897 #define DDRPHY_DX3BDLR3_DQ2RBD_SHIFT             (16U)
25898 /*! DQ2RBD - DQ2 Read Bit Delay
25899  */
25900 #define DDRPHY_DX3BDLR3_DQ2RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ2RBD_MASK)
25901 #define DDRPHY_DX3BDLR3_RESERVED_23_22_MASK      (0xC00000U)
25902 #define DDRPHY_DX3BDLR3_RESERVED_23_22_SHIFT     (22U)
25903 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25904  */
25905 #define DDRPHY_DX3BDLR3_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_23_22_MASK)
25906 #define DDRPHY_DX3BDLR3_DQ3RBD_MASK              (0x3F000000U)
25907 #define DDRPHY_DX3BDLR3_DQ3RBD_SHIFT             (24U)
25908 /*! DQ3RBD - DQ3 Read Bit Delay
25909  */
25910 #define DDRPHY_DX3BDLR3_DQ3RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ3RBD_MASK)
25911 #define DDRPHY_DX3BDLR3_RESERVED_31_30_MASK      (0xC0000000U)
25912 #define DDRPHY_DX3BDLR3_RESERVED_31_30_SHIFT     (30U)
25913 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25914  */
25915 #define DDRPHY_DX3BDLR3_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_31_30_MASK)
25916 /*! @} */
25917 
25918 /*! @name DX3BDLR4 - DATX8 n Bit Delay Line Register 4 */
25919 /*! @{ */
25920 #define DDRPHY_DX3BDLR4_DQ4RBD_MASK              (0x3FU)
25921 #define DDRPHY_DX3BDLR4_DQ4RBD_SHIFT             (0U)
25922 /*! DQ4RBD - DQ4 Read Bit Delay
25923  */
25924 #define DDRPHY_DX3BDLR4_DQ4RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ4RBD_MASK)
25925 #define DDRPHY_DX3BDLR4_RESERVED_7_6_MASK        (0xC0U)
25926 #define DDRPHY_DX3BDLR4_RESERVED_7_6_SHIFT       (6U)
25927 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25928  */
25929 #define DDRPHY_DX3BDLR4_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_7_6_MASK)
25930 #define DDRPHY_DX3BDLR4_DQ5RBD_MASK              (0x3F00U)
25931 #define DDRPHY_DX3BDLR4_DQ5RBD_SHIFT             (8U)
25932 /*! DQ5RBD - DQ5 Read Bit Delay
25933  */
25934 #define DDRPHY_DX3BDLR4_DQ5RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ5RBD_MASK)
25935 #define DDRPHY_DX3BDLR4_RESERVED_15_14_MASK      (0xC000U)
25936 #define DDRPHY_DX3BDLR4_RESERVED_15_14_SHIFT     (14U)
25937 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25938  */
25939 #define DDRPHY_DX3BDLR4_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_15_14_MASK)
25940 #define DDRPHY_DX3BDLR4_DQ6RBD_MASK              (0x3F0000U)
25941 #define DDRPHY_DX3BDLR4_DQ6RBD_SHIFT             (16U)
25942 /*! DQ6RBD - DQ6 Read Bit Delay
25943  */
25944 #define DDRPHY_DX3BDLR4_DQ6RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ6RBD_MASK)
25945 #define DDRPHY_DX3BDLR4_RESERVED_23_22_MASK      (0xC00000U)
25946 #define DDRPHY_DX3BDLR4_RESERVED_23_22_SHIFT     (22U)
25947 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25948  */
25949 #define DDRPHY_DX3BDLR4_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_23_22_MASK)
25950 #define DDRPHY_DX3BDLR4_DQ7RBD_MASK              (0x3F000000U)
25951 #define DDRPHY_DX3BDLR4_DQ7RBD_SHIFT             (24U)
25952 /*! DQ7RBD - DQ7 Read Bit Delay
25953  */
25954 #define DDRPHY_DX3BDLR4_DQ7RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ7RBD_MASK)
25955 #define DDRPHY_DX3BDLR4_RESERVED_31_30_MASK      (0xC0000000U)
25956 #define DDRPHY_DX3BDLR4_RESERVED_31_30_SHIFT     (30U)
25957 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25958  */
25959 #define DDRPHY_DX3BDLR4_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_31_30_MASK)
25960 /*! @} */
25961 
25962 /*! @name DX3BDLR5 - DATX8 n Bit Delay Line Register 5 */
25963 /*! @{ */
25964 #define DDRPHY_DX3BDLR5_DMRBD_MASK               (0x3FU)
25965 #define DDRPHY_DX3BDLR5_DMRBD_SHIFT              (0U)
25966 /*! DMRBD - DM Read Bit Delay
25967  */
25968 #define DDRPHY_DX3BDLR5_DMRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR5_DMRBD_SHIFT)) & DDRPHY_DX3BDLR5_DMRBD_MASK)
25969 #define DDRPHY_DX3BDLR5_RESERVED_31_6_MASK       (0xFFFFFFC0U)
25970 #define DDRPHY_DX3BDLR5_RESERVED_31_6_SHIFT      (6U)
25971 /*! RESERVED_31_6 - Reserved. Return zeroes on reads.
25972  */
25973 #define DDRPHY_DX3BDLR5_RESERVED_31_6(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX3BDLR5_RESERVED_31_6_MASK)
25974 /*! @} */
25975 
25976 /*! @name DX3BDLR6 - DATX8 n Bit Delay Line Register 6 */
25977 /*! @{ */
25978 #define DDRPHY_DX3BDLR6_RESERVED_7_0_MASK        (0xFFU)
25979 #define DDRPHY_DX3BDLR6_RESERVED_7_0_SHIFT       (0U)
25980 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
25981  */
25982 #define DDRPHY_DX3BDLR6_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX3BDLR6_RESERVED_7_0_MASK)
25983 #define DDRPHY_DX3BDLR6_PDRBD_MASK               (0x3F00U)
25984 #define DDRPHY_DX3BDLR6_PDRBD_SHIFT              (8U)
25985 /*! PDRBD - Power down receiver Bit Delay
25986  */
25987 #define DDRPHY_DX3BDLR6_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_PDRBD_SHIFT)) & DDRPHY_DX3BDLR6_PDRBD_MASK)
25988 #define DDRPHY_DX3BDLR6_RESERVED_15_14_MASK      (0xC000U)
25989 #define DDRPHY_DX3BDLR6_RESERVED_15_14_SHIFT     (14U)
25990 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25991  */
25992 #define DDRPHY_DX3BDLR6_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR6_RESERVED_15_14_MASK)
25993 #define DDRPHY_DX3BDLR6_TERBD_MASK               (0x3F0000U)
25994 #define DDRPHY_DX3BDLR6_TERBD_SHIFT              (16U)
25995 /*! TERBD - Termination Enable Bit Delay
25996  */
25997 #define DDRPHY_DX3BDLR6_TERBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_TERBD_SHIFT)) & DDRPHY_DX3BDLR6_TERBD_MASK)
25998 #define DDRPHY_DX3BDLR6_RESERVED_31_22_MASK      (0xFFC00000U)
25999 #define DDRPHY_DX3BDLR6_RESERVED_31_22_SHIFT     (22U)
26000 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
26001  */
26002 #define DDRPHY_DX3BDLR6_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR6_RESERVED_31_22_MASK)
26003 /*! @} */
26004 
26005 /*! @name DX3BDLR7 - DATX8 n Bit Delay Line Register 7 */
26006 /*! @{ */
26007 #define DDRPHY_DX3BDLR7_RESERVED_5_0_MASK        (0x3FU)
26008 #define DDRPHY_DX3BDLR7_RESERVED_5_0_SHIFT       (0U)
26009 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
26010  */
26011 #define DDRPHY_DX3BDLR7_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_5_0_MASK)
26012 #define DDRPHY_DX3BDLR7_RESERVED_7_6_MASK        (0xC0U)
26013 #define DDRPHY_DX3BDLR7_RESERVED_7_6_SHIFT       (6U)
26014 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
26015  */
26016 #define DDRPHY_DX3BDLR7_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_7_6_MASK)
26017 #define DDRPHY_DX3BDLR7_RESERVED_13_8_MASK       (0x3F00U)
26018 #define DDRPHY_DX3BDLR7_RESERVED_13_8_SHIFT      (8U)
26019 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
26020  */
26021 #define DDRPHY_DX3BDLR7_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_13_8_MASK)
26022 #define DDRPHY_DX3BDLR7_RESERVED_15_14_MASK      (0xC000U)
26023 #define DDRPHY_DX3BDLR7_RESERVED_15_14_SHIFT     (14U)
26024 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
26025  */
26026 #define DDRPHY_DX3BDLR7_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_15_14_MASK)
26027 #define DDRPHY_DX3BDLR7_RESERVED_21_16_MASK      (0x3F0000U)
26028 #define DDRPHY_DX3BDLR7_RESERVED_21_16_SHIFT     (16U)
26029 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
26030  */
26031 #define DDRPHY_DX3BDLR7_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_21_16_MASK)
26032 #define DDRPHY_DX3BDLR7_RESERVED_31_22_MASK      (0xFFC00000U)
26033 #define DDRPHY_DX3BDLR7_RESERVED_31_22_SHIFT     (22U)
26034 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
26035  */
26036 #define DDRPHY_DX3BDLR7_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_31_22_MASK)
26037 /*! @} */
26038 
26039 /*! @name DX3BDLR8 - DATX8 n Bit Delay Line Register 8 */
26040 /*! @{ */
26041 #define DDRPHY_DX3BDLR8_RESERVED_5_0_MASK        (0x3FU)
26042 #define DDRPHY_DX3BDLR8_RESERVED_5_0_SHIFT       (0U)
26043 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
26044  */
26045 #define DDRPHY_DX3BDLR8_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_5_0_MASK)
26046 #define DDRPHY_DX3BDLR8_RESERVED_7_6_MASK        (0xC0U)
26047 #define DDRPHY_DX3BDLR8_RESERVED_7_6_SHIFT       (6U)
26048 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
26049  */
26050 #define DDRPHY_DX3BDLR8_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_7_6_MASK)
26051 #define DDRPHY_DX3BDLR8_RESERVED_13_8_MASK       (0x3F00U)
26052 #define DDRPHY_DX3BDLR8_RESERVED_13_8_SHIFT      (8U)
26053 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
26054  */
26055 #define DDRPHY_DX3BDLR8_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_13_8_MASK)
26056 #define DDRPHY_DX3BDLR8_RESERVED_15_14_MASK      (0xC000U)
26057 #define DDRPHY_DX3BDLR8_RESERVED_15_14_SHIFT     (14U)
26058 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
26059  */
26060 #define DDRPHY_DX3BDLR8_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_15_14_MASK)
26061 #define DDRPHY_DX3BDLR8_RESERVED_21_16_MASK      (0x3F0000U)
26062 #define DDRPHY_DX3BDLR8_RESERVED_21_16_SHIFT     (16U)
26063 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
26064  */
26065 #define DDRPHY_DX3BDLR8_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_21_16_MASK)
26066 #define DDRPHY_DX3BDLR8_RESERVED_31_22_MASK      (0xFFC00000U)
26067 #define DDRPHY_DX3BDLR8_RESERVED_31_22_SHIFT     (22U)
26068 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
26069  */
26070 #define DDRPHY_DX3BDLR8_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_31_22_MASK)
26071 /*! @} */
26072 
26073 /*! @name DX3BDLR9 - DATX8 n Bit Delay Line Register 9 */
26074 /*! @{ */
26075 #define DDRPHY_DX3BDLR9_RESERVED_5_0_MASK        (0x3FU)
26076 #define DDRPHY_DX3BDLR9_RESERVED_5_0_SHIFT       (0U)
26077 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
26078  */
26079 #define DDRPHY_DX3BDLR9_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_5_0_MASK)
26080 #define DDRPHY_DX3BDLR9_RESERVED_7_6_MASK        (0xC0U)
26081 #define DDRPHY_DX3BDLR9_RESERVED_7_6_SHIFT       (6U)
26082 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
26083  */
26084 #define DDRPHY_DX3BDLR9_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_7_6_MASK)
26085 #define DDRPHY_DX3BDLR9_RESERVED_13_8_MASK       (0x3F00U)
26086 #define DDRPHY_DX3BDLR9_RESERVED_13_8_SHIFT      (8U)
26087 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
26088  */
26089 #define DDRPHY_DX3BDLR9_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_13_8_MASK)
26090 #define DDRPHY_DX3BDLR9_RESERVED_15_14_MASK      (0xC000U)
26091 #define DDRPHY_DX3BDLR9_RESERVED_15_14_SHIFT     (14U)
26092 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
26093  */
26094 #define DDRPHY_DX3BDLR9_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_15_14_MASK)
26095 #define DDRPHY_DX3BDLR9_RESERVED_21_16_MASK      (0x3F0000U)
26096 #define DDRPHY_DX3BDLR9_RESERVED_21_16_SHIFT     (16U)
26097 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
26098  */
26099 #define DDRPHY_DX3BDLR9_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_21_16_MASK)
26100 #define DDRPHY_DX3BDLR9_RESERVED_31_22_MASK      (0xFFC00000U)
26101 #define DDRPHY_DX3BDLR9_RESERVED_31_22_SHIFT     (22U)
26102 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
26103  */
26104 #define DDRPHY_DX3BDLR9_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_31_22_MASK)
26105 /*! @} */
26106 
26107 /*! @name DX3LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
26108 /*! @{ */
26109 #define DDRPHY_DX3LCDLR0_WLD_MASK                (0x1FFU)
26110 #define DDRPHY_DX3LCDLR0_WLD_SHIFT               (0U)
26111 /*! WLD - Write Leveling Delay
26112  */
26113 #define DDRPHY_DX3LCDLR0_WLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_WLD_SHIFT)) & DDRPHY_DX3LCDLR0_WLD_MASK)
26114 #define DDRPHY_DX3LCDLR0_RESERVED_15_9_MASK      (0xFE00U)
26115 #define DDRPHY_DX3LCDLR0_RESERVED_15_9_SHIFT     (9U)
26116 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26117  */
26118 #define DDRPHY_DX3LCDLR0_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR0_RESERVED_15_9_MASK)
26119 #define DDRPHY_DX3LCDLR0_RESERVED_24_16_MASK     (0x1FF0000U)
26120 #define DDRPHY_DX3LCDLR0_RESERVED_24_16_SHIFT    (16U)
26121 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26122  */
26123 #define DDRPHY_DX3LCDLR0_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR0_RESERVED_24_16_MASK)
26124 #define DDRPHY_DX3LCDLR0_RESERVED_31_25_MASK     (0xFE000000U)
26125 #define DDRPHY_DX3LCDLR0_RESERVED_31_25_SHIFT    (25U)
26126 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26127  */
26128 #define DDRPHY_DX3LCDLR0_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR0_RESERVED_31_25_MASK)
26129 /*! @} */
26130 
26131 /*! @name DX3LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
26132 /*! @{ */
26133 #define DDRPHY_DX3LCDLR1_WDQD_MASK               (0x1FFU)
26134 #define DDRPHY_DX3LCDLR1_WDQD_SHIFT              (0U)
26135 /*! WDQD - Write Data Delay
26136  */
26137 #define DDRPHY_DX3LCDLR1_WDQD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_WDQD_SHIFT)) & DDRPHY_DX3LCDLR1_WDQD_MASK)
26138 #define DDRPHY_DX3LCDLR1_RESERVED_15_9_MASK      (0xFE00U)
26139 #define DDRPHY_DX3LCDLR1_RESERVED_15_9_SHIFT     (9U)
26140 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26141  */
26142 #define DDRPHY_DX3LCDLR1_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR1_RESERVED_15_9_MASK)
26143 #define DDRPHY_DX3LCDLR1_RESERVED_24_16_MASK     (0x1FF0000U)
26144 #define DDRPHY_DX3LCDLR1_RESERVED_24_16_SHIFT    (16U)
26145 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26146  */
26147 #define DDRPHY_DX3LCDLR1_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR1_RESERVED_24_16_MASK)
26148 #define DDRPHY_DX3LCDLR1_RESERVED_31_25_MASK     (0xFE000000U)
26149 #define DDRPHY_DX3LCDLR1_RESERVED_31_25_SHIFT    (25U)
26150 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26151  */
26152 #define DDRPHY_DX3LCDLR1_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR1_RESERVED_31_25_MASK)
26153 /*! @} */
26154 
26155 /*! @name DX3LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
26156 /*! @{ */
26157 #define DDRPHY_DX3LCDLR2_DQSGD_MASK              (0x1FFU)
26158 #define DDRPHY_DX3LCDLR2_DQSGD_SHIFT             (0U)
26159 /*! DQSGD - Read DQS Gating Delay
26160  */
26161 #define DDRPHY_DX3LCDLR2_DQSGD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX3LCDLR2_DQSGD_MASK)
26162 #define DDRPHY_DX3LCDLR2_RESERVED_15_9_MASK      (0xFE00U)
26163 #define DDRPHY_DX3LCDLR2_RESERVED_15_9_SHIFT     (9U)
26164 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26165  */
26166 #define DDRPHY_DX3LCDLR2_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR2_RESERVED_15_9_MASK)
26167 #define DDRPHY_DX3LCDLR2_RESERVED_24_16_MASK     (0x1FF0000U)
26168 #define DDRPHY_DX3LCDLR2_RESERVED_24_16_SHIFT    (16U)
26169 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26170  */
26171 #define DDRPHY_DX3LCDLR2_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR2_RESERVED_24_16_MASK)
26172 #define DDRPHY_DX3LCDLR2_RESERVED_31_25_MASK     (0xFE000000U)
26173 #define DDRPHY_DX3LCDLR2_RESERVED_31_25_SHIFT    (25U)
26174 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26175  */
26176 #define DDRPHY_DX3LCDLR2_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR2_RESERVED_31_25_MASK)
26177 /*! @} */
26178 
26179 /*! @name DX3LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
26180 /*! @{ */
26181 #define DDRPHY_DX3LCDLR3_RDQSD_MASK              (0x1FFU)
26182 #define DDRPHY_DX3LCDLR3_RDQSD_SHIFT             (0U)
26183 /*! RDQSD - Read DQS Delay
26184  */
26185 #define DDRPHY_DX3LCDLR3_RDQSD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX3LCDLR3_RDQSD_MASK)
26186 #define DDRPHY_DX3LCDLR3_RESERVED_15_9_MASK      (0xFE00U)
26187 #define DDRPHY_DX3LCDLR3_RESERVED_15_9_SHIFT     (9U)
26188 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26189  */
26190 #define DDRPHY_DX3LCDLR3_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR3_RESERVED_15_9_MASK)
26191 #define DDRPHY_DX3LCDLR3_RESERVED_24_16_MASK     (0x1FF0000U)
26192 #define DDRPHY_DX3LCDLR3_RESERVED_24_16_SHIFT    (16U)
26193 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26194  */
26195 #define DDRPHY_DX3LCDLR3_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR3_RESERVED_24_16_MASK)
26196 #define DDRPHY_DX3LCDLR3_RESERVED_31_25_MASK     (0xFE000000U)
26197 #define DDRPHY_DX3LCDLR3_RESERVED_31_25_SHIFT    (25U)
26198 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26199  */
26200 #define DDRPHY_DX3LCDLR3_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR3_RESERVED_31_25_MASK)
26201 /*! @} */
26202 
26203 /*! @name DX3LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
26204 /*! @{ */
26205 #define DDRPHY_DX3LCDLR4_RDQSND_MASK             (0x1FFU)
26206 #define DDRPHY_DX3LCDLR4_RDQSND_SHIFT            (0U)
26207 /*! RDQSND - Read DQSN Delay
26208  */
26209 #define DDRPHY_DX3LCDLR4_RDQSND(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX3LCDLR4_RDQSND_MASK)
26210 #define DDRPHY_DX3LCDLR4_RESERVED_15_9_MASK      (0xFE00U)
26211 #define DDRPHY_DX3LCDLR4_RESERVED_15_9_SHIFT     (9U)
26212 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26213  */
26214 #define DDRPHY_DX3LCDLR4_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR4_RESERVED_15_9_MASK)
26215 #define DDRPHY_DX3LCDLR4_RESERVED_24_16_MASK     (0x1FF0000U)
26216 #define DDRPHY_DX3LCDLR4_RESERVED_24_16_SHIFT    (16U)
26217 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26218  */
26219 #define DDRPHY_DX3LCDLR4_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR4_RESERVED_24_16_MASK)
26220 #define DDRPHY_DX3LCDLR4_RESERVED_31_25_MASK     (0xFE000000U)
26221 #define DDRPHY_DX3LCDLR4_RESERVED_31_25_SHIFT    (25U)
26222 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26223  */
26224 #define DDRPHY_DX3LCDLR4_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR4_RESERVED_31_25_MASK)
26225 /*! @} */
26226 
26227 /*! @name DX3LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
26228 /*! @{ */
26229 #define DDRPHY_DX3LCDLR5_DQSGSD_MASK             (0x1FFU)
26230 #define DDRPHY_DX3LCDLR5_DQSGSD_SHIFT            (0U)
26231 /*! DQSGSD - DQS Gating Status Delay
26232  */
26233 #define DDRPHY_DX3LCDLR5_DQSGSD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX3LCDLR5_DQSGSD_MASK)
26234 #define DDRPHY_DX3LCDLR5_RESERVED_15_9_MASK      (0xFE00U)
26235 #define DDRPHY_DX3LCDLR5_RESERVED_15_9_SHIFT     (9U)
26236 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26237  */
26238 #define DDRPHY_DX3LCDLR5_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR5_RESERVED_15_9_MASK)
26239 #define DDRPHY_DX3LCDLR5_RESERVED_24_16_MASK     (0x1FF0000U)
26240 #define DDRPHY_DX3LCDLR5_RESERVED_24_16_SHIFT    (16U)
26241 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26242  */
26243 #define DDRPHY_DX3LCDLR5_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR5_RESERVED_24_16_MASK)
26244 #define DDRPHY_DX3LCDLR5_RESERVED_31_25_MASK     (0xFE000000U)
26245 #define DDRPHY_DX3LCDLR5_RESERVED_31_25_SHIFT    (25U)
26246 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26247  */
26248 #define DDRPHY_DX3LCDLR5_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR5_RESERVED_31_25_MASK)
26249 /*! @} */
26250 
26251 /*! @name DX3MDLR0 - DATX8 n Master Delay Line Register 0 */
26252 /*! @{ */
26253 #define DDRPHY_DX3MDLR0_IPRD_MASK                (0x1FFU)
26254 #define DDRPHY_DX3MDLR0_IPRD_SHIFT               (0U)
26255 /*! IPRD - Initial Period
26256  */
26257 #define DDRPHY_DX3MDLR0_IPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_IPRD_SHIFT)) & DDRPHY_DX3MDLR0_IPRD_MASK)
26258 #define DDRPHY_DX3MDLR0_RESERVED_15_9_MASK       (0xFE00U)
26259 #define DDRPHY_DX3MDLR0_RESERVED_15_9_SHIFT      (9U)
26260 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26261  */
26262 #define DDRPHY_DX3MDLR0_RESERVED_15_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX3MDLR0_RESERVED_15_9_MASK)
26263 #define DDRPHY_DX3MDLR0_TPRD_MASK                (0x1FF0000U)
26264 #define DDRPHY_DX3MDLR0_TPRD_SHIFT               (16U)
26265 /*! TPRD - Target Period
26266  */
26267 #define DDRPHY_DX3MDLR0_TPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_TPRD_SHIFT)) & DDRPHY_DX3MDLR0_TPRD_MASK)
26268 #define DDRPHY_DX3MDLR0_RESERVED_31_25_MASK      (0xFE000000U)
26269 #define DDRPHY_DX3MDLR0_RESERVED_31_25_SHIFT     (25U)
26270 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26271  */
26272 #define DDRPHY_DX3MDLR0_RESERVED_31_25(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX3MDLR0_RESERVED_31_25_MASK)
26273 /*! @} */
26274 
26275 /*! @name DX3MDLR1 - DATX8 n Master Delay Line Register 1 */
26276 /*! @{ */
26277 #define DDRPHY_DX3MDLR1_MDLD_MASK                (0x1FFU)
26278 #define DDRPHY_DX3MDLR1_MDLD_SHIFT               (0U)
26279 /*! MDLD - MDL Delay
26280  */
26281 #define DDRPHY_DX3MDLR1_MDLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR1_MDLD_SHIFT)) & DDRPHY_DX3MDLR1_MDLD_MASK)
26282 #define DDRPHY_DX3MDLR1_RESERVED_31_9_MASK       (0xFFFFFE00U)
26283 #define DDRPHY_DX3MDLR1_RESERVED_31_9_SHIFT      (9U)
26284 /*! RESERVED_31_9 - Reserved. Return zeroes on reads.
26285  */
26286 #define DDRPHY_DX3MDLR1_RESERVED_31_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX3MDLR1_RESERVED_31_9_MASK)
26287 /*! @} */
26288 
26289 /*! @name DX3GTR0 - DATX8 n General Timing Register 0 */
26290 /*! @{ */
26291 #define DDRPHY_DX3GTR0_DGSL_MASK                 (0x1FU)
26292 #define DDRPHY_DX3GTR0_DGSL_SHIFT                (0U)
26293 /*! DGSL - DQS Gating System Latency
26294  */
26295 #define DDRPHY_DX3GTR0_DGSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_DGSL_SHIFT)) & DDRPHY_DX3GTR0_DGSL_MASK)
26296 #define DDRPHY_DX3GTR0_RESERVED_7_5_MASK         (0xE0U)
26297 #define DDRPHY_DX3GTR0_RESERVED_7_5_SHIFT        (5U)
26298 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
26299  */
26300 #define DDRPHY_DX3GTR0_RESERVED_7_5(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_7_5_MASK)
26301 #define DDRPHY_DX3GTR0_RESERVED_12_8_MASK        (0x1F00U)
26302 #define DDRPHY_DX3GTR0_RESERVED_12_8_SHIFT       (8U)
26303 /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
26304  */
26305 #define DDRPHY_DX3GTR0_RESERVED_12_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_12_8_MASK)
26306 #define DDRPHY_DX3GTR0_RESERVED_15_13_MASK       (0xE000U)
26307 #define DDRPHY_DX3GTR0_RESERVED_15_13_SHIFT      (13U)
26308 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
26309  */
26310 #define DDRPHY_DX3GTR0_RESERVED_15_13(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_15_13_MASK)
26311 #define DDRPHY_DX3GTR0_WLSL_MASK                 (0xF0000U)
26312 #define DDRPHY_DX3GTR0_WLSL_SHIFT                (16U)
26313 /*! WLSL - Write Leveling System Latency
26314  */
26315 #define DDRPHY_DX3GTR0_WLSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_WLSL_SHIFT)) & DDRPHY_DX3GTR0_WLSL_MASK)
26316 #define DDRPHY_DX3GTR0_RESERVED_23_20_MASK       (0xF00000U)
26317 #define DDRPHY_DX3GTR0_RESERVED_23_20_SHIFT      (20U)
26318 /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
26319  */
26320 #define DDRPHY_DX3GTR0_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_23_20_MASK)
26321 #define DDRPHY_DX3GTR0_WDQSL_MASK                (0x7000000U)
26322 #define DDRPHY_DX3GTR0_WDQSL_SHIFT               (24U)
26323 /*! WDQSL - DQ Write Path Latency Pipeline
26324  */
26325 #define DDRPHY_DX3GTR0_WDQSL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_WDQSL_SHIFT)) & DDRPHY_DX3GTR0_WDQSL_MASK)
26326 #define DDRPHY_DX3GTR0_RESERVED_31_24_MASK       (0xF8000000U)
26327 #define DDRPHY_DX3GTR0_RESERVED_31_24_SHIFT      (27U)
26328 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
26329  */
26330 #define DDRPHY_DX3GTR0_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_31_24_MASK)
26331 /*! @} */
26332 
26333 /*! @name DX3RSR0 - DATX8 n Rank Status Register 0 */
26334 /*! @{ */
26335 #define DDRPHY_DX3RSR0_QSGERR_MASK               (0xFFFFU)
26336 #define DDRPHY_DX3RSR0_QSGERR_SHIFT              (0U)
26337 /*! QSGERR - DQS Gate Training Error
26338  */
26339 #define DDRPHY_DX3RSR0_QSGERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR0_QSGERR_SHIFT)) & DDRPHY_DX3RSR0_QSGERR_MASK)
26340 #define DDRPHY_DX3RSR0_RESERVED_31_16_MASK       (0xFFFF0000U)
26341 #define DDRPHY_DX3RSR0_RESERVED_31_16_SHIFT      (16U)
26342 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
26343  */
26344 #define DDRPHY_DX3RSR0_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR0_RESERVED_31_16_MASK)
26345 /*! @} */
26346 
26347 /*! @name DX3RSR1 - DATX8 n Rank Status Register 1 */
26348 /*! @{ */
26349 #define DDRPHY_DX3RSR1_RDLVLERR_MASK             (0xFFFFU)
26350 #define DDRPHY_DX3RSR1_RDLVLERR_SHIFT            (0U)
26351 /*! RDLVLERR - Read Leveling Error
26352  */
26353 #define DDRPHY_DX3RSR1_RDLVLERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX3RSR1_RDLVLERR_MASK)
26354 #define DDRPHY_DX3RSR1_RESERVED_31_16_MASK       (0xFFFF0000U)
26355 #define DDRPHY_DX3RSR1_RESERVED_31_16_SHIFT      (16U)
26356 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
26357  */
26358 #define DDRPHY_DX3RSR1_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR1_RESERVED_31_16_MASK)
26359 /*! @} */
26360 
26361 /*! @name DX3RSR2 - DATX8 n Rank Status Register 2 */
26362 /*! @{ */
26363 #define DDRPHY_DX3RSR2_WLAWN_MASK                (0xFFFFU)
26364 #define DDRPHY_DX3RSR2_WLAWN_SHIFT               (0U)
26365 /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
26366  */
26367 #define DDRPHY_DX3RSR2_WLAWN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR2_WLAWN_SHIFT)) & DDRPHY_DX3RSR2_WLAWN_MASK)
26368 #define DDRPHY_DX3RSR2_RESERVED_31_16_MASK       (0xFFFF0000U)
26369 #define DDRPHY_DX3RSR2_RESERVED_31_16_SHIFT      (16U)
26370 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
26371  */
26372 #define DDRPHY_DX3RSR2_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR2_RESERVED_31_16_MASK)
26373 /*! @} */
26374 
26375 /*! @name DX3RSR3 - DATX8 n Rank Status Register 3 */
26376 /*! @{ */
26377 #define DDRPHY_DX3RSR3_WLAERR_MASK               (0xFFFFU)
26378 #define DDRPHY_DX3RSR3_WLAERR_SHIFT              (0U)
26379 /*! WLAERR - Write Leveling Adjustment Error
26380  */
26381 #define DDRPHY_DX3RSR3_WLAERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR3_WLAERR_SHIFT)) & DDRPHY_DX3RSR3_WLAERR_MASK)
26382 #define DDRPHY_DX3RSR3_RESERVED_31_16_MASK       (0xFFFF0000U)
26383 #define DDRPHY_DX3RSR3_RESERVED_31_16_SHIFT      (16U)
26384 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
26385  */
26386 #define DDRPHY_DX3RSR3_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR3_RESERVED_31_16_MASK)
26387 /*! @} */
26388 
26389 /*! @name DX3GSR0 - DATX8 n General Status Register 0 */
26390 /*! @{ */
26391 #define DDRPHY_DX3GSR0_WDQCAL_MASK               (0x1U)
26392 #define DDRPHY_DX3GSR0_WDQCAL_SHIFT              (0U)
26393 /*! WDQCAL - Write DQ Calibration
26394  */
26395 #define DDRPHY_DX3GSR0_WDQCAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WDQCAL_SHIFT)) & DDRPHY_DX3GSR0_WDQCAL_MASK)
26396 #define DDRPHY_DX3GSR0_RDQSCAL_MASK              (0x2U)
26397 #define DDRPHY_DX3GSR0_RDQSCAL_SHIFT             (1U)
26398 /*! RDQSCAL - Read DQS Calibration
26399  */
26400 #define DDRPHY_DX3GSR0_RDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX3GSR0_RDQSCAL_MASK)
26401 #define DDRPHY_DX3GSR0_RDQSNCAL_MASK             (0x4U)
26402 #define DDRPHY_DX3GSR0_RDQSNCAL_SHIFT            (2U)
26403 /*! RDQSNCAL - Read DQS# Calibration
26404  */
26405 #define DDRPHY_DX3GSR0_RDQSNCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX3GSR0_RDQSNCAL_MASK)
26406 #define DDRPHY_DX3GSR0_GDQSCAL_MASK              (0x8U)
26407 #define DDRPHY_DX3GSR0_GDQSCAL_SHIFT             (3U)
26408 /*! GDQSCAL - Read DQS gating Calibration
26409  */
26410 #define DDRPHY_DX3GSR0_GDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX3GSR0_GDQSCAL_MASK)
26411 #define DDRPHY_DX3GSR0_WLCAL_MASK                (0x10U)
26412 #define DDRPHY_DX3GSR0_WLCAL_SHIFT               (4U)
26413 /*! WLCAL - Write Leveling Calibration
26414  */
26415 #define DDRPHY_DX3GSR0_WLCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLCAL_SHIFT)) & DDRPHY_DX3GSR0_WLCAL_MASK)
26416 #define DDRPHY_DX3GSR0_WLDONE_MASK               (0x20U)
26417 #define DDRPHY_DX3GSR0_WLDONE_SHIFT              (5U)
26418 /*! WLDONE - Write Leveling Done
26419  */
26420 #define DDRPHY_DX3GSR0_WLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLDONE_SHIFT)) & DDRPHY_DX3GSR0_WLDONE_MASK)
26421 #define DDRPHY_DX3GSR0_WLERR_MASK                (0x40U)
26422 #define DDRPHY_DX3GSR0_WLERR_SHIFT               (6U)
26423 /*! WLERR - Write Leveling Error
26424  */
26425 #define DDRPHY_DX3GSR0_WLERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLERR_SHIFT)) & DDRPHY_DX3GSR0_WLERR_MASK)
26426 #define DDRPHY_DX3GSR0_WLPRD_MASK                (0xFF80U)
26427 #define DDRPHY_DX3GSR0_WLPRD_SHIFT               (7U)
26428 /*! WLPRD - Write Leveling Period
26429  */
26430 #define DDRPHY_DX3GSR0_WLPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLPRD_SHIFT)) & DDRPHY_DX3GSR0_WLPRD_MASK)
26431 #define DDRPHY_DX3GSR0_DPLOCK_MASK               (0x10000U)
26432 #define DDRPHY_DX3GSR0_DPLOCK_SHIFT              (16U)
26433 /*! DPLOCK - DATX8 PLL Lock
26434  */
26435 #define DDRPHY_DX3GSR0_DPLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_DPLOCK_SHIFT)) & DDRPHY_DX3GSR0_DPLOCK_MASK)
26436 #define DDRPHY_DX3GSR0_GDQSPRD_MASK              (0x3FE0000U)
26437 #define DDRPHY_DX3GSR0_GDQSPRD_SHIFT             (17U)
26438 /*! GDQSPRD - Read DQS gating Period
26439  */
26440 #define DDRPHY_DX3GSR0_GDQSPRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX3GSR0_GDQSPRD_MASK)
26441 #define DDRPHY_DX3GSR0_RESERVED_29_26_MASK       (0x3C000000U)
26442 #define DDRPHY_DX3GSR0_RESERVED_29_26_SHIFT      (26U)
26443 /*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
26444  */
26445 #define DDRPHY_DX3GSR0_RESERVED_29_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX3GSR0_RESERVED_29_26_MASK)
26446 #define DDRPHY_DX3GSR0_WLDQ_MASK                 (0x40000000U)
26447 #define DDRPHY_DX3GSR0_WLDQ_SHIFT                (30U)
26448 /*! WLDQ - Write Leveling DQ Status
26449  */
26450 #define DDRPHY_DX3GSR0_WLDQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLDQ_SHIFT)) & DDRPHY_DX3GSR0_WLDQ_MASK)
26451 #define DDRPHY_DX3GSR0_RESERVED_31_MASK          (0x80000000U)
26452 #define DDRPHY_DX3GSR0_RESERVED_31_SHIFT         (31U)
26453 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
26454  */
26455 #define DDRPHY_DX3GSR0_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX3GSR0_RESERVED_31_MASK)
26456 /*! @} */
26457 
26458 /*! @name DX3GSR1 - DATX8 n General Status Register 1 */
26459 /*! @{ */
26460 #define DDRPHY_DX3GSR1_DLTDONE_MASK              (0x1U)
26461 #define DDRPHY_DX3GSR1_DLTDONE_SHIFT             (0U)
26462 /*! DLTDONE - Delay Line Test Done
26463  */
26464 #define DDRPHY_DX3GSR1_DLTDONE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR1_DLTDONE_SHIFT)) & DDRPHY_DX3GSR1_DLTDONE_MASK)
26465 #define DDRPHY_DX3GSR1_DLTCODE_MASK              (0x1FFFFFEU)
26466 #define DDRPHY_DX3GSR1_DLTCODE_SHIFT             (1U)
26467 /*! DLTCODE - Delay Line Test Code
26468  */
26469 #define DDRPHY_DX3GSR1_DLTCODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR1_DLTCODE_SHIFT)) & DDRPHY_DX3GSR1_DLTCODE_MASK)
26470 #define DDRPHY_DX3GSR1_RESERVED_31_25_MASK       (0xFE000000U)
26471 #define DDRPHY_DX3GSR1_RESERVED_31_25_SHIFT      (25U)
26472 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
26473  */
26474 #define DDRPHY_DX3GSR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX3GSR1_RESERVED_31_25_MASK)
26475 /*! @} */
26476 
26477 /*! @name DX3GSR2 - DATX8 n General Status Register 2 */
26478 /*! @{ */
26479 #define DDRPHY_DX3GSR2_RDERR_MASK                (0x1U)
26480 #define DDRPHY_DX3GSR2_RDERR_SHIFT               (0U)
26481 /*! RDERR - Read Bit Deskew Error
26482  */
26483 #define DDRPHY_DX3GSR2_RDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_RDERR_SHIFT)) & DDRPHY_DX3GSR2_RDERR_MASK)
26484 #define DDRPHY_DX3GSR2_RDWN_MASK                 (0x2U)
26485 #define DDRPHY_DX3GSR2_RDWN_SHIFT                (1U)
26486 /*! RDWN - Read Bit Deskew Warning
26487  */
26488 #define DDRPHY_DX3GSR2_RDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_RDWN_SHIFT)) & DDRPHY_DX3GSR2_RDWN_MASK)
26489 #define DDRPHY_DX3GSR2_WDERR_MASK                (0x4U)
26490 #define DDRPHY_DX3GSR2_WDERR_SHIFT               (2U)
26491 /*! WDERR - Write Bit Deskew Error
26492  */
26493 #define DDRPHY_DX3GSR2_WDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WDERR_SHIFT)) & DDRPHY_DX3GSR2_WDERR_MASK)
26494 #define DDRPHY_DX3GSR2_WDWN_MASK                 (0x8U)
26495 #define DDRPHY_DX3GSR2_WDWN_SHIFT                (3U)
26496 /*! WDWN - Write Bit Deskew Warning
26497  */
26498 #define DDRPHY_DX3GSR2_WDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WDWN_SHIFT)) & DDRPHY_DX3GSR2_WDWN_MASK)
26499 #define DDRPHY_DX3GSR2_REERR_MASK                (0x10U)
26500 #define DDRPHY_DX3GSR2_REERR_SHIFT               (4U)
26501 /*! REERR - Read Eye Centering Error
26502  */
26503 #define DDRPHY_DX3GSR2_REERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_REERR_SHIFT)) & DDRPHY_DX3GSR2_REERR_MASK)
26504 #define DDRPHY_DX3GSR2_REWN_MASK                 (0x20U)
26505 #define DDRPHY_DX3GSR2_REWN_SHIFT                (5U)
26506 /*! REWN - Read Eye Centering Warning
26507  */
26508 #define DDRPHY_DX3GSR2_REWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_REWN_SHIFT)) & DDRPHY_DX3GSR2_REWN_MASK)
26509 #define DDRPHY_DX3GSR2_WEERR_MASK                (0x40U)
26510 #define DDRPHY_DX3GSR2_WEERR_SHIFT               (6U)
26511 /*! WEERR - Write Eye Centering Error
26512  */
26513 #define DDRPHY_DX3GSR2_WEERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WEERR_SHIFT)) & DDRPHY_DX3GSR2_WEERR_MASK)
26514 #define DDRPHY_DX3GSR2_WEWN_MASK                 (0x80U)
26515 #define DDRPHY_DX3GSR2_WEWN_SHIFT                (7U)
26516 /*! WEWN - Write Eye Centering Warning
26517  */
26518 #define DDRPHY_DX3GSR2_WEWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WEWN_SHIFT)) & DDRPHY_DX3GSR2_WEWN_MASK)
26519 #define DDRPHY_DX3GSR2_ESTAT_MASK                (0xF00U)
26520 #define DDRPHY_DX3GSR2_ESTAT_SHIFT               (8U)
26521 /*! ESTAT - Error Status
26522  */
26523 #define DDRPHY_DX3GSR2_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_ESTAT_SHIFT)) & DDRPHY_DX3GSR2_ESTAT_MASK)
26524 #define DDRPHY_DX3GSR2_DQS2DQERR_MASK            (0xFF000U)
26525 #define DDRPHY_DX3GSR2_DQS2DQERR_SHIFT           (12U)
26526 /*! DQS2DQERR - Write DQS2DQ Training Error
26527  */
26528 #define DDRPHY_DX3GSR2_DQS2DQERR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX3GSR2_DQS2DQERR_MASK)
26529 #define DDRPHY_DX3GSR2_SRDERR_MASK               (0x100000U)
26530 #define DDRPHY_DX3GSR2_SRDERR_SHIFT              (20U)
26531 /*! SRDERR - Static Read Error
26532  */
26533 #define DDRPHY_DX3GSR2_SRDERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_SRDERR_SHIFT)) & DDRPHY_DX3GSR2_SRDERR_MASK)
26534 #define DDRPHY_DX3GSR2_RESERVED_21_MASK          (0x200000U)
26535 #define DDRPHY_DX3GSR2_RESERVED_21_SHIFT         (21U)
26536 /*! RESERVED_21 - Reserved. Return zeroes on reads.
26537  */
26538 #define DDRPHY_DX3GSR2_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX3GSR2_RESERVED_21_MASK)
26539 #define DDRPHY_DX3GSR2_GSDQSCAL_MASK             (0x400000U)
26540 #define DDRPHY_DX3GSR2_GSDQSCAL_SHIFT            (22U)
26541 /*! GSDQSCAL - Read DQS Gating Status Calibration
26542  */
26543 #define DDRPHY_DX3GSR2_GSDQSCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX3GSR2_GSDQSCAL_MASK)
26544 #define DDRPHY_DX3GSR2_GSDQSPRD_MASK             (0xFF800000U)
26545 #define DDRPHY_DX3GSR2_GSDQSPRD_SHIFT            (23U)
26546 /*! GSDQSPRD - Read DQS gating Status Period
26547  */
26548 #define DDRPHY_DX3GSR2_GSDQSPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX3GSR2_GSDQSPRD_MASK)
26549 /*! @} */
26550 
26551 /*! @name DX3GSR3 - DATX8 n General Status Register 3 */
26552 /*! @{ */
26553 #define DDRPHY_DX3GSR3_SRDPC_MASK                (0x3U)
26554 #define DDRPHY_DX3GSR3_SRDPC_SHIFT               (0U)
26555 /*! SRDPC - Static Read Delay Pass Count
26556  */
26557 #define DDRPHY_DX3GSR3_SRDPC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_SRDPC_SHIFT)) & DDRPHY_DX3GSR3_SRDPC_MASK)
26558 #define DDRPHY_DX3GSR3_RESERVED_7_2_MASK         (0xFCU)
26559 #define DDRPHY_DX3GSR3_RESERVED_7_2_SHIFT        (2U)
26560 /*! RESERVED_7_2 - Reserved. Return zeroes on reads.
26561  */
26562 #define DDRPHY_DX3GSR3_RESERVED_7_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX3GSR3_RESERVED_7_2_MASK)
26563 #define DDRPHY_DX3GSR3_HVERR_MASK                (0xF00U)
26564 #define DDRPHY_DX3GSR3_HVERR_SHIFT               (8U)
26565 /*! HVERR - Host VREF Training Error
26566  */
26567 #define DDRPHY_DX3GSR3_HVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_HVERR_SHIFT)) & DDRPHY_DX3GSR3_HVERR_MASK)
26568 #define DDRPHY_DX3GSR3_HVWRN_MASK                (0xF000U)
26569 #define DDRPHY_DX3GSR3_HVWRN_SHIFT               (12U)
26570 /*! HVWRN - Host VREF Training Warning
26571  */
26572 #define DDRPHY_DX3GSR3_HVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_HVWRN_SHIFT)) & DDRPHY_DX3GSR3_HVWRN_MASK)
26573 #define DDRPHY_DX3GSR3_DVERR_MASK                (0xF0000U)
26574 #define DDRPHY_DX3GSR3_DVERR_SHIFT               (16U)
26575 /*! DVERR - DRAM VREF Training Error
26576  */
26577 #define DDRPHY_DX3GSR3_DVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_DVERR_SHIFT)) & DDRPHY_DX3GSR3_DVERR_MASK)
26578 #define DDRPHY_DX3GSR3_DVWRN_MASK                (0xF00000U)
26579 #define DDRPHY_DX3GSR3_DVWRN_SHIFT               (20U)
26580 /*! DVWRN - DRAM VREF Training Warning
26581  */
26582 #define DDRPHY_DX3GSR3_DVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_DVWRN_SHIFT)) & DDRPHY_DX3GSR3_DVWRN_MASK)
26583 #define DDRPHY_DX3GSR3_ESTAT_MASK                (0x7000000U)
26584 #define DDRPHY_DX3GSR3_ESTAT_SHIFT               (24U)
26585 /*! ESTAT - VREF Training Error Status Code
26586  */
26587 #define DDRPHY_DX3GSR3_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_ESTAT_SHIFT)) & DDRPHY_DX3GSR3_ESTAT_MASK)
26588 #define DDRPHY_DX3GSR3_RESERVED_31_27_MASK       (0xF8000000U)
26589 #define DDRPHY_DX3GSR3_RESERVED_31_27_SHIFT      (27U)
26590 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
26591  */
26592 #define DDRPHY_DX3GSR3_RESERVED_31_27(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX3GSR3_RESERVED_31_27_MASK)
26593 /*! @} */
26594 
26595 /*! @name DX3GSR4 - DATX8 n General Status Register 4 */
26596 /*! @{ */
26597 #define DDRPHY_DX3GSR4_RESERVED_0_MASK           (0x1U)
26598 #define DDRPHY_DX3GSR4_RESERVED_0_SHIFT          (0U)
26599 /*! RESERVED_0 - Reserved. Return zeroes on reads.
26600  */
26601 #define DDRPHY_DX3GSR4_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_0_MASK)
26602 #define DDRPHY_DX3GSR4_RESERVED_1_MASK           (0x2U)
26603 #define DDRPHY_DX3GSR4_RESERVED_1_SHIFT          (1U)
26604 /*! RESERVED_1 - Reserved. Return zeroes on reads.
26605  */
26606 #define DDRPHY_DX3GSR4_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_1_MASK)
26607 #define DDRPHY_DX3GSR4_RESERVED_2_MASK           (0x4U)
26608 #define DDRPHY_DX3GSR4_RESERVED_2_SHIFT          (2U)
26609 /*! RESERVED_2 - Reserved. Return zeroes on reads.
26610  */
26611 #define DDRPHY_DX3GSR4_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_2_MASK)
26612 #define DDRPHY_DX3GSR4_RESERVED_3_MASK           (0x8U)
26613 #define DDRPHY_DX3GSR4_RESERVED_3_SHIFT          (3U)
26614 /*! RESERVED_3 - Reserved. Return zeroes on reads.
26615  */
26616 #define DDRPHY_DX3GSR4_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_3_MASK)
26617 #define DDRPHY_DX3GSR4_RESERVED_4_MASK           (0x10U)
26618 #define DDRPHY_DX3GSR4_RESERVED_4_SHIFT          (4U)
26619 /*! RESERVED_4 - Reserved. Return zeroes on reads.
26620  */
26621 #define DDRPHY_DX3GSR4_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_4_MASK)
26622 #define DDRPHY_DX3GSR4_RESERVED_5_MASK           (0x20U)
26623 #define DDRPHY_DX3GSR4_RESERVED_5_SHIFT          (5U)
26624 /*! RESERVED_5 - Reserved. Return zeroes on reads.
26625  */
26626 #define DDRPHY_DX3GSR4_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_5_MASK)
26627 #define DDRPHY_DX3GSR4_RESERVED_6_MASK           (0x40U)
26628 #define DDRPHY_DX3GSR4_RESERVED_6_SHIFT          (6U)
26629 /*! RESERVED_6 - Reserved. Return zeroes on reads.
26630  */
26631 #define DDRPHY_DX3GSR4_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_6_MASK)
26632 #define DDRPHY_DX3GSR4_RESERVED_15_7_MASK        (0xFF80U)
26633 #define DDRPHY_DX3GSR4_RESERVED_15_7_SHIFT       (7U)
26634 /*! RESERVED_15_7 - Reserved. Return zeroes on reads.
26635  */
26636 #define DDRPHY_DX3GSR4_RESERVED_15_7(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_15_7_MASK)
26637 #define DDRPHY_DX3GSR4_RESERVED_16_MASK          (0x10000U)
26638 #define DDRPHY_DX3GSR4_RESERVED_16_SHIFT         (16U)
26639 /*! RESERVED_16 - Reserved. Return zeroes on reads.
26640  */
26641 #define DDRPHY_DX3GSR4_RESERVED_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_16_MASK)
26642 #define DDRPHY_DX3GSR4_RESERVED_25_17_MASK       (0x3FE0000U)
26643 #define DDRPHY_DX3GSR4_RESERVED_25_17_SHIFT      (17U)
26644 /*! RESERVED_25_17 - Reserved. Return zeroes on reads.
26645  */
26646 #define DDRPHY_DX3GSR4_RESERVED_25_17(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_25_17_MASK)
26647 #define DDRPHY_DX3GSR4_RESERVED_31_26_MASK       (0xFC000000U)
26648 #define DDRPHY_DX3GSR4_RESERVED_31_26_SHIFT      (26U)
26649 /*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
26650  */
26651 #define DDRPHY_DX3GSR4_RESERVED_31_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_31_26_MASK)
26652 /*! @} */
26653 
26654 /*! @name DX3GSR5 - DATX8 n General Status Register 5 */
26655 /*! @{ */
26656 #define DDRPHY_DX3GSR5_RESERVED_0_MASK           (0x1U)
26657 #define DDRPHY_DX3GSR5_RESERVED_0_SHIFT          (0U)
26658 /*! RESERVED_0 - Reserved. Return zeroes on reads.
26659  */
26660 #define DDRPHY_DX3GSR5_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_0_MASK)
26661 #define DDRPHY_DX3GSR5_RESERVED_1_MASK           (0x2U)
26662 #define DDRPHY_DX3GSR5_RESERVED_1_SHIFT          (1U)
26663 /*! RESERVED_1 - Reserved. Return zeroes on reads.
26664  */
26665 #define DDRPHY_DX3GSR5_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_1_MASK)
26666 #define DDRPHY_DX3GSR5_RESERVED_2_MASK           (0x4U)
26667 #define DDRPHY_DX3GSR5_RESERVED_2_SHIFT          (2U)
26668 /*! RESERVED_2 - Reserved. Return zeroes on reads.
26669  */
26670 #define DDRPHY_DX3GSR5_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_2_MASK)
26671 #define DDRPHY_DX3GSR5_RESERVED_3_MASK           (0x8U)
26672 #define DDRPHY_DX3GSR5_RESERVED_3_SHIFT          (3U)
26673 /*! RESERVED_3 - Reserved. Return zeroes on reads.
26674  */
26675 #define DDRPHY_DX3GSR5_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_3_MASK)
26676 #define DDRPHY_DX3GSR5_RESERVED_4_MASK           (0x10U)
26677 #define DDRPHY_DX3GSR5_RESERVED_4_SHIFT          (4U)
26678 /*! RESERVED_4 - Reserved. Return zeroes on reads.
26679  */
26680 #define DDRPHY_DX3GSR5_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_4_MASK)
26681 #define DDRPHY_DX3GSR5_RESERVED_5_MASK           (0x20U)
26682 #define DDRPHY_DX3GSR5_RESERVED_5_SHIFT          (5U)
26683 /*! RESERVED_5 - Reserved. Return zeroes on reads.
26684  */
26685 #define DDRPHY_DX3GSR5_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_5_MASK)
26686 #define DDRPHY_DX3GSR5_RESERVED_6_MASK           (0x40U)
26687 #define DDRPHY_DX3GSR5_RESERVED_6_SHIFT          (6U)
26688 /*! RESERVED_6 - Reserved. Return zeroes on reads.
26689  */
26690 #define DDRPHY_DX3GSR5_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_6_MASK)
26691 #define DDRPHY_DX3GSR5_RESERVED_7_MASK           (0x80U)
26692 #define DDRPHY_DX3GSR5_RESERVED_7_SHIFT          (7U)
26693 /*! RESERVED_7 - Reserved. Return zeroes on reads.
26694  */
26695 #define DDRPHY_DX3GSR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_7_MASK)
26696 #define DDRPHY_DX3GSR5_RESERVED_11_8_MASK        (0xF00U)
26697 #define DDRPHY_DX3GSR5_RESERVED_11_8_SHIFT       (8U)
26698 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
26699  */
26700 #define DDRPHY_DX3GSR5_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_11_8_MASK)
26701 #define DDRPHY_DX3GSR5_RESERVED_19_12_MASK       (0xFF000U)
26702 #define DDRPHY_DX3GSR5_RESERVED_19_12_SHIFT      (12U)
26703 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
26704  */
26705 #define DDRPHY_DX3GSR5_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_19_12_MASK)
26706 #define DDRPHY_DX3GSR5_RESERVED_20_MASK          (0x100000U)
26707 #define DDRPHY_DX3GSR5_RESERVED_20_SHIFT         (20U)
26708 /*! RESERVED_20 - Reserved. Return zeroes on reads.
26709  */
26710 #define DDRPHY_DX3GSR5_RESERVED_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_20_MASK)
26711 #define DDRPHY_DX3GSR5_RESERVED_21_MASK          (0x200000U)
26712 #define DDRPHY_DX3GSR5_RESERVED_21_SHIFT         (21U)
26713 /*! RESERVED_21 - Reserved. Return zeroes on reads.
26714  */
26715 #define DDRPHY_DX3GSR5_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_21_MASK)
26716 #define DDRPHY_DX3GSR5_RESERVED_22_MASK          (0x400000U)
26717 #define DDRPHY_DX3GSR5_RESERVED_22_SHIFT         (22U)
26718 /*! RESERVED_22 - Reserved. Return zeroes on reads.
26719  */
26720 #define DDRPHY_DX3GSR5_RESERVED_22(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_22_MASK)
26721 #define DDRPHY_DX3GSR5_RESERVED_31_23_MASK       (0xFF800000U)
26722 #define DDRPHY_DX3GSR5_RESERVED_31_23_SHIFT      (23U)
26723 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
26724  */
26725 #define DDRPHY_DX3GSR5_RESERVED_31_23(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_31_23_MASK)
26726 /*! @} */
26727 
26728 /*! @name DX3GSR6 - DATX8 n General Status Register 6 */
26729 /*! @{ */
26730 #define DDRPHY_DX3GSR6_RESERVED_1_0_MASK         (0x3U)
26731 #define DDRPHY_DX3GSR6_RESERVED_1_0_SHIFT        (0U)
26732 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
26733  */
26734 #define DDRPHY_DX3GSR6_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_1_0_MASK)
26735 #define DDRPHY_DX3GSR6_RESERVED_3_2_MASK         (0xCU)
26736 #define DDRPHY_DX3GSR6_RESERVED_3_2_SHIFT        (2U)
26737 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
26738  */
26739 #define DDRPHY_DX3GSR6_RESERVED_3_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_3_2_MASK)
26740 #define DDRPHY_DX3GSR6_RESERVED_7_4_MASK         (0xF0U)
26741 #define DDRPHY_DX3GSR6_RESERVED_7_4_SHIFT        (4U)
26742 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
26743  */
26744 #define DDRPHY_DX3GSR6_RESERVED_7_4(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_7_4_MASK)
26745 #define DDRPHY_DX3GSR6_RESERVED_11_8_MASK        (0xF00U)
26746 #define DDRPHY_DX3GSR6_RESERVED_11_8_SHIFT       (8U)
26747 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
26748  */
26749 #define DDRPHY_DX3GSR6_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_11_8_MASK)
26750 #define DDRPHY_DX3GSR6_RESERVED_15_12_MASK       (0xF000U)
26751 #define DDRPHY_DX3GSR6_RESERVED_15_12_SHIFT      (12U)
26752 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
26753  */
26754 #define DDRPHY_DX3GSR6_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_15_12_MASK)
26755 #define DDRPHY_DX3GSR6_RESERVED_19_15_MASK       (0xF0000U)
26756 #define DDRPHY_DX3GSR6_RESERVED_19_15_SHIFT      (16U)
26757 /*! RESERVED_19_15 - Reserved. Return zeroes on reads.
26758  */
26759 #define DDRPHY_DX3GSR6_RESERVED_19_15(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_19_15_MASK)
26760 #define DDRPHY_DX3GSR6_RESERVED_23_20_MASK       (0xF00000U)
26761 #define DDRPHY_DX3GSR6_RESERVED_23_20_SHIFT      (20U)
26762 /*! RESERVED_23_20 - Reserved. Return zeroes on reads.
26763  */
26764 #define DDRPHY_DX3GSR6_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_23_20_MASK)
26765 #define DDRPHY_DX3GSR6_RESERVED_31_24_MASK       (0xFF000000U)
26766 #define DDRPHY_DX3GSR6_RESERVED_31_24_SHIFT      (24U)
26767 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
26768  */
26769 #define DDRPHY_DX3GSR6_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_31_24_MASK)
26770 /*! @} */
26771 
26772 /*! @name DX4GCR0 - DATX8 n General Configuration Register 0 */
26773 /*! @{ */
26774 #define DDRPHY_DX4GCR0_RESERVED_1_0_MASK         (0x3U)
26775 #define DDRPHY_DX4GCR0_RESERVED_1_0_SHIFT        (0U)
26776 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
26777  */
26778 #define DDRPHY_DX4GCR0_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX4GCR0_RESERVED_1_0_MASK)
26779 #define DDRPHY_DX4GCR0_DQSGOE_MASK               (0x4U)
26780 #define DDRPHY_DX4GCR0_DQSGOE_SHIFT              (2U)
26781 /*! DQSGOE - DQSG Output Enable
26782  */
26783 #define DDRPHY_DX4GCR0_DQSGOE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSGOE_SHIFT)) & DDRPHY_DX4GCR0_DQSGOE_MASK)
26784 #define DDRPHY_DX4GCR0_DQSGODT_MASK              (0x8U)
26785 #define DDRPHY_DX4GCR0_DQSGODT_SHIFT             (3U)
26786 /*! DQSGODT - DQSG On-Die Termination
26787  */
26788 #define DDRPHY_DX4GCR0_DQSGODT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSGODT_SHIFT)) & DDRPHY_DX4GCR0_DQSGODT_MASK)
26789 #define DDRPHY_DX4GCR0_RESERVED_4_MASK           (0x10U)
26790 #define DDRPHY_DX4GCR0_RESERVED_4_SHIFT          (4U)
26791 /*! RESERVED_4 - Reserved. Return zeroes on reads.
26792  */
26793 #define DDRPHY_DX4GCR0_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX4GCR0_RESERVED_4_MASK)
26794 #define DDRPHY_DX4GCR0_DQSGPDR_MASK              (0x20U)
26795 #define DDRPHY_DX4GCR0_DQSGPDR_SHIFT             (5U)
26796 /*! DQSGPDR - DQSG Power Down Receiver
26797  */
26798 #define DDRPHY_DX4GCR0_DQSGPDR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX4GCR0_DQSGPDR_MASK)
26799 #define DDRPHY_DX4GCR0_DQSRPD_MASK               (0x40U)
26800 #define DDRPHY_DX4GCR0_DQSRPD_SHIFT              (6U)
26801 /*! DQSRPD - DQSR Power Down
26802  */
26803 #define DDRPHY_DX4GCR0_DQSRPD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSRPD_SHIFT)) & DDRPHY_DX4GCR0_DQSRPD_MASK)
26804 #define DDRPHY_DX4GCR0_CPDRSHFT_MASK             (0x180U)
26805 #define DDRPHY_DX4GCR0_CPDRSHFT_SHIFT            (7U)
26806 /*! CPDRSHFT - Configurable PDR Phase Shift
26807  */
26808 #define DDRPHY_DX4GCR0_CPDRSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX4GCR0_CPDRSHFT_MASK)
26809 #define DDRPHY_DX4GCR0_RTTOH_MASK                (0x600U)
26810 #define DDRPHY_DX4GCR0_RTTOH_SHIFT               (9U)
26811 /*! RTTOH - RTT Output Hold
26812  */
26813 #define DDRPHY_DX4GCR0_RTTOH(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RTTOH_SHIFT)) & DDRPHY_DX4GCR0_RTTOH_MASK)
26814 #define DDRPHY_DX4GCR0_RTTOAL_MASK               (0x800U)
26815 #define DDRPHY_DX4GCR0_RTTOAL_SHIFT              (11U)
26816 /*! RTTOAL - RTT On Additive Latency
26817  */
26818 #define DDRPHY_DX4GCR0_RTTOAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RTTOAL_SHIFT)) & DDRPHY_DX4GCR0_RTTOAL_MASK)
26819 #define DDRPHY_DX4GCR0_DQSSEPDR_MASK             (0x1000U)
26820 #define DDRPHY_DX4GCR0_DQSSEPDR_SHIFT            (12U)
26821 /*! DQSSEPDR - DQSSE Power Down Receiver
26822  */
26823 #define DDRPHY_DX4GCR0_DQSSEPDR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX4GCR0_DQSSEPDR_MASK)
26824 #define DDRPHY_DX4GCR0_DQSNSEPDR_MASK            (0x2000U)
26825 #define DDRPHY_DX4GCR0_DQSNSEPDR_SHIFT           (13U)
26826 /*! DQSNSEPDR - DQSNSE Power Down Receiver
26827  */
26828 #define DDRPHY_DX4GCR0_DQSNSEPDR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX4GCR0_DQSNSEPDR_MASK)
26829 #define DDRPHY_DX4GCR0_RESERVED_19_14_MASK       (0xFC000U)
26830 #define DDRPHY_DX4GCR0_RESERVED_19_14_SHIFT      (14U)
26831 /*! RESERVED_19_14 - Reserved. Return zeroes on reads.
26832  */
26833 #define DDRPHY_DX4GCR0_RESERVED_19_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX4GCR0_RESERVED_19_14_MASK)
26834 #define DDRPHY_DX4GCR0_RDDLY_MASK                (0xF00000U)
26835 #define DDRPHY_DX4GCR0_RDDLY_SHIFT               (20U)
26836 /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
26837  */
26838 #define DDRPHY_DX4GCR0_RDDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RDDLY_SHIFT)) & DDRPHY_DX4GCR0_RDDLY_MASK)
26839 #define DDRPHY_DX4GCR0_DQSDCC_MASK               (0xF000000U)
26840 #define DDRPHY_DX4GCR0_DQSDCC_SHIFT              (24U)
26841 /*! DQSDCC - DQS Duty Cycle Correction
26842  */
26843 #define DDRPHY_DX4GCR0_DQSDCC(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSDCC_SHIFT)) & DDRPHY_DX4GCR0_DQSDCC_MASK)
26844 #define DDRPHY_DX4GCR0_CODTSHFT_MASK             (0x30000000U)
26845 #define DDRPHY_DX4GCR0_CODTSHFT_SHIFT            (28U)
26846 /*! CODTSHFT - Configurable ODT(TE) Phase Shift
26847  */
26848 #define DDRPHY_DX4GCR0_CODTSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX4GCR0_CODTSHFT_MASK)
26849 #define DDRPHY_DX4GCR0_MDLEN_MASK                (0x40000000U)
26850 #define DDRPHY_DX4GCR0_MDLEN_SHIFT               (30U)
26851 /*! MDLEN - Master Delay Line Enable
26852  */
26853 #define DDRPHY_DX4GCR0_MDLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_MDLEN_SHIFT)) & DDRPHY_DX4GCR0_MDLEN_MASK)
26854 #define DDRPHY_DX4GCR0_CALBYP_MASK               (0x80000000U)
26855 #define DDRPHY_DX4GCR0_CALBYP_SHIFT              (31U)
26856 /*! CALBYP - Calibration Bypass
26857  */
26858 #define DDRPHY_DX4GCR0_CALBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_CALBYP_SHIFT)) & DDRPHY_DX4GCR0_CALBYP_MASK)
26859 /*! @} */
26860 
26861 /*! @name DX4GCR1 - DATX8 n General Configuration Register 1 */
26862 /*! @{ */
26863 #define DDRPHY_DX4GCR1_DQEN_MASK                 (0xFFU)
26864 #define DDRPHY_DX4GCR1_DQEN_SHIFT                (0U)
26865 /*! DQEN - Enables DQ corresponding to each bit in a byte
26866  */
26867 #define DDRPHY_DX4GCR1_DQEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DQEN_SHIFT)) & DDRPHY_DX4GCR1_DQEN_MASK)
26868 #define DDRPHY_DX4GCR1_DMEN_MASK                 (0x100U)
26869 #define DDRPHY_DX4GCR1_DMEN_SHIFT                (8U)
26870 /*! DMEN - Enables DM pin in a byte lane
26871  */
26872 #define DDRPHY_DX4GCR1_DMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DMEN_SHIFT)) & DDRPHY_DX4GCR1_DMEN_MASK)
26873 #define DDRPHY_DX4GCR1_DSEN_MASK                 (0x200U)
26874 #define DDRPHY_DX4GCR1_DSEN_SHIFT                (9U)
26875 /*! DSEN - Enables Write Data strobe in a byte lane
26876  */
26877 #define DDRPHY_DX4GCR1_DSEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DSEN_SHIFT)) & DDRPHY_DX4GCR1_DSEN_MASK)
26878 #define DDRPHY_DX4GCR1_TEEN_MASK                 (0x400U)
26879 #define DDRPHY_DX4GCR1_TEEN_SHIFT                (10U)
26880 /*! TEEN - Enables ODT/TE in a byte lane
26881  */
26882 #define DDRPHY_DX4GCR1_TEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_TEEN_SHIFT)) & DDRPHY_DX4GCR1_TEEN_MASK)
26883 #define DDRPHY_DX4GCR1_PDREN_MASK                (0x800U)
26884 #define DDRPHY_DX4GCR1_PDREN_SHIFT               (11U)
26885 /*! PDREN - Enables PDR in a byte lane
26886  */
26887 #define DDRPHY_DX4GCR1_PDREN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_PDREN_SHIFT)) & DDRPHY_DX4GCR1_PDREN_MASK)
26888 #define DDRPHY_DX4GCR1_OEEN_MASK                 (0x1000U)
26889 #define DDRPHY_DX4GCR1_OEEN_SHIFT                (12U)
26890 /*! OEEN - Enables Read Data Strobe in a byte lane
26891  */
26892 #define DDRPHY_DX4GCR1_OEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_OEEN_SHIFT)) & DDRPHY_DX4GCR1_OEEN_MASK)
26893 #define DDRPHY_DX4GCR1_QSSEL_MASK                (0x2000U)
26894 #define DDRPHY_DX4GCR1_QSSEL_SHIFT               (13U)
26895 /*! QSSEL - Select the delayed or non-delayed read data strobe
26896  */
26897 #define DDRPHY_DX4GCR1_QSSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_QSSEL_SHIFT)) & DDRPHY_DX4GCR1_QSSEL_MASK)
26898 #define DDRPHY_DX4GCR1_QSNSEL_MASK               (0x4000U)
26899 #define DDRPHY_DX4GCR1_QSNSEL_SHIFT              (14U)
26900 /*! QSNSEL - Select the delayed or non-delayed read data strobe #
26901  */
26902 #define DDRPHY_DX4GCR1_QSNSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_QSNSEL_SHIFT)) & DDRPHY_DX4GCR1_QSNSEL_MASK)
26903 #define DDRPHY_DX4GCR1_RESERVED_15_MASK          (0x8000U)
26904 #define DDRPHY_DX4GCR1_RESERVED_15_SHIFT         (15U)
26905 /*! RESERVED_15 - Reserved. Returns zeroes on reads.
26906  */
26907 #define DDRPHY_DX4GCR1_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX4GCR1_RESERVED_15_MASK)
26908 #define DDRPHY_DX4GCR1_DXPDRMODE_MASK            (0xFFFF0000U)
26909 #define DDRPHY_DX4GCR1_DXPDRMODE_SHIFT           (16U)
26910 /*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
26911  */
26912 #define DDRPHY_DX4GCR1_DXPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX4GCR1_DXPDRMODE_MASK)
26913 /*! @} */
26914 
26915 /*! @name DX4GCR2 - DATX8 n General Configuration Register 2 */
26916 /*! @{ */
26917 #define DDRPHY_DX4GCR2_DXTEMODE_MASK             (0xFFFFU)
26918 #define DDRPHY_DX4GCR2_DXTEMODE_SHIFT            (0U)
26919 /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
26920  */
26921 #define DDRPHY_DX4GCR2_DXTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX4GCR2_DXTEMODE_MASK)
26922 #define DDRPHY_DX4GCR2_DXOEMODE_MASK             (0xFFFF0000U)
26923 #define DDRPHY_DX4GCR2_DXOEMODE_SHIFT            (16U)
26924 /*! DXOEMODE - Enables the OE mode values for DQ[7:0]
26925  */
26926 #define DDRPHY_DX4GCR2_DXOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX4GCR2_DXOEMODE_MASK)
26927 /*! @} */
26928 
26929 /*! @name DX4GCR3 - DATX8 n General Configuration Register 3 */
26930 /*! @{ */
26931 #define DDRPHY_DX4GCR3_WDMBVT_MASK               (0x1U)
26932 #define DDRPHY_DX4GCR3_WDMBVT_SHIFT              (0U)
26933 /*! WDMBVT - Write Data Mask BDL VT Compensation
26934  */
26935 #define DDRPHY_DX4GCR3_WDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDMBVT_SHIFT)) & DDRPHY_DX4GCR3_WDMBVT_MASK)
26936 #define DDRPHY_DX4GCR3_RDMBVT_MASK               (0x2U)
26937 #define DDRPHY_DX4GCR3_RDMBVT_SHIFT              (1U)
26938 /*! RDMBVT - Read Data Mask BDL VT Compensation
26939  */
26940 #define DDRPHY_DX4GCR3_RDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RDMBVT_SHIFT)) & DDRPHY_DX4GCR3_RDMBVT_MASK)
26941 #define DDRPHY_DX4GCR3_DSPDRMODE_MASK            (0xCU)
26942 #define DDRPHY_DX4GCR3_DSPDRMODE_SHIFT           (2U)
26943 /*! DSPDRMODE - Enables the PDR mode values for DQS.
26944  */
26945 #define DDRPHY_DX4GCR3_DSPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX4GCR3_DSPDRMODE_MASK)
26946 #define DDRPHY_DX4GCR3_DSTEMODE_MASK             (0x30U)
26947 #define DDRPHY_DX4GCR3_DSTEMODE_SHIFT            (4U)
26948 /*! DSTEMODE - Enables the TE mode values for DQS.
26949  */
26950 #define DDRPHY_DX4GCR3_DSTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSTEMODE_MASK)
26951 #define DDRPHY_DX4GCR3_DSOEMODE_MASK             (0xC0U)
26952 #define DDRPHY_DX4GCR3_DSOEMODE_SHIFT            (6U)
26953 /*! DSOEMODE - Enables the OE mode values for DQS.
26954  */
26955 #define DDRPHY_DX4GCR3_DSOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSOEMODE_MASK)
26956 #define DDRPHY_DX4GCR3_WDSBVT_MASK               (0x100U)
26957 #define DDRPHY_DX4GCR3_WDSBVT_SHIFT              (8U)
26958 /*! WDSBVT - Write Data Strobe BDL VT Compensation
26959  */
26960 #define DDRPHY_DX4GCR3_WDSBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDSBVT_SHIFT)) & DDRPHY_DX4GCR3_WDSBVT_MASK)
26961 #define DDRPHY_DX4GCR3_RESERVED_9_MASK           (0x200U)
26962 #define DDRPHY_DX4GCR3_RESERVED_9_SHIFT          (9U)
26963 /*! RESERVED_9 - Reserved. Returns zeroes on reads.
26964  */
26965 #define DDRPHY_DX4GCR3_RESERVED_9(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX4GCR3_RESERVED_9_MASK)
26966 #define DDRPHY_DX4GCR3_DMPDRMODE_MASK            (0xC00U)
26967 #define DDRPHY_DX4GCR3_DMPDRMODE_SHIFT           (10U)
26968 /*! DMPDRMODE - Enables the PDR mode values for DM.
26969  */
26970 #define DDRPHY_DX4GCR3_DMPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX4GCR3_DMPDRMODE_MASK)
26971 #define DDRPHY_DX4GCR3_DMTEMODE_MASK             (0x3000U)
26972 #define DDRPHY_DX4GCR3_DMTEMODE_SHIFT            (12U)
26973 /*! DMTEMODE - Enables the TE mode values for DM.
26974  */
26975 #define DDRPHY_DX4GCR3_DMTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX4GCR3_DMTEMODE_MASK)
26976 #define DDRPHY_DX4GCR3_DMOEMODE_MASK             (0xC000U)
26977 #define DDRPHY_DX4GCR3_DMOEMODE_SHIFT            (14U)
26978 /*! DMOEMODE - Enables the OE mode values for DM.
26979  */
26980 #define DDRPHY_DX4GCR3_DMOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX4GCR3_DMOEMODE_MASK)
26981 #define DDRPHY_DX4GCR3_DSNPDRMODE_MASK           (0x30000U)
26982 #define DDRPHY_DX4GCR3_DSNPDRMODE_SHIFT          (16U)
26983 /*! DSNPDRMODE - Enables the PDR mode for DQS
26984  */
26985 #define DDRPHY_DX4GCR3_DSNPDRMODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX4GCR3_DSNPDRMODE_MASK)
26986 #define DDRPHY_DX4GCR3_DSNTEMODE_MASK            (0xC0000U)
26987 #define DDRPHY_DX4GCR3_DSNTEMODE_SHIFT           (18U)
26988 /*! DSNTEMODE - Enables the TE mode for DQS
26989  */
26990 #define DDRPHY_DX4GCR3_DSNTEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSNTEMODE_MASK)
26991 #define DDRPHY_DX4GCR3_DSNOEMODE_MASK            (0x300000U)
26992 #define DDRPHY_DX4GCR3_DSNOEMODE_SHIFT           (20U)
26993 /*! DSNOEMODE - Enables the OE mode for DQs
26994  */
26995 #define DDRPHY_DX4GCR3_DSNOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSNOEMODE_MASK)
26996 #define DDRPHY_DX4GCR3_PDRBVT_MASK               (0x400000U)
26997 #define DDRPHY_DX4GCR3_PDRBVT_SHIFT              (22U)
26998 /*! PDRBVT - Power Down Receiver BDL VT Compensation
26999  */
27000 #define DDRPHY_DX4GCR3_PDRBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_PDRBVT_SHIFT)) & DDRPHY_DX4GCR3_PDRBVT_MASK)
27001 #define DDRPHY_DX4GCR3_RGSLVT_MASK               (0x800000U)
27002 #define DDRPHY_DX4GCR3_RGSLVT_SHIFT              (23U)
27003 /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
27004  */
27005 #define DDRPHY_DX4GCR3_RGSLVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RGSLVT_SHIFT)) & DDRPHY_DX4GCR3_RGSLVT_MASK)
27006 #define DDRPHY_DX4GCR3_WLLVT_MASK                (0x1000000U)
27007 #define DDRPHY_DX4GCR3_WLLVT_SHIFT               (24U)
27008 /*! WLLVT - Write Leveling LCDL Delay VT Compensation
27009  */
27010 #define DDRPHY_DX4GCR3_WLLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WLLVT_SHIFT)) & DDRPHY_DX4GCR3_WLLVT_MASK)
27011 #define DDRPHY_DX4GCR3_WDLVT_MASK                (0x2000000U)
27012 #define DDRPHY_DX4GCR3_WDLVT_SHIFT               (25U)
27013 /*! WDLVT - Write DQ LCDL Delay VT Compensation
27014  */
27015 #define DDRPHY_DX4GCR3_WDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDLVT_SHIFT)) & DDRPHY_DX4GCR3_WDLVT_MASK)
27016 #define DDRPHY_DX4GCR3_RDLVT_MASK                (0x4000000U)
27017 #define DDRPHY_DX4GCR3_RDLVT_SHIFT               (26U)
27018 /*! RDLVT - Read DQS LCDL Delay VT Compensation
27019  */
27020 #define DDRPHY_DX4GCR3_RDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RDLVT_SHIFT)) & DDRPHY_DX4GCR3_RDLVT_MASK)
27021 #define DDRPHY_DX4GCR3_RGLVT_MASK                (0x8000000U)
27022 #define DDRPHY_DX4GCR3_RGLVT_SHIFT               (27U)
27023 /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
27024  */
27025 #define DDRPHY_DX4GCR3_RGLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RGLVT_SHIFT)) & DDRPHY_DX4GCR3_RGLVT_MASK)
27026 #define DDRPHY_DX4GCR3_WDBVT_MASK                (0x10000000U)
27027 #define DDRPHY_DX4GCR3_WDBVT_SHIFT               (28U)
27028 /*! WDBVT - Write Data BDL VT Compensation
27029  */
27030 #define DDRPHY_DX4GCR3_WDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDBVT_SHIFT)) & DDRPHY_DX4GCR3_WDBVT_MASK)
27031 #define DDRPHY_DX4GCR3_RDBVT_MASK                (0x20000000U)
27032 #define DDRPHY_DX4GCR3_RDBVT_SHIFT               (29U)
27033 /*! RDBVT - Read Data BDL VT Compensation
27034  */
27035 #define DDRPHY_DX4GCR3_RDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RDBVT_SHIFT)) & DDRPHY_DX4GCR3_RDBVT_MASK)
27036 #define DDRPHY_DX4GCR3_TEBVT_MASK                (0x40000000U)
27037 #define DDRPHY_DX4GCR3_TEBVT_SHIFT               (30U)
27038 /*! TEBVT - Termination Enable BDL VT Compensation
27039  */
27040 #define DDRPHY_DX4GCR3_TEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_TEBVT_SHIFT)) & DDRPHY_DX4GCR3_TEBVT_MASK)
27041 #define DDRPHY_DX4GCR3_OEBVT_MASK                (0x80000000U)
27042 #define DDRPHY_DX4GCR3_OEBVT_SHIFT               (31U)
27043 /*! OEBVT - Output Enable BDL VT Compensation
27044  */
27045 #define DDRPHY_DX4GCR3_OEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_OEBVT_SHIFT)) & DDRPHY_DX4GCR3_OEBVT_MASK)
27046 /*! @} */
27047 
27048 /*! @name DX4GCR4 - DATX8 n General Configuration Register 4 */
27049 /*! @{ */
27050 #define DDRPHY_DX4GCR4_DXREFIMON_MASK            (0x3U)
27051 #define DDRPHY_DX4GCR4_DXREFIMON_SHIFT           (0U)
27052 /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
27053  */
27054 #define DDRPHY_DX4GCR4_DXREFIMON(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX4GCR4_DXREFIMON_MASK)
27055 #define DDRPHY_DX4GCR4_DXREFIEN_MASK             (0x3CU)
27056 #define DDRPHY_DX4GCR4_DXREFIEN_SHIFT            (2U)
27057 /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
27058  */
27059 #define DDRPHY_DX4GCR4_DXREFIEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFIEN_MASK)
27060 #define DDRPHY_DX4GCR4_RESERVED_7_6_MASK         (0xC0U)
27061 #define DDRPHY_DX4GCR4_RESERVED_7_6_SHIFT        (6U)
27062 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
27063  */
27064 #define DDRPHY_DX4GCR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR4_RESERVED_7_6_MASK)
27065 #define DDRPHY_DX4GCR4_DXREFSSEL_MASK            (0x7F00U)
27066 #define DDRPHY_DX4GCR4_DXREFSSEL_SHIFT           (8U)
27067 /*! DXREFSSEL - Byte Lane Single-End VREF Select
27068  */
27069 #define DDRPHY_DX4GCR4_DXREFSSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX4GCR4_DXREFSSEL_MASK)
27070 #define DDRPHY_DX4GCR4_DXREFSSELRANGE_MASK       (0x8000U)
27071 #define DDRPHY_DX4GCR4_DXREFSSELRANGE_SHIFT      (15U)
27072 /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
27073  */
27074 #define DDRPHY_DX4GCR4_DXREFSSELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX4GCR4_DXREFSSELRANGE_MASK)
27075 #define DDRPHY_DX4GCR4_DXREFESEL_MASK            (0x7F0000U)
27076 #define DDRPHY_DX4GCR4_DXREFESEL_SHIFT           (16U)
27077 /*! DXREFESEL - Byte Lane External VREF Select
27078  */
27079 #define DDRPHY_DX4GCR4_DXREFESEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX4GCR4_DXREFESEL_MASK)
27080 #define DDRPHY_DX4GCR4_DXREFESELRANGE_MASK       (0x800000U)
27081 #define DDRPHY_DX4GCR4_DXREFESELRANGE_SHIFT      (23U)
27082 /*! DXREFESELRANGE - External VREF generator REFSEL range select
27083  */
27084 #define DDRPHY_DX4GCR4_DXREFESELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX4GCR4_DXREFESELRANGE_MASK)
27085 #define DDRPHY_DX4GCR4_RESERVED_24_MASK          (0x1000000U)
27086 #define DDRPHY_DX4GCR4_RESERVED_24_SHIFT         (24U)
27087 /*! RESERVED_24 - Reserved. Returns zeros on reads.
27088  */
27089 #define DDRPHY_DX4GCR4_RESERVED_24(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX4GCR4_RESERVED_24_MASK)
27090 #define DDRPHY_DX4GCR4_DXREFSEN_MASK             (0x2000000U)
27091 #define DDRPHY_DX4GCR4_DXREFSEN_SHIFT            (25U)
27092 /*! DXREFSEN - Byte Lane Single-End VREF Enable
27093  */
27094 #define DDRPHY_DX4GCR4_DXREFSEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFSEN_MASK)
27095 #define DDRPHY_DX4GCR4_DXREFEEN_MASK             (0xC000000U)
27096 #define DDRPHY_DX4GCR4_DXREFEEN_SHIFT            (26U)
27097 /*! DXREFEEN - Byte Lane Internal VREF Enable
27098  */
27099 #define DDRPHY_DX4GCR4_DXREFEEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFEEN_MASK)
27100 #define DDRPHY_DX4GCR4_DXREFPEN_MASK             (0x10000000U)
27101 #define DDRPHY_DX4GCR4_DXREFPEN_SHIFT            (28U)
27102 /*! DXREFPEN - Byte Lane VREF Pad Enable
27103  */
27104 #define DDRPHY_DX4GCR4_DXREFPEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFPEN_MASK)
27105 #define DDRPHY_DX4GCR4_RESERVED_31_29_MASK       (0xE0000000U)
27106 #define DDRPHY_DX4GCR4_RESERVED_31_29_SHIFT      (29U)
27107 /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
27108  */
27109 #define DDRPHY_DX4GCR4_RESERVED_31_29(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX4GCR4_RESERVED_31_29_MASK)
27110 /*! @} */
27111 
27112 /*! @name DX4GCR5 - DATX8 n General Configuration Register 5 */
27113 /*! @{ */
27114 #define DDRPHY_DX4GCR5_DXREFISELR0_MASK          (0x7FU)
27115 #define DDRPHY_DX4GCR5_DXREFISELR0_SHIFT         (0U)
27116 /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
27117  */
27118 #define DDRPHY_DX4GCR5_DXREFISELR0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR0_MASK)
27119 #define DDRPHY_DX4GCR5_RESERVED_7_MASK           (0x80U)
27120 #define DDRPHY_DX4GCR5_RESERVED_7_SHIFT          (7U)
27121 /*! RESERVED_7 - Reserved. Returns zeros on reads.
27122  */
27123 #define DDRPHY_DX4GCR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_7_MASK)
27124 #define DDRPHY_DX4GCR5_DXREFISELR1_MASK          (0x7F00U)
27125 #define DDRPHY_DX4GCR5_DXREFISELR1_SHIFT         (8U)
27126 /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
27127  */
27128 #define DDRPHY_DX4GCR5_DXREFISELR1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR1_MASK)
27129 #define DDRPHY_DX4GCR5_RESERVED_15_MASK          (0x8000U)
27130 #define DDRPHY_DX4GCR5_RESERVED_15_SHIFT         (15U)
27131 /*! RESERVED_15 - Reserved. Returns zeros on reads.
27132  */
27133 #define DDRPHY_DX4GCR5_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_15_MASK)
27134 #define DDRPHY_DX4GCR5_DXREFISELR2_MASK          (0x7F0000U)
27135 #define DDRPHY_DX4GCR5_DXREFISELR2_SHIFT         (16U)
27136 /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
27137  */
27138 #define DDRPHY_DX4GCR5_DXREFISELR2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR2_MASK)
27139 #define DDRPHY_DX4GCR5_RESERVED_23_MASK          (0x800000U)
27140 #define DDRPHY_DX4GCR5_RESERVED_23_SHIFT         (23U)
27141 /*! RESERVED_23 - Reserved. Returns zeros on reads.
27142  */
27143 #define DDRPHY_DX4GCR5_RESERVED_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_23_MASK)
27144 #define DDRPHY_DX4GCR5_DXREFISELR3_MASK          (0x7F000000U)
27145 #define DDRPHY_DX4GCR5_DXREFISELR3_SHIFT         (24U)
27146 /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
27147  */
27148 #define DDRPHY_DX4GCR5_DXREFISELR3(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR3_MASK)
27149 #define DDRPHY_DX4GCR5_RESERVED_31_MASK          (0x80000000U)
27150 #define DDRPHY_DX4GCR5_RESERVED_31_SHIFT         (31U)
27151 /*! RESERVED_31 - Reserved. Returns zeros on reads.
27152  */
27153 #define DDRPHY_DX4GCR5_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_31_MASK)
27154 /*! @} */
27155 
27156 /*! @name DX4GCR6 - DATX8 n General Configuration Register 6 */
27157 /*! @{ */
27158 #define DDRPHY_DX4GCR6_DXDQVREFR0_MASK           (0x3FU)
27159 #define DDRPHY_DX4GCR6_DXDQVREFR0_SHIFT          (0U)
27160 /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
27161  */
27162 #define DDRPHY_DX4GCR6_DXDQVREFR0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR0_MASK)
27163 #define DDRPHY_DX4GCR6_RESERVED_7_6_MASK         (0xC0U)
27164 #define DDRPHY_DX4GCR6_RESERVED_7_6_SHIFT        (6U)
27165 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
27166  */
27167 #define DDRPHY_DX4GCR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_7_6_MASK)
27168 #define DDRPHY_DX4GCR6_DXDQVREFR1_MASK           (0x3F00U)
27169 #define DDRPHY_DX4GCR6_DXDQVREFR1_SHIFT          (8U)
27170 /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
27171  */
27172 #define DDRPHY_DX4GCR6_DXDQVREFR1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR1_MASK)
27173 #define DDRPHY_DX4GCR6_RESERVED_15_14_MASK       (0xC000U)
27174 #define DDRPHY_DX4GCR6_RESERVED_15_14_SHIFT      (14U)
27175 /*! RESERVED_15_14 - Reserved. Returns zeros on reads.
27176  */
27177 #define DDRPHY_DX4GCR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_15_14_MASK)
27178 #define DDRPHY_DX4GCR6_DXDQVREFR2_MASK           (0x3F0000U)
27179 #define DDRPHY_DX4GCR6_DXDQVREFR2_SHIFT          (16U)
27180 /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
27181  */
27182 #define DDRPHY_DX4GCR6_DXDQVREFR2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR2_MASK)
27183 #define DDRPHY_DX4GCR6_RESERVED_23_22_MASK       (0xC00000U)
27184 #define DDRPHY_DX4GCR6_RESERVED_23_22_SHIFT      (22U)
27185 /*! RESERVED_23_22 - Reserved. Returns zeros on reads.
27186  */
27187 #define DDRPHY_DX4GCR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_23_22_MASK)
27188 #define DDRPHY_DX4GCR6_DXDQVREFR3_MASK           (0x3F000000U)
27189 #define DDRPHY_DX4GCR6_DXDQVREFR3_SHIFT          (24U)
27190 /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
27191  */
27192 #define DDRPHY_DX4GCR6_DXDQVREFR3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR3_MASK)
27193 #define DDRPHY_DX4GCR6_RESERVED_31_30_MASK       (0xC0000000U)
27194 #define DDRPHY_DX4GCR6_RESERVED_31_30_SHIFT      (30U)
27195 /*! RESERVED_31_30 - Reserved. Returns zeros on reads.
27196  */
27197 #define DDRPHY_DX4GCR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_31_30_MASK)
27198 /*! @} */
27199 
27200 /*! @name DX4GCR7 - DATX8 n General Configuration Register 7 */
27201 /*! @{ */
27202 #define DDRPHY_DX4GCR7_DCALSVAL_MASK             (0x1FFU)
27203 #define DDRPHY_DX4GCR7_DCALSVAL_SHIFT            (0U)
27204 /*! DCALSVAL - DDL Calibration Starting Value
27205  */
27206 #define DDRPHY_DX4GCR7_DCALSVAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX4GCR7_DCALSVAL_MASK)
27207 #define DDRPHY_DX4GCR7_DCALTYPE_MASK             (0x200U)
27208 #define DDRPHY_DX4GCR7_DCALTYPE_SHIFT            (9U)
27209 /*! DCALTYPE - DDL Calibration Type
27210  */
27211 #define DDRPHY_DX4GCR7_DCALTYPE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX4GCR7_DCALTYPE_MASK)
27212 #define DDRPHY_DX4GCR7_RESERVED_17_10_MASK       (0x3FC00U)
27213 #define DDRPHY_DX4GCR7_RESERVED_17_10_SHIFT      (10U)
27214 /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
27215  */
27216 #define DDRPHY_DX4GCR7_RESERVED_17_10(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX4GCR7_RESERVED_17_10_MASK)
27217 #define DDRPHY_DX4GCR7_RESERVED_18_MASK          (0x40000U)
27218 #define DDRPHY_DX4GCR7_RESERVED_18_SHIFT         (18U)
27219 /*! RESERVED_18 - Reserved. Caution, do not write to this register field.
27220  */
27221 #define DDRPHY_DX4GCR7_RESERVED_18(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX4GCR7_RESERVED_18_MASK)
27222 #define DDRPHY_DX4GCR7_RESERVED_31_19_MASK       (0xFFF80000U)
27223 #define DDRPHY_DX4GCR7_RESERVED_31_19_SHIFT      (19U)
27224 /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
27225  */
27226 #define DDRPHY_DX4GCR7_RESERVED_31_19(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX4GCR7_RESERVED_31_19_MASK)
27227 /*! @} */
27228 
27229 /*! @name DX4GCR8 - DATX8 n General Configuration Register 8 */
27230 /*! @{ */
27231 #define DDRPHY_DX4GCR8_RESERVED_5_0_MASK         (0x3FU)
27232 #define DDRPHY_DX4GCR8_RESERVED_5_0_SHIFT        (0U)
27233 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27234  */
27235 #define DDRPHY_DX4GCR8_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_5_0_MASK)
27236 #define DDRPHY_DX4GCR8_RESERVED_7_6_MASK         (0xC0U)
27237 #define DDRPHY_DX4GCR8_RESERVED_7_6_SHIFT        (6U)
27238 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27239  */
27240 #define DDRPHY_DX4GCR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_7_6_MASK)
27241 #define DDRPHY_DX4GCR8_RESERVED_13_8_MASK        (0x3F00U)
27242 #define DDRPHY_DX4GCR8_RESERVED_13_8_SHIFT       (8U)
27243 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27244  */
27245 #define DDRPHY_DX4GCR8_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_13_8_MASK)
27246 #define DDRPHY_DX4GCR8_RESERVED_15_14_MASK       (0xC000U)
27247 #define DDRPHY_DX4GCR8_RESERVED_15_14_SHIFT      (14U)
27248 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27249  */
27250 #define DDRPHY_DX4GCR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_15_14_MASK)
27251 #define DDRPHY_DX4GCR8_RESERVED_21_16_MASK       (0x3F0000U)
27252 #define DDRPHY_DX4GCR8_RESERVED_21_16_SHIFT      (16U)
27253 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27254  */
27255 #define DDRPHY_DX4GCR8_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_21_16_MASK)
27256 #define DDRPHY_DX4GCR8_RESERVED_23_22_MASK       (0xC00000U)
27257 #define DDRPHY_DX4GCR8_RESERVED_23_22_SHIFT      (22U)
27258 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27259  */
27260 #define DDRPHY_DX4GCR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_23_22_MASK)
27261 #define DDRPHY_DX4GCR8_RESERVED_29_24_MASK       (0x3F000000U)
27262 #define DDRPHY_DX4GCR8_RESERVED_29_24_SHIFT      (24U)
27263 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
27264  */
27265 #define DDRPHY_DX4GCR8_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_29_24_MASK)
27266 #define DDRPHY_DX4GCR8_RESERVED_31_30_MASK       (0xC0000000U)
27267 #define DDRPHY_DX4GCR8_RESERVED_31_30_SHIFT      (30U)
27268 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27269  */
27270 #define DDRPHY_DX4GCR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_31_30_MASK)
27271 /*! @} */
27272 
27273 /*! @name DX4GCR9 - DATX8 n General Configuration Register 9 */
27274 /*! @{ */
27275 #define DDRPHY_DX4GCR9_RESERVED_5_0_MASK         (0x3FU)
27276 #define DDRPHY_DX4GCR9_RESERVED_5_0_SHIFT        (0U)
27277 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27278  */
27279 #define DDRPHY_DX4GCR9_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_5_0_MASK)
27280 #define DDRPHY_DX4GCR9_RESERVED_7_6_MASK         (0xC0U)
27281 #define DDRPHY_DX4GCR9_RESERVED_7_6_SHIFT        (6U)
27282 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27283  */
27284 #define DDRPHY_DX4GCR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_7_6_MASK)
27285 #define DDRPHY_DX4GCR9_RESERVED_13_8_MASK        (0x3F00U)
27286 #define DDRPHY_DX4GCR9_RESERVED_13_8_SHIFT       (8U)
27287 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27288  */
27289 #define DDRPHY_DX4GCR9_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_13_8_MASK)
27290 #define DDRPHY_DX4GCR9_RESERVED_15_14_MASK       (0xC000U)
27291 #define DDRPHY_DX4GCR9_RESERVED_15_14_SHIFT      (14U)
27292 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27293  */
27294 #define DDRPHY_DX4GCR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_15_14_MASK)
27295 #define DDRPHY_DX4GCR9_RESERVED_21_16_MASK       (0x3F0000U)
27296 #define DDRPHY_DX4GCR9_RESERVED_21_16_SHIFT      (16U)
27297 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27298  */
27299 #define DDRPHY_DX4GCR9_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_21_16_MASK)
27300 #define DDRPHY_DX4GCR9_RESERVED_23_22_MASK       (0xC00000U)
27301 #define DDRPHY_DX4GCR9_RESERVED_23_22_SHIFT      (22U)
27302 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27303  */
27304 #define DDRPHY_DX4GCR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_23_22_MASK)
27305 #define DDRPHY_DX4GCR9_RESERVED_29_24_MASK       (0x3F000000U)
27306 #define DDRPHY_DX4GCR9_RESERVED_29_24_SHIFT      (24U)
27307 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
27308  */
27309 #define DDRPHY_DX4GCR9_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_29_24_MASK)
27310 #define DDRPHY_DX4GCR9_RESERVED_31_30_MASK       (0xC0000000U)
27311 #define DDRPHY_DX4GCR9_RESERVED_31_30_SHIFT      (30U)
27312 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27313  */
27314 #define DDRPHY_DX4GCR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_31_30_MASK)
27315 /*! @} */
27316 
27317 /*! @name DX4DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
27318 /*! @{ */
27319 #define DDRPHY_DX4DQMAP0_DQ0MAP_MASK             (0xFU)
27320 #define DDRPHY_DX4DQMAP0_DQ0MAP_SHIFT            (0U)
27321 /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
27322  */
27323 #define DDRPHY_DX4DQMAP0_DQ0MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ0MAP_MASK)
27324 #define DDRPHY_DX4DQMAP0_DQ1MAP_MASK             (0xF0U)
27325 #define DDRPHY_DX4DQMAP0_DQ1MAP_SHIFT            (4U)
27326 /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
27327  */
27328 #define DDRPHY_DX4DQMAP0_DQ1MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ1MAP_MASK)
27329 #define DDRPHY_DX4DQMAP0_DQ2MAP_MASK             (0xF00U)
27330 #define DDRPHY_DX4DQMAP0_DQ2MAP_SHIFT            (8U)
27331 /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
27332  */
27333 #define DDRPHY_DX4DQMAP0_DQ2MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ2MAP_MASK)
27334 #define DDRPHY_DX4DQMAP0_DQ3MAP_MASK             (0xF000U)
27335 #define DDRPHY_DX4DQMAP0_DQ3MAP_SHIFT            (12U)
27336 /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
27337  */
27338 #define DDRPHY_DX4DQMAP0_DQ3MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ3MAP_MASK)
27339 #define DDRPHY_DX4DQMAP0_DQ4MAP_MASK             (0xF0000U)
27340 #define DDRPHY_DX4DQMAP0_DQ4MAP_SHIFT            (16U)
27341 /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
27342  */
27343 #define DDRPHY_DX4DQMAP0_DQ4MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ4MAP_MASK)
27344 #define DDRPHY_DX4DQMAP0_RESERVED_30_20_MASK     (0x7FF00000U)
27345 #define DDRPHY_DX4DQMAP0_RESERVED_30_20_SHIFT    (20U)
27346 /*! RESERVED_30_20 - Reserved. Return zeroes on reads.
27347  */
27348 #define DDRPHY_DX4DQMAP0_RESERVED_30_20(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX4DQMAP0_RESERVED_30_20_MASK)
27349 #define DDRPHY_DX4DQMAP0_MAPOK_MASK              (0x80000000U)
27350 #define DDRPHY_DX4DQMAP0_MAPOK_SHIFT             (31U)
27351 /*! MAPOK - Checksum bit
27352  */
27353 #define DDRPHY_DX4DQMAP0_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX4DQMAP0_MAPOK_MASK)
27354 /*! @} */
27355 
27356 /*! @name DX4DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
27357 /*! @{ */
27358 #define DDRPHY_DX4DQMAP1_DQ5MAP_MASK             (0xFU)
27359 #define DDRPHY_DX4DQMAP1_DQ5MAP_SHIFT            (0U)
27360 /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
27361  */
27362 #define DDRPHY_DX4DQMAP1_DQ5MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX4DQMAP1_DQ5MAP_MASK)
27363 #define DDRPHY_DX4DQMAP1_DQ6MAP_MASK             (0xF0U)
27364 #define DDRPHY_DX4DQMAP1_DQ6MAP_SHIFT            (4U)
27365 /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
27366  */
27367 #define DDRPHY_DX4DQMAP1_DQ6MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX4DQMAP1_DQ6MAP_MASK)
27368 #define DDRPHY_DX4DQMAP1_DQ7MAP_MASK             (0xF00U)
27369 #define DDRPHY_DX4DQMAP1_DQ7MAP_SHIFT            (8U)
27370 /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
27371  */
27372 #define DDRPHY_DX4DQMAP1_DQ7MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX4DQMAP1_DQ7MAP_MASK)
27373 #define DDRPHY_DX4DQMAP1_DMMAP_MASK              (0xF000U)
27374 #define DDRPHY_DX4DQMAP1_DMMAP_SHIFT             (12U)
27375 /*! DMMAP - DM bit DATX8 slice mapping index
27376  */
27377 #define DDRPHY_DX4DQMAP1_DMMAP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX4DQMAP1_DMMAP_MASK)
27378 #define DDRPHY_DX4DQMAP1_RESERVED_30_16_MASK     (0x7FFF0000U)
27379 #define DDRPHY_DX4DQMAP1_RESERVED_30_16_SHIFT    (16U)
27380 /*! RESERVED_30_16 - Reserved. Return zeroes on reads.
27381  */
27382 #define DDRPHY_DX4DQMAP1_RESERVED_30_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX4DQMAP1_RESERVED_30_16_MASK)
27383 #define DDRPHY_DX4DQMAP1_MAPOK_MASK              (0x80000000U)
27384 #define DDRPHY_DX4DQMAP1_MAPOK_SHIFT             (31U)
27385 /*! MAPOK - Checksum bit
27386  */
27387 #define DDRPHY_DX4DQMAP1_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX4DQMAP1_MAPOK_MASK)
27388 /*! @} */
27389 
27390 /*! @name DX4BDLR0 - DATX8 n Bit Delay Line Register 0 */
27391 /*! @{ */
27392 #define DDRPHY_DX4BDLR0_DQ0WBD_MASK              (0x3FU)
27393 #define DDRPHY_DX4BDLR0_DQ0WBD_SHIFT             (0U)
27394 /*! DQ0WBD - DQ0 Write Bit Delay
27395  */
27396 #define DDRPHY_DX4BDLR0_DQ0WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ0WBD_MASK)
27397 #define DDRPHY_DX4BDLR0_RESERVED_7_6_MASK        (0xC0U)
27398 #define DDRPHY_DX4BDLR0_RESERVED_7_6_SHIFT       (6U)
27399 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27400  */
27401 #define DDRPHY_DX4BDLR0_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_7_6_MASK)
27402 #define DDRPHY_DX4BDLR0_DQ1WBD_MASK              (0x3F00U)
27403 #define DDRPHY_DX4BDLR0_DQ1WBD_SHIFT             (8U)
27404 /*! DQ1WBD - DQ1 Write Bit Delay
27405  */
27406 #define DDRPHY_DX4BDLR0_DQ1WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ1WBD_MASK)
27407 #define DDRPHY_DX4BDLR0_RESERVED_15_14_MASK      (0xC000U)
27408 #define DDRPHY_DX4BDLR0_RESERVED_15_14_SHIFT     (14U)
27409 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27410  */
27411 #define DDRPHY_DX4BDLR0_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_15_14_MASK)
27412 #define DDRPHY_DX4BDLR0_DQ2WBD_MASK              (0x3F0000U)
27413 #define DDRPHY_DX4BDLR0_DQ2WBD_SHIFT             (16U)
27414 /*! DQ2WBD - DQ2 Write Bit Delay
27415  */
27416 #define DDRPHY_DX4BDLR0_DQ2WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ2WBD_MASK)
27417 #define DDRPHY_DX4BDLR0_RESERVED_23_22_MASK      (0xC00000U)
27418 #define DDRPHY_DX4BDLR0_RESERVED_23_22_SHIFT     (22U)
27419 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27420  */
27421 #define DDRPHY_DX4BDLR0_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_23_22_MASK)
27422 #define DDRPHY_DX4BDLR0_DQ3WBD_MASK              (0x3F000000U)
27423 #define DDRPHY_DX4BDLR0_DQ3WBD_SHIFT             (24U)
27424 /*! DQ3WBD - DQ3 Write Bit Delay
27425  */
27426 #define DDRPHY_DX4BDLR0_DQ3WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ3WBD_MASK)
27427 #define DDRPHY_DX4BDLR0_RESERVED_31_30_MASK      (0xC0000000U)
27428 #define DDRPHY_DX4BDLR0_RESERVED_31_30_SHIFT     (30U)
27429 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27430  */
27431 #define DDRPHY_DX4BDLR0_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_31_30_MASK)
27432 /*! @} */
27433 
27434 /*! @name DX4BDLR1 - DATX8 n Bit Delay Line Register 1 */
27435 /*! @{ */
27436 #define DDRPHY_DX4BDLR1_DQ4WBD_MASK              (0x3FU)
27437 #define DDRPHY_DX4BDLR1_DQ4WBD_SHIFT             (0U)
27438 /*! DQ4WBD - DQ4 Write Bit Delay
27439  */
27440 #define DDRPHY_DX4BDLR1_DQ4WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ4WBD_MASK)
27441 #define DDRPHY_DX4BDLR1_RESERVED_7_6_MASK        (0xC0U)
27442 #define DDRPHY_DX4BDLR1_RESERVED_7_6_SHIFT       (6U)
27443 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27444  */
27445 #define DDRPHY_DX4BDLR1_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_7_6_MASK)
27446 #define DDRPHY_DX4BDLR1_DQ5WBD_MASK              (0x3F00U)
27447 #define DDRPHY_DX4BDLR1_DQ5WBD_SHIFT             (8U)
27448 /*! DQ5WBD - DQ5 Write Bit Delay
27449  */
27450 #define DDRPHY_DX4BDLR1_DQ5WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ5WBD_MASK)
27451 #define DDRPHY_DX4BDLR1_RESERVED_15_14_MASK      (0xC000U)
27452 #define DDRPHY_DX4BDLR1_RESERVED_15_14_SHIFT     (14U)
27453 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27454  */
27455 #define DDRPHY_DX4BDLR1_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_15_14_MASK)
27456 #define DDRPHY_DX4BDLR1_DQ6WBD_MASK              (0x3F0000U)
27457 #define DDRPHY_DX4BDLR1_DQ6WBD_SHIFT             (16U)
27458 /*! DQ6WBD - DQ6 Write Bit Delay
27459  */
27460 #define DDRPHY_DX4BDLR1_DQ6WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ6WBD_MASK)
27461 #define DDRPHY_DX4BDLR1_RESERVED_23_22_MASK      (0xC00000U)
27462 #define DDRPHY_DX4BDLR1_RESERVED_23_22_SHIFT     (22U)
27463 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27464  */
27465 #define DDRPHY_DX4BDLR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_23_22_MASK)
27466 #define DDRPHY_DX4BDLR1_DQ7WBD_MASK              (0x3F000000U)
27467 #define DDRPHY_DX4BDLR1_DQ7WBD_SHIFT             (24U)
27468 /*! DQ7WBD - DQ7 Write Bit Delay
27469  */
27470 #define DDRPHY_DX4BDLR1_DQ7WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ7WBD_MASK)
27471 #define DDRPHY_DX4BDLR1_RESERVED_31_30_MASK      (0xC0000000U)
27472 #define DDRPHY_DX4BDLR1_RESERVED_31_30_SHIFT     (30U)
27473 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27474  */
27475 #define DDRPHY_DX4BDLR1_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_31_30_MASK)
27476 /*! @} */
27477 
27478 /*! @name DX4BDLR2 - DATX8 n Bit Delay Line Register 2 */
27479 /*! @{ */
27480 #define DDRPHY_DX4BDLR2_DMWBD_MASK               (0x3FU)
27481 #define DDRPHY_DX4BDLR2_DMWBD_SHIFT              (0U)
27482 /*! DMWBD - DM Write Bit Delay
27483  */
27484 #define DDRPHY_DX4BDLR2_DMWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DMWBD_SHIFT)) & DDRPHY_DX4BDLR2_DMWBD_MASK)
27485 #define DDRPHY_DX4BDLR2_RESERVED_7_6_MASK        (0xC0U)
27486 #define DDRPHY_DX4BDLR2_RESERVED_7_6_SHIFT       (6U)
27487 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27488  */
27489 #define DDRPHY_DX4BDLR2_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_7_6_MASK)
27490 #define DDRPHY_DX4BDLR2_DSWBD_MASK               (0x3F00U)
27491 #define DDRPHY_DX4BDLR2_DSWBD_SHIFT              (8U)
27492 /*! DSWBD - DQS Write Bit Delay
27493  */
27494 #define DDRPHY_DX4BDLR2_DSWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DSWBD_SHIFT)) & DDRPHY_DX4BDLR2_DSWBD_MASK)
27495 #define DDRPHY_DX4BDLR2_RESERVED_15_14_MASK      (0xC000U)
27496 #define DDRPHY_DX4BDLR2_RESERVED_15_14_SHIFT     (14U)
27497 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27498  */
27499 #define DDRPHY_DX4BDLR2_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_15_14_MASK)
27500 #define DDRPHY_DX4BDLR2_DSOEBD_MASK              (0x3F0000U)
27501 #define DDRPHY_DX4BDLR2_DSOEBD_SHIFT             (16U)
27502 /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
27503  */
27504 #define DDRPHY_DX4BDLR2_DSOEBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX4BDLR2_DSOEBD_MASK)
27505 #define DDRPHY_DX4BDLR2_RESERVED_23_22_MASK      (0xC00000U)
27506 #define DDRPHY_DX4BDLR2_RESERVED_23_22_SHIFT     (22U)
27507 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27508  */
27509 #define DDRPHY_DX4BDLR2_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_23_22_MASK)
27510 #define DDRPHY_DX4BDLR2_DSNWBD_MASK              (0x3F000000U)
27511 #define DDRPHY_DX4BDLR2_DSNWBD_SHIFT             (24U)
27512 /*! DSNWBD - DQSN Write Bit Delay
27513  */
27514 #define DDRPHY_DX4BDLR2_DSNWBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX4BDLR2_DSNWBD_MASK)
27515 #define DDRPHY_DX4BDLR2_RESERVED_31_30_MASK      (0xC0000000U)
27516 #define DDRPHY_DX4BDLR2_RESERVED_31_30_SHIFT     (30U)
27517 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27518  */
27519 #define DDRPHY_DX4BDLR2_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_31_30_MASK)
27520 /*! @} */
27521 
27522 /*! @name DX4BDLR3 - DATX8 n Bit Delay Line Register 3 */
27523 /*! @{ */
27524 #define DDRPHY_DX4BDLR3_DQ0RBD_MASK              (0x3FU)
27525 #define DDRPHY_DX4BDLR3_DQ0RBD_SHIFT             (0U)
27526 /*! DQ0RBD - DQ0 Read Bit Delay
27527  */
27528 #define DDRPHY_DX4BDLR3_DQ0RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ0RBD_MASK)
27529 #define DDRPHY_DX4BDLR3_RESERVED_7_6_MASK        (0xC0U)
27530 #define DDRPHY_DX4BDLR3_RESERVED_7_6_SHIFT       (6U)
27531 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27532  */
27533 #define DDRPHY_DX4BDLR3_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_7_6_MASK)
27534 #define DDRPHY_DX4BDLR3_DQ1RBD_MASK              (0x3F00U)
27535 #define DDRPHY_DX4BDLR3_DQ1RBD_SHIFT             (8U)
27536 /*! DQ1RBD - DQ1 Read Bit Delay
27537  */
27538 #define DDRPHY_DX4BDLR3_DQ1RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ1RBD_MASK)
27539 #define DDRPHY_DX4BDLR3_RESERVED_15_14_MASK      (0xC000U)
27540 #define DDRPHY_DX4BDLR3_RESERVED_15_14_SHIFT     (14U)
27541 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27542  */
27543 #define DDRPHY_DX4BDLR3_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_15_14_MASK)
27544 #define DDRPHY_DX4BDLR3_DQ2RBD_MASK              (0x3F0000U)
27545 #define DDRPHY_DX4BDLR3_DQ2RBD_SHIFT             (16U)
27546 /*! DQ2RBD - DQ2 Read Bit Delay
27547  */
27548 #define DDRPHY_DX4BDLR3_DQ2RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ2RBD_MASK)
27549 #define DDRPHY_DX4BDLR3_RESERVED_23_22_MASK      (0xC00000U)
27550 #define DDRPHY_DX4BDLR3_RESERVED_23_22_SHIFT     (22U)
27551 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27552  */
27553 #define DDRPHY_DX4BDLR3_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_23_22_MASK)
27554 #define DDRPHY_DX4BDLR3_DQ3RBD_MASK              (0x3F000000U)
27555 #define DDRPHY_DX4BDLR3_DQ3RBD_SHIFT             (24U)
27556 /*! DQ3RBD - DQ3 Read Bit Delay
27557  */
27558 #define DDRPHY_DX4BDLR3_DQ3RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ3RBD_MASK)
27559 #define DDRPHY_DX4BDLR3_RESERVED_31_30_MASK      (0xC0000000U)
27560 #define DDRPHY_DX4BDLR3_RESERVED_31_30_SHIFT     (30U)
27561 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27562  */
27563 #define DDRPHY_DX4BDLR3_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_31_30_MASK)
27564 /*! @} */
27565 
27566 /*! @name DX4BDLR4 - DATX8 n Bit Delay Line Register 4 */
27567 /*! @{ */
27568 #define DDRPHY_DX4BDLR4_DQ4RBD_MASK              (0x3FU)
27569 #define DDRPHY_DX4BDLR4_DQ4RBD_SHIFT             (0U)
27570 /*! DQ4RBD - DQ4 Read Bit Delay
27571  */
27572 #define DDRPHY_DX4BDLR4_DQ4RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ4RBD_MASK)
27573 #define DDRPHY_DX4BDLR4_RESERVED_7_6_MASK        (0xC0U)
27574 #define DDRPHY_DX4BDLR4_RESERVED_7_6_SHIFT       (6U)
27575 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27576  */
27577 #define DDRPHY_DX4BDLR4_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_7_6_MASK)
27578 #define DDRPHY_DX4BDLR4_DQ5RBD_MASK              (0x3F00U)
27579 #define DDRPHY_DX4BDLR4_DQ5RBD_SHIFT             (8U)
27580 /*! DQ5RBD - DQ5 Read Bit Delay
27581  */
27582 #define DDRPHY_DX4BDLR4_DQ5RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ5RBD_MASK)
27583 #define DDRPHY_DX4BDLR4_RESERVED_15_14_MASK      (0xC000U)
27584 #define DDRPHY_DX4BDLR4_RESERVED_15_14_SHIFT     (14U)
27585 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27586  */
27587 #define DDRPHY_DX4BDLR4_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_15_14_MASK)
27588 #define DDRPHY_DX4BDLR4_DQ6RBD_MASK              (0x3F0000U)
27589 #define DDRPHY_DX4BDLR4_DQ6RBD_SHIFT             (16U)
27590 /*! DQ6RBD - DQ6 Read Bit Delay
27591  */
27592 #define DDRPHY_DX4BDLR4_DQ6RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ6RBD_MASK)
27593 #define DDRPHY_DX4BDLR4_RESERVED_23_22_MASK      (0xC00000U)
27594 #define DDRPHY_DX4BDLR4_RESERVED_23_22_SHIFT     (22U)
27595 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27596  */
27597 #define DDRPHY_DX4BDLR4_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_23_22_MASK)
27598 #define DDRPHY_DX4BDLR4_DQ7RBD_MASK              (0x3F000000U)
27599 #define DDRPHY_DX4BDLR4_DQ7RBD_SHIFT             (24U)
27600 /*! DQ7RBD - DQ7 Read Bit Delay
27601  */
27602 #define DDRPHY_DX4BDLR4_DQ7RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ7RBD_MASK)
27603 #define DDRPHY_DX4BDLR4_RESERVED_31_30_MASK      (0xC0000000U)
27604 #define DDRPHY_DX4BDLR4_RESERVED_31_30_SHIFT     (30U)
27605 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27606  */
27607 #define DDRPHY_DX4BDLR4_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_31_30_MASK)
27608 /*! @} */
27609 
27610 /*! @name DX4BDLR5 - DATX8 n Bit Delay Line Register 5 */
27611 /*! @{ */
27612 #define DDRPHY_DX4BDLR5_DMRBD_MASK               (0x3FU)
27613 #define DDRPHY_DX4BDLR5_DMRBD_SHIFT              (0U)
27614 /*! DMRBD - DM Read Bit Delay
27615  */
27616 #define DDRPHY_DX4BDLR5_DMRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR5_DMRBD_SHIFT)) & DDRPHY_DX4BDLR5_DMRBD_MASK)
27617 #define DDRPHY_DX4BDLR5_RESERVED_31_6_MASK       (0xFFFFFFC0U)
27618 #define DDRPHY_DX4BDLR5_RESERVED_31_6_SHIFT      (6U)
27619 /*! RESERVED_31_6 - Reserved. Return zeroes on reads.
27620  */
27621 #define DDRPHY_DX4BDLR5_RESERVED_31_6(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX4BDLR5_RESERVED_31_6_MASK)
27622 /*! @} */
27623 
27624 /*! @name DX4BDLR6 - DATX8 n Bit Delay Line Register 6 */
27625 /*! @{ */
27626 #define DDRPHY_DX4BDLR6_RESERVED_7_0_MASK        (0xFFU)
27627 #define DDRPHY_DX4BDLR6_RESERVED_7_0_SHIFT       (0U)
27628 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
27629  */
27630 #define DDRPHY_DX4BDLR6_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX4BDLR6_RESERVED_7_0_MASK)
27631 #define DDRPHY_DX4BDLR6_PDRBD_MASK               (0x3F00U)
27632 #define DDRPHY_DX4BDLR6_PDRBD_SHIFT              (8U)
27633 /*! PDRBD - Power down receiver Bit Delay
27634  */
27635 #define DDRPHY_DX4BDLR6_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_PDRBD_SHIFT)) & DDRPHY_DX4BDLR6_PDRBD_MASK)
27636 #define DDRPHY_DX4BDLR6_RESERVED_15_14_MASK      (0xC000U)
27637 #define DDRPHY_DX4BDLR6_RESERVED_15_14_SHIFT     (14U)
27638 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27639  */
27640 #define DDRPHY_DX4BDLR6_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR6_RESERVED_15_14_MASK)
27641 #define DDRPHY_DX4BDLR6_TERBD_MASK               (0x3F0000U)
27642 #define DDRPHY_DX4BDLR6_TERBD_SHIFT              (16U)
27643 /*! TERBD - Termination Enable Bit Delay
27644  */
27645 #define DDRPHY_DX4BDLR6_TERBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_TERBD_SHIFT)) & DDRPHY_DX4BDLR6_TERBD_MASK)
27646 #define DDRPHY_DX4BDLR6_RESERVED_31_22_MASK      (0xFFC00000U)
27647 #define DDRPHY_DX4BDLR6_RESERVED_31_22_SHIFT     (22U)
27648 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
27649  */
27650 #define DDRPHY_DX4BDLR6_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR6_RESERVED_31_22_MASK)
27651 /*! @} */
27652 
27653 /*! @name DX4BDLR7 - DATX8 n Bit Delay Line Register 7 */
27654 /*! @{ */
27655 #define DDRPHY_DX4BDLR7_RESERVED_5_0_MASK        (0x3FU)
27656 #define DDRPHY_DX4BDLR7_RESERVED_5_0_SHIFT       (0U)
27657 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27658  */
27659 #define DDRPHY_DX4BDLR7_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_5_0_MASK)
27660 #define DDRPHY_DX4BDLR7_RESERVED_7_6_MASK        (0xC0U)
27661 #define DDRPHY_DX4BDLR7_RESERVED_7_6_SHIFT       (6U)
27662 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27663  */
27664 #define DDRPHY_DX4BDLR7_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_7_6_MASK)
27665 #define DDRPHY_DX4BDLR7_RESERVED_13_8_MASK       (0x3F00U)
27666 #define DDRPHY_DX4BDLR7_RESERVED_13_8_SHIFT      (8U)
27667 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27668  */
27669 #define DDRPHY_DX4BDLR7_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_13_8_MASK)
27670 #define DDRPHY_DX4BDLR7_RESERVED_15_14_MASK      (0xC000U)
27671 #define DDRPHY_DX4BDLR7_RESERVED_15_14_SHIFT     (14U)
27672 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27673  */
27674 #define DDRPHY_DX4BDLR7_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_15_14_MASK)
27675 #define DDRPHY_DX4BDLR7_RESERVED_21_16_MASK      (0x3F0000U)
27676 #define DDRPHY_DX4BDLR7_RESERVED_21_16_SHIFT     (16U)
27677 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27678  */
27679 #define DDRPHY_DX4BDLR7_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_21_16_MASK)
27680 #define DDRPHY_DX4BDLR7_RESERVED_31_22_MASK      (0xFFC00000U)
27681 #define DDRPHY_DX4BDLR7_RESERVED_31_22_SHIFT     (22U)
27682 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
27683  */
27684 #define DDRPHY_DX4BDLR7_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_31_22_MASK)
27685 /*! @} */
27686 
27687 /*! @name DX4BDLR8 - DATX8 n Bit Delay Line Register 8 */
27688 /*! @{ */
27689 #define DDRPHY_DX4BDLR8_RESERVED_5_0_MASK        (0x3FU)
27690 #define DDRPHY_DX4BDLR8_RESERVED_5_0_SHIFT       (0U)
27691 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27692  */
27693 #define DDRPHY_DX4BDLR8_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_5_0_MASK)
27694 #define DDRPHY_DX4BDLR8_RESERVED_7_6_MASK        (0xC0U)
27695 #define DDRPHY_DX4BDLR8_RESERVED_7_6_SHIFT       (6U)
27696 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27697  */
27698 #define DDRPHY_DX4BDLR8_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_7_6_MASK)
27699 #define DDRPHY_DX4BDLR8_RESERVED_13_8_MASK       (0x3F00U)
27700 #define DDRPHY_DX4BDLR8_RESERVED_13_8_SHIFT      (8U)
27701 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27702  */
27703 #define DDRPHY_DX4BDLR8_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_13_8_MASK)
27704 #define DDRPHY_DX4BDLR8_RESERVED_15_14_MASK      (0xC000U)
27705 #define DDRPHY_DX4BDLR8_RESERVED_15_14_SHIFT     (14U)
27706 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27707  */
27708 #define DDRPHY_DX4BDLR8_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_15_14_MASK)
27709 #define DDRPHY_DX4BDLR8_RESERVED_21_16_MASK      (0x3F0000U)
27710 #define DDRPHY_DX4BDLR8_RESERVED_21_16_SHIFT     (16U)
27711 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27712  */
27713 #define DDRPHY_DX4BDLR8_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_21_16_MASK)
27714 #define DDRPHY_DX4BDLR8_RESERVED_31_22_MASK      (0xFFC00000U)
27715 #define DDRPHY_DX4BDLR8_RESERVED_31_22_SHIFT     (22U)
27716 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
27717  */
27718 #define DDRPHY_DX4BDLR8_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_31_22_MASK)
27719 /*! @} */
27720 
27721 /*! @name DX4BDLR9 - DATX8 n Bit Delay Line Register 9 */
27722 /*! @{ */
27723 #define DDRPHY_DX4BDLR9_RESERVED_5_0_MASK        (0x3FU)
27724 #define DDRPHY_DX4BDLR9_RESERVED_5_0_SHIFT       (0U)
27725 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27726  */
27727 #define DDRPHY_DX4BDLR9_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_5_0_MASK)
27728 #define DDRPHY_DX4BDLR9_RESERVED_7_6_MASK        (0xC0U)
27729 #define DDRPHY_DX4BDLR9_RESERVED_7_6_SHIFT       (6U)
27730 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27731  */
27732 #define DDRPHY_DX4BDLR9_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_7_6_MASK)
27733 #define DDRPHY_DX4BDLR9_RESERVED_13_8_MASK       (0x3F00U)
27734 #define DDRPHY_DX4BDLR9_RESERVED_13_8_SHIFT      (8U)
27735 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27736  */
27737 #define DDRPHY_DX4BDLR9_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_13_8_MASK)
27738 #define DDRPHY_DX4BDLR9_RESERVED_15_14_MASK      (0xC000U)
27739 #define DDRPHY_DX4BDLR9_RESERVED_15_14_SHIFT     (14U)
27740 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27741  */
27742 #define DDRPHY_DX4BDLR9_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_15_14_MASK)
27743 #define DDRPHY_DX4BDLR9_RESERVED_21_16_MASK      (0x3F0000U)
27744 #define DDRPHY_DX4BDLR9_RESERVED_21_16_SHIFT     (16U)
27745 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27746  */
27747 #define DDRPHY_DX4BDLR9_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_21_16_MASK)
27748 #define DDRPHY_DX4BDLR9_RESERVED_31_22_MASK      (0xFFC00000U)
27749 #define DDRPHY_DX4BDLR9_RESERVED_31_22_SHIFT     (22U)
27750 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
27751  */
27752 #define DDRPHY_DX4BDLR9_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_31_22_MASK)
27753 /*! @} */
27754 
27755 /*! @name DX4LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
27756 /*! @{ */
27757 #define DDRPHY_DX4LCDLR0_WLD_MASK                (0x1FFU)
27758 #define DDRPHY_DX4LCDLR0_WLD_SHIFT               (0U)
27759 /*! WLD - Write Leveling Delay
27760  */
27761 #define DDRPHY_DX4LCDLR0_WLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_WLD_SHIFT)) & DDRPHY_DX4LCDLR0_WLD_MASK)
27762 #define DDRPHY_DX4LCDLR0_RESERVED_15_9_MASK      (0xFE00U)
27763 #define DDRPHY_DX4LCDLR0_RESERVED_15_9_SHIFT     (9U)
27764 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27765  */
27766 #define DDRPHY_DX4LCDLR0_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR0_RESERVED_15_9_MASK)
27767 #define DDRPHY_DX4LCDLR0_RESERVED_24_16_MASK     (0x1FF0000U)
27768 #define DDRPHY_DX4LCDLR0_RESERVED_24_16_SHIFT    (16U)
27769 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27770  */
27771 #define DDRPHY_DX4LCDLR0_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR0_RESERVED_24_16_MASK)
27772 #define DDRPHY_DX4LCDLR0_RESERVED_31_25_MASK     (0xFE000000U)
27773 #define DDRPHY_DX4LCDLR0_RESERVED_31_25_SHIFT    (25U)
27774 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27775  */
27776 #define DDRPHY_DX4LCDLR0_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR0_RESERVED_31_25_MASK)
27777 /*! @} */
27778 
27779 /*! @name DX4LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
27780 /*! @{ */
27781 #define DDRPHY_DX4LCDLR1_WDQD_MASK               (0x1FFU)
27782 #define DDRPHY_DX4LCDLR1_WDQD_SHIFT              (0U)
27783 /*! WDQD - Write Data Delay
27784  */
27785 #define DDRPHY_DX4LCDLR1_WDQD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_WDQD_SHIFT)) & DDRPHY_DX4LCDLR1_WDQD_MASK)
27786 #define DDRPHY_DX4LCDLR1_RESERVED_15_9_MASK      (0xFE00U)
27787 #define DDRPHY_DX4LCDLR1_RESERVED_15_9_SHIFT     (9U)
27788 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27789  */
27790 #define DDRPHY_DX4LCDLR1_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR1_RESERVED_15_9_MASK)
27791 #define DDRPHY_DX4LCDLR1_RESERVED_24_16_MASK     (0x1FF0000U)
27792 #define DDRPHY_DX4LCDLR1_RESERVED_24_16_SHIFT    (16U)
27793 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27794  */
27795 #define DDRPHY_DX4LCDLR1_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR1_RESERVED_24_16_MASK)
27796 #define DDRPHY_DX4LCDLR1_RESERVED_31_25_MASK     (0xFE000000U)
27797 #define DDRPHY_DX4LCDLR1_RESERVED_31_25_SHIFT    (25U)
27798 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27799  */
27800 #define DDRPHY_DX4LCDLR1_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR1_RESERVED_31_25_MASK)
27801 /*! @} */
27802 
27803 /*! @name DX4LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
27804 /*! @{ */
27805 #define DDRPHY_DX4LCDLR2_DQSGD_MASK              (0x1FFU)
27806 #define DDRPHY_DX4LCDLR2_DQSGD_SHIFT             (0U)
27807 /*! DQSGD - Read DQS Gating Delay
27808  */
27809 #define DDRPHY_DX4LCDLR2_DQSGD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX4LCDLR2_DQSGD_MASK)
27810 #define DDRPHY_DX4LCDLR2_RESERVED_15_9_MASK      (0xFE00U)
27811 #define DDRPHY_DX4LCDLR2_RESERVED_15_9_SHIFT     (9U)
27812 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27813  */
27814 #define DDRPHY_DX4LCDLR2_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR2_RESERVED_15_9_MASK)
27815 #define DDRPHY_DX4LCDLR2_RESERVED_24_16_MASK     (0x1FF0000U)
27816 #define DDRPHY_DX4LCDLR2_RESERVED_24_16_SHIFT    (16U)
27817 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27818  */
27819 #define DDRPHY_DX4LCDLR2_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR2_RESERVED_24_16_MASK)
27820 #define DDRPHY_DX4LCDLR2_RESERVED_31_25_MASK     (0xFE000000U)
27821 #define DDRPHY_DX4LCDLR2_RESERVED_31_25_SHIFT    (25U)
27822 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27823  */
27824 #define DDRPHY_DX4LCDLR2_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR2_RESERVED_31_25_MASK)
27825 /*! @} */
27826 
27827 /*! @name DX4LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
27828 /*! @{ */
27829 #define DDRPHY_DX4LCDLR3_RDQSD_MASK              (0x1FFU)
27830 #define DDRPHY_DX4LCDLR3_RDQSD_SHIFT             (0U)
27831 /*! RDQSD - Read DQS Delay
27832  */
27833 #define DDRPHY_DX4LCDLR3_RDQSD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX4LCDLR3_RDQSD_MASK)
27834 #define DDRPHY_DX4LCDLR3_RESERVED_15_9_MASK      (0xFE00U)
27835 #define DDRPHY_DX4LCDLR3_RESERVED_15_9_SHIFT     (9U)
27836 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27837  */
27838 #define DDRPHY_DX4LCDLR3_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR3_RESERVED_15_9_MASK)
27839 #define DDRPHY_DX4LCDLR3_RESERVED_24_16_MASK     (0x1FF0000U)
27840 #define DDRPHY_DX4LCDLR3_RESERVED_24_16_SHIFT    (16U)
27841 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27842  */
27843 #define DDRPHY_DX4LCDLR3_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR3_RESERVED_24_16_MASK)
27844 #define DDRPHY_DX4LCDLR3_RESERVED_31_25_MASK     (0xFE000000U)
27845 #define DDRPHY_DX4LCDLR3_RESERVED_31_25_SHIFT    (25U)
27846 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27847  */
27848 #define DDRPHY_DX4LCDLR3_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR3_RESERVED_31_25_MASK)
27849 /*! @} */
27850 
27851 /*! @name DX4LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
27852 /*! @{ */
27853 #define DDRPHY_DX4LCDLR4_RDQSND_MASK             (0x1FFU)
27854 #define DDRPHY_DX4LCDLR4_RDQSND_SHIFT            (0U)
27855 /*! RDQSND - Read DQSN Delay
27856  */
27857 #define DDRPHY_DX4LCDLR4_RDQSND(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX4LCDLR4_RDQSND_MASK)
27858 #define DDRPHY_DX4LCDLR4_RESERVED_15_9_MASK      (0xFE00U)
27859 #define DDRPHY_DX4LCDLR4_RESERVED_15_9_SHIFT     (9U)
27860 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27861  */
27862 #define DDRPHY_DX4LCDLR4_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR4_RESERVED_15_9_MASK)
27863 #define DDRPHY_DX4LCDLR4_RESERVED_24_16_MASK     (0x1FF0000U)
27864 #define DDRPHY_DX4LCDLR4_RESERVED_24_16_SHIFT    (16U)
27865 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27866  */
27867 #define DDRPHY_DX4LCDLR4_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR4_RESERVED_24_16_MASK)
27868 #define DDRPHY_DX4LCDLR4_RESERVED_31_25_MASK     (0xFE000000U)
27869 #define DDRPHY_DX4LCDLR4_RESERVED_31_25_SHIFT    (25U)
27870 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27871  */
27872 #define DDRPHY_DX4LCDLR4_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR4_RESERVED_31_25_MASK)
27873 /*! @} */
27874 
27875 /*! @name DX4LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
27876 /*! @{ */
27877 #define DDRPHY_DX4LCDLR5_DQSGSD_MASK             (0x1FFU)
27878 #define DDRPHY_DX4LCDLR5_DQSGSD_SHIFT            (0U)
27879 /*! DQSGSD - DQS Gating Status Delay
27880  */
27881 #define DDRPHY_DX4LCDLR5_DQSGSD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX4LCDLR5_DQSGSD_MASK)
27882 #define DDRPHY_DX4LCDLR5_RESERVED_15_9_MASK      (0xFE00U)
27883 #define DDRPHY_DX4LCDLR5_RESERVED_15_9_SHIFT     (9U)
27884 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27885  */
27886 #define DDRPHY_DX4LCDLR5_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR5_RESERVED_15_9_MASK)
27887 #define DDRPHY_DX4LCDLR5_RESERVED_24_16_MASK     (0x1FF0000U)
27888 #define DDRPHY_DX4LCDLR5_RESERVED_24_16_SHIFT    (16U)
27889 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27890  */
27891 #define DDRPHY_DX4LCDLR5_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR5_RESERVED_24_16_MASK)
27892 #define DDRPHY_DX4LCDLR5_RESERVED_31_25_MASK     (0xFE000000U)
27893 #define DDRPHY_DX4LCDLR5_RESERVED_31_25_SHIFT    (25U)
27894 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27895  */
27896 #define DDRPHY_DX4LCDLR5_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR5_RESERVED_31_25_MASK)
27897 /*! @} */
27898 
27899 /*! @name DX4MDLR0 - DATX8 n Master Delay Line Register 0 */
27900 /*! @{ */
27901 #define DDRPHY_DX4MDLR0_IPRD_MASK                (0x1FFU)
27902 #define DDRPHY_DX4MDLR0_IPRD_SHIFT               (0U)
27903 /*! IPRD - Initial Period
27904  */
27905 #define DDRPHY_DX4MDLR0_IPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_IPRD_SHIFT)) & DDRPHY_DX4MDLR0_IPRD_MASK)
27906 #define DDRPHY_DX4MDLR0_RESERVED_15_9_MASK       (0xFE00U)
27907 #define DDRPHY_DX4MDLR0_RESERVED_15_9_SHIFT      (9U)
27908 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27909  */
27910 #define DDRPHY_DX4MDLR0_RESERVED_15_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX4MDLR0_RESERVED_15_9_MASK)
27911 #define DDRPHY_DX4MDLR0_TPRD_MASK                (0x1FF0000U)
27912 #define DDRPHY_DX4MDLR0_TPRD_SHIFT               (16U)
27913 /*! TPRD - Target Period
27914  */
27915 #define DDRPHY_DX4MDLR0_TPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_TPRD_SHIFT)) & DDRPHY_DX4MDLR0_TPRD_MASK)
27916 #define DDRPHY_DX4MDLR0_RESERVED_31_25_MASK      (0xFE000000U)
27917 #define DDRPHY_DX4MDLR0_RESERVED_31_25_SHIFT     (25U)
27918 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27919  */
27920 #define DDRPHY_DX4MDLR0_RESERVED_31_25(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX4MDLR0_RESERVED_31_25_MASK)
27921 /*! @} */
27922 
27923 /*! @name DX4MDLR1 - DATX8 n Master Delay Line Register 1 */
27924 /*! @{ */
27925 #define DDRPHY_DX4MDLR1_MDLD_MASK                (0x1FFU)
27926 #define DDRPHY_DX4MDLR1_MDLD_SHIFT               (0U)
27927 /*! MDLD - MDL Delay
27928  */
27929 #define DDRPHY_DX4MDLR1_MDLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR1_MDLD_SHIFT)) & DDRPHY_DX4MDLR1_MDLD_MASK)
27930 #define DDRPHY_DX4MDLR1_RESERVED_31_9_MASK       (0xFFFFFE00U)
27931 #define DDRPHY_DX4MDLR1_RESERVED_31_9_SHIFT      (9U)
27932 /*! RESERVED_31_9 - Reserved. Return zeroes on reads.
27933  */
27934 #define DDRPHY_DX4MDLR1_RESERVED_31_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX4MDLR1_RESERVED_31_9_MASK)
27935 /*! @} */
27936 
27937 /*! @name DX4GTR0 - DATX8 n General Timing Register 0 */
27938 /*! @{ */
27939 #define DDRPHY_DX4GTR0_DGSL_MASK                 (0x1FU)
27940 #define DDRPHY_DX4GTR0_DGSL_SHIFT                (0U)
27941 /*! DGSL - DQS Gating System Latency
27942  */
27943 #define DDRPHY_DX4GTR0_DGSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_DGSL_SHIFT)) & DDRPHY_DX4GTR0_DGSL_MASK)
27944 #define DDRPHY_DX4GTR0_RESERVED_7_5_MASK         (0xE0U)
27945 #define DDRPHY_DX4GTR0_RESERVED_7_5_SHIFT        (5U)
27946 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
27947  */
27948 #define DDRPHY_DX4GTR0_RESERVED_7_5(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_7_5_MASK)
27949 #define DDRPHY_DX4GTR0_RESERVED_12_8_MASK        (0x1F00U)
27950 #define DDRPHY_DX4GTR0_RESERVED_12_8_SHIFT       (8U)
27951 /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
27952  */
27953 #define DDRPHY_DX4GTR0_RESERVED_12_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_12_8_MASK)
27954 #define DDRPHY_DX4GTR0_RESERVED_15_13_MASK       (0xE000U)
27955 #define DDRPHY_DX4GTR0_RESERVED_15_13_SHIFT      (13U)
27956 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
27957  */
27958 #define DDRPHY_DX4GTR0_RESERVED_15_13(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_15_13_MASK)
27959 #define DDRPHY_DX4GTR0_WLSL_MASK                 (0xF0000U)
27960 #define DDRPHY_DX4GTR0_WLSL_SHIFT                (16U)
27961 /*! WLSL - Write Leveling System Latency
27962  */
27963 #define DDRPHY_DX4GTR0_WLSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_WLSL_SHIFT)) & DDRPHY_DX4GTR0_WLSL_MASK)
27964 #define DDRPHY_DX4GTR0_RESERVED_23_20_MASK       (0xF00000U)
27965 #define DDRPHY_DX4GTR0_RESERVED_23_20_SHIFT      (20U)
27966 /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
27967  */
27968 #define DDRPHY_DX4GTR0_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_23_20_MASK)
27969 #define DDRPHY_DX4GTR0_WDQSL_MASK                (0x7000000U)
27970 #define DDRPHY_DX4GTR0_WDQSL_SHIFT               (24U)
27971 /*! WDQSL - DQ Write Path Latency Pipeline
27972  */
27973 #define DDRPHY_DX4GTR0_WDQSL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_WDQSL_SHIFT)) & DDRPHY_DX4GTR0_WDQSL_MASK)
27974 #define DDRPHY_DX4GTR0_RESERVED_31_24_MASK       (0xF8000000U)
27975 #define DDRPHY_DX4GTR0_RESERVED_31_24_SHIFT      (27U)
27976 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
27977  */
27978 #define DDRPHY_DX4GTR0_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_31_24_MASK)
27979 /*! @} */
27980 
27981 /*! @name DX4RSR0 - DATX8 n Rank Status Register 0 */
27982 /*! @{ */
27983 #define DDRPHY_DX4RSR0_QSGERR_MASK               (0xFFFFU)
27984 #define DDRPHY_DX4RSR0_QSGERR_SHIFT              (0U)
27985 /*! QSGERR - DQS Gate Training Error
27986  */
27987 #define DDRPHY_DX4RSR0_QSGERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR0_QSGERR_SHIFT)) & DDRPHY_DX4RSR0_QSGERR_MASK)
27988 #define DDRPHY_DX4RSR0_RESERVED_31_16_MASK       (0xFFFF0000U)
27989 #define DDRPHY_DX4RSR0_RESERVED_31_16_SHIFT      (16U)
27990 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
27991  */
27992 #define DDRPHY_DX4RSR0_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR0_RESERVED_31_16_MASK)
27993 /*! @} */
27994 
27995 /*! @name DX4RSR1 - DATX8 n Rank Status Register 1 */
27996 /*! @{ */
27997 #define DDRPHY_DX4RSR1_RDLVLERR_MASK             (0xFFFFU)
27998 #define DDRPHY_DX4RSR1_RDLVLERR_SHIFT            (0U)
27999 /*! RDLVLERR - Read Leveling Error
28000  */
28001 #define DDRPHY_DX4RSR1_RDLVLERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX4RSR1_RDLVLERR_MASK)
28002 #define DDRPHY_DX4RSR1_RESERVED_31_16_MASK       (0xFFFF0000U)
28003 #define DDRPHY_DX4RSR1_RESERVED_31_16_SHIFT      (16U)
28004 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
28005  */
28006 #define DDRPHY_DX4RSR1_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR1_RESERVED_31_16_MASK)
28007 /*! @} */
28008 
28009 /*! @name DX4RSR2 - DATX8 n Rank Status Register 2 */
28010 /*! @{ */
28011 #define DDRPHY_DX4RSR2_WLAWN_MASK                (0xFFFFU)
28012 #define DDRPHY_DX4RSR2_WLAWN_SHIFT               (0U)
28013 /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
28014  */
28015 #define DDRPHY_DX4RSR2_WLAWN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR2_WLAWN_SHIFT)) & DDRPHY_DX4RSR2_WLAWN_MASK)
28016 #define DDRPHY_DX4RSR2_RESERVED_31_16_MASK       (0xFFFF0000U)
28017 #define DDRPHY_DX4RSR2_RESERVED_31_16_SHIFT      (16U)
28018 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
28019  */
28020 #define DDRPHY_DX4RSR2_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR2_RESERVED_31_16_MASK)
28021 /*! @} */
28022 
28023 /*! @name DX4RSR3 - DATX8 n Rank Status Register 3 */
28024 /*! @{ */
28025 #define DDRPHY_DX4RSR3_WLAERR_MASK               (0xFFFFU)
28026 #define DDRPHY_DX4RSR3_WLAERR_SHIFT              (0U)
28027 /*! WLAERR - Write Leveling Adjustment Error
28028  */
28029 #define DDRPHY_DX4RSR3_WLAERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR3_WLAERR_SHIFT)) & DDRPHY_DX4RSR3_WLAERR_MASK)
28030 #define DDRPHY_DX4RSR3_RESERVED_31_16_MASK       (0xFFFF0000U)
28031 #define DDRPHY_DX4RSR3_RESERVED_31_16_SHIFT      (16U)
28032 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
28033  */
28034 #define DDRPHY_DX4RSR3_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR3_RESERVED_31_16_MASK)
28035 /*! @} */
28036 
28037 /*! @name DX4GSR0 - DATX8 n General Status Register 0 */
28038 /*! @{ */
28039 #define DDRPHY_DX4GSR0_WDQCAL_MASK               (0x1U)
28040 #define DDRPHY_DX4GSR0_WDQCAL_SHIFT              (0U)
28041 /*! WDQCAL - Write DQ Calibration
28042  */
28043 #define DDRPHY_DX4GSR0_WDQCAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WDQCAL_SHIFT)) & DDRPHY_DX4GSR0_WDQCAL_MASK)
28044 #define DDRPHY_DX4GSR0_RDQSCAL_MASK              (0x2U)
28045 #define DDRPHY_DX4GSR0_RDQSCAL_SHIFT             (1U)
28046 /*! RDQSCAL - Read DQS Calibration
28047  */
28048 #define DDRPHY_DX4GSR0_RDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX4GSR0_RDQSCAL_MASK)
28049 #define DDRPHY_DX4GSR0_RDQSNCAL_MASK             (0x4U)
28050 #define DDRPHY_DX4GSR0_RDQSNCAL_SHIFT            (2U)
28051 /*! RDQSNCAL - Read DQS# Calibration
28052  */
28053 #define DDRPHY_DX4GSR0_RDQSNCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX4GSR0_RDQSNCAL_MASK)
28054 #define DDRPHY_DX4GSR0_GDQSCAL_MASK              (0x8U)
28055 #define DDRPHY_DX4GSR0_GDQSCAL_SHIFT             (3U)
28056 /*! GDQSCAL - Read DQS gating Calibration
28057  */
28058 #define DDRPHY_DX4GSR0_GDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX4GSR0_GDQSCAL_MASK)
28059 #define DDRPHY_DX4GSR0_WLCAL_MASK                (0x10U)
28060 #define DDRPHY_DX4GSR0_WLCAL_SHIFT               (4U)
28061 /*! WLCAL - Write Leveling Calibration
28062  */
28063 #define DDRPHY_DX4GSR0_WLCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLCAL_SHIFT)) & DDRPHY_DX4GSR0_WLCAL_MASK)
28064 #define DDRPHY_DX4GSR0_WLDONE_MASK               (0x20U)
28065 #define DDRPHY_DX4GSR0_WLDONE_SHIFT              (5U)
28066 /*! WLDONE - Write Leveling Done
28067  */
28068 #define DDRPHY_DX4GSR0_WLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLDONE_SHIFT)) & DDRPHY_DX4GSR0_WLDONE_MASK)
28069 #define DDRPHY_DX4GSR0_WLERR_MASK                (0x40U)
28070 #define DDRPHY_DX4GSR0_WLERR_SHIFT               (6U)
28071 /*! WLERR - Write Leveling Error
28072  */
28073 #define DDRPHY_DX4GSR0_WLERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLERR_SHIFT)) & DDRPHY_DX4GSR0_WLERR_MASK)
28074 #define DDRPHY_DX4GSR0_WLPRD_MASK                (0xFF80U)
28075 #define DDRPHY_DX4GSR0_WLPRD_SHIFT               (7U)
28076 /*! WLPRD - Write Leveling Period
28077  */
28078 #define DDRPHY_DX4GSR0_WLPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLPRD_SHIFT)) & DDRPHY_DX4GSR0_WLPRD_MASK)
28079 #define DDRPHY_DX4GSR0_DPLOCK_MASK               (0x10000U)
28080 #define DDRPHY_DX4GSR0_DPLOCK_SHIFT              (16U)
28081 /*! DPLOCK - DATX8 PLL Lock
28082  */
28083 #define DDRPHY_DX4GSR0_DPLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_DPLOCK_SHIFT)) & DDRPHY_DX4GSR0_DPLOCK_MASK)
28084 #define DDRPHY_DX4GSR0_GDQSPRD_MASK              (0x3FE0000U)
28085 #define DDRPHY_DX4GSR0_GDQSPRD_SHIFT             (17U)
28086 /*! GDQSPRD - Read DQS gating Period
28087  */
28088 #define DDRPHY_DX4GSR0_GDQSPRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX4GSR0_GDQSPRD_MASK)
28089 #define DDRPHY_DX4GSR0_RESERVED_29_26_MASK       (0x3C000000U)
28090 #define DDRPHY_DX4GSR0_RESERVED_29_26_SHIFT      (26U)
28091 /*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
28092  */
28093 #define DDRPHY_DX4GSR0_RESERVED_29_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX4GSR0_RESERVED_29_26_MASK)
28094 #define DDRPHY_DX4GSR0_WLDQ_MASK                 (0x40000000U)
28095 #define DDRPHY_DX4GSR0_WLDQ_SHIFT                (30U)
28096 /*! WLDQ - Write Leveling DQ Status
28097  */
28098 #define DDRPHY_DX4GSR0_WLDQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLDQ_SHIFT)) & DDRPHY_DX4GSR0_WLDQ_MASK)
28099 #define DDRPHY_DX4GSR0_RESERVED_31_MASK          (0x80000000U)
28100 #define DDRPHY_DX4GSR0_RESERVED_31_SHIFT         (31U)
28101 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
28102  */
28103 #define DDRPHY_DX4GSR0_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX4GSR0_RESERVED_31_MASK)
28104 /*! @} */
28105 
28106 /*! @name DX4GSR1 - DATX8 n General Status Register 1 */
28107 /*! @{ */
28108 #define DDRPHY_DX4GSR1_DLTDONE_MASK              (0x1U)
28109 #define DDRPHY_DX4GSR1_DLTDONE_SHIFT             (0U)
28110 /*! DLTDONE - Delay Line Test Done
28111  */
28112 #define DDRPHY_DX4GSR1_DLTDONE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR1_DLTDONE_SHIFT)) & DDRPHY_DX4GSR1_DLTDONE_MASK)
28113 #define DDRPHY_DX4GSR1_DLTCODE_MASK              (0x1FFFFFEU)
28114 #define DDRPHY_DX4GSR1_DLTCODE_SHIFT             (1U)
28115 /*! DLTCODE - Delay Line Test Code
28116  */
28117 #define DDRPHY_DX4GSR1_DLTCODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR1_DLTCODE_SHIFT)) & DDRPHY_DX4GSR1_DLTCODE_MASK)
28118 #define DDRPHY_DX4GSR1_RESERVED_31_25_MASK       (0xFE000000U)
28119 #define DDRPHY_DX4GSR1_RESERVED_31_25_SHIFT      (25U)
28120 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
28121  */
28122 #define DDRPHY_DX4GSR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX4GSR1_RESERVED_31_25_MASK)
28123 /*! @} */
28124 
28125 /*! @name DX4GSR2 - DATX8 n General Status Register 2 */
28126 /*! @{ */
28127 #define DDRPHY_DX4GSR2_RDERR_MASK                (0x1U)
28128 #define DDRPHY_DX4GSR2_RDERR_SHIFT               (0U)
28129 /*! RDERR - Read Bit Deskew Error
28130  */
28131 #define DDRPHY_DX4GSR2_RDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_RDERR_SHIFT)) & DDRPHY_DX4GSR2_RDERR_MASK)
28132 #define DDRPHY_DX4GSR2_RDWN_MASK                 (0x2U)
28133 #define DDRPHY_DX4GSR2_RDWN_SHIFT                (1U)
28134 /*! RDWN - Read Bit Deskew Warning
28135  */
28136 #define DDRPHY_DX4GSR2_RDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_RDWN_SHIFT)) & DDRPHY_DX4GSR2_RDWN_MASK)
28137 #define DDRPHY_DX4GSR2_WDERR_MASK                (0x4U)
28138 #define DDRPHY_DX4GSR2_WDERR_SHIFT               (2U)
28139 /*! WDERR - Write Bit Deskew Error
28140  */
28141 #define DDRPHY_DX4GSR2_WDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WDERR_SHIFT)) & DDRPHY_DX4GSR2_WDERR_MASK)
28142 #define DDRPHY_DX4GSR2_WDWN_MASK                 (0x8U)
28143 #define DDRPHY_DX4GSR2_WDWN_SHIFT                (3U)
28144 /*! WDWN - Write Bit Deskew Warning
28145  */
28146 #define DDRPHY_DX4GSR2_WDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WDWN_SHIFT)) & DDRPHY_DX4GSR2_WDWN_MASK)
28147 #define DDRPHY_DX4GSR2_REERR_MASK                (0x10U)
28148 #define DDRPHY_DX4GSR2_REERR_SHIFT               (4U)
28149 /*! REERR - Read Eye Centering Error
28150  */
28151 #define DDRPHY_DX4GSR2_REERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_REERR_SHIFT)) & DDRPHY_DX4GSR2_REERR_MASK)
28152 #define DDRPHY_DX4GSR2_REWN_MASK                 (0x20U)
28153 #define DDRPHY_DX4GSR2_REWN_SHIFT                (5U)
28154 /*! REWN - Read Eye Centering Warning
28155  */
28156 #define DDRPHY_DX4GSR2_REWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_REWN_SHIFT)) & DDRPHY_DX4GSR2_REWN_MASK)
28157 #define DDRPHY_DX4GSR2_WEERR_MASK                (0x40U)
28158 #define DDRPHY_DX4GSR2_WEERR_SHIFT               (6U)
28159 /*! WEERR - Write Eye Centering Error
28160  */
28161 #define DDRPHY_DX4GSR2_WEERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WEERR_SHIFT)) & DDRPHY_DX4GSR2_WEERR_MASK)
28162 #define DDRPHY_DX4GSR2_WEWN_MASK                 (0x80U)
28163 #define DDRPHY_DX4GSR2_WEWN_SHIFT                (7U)
28164 /*! WEWN - Write Eye Centering Warning
28165  */
28166 #define DDRPHY_DX4GSR2_WEWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WEWN_SHIFT)) & DDRPHY_DX4GSR2_WEWN_MASK)
28167 #define DDRPHY_DX4GSR2_ESTAT_MASK                (0xF00U)
28168 #define DDRPHY_DX4GSR2_ESTAT_SHIFT               (8U)
28169 /*! ESTAT - Error Status
28170  */
28171 #define DDRPHY_DX4GSR2_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_ESTAT_SHIFT)) & DDRPHY_DX4GSR2_ESTAT_MASK)
28172 #define DDRPHY_DX4GSR2_DQS2DQERR_MASK            (0xFF000U)
28173 #define DDRPHY_DX4GSR2_DQS2DQERR_SHIFT           (12U)
28174 /*! DQS2DQERR - Write DQS2DQ Training Error
28175  */
28176 #define DDRPHY_DX4GSR2_DQS2DQERR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX4GSR2_DQS2DQERR_MASK)
28177 #define DDRPHY_DX4GSR2_SRDERR_MASK               (0x100000U)
28178 #define DDRPHY_DX4GSR2_SRDERR_SHIFT              (20U)
28179 /*! SRDERR - Static Read Error
28180  */
28181 #define DDRPHY_DX4GSR2_SRDERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_SRDERR_SHIFT)) & DDRPHY_DX4GSR2_SRDERR_MASK)
28182 #define DDRPHY_DX4GSR2_RESERVED_21_MASK          (0x200000U)
28183 #define DDRPHY_DX4GSR2_RESERVED_21_SHIFT         (21U)
28184 /*! RESERVED_21 - Reserved. Return zeroes on reads.
28185  */
28186 #define DDRPHY_DX4GSR2_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX4GSR2_RESERVED_21_MASK)
28187 #define DDRPHY_DX4GSR2_GSDQSCAL_MASK             (0x400000U)
28188 #define DDRPHY_DX4GSR2_GSDQSCAL_SHIFT            (22U)
28189 /*! GSDQSCAL - Read DQS Gating Status Calibration
28190  */
28191 #define DDRPHY_DX4GSR2_GSDQSCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX4GSR2_GSDQSCAL_MASK)
28192 #define DDRPHY_DX4GSR2_GSDQSPRD_MASK             (0xFF800000U)
28193 #define DDRPHY_DX4GSR2_GSDQSPRD_SHIFT            (23U)
28194 /*! GSDQSPRD - Read DQS gating Status Period
28195  */
28196 #define DDRPHY_DX4GSR2_GSDQSPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX4GSR2_GSDQSPRD_MASK)
28197 /*! @} */
28198 
28199 /*! @name DX4GSR3 - DATX8 n General Status Register 3 */
28200 /*! @{ */
28201 #define DDRPHY_DX4GSR3_SRDPC_MASK                (0x3U)
28202 #define DDRPHY_DX4GSR3_SRDPC_SHIFT               (0U)
28203 /*! SRDPC - Static Read Delay Pass Count
28204  */
28205 #define DDRPHY_DX4GSR3_SRDPC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_SRDPC_SHIFT)) & DDRPHY_DX4GSR3_SRDPC_MASK)
28206 #define DDRPHY_DX4GSR3_RESERVED_7_2_MASK         (0xFCU)
28207 #define DDRPHY_DX4GSR3_RESERVED_7_2_SHIFT        (2U)
28208 /*! RESERVED_7_2 - Reserved. Return zeroes on reads.
28209  */
28210 #define DDRPHY_DX4GSR3_RESERVED_7_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX4GSR3_RESERVED_7_2_MASK)
28211 #define DDRPHY_DX4GSR3_HVERR_MASK                (0xF00U)
28212 #define DDRPHY_DX4GSR3_HVERR_SHIFT               (8U)
28213 /*! HVERR - Host VREF Training Error
28214  */
28215 #define DDRPHY_DX4GSR3_HVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_HVERR_SHIFT)) & DDRPHY_DX4GSR3_HVERR_MASK)
28216 #define DDRPHY_DX4GSR3_HVWRN_MASK                (0xF000U)
28217 #define DDRPHY_DX4GSR3_HVWRN_SHIFT               (12U)
28218 /*! HVWRN - Host VREF Training Warning
28219  */
28220 #define DDRPHY_DX4GSR3_HVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_HVWRN_SHIFT)) & DDRPHY_DX4GSR3_HVWRN_MASK)
28221 #define DDRPHY_DX4GSR3_DVERR_MASK                (0xF0000U)
28222 #define DDRPHY_DX4GSR3_DVERR_SHIFT               (16U)
28223 /*! DVERR - DRAM VREF Training Error
28224  */
28225 #define DDRPHY_DX4GSR3_DVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_DVERR_SHIFT)) & DDRPHY_DX4GSR3_DVERR_MASK)
28226 #define DDRPHY_DX4GSR3_DVWRN_MASK                (0xF00000U)
28227 #define DDRPHY_DX4GSR3_DVWRN_SHIFT               (20U)
28228 /*! DVWRN - DRAM VREF Training Warning
28229  */
28230 #define DDRPHY_DX4GSR3_DVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_DVWRN_SHIFT)) & DDRPHY_DX4GSR3_DVWRN_MASK)
28231 #define DDRPHY_DX4GSR3_ESTAT_MASK                (0x7000000U)
28232 #define DDRPHY_DX4GSR3_ESTAT_SHIFT               (24U)
28233 /*! ESTAT - VREF Training Error Status Code
28234  */
28235 #define DDRPHY_DX4GSR3_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_ESTAT_SHIFT)) & DDRPHY_DX4GSR3_ESTAT_MASK)
28236 #define DDRPHY_DX4GSR3_RESERVED_31_27_MASK       (0xF8000000U)
28237 #define DDRPHY_DX4GSR3_RESERVED_31_27_SHIFT      (27U)
28238 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
28239  */
28240 #define DDRPHY_DX4GSR3_RESERVED_31_27(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX4GSR3_RESERVED_31_27_MASK)
28241 /*! @} */
28242 
28243 /*! @name DX4GSR4 - DATX8 n General Status Register 4 */
28244 /*! @{ */
28245 #define DDRPHY_DX4GSR4_RESERVED_0_MASK           (0x1U)
28246 #define DDRPHY_DX4GSR4_RESERVED_0_SHIFT          (0U)
28247 /*! RESERVED_0 - Reserved. Return zeroes on reads.
28248  */
28249 #define DDRPHY_DX4GSR4_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_0_MASK)
28250 #define DDRPHY_DX4GSR4_RESERVED_1_MASK           (0x2U)
28251 #define DDRPHY_DX4GSR4_RESERVED_1_SHIFT          (1U)
28252 /*! RESERVED_1 - Reserved. Return zeroes on reads.
28253  */
28254 #define DDRPHY_DX4GSR4_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_1_MASK)
28255 #define DDRPHY_DX4GSR4_RESERVED_2_MASK           (0x4U)
28256 #define DDRPHY_DX4GSR4_RESERVED_2_SHIFT          (2U)
28257 /*! RESERVED_2 - Reserved. Return zeroes on reads.
28258  */
28259 #define DDRPHY_DX4GSR4_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_2_MASK)
28260 #define DDRPHY_DX4GSR4_RESERVED_3_MASK           (0x8U)
28261 #define DDRPHY_DX4GSR4_RESERVED_3_SHIFT          (3U)
28262 /*! RESERVED_3 - Reserved. Return zeroes on reads.
28263  */
28264 #define DDRPHY_DX4GSR4_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_3_MASK)
28265 #define DDRPHY_DX4GSR4_RESERVED_4_MASK           (0x10U)
28266 #define DDRPHY_DX4GSR4_RESERVED_4_SHIFT          (4U)
28267 /*! RESERVED_4 - Reserved. Return zeroes on reads.
28268  */
28269 #define DDRPHY_DX4GSR4_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_4_MASK)
28270 #define DDRPHY_DX4GSR4_RESERVED_5_MASK           (0x20U)
28271 #define DDRPHY_DX4GSR4_RESERVED_5_SHIFT          (5U)
28272 /*! RESERVED_5 - Reserved. Return zeroes on reads.
28273  */
28274 #define DDRPHY_DX4GSR4_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_5_MASK)
28275 #define DDRPHY_DX4GSR4_RESERVED_6_MASK           (0x40U)
28276 #define DDRPHY_DX4GSR4_RESERVED_6_SHIFT          (6U)
28277 /*! RESERVED_6 - Reserved. Return zeroes on reads.
28278  */
28279 #define DDRPHY_DX4GSR4_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_6_MASK)
28280 #define DDRPHY_DX4GSR4_RESERVED_15_7_MASK        (0xFF80U)
28281 #define DDRPHY_DX4GSR4_RESERVED_15_7_SHIFT       (7U)
28282 /*! RESERVED_15_7 - Reserved. Return zeroes on reads.
28283  */
28284 #define DDRPHY_DX4GSR4_RESERVED_15_7(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_15_7_MASK)
28285 #define DDRPHY_DX4GSR4_RESERVED_16_MASK          (0x10000U)
28286 #define DDRPHY_DX4GSR4_RESERVED_16_SHIFT         (16U)
28287 /*! RESERVED_16 - Reserved. Return zeroes on reads.
28288  */
28289 #define DDRPHY_DX4GSR4_RESERVED_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_16_MASK)
28290 #define DDRPHY_DX4GSR4_RESERVED_25_17_MASK       (0x3FE0000U)
28291 #define DDRPHY_DX4GSR4_RESERVED_25_17_SHIFT      (17U)
28292 /*! RESERVED_25_17 - Reserved. Return zeroes on reads.
28293  */
28294 #define DDRPHY_DX4GSR4_RESERVED_25_17(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_25_17_MASK)
28295 #define DDRPHY_DX4GSR4_RESERVED_31_26_MASK       (0xFC000000U)
28296 #define DDRPHY_DX4GSR4_RESERVED_31_26_SHIFT      (26U)
28297 /*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
28298  */
28299 #define DDRPHY_DX4GSR4_RESERVED_31_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_31_26_MASK)
28300 /*! @} */
28301 
28302 /*! @name DX4GSR5 - DATX8 n General Status Register 5 */
28303 /*! @{ */
28304 #define DDRPHY_DX4GSR5_RESERVED_0_MASK           (0x1U)
28305 #define DDRPHY_DX4GSR5_RESERVED_0_SHIFT          (0U)
28306 /*! RESERVED_0 - Reserved. Return zeroes on reads.
28307  */
28308 #define DDRPHY_DX4GSR5_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_0_MASK)
28309 #define DDRPHY_DX4GSR5_RESERVED_1_MASK           (0x2U)
28310 #define DDRPHY_DX4GSR5_RESERVED_1_SHIFT          (1U)
28311 /*! RESERVED_1 - Reserved. Return zeroes on reads.
28312  */
28313 #define DDRPHY_DX4GSR5_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_1_MASK)
28314 #define DDRPHY_DX4GSR5_RESERVED_2_MASK           (0x4U)
28315 #define DDRPHY_DX4GSR5_RESERVED_2_SHIFT          (2U)
28316 /*! RESERVED_2 - Reserved. Return zeroes on reads.
28317  */
28318 #define DDRPHY_DX4GSR5_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_2_MASK)
28319 #define DDRPHY_DX4GSR5_RESERVED_3_MASK           (0x8U)
28320 #define DDRPHY_DX4GSR5_RESERVED_3_SHIFT          (3U)
28321 /*! RESERVED_3 - Reserved. Return zeroes on reads.
28322  */
28323 #define DDRPHY_DX4GSR5_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_3_MASK)
28324 #define DDRPHY_DX4GSR5_RESERVED_4_MASK           (0x10U)
28325 #define DDRPHY_DX4GSR5_RESERVED_4_SHIFT          (4U)
28326 /*! RESERVED_4 - Reserved. Return zeroes on reads.
28327  */
28328 #define DDRPHY_DX4GSR5_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_4_MASK)
28329 #define DDRPHY_DX4GSR5_RESERVED_5_MASK           (0x20U)
28330 #define DDRPHY_DX4GSR5_RESERVED_5_SHIFT          (5U)
28331 /*! RESERVED_5 - Reserved. Return zeroes on reads.
28332  */
28333 #define DDRPHY_DX4GSR5_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_5_MASK)
28334 #define DDRPHY_DX4GSR5_RESERVED_6_MASK           (0x40U)
28335 #define DDRPHY_DX4GSR5_RESERVED_6_SHIFT          (6U)
28336 /*! RESERVED_6 - Reserved. Return zeroes on reads.
28337  */
28338 #define DDRPHY_DX4GSR5_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_6_MASK)
28339 #define DDRPHY_DX4GSR5_RESERVED_7_MASK           (0x80U)
28340 #define DDRPHY_DX4GSR5_RESERVED_7_SHIFT          (7U)
28341 /*! RESERVED_7 - Reserved. Return zeroes on reads.
28342  */
28343 #define DDRPHY_DX4GSR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_7_MASK)
28344 #define DDRPHY_DX4GSR5_RESERVED_11_8_MASK        (0xF00U)
28345 #define DDRPHY_DX4GSR5_RESERVED_11_8_SHIFT       (8U)
28346 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
28347  */
28348 #define DDRPHY_DX4GSR5_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_11_8_MASK)
28349 #define DDRPHY_DX4GSR5_RESERVED_19_12_MASK       (0xFF000U)
28350 #define DDRPHY_DX4GSR5_RESERVED_19_12_SHIFT      (12U)
28351 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
28352  */
28353 #define DDRPHY_DX4GSR5_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_19_12_MASK)
28354 #define DDRPHY_DX4GSR5_RESERVED_20_MASK          (0x100000U)
28355 #define DDRPHY_DX4GSR5_RESERVED_20_SHIFT         (20U)
28356 /*! RESERVED_20 - Reserved. Return zeroes on reads.
28357  */
28358 #define DDRPHY_DX4GSR5_RESERVED_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_20_MASK)
28359 #define DDRPHY_DX4GSR5_RESERVED_21_MASK          (0x200000U)
28360 #define DDRPHY_DX4GSR5_RESERVED_21_SHIFT         (21U)
28361 /*! RESERVED_21 - Reserved. Return zeroes on reads.
28362  */
28363 #define DDRPHY_DX4GSR5_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_21_MASK)
28364 #define DDRPHY_DX4GSR5_RESERVED_22_MASK          (0x400000U)
28365 #define DDRPHY_DX4GSR5_RESERVED_22_SHIFT         (22U)
28366 /*! RESERVED_22 - Reserved. Return zeroes on reads.
28367  */
28368 #define DDRPHY_DX4GSR5_RESERVED_22(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_22_MASK)
28369 #define DDRPHY_DX4GSR5_RESERVED_31_23_MASK       (0xFF800000U)
28370 #define DDRPHY_DX4GSR5_RESERVED_31_23_SHIFT      (23U)
28371 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
28372  */
28373 #define DDRPHY_DX4GSR5_RESERVED_31_23(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_31_23_MASK)
28374 /*! @} */
28375 
28376 /*! @name DX4GSR6 - DATX8 n General Status Register 6 */
28377 /*! @{ */
28378 #define DDRPHY_DX4GSR6_RESERVED_1_0_MASK         (0x3U)
28379 #define DDRPHY_DX4GSR6_RESERVED_1_0_SHIFT        (0U)
28380 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
28381  */
28382 #define DDRPHY_DX4GSR6_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_1_0_MASK)
28383 #define DDRPHY_DX4GSR6_RESERVED_3_2_MASK         (0xCU)
28384 #define DDRPHY_DX4GSR6_RESERVED_3_2_SHIFT        (2U)
28385 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
28386  */
28387 #define DDRPHY_DX4GSR6_RESERVED_3_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_3_2_MASK)
28388 #define DDRPHY_DX4GSR6_RESERVED_7_4_MASK         (0xF0U)
28389 #define DDRPHY_DX4GSR6_RESERVED_7_4_SHIFT        (4U)
28390 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
28391  */
28392 #define DDRPHY_DX4GSR6_RESERVED_7_4(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_7_4_MASK)
28393 #define DDRPHY_DX4GSR6_RESERVED_11_8_MASK        (0xF00U)
28394 #define DDRPHY_DX4GSR6_RESERVED_11_8_SHIFT       (8U)
28395 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
28396  */
28397 #define DDRPHY_DX4GSR6_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_11_8_MASK)
28398 #define DDRPHY_DX4GSR6_RESERVED_15_12_MASK       (0xF000U)
28399 #define DDRPHY_DX4GSR6_RESERVED_15_12_SHIFT      (12U)
28400 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
28401  */
28402 #define DDRPHY_DX4GSR6_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_15_12_MASK)
28403 #define DDRPHY_DX4GSR6_RESERVED_19_15_MASK       (0xF0000U)
28404 #define DDRPHY_DX4GSR6_RESERVED_19_15_SHIFT      (16U)
28405 /*! RESERVED_19_15 - Reserved. Return zeroes on reads.
28406  */
28407 #define DDRPHY_DX4GSR6_RESERVED_19_15(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_19_15_MASK)
28408 #define DDRPHY_DX4GSR6_RESERVED_23_20_MASK       (0xF00000U)
28409 #define DDRPHY_DX4GSR6_RESERVED_23_20_SHIFT      (20U)
28410 /*! RESERVED_23_20 - Reserved. Return zeroes on reads.
28411  */
28412 #define DDRPHY_DX4GSR6_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_23_20_MASK)
28413 #define DDRPHY_DX4GSR6_RESERVED_31_24_MASK       (0xFF000000U)
28414 #define DDRPHY_DX4GSR6_RESERVED_31_24_SHIFT      (24U)
28415 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
28416  */
28417 #define DDRPHY_DX4GSR6_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_31_24_MASK)
28418 /*! @} */
28419 
28420 /*! @name DX5GCR0 - DATX8 n General Configuration Register 0 */
28421 /*! @{ */
28422 #define DDRPHY_DX5GCR0_RESERVED_1_0_MASK         (0x3U)
28423 #define DDRPHY_DX5GCR0_RESERVED_1_0_SHIFT        (0U)
28424 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
28425  */
28426 #define DDRPHY_DX5GCR0_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX5GCR0_RESERVED_1_0_MASK)
28427 #define DDRPHY_DX5GCR0_DQSGOE_MASK               (0x4U)
28428 #define DDRPHY_DX5GCR0_DQSGOE_SHIFT              (2U)
28429 /*! DQSGOE - DQSG Output Enable
28430  */
28431 #define DDRPHY_DX5GCR0_DQSGOE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSGOE_SHIFT)) & DDRPHY_DX5GCR0_DQSGOE_MASK)
28432 #define DDRPHY_DX5GCR0_DQSGODT_MASK              (0x8U)
28433 #define DDRPHY_DX5GCR0_DQSGODT_SHIFT             (3U)
28434 /*! DQSGODT - DQSG On-Die Termination
28435  */
28436 #define DDRPHY_DX5GCR0_DQSGODT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSGODT_SHIFT)) & DDRPHY_DX5GCR0_DQSGODT_MASK)
28437 #define DDRPHY_DX5GCR0_RESERVED_4_MASK           (0x10U)
28438 #define DDRPHY_DX5GCR0_RESERVED_4_SHIFT          (4U)
28439 /*! RESERVED_4 - Reserved. Return zeroes on reads.
28440  */
28441 #define DDRPHY_DX5GCR0_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX5GCR0_RESERVED_4_MASK)
28442 #define DDRPHY_DX5GCR0_DQSGPDR_MASK              (0x20U)
28443 #define DDRPHY_DX5GCR0_DQSGPDR_SHIFT             (5U)
28444 /*! DQSGPDR - DQSG Power Down Receiver
28445  */
28446 #define DDRPHY_DX5GCR0_DQSGPDR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX5GCR0_DQSGPDR_MASK)
28447 #define DDRPHY_DX5GCR0_DQSRPD_MASK               (0x40U)
28448 #define DDRPHY_DX5GCR0_DQSRPD_SHIFT              (6U)
28449 /*! DQSRPD - DQSR Power Down
28450  */
28451 #define DDRPHY_DX5GCR0_DQSRPD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSRPD_SHIFT)) & DDRPHY_DX5GCR0_DQSRPD_MASK)
28452 #define DDRPHY_DX5GCR0_CPDRSHFT_MASK             (0x180U)
28453 #define DDRPHY_DX5GCR0_CPDRSHFT_SHIFT            (7U)
28454 /*! CPDRSHFT - Configurable PDR Phase Shift
28455  */
28456 #define DDRPHY_DX5GCR0_CPDRSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX5GCR0_CPDRSHFT_MASK)
28457 #define DDRPHY_DX5GCR0_RTTOH_MASK                (0x600U)
28458 #define DDRPHY_DX5GCR0_RTTOH_SHIFT               (9U)
28459 /*! RTTOH - RTT Output Hold
28460  */
28461 #define DDRPHY_DX5GCR0_RTTOH(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RTTOH_SHIFT)) & DDRPHY_DX5GCR0_RTTOH_MASK)
28462 #define DDRPHY_DX5GCR0_RTTOAL_MASK               (0x800U)
28463 #define DDRPHY_DX5GCR0_RTTOAL_SHIFT              (11U)
28464 /*! RTTOAL - RTT On Additive Latency
28465  */
28466 #define DDRPHY_DX5GCR0_RTTOAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RTTOAL_SHIFT)) & DDRPHY_DX5GCR0_RTTOAL_MASK)
28467 #define DDRPHY_DX5GCR0_DQSSEPDR_MASK             (0x1000U)
28468 #define DDRPHY_DX5GCR0_DQSSEPDR_SHIFT            (12U)
28469 /*! DQSSEPDR - DQSSE Power Down Receiver
28470  */
28471 #define DDRPHY_DX5GCR0_DQSSEPDR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX5GCR0_DQSSEPDR_MASK)
28472 #define DDRPHY_DX5GCR0_DQSNSEPDR_MASK            (0x2000U)
28473 #define DDRPHY_DX5GCR0_DQSNSEPDR_SHIFT           (13U)
28474 /*! DQSNSEPDR - DQSNSE Power Down Receiver
28475  */
28476 #define DDRPHY_DX5GCR0_DQSNSEPDR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX5GCR0_DQSNSEPDR_MASK)
28477 #define DDRPHY_DX5GCR0_RESERVED_19_14_MASK       (0xFC000U)
28478 #define DDRPHY_DX5GCR0_RESERVED_19_14_SHIFT      (14U)
28479 /*! RESERVED_19_14 - Reserved. Return zeroes on reads.
28480  */
28481 #define DDRPHY_DX5GCR0_RESERVED_19_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX5GCR0_RESERVED_19_14_MASK)
28482 #define DDRPHY_DX5GCR0_RDDLY_MASK                (0xF00000U)
28483 #define DDRPHY_DX5GCR0_RDDLY_SHIFT               (20U)
28484 /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
28485  */
28486 #define DDRPHY_DX5GCR0_RDDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RDDLY_SHIFT)) & DDRPHY_DX5GCR0_RDDLY_MASK)
28487 #define DDRPHY_DX5GCR0_DQSDCC_MASK               (0xF000000U)
28488 #define DDRPHY_DX5GCR0_DQSDCC_SHIFT              (24U)
28489 /*! DQSDCC - DQS Duty Cycle Correction
28490  */
28491 #define DDRPHY_DX5GCR0_DQSDCC(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSDCC_SHIFT)) & DDRPHY_DX5GCR0_DQSDCC_MASK)
28492 #define DDRPHY_DX5GCR0_CODTSHFT_MASK             (0x30000000U)
28493 #define DDRPHY_DX5GCR0_CODTSHFT_SHIFT            (28U)
28494 /*! CODTSHFT - Configurable ODT(TE) Phase Shift
28495  */
28496 #define DDRPHY_DX5GCR0_CODTSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX5GCR0_CODTSHFT_MASK)
28497 #define DDRPHY_DX5GCR0_MDLEN_MASK                (0x40000000U)
28498 #define DDRPHY_DX5GCR0_MDLEN_SHIFT               (30U)
28499 /*! MDLEN - Master Delay Line Enable
28500  */
28501 #define DDRPHY_DX5GCR0_MDLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_MDLEN_SHIFT)) & DDRPHY_DX5GCR0_MDLEN_MASK)
28502 #define DDRPHY_DX5GCR0_CALBYP_MASK               (0x80000000U)
28503 #define DDRPHY_DX5GCR0_CALBYP_SHIFT              (31U)
28504 /*! CALBYP - Calibration Bypass
28505  */
28506 #define DDRPHY_DX5GCR0_CALBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_CALBYP_SHIFT)) & DDRPHY_DX5GCR0_CALBYP_MASK)
28507 /*! @} */
28508 
28509 /*! @name DX5GCR1 - DATX8 n General Configuration Register 1 */
28510 /*! @{ */
28511 #define DDRPHY_DX5GCR1_DQEN_MASK                 (0xFFU)
28512 #define DDRPHY_DX5GCR1_DQEN_SHIFT                (0U)
28513 /*! DQEN - Enables DQ corresponding to each bit in a byte
28514  */
28515 #define DDRPHY_DX5GCR1_DQEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DQEN_SHIFT)) & DDRPHY_DX5GCR1_DQEN_MASK)
28516 #define DDRPHY_DX5GCR1_DMEN_MASK                 (0x100U)
28517 #define DDRPHY_DX5GCR1_DMEN_SHIFT                (8U)
28518 /*! DMEN - Enables DM pin in a byte lane
28519  */
28520 #define DDRPHY_DX5GCR1_DMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DMEN_SHIFT)) & DDRPHY_DX5GCR1_DMEN_MASK)
28521 #define DDRPHY_DX5GCR1_DSEN_MASK                 (0x200U)
28522 #define DDRPHY_DX5GCR1_DSEN_SHIFT                (9U)
28523 /*! DSEN - Enables Write Data strobe in a byte lane
28524  */
28525 #define DDRPHY_DX5GCR1_DSEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DSEN_SHIFT)) & DDRPHY_DX5GCR1_DSEN_MASK)
28526 #define DDRPHY_DX5GCR1_TEEN_MASK                 (0x400U)
28527 #define DDRPHY_DX5GCR1_TEEN_SHIFT                (10U)
28528 /*! TEEN - Enables ODT/TE in a byte lane
28529  */
28530 #define DDRPHY_DX5GCR1_TEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_TEEN_SHIFT)) & DDRPHY_DX5GCR1_TEEN_MASK)
28531 #define DDRPHY_DX5GCR1_PDREN_MASK                (0x800U)
28532 #define DDRPHY_DX5GCR1_PDREN_SHIFT               (11U)
28533 /*! PDREN - Enables PDR in a byte lane
28534  */
28535 #define DDRPHY_DX5GCR1_PDREN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_PDREN_SHIFT)) & DDRPHY_DX5GCR1_PDREN_MASK)
28536 #define DDRPHY_DX5GCR1_OEEN_MASK                 (0x1000U)
28537 #define DDRPHY_DX5GCR1_OEEN_SHIFT                (12U)
28538 /*! OEEN - Enables Read Data Strobe in a byte lane
28539  */
28540 #define DDRPHY_DX5GCR1_OEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_OEEN_SHIFT)) & DDRPHY_DX5GCR1_OEEN_MASK)
28541 #define DDRPHY_DX5GCR1_QSSEL_MASK                (0x2000U)
28542 #define DDRPHY_DX5GCR1_QSSEL_SHIFT               (13U)
28543 /*! QSSEL - Select the delayed or non-delayed read data strobe
28544  */
28545 #define DDRPHY_DX5GCR1_QSSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_QSSEL_SHIFT)) & DDRPHY_DX5GCR1_QSSEL_MASK)
28546 #define DDRPHY_DX5GCR1_QSNSEL_MASK               (0x4000U)
28547 #define DDRPHY_DX5GCR1_QSNSEL_SHIFT              (14U)
28548 /*! QSNSEL - Select the delayed or non-delayed read data strobe #
28549  */
28550 #define DDRPHY_DX5GCR1_QSNSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_QSNSEL_SHIFT)) & DDRPHY_DX5GCR1_QSNSEL_MASK)
28551 #define DDRPHY_DX5GCR1_RESERVED_15_MASK          (0x8000U)
28552 #define DDRPHY_DX5GCR1_RESERVED_15_SHIFT         (15U)
28553 /*! RESERVED_15 - Reserved. Returns zeroes on reads.
28554  */
28555 #define DDRPHY_DX5GCR1_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX5GCR1_RESERVED_15_MASK)
28556 #define DDRPHY_DX5GCR1_DXPDRMODE_MASK            (0xFFFF0000U)
28557 #define DDRPHY_DX5GCR1_DXPDRMODE_SHIFT           (16U)
28558 /*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
28559  */
28560 #define DDRPHY_DX5GCR1_DXPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX5GCR1_DXPDRMODE_MASK)
28561 /*! @} */
28562 
28563 /*! @name DX5GCR2 - DATX8 n General Configuration Register 2 */
28564 /*! @{ */
28565 #define DDRPHY_DX5GCR2_DXTEMODE_MASK             (0xFFFFU)
28566 #define DDRPHY_DX5GCR2_DXTEMODE_SHIFT            (0U)
28567 /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
28568  */
28569 #define DDRPHY_DX5GCR2_DXTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX5GCR2_DXTEMODE_MASK)
28570 #define DDRPHY_DX5GCR2_DXOEMODE_MASK             (0xFFFF0000U)
28571 #define DDRPHY_DX5GCR2_DXOEMODE_SHIFT            (16U)
28572 /*! DXOEMODE - Enables the OE mode values for DQ[7:0]
28573  */
28574 #define DDRPHY_DX5GCR2_DXOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX5GCR2_DXOEMODE_MASK)
28575 /*! @} */
28576 
28577 /*! @name DX5GCR3 - DATX8 n General Configuration Register 3 */
28578 /*! @{ */
28579 #define DDRPHY_DX5GCR3_WDMBVT_MASK               (0x1U)
28580 #define DDRPHY_DX5GCR3_WDMBVT_SHIFT              (0U)
28581 /*! WDMBVT - Write Data Mask BDL VT Compensation
28582  */
28583 #define DDRPHY_DX5GCR3_WDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDMBVT_SHIFT)) & DDRPHY_DX5GCR3_WDMBVT_MASK)
28584 #define DDRPHY_DX5GCR3_RDMBVT_MASK               (0x2U)
28585 #define DDRPHY_DX5GCR3_RDMBVT_SHIFT              (1U)
28586 /*! RDMBVT - Read Data Mask BDL VT Compensation
28587  */
28588 #define DDRPHY_DX5GCR3_RDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RDMBVT_SHIFT)) & DDRPHY_DX5GCR3_RDMBVT_MASK)
28589 #define DDRPHY_DX5GCR3_DSPDRMODE_MASK            (0xCU)
28590 #define DDRPHY_DX5GCR3_DSPDRMODE_SHIFT           (2U)
28591 /*! DSPDRMODE - Enables the PDR mode values for DQS.
28592  */
28593 #define DDRPHY_DX5GCR3_DSPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX5GCR3_DSPDRMODE_MASK)
28594 #define DDRPHY_DX5GCR3_DSTEMODE_MASK             (0x30U)
28595 #define DDRPHY_DX5GCR3_DSTEMODE_SHIFT            (4U)
28596 /*! DSTEMODE - Enables the TE mode values for DQS.
28597  */
28598 #define DDRPHY_DX5GCR3_DSTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSTEMODE_MASK)
28599 #define DDRPHY_DX5GCR3_DSOEMODE_MASK             (0xC0U)
28600 #define DDRPHY_DX5GCR3_DSOEMODE_SHIFT            (6U)
28601 /*! DSOEMODE - Enables the OE mode values for DQS.
28602  */
28603 #define DDRPHY_DX5GCR3_DSOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSOEMODE_MASK)
28604 #define DDRPHY_DX5GCR3_WDSBVT_MASK               (0x100U)
28605 #define DDRPHY_DX5GCR3_WDSBVT_SHIFT              (8U)
28606 /*! WDSBVT - Write Data Strobe BDL VT Compensation
28607  */
28608 #define DDRPHY_DX5GCR3_WDSBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDSBVT_SHIFT)) & DDRPHY_DX5GCR3_WDSBVT_MASK)
28609 #define DDRPHY_DX5GCR3_RESERVED_9_MASK           (0x200U)
28610 #define DDRPHY_DX5GCR3_RESERVED_9_SHIFT          (9U)
28611 /*! RESERVED_9 - Reserved. Returns zeroes on reads.
28612  */
28613 #define DDRPHY_DX5GCR3_RESERVED_9(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX5GCR3_RESERVED_9_MASK)
28614 #define DDRPHY_DX5GCR3_DMPDRMODE_MASK            (0xC00U)
28615 #define DDRPHY_DX5GCR3_DMPDRMODE_SHIFT           (10U)
28616 /*! DMPDRMODE - Enables the PDR mode values for DM.
28617  */
28618 #define DDRPHY_DX5GCR3_DMPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX5GCR3_DMPDRMODE_MASK)
28619 #define DDRPHY_DX5GCR3_DMTEMODE_MASK             (0x3000U)
28620 #define DDRPHY_DX5GCR3_DMTEMODE_SHIFT            (12U)
28621 /*! DMTEMODE - Enables the TE mode values for DM.
28622  */
28623 #define DDRPHY_DX5GCR3_DMTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX5GCR3_DMTEMODE_MASK)
28624 #define DDRPHY_DX5GCR3_DMOEMODE_MASK             (0xC000U)
28625 #define DDRPHY_DX5GCR3_DMOEMODE_SHIFT            (14U)
28626 /*! DMOEMODE - Enables the OE mode values for DM.
28627  */
28628 #define DDRPHY_DX5GCR3_DMOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX5GCR3_DMOEMODE_MASK)
28629 #define DDRPHY_DX5GCR3_DSNPDRMODE_MASK           (0x30000U)
28630 #define DDRPHY_DX5GCR3_DSNPDRMODE_SHIFT          (16U)
28631 /*! DSNPDRMODE - Enables the PDR mode for DQS
28632  */
28633 #define DDRPHY_DX5GCR3_DSNPDRMODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX5GCR3_DSNPDRMODE_MASK)
28634 #define DDRPHY_DX5GCR3_DSNTEMODE_MASK            (0xC0000U)
28635 #define DDRPHY_DX5GCR3_DSNTEMODE_SHIFT           (18U)
28636 /*! DSNTEMODE - Enables the TE mode for DQS
28637  */
28638 #define DDRPHY_DX5GCR3_DSNTEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSNTEMODE_MASK)
28639 #define DDRPHY_DX5GCR3_DSNOEMODE_MASK            (0x300000U)
28640 #define DDRPHY_DX5GCR3_DSNOEMODE_SHIFT           (20U)
28641 /*! DSNOEMODE - Enables the OE mode for DQs
28642  */
28643 #define DDRPHY_DX5GCR3_DSNOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSNOEMODE_MASK)
28644 #define DDRPHY_DX5GCR3_PDRBVT_MASK               (0x400000U)
28645 #define DDRPHY_DX5GCR3_PDRBVT_SHIFT              (22U)
28646 /*! PDRBVT - Power Down Receiver BDL VT Compensation
28647  */
28648 #define DDRPHY_DX5GCR3_PDRBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_PDRBVT_SHIFT)) & DDRPHY_DX5GCR3_PDRBVT_MASK)
28649 #define DDRPHY_DX5GCR3_RGSLVT_MASK               (0x800000U)
28650 #define DDRPHY_DX5GCR3_RGSLVT_SHIFT              (23U)
28651 /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
28652  */
28653 #define DDRPHY_DX5GCR3_RGSLVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RGSLVT_SHIFT)) & DDRPHY_DX5GCR3_RGSLVT_MASK)
28654 #define DDRPHY_DX5GCR3_WLLVT_MASK                (0x1000000U)
28655 #define DDRPHY_DX5GCR3_WLLVT_SHIFT               (24U)
28656 /*! WLLVT - Write Leveling LCDL Delay VT Compensation
28657  */
28658 #define DDRPHY_DX5GCR3_WLLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WLLVT_SHIFT)) & DDRPHY_DX5GCR3_WLLVT_MASK)
28659 #define DDRPHY_DX5GCR3_WDLVT_MASK                (0x2000000U)
28660 #define DDRPHY_DX5GCR3_WDLVT_SHIFT               (25U)
28661 /*! WDLVT - Write DQ LCDL Delay VT Compensation
28662  */
28663 #define DDRPHY_DX5GCR3_WDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDLVT_SHIFT)) & DDRPHY_DX5GCR3_WDLVT_MASK)
28664 #define DDRPHY_DX5GCR3_RDLVT_MASK                (0x4000000U)
28665 #define DDRPHY_DX5GCR3_RDLVT_SHIFT               (26U)
28666 /*! RDLVT - Read DQS LCDL Delay VT Compensation
28667  */
28668 #define DDRPHY_DX5GCR3_RDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RDLVT_SHIFT)) & DDRPHY_DX5GCR3_RDLVT_MASK)
28669 #define DDRPHY_DX5GCR3_RGLVT_MASK                (0x8000000U)
28670 #define DDRPHY_DX5GCR3_RGLVT_SHIFT               (27U)
28671 /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
28672  */
28673 #define DDRPHY_DX5GCR3_RGLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RGLVT_SHIFT)) & DDRPHY_DX5GCR3_RGLVT_MASK)
28674 #define DDRPHY_DX5GCR3_WDBVT_MASK                (0x10000000U)
28675 #define DDRPHY_DX5GCR3_WDBVT_SHIFT               (28U)
28676 /*! WDBVT - Write Data BDL VT Compensation
28677  */
28678 #define DDRPHY_DX5GCR3_WDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDBVT_SHIFT)) & DDRPHY_DX5GCR3_WDBVT_MASK)
28679 #define DDRPHY_DX5GCR3_RDBVT_MASK                (0x20000000U)
28680 #define DDRPHY_DX5GCR3_RDBVT_SHIFT               (29U)
28681 /*! RDBVT - Read Data BDL VT Compensation
28682  */
28683 #define DDRPHY_DX5GCR3_RDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RDBVT_SHIFT)) & DDRPHY_DX5GCR3_RDBVT_MASK)
28684 #define DDRPHY_DX5GCR3_TEBVT_MASK                (0x40000000U)
28685 #define DDRPHY_DX5GCR3_TEBVT_SHIFT               (30U)
28686 /*! TEBVT - Termination Enable BDL VT Compensation
28687  */
28688 #define DDRPHY_DX5GCR3_TEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_TEBVT_SHIFT)) & DDRPHY_DX5GCR3_TEBVT_MASK)
28689 #define DDRPHY_DX5GCR3_OEBVT_MASK                (0x80000000U)
28690 #define DDRPHY_DX5GCR3_OEBVT_SHIFT               (31U)
28691 /*! OEBVT - Output Enable BDL VT Compensation
28692  */
28693 #define DDRPHY_DX5GCR3_OEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_OEBVT_SHIFT)) & DDRPHY_DX5GCR3_OEBVT_MASK)
28694 /*! @} */
28695 
28696 /*! @name DX5GCR4 - DATX8 n General Configuration Register 4 */
28697 /*! @{ */
28698 #define DDRPHY_DX5GCR4_DXREFIMON_MASK            (0x3U)
28699 #define DDRPHY_DX5GCR4_DXREFIMON_SHIFT           (0U)
28700 /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
28701  */
28702 #define DDRPHY_DX5GCR4_DXREFIMON(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX5GCR4_DXREFIMON_MASK)
28703 #define DDRPHY_DX5GCR4_DXREFIEN_MASK             (0x3CU)
28704 #define DDRPHY_DX5GCR4_DXREFIEN_SHIFT            (2U)
28705 /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
28706  */
28707 #define DDRPHY_DX5GCR4_DXREFIEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFIEN_MASK)
28708 #define DDRPHY_DX5GCR4_RESERVED_7_6_MASK         (0xC0U)
28709 #define DDRPHY_DX5GCR4_RESERVED_7_6_SHIFT        (6U)
28710 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
28711  */
28712 #define DDRPHY_DX5GCR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR4_RESERVED_7_6_MASK)
28713 #define DDRPHY_DX5GCR4_DXREFSSEL_MASK            (0x7F00U)
28714 #define DDRPHY_DX5GCR4_DXREFSSEL_SHIFT           (8U)
28715 /*! DXREFSSEL - Byte Lane Single-End VREF Select
28716  */
28717 #define DDRPHY_DX5GCR4_DXREFSSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX5GCR4_DXREFSSEL_MASK)
28718 #define DDRPHY_DX5GCR4_DXREFSSELRANGE_MASK       (0x8000U)
28719 #define DDRPHY_DX5GCR4_DXREFSSELRANGE_SHIFT      (15U)
28720 /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
28721  */
28722 #define DDRPHY_DX5GCR4_DXREFSSELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX5GCR4_DXREFSSELRANGE_MASK)
28723 #define DDRPHY_DX5GCR4_DXREFESEL_MASK            (0x7F0000U)
28724 #define DDRPHY_DX5GCR4_DXREFESEL_SHIFT           (16U)
28725 /*! DXREFESEL - Byte Lane External VREF Select
28726  */
28727 #define DDRPHY_DX5GCR4_DXREFESEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX5GCR4_DXREFESEL_MASK)
28728 #define DDRPHY_DX5GCR4_DXREFESELRANGE_MASK       (0x800000U)
28729 #define DDRPHY_DX5GCR4_DXREFESELRANGE_SHIFT      (23U)
28730 /*! DXREFESELRANGE - External VREF generator REFSEL range select
28731  */
28732 #define DDRPHY_DX5GCR4_DXREFESELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX5GCR4_DXREFESELRANGE_MASK)
28733 #define DDRPHY_DX5GCR4_RESERVED_24_MASK          (0x1000000U)
28734 #define DDRPHY_DX5GCR4_RESERVED_24_SHIFT         (24U)
28735 /*! RESERVED_24 - Reserved. Returns zeros on reads.
28736  */
28737 #define DDRPHY_DX5GCR4_RESERVED_24(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX5GCR4_RESERVED_24_MASK)
28738 #define DDRPHY_DX5GCR4_DXREFSEN_MASK             (0x2000000U)
28739 #define DDRPHY_DX5GCR4_DXREFSEN_SHIFT            (25U)
28740 /*! DXREFSEN - Byte Lane Single-End VREF Enable
28741  */
28742 #define DDRPHY_DX5GCR4_DXREFSEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFSEN_MASK)
28743 #define DDRPHY_DX5GCR4_DXREFEEN_MASK             (0xC000000U)
28744 #define DDRPHY_DX5GCR4_DXREFEEN_SHIFT            (26U)
28745 /*! DXREFEEN - Byte Lane Internal VREF Enable
28746  */
28747 #define DDRPHY_DX5GCR4_DXREFEEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFEEN_MASK)
28748 #define DDRPHY_DX5GCR4_DXREFPEN_MASK             (0x10000000U)
28749 #define DDRPHY_DX5GCR4_DXREFPEN_SHIFT            (28U)
28750 /*! DXREFPEN - Byte Lane VREF Pad Enable
28751  */
28752 #define DDRPHY_DX5GCR4_DXREFPEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFPEN_MASK)
28753 #define DDRPHY_DX5GCR4_RESERVED_31_29_MASK       (0xE0000000U)
28754 #define DDRPHY_DX5GCR4_RESERVED_31_29_SHIFT      (29U)
28755 /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
28756  */
28757 #define DDRPHY_DX5GCR4_RESERVED_31_29(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX5GCR4_RESERVED_31_29_MASK)
28758 /*! @} */
28759 
28760 /*! @name DX5GCR5 - DATX8 n General Configuration Register 5 */
28761 /*! @{ */
28762 #define DDRPHY_DX5GCR5_DXREFISELR0_MASK          (0x7FU)
28763 #define DDRPHY_DX5GCR5_DXREFISELR0_SHIFT         (0U)
28764 /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
28765  */
28766 #define DDRPHY_DX5GCR5_DXREFISELR0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR0_MASK)
28767 #define DDRPHY_DX5GCR5_RESERVED_7_MASK           (0x80U)
28768 #define DDRPHY_DX5GCR5_RESERVED_7_SHIFT          (7U)
28769 /*! RESERVED_7 - Reserved. Returns zeros on reads.
28770  */
28771 #define DDRPHY_DX5GCR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_7_MASK)
28772 #define DDRPHY_DX5GCR5_DXREFISELR1_MASK          (0x7F00U)
28773 #define DDRPHY_DX5GCR5_DXREFISELR1_SHIFT         (8U)
28774 /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
28775  */
28776 #define DDRPHY_DX5GCR5_DXREFISELR1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR1_MASK)
28777 #define DDRPHY_DX5GCR5_RESERVED_15_MASK          (0x8000U)
28778 #define DDRPHY_DX5GCR5_RESERVED_15_SHIFT         (15U)
28779 /*! RESERVED_15 - Reserved. Returns zeros on reads.
28780  */
28781 #define DDRPHY_DX5GCR5_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_15_MASK)
28782 #define DDRPHY_DX5GCR5_DXREFISELR2_MASK          (0x7F0000U)
28783 #define DDRPHY_DX5GCR5_DXREFISELR2_SHIFT         (16U)
28784 /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
28785  */
28786 #define DDRPHY_DX5GCR5_DXREFISELR2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR2_MASK)
28787 #define DDRPHY_DX5GCR5_RESERVED_23_MASK          (0x800000U)
28788 #define DDRPHY_DX5GCR5_RESERVED_23_SHIFT         (23U)
28789 /*! RESERVED_23 - Reserved. Returns zeros on reads.
28790  */
28791 #define DDRPHY_DX5GCR5_RESERVED_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_23_MASK)
28792 #define DDRPHY_DX5GCR5_DXREFISELR3_MASK          (0x7F000000U)
28793 #define DDRPHY_DX5GCR5_DXREFISELR3_SHIFT         (24U)
28794 /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
28795  */
28796 #define DDRPHY_DX5GCR5_DXREFISELR3(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR3_MASK)
28797 #define DDRPHY_DX5GCR5_RESERVED_31_MASK          (0x80000000U)
28798 #define DDRPHY_DX5GCR5_RESERVED_31_SHIFT         (31U)
28799 /*! RESERVED_31 - Reserved. Returns zeros on reads.
28800  */
28801 #define DDRPHY_DX5GCR5_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_31_MASK)
28802 /*! @} */
28803 
28804 /*! @name DX5GCR6 - DATX8 n General Configuration Register 6 */
28805 /*! @{ */
28806 #define DDRPHY_DX5GCR6_DXDQVREFR0_MASK           (0x3FU)
28807 #define DDRPHY_DX5GCR6_DXDQVREFR0_SHIFT          (0U)
28808 /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
28809  */
28810 #define DDRPHY_DX5GCR6_DXDQVREFR0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR0_MASK)
28811 #define DDRPHY_DX5GCR6_RESERVED_7_6_MASK         (0xC0U)
28812 #define DDRPHY_DX5GCR6_RESERVED_7_6_SHIFT        (6U)
28813 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
28814  */
28815 #define DDRPHY_DX5GCR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_7_6_MASK)
28816 #define DDRPHY_DX5GCR6_DXDQVREFR1_MASK           (0x3F00U)
28817 #define DDRPHY_DX5GCR6_DXDQVREFR1_SHIFT          (8U)
28818 /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
28819  */
28820 #define DDRPHY_DX5GCR6_DXDQVREFR1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR1_MASK)
28821 #define DDRPHY_DX5GCR6_RESERVED_15_14_MASK       (0xC000U)
28822 #define DDRPHY_DX5GCR6_RESERVED_15_14_SHIFT      (14U)
28823 /*! RESERVED_15_14 - Reserved. Returns zeros on reads.
28824  */
28825 #define DDRPHY_DX5GCR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_15_14_MASK)
28826 #define DDRPHY_DX5GCR6_DXDQVREFR2_MASK           (0x3F0000U)
28827 #define DDRPHY_DX5GCR6_DXDQVREFR2_SHIFT          (16U)
28828 /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
28829  */
28830 #define DDRPHY_DX5GCR6_DXDQVREFR2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR2_MASK)
28831 #define DDRPHY_DX5GCR6_RESERVED_23_22_MASK       (0xC00000U)
28832 #define DDRPHY_DX5GCR6_RESERVED_23_22_SHIFT      (22U)
28833 /*! RESERVED_23_22 - Reserved. Returns zeros on reads.
28834  */
28835 #define DDRPHY_DX5GCR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_23_22_MASK)
28836 #define DDRPHY_DX5GCR6_DXDQVREFR3_MASK           (0x3F000000U)
28837 #define DDRPHY_DX5GCR6_DXDQVREFR3_SHIFT          (24U)
28838 /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
28839  */
28840 #define DDRPHY_DX5GCR6_DXDQVREFR3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR3_MASK)
28841 #define DDRPHY_DX5GCR6_RESERVED_31_30_MASK       (0xC0000000U)
28842 #define DDRPHY_DX5GCR6_RESERVED_31_30_SHIFT      (30U)
28843 /*! RESERVED_31_30 - Reserved. Returns zeros on reads.
28844  */
28845 #define DDRPHY_DX5GCR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_31_30_MASK)
28846 /*! @} */
28847 
28848 /*! @name DX5GCR7 - DATX8 n General Configuration Register 7 */
28849 /*! @{ */
28850 #define DDRPHY_DX5GCR7_DCALSVAL_MASK             (0x1FFU)
28851 #define DDRPHY_DX5GCR7_DCALSVAL_SHIFT            (0U)
28852 /*! DCALSVAL - DDL Calibration Starting Value
28853  */
28854 #define DDRPHY_DX5GCR7_DCALSVAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX5GCR7_DCALSVAL_MASK)
28855 #define DDRPHY_DX5GCR7_DCALTYPE_MASK             (0x200U)
28856 #define DDRPHY_DX5GCR7_DCALTYPE_SHIFT            (9U)
28857 /*! DCALTYPE - DDL Calibration Type
28858  */
28859 #define DDRPHY_DX5GCR7_DCALTYPE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX5GCR7_DCALTYPE_MASK)
28860 #define DDRPHY_DX5GCR7_RESERVED_17_10_MASK       (0x3FC00U)
28861 #define DDRPHY_DX5GCR7_RESERVED_17_10_SHIFT      (10U)
28862 /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
28863  */
28864 #define DDRPHY_DX5GCR7_RESERVED_17_10(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX5GCR7_RESERVED_17_10_MASK)
28865 #define DDRPHY_DX5GCR7_RESERVED_18_MASK          (0x40000U)
28866 #define DDRPHY_DX5GCR7_RESERVED_18_SHIFT         (18U)
28867 /*! RESERVED_18 - Reserved. Caution, do not write to this register field.
28868  */
28869 #define DDRPHY_DX5GCR7_RESERVED_18(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX5GCR7_RESERVED_18_MASK)
28870 #define DDRPHY_DX5GCR7_RESERVED_31_19_MASK       (0xFFF80000U)
28871 #define DDRPHY_DX5GCR7_RESERVED_31_19_SHIFT      (19U)
28872 /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
28873  */
28874 #define DDRPHY_DX5GCR7_RESERVED_31_19(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX5GCR7_RESERVED_31_19_MASK)
28875 /*! @} */
28876 
28877 /*! @name DX5GCR8 - DATX8 n General Configuration Register 8 */
28878 /*! @{ */
28879 #define DDRPHY_DX5GCR8_RESERVED_5_0_MASK         (0x3FU)
28880 #define DDRPHY_DX5GCR8_RESERVED_5_0_SHIFT        (0U)
28881 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
28882  */
28883 #define DDRPHY_DX5GCR8_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_5_0_MASK)
28884 #define DDRPHY_DX5GCR8_RESERVED_7_6_MASK         (0xC0U)
28885 #define DDRPHY_DX5GCR8_RESERVED_7_6_SHIFT        (6U)
28886 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
28887  */
28888 #define DDRPHY_DX5GCR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_7_6_MASK)
28889 #define DDRPHY_DX5GCR8_RESERVED_13_8_MASK        (0x3F00U)
28890 #define DDRPHY_DX5GCR8_RESERVED_13_8_SHIFT       (8U)
28891 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
28892  */
28893 #define DDRPHY_DX5GCR8_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_13_8_MASK)
28894 #define DDRPHY_DX5GCR8_RESERVED_15_14_MASK       (0xC000U)
28895 #define DDRPHY_DX5GCR8_RESERVED_15_14_SHIFT      (14U)
28896 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
28897  */
28898 #define DDRPHY_DX5GCR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_15_14_MASK)
28899 #define DDRPHY_DX5GCR8_RESERVED_21_16_MASK       (0x3F0000U)
28900 #define DDRPHY_DX5GCR8_RESERVED_21_16_SHIFT      (16U)
28901 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
28902  */
28903 #define DDRPHY_DX5GCR8_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_21_16_MASK)
28904 #define DDRPHY_DX5GCR8_RESERVED_23_22_MASK       (0xC00000U)
28905 #define DDRPHY_DX5GCR8_RESERVED_23_22_SHIFT      (22U)
28906 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
28907  */
28908 #define DDRPHY_DX5GCR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_23_22_MASK)
28909 #define DDRPHY_DX5GCR8_RESERVED_29_24_MASK       (0x3F000000U)
28910 #define DDRPHY_DX5GCR8_RESERVED_29_24_SHIFT      (24U)
28911 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
28912  */
28913 #define DDRPHY_DX5GCR8_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_29_24_MASK)
28914 #define DDRPHY_DX5GCR8_RESERVED_31_30_MASK       (0xC0000000U)
28915 #define DDRPHY_DX5GCR8_RESERVED_31_30_SHIFT      (30U)
28916 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
28917  */
28918 #define DDRPHY_DX5GCR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_31_30_MASK)
28919 /*! @} */
28920 
28921 /*! @name DX5GCR9 - DATX8 n General Configuration Register 9 */
28922 /*! @{ */
28923 #define DDRPHY_DX5GCR9_RESERVED_5_0_MASK         (0x3FU)
28924 #define DDRPHY_DX5GCR9_RESERVED_5_0_SHIFT        (0U)
28925 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
28926  */
28927 #define DDRPHY_DX5GCR9_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_5_0_MASK)
28928 #define DDRPHY_DX5GCR9_RESERVED_7_6_MASK         (0xC0U)
28929 #define DDRPHY_DX5GCR9_RESERVED_7_6_SHIFT        (6U)
28930 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
28931  */
28932 #define DDRPHY_DX5GCR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_7_6_MASK)
28933 #define DDRPHY_DX5GCR9_RESERVED_13_8_MASK        (0x3F00U)
28934 #define DDRPHY_DX5GCR9_RESERVED_13_8_SHIFT       (8U)
28935 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
28936  */
28937 #define DDRPHY_DX5GCR9_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_13_8_MASK)
28938 #define DDRPHY_DX5GCR9_RESERVED_15_14_MASK       (0xC000U)
28939 #define DDRPHY_DX5GCR9_RESERVED_15_14_SHIFT      (14U)
28940 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
28941  */
28942 #define DDRPHY_DX5GCR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_15_14_MASK)
28943 #define DDRPHY_DX5GCR9_RESERVED_21_16_MASK       (0x3F0000U)
28944 #define DDRPHY_DX5GCR9_RESERVED_21_16_SHIFT      (16U)
28945 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
28946  */
28947 #define DDRPHY_DX5GCR9_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_21_16_MASK)
28948 #define DDRPHY_DX5GCR9_RESERVED_23_22_MASK       (0xC00000U)
28949 #define DDRPHY_DX5GCR9_RESERVED_23_22_SHIFT      (22U)
28950 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
28951  */
28952 #define DDRPHY_DX5GCR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_23_22_MASK)
28953 #define DDRPHY_DX5GCR9_RESERVED_29_24_MASK       (0x3F000000U)
28954 #define DDRPHY_DX5GCR9_RESERVED_29_24_SHIFT      (24U)
28955 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
28956  */
28957 #define DDRPHY_DX5GCR9_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_29_24_MASK)
28958 #define DDRPHY_DX5GCR9_RESERVED_31_30_MASK       (0xC0000000U)
28959 #define DDRPHY_DX5GCR9_RESERVED_31_30_SHIFT      (30U)
28960 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
28961  */
28962 #define DDRPHY_DX5GCR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_31_30_MASK)
28963 /*! @} */
28964 
28965 /*! @name DX5DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
28966 /*! @{ */
28967 #define DDRPHY_DX5DQMAP0_DQ0MAP_MASK             (0xFU)
28968 #define DDRPHY_DX5DQMAP0_DQ0MAP_SHIFT            (0U)
28969 /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
28970  */
28971 #define DDRPHY_DX5DQMAP0_DQ0MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ0MAP_MASK)
28972 #define DDRPHY_DX5DQMAP0_DQ1MAP_MASK             (0xF0U)
28973 #define DDRPHY_DX5DQMAP0_DQ1MAP_SHIFT            (4U)
28974 /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
28975  */
28976 #define DDRPHY_DX5DQMAP0_DQ1MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ1MAP_MASK)
28977 #define DDRPHY_DX5DQMAP0_DQ2MAP_MASK             (0xF00U)
28978 #define DDRPHY_DX5DQMAP0_DQ2MAP_SHIFT            (8U)
28979 /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
28980  */
28981 #define DDRPHY_DX5DQMAP0_DQ2MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ2MAP_MASK)
28982 #define DDRPHY_DX5DQMAP0_DQ3MAP_MASK             (0xF000U)
28983 #define DDRPHY_DX5DQMAP0_DQ3MAP_SHIFT            (12U)
28984 /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
28985  */
28986 #define DDRPHY_DX5DQMAP0_DQ3MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ3MAP_MASK)
28987 #define DDRPHY_DX5DQMAP0_DQ4MAP_MASK             (0xF0000U)
28988 #define DDRPHY_DX5DQMAP0_DQ4MAP_SHIFT            (16U)
28989 /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
28990  */
28991 #define DDRPHY_DX5DQMAP0_DQ4MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ4MAP_MASK)
28992 #define DDRPHY_DX5DQMAP0_RESERVED_30_20_MASK     (0x7FF00000U)
28993 #define DDRPHY_DX5DQMAP0_RESERVED_30_20_SHIFT    (20U)
28994 /*! RESERVED_30_20 - Reserved. Return zeroes on reads.
28995  */
28996 #define DDRPHY_DX5DQMAP0_RESERVED_30_20(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX5DQMAP0_RESERVED_30_20_MASK)
28997 #define DDRPHY_DX5DQMAP0_MAPOK_MASK              (0x80000000U)
28998 #define DDRPHY_DX5DQMAP0_MAPOK_SHIFT             (31U)
28999 /*! MAPOK - Checksum bit
29000  */
29001 #define DDRPHY_DX5DQMAP0_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX5DQMAP0_MAPOK_MASK)
29002 /*! @} */
29003 
29004 /*! @name DX5DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
29005 /*! @{ */
29006 #define DDRPHY_DX5DQMAP1_DQ5MAP_MASK             (0xFU)
29007 #define DDRPHY_DX5DQMAP1_DQ5MAP_SHIFT            (0U)
29008 /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
29009  */
29010 #define DDRPHY_DX5DQMAP1_DQ5MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX5DQMAP1_DQ5MAP_MASK)
29011 #define DDRPHY_DX5DQMAP1_DQ6MAP_MASK             (0xF0U)
29012 #define DDRPHY_DX5DQMAP1_DQ6MAP_SHIFT            (4U)
29013 /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
29014  */
29015 #define DDRPHY_DX5DQMAP1_DQ6MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX5DQMAP1_DQ6MAP_MASK)
29016 #define DDRPHY_DX5DQMAP1_DQ7MAP_MASK             (0xF00U)
29017 #define DDRPHY_DX5DQMAP1_DQ7MAP_SHIFT            (8U)
29018 /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
29019  */
29020 #define DDRPHY_DX5DQMAP1_DQ7MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX5DQMAP1_DQ7MAP_MASK)
29021 #define DDRPHY_DX5DQMAP1_DMMAP_MASK              (0xF000U)
29022 #define DDRPHY_DX5DQMAP1_DMMAP_SHIFT             (12U)
29023 /*! DMMAP - DM bit DATX8 slice mapping index
29024  */
29025 #define DDRPHY_DX5DQMAP1_DMMAP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX5DQMAP1_DMMAP_MASK)
29026 #define DDRPHY_DX5DQMAP1_RESERVED_30_16_MASK     (0x7FFF0000U)
29027 #define DDRPHY_DX5DQMAP1_RESERVED_30_16_SHIFT    (16U)
29028 /*! RESERVED_30_16 - Reserved. Return zeroes on reads.
29029  */
29030 #define DDRPHY_DX5DQMAP1_RESERVED_30_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX5DQMAP1_RESERVED_30_16_MASK)
29031 #define DDRPHY_DX5DQMAP1_MAPOK_MASK              (0x80000000U)
29032 #define DDRPHY_DX5DQMAP1_MAPOK_SHIFT             (31U)
29033 /*! MAPOK - Checksum bit
29034  */
29035 #define DDRPHY_DX5DQMAP1_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX5DQMAP1_MAPOK_MASK)
29036 /*! @} */
29037 
29038 /*! @name DX5BDLR0 - DATX8 n Bit Delay Line Register 0 */
29039 /*! @{ */
29040 #define DDRPHY_DX5BDLR0_DQ0WBD_MASK              (0x3FU)
29041 #define DDRPHY_DX5BDLR0_DQ0WBD_SHIFT             (0U)
29042 /*! DQ0WBD - DQ0 Write Bit Delay
29043  */
29044 #define DDRPHY_DX5BDLR0_DQ0WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ0WBD_MASK)
29045 #define DDRPHY_DX5BDLR0_RESERVED_7_6_MASK        (0xC0U)
29046 #define DDRPHY_DX5BDLR0_RESERVED_7_6_SHIFT       (6U)
29047 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29048  */
29049 #define DDRPHY_DX5BDLR0_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_7_6_MASK)
29050 #define DDRPHY_DX5BDLR0_DQ1WBD_MASK              (0x3F00U)
29051 #define DDRPHY_DX5BDLR0_DQ1WBD_SHIFT             (8U)
29052 /*! DQ1WBD - DQ1 Write Bit Delay
29053  */
29054 #define DDRPHY_DX5BDLR0_DQ1WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ1WBD_MASK)
29055 #define DDRPHY_DX5BDLR0_RESERVED_15_14_MASK      (0xC000U)
29056 #define DDRPHY_DX5BDLR0_RESERVED_15_14_SHIFT     (14U)
29057 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29058  */
29059 #define DDRPHY_DX5BDLR0_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_15_14_MASK)
29060 #define DDRPHY_DX5BDLR0_DQ2WBD_MASK              (0x3F0000U)
29061 #define DDRPHY_DX5BDLR0_DQ2WBD_SHIFT             (16U)
29062 /*! DQ2WBD - DQ2 Write Bit Delay
29063  */
29064 #define DDRPHY_DX5BDLR0_DQ2WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ2WBD_MASK)
29065 #define DDRPHY_DX5BDLR0_RESERVED_23_22_MASK      (0xC00000U)
29066 #define DDRPHY_DX5BDLR0_RESERVED_23_22_SHIFT     (22U)
29067 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29068  */
29069 #define DDRPHY_DX5BDLR0_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_23_22_MASK)
29070 #define DDRPHY_DX5BDLR0_DQ3WBD_MASK              (0x3F000000U)
29071 #define DDRPHY_DX5BDLR0_DQ3WBD_SHIFT             (24U)
29072 /*! DQ3WBD - DQ3 Write Bit Delay
29073  */
29074 #define DDRPHY_DX5BDLR0_DQ3WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ3WBD_MASK)
29075 #define DDRPHY_DX5BDLR0_RESERVED_31_30_MASK      (0xC0000000U)
29076 #define DDRPHY_DX5BDLR0_RESERVED_31_30_SHIFT     (30U)
29077 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29078  */
29079 #define DDRPHY_DX5BDLR0_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_31_30_MASK)
29080 /*! @} */
29081 
29082 /*! @name DX5BDLR1 - DATX8 n Bit Delay Line Register 1 */
29083 /*! @{ */
29084 #define DDRPHY_DX5BDLR1_DQ4WBD_MASK              (0x3FU)
29085 #define DDRPHY_DX5BDLR1_DQ4WBD_SHIFT             (0U)
29086 /*! DQ4WBD - DQ4 Write Bit Delay
29087  */
29088 #define DDRPHY_DX5BDLR1_DQ4WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ4WBD_MASK)
29089 #define DDRPHY_DX5BDLR1_RESERVED_7_6_MASK        (0xC0U)
29090 #define DDRPHY_DX5BDLR1_RESERVED_7_6_SHIFT       (6U)
29091 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29092  */
29093 #define DDRPHY_DX5BDLR1_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_7_6_MASK)
29094 #define DDRPHY_DX5BDLR1_DQ5WBD_MASK              (0x3F00U)
29095 #define DDRPHY_DX5BDLR1_DQ5WBD_SHIFT             (8U)
29096 /*! DQ5WBD - DQ5 Write Bit Delay
29097  */
29098 #define DDRPHY_DX5BDLR1_DQ5WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ5WBD_MASK)
29099 #define DDRPHY_DX5BDLR1_RESERVED_15_14_MASK      (0xC000U)
29100 #define DDRPHY_DX5BDLR1_RESERVED_15_14_SHIFT     (14U)
29101 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29102  */
29103 #define DDRPHY_DX5BDLR1_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_15_14_MASK)
29104 #define DDRPHY_DX5BDLR1_DQ6WBD_MASK              (0x3F0000U)
29105 #define DDRPHY_DX5BDLR1_DQ6WBD_SHIFT             (16U)
29106 /*! DQ6WBD - DQ6 Write Bit Delay
29107  */
29108 #define DDRPHY_DX5BDLR1_DQ6WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ6WBD_MASK)
29109 #define DDRPHY_DX5BDLR1_RESERVED_23_22_MASK      (0xC00000U)
29110 #define DDRPHY_DX5BDLR1_RESERVED_23_22_SHIFT     (22U)
29111 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29112  */
29113 #define DDRPHY_DX5BDLR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_23_22_MASK)
29114 #define DDRPHY_DX5BDLR1_DQ7WBD_MASK              (0x3F000000U)
29115 #define DDRPHY_DX5BDLR1_DQ7WBD_SHIFT             (24U)
29116 /*! DQ7WBD - DQ7 Write Bit Delay
29117  */
29118 #define DDRPHY_DX5BDLR1_DQ7WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ7WBD_MASK)
29119 #define DDRPHY_DX5BDLR1_RESERVED_31_30_MASK      (0xC0000000U)
29120 #define DDRPHY_DX5BDLR1_RESERVED_31_30_SHIFT     (30U)
29121 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29122  */
29123 #define DDRPHY_DX5BDLR1_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_31_30_MASK)
29124 /*! @} */
29125 
29126 /*! @name DX5BDLR2 - DATX8 n Bit Delay Line Register 2 */
29127 /*! @{ */
29128 #define DDRPHY_DX5BDLR2_DMWBD_MASK               (0x3FU)
29129 #define DDRPHY_DX5BDLR2_DMWBD_SHIFT              (0U)
29130 /*! DMWBD - DM Write Bit Delay
29131  */
29132 #define DDRPHY_DX5BDLR2_DMWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DMWBD_SHIFT)) & DDRPHY_DX5BDLR2_DMWBD_MASK)
29133 #define DDRPHY_DX5BDLR2_RESERVED_7_6_MASK        (0xC0U)
29134 #define DDRPHY_DX5BDLR2_RESERVED_7_6_SHIFT       (6U)
29135 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29136  */
29137 #define DDRPHY_DX5BDLR2_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_7_6_MASK)
29138 #define DDRPHY_DX5BDLR2_DSWBD_MASK               (0x3F00U)
29139 #define DDRPHY_DX5BDLR2_DSWBD_SHIFT              (8U)
29140 /*! DSWBD - DQS Write Bit Delay
29141  */
29142 #define DDRPHY_DX5BDLR2_DSWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DSWBD_SHIFT)) & DDRPHY_DX5BDLR2_DSWBD_MASK)
29143 #define DDRPHY_DX5BDLR2_RESERVED_15_14_MASK      (0xC000U)
29144 #define DDRPHY_DX5BDLR2_RESERVED_15_14_SHIFT     (14U)
29145 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29146  */
29147 #define DDRPHY_DX5BDLR2_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_15_14_MASK)
29148 #define DDRPHY_DX5BDLR2_DSOEBD_MASK              (0x3F0000U)
29149 #define DDRPHY_DX5BDLR2_DSOEBD_SHIFT             (16U)
29150 /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
29151  */
29152 #define DDRPHY_DX5BDLR2_DSOEBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX5BDLR2_DSOEBD_MASK)
29153 #define DDRPHY_DX5BDLR2_RESERVED_23_22_MASK      (0xC00000U)
29154 #define DDRPHY_DX5BDLR2_RESERVED_23_22_SHIFT     (22U)
29155 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29156  */
29157 #define DDRPHY_DX5BDLR2_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_23_22_MASK)
29158 #define DDRPHY_DX5BDLR2_DSNWBD_MASK              (0x3F000000U)
29159 #define DDRPHY_DX5BDLR2_DSNWBD_SHIFT             (24U)
29160 /*! DSNWBD - DQSN Write Bit Delay
29161  */
29162 #define DDRPHY_DX5BDLR2_DSNWBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX5BDLR2_DSNWBD_MASK)
29163 #define DDRPHY_DX5BDLR2_RESERVED_31_30_MASK      (0xC0000000U)
29164 #define DDRPHY_DX5BDLR2_RESERVED_31_30_SHIFT     (30U)
29165 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29166  */
29167 #define DDRPHY_DX5BDLR2_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_31_30_MASK)
29168 /*! @} */
29169 
29170 /*! @name DX5BDLR3 - DATX8 n Bit Delay Line Register 3 */
29171 /*! @{ */
29172 #define DDRPHY_DX5BDLR3_DQ0RBD_MASK              (0x3FU)
29173 #define DDRPHY_DX5BDLR3_DQ0RBD_SHIFT             (0U)
29174 /*! DQ0RBD - DQ0 Read Bit Delay
29175  */
29176 #define DDRPHY_DX5BDLR3_DQ0RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ0RBD_MASK)
29177 #define DDRPHY_DX5BDLR3_RESERVED_7_6_MASK        (0xC0U)
29178 #define DDRPHY_DX5BDLR3_RESERVED_7_6_SHIFT       (6U)
29179 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29180  */
29181 #define DDRPHY_DX5BDLR3_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_7_6_MASK)
29182 #define DDRPHY_DX5BDLR3_DQ1RBD_MASK              (0x3F00U)
29183 #define DDRPHY_DX5BDLR3_DQ1RBD_SHIFT             (8U)
29184 /*! DQ1RBD - DQ1 Read Bit Delay
29185  */
29186 #define DDRPHY_DX5BDLR3_DQ1RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ1RBD_MASK)
29187 #define DDRPHY_DX5BDLR3_RESERVED_15_14_MASK      (0xC000U)
29188 #define DDRPHY_DX5BDLR3_RESERVED_15_14_SHIFT     (14U)
29189 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29190  */
29191 #define DDRPHY_DX5BDLR3_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_15_14_MASK)
29192 #define DDRPHY_DX5BDLR3_DQ2RBD_MASK              (0x3F0000U)
29193 #define DDRPHY_DX5BDLR3_DQ2RBD_SHIFT             (16U)
29194 /*! DQ2RBD - DQ2 Read Bit Delay
29195  */
29196 #define DDRPHY_DX5BDLR3_DQ2RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ2RBD_MASK)
29197 #define DDRPHY_DX5BDLR3_RESERVED_23_22_MASK      (0xC00000U)
29198 #define DDRPHY_DX5BDLR3_RESERVED_23_22_SHIFT     (22U)
29199 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29200  */
29201 #define DDRPHY_DX5BDLR3_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_23_22_MASK)
29202 #define DDRPHY_DX5BDLR3_DQ3RBD_MASK              (0x3F000000U)
29203 #define DDRPHY_DX5BDLR3_DQ3RBD_SHIFT             (24U)
29204 /*! DQ3RBD - DQ3 Read Bit Delay
29205  */
29206 #define DDRPHY_DX5BDLR3_DQ3RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ3RBD_MASK)
29207 #define DDRPHY_DX5BDLR3_RESERVED_31_30_MASK      (0xC0000000U)
29208 #define DDRPHY_DX5BDLR3_RESERVED_31_30_SHIFT     (30U)
29209 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29210  */
29211 #define DDRPHY_DX5BDLR3_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_31_30_MASK)
29212 /*! @} */
29213 
29214 /*! @name DX5BDLR4 - DATX8 n Bit Delay Line Register 4 */
29215 /*! @{ */
29216 #define DDRPHY_DX5BDLR4_DQ4RBD_MASK              (0x3FU)
29217 #define DDRPHY_DX5BDLR4_DQ4RBD_SHIFT             (0U)
29218 /*! DQ4RBD - DQ4 Read Bit Delay
29219  */
29220 #define DDRPHY_DX5BDLR4_DQ4RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ4RBD_MASK)
29221 #define DDRPHY_DX5BDLR4_RESERVED_7_6_MASK        (0xC0U)
29222 #define DDRPHY_DX5BDLR4_RESERVED_7_6_SHIFT       (6U)
29223 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29224  */
29225 #define DDRPHY_DX5BDLR4_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_7_6_MASK)
29226 #define DDRPHY_DX5BDLR4_DQ5RBD_MASK              (0x3F00U)
29227 #define DDRPHY_DX5BDLR4_DQ5RBD_SHIFT             (8U)
29228 /*! DQ5RBD - DQ5 Read Bit Delay
29229  */
29230 #define DDRPHY_DX5BDLR4_DQ5RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ5RBD_MASK)
29231 #define DDRPHY_DX5BDLR4_RESERVED_15_14_MASK      (0xC000U)
29232 #define DDRPHY_DX5BDLR4_RESERVED_15_14_SHIFT     (14U)
29233 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29234  */
29235 #define DDRPHY_DX5BDLR4_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_15_14_MASK)
29236 #define DDRPHY_DX5BDLR4_DQ6RBD_MASK              (0x3F0000U)
29237 #define DDRPHY_DX5BDLR4_DQ6RBD_SHIFT             (16U)
29238 /*! DQ6RBD - DQ6 Read Bit Delay
29239  */
29240 #define DDRPHY_DX5BDLR4_DQ6RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ6RBD_MASK)
29241 #define DDRPHY_DX5BDLR4_RESERVED_23_22_MASK      (0xC00000U)
29242 #define DDRPHY_DX5BDLR4_RESERVED_23_22_SHIFT     (22U)
29243 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29244  */
29245 #define DDRPHY_DX5BDLR4_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_23_22_MASK)
29246 #define DDRPHY_DX5BDLR4_DQ7RBD_MASK              (0x3F000000U)
29247 #define DDRPHY_DX5BDLR4_DQ7RBD_SHIFT             (24U)
29248 /*! DQ7RBD - DQ7 Read Bit Delay
29249  */
29250 #define DDRPHY_DX5BDLR4_DQ7RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ7RBD_MASK)
29251 #define DDRPHY_DX5BDLR4_RESERVED_31_30_MASK      (0xC0000000U)
29252 #define DDRPHY_DX5BDLR4_RESERVED_31_30_SHIFT     (30U)
29253 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29254  */
29255 #define DDRPHY_DX5BDLR4_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_31_30_MASK)
29256 /*! @} */
29257 
29258 /*! @name DX5BDLR5 - DATX8 n Bit Delay Line Register 5 */
29259 /*! @{ */
29260 #define DDRPHY_DX5BDLR5_DMRBD_MASK               (0x3FU)
29261 #define DDRPHY_DX5BDLR5_DMRBD_SHIFT              (0U)
29262 /*! DMRBD - DM Read Bit Delay
29263  */
29264 #define DDRPHY_DX5BDLR5_DMRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR5_DMRBD_SHIFT)) & DDRPHY_DX5BDLR5_DMRBD_MASK)
29265 #define DDRPHY_DX5BDLR5_RESERVED_31_6_MASK       (0xFFFFFFC0U)
29266 #define DDRPHY_DX5BDLR5_RESERVED_31_6_SHIFT      (6U)
29267 /*! RESERVED_31_6 - Reserved. Return zeroes on reads.
29268  */
29269 #define DDRPHY_DX5BDLR5_RESERVED_31_6(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX5BDLR5_RESERVED_31_6_MASK)
29270 /*! @} */
29271 
29272 /*! @name DX5BDLR6 - DATX8 n Bit Delay Line Register 6 */
29273 /*! @{ */
29274 #define DDRPHY_DX5BDLR6_RESERVED_7_0_MASK        (0xFFU)
29275 #define DDRPHY_DX5BDLR6_RESERVED_7_0_SHIFT       (0U)
29276 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
29277  */
29278 #define DDRPHY_DX5BDLR6_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX5BDLR6_RESERVED_7_0_MASK)
29279 #define DDRPHY_DX5BDLR6_PDRBD_MASK               (0x3F00U)
29280 #define DDRPHY_DX5BDLR6_PDRBD_SHIFT              (8U)
29281 /*! PDRBD - Power down receiver Bit Delay
29282  */
29283 #define DDRPHY_DX5BDLR6_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_PDRBD_SHIFT)) & DDRPHY_DX5BDLR6_PDRBD_MASK)
29284 #define DDRPHY_DX5BDLR6_RESERVED_15_14_MASK      (0xC000U)
29285 #define DDRPHY_DX5BDLR6_RESERVED_15_14_SHIFT     (14U)
29286 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29287  */
29288 #define DDRPHY_DX5BDLR6_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR6_RESERVED_15_14_MASK)
29289 #define DDRPHY_DX5BDLR6_TERBD_MASK               (0x3F0000U)
29290 #define DDRPHY_DX5BDLR6_TERBD_SHIFT              (16U)
29291 /*! TERBD - Termination Enable Bit Delay
29292  */
29293 #define DDRPHY_DX5BDLR6_TERBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_TERBD_SHIFT)) & DDRPHY_DX5BDLR6_TERBD_MASK)
29294 #define DDRPHY_DX5BDLR6_RESERVED_31_22_MASK      (0xFFC00000U)
29295 #define DDRPHY_DX5BDLR6_RESERVED_31_22_SHIFT     (22U)
29296 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
29297  */
29298 #define DDRPHY_DX5BDLR6_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR6_RESERVED_31_22_MASK)
29299 /*! @} */
29300 
29301 /*! @name DX5BDLR7 - DATX8 n Bit Delay Line Register 7 */
29302 /*! @{ */
29303 #define DDRPHY_DX5BDLR7_RESERVED_5_0_MASK        (0x3FU)
29304 #define DDRPHY_DX5BDLR7_RESERVED_5_0_SHIFT       (0U)
29305 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
29306  */
29307 #define DDRPHY_DX5BDLR7_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_5_0_MASK)
29308 #define DDRPHY_DX5BDLR7_RESERVED_7_6_MASK        (0xC0U)
29309 #define DDRPHY_DX5BDLR7_RESERVED_7_6_SHIFT       (6U)
29310 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29311  */
29312 #define DDRPHY_DX5BDLR7_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_7_6_MASK)
29313 #define DDRPHY_DX5BDLR7_RESERVED_13_8_MASK       (0x3F00U)
29314 #define DDRPHY_DX5BDLR7_RESERVED_13_8_SHIFT      (8U)
29315 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
29316  */
29317 #define DDRPHY_DX5BDLR7_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_13_8_MASK)
29318 #define DDRPHY_DX5BDLR7_RESERVED_15_14_MASK      (0xC000U)
29319 #define DDRPHY_DX5BDLR7_RESERVED_15_14_SHIFT     (14U)
29320 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29321  */
29322 #define DDRPHY_DX5BDLR7_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_15_14_MASK)
29323 #define DDRPHY_DX5BDLR7_RESERVED_21_16_MASK      (0x3F0000U)
29324 #define DDRPHY_DX5BDLR7_RESERVED_21_16_SHIFT     (16U)
29325 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
29326  */
29327 #define DDRPHY_DX5BDLR7_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_21_16_MASK)
29328 #define DDRPHY_DX5BDLR7_RESERVED_31_22_MASK      (0xFFC00000U)
29329 #define DDRPHY_DX5BDLR7_RESERVED_31_22_SHIFT     (22U)
29330 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
29331  */
29332 #define DDRPHY_DX5BDLR7_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_31_22_MASK)
29333 /*! @} */
29334 
29335 /*! @name DX5BDLR8 - DATX8 n Bit Delay Line Register 8 */
29336 /*! @{ */
29337 #define DDRPHY_DX5BDLR8_RESERVED_5_0_MASK        (0x3FU)
29338 #define DDRPHY_DX5BDLR8_RESERVED_5_0_SHIFT       (0U)
29339 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
29340  */
29341 #define DDRPHY_DX5BDLR8_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_5_0_MASK)
29342 #define DDRPHY_DX5BDLR8_RESERVED_7_6_MASK        (0xC0U)
29343 #define DDRPHY_DX5BDLR8_RESERVED_7_6_SHIFT       (6U)
29344 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29345  */
29346 #define DDRPHY_DX5BDLR8_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_7_6_MASK)
29347 #define DDRPHY_DX5BDLR8_RESERVED_13_8_MASK       (0x3F00U)
29348 #define DDRPHY_DX5BDLR8_RESERVED_13_8_SHIFT      (8U)
29349 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
29350  */
29351 #define DDRPHY_DX5BDLR8_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_13_8_MASK)
29352 #define DDRPHY_DX5BDLR8_RESERVED_15_14_MASK      (0xC000U)
29353 #define DDRPHY_DX5BDLR8_RESERVED_15_14_SHIFT     (14U)
29354 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29355  */
29356 #define DDRPHY_DX5BDLR8_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_15_14_MASK)
29357 #define DDRPHY_DX5BDLR8_RESERVED_21_16_MASK      (0x3F0000U)
29358 #define DDRPHY_DX5BDLR8_RESERVED_21_16_SHIFT     (16U)
29359 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
29360  */
29361 #define DDRPHY_DX5BDLR8_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_21_16_MASK)
29362 #define DDRPHY_DX5BDLR8_RESERVED_31_22_MASK      (0xFFC00000U)
29363 #define DDRPHY_DX5BDLR8_RESERVED_31_22_SHIFT     (22U)
29364 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
29365  */
29366 #define DDRPHY_DX5BDLR8_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_31_22_MASK)
29367 /*! @} */
29368 
29369 /*! @name DX5BDLR9 - DATX8 n Bit Delay Line Register 9 */
29370 /*! @{ */
29371 #define DDRPHY_DX5BDLR9_RESERVED_5_0_MASK        (0x3FU)
29372 #define DDRPHY_DX5BDLR9_RESERVED_5_0_SHIFT       (0U)
29373 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
29374  */
29375 #define DDRPHY_DX5BDLR9_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_5_0_MASK)
29376 #define DDRPHY_DX5BDLR9_RESERVED_7_6_MASK        (0xC0U)
29377 #define DDRPHY_DX5BDLR9_RESERVED_7_6_SHIFT       (6U)
29378 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29379  */
29380 #define DDRPHY_DX5BDLR9_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_7_6_MASK)
29381 #define DDRPHY_DX5BDLR9_RESERVED_13_8_MASK       (0x3F00U)
29382 #define DDRPHY_DX5BDLR9_RESERVED_13_8_SHIFT      (8U)
29383 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
29384  */
29385 #define DDRPHY_DX5BDLR9_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_13_8_MASK)
29386 #define DDRPHY_DX5BDLR9_RESERVED_15_14_MASK      (0xC000U)
29387 #define DDRPHY_DX5BDLR9_RESERVED_15_14_SHIFT     (14U)
29388 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29389  */
29390 #define DDRPHY_DX5BDLR9_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_15_14_MASK)
29391 #define DDRPHY_DX5BDLR9_RESERVED_21_16_MASK      (0x3F0000U)
29392 #define DDRPHY_DX5BDLR9_RESERVED_21_16_SHIFT     (16U)
29393 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
29394  */
29395 #define DDRPHY_DX5BDLR9_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_21_16_MASK)
29396 #define DDRPHY_DX5BDLR9_RESERVED_31_22_MASK      (0xFFC00000U)
29397 #define DDRPHY_DX5BDLR9_RESERVED_31_22_SHIFT     (22U)
29398 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
29399  */
29400 #define DDRPHY_DX5BDLR9_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_31_22_MASK)
29401 /*! @} */
29402 
29403 /*! @name DX5LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
29404 /*! @{ */
29405 #define DDRPHY_DX5LCDLR0_WLD_MASK                (0x1FFU)
29406 #define DDRPHY_DX5LCDLR0_WLD_SHIFT               (0U)
29407 /*! WLD - Write Leveling Delay
29408  */
29409 #define DDRPHY_DX5LCDLR0_WLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_WLD_SHIFT)) & DDRPHY_DX5LCDLR0_WLD_MASK)
29410 #define DDRPHY_DX5LCDLR0_RESERVED_15_9_MASK      (0xFE00U)
29411 #define DDRPHY_DX5LCDLR0_RESERVED_15_9_SHIFT     (9U)
29412 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29413  */
29414 #define DDRPHY_DX5LCDLR0_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR0_RESERVED_15_9_MASK)
29415 #define DDRPHY_DX5LCDLR0_RESERVED_24_16_MASK     (0x1FF0000U)
29416 #define DDRPHY_DX5LCDLR0_RESERVED_24_16_SHIFT    (16U)
29417 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29418  */
29419 #define DDRPHY_DX5LCDLR0_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR0_RESERVED_24_16_MASK)
29420 #define DDRPHY_DX5LCDLR0_RESERVED_31_25_MASK     (0xFE000000U)
29421 #define DDRPHY_DX5LCDLR0_RESERVED_31_25_SHIFT    (25U)
29422 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29423  */
29424 #define DDRPHY_DX5LCDLR0_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR0_RESERVED_31_25_MASK)
29425 /*! @} */
29426 
29427 /*! @name DX5LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
29428 /*! @{ */
29429 #define DDRPHY_DX5LCDLR1_WDQD_MASK               (0x1FFU)
29430 #define DDRPHY_DX5LCDLR1_WDQD_SHIFT              (0U)
29431 /*! WDQD - Write Data Delay
29432  */
29433 #define DDRPHY_DX5LCDLR1_WDQD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_WDQD_SHIFT)) & DDRPHY_DX5LCDLR1_WDQD_MASK)
29434 #define DDRPHY_DX5LCDLR1_RESERVED_15_9_MASK      (0xFE00U)
29435 #define DDRPHY_DX5LCDLR1_RESERVED_15_9_SHIFT     (9U)
29436 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29437  */
29438 #define DDRPHY_DX5LCDLR1_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR1_RESERVED_15_9_MASK)
29439 #define DDRPHY_DX5LCDLR1_RESERVED_24_16_MASK     (0x1FF0000U)
29440 #define DDRPHY_DX5LCDLR1_RESERVED_24_16_SHIFT    (16U)
29441 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29442  */
29443 #define DDRPHY_DX5LCDLR1_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR1_RESERVED_24_16_MASK)
29444 #define DDRPHY_DX5LCDLR1_RESERVED_31_25_MASK     (0xFE000000U)
29445 #define DDRPHY_DX5LCDLR1_RESERVED_31_25_SHIFT    (25U)
29446 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29447  */
29448 #define DDRPHY_DX5LCDLR1_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR1_RESERVED_31_25_MASK)
29449 /*! @} */
29450 
29451 /*! @name DX5LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
29452 /*! @{ */
29453 #define DDRPHY_DX5LCDLR2_DQSGD_MASK              (0x1FFU)
29454 #define DDRPHY_DX5LCDLR2_DQSGD_SHIFT             (0U)
29455 /*! DQSGD - Read DQS Gating Delay
29456  */
29457 #define DDRPHY_DX5LCDLR2_DQSGD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX5LCDLR2_DQSGD_MASK)
29458 #define DDRPHY_DX5LCDLR2_RESERVED_15_9_MASK      (0xFE00U)
29459 #define DDRPHY_DX5LCDLR2_RESERVED_15_9_SHIFT     (9U)
29460 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29461  */
29462 #define DDRPHY_DX5LCDLR2_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR2_RESERVED_15_9_MASK)
29463 #define DDRPHY_DX5LCDLR2_RESERVED_24_16_MASK     (0x1FF0000U)
29464 #define DDRPHY_DX5LCDLR2_RESERVED_24_16_SHIFT    (16U)
29465 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29466  */
29467 #define DDRPHY_DX5LCDLR2_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR2_RESERVED_24_16_MASK)
29468 #define DDRPHY_DX5LCDLR2_RESERVED_31_25_MASK     (0xFE000000U)
29469 #define DDRPHY_DX5LCDLR2_RESERVED_31_25_SHIFT    (25U)
29470 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29471  */
29472 #define DDRPHY_DX5LCDLR2_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR2_RESERVED_31_25_MASK)
29473 /*! @} */
29474 
29475 /*! @name DX5LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
29476 /*! @{ */
29477 #define DDRPHY_DX5LCDLR3_RDQSD_MASK              (0x1FFU)
29478 #define DDRPHY_DX5LCDLR3_RDQSD_SHIFT             (0U)
29479 /*! RDQSD - Read DQS Delay
29480  */
29481 #define DDRPHY_DX5LCDLR3_RDQSD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX5LCDLR3_RDQSD_MASK)
29482 #define DDRPHY_DX5LCDLR3_RESERVED_15_9_MASK      (0xFE00U)
29483 #define DDRPHY_DX5LCDLR3_RESERVED_15_9_SHIFT     (9U)
29484 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29485  */
29486 #define DDRPHY_DX5LCDLR3_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR3_RESERVED_15_9_MASK)
29487 #define DDRPHY_DX5LCDLR3_RESERVED_24_16_MASK     (0x1FF0000U)
29488 #define DDRPHY_DX5LCDLR3_RESERVED_24_16_SHIFT    (16U)
29489 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29490  */
29491 #define DDRPHY_DX5LCDLR3_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR3_RESERVED_24_16_MASK)
29492 #define DDRPHY_DX5LCDLR3_RESERVED_31_25_MASK     (0xFE000000U)
29493 #define DDRPHY_DX5LCDLR3_RESERVED_31_25_SHIFT    (25U)
29494 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29495  */
29496 #define DDRPHY_DX5LCDLR3_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR3_RESERVED_31_25_MASK)
29497 /*! @} */
29498 
29499 /*! @name DX5LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
29500 /*! @{ */
29501 #define DDRPHY_DX5LCDLR4_RDQSND_MASK             (0x1FFU)
29502 #define DDRPHY_DX5LCDLR4_RDQSND_SHIFT            (0U)
29503 /*! RDQSND - Read DQSN Delay
29504  */
29505 #define DDRPHY_DX5LCDLR4_RDQSND(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX5LCDLR4_RDQSND_MASK)
29506 #define DDRPHY_DX5LCDLR4_RESERVED_15_9_MASK      (0xFE00U)
29507 #define DDRPHY_DX5LCDLR4_RESERVED_15_9_SHIFT     (9U)
29508 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29509  */
29510 #define DDRPHY_DX5LCDLR4_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR4_RESERVED_15_9_MASK)
29511 #define DDRPHY_DX5LCDLR4_RESERVED_24_16_MASK     (0x1FF0000U)
29512 #define DDRPHY_DX5LCDLR4_RESERVED_24_16_SHIFT    (16U)
29513 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29514  */
29515 #define DDRPHY_DX5LCDLR4_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR4_RESERVED_24_16_MASK)
29516 #define DDRPHY_DX5LCDLR4_RESERVED_31_25_MASK     (0xFE000000U)
29517 #define DDRPHY_DX5LCDLR4_RESERVED_31_25_SHIFT    (25U)
29518 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29519  */
29520 #define DDRPHY_DX5LCDLR4_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR4_RESERVED_31_25_MASK)
29521 /*! @} */
29522 
29523 /*! @name DX5LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
29524 /*! @{ */
29525 #define DDRPHY_DX5LCDLR5_DQSGSD_MASK             (0x1FFU)
29526 #define DDRPHY_DX5LCDLR5_DQSGSD_SHIFT            (0U)
29527 /*! DQSGSD - DQS Gating Status Delay
29528  */
29529 #define DDRPHY_DX5LCDLR5_DQSGSD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX5LCDLR5_DQSGSD_MASK)
29530 #define DDRPHY_DX5LCDLR5_RESERVED_15_9_MASK      (0xFE00U)
29531 #define DDRPHY_DX5LCDLR5_RESERVED_15_9_SHIFT     (9U)
29532 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29533  */
29534 #define DDRPHY_DX5LCDLR5_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR5_RESERVED_15_9_MASK)
29535 #define DDRPHY_DX5LCDLR5_RESERVED_24_16_MASK     (0x1FF0000U)
29536 #define DDRPHY_DX5LCDLR5_RESERVED_24_16_SHIFT    (16U)
29537 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29538  */
29539 #define DDRPHY_DX5LCDLR5_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR5_RESERVED_24_16_MASK)
29540 #define DDRPHY_DX5LCDLR5_RESERVED_31_25_MASK     (0xFE000000U)
29541 #define DDRPHY_DX5LCDLR5_RESERVED_31_25_SHIFT    (25U)
29542 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29543  */
29544 #define DDRPHY_DX5LCDLR5_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR5_RESERVED_31_25_MASK)
29545 /*! @} */
29546 
29547 /*! @name DX5MDLR0 - DATX8 n Master Delay Line Register 0 */
29548 /*! @{ */
29549 #define DDRPHY_DX5MDLR0_IPRD_MASK                (0x1FFU)
29550 #define DDRPHY_DX5MDLR0_IPRD_SHIFT               (0U)
29551 /*! IPRD - Initial Period
29552  */
29553 #define DDRPHY_DX5MDLR0_IPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_IPRD_SHIFT)) & DDRPHY_DX5MDLR0_IPRD_MASK)
29554 #define DDRPHY_DX5MDLR0_RESERVED_15_9_MASK       (0xFE00U)
29555 #define DDRPHY_DX5MDLR0_RESERVED_15_9_SHIFT      (9U)
29556 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29557  */
29558 #define DDRPHY_DX5MDLR0_RESERVED_15_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX5MDLR0_RESERVED_15_9_MASK)
29559 #define DDRPHY_DX5MDLR0_TPRD_MASK                (0x1FF0000U)
29560 #define DDRPHY_DX5MDLR0_TPRD_SHIFT               (16U)
29561 /*! TPRD - Target Period
29562  */
29563 #define DDRPHY_DX5MDLR0_TPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_TPRD_SHIFT)) & DDRPHY_DX5MDLR0_TPRD_MASK)
29564 #define DDRPHY_DX5MDLR0_RESERVED_31_25_MASK      (0xFE000000U)
29565 #define DDRPHY_DX5MDLR0_RESERVED_31_25_SHIFT     (25U)
29566 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29567  */
29568 #define DDRPHY_DX5MDLR0_RESERVED_31_25(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX5MDLR0_RESERVED_31_25_MASK)
29569 /*! @} */
29570 
29571 /*! @name DX5MDLR1 - DATX8 n Master Delay Line Register 1 */
29572 /*! @{ */
29573 #define DDRPHY_DX5MDLR1_MDLD_MASK                (0x1FFU)
29574 #define DDRPHY_DX5MDLR1_MDLD_SHIFT               (0U)
29575 /*! MDLD - MDL Delay
29576  */
29577 #define DDRPHY_DX5MDLR1_MDLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR1_MDLD_SHIFT)) & DDRPHY_DX5MDLR1_MDLD_MASK)
29578 #define DDRPHY_DX5MDLR1_RESERVED_31_9_MASK       (0xFFFFFE00U)
29579 #define DDRPHY_DX5MDLR1_RESERVED_31_9_SHIFT      (9U)
29580 /*! RESERVED_31_9 - Reserved. Return zeroes on reads.
29581  */
29582 #define DDRPHY_DX5MDLR1_RESERVED_31_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX5MDLR1_RESERVED_31_9_MASK)
29583 /*! @} */
29584 
29585 /*! @name DX5GTR0 - DATX8 n General Timing Register 0 */
29586 /*! @{ */
29587 #define DDRPHY_DX5GTR0_DGSL_MASK                 (0x1FU)
29588 #define DDRPHY_DX5GTR0_DGSL_SHIFT                (0U)
29589 /*! DGSL - DQS Gating System Latency
29590  */
29591 #define DDRPHY_DX5GTR0_DGSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_DGSL_SHIFT)) & DDRPHY_DX5GTR0_DGSL_MASK)
29592 #define DDRPHY_DX5GTR0_RESERVED_7_5_MASK         (0xE0U)
29593 #define DDRPHY_DX5GTR0_RESERVED_7_5_SHIFT        (5U)
29594 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
29595  */
29596 #define DDRPHY_DX5GTR0_RESERVED_7_5(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_7_5_MASK)
29597 #define DDRPHY_DX5GTR0_RESERVED_12_8_MASK        (0x1F00U)
29598 #define DDRPHY_DX5GTR0_RESERVED_12_8_SHIFT       (8U)
29599 /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
29600  */
29601 #define DDRPHY_DX5GTR0_RESERVED_12_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_12_8_MASK)
29602 #define DDRPHY_DX5GTR0_RESERVED_15_13_MASK       (0xE000U)
29603 #define DDRPHY_DX5GTR0_RESERVED_15_13_SHIFT      (13U)
29604 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
29605  */
29606 #define DDRPHY_DX5GTR0_RESERVED_15_13(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_15_13_MASK)
29607 #define DDRPHY_DX5GTR0_WLSL_MASK                 (0xF0000U)
29608 #define DDRPHY_DX5GTR0_WLSL_SHIFT                (16U)
29609 /*! WLSL - Write Leveling System Latency
29610  */
29611 #define DDRPHY_DX5GTR0_WLSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_WLSL_SHIFT)) & DDRPHY_DX5GTR0_WLSL_MASK)
29612 #define DDRPHY_DX5GTR0_RESERVED_23_20_MASK       (0xF00000U)
29613 #define DDRPHY_DX5GTR0_RESERVED_23_20_SHIFT      (20U)
29614 /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
29615  */
29616 #define DDRPHY_DX5GTR0_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_23_20_MASK)
29617 #define DDRPHY_DX5GTR0_WDQSL_MASK                (0x7000000U)
29618 #define DDRPHY_DX5GTR0_WDQSL_SHIFT               (24U)
29619 /*! WDQSL - DQ Write Path Latency Pipeline
29620  */
29621 #define DDRPHY_DX5GTR0_WDQSL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_WDQSL_SHIFT)) & DDRPHY_DX5GTR0_WDQSL_MASK)
29622 #define DDRPHY_DX5GTR0_RESERVED_31_24_MASK       (0xF8000000U)
29623 #define DDRPHY_DX5GTR0_RESERVED_31_24_SHIFT      (27U)
29624 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
29625  */
29626 #define DDRPHY_DX5GTR0_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_31_24_MASK)
29627 /*! @} */
29628 
29629 /*! @name DX5RSR0 - DATX8 n Rank Status Register 0 */
29630 /*! @{ */
29631 #define DDRPHY_DX5RSR0_QSGERR_MASK               (0xFFFFU)
29632 #define DDRPHY_DX5RSR0_QSGERR_SHIFT              (0U)
29633 /*! QSGERR - DQS Gate Training Error
29634  */
29635 #define DDRPHY_DX5RSR0_QSGERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR0_QSGERR_SHIFT)) & DDRPHY_DX5RSR0_QSGERR_MASK)
29636 #define DDRPHY_DX5RSR0_RESERVED_31_16_MASK       (0xFFFF0000U)
29637 #define DDRPHY_DX5RSR0_RESERVED_31_16_SHIFT      (16U)
29638 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
29639  */
29640 #define DDRPHY_DX5RSR0_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR0_RESERVED_31_16_MASK)
29641 /*! @} */
29642 
29643 /*! @name DX5RSR1 - DATX8 n Rank Status Register 1 */
29644 /*! @{ */
29645 #define DDRPHY_DX5RSR1_RDLVLERR_MASK             (0xFFFFU)
29646 #define DDRPHY_DX5RSR1_RDLVLERR_SHIFT            (0U)
29647 /*! RDLVLERR - Read Leveling Error
29648  */
29649 #define DDRPHY_DX5RSR1_RDLVLERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX5RSR1_RDLVLERR_MASK)
29650 #define DDRPHY_DX5RSR1_RESERVED_31_16_MASK       (0xFFFF0000U)
29651 #define DDRPHY_DX5RSR1_RESERVED_31_16_SHIFT      (16U)
29652 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
29653  */
29654 #define DDRPHY_DX5RSR1_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR1_RESERVED_31_16_MASK)
29655 /*! @} */
29656 
29657 /*! @name DX5RSR2 - DATX8 n Rank Status Register 2 */
29658 /*! @{ */
29659 #define DDRPHY_DX5RSR2_WLAWN_MASK                (0xFFFFU)
29660 #define DDRPHY_DX5RSR2_WLAWN_SHIFT               (0U)
29661 /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
29662  */
29663 #define DDRPHY_DX5RSR2_WLAWN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR2_WLAWN_SHIFT)) & DDRPHY_DX5RSR2_WLAWN_MASK)
29664 #define DDRPHY_DX5RSR2_RESERVED_31_16_MASK       (0xFFFF0000U)
29665 #define DDRPHY_DX5RSR2_RESERVED_31_16_SHIFT      (16U)
29666 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
29667  */
29668 #define DDRPHY_DX5RSR2_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR2_RESERVED_31_16_MASK)
29669 /*! @} */
29670 
29671 /*! @name DX5RSR3 - DATX8 n Rank Status Register 3 */
29672 /*! @{ */
29673 #define DDRPHY_DX5RSR3_WLAERR_MASK               (0xFFFFU)
29674 #define DDRPHY_DX5RSR3_WLAERR_SHIFT              (0U)
29675 /*! WLAERR - Write Leveling Adjustment Error
29676  */
29677 #define DDRPHY_DX5RSR3_WLAERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR3_WLAERR_SHIFT)) & DDRPHY_DX5RSR3_WLAERR_MASK)
29678 #define DDRPHY_DX5RSR3_RESERVED_31_16_MASK       (0xFFFF0000U)
29679 #define DDRPHY_DX5RSR3_RESERVED_31_16_SHIFT      (16U)
29680 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
29681  */
29682 #define DDRPHY_DX5RSR3_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR3_RESERVED_31_16_MASK)
29683 /*! @} */
29684 
29685 /*! @name DX5GSR0 - DATX8 n General Status Register 0 */
29686 /*! @{ */
29687 #define DDRPHY_DX5GSR0_WDQCAL_MASK               (0x1U)
29688 #define DDRPHY_DX5GSR0_WDQCAL_SHIFT              (0U)
29689 /*! WDQCAL - Write DQ Calibration
29690  */
29691 #define DDRPHY_DX5GSR0_WDQCAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WDQCAL_SHIFT)) & DDRPHY_DX5GSR0_WDQCAL_MASK)
29692 #define DDRPHY_DX5GSR0_RDQSCAL_MASK              (0x2U)
29693 #define DDRPHY_DX5GSR0_RDQSCAL_SHIFT             (1U)
29694 /*! RDQSCAL - Read DQS Calibration
29695  */
29696 #define DDRPHY_DX5GSR0_RDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX5GSR0_RDQSCAL_MASK)
29697 #define DDRPHY_DX5GSR0_RDQSNCAL_MASK             (0x4U)
29698 #define DDRPHY_DX5GSR0_RDQSNCAL_SHIFT            (2U)
29699 /*! RDQSNCAL - Read DQS# Calibration
29700  */
29701 #define DDRPHY_DX5GSR0_RDQSNCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX5GSR0_RDQSNCAL_MASK)
29702 #define DDRPHY_DX5GSR0_GDQSCAL_MASK              (0x8U)
29703 #define DDRPHY_DX5GSR0_GDQSCAL_SHIFT             (3U)
29704 /*! GDQSCAL - Read DQS gating Calibration
29705  */
29706 #define DDRPHY_DX5GSR0_GDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX5GSR0_GDQSCAL_MASK)
29707 #define DDRPHY_DX5GSR0_WLCAL_MASK                (0x10U)
29708 #define DDRPHY_DX5GSR0_WLCAL_SHIFT               (4U)
29709 /*! WLCAL - Write Leveling Calibration
29710  */
29711 #define DDRPHY_DX5GSR0_WLCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLCAL_SHIFT)) & DDRPHY_DX5GSR0_WLCAL_MASK)
29712 #define DDRPHY_DX5GSR0_WLDONE_MASK               (0x20U)
29713 #define DDRPHY_DX5GSR0_WLDONE_SHIFT              (5U)
29714 /*! WLDONE - Write Leveling Done
29715  */
29716 #define DDRPHY_DX5GSR0_WLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLDONE_SHIFT)) & DDRPHY_DX5GSR0_WLDONE_MASK)
29717 #define DDRPHY_DX5GSR0_WLERR_MASK                (0x40U)
29718 #define DDRPHY_DX5GSR0_WLERR_SHIFT               (6U)
29719 /*! WLERR - Write Leveling Error
29720  */
29721 #define DDRPHY_DX5GSR0_WLERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLERR_SHIFT)) & DDRPHY_DX5GSR0_WLERR_MASK)
29722 #define DDRPHY_DX5GSR0_WLPRD_MASK                (0xFF80U)
29723 #define DDRPHY_DX5GSR0_WLPRD_SHIFT               (7U)
29724 /*! WLPRD - Write Leveling Period
29725  */
29726 #define DDRPHY_DX5GSR0_WLPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLPRD_SHIFT)) & DDRPHY_DX5GSR0_WLPRD_MASK)
29727 #define DDRPHY_DX5GSR0_DPLOCK_MASK               (0x10000U)
29728 #define DDRPHY_DX5GSR0_DPLOCK_SHIFT              (16U)
29729 /*! DPLOCK - DATX8 PLL Lock
29730  */
29731 #define DDRPHY_DX5GSR0_DPLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_DPLOCK_SHIFT)) & DDRPHY_DX5GSR0_DPLOCK_MASK)
29732 #define DDRPHY_DX5GSR0_GDQSPRD_MASK              (0x3FE0000U)
29733 #define DDRPHY_DX5GSR0_GDQSPRD_SHIFT             (17U)
29734 /*! GDQSPRD - Read DQS gating Period
29735  */
29736 #define DDRPHY_DX5GSR0_GDQSPRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX5GSR0_GDQSPRD_MASK)
29737 #define DDRPHY_DX5GSR0_RESERVED_29_26_MASK       (0x3C000000U)
29738 #define DDRPHY_DX5GSR0_RESERVED_29_26_SHIFT      (26U)
29739 /*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
29740  */
29741 #define DDRPHY_DX5GSR0_RESERVED_29_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX5GSR0_RESERVED_29_26_MASK)
29742 #define DDRPHY_DX5GSR0_WLDQ_MASK                 (0x40000000U)
29743 #define DDRPHY_DX5GSR0_WLDQ_SHIFT                (30U)
29744 /*! WLDQ - Write Leveling DQ Status
29745  */
29746 #define DDRPHY_DX5GSR0_WLDQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLDQ_SHIFT)) & DDRPHY_DX5GSR0_WLDQ_MASK)
29747 #define DDRPHY_DX5GSR0_RESERVED_31_MASK          (0x80000000U)
29748 #define DDRPHY_DX5GSR0_RESERVED_31_SHIFT         (31U)
29749 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
29750  */
29751 #define DDRPHY_DX5GSR0_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX5GSR0_RESERVED_31_MASK)
29752 /*! @} */
29753 
29754 /*! @name DX5GSR1 - DATX8 n General Status Register 1 */
29755 /*! @{ */
29756 #define DDRPHY_DX5GSR1_DLTDONE_MASK              (0x1U)
29757 #define DDRPHY_DX5GSR1_DLTDONE_SHIFT             (0U)
29758 /*! DLTDONE - Delay Line Test Done
29759  */
29760 #define DDRPHY_DX5GSR1_DLTDONE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR1_DLTDONE_SHIFT)) & DDRPHY_DX5GSR1_DLTDONE_MASK)
29761 #define DDRPHY_DX5GSR1_DLTCODE_MASK              (0x1FFFFFEU)
29762 #define DDRPHY_DX5GSR1_DLTCODE_SHIFT             (1U)
29763 /*! DLTCODE - Delay Line Test Code
29764  */
29765 #define DDRPHY_DX5GSR1_DLTCODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR1_DLTCODE_SHIFT)) & DDRPHY_DX5GSR1_DLTCODE_MASK)
29766 #define DDRPHY_DX5GSR1_RESERVED_31_25_MASK       (0xFE000000U)
29767 #define DDRPHY_DX5GSR1_RESERVED_31_25_SHIFT      (25U)
29768 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
29769  */
29770 #define DDRPHY_DX5GSR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX5GSR1_RESERVED_31_25_MASK)
29771 /*! @} */
29772 
29773 /*! @name DX5GSR2 - DATX8 n General Status Register 2 */
29774 /*! @{ */
29775 #define DDRPHY_DX5GSR2_RDERR_MASK                (0x1U)
29776 #define DDRPHY_DX5GSR2_RDERR_SHIFT               (0U)
29777 /*! RDERR - Read Bit Deskew Error
29778  */
29779 #define DDRPHY_DX5GSR2_RDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_RDERR_SHIFT)) & DDRPHY_DX5GSR2_RDERR_MASK)
29780 #define DDRPHY_DX5GSR2_RDWN_MASK                 (0x2U)
29781 #define DDRPHY_DX5GSR2_RDWN_SHIFT                (1U)
29782 /*! RDWN - Read Bit Deskew Warning
29783  */
29784 #define DDRPHY_DX5GSR2_RDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_RDWN_SHIFT)) & DDRPHY_DX5GSR2_RDWN_MASK)
29785 #define DDRPHY_DX5GSR2_WDERR_MASK                (0x4U)
29786 #define DDRPHY_DX5GSR2_WDERR_SHIFT               (2U)
29787 /*! WDERR - Write Bit Deskew Error
29788  */
29789 #define DDRPHY_DX5GSR2_WDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WDERR_SHIFT)) & DDRPHY_DX5GSR2_WDERR_MASK)
29790 #define DDRPHY_DX5GSR2_WDWN_MASK                 (0x8U)
29791 #define DDRPHY_DX5GSR2_WDWN_SHIFT                (3U)
29792 /*! WDWN - Write Bit Deskew Warning
29793  */
29794 #define DDRPHY_DX5GSR2_WDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WDWN_SHIFT)) & DDRPHY_DX5GSR2_WDWN_MASK)
29795 #define DDRPHY_DX5GSR2_REERR_MASK                (0x10U)
29796 #define DDRPHY_DX5GSR2_REERR_SHIFT               (4U)
29797 /*! REERR - Read Eye Centering Error
29798  */
29799 #define DDRPHY_DX5GSR2_REERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_REERR_SHIFT)) & DDRPHY_DX5GSR2_REERR_MASK)
29800 #define DDRPHY_DX5GSR2_REWN_MASK                 (0x20U)
29801 #define DDRPHY_DX5GSR2_REWN_SHIFT                (5U)
29802 /*! REWN - Read Eye Centering Warning
29803  */
29804 #define DDRPHY_DX5GSR2_REWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_REWN_SHIFT)) & DDRPHY_DX5GSR2_REWN_MASK)
29805 #define DDRPHY_DX5GSR2_WEERR_MASK                (0x40U)
29806 #define DDRPHY_DX5GSR2_WEERR_SHIFT               (6U)
29807 /*! WEERR - Write Eye Centering Error
29808  */
29809 #define DDRPHY_DX5GSR2_WEERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WEERR_SHIFT)) & DDRPHY_DX5GSR2_WEERR_MASK)
29810 #define DDRPHY_DX5GSR2_WEWN_MASK                 (0x80U)
29811 #define DDRPHY_DX5GSR2_WEWN_SHIFT                (7U)
29812 /*! WEWN - Write Eye Centering Warning
29813  */
29814 #define DDRPHY_DX5GSR2_WEWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WEWN_SHIFT)) & DDRPHY_DX5GSR2_WEWN_MASK)
29815 #define DDRPHY_DX5GSR2_ESTAT_MASK                (0xF00U)
29816 #define DDRPHY_DX5GSR2_ESTAT_SHIFT               (8U)
29817 /*! ESTAT - Error Status
29818  */
29819 #define DDRPHY_DX5GSR2_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_ESTAT_SHIFT)) & DDRPHY_DX5GSR2_ESTAT_MASK)
29820 #define DDRPHY_DX5GSR2_DQS2DQERR_MASK            (0xFF000U)
29821 #define DDRPHY_DX5GSR2_DQS2DQERR_SHIFT           (12U)
29822 /*! DQS2DQERR - Write DQS2DQ Training Error
29823  */
29824 #define DDRPHY_DX5GSR2_DQS2DQERR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX5GSR2_DQS2DQERR_MASK)
29825 #define DDRPHY_DX5GSR2_SRDERR_MASK               (0x100000U)
29826 #define DDRPHY_DX5GSR2_SRDERR_SHIFT              (20U)
29827 /*! SRDERR - Static Read Error
29828  */
29829 #define DDRPHY_DX5GSR2_SRDERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_SRDERR_SHIFT)) & DDRPHY_DX5GSR2_SRDERR_MASK)
29830 #define DDRPHY_DX5GSR2_RESERVED_21_MASK          (0x200000U)
29831 #define DDRPHY_DX5GSR2_RESERVED_21_SHIFT         (21U)
29832 /*! RESERVED_21 - Reserved. Return zeroes on reads.
29833  */
29834 #define DDRPHY_DX5GSR2_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX5GSR2_RESERVED_21_MASK)
29835 #define DDRPHY_DX5GSR2_GSDQSCAL_MASK             (0x400000U)
29836 #define DDRPHY_DX5GSR2_GSDQSCAL_SHIFT            (22U)
29837 /*! GSDQSCAL - Read DQS Gating Status Calibration
29838  */
29839 #define DDRPHY_DX5GSR2_GSDQSCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX5GSR2_GSDQSCAL_MASK)
29840 #define DDRPHY_DX5GSR2_GSDQSPRD_MASK             (0xFF800000U)
29841 #define DDRPHY_DX5GSR2_GSDQSPRD_SHIFT            (23U)
29842 /*! GSDQSPRD - Read DQS gating Status Period
29843  */
29844 #define DDRPHY_DX5GSR2_GSDQSPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX5GSR2_GSDQSPRD_MASK)
29845 /*! @} */
29846 
29847 /*! @name DX5GSR3 - DATX8 n General Status Register 3 */
29848 /*! @{ */
29849 #define DDRPHY_DX5GSR3_SRDPC_MASK                (0x3U)
29850 #define DDRPHY_DX5GSR3_SRDPC_SHIFT               (0U)
29851 /*! SRDPC - Static Read Delay Pass Count
29852  */
29853 #define DDRPHY_DX5GSR3_SRDPC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_SRDPC_SHIFT)) & DDRPHY_DX5GSR3_SRDPC_MASK)
29854 #define DDRPHY_DX5GSR3_RESERVED_7_2_MASK         (0xFCU)
29855 #define DDRPHY_DX5GSR3_RESERVED_7_2_SHIFT        (2U)
29856 /*! RESERVED_7_2 - Reserved. Return zeroes on reads.
29857  */
29858 #define DDRPHY_DX5GSR3_RESERVED_7_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX5GSR3_RESERVED_7_2_MASK)
29859 #define DDRPHY_DX5GSR3_HVERR_MASK                (0xF00U)
29860 #define DDRPHY_DX5GSR3_HVERR_SHIFT               (8U)
29861 /*! HVERR - Host VREF Training Error
29862  */
29863 #define DDRPHY_DX5GSR3_HVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_HVERR_SHIFT)) & DDRPHY_DX5GSR3_HVERR_MASK)
29864 #define DDRPHY_DX5GSR3_HVWRN_MASK                (0xF000U)
29865 #define DDRPHY_DX5GSR3_HVWRN_SHIFT               (12U)
29866 /*! HVWRN - Host VREF Training Warning
29867  */
29868 #define DDRPHY_DX5GSR3_HVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_HVWRN_SHIFT)) & DDRPHY_DX5GSR3_HVWRN_MASK)
29869 #define DDRPHY_DX5GSR3_DVERR_MASK                (0xF0000U)
29870 #define DDRPHY_DX5GSR3_DVERR_SHIFT               (16U)
29871 /*! DVERR - DRAM VREF Training Error
29872  */
29873 #define DDRPHY_DX5GSR3_DVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_DVERR_SHIFT)) & DDRPHY_DX5GSR3_DVERR_MASK)
29874 #define DDRPHY_DX5GSR3_DVWRN_MASK                (0xF00000U)
29875 #define DDRPHY_DX5GSR3_DVWRN_SHIFT               (20U)
29876 /*! DVWRN - DRAM VREF Training Warning
29877  */
29878 #define DDRPHY_DX5GSR3_DVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_DVWRN_SHIFT)) & DDRPHY_DX5GSR3_DVWRN_MASK)
29879 #define DDRPHY_DX5GSR3_ESTAT_MASK                (0x7000000U)
29880 #define DDRPHY_DX5GSR3_ESTAT_SHIFT               (24U)
29881 /*! ESTAT - VREF Training Error Status Code
29882  */
29883 #define DDRPHY_DX5GSR3_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_ESTAT_SHIFT)) & DDRPHY_DX5GSR3_ESTAT_MASK)
29884 #define DDRPHY_DX5GSR3_RESERVED_31_27_MASK       (0xF8000000U)
29885 #define DDRPHY_DX5GSR3_RESERVED_31_27_SHIFT      (27U)
29886 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
29887  */
29888 #define DDRPHY_DX5GSR3_RESERVED_31_27(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX5GSR3_RESERVED_31_27_MASK)
29889 /*! @} */
29890 
29891 /*! @name DX5GSR4 - DATX8 n General Status Register 4 */
29892 /*! @{ */
29893 #define DDRPHY_DX5GSR4_RESERVED_0_MASK           (0x1U)
29894 #define DDRPHY_DX5GSR4_RESERVED_0_SHIFT          (0U)
29895 /*! RESERVED_0 - Reserved. Return zeroes on reads.
29896  */
29897 #define DDRPHY_DX5GSR4_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_0_MASK)
29898 #define DDRPHY_DX5GSR4_RESERVED_1_MASK           (0x2U)
29899 #define DDRPHY_DX5GSR4_RESERVED_1_SHIFT          (1U)
29900 /*! RESERVED_1 - Reserved. Return zeroes on reads.
29901  */
29902 #define DDRPHY_DX5GSR4_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_1_MASK)
29903 #define DDRPHY_DX5GSR4_RESERVED_2_MASK           (0x4U)
29904 #define DDRPHY_DX5GSR4_RESERVED_2_SHIFT          (2U)
29905 /*! RESERVED_2 - Reserved. Return zeroes on reads.
29906  */
29907 #define DDRPHY_DX5GSR4_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_2_MASK)
29908 #define DDRPHY_DX5GSR4_RESERVED_3_MASK           (0x8U)
29909 #define DDRPHY_DX5GSR4_RESERVED_3_SHIFT          (3U)
29910 /*! RESERVED_3 - Reserved. Return zeroes on reads.
29911  */
29912 #define DDRPHY_DX5GSR4_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_3_MASK)
29913 #define DDRPHY_DX5GSR4_RESERVED_4_MASK           (0x10U)
29914 #define DDRPHY_DX5GSR4_RESERVED_4_SHIFT          (4U)
29915 /*! RESERVED_4 - Reserved. Return zeroes on reads.
29916  */
29917 #define DDRPHY_DX5GSR4_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_4_MASK)
29918 #define DDRPHY_DX5GSR4_RESERVED_5_MASK           (0x20U)
29919 #define DDRPHY_DX5GSR4_RESERVED_5_SHIFT          (5U)
29920 /*! RESERVED_5 - Reserved. Return zeroes on reads.
29921  */
29922 #define DDRPHY_DX5GSR4_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_5_MASK)
29923 #define DDRPHY_DX5GSR4_RESERVED_6_MASK           (0x40U)
29924 #define DDRPHY_DX5GSR4_RESERVED_6_SHIFT          (6U)
29925 /*! RESERVED_6 - Reserved. Return zeroes on reads.
29926  */
29927 #define DDRPHY_DX5GSR4_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_6_MASK)
29928 #define DDRPHY_DX5GSR4_RESERVED_15_7_MASK        (0xFF80U)
29929 #define DDRPHY_DX5GSR4_RESERVED_15_7_SHIFT       (7U)
29930 /*! RESERVED_15_7 - Reserved. Return zeroes on reads.
29931  */
29932 #define DDRPHY_DX5GSR4_RESERVED_15_7(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_15_7_MASK)
29933 #define DDRPHY_DX5GSR4_RESERVED_16_MASK          (0x10000U)
29934 #define DDRPHY_DX5GSR4_RESERVED_16_SHIFT         (16U)
29935 /*! RESERVED_16 - Reserved. Return zeroes on reads.
29936  */
29937 #define DDRPHY_DX5GSR4_RESERVED_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_16_MASK)
29938 #define DDRPHY_DX5GSR4_RESERVED_25_17_MASK       (0x3FE0000U)
29939 #define DDRPHY_DX5GSR4_RESERVED_25_17_SHIFT      (17U)
29940 /*! RESERVED_25_17 - Reserved. Return zeroes on reads.
29941  */
29942 #define DDRPHY_DX5GSR4_RESERVED_25_17(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_25_17_MASK)
29943 #define DDRPHY_DX5GSR4_RESERVED_31_26_MASK       (0xFC000000U)
29944 #define DDRPHY_DX5GSR4_RESERVED_31_26_SHIFT      (26U)
29945 /*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
29946  */
29947 #define DDRPHY_DX5GSR4_RESERVED_31_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_31_26_MASK)
29948 /*! @} */
29949 
29950 /*! @name DX5GSR5 - DATX8 n General Status Register 5 */
29951 /*! @{ */
29952 #define DDRPHY_DX5GSR5_RESERVED_0_MASK           (0x1U)
29953 #define DDRPHY_DX5GSR5_RESERVED_0_SHIFT          (0U)
29954 /*! RESERVED_0 - Reserved. Return zeroes on reads.
29955  */
29956 #define DDRPHY_DX5GSR5_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_0_MASK)
29957 #define DDRPHY_DX5GSR5_RESERVED_1_MASK           (0x2U)
29958 #define DDRPHY_DX5GSR5_RESERVED_1_SHIFT          (1U)
29959 /*! RESERVED_1 - Reserved. Return zeroes on reads.
29960  */
29961 #define DDRPHY_DX5GSR5_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_1_MASK)
29962 #define DDRPHY_DX5GSR5_RESERVED_2_MASK           (0x4U)
29963 #define DDRPHY_DX5GSR5_RESERVED_2_SHIFT          (2U)
29964 /*! RESERVED_2 - Reserved. Return zeroes on reads.
29965  */
29966 #define DDRPHY_DX5GSR5_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_2_MASK)
29967 #define DDRPHY_DX5GSR5_RESERVED_3_MASK           (0x8U)
29968 #define DDRPHY_DX5GSR5_RESERVED_3_SHIFT          (3U)
29969 /*! RESERVED_3 - Reserved. Return zeroes on reads.
29970  */
29971 #define DDRPHY_DX5GSR5_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_3_MASK)
29972 #define DDRPHY_DX5GSR5_RESERVED_4_MASK           (0x10U)
29973 #define DDRPHY_DX5GSR5_RESERVED_4_SHIFT          (4U)
29974 /*! RESERVED_4 - Reserved. Return zeroes on reads.
29975  */
29976 #define DDRPHY_DX5GSR5_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_4_MASK)
29977 #define DDRPHY_DX5GSR5_RESERVED_5_MASK           (0x20U)
29978 #define DDRPHY_DX5GSR5_RESERVED_5_SHIFT          (5U)
29979 /*! RESERVED_5 - Reserved. Return zeroes on reads.
29980  */
29981 #define DDRPHY_DX5GSR5_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_5_MASK)
29982 #define DDRPHY_DX5GSR5_RESERVED_6_MASK           (0x40U)
29983 #define DDRPHY_DX5GSR5_RESERVED_6_SHIFT          (6U)
29984 /*! RESERVED_6 - Reserved. Return zeroes on reads.
29985  */
29986 #define DDRPHY_DX5GSR5_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_6_MASK)
29987 #define DDRPHY_DX5GSR5_RESERVED_7_MASK           (0x80U)
29988 #define DDRPHY_DX5GSR5_RESERVED_7_SHIFT          (7U)
29989 /*! RESERVED_7 - Reserved. Return zeroes on reads.
29990  */
29991 #define DDRPHY_DX5GSR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_7_MASK)
29992 #define DDRPHY_DX5GSR5_RESERVED_11_8_MASK        (0xF00U)
29993 #define DDRPHY_DX5GSR5_RESERVED_11_8_SHIFT       (8U)
29994 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
29995  */
29996 #define DDRPHY_DX5GSR5_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_11_8_MASK)
29997 #define DDRPHY_DX5GSR5_RESERVED_19_12_MASK       (0xFF000U)
29998 #define DDRPHY_DX5GSR5_RESERVED_19_12_SHIFT      (12U)
29999 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
30000  */
30001 #define DDRPHY_DX5GSR5_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_19_12_MASK)
30002 #define DDRPHY_DX5GSR5_RESERVED_20_MASK          (0x100000U)
30003 #define DDRPHY_DX5GSR5_RESERVED_20_SHIFT         (20U)
30004 /*! RESERVED_20 - Reserved. Return zeroes on reads.
30005  */
30006 #define DDRPHY_DX5GSR5_RESERVED_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_20_MASK)
30007 #define DDRPHY_DX5GSR5_RESERVED_21_MASK          (0x200000U)
30008 #define DDRPHY_DX5GSR5_RESERVED_21_SHIFT         (21U)
30009 /*! RESERVED_21 - Reserved. Return zeroes on reads.
30010  */
30011 #define DDRPHY_DX5GSR5_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_21_MASK)
30012 #define DDRPHY_DX5GSR5_RESERVED_22_MASK          (0x400000U)
30013 #define DDRPHY_DX5GSR5_RESERVED_22_SHIFT         (22U)
30014 /*! RESERVED_22 - Reserved. Return zeroes on reads.
30015  */
30016 #define DDRPHY_DX5GSR5_RESERVED_22(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_22_MASK)
30017 #define DDRPHY_DX5GSR5_RESERVED_31_23_MASK       (0xFF800000U)
30018 #define DDRPHY_DX5GSR5_RESERVED_31_23_SHIFT      (23U)
30019 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
30020  */
30021 #define DDRPHY_DX5GSR5_RESERVED_31_23(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_31_23_MASK)
30022 /*! @} */
30023 
30024 /*! @name DX5GSR6 - DATX8 n General Status Register 6 */
30025 /*! @{ */
30026 #define DDRPHY_DX5GSR6_RESERVED_1_0_MASK         (0x3U)
30027 #define DDRPHY_DX5GSR6_RESERVED_1_0_SHIFT        (0U)
30028 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
30029  */
30030 #define DDRPHY_DX5GSR6_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_1_0_MASK)
30031 #define DDRPHY_DX5GSR6_RESERVED_3_2_MASK         (0xCU)
30032 #define DDRPHY_DX5GSR6_RESERVED_3_2_SHIFT        (2U)
30033 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
30034  */
30035 #define DDRPHY_DX5GSR6_RESERVED_3_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_3_2_MASK)
30036 #define DDRPHY_DX5GSR6_RESERVED_7_4_MASK         (0xF0U)
30037 #define DDRPHY_DX5GSR6_RESERVED_7_4_SHIFT        (4U)
30038 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
30039  */
30040 #define DDRPHY_DX5GSR6_RESERVED_7_4(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_7_4_MASK)
30041 #define DDRPHY_DX5GSR6_RESERVED_11_8_MASK        (0xF00U)
30042 #define DDRPHY_DX5GSR6_RESERVED_11_8_SHIFT       (8U)
30043 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
30044  */
30045 #define DDRPHY_DX5GSR6_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_11_8_MASK)
30046 #define DDRPHY_DX5GSR6_RESERVED_15_12_MASK       (0xF000U)
30047 #define DDRPHY_DX5GSR6_RESERVED_15_12_SHIFT      (12U)
30048 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
30049  */
30050 #define DDRPHY_DX5GSR6_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_15_12_MASK)
30051 #define DDRPHY_DX5GSR6_RESERVED_19_15_MASK       (0xF0000U)
30052 #define DDRPHY_DX5GSR6_RESERVED_19_15_SHIFT      (16U)
30053 /*! RESERVED_19_15 - Reserved. Return zeroes on reads.
30054  */
30055 #define DDRPHY_DX5GSR6_RESERVED_19_15(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_19_15_MASK)
30056 #define DDRPHY_DX5GSR6_RESERVED_23_20_MASK       (0xF00000U)
30057 #define DDRPHY_DX5GSR6_RESERVED_23_20_SHIFT      (20U)
30058 /*! RESERVED_23_20 - Reserved. Return zeroes on reads.
30059  */
30060 #define DDRPHY_DX5GSR6_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_23_20_MASK)
30061 #define DDRPHY_DX5GSR6_RESERVED_31_24_MASK       (0xFF000000U)
30062 #define DDRPHY_DX5GSR6_RESERVED_31_24_SHIFT      (24U)
30063 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
30064  */
30065 #define DDRPHY_DX5GSR6_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_31_24_MASK)
30066 /*! @} */
30067 
30068 /*! @name DX6GCR0 - DATX8 n General Configuration Register 0 */
30069 /*! @{ */
30070 #define DDRPHY_DX6GCR0_RESERVED_1_0_MASK         (0x3U)
30071 #define DDRPHY_DX6GCR0_RESERVED_1_0_SHIFT        (0U)
30072 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
30073  */
30074 #define DDRPHY_DX6GCR0_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX6GCR0_RESERVED_1_0_MASK)
30075 #define DDRPHY_DX6GCR0_DQSGOE_MASK               (0x4U)
30076 #define DDRPHY_DX6GCR0_DQSGOE_SHIFT              (2U)
30077 /*! DQSGOE - DQSG Output Enable
30078  */
30079 #define DDRPHY_DX6GCR0_DQSGOE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSGOE_SHIFT)) & DDRPHY_DX6GCR0_DQSGOE_MASK)
30080 #define DDRPHY_DX6GCR0_DQSGODT_MASK              (0x8U)
30081 #define DDRPHY_DX6GCR0_DQSGODT_SHIFT             (3U)
30082 /*! DQSGODT - DQSG On-Die Termination
30083  */
30084 #define DDRPHY_DX6GCR0_DQSGODT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSGODT_SHIFT)) & DDRPHY_DX6GCR0_DQSGODT_MASK)
30085 #define DDRPHY_DX6GCR0_RESERVED_4_MASK           (0x10U)
30086 #define DDRPHY_DX6GCR0_RESERVED_4_SHIFT          (4U)
30087 /*! RESERVED_4 - Reserved. Return zeroes on reads.
30088  */
30089 #define DDRPHY_DX6GCR0_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX6GCR0_RESERVED_4_MASK)
30090 #define DDRPHY_DX6GCR0_DQSGPDR_MASK              (0x20U)
30091 #define DDRPHY_DX6GCR0_DQSGPDR_SHIFT             (5U)
30092 /*! DQSGPDR - DQSG Power Down Receiver
30093  */
30094 #define DDRPHY_DX6GCR0_DQSGPDR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX6GCR0_DQSGPDR_MASK)
30095 #define DDRPHY_DX6GCR0_DQSRPD_MASK               (0x40U)
30096 #define DDRPHY_DX6GCR0_DQSRPD_SHIFT              (6U)
30097 /*! DQSRPD - DQSR Power Down
30098  */
30099 #define DDRPHY_DX6GCR0_DQSRPD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSRPD_SHIFT)) & DDRPHY_DX6GCR0_DQSRPD_MASK)
30100 #define DDRPHY_DX6GCR0_CPDRSHFT_MASK             (0x180U)
30101 #define DDRPHY_DX6GCR0_CPDRSHFT_SHIFT            (7U)
30102 /*! CPDRSHFT - Configurable PDR Phase Shift
30103  */
30104 #define DDRPHY_DX6GCR0_CPDRSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX6GCR0_CPDRSHFT_MASK)
30105 #define DDRPHY_DX6GCR0_RTTOH_MASK                (0x600U)
30106 #define DDRPHY_DX6GCR0_RTTOH_SHIFT               (9U)
30107 /*! RTTOH - RTT Output Hold
30108  */
30109 #define DDRPHY_DX6GCR0_RTTOH(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RTTOH_SHIFT)) & DDRPHY_DX6GCR0_RTTOH_MASK)
30110 #define DDRPHY_DX6GCR0_RTTOAL_MASK               (0x800U)
30111 #define DDRPHY_DX6GCR0_RTTOAL_SHIFT              (11U)
30112 /*! RTTOAL - RTT On Additive Latency
30113  */
30114 #define DDRPHY_DX6GCR0_RTTOAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RTTOAL_SHIFT)) & DDRPHY_DX6GCR0_RTTOAL_MASK)
30115 #define DDRPHY_DX6GCR0_DQSSEPDR_MASK             (0x1000U)
30116 #define DDRPHY_DX6GCR0_DQSSEPDR_SHIFT            (12U)
30117 /*! DQSSEPDR - DQSSE Power Down Receiver
30118  */
30119 #define DDRPHY_DX6GCR0_DQSSEPDR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX6GCR0_DQSSEPDR_MASK)
30120 #define DDRPHY_DX6GCR0_DQSNSEPDR_MASK            (0x2000U)
30121 #define DDRPHY_DX6GCR0_DQSNSEPDR_SHIFT           (13U)
30122 /*! DQSNSEPDR - DQSNSE Power Down Receiver
30123  */
30124 #define DDRPHY_DX6GCR0_DQSNSEPDR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX6GCR0_DQSNSEPDR_MASK)
30125 #define DDRPHY_DX6GCR0_RESERVED_19_14_MASK       (0xFC000U)
30126 #define DDRPHY_DX6GCR0_RESERVED_19_14_SHIFT      (14U)
30127 /*! RESERVED_19_14 - Reserved. Return zeroes on reads.
30128  */
30129 #define DDRPHY_DX6GCR0_RESERVED_19_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX6GCR0_RESERVED_19_14_MASK)
30130 #define DDRPHY_DX6GCR0_RDDLY_MASK                (0xF00000U)
30131 #define DDRPHY_DX6GCR0_RDDLY_SHIFT               (20U)
30132 /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
30133  */
30134 #define DDRPHY_DX6GCR0_RDDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RDDLY_SHIFT)) & DDRPHY_DX6GCR0_RDDLY_MASK)
30135 #define DDRPHY_DX6GCR0_DQSDCC_MASK               (0xF000000U)
30136 #define DDRPHY_DX6GCR0_DQSDCC_SHIFT              (24U)
30137 /*! DQSDCC - DQS Duty Cycle Correction
30138  */
30139 #define DDRPHY_DX6GCR0_DQSDCC(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSDCC_SHIFT)) & DDRPHY_DX6GCR0_DQSDCC_MASK)
30140 #define DDRPHY_DX6GCR0_CODTSHFT_MASK             (0x30000000U)
30141 #define DDRPHY_DX6GCR0_CODTSHFT_SHIFT            (28U)
30142 /*! CODTSHFT - Configurable ODT(TE) Phase Shift
30143  */
30144 #define DDRPHY_DX6GCR0_CODTSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX6GCR0_CODTSHFT_MASK)
30145 #define DDRPHY_DX6GCR0_MDLEN_MASK                (0x40000000U)
30146 #define DDRPHY_DX6GCR0_MDLEN_SHIFT               (30U)
30147 /*! MDLEN - Master Delay Line Enable
30148  */
30149 #define DDRPHY_DX6GCR0_MDLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_MDLEN_SHIFT)) & DDRPHY_DX6GCR0_MDLEN_MASK)
30150 #define DDRPHY_DX6GCR0_CALBYP_MASK               (0x80000000U)
30151 #define DDRPHY_DX6GCR0_CALBYP_SHIFT              (31U)
30152 /*! CALBYP - Calibration Bypass
30153  */
30154 #define DDRPHY_DX6GCR0_CALBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_CALBYP_SHIFT)) & DDRPHY_DX6GCR0_CALBYP_MASK)
30155 /*! @} */
30156 
30157 /*! @name DX6GCR1 - DATX8 n General Configuration Register 1 */
30158 /*! @{ */
30159 #define DDRPHY_DX6GCR1_DQEN_MASK                 (0xFFU)
30160 #define DDRPHY_DX6GCR1_DQEN_SHIFT                (0U)
30161 /*! DQEN - Enables DQ corresponding to each bit in a byte
30162  */
30163 #define DDRPHY_DX6GCR1_DQEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DQEN_SHIFT)) & DDRPHY_DX6GCR1_DQEN_MASK)
30164 #define DDRPHY_DX6GCR1_DMEN_MASK                 (0x100U)
30165 #define DDRPHY_DX6GCR1_DMEN_SHIFT                (8U)
30166 /*! DMEN - Enables DM pin in a byte lane
30167  */
30168 #define DDRPHY_DX6GCR1_DMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DMEN_SHIFT)) & DDRPHY_DX6GCR1_DMEN_MASK)
30169 #define DDRPHY_DX6GCR1_DSEN_MASK                 (0x200U)
30170 #define DDRPHY_DX6GCR1_DSEN_SHIFT                (9U)
30171 /*! DSEN - Enables Write Data strobe in a byte lane
30172  */
30173 #define DDRPHY_DX6GCR1_DSEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DSEN_SHIFT)) & DDRPHY_DX6GCR1_DSEN_MASK)
30174 #define DDRPHY_DX6GCR1_TEEN_MASK                 (0x400U)
30175 #define DDRPHY_DX6GCR1_TEEN_SHIFT                (10U)
30176 /*! TEEN - Enables ODT/TE in a byte lane
30177  */
30178 #define DDRPHY_DX6GCR1_TEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_TEEN_SHIFT)) & DDRPHY_DX6GCR1_TEEN_MASK)
30179 #define DDRPHY_DX6GCR1_PDREN_MASK                (0x800U)
30180 #define DDRPHY_DX6GCR1_PDREN_SHIFT               (11U)
30181 /*! PDREN - Enables PDR in a byte lane
30182  */
30183 #define DDRPHY_DX6GCR1_PDREN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_PDREN_SHIFT)) & DDRPHY_DX6GCR1_PDREN_MASK)
30184 #define DDRPHY_DX6GCR1_OEEN_MASK                 (0x1000U)
30185 #define DDRPHY_DX6GCR1_OEEN_SHIFT                (12U)
30186 /*! OEEN - Enables Read Data Strobe in a byte lane
30187  */
30188 #define DDRPHY_DX6GCR1_OEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_OEEN_SHIFT)) & DDRPHY_DX6GCR1_OEEN_MASK)
30189 #define DDRPHY_DX6GCR1_QSSEL_MASK                (0x2000U)
30190 #define DDRPHY_DX6GCR1_QSSEL_SHIFT               (13U)
30191 /*! QSSEL - Select the delayed or non-delayed read data strobe
30192  */
30193 #define DDRPHY_DX6GCR1_QSSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_QSSEL_SHIFT)) & DDRPHY_DX6GCR1_QSSEL_MASK)
30194 #define DDRPHY_DX6GCR1_QSNSEL_MASK               (0x4000U)
30195 #define DDRPHY_DX6GCR1_QSNSEL_SHIFT              (14U)
30196 /*! QSNSEL - Select the delayed or non-delayed read data strobe #
30197  */
30198 #define DDRPHY_DX6GCR1_QSNSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_QSNSEL_SHIFT)) & DDRPHY_DX6GCR1_QSNSEL_MASK)
30199 #define DDRPHY_DX6GCR1_RESERVED_15_MASK          (0x8000U)
30200 #define DDRPHY_DX6GCR1_RESERVED_15_SHIFT         (15U)
30201 /*! RESERVED_15 - Reserved. Returns zeroes on reads.
30202  */
30203 #define DDRPHY_DX6GCR1_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX6GCR1_RESERVED_15_MASK)
30204 #define DDRPHY_DX6GCR1_DXPDRMODE_MASK            (0xFFFF0000U)
30205 #define DDRPHY_DX6GCR1_DXPDRMODE_SHIFT           (16U)
30206 /*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
30207  */
30208 #define DDRPHY_DX6GCR1_DXPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX6GCR1_DXPDRMODE_MASK)
30209 /*! @} */
30210 
30211 /*! @name DX6GCR2 - DATX8 n General Configuration Register 2 */
30212 /*! @{ */
30213 #define DDRPHY_DX6GCR2_DXTEMODE_MASK             (0xFFFFU)
30214 #define DDRPHY_DX6GCR2_DXTEMODE_SHIFT            (0U)
30215 /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
30216  */
30217 #define DDRPHY_DX6GCR2_DXTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX6GCR2_DXTEMODE_MASK)
30218 #define DDRPHY_DX6GCR2_DXOEMODE_MASK             (0xFFFF0000U)
30219 #define DDRPHY_DX6GCR2_DXOEMODE_SHIFT            (16U)
30220 /*! DXOEMODE - Enables the OE mode values for DQ[7:0]
30221  */
30222 #define DDRPHY_DX6GCR2_DXOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX6GCR2_DXOEMODE_MASK)
30223 /*! @} */
30224 
30225 /*! @name DX6GCR3 - DATX8 n General Configuration Register 3 */
30226 /*! @{ */
30227 #define DDRPHY_DX6GCR3_WDMBVT_MASK               (0x1U)
30228 #define DDRPHY_DX6GCR3_WDMBVT_SHIFT              (0U)
30229 /*! WDMBVT - Write Data Mask BDL VT Compensation
30230  */
30231 #define DDRPHY_DX6GCR3_WDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDMBVT_SHIFT)) & DDRPHY_DX6GCR3_WDMBVT_MASK)
30232 #define DDRPHY_DX6GCR3_RDMBVT_MASK               (0x2U)
30233 #define DDRPHY_DX6GCR3_RDMBVT_SHIFT              (1U)
30234 /*! RDMBVT - Read Data Mask BDL VT Compensation
30235  */
30236 #define DDRPHY_DX6GCR3_RDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RDMBVT_SHIFT)) & DDRPHY_DX6GCR3_RDMBVT_MASK)
30237 #define DDRPHY_DX6GCR3_DSPDRMODE_MASK            (0xCU)
30238 #define DDRPHY_DX6GCR3_DSPDRMODE_SHIFT           (2U)
30239 /*! DSPDRMODE - Enables the PDR mode values for DQS.
30240  */
30241 #define DDRPHY_DX6GCR3_DSPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX6GCR3_DSPDRMODE_MASK)
30242 #define DDRPHY_DX6GCR3_DSTEMODE_MASK             (0x30U)
30243 #define DDRPHY_DX6GCR3_DSTEMODE_SHIFT            (4U)
30244 /*! DSTEMODE - Enables the TE mode values for DQS.
30245  */
30246 #define DDRPHY_DX6GCR3_DSTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSTEMODE_MASK)
30247 #define DDRPHY_DX6GCR3_DSOEMODE_MASK             (0xC0U)
30248 #define DDRPHY_DX6GCR3_DSOEMODE_SHIFT            (6U)
30249 /*! DSOEMODE - Enables the OE mode values for DQS.
30250  */
30251 #define DDRPHY_DX6GCR3_DSOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSOEMODE_MASK)
30252 #define DDRPHY_DX6GCR3_WDSBVT_MASK               (0x100U)
30253 #define DDRPHY_DX6GCR3_WDSBVT_SHIFT              (8U)
30254 /*! WDSBVT - Write Data Strobe BDL VT Compensation
30255  */
30256 #define DDRPHY_DX6GCR3_WDSBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDSBVT_SHIFT)) & DDRPHY_DX6GCR3_WDSBVT_MASK)
30257 #define DDRPHY_DX6GCR3_RESERVED_9_MASK           (0x200U)
30258 #define DDRPHY_DX6GCR3_RESERVED_9_SHIFT          (9U)
30259 /*! RESERVED_9 - Reserved. Returns zeroes on reads.
30260  */
30261 #define DDRPHY_DX6GCR3_RESERVED_9(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX6GCR3_RESERVED_9_MASK)
30262 #define DDRPHY_DX6GCR3_DMPDRMODE_MASK            (0xC00U)
30263 #define DDRPHY_DX6GCR3_DMPDRMODE_SHIFT           (10U)
30264 /*! DMPDRMODE - Enables the PDR mode values for DM.
30265  */
30266 #define DDRPHY_DX6GCR3_DMPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX6GCR3_DMPDRMODE_MASK)
30267 #define DDRPHY_DX6GCR3_DMTEMODE_MASK             (0x3000U)
30268 #define DDRPHY_DX6GCR3_DMTEMODE_SHIFT            (12U)
30269 /*! DMTEMODE - Enables the TE mode values for DM.
30270  */
30271 #define DDRPHY_DX6GCR3_DMTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX6GCR3_DMTEMODE_MASK)
30272 #define DDRPHY_DX6GCR3_DMOEMODE_MASK             (0xC000U)
30273 #define DDRPHY_DX6GCR3_DMOEMODE_SHIFT            (14U)
30274 /*! DMOEMODE - Enables the OE mode values for DM.
30275  */
30276 #define DDRPHY_DX6GCR3_DMOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX6GCR3_DMOEMODE_MASK)
30277 #define DDRPHY_DX6GCR3_DSNPDRMODE_MASK           (0x30000U)
30278 #define DDRPHY_DX6GCR3_DSNPDRMODE_SHIFT          (16U)
30279 /*! DSNPDRMODE - Enables the PDR mode for DQS
30280  */
30281 #define DDRPHY_DX6GCR3_DSNPDRMODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX6GCR3_DSNPDRMODE_MASK)
30282 #define DDRPHY_DX6GCR3_DSNTEMODE_MASK            (0xC0000U)
30283 #define DDRPHY_DX6GCR3_DSNTEMODE_SHIFT           (18U)
30284 /*! DSNTEMODE - Enables the TE mode for DQS
30285  */
30286 #define DDRPHY_DX6GCR3_DSNTEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSNTEMODE_MASK)
30287 #define DDRPHY_DX6GCR3_DSNOEMODE_MASK            (0x300000U)
30288 #define DDRPHY_DX6GCR3_DSNOEMODE_SHIFT           (20U)
30289 /*! DSNOEMODE - Enables the OE mode for DQs
30290  */
30291 #define DDRPHY_DX6GCR3_DSNOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSNOEMODE_MASK)
30292 #define DDRPHY_DX6GCR3_PDRBVT_MASK               (0x400000U)
30293 #define DDRPHY_DX6GCR3_PDRBVT_SHIFT              (22U)
30294 /*! PDRBVT - Power Down Receiver BDL VT Compensation
30295  */
30296 #define DDRPHY_DX6GCR3_PDRBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_PDRBVT_SHIFT)) & DDRPHY_DX6GCR3_PDRBVT_MASK)
30297 #define DDRPHY_DX6GCR3_RGSLVT_MASK               (0x800000U)
30298 #define DDRPHY_DX6GCR3_RGSLVT_SHIFT              (23U)
30299 /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
30300  */
30301 #define DDRPHY_DX6GCR3_RGSLVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RGSLVT_SHIFT)) & DDRPHY_DX6GCR3_RGSLVT_MASK)
30302 #define DDRPHY_DX6GCR3_WLLVT_MASK                (0x1000000U)
30303 #define DDRPHY_DX6GCR3_WLLVT_SHIFT               (24U)
30304 /*! WLLVT - Write Leveling LCDL Delay VT Compensation
30305  */
30306 #define DDRPHY_DX6GCR3_WLLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WLLVT_SHIFT)) & DDRPHY_DX6GCR3_WLLVT_MASK)
30307 #define DDRPHY_DX6GCR3_WDLVT_MASK                (0x2000000U)
30308 #define DDRPHY_DX6GCR3_WDLVT_SHIFT               (25U)
30309 /*! WDLVT - Write DQ LCDL Delay VT Compensation
30310  */
30311 #define DDRPHY_DX6GCR3_WDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDLVT_SHIFT)) & DDRPHY_DX6GCR3_WDLVT_MASK)
30312 #define DDRPHY_DX6GCR3_RDLVT_MASK                (0x4000000U)
30313 #define DDRPHY_DX6GCR3_RDLVT_SHIFT               (26U)
30314 /*! RDLVT - Read DQS LCDL Delay VT Compensation
30315  */
30316 #define DDRPHY_DX6GCR3_RDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RDLVT_SHIFT)) & DDRPHY_DX6GCR3_RDLVT_MASK)
30317 #define DDRPHY_DX6GCR3_RGLVT_MASK                (0x8000000U)
30318 #define DDRPHY_DX6GCR3_RGLVT_SHIFT               (27U)
30319 /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
30320  */
30321 #define DDRPHY_DX6GCR3_RGLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RGLVT_SHIFT)) & DDRPHY_DX6GCR3_RGLVT_MASK)
30322 #define DDRPHY_DX6GCR3_WDBVT_MASK                (0x10000000U)
30323 #define DDRPHY_DX6GCR3_WDBVT_SHIFT               (28U)
30324 /*! WDBVT - Write Data BDL VT Compensation
30325  */
30326 #define DDRPHY_DX6GCR3_WDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDBVT_SHIFT)) & DDRPHY_DX6GCR3_WDBVT_MASK)
30327 #define DDRPHY_DX6GCR3_RDBVT_MASK                (0x20000000U)
30328 #define DDRPHY_DX6GCR3_RDBVT_SHIFT               (29U)
30329 /*! RDBVT - Read Data BDL VT Compensation
30330  */
30331 #define DDRPHY_DX6GCR3_RDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RDBVT_SHIFT)) & DDRPHY_DX6GCR3_RDBVT_MASK)
30332 #define DDRPHY_DX6GCR3_TEBVT_MASK                (0x40000000U)
30333 #define DDRPHY_DX6GCR3_TEBVT_SHIFT               (30U)
30334 /*! TEBVT - Termination Enable BDL VT Compensation
30335  */
30336 #define DDRPHY_DX6GCR3_TEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_TEBVT_SHIFT)) & DDRPHY_DX6GCR3_TEBVT_MASK)
30337 #define DDRPHY_DX6GCR3_OEBVT_MASK                (0x80000000U)
30338 #define DDRPHY_DX6GCR3_OEBVT_SHIFT               (31U)
30339 /*! OEBVT - Output Enable BDL VT Compensation
30340  */
30341 #define DDRPHY_DX6GCR3_OEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_OEBVT_SHIFT)) & DDRPHY_DX6GCR3_OEBVT_MASK)
30342 /*! @} */
30343 
30344 /*! @name DX6GCR4 - DATX8 n General Configuration Register 4 */
30345 /*! @{ */
30346 #define DDRPHY_DX6GCR4_DXREFIMON_MASK            (0x3U)
30347 #define DDRPHY_DX6GCR4_DXREFIMON_SHIFT           (0U)
30348 /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
30349  */
30350 #define DDRPHY_DX6GCR4_DXREFIMON(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX6GCR4_DXREFIMON_MASK)
30351 #define DDRPHY_DX6GCR4_DXREFIEN_MASK             (0x3CU)
30352 #define DDRPHY_DX6GCR4_DXREFIEN_SHIFT            (2U)
30353 /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
30354  */
30355 #define DDRPHY_DX6GCR4_DXREFIEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFIEN_MASK)
30356 #define DDRPHY_DX6GCR4_RESERVED_7_6_MASK         (0xC0U)
30357 #define DDRPHY_DX6GCR4_RESERVED_7_6_SHIFT        (6U)
30358 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
30359  */
30360 #define DDRPHY_DX6GCR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR4_RESERVED_7_6_MASK)
30361 #define DDRPHY_DX6GCR4_DXREFSSEL_MASK            (0x7F00U)
30362 #define DDRPHY_DX6GCR4_DXREFSSEL_SHIFT           (8U)
30363 /*! DXREFSSEL - Byte Lane Single-End VREF Select
30364  */
30365 #define DDRPHY_DX6GCR4_DXREFSSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX6GCR4_DXREFSSEL_MASK)
30366 #define DDRPHY_DX6GCR4_DXREFSSELRANGE_MASK       (0x8000U)
30367 #define DDRPHY_DX6GCR4_DXREFSSELRANGE_SHIFT      (15U)
30368 /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
30369  */
30370 #define DDRPHY_DX6GCR4_DXREFSSELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX6GCR4_DXREFSSELRANGE_MASK)
30371 #define DDRPHY_DX6GCR4_DXREFESEL_MASK            (0x7F0000U)
30372 #define DDRPHY_DX6GCR4_DXREFESEL_SHIFT           (16U)
30373 /*! DXREFESEL - Byte Lane External VREF Select
30374  */
30375 #define DDRPHY_DX6GCR4_DXREFESEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX6GCR4_DXREFESEL_MASK)
30376 #define DDRPHY_DX6GCR4_DXREFESELRANGE_MASK       (0x800000U)
30377 #define DDRPHY_DX6GCR4_DXREFESELRANGE_SHIFT      (23U)
30378 /*! DXREFESELRANGE - External VREF generator REFSEL range select
30379  */
30380 #define DDRPHY_DX6GCR4_DXREFESELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX6GCR4_DXREFESELRANGE_MASK)
30381 #define DDRPHY_DX6GCR4_RESERVED_24_MASK          (0x1000000U)
30382 #define DDRPHY_DX6GCR4_RESERVED_24_SHIFT         (24U)
30383 /*! RESERVED_24 - Reserved. Returns zeros on reads.
30384  */
30385 #define DDRPHY_DX6GCR4_RESERVED_24(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX6GCR4_RESERVED_24_MASK)
30386 #define DDRPHY_DX6GCR4_DXREFSEN_MASK             (0x2000000U)
30387 #define DDRPHY_DX6GCR4_DXREFSEN_SHIFT            (25U)
30388 /*! DXREFSEN - Byte Lane Single-End VREF Enable
30389  */
30390 #define DDRPHY_DX6GCR4_DXREFSEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFSEN_MASK)
30391 #define DDRPHY_DX6GCR4_DXREFEEN_MASK             (0xC000000U)
30392 #define DDRPHY_DX6GCR4_DXREFEEN_SHIFT            (26U)
30393 /*! DXREFEEN - Byte Lane Internal VREF Enable
30394  */
30395 #define DDRPHY_DX6GCR4_DXREFEEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFEEN_MASK)
30396 #define DDRPHY_DX6GCR4_DXREFPEN_MASK             (0x10000000U)
30397 #define DDRPHY_DX6GCR4_DXREFPEN_SHIFT            (28U)
30398 /*! DXREFPEN - Byte Lane VREF Pad Enable
30399  */
30400 #define DDRPHY_DX6GCR4_DXREFPEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFPEN_MASK)
30401 #define DDRPHY_DX6GCR4_RESERVED_31_29_MASK       (0xE0000000U)
30402 #define DDRPHY_DX6GCR4_RESERVED_31_29_SHIFT      (29U)
30403 /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
30404  */
30405 #define DDRPHY_DX6GCR4_RESERVED_31_29(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX6GCR4_RESERVED_31_29_MASK)
30406 /*! @} */
30407 
30408 /*! @name DX6GCR5 - DATX8 n General Configuration Register 5 */
30409 /*! @{ */
30410 #define DDRPHY_DX6GCR5_DXREFISELR0_MASK          (0x7FU)
30411 #define DDRPHY_DX6GCR5_DXREFISELR0_SHIFT         (0U)
30412 /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
30413  */
30414 #define DDRPHY_DX6GCR5_DXREFISELR0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR0_MASK)
30415 #define DDRPHY_DX6GCR5_RESERVED_7_MASK           (0x80U)
30416 #define DDRPHY_DX6GCR5_RESERVED_7_SHIFT          (7U)
30417 /*! RESERVED_7 - Reserved. Returns zeros on reads.
30418  */
30419 #define DDRPHY_DX6GCR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_7_MASK)
30420 #define DDRPHY_DX6GCR5_DXREFISELR1_MASK          (0x7F00U)
30421 #define DDRPHY_DX6GCR5_DXREFISELR1_SHIFT         (8U)
30422 /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
30423  */
30424 #define DDRPHY_DX6GCR5_DXREFISELR1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR1_MASK)
30425 #define DDRPHY_DX6GCR5_RESERVED_15_MASK          (0x8000U)
30426 #define DDRPHY_DX6GCR5_RESERVED_15_SHIFT         (15U)
30427 /*! RESERVED_15 - Reserved. Returns zeros on reads.
30428  */
30429 #define DDRPHY_DX6GCR5_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_15_MASK)
30430 #define DDRPHY_DX6GCR5_DXREFISELR2_MASK          (0x7F0000U)
30431 #define DDRPHY_DX6GCR5_DXREFISELR2_SHIFT         (16U)
30432 /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
30433  */
30434 #define DDRPHY_DX6GCR5_DXREFISELR2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR2_MASK)
30435 #define DDRPHY_DX6GCR5_RESERVED_23_MASK          (0x800000U)
30436 #define DDRPHY_DX6GCR5_RESERVED_23_SHIFT         (23U)
30437 /*! RESERVED_23 - Reserved. Returns zeros on reads.
30438  */
30439 #define DDRPHY_DX6GCR5_RESERVED_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_23_MASK)
30440 #define DDRPHY_DX6GCR5_DXREFISELR3_MASK          (0x7F000000U)
30441 #define DDRPHY_DX6GCR5_DXREFISELR3_SHIFT         (24U)
30442 /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
30443  */
30444 #define DDRPHY_DX6GCR5_DXREFISELR3(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR3_MASK)
30445 #define DDRPHY_DX6GCR5_RESERVED_31_MASK          (0x80000000U)
30446 #define DDRPHY_DX6GCR5_RESERVED_31_SHIFT         (31U)
30447 /*! RESERVED_31 - Reserved. Returns zeros on reads.
30448  */
30449 #define DDRPHY_DX6GCR5_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_31_MASK)
30450 /*! @} */
30451 
30452 /*! @name DX6GCR6 - DATX8 n General Configuration Register 6 */
30453 /*! @{ */
30454 #define DDRPHY_DX6GCR6_DXDQVREFR0_MASK           (0x3FU)
30455 #define DDRPHY_DX6GCR6_DXDQVREFR0_SHIFT          (0U)
30456 /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
30457  */
30458 #define DDRPHY_DX6GCR6_DXDQVREFR0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR0_MASK)
30459 #define DDRPHY_DX6GCR6_RESERVED_7_6_MASK         (0xC0U)
30460 #define DDRPHY_DX6GCR6_RESERVED_7_6_SHIFT        (6U)
30461 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
30462  */
30463 #define DDRPHY_DX6GCR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_7_6_MASK)
30464 #define DDRPHY_DX6GCR6_DXDQVREFR1_MASK           (0x3F00U)
30465 #define DDRPHY_DX6GCR6_DXDQVREFR1_SHIFT          (8U)
30466 /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
30467  */
30468 #define DDRPHY_DX6GCR6_DXDQVREFR1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR1_MASK)
30469 #define DDRPHY_DX6GCR6_RESERVED_15_14_MASK       (0xC000U)
30470 #define DDRPHY_DX6GCR6_RESERVED_15_14_SHIFT      (14U)
30471 /*! RESERVED_15_14 - Reserved. Returns zeros on reads.
30472  */
30473 #define DDRPHY_DX6GCR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_15_14_MASK)
30474 #define DDRPHY_DX6GCR6_DXDQVREFR2_MASK           (0x3F0000U)
30475 #define DDRPHY_DX6GCR6_DXDQVREFR2_SHIFT          (16U)
30476 /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
30477  */
30478 #define DDRPHY_DX6GCR6_DXDQVREFR2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR2_MASK)
30479 #define DDRPHY_DX6GCR6_RESERVED_23_22_MASK       (0xC00000U)
30480 #define DDRPHY_DX6GCR6_RESERVED_23_22_SHIFT      (22U)
30481 /*! RESERVED_23_22 - Reserved. Returns zeros on reads.
30482  */
30483 #define DDRPHY_DX6GCR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_23_22_MASK)
30484 #define DDRPHY_DX6GCR6_DXDQVREFR3_MASK           (0x3F000000U)
30485 #define DDRPHY_DX6GCR6_DXDQVREFR3_SHIFT          (24U)
30486 /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
30487  */
30488 #define DDRPHY_DX6GCR6_DXDQVREFR3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR3_MASK)
30489 #define DDRPHY_DX6GCR6_RESERVED_31_30_MASK       (0xC0000000U)
30490 #define DDRPHY_DX6GCR6_RESERVED_31_30_SHIFT      (30U)
30491 /*! RESERVED_31_30 - Reserved. Returns zeros on reads.
30492  */
30493 #define DDRPHY_DX6GCR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_31_30_MASK)
30494 /*! @} */
30495 
30496 /*! @name DX6GCR7 - DATX8 n General Configuration Register 7 */
30497 /*! @{ */
30498 #define DDRPHY_DX6GCR7_DCALSVAL_MASK             (0x1FFU)
30499 #define DDRPHY_DX6GCR7_DCALSVAL_SHIFT            (0U)
30500 /*! DCALSVAL - DDL Calibration Starting Value
30501  */
30502 #define DDRPHY_DX6GCR7_DCALSVAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX6GCR7_DCALSVAL_MASK)
30503 #define DDRPHY_DX6GCR7_DCALTYPE_MASK             (0x200U)
30504 #define DDRPHY_DX6GCR7_DCALTYPE_SHIFT            (9U)
30505 /*! DCALTYPE - DDL Calibration Type
30506  */
30507 #define DDRPHY_DX6GCR7_DCALTYPE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX6GCR7_DCALTYPE_MASK)
30508 #define DDRPHY_DX6GCR7_RESERVED_17_10_MASK       (0x3FC00U)
30509 #define DDRPHY_DX6GCR7_RESERVED_17_10_SHIFT      (10U)
30510 /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
30511  */
30512 #define DDRPHY_DX6GCR7_RESERVED_17_10(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX6GCR7_RESERVED_17_10_MASK)
30513 #define DDRPHY_DX6GCR7_RESERVED_18_MASK          (0x40000U)
30514 #define DDRPHY_DX6GCR7_RESERVED_18_SHIFT         (18U)
30515 /*! RESERVED_18 - Reserved. Caution, do not write to this register field.
30516  */
30517 #define DDRPHY_DX6GCR7_RESERVED_18(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX6GCR7_RESERVED_18_MASK)
30518 #define DDRPHY_DX6GCR7_RESERVED_31_19_MASK       (0xFFF80000U)
30519 #define DDRPHY_DX6GCR7_RESERVED_31_19_SHIFT      (19U)
30520 /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
30521  */
30522 #define DDRPHY_DX6GCR7_RESERVED_31_19(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX6GCR7_RESERVED_31_19_MASK)
30523 /*! @} */
30524 
30525 /*! @name DX6GCR8 - DATX8 n General Configuration Register 8 */
30526 /*! @{ */
30527 #define DDRPHY_DX6GCR8_RESERVED_5_0_MASK         (0x3FU)
30528 #define DDRPHY_DX6GCR8_RESERVED_5_0_SHIFT        (0U)
30529 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
30530  */
30531 #define DDRPHY_DX6GCR8_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_5_0_MASK)
30532 #define DDRPHY_DX6GCR8_RESERVED_7_6_MASK         (0xC0U)
30533 #define DDRPHY_DX6GCR8_RESERVED_7_6_SHIFT        (6U)
30534 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30535  */
30536 #define DDRPHY_DX6GCR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_7_6_MASK)
30537 #define DDRPHY_DX6GCR8_RESERVED_13_8_MASK        (0x3F00U)
30538 #define DDRPHY_DX6GCR8_RESERVED_13_8_SHIFT       (8U)
30539 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
30540  */
30541 #define DDRPHY_DX6GCR8_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_13_8_MASK)
30542 #define DDRPHY_DX6GCR8_RESERVED_15_14_MASK       (0xC000U)
30543 #define DDRPHY_DX6GCR8_RESERVED_15_14_SHIFT      (14U)
30544 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30545  */
30546 #define DDRPHY_DX6GCR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_15_14_MASK)
30547 #define DDRPHY_DX6GCR8_RESERVED_21_16_MASK       (0x3F0000U)
30548 #define DDRPHY_DX6GCR8_RESERVED_21_16_SHIFT      (16U)
30549 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
30550  */
30551 #define DDRPHY_DX6GCR8_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_21_16_MASK)
30552 #define DDRPHY_DX6GCR8_RESERVED_23_22_MASK       (0xC00000U)
30553 #define DDRPHY_DX6GCR8_RESERVED_23_22_SHIFT      (22U)
30554 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30555  */
30556 #define DDRPHY_DX6GCR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_23_22_MASK)
30557 #define DDRPHY_DX6GCR8_RESERVED_29_24_MASK       (0x3F000000U)
30558 #define DDRPHY_DX6GCR8_RESERVED_29_24_SHIFT      (24U)
30559 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
30560  */
30561 #define DDRPHY_DX6GCR8_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_29_24_MASK)
30562 #define DDRPHY_DX6GCR8_RESERVED_31_30_MASK       (0xC0000000U)
30563 #define DDRPHY_DX6GCR8_RESERVED_31_30_SHIFT      (30U)
30564 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30565  */
30566 #define DDRPHY_DX6GCR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_31_30_MASK)
30567 /*! @} */
30568 
30569 /*! @name DX6GCR9 - DATX8 n General Configuration Register 9 */
30570 /*! @{ */
30571 #define DDRPHY_DX6GCR9_RESERVED_5_0_MASK         (0x3FU)
30572 #define DDRPHY_DX6GCR9_RESERVED_5_0_SHIFT        (0U)
30573 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
30574  */
30575 #define DDRPHY_DX6GCR9_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_5_0_MASK)
30576 #define DDRPHY_DX6GCR9_RESERVED_7_6_MASK         (0xC0U)
30577 #define DDRPHY_DX6GCR9_RESERVED_7_6_SHIFT        (6U)
30578 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30579  */
30580 #define DDRPHY_DX6GCR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_7_6_MASK)
30581 #define DDRPHY_DX6GCR9_RESERVED_13_8_MASK        (0x3F00U)
30582 #define DDRPHY_DX6GCR9_RESERVED_13_8_SHIFT       (8U)
30583 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
30584  */
30585 #define DDRPHY_DX6GCR9_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_13_8_MASK)
30586 #define DDRPHY_DX6GCR9_RESERVED_15_14_MASK       (0xC000U)
30587 #define DDRPHY_DX6GCR9_RESERVED_15_14_SHIFT      (14U)
30588 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30589  */
30590 #define DDRPHY_DX6GCR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_15_14_MASK)
30591 #define DDRPHY_DX6GCR9_RESERVED_21_16_MASK       (0x3F0000U)
30592 #define DDRPHY_DX6GCR9_RESERVED_21_16_SHIFT      (16U)
30593 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
30594  */
30595 #define DDRPHY_DX6GCR9_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_21_16_MASK)
30596 #define DDRPHY_DX6GCR9_RESERVED_23_22_MASK       (0xC00000U)
30597 #define DDRPHY_DX6GCR9_RESERVED_23_22_SHIFT      (22U)
30598 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30599  */
30600 #define DDRPHY_DX6GCR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_23_22_MASK)
30601 #define DDRPHY_DX6GCR9_RESERVED_29_24_MASK       (0x3F000000U)
30602 #define DDRPHY_DX6GCR9_RESERVED_29_24_SHIFT      (24U)
30603 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
30604  */
30605 #define DDRPHY_DX6GCR9_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_29_24_MASK)
30606 #define DDRPHY_DX6GCR9_RESERVED_31_30_MASK       (0xC0000000U)
30607 #define DDRPHY_DX6GCR9_RESERVED_31_30_SHIFT      (30U)
30608 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30609  */
30610 #define DDRPHY_DX6GCR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_31_30_MASK)
30611 /*! @} */
30612 
30613 /*! @name DX6DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
30614 /*! @{ */
30615 #define DDRPHY_DX6DQMAP0_DQ0MAP_MASK             (0xFU)
30616 #define DDRPHY_DX6DQMAP0_DQ0MAP_SHIFT            (0U)
30617 /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
30618  */
30619 #define DDRPHY_DX6DQMAP0_DQ0MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ0MAP_MASK)
30620 #define DDRPHY_DX6DQMAP0_DQ1MAP_MASK             (0xF0U)
30621 #define DDRPHY_DX6DQMAP0_DQ1MAP_SHIFT            (4U)
30622 /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
30623  */
30624 #define DDRPHY_DX6DQMAP0_DQ1MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ1MAP_MASK)
30625 #define DDRPHY_DX6DQMAP0_DQ2MAP_MASK             (0xF00U)
30626 #define DDRPHY_DX6DQMAP0_DQ2MAP_SHIFT            (8U)
30627 /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
30628  */
30629 #define DDRPHY_DX6DQMAP0_DQ2MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ2MAP_MASK)
30630 #define DDRPHY_DX6DQMAP0_DQ3MAP_MASK             (0xF000U)
30631 #define DDRPHY_DX6DQMAP0_DQ3MAP_SHIFT            (12U)
30632 /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
30633  */
30634 #define DDRPHY_DX6DQMAP0_DQ3MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ3MAP_MASK)
30635 #define DDRPHY_DX6DQMAP0_DQ4MAP_MASK             (0xF0000U)
30636 #define DDRPHY_DX6DQMAP0_DQ4MAP_SHIFT            (16U)
30637 /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
30638  */
30639 #define DDRPHY_DX6DQMAP0_DQ4MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ4MAP_MASK)
30640 #define DDRPHY_DX6DQMAP0_RESERVED_30_20_MASK     (0x7FF00000U)
30641 #define DDRPHY_DX6DQMAP0_RESERVED_30_20_SHIFT    (20U)
30642 /*! RESERVED_30_20 - Reserved. Return zeroes on reads.
30643  */
30644 #define DDRPHY_DX6DQMAP0_RESERVED_30_20(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX6DQMAP0_RESERVED_30_20_MASK)
30645 #define DDRPHY_DX6DQMAP0_MAPOK_MASK              (0x80000000U)
30646 #define DDRPHY_DX6DQMAP0_MAPOK_SHIFT             (31U)
30647 /*! MAPOK - Checksum bit
30648  */
30649 #define DDRPHY_DX6DQMAP0_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX6DQMAP0_MAPOK_MASK)
30650 /*! @} */
30651 
30652 /*! @name DX6DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
30653 /*! @{ */
30654 #define DDRPHY_DX6DQMAP1_DQ5MAP_MASK             (0xFU)
30655 #define DDRPHY_DX6DQMAP1_DQ5MAP_SHIFT            (0U)
30656 /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
30657  */
30658 #define DDRPHY_DX6DQMAP1_DQ5MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX6DQMAP1_DQ5MAP_MASK)
30659 #define DDRPHY_DX6DQMAP1_DQ6MAP_MASK             (0xF0U)
30660 #define DDRPHY_DX6DQMAP1_DQ6MAP_SHIFT            (4U)
30661 /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
30662  */
30663 #define DDRPHY_DX6DQMAP1_DQ6MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX6DQMAP1_DQ6MAP_MASK)
30664 #define DDRPHY_DX6DQMAP1_DQ7MAP_MASK             (0xF00U)
30665 #define DDRPHY_DX6DQMAP1_DQ7MAP_SHIFT            (8U)
30666 /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
30667  */
30668 #define DDRPHY_DX6DQMAP1_DQ7MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX6DQMAP1_DQ7MAP_MASK)
30669 #define DDRPHY_DX6DQMAP1_DMMAP_MASK              (0xF000U)
30670 #define DDRPHY_DX6DQMAP1_DMMAP_SHIFT             (12U)
30671 /*! DMMAP - DM bit DATX8 slice mapping index
30672  */
30673 #define DDRPHY_DX6DQMAP1_DMMAP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX6DQMAP1_DMMAP_MASK)
30674 #define DDRPHY_DX6DQMAP1_RESERVED_30_16_MASK     (0x7FFF0000U)
30675 #define DDRPHY_DX6DQMAP1_RESERVED_30_16_SHIFT    (16U)
30676 /*! RESERVED_30_16 - Reserved. Return zeroes on reads.
30677  */
30678 #define DDRPHY_DX6DQMAP1_RESERVED_30_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX6DQMAP1_RESERVED_30_16_MASK)
30679 #define DDRPHY_DX6DQMAP1_MAPOK_MASK              (0x80000000U)
30680 #define DDRPHY_DX6DQMAP1_MAPOK_SHIFT             (31U)
30681 /*! MAPOK - Checksum bit
30682  */
30683 #define DDRPHY_DX6DQMAP1_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX6DQMAP1_MAPOK_MASK)
30684 /*! @} */
30685 
30686 /*! @name DX6BDLR0 - DATX8 n Bit Delay Line Register 0 */
30687 /*! @{ */
30688 #define DDRPHY_DX6BDLR0_DQ0WBD_MASK              (0x3FU)
30689 #define DDRPHY_DX6BDLR0_DQ0WBD_SHIFT             (0U)
30690 /*! DQ0WBD - DQ0 Write Bit Delay
30691  */
30692 #define DDRPHY_DX6BDLR0_DQ0WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ0WBD_MASK)
30693 #define DDRPHY_DX6BDLR0_RESERVED_7_6_MASK        (0xC0U)
30694 #define DDRPHY_DX6BDLR0_RESERVED_7_6_SHIFT       (6U)
30695 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30696  */
30697 #define DDRPHY_DX6BDLR0_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_7_6_MASK)
30698 #define DDRPHY_DX6BDLR0_DQ1WBD_MASK              (0x3F00U)
30699 #define DDRPHY_DX6BDLR0_DQ1WBD_SHIFT             (8U)
30700 /*! DQ1WBD - DQ1 Write Bit Delay
30701  */
30702 #define DDRPHY_DX6BDLR0_DQ1WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ1WBD_MASK)
30703 #define DDRPHY_DX6BDLR0_RESERVED_15_14_MASK      (0xC000U)
30704 #define DDRPHY_DX6BDLR0_RESERVED_15_14_SHIFT     (14U)
30705 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30706  */
30707 #define DDRPHY_DX6BDLR0_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_15_14_MASK)
30708 #define DDRPHY_DX6BDLR0_DQ2WBD_MASK              (0x3F0000U)
30709 #define DDRPHY_DX6BDLR0_DQ2WBD_SHIFT             (16U)
30710 /*! DQ2WBD - DQ2 Write Bit Delay
30711  */
30712 #define DDRPHY_DX6BDLR0_DQ2WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ2WBD_MASK)
30713 #define DDRPHY_DX6BDLR0_RESERVED_23_22_MASK      (0xC00000U)
30714 #define DDRPHY_DX6BDLR0_RESERVED_23_22_SHIFT     (22U)
30715 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30716  */
30717 #define DDRPHY_DX6BDLR0_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_23_22_MASK)
30718 #define DDRPHY_DX6BDLR0_DQ3WBD_MASK              (0x3F000000U)
30719 #define DDRPHY_DX6BDLR0_DQ3WBD_SHIFT             (24U)
30720 /*! DQ3WBD - DQ3 Write Bit Delay
30721  */
30722 #define DDRPHY_DX6BDLR0_DQ3WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ3WBD_MASK)
30723 #define DDRPHY_DX6BDLR0_RESERVED_31_30_MASK      (0xC0000000U)
30724 #define DDRPHY_DX6BDLR0_RESERVED_31_30_SHIFT     (30U)
30725 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30726  */
30727 #define DDRPHY_DX6BDLR0_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_31_30_MASK)
30728 /*! @} */
30729 
30730 /*! @name DX6BDLR1 - DATX8 n Bit Delay Line Register 1 */
30731 /*! @{ */
30732 #define DDRPHY_DX6BDLR1_DQ4WBD_MASK              (0x3FU)
30733 #define DDRPHY_DX6BDLR1_DQ4WBD_SHIFT             (0U)
30734 /*! DQ4WBD - DQ4 Write Bit Delay
30735  */
30736 #define DDRPHY_DX6BDLR1_DQ4WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ4WBD_MASK)
30737 #define DDRPHY_DX6BDLR1_RESERVED_7_6_MASK        (0xC0U)
30738 #define DDRPHY_DX6BDLR1_RESERVED_7_6_SHIFT       (6U)
30739 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30740  */
30741 #define DDRPHY_DX6BDLR1_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_7_6_MASK)
30742 #define DDRPHY_DX6BDLR1_DQ5WBD_MASK              (0x3F00U)
30743 #define DDRPHY_DX6BDLR1_DQ5WBD_SHIFT             (8U)
30744 /*! DQ5WBD - DQ5 Write Bit Delay
30745  */
30746 #define DDRPHY_DX6BDLR1_DQ5WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ5WBD_MASK)
30747 #define DDRPHY_DX6BDLR1_RESERVED_15_14_MASK      (0xC000U)
30748 #define DDRPHY_DX6BDLR1_RESERVED_15_14_SHIFT     (14U)
30749 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30750  */
30751 #define DDRPHY_DX6BDLR1_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_15_14_MASK)
30752 #define DDRPHY_DX6BDLR1_DQ6WBD_MASK              (0x3F0000U)
30753 #define DDRPHY_DX6BDLR1_DQ6WBD_SHIFT             (16U)
30754 /*! DQ6WBD - DQ6 Write Bit Delay
30755  */
30756 #define DDRPHY_DX6BDLR1_DQ6WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ6WBD_MASK)
30757 #define DDRPHY_DX6BDLR1_RESERVED_23_22_MASK      (0xC00000U)
30758 #define DDRPHY_DX6BDLR1_RESERVED_23_22_SHIFT     (22U)
30759 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30760  */
30761 #define DDRPHY_DX6BDLR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_23_22_MASK)
30762 #define DDRPHY_DX6BDLR1_DQ7WBD_MASK              (0x3F000000U)
30763 #define DDRPHY_DX6BDLR1_DQ7WBD_SHIFT             (24U)
30764 /*! DQ7WBD - DQ7 Write Bit Delay
30765  */
30766 #define DDRPHY_DX6BDLR1_DQ7WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ7WBD_MASK)
30767 #define DDRPHY_DX6BDLR1_RESERVED_31_30_MASK      (0xC0000000U)
30768 #define DDRPHY_DX6BDLR1_RESERVED_31_30_SHIFT     (30U)
30769 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30770  */
30771 #define DDRPHY_DX6BDLR1_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_31_30_MASK)
30772 /*! @} */
30773 
30774 /*! @name DX6BDLR2 - DATX8 n Bit Delay Line Register 2 */
30775 /*! @{ */
30776 #define DDRPHY_DX6BDLR2_DMWBD_MASK               (0x3FU)
30777 #define DDRPHY_DX6BDLR2_DMWBD_SHIFT              (0U)
30778 /*! DMWBD - DM Write Bit Delay
30779  */
30780 #define DDRPHY_DX6BDLR2_DMWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DMWBD_SHIFT)) & DDRPHY_DX6BDLR2_DMWBD_MASK)
30781 #define DDRPHY_DX6BDLR2_RESERVED_7_6_MASK        (0xC0U)
30782 #define DDRPHY_DX6BDLR2_RESERVED_7_6_SHIFT       (6U)
30783 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30784  */
30785 #define DDRPHY_DX6BDLR2_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_7_6_MASK)
30786 #define DDRPHY_DX6BDLR2_DSWBD_MASK               (0x3F00U)
30787 #define DDRPHY_DX6BDLR2_DSWBD_SHIFT              (8U)
30788 /*! DSWBD - DQS Write Bit Delay
30789  */
30790 #define DDRPHY_DX6BDLR2_DSWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DSWBD_SHIFT)) & DDRPHY_DX6BDLR2_DSWBD_MASK)
30791 #define DDRPHY_DX6BDLR2_RESERVED_15_14_MASK      (0xC000U)
30792 #define DDRPHY_DX6BDLR2_RESERVED_15_14_SHIFT     (14U)
30793 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30794  */
30795 #define DDRPHY_DX6BDLR2_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_15_14_MASK)
30796 #define DDRPHY_DX6BDLR2_DSOEBD_MASK              (0x3F0000U)
30797 #define DDRPHY_DX6BDLR2_DSOEBD_SHIFT             (16U)
30798 /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
30799  */
30800 #define DDRPHY_DX6BDLR2_DSOEBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX6BDLR2_DSOEBD_MASK)
30801 #define DDRPHY_DX6BDLR2_RESERVED_23_22_MASK      (0xC00000U)
30802 #define DDRPHY_DX6BDLR2_RESERVED_23_22_SHIFT     (22U)
30803 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30804  */
30805 #define DDRPHY_DX6BDLR2_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_23_22_MASK)
30806 #define DDRPHY_DX6BDLR2_DSNWBD_MASK              (0x3F000000U)
30807 #define DDRPHY_DX6BDLR2_DSNWBD_SHIFT             (24U)
30808 /*! DSNWBD - DQSN Write Bit Delay
30809  */
30810 #define DDRPHY_DX6BDLR2_DSNWBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX6BDLR2_DSNWBD_MASK)
30811 #define DDRPHY_DX6BDLR2_RESERVED_31_30_MASK      (0xC0000000U)
30812 #define DDRPHY_DX6BDLR2_RESERVED_31_30_SHIFT     (30U)
30813 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30814  */
30815 #define DDRPHY_DX6BDLR2_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_31_30_MASK)
30816 /*! @} */
30817 
30818 /*! @name DX6BDLR3 - DATX8 n Bit Delay Line Register 3 */
30819 /*! @{ */
30820 #define DDRPHY_DX6BDLR3_DQ0RBD_MASK              (0x3FU)
30821 #define DDRPHY_DX6BDLR3_DQ0RBD_SHIFT             (0U)
30822 /*! DQ0RBD - DQ0 Read Bit Delay
30823  */
30824 #define DDRPHY_DX6BDLR3_DQ0RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ0RBD_MASK)
30825 #define DDRPHY_DX6BDLR3_RESERVED_7_6_MASK        (0xC0U)
30826 #define DDRPHY_DX6BDLR3_RESERVED_7_6_SHIFT       (6U)
30827 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30828  */
30829 #define DDRPHY_DX6BDLR3_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_7_6_MASK)
30830 #define DDRPHY_DX6BDLR3_DQ1RBD_MASK              (0x3F00U)
30831 #define DDRPHY_DX6BDLR3_DQ1RBD_SHIFT             (8U)
30832 /*! DQ1RBD - DQ1 Read Bit Delay
30833  */
30834 #define DDRPHY_DX6BDLR3_DQ1RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ1RBD_MASK)
30835 #define DDRPHY_DX6BDLR3_RESERVED_15_14_MASK      (0xC000U)
30836 #define DDRPHY_DX6BDLR3_RESERVED_15_14_SHIFT     (14U)
30837 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30838  */
30839 #define DDRPHY_DX6BDLR3_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_15_14_MASK)
30840 #define DDRPHY_DX6BDLR3_DQ2RBD_MASK              (0x3F0000U)
30841 #define DDRPHY_DX6BDLR3_DQ2RBD_SHIFT             (16U)
30842 /*! DQ2RBD - DQ2 Read Bit Delay
30843  */
30844 #define DDRPHY_DX6BDLR3_DQ2RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ2RBD_MASK)
30845 #define DDRPHY_DX6BDLR3_RESERVED_23_22_MASK      (0xC00000U)
30846 #define DDRPHY_DX6BDLR3_RESERVED_23_22_SHIFT     (22U)
30847 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30848  */
30849 #define DDRPHY_DX6BDLR3_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_23_22_MASK)
30850 #define DDRPHY_DX6BDLR3_DQ3RBD_MASK              (0x3F000000U)
30851 #define DDRPHY_DX6BDLR3_DQ3RBD_SHIFT             (24U)
30852 /*! DQ3RBD - DQ3 Read Bit Delay
30853  */
30854 #define DDRPHY_DX6BDLR3_DQ3RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ3RBD_MASK)
30855 #define DDRPHY_DX6BDLR3_RESERVED_31_30_MASK      (0xC0000000U)
30856 #define DDRPHY_DX6BDLR3_RESERVED_31_30_SHIFT     (30U)
30857 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30858  */
30859 #define DDRPHY_DX6BDLR3_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_31_30_MASK)
30860 /*! @} */
30861 
30862 /*! @name DX6BDLR4 - DATX8 n Bit Delay Line Register 4 */
30863 /*! @{ */
30864 #define DDRPHY_DX6BDLR4_DQ4RBD_MASK              (0x3FU)
30865 #define DDRPHY_DX6BDLR4_DQ4RBD_SHIFT             (0U)
30866 /*! DQ4RBD - DQ4 Read Bit Delay
30867  */
30868 #define DDRPHY_DX6BDLR4_DQ4RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ4RBD_MASK)
30869 #define DDRPHY_DX6BDLR4_RESERVED_7_6_MASK        (0xC0U)
30870 #define DDRPHY_DX6BDLR4_RESERVED_7_6_SHIFT       (6U)
30871 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30872  */
30873 #define DDRPHY_DX6BDLR4_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_7_6_MASK)
30874 #define DDRPHY_DX6BDLR4_DQ5RBD_MASK              (0x3F00U)
30875 #define DDRPHY_DX6BDLR4_DQ5RBD_SHIFT             (8U)
30876 /*! DQ5RBD - DQ5 Read Bit Delay
30877  */
30878 #define DDRPHY_DX6BDLR4_DQ5RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ5RBD_MASK)
30879 #define DDRPHY_DX6BDLR4_RESERVED_15_14_MASK      (0xC000U)
30880 #define DDRPHY_DX6BDLR4_RESERVED_15_14_SHIFT     (14U)
30881 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30882  */
30883 #define DDRPHY_DX6BDLR4_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_15_14_MASK)
30884 #define DDRPHY_DX6BDLR4_DQ6RBD_MASK              (0x3F0000U)
30885 #define DDRPHY_DX6BDLR4_DQ6RBD_SHIFT             (16U)
30886 /*! DQ6RBD - DQ6 Read Bit Delay
30887  */
30888 #define DDRPHY_DX6BDLR4_DQ6RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ6RBD_MASK)
30889 #define DDRPHY_DX6BDLR4_RESERVED_23_22_MASK      (0xC00000U)
30890 #define DDRPHY_DX6BDLR4_RESERVED_23_22_SHIFT     (22U)
30891 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30892  */
30893 #define DDRPHY_DX6BDLR4_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_23_22_MASK)
30894 #define DDRPHY_DX6BDLR4_DQ7RBD_MASK              (0x3F000000U)
30895 #define DDRPHY_DX6BDLR4_DQ7RBD_SHIFT             (24U)
30896 /*! DQ7RBD - DQ7 Read Bit Delay
30897  */
30898 #define DDRPHY_DX6BDLR4_DQ7RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ7RBD_MASK)
30899 #define DDRPHY_DX6BDLR4_RESERVED_31_30_MASK      (0xC0000000U)
30900 #define DDRPHY_DX6BDLR4_RESERVED_31_30_SHIFT     (30U)
30901 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30902  */
30903 #define DDRPHY_DX6BDLR4_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_31_30_MASK)
30904 /*! @} */
30905 
30906 /*! @name DX6BDLR5 - DATX8 n Bit Delay Line Register 5 */
30907 /*! @{ */
30908 #define DDRPHY_DX6BDLR5_DMRBD_MASK               (0x3FU)
30909 #define DDRPHY_DX6BDLR5_DMRBD_SHIFT              (0U)
30910 /*! DMRBD - DM Read Bit Delay
30911  */
30912 #define DDRPHY_DX6BDLR5_DMRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR5_DMRBD_SHIFT)) & DDRPHY_DX6BDLR5_DMRBD_MASK)
30913 #define DDRPHY_DX6BDLR5_RESERVED_31_6_MASK       (0xFFFFFFC0U)
30914 #define DDRPHY_DX6BDLR5_RESERVED_31_6_SHIFT      (6U)
30915 /*! RESERVED_31_6 - Reserved. Return zeroes on reads.
30916  */
30917 #define DDRPHY_DX6BDLR5_RESERVED_31_6(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX6BDLR5_RESERVED_31_6_MASK)
30918 /*! @} */
30919 
30920 /*! @name DX6BDLR6 - DATX8 n Bit Delay Line Register 6 */
30921 /*! @{ */
30922 #define DDRPHY_DX6BDLR6_RESERVED_7_0_MASK        (0xFFU)
30923 #define DDRPHY_DX6BDLR6_RESERVED_7_0_SHIFT       (0U)
30924 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
30925  */
30926 #define DDRPHY_DX6BDLR6_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX6BDLR6_RESERVED_7_0_MASK)
30927 #define DDRPHY_DX6BDLR6_PDRBD_MASK               (0x3F00U)
30928 #define DDRPHY_DX6BDLR6_PDRBD_SHIFT              (8U)
30929 /*! PDRBD - Power down receiver Bit Delay
30930  */
30931 #define DDRPHY_DX6BDLR6_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_PDRBD_SHIFT)) & DDRPHY_DX6BDLR6_PDRBD_MASK)
30932 #define DDRPHY_DX6BDLR6_RESERVED_15_14_MASK      (0xC000U)
30933 #define DDRPHY_DX6BDLR6_RESERVED_15_14_SHIFT     (14U)
30934 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30935  */
30936 #define DDRPHY_DX6BDLR6_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR6_RESERVED_15_14_MASK)
30937 #define DDRPHY_DX6BDLR6_TERBD_MASK               (0x3F0000U)
30938 #define DDRPHY_DX6BDLR6_TERBD_SHIFT              (16U)
30939 /*! TERBD - Termination Enable Bit Delay
30940  */
30941 #define DDRPHY_DX6BDLR6_TERBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_TERBD_SHIFT)) & DDRPHY_DX6BDLR6_TERBD_MASK)
30942 #define DDRPHY_DX6BDLR6_RESERVED_31_22_MASK      (0xFFC00000U)
30943 #define DDRPHY_DX6BDLR6_RESERVED_31_22_SHIFT     (22U)
30944 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
30945  */
30946 #define DDRPHY_DX6BDLR6_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR6_RESERVED_31_22_MASK)
30947 /*! @} */
30948 
30949 /*! @name DX6BDLR7 - DATX8 n Bit Delay Line Register 7 */
30950 /*! @{ */
30951 #define DDRPHY_DX6BDLR7_RESERVED_5_0_MASK        (0x3FU)
30952 #define DDRPHY_DX6BDLR7_RESERVED_5_0_SHIFT       (0U)
30953 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
30954  */
30955 #define DDRPHY_DX6BDLR7_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_5_0_MASK)
30956 #define DDRPHY_DX6BDLR7_RESERVED_7_6_MASK        (0xC0U)
30957 #define DDRPHY_DX6BDLR7_RESERVED_7_6_SHIFT       (6U)
30958 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30959  */
30960 #define DDRPHY_DX6BDLR7_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_7_6_MASK)
30961 #define DDRPHY_DX6BDLR7_RESERVED_13_8_MASK       (0x3F00U)
30962 #define DDRPHY_DX6BDLR7_RESERVED_13_8_SHIFT      (8U)
30963 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
30964  */
30965 #define DDRPHY_DX6BDLR7_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_13_8_MASK)
30966 #define DDRPHY_DX6BDLR7_RESERVED_15_14_MASK      (0xC000U)
30967 #define DDRPHY_DX6BDLR7_RESERVED_15_14_SHIFT     (14U)
30968 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30969  */
30970 #define DDRPHY_DX6BDLR7_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_15_14_MASK)
30971 #define DDRPHY_DX6BDLR7_RESERVED_21_16_MASK      (0x3F0000U)
30972 #define DDRPHY_DX6BDLR7_RESERVED_21_16_SHIFT     (16U)
30973 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
30974  */
30975 #define DDRPHY_DX6BDLR7_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_21_16_MASK)
30976 #define DDRPHY_DX6BDLR7_RESERVED_31_22_MASK      (0xFFC00000U)
30977 #define DDRPHY_DX6BDLR7_RESERVED_31_22_SHIFT     (22U)
30978 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
30979  */
30980 #define DDRPHY_DX6BDLR7_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_31_22_MASK)
30981 /*! @} */
30982 
30983 /*! @name DX6BDLR8 - DATX8 n Bit Delay Line Register 8 */
30984 /*! @{ */
30985 #define DDRPHY_DX6BDLR8_RESERVED_5_0_MASK        (0x3FU)
30986 #define DDRPHY_DX6BDLR8_RESERVED_5_0_SHIFT       (0U)
30987 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
30988  */
30989 #define DDRPHY_DX6BDLR8_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_5_0_MASK)
30990 #define DDRPHY_DX6BDLR8_RESERVED_7_6_MASK        (0xC0U)
30991 #define DDRPHY_DX6BDLR8_RESERVED_7_6_SHIFT       (6U)
30992 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30993  */
30994 #define DDRPHY_DX6BDLR8_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_7_6_MASK)
30995 #define DDRPHY_DX6BDLR8_RESERVED_13_8_MASK       (0x3F00U)
30996 #define DDRPHY_DX6BDLR8_RESERVED_13_8_SHIFT      (8U)
30997 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
30998  */
30999 #define DDRPHY_DX6BDLR8_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_13_8_MASK)
31000 #define DDRPHY_DX6BDLR8_RESERVED_15_14_MASK      (0xC000U)
31001 #define DDRPHY_DX6BDLR8_RESERVED_15_14_SHIFT     (14U)
31002 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
31003  */
31004 #define DDRPHY_DX6BDLR8_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_15_14_MASK)
31005 #define DDRPHY_DX6BDLR8_RESERVED_21_16_MASK      (0x3F0000U)
31006 #define DDRPHY_DX6BDLR8_RESERVED_21_16_SHIFT     (16U)
31007 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
31008  */
31009 #define DDRPHY_DX6BDLR8_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_21_16_MASK)
31010 #define DDRPHY_DX6BDLR8_RESERVED_31_22_MASK      (0xFFC00000U)
31011 #define DDRPHY_DX6BDLR8_RESERVED_31_22_SHIFT     (22U)
31012 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
31013  */
31014 #define DDRPHY_DX6BDLR8_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_31_22_MASK)
31015 /*! @} */
31016 
31017 /*! @name DX6BDLR9 - DATX8 n Bit Delay Line Register 9 */
31018 /*! @{ */
31019 #define DDRPHY_DX6BDLR9_RESERVED_5_0_MASK        (0x3FU)
31020 #define DDRPHY_DX6BDLR9_RESERVED_5_0_SHIFT       (0U)
31021 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
31022  */
31023 #define DDRPHY_DX6BDLR9_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_5_0_MASK)
31024 #define DDRPHY_DX6BDLR9_RESERVED_7_6_MASK        (0xC0U)
31025 #define DDRPHY_DX6BDLR9_RESERVED_7_6_SHIFT       (6U)
31026 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
31027  */
31028 #define DDRPHY_DX6BDLR9_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_7_6_MASK)
31029 #define DDRPHY_DX6BDLR9_RESERVED_13_8_MASK       (0x3F00U)
31030 #define DDRPHY_DX6BDLR9_RESERVED_13_8_SHIFT      (8U)
31031 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
31032  */
31033 #define DDRPHY_DX6BDLR9_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_13_8_MASK)
31034 #define DDRPHY_DX6BDLR9_RESERVED_15_14_MASK      (0xC000U)
31035 #define DDRPHY_DX6BDLR9_RESERVED_15_14_SHIFT     (14U)
31036 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
31037  */
31038 #define DDRPHY_DX6BDLR9_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_15_14_MASK)
31039 #define DDRPHY_DX6BDLR9_RESERVED_21_16_MASK      (0x3F0000U)
31040 #define DDRPHY_DX6BDLR9_RESERVED_21_16_SHIFT     (16U)
31041 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
31042  */
31043 #define DDRPHY_DX6BDLR9_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_21_16_MASK)
31044 #define DDRPHY_DX6BDLR9_RESERVED_31_22_MASK      (0xFFC00000U)
31045 #define DDRPHY_DX6BDLR9_RESERVED_31_22_SHIFT     (22U)
31046 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
31047  */
31048 #define DDRPHY_DX6BDLR9_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_31_22_MASK)
31049 /*! @} */
31050 
31051 /*! @name DX6LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
31052 /*! @{ */
31053 #define DDRPHY_DX6LCDLR0_WLD_MASK                (0x1FFU)
31054 #define DDRPHY_DX6LCDLR0_WLD_SHIFT               (0U)
31055 /*! WLD - Write Leveling Delay
31056  */
31057 #define DDRPHY_DX6LCDLR0_WLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_WLD_SHIFT)) & DDRPHY_DX6LCDLR0_WLD_MASK)
31058 #define DDRPHY_DX6LCDLR0_RESERVED_15_9_MASK      (0xFE00U)
31059 #define DDRPHY_DX6LCDLR0_RESERVED_15_9_SHIFT     (9U)
31060 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31061  */
31062 #define DDRPHY_DX6LCDLR0_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR0_RESERVED_15_9_MASK)
31063 #define DDRPHY_DX6LCDLR0_RESERVED_24_16_MASK     (0x1FF0000U)
31064 #define DDRPHY_DX6LCDLR0_RESERVED_24_16_SHIFT    (16U)
31065 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31066  */
31067 #define DDRPHY_DX6LCDLR0_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR0_RESERVED_24_16_MASK)
31068 #define DDRPHY_DX6LCDLR0_RESERVED_31_25_MASK     (0xFE000000U)
31069 #define DDRPHY_DX6LCDLR0_RESERVED_31_25_SHIFT    (25U)
31070 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31071  */
31072 #define DDRPHY_DX6LCDLR0_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR0_RESERVED_31_25_MASK)
31073 /*! @} */
31074 
31075 /*! @name DX6LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
31076 /*! @{ */
31077 #define DDRPHY_DX6LCDLR1_WDQD_MASK               (0x1FFU)
31078 #define DDRPHY_DX6LCDLR1_WDQD_SHIFT              (0U)
31079 /*! WDQD - Write Data Delay
31080  */
31081 #define DDRPHY_DX6LCDLR1_WDQD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_WDQD_SHIFT)) & DDRPHY_DX6LCDLR1_WDQD_MASK)
31082 #define DDRPHY_DX6LCDLR1_RESERVED_15_9_MASK      (0xFE00U)
31083 #define DDRPHY_DX6LCDLR1_RESERVED_15_9_SHIFT     (9U)
31084 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31085  */
31086 #define DDRPHY_DX6LCDLR1_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR1_RESERVED_15_9_MASK)
31087 #define DDRPHY_DX6LCDLR1_RESERVED_24_16_MASK     (0x1FF0000U)
31088 #define DDRPHY_DX6LCDLR1_RESERVED_24_16_SHIFT    (16U)
31089 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31090  */
31091 #define DDRPHY_DX6LCDLR1_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR1_RESERVED_24_16_MASK)
31092 #define DDRPHY_DX6LCDLR1_RESERVED_31_25_MASK     (0xFE000000U)
31093 #define DDRPHY_DX6LCDLR1_RESERVED_31_25_SHIFT    (25U)
31094 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31095  */
31096 #define DDRPHY_DX6LCDLR1_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR1_RESERVED_31_25_MASK)
31097 /*! @} */
31098 
31099 /*! @name DX6LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
31100 /*! @{ */
31101 #define DDRPHY_DX6LCDLR2_DQSGD_MASK              (0x1FFU)
31102 #define DDRPHY_DX6LCDLR2_DQSGD_SHIFT             (0U)
31103 /*! DQSGD - Read DQS Gating Delay
31104  */
31105 #define DDRPHY_DX6LCDLR2_DQSGD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX6LCDLR2_DQSGD_MASK)
31106 #define DDRPHY_DX6LCDLR2_RESERVED_15_9_MASK      (0xFE00U)
31107 #define DDRPHY_DX6LCDLR2_RESERVED_15_9_SHIFT     (9U)
31108 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31109  */
31110 #define DDRPHY_DX6LCDLR2_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR2_RESERVED_15_9_MASK)
31111 #define DDRPHY_DX6LCDLR2_RESERVED_24_16_MASK     (0x1FF0000U)
31112 #define DDRPHY_DX6LCDLR2_RESERVED_24_16_SHIFT    (16U)
31113 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31114  */
31115 #define DDRPHY_DX6LCDLR2_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR2_RESERVED_24_16_MASK)
31116 #define DDRPHY_DX6LCDLR2_RESERVED_31_25_MASK     (0xFE000000U)
31117 #define DDRPHY_DX6LCDLR2_RESERVED_31_25_SHIFT    (25U)
31118 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31119  */
31120 #define DDRPHY_DX6LCDLR2_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR2_RESERVED_31_25_MASK)
31121 /*! @} */
31122 
31123 /*! @name DX6LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
31124 /*! @{ */
31125 #define DDRPHY_DX6LCDLR3_RDQSD_MASK              (0x1FFU)
31126 #define DDRPHY_DX6LCDLR3_RDQSD_SHIFT             (0U)
31127 /*! RDQSD - Read DQS Delay
31128  */
31129 #define DDRPHY_DX6LCDLR3_RDQSD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX6LCDLR3_RDQSD_MASK)
31130 #define DDRPHY_DX6LCDLR3_RESERVED_15_9_MASK      (0xFE00U)
31131 #define DDRPHY_DX6LCDLR3_RESERVED_15_9_SHIFT     (9U)
31132 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31133  */
31134 #define DDRPHY_DX6LCDLR3_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR3_RESERVED_15_9_MASK)
31135 #define DDRPHY_DX6LCDLR3_RESERVED_24_16_MASK     (0x1FF0000U)
31136 #define DDRPHY_DX6LCDLR3_RESERVED_24_16_SHIFT    (16U)
31137 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31138  */
31139 #define DDRPHY_DX6LCDLR3_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR3_RESERVED_24_16_MASK)
31140 #define DDRPHY_DX6LCDLR3_RESERVED_31_25_MASK     (0xFE000000U)
31141 #define DDRPHY_DX6LCDLR3_RESERVED_31_25_SHIFT    (25U)
31142 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31143  */
31144 #define DDRPHY_DX6LCDLR3_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR3_RESERVED_31_25_MASK)
31145 /*! @} */
31146 
31147 /*! @name DX6LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
31148 /*! @{ */
31149 #define DDRPHY_DX6LCDLR4_RDQSND_MASK             (0x1FFU)
31150 #define DDRPHY_DX6LCDLR4_RDQSND_SHIFT            (0U)
31151 /*! RDQSND - Read DQSN Delay
31152  */
31153 #define DDRPHY_DX6LCDLR4_RDQSND(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX6LCDLR4_RDQSND_MASK)
31154 #define DDRPHY_DX6LCDLR4_RESERVED_15_9_MASK      (0xFE00U)
31155 #define DDRPHY_DX6LCDLR4_RESERVED_15_9_SHIFT     (9U)
31156 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31157  */
31158 #define DDRPHY_DX6LCDLR4_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR4_RESERVED_15_9_MASK)
31159 #define DDRPHY_DX6LCDLR4_RESERVED_24_16_MASK     (0x1FF0000U)
31160 #define DDRPHY_DX6LCDLR4_RESERVED_24_16_SHIFT    (16U)
31161 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31162  */
31163 #define DDRPHY_DX6LCDLR4_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR4_RESERVED_24_16_MASK)
31164 #define DDRPHY_DX6LCDLR4_RESERVED_31_25_MASK     (0xFE000000U)
31165 #define DDRPHY_DX6LCDLR4_RESERVED_31_25_SHIFT    (25U)
31166 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31167  */
31168 #define DDRPHY_DX6LCDLR4_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR4_RESERVED_31_25_MASK)
31169 /*! @} */
31170 
31171 /*! @name DX6LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
31172 /*! @{ */
31173 #define DDRPHY_DX6LCDLR5_DQSGSD_MASK             (0x1FFU)
31174 #define DDRPHY_DX6LCDLR5_DQSGSD_SHIFT            (0U)
31175 /*! DQSGSD - DQS Gating Status Delay
31176  */
31177 #define DDRPHY_DX6LCDLR5_DQSGSD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX6LCDLR5_DQSGSD_MASK)
31178 #define DDRPHY_DX6LCDLR5_RESERVED_15_9_MASK      (0xFE00U)
31179 #define DDRPHY_DX6LCDLR5_RESERVED_15_9_SHIFT     (9U)
31180 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31181  */
31182 #define DDRPHY_DX6LCDLR5_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR5_RESERVED_15_9_MASK)
31183 #define DDRPHY_DX6LCDLR5_RESERVED_24_16_MASK     (0x1FF0000U)
31184 #define DDRPHY_DX6LCDLR5_RESERVED_24_16_SHIFT    (16U)
31185 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31186  */
31187 #define DDRPHY_DX6LCDLR5_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR5_RESERVED_24_16_MASK)
31188 #define DDRPHY_DX6LCDLR5_RESERVED_31_25_MASK     (0xFE000000U)
31189 #define DDRPHY_DX6LCDLR5_RESERVED_31_25_SHIFT    (25U)
31190 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31191  */
31192 #define DDRPHY_DX6LCDLR5_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR5_RESERVED_31_25_MASK)
31193 /*! @} */
31194 
31195 /*! @name DX6MDLR0 - DATX8 n Master Delay Line Register 0 */
31196 /*! @{ */
31197 #define DDRPHY_DX6MDLR0_IPRD_MASK                (0x1FFU)
31198 #define DDRPHY_DX6MDLR0_IPRD_SHIFT               (0U)
31199 /*! IPRD - Initial Period
31200  */
31201 #define DDRPHY_DX6MDLR0_IPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_IPRD_SHIFT)) & DDRPHY_DX6MDLR0_IPRD_MASK)
31202 #define DDRPHY_DX6MDLR0_RESERVED_15_9_MASK       (0xFE00U)
31203 #define DDRPHY_DX6MDLR0_RESERVED_15_9_SHIFT      (9U)
31204 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31205  */
31206 #define DDRPHY_DX6MDLR0_RESERVED_15_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX6MDLR0_RESERVED_15_9_MASK)
31207 #define DDRPHY_DX6MDLR0_TPRD_MASK                (0x1FF0000U)
31208 #define DDRPHY_DX6MDLR0_TPRD_SHIFT               (16U)
31209 /*! TPRD - Target Period
31210  */
31211 #define DDRPHY_DX6MDLR0_TPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_TPRD_SHIFT)) & DDRPHY_DX6MDLR0_TPRD_MASK)
31212 #define DDRPHY_DX6MDLR0_RESERVED_31_25_MASK      (0xFE000000U)
31213 #define DDRPHY_DX6MDLR0_RESERVED_31_25_SHIFT     (25U)
31214 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31215  */
31216 #define DDRPHY_DX6MDLR0_RESERVED_31_25(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX6MDLR0_RESERVED_31_25_MASK)
31217 /*! @} */
31218 
31219 /*! @name DX6MDLR1 - DATX8 n Master Delay Line Register 1 */
31220 /*! @{ */
31221 #define DDRPHY_DX6MDLR1_MDLD_MASK                (0x1FFU)
31222 #define DDRPHY_DX6MDLR1_MDLD_SHIFT               (0U)
31223 /*! MDLD - MDL Delay
31224  */
31225 #define DDRPHY_DX6MDLR1_MDLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR1_MDLD_SHIFT)) & DDRPHY_DX6MDLR1_MDLD_MASK)
31226 #define DDRPHY_DX6MDLR1_RESERVED_31_9_MASK       (0xFFFFFE00U)
31227 #define DDRPHY_DX6MDLR1_RESERVED_31_9_SHIFT      (9U)
31228 /*! RESERVED_31_9 - Reserved. Return zeroes on reads.
31229  */
31230 #define DDRPHY_DX6MDLR1_RESERVED_31_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX6MDLR1_RESERVED_31_9_MASK)
31231 /*! @} */
31232 
31233 /*! @name DX6GTR0 - DATX8 n General Timing Register 0 */
31234 /*! @{ */
31235 #define DDRPHY_DX6GTR0_DGSL_MASK                 (0x1FU)
31236 #define DDRPHY_DX6GTR0_DGSL_SHIFT                (0U)
31237 /*! DGSL - DQS Gating System Latency
31238  */
31239 #define DDRPHY_DX6GTR0_DGSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_DGSL_SHIFT)) & DDRPHY_DX6GTR0_DGSL_MASK)
31240 #define DDRPHY_DX6GTR0_RESERVED_7_5_MASK         (0xE0U)
31241 #define DDRPHY_DX6GTR0_RESERVED_7_5_SHIFT        (5U)
31242 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
31243  */
31244 #define DDRPHY_DX6GTR0_RESERVED_7_5(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_7_5_MASK)
31245 #define DDRPHY_DX6GTR0_RESERVED_12_8_MASK        (0x1F00U)
31246 #define DDRPHY_DX6GTR0_RESERVED_12_8_SHIFT       (8U)
31247 /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
31248  */
31249 #define DDRPHY_DX6GTR0_RESERVED_12_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_12_8_MASK)
31250 #define DDRPHY_DX6GTR0_RESERVED_15_13_MASK       (0xE000U)
31251 #define DDRPHY_DX6GTR0_RESERVED_15_13_SHIFT      (13U)
31252 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
31253  */
31254 #define DDRPHY_DX6GTR0_RESERVED_15_13(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_15_13_MASK)
31255 #define DDRPHY_DX6GTR0_WLSL_MASK                 (0xF0000U)
31256 #define DDRPHY_DX6GTR0_WLSL_SHIFT                (16U)
31257 /*! WLSL - Write Leveling System Latency
31258  */
31259 #define DDRPHY_DX6GTR0_WLSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_WLSL_SHIFT)) & DDRPHY_DX6GTR0_WLSL_MASK)
31260 #define DDRPHY_DX6GTR0_RESERVED_23_20_MASK       (0xF00000U)
31261 #define DDRPHY_DX6GTR0_RESERVED_23_20_SHIFT      (20U)
31262 /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
31263  */
31264 #define DDRPHY_DX6GTR0_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_23_20_MASK)
31265 #define DDRPHY_DX6GTR0_WDQSL_MASK                (0x7000000U)
31266 #define DDRPHY_DX6GTR0_WDQSL_SHIFT               (24U)
31267 /*! WDQSL - DQ Write Path Latency Pipeline
31268  */
31269 #define DDRPHY_DX6GTR0_WDQSL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_WDQSL_SHIFT)) & DDRPHY_DX6GTR0_WDQSL_MASK)
31270 #define DDRPHY_DX6GTR0_RESERVED_31_24_MASK       (0xF8000000U)
31271 #define DDRPHY_DX6GTR0_RESERVED_31_24_SHIFT      (27U)
31272 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
31273  */
31274 #define DDRPHY_DX6GTR0_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_31_24_MASK)
31275 /*! @} */
31276 
31277 /*! @name DX6RSR0 - DATX8 n Rank Status Register 0 */
31278 /*! @{ */
31279 #define DDRPHY_DX6RSR0_QSGERR_MASK               (0xFFFFU)
31280 #define DDRPHY_DX6RSR0_QSGERR_SHIFT              (0U)
31281 /*! QSGERR - DQS Gate Training Error
31282  */
31283 #define DDRPHY_DX6RSR0_QSGERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR0_QSGERR_SHIFT)) & DDRPHY_DX6RSR0_QSGERR_MASK)
31284 #define DDRPHY_DX6RSR0_RESERVED_31_16_MASK       (0xFFFF0000U)
31285 #define DDRPHY_DX6RSR0_RESERVED_31_16_SHIFT      (16U)
31286 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
31287  */
31288 #define DDRPHY_DX6RSR0_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR0_RESERVED_31_16_MASK)
31289 /*! @} */
31290 
31291 /*! @name DX6RSR1 - DATX8 n Rank Status Register 1 */
31292 /*! @{ */
31293 #define DDRPHY_DX6RSR1_RDLVLERR_MASK             (0xFFFFU)
31294 #define DDRPHY_DX6RSR1_RDLVLERR_SHIFT            (0U)
31295 /*! RDLVLERR - Read Leveling Error
31296  */
31297 #define DDRPHY_DX6RSR1_RDLVLERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX6RSR1_RDLVLERR_MASK)
31298 #define DDRPHY_DX6RSR1_RESERVED_31_16_MASK       (0xFFFF0000U)
31299 #define DDRPHY_DX6RSR1_RESERVED_31_16_SHIFT      (16U)
31300 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
31301  */
31302 #define DDRPHY_DX6RSR1_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR1_RESERVED_31_16_MASK)
31303 /*! @} */
31304 
31305 /*! @name DX6RSR2 - DATX8 n Rank Status Register 2 */
31306 /*! @{ */
31307 #define DDRPHY_DX6RSR2_WLAWN_MASK                (0xFFFFU)
31308 #define DDRPHY_DX6RSR2_WLAWN_SHIFT               (0U)
31309 /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
31310  */
31311 #define DDRPHY_DX6RSR2_WLAWN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR2_WLAWN_SHIFT)) & DDRPHY_DX6RSR2_WLAWN_MASK)
31312 #define DDRPHY_DX6RSR2_RESERVED_31_16_MASK       (0xFFFF0000U)
31313 #define DDRPHY_DX6RSR2_RESERVED_31_16_SHIFT      (16U)
31314 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
31315  */
31316 #define DDRPHY_DX6RSR2_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR2_RESERVED_31_16_MASK)
31317 /*! @} */
31318 
31319 /*! @name DX6RSR3 - DATX8 n Rank Status Register 3 */
31320 /*! @{ */
31321 #define DDRPHY_DX6RSR3_WLAERR_MASK               (0xFFFFU)
31322 #define DDRPHY_DX6RSR3_WLAERR_SHIFT              (0U)
31323 /*! WLAERR - Write Leveling Adjustment Error
31324  */
31325 #define DDRPHY_DX6RSR3_WLAERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR3_WLAERR_SHIFT)) & DDRPHY_DX6RSR3_WLAERR_MASK)
31326 #define DDRPHY_DX6RSR3_RESERVED_31_16_MASK       (0xFFFF0000U)
31327 #define DDRPHY_DX6RSR3_RESERVED_31_16_SHIFT      (16U)
31328 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
31329  */
31330 #define DDRPHY_DX6RSR3_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR3_RESERVED_31_16_MASK)
31331 /*! @} */
31332 
31333 /*! @name DX6GSR0 - DATX8 n General Status Register 0 */
31334 /*! @{ */
31335 #define DDRPHY_DX6GSR0_WDQCAL_MASK               (0x1U)
31336 #define DDRPHY_DX6GSR0_WDQCAL_SHIFT              (0U)
31337 /*! WDQCAL - Write DQ Calibration
31338  */
31339 #define DDRPHY_DX6GSR0_WDQCAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WDQCAL_SHIFT)) & DDRPHY_DX6GSR0_WDQCAL_MASK)
31340 #define DDRPHY_DX6GSR0_RDQSCAL_MASK              (0x2U)
31341 #define DDRPHY_DX6GSR0_RDQSCAL_SHIFT             (1U)
31342 /*! RDQSCAL - Read DQS Calibration
31343  */
31344 #define DDRPHY_DX6GSR0_RDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX6GSR0_RDQSCAL_MASK)
31345 #define DDRPHY_DX6GSR0_RDQSNCAL_MASK             (0x4U)
31346 #define DDRPHY_DX6GSR0_RDQSNCAL_SHIFT            (2U)
31347 /*! RDQSNCAL - Read DQS# Calibration
31348  */
31349 #define DDRPHY_DX6GSR0_RDQSNCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX6GSR0_RDQSNCAL_MASK)
31350 #define DDRPHY_DX6GSR0_GDQSCAL_MASK              (0x8U)
31351 #define DDRPHY_DX6GSR0_GDQSCAL_SHIFT             (3U)
31352 /*! GDQSCAL - Read DQS gating Calibration
31353  */
31354 #define DDRPHY_DX6GSR0_GDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX6GSR0_GDQSCAL_MASK)
31355 #define DDRPHY_DX6GSR0_WLCAL_MASK                (0x10U)
31356 #define DDRPHY_DX6GSR0_WLCAL_SHIFT               (4U)
31357 /*! WLCAL - Write Leveling Calibration
31358  */
31359 #define DDRPHY_DX6GSR0_WLCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLCAL_SHIFT)) & DDRPHY_DX6GSR0_WLCAL_MASK)
31360 #define DDRPHY_DX6GSR0_WLDONE_MASK               (0x20U)
31361 #define DDRPHY_DX6GSR0_WLDONE_SHIFT              (5U)
31362 /*! WLDONE - Write Leveling Done
31363  */
31364 #define DDRPHY_DX6GSR0_WLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLDONE_SHIFT)) & DDRPHY_DX6GSR0_WLDONE_MASK)
31365 #define DDRPHY_DX6GSR0_WLERR_MASK                (0x40U)
31366 #define DDRPHY_DX6GSR0_WLERR_SHIFT               (6U)
31367 /*! WLERR - Write Leveling Error
31368  */
31369 #define DDRPHY_DX6GSR0_WLERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLERR_SHIFT)) & DDRPHY_DX6GSR0_WLERR_MASK)
31370 #define DDRPHY_DX6GSR0_WLPRD_MASK                (0xFF80U)
31371 #define DDRPHY_DX6GSR0_WLPRD_SHIFT               (7U)
31372 /*! WLPRD - Write Leveling Period
31373  */
31374 #define DDRPHY_DX6GSR0_WLPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLPRD_SHIFT)) & DDRPHY_DX6GSR0_WLPRD_MASK)
31375 #define DDRPHY_DX6GSR0_DPLOCK_MASK               (0x10000U)
31376 #define DDRPHY_DX6GSR0_DPLOCK_SHIFT              (16U)
31377 /*! DPLOCK - DATX8 PLL Lock
31378  */
31379 #define DDRPHY_DX6GSR0_DPLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_DPLOCK_SHIFT)) & DDRPHY_DX6GSR0_DPLOCK_MASK)
31380 #define DDRPHY_DX6GSR0_GDQSPRD_MASK              (0x3FE0000U)
31381 #define DDRPHY_DX6GSR0_GDQSPRD_SHIFT             (17U)
31382 /*! GDQSPRD - Read DQS gating Period
31383  */
31384 #define DDRPHY_DX6GSR0_GDQSPRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX6GSR0_GDQSPRD_MASK)
31385 #define DDRPHY_DX6GSR0_RESERVED_29_26_MASK       (0x3C000000U)
31386 #define DDRPHY_DX6GSR0_RESERVED_29_26_SHIFT      (26U)
31387 /*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
31388  */
31389 #define DDRPHY_DX6GSR0_RESERVED_29_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX6GSR0_RESERVED_29_26_MASK)
31390 #define DDRPHY_DX6GSR0_WLDQ_MASK                 (0x40000000U)
31391 #define DDRPHY_DX6GSR0_WLDQ_SHIFT                (30U)
31392 /*! WLDQ - Write Leveling DQ Status
31393  */
31394 #define DDRPHY_DX6GSR0_WLDQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLDQ_SHIFT)) & DDRPHY_DX6GSR0_WLDQ_MASK)
31395 #define DDRPHY_DX6GSR0_RESERVED_31_MASK          (0x80000000U)
31396 #define DDRPHY_DX6GSR0_RESERVED_31_SHIFT         (31U)
31397 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
31398  */
31399 #define DDRPHY_DX6GSR0_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX6GSR0_RESERVED_31_MASK)
31400 /*! @} */
31401 
31402 /*! @name DX6GSR1 - DATX8 n General Status Register 1 */
31403 /*! @{ */
31404 #define DDRPHY_DX6GSR1_DLTDONE_MASK              (0x1U)
31405 #define DDRPHY_DX6GSR1_DLTDONE_SHIFT             (0U)
31406 /*! DLTDONE - Delay Line Test Done
31407  */
31408 #define DDRPHY_DX6GSR1_DLTDONE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR1_DLTDONE_SHIFT)) & DDRPHY_DX6GSR1_DLTDONE_MASK)
31409 #define DDRPHY_DX6GSR1_DLTCODE_MASK              (0x1FFFFFEU)
31410 #define DDRPHY_DX6GSR1_DLTCODE_SHIFT             (1U)
31411 /*! DLTCODE - Delay Line Test Code
31412  */
31413 #define DDRPHY_DX6GSR1_DLTCODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR1_DLTCODE_SHIFT)) & DDRPHY_DX6GSR1_DLTCODE_MASK)
31414 #define DDRPHY_DX6GSR1_RESERVED_31_25_MASK       (0xFE000000U)
31415 #define DDRPHY_DX6GSR1_RESERVED_31_25_SHIFT      (25U)
31416 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
31417  */
31418 #define DDRPHY_DX6GSR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX6GSR1_RESERVED_31_25_MASK)
31419 /*! @} */
31420 
31421 /*! @name DX6GSR2 - DATX8 n General Status Register 2 */
31422 /*! @{ */
31423 #define DDRPHY_DX6GSR2_RDERR_MASK                (0x1U)
31424 #define DDRPHY_DX6GSR2_RDERR_SHIFT               (0U)
31425 /*! RDERR - Read Bit Deskew Error
31426  */
31427 #define DDRPHY_DX6GSR2_RDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_RDERR_SHIFT)) & DDRPHY_DX6GSR2_RDERR_MASK)
31428 #define DDRPHY_DX6GSR2_RDWN_MASK                 (0x2U)
31429 #define DDRPHY_DX6GSR2_RDWN_SHIFT                (1U)
31430 /*! RDWN - Read Bit Deskew Warning
31431  */
31432 #define DDRPHY_DX6GSR2_RDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_RDWN_SHIFT)) & DDRPHY_DX6GSR2_RDWN_MASK)
31433 #define DDRPHY_DX6GSR2_WDERR_MASK                (0x4U)
31434 #define DDRPHY_DX6GSR2_WDERR_SHIFT               (2U)
31435 /*! WDERR - Write Bit Deskew Error
31436  */
31437 #define DDRPHY_DX6GSR2_WDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WDERR_SHIFT)) & DDRPHY_DX6GSR2_WDERR_MASK)
31438 #define DDRPHY_DX6GSR2_WDWN_MASK                 (0x8U)
31439 #define DDRPHY_DX6GSR2_WDWN_SHIFT                (3U)
31440 /*! WDWN - Write Bit Deskew Warning
31441  */
31442 #define DDRPHY_DX6GSR2_WDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WDWN_SHIFT)) & DDRPHY_DX6GSR2_WDWN_MASK)
31443 #define DDRPHY_DX6GSR2_REERR_MASK                (0x10U)
31444 #define DDRPHY_DX6GSR2_REERR_SHIFT               (4U)
31445 /*! REERR - Read Eye Centering Error
31446  */
31447 #define DDRPHY_DX6GSR2_REERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_REERR_SHIFT)) & DDRPHY_DX6GSR2_REERR_MASK)
31448 #define DDRPHY_DX6GSR2_REWN_MASK                 (0x20U)
31449 #define DDRPHY_DX6GSR2_REWN_SHIFT                (5U)
31450 /*! REWN - Read Eye Centering Warning
31451  */
31452 #define DDRPHY_DX6GSR2_REWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_REWN_SHIFT)) & DDRPHY_DX6GSR2_REWN_MASK)
31453 #define DDRPHY_DX6GSR2_WEERR_MASK                (0x40U)
31454 #define DDRPHY_DX6GSR2_WEERR_SHIFT               (6U)
31455 /*! WEERR - Write Eye Centering Error
31456  */
31457 #define DDRPHY_DX6GSR2_WEERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WEERR_SHIFT)) & DDRPHY_DX6GSR2_WEERR_MASK)
31458 #define DDRPHY_DX6GSR2_WEWN_MASK                 (0x80U)
31459 #define DDRPHY_DX6GSR2_WEWN_SHIFT                (7U)
31460 /*! WEWN - Write Eye Centering Warning
31461  */
31462 #define DDRPHY_DX6GSR2_WEWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WEWN_SHIFT)) & DDRPHY_DX6GSR2_WEWN_MASK)
31463 #define DDRPHY_DX6GSR2_ESTAT_MASK                (0xF00U)
31464 #define DDRPHY_DX6GSR2_ESTAT_SHIFT               (8U)
31465 /*! ESTAT - Error Status
31466  */
31467 #define DDRPHY_DX6GSR2_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_ESTAT_SHIFT)) & DDRPHY_DX6GSR2_ESTAT_MASK)
31468 #define DDRPHY_DX6GSR2_DQS2DQERR_MASK            (0xFF000U)
31469 #define DDRPHY_DX6GSR2_DQS2DQERR_SHIFT           (12U)
31470 /*! DQS2DQERR - Write DQS2DQ Training Error
31471  */
31472 #define DDRPHY_DX6GSR2_DQS2DQERR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX6GSR2_DQS2DQERR_MASK)
31473 #define DDRPHY_DX6GSR2_SRDERR_MASK               (0x100000U)
31474 #define DDRPHY_DX6GSR2_SRDERR_SHIFT              (20U)
31475 /*! SRDERR - Static Read Error
31476  */
31477 #define DDRPHY_DX6GSR2_SRDERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_SRDERR_SHIFT)) & DDRPHY_DX6GSR2_SRDERR_MASK)
31478 #define DDRPHY_DX6GSR2_RESERVED_21_MASK          (0x200000U)
31479 #define DDRPHY_DX6GSR2_RESERVED_21_SHIFT         (21U)
31480 /*! RESERVED_21 - Reserved. Return zeroes on reads.
31481  */
31482 #define DDRPHY_DX6GSR2_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX6GSR2_RESERVED_21_MASK)
31483 #define DDRPHY_DX6GSR2_GSDQSCAL_MASK             (0x400000U)
31484 #define DDRPHY_DX6GSR2_GSDQSCAL_SHIFT            (22U)
31485 /*! GSDQSCAL - Read DQS Gating Status Calibration
31486  */
31487 #define DDRPHY_DX6GSR2_GSDQSCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX6GSR2_GSDQSCAL_MASK)
31488 #define DDRPHY_DX6GSR2_GSDQSPRD_MASK             (0xFF800000U)
31489 #define DDRPHY_DX6GSR2_GSDQSPRD_SHIFT            (23U)
31490 /*! GSDQSPRD - Read DQS gating Status Period
31491  */
31492 #define DDRPHY_DX6GSR2_GSDQSPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX6GSR2_GSDQSPRD_MASK)
31493 /*! @} */
31494 
31495 /*! @name DX6GSR3 - DATX8 n General Status Register 3 */
31496 /*! @{ */
31497 #define DDRPHY_DX6GSR3_SRDPC_MASK                (0x3U)
31498 #define DDRPHY_DX6GSR3_SRDPC_SHIFT               (0U)
31499 /*! SRDPC - Static Read Delay Pass Count
31500  */
31501 #define DDRPHY_DX6GSR3_SRDPC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_SRDPC_SHIFT)) & DDRPHY_DX6GSR3_SRDPC_MASK)
31502 #define DDRPHY_DX6GSR3_RESERVED_7_2_MASK         (0xFCU)
31503 #define DDRPHY_DX6GSR3_RESERVED_7_2_SHIFT        (2U)
31504 /*! RESERVED_7_2 - Reserved. Return zeroes on reads.
31505  */
31506 #define DDRPHY_DX6GSR3_RESERVED_7_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX6GSR3_RESERVED_7_2_MASK)
31507 #define DDRPHY_DX6GSR3_HVERR_MASK                (0xF00U)
31508 #define DDRPHY_DX6GSR3_HVERR_SHIFT               (8U)
31509 /*! HVERR - Host VREF Training Error
31510  */
31511 #define DDRPHY_DX6GSR3_HVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_HVERR_SHIFT)) & DDRPHY_DX6GSR3_HVERR_MASK)
31512 #define DDRPHY_DX6GSR3_HVWRN_MASK                (0xF000U)
31513 #define DDRPHY_DX6GSR3_HVWRN_SHIFT               (12U)
31514 /*! HVWRN - Host VREF Training Warning
31515  */
31516 #define DDRPHY_DX6GSR3_HVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_HVWRN_SHIFT)) & DDRPHY_DX6GSR3_HVWRN_MASK)
31517 #define DDRPHY_DX6GSR3_DVERR_MASK                (0xF0000U)
31518 #define DDRPHY_DX6GSR3_DVERR_SHIFT               (16U)
31519 /*! DVERR - DRAM VREF Training Error
31520  */
31521 #define DDRPHY_DX6GSR3_DVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_DVERR_SHIFT)) & DDRPHY_DX6GSR3_DVERR_MASK)
31522 #define DDRPHY_DX6GSR3_DVWRN_MASK                (0xF00000U)
31523 #define DDRPHY_DX6GSR3_DVWRN_SHIFT               (20U)
31524 /*! DVWRN - DRAM VREF Training Warning
31525  */
31526 #define DDRPHY_DX6GSR3_DVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_DVWRN_SHIFT)) & DDRPHY_DX6GSR3_DVWRN_MASK)
31527 #define DDRPHY_DX6GSR3_ESTAT_MASK                (0x7000000U)
31528 #define DDRPHY_DX6GSR3_ESTAT_SHIFT               (24U)
31529 /*! ESTAT - VREF Training Error Status Code
31530  */
31531 #define DDRPHY_DX6GSR3_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_ESTAT_SHIFT)) & DDRPHY_DX6GSR3_ESTAT_MASK)
31532 #define DDRPHY_DX6GSR3_RESERVED_31_27_MASK       (0xF8000000U)
31533 #define DDRPHY_DX6GSR3_RESERVED_31_27_SHIFT      (27U)
31534 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
31535  */
31536 #define DDRPHY_DX6GSR3_RESERVED_31_27(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX6GSR3_RESERVED_31_27_MASK)
31537 /*! @} */
31538 
31539 /*! @name DX6GSR4 - DATX8 n General Status Register 4 */
31540 /*! @{ */
31541 #define DDRPHY_DX6GSR4_RESERVED_0_MASK           (0x1U)
31542 #define DDRPHY_DX6GSR4_RESERVED_0_SHIFT          (0U)
31543 /*! RESERVED_0 - Reserved. Return zeroes on reads.
31544  */
31545 #define DDRPHY_DX6GSR4_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_0_MASK)
31546 #define DDRPHY_DX6GSR4_RESERVED_1_MASK           (0x2U)
31547 #define DDRPHY_DX6GSR4_RESERVED_1_SHIFT          (1U)
31548 /*! RESERVED_1 - Reserved. Return zeroes on reads.
31549  */
31550 #define DDRPHY_DX6GSR4_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_1_MASK)
31551 #define DDRPHY_DX6GSR4_RESERVED_2_MASK           (0x4U)
31552 #define DDRPHY_DX6GSR4_RESERVED_2_SHIFT          (2U)
31553 /*! RESERVED_2 - Reserved. Return zeroes on reads.
31554  */
31555 #define DDRPHY_DX6GSR4_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_2_MASK)
31556 #define DDRPHY_DX6GSR4_RESERVED_3_MASK           (0x8U)
31557 #define DDRPHY_DX6GSR4_RESERVED_3_SHIFT          (3U)
31558 /*! RESERVED_3 - Reserved. Return zeroes on reads.
31559  */
31560 #define DDRPHY_DX6GSR4_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_3_MASK)
31561 #define DDRPHY_DX6GSR4_RESERVED_4_MASK           (0x10U)
31562 #define DDRPHY_DX6GSR4_RESERVED_4_SHIFT          (4U)
31563 /*! RESERVED_4 - Reserved. Return zeroes on reads.
31564  */
31565 #define DDRPHY_DX6GSR4_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_4_MASK)
31566 #define DDRPHY_DX6GSR4_RESERVED_5_MASK           (0x20U)
31567 #define DDRPHY_DX6GSR4_RESERVED_5_SHIFT          (5U)
31568 /*! RESERVED_5 - Reserved. Return zeroes on reads.
31569  */
31570 #define DDRPHY_DX6GSR4_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_5_MASK)
31571 #define DDRPHY_DX6GSR4_RESERVED_6_MASK           (0x40U)
31572 #define DDRPHY_DX6GSR4_RESERVED_6_SHIFT          (6U)
31573 /*! RESERVED_6 - Reserved. Return zeroes on reads.
31574  */
31575 #define DDRPHY_DX6GSR4_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_6_MASK)
31576 #define DDRPHY_DX6GSR4_RESERVED_15_7_MASK        (0xFF80U)
31577 #define DDRPHY_DX6GSR4_RESERVED_15_7_SHIFT       (7U)
31578 /*! RESERVED_15_7 - Reserved. Return zeroes on reads.
31579  */
31580 #define DDRPHY_DX6GSR4_RESERVED_15_7(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_15_7_MASK)
31581 #define DDRPHY_DX6GSR4_RESERVED_16_MASK          (0x10000U)
31582 #define DDRPHY_DX6GSR4_RESERVED_16_SHIFT         (16U)
31583 /*! RESERVED_16 - Reserved. Return zeroes on reads.
31584  */
31585 #define DDRPHY_DX6GSR4_RESERVED_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_16_MASK)
31586 #define DDRPHY_DX6GSR4_RESERVED_25_17_MASK       (0x3FE0000U)
31587 #define DDRPHY_DX6GSR4_RESERVED_25_17_SHIFT      (17U)
31588 /*! RESERVED_25_17 - Reserved. Return zeroes on reads.
31589  */
31590 #define DDRPHY_DX6GSR4_RESERVED_25_17(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_25_17_MASK)
31591 #define DDRPHY_DX6GSR4_RESERVED_31_26_MASK       (0xFC000000U)
31592 #define DDRPHY_DX6GSR4_RESERVED_31_26_SHIFT      (26U)
31593 /*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
31594  */
31595 #define DDRPHY_DX6GSR4_RESERVED_31_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_31_26_MASK)
31596 /*! @} */
31597 
31598 /*! @name DX6GSR5 - DATX8 n General Status Register 5 */
31599 /*! @{ */
31600 #define DDRPHY_DX6GSR5_RESERVED_0_MASK           (0x1U)
31601 #define DDRPHY_DX6GSR5_RESERVED_0_SHIFT          (0U)
31602 /*! RESERVED_0 - Reserved. Return zeroes on reads.
31603  */
31604 #define DDRPHY_DX6GSR5_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_0_MASK)
31605 #define DDRPHY_DX6GSR5_RESERVED_1_MASK           (0x2U)
31606 #define DDRPHY_DX6GSR5_RESERVED_1_SHIFT          (1U)
31607 /*! RESERVED_1 - Reserved. Return zeroes on reads.
31608  */
31609 #define DDRPHY_DX6GSR5_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_1_MASK)
31610 #define DDRPHY_DX6GSR5_RESERVED_2_MASK           (0x4U)
31611 #define DDRPHY_DX6GSR5_RESERVED_2_SHIFT          (2U)
31612 /*! RESERVED_2 - Reserved. Return zeroes on reads.
31613  */
31614 #define DDRPHY_DX6GSR5_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_2_MASK)
31615 #define DDRPHY_DX6GSR5_RESERVED_3_MASK           (0x8U)
31616 #define DDRPHY_DX6GSR5_RESERVED_3_SHIFT          (3U)
31617 /*! RESERVED_3 - Reserved. Return zeroes on reads.
31618  */
31619 #define DDRPHY_DX6GSR5_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_3_MASK)
31620 #define DDRPHY_DX6GSR5_RESERVED_4_MASK           (0x10U)
31621 #define DDRPHY_DX6GSR5_RESERVED_4_SHIFT          (4U)
31622 /*! RESERVED_4 - Reserved. Return zeroes on reads.
31623  */
31624 #define DDRPHY_DX6GSR5_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_4_MASK)
31625 #define DDRPHY_DX6GSR5_RESERVED_5_MASK           (0x20U)
31626 #define DDRPHY_DX6GSR5_RESERVED_5_SHIFT          (5U)
31627 /*! RESERVED_5 - Reserved. Return zeroes on reads.
31628  */
31629 #define DDRPHY_DX6GSR5_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_5_MASK)
31630 #define DDRPHY_DX6GSR5_RESERVED_6_MASK           (0x40U)
31631 #define DDRPHY_DX6GSR5_RESERVED_6_SHIFT          (6U)
31632 /*! RESERVED_6 - Reserved. Return zeroes on reads.
31633  */
31634 #define DDRPHY_DX6GSR5_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_6_MASK)
31635 #define DDRPHY_DX6GSR5_RESERVED_7_MASK           (0x80U)
31636 #define DDRPHY_DX6GSR5_RESERVED_7_SHIFT          (7U)
31637 /*! RESERVED_7 - Reserved. Return zeroes on reads.
31638  */
31639 #define DDRPHY_DX6GSR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_7_MASK)
31640 #define DDRPHY_DX6GSR5_RESERVED_11_8_MASK        (0xF00U)
31641 #define DDRPHY_DX6GSR5_RESERVED_11_8_SHIFT       (8U)
31642 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
31643  */
31644 #define DDRPHY_DX6GSR5_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_11_8_MASK)
31645 #define DDRPHY_DX6GSR5_RESERVED_19_12_MASK       (0xFF000U)
31646 #define DDRPHY_DX6GSR5_RESERVED_19_12_SHIFT      (12U)
31647 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
31648  */
31649 #define DDRPHY_DX6GSR5_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_19_12_MASK)
31650 #define DDRPHY_DX6GSR5_RESERVED_20_MASK          (0x100000U)
31651 #define DDRPHY_DX6GSR5_RESERVED_20_SHIFT         (20U)
31652 /*! RESERVED_20 - Reserved. Return zeroes on reads.
31653  */
31654 #define DDRPHY_DX6GSR5_RESERVED_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_20_MASK)
31655 #define DDRPHY_DX6GSR5_RESERVED_21_MASK          (0x200000U)
31656 #define DDRPHY_DX6GSR5_RESERVED_21_SHIFT         (21U)
31657 /*! RESERVED_21 - Reserved. Return zeroes on reads.
31658  */
31659 #define DDRPHY_DX6GSR5_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_21_MASK)
31660 #define DDRPHY_DX6GSR5_RESERVED_22_MASK          (0x400000U)
31661 #define DDRPHY_DX6GSR5_RESERVED_22_SHIFT         (22U)
31662 /*! RESERVED_22 - Reserved. Return zeroes on reads.
31663  */
31664 #define DDRPHY_DX6GSR5_RESERVED_22(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_22_MASK)
31665 #define DDRPHY_DX6GSR5_RESERVED_31_23_MASK       (0xFF800000U)
31666 #define DDRPHY_DX6GSR5_RESERVED_31_23_SHIFT      (23U)
31667 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
31668  */
31669 #define DDRPHY_DX6GSR5_RESERVED_31_23(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_31_23_MASK)
31670 /*! @} */
31671 
31672 /*! @name DX6GSR6 - DATX8 n General Status Register 6 */
31673 /*! @{ */
31674 #define DDRPHY_DX6GSR6_RESERVED_1_0_MASK         (0x3U)
31675 #define DDRPHY_DX6GSR6_RESERVED_1_0_SHIFT        (0U)
31676 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
31677  */
31678 #define DDRPHY_DX6GSR6_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_1_0_MASK)
31679 #define DDRPHY_DX6GSR6_RESERVED_3_2_MASK         (0xCU)
31680 #define DDRPHY_DX6GSR6_RESERVED_3_2_SHIFT        (2U)
31681 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
31682  */
31683 #define DDRPHY_DX6GSR6_RESERVED_3_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_3_2_MASK)
31684 #define DDRPHY_DX6GSR6_RESERVED_7_4_MASK         (0xF0U)
31685 #define DDRPHY_DX6GSR6_RESERVED_7_4_SHIFT        (4U)
31686 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
31687  */
31688 #define DDRPHY_DX6GSR6_RESERVED_7_4(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_7_4_MASK)
31689 #define DDRPHY_DX6GSR6_RESERVED_11_8_MASK        (0xF00U)
31690 #define DDRPHY_DX6GSR6_RESERVED_11_8_SHIFT       (8U)
31691 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
31692  */
31693 #define DDRPHY_DX6GSR6_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_11_8_MASK)
31694 #define DDRPHY_DX6GSR6_RESERVED_15_12_MASK       (0xF000U)
31695 #define DDRPHY_DX6GSR6_RESERVED_15_12_SHIFT      (12U)
31696 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
31697  */
31698 #define DDRPHY_DX6GSR6_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_15_12_MASK)
31699 #define DDRPHY_DX6GSR6_RESERVED_19_15_MASK       (0xF0000U)
31700 #define DDRPHY_DX6GSR6_RESERVED_19_15_SHIFT      (16U)
31701 /*! RESERVED_19_15 - Reserved. Return zeroes on reads.
31702  */
31703 #define DDRPHY_DX6GSR6_RESERVED_19_15(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_19_15_MASK)
31704 #define DDRPHY_DX6GSR6_RESERVED_23_20_MASK       (0xF00000U)
31705 #define DDRPHY_DX6GSR6_RESERVED_23_20_SHIFT      (20U)
31706 /*! RESERVED_23_20 - Reserved. Return zeroes on reads.
31707  */
31708 #define DDRPHY_DX6GSR6_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_23_20_MASK)
31709 #define DDRPHY_DX6GSR6_RESERVED_31_24_MASK       (0xFF000000U)
31710 #define DDRPHY_DX6GSR6_RESERVED_31_24_SHIFT      (24U)
31711 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
31712  */
31713 #define DDRPHY_DX6GSR6_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_31_24_MASK)
31714 /*! @} */
31715 
31716 /*! @name DX7GCR0 - DATX8 n General Configuration Register 0 */
31717 /*! @{ */
31718 #define DDRPHY_DX7GCR0_RESERVED_1_0_MASK         (0x3U)
31719 #define DDRPHY_DX7GCR0_RESERVED_1_0_SHIFT        (0U)
31720 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
31721  */
31722 #define DDRPHY_DX7GCR0_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX7GCR0_RESERVED_1_0_MASK)
31723 #define DDRPHY_DX7GCR0_DQSGOE_MASK               (0x4U)
31724 #define DDRPHY_DX7GCR0_DQSGOE_SHIFT              (2U)
31725 /*! DQSGOE - DQSG Output Enable
31726  */
31727 #define DDRPHY_DX7GCR0_DQSGOE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSGOE_SHIFT)) & DDRPHY_DX7GCR0_DQSGOE_MASK)
31728 #define DDRPHY_DX7GCR0_DQSGODT_MASK              (0x8U)
31729 #define DDRPHY_DX7GCR0_DQSGODT_SHIFT             (3U)
31730 /*! DQSGODT - DQSG On-Die Termination
31731  */
31732 #define DDRPHY_DX7GCR0_DQSGODT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSGODT_SHIFT)) & DDRPHY_DX7GCR0_DQSGODT_MASK)
31733 #define DDRPHY_DX7GCR0_RESERVED_4_MASK           (0x10U)
31734 #define DDRPHY_DX7GCR0_RESERVED_4_SHIFT          (4U)
31735 /*! RESERVED_4 - Reserved. Return zeroes on reads.
31736  */
31737 #define DDRPHY_DX7GCR0_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX7GCR0_RESERVED_4_MASK)
31738 #define DDRPHY_DX7GCR0_DQSGPDR_MASK              (0x20U)
31739 #define DDRPHY_DX7GCR0_DQSGPDR_SHIFT             (5U)
31740 /*! DQSGPDR - DQSG Power Down Receiver
31741  */
31742 #define DDRPHY_DX7GCR0_DQSGPDR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX7GCR0_DQSGPDR_MASK)
31743 #define DDRPHY_DX7GCR0_DQSRPD_MASK               (0x40U)
31744 #define DDRPHY_DX7GCR0_DQSRPD_SHIFT              (6U)
31745 /*! DQSRPD - DQSR Power Down
31746  */
31747 #define DDRPHY_DX7GCR0_DQSRPD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSRPD_SHIFT)) & DDRPHY_DX7GCR0_DQSRPD_MASK)
31748 #define DDRPHY_DX7GCR0_CPDRSHFT_MASK             (0x180U)
31749 #define DDRPHY_DX7GCR0_CPDRSHFT_SHIFT            (7U)
31750 /*! CPDRSHFT - Configurable PDR Phase Shift
31751  */
31752 #define DDRPHY_DX7GCR0_CPDRSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX7GCR0_CPDRSHFT_MASK)
31753 #define DDRPHY_DX7GCR0_RTTOH_MASK                (0x600U)
31754 #define DDRPHY_DX7GCR0_RTTOH_SHIFT               (9U)
31755 /*! RTTOH - RTT Output Hold
31756  */
31757 #define DDRPHY_DX7GCR0_RTTOH(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RTTOH_SHIFT)) & DDRPHY_DX7GCR0_RTTOH_MASK)
31758 #define DDRPHY_DX7GCR0_RTTOAL_MASK               (0x800U)
31759 #define DDRPHY_DX7GCR0_RTTOAL_SHIFT              (11U)
31760 /*! RTTOAL - RTT On Additive Latency
31761  */
31762 #define DDRPHY_DX7GCR0_RTTOAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RTTOAL_SHIFT)) & DDRPHY_DX7GCR0_RTTOAL_MASK)
31763 #define DDRPHY_DX7GCR0_DQSSEPDR_MASK             (0x1000U)
31764 #define DDRPHY_DX7GCR0_DQSSEPDR_SHIFT            (12U)
31765 /*! DQSSEPDR - DQSSE Power Down Receiver
31766  */
31767 #define DDRPHY_DX7GCR0_DQSSEPDR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX7GCR0_DQSSEPDR_MASK)
31768 #define DDRPHY_DX7GCR0_DQSNSEPDR_MASK            (0x2000U)
31769 #define DDRPHY_DX7GCR0_DQSNSEPDR_SHIFT           (13U)
31770 /*! DQSNSEPDR - DQSNSE Power Down Receiver
31771  */
31772 #define DDRPHY_DX7GCR0_DQSNSEPDR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX7GCR0_DQSNSEPDR_MASK)
31773 #define DDRPHY_DX7GCR0_RESERVED_19_14_MASK       (0xFC000U)
31774 #define DDRPHY_DX7GCR0_RESERVED_19_14_SHIFT      (14U)
31775 /*! RESERVED_19_14 - Reserved. Return zeroes on reads.
31776  */
31777 #define DDRPHY_DX7GCR0_RESERVED_19_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX7GCR0_RESERVED_19_14_MASK)
31778 #define DDRPHY_DX7GCR0_RDDLY_MASK                (0xF00000U)
31779 #define DDRPHY_DX7GCR0_RDDLY_SHIFT               (20U)
31780 /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
31781  */
31782 #define DDRPHY_DX7GCR0_RDDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RDDLY_SHIFT)) & DDRPHY_DX7GCR0_RDDLY_MASK)
31783 #define DDRPHY_DX7GCR0_DQSDCC_MASK               (0xF000000U)
31784 #define DDRPHY_DX7GCR0_DQSDCC_SHIFT              (24U)
31785 /*! DQSDCC - DQS Duty Cycle Correction
31786  */
31787 #define DDRPHY_DX7GCR0_DQSDCC(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSDCC_SHIFT)) & DDRPHY_DX7GCR0_DQSDCC_MASK)
31788 #define DDRPHY_DX7GCR0_CODTSHFT_MASK             (0x30000000U)
31789 #define DDRPHY_DX7GCR0_CODTSHFT_SHIFT            (28U)
31790 /*! CODTSHFT - Configurable ODT(TE) Phase Shift
31791  */
31792 #define DDRPHY_DX7GCR0_CODTSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX7GCR0_CODTSHFT_MASK)
31793 #define DDRPHY_DX7GCR0_MDLEN_MASK                (0x40000000U)
31794 #define DDRPHY_DX7GCR0_MDLEN_SHIFT               (30U)
31795 /*! MDLEN - Master Delay Line Enable
31796  */
31797 #define DDRPHY_DX7GCR0_MDLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_MDLEN_SHIFT)) & DDRPHY_DX7GCR0_MDLEN_MASK)
31798 #define DDRPHY_DX7GCR0_CALBYP_MASK               (0x80000000U)
31799 #define DDRPHY_DX7GCR0_CALBYP_SHIFT              (31U)
31800 /*! CALBYP - Calibration Bypass
31801  */
31802 #define DDRPHY_DX7GCR0_CALBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_CALBYP_SHIFT)) & DDRPHY_DX7GCR0_CALBYP_MASK)
31803 /*! @} */
31804 
31805 /*! @name DX7GCR1 - DATX8 n General Configuration Register 1 */
31806 /*! @{ */
31807 #define DDRPHY_DX7GCR1_DQEN_MASK                 (0xFFU)
31808 #define DDRPHY_DX7GCR1_DQEN_SHIFT                (0U)
31809 /*! DQEN - Enables DQ corresponding to each bit in a byte
31810  */
31811 #define DDRPHY_DX7GCR1_DQEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DQEN_SHIFT)) & DDRPHY_DX7GCR1_DQEN_MASK)
31812 #define DDRPHY_DX7GCR1_DMEN_MASK                 (0x100U)
31813 #define DDRPHY_DX7GCR1_DMEN_SHIFT                (8U)
31814 /*! DMEN - Enables DM pin in a byte lane
31815  */
31816 #define DDRPHY_DX7GCR1_DMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DMEN_SHIFT)) & DDRPHY_DX7GCR1_DMEN_MASK)
31817 #define DDRPHY_DX7GCR1_DSEN_MASK                 (0x200U)
31818 #define DDRPHY_DX7GCR1_DSEN_SHIFT                (9U)
31819 /*! DSEN - Enables Write Data strobe in a byte lane
31820  */
31821 #define DDRPHY_DX7GCR1_DSEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DSEN_SHIFT)) & DDRPHY_DX7GCR1_DSEN_MASK)
31822 #define DDRPHY_DX7GCR1_TEEN_MASK                 (0x400U)
31823 #define DDRPHY_DX7GCR1_TEEN_SHIFT                (10U)
31824 /*! TEEN - Enables ODT/TE in a byte lane
31825  */
31826 #define DDRPHY_DX7GCR1_TEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_TEEN_SHIFT)) & DDRPHY_DX7GCR1_TEEN_MASK)
31827 #define DDRPHY_DX7GCR1_PDREN_MASK                (0x800U)
31828 #define DDRPHY_DX7GCR1_PDREN_SHIFT               (11U)
31829 /*! PDREN - Enables PDR in a byte lane
31830  */
31831 #define DDRPHY_DX7GCR1_PDREN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_PDREN_SHIFT)) & DDRPHY_DX7GCR1_PDREN_MASK)
31832 #define DDRPHY_DX7GCR1_OEEN_MASK                 (0x1000U)
31833 #define DDRPHY_DX7GCR1_OEEN_SHIFT                (12U)
31834 /*! OEEN - Enables Read Data Strobe in a byte lane
31835  */
31836 #define DDRPHY_DX7GCR1_OEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_OEEN_SHIFT)) & DDRPHY_DX7GCR1_OEEN_MASK)
31837 #define DDRPHY_DX7GCR1_QSSEL_MASK                (0x2000U)
31838 #define DDRPHY_DX7GCR1_QSSEL_SHIFT               (13U)
31839 /*! QSSEL - Select the delayed or non-delayed read data strobe
31840  */
31841 #define DDRPHY_DX7GCR1_QSSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_QSSEL_SHIFT)) & DDRPHY_DX7GCR1_QSSEL_MASK)
31842 #define DDRPHY_DX7GCR1_QSNSEL_MASK               (0x4000U)
31843 #define DDRPHY_DX7GCR1_QSNSEL_SHIFT              (14U)
31844 /*! QSNSEL - Select the delayed or non-delayed read data strobe #
31845  */
31846 #define DDRPHY_DX7GCR1_QSNSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_QSNSEL_SHIFT)) & DDRPHY_DX7GCR1_QSNSEL_MASK)
31847 #define DDRPHY_DX7GCR1_RESERVED_15_MASK          (0x8000U)
31848 #define DDRPHY_DX7GCR1_RESERVED_15_SHIFT         (15U)
31849 /*! RESERVED_15 - Reserved. Returns zeroes on reads.
31850  */
31851 #define DDRPHY_DX7GCR1_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX7GCR1_RESERVED_15_MASK)
31852 #define DDRPHY_DX7GCR1_DXPDRMODE_MASK            (0xFFFF0000U)
31853 #define DDRPHY_DX7GCR1_DXPDRMODE_SHIFT           (16U)
31854 /*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
31855  */
31856 #define DDRPHY_DX7GCR1_DXPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX7GCR1_DXPDRMODE_MASK)
31857 /*! @} */
31858 
31859 /*! @name DX7GCR2 - DATX8 n General Configuration Register 2 */
31860 /*! @{ */
31861 #define DDRPHY_DX7GCR2_DXTEMODE_MASK             (0xFFFFU)
31862 #define DDRPHY_DX7GCR2_DXTEMODE_SHIFT            (0U)
31863 /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
31864  */
31865 #define DDRPHY_DX7GCR2_DXTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX7GCR2_DXTEMODE_MASK)
31866 #define DDRPHY_DX7GCR2_DXOEMODE_MASK             (0xFFFF0000U)
31867 #define DDRPHY_DX7GCR2_DXOEMODE_SHIFT            (16U)
31868 /*! DXOEMODE - Enables the OE mode values for DQ[7:0]
31869  */
31870 #define DDRPHY_DX7GCR2_DXOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX7GCR2_DXOEMODE_MASK)
31871 /*! @} */
31872 
31873 /*! @name DX7GCR3 - DATX8 n General Configuration Register 3 */
31874 /*! @{ */
31875 #define DDRPHY_DX7GCR3_WDMBVT_MASK               (0x1U)
31876 #define DDRPHY_DX7GCR3_WDMBVT_SHIFT              (0U)
31877 /*! WDMBVT - Write Data Mask BDL VT Compensation
31878  */
31879 #define DDRPHY_DX7GCR3_WDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDMBVT_SHIFT)) & DDRPHY_DX7GCR3_WDMBVT_MASK)
31880 #define DDRPHY_DX7GCR3_RDMBVT_MASK               (0x2U)
31881 #define DDRPHY_DX7GCR3_RDMBVT_SHIFT              (1U)
31882 /*! RDMBVT - Read Data Mask BDL VT Compensation
31883  */
31884 #define DDRPHY_DX7GCR3_RDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RDMBVT_SHIFT)) & DDRPHY_DX7GCR3_RDMBVT_MASK)
31885 #define DDRPHY_DX7GCR3_DSPDRMODE_MASK            (0xCU)
31886 #define DDRPHY_DX7GCR3_DSPDRMODE_SHIFT           (2U)
31887 /*! DSPDRMODE - Enables the PDR mode values for DQS.
31888  */
31889 #define DDRPHY_DX7GCR3_DSPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX7GCR3_DSPDRMODE_MASK)
31890 #define DDRPHY_DX7GCR3_DSTEMODE_MASK             (0x30U)
31891 #define DDRPHY_DX7GCR3_DSTEMODE_SHIFT            (4U)
31892 /*! DSTEMODE - Enables the TE mode values for DQS.
31893  */
31894 #define DDRPHY_DX7GCR3_DSTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSTEMODE_MASK)
31895 #define DDRPHY_DX7GCR3_DSOEMODE_MASK             (0xC0U)
31896 #define DDRPHY_DX7GCR3_DSOEMODE_SHIFT            (6U)
31897 /*! DSOEMODE - Enables the OE mode values for DQS.
31898  */
31899 #define DDRPHY_DX7GCR3_DSOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSOEMODE_MASK)
31900 #define DDRPHY_DX7GCR3_WDSBVT_MASK               (0x100U)
31901 #define DDRPHY_DX7GCR3_WDSBVT_SHIFT              (8U)
31902 /*! WDSBVT - Write Data Strobe BDL VT Compensation
31903  */
31904 #define DDRPHY_DX7GCR3_WDSBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDSBVT_SHIFT)) & DDRPHY_DX7GCR3_WDSBVT_MASK)
31905 #define DDRPHY_DX7GCR3_RESERVED_9_MASK           (0x200U)
31906 #define DDRPHY_DX7GCR3_RESERVED_9_SHIFT          (9U)
31907 /*! RESERVED_9 - Reserved. Returns zeroes on reads.
31908  */
31909 #define DDRPHY_DX7GCR3_RESERVED_9(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX7GCR3_RESERVED_9_MASK)
31910 #define DDRPHY_DX7GCR3_DMPDRMODE_MASK            (0xC00U)
31911 #define DDRPHY_DX7GCR3_DMPDRMODE_SHIFT           (10U)
31912 /*! DMPDRMODE - Enables the PDR mode values for DM.
31913  */
31914 #define DDRPHY_DX7GCR3_DMPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX7GCR3_DMPDRMODE_MASK)
31915 #define DDRPHY_DX7GCR3_DMTEMODE_MASK             (0x3000U)
31916 #define DDRPHY_DX7GCR3_DMTEMODE_SHIFT            (12U)
31917 /*! DMTEMODE - Enables the TE mode values for DM.
31918  */
31919 #define DDRPHY_DX7GCR3_DMTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX7GCR3_DMTEMODE_MASK)
31920 #define DDRPHY_DX7GCR3_DMOEMODE_MASK             (0xC000U)
31921 #define DDRPHY_DX7GCR3_DMOEMODE_SHIFT            (14U)
31922 /*! DMOEMODE - Enables the OE mode values for DM.
31923  */
31924 #define DDRPHY_DX7GCR3_DMOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX7GCR3_DMOEMODE_MASK)
31925 #define DDRPHY_DX7GCR3_DSNPDRMODE_MASK           (0x30000U)
31926 #define DDRPHY_DX7GCR3_DSNPDRMODE_SHIFT          (16U)
31927 /*! DSNPDRMODE - Enables the PDR mode for DQS
31928  */
31929 #define DDRPHY_DX7GCR3_DSNPDRMODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX7GCR3_DSNPDRMODE_MASK)
31930 #define DDRPHY_DX7GCR3_DSNTEMODE_MASK            (0xC0000U)
31931 #define DDRPHY_DX7GCR3_DSNTEMODE_SHIFT           (18U)
31932 /*! DSNTEMODE - Enables the TE mode for DQS
31933  */
31934 #define DDRPHY_DX7GCR3_DSNTEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSNTEMODE_MASK)
31935 #define DDRPHY_DX7GCR3_DSNOEMODE_MASK            (0x300000U)
31936 #define DDRPHY_DX7GCR3_DSNOEMODE_SHIFT           (20U)
31937 /*! DSNOEMODE - Enables the OE mode for DQs
31938  */
31939 #define DDRPHY_DX7GCR3_DSNOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSNOEMODE_MASK)
31940 #define DDRPHY_DX7GCR3_PDRBVT_MASK               (0x400000U)
31941 #define DDRPHY_DX7GCR3_PDRBVT_SHIFT              (22U)
31942 /*! PDRBVT - Power Down Receiver BDL VT Compensation
31943  */
31944 #define DDRPHY_DX7GCR3_PDRBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_PDRBVT_SHIFT)) & DDRPHY_DX7GCR3_PDRBVT_MASK)
31945 #define DDRPHY_DX7GCR3_RGSLVT_MASK               (0x800000U)
31946 #define DDRPHY_DX7GCR3_RGSLVT_SHIFT              (23U)
31947 /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
31948  */
31949 #define DDRPHY_DX7GCR3_RGSLVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RGSLVT_SHIFT)) & DDRPHY_DX7GCR3_RGSLVT_MASK)
31950 #define DDRPHY_DX7GCR3_WLLVT_MASK                (0x1000000U)
31951 #define DDRPHY_DX7GCR3_WLLVT_SHIFT               (24U)
31952 /*! WLLVT - Write Leveling LCDL Delay VT Compensation
31953  */
31954 #define DDRPHY_DX7GCR3_WLLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WLLVT_SHIFT)) & DDRPHY_DX7GCR3_WLLVT_MASK)
31955 #define DDRPHY_DX7GCR3_WDLVT_MASK                (0x2000000U)
31956 #define DDRPHY_DX7GCR3_WDLVT_SHIFT               (25U)
31957 /*! WDLVT - Write DQ LCDL Delay VT Compensation
31958  */
31959 #define DDRPHY_DX7GCR3_WDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDLVT_SHIFT)) & DDRPHY_DX7GCR3_WDLVT_MASK)
31960 #define DDRPHY_DX7GCR3_RDLVT_MASK                (0x4000000U)
31961 #define DDRPHY_DX7GCR3_RDLVT_SHIFT               (26U)
31962 /*! RDLVT - Read DQS LCDL Delay VT Compensation
31963  */
31964 #define DDRPHY_DX7GCR3_RDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RDLVT_SHIFT)) & DDRPHY_DX7GCR3_RDLVT_MASK)
31965 #define DDRPHY_DX7GCR3_RGLVT_MASK                (0x8000000U)
31966 #define DDRPHY_DX7GCR3_RGLVT_SHIFT               (27U)
31967 /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
31968  */
31969 #define DDRPHY_DX7GCR3_RGLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RGLVT_SHIFT)) & DDRPHY_DX7GCR3_RGLVT_MASK)
31970 #define DDRPHY_DX7GCR3_WDBVT_MASK                (0x10000000U)
31971 #define DDRPHY_DX7GCR3_WDBVT_SHIFT               (28U)
31972 /*! WDBVT - Write Data BDL VT Compensation
31973  */
31974 #define DDRPHY_DX7GCR3_WDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDBVT_SHIFT)) & DDRPHY_DX7GCR3_WDBVT_MASK)
31975 #define DDRPHY_DX7GCR3_RDBVT_MASK                (0x20000000U)
31976 #define DDRPHY_DX7GCR3_RDBVT_SHIFT               (29U)
31977 /*! RDBVT - Read Data BDL VT Compensation
31978  */
31979 #define DDRPHY_DX7GCR3_RDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RDBVT_SHIFT)) & DDRPHY_DX7GCR3_RDBVT_MASK)
31980 #define DDRPHY_DX7GCR3_TEBVT_MASK                (0x40000000U)
31981 #define DDRPHY_DX7GCR3_TEBVT_SHIFT               (30U)
31982 /*! TEBVT - Termination Enable BDL VT Compensation
31983  */
31984 #define DDRPHY_DX7GCR3_TEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_TEBVT_SHIFT)) & DDRPHY_DX7GCR3_TEBVT_MASK)
31985 #define DDRPHY_DX7GCR3_OEBVT_MASK                (0x80000000U)
31986 #define DDRPHY_DX7GCR3_OEBVT_SHIFT               (31U)
31987 /*! OEBVT - Output Enable BDL VT Compensation
31988  */
31989 #define DDRPHY_DX7GCR3_OEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_OEBVT_SHIFT)) & DDRPHY_DX7GCR3_OEBVT_MASK)
31990 /*! @} */
31991 
31992 /*! @name DX7GCR4 - DATX8 n General Configuration Register 4 */
31993 /*! @{ */
31994 #define DDRPHY_DX7GCR4_DXREFIMON_MASK            (0x3U)
31995 #define DDRPHY_DX7GCR4_DXREFIMON_SHIFT           (0U)
31996 /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
31997  */
31998 #define DDRPHY_DX7GCR4_DXREFIMON(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX7GCR4_DXREFIMON_MASK)
31999 #define DDRPHY_DX7GCR4_DXREFIEN_MASK             (0x3CU)
32000 #define DDRPHY_DX7GCR4_DXREFIEN_SHIFT            (2U)
32001 /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
32002  */
32003 #define DDRPHY_DX7GCR4_DXREFIEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFIEN_MASK)
32004 #define DDRPHY_DX7GCR4_RESERVED_7_6_MASK         (0xC0U)
32005 #define DDRPHY_DX7GCR4_RESERVED_7_6_SHIFT        (6U)
32006 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
32007  */
32008 #define DDRPHY_DX7GCR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR4_RESERVED_7_6_MASK)
32009 #define DDRPHY_DX7GCR4_DXREFSSEL_MASK            (0x7F00U)
32010 #define DDRPHY_DX7GCR4_DXREFSSEL_SHIFT           (8U)
32011 /*! DXREFSSEL - Byte Lane Single-End VREF Select
32012  */
32013 #define DDRPHY_DX7GCR4_DXREFSSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX7GCR4_DXREFSSEL_MASK)
32014 #define DDRPHY_DX7GCR4_DXREFSSELRANGE_MASK       (0x8000U)
32015 #define DDRPHY_DX7GCR4_DXREFSSELRANGE_SHIFT      (15U)
32016 /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
32017  */
32018 #define DDRPHY_DX7GCR4_DXREFSSELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX7GCR4_DXREFSSELRANGE_MASK)
32019 #define DDRPHY_DX7GCR4_DXREFESEL_MASK            (0x7F0000U)
32020 #define DDRPHY_DX7GCR4_DXREFESEL_SHIFT           (16U)
32021 /*! DXREFESEL - Byte Lane External VREF Select
32022  */
32023 #define DDRPHY_DX7GCR4_DXREFESEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX7GCR4_DXREFESEL_MASK)
32024 #define DDRPHY_DX7GCR4_DXREFESELRANGE_MASK       (0x800000U)
32025 #define DDRPHY_DX7GCR4_DXREFESELRANGE_SHIFT      (23U)
32026 /*! DXREFESELRANGE - External VREF generator REFSEL range select
32027  */
32028 #define DDRPHY_DX7GCR4_DXREFESELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX7GCR4_DXREFESELRANGE_MASK)
32029 #define DDRPHY_DX7GCR4_RESERVED_24_MASK          (0x1000000U)
32030 #define DDRPHY_DX7GCR4_RESERVED_24_SHIFT         (24U)
32031 /*! RESERVED_24 - Reserved. Returns zeros on reads.
32032  */
32033 #define DDRPHY_DX7GCR4_RESERVED_24(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX7GCR4_RESERVED_24_MASK)
32034 #define DDRPHY_DX7GCR4_DXREFSEN_MASK             (0x2000000U)
32035 #define DDRPHY_DX7GCR4_DXREFSEN_SHIFT            (25U)
32036 /*! DXREFSEN - Byte Lane Single-End VREF Enable
32037  */
32038 #define DDRPHY_DX7GCR4_DXREFSEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFSEN_MASK)
32039 #define DDRPHY_DX7GCR4_DXREFEEN_MASK             (0xC000000U)
32040 #define DDRPHY_DX7GCR4_DXREFEEN_SHIFT            (26U)
32041 /*! DXREFEEN - Byte Lane Internal VREF Enable
32042  */
32043 #define DDRPHY_DX7GCR4_DXREFEEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFEEN_MASK)
32044 #define DDRPHY_DX7GCR4_DXREFPEN_MASK             (0x10000000U)
32045 #define DDRPHY_DX7GCR4_DXREFPEN_SHIFT            (28U)
32046 /*! DXREFPEN - Byte Lane VREF Pad Enable
32047  */
32048 #define DDRPHY_DX7GCR4_DXREFPEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFPEN_MASK)
32049 #define DDRPHY_DX7GCR4_RESERVED_31_29_MASK       (0xE0000000U)
32050 #define DDRPHY_DX7GCR4_RESERVED_31_29_SHIFT      (29U)
32051 /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
32052  */
32053 #define DDRPHY_DX7GCR4_RESERVED_31_29(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX7GCR4_RESERVED_31_29_MASK)
32054 /*! @} */
32055 
32056 /*! @name DX7GCR5 - DATX8 n General Configuration Register 5 */
32057 /*! @{ */
32058 #define DDRPHY_DX7GCR5_DXREFISELR0_MASK          (0x7FU)
32059 #define DDRPHY_DX7GCR5_DXREFISELR0_SHIFT         (0U)
32060 /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
32061  */
32062 #define DDRPHY_DX7GCR5_DXREFISELR0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR0_MASK)
32063 #define DDRPHY_DX7GCR5_RESERVED_7_MASK           (0x80U)
32064 #define DDRPHY_DX7GCR5_RESERVED_7_SHIFT          (7U)
32065 /*! RESERVED_7 - Reserved. Returns zeros on reads.
32066  */
32067 #define DDRPHY_DX7GCR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_7_MASK)
32068 #define DDRPHY_DX7GCR5_DXREFISELR1_MASK          (0x7F00U)
32069 #define DDRPHY_DX7GCR5_DXREFISELR1_SHIFT         (8U)
32070 /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
32071  */
32072 #define DDRPHY_DX7GCR5_DXREFISELR1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR1_MASK)
32073 #define DDRPHY_DX7GCR5_RESERVED_15_MASK          (0x8000U)
32074 #define DDRPHY_DX7GCR5_RESERVED_15_SHIFT         (15U)
32075 /*! RESERVED_15 - Reserved. Returns zeros on reads.
32076  */
32077 #define DDRPHY_DX7GCR5_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_15_MASK)
32078 #define DDRPHY_DX7GCR5_DXREFISELR2_MASK          (0x7F0000U)
32079 #define DDRPHY_DX7GCR5_DXREFISELR2_SHIFT         (16U)
32080 /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
32081  */
32082 #define DDRPHY_DX7GCR5_DXREFISELR2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR2_MASK)
32083 #define DDRPHY_DX7GCR5_RESERVED_23_MASK          (0x800000U)
32084 #define DDRPHY_DX7GCR5_RESERVED_23_SHIFT         (23U)
32085 /*! RESERVED_23 - Reserved. Returns zeros on reads.
32086  */
32087 #define DDRPHY_DX7GCR5_RESERVED_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_23_MASK)
32088 #define DDRPHY_DX7GCR5_DXREFISELR3_MASK          (0x7F000000U)
32089 #define DDRPHY_DX7GCR5_DXREFISELR3_SHIFT         (24U)
32090 /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
32091  */
32092 #define DDRPHY_DX7GCR5_DXREFISELR3(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR3_MASK)
32093 #define DDRPHY_DX7GCR5_RESERVED_31_MASK          (0x80000000U)
32094 #define DDRPHY_DX7GCR5_RESERVED_31_SHIFT         (31U)
32095 /*! RESERVED_31 - Reserved. Returns zeros on reads.
32096  */
32097 #define DDRPHY_DX7GCR5_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_31_MASK)
32098 /*! @} */
32099 
32100 /*! @name DX7GCR6 - DATX8 n General Configuration Register 6 */
32101 /*! @{ */
32102 #define DDRPHY_DX7GCR6_DXDQVREFR0_MASK           (0x3FU)
32103 #define DDRPHY_DX7GCR6_DXDQVREFR0_SHIFT          (0U)
32104 /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
32105  */
32106 #define DDRPHY_DX7GCR6_DXDQVREFR0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR0_MASK)
32107 #define DDRPHY_DX7GCR6_RESERVED_7_6_MASK         (0xC0U)
32108 #define DDRPHY_DX7GCR6_RESERVED_7_6_SHIFT        (6U)
32109 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
32110  */
32111 #define DDRPHY_DX7GCR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_7_6_MASK)
32112 #define DDRPHY_DX7GCR6_DXDQVREFR1_MASK           (0x3F00U)
32113 #define DDRPHY_DX7GCR6_DXDQVREFR1_SHIFT          (8U)
32114 /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
32115  */
32116 #define DDRPHY_DX7GCR6_DXDQVREFR1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR1_MASK)
32117 #define DDRPHY_DX7GCR6_RESERVED_15_14_MASK       (0xC000U)
32118 #define DDRPHY_DX7GCR6_RESERVED_15_14_SHIFT      (14U)
32119 /*! RESERVED_15_14 - Reserved. Returns zeros on reads.
32120  */
32121 #define DDRPHY_DX7GCR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_15_14_MASK)
32122 #define DDRPHY_DX7GCR6_DXDQVREFR2_MASK           (0x3F0000U)
32123 #define DDRPHY_DX7GCR6_DXDQVREFR2_SHIFT          (16U)
32124 /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
32125  */
32126 #define DDRPHY_DX7GCR6_DXDQVREFR2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR2_MASK)
32127 #define DDRPHY_DX7GCR6_RESERVED_23_22_MASK       (0xC00000U)
32128 #define DDRPHY_DX7GCR6_RESERVED_23_22_SHIFT      (22U)
32129 /*! RESERVED_23_22 - Reserved. Returns zeros on reads.
32130  */
32131 #define DDRPHY_DX7GCR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_23_22_MASK)
32132 #define DDRPHY_DX7GCR6_DXDQVREFR3_MASK           (0x3F000000U)
32133 #define DDRPHY_DX7GCR6_DXDQVREFR3_SHIFT          (24U)
32134 /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
32135  */
32136 #define DDRPHY_DX7GCR6_DXDQVREFR3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR3_MASK)
32137 #define DDRPHY_DX7GCR6_RESERVED_31_30_MASK       (0xC0000000U)
32138 #define DDRPHY_DX7GCR6_RESERVED_31_30_SHIFT      (30U)
32139 /*! RESERVED_31_30 - Reserved. Returns zeros on reads.
32140  */
32141 #define DDRPHY_DX7GCR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_31_30_MASK)
32142 /*! @} */
32143 
32144 /*! @name DX7GCR7 - DATX8 n General Configuration Register 7 */
32145 /*! @{ */
32146 #define DDRPHY_DX7GCR7_DCALSVAL_MASK             (0x1FFU)
32147 #define DDRPHY_DX7GCR7_DCALSVAL_SHIFT            (0U)
32148 /*! DCALSVAL - DDL Calibration Starting Value
32149  */
32150 #define DDRPHY_DX7GCR7_DCALSVAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX7GCR7_DCALSVAL_MASK)
32151 #define DDRPHY_DX7GCR7_DCALTYPE_MASK             (0x200U)
32152 #define DDRPHY_DX7GCR7_DCALTYPE_SHIFT            (9U)
32153 /*! DCALTYPE - DDL Calibration Type
32154  */
32155 #define DDRPHY_DX7GCR7_DCALTYPE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX7GCR7_DCALTYPE_MASK)
32156 #define DDRPHY_DX7GCR7_RESERVED_17_10_MASK       (0x3FC00U)
32157 #define DDRPHY_DX7GCR7_RESERVED_17_10_SHIFT      (10U)
32158 /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
32159  */
32160 #define DDRPHY_DX7GCR7_RESERVED_17_10(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX7GCR7_RESERVED_17_10_MASK)
32161 #define DDRPHY_DX7GCR7_RESERVED_18_MASK          (0x40000U)
32162 #define DDRPHY_DX7GCR7_RESERVED_18_SHIFT         (18U)
32163 /*! RESERVED_18 - Reserved. Caution, do not write to this register field.
32164  */
32165 #define DDRPHY_DX7GCR7_RESERVED_18(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX7GCR7_RESERVED_18_MASK)
32166 #define DDRPHY_DX7GCR7_RESERVED_31_19_MASK       (0xFFF80000U)
32167 #define DDRPHY_DX7GCR7_RESERVED_31_19_SHIFT      (19U)
32168 /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
32169  */
32170 #define DDRPHY_DX7GCR7_RESERVED_31_19(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX7GCR7_RESERVED_31_19_MASK)
32171 /*! @} */
32172 
32173 /*! @name DX7GCR8 - DATX8 n General Configuration Register 8 */
32174 /*! @{ */
32175 #define DDRPHY_DX7GCR8_RESERVED_5_0_MASK         (0x3FU)
32176 #define DDRPHY_DX7GCR8_RESERVED_5_0_SHIFT        (0U)
32177 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32178  */
32179 #define DDRPHY_DX7GCR8_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_5_0_MASK)
32180 #define DDRPHY_DX7GCR8_RESERVED_7_6_MASK         (0xC0U)
32181 #define DDRPHY_DX7GCR8_RESERVED_7_6_SHIFT        (6U)
32182 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32183  */
32184 #define DDRPHY_DX7GCR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_7_6_MASK)
32185 #define DDRPHY_DX7GCR8_RESERVED_13_8_MASK        (0x3F00U)
32186 #define DDRPHY_DX7GCR8_RESERVED_13_8_SHIFT       (8U)
32187 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32188  */
32189 #define DDRPHY_DX7GCR8_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_13_8_MASK)
32190 #define DDRPHY_DX7GCR8_RESERVED_15_14_MASK       (0xC000U)
32191 #define DDRPHY_DX7GCR8_RESERVED_15_14_SHIFT      (14U)
32192 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32193  */
32194 #define DDRPHY_DX7GCR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_15_14_MASK)
32195 #define DDRPHY_DX7GCR8_RESERVED_21_16_MASK       (0x3F0000U)
32196 #define DDRPHY_DX7GCR8_RESERVED_21_16_SHIFT      (16U)
32197 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32198  */
32199 #define DDRPHY_DX7GCR8_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_21_16_MASK)
32200 #define DDRPHY_DX7GCR8_RESERVED_23_22_MASK       (0xC00000U)
32201 #define DDRPHY_DX7GCR8_RESERVED_23_22_SHIFT      (22U)
32202 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32203  */
32204 #define DDRPHY_DX7GCR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_23_22_MASK)
32205 #define DDRPHY_DX7GCR8_RESERVED_29_24_MASK       (0x3F000000U)
32206 #define DDRPHY_DX7GCR8_RESERVED_29_24_SHIFT      (24U)
32207 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
32208  */
32209 #define DDRPHY_DX7GCR8_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_29_24_MASK)
32210 #define DDRPHY_DX7GCR8_RESERVED_31_30_MASK       (0xC0000000U)
32211 #define DDRPHY_DX7GCR8_RESERVED_31_30_SHIFT      (30U)
32212 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32213  */
32214 #define DDRPHY_DX7GCR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_31_30_MASK)
32215 /*! @} */
32216 
32217 /*! @name DX7GCR9 - DATX8 n General Configuration Register 9 */
32218 /*! @{ */
32219 #define DDRPHY_DX7GCR9_RESERVED_5_0_MASK         (0x3FU)
32220 #define DDRPHY_DX7GCR9_RESERVED_5_0_SHIFT        (0U)
32221 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32222  */
32223 #define DDRPHY_DX7GCR9_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_5_0_MASK)
32224 #define DDRPHY_DX7GCR9_RESERVED_7_6_MASK         (0xC0U)
32225 #define DDRPHY_DX7GCR9_RESERVED_7_6_SHIFT        (6U)
32226 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32227  */
32228 #define DDRPHY_DX7GCR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_7_6_MASK)
32229 #define DDRPHY_DX7GCR9_RESERVED_13_8_MASK        (0x3F00U)
32230 #define DDRPHY_DX7GCR9_RESERVED_13_8_SHIFT       (8U)
32231 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32232  */
32233 #define DDRPHY_DX7GCR9_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_13_8_MASK)
32234 #define DDRPHY_DX7GCR9_RESERVED_15_14_MASK       (0xC000U)
32235 #define DDRPHY_DX7GCR9_RESERVED_15_14_SHIFT      (14U)
32236 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32237  */
32238 #define DDRPHY_DX7GCR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_15_14_MASK)
32239 #define DDRPHY_DX7GCR9_RESERVED_21_16_MASK       (0x3F0000U)
32240 #define DDRPHY_DX7GCR9_RESERVED_21_16_SHIFT      (16U)
32241 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32242  */
32243 #define DDRPHY_DX7GCR9_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_21_16_MASK)
32244 #define DDRPHY_DX7GCR9_RESERVED_23_22_MASK       (0xC00000U)
32245 #define DDRPHY_DX7GCR9_RESERVED_23_22_SHIFT      (22U)
32246 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32247  */
32248 #define DDRPHY_DX7GCR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_23_22_MASK)
32249 #define DDRPHY_DX7GCR9_RESERVED_29_24_MASK       (0x3F000000U)
32250 #define DDRPHY_DX7GCR9_RESERVED_29_24_SHIFT      (24U)
32251 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
32252  */
32253 #define DDRPHY_DX7GCR9_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_29_24_MASK)
32254 #define DDRPHY_DX7GCR9_RESERVED_31_30_MASK       (0xC0000000U)
32255 #define DDRPHY_DX7GCR9_RESERVED_31_30_SHIFT      (30U)
32256 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32257  */
32258 #define DDRPHY_DX7GCR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_31_30_MASK)
32259 /*! @} */
32260 
32261 /*! @name DX7DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
32262 /*! @{ */
32263 #define DDRPHY_DX7DQMAP0_DQ0MAP_MASK             (0xFU)
32264 #define DDRPHY_DX7DQMAP0_DQ0MAP_SHIFT            (0U)
32265 /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
32266  */
32267 #define DDRPHY_DX7DQMAP0_DQ0MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ0MAP_MASK)
32268 #define DDRPHY_DX7DQMAP0_DQ1MAP_MASK             (0xF0U)
32269 #define DDRPHY_DX7DQMAP0_DQ1MAP_SHIFT            (4U)
32270 /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
32271  */
32272 #define DDRPHY_DX7DQMAP0_DQ1MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ1MAP_MASK)
32273 #define DDRPHY_DX7DQMAP0_DQ2MAP_MASK             (0xF00U)
32274 #define DDRPHY_DX7DQMAP0_DQ2MAP_SHIFT            (8U)
32275 /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
32276  */
32277 #define DDRPHY_DX7DQMAP0_DQ2MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ2MAP_MASK)
32278 #define DDRPHY_DX7DQMAP0_DQ3MAP_MASK             (0xF000U)
32279 #define DDRPHY_DX7DQMAP0_DQ3MAP_SHIFT            (12U)
32280 /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
32281  */
32282 #define DDRPHY_DX7DQMAP0_DQ3MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ3MAP_MASK)
32283 #define DDRPHY_DX7DQMAP0_DQ4MAP_MASK             (0xF0000U)
32284 #define DDRPHY_DX7DQMAP0_DQ4MAP_SHIFT            (16U)
32285 /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
32286  */
32287 #define DDRPHY_DX7DQMAP0_DQ4MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ4MAP_MASK)
32288 #define DDRPHY_DX7DQMAP0_RESERVED_30_20_MASK     (0x7FF00000U)
32289 #define DDRPHY_DX7DQMAP0_RESERVED_30_20_SHIFT    (20U)
32290 /*! RESERVED_30_20 - Reserved. Return zeroes on reads.
32291  */
32292 #define DDRPHY_DX7DQMAP0_RESERVED_30_20(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX7DQMAP0_RESERVED_30_20_MASK)
32293 #define DDRPHY_DX7DQMAP0_MAPOK_MASK              (0x80000000U)
32294 #define DDRPHY_DX7DQMAP0_MAPOK_SHIFT             (31U)
32295 /*! MAPOK - Checksum bit
32296  */
32297 #define DDRPHY_DX7DQMAP0_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX7DQMAP0_MAPOK_MASK)
32298 /*! @} */
32299 
32300 /*! @name DX7DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
32301 /*! @{ */
32302 #define DDRPHY_DX7DQMAP1_DQ5MAP_MASK             (0xFU)
32303 #define DDRPHY_DX7DQMAP1_DQ5MAP_SHIFT            (0U)
32304 /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
32305  */
32306 #define DDRPHY_DX7DQMAP1_DQ5MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX7DQMAP1_DQ5MAP_MASK)
32307 #define DDRPHY_DX7DQMAP1_DQ6MAP_MASK             (0xF0U)
32308 #define DDRPHY_DX7DQMAP1_DQ6MAP_SHIFT            (4U)
32309 /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
32310  */
32311 #define DDRPHY_DX7DQMAP1_DQ6MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX7DQMAP1_DQ6MAP_MASK)
32312 #define DDRPHY_DX7DQMAP1_DQ7MAP_MASK             (0xF00U)
32313 #define DDRPHY_DX7DQMAP1_DQ7MAP_SHIFT            (8U)
32314 /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
32315  */
32316 #define DDRPHY_DX7DQMAP1_DQ7MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX7DQMAP1_DQ7MAP_MASK)
32317 #define DDRPHY_DX7DQMAP1_DMMAP_MASK              (0xF000U)
32318 #define DDRPHY_DX7DQMAP1_DMMAP_SHIFT             (12U)
32319 /*! DMMAP - DM bit DATX8 slice mapping index
32320  */
32321 #define DDRPHY_DX7DQMAP1_DMMAP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX7DQMAP1_DMMAP_MASK)
32322 #define DDRPHY_DX7DQMAP1_RESERVED_30_16_MASK     (0x7FFF0000U)
32323 #define DDRPHY_DX7DQMAP1_RESERVED_30_16_SHIFT    (16U)
32324 /*! RESERVED_30_16 - Reserved. Return zeroes on reads.
32325  */
32326 #define DDRPHY_DX7DQMAP1_RESERVED_30_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX7DQMAP1_RESERVED_30_16_MASK)
32327 #define DDRPHY_DX7DQMAP1_MAPOK_MASK              (0x80000000U)
32328 #define DDRPHY_DX7DQMAP1_MAPOK_SHIFT             (31U)
32329 /*! MAPOK - Checksum bit
32330  */
32331 #define DDRPHY_DX7DQMAP1_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX7DQMAP1_MAPOK_MASK)
32332 /*! @} */
32333 
32334 /*! @name DX7BDLR0 - DATX8 n Bit Delay Line Register 0 */
32335 /*! @{ */
32336 #define DDRPHY_DX7BDLR0_DQ0WBD_MASK              (0x3FU)
32337 #define DDRPHY_DX7BDLR0_DQ0WBD_SHIFT             (0U)
32338 /*! DQ0WBD - DQ0 Write Bit Delay
32339  */
32340 #define DDRPHY_DX7BDLR0_DQ0WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ0WBD_MASK)
32341 #define DDRPHY_DX7BDLR0_RESERVED_7_6_MASK        (0xC0U)
32342 #define DDRPHY_DX7BDLR0_RESERVED_7_6_SHIFT       (6U)
32343 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32344  */
32345 #define DDRPHY_DX7BDLR0_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_7_6_MASK)
32346 #define DDRPHY_DX7BDLR0_DQ1WBD_MASK              (0x3F00U)
32347 #define DDRPHY_DX7BDLR0_DQ1WBD_SHIFT             (8U)
32348 /*! DQ1WBD - DQ1 Write Bit Delay
32349  */
32350 #define DDRPHY_DX7BDLR0_DQ1WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ1WBD_MASK)
32351 #define DDRPHY_DX7BDLR0_RESERVED_15_14_MASK      (0xC000U)
32352 #define DDRPHY_DX7BDLR0_RESERVED_15_14_SHIFT     (14U)
32353 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32354  */
32355 #define DDRPHY_DX7BDLR0_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_15_14_MASK)
32356 #define DDRPHY_DX7BDLR0_DQ2WBD_MASK              (0x3F0000U)
32357 #define DDRPHY_DX7BDLR0_DQ2WBD_SHIFT             (16U)
32358 /*! DQ2WBD - DQ2 Write Bit Delay
32359  */
32360 #define DDRPHY_DX7BDLR0_DQ2WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ2WBD_MASK)
32361 #define DDRPHY_DX7BDLR0_RESERVED_23_22_MASK      (0xC00000U)
32362 #define DDRPHY_DX7BDLR0_RESERVED_23_22_SHIFT     (22U)
32363 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32364  */
32365 #define DDRPHY_DX7BDLR0_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_23_22_MASK)
32366 #define DDRPHY_DX7BDLR0_DQ3WBD_MASK              (0x3F000000U)
32367 #define DDRPHY_DX7BDLR0_DQ3WBD_SHIFT             (24U)
32368 /*! DQ3WBD - DQ3 Write Bit Delay
32369  */
32370 #define DDRPHY_DX7BDLR0_DQ3WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ3WBD_MASK)
32371 #define DDRPHY_DX7BDLR0_RESERVED_31_30_MASK      (0xC0000000U)
32372 #define DDRPHY_DX7BDLR0_RESERVED_31_30_SHIFT     (30U)
32373 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32374  */
32375 #define DDRPHY_DX7BDLR0_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_31_30_MASK)
32376 /*! @} */
32377 
32378 /*! @name DX7BDLR1 - DATX8 n Bit Delay Line Register 1 */
32379 /*! @{ */
32380 #define DDRPHY_DX7BDLR1_DQ4WBD_MASK              (0x3FU)
32381 #define DDRPHY_DX7BDLR1_DQ4WBD_SHIFT             (0U)
32382 /*! DQ4WBD - DQ4 Write Bit Delay
32383  */
32384 #define DDRPHY_DX7BDLR1_DQ4WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ4WBD_MASK)
32385 #define DDRPHY_DX7BDLR1_RESERVED_7_6_MASK        (0xC0U)
32386 #define DDRPHY_DX7BDLR1_RESERVED_7_6_SHIFT       (6U)
32387 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32388  */
32389 #define DDRPHY_DX7BDLR1_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_7_6_MASK)
32390 #define DDRPHY_DX7BDLR1_DQ5WBD_MASK              (0x3F00U)
32391 #define DDRPHY_DX7BDLR1_DQ5WBD_SHIFT             (8U)
32392 /*! DQ5WBD - DQ5 Write Bit Delay
32393  */
32394 #define DDRPHY_DX7BDLR1_DQ5WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ5WBD_MASK)
32395 #define DDRPHY_DX7BDLR1_RESERVED_15_14_MASK      (0xC000U)
32396 #define DDRPHY_DX7BDLR1_RESERVED_15_14_SHIFT     (14U)
32397 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32398  */
32399 #define DDRPHY_DX7BDLR1_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_15_14_MASK)
32400 #define DDRPHY_DX7BDLR1_DQ6WBD_MASK              (0x3F0000U)
32401 #define DDRPHY_DX7BDLR1_DQ6WBD_SHIFT             (16U)
32402 /*! DQ6WBD - DQ6 Write Bit Delay
32403  */
32404 #define DDRPHY_DX7BDLR1_DQ6WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ6WBD_MASK)
32405 #define DDRPHY_DX7BDLR1_RESERVED_23_22_MASK      (0xC00000U)
32406 #define DDRPHY_DX7BDLR1_RESERVED_23_22_SHIFT     (22U)
32407 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32408  */
32409 #define DDRPHY_DX7BDLR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_23_22_MASK)
32410 #define DDRPHY_DX7BDLR1_DQ7WBD_MASK              (0x3F000000U)
32411 #define DDRPHY_DX7BDLR1_DQ7WBD_SHIFT             (24U)
32412 /*! DQ7WBD - DQ7 Write Bit Delay
32413  */
32414 #define DDRPHY_DX7BDLR1_DQ7WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ7WBD_MASK)
32415 #define DDRPHY_DX7BDLR1_RESERVED_31_30_MASK      (0xC0000000U)
32416 #define DDRPHY_DX7BDLR1_RESERVED_31_30_SHIFT     (30U)
32417 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32418  */
32419 #define DDRPHY_DX7BDLR1_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_31_30_MASK)
32420 /*! @} */
32421 
32422 /*! @name DX7BDLR2 - DATX8 n Bit Delay Line Register 2 */
32423 /*! @{ */
32424 #define DDRPHY_DX7BDLR2_DMWBD_MASK               (0x3FU)
32425 #define DDRPHY_DX7BDLR2_DMWBD_SHIFT              (0U)
32426 /*! DMWBD - DM Write Bit Delay
32427  */
32428 #define DDRPHY_DX7BDLR2_DMWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DMWBD_SHIFT)) & DDRPHY_DX7BDLR2_DMWBD_MASK)
32429 #define DDRPHY_DX7BDLR2_RESERVED_7_6_MASK        (0xC0U)
32430 #define DDRPHY_DX7BDLR2_RESERVED_7_6_SHIFT       (6U)
32431 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32432  */
32433 #define DDRPHY_DX7BDLR2_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_7_6_MASK)
32434 #define DDRPHY_DX7BDLR2_DSWBD_MASK               (0x3F00U)
32435 #define DDRPHY_DX7BDLR2_DSWBD_SHIFT              (8U)
32436 /*! DSWBD - DQS Write Bit Delay
32437  */
32438 #define DDRPHY_DX7BDLR2_DSWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DSWBD_SHIFT)) & DDRPHY_DX7BDLR2_DSWBD_MASK)
32439 #define DDRPHY_DX7BDLR2_RESERVED_15_14_MASK      (0xC000U)
32440 #define DDRPHY_DX7BDLR2_RESERVED_15_14_SHIFT     (14U)
32441 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32442  */
32443 #define DDRPHY_DX7BDLR2_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_15_14_MASK)
32444 #define DDRPHY_DX7BDLR2_DSOEBD_MASK              (0x3F0000U)
32445 #define DDRPHY_DX7BDLR2_DSOEBD_SHIFT             (16U)
32446 /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
32447  */
32448 #define DDRPHY_DX7BDLR2_DSOEBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX7BDLR2_DSOEBD_MASK)
32449 #define DDRPHY_DX7BDLR2_RESERVED_23_22_MASK      (0xC00000U)
32450 #define DDRPHY_DX7BDLR2_RESERVED_23_22_SHIFT     (22U)
32451 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32452  */
32453 #define DDRPHY_DX7BDLR2_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_23_22_MASK)
32454 #define DDRPHY_DX7BDLR2_DSNWBD_MASK              (0x3F000000U)
32455 #define DDRPHY_DX7BDLR2_DSNWBD_SHIFT             (24U)
32456 /*! DSNWBD - DQSN Write Bit Delay
32457  */
32458 #define DDRPHY_DX7BDLR2_DSNWBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX7BDLR2_DSNWBD_MASK)
32459 #define DDRPHY_DX7BDLR2_RESERVED_31_30_MASK      (0xC0000000U)
32460 #define DDRPHY_DX7BDLR2_RESERVED_31_30_SHIFT     (30U)
32461 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32462  */
32463 #define DDRPHY_DX7BDLR2_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_31_30_MASK)
32464 /*! @} */
32465 
32466 /*! @name DX7BDLR3 - DATX8 n Bit Delay Line Register 3 */
32467 /*! @{ */
32468 #define DDRPHY_DX7BDLR3_DQ0RBD_MASK              (0x3FU)
32469 #define DDRPHY_DX7BDLR3_DQ0RBD_SHIFT             (0U)
32470 /*! DQ0RBD - DQ0 Read Bit Delay
32471  */
32472 #define DDRPHY_DX7BDLR3_DQ0RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ0RBD_MASK)
32473 #define DDRPHY_DX7BDLR3_RESERVED_7_6_MASK        (0xC0U)
32474 #define DDRPHY_DX7BDLR3_RESERVED_7_6_SHIFT       (6U)
32475 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32476  */
32477 #define DDRPHY_DX7BDLR3_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_7_6_MASK)
32478 #define DDRPHY_DX7BDLR3_DQ1RBD_MASK              (0x3F00U)
32479 #define DDRPHY_DX7BDLR3_DQ1RBD_SHIFT             (8U)
32480 /*! DQ1RBD - DQ1 Read Bit Delay
32481  */
32482 #define DDRPHY_DX7BDLR3_DQ1RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ1RBD_MASK)
32483 #define DDRPHY_DX7BDLR3_RESERVED_15_14_MASK      (0xC000U)
32484 #define DDRPHY_DX7BDLR3_RESERVED_15_14_SHIFT     (14U)
32485 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32486  */
32487 #define DDRPHY_DX7BDLR3_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_15_14_MASK)
32488 #define DDRPHY_DX7BDLR3_DQ2RBD_MASK              (0x3F0000U)
32489 #define DDRPHY_DX7BDLR3_DQ2RBD_SHIFT             (16U)
32490 /*! DQ2RBD - DQ2 Read Bit Delay
32491  */
32492 #define DDRPHY_DX7BDLR3_DQ2RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ2RBD_MASK)
32493 #define DDRPHY_DX7BDLR3_RESERVED_23_22_MASK      (0xC00000U)
32494 #define DDRPHY_DX7BDLR3_RESERVED_23_22_SHIFT     (22U)
32495 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32496  */
32497 #define DDRPHY_DX7BDLR3_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_23_22_MASK)
32498 #define DDRPHY_DX7BDLR3_DQ3RBD_MASK              (0x3F000000U)
32499 #define DDRPHY_DX7BDLR3_DQ3RBD_SHIFT             (24U)
32500 /*! DQ3RBD - DQ3 Read Bit Delay
32501  */
32502 #define DDRPHY_DX7BDLR3_DQ3RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ3RBD_MASK)
32503 #define DDRPHY_DX7BDLR3_RESERVED_31_30_MASK      (0xC0000000U)
32504 #define DDRPHY_DX7BDLR3_RESERVED_31_30_SHIFT     (30U)
32505 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32506  */
32507 #define DDRPHY_DX7BDLR3_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_31_30_MASK)
32508 /*! @} */
32509 
32510 /*! @name DX7BDLR4 - DATX8 n Bit Delay Line Register 4 */
32511 /*! @{ */
32512 #define DDRPHY_DX7BDLR4_DQ4RBD_MASK              (0x3FU)
32513 #define DDRPHY_DX7BDLR4_DQ4RBD_SHIFT             (0U)
32514 /*! DQ4RBD - DQ4 Read Bit Delay
32515  */
32516 #define DDRPHY_DX7BDLR4_DQ4RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ4RBD_MASK)
32517 #define DDRPHY_DX7BDLR4_RESERVED_7_6_MASK        (0xC0U)
32518 #define DDRPHY_DX7BDLR4_RESERVED_7_6_SHIFT       (6U)
32519 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32520  */
32521 #define DDRPHY_DX7BDLR4_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_7_6_MASK)
32522 #define DDRPHY_DX7BDLR4_DQ5RBD_MASK              (0x3F00U)
32523 #define DDRPHY_DX7BDLR4_DQ5RBD_SHIFT             (8U)
32524 /*! DQ5RBD - DQ5 Read Bit Delay
32525  */
32526 #define DDRPHY_DX7BDLR4_DQ5RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ5RBD_MASK)
32527 #define DDRPHY_DX7BDLR4_RESERVED_15_14_MASK      (0xC000U)
32528 #define DDRPHY_DX7BDLR4_RESERVED_15_14_SHIFT     (14U)
32529 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32530  */
32531 #define DDRPHY_DX7BDLR4_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_15_14_MASK)
32532 #define DDRPHY_DX7BDLR4_DQ6RBD_MASK              (0x3F0000U)
32533 #define DDRPHY_DX7BDLR4_DQ6RBD_SHIFT             (16U)
32534 /*! DQ6RBD - DQ6 Read Bit Delay
32535  */
32536 #define DDRPHY_DX7BDLR4_DQ6RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ6RBD_MASK)
32537 #define DDRPHY_DX7BDLR4_RESERVED_23_22_MASK      (0xC00000U)
32538 #define DDRPHY_DX7BDLR4_RESERVED_23_22_SHIFT     (22U)
32539 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32540  */
32541 #define DDRPHY_DX7BDLR4_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_23_22_MASK)
32542 #define DDRPHY_DX7BDLR4_DQ7RBD_MASK              (0x3F000000U)
32543 #define DDRPHY_DX7BDLR4_DQ7RBD_SHIFT             (24U)
32544 /*! DQ7RBD - DQ7 Read Bit Delay
32545  */
32546 #define DDRPHY_DX7BDLR4_DQ7RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ7RBD_MASK)
32547 #define DDRPHY_DX7BDLR4_RESERVED_31_30_MASK      (0xC0000000U)
32548 #define DDRPHY_DX7BDLR4_RESERVED_31_30_SHIFT     (30U)
32549 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32550  */
32551 #define DDRPHY_DX7BDLR4_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_31_30_MASK)
32552 /*! @} */
32553 
32554 /*! @name DX7BDLR5 - DATX8 n Bit Delay Line Register 5 */
32555 /*! @{ */
32556 #define DDRPHY_DX7BDLR5_DMRBD_MASK               (0x3FU)
32557 #define DDRPHY_DX7BDLR5_DMRBD_SHIFT              (0U)
32558 /*! DMRBD - DM Read Bit Delay
32559  */
32560 #define DDRPHY_DX7BDLR5_DMRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR5_DMRBD_SHIFT)) & DDRPHY_DX7BDLR5_DMRBD_MASK)
32561 #define DDRPHY_DX7BDLR5_RESERVED_31_6_MASK       (0xFFFFFFC0U)
32562 #define DDRPHY_DX7BDLR5_RESERVED_31_6_SHIFT      (6U)
32563 /*! RESERVED_31_6 - Reserved. Return zeroes on reads.
32564  */
32565 #define DDRPHY_DX7BDLR5_RESERVED_31_6(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX7BDLR5_RESERVED_31_6_MASK)
32566 /*! @} */
32567 
32568 /*! @name DX7BDLR6 - DATX8 n Bit Delay Line Register 6 */
32569 /*! @{ */
32570 #define DDRPHY_DX7BDLR6_RESERVED_7_0_MASK        (0xFFU)
32571 #define DDRPHY_DX7BDLR6_RESERVED_7_0_SHIFT       (0U)
32572 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
32573  */
32574 #define DDRPHY_DX7BDLR6_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX7BDLR6_RESERVED_7_0_MASK)
32575 #define DDRPHY_DX7BDLR6_PDRBD_MASK               (0x3F00U)
32576 #define DDRPHY_DX7BDLR6_PDRBD_SHIFT              (8U)
32577 /*! PDRBD - Power down receiver Bit Delay
32578  */
32579 #define DDRPHY_DX7BDLR6_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_PDRBD_SHIFT)) & DDRPHY_DX7BDLR6_PDRBD_MASK)
32580 #define DDRPHY_DX7BDLR6_RESERVED_15_14_MASK      (0xC000U)
32581 #define DDRPHY_DX7BDLR6_RESERVED_15_14_SHIFT     (14U)
32582 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32583  */
32584 #define DDRPHY_DX7BDLR6_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR6_RESERVED_15_14_MASK)
32585 #define DDRPHY_DX7BDLR6_TERBD_MASK               (0x3F0000U)
32586 #define DDRPHY_DX7BDLR6_TERBD_SHIFT              (16U)
32587 /*! TERBD - Termination Enable Bit Delay
32588  */
32589 #define DDRPHY_DX7BDLR6_TERBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_TERBD_SHIFT)) & DDRPHY_DX7BDLR6_TERBD_MASK)
32590 #define DDRPHY_DX7BDLR6_RESERVED_31_22_MASK      (0xFFC00000U)
32591 #define DDRPHY_DX7BDLR6_RESERVED_31_22_SHIFT     (22U)
32592 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
32593  */
32594 #define DDRPHY_DX7BDLR6_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR6_RESERVED_31_22_MASK)
32595 /*! @} */
32596 
32597 /*! @name DX7BDLR7 - DATX8 n Bit Delay Line Register 7 */
32598 /*! @{ */
32599 #define DDRPHY_DX7BDLR7_RESERVED_5_0_MASK        (0x3FU)
32600 #define DDRPHY_DX7BDLR7_RESERVED_5_0_SHIFT       (0U)
32601 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32602  */
32603 #define DDRPHY_DX7BDLR7_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_5_0_MASK)
32604 #define DDRPHY_DX7BDLR7_RESERVED_7_6_MASK        (0xC0U)
32605 #define DDRPHY_DX7BDLR7_RESERVED_7_6_SHIFT       (6U)
32606 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32607  */
32608 #define DDRPHY_DX7BDLR7_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_7_6_MASK)
32609 #define DDRPHY_DX7BDLR7_RESERVED_13_8_MASK       (0x3F00U)
32610 #define DDRPHY_DX7BDLR7_RESERVED_13_8_SHIFT      (8U)
32611 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32612  */
32613 #define DDRPHY_DX7BDLR7_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_13_8_MASK)
32614 #define DDRPHY_DX7BDLR7_RESERVED_15_14_MASK      (0xC000U)
32615 #define DDRPHY_DX7BDLR7_RESERVED_15_14_SHIFT     (14U)
32616 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32617  */
32618 #define DDRPHY_DX7BDLR7_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_15_14_MASK)
32619 #define DDRPHY_DX7BDLR7_RESERVED_21_16_MASK      (0x3F0000U)
32620 #define DDRPHY_DX7BDLR7_RESERVED_21_16_SHIFT     (16U)
32621 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32622  */
32623 #define DDRPHY_DX7BDLR7_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_21_16_MASK)
32624 #define DDRPHY_DX7BDLR7_RESERVED_31_22_MASK      (0xFFC00000U)
32625 #define DDRPHY_DX7BDLR7_RESERVED_31_22_SHIFT     (22U)
32626 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
32627  */
32628 #define DDRPHY_DX7BDLR7_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_31_22_MASK)
32629 /*! @} */
32630 
32631 /*! @name DX7BDLR8 - DATX8 n Bit Delay Line Register 8 */
32632 /*! @{ */
32633 #define DDRPHY_DX7BDLR8_RESERVED_5_0_MASK        (0x3FU)
32634 #define DDRPHY_DX7BDLR8_RESERVED_5_0_SHIFT       (0U)
32635 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32636  */
32637 #define DDRPHY_DX7BDLR8_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_5_0_MASK)
32638 #define DDRPHY_DX7BDLR8_RESERVED_7_6_MASK        (0xC0U)
32639 #define DDRPHY_DX7BDLR8_RESERVED_7_6_SHIFT       (6U)
32640 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32641  */
32642 #define DDRPHY_DX7BDLR8_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_7_6_MASK)
32643 #define DDRPHY_DX7BDLR8_RESERVED_13_8_MASK       (0x3F00U)
32644 #define DDRPHY_DX7BDLR8_RESERVED_13_8_SHIFT      (8U)
32645 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32646  */
32647 #define DDRPHY_DX7BDLR8_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_13_8_MASK)
32648 #define DDRPHY_DX7BDLR8_RESERVED_15_14_MASK      (0xC000U)
32649 #define DDRPHY_DX7BDLR8_RESERVED_15_14_SHIFT     (14U)
32650 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32651  */
32652 #define DDRPHY_DX7BDLR8_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_15_14_MASK)
32653 #define DDRPHY_DX7BDLR8_RESERVED_21_16_MASK      (0x3F0000U)
32654 #define DDRPHY_DX7BDLR8_RESERVED_21_16_SHIFT     (16U)
32655 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32656  */
32657 #define DDRPHY_DX7BDLR8_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_21_16_MASK)
32658 #define DDRPHY_DX7BDLR8_RESERVED_31_22_MASK      (0xFFC00000U)
32659 #define DDRPHY_DX7BDLR8_RESERVED_31_22_SHIFT     (22U)
32660 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
32661  */
32662 #define DDRPHY_DX7BDLR8_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_31_22_MASK)
32663 /*! @} */
32664 
32665 /*! @name DX7BDLR9 - DATX8 n Bit Delay Line Register 9 */
32666 /*! @{ */
32667 #define DDRPHY_DX7BDLR9_RESERVED_5_0_MASK        (0x3FU)
32668 #define DDRPHY_DX7BDLR9_RESERVED_5_0_SHIFT       (0U)
32669 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32670  */
32671 #define DDRPHY_DX7BDLR9_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_5_0_MASK)
32672 #define DDRPHY_DX7BDLR9_RESERVED_7_6_MASK        (0xC0U)
32673 #define DDRPHY_DX7BDLR9_RESERVED_7_6_SHIFT       (6U)
32674 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32675  */
32676 #define DDRPHY_DX7BDLR9_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_7_6_MASK)
32677 #define DDRPHY_DX7BDLR9_RESERVED_13_8_MASK       (0x3F00U)
32678 #define DDRPHY_DX7BDLR9_RESERVED_13_8_SHIFT      (8U)
32679 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32680  */
32681 #define DDRPHY_DX7BDLR9_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_13_8_MASK)
32682 #define DDRPHY_DX7BDLR9_RESERVED_15_14_MASK      (0xC000U)
32683 #define DDRPHY_DX7BDLR9_RESERVED_15_14_SHIFT     (14U)
32684 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32685  */
32686 #define DDRPHY_DX7BDLR9_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_15_14_MASK)
32687 #define DDRPHY_DX7BDLR9_RESERVED_21_16_MASK      (0x3F0000U)
32688 #define DDRPHY_DX7BDLR9_RESERVED_21_16_SHIFT     (16U)
32689 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32690  */
32691 #define DDRPHY_DX7BDLR9_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_21_16_MASK)
32692 #define DDRPHY_DX7BDLR9_RESERVED_31_22_MASK      (0xFFC00000U)
32693 #define DDRPHY_DX7BDLR9_RESERVED_31_22_SHIFT     (22U)
32694 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
32695  */
32696 #define DDRPHY_DX7BDLR9_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_31_22_MASK)
32697 /*! @} */
32698 
32699 /*! @name DX7LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
32700 /*! @{ */
32701 #define DDRPHY_DX7LCDLR0_WLD_MASK                (0x1FFU)
32702 #define DDRPHY_DX7LCDLR0_WLD_SHIFT               (0U)
32703 /*! WLD - Write Leveling Delay
32704  */
32705 #define DDRPHY_DX7LCDLR0_WLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_WLD_SHIFT)) & DDRPHY_DX7LCDLR0_WLD_MASK)
32706 #define DDRPHY_DX7LCDLR0_RESERVED_15_9_MASK      (0xFE00U)
32707 #define DDRPHY_DX7LCDLR0_RESERVED_15_9_SHIFT     (9U)
32708 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32709  */
32710 #define DDRPHY_DX7LCDLR0_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR0_RESERVED_15_9_MASK)
32711 #define DDRPHY_DX7LCDLR0_RESERVED_24_16_MASK     (0x1FF0000U)
32712 #define DDRPHY_DX7LCDLR0_RESERVED_24_16_SHIFT    (16U)
32713 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32714  */
32715 #define DDRPHY_DX7LCDLR0_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR0_RESERVED_24_16_MASK)
32716 #define DDRPHY_DX7LCDLR0_RESERVED_31_25_MASK     (0xFE000000U)
32717 #define DDRPHY_DX7LCDLR0_RESERVED_31_25_SHIFT    (25U)
32718 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32719  */
32720 #define DDRPHY_DX7LCDLR0_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR0_RESERVED_31_25_MASK)
32721 /*! @} */
32722 
32723 /*! @name DX7LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
32724 /*! @{ */
32725 #define DDRPHY_DX7LCDLR1_WDQD_MASK               (0x1FFU)
32726 #define DDRPHY_DX7LCDLR1_WDQD_SHIFT              (0U)
32727 /*! WDQD - Write Data Delay
32728  */
32729 #define DDRPHY_DX7LCDLR1_WDQD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_WDQD_SHIFT)) & DDRPHY_DX7LCDLR1_WDQD_MASK)
32730 #define DDRPHY_DX7LCDLR1_RESERVED_15_9_MASK      (0xFE00U)
32731 #define DDRPHY_DX7LCDLR1_RESERVED_15_9_SHIFT     (9U)
32732 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32733  */
32734 #define DDRPHY_DX7LCDLR1_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR1_RESERVED_15_9_MASK)
32735 #define DDRPHY_DX7LCDLR1_RESERVED_24_16_MASK     (0x1FF0000U)
32736 #define DDRPHY_DX7LCDLR1_RESERVED_24_16_SHIFT    (16U)
32737 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32738  */
32739 #define DDRPHY_DX7LCDLR1_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR1_RESERVED_24_16_MASK)
32740 #define DDRPHY_DX7LCDLR1_RESERVED_31_25_MASK     (0xFE000000U)
32741 #define DDRPHY_DX7LCDLR1_RESERVED_31_25_SHIFT    (25U)
32742 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32743  */
32744 #define DDRPHY_DX7LCDLR1_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR1_RESERVED_31_25_MASK)
32745 /*! @} */
32746 
32747 /*! @name DX7LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
32748 /*! @{ */
32749 #define DDRPHY_DX7LCDLR2_DQSGD_MASK              (0x1FFU)
32750 #define DDRPHY_DX7LCDLR2_DQSGD_SHIFT             (0U)
32751 /*! DQSGD - Read DQS Gating Delay
32752  */
32753 #define DDRPHY_DX7LCDLR2_DQSGD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX7LCDLR2_DQSGD_MASK)
32754 #define DDRPHY_DX7LCDLR2_RESERVED_15_9_MASK      (0xFE00U)
32755 #define DDRPHY_DX7LCDLR2_RESERVED_15_9_SHIFT     (9U)
32756 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32757  */
32758 #define DDRPHY_DX7LCDLR2_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR2_RESERVED_15_9_MASK)
32759 #define DDRPHY_DX7LCDLR2_RESERVED_24_16_MASK     (0x1FF0000U)
32760 #define DDRPHY_DX7LCDLR2_RESERVED_24_16_SHIFT    (16U)
32761 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32762  */
32763 #define DDRPHY_DX7LCDLR2_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR2_RESERVED_24_16_MASK)
32764 #define DDRPHY_DX7LCDLR2_RESERVED_31_25_MASK     (0xFE000000U)
32765 #define DDRPHY_DX7LCDLR2_RESERVED_31_25_SHIFT    (25U)
32766 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32767  */
32768 #define DDRPHY_DX7LCDLR2_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR2_RESERVED_31_25_MASK)
32769 /*! @} */
32770 
32771 /*! @name DX7LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
32772 /*! @{ */
32773 #define DDRPHY_DX7LCDLR3_RDQSD_MASK              (0x1FFU)
32774 #define DDRPHY_DX7LCDLR3_RDQSD_SHIFT             (0U)
32775 /*! RDQSD - Read DQS Delay
32776  */
32777 #define DDRPHY_DX7LCDLR3_RDQSD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX7LCDLR3_RDQSD_MASK)
32778 #define DDRPHY_DX7LCDLR3_RESERVED_15_9_MASK      (0xFE00U)
32779 #define DDRPHY_DX7LCDLR3_RESERVED_15_9_SHIFT     (9U)
32780 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32781  */
32782 #define DDRPHY_DX7LCDLR3_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR3_RESERVED_15_9_MASK)
32783 #define DDRPHY_DX7LCDLR3_RESERVED_24_16_MASK     (0x1FF0000U)
32784 #define DDRPHY_DX7LCDLR3_RESERVED_24_16_SHIFT    (16U)
32785 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32786  */
32787 #define DDRPHY_DX7LCDLR3_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR3_RESERVED_24_16_MASK)
32788 #define DDRPHY_DX7LCDLR3_RESERVED_31_25_MASK     (0xFE000000U)
32789 #define DDRPHY_DX7LCDLR3_RESERVED_31_25_SHIFT    (25U)
32790 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32791  */
32792 #define DDRPHY_DX7LCDLR3_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR3_RESERVED_31_25_MASK)
32793 /*! @} */
32794 
32795 /*! @name DX7LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
32796 /*! @{ */
32797 #define DDRPHY_DX7LCDLR4_RDQSND_MASK             (0x1FFU)
32798 #define DDRPHY_DX7LCDLR4_RDQSND_SHIFT            (0U)
32799 /*! RDQSND - Read DQSN Delay
32800  */
32801 #define DDRPHY_DX7LCDLR4_RDQSND(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX7LCDLR4_RDQSND_MASK)
32802 #define DDRPHY_DX7LCDLR4_RESERVED_15_9_MASK      (0xFE00U)
32803 #define DDRPHY_DX7LCDLR4_RESERVED_15_9_SHIFT     (9U)
32804 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32805  */
32806 #define DDRPHY_DX7LCDLR4_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR4_RESERVED_15_9_MASK)
32807 #define DDRPHY_DX7LCDLR4_RESERVED_24_16_MASK     (0x1FF0000U)
32808 #define DDRPHY_DX7LCDLR4_RESERVED_24_16_SHIFT    (16U)
32809 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32810  */
32811 #define DDRPHY_DX7LCDLR4_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR4_RESERVED_24_16_MASK)
32812 #define DDRPHY_DX7LCDLR4_RESERVED_31_25_MASK     (0xFE000000U)
32813 #define DDRPHY_DX7LCDLR4_RESERVED_31_25_SHIFT    (25U)
32814 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32815  */
32816 #define DDRPHY_DX7LCDLR4_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR4_RESERVED_31_25_MASK)
32817 /*! @} */
32818 
32819 /*! @name DX7LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
32820 /*! @{ */
32821 #define DDRPHY_DX7LCDLR5_DQSGSD_MASK             (0x1FFU)
32822 #define DDRPHY_DX7LCDLR5_DQSGSD_SHIFT            (0U)
32823 /*! DQSGSD - DQS Gating Status Delay
32824  */
32825 #define DDRPHY_DX7LCDLR5_DQSGSD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX7LCDLR5_DQSGSD_MASK)
32826 #define DDRPHY_DX7LCDLR5_RESERVED_15_9_MASK      (0xFE00U)
32827 #define DDRPHY_DX7LCDLR5_RESERVED_15_9_SHIFT     (9U)
32828 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32829  */
32830 #define DDRPHY_DX7LCDLR5_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR5_RESERVED_15_9_MASK)
32831 #define DDRPHY_DX7LCDLR5_RESERVED_24_16_MASK     (0x1FF0000U)
32832 #define DDRPHY_DX7LCDLR5_RESERVED_24_16_SHIFT    (16U)
32833 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32834  */
32835 #define DDRPHY_DX7LCDLR5_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR5_RESERVED_24_16_MASK)
32836 #define DDRPHY_DX7LCDLR5_RESERVED_31_25_MASK     (0xFE000000U)
32837 #define DDRPHY_DX7LCDLR5_RESERVED_31_25_SHIFT    (25U)
32838 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32839  */
32840 #define DDRPHY_DX7LCDLR5_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR5_RESERVED_31_25_MASK)
32841 /*! @} */
32842 
32843 /*! @name DX7MDLR0 - DATX8 n Master Delay Line Register 0 */
32844 /*! @{ */
32845 #define DDRPHY_DX7MDLR0_IPRD_MASK                (0x1FFU)
32846 #define DDRPHY_DX7MDLR0_IPRD_SHIFT               (0U)
32847 /*! IPRD - Initial Period
32848  */
32849 #define DDRPHY_DX7MDLR0_IPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_IPRD_SHIFT)) & DDRPHY_DX7MDLR0_IPRD_MASK)
32850 #define DDRPHY_DX7MDLR0_RESERVED_15_9_MASK       (0xFE00U)
32851 #define DDRPHY_DX7MDLR0_RESERVED_15_9_SHIFT      (9U)
32852 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32853  */
32854 #define DDRPHY_DX7MDLR0_RESERVED_15_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX7MDLR0_RESERVED_15_9_MASK)
32855 #define DDRPHY_DX7MDLR0_TPRD_MASK                (0x1FF0000U)
32856 #define DDRPHY_DX7MDLR0_TPRD_SHIFT               (16U)
32857 /*! TPRD - Target Period
32858  */
32859 #define DDRPHY_DX7MDLR0_TPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_TPRD_SHIFT)) & DDRPHY_DX7MDLR0_TPRD_MASK)
32860 #define DDRPHY_DX7MDLR0_RESERVED_31_25_MASK      (0xFE000000U)
32861 #define DDRPHY_DX7MDLR0_RESERVED_31_25_SHIFT     (25U)
32862 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32863  */
32864 #define DDRPHY_DX7MDLR0_RESERVED_31_25(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX7MDLR0_RESERVED_31_25_MASK)
32865 /*! @} */
32866 
32867 /*! @name DX7MDLR1 - DATX8 n Master Delay Line Register 1 */
32868 /*! @{ */
32869 #define DDRPHY_DX7MDLR1_MDLD_MASK                (0x1FFU)
32870 #define DDRPHY_DX7MDLR1_MDLD_SHIFT               (0U)
32871 /*! MDLD - MDL Delay
32872  */
32873 #define DDRPHY_DX7MDLR1_MDLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR1_MDLD_SHIFT)) & DDRPHY_DX7MDLR1_MDLD_MASK)
32874 #define DDRPHY_DX7MDLR1_RESERVED_31_9_MASK       (0xFFFFFE00U)
32875 #define DDRPHY_DX7MDLR1_RESERVED_31_9_SHIFT      (9U)
32876 /*! RESERVED_31_9 - Reserved. Return zeroes on reads.
32877  */
32878 #define DDRPHY_DX7MDLR1_RESERVED_31_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX7MDLR1_RESERVED_31_9_MASK)
32879 /*! @} */
32880 
32881 /*! @name DX7GTR0 - DATX8 n General Timing Register 0 */
32882 /*! @{ */
32883 #define DDRPHY_DX7GTR0_DGSL_MASK                 (0x1FU)
32884 #define DDRPHY_DX7GTR0_DGSL_SHIFT                (0U)
32885 /*! DGSL - DQS Gating System Latency
32886  */
32887 #define DDRPHY_DX7GTR0_DGSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_DGSL_SHIFT)) & DDRPHY_DX7GTR0_DGSL_MASK)
32888 #define DDRPHY_DX7GTR0_RESERVED_7_5_MASK         (0xE0U)
32889 #define DDRPHY_DX7GTR0_RESERVED_7_5_SHIFT        (5U)
32890 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
32891  */
32892 #define DDRPHY_DX7GTR0_RESERVED_7_5(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_7_5_MASK)
32893 #define DDRPHY_DX7GTR0_RESERVED_12_8_MASK        (0x1F00U)
32894 #define DDRPHY_DX7GTR0_RESERVED_12_8_SHIFT       (8U)
32895 /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
32896  */
32897 #define DDRPHY_DX7GTR0_RESERVED_12_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_12_8_MASK)
32898 #define DDRPHY_DX7GTR0_RESERVED_15_13_MASK       (0xE000U)
32899 #define DDRPHY_DX7GTR0_RESERVED_15_13_SHIFT      (13U)
32900 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
32901  */
32902 #define DDRPHY_DX7GTR0_RESERVED_15_13(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_15_13_MASK)
32903 #define DDRPHY_DX7GTR0_WLSL_MASK                 (0xF0000U)
32904 #define DDRPHY_DX7GTR0_WLSL_SHIFT                (16U)
32905 /*! WLSL - Write Leveling System Latency
32906  */
32907 #define DDRPHY_DX7GTR0_WLSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_WLSL_SHIFT)) & DDRPHY_DX7GTR0_WLSL_MASK)
32908 #define DDRPHY_DX7GTR0_RESERVED_23_20_MASK       (0xF00000U)
32909 #define DDRPHY_DX7GTR0_RESERVED_23_20_SHIFT      (20U)
32910 /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
32911  */
32912 #define DDRPHY_DX7GTR0_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_23_20_MASK)
32913 #define DDRPHY_DX7GTR0_WDQSL_MASK                (0x7000000U)
32914 #define DDRPHY_DX7GTR0_WDQSL_SHIFT               (24U)
32915 /*! WDQSL - DQ Write Path Latency Pipeline
32916  */
32917 #define DDRPHY_DX7GTR0_WDQSL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_WDQSL_SHIFT)) & DDRPHY_DX7GTR0_WDQSL_MASK)
32918 #define DDRPHY_DX7GTR0_RESERVED_31_24_MASK       (0xF8000000U)
32919 #define DDRPHY_DX7GTR0_RESERVED_31_24_SHIFT      (27U)
32920 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
32921  */
32922 #define DDRPHY_DX7GTR0_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_31_24_MASK)
32923 /*! @} */
32924 
32925 /*! @name DX7RSR0 - DATX8 n Rank Status Register 0 */
32926 /*! @{ */
32927 #define DDRPHY_DX7RSR0_QSGERR_MASK               (0xFFFFU)
32928 #define DDRPHY_DX7RSR0_QSGERR_SHIFT              (0U)
32929 /*! QSGERR - DQS Gate Training Error
32930  */
32931 #define DDRPHY_DX7RSR0_QSGERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR0_QSGERR_SHIFT)) & DDRPHY_DX7RSR0_QSGERR_MASK)
32932 #define DDRPHY_DX7RSR0_RESERVED_31_16_MASK       (0xFFFF0000U)
32933 #define DDRPHY_DX7RSR0_RESERVED_31_16_SHIFT      (16U)
32934 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
32935  */
32936 #define DDRPHY_DX7RSR0_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR0_RESERVED_31_16_MASK)
32937 /*! @} */
32938 
32939 /*! @name DX7RSR1 - DATX8 n Rank Status Register 1 */
32940 /*! @{ */
32941 #define DDRPHY_DX7RSR1_RDLVLERR_MASK             (0xFFFFU)
32942 #define DDRPHY_DX7RSR1_RDLVLERR_SHIFT            (0U)
32943 /*! RDLVLERR - Read Leveling Error
32944  */
32945 #define DDRPHY_DX7RSR1_RDLVLERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX7RSR1_RDLVLERR_MASK)
32946 #define DDRPHY_DX7RSR1_RESERVED_31_16_MASK       (0xFFFF0000U)
32947 #define DDRPHY_DX7RSR1_RESERVED_31_16_SHIFT      (16U)
32948 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
32949  */
32950 #define DDRPHY_DX7RSR1_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR1_RESERVED_31_16_MASK)
32951 /*! @} */
32952 
32953 /*! @name DX7RSR2 - DATX8 n Rank Status Register 2 */
32954 /*! @{ */
32955 #define DDRPHY_DX7RSR2_WLAWN_MASK                (0xFFFFU)
32956 #define DDRPHY_DX7RSR2_WLAWN_SHIFT               (0U)
32957 /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
32958  */
32959 #define DDRPHY_DX7RSR2_WLAWN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR2_WLAWN_SHIFT)) & DDRPHY_DX7RSR2_WLAWN_MASK)
32960 #define DDRPHY_DX7RSR2_RESERVED_31_16_MASK       (0xFFFF0000U)
32961 #define DDRPHY_DX7RSR2_RESERVED_31_16_SHIFT      (16U)
32962 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
32963  */
32964 #define DDRPHY_DX7RSR2_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR2_RESERVED_31_16_MASK)
32965 /*! @} */
32966 
32967 /*! @name DX7RSR3 - DATX8 n Rank Status Register 3 */
32968 /*! @{ */
32969 #define DDRPHY_DX7RSR3_WLAERR_MASK               (0xFFFFU)
32970 #define DDRPHY_DX7RSR3_WLAERR_SHIFT              (0U)
32971 /*! WLAERR - Write Leveling Adjustment Error
32972  */
32973 #define DDRPHY_DX7RSR3_WLAERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR3_WLAERR_SHIFT)) & DDRPHY_DX7RSR3_WLAERR_MASK)
32974 #define DDRPHY_DX7RSR3_RESERVED_31_16_MASK       (0xFFFF0000U)
32975 #define DDRPHY_DX7RSR3_RESERVED_31_16_SHIFT      (16U)
32976 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
32977  */
32978 #define DDRPHY_DX7RSR3_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR3_RESERVED_31_16_MASK)
32979 /*! @} */
32980 
32981 /*! @name DX7GSR0 - DATX8 n General Status Register 0 */
32982 /*! @{ */
32983 #define DDRPHY_DX7GSR0_WDQCAL_MASK               (0x1U)
32984 #define DDRPHY_DX7GSR0_WDQCAL_SHIFT              (0U)
32985 /*! WDQCAL - Write DQ Calibration
32986  */
32987 #define DDRPHY_DX7GSR0_WDQCAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WDQCAL_SHIFT)) & DDRPHY_DX7GSR0_WDQCAL_MASK)
32988 #define DDRPHY_DX7GSR0_RDQSCAL_MASK              (0x2U)
32989 #define DDRPHY_DX7GSR0_RDQSCAL_SHIFT             (1U)
32990 /*! RDQSCAL - Read DQS Calibration
32991  */
32992 #define DDRPHY_DX7GSR0_RDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX7GSR0_RDQSCAL_MASK)
32993 #define DDRPHY_DX7GSR0_RDQSNCAL_MASK             (0x4U)
32994 #define DDRPHY_DX7GSR0_RDQSNCAL_SHIFT            (2U)
32995 /*! RDQSNCAL - Read DQS# Calibration
32996  */
32997 #define DDRPHY_DX7GSR0_RDQSNCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX7GSR0_RDQSNCAL_MASK)
32998 #define DDRPHY_DX7GSR0_GDQSCAL_MASK              (0x8U)
32999 #define DDRPHY_DX7GSR0_GDQSCAL_SHIFT             (3U)
33000 /*! GDQSCAL - Read DQS gating Calibration
33001  */
33002 #define DDRPHY_DX7GSR0_GDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX7GSR0_GDQSCAL_MASK)
33003 #define DDRPHY_DX7GSR0_WLCAL_MASK                (0x10U)
33004 #define DDRPHY_DX7GSR0_WLCAL_SHIFT               (4U)
33005 /*! WLCAL - Write Leveling Calibration
33006  */
33007 #define DDRPHY_DX7GSR0_WLCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLCAL_SHIFT)) & DDRPHY_DX7GSR0_WLCAL_MASK)
33008 #define DDRPHY_DX7GSR0_WLDONE_MASK               (0x20U)
33009 #define DDRPHY_DX7GSR0_WLDONE_SHIFT              (5U)
33010 /*! WLDONE - Write Leveling Done
33011  */
33012 #define DDRPHY_DX7GSR0_WLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLDONE_SHIFT)) & DDRPHY_DX7GSR0_WLDONE_MASK)
33013 #define DDRPHY_DX7GSR0_WLERR_MASK                (0x40U)
33014 #define DDRPHY_DX7GSR0_WLERR_SHIFT               (6U)
33015 /*! WLERR - Write Leveling Error
33016  */
33017 #define DDRPHY_DX7GSR0_WLERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLERR_SHIFT)) & DDRPHY_DX7GSR0_WLERR_MASK)
33018 #define DDRPHY_DX7GSR0_WLPRD_MASK                (0xFF80U)
33019 #define DDRPHY_DX7GSR0_WLPRD_SHIFT               (7U)
33020 /*! WLPRD - Write Leveling Period
33021  */
33022 #define DDRPHY_DX7GSR0_WLPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLPRD_SHIFT)) & DDRPHY_DX7GSR0_WLPRD_MASK)
33023 #define DDRPHY_DX7GSR0_DPLOCK_MASK               (0x10000U)
33024 #define DDRPHY_DX7GSR0_DPLOCK_SHIFT              (16U)
33025 /*! DPLOCK - DATX8 PLL Lock
33026  */
33027 #define DDRPHY_DX7GSR0_DPLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_DPLOCK_SHIFT)) & DDRPHY_DX7GSR0_DPLOCK_MASK)
33028 #define DDRPHY_DX7GSR0_GDQSPRD_MASK              (0x3FE0000U)
33029 #define DDRPHY_DX7GSR0_GDQSPRD_SHIFT             (17U)
33030 /*! GDQSPRD - Read DQS gating Period
33031  */
33032 #define DDRPHY_DX7GSR0_GDQSPRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX7GSR0_GDQSPRD_MASK)
33033 #define DDRPHY_DX7GSR0_RESERVED_29_26_MASK       (0x3C000000U)
33034 #define DDRPHY_DX7GSR0_RESERVED_29_26_SHIFT      (26U)
33035 /*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
33036  */
33037 #define DDRPHY_DX7GSR0_RESERVED_29_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX7GSR0_RESERVED_29_26_MASK)
33038 #define DDRPHY_DX7GSR0_WLDQ_MASK                 (0x40000000U)
33039 #define DDRPHY_DX7GSR0_WLDQ_SHIFT                (30U)
33040 /*! WLDQ - Write Leveling DQ Status
33041  */
33042 #define DDRPHY_DX7GSR0_WLDQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLDQ_SHIFT)) & DDRPHY_DX7GSR0_WLDQ_MASK)
33043 #define DDRPHY_DX7GSR0_RESERVED_31_MASK          (0x80000000U)
33044 #define DDRPHY_DX7GSR0_RESERVED_31_SHIFT         (31U)
33045 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
33046  */
33047 #define DDRPHY_DX7GSR0_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX7GSR0_RESERVED_31_MASK)
33048 /*! @} */
33049 
33050 /*! @name DX7GSR1 - DATX8 n General Status Register 1 */
33051 /*! @{ */
33052 #define DDRPHY_DX7GSR1_DLTDONE_MASK              (0x1U)
33053 #define DDRPHY_DX7GSR1_DLTDONE_SHIFT             (0U)
33054 /*! DLTDONE - Delay Line Test Done
33055  */
33056 #define DDRPHY_DX7GSR1_DLTDONE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR1_DLTDONE_SHIFT)) & DDRPHY_DX7GSR1_DLTDONE_MASK)
33057 #define DDRPHY_DX7GSR1_DLTCODE_MASK              (0x1FFFFFEU)
33058 #define DDRPHY_DX7GSR1_DLTCODE_SHIFT             (1U)
33059 /*! DLTCODE - Delay Line Test Code
33060  */
33061 #define DDRPHY_DX7GSR1_DLTCODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR1_DLTCODE_SHIFT)) & DDRPHY_DX7GSR1_DLTCODE_MASK)
33062 #define DDRPHY_DX7GSR1_RESERVED_31_25_MASK       (0xFE000000U)
33063 #define DDRPHY_DX7GSR1_RESERVED_31_25_SHIFT      (25U)
33064 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
33065  */
33066 #define DDRPHY_DX7GSR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX7GSR1_RESERVED_31_25_MASK)
33067 /*! @} */
33068 
33069 /*! @name DX7GSR2 - DATX8 n General Status Register 2 */
33070 /*! @{ */
33071 #define DDRPHY_DX7GSR2_RDERR_MASK                (0x1U)
33072 #define DDRPHY_DX7GSR2_RDERR_SHIFT               (0U)
33073 /*! RDERR - Read Bit Deskew Error
33074  */
33075 #define DDRPHY_DX7GSR2_RDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_RDERR_SHIFT)) & DDRPHY_DX7GSR2_RDERR_MASK)
33076 #define DDRPHY_DX7GSR2_RDWN_MASK                 (0x2U)
33077 #define DDRPHY_DX7GSR2_RDWN_SHIFT                (1U)
33078 /*! RDWN - Read Bit Deskew Warning
33079  */
33080 #define DDRPHY_DX7GSR2_RDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_RDWN_SHIFT)) & DDRPHY_DX7GSR2_RDWN_MASK)
33081 #define DDRPHY_DX7GSR2_WDERR_MASK                (0x4U)
33082 #define DDRPHY_DX7GSR2_WDERR_SHIFT               (2U)
33083 /*! WDERR - Write Bit Deskew Error
33084  */
33085 #define DDRPHY_DX7GSR2_WDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WDERR_SHIFT)) & DDRPHY_DX7GSR2_WDERR_MASK)
33086 #define DDRPHY_DX7GSR2_WDWN_MASK                 (0x8U)
33087 #define DDRPHY_DX7GSR2_WDWN_SHIFT                (3U)
33088 /*! WDWN - Write Bit Deskew Warning
33089  */
33090 #define DDRPHY_DX7GSR2_WDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WDWN_SHIFT)) & DDRPHY_DX7GSR2_WDWN_MASK)
33091 #define DDRPHY_DX7GSR2_REERR_MASK                (0x10U)
33092 #define DDRPHY_DX7GSR2_REERR_SHIFT               (4U)
33093 /*! REERR - Read Eye Centering Error
33094  */
33095 #define DDRPHY_DX7GSR2_REERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_REERR_SHIFT)) & DDRPHY_DX7GSR2_REERR_MASK)
33096 #define DDRPHY_DX7GSR2_REWN_MASK                 (0x20U)
33097 #define DDRPHY_DX7GSR2_REWN_SHIFT                (5U)
33098 /*! REWN - Read Eye Centering Warning
33099  */
33100 #define DDRPHY_DX7GSR2_REWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_REWN_SHIFT)) & DDRPHY_DX7GSR2_REWN_MASK)
33101 #define DDRPHY_DX7GSR2_WEERR_MASK                (0x40U)
33102 #define DDRPHY_DX7GSR2_WEERR_SHIFT               (6U)
33103 /*! WEERR - Write Eye Centering Error
33104  */
33105 #define DDRPHY_DX7GSR2_WEERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WEERR_SHIFT)) & DDRPHY_DX7GSR2_WEERR_MASK)
33106 #define DDRPHY_DX7GSR2_WEWN_MASK                 (0x80U)
33107 #define DDRPHY_DX7GSR2_WEWN_SHIFT                (7U)
33108 /*! WEWN - Write Eye Centering Warning
33109  */
33110 #define DDRPHY_DX7GSR2_WEWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WEWN_SHIFT)) & DDRPHY_DX7GSR2_WEWN_MASK)
33111 #define DDRPHY_DX7GSR2_ESTAT_MASK                (0xF00U)
33112 #define DDRPHY_DX7GSR2_ESTAT_SHIFT               (8U)
33113 /*! ESTAT - Error Status
33114  */
33115 #define DDRPHY_DX7GSR2_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_ESTAT_SHIFT)) & DDRPHY_DX7GSR2_ESTAT_MASK)
33116 #define DDRPHY_DX7GSR2_DQS2DQERR_MASK            (0xFF000U)
33117 #define DDRPHY_DX7GSR2_DQS2DQERR_SHIFT           (12U)
33118 /*! DQS2DQERR - Write DQS2DQ Training Error
33119  */
33120 #define DDRPHY_DX7GSR2_DQS2DQERR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX7GSR2_DQS2DQERR_MASK)
33121 #define DDRPHY_DX7GSR2_SRDERR_MASK               (0x100000U)
33122 #define DDRPHY_DX7GSR2_SRDERR_SHIFT              (20U)
33123 /*! SRDERR - Static Read Error
33124  */
33125 #define DDRPHY_DX7GSR2_SRDERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_SRDERR_SHIFT)) & DDRPHY_DX7GSR2_SRDERR_MASK)
33126 #define DDRPHY_DX7GSR2_RESERVED_21_MASK          (0x200000U)
33127 #define DDRPHY_DX7GSR2_RESERVED_21_SHIFT         (21U)
33128 /*! RESERVED_21 - Reserved. Return zeroes on reads.
33129  */
33130 #define DDRPHY_DX7GSR2_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX7GSR2_RESERVED_21_MASK)
33131 #define DDRPHY_DX7GSR2_GSDQSCAL_MASK             (0x400000U)
33132 #define DDRPHY_DX7GSR2_GSDQSCAL_SHIFT            (22U)
33133 /*! GSDQSCAL - Read DQS Gating Status Calibration
33134  */
33135 #define DDRPHY_DX7GSR2_GSDQSCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX7GSR2_GSDQSCAL_MASK)
33136 #define DDRPHY_DX7GSR2_GSDQSPRD_MASK             (0xFF800000U)
33137 #define DDRPHY_DX7GSR2_GSDQSPRD_SHIFT            (23U)
33138 /*! GSDQSPRD - Read DQS gating Status Period
33139  */
33140 #define DDRPHY_DX7GSR2_GSDQSPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX7GSR2_GSDQSPRD_MASK)
33141 /*! @} */
33142 
33143 /*! @name DX7GSR3 - DATX8 n General Status Register 3 */
33144 /*! @{ */
33145 #define DDRPHY_DX7GSR3_SRDPC_MASK                (0x3U)
33146 #define DDRPHY_DX7GSR3_SRDPC_SHIFT               (0U)
33147 /*! SRDPC - Static Read Delay Pass Count
33148  */
33149 #define DDRPHY_DX7GSR3_SRDPC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_SRDPC_SHIFT)) & DDRPHY_DX7GSR3_SRDPC_MASK)
33150 #define DDRPHY_DX7GSR3_RESERVED_7_2_MASK         (0xFCU)
33151 #define DDRPHY_DX7GSR3_RESERVED_7_2_SHIFT        (2U)
33152 /*! RESERVED_7_2 - Reserved. Return zeroes on reads.
33153  */
33154 #define DDRPHY_DX7GSR3_RESERVED_7_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX7GSR3_RESERVED_7_2_MASK)
33155 #define DDRPHY_DX7GSR3_HVERR_MASK                (0xF00U)
33156 #define DDRPHY_DX7GSR3_HVERR_SHIFT               (8U)
33157 /*! HVERR - Host VREF Training Error
33158  */
33159 #define DDRPHY_DX7GSR3_HVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_HVERR_SHIFT)) & DDRPHY_DX7GSR3_HVERR_MASK)
33160 #define DDRPHY_DX7GSR3_HVWRN_MASK                (0xF000U)
33161 #define DDRPHY_DX7GSR3_HVWRN_SHIFT               (12U)
33162 /*! HVWRN - Host VREF Training Warning
33163  */
33164 #define DDRPHY_DX7GSR3_HVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_HVWRN_SHIFT)) & DDRPHY_DX7GSR3_HVWRN_MASK)
33165 #define DDRPHY_DX7GSR3_DVERR_MASK                (0xF0000U)
33166 #define DDRPHY_DX7GSR3_DVERR_SHIFT               (16U)
33167 /*! DVERR - DRAM VREF Training Error
33168  */
33169 #define DDRPHY_DX7GSR3_DVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_DVERR_SHIFT)) & DDRPHY_DX7GSR3_DVERR_MASK)
33170 #define DDRPHY_DX7GSR3_DVWRN_MASK                (0xF00000U)
33171 #define DDRPHY_DX7GSR3_DVWRN_SHIFT               (20U)
33172 /*! DVWRN - DRAM VREF Training Warning
33173  */
33174 #define DDRPHY_DX7GSR3_DVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_DVWRN_SHIFT)) & DDRPHY_DX7GSR3_DVWRN_MASK)
33175 #define DDRPHY_DX7GSR3_ESTAT_MASK                (0x7000000U)
33176 #define DDRPHY_DX7GSR3_ESTAT_SHIFT               (24U)
33177 /*! ESTAT - VREF Training Error Status Code
33178  */
33179 #define DDRPHY_DX7GSR3_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_ESTAT_SHIFT)) & DDRPHY_DX7GSR3_ESTAT_MASK)
33180 #define DDRPHY_DX7GSR3_RESERVED_31_27_MASK       (0xF8000000U)
33181 #define DDRPHY_DX7GSR3_RESERVED_31_27_SHIFT      (27U)
33182 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
33183  */
33184 #define DDRPHY_DX7GSR3_RESERVED_31_27(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX7GSR3_RESERVED_31_27_MASK)
33185 /*! @} */
33186 
33187 /*! @name DX7GSR4 - DATX8 n General Status Register 4 */
33188 /*! @{ */
33189 #define DDRPHY_DX7GSR4_RESERVED_0_MASK           (0x1U)
33190 #define DDRPHY_DX7GSR4_RESERVED_0_SHIFT          (0U)
33191 /*! RESERVED_0 - Reserved. Return zeroes on reads.
33192  */
33193 #define DDRPHY_DX7GSR4_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_0_MASK)
33194 #define DDRPHY_DX7GSR4_RESERVED_1_MASK           (0x2U)
33195 #define DDRPHY_DX7GSR4_RESERVED_1_SHIFT          (1U)
33196 /*! RESERVED_1 - Reserved. Return zeroes on reads.
33197  */
33198 #define DDRPHY_DX7GSR4_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_1_MASK)
33199 #define DDRPHY_DX7GSR4_RESERVED_2_MASK           (0x4U)
33200 #define DDRPHY_DX7GSR4_RESERVED_2_SHIFT          (2U)
33201 /*! RESERVED_2 - Reserved. Return zeroes on reads.
33202  */
33203 #define DDRPHY_DX7GSR4_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_2_MASK)
33204 #define DDRPHY_DX7GSR4_RESERVED_3_MASK           (0x8U)
33205 #define DDRPHY_DX7GSR4_RESERVED_3_SHIFT          (3U)
33206 /*! RESERVED_3 - Reserved. Return zeroes on reads.
33207  */
33208 #define DDRPHY_DX7GSR4_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_3_MASK)
33209 #define DDRPHY_DX7GSR4_RESERVED_4_MASK           (0x10U)
33210 #define DDRPHY_DX7GSR4_RESERVED_4_SHIFT          (4U)
33211 /*! RESERVED_4 - Reserved. Return zeroes on reads.
33212  */
33213 #define DDRPHY_DX7GSR4_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_4_MASK)
33214 #define DDRPHY_DX7GSR4_RESERVED_5_MASK           (0x20U)
33215 #define DDRPHY_DX7GSR4_RESERVED_5_SHIFT          (5U)
33216 /*! RESERVED_5 - Reserved. Return zeroes on reads.
33217  */
33218 #define DDRPHY_DX7GSR4_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_5_MASK)
33219 #define DDRPHY_DX7GSR4_RESERVED_6_MASK           (0x40U)
33220 #define DDRPHY_DX7GSR4_RESERVED_6_SHIFT          (6U)
33221 /*! RESERVED_6 - Reserved. Return zeroes on reads.
33222  */
33223 #define DDRPHY_DX7GSR4_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_6_MASK)
33224 #define DDRPHY_DX7GSR4_RESERVED_15_7_MASK        (0xFF80U)
33225 #define DDRPHY_DX7GSR4_RESERVED_15_7_SHIFT       (7U)
33226 /*! RESERVED_15_7 - Reserved. Return zeroes on reads.
33227  */
33228 #define DDRPHY_DX7GSR4_RESERVED_15_7(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_15_7_MASK)
33229 #define DDRPHY_DX7GSR4_RESERVED_16_MASK          (0x10000U)
33230 #define DDRPHY_DX7GSR4_RESERVED_16_SHIFT         (16U)
33231 /*! RESERVED_16 - Reserved. Return zeroes on reads.
33232  */
33233 #define DDRPHY_DX7GSR4_RESERVED_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_16_MASK)
33234 #define DDRPHY_DX7GSR4_RESERVED_25_17_MASK       (0x3FE0000U)
33235 #define DDRPHY_DX7GSR4_RESERVED_25_17_SHIFT      (17U)
33236 /*! RESERVED_25_17 - Reserved. Return zeroes on reads.
33237  */
33238 #define DDRPHY_DX7GSR4_RESERVED_25_17(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_25_17_MASK)
33239 #define DDRPHY_DX7GSR4_RESERVED_31_26_MASK       (0xFC000000U)
33240 #define DDRPHY_DX7GSR4_RESERVED_31_26_SHIFT      (26U)
33241 /*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
33242  */
33243 #define DDRPHY_DX7GSR4_RESERVED_31_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_31_26_MASK)
33244 /*! @} */
33245 
33246 /*! @name DX7GSR5 - DATX8 n General Status Register 5 */
33247 /*! @{ */
33248 #define DDRPHY_DX7GSR5_RESERVED_0_MASK           (0x1U)
33249 #define DDRPHY_DX7GSR5_RESERVED_0_SHIFT          (0U)
33250 /*! RESERVED_0 - Reserved. Return zeroes on reads.
33251  */
33252 #define DDRPHY_DX7GSR5_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_0_MASK)
33253 #define DDRPHY_DX7GSR5_RESERVED_1_MASK           (0x2U)
33254 #define DDRPHY_DX7GSR5_RESERVED_1_SHIFT          (1U)
33255 /*! RESERVED_1 - Reserved. Return zeroes on reads.
33256  */
33257 #define DDRPHY_DX7GSR5_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_1_MASK)
33258 #define DDRPHY_DX7GSR5_RESERVED_2_MASK           (0x4U)
33259 #define DDRPHY_DX7GSR5_RESERVED_2_SHIFT          (2U)
33260 /*! RESERVED_2 - Reserved. Return zeroes on reads.
33261  */
33262 #define DDRPHY_DX7GSR5_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_2_MASK)
33263 #define DDRPHY_DX7GSR5_RESERVED_3_MASK           (0x8U)
33264 #define DDRPHY_DX7GSR5_RESERVED_3_SHIFT          (3U)
33265 /*! RESERVED_3 - Reserved. Return zeroes on reads.
33266  */
33267 #define DDRPHY_DX7GSR5_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_3_MASK)
33268 #define DDRPHY_DX7GSR5_RESERVED_4_MASK           (0x10U)
33269 #define DDRPHY_DX7GSR5_RESERVED_4_SHIFT          (4U)
33270 /*! RESERVED_4 - Reserved. Return zeroes on reads.
33271  */
33272 #define DDRPHY_DX7GSR5_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_4_MASK)
33273 #define DDRPHY_DX7GSR5_RESERVED_5_MASK           (0x20U)
33274 #define DDRPHY_DX7GSR5_RESERVED_5_SHIFT          (5U)
33275 /*! RESERVED_5 - Reserved. Return zeroes on reads.
33276  */
33277 #define DDRPHY_DX7GSR5_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_5_MASK)
33278 #define DDRPHY_DX7GSR5_RESERVED_6_MASK           (0x40U)
33279 #define DDRPHY_DX7GSR5_RESERVED_6_SHIFT          (6U)
33280 /*! RESERVED_6 - Reserved. Return zeroes on reads.
33281  */
33282 #define DDRPHY_DX7GSR5_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_6_MASK)
33283 #define DDRPHY_DX7GSR5_RESERVED_7_MASK           (0x80U)
33284 #define DDRPHY_DX7GSR5_RESERVED_7_SHIFT          (7U)
33285 /*! RESERVED_7 - Reserved. Return zeroes on reads.
33286  */
33287 #define DDRPHY_DX7GSR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_7_MASK)
33288 #define DDRPHY_DX7GSR5_RESERVED_11_8_MASK        (0xF00U)
33289 #define DDRPHY_DX7GSR5_RESERVED_11_8_SHIFT       (8U)
33290 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
33291  */
33292 #define DDRPHY_DX7GSR5_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_11_8_MASK)
33293 #define DDRPHY_DX7GSR5_RESERVED_19_12_MASK       (0xFF000U)
33294 #define DDRPHY_DX7GSR5_RESERVED_19_12_SHIFT      (12U)
33295 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
33296  */
33297 #define DDRPHY_DX7GSR5_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_19_12_MASK)
33298 #define DDRPHY_DX7GSR5_RESERVED_20_MASK          (0x100000U)
33299 #define DDRPHY_DX7GSR5_RESERVED_20_SHIFT         (20U)
33300 /*! RESERVED_20 - Reserved. Return zeroes on reads.
33301  */
33302 #define DDRPHY_DX7GSR5_RESERVED_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_20_MASK)
33303 #define DDRPHY_DX7GSR5_RESERVED_21_MASK          (0x200000U)
33304 #define DDRPHY_DX7GSR5_RESERVED_21_SHIFT         (21U)
33305 /*! RESERVED_21 - Reserved. Return zeroes on reads.
33306  */
33307 #define DDRPHY_DX7GSR5_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_21_MASK)
33308 #define DDRPHY_DX7GSR5_RESERVED_22_MASK          (0x400000U)
33309 #define DDRPHY_DX7GSR5_RESERVED_22_SHIFT         (22U)
33310 /*! RESERVED_22 - Reserved. Return zeroes on reads.
33311  */
33312 #define DDRPHY_DX7GSR5_RESERVED_22(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_22_MASK)
33313 #define DDRPHY_DX7GSR5_RESERVED_31_23_MASK       (0xFF800000U)
33314 #define DDRPHY_DX7GSR5_RESERVED_31_23_SHIFT      (23U)
33315 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
33316  */
33317 #define DDRPHY_DX7GSR5_RESERVED_31_23(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_31_23_MASK)
33318 /*! @} */
33319 
33320 /*! @name DX7GSR6 - DATX8 n General Status Register 6 */
33321 /*! @{ */
33322 #define DDRPHY_DX7GSR6_RESERVED_1_0_MASK         (0x3U)
33323 #define DDRPHY_DX7GSR6_RESERVED_1_0_SHIFT        (0U)
33324 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
33325  */
33326 #define DDRPHY_DX7GSR6_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_1_0_MASK)
33327 #define DDRPHY_DX7GSR6_RESERVED_3_2_MASK         (0xCU)
33328 #define DDRPHY_DX7GSR6_RESERVED_3_2_SHIFT        (2U)
33329 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
33330  */
33331 #define DDRPHY_DX7GSR6_RESERVED_3_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_3_2_MASK)
33332 #define DDRPHY_DX7GSR6_RESERVED_7_4_MASK         (0xF0U)
33333 #define DDRPHY_DX7GSR6_RESERVED_7_4_SHIFT        (4U)
33334 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
33335  */
33336 #define DDRPHY_DX7GSR6_RESERVED_7_4(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_7_4_MASK)
33337 #define DDRPHY_DX7GSR6_RESERVED_11_8_MASK        (0xF00U)
33338 #define DDRPHY_DX7GSR6_RESERVED_11_8_SHIFT       (8U)
33339 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
33340  */
33341 #define DDRPHY_DX7GSR6_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_11_8_MASK)
33342 #define DDRPHY_DX7GSR6_RESERVED_15_12_MASK       (0xF000U)
33343 #define DDRPHY_DX7GSR6_RESERVED_15_12_SHIFT      (12U)
33344 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
33345  */
33346 #define DDRPHY_DX7GSR6_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_15_12_MASK)
33347 #define DDRPHY_DX7GSR6_RESERVED_19_15_MASK       (0xF0000U)
33348 #define DDRPHY_DX7GSR6_RESERVED_19_15_SHIFT      (16U)
33349 /*! RESERVED_19_15 - Reserved. Return zeroes on reads.
33350  */
33351 #define DDRPHY_DX7GSR6_RESERVED_19_15(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_19_15_MASK)
33352 #define DDRPHY_DX7GSR6_RESERVED_23_20_MASK       (0xF00000U)
33353 #define DDRPHY_DX7GSR6_RESERVED_23_20_SHIFT      (20U)
33354 /*! RESERVED_23_20 - Reserved. Return zeroes on reads.
33355  */
33356 #define DDRPHY_DX7GSR6_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_23_20_MASK)
33357 #define DDRPHY_DX7GSR6_RESERVED_31_24_MASK       (0xFF000000U)
33358 #define DDRPHY_DX7GSR6_RESERVED_31_24_SHIFT      (24U)
33359 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
33360  */
33361 #define DDRPHY_DX7GSR6_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_31_24_MASK)
33362 /*! @} */
33363 
33364 /*! @name DX8GCR0 - DATX8 n General Configuration Register 0 */
33365 /*! @{ */
33366 #define DDRPHY_DX8GCR0_RESERVED_1_0_MASK         (0x3U)
33367 #define DDRPHY_DX8GCR0_RESERVED_1_0_SHIFT        (0U)
33368 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
33369  */
33370 #define DDRPHY_DX8GCR0_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX8GCR0_RESERVED_1_0_MASK)
33371 #define DDRPHY_DX8GCR0_DQSGOE_MASK               (0x4U)
33372 #define DDRPHY_DX8GCR0_DQSGOE_SHIFT              (2U)
33373 /*! DQSGOE - DQSG Output Enable
33374  */
33375 #define DDRPHY_DX8GCR0_DQSGOE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSGOE_SHIFT)) & DDRPHY_DX8GCR0_DQSGOE_MASK)
33376 #define DDRPHY_DX8GCR0_DQSGODT_MASK              (0x8U)
33377 #define DDRPHY_DX8GCR0_DQSGODT_SHIFT             (3U)
33378 /*! DQSGODT - DQSG On-Die Termination
33379  */
33380 #define DDRPHY_DX8GCR0_DQSGODT(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSGODT_SHIFT)) & DDRPHY_DX8GCR0_DQSGODT_MASK)
33381 #define DDRPHY_DX8GCR0_RESERVED_4_MASK           (0x10U)
33382 #define DDRPHY_DX8GCR0_RESERVED_4_SHIFT          (4U)
33383 /*! RESERVED_4 - Reserved. Return zeroes on reads.
33384  */
33385 #define DDRPHY_DX8GCR0_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX8GCR0_RESERVED_4_MASK)
33386 #define DDRPHY_DX8GCR0_DQSGPDR_MASK              (0x20U)
33387 #define DDRPHY_DX8GCR0_DQSGPDR_SHIFT             (5U)
33388 /*! DQSGPDR - DQSG Power Down Receiver
33389  */
33390 #define DDRPHY_DX8GCR0_DQSGPDR(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX8GCR0_DQSGPDR_MASK)
33391 #define DDRPHY_DX8GCR0_DQSRPD_MASK               (0x40U)
33392 #define DDRPHY_DX8GCR0_DQSRPD_SHIFT              (6U)
33393 /*! DQSRPD - DQSR Power Down
33394  */
33395 #define DDRPHY_DX8GCR0_DQSRPD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSRPD_SHIFT)) & DDRPHY_DX8GCR0_DQSRPD_MASK)
33396 #define DDRPHY_DX8GCR0_CPDRSHFT_MASK             (0x180U)
33397 #define DDRPHY_DX8GCR0_CPDRSHFT_SHIFT            (7U)
33398 /*! CPDRSHFT - Configurable PDR Phase Shift
33399  */
33400 #define DDRPHY_DX8GCR0_CPDRSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX8GCR0_CPDRSHFT_MASK)
33401 #define DDRPHY_DX8GCR0_RTTOH_MASK                (0x600U)
33402 #define DDRPHY_DX8GCR0_RTTOH_SHIFT               (9U)
33403 /*! RTTOH - RTT Output Hold
33404  */
33405 #define DDRPHY_DX8GCR0_RTTOH(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RTTOH_SHIFT)) & DDRPHY_DX8GCR0_RTTOH_MASK)
33406 #define DDRPHY_DX8GCR0_RTTOAL_MASK               (0x800U)
33407 #define DDRPHY_DX8GCR0_RTTOAL_SHIFT              (11U)
33408 /*! RTTOAL - RTT On Additive Latency
33409  */
33410 #define DDRPHY_DX8GCR0_RTTOAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RTTOAL_SHIFT)) & DDRPHY_DX8GCR0_RTTOAL_MASK)
33411 #define DDRPHY_DX8GCR0_DQSSEPDR_MASK             (0x1000U)
33412 #define DDRPHY_DX8GCR0_DQSSEPDR_SHIFT            (12U)
33413 /*! DQSSEPDR - DQSSE Power Down Receiver
33414  */
33415 #define DDRPHY_DX8GCR0_DQSSEPDR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX8GCR0_DQSSEPDR_MASK)
33416 #define DDRPHY_DX8GCR0_DQSNSEPDR_MASK            (0x2000U)
33417 #define DDRPHY_DX8GCR0_DQSNSEPDR_SHIFT           (13U)
33418 /*! DQSNSEPDR - DQSNSE Power Down Receiver
33419  */
33420 #define DDRPHY_DX8GCR0_DQSNSEPDR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX8GCR0_DQSNSEPDR_MASK)
33421 #define DDRPHY_DX8GCR0_RESERVED_19_14_MASK       (0xFC000U)
33422 #define DDRPHY_DX8GCR0_RESERVED_19_14_SHIFT      (14U)
33423 /*! RESERVED_19_14 - Reserved. Return zeroes on reads.
33424  */
33425 #define DDRPHY_DX8GCR0_RESERVED_19_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX8GCR0_RESERVED_19_14_MASK)
33426 #define DDRPHY_DX8GCR0_RDDLY_MASK                (0xF00000U)
33427 #define DDRPHY_DX8GCR0_RDDLY_SHIFT               (20U)
33428 /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
33429  */
33430 #define DDRPHY_DX8GCR0_RDDLY(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RDDLY_SHIFT)) & DDRPHY_DX8GCR0_RDDLY_MASK)
33431 #define DDRPHY_DX8GCR0_DQSDCC_MASK               (0xF000000U)
33432 #define DDRPHY_DX8GCR0_DQSDCC_SHIFT              (24U)
33433 /*! DQSDCC - DQS Duty Cycle Correction
33434  */
33435 #define DDRPHY_DX8GCR0_DQSDCC(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSDCC_SHIFT)) & DDRPHY_DX8GCR0_DQSDCC_MASK)
33436 #define DDRPHY_DX8GCR0_CODTSHFT_MASK             (0x30000000U)
33437 #define DDRPHY_DX8GCR0_CODTSHFT_SHIFT            (28U)
33438 /*! CODTSHFT - Configurable ODT(TE) Phase Shift
33439  */
33440 #define DDRPHY_DX8GCR0_CODTSHFT(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX8GCR0_CODTSHFT_MASK)
33441 #define DDRPHY_DX8GCR0_MDLEN_MASK                (0x40000000U)
33442 #define DDRPHY_DX8GCR0_MDLEN_SHIFT               (30U)
33443 /*! MDLEN - Master Delay Line Enable
33444  */
33445 #define DDRPHY_DX8GCR0_MDLEN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_MDLEN_SHIFT)) & DDRPHY_DX8GCR0_MDLEN_MASK)
33446 #define DDRPHY_DX8GCR0_CALBYP_MASK               (0x80000000U)
33447 #define DDRPHY_DX8GCR0_CALBYP_SHIFT              (31U)
33448 /*! CALBYP - Calibration Bypass
33449  */
33450 #define DDRPHY_DX8GCR0_CALBYP(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_CALBYP_SHIFT)) & DDRPHY_DX8GCR0_CALBYP_MASK)
33451 /*! @} */
33452 
33453 /*! @name DX8GCR1 - DATX8 n General Configuration Register 1 */
33454 /*! @{ */
33455 #define DDRPHY_DX8GCR1_DQEN_MASK                 (0xFFU)
33456 #define DDRPHY_DX8GCR1_DQEN_SHIFT                (0U)
33457 /*! DQEN - Enables DQ corresponding to each bit in a byte
33458  */
33459 #define DDRPHY_DX8GCR1_DQEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DQEN_SHIFT)) & DDRPHY_DX8GCR1_DQEN_MASK)
33460 #define DDRPHY_DX8GCR1_DMEN_MASK                 (0x100U)
33461 #define DDRPHY_DX8GCR1_DMEN_SHIFT                (8U)
33462 /*! DMEN - Enables DM pin in a byte lane
33463  */
33464 #define DDRPHY_DX8GCR1_DMEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DMEN_SHIFT)) & DDRPHY_DX8GCR1_DMEN_MASK)
33465 #define DDRPHY_DX8GCR1_DSEN_MASK                 (0x200U)
33466 #define DDRPHY_DX8GCR1_DSEN_SHIFT                (9U)
33467 /*! DSEN - Enables Write Data strobe in a byte lane
33468  */
33469 #define DDRPHY_DX8GCR1_DSEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DSEN_SHIFT)) & DDRPHY_DX8GCR1_DSEN_MASK)
33470 #define DDRPHY_DX8GCR1_TEEN_MASK                 (0x400U)
33471 #define DDRPHY_DX8GCR1_TEEN_SHIFT                (10U)
33472 /*! TEEN - Enables ODT/TE in a byte lane
33473  */
33474 #define DDRPHY_DX8GCR1_TEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_TEEN_SHIFT)) & DDRPHY_DX8GCR1_TEEN_MASK)
33475 #define DDRPHY_DX8GCR1_PDREN_MASK                (0x800U)
33476 #define DDRPHY_DX8GCR1_PDREN_SHIFT               (11U)
33477 /*! PDREN - Enables PDR in a byte lane
33478  */
33479 #define DDRPHY_DX8GCR1_PDREN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_PDREN_SHIFT)) & DDRPHY_DX8GCR1_PDREN_MASK)
33480 #define DDRPHY_DX8GCR1_OEEN_MASK                 (0x1000U)
33481 #define DDRPHY_DX8GCR1_OEEN_SHIFT                (12U)
33482 /*! OEEN - Enables Read Data Strobe in a byte lane
33483  */
33484 #define DDRPHY_DX8GCR1_OEEN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_OEEN_SHIFT)) & DDRPHY_DX8GCR1_OEEN_MASK)
33485 #define DDRPHY_DX8GCR1_QSSEL_MASK                (0x2000U)
33486 #define DDRPHY_DX8GCR1_QSSEL_SHIFT               (13U)
33487 /*! QSSEL - Select the delayed or non-delayed read data strobe
33488  */
33489 #define DDRPHY_DX8GCR1_QSSEL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_QSSEL_SHIFT)) & DDRPHY_DX8GCR1_QSSEL_MASK)
33490 #define DDRPHY_DX8GCR1_QSNSEL_MASK               (0x4000U)
33491 #define DDRPHY_DX8GCR1_QSNSEL_SHIFT              (14U)
33492 /*! QSNSEL - Select the delayed or non-delayed read data strobe #
33493  */
33494 #define DDRPHY_DX8GCR1_QSNSEL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_QSNSEL_SHIFT)) & DDRPHY_DX8GCR1_QSNSEL_MASK)
33495 #define DDRPHY_DX8GCR1_RESERVED_15_MASK          (0x8000U)
33496 #define DDRPHY_DX8GCR1_RESERVED_15_SHIFT         (15U)
33497 /*! RESERVED_15 - Reserved. Returns zeroes on reads.
33498  */
33499 #define DDRPHY_DX8GCR1_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX8GCR1_RESERVED_15_MASK)
33500 #define DDRPHY_DX8GCR1_DXPDRMODE_MASK            (0xFFFF0000U)
33501 #define DDRPHY_DX8GCR1_DXPDRMODE_SHIFT           (16U)
33502 /*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
33503  */
33504 #define DDRPHY_DX8GCR1_DXPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX8GCR1_DXPDRMODE_MASK)
33505 /*! @} */
33506 
33507 /*! @name DX8GCR2 - DATX8 n General Configuration Register 2 */
33508 /*! @{ */
33509 #define DDRPHY_DX8GCR2_DXTEMODE_MASK             (0xFFFFU)
33510 #define DDRPHY_DX8GCR2_DXTEMODE_SHIFT            (0U)
33511 /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
33512  */
33513 #define DDRPHY_DX8GCR2_DXTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX8GCR2_DXTEMODE_MASK)
33514 #define DDRPHY_DX8GCR2_DXOEMODE_MASK             (0xFFFF0000U)
33515 #define DDRPHY_DX8GCR2_DXOEMODE_SHIFT            (16U)
33516 /*! DXOEMODE - Enables the OE mode values for DQ[7:0]
33517  */
33518 #define DDRPHY_DX8GCR2_DXOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX8GCR2_DXOEMODE_MASK)
33519 /*! @} */
33520 
33521 /*! @name DX8GCR3 - DATX8 n General Configuration Register 3 */
33522 /*! @{ */
33523 #define DDRPHY_DX8GCR3_WDMBVT_MASK               (0x1U)
33524 #define DDRPHY_DX8GCR3_WDMBVT_SHIFT              (0U)
33525 /*! WDMBVT - Write Data Mask BDL VT Compensation
33526  */
33527 #define DDRPHY_DX8GCR3_WDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDMBVT_SHIFT)) & DDRPHY_DX8GCR3_WDMBVT_MASK)
33528 #define DDRPHY_DX8GCR3_RDMBVT_MASK               (0x2U)
33529 #define DDRPHY_DX8GCR3_RDMBVT_SHIFT              (1U)
33530 /*! RDMBVT - Read Data Mask BDL VT Compensation
33531  */
33532 #define DDRPHY_DX8GCR3_RDMBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RDMBVT_SHIFT)) & DDRPHY_DX8GCR3_RDMBVT_MASK)
33533 #define DDRPHY_DX8GCR3_DSPDRMODE_MASK            (0xCU)
33534 #define DDRPHY_DX8GCR3_DSPDRMODE_SHIFT           (2U)
33535 /*! DSPDRMODE - Enables the PDR mode values for DQS.
33536  */
33537 #define DDRPHY_DX8GCR3_DSPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX8GCR3_DSPDRMODE_MASK)
33538 #define DDRPHY_DX8GCR3_DSTEMODE_MASK             (0x30U)
33539 #define DDRPHY_DX8GCR3_DSTEMODE_SHIFT            (4U)
33540 /*! DSTEMODE - Enables the TE mode values for DQS.
33541  */
33542 #define DDRPHY_DX8GCR3_DSTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSTEMODE_MASK)
33543 #define DDRPHY_DX8GCR3_DSOEMODE_MASK             (0xC0U)
33544 #define DDRPHY_DX8GCR3_DSOEMODE_SHIFT            (6U)
33545 /*! DSOEMODE - Enables the OE mode values for DQS.
33546  */
33547 #define DDRPHY_DX8GCR3_DSOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSOEMODE_MASK)
33548 #define DDRPHY_DX8GCR3_WDSBVT_MASK               (0x100U)
33549 #define DDRPHY_DX8GCR3_WDSBVT_SHIFT              (8U)
33550 /*! WDSBVT - Write Data Strobe BDL VT Compensation
33551  */
33552 #define DDRPHY_DX8GCR3_WDSBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDSBVT_SHIFT)) & DDRPHY_DX8GCR3_WDSBVT_MASK)
33553 #define DDRPHY_DX8GCR3_RESERVED_9_MASK           (0x200U)
33554 #define DDRPHY_DX8GCR3_RESERVED_9_SHIFT          (9U)
33555 /*! RESERVED_9 - Reserved. Returns zeroes on reads.
33556  */
33557 #define DDRPHY_DX8GCR3_RESERVED_9(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX8GCR3_RESERVED_9_MASK)
33558 #define DDRPHY_DX8GCR3_DMPDRMODE_MASK            (0xC00U)
33559 #define DDRPHY_DX8GCR3_DMPDRMODE_SHIFT           (10U)
33560 /*! DMPDRMODE - Enables the PDR mode values for DM.
33561  */
33562 #define DDRPHY_DX8GCR3_DMPDRMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX8GCR3_DMPDRMODE_MASK)
33563 #define DDRPHY_DX8GCR3_DMTEMODE_MASK             (0x3000U)
33564 #define DDRPHY_DX8GCR3_DMTEMODE_SHIFT            (12U)
33565 /*! DMTEMODE - Enables the TE mode values for DM.
33566  */
33567 #define DDRPHY_DX8GCR3_DMTEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX8GCR3_DMTEMODE_MASK)
33568 #define DDRPHY_DX8GCR3_DMOEMODE_MASK             (0xC000U)
33569 #define DDRPHY_DX8GCR3_DMOEMODE_SHIFT            (14U)
33570 /*! DMOEMODE - Enables the OE mode values for DM.
33571  */
33572 #define DDRPHY_DX8GCR3_DMOEMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX8GCR3_DMOEMODE_MASK)
33573 #define DDRPHY_DX8GCR3_DSNPDRMODE_MASK           (0x30000U)
33574 #define DDRPHY_DX8GCR3_DSNPDRMODE_SHIFT          (16U)
33575 /*! DSNPDRMODE - Enables the PDR mode for DQS
33576  */
33577 #define DDRPHY_DX8GCR3_DSNPDRMODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX8GCR3_DSNPDRMODE_MASK)
33578 #define DDRPHY_DX8GCR3_DSNTEMODE_MASK            (0xC0000U)
33579 #define DDRPHY_DX8GCR3_DSNTEMODE_SHIFT           (18U)
33580 /*! DSNTEMODE - Enables the TE mode for DQS
33581  */
33582 #define DDRPHY_DX8GCR3_DSNTEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSNTEMODE_MASK)
33583 #define DDRPHY_DX8GCR3_DSNOEMODE_MASK            (0x300000U)
33584 #define DDRPHY_DX8GCR3_DSNOEMODE_SHIFT           (20U)
33585 /*! DSNOEMODE - Enables the OE mode for DQs
33586  */
33587 #define DDRPHY_DX8GCR3_DSNOEMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSNOEMODE_MASK)
33588 #define DDRPHY_DX8GCR3_PDRBVT_MASK               (0x400000U)
33589 #define DDRPHY_DX8GCR3_PDRBVT_SHIFT              (22U)
33590 /*! PDRBVT - Power Down Receiver BDL VT Compensation
33591  */
33592 #define DDRPHY_DX8GCR3_PDRBVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_PDRBVT_SHIFT)) & DDRPHY_DX8GCR3_PDRBVT_MASK)
33593 #define DDRPHY_DX8GCR3_RGSLVT_MASK               (0x800000U)
33594 #define DDRPHY_DX8GCR3_RGSLVT_SHIFT              (23U)
33595 /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
33596  */
33597 #define DDRPHY_DX8GCR3_RGSLVT(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RGSLVT_SHIFT)) & DDRPHY_DX8GCR3_RGSLVT_MASK)
33598 #define DDRPHY_DX8GCR3_WLLVT_MASK                (0x1000000U)
33599 #define DDRPHY_DX8GCR3_WLLVT_SHIFT               (24U)
33600 /*! WLLVT - Write Leveling LCDL Delay VT Compensation
33601  */
33602 #define DDRPHY_DX8GCR3_WLLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WLLVT_SHIFT)) & DDRPHY_DX8GCR3_WLLVT_MASK)
33603 #define DDRPHY_DX8GCR3_WDLVT_MASK                (0x2000000U)
33604 #define DDRPHY_DX8GCR3_WDLVT_SHIFT               (25U)
33605 /*! WDLVT - Write DQ LCDL Delay VT Compensation
33606  */
33607 #define DDRPHY_DX8GCR3_WDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDLVT_SHIFT)) & DDRPHY_DX8GCR3_WDLVT_MASK)
33608 #define DDRPHY_DX8GCR3_RDLVT_MASK                (0x4000000U)
33609 #define DDRPHY_DX8GCR3_RDLVT_SHIFT               (26U)
33610 /*! RDLVT - Read DQS LCDL Delay VT Compensation
33611  */
33612 #define DDRPHY_DX8GCR3_RDLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RDLVT_SHIFT)) & DDRPHY_DX8GCR3_RDLVT_MASK)
33613 #define DDRPHY_DX8GCR3_RGLVT_MASK                (0x8000000U)
33614 #define DDRPHY_DX8GCR3_RGLVT_SHIFT               (27U)
33615 /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
33616  */
33617 #define DDRPHY_DX8GCR3_RGLVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RGLVT_SHIFT)) & DDRPHY_DX8GCR3_RGLVT_MASK)
33618 #define DDRPHY_DX8GCR3_WDBVT_MASK                (0x10000000U)
33619 #define DDRPHY_DX8GCR3_WDBVT_SHIFT               (28U)
33620 /*! WDBVT - Write Data BDL VT Compensation
33621  */
33622 #define DDRPHY_DX8GCR3_WDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDBVT_SHIFT)) & DDRPHY_DX8GCR3_WDBVT_MASK)
33623 #define DDRPHY_DX8GCR3_RDBVT_MASK                (0x20000000U)
33624 #define DDRPHY_DX8GCR3_RDBVT_SHIFT               (29U)
33625 /*! RDBVT - Read Data BDL VT Compensation
33626  */
33627 #define DDRPHY_DX8GCR3_RDBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RDBVT_SHIFT)) & DDRPHY_DX8GCR3_RDBVT_MASK)
33628 #define DDRPHY_DX8GCR3_TEBVT_MASK                (0x40000000U)
33629 #define DDRPHY_DX8GCR3_TEBVT_SHIFT               (30U)
33630 /*! TEBVT - Termination Enable BDL VT Compensation
33631  */
33632 #define DDRPHY_DX8GCR3_TEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_TEBVT_SHIFT)) & DDRPHY_DX8GCR3_TEBVT_MASK)
33633 #define DDRPHY_DX8GCR3_OEBVT_MASK                (0x80000000U)
33634 #define DDRPHY_DX8GCR3_OEBVT_SHIFT               (31U)
33635 /*! OEBVT - Output Enable BDL VT Compensation
33636  */
33637 #define DDRPHY_DX8GCR3_OEBVT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_OEBVT_SHIFT)) & DDRPHY_DX8GCR3_OEBVT_MASK)
33638 /*! @} */
33639 
33640 /*! @name DX8GCR4 - DATX8 n General Configuration Register 4 */
33641 /*! @{ */
33642 #define DDRPHY_DX8GCR4_DXREFIMON_MASK            (0x3U)
33643 #define DDRPHY_DX8GCR4_DXREFIMON_SHIFT           (0U)
33644 /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
33645  */
33646 #define DDRPHY_DX8GCR4_DXREFIMON(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX8GCR4_DXREFIMON_MASK)
33647 #define DDRPHY_DX8GCR4_DXREFIEN_MASK             (0x3CU)
33648 #define DDRPHY_DX8GCR4_DXREFIEN_SHIFT            (2U)
33649 /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
33650  */
33651 #define DDRPHY_DX8GCR4_DXREFIEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFIEN_MASK)
33652 #define DDRPHY_DX8GCR4_RESERVED_7_6_MASK         (0xC0U)
33653 #define DDRPHY_DX8GCR4_RESERVED_7_6_SHIFT        (6U)
33654 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
33655  */
33656 #define DDRPHY_DX8GCR4_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR4_RESERVED_7_6_MASK)
33657 #define DDRPHY_DX8GCR4_DXREFSSEL_MASK            (0x7F00U)
33658 #define DDRPHY_DX8GCR4_DXREFSSEL_SHIFT           (8U)
33659 /*! DXREFSSEL - Byte Lane Single-End VREF Select
33660  */
33661 #define DDRPHY_DX8GCR4_DXREFSSEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX8GCR4_DXREFSSEL_MASK)
33662 #define DDRPHY_DX8GCR4_DXREFSSELRANGE_MASK       (0x8000U)
33663 #define DDRPHY_DX8GCR4_DXREFSSELRANGE_SHIFT      (15U)
33664 /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
33665  */
33666 #define DDRPHY_DX8GCR4_DXREFSSELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX8GCR4_DXREFSSELRANGE_MASK)
33667 #define DDRPHY_DX8GCR4_DXREFESEL_MASK            (0x7F0000U)
33668 #define DDRPHY_DX8GCR4_DXREFESEL_SHIFT           (16U)
33669 /*! DXREFESEL - Byte Lane External VREF Select
33670  */
33671 #define DDRPHY_DX8GCR4_DXREFESEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX8GCR4_DXREFESEL_MASK)
33672 #define DDRPHY_DX8GCR4_DXREFESELRANGE_MASK       (0x800000U)
33673 #define DDRPHY_DX8GCR4_DXREFESELRANGE_SHIFT      (23U)
33674 /*! DXREFESELRANGE - External VREF generator REFSEL range select
33675  */
33676 #define DDRPHY_DX8GCR4_DXREFESELRANGE(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX8GCR4_DXREFESELRANGE_MASK)
33677 #define DDRPHY_DX8GCR4_RESERVED_24_MASK          (0x1000000U)
33678 #define DDRPHY_DX8GCR4_RESERVED_24_SHIFT         (24U)
33679 /*! RESERVED_24 - Reserved. Returns zeros on reads.
33680  */
33681 #define DDRPHY_DX8GCR4_RESERVED_24(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX8GCR4_RESERVED_24_MASK)
33682 #define DDRPHY_DX8GCR4_DXREFSEN_MASK             (0x2000000U)
33683 #define DDRPHY_DX8GCR4_DXREFSEN_SHIFT            (25U)
33684 /*! DXREFSEN - Byte Lane Single-End VREF Enable
33685  */
33686 #define DDRPHY_DX8GCR4_DXREFSEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFSEN_MASK)
33687 #define DDRPHY_DX8GCR4_DXREFEEN_MASK             (0xC000000U)
33688 #define DDRPHY_DX8GCR4_DXREFEEN_SHIFT            (26U)
33689 /*! DXREFEEN - Byte Lane Internal VREF Enable
33690  */
33691 #define DDRPHY_DX8GCR4_DXREFEEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFEEN_MASK)
33692 #define DDRPHY_DX8GCR4_DXREFPEN_MASK             (0x10000000U)
33693 #define DDRPHY_DX8GCR4_DXREFPEN_SHIFT            (28U)
33694 /*! DXREFPEN - Byte Lane VREF Pad Enable
33695  */
33696 #define DDRPHY_DX8GCR4_DXREFPEN(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFPEN_MASK)
33697 #define DDRPHY_DX8GCR4_RESERVED_31_29_MASK       (0xE0000000U)
33698 #define DDRPHY_DX8GCR4_RESERVED_31_29_SHIFT      (29U)
33699 /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
33700  */
33701 #define DDRPHY_DX8GCR4_RESERVED_31_29(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX8GCR4_RESERVED_31_29_MASK)
33702 /*! @} */
33703 
33704 /*! @name DX8GCR5 - DATX8 n General Configuration Register 5 */
33705 /*! @{ */
33706 #define DDRPHY_DX8GCR5_DXREFISELR0_MASK          (0x7FU)
33707 #define DDRPHY_DX8GCR5_DXREFISELR0_SHIFT         (0U)
33708 /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
33709  */
33710 #define DDRPHY_DX8GCR5_DXREFISELR0(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR0_MASK)
33711 #define DDRPHY_DX8GCR5_RESERVED_7_MASK           (0x80U)
33712 #define DDRPHY_DX8GCR5_RESERVED_7_SHIFT          (7U)
33713 /*! RESERVED_7 - Reserved. Returns zeros on reads.
33714  */
33715 #define DDRPHY_DX8GCR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_7_MASK)
33716 #define DDRPHY_DX8GCR5_DXREFISELR1_MASK          (0x7F00U)
33717 #define DDRPHY_DX8GCR5_DXREFISELR1_SHIFT         (8U)
33718 /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
33719  */
33720 #define DDRPHY_DX8GCR5_DXREFISELR1(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR1_MASK)
33721 #define DDRPHY_DX8GCR5_RESERVED_15_MASK          (0x8000U)
33722 #define DDRPHY_DX8GCR5_RESERVED_15_SHIFT         (15U)
33723 /*! RESERVED_15 - Reserved. Returns zeros on reads.
33724  */
33725 #define DDRPHY_DX8GCR5_RESERVED_15(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_15_MASK)
33726 #define DDRPHY_DX8GCR5_DXREFISELR2_MASK          (0x7F0000U)
33727 #define DDRPHY_DX8GCR5_DXREFISELR2_SHIFT         (16U)
33728 /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
33729  */
33730 #define DDRPHY_DX8GCR5_DXREFISELR2(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR2_MASK)
33731 #define DDRPHY_DX8GCR5_RESERVED_23_MASK          (0x800000U)
33732 #define DDRPHY_DX8GCR5_RESERVED_23_SHIFT         (23U)
33733 /*! RESERVED_23 - Reserved. Returns zeros on reads.
33734  */
33735 #define DDRPHY_DX8GCR5_RESERVED_23(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_23_MASK)
33736 #define DDRPHY_DX8GCR5_DXREFISELR3_MASK          (0x7F000000U)
33737 #define DDRPHY_DX8GCR5_DXREFISELR3_SHIFT         (24U)
33738 /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
33739  */
33740 #define DDRPHY_DX8GCR5_DXREFISELR3(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR3_MASK)
33741 #define DDRPHY_DX8GCR5_RESERVED_31_MASK          (0x80000000U)
33742 #define DDRPHY_DX8GCR5_RESERVED_31_SHIFT         (31U)
33743 /*! RESERVED_31 - Reserved. Returns zeros on reads.
33744  */
33745 #define DDRPHY_DX8GCR5_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_31_MASK)
33746 /*! @} */
33747 
33748 /*! @name DX8GCR6 - DATX8 n General Configuration Register 6 */
33749 /*! @{ */
33750 #define DDRPHY_DX8GCR6_DXDQVREFR0_MASK           (0x3FU)
33751 #define DDRPHY_DX8GCR6_DXDQVREFR0_SHIFT          (0U)
33752 /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
33753  */
33754 #define DDRPHY_DX8GCR6_DXDQVREFR0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR0_MASK)
33755 #define DDRPHY_DX8GCR6_RESERVED_7_6_MASK         (0xC0U)
33756 #define DDRPHY_DX8GCR6_RESERVED_7_6_SHIFT        (6U)
33757 /*! RESERVED_7_6 - Reserved. Returns zeros on reads.
33758  */
33759 #define DDRPHY_DX8GCR6_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_7_6_MASK)
33760 #define DDRPHY_DX8GCR6_DXDQVREFR1_MASK           (0x3F00U)
33761 #define DDRPHY_DX8GCR6_DXDQVREFR1_SHIFT          (8U)
33762 /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
33763  */
33764 #define DDRPHY_DX8GCR6_DXDQVREFR1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR1_MASK)
33765 #define DDRPHY_DX8GCR6_RESERVED_15_14_MASK       (0xC000U)
33766 #define DDRPHY_DX8GCR6_RESERVED_15_14_SHIFT      (14U)
33767 /*! RESERVED_15_14 - Reserved. Returns zeros on reads.
33768  */
33769 #define DDRPHY_DX8GCR6_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_15_14_MASK)
33770 #define DDRPHY_DX8GCR6_DXDQVREFR2_MASK           (0x3F0000U)
33771 #define DDRPHY_DX8GCR6_DXDQVREFR2_SHIFT          (16U)
33772 /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
33773  */
33774 #define DDRPHY_DX8GCR6_DXDQVREFR2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR2_MASK)
33775 #define DDRPHY_DX8GCR6_RESERVED_23_22_MASK       (0xC00000U)
33776 #define DDRPHY_DX8GCR6_RESERVED_23_22_SHIFT      (22U)
33777 /*! RESERVED_23_22 - Reserved. Returns zeros on reads.
33778  */
33779 #define DDRPHY_DX8GCR6_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_23_22_MASK)
33780 #define DDRPHY_DX8GCR6_DXDQVREFR3_MASK           (0x3F000000U)
33781 #define DDRPHY_DX8GCR6_DXDQVREFR3_SHIFT          (24U)
33782 /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
33783  */
33784 #define DDRPHY_DX8GCR6_DXDQVREFR3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR3_MASK)
33785 #define DDRPHY_DX8GCR6_RESERVED_31_30_MASK       (0xC0000000U)
33786 #define DDRPHY_DX8GCR6_RESERVED_31_30_SHIFT      (30U)
33787 /*! RESERVED_31_30 - Reserved. Returns zeros on reads.
33788  */
33789 #define DDRPHY_DX8GCR6_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_31_30_MASK)
33790 /*! @} */
33791 
33792 /*! @name DX8GCR7 - DATX8 n General Configuration Register 7 */
33793 /*! @{ */
33794 #define DDRPHY_DX8GCR7_DCALSVAL_MASK             (0x1FFU)
33795 #define DDRPHY_DX8GCR7_DCALSVAL_SHIFT            (0U)
33796 /*! DCALSVAL - DDL Calibration Starting Value
33797  */
33798 #define DDRPHY_DX8GCR7_DCALSVAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX8GCR7_DCALSVAL_MASK)
33799 #define DDRPHY_DX8GCR7_DCALTYPE_MASK             (0x200U)
33800 #define DDRPHY_DX8GCR7_DCALTYPE_SHIFT            (9U)
33801 /*! DCALTYPE - DDL Calibration Type
33802  */
33803 #define DDRPHY_DX8GCR7_DCALTYPE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX8GCR7_DCALTYPE_MASK)
33804 #define DDRPHY_DX8GCR7_RESERVED_17_10_MASK       (0x3FC00U)
33805 #define DDRPHY_DX8GCR7_RESERVED_17_10_SHIFT      (10U)
33806 /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
33807  */
33808 #define DDRPHY_DX8GCR7_RESERVED_17_10(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX8GCR7_RESERVED_17_10_MASK)
33809 #define DDRPHY_DX8GCR7_RESERVED_18_MASK          (0x40000U)
33810 #define DDRPHY_DX8GCR7_RESERVED_18_SHIFT         (18U)
33811 /*! RESERVED_18 - Reserved. Caution, do not write to this register field.
33812  */
33813 #define DDRPHY_DX8GCR7_RESERVED_18(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX8GCR7_RESERVED_18_MASK)
33814 #define DDRPHY_DX8GCR7_RESERVED_31_19_MASK       (0xFFF80000U)
33815 #define DDRPHY_DX8GCR7_RESERVED_31_19_SHIFT      (19U)
33816 /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
33817  */
33818 #define DDRPHY_DX8GCR7_RESERVED_31_19(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX8GCR7_RESERVED_31_19_MASK)
33819 /*! @} */
33820 
33821 /*! @name DX8GCR8 - DATX8 n General Configuration Register 8 */
33822 /*! @{ */
33823 #define DDRPHY_DX8GCR8_RESERVED_5_0_MASK         (0x3FU)
33824 #define DDRPHY_DX8GCR8_RESERVED_5_0_SHIFT        (0U)
33825 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
33826  */
33827 #define DDRPHY_DX8GCR8_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_5_0_MASK)
33828 #define DDRPHY_DX8GCR8_RESERVED_7_6_MASK         (0xC0U)
33829 #define DDRPHY_DX8GCR8_RESERVED_7_6_SHIFT        (6U)
33830 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
33831  */
33832 #define DDRPHY_DX8GCR8_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_7_6_MASK)
33833 #define DDRPHY_DX8GCR8_RESERVED_13_8_MASK        (0x3F00U)
33834 #define DDRPHY_DX8GCR8_RESERVED_13_8_SHIFT       (8U)
33835 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
33836  */
33837 #define DDRPHY_DX8GCR8_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_13_8_MASK)
33838 #define DDRPHY_DX8GCR8_RESERVED_15_14_MASK       (0xC000U)
33839 #define DDRPHY_DX8GCR8_RESERVED_15_14_SHIFT      (14U)
33840 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
33841  */
33842 #define DDRPHY_DX8GCR8_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_15_14_MASK)
33843 #define DDRPHY_DX8GCR8_RESERVED_21_16_MASK       (0x3F0000U)
33844 #define DDRPHY_DX8GCR8_RESERVED_21_16_SHIFT      (16U)
33845 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
33846  */
33847 #define DDRPHY_DX8GCR8_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_21_16_MASK)
33848 #define DDRPHY_DX8GCR8_RESERVED_23_22_MASK       (0xC00000U)
33849 #define DDRPHY_DX8GCR8_RESERVED_23_22_SHIFT      (22U)
33850 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
33851  */
33852 #define DDRPHY_DX8GCR8_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_23_22_MASK)
33853 #define DDRPHY_DX8GCR8_RESERVED_29_24_MASK       (0x3F000000U)
33854 #define DDRPHY_DX8GCR8_RESERVED_29_24_SHIFT      (24U)
33855 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
33856  */
33857 #define DDRPHY_DX8GCR8_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_29_24_MASK)
33858 #define DDRPHY_DX8GCR8_RESERVED_31_30_MASK       (0xC0000000U)
33859 #define DDRPHY_DX8GCR8_RESERVED_31_30_SHIFT      (30U)
33860 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
33861  */
33862 #define DDRPHY_DX8GCR8_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_31_30_MASK)
33863 /*! @} */
33864 
33865 /*! @name DX8GCR9 - DATX8 n General Configuration Register 9 */
33866 /*! @{ */
33867 #define DDRPHY_DX8GCR9_RESERVED_5_0_MASK         (0x3FU)
33868 #define DDRPHY_DX8GCR9_RESERVED_5_0_SHIFT        (0U)
33869 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
33870  */
33871 #define DDRPHY_DX8GCR9_RESERVED_5_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_5_0_MASK)
33872 #define DDRPHY_DX8GCR9_RESERVED_7_6_MASK         (0xC0U)
33873 #define DDRPHY_DX8GCR9_RESERVED_7_6_SHIFT        (6U)
33874 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
33875  */
33876 #define DDRPHY_DX8GCR9_RESERVED_7_6(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_7_6_MASK)
33877 #define DDRPHY_DX8GCR9_RESERVED_13_8_MASK        (0x3F00U)
33878 #define DDRPHY_DX8GCR9_RESERVED_13_8_SHIFT       (8U)
33879 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
33880  */
33881 #define DDRPHY_DX8GCR9_RESERVED_13_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_13_8_MASK)
33882 #define DDRPHY_DX8GCR9_RESERVED_15_14_MASK       (0xC000U)
33883 #define DDRPHY_DX8GCR9_RESERVED_15_14_SHIFT      (14U)
33884 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
33885  */
33886 #define DDRPHY_DX8GCR9_RESERVED_15_14(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_15_14_MASK)
33887 #define DDRPHY_DX8GCR9_RESERVED_21_16_MASK       (0x3F0000U)
33888 #define DDRPHY_DX8GCR9_RESERVED_21_16_SHIFT      (16U)
33889 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
33890  */
33891 #define DDRPHY_DX8GCR9_RESERVED_21_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_21_16_MASK)
33892 #define DDRPHY_DX8GCR9_RESERVED_23_22_MASK       (0xC00000U)
33893 #define DDRPHY_DX8GCR9_RESERVED_23_22_SHIFT      (22U)
33894 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
33895  */
33896 #define DDRPHY_DX8GCR9_RESERVED_23_22(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_23_22_MASK)
33897 #define DDRPHY_DX8GCR9_RESERVED_29_24_MASK       (0x3F000000U)
33898 #define DDRPHY_DX8GCR9_RESERVED_29_24_SHIFT      (24U)
33899 /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
33900  */
33901 #define DDRPHY_DX8GCR9_RESERVED_29_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_29_24_MASK)
33902 #define DDRPHY_DX8GCR9_RESERVED_31_30_MASK       (0xC0000000U)
33903 #define DDRPHY_DX8GCR9_RESERVED_31_30_SHIFT      (30U)
33904 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
33905  */
33906 #define DDRPHY_DX8GCR9_RESERVED_31_30(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_31_30_MASK)
33907 /*! @} */
33908 
33909 /*! @name DX8DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
33910 /*! @{ */
33911 #define DDRPHY_DX8DQMAP0_DQ0MAP_MASK             (0xFU)
33912 #define DDRPHY_DX8DQMAP0_DQ0MAP_SHIFT            (0U)
33913 /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
33914  */
33915 #define DDRPHY_DX8DQMAP0_DQ0MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ0MAP_MASK)
33916 #define DDRPHY_DX8DQMAP0_DQ1MAP_MASK             (0xF0U)
33917 #define DDRPHY_DX8DQMAP0_DQ1MAP_SHIFT            (4U)
33918 /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
33919  */
33920 #define DDRPHY_DX8DQMAP0_DQ1MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ1MAP_MASK)
33921 #define DDRPHY_DX8DQMAP0_DQ2MAP_MASK             (0xF00U)
33922 #define DDRPHY_DX8DQMAP0_DQ2MAP_SHIFT            (8U)
33923 /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
33924  */
33925 #define DDRPHY_DX8DQMAP0_DQ2MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ2MAP_MASK)
33926 #define DDRPHY_DX8DQMAP0_DQ3MAP_MASK             (0xF000U)
33927 #define DDRPHY_DX8DQMAP0_DQ3MAP_SHIFT            (12U)
33928 /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
33929  */
33930 #define DDRPHY_DX8DQMAP0_DQ3MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ3MAP_MASK)
33931 #define DDRPHY_DX8DQMAP0_DQ4MAP_MASK             (0xF0000U)
33932 #define DDRPHY_DX8DQMAP0_DQ4MAP_SHIFT            (16U)
33933 /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
33934  */
33935 #define DDRPHY_DX8DQMAP0_DQ4MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ4MAP_MASK)
33936 #define DDRPHY_DX8DQMAP0_RESERVED_30_20_MASK     (0x7FF00000U)
33937 #define DDRPHY_DX8DQMAP0_RESERVED_30_20_SHIFT    (20U)
33938 /*! RESERVED_30_20 - Reserved. Return zeroes on reads.
33939  */
33940 #define DDRPHY_DX8DQMAP0_RESERVED_30_20(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX8DQMAP0_RESERVED_30_20_MASK)
33941 #define DDRPHY_DX8DQMAP0_MAPOK_MASK              (0x80000000U)
33942 #define DDRPHY_DX8DQMAP0_MAPOK_SHIFT             (31U)
33943 /*! MAPOK - Checksum bit
33944  */
33945 #define DDRPHY_DX8DQMAP0_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX8DQMAP0_MAPOK_MASK)
33946 /*! @} */
33947 
33948 /*! @name DX8DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
33949 /*! @{ */
33950 #define DDRPHY_DX8DQMAP1_DQ5MAP_MASK             (0xFU)
33951 #define DDRPHY_DX8DQMAP1_DQ5MAP_SHIFT            (0U)
33952 /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
33953  */
33954 #define DDRPHY_DX8DQMAP1_DQ5MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX8DQMAP1_DQ5MAP_MASK)
33955 #define DDRPHY_DX8DQMAP1_DQ6MAP_MASK             (0xF0U)
33956 #define DDRPHY_DX8DQMAP1_DQ6MAP_SHIFT            (4U)
33957 /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
33958  */
33959 #define DDRPHY_DX8DQMAP1_DQ6MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX8DQMAP1_DQ6MAP_MASK)
33960 #define DDRPHY_DX8DQMAP1_DQ7MAP_MASK             (0xF00U)
33961 #define DDRPHY_DX8DQMAP1_DQ7MAP_SHIFT            (8U)
33962 /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
33963  */
33964 #define DDRPHY_DX8DQMAP1_DQ7MAP(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX8DQMAP1_DQ7MAP_MASK)
33965 #define DDRPHY_DX8DQMAP1_DMMAP_MASK              (0xF000U)
33966 #define DDRPHY_DX8DQMAP1_DMMAP_SHIFT             (12U)
33967 /*! DMMAP - DM bit DATX8 slice mapping index
33968  */
33969 #define DDRPHY_DX8DQMAP1_DMMAP(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX8DQMAP1_DMMAP_MASK)
33970 #define DDRPHY_DX8DQMAP1_RESERVED_30_16_MASK     (0x7FFF0000U)
33971 #define DDRPHY_DX8DQMAP1_RESERVED_30_16_SHIFT    (16U)
33972 /*! RESERVED_30_16 - Reserved. Return zeroes on reads.
33973  */
33974 #define DDRPHY_DX8DQMAP1_RESERVED_30_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX8DQMAP1_RESERVED_30_16_MASK)
33975 #define DDRPHY_DX8DQMAP1_MAPOK_MASK              (0x80000000U)
33976 #define DDRPHY_DX8DQMAP1_MAPOK_SHIFT             (31U)
33977 /*! MAPOK - Checksum bit
33978  */
33979 #define DDRPHY_DX8DQMAP1_MAPOK(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX8DQMAP1_MAPOK_MASK)
33980 /*! @} */
33981 
33982 /*! @name DX8BDLR0 - DATX8 n Bit Delay Line Register 0 */
33983 /*! @{ */
33984 #define DDRPHY_DX8BDLR0_DQ0WBD_MASK              (0x3FU)
33985 #define DDRPHY_DX8BDLR0_DQ0WBD_SHIFT             (0U)
33986 /*! DQ0WBD - DQ0 Write Bit Delay
33987  */
33988 #define DDRPHY_DX8BDLR0_DQ0WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ0WBD_MASK)
33989 #define DDRPHY_DX8BDLR0_RESERVED_7_6_MASK        (0xC0U)
33990 #define DDRPHY_DX8BDLR0_RESERVED_7_6_SHIFT       (6U)
33991 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
33992  */
33993 #define DDRPHY_DX8BDLR0_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_7_6_MASK)
33994 #define DDRPHY_DX8BDLR0_DQ1WBD_MASK              (0x3F00U)
33995 #define DDRPHY_DX8BDLR0_DQ1WBD_SHIFT             (8U)
33996 /*! DQ1WBD - DQ1 Write Bit Delay
33997  */
33998 #define DDRPHY_DX8BDLR0_DQ1WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ1WBD_MASK)
33999 #define DDRPHY_DX8BDLR0_RESERVED_15_14_MASK      (0xC000U)
34000 #define DDRPHY_DX8BDLR0_RESERVED_15_14_SHIFT     (14U)
34001 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34002  */
34003 #define DDRPHY_DX8BDLR0_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_15_14_MASK)
34004 #define DDRPHY_DX8BDLR0_DQ2WBD_MASK              (0x3F0000U)
34005 #define DDRPHY_DX8BDLR0_DQ2WBD_SHIFT             (16U)
34006 /*! DQ2WBD - DQ2 Write Bit Delay
34007  */
34008 #define DDRPHY_DX8BDLR0_DQ2WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ2WBD_MASK)
34009 #define DDRPHY_DX8BDLR0_RESERVED_23_22_MASK      (0xC00000U)
34010 #define DDRPHY_DX8BDLR0_RESERVED_23_22_SHIFT     (22U)
34011 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34012  */
34013 #define DDRPHY_DX8BDLR0_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_23_22_MASK)
34014 #define DDRPHY_DX8BDLR0_DQ3WBD_MASK              (0x3F000000U)
34015 #define DDRPHY_DX8BDLR0_DQ3WBD_SHIFT             (24U)
34016 /*! DQ3WBD - DQ3 Write Bit Delay
34017  */
34018 #define DDRPHY_DX8BDLR0_DQ3WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ3WBD_MASK)
34019 #define DDRPHY_DX8BDLR0_RESERVED_31_30_MASK      (0xC0000000U)
34020 #define DDRPHY_DX8BDLR0_RESERVED_31_30_SHIFT     (30U)
34021 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34022  */
34023 #define DDRPHY_DX8BDLR0_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_31_30_MASK)
34024 /*! @} */
34025 
34026 /*! @name DX8BDLR1 - DATX8 n Bit Delay Line Register 1 */
34027 /*! @{ */
34028 #define DDRPHY_DX8BDLR1_DQ4WBD_MASK              (0x3FU)
34029 #define DDRPHY_DX8BDLR1_DQ4WBD_SHIFT             (0U)
34030 /*! DQ4WBD - DQ4 Write Bit Delay
34031  */
34032 #define DDRPHY_DX8BDLR1_DQ4WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ4WBD_MASK)
34033 #define DDRPHY_DX8BDLR1_RESERVED_7_6_MASK        (0xC0U)
34034 #define DDRPHY_DX8BDLR1_RESERVED_7_6_SHIFT       (6U)
34035 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34036  */
34037 #define DDRPHY_DX8BDLR1_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_7_6_MASK)
34038 #define DDRPHY_DX8BDLR1_DQ5WBD_MASK              (0x3F00U)
34039 #define DDRPHY_DX8BDLR1_DQ5WBD_SHIFT             (8U)
34040 /*! DQ5WBD - DQ5 Write Bit Delay
34041  */
34042 #define DDRPHY_DX8BDLR1_DQ5WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ5WBD_MASK)
34043 #define DDRPHY_DX8BDLR1_RESERVED_15_14_MASK      (0xC000U)
34044 #define DDRPHY_DX8BDLR1_RESERVED_15_14_SHIFT     (14U)
34045 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34046  */
34047 #define DDRPHY_DX8BDLR1_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_15_14_MASK)
34048 #define DDRPHY_DX8BDLR1_DQ6WBD_MASK              (0x3F0000U)
34049 #define DDRPHY_DX8BDLR1_DQ6WBD_SHIFT             (16U)
34050 /*! DQ6WBD - DQ6 Write Bit Delay
34051  */
34052 #define DDRPHY_DX8BDLR1_DQ6WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ6WBD_MASK)
34053 #define DDRPHY_DX8BDLR1_RESERVED_23_22_MASK      (0xC00000U)
34054 #define DDRPHY_DX8BDLR1_RESERVED_23_22_SHIFT     (22U)
34055 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34056  */
34057 #define DDRPHY_DX8BDLR1_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_23_22_MASK)
34058 #define DDRPHY_DX8BDLR1_DQ7WBD_MASK              (0x3F000000U)
34059 #define DDRPHY_DX8BDLR1_DQ7WBD_SHIFT             (24U)
34060 /*! DQ7WBD - DQ7 Write Bit Delay
34061  */
34062 #define DDRPHY_DX8BDLR1_DQ7WBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ7WBD_MASK)
34063 #define DDRPHY_DX8BDLR1_RESERVED_31_30_MASK      (0xC0000000U)
34064 #define DDRPHY_DX8BDLR1_RESERVED_31_30_SHIFT     (30U)
34065 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34066  */
34067 #define DDRPHY_DX8BDLR1_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_31_30_MASK)
34068 /*! @} */
34069 
34070 /*! @name DX8BDLR2 - DATX8 n Bit Delay Line Register 2 */
34071 /*! @{ */
34072 #define DDRPHY_DX8BDLR2_DMWBD_MASK               (0x3FU)
34073 #define DDRPHY_DX8BDLR2_DMWBD_SHIFT              (0U)
34074 /*! DMWBD - DM Write Bit Delay
34075  */
34076 #define DDRPHY_DX8BDLR2_DMWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DMWBD_SHIFT)) & DDRPHY_DX8BDLR2_DMWBD_MASK)
34077 #define DDRPHY_DX8BDLR2_RESERVED_7_6_MASK        (0xC0U)
34078 #define DDRPHY_DX8BDLR2_RESERVED_7_6_SHIFT       (6U)
34079 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34080  */
34081 #define DDRPHY_DX8BDLR2_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_7_6_MASK)
34082 #define DDRPHY_DX8BDLR2_DSWBD_MASK               (0x3F00U)
34083 #define DDRPHY_DX8BDLR2_DSWBD_SHIFT              (8U)
34084 /*! DSWBD - DQS Write Bit Delay
34085  */
34086 #define DDRPHY_DX8BDLR2_DSWBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DSWBD_SHIFT)) & DDRPHY_DX8BDLR2_DSWBD_MASK)
34087 #define DDRPHY_DX8BDLR2_RESERVED_15_14_MASK      (0xC000U)
34088 #define DDRPHY_DX8BDLR2_RESERVED_15_14_SHIFT     (14U)
34089 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34090  */
34091 #define DDRPHY_DX8BDLR2_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_15_14_MASK)
34092 #define DDRPHY_DX8BDLR2_DSOEBD_MASK              (0x3F0000U)
34093 #define DDRPHY_DX8BDLR2_DSOEBD_SHIFT             (16U)
34094 /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
34095  */
34096 #define DDRPHY_DX8BDLR2_DSOEBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX8BDLR2_DSOEBD_MASK)
34097 #define DDRPHY_DX8BDLR2_RESERVED_23_22_MASK      (0xC00000U)
34098 #define DDRPHY_DX8BDLR2_RESERVED_23_22_SHIFT     (22U)
34099 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34100  */
34101 #define DDRPHY_DX8BDLR2_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_23_22_MASK)
34102 #define DDRPHY_DX8BDLR2_DSNWBD_MASK              (0x3F000000U)
34103 #define DDRPHY_DX8BDLR2_DSNWBD_SHIFT             (24U)
34104 /*! DSNWBD - DQSN Write Bit Delay
34105  */
34106 #define DDRPHY_DX8BDLR2_DSNWBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX8BDLR2_DSNWBD_MASK)
34107 #define DDRPHY_DX8BDLR2_RESERVED_31_30_MASK      (0xC0000000U)
34108 #define DDRPHY_DX8BDLR2_RESERVED_31_30_SHIFT     (30U)
34109 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34110  */
34111 #define DDRPHY_DX8BDLR2_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_31_30_MASK)
34112 /*! @} */
34113 
34114 /*! @name DX8BDLR3 - DATX8 n Bit Delay Line Register 3 */
34115 /*! @{ */
34116 #define DDRPHY_DX8BDLR3_DQ0RBD_MASK              (0x3FU)
34117 #define DDRPHY_DX8BDLR3_DQ0RBD_SHIFT             (0U)
34118 /*! DQ0RBD - DQ0 Read Bit Delay
34119  */
34120 #define DDRPHY_DX8BDLR3_DQ0RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ0RBD_MASK)
34121 #define DDRPHY_DX8BDLR3_RESERVED_7_6_MASK        (0xC0U)
34122 #define DDRPHY_DX8BDLR3_RESERVED_7_6_SHIFT       (6U)
34123 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34124  */
34125 #define DDRPHY_DX8BDLR3_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_7_6_MASK)
34126 #define DDRPHY_DX8BDLR3_DQ1RBD_MASK              (0x3F00U)
34127 #define DDRPHY_DX8BDLR3_DQ1RBD_SHIFT             (8U)
34128 /*! DQ1RBD - DQ1 Read Bit Delay
34129  */
34130 #define DDRPHY_DX8BDLR3_DQ1RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ1RBD_MASK)
34131 #define DDRPHY_DX8BDLR3_RESERVED_15_14_MASK      (0xC000U)
34132 #define DDRPHY_DX8BDLR3_RESERVED_15_14_SHIFT     (14U)
34133 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34134  */
34135 #define DDRPHY_DX8BDLR3_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_15_14_MASK)
34136 #define DDRPHY_DX8BDLR3_DQ2RBD_MASK              (0x3F0000U)
34137 #define DDRPHY_DX8BDLR3_DQ2RBD_SHIFT             (16U)
34138 /*! DQ2RBD - DQ2 Read Bit Delay
34139  */
34140 #define DDRPHY_DX8BDLR3_DQ2RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ2RBD_MASK)
34141 #define DDRPHY_DX8BDLR3_RESERVED_23_22_MASK      (0xC00000U)
34142 #define DDRPHY_DX8BDLR3_RESERVED_23_22_SHIFT     (22U)
34143 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34144  */
34145 #define DDRPHY_DX8BDLR3_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_23_22_MASK)
34146 #define DDRPHY_DX8BDLR3_DQ3RBD_MASK              (0x3F000000U)
34147 #define DDRPHY_DX8BDLR3_DQ3RBD_SHIFT             (24U)
34148 /*! DQ3RBD - DQ3 Read Bit Delay
34149  */
34150 #define DDRPHY_DX8BDLR3_DQ3RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ3RBD_MASK)
34151 #define DDRPHY_DX8BDLR3_RESERVED_31_30_MASK      (0xC0000000U)
34152 #define DDRPHY_DX8BDLR3_RESERVED_31_30_SHIFT     (30U)
34153 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34154  */
34155 #define DDRPHY_DX8BDLR3_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_31_30_MASK)
34156 /*! @} */
34157 
34158 /*! @name DX8BDLR4 - DATX8 n Bit Delay Line Register 4 */
34159 /*! @{ */
34160 #define DDRPHY_DX8BDLR4_DQ4RBD_MASK              (0x3FU)
34161 #define DDRPHY_DX8BDLR4_DQ4RBD_SHIFT             (0U)
34162 /*! DQ4RBD - DQ4 Read Bit Delay
34163  */
34164 #define DDRPHY_DX8BDLR4_DQ4RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ4RBD_MASK)
34165 #define DDRPHY_DX8BDLR4_RESERVED_7_6_MASK        (0xC0U)
34166 #define DDRPHY_DX8BDLR4_RESERVED_7_6_SHIFT       (6U)
34167 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34168  */
34169 #define DDRPHY_DX8BDLR4_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_7_6_MASK)
34170 #define DDRPHY_DX8BDLR4_DQ5RBD_MASK              (0x3F00U)
34171 #define DDRPHY_DX8BDLR4_DQ5RBD_SHIFT             (8U)
34172 /*! DQ5RBD - DQ5 Read Bit Delay
34173  */
34174 #define DDRPHY_DX8BDLR4_DQ5RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ5RBD_MASK)
34175 #define DDRPHY_DX8BDLR4_RESERVED_15_14_MASK      (0xC000U)
34176 #define DDRPHY_DX8BDLR4_RESERVED_15_14_SHIFT     (14U)
34177 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34178  */
34179 #define DDRPHY_DX8BDLR4_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_15_14_MASK)
34180 #define DDRPHY_DX8BDLR4_DQ6RBD_MASK              (0x3F0000U)
34181 #define DDRPHY_DX8BDLR4_DQ6RBD_SHIFT             (16U)
34182 /*! DQ6RBD - DQ6 Read Bit Delay
34183  */
34184 #define DDRPHY_DX8BDLR4_DQ6RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ6RBD_MASK)
34185 #define DDRPHY_DX8BDLR4_RESERVED_23_22_MASK      (0xC00000U)
34186 #define DDRPHY_DX8BDLR4_RESERVED_23_22_SHIFT     (22U)
34187 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34188  */
34189 #define DDRPHY_DX8BDLR4_RESERVED_23_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_23_22_MASK)
34190 #define DDRPHY_DX8BDLR4_DQ7RBD_MASK              (0x3F000000U)
34191 #define DDRPHY_DX8BDLR4_DQ7RBD_SHIFT             (24U)
34192 /*! DQ7RBD - DQ7 Read Bit Delay
34193  */
34194 #define DDRPHY_DX8BDLR4_DQ7RBD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ7RBD_MASK)
34195 #define DDRPHY_DX8BDLR4_RESERVED_31_30_MASK      (0xC0000000U)
34196 #define DDRPHY_DX8BDLR4_RESERVED_31_30_SHIFT     (30U)
34197 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34198  */
34199 #define DDRPHY_DX8BDLR4_RESERVED_31_30(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_31_30_MASK)
34200 /*! @} */
34201 
34202 /*! @name DX8BDLR5 - DATX8 n Bit Delay Line Register 5 */
34203 /*! @{ */
34204 #define DDRPHY_DX8BDLR5_DMRBD_MASK               (0x3FU)
34205 #define DDRPHY_DX8BDLR5_DMRBD_SHIFT              (0U)
34206 /*! DMRBD - DM Read Bit Delay
34207  */
34208 #define DDRPHY_DX8BDLR5_DMRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR5_DMRBD_SHIFT)) & DDRPHY_DX8BDLR5_DMRBD_MASK)
34209 #define DDRPHY_DX8BDLR5_RESERVED_31_6_MASK       (0xFFFFFFC0U)
34210 #define DDRPHY_DX8BDLR5_RESERVED_31_6_SHIFT      (6U)
34211 /*! RESERVED_31_6 - Reserved. Return zeroes on reads.
34212  */
34213 #define DDRPHY_DX8BDLR5_RESERVED_31_6(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX8BDLR5_RESERVED_31_6_MASK)
34214 /*! @} */
34215 
34216 /*! @name DX8BDLR6 - DATX8 n Bit Delay Line Register 6 */
34217 /*! @{ */
34218 #define DDRPHY_DX8BDLR6_RESERVED_7_0_MASK        (0xFFU)
34219 #define DDRPHY_DX8BDLR6_RESERVED_7_0_SHIFT       (0U)
34220 /*! RESERVED_7_0 - Reserved. Return zeroes on reads.
34221  */
34222 #define DDRPHY_DX8BDLR6_RESERVED_7_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX8BDLR6_RESERVED_7_0_MASK)
34223 #define DDRPHY_DX8BDLR6_PDRBD_MASK               (0x3F00U)
34224 #define DDRPHY_DX8BDLR6_PDRBD_SHIFT              (8U)
34225 /*! PDRBD - Power down receiver Bit Delay
34226  */
34227 #define DDRPHY_DX8BDLR6_PDRBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_PDRBD_SHIFT)) & DDRPHY_DX8BDLR6_PDRBD_MASK)
34228 #define DDRPHY_DX8BDLR6_RESERVED_15_14_MASK      (0xC000U)
34229 #define DDRPHY_DX8BDLR6_RESERVED_15_14_SHIFT     (14U)
34230 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34231  */
34232 #define DDRPHY_DX8BDLR6_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR6_RESERVED_15_14_MASK)
34233 #define DDRPHY_DX8BDLR6_TERBD_MASK               (0x3F0000U)
34234 #define DDRPHY_DX8BDLR6_TERBD_SHIFT              (16U)
34235 /*! TERBD - Termination Enable Bit Delay
34236  */
34237 #define DDRPHY_DX8BDLR6_TERBD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_TERBD_SHIFT)) & DDRPHY_DX8BDLR6_TERBD_MASK)
34238 #define DDRPHY_DX8BDLR6_RESERVED_31_22_MASK      (0xFFC00000U)
34239 #define DDRPHY_DX8BDLR6_RESERVED_31_22_SHIFT     (22U)
34240 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
34241  */
34242 #define DDRPHY_DX8BDLR6_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR6_RESERVED_31_22_MASK)
34243 /*! @} */
34244 
34245 /*! @name DX8BDLR7 - DATX8 n Bit Delay Line Register 7 */
34246 /*! @{ */
34247 #define DDRPHY_DX8BDLR7_RESERVED_5_0_MASK        (0x3FU)
34248 #define DDRPHY_DX8BDLR7_RESERVED_5_0_SHIFT       (0U)
34249 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
34250  */
34251 #define DDRPHY_DX8BDLR7_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_5_0_MASK)
34252 #define DDRPHY_DX8BDLR7_RESERVED_7_6_MASK        (0xC0U)
34253 #define DDRPHY_DX8BDLR7_RESERVED_7_6_SHIFT       (6U)
34254 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34255  */
34256 #define DDRPHY_DX8BDLR7_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_7_6_MASK)
34257 #define DDRPHY_DX8BDLR7_RESERVED_13_8_MASK       (0x3F00U)
34258 #define DDRPHY_DX8BDLR7_RESERVED_13_8_SHIFT      (8U)
34259 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
34260  */
34261 #define DDRPHY_DX8BDLR7_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_13_8_MASK)
34262 #define DDRPHY_DX8BDLR7_RESERVED_15_14_MASK      (0xC000U)
34263 #define DDRPHY_DX8BDLR7_RESERVED_15_14_SHIFT     (14U)
34264 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34265  */
34266 #define DDRPHY_DX8BDLR7_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_15_14_MASK)
34267 #define DDRPHY_DX8BDLR7_RESERVED_21_16_MASK      (0x3F0000U)
34268 #define DDRPHY_DX8BDLR7_RESERVED_21_16_SHIFT     (16U)
34269 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
34270  */
34271 #define DDRPHY_DX8BDLR7_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_21_16_MASK)
34272 #define DDRPHY_DX8BDLR7_RESERVED_31_22_MASK      (0xFFC00000U)
34273 #define DDRPHY_DX8BDLR7_RESERVED_31_22_SHIFT     (22U)
34274 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
34275  */
34276 #define DDRPHY_DX8BDLR7_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_31_22_MASK)
34277 /*! @} */
34278 
34279 /*! @name DX8BDLR8 - DATX8 n Bit Delay Line Register 8 */
34280 /*! @{ */
34281 #define DDRPHY_DX8BDLR8_RESERVED_5_0_MASK        (0x3FU)
34282 #define DDRPHY_DX8BDLR8_RESERVED_5_0_SHIFT       (0U)
34283 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
34284  */
34285 #define DDRPHY_DX8BDLR8_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_5_0_MASK)
34286 #define DDRPHY_DX8BDLR8_RESERVED_7_6_MASK        (0xC0U)
34287 #define DDRPHY_DX8BDLR8_RESERVED_7_6_SHIFT       (6U)
34288 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34289  */
34290 #define DDRPHY_DX8BDLR8_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_7_6_MASK)
34291 #define DDRPHY_DX8BDLR8_RESERVED_13_8_MASK       (0x3F00U)
34292 #define DDRPHY_DX8BDLR8_RESERVED_13_8_SHIFT      (8U)
34293 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
34294  */
34295 #define DDRPHY_DX8BDLR8_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_13_8_MASK)
34296 #define DDRPHY_DX8BDLR8_RESERVED_15_14_MASK      (0xC000U)
34297 #define DDRPHY_DX8BDLR8_RESERVED_15_14_SHIFT     (14U)
34298 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34299  */
34300 #define DDRPHY_DX8BDLR8_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_15_14_MASK)
34301 #define DDRPHY_DX8BDLR8_RESERVED_21_16_MASK      (0x3F0000U)
34302 #define DDRPHY_DX8BDLR8_RESERVED_21_16_SHIFT     (16U)
34303 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
34304  */
34305 #define DDRPHY_DX8BDLR8_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_21_16_MASK)
34306 #define DDRPHY_DX8BDLR8_RESERVED_31_22_MASK      (0xFFC00000U)
34307 #define DDRPHY_DX8BDLR8_RESERVED_31_22_SHIFT     (22U)
34308 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
34309  */
34310 #define DDRPHY_DX8BDLR8_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_31_22_MASK)
34311 /*! @} */
34312 
34313 /*! @name DX8BDLR9 - DATX8 n Bit Delay Line Register 9 */
34314 /*! @{ */
34315 #define DDRPHY_DX8BDLR9_RESERVED_5_0_MASK        (0x3FU)
34316 #define DDRPHY_DX8BDLR9_RESERVED_5_0_SHIFT       (0U)
34317 /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
34318  */
34319 #define DDRPHY_DX8BDLR9_RESERVED_5_0(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_5_0_MASK)
34320 #define DDRPHY_DX8BDLR9_RESERVED_7_6_MASK        (0xC0U)
34321 #define DDRPHY_DX8BDLR9_RESERVED_7_6_SHIFT       (6U)
34322 /*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34323  */
34324 #define DDRPHY_DX8BDLR9_RESERVED_7_6(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_7_6_MASK)
34325 #define DDRPHY_DX8BDLR9_RESERVED_13_8_MASK       (0x3F00U)
34326 #define DDRPHY_DX8BDLR9_RESERVED_13_8_SHIFT      (8U)
34327 /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
34328  */
34329 #define DDRPHY_DX8BDLR9_RESERVED_13_8(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_13_8_MASK)
34330 #define DDRPHY_DX8BDLR9_RESERVED_15_14_MASK      (0xC000U)
34331 #define DDRPHY_DX8BDLR9_RESERVED_15_14_SHIFT     (14U)
34332 /*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34333  */
34334 #define DDRPHY_DX8BDLR9_RESERVED_15_14(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_15_14_MASK)
34335 #define DDRPHY_DX8BDLR9_RESERVED_21_16_MASK      (0x3F0000U)
34336 #define DDRPHY_DX8BDLR9_RESERVED_21_16_SHIFT     (16U)
34337 /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
34338  */
34339 #define DDRPHY_DX8BDLR9_RESERVED_21_16(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_21_16_MASK)
34340 #define DDRPHY_DX8BDLR9_RESERVED_31_22_MASK      (0xFFC00000U)
34341 #define DDRPHY_DX8BDLR9_RESERVED_31_22_SHIFT     (22U)
34342 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
34343  */
34344 #define DDRPHY_DX8BDLR9_RESERVED_31_22(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_31_22_MASK)
34345 /*! @} */
34346 
34347 /*! @name DX8LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
34348 /*! @{ */
34349 #define DDRPHY_DX8LCDLR0_WLD_MASK                (0x1FFU)
34350 #define DDRPHY_DX8LCDLR0_WLD_SHIFT               (0U)
34351 /*! WLD - Write Leveling Delay
34352  */
34353 #define DDRPHY_DX8LCDLR0_WLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_WLD_SHIFT)) & DDRPHY_DX8LCDLR0_WLD_MASK)
34354 #define DDRPHY_DX8LCDLR0_RESERVED_15_9_MASK      (0xFE00U)
34355 #define DDRPHY_DX8LCDLR0_RESERVED_15_9_SHIFT     (9U)
34356 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34357  */
34358 #define DDRPHY_DX8LCDLR0_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR0_RESERVED_15_9_MASK)
34359 #define DDRPHY_DX8LCDLR0_RESERVED_24_16_MASK     (0x1FF0000U)
34360 #define DDRPHY_DX8LCDLR0_RESERVED_24_16_SHIFT    (16U)
34361 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34362  */
34363 #define DDRPHY_DX8LCDLR0_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR0_RESERVED_24_16_MASK)
34364 #define DDRPHY_DX8LCDLR0_RESERVED_31_25_MASK     (0xFE000000U)
34365 #define DDRPHY_DX8LCDLR0_RESERVED_31_25_SHIFT    (25U)
34366 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34367  */
34368 #define DDRPHY_DX8LCDLR0_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR0_RESERVED_31_25_MASK)
34369 /*! @} */
34370 
34371 /*! @name DX8LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
34372 /*! @{ */
34373 #define DDRPHY_DX8LCDLR1_WDQD_MASK               (0x1FFU)
34374 #define DDRPHY_DX8LCDLR1_WDQD_SHIFT              (0U)
34375 /*! WDQD - Write Data Delay
34376  */
34377 #define DDRPHY_DX8LCDLR1_WDQD(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_WDQD_SHIFT)) & DDRPHY_DX8LCDLR1_WDQD_MASK)
34378 #define DDRPHY_DX8LCDLR1_RESERVED_15_9_MASK      (0xFE00U)
34379 #define DDRPHY_DX8LCDLR1_RESERVED_15_9_SHIFT     (9U)
34380 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34381  */
34382 #define DDRPHY_DX8LCDLR1_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR1_RESERVED_15_9_MASK)
34383 #define DDRPHY_DX8LCDLR1_RESERVED_24_16_MASK     (0x1FF0000U)
34384 #define DDRPHY_DX8LCDLR1_RESERVED_24_16_SHIFT    (16U)
34385 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34386  */
34387 #define DDRPHY_DX8LCDLR1_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR1_RESERVED_24_16_MASK)
34388 #define DDRPHY_DX8LCDLR1_RESERVED_31_25_MASK     (0xFE000000U)
34389 #define DDRPHY_DX8LCDLR1_RESERVED_31_25_SHIFT    (25U)
34390 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34391  */
34392 #define DDRPHY_DX8LCDLR1_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR1_RESERVED_31_25_MASK)
34393 /*! @} */
34394 
34395 /*! @name DX8LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
34396 /*! @{ */
34397 #define DDRPHY_DX8LCDLR2_DQSGD_MASK              (0x1FFU)
34398 #define DDRPHY_DX8LCDLR2_DQSGD_SHIFT             (0U)
34399 /*! DQSGD - Read DQS Gating Delay
34400  */
34401 #define DDRPHY_DX8LCDLR2_DQSGD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX8LCDLR2_DQSGD_MASK)
34402 #define DDRPHY_DX8LCDLR2_RESERVED_15_9_MASK      (0xFE00U)
34403 #define DDRPHY_DX8LCDLR2_RESERVED_15_9_SHIFT     (9U)
34404 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34405  */
34406 #define DDRPHY_DX8LCDLR2_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR2_RESERVED_15_9_MASK)
34407 #define DDRPHY_DX8LCDLR2_RESERVED_24_16_MASK     (0x1FF0000U)
34408 #define DDRPHY_DX8LCDLR2_RESERVED_24_16_SHIFT    (16U)
34409 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34410  */
34411 #define DDRPHY_DX8LCDLR2_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR2_RESERVED_24_16_MASK)
34412 #define DDRPHY_DX8LCDLR2_RESERVED_31_25_MASK     (0xFE000000U)
34413 #define DDRPHY_DX8LCDLR2_RESERVED_31_25_SHIFT    (25U)
34414 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34415  */
34416 #define DDRPHY_DX8LCDLR2_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR2_RESERVED_31_25_MASK)
34417 /*! @} */
34418 
34419 /*! @name DX8LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
34420 /*! @{ */
34421 #define DDRPHY_DX8LCDLR3_RDQSD_MASK              (0x1FFU)
34422 #define DDRPHY_DX8LCDLR3_RDQSD_SHIFT             (0U)
34423 /*! RDQSD - Read DQS Delay
34424  */
34425 #define DDRPHY_DX8LCDLR3_RDQSD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX8LCDLR3_RDQSD_MASK)
34426 #define DDRPHY_DX8LCDLR3_RESERVED_15_9_MASK      (0xFE00U)
34427 #define DDRPHY_DX8LCDLR3_RESERVED_15_9_SHIFT     (9U)
34428 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34429  */
34430 #define DDRPHY_DX8LCDLR3_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR3_RESERVED_15_9_MASK)
34431 #define DDRPHY_DX8LCDLR3_RESERVED_24_16_MASK     (0x1FF0000U)
34432 #define DDRPHY_DX8LCDLR3_RESERVED_24_16_SHIFT    (16U)
34433 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34434  */
34435 #define DDRPHY_DX8LCDLR3_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR3_RESERVED_24_16_MASK)
34436 #define DDRPHY_DX8LCDLR3_RESERVED_31_25_MASK     (0xFE000000U)
34437 #define DDRPHY_DX8LCDLR3_RESERVED_31_25_SHIFT    (25U)
34438 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34439  */
34440 #define DDRPHY_DX8LCDLR3_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR3_RESERVED_31_25_MASK)
34441 /*! @} */
34442 
34443 /*! @name DX8LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
34444 /*! @{ */
34445 #define DDRPHY_DX8LCDLR4_RDQSND_MASK             (0x1FFU)
34446 #define DDRPHY_DX8LCDLR4_RDQSND_SHIFT            (0U)
34447 /*! RDQSND - Read DQSN Delay
34448  */
34449 #define DDRPHY_DX8LCDLR4_RDQSND(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX8LCDLR4_RDQSND_MASK)
34450 #define DDRPHY_DX8LCDLR4_RESERVED_15_9_MASK      (0xFE00U)
34451 #define DDRPHY_DX8LCDLR4_RESERVED_15_9_SHIFT     (9U)
34452 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34453  */
34454 #define DDRPHY_DX8LCDLR4_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR4_RESERVED_15_9_MASK)
34455 #define DDRPHY_DX8LCDLR4_RESERVED_24_16_MASK     (0x1FF0000U)
34456 #define DDRPHY_DX8LCDLR4_RESERVED_24_16_SHIFT    (16U)
34457 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34458  */
34459 #define DDRPHY_DX8LCDLR4_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR4_RESERVED_24_16_MASK)
34460 #define DDRPHY_DX8LCDLR4_RESERVED_31_25_MASK     (0xFE000000U)
34461 #define DDRPHY_DX8LCDLR4_RESERVED_31_25_SHIFT    (25U)
34462 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34463  */
34464 #define DDRPHY_DX8LCDLR4_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR4_RESERVED_31_25_MASK)
34465 /*! @} */
34466 
34467 /*! @name DX8LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
34468 /*! @{ */
34469 #define DDRPHY_DX8LCDLR5_DQSGSD_MASK             (0x1FFU)
34470 #define DDRPHY_DX8LCDLR5_DQSGSD_SHIFT            (0U)
34471 /*! DQSGSD - DQS Gating Status Delay
34472  */
34473 #define DDRPHY_DX8LCDLR5_DQSGSD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX8LCDLR5_DQSGSD_MASK)
34474 #define DDRPHY_DX8LCDLR5_RESERVED_15_9_MASK      (0xFE00U)
34475 #define DDRPHY_DX8LCDLR5_RESERVED_15_9_SHIFT     (9U)
34476 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34477  */
34478 #define DDRPHY_DX8LCDLR5_RESERVED_15_9(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR5_RESERVED_15_9_MASK)
34479 #define DDRPHY_DX8LCDLR5_RESERVED_24_16_MASK     (0x1FF0000U)
34480 #define DDRPHY_DX8LCDLR5_RESERVED_24_16_SHIFT    (16U)
34481 /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34482  */
34483 #define DDRPHY_DX8LCDLR5_RESERVED_24_16(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR5_RESERVED_24_16_MASK)
34484 #define DDRPHY_DX8LCDLR5_RESERVED_31_25_MASK     (0xFE000000U)
34485 #define DDRPHY_DX8LCDLR5_RESERVED_31_25_SHIFT    (25U)
34486 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34487  */
34488 #define DDRPHY_DX8LCDLR5_RESERVED_31_25(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR5_RESERVED_31_25_MASK)
34489 /*! @} */
34490 
34491 /*! @name DX8MDLR0 - DATX8 n Master Delay Line Register 0 */
34492 /*! @{ */
34493 #define DDRPHY_DX8MDLR0_IPRD_MASK                (0x1FFU)
34494 #define DDRPHY_DX8MDLR0_IPRD_SHIFT               (0U)
34495 /*! IPRD - Initial Period
34496  */
34497 #define DDRPHY_DX8MDLR0_IPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_IPRD_SHIFT)) & DDRPHY_DX8MDLR0_IPRD_MASK)
34498 #define DDRPHY_DX8MDLR0_RESERVED_15_9_MASK       (0xFE00U)
34499 #define DDRPHY_DX8MDLR0_RESERVED_15_9_SHIFT      (9U)
34500 /*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34501  */
34502 #define DDRPHY_DX8MDLR0_RESERVED_15_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX8MDLR0_RESERVED_15_9_MASK)
34503 #define DDRPHY_DX8MDLR0_TPRD_MASK                (0x1FF0000U)
34504 #define DDRPHY_DX8MDLR0_TPRD_SHIFT               (16U)
34505 /*! TPRD - Target Period
34506  */
34507 #define DDRPHY_DX8MDLR0_TPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_TPRD_SHIFT)) & DDRPHY_DX8MDLR0_TPRD_MASK)
34508 #define DDRPHY_DX8MDLR0_RESERVED_31_25_MASK      (0xFE000000U)
34509 #define DDRPHY_DX8MDLR0_RESERVED_31_25_SHIFT     (25U)
34510 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34511  */
34512 #define DDRPHY_DX8MDLR0_RESERVED_31_25(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX8MDLR0_RESERVED_31_25_MASK)
34513 /*! @} */
34514 
34515 /*! @name DX8MDLR1 - DATX8 n Master Delay Line Register 1 */
34516 /*! @{ */
34517 #define DDRPHY_DX8MDLR1_MDLD_MASK                (0x1FFU)
34518 #define DDRPHY_DX8MDLR1_MDLD_SHIFT               (0U)
34519 /*! MDLD - MDL Delay
34520  */
34521 #define DDRPHY_DX8MDLR1_MDLD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR1_MDLD_SHIFT)) & DDRPHY_DX8MDLR1_MDLD_MASK)
34522 #define DDRPHY_DX8MDLR1_RESERVED_31_9_MASK       (0xFFFFFE00U)
34523 #define DDRPHY_DX8MDLR1_RESERVED_31_9_SHIFT      (9U)
34524 /*! RESERVED_31_9 - Reserved. Return zeroes on reads.
34525  */
34526 #define DDRPHY_DX8MDLR1_RESERVED_31_9(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX8MDLR1_RESERVED_31_9_MASK)
34527 /*! @} */
34528 
34529 /*! @name DX8GTR0 - DATX8 n General Timing Register 0 */
34530 /*! @{ */
34531 #define DDRPHY_DX8GTR0_DGSL_MASK                 (0x1FU)
34532 #define DDRPHY_DX8GTR0_DGSL_SHIFT                (0U)
34533 /*! DGSL - DQS Gating System Latency
34534  */
34535 #define DDRPHY_DX8GTR0_DGSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_DGSL_SHIFT)) & DDRPHY_DX8GTR0_DGSL_MASK)
34536 #define DDRPHY_DX8GTR0_RESERVED_7_5_MASK         (0xE0U)
34537 #define DDRPHY_DX8GTR0_RESERVED_7_5_SHIFT        (5U)
34538 /*! RESERVED_7_5 - Reserved. Return zeroes on reads.
34539  */
34540 #define DDRPHY_DX8GTR0_RESERVED_7_5(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_7_5_MASK)
34541 #define DDRPHY_DX8GTR0_RESERVED_12_8_MASK        (0x1F00U)
34542 #define DDRPHY_DX8GTR0_RESERVED_12_8_SHIFT       (8U)
34543 /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
34544  */
34545 #define DDRPHY_DX8GTR0_RESERVED_12_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_12_8_MASK)
34546 #define DDRPHY_DX8GTR0_RESERVED_15_13_MASK       (0xE000U)
34547 #define DDRPHY_DX8GTR0_RESERVED_15_13_SHIFT      (13U)
34548 /*! RESERVED_15_13 - Reserved. Return zeroes on reads.
34549  */
34550 #define DDRPHY_DX8GTR0_RESERVED_15_13(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_15_13_MASK)
34551 #define DDRPHY_DX8GTR0_WLSL_MASK                 (0xF0000U)
34552 #define DDRPHY_DX8GTR0_WLSL_SHIFT                (16U)
34553 /*! WLSL - Write Leveling System Latency
34554  */
34555 #define DDRPHY_DX8GTR0_WLSL(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_WLSL_SHIFT)) & DDRPHY_DX8GTR0_WLSL_MASK)
34556 #define DDRPHY_DX8GTR0_RESERVED_23_20_MASK       (0xF00000U)
34557 #define DDRPHY_DX8GTR0_RESERVED_23_20_SHIFT      (20U)
34558 /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
34559  */
34560 #define DDRPHY_DX8GTR0_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_23_20_MASK)
34561 #define DDRPHY_DX8GTR0_WDQSL_MASK                (0x7000000U)
34562 #define DDRPHY_DX8GTR0_WDQSL_SHIFT               (24U)
34563 /*! WDQSL - DQ Write Path Latency Pipeline
34564  */
34565 #define DDRPHY_DX8GTR0_WDQSL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_WDQSL_SHIFT)) & DDRPHY_DX8GTR0_WDQSL_MASK)
34566 #define DDRPHY_DX8GTR0_RESERVED_31_24_MASK       (0xF8000000U)
34567 #define DDRPHY_DX8GTR0_RESERVED_31_24_SHIFT      (27U)
34568 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
34569  */
34570 #define DDRPHY_DX8GTR0_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_31_24_MASK)
34571 /*! @} */
34572 
34573 /*! @name DX8RSR0 - DATX8 n Rank Status Register 0 */
34574 /*! @{ */
34575 #define DDRPHY_DX8RSR0_QSGERR_MASK               (0xFFFFU)
34576 #define DDRPHY_DX8RSR0_QSGERR_SHIFT              (0U)
34577 /*! QSGERR - DQS Gate Training Error
34578  */
34579 #define DDRPHY_DX8RSR0_QSGERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR0_QSGERR_SHIFT)) & DDRPHY_DX8RSR0_QSGERR_MASK)
34580 #define DDRPHY_DX8RSR0_RESERVED_31_16_MASK       (0xFFFF0000U)
34581 #define DDRPHY_DX8RSR0_RESERVED_31_16_SHIFT      (16U)
34582 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
34583  */
34584 #define DDRPHY_DX8RSR0_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR0_RESERVED_31_16_MASK)
34585 /*! @} */
34586 
34587 /*! @name DX8RSR1 - DATX8 n Rank Status Register 1 */
34588 /*! @{ */
34589 #define DDRPHY_DX8RSR1_RDLVLERR_MASK             (0xFFFFU)
34590 #define DDRPHY_DX8RSR1_RDLVLERR_SHIFT            (0U)
34591 /*! RDLVLERR - Read Leveling Error
34592  */
34593 #define DDRPHY_DX8RSR1_RDLVLERR(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX8RSR1_RDLVLERR_MASK)
34594 #define DDRPHY_DX8RSR1_RESERVED_31_16_MASK       (0xFFFF0000U)
34595 #define DDRPHY_DX8RSR1_RESERVED_31_16_SHIFT      (16U)
34596 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
34597  */
34598 #define DDRPHY_DX8RSR1_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR1_RESERVED_31_16_MASK)
34599 /*! @} */
34600 
34601 /*! @name DX8RSR2 - DATX8 n Rank Status Register 2 */
34602 /*! @{ */
34603 #define DDRPHY_DX8RSR2_WLAWN_MASK                (0xFFFFU)
34604 #define DDRPHY_DX8RSR2_WLAWN_SHIFT               (0U)
34605 /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
34606  */
34607 #define DDRPHY_DX8RSR2_WLAWN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR2_WLAWN_SHIFT)) & DDRPHY_DX8RSR2_WLAWN_MASK)
34608 #define DDRPHY_DX8RSR2_RESERVED_31_16_MASK       (0xFFFF0000U)
34609 #define DDRPHY_DX8RSR2_RESERVED_31_16_SHIFT      (16U)
34610 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
34611  */
34612 #define DDRPHY_DX8RSR2_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR2_RESERVED_31_16_MASK)
34613 /*! @} */
34614 
34615 /*! @name DX8RSR3 - DATX8 n Rank Status Register 3 */
34616 /*! @{ */
34617 #define DDRPHY_DX8RSR3_WLAERR_MASK               (0xFFFFU)
34618 #define DDRPHY_DX8RSR3_WLAERR_SHIFT              (0U)
34619 /*! WLAERR - Write Leveling Adjustment Error
34620  */
34621 #define DDRPHY_DX8RSR3_WLAERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR3_WLAERR_SHIFT)) & DDRPHY_DX8RSR3_WLAERR_MASK)
34622 #define DDRPHY_DX8RSR3_RESERVED_31_16_MASK       (0xFFFF0000U)
34623 #define DDRPHY_DX8RSR3_RESERVED_31_16_SHIFT      (16U)
34624 /*! RESERVED_31_16 - Reserved. Return zeroes on reads.
34625  */
34626 #define DDRPHY_DX8RSR3_RESERVED_31_16(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR3_RESERVED_31_16_MASK)
34627 /*! @} */
34628 
34629 /*! @name DX8GSR0 - DATX8 n General Status Register 0 */
34630 /*! @{ */
34631 #define DDRPHY_DX8GSR0_WDQCAL_MASK               (0x1U)
34632 #define DDRPHY_DX8GSR0_WDQCAL_SHIFT              (0U)
34633 /*! WDQCAL - Write DQ Calibration
34634  */
34635 #define DDRPHY_DX8GSR0_WDQCAL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WDQCAL_SHIFT)) & DDRPHY_DX8GSR0_WDQCAL_MASK)
34636 #define DDRPHY_DX8GSR0_RDQSCAL_MASK              (0x2U)
34637 #define DDRPHY_DX8GSR0_RDQSCAL_SHIFT             (1U)
34638 /*! RDQSCAL - Read DQS Calibration
34639  */
34640 #define DDRPHY_DX8GSR0_RDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX8GSR0_RDQSCAL_MASK)
34641 #define DDRPHY_DX8GSR0_RDQSNCAL_MASK             (0x4U)
34642 #define DDRPHY_DX8GSR0_RDQSNCAL_SHIFT            (2U)
34643 /*! RDQSNCAL - Read DQS# Calibration
34644  */
34645 #define DDRPHY_DX8GSR0_RDQSNCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX8GSR0_RDQSNCAL_MASK)
34646 #define DDRPHY_DX8GSR0_GDQSCAL_MASK              (0x8U)
34647 #define DDRPHY_DX8GSR0_GDQSCAL_SHIFT             (3U)
34648 /*! GDQSCAL - Read DQS gating Calibration
34649  */
34650 #define DDRPHY_DX8GSR0_GDQSCAL(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX8GSR0_GDQSCAL_MASK)
34651 #define DDRPHY_DX8GSR0_WLCAL_MASK                (0x10U)
34652 #define DDRPHY_DX8GSR0_WLCAL_SHIFT               (4U)
34653 /*! WLCAL - Write Leveling Calibration
34654  */
34655 #define DDRPHY_DX8GSR0_WLCAL(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLCAL_SHIFT)) & DDRPHY_DX8GSR0_WLCAL_MASK)
34656 #define DDRPHY_DX8GSR0_WLDONE_MASK               (0x20U)
34657 #define DDRPHY_DX8GSR0_WLDONE_SHIFT              (5U)
34658 /*! WLDONE - Write Leveling Done
34659  */
34660 #define DDRPHY_DX8GSR0_WLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLDONE_SHIFT)) & DDRPHY_DX8GSR0_WLDONE_MASK)
34661 #define DDRPHY_DX8GSR0_WLERR_MASK                (0x40U)
34662 #define DDRPHY_DX8GSR0_WLERR_SHIFT               (6U)
34663 /*! WLERR - Write Leveling Error
34664  */
34665 #define DDRPHY_DX8GSR0_WLERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLERR_SHIFT)) & DDRPHY_DX8GSR0_WLERR_MASK)
34666 #define DDRPHY_DX8GSR0_WLPRD_MASK                (0xFF80U)
34667 #define DDRPHY_DX8GSR0_WLPRD_SHIFT               (7U)
34668 /*! WLPRD - Write Leveling Period
34669  */
34670 #define DDRPHY_DX8GSR0_WLPRD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLPRD_SHIFT)) & DDRPHY_DX8GSR0_WLPRD_MASK)
34671 #define DDRPHY_DX8GSR0_DPLOCK_MASK               (0x10000U)
34672 #define DDRPHY_DX8GSR0_DPLOCK_SHIFT              (16U)
34673 /*! DPLOCK - DATX8 PLL Lock
34674  */
34675 #define DDRPHY_DX8GSR0_DPLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_DPLOCK_SHIFT)) & DDRPHY_DX8GSR0_DPLOCK_MASK)
34676 #define DDRPHY_DX8GSR0_GDQSPRD_MASK              (0x3FE0000U)
34677 #define DDRPHY_DX8GSR0_GDQSPRD_SHIFT             (17U)
34678 /*! GDQSPRD - Read DQS gating Period
34679  */
34680 #define DDRPHY_DX8GSR0_GDQSPRD(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX8GSR0_GDQSPRD_MASK)
34681 #define DDRPHY_DX8GSR0_RESERVED_29_26_MASK       (0x3C000000U)
34682 #define DDRPHY_DX8GSR0_RESERVED_29_26_SHIFT      (26U)
34683 /*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
34684  */
34685 #define DDRPHY_DX8GSR0_RESERVED_29_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX8GSR0_RESERVED_29_26_MASK)
34686 #define DDRPHY_DX8GSR0_WLDQ_MASK                 (0x40000000U)
34687 #define DDRPHY_DX8GSR0_WLDQ_SHIFT                (30U)
34688 /*! WLDQ - Write Leveling DQ Status
34689  */
34690 #define DDRPHY_DX8GSR0_WLDQ(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLDQ_SHIFT)) & DDRPHY_DX8GSR0_WLDQ_MASK)
34691 #define DDRPHY_DX8GSR0_RESERVED_31_MASK          (0x80000000U)
34692 #define DDRPHY_DX8GSR0_RESERVED_31_SHIFT         (31U)
34693 /*! RESERVED_31 - Reserved. Returns zeroes on reads.
34694  */
34695 #define DDRPHY_DX8GSR0_RESERVED_31(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX8GSR0_RESERVED_31_MASK)
34696 /*! @} */
34697 
34698 /*! @name DX8GSR1 - DATX8 n General Status Register 1 */
34699 /*! @{ */
34700 #define DDRPHY_DX8GSR1_DLTDONE_MASK              (0x1U)
34701 #define DDRPHY_DX8GSR1_DLTDONE_SHIFT             (0U)
34702 /*! DLTDONE - Delay Line Test Done
34703  */
34704 #define DDRPHY_DX8GSR1_DLTDONE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR1_DLTDONE_SHIFT)) & DDRPHY_DX8GSR1_DLTDONE_MASK)
34705 #define DDRPHY_DX8GSR1_DLTCODE_MASK              (0x1FFFFFEU)
34706 #define DDRPHY_DX8GSR1_DLTCODE_SHIFT             (1U)
34707 /*! DLTCODE - Delay Line Test Code
34708  */
34709 #define DDRPHY_DX8GSR1_DLTCODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR1_DLTCODE_SHIFT)) & DDRPHY_DX8GSR1_DLTCODE_MASK)
34710 #define DDRPHY_DX8GSR1_RESERVED_31_25_MASK       (0xFE000000U)
34711 #define DDRPHY_DX8GSR1_RESERVED_31_25_SHIFT      (25U)
34712 /*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
34713  */
34714 #define DDRPHY_DX8GSR1_RESERVED_31_25(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8GSR1_RESERVED_31_25_MASK)
34715 /*! @} */
34716 
34717 /*! @name DX8GSR2 - DATX8 n General Status Register 2 */
34718 /*! @{ */
34719 #define DDRPHY_DX8GSR2_RDERR_MASK                (0x1U)
34720 #define DDRPHY_DX8GSR2_RDERR_SHIFT               (0U)
34721 /*! RDERR - Read Bit Deskew Error
34722  */
34723 #define DDRPHY_DX8GSR2_RDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_RDERR_SHIFT)) & DDRPHY_DX8GSR2_RDERR_MASK)
34724 #define DDRPHY_DX8GSR2_RDWN_MASK                 (0x2U)
34725 #define DDRPHY_DX8GSR2_RDWN_SHIFT                (1U)
34726 /*! RDWN - Read Bit Deskew Warning
34727  */
34728 #define DDRPHY_DX8GSR2_RDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_RDWN_SHIFT)) & DDRPHY_DX8GSR2_RDWN_MASK)
34729 #define DDRPHY_DX8GSR2_WDERR_MASK                (0x4U)
34730 #define DDRPHY_DX8GSR2_WDERR_SHIFT               (2U)
34731 /*! WDERR - Write Bit Deskew Error
34732  */
34733 #define DDRPHY_DX8GSR2_WDERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WDERR_SHIFT)) & DDRPHY_DX8GSR2_WDERR_MASK)
34734 #define DDRPHY_DX8GSR2_WDWN_MASK                 (0x8U)
34735 #define DDRPHY_DX8GSR2_WDWN_SHIFT                (3U)
34736 /*! WDWN - Write Bit Deskew Warning
34737  */
34738 #define DDRPHY_DX8GSR2_WDWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WDWN_SHIFT)) & DDRPHY_DX8GSR2_WDWN_MASK)
34739 #define DDRPHY_DX8GSR2_REERR_MASK                (0x10U)
34740 #define DDRPHY_DX8GSR2_REERR_SHIFT               (4U)
34741 /*! REERR - Read Eye Centering Error
34742  */
34743 #define DDRPHY_DX8GSR2_REERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_REERR_SHIFT)) & DDRPHY_DX8GSR2_REERR_MASK)
34744 #define DDRPHY_DX8GSR2_REWN_MASK                 (0x20U)
34745 #define DDRPHY_DX8GSR2_REWN_SHIFT                (5U)
34746 /*! REWN - Read Eye Centering Warning
34747  */
34748 #define DDRPHY_DX8GSR2_REWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_REWN_SHIFT)) & DDRPHY_DX8GSR2_REWN_MASK)
34749 #define DDRPHY_DX8GSR2_WEERR_MASK                (0x40U)
34750 #define DDRPHY_DX8GSR2_WEERR_SHIFT               (6U)
34751 /*! WEERR - Write Eye Centering Error
34752  */
34753 #define DDRPHY_DX8GSR2_WEERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WEERR_SHIFT)) & DDRPHY_DX8GSR2_WEERR_MASK)
34754 #define DDRPHY_DX8GSR2_WEWN_MASK                 (0x80U)
34755 #define DDRPHY_DX8GSR2_WEWN_SHIFT                (7U)
34756 /*! WEWN - Write Eye Centering Warning
34757  */
34758 #define DDRPHY_DX8GSR2_WEWN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WEWN_SHIFT)) & DDRPHY_DX8GSR2_WEWN_MASK)
34759 #define DDRPHY_DX8GSR2_ESTAT_MASK                (0xF00U)
34760 #define DDRPHY_DX8GSR2_ESTAT_SHIFT               (8U)
34761 /*! ESTAT - Error Status
34762  */
34763 #define DDRPHY_DX8GSR2_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_ESTAT_SHIFT)) & DDRPHY_DX8GSR2_ESTAT_MASK)
34764 #define DDRPHY_DX8GSR2_DQS2DQERR_MASK            (0xFF000U)
34765 #define DDRPHY_DX8GSR2_DQS2DQERR_SHIFT           (12U)
34766 /*! DQS2DQERR - Write DQS2DQ Training Error
34767  */
34768 #define DDRPHY_DX8GSR2_DQS2DQERR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX8GSR2_DQS2DQERR_MASK)
34769 #define DDRPHY_DX8GSR2_SRDERR_MASK               (0x100000U)
34770 #define DDRPHY_DX8GSR2_SRDERR_SHIFT              (20U)
34771 /*! SRDERR - Static Read Error
34772  */
34773 #define DDRPHY_DX8GSR2_SRDERR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_SRDERR_SHIFT)) & DDRPHY_DX8GSR2_SRDERR_MASK)
34774 #define DDRPHY_DX8GSR2_RESERVED_21_MASK          (0x200000U)
34775 #define DDRPHY_DX8GSR2_RESERVED_21_SHIFT         (21U)
34776 /*! RESERVED_21 - Reserved. Return zeroes on reads.
34777  */
34778 #define DDRPHY_DX8GSR2_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX8GSR2_RESERVED_21_MASK)
34779 #define DDRPHY_DX8GSR2_GSDQSCAL_MASK             (0x400000U)
34780 #define DDRPHY_DX8GSR2_GSDQSCAL_SHIFT            (22U)
34781 /*! GSDQSCAL - Read DQS Gating Status Calibration
34782  */
34783 #define DDRPHY_DX8GSR2_GSDQSCAL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX8GSR2_GSDQSCAL_MASK)
34784 #define DDRPHY_DX8GSR2_GSDQSPRD_MASK             (0xFF800000U)
34785 #define DDRPHY_DX8GSR2_GSDQSPRD_SHIFT            (23U)
34786 /*! GSDQSPRD - Read DQS gating Status Period
34787  */
34788 #define DDRPHY_DX8GSR2_GSDQSPRD(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX8GSR2_GSDQSPRD_MASK)
34789 /*! @} */
34790 
34791 /*! @name DX8GSR3 - DATX8 n General Status Register 3 */
34792 /*! @{ */
34793 #define DDRPHY_DX8GSR3_SRDPC_MASK                (0x3U)
34794 #define DDRPHY_DX8GSR3_SRDPC_SHIFT               (0U)
34795 /*! SRDPC - Static Read Delay Pass Count
34796  */
34797 #define DDRPHY_DX8GSR3_SRDPC(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_SRDPC_SHIFT)) & DDRPHY_DX8GSR3_SRDPC_MASK)
34798 #define DDRPHY_DX8GSR3_RESERVED_7_2_MASK         (0xFCU)
34799 #define DDRPHY_DX8GSR3_RESERVED_7_2_SHIFT        (2U)
34800 /*! RESERVED_7_2 - Reserved. Return zeroes on reads.
34801  */
34802 #define DDRPHY_DX8GSR3_RESERVED_7_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX8GSR3_RESERVED_7_2_MASK)
34803 #define DDRPHY_DX8GSR3_HVERR_MASK                (0xF00U)
34804 #define DDRPHY_DX8GSR3_HVERR_SHIFT               (8U)
34805 /*! HVERR - Host VREF Training Error
34806  */
34807 #define DDRPHY_DX8GSR3_HVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_HVERR_SHIFT)) & DDRPHY_DX8GSR3_HVERR_MASK)
34808 #define DDRPHY_DX8GSR3_HVWRN_MASK                (0xF000U)
34809 #define DDRPHY_DX8GSR3_HVWRN_SHIFT               (12U)
34810 /*! HVWRN - Host VREF Training Warning
34811  */
34812 #define DDRPHY_DX8GSR3_HVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_HVWRN_SHIFT)) & DDRPHY_DX8GSR3_HVWRN_MASK)
34813 #define DDRPHY_DX8GSR3_DVERR_MASK                (0xF0000U)
34814 #define DDRPHY_DX8GSR3_DVERR_SHIFT               (16U)
34815 /*! DVERR - DRAM VREF Training Error
34816  */
34817 #define DDRPHY_DX8GSR3_DVERR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_DVERR_SHIFT)) & DDRPHY_DX8GSR3_DVERR_MASK)
34818 #define DDRPHY_DX8GSR3_DVWRN_MASK                (0xF00000U)
34819 #define DDRPHY_DX8GSR3_DVWRN_SHIFT               (20U)
34820 /*! DVWRN - DRAM VREF Training Warning
34821  */
34822 #define DDRPHY_DX8GSR3_DVWRN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_DVWRN_SHIFT)) & DDRPHY_DX8GSR3_DVWRN_MASK)
34823 #define DDRPHY_DX8GSR3_ESTAT_MASK                (0x7000000U)
34824 #define DDRPHY_DX8GSR3_ESTAT_SHIFT               (24U)
34825 /*! ESTAT - VREF Training Error Status Code
34826  */
34827 #define DDRPHY_DX8GSR3_ESTAT(x)                  (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_ESTAT_SHIFT)) & DDRPHY_DX8GSR3_ESTAT_MASK)
34828 #define DDRPHY_DX8GSR3_RESERVED_31_27_MASK       (0xF8000000U)
34829 #define DDRPHY_DX8GSR3_RESERVED_31_27_SHIFT      (27U)
34830 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
34831  */
34832 #define DDRPHY_DX8GSR3_RESERVED_31_27(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX8GSR3_RESERVED_31_27_MASK)
34833 /*! @} */
34834 
34835 /*! @name DX8GSR4 - DATX8 n General Status Register 4 */
34836 /*! @{ */
34837 #define DDRPHY_DX8GSR4_RESERVED_0_MASK           (0x1U)
34838 #define DDRPHY_DX8GSR4_RESERVED_0_SHIFT          (0U)
34839 /*! RESERVED_0 - Reserved. Return zeroes on reads.
34840  */
34841 #define DDRPHY_DX8GSR4_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_0_MASK)
34842 #define DDRPHY_DX8GSR4_RESERVED_1_MASK           (0x2U)
34843 #define DDRPHY_DX8GSR4_RESERVED_1_SHIFT          (1U)
34844 /*! RESERVED_1 - Reserved. Return zeroes on reads.
34845  */
34846 #define DDRPHY_DX8GSR4_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_1_MASK)
34847 #define DDRPHY_DX8GSR4_RESERVED_2_MASK           (0x4U)
34848 #define DDRPHY_DX8GSR4_RESERVED_2_SHIFT          (2U)
34849 /*! RESERVED_2 - Reserved. Return zeroes on reads.
34850  */
34851 #define DDRPHY_DX8GSR4_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_2_MASK)
34852 #define DDRPHY_DX8GSR4_RESERVED_3_MASK           (0x8U)
34853 #define DDRPHY_DX8GSR4_RESERVED_3_SHIFT          (3U)
34854 /*! RESERVED_3 - Reserved. Return zeroes on reads.
34855  */
34856 #define DDRPHY_DX8GSR4_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_3_MASK)
34857 #define DDRPHY_DX8GSR4_RESERVED_4_MASK           (0x10U)
34858 #define DDRPHY_DX8GSR4_RESERVED_4_SHIFT          (4U)
34859 /*! RESERVED_4 - Reserved. Return zeroes on reads.
34860  */
34861 #define DDRPHY_DX8GSR4_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_4_MASK)
34862 #define DDRPHY_DX8GSR4_RESERVED_5_MASK           (0x20U)
34863 #define DDRPHY_DX8GSR4_RESERVED_5_SHIFT          (5U)
34864 /*! RESERVED_5 - Reserved. Return zeroes on reads.
34865  */
34866 #define DDRPHY_DX8GSR4_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_5_MASK)
34867 #define DDRPHY_DX8GSR4_RESERVED_6_MASK           (0x40U)
34868 #define DDRPHY_DX8GSR4_RESERVED_6_SHIFT          (6U)
34869 /*! RESERVED_6 - Reserved. Return zeroes on reads.
34870  */
34871 #define DDRPHY_DX8GSR4_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_6_MASK)
34872 #define DDRPHY_DX8GSR4_RESERVED_15_7_MASK        (0xFF80U)
34873 #define DDRPHY_DX8GSR4_RESERVED_15_7_SHIFT       (7U)
34874 /*! RESERVED_15_7 - Reserved. Return zeroes on reads.
34875  */
34876 #define DDRPHY_DX8GSR4_RESERVED_15_7(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_15_7_MASK)
34877 #define DDRPHY_DX8GSR4_RESERVED_16_MASK          (0x10000U)
34878 #define DDRPHY_DX8GSR4_RESERVED_16_SHIFT         (16U)
34879 /*! RESERVED_16 - Reserved. Return zeroes on reads.
34880  */
34881 #define DDRPHY_DX8GSR4_RESERVED_16(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_16_MASK)
34882 #define DDRPHY_DX8GSR4_RESERVED_25_17_MASK       (0x3FE0000U)
34883 #define DDRPHY_DX8GSR4_RESERVED_25_17_SHIFT      (17U)
34884 /*! RESERVED_25_17 - Reserved. Return zeroes on reads.
34885  */
34886 #define DDRPHY_DX8GSR4_RESERVED_25_17(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_25_17_MASK)
34887 #define DDRPHY_DX8GSR4_RESERVED_31_26_MASK       (0xFC000000U)
34888 #define DDRPHY_DX8GSR4_RESERVED_31_26_SHIFT      (26U)
34889 /*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
34890  */
34891 #define DDRPHY_DX8GSR4_RESERVED_31_26(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_31_26_MASK)
34892 /*! @} */
34893 
34894 /*! @name DX8GSR5 - DATX8 n General Status Register 5 */
34895 /*! @{ */
34896 #define DDRPHY_DX8GSR5_RESERVED_0_MASK           (0x1U)
34897 #define DDRPHY_DX8GSR5_RESERVED_0_SHIFT          (0U)
34898 /*! RESERVED_0 - Reserved. Return zeroes on reads.
34899  */
34900 #define DDRPHY_DX8GSR5_RESERVED_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_0_MASK)
34901 #define DDRPHY_DX8GSR5_RESERVED_1_MASK           (0x2U)
34902 #define DDRPHY_DX8GSR5_RESERVED_1_SHIFT          (1U)
34903 /*! RESERVED_1 - Reserved. Return zeroes on reads.
34904  */
34905 #define DDRPHY_DX8GSR5_RESERVED_1(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_1_MASK)
34906 #define DDRPHY_DX8GSR5_RESERVED_2_MASK           (0x4U)
34907 #define DDRPHY_DX8GSR5_RESERVED_2_SHIFT          (2U)
34908 /*! RESERVED_2 - Reserved. Return zeroes on reads.
34909  */
34910 #define DDRPHY_DX8GSR5_RESERVED_2(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_2_MASK)
34911 #define DDRPHY_DX8GSR5_RESERVED_3_MASK           (0x8U)
34912 #define DDRPHY_DX8GSR5_RESERVED_3_SHIFT          (3U)
34913 /*! RESERVED_3 - Reserved. Return zeroes on reads.
34914  */
34915 #define DDRPHY_DX8GSR5_RESERVED_3(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_3_MASK)
34916 #define DDRPHY_DX8GSR5_RESERVED_4_MASK           (0x10U)
34917 #define DDRPHY_DX8GSR5_RESERVED_4_SHIFT          (4U)
34918 /*! RESERVED_4 - Reserved. Return zeroes on reads.
34919  */
34920 #define DDRPHY_DX8GSR5_RESERVED_4(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_4_MASK)
34921 #define DDRPHY_DX8GSR5_RESERVED_5_MASK           (0x20U)
34922 #define DDRPHY_DX8GSR5_RESERVED_5_SHIFT          (5U)
34923 /*! RESERVED_5 - Reserved. Return zeroes on reads.
34924  */
34925 #define DDRPHY_DX8GSR5_RESERVED_5(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_5_MASK)
34926 #define DDRPHY_DX8GSR5_RESERVED_6_MASK           (0x40U)
34927 #define DDRPHY_DX8GSR5_RESERVED_6_SHIFT          (6U)
34928 /*! RESERVED_6 - Reserved. Return zeroes on reads.
34929  */
34930 #define DDRPHY_DX8GSR5_RESERVED_6(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_6_MASK)
34931 #define DDRPHY_DX8GSR5_RESERVED_7_MASK           (0x80U)
34932 #define DDRPHY_DX8GSR5_RESERVED_7_SHIFT          (7U)
34933 /*! RESERVED_7 - Reserved. Return zeroes on reads.
34934  */
34935 #define DDRPHY_DX8GSR5_RESERVED_7(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_7_MASK)
34936 #define DDRPHY_DX8GSR5_RESERVED_11_8_MASK        (0xF00U)
34937 #define DDRPHY_DX8GSR5_RESERVED_11_8_SHIFT       (8U)
34938 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
34939  */
34940 #define DDRPHY_DX8GSR5_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_11_8_MASK)
34941 #define DDRPHY_DX8GSR5_RESERVED_19_12_MASK       (0xFF000U)
34942 #define DDRPHY_DX8GSR5_RESERVED_19_12_SHIFT      (12U)
34943 /*! RESERVED_19_12 - Reserved. Return zeroes on reads.
34944  */
34945 #define DDRPHY_DX8GSR5_RESERVED_19_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_19_12_MASK)
34946 #define DDRPHY_DX8GSR5_RESERVED_20_MASK          (0x100000U)
34947 #define DDRPHY_DX8GSR5_RESERVED_20_SHIFT         (20U)
34948 /*! RESERVED_20 - Reserved. Return zeroes on reads.
34949  */
34950 #define DDRPHY_DX8GSR5_RESERVED_20(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_20_MASK)
34951 #define DDRPHY_DX8GSR5_RESERVED_21_MASK          (0x200000U)
34952 #define DDRPHY_DX8GSR5_RESERVED_21_SHIFT         (21U)
34953 /*! RESERVED_21 - Reserved. Return zeroes on reads.
34954  */
34955 #define DDRPHY_DX8GSR5_RESERVED_21(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_21_MASK)
34956 #define DDRPHY_DX8GSR5_RESERVED_22_MASK          (0x400000U)
34957 #define DDRPHY_DX8GSR5_RESERVED_22_SHIFT         (22U)
34958 /*! RESERVED_22 - Reserved. Return zeroes on reads.
34959  */
34960 #define DDRPHY_DX8GSR5_RESERVED_22(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_22_MASK)
34961 #define DDRPHY_DX8GSR5_RESERVED_31_23_MASK       (0xFF800000U)
34962 #define DDRPHY_DX8GSR5_RESERVED_31_23_SHIFT      (23U)
34963 /*! RESERVED_31_23 - Reserved. Return zeroes on reads.
34964  */
34965 #define DDRPHY_DX8GSR5_RESERVED_31_23(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_31_23_MASK)
34966 /*! @} */
34967 
34968 /*! @name DX8GSR6 - DATX8 n General Status Register 6 */
34969 /*! @{ */
34970 #define DDRPHY_DX8GSR6_RESERVED_1_0_MASK         (0x3U)
34971 #define DDRPHY_DX8GSR6_RESERVED_1_0_SHIFT        (0U)
34972 /*! RESERVED_1_0 - Reserved. Return zeroes on reads.
34973  */
34974 #define DDRPHY_DX8GSR6_RESERVED_1_0(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_1_0_MASK)
34975 #define DDRPHY_DX8GSR6_RESERVED_3_2_MASK         (0xCU)
34976 #define DDRPHY_DX8GSR6_RESERVED_3_2_SHIFT        (2U)
34977 /*! RESERVED_3_2 - Reserved. Return zeroes on reads.
34978  */
34979 #define DDRPHY_DX8GSR6_RESERVED_3_2(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_3_2_MASK)
34980 #define DDRPHY_DX8GSR6_RESERVED_7_4_MASK         (0xF0U)
34981 #define DDRPHY_DX8GSR6_RESERVED_7_4_SHIFT        (4U)
34982 /*! RESERVED_7_4 - Reserved. Return zeroes on reads.
34983  */
34984 #define DDRPHY_DX8GSR6_RESERVED_7_4(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_7_4_MASK)
34985 #define DDRPHY_DX8GSR6_RESERVED_11_8_MASK        (0xF00U)
34986 #define DDRPHY_DX8GSR6_RESERVED_11_8_SHIFT       (8U)
34987 /*! RESERVED_11_8 - Reserved. Return zeroes on reads.
34988  */
34989 #define DDRPHY_DX8GSR6_RESERVED_11_8(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_11_8_MASK)
34990 #define DDRPHY_DX8GSR6_RESERVED_15_12_MASK       (0xF000U)
34991 #define DDRPHY_DX8GSR6_RESERVED_15_12_SHIFT      (12U)
34992 /*! RESERVED_15_12 - Reserved. Return zeroes on reads.
34993  */
34994 #define DDRPHY_DX8GSR6_RESERVED_15_12(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_15_12_MASK)
34995 #define DDRPHY_DX8GSR6_RESERVED_19_15_MASK       (0xF0000U)
34996 #define DDRPHY_DX8GSR6_RESERVED_19_15_SHIFT      (16U)
34997 /*! RESERVED_19_15 - Reserved. Return zeroes on reads.
34998  */
34999 #define DDRPHY_DX8GSR6_RESERVED_19_15(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_19_15_MASK)
35000 #define DDRPHY_DX8GSR6_RESERVED_23_20_MASK       (0xF00000U)
35001 #define DDRPHY_DX8GSR6_RESERVED_23_20_SHIFT      (20U)
35002 /*! RESERVED_23_20 - Reserved. Return zeroes on reads.
35003  */
35004 #define DDRPHY_DX8GSR6_RESERVED_23_20(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_23_20_MASK)
35005 #define DDRPHY_DX8GSR6_RESERVED_31_24_MASK       (0xFF000000U)
35006 #define DDRPHY_DX8GSR6_RESERVED_31_24_SHIFT      (24U)
35007 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
35008  */
35009 #define DDRPHY_DX8GSR6_RESERVED_31_24(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_31_24_MASK)
35010 /*! @} */
35011 
35012 /*! @name DX8SL0OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
35013 /*! @{ */
35014 #define DDRPHY_DX8SL0OSC_OSCEN_MASK              (0x1U)
35015 #define DDRPHY_DX8SL0OSC_OSCEN_SHIFT             (0U)
35016 /*! OSCEN - Oscillator Enable
35017  */
35018 #define DDRPHY_DX8SL0OSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL0OSC_OSCEN_MASK)
35019 #define DDRPHY_DX8SL0OSC_OSCDIV_MASK             (0x1EU)
35020 #define DDRPHY_DX8SL0OSC_OSCDIV_SHIFT            (1U)
35021 /*! OSCDIV - Oscillator Mode Division
35022  */
35023 #define DDRPHY_DX8SL0OSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL0OSC_OSCDIV_MASK)
35024 #define DDRPHY_DX8SL0OSC_OSCWDL_MASK             (0x60U)
35025 #define DDRPHY_DX8SL0OSC_OSCWDL_SHIFT            (5U)
35026 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
35027  */
35028 #define DDRPHY_DX8SL0OSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL0OSC_OSCWDL_MASK)
35029 #define DDRPHY_DX8SL0OSC_RESERVED_8_7_MASK       (0x180U)
35030 #define DDRPHY_DX8SL0OSC_RESERVED_8_7_SHIFT      (7U)
35031 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
35032  */
35033 #define DDRPHY_DX8SL0OSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL0OSC_RESERVED_8_7_MASK)
35034 #define DDRPHY_DX8SL0OSC_OSCWDDL_MASK            (0x600U)
35035 #define DDRPHY_DX8SL0OSC_OSCWDDL_SHIFT           (9U)
35036 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
35037  */
35038 #define DDRPHY_DX8SL0OSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL0OSC_OSCWDDL_MASK)
35039 #define DDRPHY_DX8SL0OSC_RESERVED_12_11_MASK     (0x1800U)
35040 #define DDRPHY_DX8SL0OSC_RESERVED_12_11_SHIFT    (11U)
35041 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
35042  */
35043 #define DDRPHY_DX8SL0OSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL0OSC_RESERVED_12_11_MASK)
35044 #define DDRPHY_DX8SL0OSC_DLTMODE_MASK            (0x2000U)
35045 #define DDRPHY_DX8SL0OSC_DLTMODE_SHIFT           (13U)
35046 /*! DLTMODE - Delay Line Test Mode
35047  */
35048 #define DDRPHY_DX8SL0OSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL0OSC_DLTMODE_MASK)
35049 #define DDRPHY_DX8SL0OSC_DLTST_MASK              (0x4000U)
35050 #define DDRPHY_DX8SL0OSC_DLTST_SHIFT             (14U)
35051 /*! DLTST - Delay Line Test Start
35052  */
35053 #define DDRPHY_DX8SL0OSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_DLTST_SHIFT)) & DDRPHY_DX8SL0OSC_DLTST_MASK)
35054 #define DDRPHY_DX8SL0OSC_PHYFRST_MASK            (0x8000U)
35055 #define DDRPHY_DX8SL0OSC_PHYFRST_SHIFT           (15U)
35056 /*! PHYFRST - PHY FIFO Reset
35057  */
35058 #define DDRPHY_DX8SL0OSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL0OSC_PHYFRST_MASK)
35059 #define DDRPHY_DX8SL0OSC_PHYHRST_MASK            (0x10000U)
35060 #define DDRPHY_DX8SL0OSC_PHYHRST_SHIFT           (16U)
35061 /*! PHYHRST - PHY High-Speed Reset
35062  */
35063 #define DDRPHY_DX8SL0OSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL0OSC_PHYHRST_MASK)
35064 #define DDRPHY_DX8SL0OSC_LBDQSS_MASK             (0x20000U)
35065 #define DDRPHY_DX8SL0OSC_LBDQSS_SHIFT            (17U)
35066 /*! LBDQSS - Loopback DQS Shift
35067  */
35068 #define DDRPHY_DX8SL0OSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL0OSC_LBDQSS_MASK)
35069 #define DDRPHY_DX8SL0OSC_LBGDQS_MASK             (0xC0000U)
35070 #define DDRPHY_DX8SL0OSC_LBGDQS_SHIFT            (18U)
35071 /*! LBGDQS - Loopback DQS Gating
35072  */
35073 #define DDRPHY_DX8SL0OSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL0OSC_LBGDQS_MASK)
35074 #define DDRPHY_DX8SL0OSC_LBGSDQS_MASK            (0x100000U)
35075 #define DDRPHY_DX8SL0OSC_LBGSDQS_SHIFT           (20U)
35076 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
35077  */
35078 #define DDRPHY_DX8SL0OSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL0OSC_LBGSDQS_MASK)
35079 #define DDRPHY_DX8SL0OSC_LBMODE_MASK             (0x200000U)
35080 #define DDRPHY_DX8SL0OSC_LBMODE_SHIFT            (21U)
35081 /*! LBMODE - Loopback Mode
35082  */
35083 #define DDRPHY_DX8SL0OSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL0OSC_LBMODE_MASK)
35084 #define DDRPHY_DX8SL0OSC_CLKLEVEL_MASK           (0xC00000U)
35085 #define DDRPHY_DX8SL0OSC_CLKLEVEL_SHIFT          (22U)
35086 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
35087  */
35088 #define DDRPHY_DX8SL0OSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL0OSC_CLKLEVEL_MASK)
35089 #define DDRPHY_DX8SL0OSC_GATEDXCTLCLK_MASK       (0x3000000U)
35090 #define DDRPHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT      (24U)
35091 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
35092  */
35093 #define DDRPHY_DX8SL0OSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL0OSC_GATEDXCTLCLK_MASK)
35094 #define DDRPHY_DX8SL0OSC_GATEDXDDRCLK_MASK       (0xC000000U)
35095 #define DDRPHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT      (26U)
35096 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
35097  */
35098 #define DDRPHY_DX8SL0OSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL0OSC_GATEDXDDRCLK_MASK)
35099 #define DDRPHY_DX8SL0OSC_GATEDXRDCLK_MASK        (0x30000000U)
35100 #define DDRPHY_DX8SL0OSC_GATEDXRDCLK_SHIFT       (28U)
35101 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
35102  */
35103 #define DDRPHY_DX8SL0OSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL0OSC_GATEDXRDCLK_MASK)
35104 #define DDRPHY_DX8SL0OSC_RESERVED_31_30_MASK     (0xC0000000U)
35105 #define DDRPHY_DX8SL0OSC_RESERVED_31_30_SHIFT    (30U)
35106 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
35107  */
35108 #define DDRPHY_DX8SL0OSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL0OSC_RESERVED_31_30_MASK)
35109 /*! @} */
35110 
35111 /*! @name DX8SL0PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
35112 /*! @{ */
35113 #define DDRPHY_DX8SL0PLLCR0_DTC_MASK             (0xFU)
35114 #define DDRPHY_DX8SL0PLLCR0_DTC_SHIFT            (0U)
35115 /*! DTC - Digital Test Control
35116  */
35117 #define DDRPHY_DX8SL0PLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_DTC_MASK)
35118 #define DDRPHY_DX8SL0PLLCR0_ATC_MASK             (0xF0U)
35119 #define DDRPHY_DX8SL0PLLCR0_ATC_SHIFT            (4U)
35120 /*! ATC - Analog Test Control
35121  */
35122 #define DDRPHY_DX8SL0PLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_ATC_MASK)
35123 #define DDRPHY_DX8SL0PLLCR0_ATOEN_MASK           (0x100U)
35124 #define DDRPHY_DX8SL0PLLCR0_ATOEN_SHIFT          (8U)
35125 /*! ATOEN - Analog Test Enable (ATOEN)
35126  */
35127 #define DDRPHY_DX8SL0PLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL0PLLCR0_ATOEN_MASK)
35128 #define DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_MASK   (0xE00U)
35129 #define DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT  (9U)
35130 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
35131  */
35132 #define DDRPHY_DX8SL0PLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_MASK)
35133 #define DDRPHY_DX8SL0PLLCR0_GSHIFT_MASK          (0x1000U)
35134 #define DDRPHY_DX8SL0PLLCR0_GSHIFT_SHIFT         (12U)
35135 /*! GSHIFT - Gear Shift
35136  */
35137 #define DDRPHY_DX8SL0PLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL0PLLCR0_GSHIFT_MASK)
35138 #define DDRPHY_DX8SL0PLLCR0_CPIC_MASK            (0x1E000U)
35139 #define DDRPHY_DX8SL0PLLCR0_CPIC_SHIFT           (13U)
35140 /*! CPIC - Charge Pump Integrating Current Control
35141  */
35142 #define DDRPHY_DX8SL0PLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_CPIC_MASK)
35143 #define DDRPHY_DX8SL0PLLCR0_CPPC_MASK            (0x7E0000U)
35144 #define DDRPHY_DX8SL0PLLCR0_CPPC_SHIFT           (17U)
35145 /*! CPPC - Charge Pump Proportional Current Control
35146  */
35147 #define DDRPHY_DX8SL0PLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_CPPC_MASK)
35148 #define DDRPHY_DX8SL0PLLCR0_RLOCKM_MASK          (0x800000U)
35149 #define DDRPHY_DX8SL0PLLCR0_RLOCKM_SHIFT         (23U)
35150 /*! RLOCKM - Relock Mode
35151  */
35152 #define DDRPHY_DX8SL0PLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL0PLLCR0_RLOCKM_MASK)
35153 #define DDRPHY_DX8SL0PLLCR0_FRQSEL_MASK          (0xF000000U)
35154 #define DDRPHY_DX8SL0PLLCR0_FRQSEL_SHIFT         (24U)
35155 /*! FRQSEL - PLL Frequency Select
35156  */
35157 #define DDRPHY_DX8SL0PLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL0PLLCR0_FRQSEL_MASK)
35158 #define DDRPHY_DX8SL0PLLCR0_RSTOPM_MASK          (0x10000000U)
35159 #define DDRPHY_DX8SL0PLLCR0_RSTOPM_SHIFT         (28U)
35160 /*! RSTOPM - Reference Stop Mode
35161  */
35162 #define DDRPHY_DX8SL0PLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL0PLLCR0_RSTOPM_MASK)
35163 #define DDRPHY_DX8SL0PLLCR0_PLLPD_MASK           (0x20000000U)
35164 #define DDRPHY_DX8SL0PLLCR0_PLLPD_SHIFT          (29U)
35165 /*! PLLPD - PLL Power Down
35166  */
35167 #define DDRPHY_DX8SL0PLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL0PLLCR0_PLLPD_MASK)
35168 #define DDRPHY_DX8SL0PLLCR0_PLLRST_MASK          (0x40000000U)
35169 #define DDRPHY_DX8SL0PLLCR0_PLLRST_SHIFT         (30U)
35170 /*! PLLRST - PLL Reset
35171  */
35172 #define DDRPHY_DX8SL0PLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL0PLLCR0_PLLRST_MASK)
35173 #define DDRPHY_DX8SL0PLLCR0_PLLBYP_MASK          (0x80000000U)
35174 #define DDRPHY_DX8SL0PLLCR0_PLLBYP_SHIFT         (31U)
35175 /*! PLLBYP - PLL Bypass
35176  */
35177 #define DDRPHY_DX8SL0PLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL0PLLCR0_PLLBYP_MASK)
35178 /*! @} */
35179 
35180 /*! @name DX8SL0PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
35181 /*! @{ */
35182 #define DDRPHY_DX8SL0PLLCR1_LOCKDS_MASK          (0x1U)
35183 #define DDRPHY_DX8SL0PLLCR1_LOCKDS_SHIFT         (0U)
35184 /*! LOCKDS - Lock Detector Select
35185  */
35186 #define DDRPHY_DX8SL0PLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL0PLLCR1_LOCKDS_MASK)
35187 #define DDRPHY_DX8SL0PLLCR1_LOCKCS_MASK          (0x2U)
35188 #define DDRPHY_DX8SL0PLLCR1_LOCKCS_SHIFT         (1U)
35189 /*! LOCKCS - Lock Detector Counter Select
35190  */
35191 #define DDRPHY_DX8SL0PLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL0PLLCR1_LOCKCS_MASK)
35192 #define DDRPHY_DX8SL0PLLCR1_LOCKPS_MASK          (0x4U)
35193 #define DDRPHY_DX8SL0PLLCR1_LOCKPS_SHIFT         (2U)
35194 /*! LOCKPS - Lock Detector Phase Select
35195  */
35196 #define DDRPHY_DX8SL0PLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL0PLLCR1_LOCKPS_MASK)
35197 #define DDRPHY_DX8SL0PLLCR1_BYPVDD_MASK          (0x8U)
35198 #define DDRPHY_DX8SL0PLLCR1_BYPVDD_SHIFT         (3U)
35199 /*! BYPVDD - PLL VDD voltage level control
35200  */
35201 #define DDRPHY_DX8SL0PLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL0PLLCR1_BYPVDD_MASK)
35202 #define DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_MASK      (0x10U)
35203 #define DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_SHIFT     (4U)
35204 /*! BYPVREGDIG - Bypass PLL vreg_dig
35205  */
35206 #define DDRPHY_DX8SL0PLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_MASK)
35207 #define DDRPHY_DX8SL0PLLCR1_BYPVREGCP_MASK       (0x20U)
35208 #define DDRPHY_DX8SL0PLLCR1_BYPVREGCP_SHIFT      (5U)
35209 /*! BYPVREGCP - Bypass PLL vreg_cp
35210  */
35211 #define DDRPHY_DX8SL0PLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL0PLLCR1_BYPVREGCP_MASK)
35212 #define DDRPHY_DX8SL0PLLCR1_PLLPROG_MASK         (0x3FFFC0U)
35213 #define DDRPHY_DX8SL0PLLCR1_PLLPROG_SHIFT        (6U)
35214 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
35215  */
35216 #define DDRPHY_DX8SL0PLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL0PLLCR1_PLLPROG_MASK)
35217 #define DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
35218 #define DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_SHIFT (22U)
35219 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
35220  */
35221 #define DDRPHY_DX8SL0PLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_MASK)
35222 /*! @} */
35223 
35224 /*! @name DX8SL0PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
35225 /*! @{ */
35226 #define DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
35227 #define DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_SHIFT   (0U)
35228 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
35229  */
35230 #define DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_MASK)
35231 /*! @} */
35232 
35233 /*! @name DX8SL0PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
35234 /*! @{ */
35235 #define DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
35236 #define DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_SHIFT  (0U)
35237 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
35238  */
35239 #define DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_MASK)
35240 /*! @} */
35241 
35242 /*! @name DX8SL0PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
35243 /*! @{ */
35244 #define DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
35245 #define DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_SHIFT  (0U)
35246 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
35247  */
35248 #define DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_MASK)
35249 /*! @} */
35250 
35251 /*! @name DX8SL0PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
35252 /*! @{ */
35253 #define DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
35254 #define DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_SHIFT (0U)
35255 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
35256  */
35257 #define DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_MASK)
35258 #define DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
35259 #define DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_SHIFT  (8U)
35260 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
35261  */
35262 #define DDRPHY_DX8SL0PLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_MASK)
35263 /*! @} */
35264 
35265 /*! @name DX8SL0DQSCTL - DATX8 0-1 DQS Control Register */
35266 /*! @{ */
35267 #define DDRPHY_DX8SL0DQSCTL_DQSRES_MASK          (0xFU)
35268 #define DDRPHY_DX8SL0DQSCTL_DQSRES_SHIFT         (0U)
35269 /*! DQSRES - DQS Resistor
35270  */
35271 #define DDRPHY_DX8SL0DQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DQSRES_MASK)
35272 #define DDRPHY_DX8SL0DQSCTL_DQSNRES_MASK         (0xF0U)
35273 #define DDRPHY_DX8SL0DQSCTL_DQSNRES_SHIFT        (4U)
35274 /*! DQSNRES - DQS_N Resistor
35275  */
35276 #define DDRPHY_DX8SL0DQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DQSNRES_MASK)
35277 #define DDRPHY_DX8SL0DQSCTL_DXSR_MASK            (0x300U)
35278 #define DDRPHY_DX8SL0DQSCTL_DXSR_SHIFT           (8U)
35279 /*! DXSR - Data Slew Rate
35280  */
35281 #define DDRPHY_DX8SL0DQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DXSR_MASK)
35282 #define DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_MASK  (0x1C00U)
35283 #define DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT (10U)
35284 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
35285  */
35286 #define DDRPHY_DX8SL0DQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_MASK)
35287 #define DDRPHY_DX8SL0DQSCTL_UDQIOM_MASK          (0x2000U)
35288 #define DDRPHY_DX8SL0DQSCTL_UDQIOM_SHIFT         (13U)
35289 /*! UDQIOM - Unused DQ I/O Mode
35290  */
35291 #define DDRPHY_DX8SL0DQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL0DQSCTL_UDQIOM_MASK)
35292 #define DDRPHY_DX8SL0DQSCTL_QSCNTEN_MASK         (0x4000U)
35293 #define DDRPHY_DX8SL0DQSCTL_QSCNTEN_SHIFT        (14U)
35294 /*! QSCNTEN - QS Counter Enable
35295  */
35296 #define DDRPHY_DX8SL0DQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL0DQSCTL_QSCNTEN_MASK)
35297 #define DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_MASK  (0x18000U)
35298 #define DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT (15U)
35299 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
35300  */
35301 #define DDRPHY_DX8SL0DQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_MASK)
35302 #define DDRPHY_DX8SL0DQSCTL_LPIOPD_MASK          (0x20000U)
35303 #define DDRPHY_DX8SL0DQSCTL_LPIOPD_SHIFT         (17U)
35304 /*! LPIOPD - Low Power I/O Power Down
35305  */
35306 #define DDRPHY_DX8SL0DQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL0DQSCTL_LPIOPD_MASK)
35307 #define DDRPHY_DX8SL0DQSCTL_LPPLLPD_MASK         (0x40000U)
35308 #define DDRPHY_DX8SL0DQSCTL_LPPLLPD_SHIFT        (18U)
35309 /*! LPPLLPD - Low Power PLL Power Down
35310  */
35311 #define DDRPHY_DX8SL0DQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL0DQSCTL_LPPLLPD_MASK)
35312 #define DDRPHY_DX8SL0DQSCTL_DQSGX_MASK           (0x180000U)
35313 #define DDRPHY_DX8SL0DQSCTL_DQSGX_SHIFT          (19U)
35314 /*! DQSGX - DQS Gate Extension
35315  */
35316 #define DDRPHY_DX8SL0DQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DQSGX_MASK)
35317 #define DDRPHY_DX8SL0DQSCTL_WRRMODE_MASK         (0x200000U)
35318 #define DDRPHY_DX8SL0DQSCTL_WRRMODE_SHIFT        (21U)
35319 /*! WRRMODE - Write Path Rise-to-Rise Mode
35320  */
35321 #define DDRPHY_DX8SL0DQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL0DQSCTL_WRRMODE_MASK)
35322 #define DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_MASK  (0xC00000U)
35323 #define DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT (22U)
35324 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
35325  */
35326 #define DDRPHY_DX8SL0DQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_MASK)
35327 #define DDRPHY_DX8SL0DQSCTL_RRRMODE_MASK         (0x1000000U)
35328 #define DDRPHY_DX8SL0DQSCTL_RRRMODE_SHIFT        (24U)
35329 /*! RRRMODE - Read Path Rise-to-Rise Mode
35330  */
35331 #define DDRPHY_DX8SL0DQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RRRMODE_MASK)
35332 #define DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
35333 #define DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT (25U)
35334 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
35335  */
35336 #define DDRPHY_DX8SL0DQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_MASK)
35337 /*! @} */
35338 
35339 /*! @name DX8SL0TRNCTL - DATX8 0-1 Training Control Register */
35340 /*! @{ */
35341 #define DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
35342 #define DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_SHIFT  (0U)
35343 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
35344  */
35345 #define DDRPHY_DX8SL0TRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_MASK)
35346 /*! @} */
35347 
35348 /*! @name DX8SL0DDLCTL - DATX8 0-1 DDL Control Register */
35349 /*! @{ */
35350 #define DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_MASK      (0x3U)
35351 #define DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_SHIFT     (0U)
35352 /*! DDLBYPMODE - Controls DDL Bypass Mode
35353  */
35354 #define DDRPHY_DX8SL0DDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_MASK)
35355 #define DDRPHY_DX8SL0DDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
35356 #define DDRPHY_DX8SL0DDLCTL_DXDDLBYP_SHIFT       (2U)
35357 /*! DXDDLBYP - DATX8 DDL Bypass
35358  */
35359 #define DDRPHY_DX8SL0DDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DXDDLBYP_MASK)
35360 #define DDRPHY_DX8SL0DDLCTL_DXDDLLD_MASK         (0x7C0000U)
35361 #define DDRPHY_DX8SL0DDLCTL_DXDDLLD_SHIFT        (18U)
35362 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
35363  */
35364 #define DDRPHY_DX8SL0DDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DXDDLLD_MASK)
35365 #define DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_MASK  (0x1800000U)
35366 #define DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_SHIFT (23U)
35367 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
35368  */
35369 #define DDRPHY_DX8SL0DDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_MASK)
35370 #define DDRPHY_DX8SL0DDLCTL_DXDDLLDT_MASK        (0x2000000U)
35371 #define DDRPHY_DX8SL0DDLCTL_DXDDLLDT_SHIFT       (25U)
35372 /*! DXDDLLDT - DX DDL Load Type
35373  */
35374 #define DDRPHY_DX8SL0DDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DXDDLLDT_MASK)
35375 #define DDRPHY_DX8SL0DDLCTL_DLYLDTM_MASK         (0x4000000U)
35376 #define DDRPHY_DX8SL0DDLCTL_DLYLDTM_SHIFT        (26U)
35377 /*! DLYLDTM - Delay Load Timing
35378  */
35379 #define DDRPHY_DX8SL0DDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DLYLDTM_MASK)
35380 #define DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
35381 #define DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_SHIFT (27U)
35382 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
35383  */
35384 #define DDRPHY_DX8SL0DDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_MASK)
35385 /*! @} */
35386 
35387 /*! @name DX8SL0DXCTL1 - DATX8 0-1 DX Control Register 1 */
35388 /*! @{ */
35389 #define DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
35390 #define DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_SHIFT  (0U)
35391 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
35392  */
35393 #define DDRPHY_DX8SL0DXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_MASK)
35394 #define DDRPHY_DX8SL0DXCTL1_DXTMODE_MASK         (0x10000U)
35395 #define DDRPHY_DX8SL0DXCTL1_DXTMODE_SHIFT        (16U)
35396 /*! DXTMODE - DATX8 Test Mode
35397  */
35398 #define DDRPHY_DX8SL0DXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXTMODE_MASK)
35399 #define DDRPHY_DX8SL0DXCTL1_DXGDBYP_MASK         (0x20000U)
35400 #define DDRPHY_DX8SL0DXCTL1_DXGDBYP_SHIFT        (17U)
35401 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
35402  */
35403 #define DDRPHY_DX8SL0DXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXGDBYP_MASK)
35404 #define DDRPHY_DX8SL0DXCTL1_DXQSDBYP_MASK        (0x40000U)
35405 #define DDRPHY_DX8SL0DXCTL1_DXQSDBYP_SHIFT       (18U)
35406 /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
35407  */
35408 #define DDRPHY_DX8SL0DXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXQSDBYP_MASK)
35409 #define DDRPHY_DX8SL0DXCTL1_DXGSMD_MASK          (0x80000U)
35410 #define DDRPHY_DX8SL0DXCTL1_DXGSMD_SHIFT         (19U)
35411 /*! DXGSMD - Read DQS Gating Status Mode
35412  */
35413 #define DDRPHY_DX8SL0DXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXGSMD_MASK)
35414 #define DDRPHY_DX8SL0DXCTL1_DXDTOSEL_MASK        (0x300000U)
35415 #define DDRPHY_DX8SL0DXCTL1_DXDTOSEL_SHIFT       (20U)
35416 /*! DXDTOSEL - DATX8 Digital Test Output Select
35417  */
35418 #define DDRPHY_DX8SL0DXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXDTOSEL_MASK)
35419 #define DDRPHY_DX8SL0DXCTL1_RESERVED_22_MASK     (0x400000U)
35420 #define DDRPHY_DX8SL0DXCTL1_RESERVED_22_SHIFT    (22U)
35421 /*! RESERVED_22 - Reserved. Return zeroes on reads.
35422  */
35423 #define DDRPHY_DX8SL0DXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL0DXCTL1_RESERVED_22_MASK)
35424 #define DDRPHY_DX8SL0DXCTL1_DXRCLKMD_MASK        (0x800000U)
35425 #define DDRPHY_DX8SL0DXCTL1_DXRCLKMD_SHIFT       (23U)
35426 /*! DXRCLKMD - DATX8 Read Clock Mode
35427  */
35428 #define DDRPHY_DX8SL0DXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXRCLKMD_MASK)
35429 #define DDRPHY_DX8SL0DXCTL1_DXCALCLK_MASK        (0x1000000U)
35430 #define DDRPHY_DX8SL0DXCTL1_DXCALCLK_SHIFT       (24U)
35431 /*! DXCALCLK - DATX Calibration Clock Select
35432  */
35433 #define DDRPHY_DX8SL0DXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXCALCLK_MASK)
35434 #define DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
35435 #define DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_SHIFT (25U)
35436 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
35437  */
35438 #define DDRPHY_DX8SL0DXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_MASK)
35439 /*! @} */
35440 
35441 /*! @name DX8SL0DXCTL2 - DATX8 0-1 DX Control Register 2 */
35442 /*! @{ */
35443 #define DDRPHY_DX8SL0DXCTL2_RESERVED_0_MASK      (0x1U)
35444 #define DDRPHY_DX8SL0DXCTL2_RESERVED_0_SHIFT     (0U)
35445 /*! RESERVED_0 - Reserved. Return zeroes on reads.
35446  */
35447 #define DDRPHY_DX8SL0DXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_0_MASK)
35448 #define DDRPHY_DX8SL0DXCTL2_DQSGLB_MASK          (0x6U)
35449 #define DDRPHY_DX8SL0DXCTL2_DQSGLB_SHIFT         (1U)
35450 /*! DQSGLB - Read DQS Gate I/O Loopback
35451  */
35452 #define DDRPHY_DX8SL0DXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL0DXCTL2_DQSGLB_MASK)
35453 #define DDRPHY_DX8SL0DXCTL2_DISRST_MASK          (0x8U)
35454 #define DDRPHY_DX8SL0DXCTL2_DISRST_SHIFT         (3U)
35455 /*! DISRST - Disables the Read FIFO Reset
35456  */
35457 #define DDRPHY_DX8SL0DXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL0DXCTL2_DISRST_MASK)
35458 #define DDRPHY_DX8SL0DXCTL2_RDMODE_MASK          (0x30U)
35459 #define DDRPHY_DX8SL0DXCTL2_RDMODE_SHIFT         (4U)
35460 /*! RDMODE - DATX8 Receive FIFO Read Mode
35461  */
35462 #define DDRPHY_DX8SL0DXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RDMODE_MASK)
35463 #define DDRPHY_DX8SL0DXCTL2_PRFBYP_MASK          (0x40U)
35464 #define DDRPHY_DX8SL0DXCTL2_PRFBYP_SHIFT         (6U)
35465 /*! PRFBYP - PUB Read FIFO Bypass
35466  */
35467 #define DDRPHY_DX8SL0DXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL0DXCTL2_PRFBYP_MASK)
35468 #define DDRPHY_DX8SL0DXCTL2_WDBI_MASK            (0x80U)
35469 #define DDRPHY_DX8SL0DXCTL2_WDBI_SHIFT           (7U)
35470 /*! WDBI - Write Data Bus Inversion Enable
35471  */
35472 #define DDRPHY_DX8SL0DXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL0DXCTL2_WDBI_MASK)
35473 #define DDRPHY_DX8SL0DXCTL2_RDBI_MASK            (0x100U)
35474 #define DDRPHY_DX8SL0DXCTL2_RDBI_SHIFT           (8U)
35475 /*! RDBI - Read Data Bus Inversion Enable
35476  */
35477 #define DDRPHY_DX8SL0DXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RDBI_MASK)
35478 #define DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
35479 #define DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
35480 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
35481  */
35482 #define DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK)
35483 #define DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_MASK  (0x6000U)
35484 #define DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT (13U)
35485 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
35486  */
35487 #define DDRPHY_DX8SL0DXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_MASK)
35488 #define DDRPHY_DX8SL0DXCTL2_IOLB_MASK            (0x8000U)
35489 #define DDRPHY_DX8SL0DXCTL2_IOLB_SHIFT           (15U)
35490 /*! IOLB - I/O Loopback Select
35491  */
35492 #define DDRPHY_DX8SL0DXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL0DXCTL2_IOLB_MASK)
35493 #define DDRPHY_DX8SL0DXCTL2_IOAG_MASK            (0x10000U)
35494 #define DDRPHY_DX8SL0DXCTL2_IOAG_SHIFT           (16U)
35495 /*! IOAG - I/O Assisted Gate Select
35496  */
35497 #define DDRPHY_DX8SL0DXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL0DXCTL2_IOAG_MASK)
35498 #define DDRPHY_DX8SL0DXCTL2_RESERVED_17_MASK     (0x20000U)
35499 #define DDRPHY_DX8SL0DXCTL2_RESERVED_17_SHIFT    (17U)
35500 /*! RESERVED_17 - Reserved. Return zeroes on reads.
35501  */
35502 #define DDRPHY_DX8SL0DXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_17_MASK)
35503 #define DDRPHY_DX8SL0DXCTL2_PREOEX_MASK          (0xC0000U)
35504 #define DDRPHY_DX8SL0DXCTL2_PREOEX_SHIFT         (18U)
35505 /*! PREOEX - OE Extension during Pre-amble
35506  */
35507 #define DDRPHY_DX8SL0DXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL0DXCTL2_PREOEX_MASK)
35508 #define DDRPHY_DX8SL0DXCTL2_POSOEX_MASK          (0x700000U)
35509 #define DDRPHY_DX8SL0DXCTL2_POSOEX_SHIFT         (20U)
35510 /*! POSOEX - OX Extension during Post-amble
35511  */
35512 #define DDRPHY_DX8SL0DXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL0DXCTL2_POSOEX_MASK)
35513 #define DDRPHY_DX8SL0DXCTL2_CRDEN_MASK           (0x800000U)
35514 #define DDRPHY_DX8SL0DXCTL2_CRDEN_SHIFT          (23U)
35515 /*! CRDEN - Configurable Read Data Enable
35516  */
35517 #define DDRPHY_DX8SL0DXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL0DXCTL2_CRDEN_MASK)
35518 #define DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
35519 #define DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT (24U)
35520 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
35521  */
35522 #define DDRPHY_DX8SL0DXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_MASK)
35523 /*! @} */
35524 
35525 /*! @name DX8SL0IOCR - DATX8 0-1 I/O Configuration Register */
35526 /*! @{ */
35527 #define DDRPHY_DX8SL0IOCR_DXRXM_MASK             (0x7FFU)
35528 #define DDRPHY_DX8SL0IOCR_DXRXM_SHIFT            (0U)
35529 /*! DXRXM - DX IO Receiver Mode
35530  */
35531 #define DDRPHY_DX8SL0IOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXRXM_MASK)
35532 #define DDRPHY_DX8SL0IOCR_DXTXM_MASK             (0x3FF800U)
35533 #define DDRPHY_DX8SL0IOCR_DXTXM_SHIFT            (11U)
35534 /*! DXTXM - DX IO Transmitter Mode
35535  */
35536 #define DDRPHY_DX8SL0IOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXTXM_MASK)
35537 #define DDRPHY_DX8SL0IOCR_DXIOM_MASK             (0x1C00000U)
35538 #define DDRPHY_DX8SL0IOCR_DXIOM_SHIFT            (22U)
35539 /*! DXIOM - DX IO Mode
35540  */
35541 #define DDRPHY_DX8SL0IOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXIOM_MASK)
35542 #define DDRPHY_DX8SL0IOCR_DXVREFIOM_MASK         (0xE000000U)
35543 #define DDRPHY_DX8SL0IOCR_DXVREFIOM_SHIFT        (25U)
35544 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
35545  */
35546 #define DDRPHY_DX8SL0IOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXVREFIOM_MASK)
35547 #define DDRPHY_DX8SL0IOCR_DXDACRANGE_MASK        (0x70000000U)
35548 #define DDRPHY_DX8SL0IOCR_DXDACRANGE_SHIFT       (28U)
35549 /*! DXDACRANGE - PVREF_DAC REFSEL range select
35550  */
35551 #define DDRPHY_DX8SL0IOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL0IOCR_DXDACRANGE_MASK)
35552 #define DDRPHY_DX8SL0IOCR_RESERVED_31_MASK       (0x80000000U)
35553 #define DDRPHY_DX8SL0IOCR_RESERVED_31_SHIFT      (31U)
35554 /*! RESERVED_31 - Reserved. Return zeroes on reads.
35555  */
35556 #define DDRPHY_DX8SL0IOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL0IOCR_RESERVED_31_MASK)
35557 /*! @} */
35558 
35559 /*! @name DX4SL0IOCR - DATX4 Slice 0-1 I/O Configuration Register */
35560 /*! @{ */
35561 #define DDRPHY_DX4SL0IOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
35562 #define DDRPHY_DX4SL0IOCR_RESERVED_31_0_SHIFT    (0U)
35563 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
35564  */
35565 #define DDRPHY_DX4SL0IOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL0IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL0IOCR_RESERVED_31_0_MASK)
35566 /*! @} */
35567 
35568 /*! @name DX8SL1OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
35569 /*! @{ */
35570 #define DDRPHY_DX8SL1OSC_OSCEN_MASK              (0x1U)
35571 #define DDRPHY_DX8SL1OSC_OSCEN_SHIFT             (0U)
35572 /*! OSCEN - Oscillator Enable
35573  */
35574 #define DDRPHY_DX8SL1OSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL1OSC_OSCEN_MASK)
35575 #define DDRPHY_DX8SL1OSC_OSCDIV_MASK             (0x1EU)
35576 #define DDRPHY_DX8SL1OSC_OSCDIV_SHIFT            (1U)
35577 /*! OSCDIV - Oscillator Mode Division
35578  */
35579 #define DDRPHY_DX8SL1OSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL1OSC_OSCDIV_MASK)
35580 #define DDRPHY_DX8SL1OSC_OSCWDL_MASK             (0x60U)
35581 #define DDRPHY_DX8SL1OSC_OSCWDL_SHIFT            (5U)
35582 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
35583  */
35584 #define DDRPHY_DX8SL1OSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL1OSC_OSCWDL_MASK)
35585 #define DDRPHY_DX8SL1OSC_RESERVED_8_7_MASK       (0x180U)
35586 #define DDRPHY_DX8SL1OSC_RESERVED_8_7_SHIFT      (7U)
35587 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
35588  */
35589 #define DDRPHY_DX8SL1OSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL1OSC_RESERVED_8_7_MASK)
35590 #define DDRPHY_DX8SL1OSC_OSCWDDL_MASK            (0x600U)
35591 #define DDRPHY_DX8SL1OSC_OSCWDDL_SHIFT           (9U)
35592 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
35593  */
35594 #define DDRPHY_DX8SL1OSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL1OSC_OSCWDDL_MASK)
35595 #define DDRPHY_DX8SL1OSC_RESERVED_12_11_MASK     (0x1800U)
35596 #define DDRPHY_DX8SL1OSC_RESERVED_12_11_SHIFT    (11U)
35597 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
35598  */
35599 #define DDRPHY_DX8SL1OSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL1OSC_RESERVED_12_11_MASK)
35600 #define DDRPHY_DX8SL1OSC_DLTMODE_MASK            (0x2000U)
35601 #define DDRPHY_DX8SL1OSC_DLTMODE_SHIFT           (13U)
35602 /*! DLTMODE - Delay Line Test Mode
35603  */
35604 #define DDRPHY_DX8SL1OSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL1OSC_DLTMODE_MASK)
35605 #define DDRPHY_DX8SL1OSC_DLTST_MASK              (0x4000U)
35606 #define DDRPHY_DX8SL1OSC_DLTST_SHIFT             (14U)
35607 /*! DLTST - Delay Line Test Start
35608  */
35609 #define DDRPHY_DX8SL1OSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_DLTST_SHIFT)) & DDRPHY_DX8SL1OSC_DLTST_MASK)
35610 #define DDRPHY_DX8SL1OSC_PHYFRST_MASK            (0x8000U)
35611 #define DDRPHY_DX8SL1OSC_PHYFRST_SHIFT           (15U)
35612 /*! PHYFRST - PHY FIFO Reset
35613  */
35614 #define DDRPHY_DX8SL1OSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL1OSC_PHYFRST_MASK)
35615 #define DDRPHY_DX8SL1OSC_PHYHRST_MASK            (0x10000U)
35616 #define DDRPHY_DX8SL1OSC_PHYHRST_SHIFT           (16U)
35617 /*! PHYHRST - PHY High-Speed Reset
35618  */
35619 #define DDRPHY_DX8SL1OSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL1OSC_PHYHRST_MASK)
35620 #define DDRPHY_DX8SL1OSC_LBDQSS_MASK             (0x20000U)
35621 #define DDRPHY_DX8SL1OSC_LBDQSS_SHIFT            (17U)
35622 /*! LBDQSS - Loopback DQS Shift
35623  */
35624 #define DDRPHY_DX8SL1OSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL1OSC_LBDQSS_MASK)
35625 #define DDRPHY_DX8SL1OSC_LBGDQS_MASK             (0xC0000U)
35626 #define DDRPHY_DX8SL1OSC_LBGDQS_SHIFT            (18U)
35627 /*! LBGDQS - Loopback DQS Gating
35628  */
35629 #define DDRPHY_DX8SL1OSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL1OSC_LBGDQS_MASK)
35630 #define DDRPHY_DX8SL1OSC_LBGSDQS_MASK            (0x100000U)
35631 #define DDRPHY_DX8SL1OSC_LBGSDQS_SHIFT           (20U)
35632 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
35633  */
35634 #define DDRPHY_DX8SL1OSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL1OSC_LBGSDQS_MASK)
35635 #define DDRPHY_DX8SL1OSC_LBMODE_MASK             (0x200000U)
35636 #define DDRPHY_DX8SL1OSC_LBMODE_SHIFT            (21U)
35637 /*! LBMODE - Loopback Mode
35638  */
35639 #define DDRPHY_DX8SL1OSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL1OSC_LBMODE_MASK)
35640 #define DDRPHY_DX8SL1OSC_CLKLEVEL_MASK           (0xC00000U)
35641 #define DDRPHY_DX8SL1OSC_CLKLEVEL_SHIFT          (22U)
35642 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
35643  */
35644 #define DDRPHY_DX8SL1OSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL1OSC_CLKLEVEL_MASK)
35645 #define DDRPHY_DX8SL1OSC_GATEDXCTLCLK_MASK       (0x3000000U)
35646 #define DDRPHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT      (24U)
35647 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
35648  */
35649 #define DDRPHY_DX8SL1OSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL1OSC_GATEDXCTLCLK_MASK)
35650 #define DDRPHY_DX8SL1OSC_GATEDXDDRCLK_MASK       (0xC000000U)
35651 #define DDRPHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT      (26U)
35652 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
35653  */
35654 #define DDRPHY_DX8SL1OSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL1OSC_GATEDXDDRCLK_MASK)
35655 #define DDRPHY_DX8SL1OSC_GATEDXRDCLK_MASK        (0x30000000U)
35656 #define DDRPHY_DX8SL1OSC_GATEDXRDCLK_SHIFT       (28U)
35657 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
35658  */
35659 #define DDRPHY_DX8SL1OSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL1OSC_GATEDXRDCLK_MASK)
35660 #define DDRPHY_DX8SL1OSC_RESERVED_31_30_MASK     (0xC0000000U)
35661 #define DDRPHY_DX8SL1OSC_RESERVED_31_30_SHIFT    (30U)
35662 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
35663  */
35664 #define DDRPHY_DX8SL1OSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL1OSC_RESERVED_31_30_MASK)
35665 /*! @} */
35666 
35667 /*! @name DX8SL1PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
35668 /*! @{ */
35669 #define DDRPHY_DX8SL1PLLCR0_DTC_MASK             (0xFU)
35670 #define DDRPHY_DX8SL1PLLCR0_DTC_SHIFT            (0U)
35671 /*! DTC - Digital Test Control
35672  */
35673 #define DDRPHY_DX8SL1PLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_DTC_MASK)
35674 #define DDRPHY_DX8SL1PLLCR0_ATC_MASK             (0xF0U)
35675 #define DDRPHY_DX8SL1PLLCR0_ATC_SHIFT            (4U)
35676 /*! ATC - Analog Test Control
35677  */
35678 #define DDRPHY_DX8SL1PLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_ATC_MASK)
35679 #define DDRPHY_DX8SL1PLLCR0_ATOEN_MASK           (0x100U)
35680 #define DDRPHY_DX8SL1PLLCR0_ATOEN_SHIFT          (8U)
35681 /*! ATOEN - Analog Test Enable (ATOEN)
35682  */
35683 #define DDRPHY_DX8SL1PLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL1PLLCR0_ATOEN_MASK)
35684 #define DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_MASK   (0xE00U)
35685 #define DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT  (9U)
35686 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
35687  */
35688 #define DDRPHY_DX8SL1PLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_MASK)
35689 #define DDRPHY_DX8SL1PLLCR0_GSHIFT_MASK          (0x1000U)
35690 #define DDRPHY_DX8SL1PLLCR0_GSHIFT_SHIFT         (12U)
35691 /*! GSHIFT - Gear Shift
35692  */
35693 #define DDRPHY_DX8SL1PLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL1PLLCR0_GSHIFT_MASK)
35694 #define DDRPHY_DX8SL1PLLCR0_CPIC_MASK            (0x1E000U)
35695 #define DDRPHY_DX8SL1PLLCR0_CPIC_SHIFT           (13U)
35696 /*! CPIC - Charge Pump Integrating Current Control
35697  */
35698 #define DDRPHY_DX8SL1PLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_CPIC_MASK)
35699 #define DDRPHY_DX8SL1PLLCR0_CPPC_MASK            (0x7E0000U)
35700 #define DDRPHY_DX8SL1PLLCR0_CPPC_SHIFT           (17U)
35701 /*! CPPC - Charge Pump Proportional Current Control
35702  */
35703 #define DDRPHY_DX8SL1PLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_CPPC_MASK)
35704 #define DDRPHY_DX8SL1PLLCR0_RLOCKM_MASK          (0x800000U)
35705 #define DDRPHY_DX8SL1PLLCR0_RLOCKM_SHIFT         (23U)
35706 /*! RLOCKM - Relock Mode
35707  */
35708 #define DDRPHY_DX8SL1PLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL1PLLCR0_RLOCKM_MASK)
35709 #define DDRPHY_DX8SL1PLLCR0_FRQSEL_MASK          (0xF000000U)
35710 #define DDRPHY_DX8SL1PLLCR0_FRQSEL_SHIFT         (24U)
35711 /*! FRQSEL - PLL Frequency Select
35712  */
35713 #define DDRPHY_DX8SL1PLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL1PLLCR0_FRQSEL_MASK)
35714 #define DDRPHY_DX8SL1PLLCR0_RSTOPM_MASK          (0x10000000U)
35715 #define DDRPHY_DX8SL1PLLCR0_RSTOPM_SHIFT         (28U)
35716 /*! RSTOPM - Reference Stop Mode
35717  */
35718 #define DDRPHY_DX8SL1PLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL1PLLCR0_RSTOPM_MASK)
35719 #define DDRPHY_DX8SL1PLLCR0_PLLPD_MASK           (0x20000000U)
35720 #define DDRPHY_DX8SL1PLLCR0_PLLPD_SHIFT          (29U)
35721 /*! PLLPD - PLL Power Down
35722  */
35723 #define DDRPHY_DX8SL1PLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL1PLLCR0_PLLPD_MASK)
35724 #define DDRPHY_DX8SL1PLLCR0_PLLRST_MASK          (0x40000000U)
35725 #define DDRPHY_DX8SL1PLLCR0_PLLRST_SHIFT         (30U)
35726 /*! PLLRST - PLL Reset
35727  */
35728 #define DDRPHY_DX8SL1PLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL1PLLCR0_PLLRST_MASK)
35729 #define DDRPHY_DX8SL1PLLCR0_PLLBYP_MASK          (0x80000000U)
35730 #define DDRPHY_DX8SL1PLLCR0_PLLBYP_SHIFT         (31U)
35731 /*! PLLBYP - PLL Bypass
35732  */
35733 #define DDRPHY_DX8SL1PLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL1PLLCR0_PLLBYP_MASK)
35734 /*! @} */
35735 
35736 /*! @name DX8SL1PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
35737 /*! @{ */
35738 #define DDRPHY_DX8SL1PLLCR1_LOCKDS_MASK          (0x1U)
35739 #define DDRPHY_DX8SL1PLLCR1_LOCKDS_SHIFT         (0U)
35740 /*! LOCKDS - Lock Detector Select
35741  */
35742 #define DDRPHY_DX8SL1PLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL1PLLCR1_LOCKDS_MASK)
35743 #define DDRPHY_DX8SL1PLLCR1_LOCKCS_MASK          (0x2U)
35744 #define DDRPHY_DX8SL1PLLCR1_LOCKCS_SHIFT         (1U)
35745 /*! LOCKCS - Lock Detector Counter Select
35746  */
35747 #define DDRPHY_DX8SL1PLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL1PLLCR1_LOCKCS_MASK)
35748 #define DDRPHY_DX8SL1PLLCR1_LOCKPS_MASK          (0x4U)
35749 #define DDRPHY_DX8SL1PLLCR1_LOCKPS_SHIFT         (2U)
35750 /*! LOCKPS - Lock Detector Phase Select
35751  */
35752 #define DDRPHY_DX8SL1PLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL1PLLCR1_LOCKPS_MASK)
35753 #define DDRPHY_DX8SL1PLLCR1_BYPVDD_MASK          (0x8U)
35754 #define DDRPHY_DX8SL1PLLCR1_BYPVDD_SHIFT         (3U)
35755 /*! BYPVDD - PLL VDD voltage level control
35756  */
35757 #define DDRPHY_DX8SL1PLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL1PLLCR1_BYPVDD_MASK)
35758 #define DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_MASK      (0x10U)
35759 #define DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_SHIFT     (4U)
35760 /*! BYPVREGDIG - Bypass PLL vreg_dig
35761  */
35762 #define DDRPHY_DX8SL1PLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_MASK)
35763 #define DDRPHY_DX8SL1PLLCR1_BYPVREGCP_MASK       (0x20U)
35764 #define DDRPHY_DX8SL1PLLCR1_BYPVREGCP_SHIFT      (5U)
35765 /*! BYPVREGCP - Bypass PLL vreg_cp
35766  */
35767 #define DDRPHY_DX8SL1PLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL1PLLCR1_BYPVREGCP_MASK)
35768 #define DDRPHY_DX8SL1PLLCR1_PLLPROG_MASK         (0x3FFFC0U)
35769 #define DDRPHY_DX8SL1PLLCR1_PLLPROG_SHIFT        (6U)
35770 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
35771  */
35772 #define DDRPHY_DX8SL1PLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL1PLLCR1_PLLPROG_MASK)
35773 #define DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
35774 #define DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_SHIFT (22U)
35775 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
35776  */
35777 #define DDRPHY_DX8SL1PLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_MASK)
35778 /*! @} */
35779 
35780 /*! @name DX8SL1PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
35781 /*! @{ */
35782 #define DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
35783 #define DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_SHIFT   (0U)
35784 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
35785  */
35786 #define DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_MASK)
35787 /*! @} */
35788 
35789 /*! @name DX8SL1PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
35790 /*! @{ */
35791 #define DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
35792 #define DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_SHIFT  (0U)
35793 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
35794  */
35795 #define DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_MASK)
35796 /*! @} */
35797 
35798 /*! @name DX8SL1PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
35799 /*! @{ */
35800 #define DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
35801 #define DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_SHIFT  (0U)
35802 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
35803  */
35804 #define DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_MASK)
35805 /*! @} */
35806 
35807 /*! @name DX8SL1PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
35808 /*! @{ */
35809 #define DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
35810 #define DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_SHIFT (0U)
35811 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
35812  */
35813 #define DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_MASK)
35814 #define DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
35815 #define DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_SHIFT  (8U)
35816 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
35817  */
35818 #define DDRPHY_DX8SL1PLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_MASK)
35819 /*! @} */
35820 
35821 /*! @name DX8SL1DQSCTL - DATX8 0-1 DQS Control Register */
35822 /*! @{ */
35823 #define DDRPHY_DX8SL1DQSCTL_DQSRES_MASK          (0xFU)
35824 #define DDRPHY_DX8SL1DQSCTL_DQSRES_SHIFT         (0U)
35825 /*! DQSRES - DQS Resistor
35826  */
35827 #define DDRPHY_DX8SL1DQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DQSRES_MASK)
35828 #define DDRPHY_DX8SL1DQSCTL_DQSNRES_MASK         (0xF0U)
35829 #define DDRPHY_DX8SL1DQSCTL_DQSNRES_SHIFT        (4U)
35830 /*! DQSNRES - DQS_N Resistor
35831  */
35832 #define DDRPHY_DX8SL1DQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DQSNRES_MASK)
35833 #define DDRPHY_DX8SL1DQSCTL_DXSR_MASK            (0x300U)
35834 #define DDRPHY_DX8SL1DQSCTL_DXSR_SHIFT           (8U)
35835 /*! DXSR - Data Slew Rate
35836  */
35837 #define DDRPHY_DX8SL1DQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DXSR_MASK)
35838 #define DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_MASK  (0x1C00U)
35839 #define DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT (10U)
35840 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
35841  */
35842 #define DDRPHY_DX8SL1DQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_MASK)
35843 #define DDRPHY_DX8SL1DQSCTL_UDQIOM_MASK          (0x2000U)
35844 #define DDRPHY_DX8SL1DQSCTL_UDQIOM_SHIFT         (13U)
35845 /*! UDQIOM - Unused DQ I/O Mode
35846  */
35847 #define DDRPHY_DX8SL1DQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL1DQSCTL_UDQIOM_MASK)
35848 #define DDRPHY_DX8SL1DQSCTL_QSCNTEN_MASK         (0x4000U)
35849 #define DDRPHY_DX8SL1DQSCTL_QSCNTEN_SHIFT        (14U)
35850 /*! QSCNTEN - QS Counter Enable
35851  */
35852 #define DDRPHY_DX8SL1DQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL1DQSCTL_QSCNTEN_MASK)
35853 #define DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_MASK  (0x18000U)
35854 #define DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT (15U)
35855 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
35856  */
35857 #define DDRPHY_DX8SL1DQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_MASK)
35858 #define DDRPHY_DX8SL1DQSCTL_LPIOPD_MASK          (0x20000U)
35859 #define DDRPHY_DX8SL1DQSCTL_LPIOPD_SHIFT         (17U)
35860 /*! LPIOPD - Low Power I/O Power Down
35861  */
35862 #define DDRPHY_DX8SL1DQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL1DQSCTL_LPIOPD_MASK)
35863 #define DDRPHY_DX8SL1DQSCTL_LPPLLPD_MASK         (0x40000U)
35864 #define DDRPHY_DX8SL1DQSCTL_LPPLLPD_SHIFT        (18U)
35865 /*! LPPLLPD - Low Power PLL Power Down
35866  */
35867 #define DDRPHY_DX8SL1DQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL1DQSCTL_LPPLLPD_MASK)
35868 #define DDRPHY_DX8SL1DQSCTL_DQSGX_MASK           (0x180000U)
35869 #define DDRPHY_DX8SL1DQSCTL_DQSGX_SHIFT          (19U)
35870 /*! DQSGX - DQS Gate Extension
35871  */
35872 #define DDRPHY_DX8SL1DQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DQSGX_MASK)
35873 #define DDRPHY_DX8SL1DQSCTL_WRRMODE_MASK         (0x200000U)
35874 #define DDRPHY_DX8SL1DQSCTL_WRRMODE_SHIFT        (21U)
35875 /*! WRRMODE - Write Path Rise-to-Rise Mode
35876  */
35877 #define DDRPHY_DX8SL1DQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL1DQSCTL_WRRMODE_MASK)
35878 #define DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_MASK  (0xC00000U)
35879 #define DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT (22U)
35880 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
35881  */
35882 #define DDRPHY_DX8SL1DQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_MASK)
35883 #define DDRPHY_DX8SL1DQSCTL_RRRMODE_MASK         (0x1000000U)
35884 #define DDRPHY_DX8SL1DQSCTL_RRRMODE_SHIFT        (24U)
35885 /*! RRRMODE - Read Path Rise-to-Rise Mode
35886  */
35887 #define DDRPHY_DX8SL1DQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RRRMODE_MASK)
35888 #define DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
35889 #define DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT (25U)
35890 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
35891  */
35892 #define DDRPHY_DX8SL1DQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_MASK)
35893 /*! @} */
35894 
35895 /*! @name DX8SL1TRNCTL - DATX8 0-1 Training Control Register */
35896 /*! @{ */
35897 #define DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
35898 #define DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_SHIFT  (0U)
35899 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
35900  */
35901 #define DDRPHY_DX8SL1TRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_MASK)
35902 /*! @} */
35903 
35904 /*! @name DX8SL1DDLCTL - DATX8 0-1 DDL Control Register */
35905 /*! @{ */
35906 #define DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_MASK      (0x3U)
35907 #define DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_SHIFT     (0U)
35908 /*! DDLBYPMODE - Controls DDL Bypass Mode
35909  */
35910 #define DDRPHY_DX8SL1DDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_MASK)
35911 #define DDRPHY_DX8SL1DDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
35912 #define DDRPHY_DX8SL1DDLCTL_DXDDLBYP_SHIFT       (2U)
35913 /*! DXDDLBYP - DATX8 DDL Bypass
35914  */
35915 #define DDRPHY_DX8SL1DDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DXDDLBYP_MASK)
35916 #define DDRPHY_DX8SL1DDLCTL_DXDDLLD_MASK         (0x7C0000U)
35917 #define DDRPHY_DX8SL1DDLCTL_DXDDLLD_SHIFT        (18U)
35918 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
35919  */
35920 #define DDRPHY_DX8SL1DDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DXDDLLD_MASK)
35921 #define DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_MASK  (0x1800000U)
35922 #define DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_SHIFT (23U)
35923 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
35924  */
35925 #define DDRPHY_DX8SL1DDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_MASK)
35926 #define DDRPHY_DX8SL1DDLCTL_DXDDLLDT_MASK        (0x2000000U)
35927 #define DDRPHY_DX8SL1DDLCTL_DXDDLLDT_SHIFT       (25U)
35928 /*! DXDDLLDT - DX DDL Load Type
35929  */
35930 #define DDRPHY_DX8SL1DDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DXDDLLDT_MASK)
35931 #define DDRPHY_DX8SL1DDLCTL_DLYLDTM_MASK         (0x4000000U)
35932 #define DDRPHY_DX8SL1DDLCTL_DLYLDTM_SHIFT        (26U)
35933 /*! DLYLDTM - Delay Load Timing
35934  */
35935 #define DDRPHY_DX8SL1DDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DLYLDTM_MASK)
35936 #define DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
35937 #define DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_SHIFT (27U)
35938 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
35939  */
35940 #define DDRPHY_DX8SL1DDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_MASK)
35941 /*! @} */
35942 
35943 /*! @name DX8SL1DXCTL1 - DATX8 0-1 DX Control Register 1 */
35944 /*! @{ */
35945 #define DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
35946 #define DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_SHIFT  (0U)
35947 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
35948  */
35949 #define DDRPHY_DX8SL1DXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_MASK)
35950 #define DDRPHY_DX8SL1DXCTL1_DXTMODE_MASK         (0x10000U)
35951 #define DDRPHY_DX8SL1DXCTL1_DXTMODE_SHIFT        (16U)
35952 /*! DXTMODE - DATX8 Test Mode
35953  */
35954 #define DDRPHY_DX8SL1DXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXTMODE_MASK)
35955 #define DDRPHY_DX8SL1DXCTL1_DXGDBYP_MASK         (0x20000U)
35956 #define DDRPHY_DX8SL1DXCTL1_DXGDBYP_SHIFT        (17U)
35957 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
35958  */
35959 #define DDRPHY_DX8SL1DXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXGDBYP_MASK)
35960 #define DDRPHY_DX8SL1DXCTL1_DXQSDBYP_MASK        (0x40000U)
35961 #define DDRPHY_DX8SL1DXCTL1_DXQSDBYP_SHIFT       (18U)
35962 /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
35963  */
35964 #define DDRPHY_DX8SL1DXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXQSDBYP_MASK)
35965 #define DDRPHY_DX8SL1DXCTL1_DXGSMD_MASK          (0x80000U)
35966 #define DDRPHY_DX8SL1DXCTL1_DXGSMD_SHIFT         (19U)
35967 /*! DXGSMD - Read DQS Gating Status Mode
35968  */
35969 #define DDRPHY_DX8SL1DXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXGSMD_MASK)
35970 #define DDRPHY_DX8SL1DXCTL1_DXDTOSEL_MASK        (0x300000U)
35971 #define DDRPHY_DX8SL1DXCTL1_DXDTOSEL_SHIFT       (20U)
35972 /*! DXDTOSEL - DATX8 Digital Test Output Select
35973  */
35974 #define DDRPHY_DX8SL1DXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXDTOSEL_MASK)
35975 #define DDRPHY_DX8SL1DXCTL1_RESERVED_22_MASK     (0x400000U)
35976 #define DDRPHY_DX8SL1DXCTL1_RESERVED_22_SHIFT    (22U)
35977 /*! RESERVED_22 - Reserved. Return zeroes on reads.
35978  */
35979 #define DDRPHY_DX8SL1DXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL1DXCTL1_RESERVED_22_MASK)
35980 #define DDRPHY_DX8SL1DXCTL1_DXRCLKMD_MASK        (0x800000U)
35981 #define DDRPHY_DX8SL1DXCTL1_DXRCLKMD_SHIFT       (23U)
35982 /*! DXRCLKMD - DATX8 Read Clock Mode
35983  */
35984 #define DDRPHY_DX8SL1DXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXRCLKMD_MASK)
35985 #define DDRPHY_DX8SL1DXCTL1_DXCALCLK_MASK        (0x1000000U)
35986 #define DDRPHY_DX8SL1DXCTL1_DXCALCLK_SHIFT       (24U)
35987 /*! DXCALCLK - DATX Calibration Clock Select
35988  */
35989 #define DDRPHY_DX8SL1DXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXCALCLK_MASK)
35990 #define DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
35991 #define DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_SHIFT (25U)
35992 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
35993  */
35994 #define DDRPHY_DX8SL1DXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_MASK)
35995 /*! @} */
35996 
35997 /*! @name DX8SL1DXCTL2 - DATX8 0-1 DX Control Register 2 */
35998 /*! @{ */
35999 #define DDRPHY_DX8SL1DXCTL2_RESERVED_0_MASK      (0x1U)
36000 #define DDRPHY_DX8SL1DXCTL2_RESERVED_0_SHIFT     (0U)
36001 /*! RESERVED_0 - Reserved. Return zeroes on reads.
36002  */
36003 #define DDRPHY_DX8SL1DXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_0_MASK)
36004 #define DDRPHY_DX8SL1DXCTL2_DQSGLB_MASK          (0x6U)
36005 #define DDRPHY_DX8SL1DXCTL2_DQSGLB_SHIFT         (1U)
36006 /*! DQSGLB - Read DQS Gate I/O Loopback
36007  */
36008 #define DDRPHY_DX8SL1DXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL1DXCTL2_DQSGLB_MASK)
36009 #define DDRPHY_DX8SL1DXCTL2_DISRST_MASK          (0x8U)
36010 #define DDRPHY_DX8SL1DXCTL2_DISRST_SHIFT         (3U)
36011 /*! DISRST - Disables the Read FIFO Reset
36012  */
36013 #define DDRPHY_DX8SL1DXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL1DXCTL2_DISRST_MASK)
36014 #define DDRPHY_DX8SL1DXCTL2_RDMODE_MASK          (0x30U)
36015 #define DDRPHY_DX8SL1DXCTL2_RDMODE_SHIFT         (4U)
36016 /*! RDMODE - DATX8 Receive FIFO Read Mode
36017  */
36018 #define DDRPHY_DX8SL1DXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RDMODE_MASK)
36019 #define DDRPHY_DX8SL1DXCTL2_PRFBYP_MASK          (0x40U)
36020 #define DDRPHY_DX8SL1DXCTL2_PRFBYP_SHIFT         (6U)
36021 /*! PRFBYP - PUB Read FIFO Bypass
36022  */
36023 #define DDRPHY_DX8SL1DXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL1DXCTL2_PRFBYP_MASK)
36024 #define DDRPHY_DX8SL1DXCTL2_WDBI_MASK            (0x80U)
36025 #define DDRPHY_DX8SL1DXCTL2_WDBI_SHIFT           (7U)
36026 /*! WDBI - Write Data Bus Inversion Enable
36027  */
36028 #define DDRPHY_DX8SL1DXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL1DXCTL2_WDBI_MASK)
36029 #define DDRPHY_DX8SL1DXCTL2_RDBI_MASK            (0x100U)
36030 #define DDRPHY_DX8SL1DXCTL2_RDBI_SHIFT           (8U)
36031 /*! RDBI - Read Data Bus Inversion Enable
36032  */
36033 #define DDRPHY_DX8SL1DXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RDBI_MASK)
36034 #define DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
36035 #define DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
36036 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
36037  */
36038 #define DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK)
36039 #define DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_MASK  (0x6000U)
36040 #define DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT (13U)
36041 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
36042  */
36043 #define DDRPHY_DX8SL1DXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_MASK)
36044 #define DDRPHY_DX8SL1DXCTL2_IOLB_MASK            (0x8000U)
36045 #define DDRPHY_DX8SL1DXCTL2_IOLB_SHIFT           (15U)
36046 /*! IOLB - I/O Loopback Select
36047  */
36048 #define DDRPHY_DX8SL1DXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL1DXCTL2_IOLB_MASK)
36049 #define DDRPHY_DX8SL1DXCTL2_IOAG_MASK            (0x10000U)
36050 #define DDRPHY_DX8SL1DXCTL2_IOAG_SHIFT           (16U)
36051 /*! IOAG - I/O Assisted Gate Select
36052  */
36053 #define DDRPHY_DX8SL1DXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL1DXCTL2_IOAG_MASK)
36054 #define DDRPHY_DX8SL1DXCTL2_RESERVED_17_MASK     (0x20000U)
36055 #define DDRPHY_DX8SL1DXCTL2_RESERVED_17_SHIFT    (17U)
36056 /*! RESERVED_17 - Reserved. Return zeroes on reads.
36057  */
36058 #define DDRPHY_DX8SL1DXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_17_MASK)
36059 #define DDRPHY_DX8SL1DXCTL2_PREOEX_MASK          (0xC0000U)
36060 #define DDRPHY_DX8SL1DXCTL2_PREOEX_SHIFT         (18U)
36061 /*! PREOEX - OE Extension during Pre-amble
36062  */
36063 #define DDRPHY_DX8SL1DXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL1DXCTL2_PREOEX_MASK)
36064 #define DDRPHY_DX8SL1DXCTL2_POSOEX_MASK          (0x700000U)
36065 #define DDRPHY_DX8SL1DXCTL2_POSOEX_SHIFT         (20U)
36066 /*! POSOEX - OX Extension during Post-amble
36067  */
36068 #define DDRPHY_DX8SL1DXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL1DXCTL2_POSOEX_MASK)
36069 #define DDRPHY_DX8SL1DXCTL2_CRDEN_MASK           (0x800000U)
36070 #define DDRPHY_DX8SL1DXCTL2_CRDEN_SHIFT          (23U)
36071 /*! CRDEN - Configurable Read Data Enable
36072  */
36073 #define DDRPHY_DX8SL1DXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL1DXCTL2_CRDEN_MASK)
36074 #define DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
36075 #define DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT (24U)
36076 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
36077  */
36078 #define DDRPHY_DX8SL1DXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_MASK)
36079 /*! @} */
36080 
36081 /*! @name DX8SL1IOCR - DATX8 0-1 I/O Configuration Register */
36082 /*! @{ */
36083 #define DDRPHY_DX8SL1IOCR_DXRXM_MASK             (0x7FFU)
36084 #define DDRPHY_DX8SL1IOCR_DXRXM_SHIFT            (0U)
36085 /*! DXRXM - DX IO Receiver Mode
36086  */
36087 #define DDRPHY_DX8SL1IOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXRXM_MASK)
36088 #define DDRPHY_DX8SL1IOCR_DXTXM_MASK             (0x3FF800U)
36089 #define DDRPHY_DX8SL1IOCR_DXTXM_SHIFT            (11U)
36090 /*! DXTXM - DX IO Transmitter Mode
36091  */
36092 #define DDRPHY_DX8SL1IOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXTXM_MASK)
36093 #define DDRPHY_DX8SL1IOCR_DXIOM_MASK             (0x1C00000U)
36094 #define DDRPHY_DX8SL1IOCR_DXIOM_SHIFT            (22U)
36095 /*! DXIOM - DX IO Mode
36096  */
36097 #define DDRPHY_DX8SL1IOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXIOM_MASK)
36098 #define DDRPHY_DX8SL1IOCR_DXVREFIOM_MASK         (0xE000000U)
36099 #define DDRPHY_DX8SL1IOCR_DXVREFIOM_SHIFT        (25U)
36100 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
36101  */
36102 #define DDRPHY_DX8SL1IOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXVREFIOM_MASK)
36103 #define DDRPHY_DX8SL1IOCR_DXDACRANGE_MASK        (0x70000000U)
36104 #define DDRPHY_DX8SL1IOCR_DXDACRANGE_SHIFT       (28U)
36105 /*! DXDACRANGE - PVREF_DAC REFSEL range select
36106  */
36107 #define DDRPHY_DX8SL1IOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL1IOCR_DXDACRANGE_MASK)
36108 #define DDRPHY_DX8SL1IOCR_RESERVED_31_MASK       (0x80000000U)
36109 #define DDRPHY_DX8SL1IOCR_RESERVED_31_SHIFT      (31U)
36110 /*! RESERVED_31 - Reserved. Return zeroes on reads.
36111  */
36112 #define DDRPHY_DX8SL1IOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL1IOCR_RESERVED_31_MASK)
36113 /*! @} */
36114 
36115 /*! @name DX4SL1IOCR - DATX4 Slice 0-1 I/O Configuration Register */
36116 /*! @{ */
36117 #define DDRPHY_DX4SL1IOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
36118 #define DDRPHY_DX4SL1IOCR_RESERVED_31_0_SHIFT    (0U)
36119 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
36120  */
36121 #define DDRPHY_DX4SL1IOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL1IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL1IOCR_RESERVED_31_0_MASK)
36122 /*! @} */
36123 
36124 /*! @name DX8SL2OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
36125 /*! @{ */
36126 #define DDRPHY_DX8SL2OSC_OSCEN_MASK              (0x1U)
36127 #define DDRPHY_DX8SL2OSC_OSCEN_SHIFT             (0U)
36128 /*! OSCEN - Oscillator Enable
36129  */
36130 #define DDRPHY_DX8SL2OSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL2OSC_OSCEN_MASK)
36131 #define DDRPHY_DX8SL2OSC_OSCDIV_MASK             (0x1EU)
36132 #define DDRPHY_DX8SL2OSC_OSCDIV_SHIFT            (1U)
36133 /*! OSCDIV - Oscillator Mode Division
36134  */
36135 #define DDRPHY_DX8SL2OSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL2OSC_OSCDIV_MASK)
36136 #define DDRPHY_DX8SL2OSC_OSCWDL_MASK             (0x60U)
36137 #define DDRPHY_DX8SL2OSC_OSCWDL_SHIFT            (5U)
36138 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
36139  */
36140 #define DDRPHY_DX8SL2OSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL2OSC_OSCWDL_MASK)
36141 #define DDRPHY_DX8SL2OSC_RESERVED_8_7_MASK       (0x180U)
36142 #define DDRPHY_DX8SL2OSC_RESERVED_8_7_SHIFT      (7U)
36143 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
36144  */
36145 #define DDRPHY_DX8SL2OSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL2OSC_RESERVED_8_7_MASK)
36146 #define DDRPHY_DX8SL2OSC_OSCWDDL_MASK            (0x600U)
36147 #define DDRPHY_DX8SL2OSC_OSCWDDL_SHIFT           (9U)
36148 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
36149  */
36150 #define DDRPHY_DX8SL2OSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL2OSC_OSCWDDL_MASK)
36151 #define DDRPHY_DX8SL2OSC_RESERVED_12_11_MASK     (0x1800U)
36152 #define DDRPHY_DX8SL2OSC_RESERVED_12_11_SHIFT    (11U)
36153 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
36154  */
36155 #define DDRPHY_DX8SL2OSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL2OSC_RESERVED_12_11_MASK)
36156 #define DDRPHY_DX8SL2OSC_DLTMODE_MASK            (0x2000U)
36157 #define DDRPHY_DX8SL2OSC_DLTMODE_SHIFT           (13U)
36158 /*! DLTMODE - Delay Line Test Mode
36159  */
36160 #define DDRPHY_DX8SL2OSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL2OSC_DLTMODE_MASK)
36161 #define DDRPHY_DX8SL2OSC_DLTST_MASK              (0x4000U)
36162 #define DDRPHY_DX8SL2OSC_DLTST_SHIFT             (14U)
36163 /*! DLTST - Delay Line Test Start
36164  */
36165 #define DDRPHY_DX8SL2OSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_DLTST_SHIFT)) & DDRPHY_DX8SL2OSC_DLTST_MASK)
36166 #define DDRPHY_DX8SL2OSC_PHYFRST_MASK            (0x8000U)
36167 #define DDRPHY_DX8SL2OSC_PHYFRST_SHIFT           (15U)
36168 /*! PHYFRST - PHY FIFO Reset
36169  */
36170 #define DDRPHY_DX8SL2OSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL2OSC_PHYFRST_MASK)
36171 #define DDRPHY_DX8SL2OSC_PHYHRST_MASK            (0x10000U)
36172 #define DDRPHY_DX8SL2OSC_PHYHRST_SHIFT           (16U)
36173 /*! PHYHRST - PHY High-Speed Reset
36174  */
36175 #define DDRPHY_DX8SL2OSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL2OSC_PHYHRST_MASK)
36176 #define DDRPHY_DX8SL2OSC_LBDQSS_MASK             (0x20000U)
36177 #define DDRPHY_DX8SL2OSC_LBDQSS_SHIFT            (17U)
36178 /*! LBDQSS - Loopback DQS Shift
36179  */
36180 #define DDRPHY_DX8SL2OSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL2OSC_LBDQSS_MASK)
36181 #define DDRPHY_DX8SL2OSC_LBGDQS_MASK             (0xC0000U)
36182 #define DDRPHY_DX8SL2OSC_LBGDQS_SHIFT            (18U)
36183 /*! LBGDQS - Loopback DQS Gating
36184  */
36185 #define DDRPHY_DX8SL2OSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL2OSC_LBGDQS_MASK)
36186 #define DDRPHY_DX8SL2OSC_LBGSDQS_MASK            (0x100000U)
36187 #define DDRPHY_DX8SL2OSC_LBGSDQS_SHIFT           (20U)
36188 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
36189  */
36190 #define DDRPHY_DX8SL2OSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL2OSC_LBGSDQS_MASK)
36191 #define DDRPHY_DX8SL2OSC_LBMODE_MASK             (0x200000U)
36192 #define DDRPHY_DX8SL2OSC_LBMODE_SHIFT            (21U)
36193 /*! LBMODE - Loopback Mode
36194  */
36195 #define DDRPHY_DX8SL2OSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL2OSC_LBMODE_MASK)
36196 #define DDRPHY_DX8SL2OSC_CLKLEVEL_MASK           (0xC00000U)
36197 #define DDRPHY_DX8SL2OSC_CLKLEVEL_SHIFT          (22U)
36198 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
36199  */
36200 #define DDRPHY_DX8SL2OSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL2OSC_CLKLEVEL_MASK)
36201 #define DDRPHY_DX8SL2OSC_GATEDXCTLCLK_MASK       (0x3000000U)
36202 #define DDRPHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT      (24U)
36203 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
36204  */
36205 #define DDRPHY_DX8SL2OSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL2OSC_GATEDXCTLCLK_MASK)
36206 #define DDRPHY_DX8SL2OSC_GATEDXDDRCLK_MASK       (0xC000000U)
36207 #define DDRPHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT      (26U)
36208 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
36209  */
36210 #define DDRPHY_DX8SL2OSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL2OSC_GATEDXDDRCLK_MASK)
36211 #define DDRPHY_DX8SL2OSC_GATEDXRDCLK_MASK        (0x30000000U)
36212 #define DDRPHY_DX8SL2OSC_GATEDXRDCLK_SHIFT       (28U)
36213 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
36214  */
36215 #define DDRPHY_DX8SL2OSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL2OSC_GATEDXRDCLK_MASK)
36216 #define DDRPHY_DX8SL2OSC_RESERVED_31_30_MASK     (0xC0000000U)
36217 #define DDRPHY_DX8SL2OSC_RESERVED_31_30_SHIFT    (30U)
36218 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
36219  */
36220 #define DDRPHY_DX8SL2OSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL2OSC_RESERVED_31_30_MASK)
36221 /*! @} */
36222 
36223 /*! @name DX8SL2PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
36224 /*! @{ */
36225 #define DDRPHY_DX8SL2PLLCR0_DTC_MASK             (0xFU)
36226 #define DDRPHY_DX8SL2PLLCR0_DTC_SHIFT            (0U)
36227 /*! DTC - Digital Test Control
36228  */
36229 #define DDRPHY_DX8SL2PLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_DTC_MASK)
36230 #define DDRPHY_DX8SL2PLLCR0_ATC_MASK             (0xF0U)
36231 #define DDRPHY_DX8SL2PLLCR0_ATC_SHIFT            (4U)
36232 /*! ATC - Analog Test Control
36233  */
36234 #define DDRPHY_DX8SL2PLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_ATC_MASK)
36235 #define DDRPHY_DX8SL2PLLCR0_ATOEN_MASK           (0x100U)
36236 #define DDRPHY_DX8SL2PLLCR0_ATOEN_SHIFT          (8U)
36237 /*! ATOEN - Analog Test Enable (ATOEN)
36238  */
36239 #define DDRPHY_DX8SL2PLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL2PLLCR0_ATOEN_MASK)
36240 #define DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_MASK   (0xE00U)
36241 #define DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT  (9U)
36242 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
36243  */
36244 #define DDRPHY_DX8SL2PLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_MASK)
36245 #define DDRPHY_DX8SL2PLLCR0_GSHIFT_MASK          (0x1000U)
36246 #define DDRPHY_DX8SL2PLLCR0_GSHIFT_SHIFT         (12U)
36247 /*! GSHIFT - Gear Shift
36248  */
36249 #define DDRPHY_DX8SL2PLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL2PLLCR0_GSHIFT_MASK)
36250 #define DDRPHY_DX8SL2PLLCR0_CPIC_MASK            (0x1E000U)
36251 #define DDRPHY_DX8SL2PLLCR0_CPIC_SHIFT           (13U)
36252 /*! CPIC - Charge Pump Integrating Current Control
36253  */
36254 #define DDRPHY_DX8SL2PLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_CPIC_MASK)
36255 #define DDRPHY_DX8SL2PLLCR0_CPPC_MASK            (0x7E0000U)
36256 #define DDRPHY_DX8SL2PLLCR0_CPPC_SHIFT           (17U)
36257 /*! CPPC - Charge Pump Proportional Current Control
36258  */
36259 #define DDRPHY_DX8SL2PLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_CPPC_MASK)
36260 #define DDRPHY_DX8SL2PLLCR0_RLOCKM_MASK          (0x800000U)
36261 #define DDRPHY_DX8SL2PLLCR0_RLOCKM_SHIFT         (23U)
36262 /*! RLOCKM - Relock Mode
36263  */
36264 #define DDRPHY_DX8SL2PLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL2PLLCR0_RLOCKM_MASK)
36265 #define DDRPHY_DX8SL2PLLCR0_FRQSEL_MASK          (0xF000000U)
36266 #define DDRPHY_DX8SL2PLLCR0_FRQSEL_SHIFT         (24U)
36267 /*! FRQSEL - PLL Frequency Select
36268  */
36269 #define DDRPHY_DX8SL2PLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL2PLLCR0_FRQSEL_MASK)
36270 #define DDRPHY_DX8SL2PLLCR0_RSTOPM_MASK          (0x10000000U)
36271 #define DDRPHY_DX8SL2PLLCR0_RSTOPM_SHIFT         (28U)
36272 /*! RSTOPM - Reference Stop Mode
36273  */
36274 #define DDRPHY_DX8SL2PLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL2PLLCR0_RSTOPM_MASK)
36275 #define DDRPHY_DX8SL2PLLCR0_PLLPD_MASK           (0x20000000U)
36276 #define DDRPHY_DX8SL2PLLCR0_PLLPD_SHIFT          (29U)
36277 /*! PLLPD - PLL Power Down
36278  */
36279 #define DDRPHY_DX8SL2PLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL2PLLCR0_PLLPD_MASK)
36280 #define DDRPHY_DX8SL2PLLCR0_PLLRST_MASK          (0x40000000U)
36281 #define DDRPHY_DX8SL2PLLCR0_PLLRST_SHIFT         (30U)
36282 /*! PLLRST - PLL Reset
36283  */
36284 #define DDRPHY_DX8SL2PLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL2PLLCR0_PLLRST_MASK)
36285 #define DDRPHY_DX8SL2PLLCR0_PLLBYP_MASK          (0x80000000U)
36286 #define DDRPHY_DX8SL2PLLCR0_PLLBYP_SHIFT         (31U)
36287 /*! PLLBYP - PLL Bypass
36288  */
36289 #define DDRPHY_DX8SL2PLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL2PLLCR0_PLLBYP_MASK)
36290 /*! @} */
36291 
36292 /*! @name DX8SL2PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
36293 /*! @{ */
36294 #define DDRPHY_DX8SL2PLLCR1_LOCKDS_MASK          (0x1U)
36295 #define DDRPHY_DX8SL2PLLCR1_LOCKDS_SHIFT         (0U)
36296 /*! LOCKDS - Lock Detector Select
36297  */
36298 #define DDRPHY_DX8SL2PLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL2PLLCR1_LOCKDS_MASK)
36299 #define DDRPHY_DX8SL2PLLCR1_LOCKCS_MASK          (0x2U)
36300 #define DDRPHY_DX8SL2PLLCR1_LOCKCS_SHIFT         (1U)
36301 /*! LOCKCS - Lock Detector Counter Select
36302  */
36303 #define DDRPHY_DX8SL2PLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL2PLLCR1_LOCKCS_MASK)
36304 #define DDRPHY_DX8SL2PLLCR1_LOCKPS_MASK          (0x4U)
36305 #define DDRPHY_DX8SL2PLLCR1_LOCKPS_SHIFT         (2U)
36306 /*! LOCKPS - Lock Detector Phase Select
36307  */
36308 #define DDRPHY_DX8SL2PLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL2PLLCR1_LOCKPS_MASK)
36309 #define DDRPHY_DX8SL2PLLCR1_BYPVDD_MASK          (0x8U)
36310 #define DDRPHY_DX8SL2PLLCR1_BYPVDD_SHIFT         (3U)
36311 /*! BYPVDD - PLL VDD voltage level control
36312  */
36313 #define DDRPHY_DX8SL2PLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL2PLLCR1_BYPVDD_MASK)
36314 #define DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_MASK      (0x10U)
36315 #define DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_SHIFT     (4U)
36316 /*! BYPVREGDIG - Bypass PLL vreg_dig
36317  */
36318 #define DDRPHY_DX8SL2PLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_MASK)
36319 #define DDRPHY_DX8SL2PLLCR1_BYPVREGCP_MASK       (0x20U)
36320 #define DDRPHY_DX8SL2PLLCR1_BYPVREGCP_SHIFT      (5U)
36321 /*! BYPVREGCP - Bypass PLL vreg_cp
36322  */
36323 #define DDRPHY_DX8SL2PLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL2PLLCR1_BYPVREGCP_MASK)
36324 #define DDRPHY_DX8SL2PLLCR1_PLLPROG_MASK         (0x3FFFC0U)
36325 #define DDRPHY_DX8SL2PLLCR1_PLLPROG_SHIFT        (6U)
36326 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
36327  */
36328 #define DDRPHY_DX8SL2PLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL2PLLCR1_PLLPROG_MASK)
36329 #define DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
36330 #define DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_SHIFT (22U)
36331 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
36332  */
36333 #define DDRPHY_DX8SL2PLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_MASK)
36334 /*! @} */
36335 
36336 /*! @name DX8SL2PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
36337 /*! @{ */
36338 #define DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
36339 #define DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_SHIFT   (0U)
36340 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
36341  */
36342 #define DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_MASK)
36343 /*! @} */
36344 
36345 /*! @name DX8SL2PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
36346 /*! @{ */
36347 #define DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
36348 #define DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_SHIFT  (0U)
36349 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
36350  */
36351 #define DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_MASK)
36352 /*! @} */
36353 
36354 /*! @name DX8SL2PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
36355 /*! @{ */
36356 #define DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
36357 #define DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_SHIFT  (0U)
36358 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
36359  */
36360 #define DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_MASK)
36361 /*! @} */
36362 
36363 /*! @name DX8SL2PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
36364 /*! @{ */
36365 #define DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
36366 #define DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_SHIFT (0U)
36367 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
36368  */
36369 #define DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_MASK)
36370 #define DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
36371 #define DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_SHIFT  (8U)
36372 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
36373  */
36374 #define DDRPHY_DX8SL2PLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_MASK)
36375 /*! @} */
36376 
36377 /*! @name DX8SL2DQSCTL - DATX8 0-1 DQS Control Register */
36378 /*! @{ */
36379 #define DDRPHY_DX8SL2DQSCTL_DQSRES_MASK          (0xFU)
36380 #define DDRPHY_DX8SL2DQSCTL_DQSRES_SHIFT         (0U)
36381 /*! DQSRES - DQS Resistor
36382  */
36383 #define DDRPHY_DX8SL2DQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DQSRES_MASK)
36384 #define DDRPHY_DX8SL2DQSCTL_DQSNRES_MASK         (0xF0U)
36385 #define DDRPHY_DX8SL2DQSCTL_DQSNRES_SHIFT        (4U)
36386 /*! DQSNRES - DQS_N Resistor
36387  */
36388 #define DDRPHY_DX8SL2DQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DQSNRES_MASK)
36389 #define DDRPHY_DX8SL2DQSCTL_DXSR_MASK            (0x300U)
36390 #define DDRPHY_DX8SL2DQSCTL_DXSR_SHIFT           (8U)
36391 /*! DXSR - Data Slew Rate
36392  */
36393 #define DDRPHY_DX8SL2DQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DXSR_MASK)
36394 #define DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_MASK  (0x1C00U)
36395 #define DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT (10U)
36396 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
36397  */
36398 #define DDRPHY_DX8SL2DQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_MASK)
36399 #define DDRPHY_DX8SL2DQSCTL_UDQIOM_MASK          (0x2000U)
36400 #define DDRPHY_DX8SL2DQSCTL_UDQIOM_SHIFT         (13U)
36401 /*! UDQIOM - Unused DQ I/O Mode
36402  */
36403 #define DDRPHY_DX8SL2DQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL2DQSCTL_UDQIOM_MASK)
36404 #define DDRPHY_DX8SL2DQSCTL_QSCNTEN_MASK         (0x4000U)
36405 #define DDRPHY_DX8SL2DQSCTL_QSCNTEN_SHIFT        (14U)
36406 /*! QSCNTEN - QS Counter Enable
36407  */
36408 #define DDRPHY_DX8SL2DQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL2DQSCTL_QSCNTEN_MASK)
36409 #define DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_MASK  (0x18000U)
36410 #define DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT (15U)
36411 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
36412  */
36413 #define DDRPHY_DX8SL2DQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_MASK)
36414 #define DDRPHY_DX8SL2DQSCTL_LPIOPD_MASK          (0x20000U)
36415 #define DDRPHY_DX8SL2DQSCTL_LPIOPD_SHIFT         (17U)
36416 /*! LPIOPD - Low Power I/O Power Down
36417  */
36418 #define DDRPHY_DX8SL2DQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL2DQSCTL_LPIOPD_MASK)
36419 #define DDRPHY_DX8SL2DQSCTL_LPPLLPD_MASK         (0x40000U)
36420 #define DDRPHY_DX8SL2DQSCTL_LPPLLPD_SHIFT        (18U)
36421 /*! LPPLLPD - Low Power PLL Power Down
36422  */
36423 #define DDRPHY_DX8SL2DQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL2DQSCTL_LPPLLPD_MASK)
36424 #define DDRPHY_DX8SL2DQSCTL_DQSGX_MASK           (0x180000U)
36425 #define DDRPHY_DX8SL2DQSCTL_DQSGX_SHIFT          (19U)
36426 /*! DQSGX - DQS Gate Extension
36427  */
36428 #define DDRPHY_DX8SL2DQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DQSGX_MASK)
36429 #define DDRPHY_DX8SL2DQSCTL_WRRMODE_MASK         (0x200000U)
36430 #define DDRPHY_DX8SL2DQSCTL_WRRMODE_SHIFT        (21U)
36431 /*! WRRMODE - Write Path Rise-to-Rise Mode
36432  */
36433 #define DDRPHY_DX8SL2DQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL2DQSCTL_WRRMODE_MASK)
36434 #define DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_MASK  (0xC00000U)
36435 #define DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT (22U)
36436 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
36437  */
36438 #define DDRPHY_DX8SL2DQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_MASK)
36439 #define DDRPHY_DX8SL2DQSCTL_RRRMODE_MASK         (0x1000000U)
36440 #define DDRPHY_DX8SL2DQSCTL_RRRMODE_SHIFT        (24U)
36441 /*! RRRMODE - Read Path Rise-to-Rise Mode
36442  */
36443 #define DDRPHY_DX8SL2DQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RRRMODE_MASK)
36444 #define DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
36445 #define DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT (25U)
36446 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
36447  */
36448 #define DDRPHY_DX8SL2DQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_MASK)
36449 /*! @} */
36450 
36451 /*! @name DX8SL2TRNCTL - DATX8 0-1 Training Control Register */
36452 /*! @{ */
36453 #define DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
36454 #define DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_SHIFT  (0U)
36455 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
36456  */
36457 #define DDRPHY_DX8SL2TRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_MASK)
36458 /*! @} */
36459 
36460 /*! @name DX8SL2DDLCTL - DATX8 0-1 DDL Control Register */
36461 /*! @{ */
36462 #define DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_MASK      (0x3U)
36463 #define DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_SHIFT     (0U)
36464 /*! DDLBYPMODE - Controls DDL Bypass Mode
36465  */
36466 #define DDRPHY_DX8SL2DDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_MASK)
36467 #define DDRPHY_DX8SL2DDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
36468 #define DDRPHY_DX8SL2DDLCTL_DXDDLBYP_SHIFT       (2U)
36469 /*! DXDDLBYP - DATX8 DDL Bypass
36470  */
36471 #define DDRPHY_DX8SL2DDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DXDDLBYP_MASK)
36472 #define DDRPHY_DX8SL2DDLCTL_DXDDLLD_MASK         (0x7C0000U)
36473 #define DDRPHY_DX8SL2DDLCTL_DXDDLLD_SHIFT        (18U)
36474 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
36475  */
36476 #define DDRPHY_DX8SL2DDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DXDDLLD_MASK)
36477 #define DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_MASK  (0x1800000U)
36478 #define DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_SHIFT (23U)
36479 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
36480  */
36481 #define DDRPHY_DX8SL2DDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_MASK)
36482 #define DDRPHY_DX8SL2DDLCTL_DXDDLLDT_MASK        (0x2000000U)
36483 #define DDRPHY_DX8SL2DDLCTL_DXDDLLDT_SHIFT       (25U)
36484 /*! DXDDLLDT - DX DDL Load Type
36485  */
36486 #define DDRPHY_DX8SL2DDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DXDDLLDT_MASK)
36487 #define DDRPHY_DX8SL2DDLCTL_DLYLDTM_MASK         (0x4000000U)
36488 #define DDRPHY_DX8SL2DDLCTL_DLYLDTM_SHIFT        (26U)
36489 /*! DLYLDTM - Delay Load Timing
36490  */
36491 #define DDRPHY_DX8SL2DDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DLYLDTM_MASK)
36492 #define DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
36493 #define DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_SHIFT (27U)
36494 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
36495  */
36496 #define DDRPHY_DX8SL2DDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_MASK)
36497 /*! @} */
36498 
36499 /*! @name DX8SL2DXCTL1 - DATX8 0-1 DX Control Register 1 */
36500 /*! @{ */
36501 #define DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
36502 #define DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_SHIFT  (0U)
36503 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
36504  */
36505 #define DDRPHY_DX8SL2DXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_MASK)
36506 #define DDRPHY_DX8SL2DXCTL1_DXTMODE_MASK         (0x10000U)
36507 #define DDRPHY_DX8SL2DXCTL1_DXTMODE_SHIFT        (16U)
36508 /*! DXTMODE - DATX8 Test Mode
36509  */
36510 #define DDRPHY_DX8SL2DXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXTMODE_MASK)
36511 #define DDRPHY_DX8SL2DXCTL1_DXGDBYP_MASK         (0x20000U)
36512 #define DDRPHY_DX8SL2DXCTL1_DXGDBYP_SHIFT        (17U)
36513 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
36514  */
36515 #define DDRPHY_DX8SL2DXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXGDBYP_MASK)
36516 #define DDRPHY_DX8SL2DXCTL1_DXQSDBYP_MASK        (0x40000U)
36517 #define DDRPHY_DX8SL2DXCTL1_DXQSDBYP_SHIFT       (18U)
36518 /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
36519  */
36520 #define DDRPHY_DX8SL2DXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXQSDBYP_MASK)
36521 #define DDRPHY_DX8SL2DXCTL1_DXGSMD_MASK          (0x80000U)
36522 #define DDRPHY_DX8SL2DXCTL1_DXGSMD_SHIFT         (19U)
36523 /*! DXGSMD - Read DQS Gating Status Mode
36524  */
36525 #define DDRPHY_DX8SL2DXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXGSMD_MASK)
36526 #define DDRPHY_DX8SL2DXCTL1_DXDTOSEL_MASK        (0x300000U)
36527 #define DDRPHY_DX8SL2DXCTL1_DXDTOSEL_SHIFT       (20U)
36528 /*! DXDTOSEL - DATX8 Digital Test Output Select
36529  */
36530 #define DDRPHY_DX8SL2DXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXDTOSEL_MASK)
36531 #define DDRPHY_DX8SL2DXCTL1_RESERVED_22_MASK     (0x400000U)
36532 #define DDRPHY_DX8SL2DXCTL1_RESERVED_22_SHIFT    (22U)
36533 /*! RESERVED_22 - Reserved. Return zeroes on reads.
36534  */
36535 #define DDRPHY_DX8SL2DXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL2DXCTL1_RESERVED_22_MASK)
36536 #define DDRPHY_DX8SL2DXCTL1_DXRCLKMD_MASK        (0x800000U)
36537 #define DDRPHY_DX8SL2DXCTL1_DXRCLKMD_SHIFT       (23U)
36538 /*! DXRCLKMD - DATX8 Read Clock Mode
36539  */
36540 #define DDRPHY_DX8SL2DXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXRCLKMD_MASK)
36541 #define DDRPHY_DX8SL2DXCTL1_DXCALCLK_MASK        (0x1000000U)
36542 #define DDRPHY_DX8SL2DXCTL1_DXCALCLK_SHIFT       (24U)
36543 /*! DXCALCLK - DATX Calibration Clock Select
36544  */
36545 #define DDRPHY_DX8SL2DXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXCALCLK_MASK)
36546 #define DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
36547 #define DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_SHIFT (25U)
36548 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
36549  */
36550 #define DDRPHY_DX8SL2DXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_MASK)
36551 /*! @} */
36552 
36553 /*! @name DX8SL2DXCTL2 - DATX8 0-1 DX Control Register 2 */
36554 /*! @{ */
36555 #define DDRPHY_DX8SL2DXCTL2_RESERVED_0_MASK      (0x1U)
36556 #define DDRPHY_DX8SL2DXCTL2_RESERVED_0_SHIFT     (0U)
36557 /*! RESERVED_0 - Reserved. Return zeroes on reads.
36558  */
36559 #define DDRPHY_DX8SL2DXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_0_MASK)
36560 #define DDRPHY_DX8SL2DXCTL2_DQSGLB_MASK          (0x6U)
36561 #define DDRPHY_DX8SL2DXCTL2_DQSGLB_SHIFT         (1U)
36562 /*! DQSGLB - Read DQS Gate I/O Loopback
36563  */
36564 #define DDRPHY_DX8SL2DXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL2DXCTL2_DQSGLB_MASK)
36565 #define DDRPHY_DX8SL2DXCTL2_DISRST_MASK          (0x8U)
36566 #define DDRPHY_DX8SL2DXCTL2_DISRST_SHIFT         (3U)
36567 /*! DISRST - Disables the Read FIFO Reset
36568  */
36569 #define DDRPHY_DX8SL2DXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL2DXCTL2_DISRST_MASK)
36570 #define DDRPHY_DX8SL2DXCTL2_RDMODE_MASK          (0x30U)
36571 #define DDRPHY_DX8SL2DXCTL2_RDMODE_SHIFT         (4U)
36572 /*! RDMODE - DATX8 Receive FIFO Read Mode
36573  */
36574 #define DDRPHY_DX8SL2DXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RDMODE_MASK)
36575 #define DDRPHY_DX8SL2DXCTL2_PRFBYP_MASK          (0x40U)
36576 #define DDRPHY_DX8SL2DXCTL2_PRFBYP_SHIFT         (6U)
36577 /*! PRFBYP - PUB Read FIFO Bypass
36578  */
36579 #define DDRPHY_DX8SL2DXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL2DXCTL2_PRFBYP_MASK)
36580 #define DDRPHY_DX8SL2DXCTL2_WDBI_MASK            (0x80U)
36581 #define DDRPHY_DX8SL2DXCTL2_WDBI_SHIFT           (7U)
36582 /*! WDBI - Write Data Bus Inversion Enable
36583  */
36584 #define DDRPHY_DX8SL2DXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL2DXCTL2_WDBI_MASK)
36585 #define DDRPHY_DX8SL2DXCTL2_RDBI_MASK            (0x100U)
36586 #define DDRPHY_DX8SL2DXCTL2_RDBI_SHIFT           (8U)
36587 /*! RDBI - Read Data Bus Inversion Enable
36588  */
36589 #define DDRPHY_DX8SL2DXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RDBI_MASK)
36590 #define DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
36591 #define DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
36592 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
36593  */
36594 #define DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK)
36595 #define DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_MASK  (0x6000U)
36596 #define DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT (13U)
36597 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
36598  */
36599 #define DDRPHY_DX8SL2DXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_MASK)
36600 #define DDRPHY_DX8SL2DXCTL2_IOLB_MASK            (0x8000U)
36601 #define DDRPHY_DX8SL2DXCTL2_IOLB_SHIFT           (15U)
36602 /*! IOLB - I/O Loopback Select
36603  */
36604 #define DDRPHY_DX8SL2DXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL2DXCTL2_IOLB_MASK)
36605 #define DDRPHY_DX8SL2DXCTL2_IOAG_MASK            (0x10000U)
36606 #define DDRPHY_DX8SL2DXCTL2_IOAG_SHIFT           (16U)
36607 /*! IOAG - I/O Assisted Gate Select
36608  */
36609 #define DDRPHY_DX8SL2DXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL2DXCTL2_IOAG_MASK)
36610 #define DDRPHY_DX8SL2DXCTL2_RESERVED_17_MASK     (0x20000U)
36611 #define DDRPHY_DX8SL2DXCTL2_RESERVED_17_SHIFT    (17U)
36612 /*! RESERVED_17 - Reserved. Return zeroes on reads.
36613  */
36614 #define DDRPHY_DX8SL2DXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_17_MASK)
36615 #define DDRPHY_DX8SL2DXCTL2_PREOEX_MASK          (0xC0000U)
36616 #define DDRPHY_DX8SL2DXCTL2_PREOEX_SHIFT         (18U)
36617 /*! PREOEX - OE Extension during Pre-amble
36618  */
36619 #define DDRPHY_DX8SL2DXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL2DXCTL2_PREOEX_MASK)
36620 #define DDRPHY_DX8SL2DXCTL2_POSOEX_MASK          (0x700000U)
36621 #define DDRPHY_DX8SL2DXCTL2_POSOEX_SHIFT         (20U)
36622 /*! POSOEX - OX Extension during Post-amble
36623  */
36624 #define DDRPHY_DX8SL2DXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL2DXCTL2_POSOEX_MASK)
36625 #define DDRPHY_DX8SL2DXCTL2_CRDEN_MASK           (0x800000U)
36626 #define DDRPHY_DX8SL2DXCTL2_CRDEN_SHIFT          (23U)
36627 /*! CRDEN - Configurable Read Data Enable
36628  */
36629 #define DDRPHY_DX8SL2DXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL2DXCTL2_CRDEN_MASK)
36630 #define DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
36631 #define DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT (24U)
36632 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
36633  */
36634 #define DDRPHY_DX8SL2DXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_MASK)
36635 /*! @} */
36636 
36637 /*! @name DX8SL2IOCR - DATX8 0-1 I/O Configuration Register */
36638 /*! @{ */
36639 #define DDRPHY_DX8SL2IOCR_DXRXM_MASK             (0x7FFU)
36640 #define DDRPHY_DX8SL2IOCR_DXRXM_SHIFT            (0U)
36641 /*! DXRXM - DX IO Receiver Mode
36642  */
36643 #define DDRPHY_DX8SL2IOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXRXM_MASK)
36644 #define DDRPHY_DX8SL2IOCR_DXTXM_MASK             (0x3FF800U)
36645 #define DDRPHY_DX8SL2IOCR_DXTXM_SHIFT            (11U)
36646 /*! DXTXM - DX IO Transmitter Mode
36647  */
36648 #define DDRPHY_DX8SL2IOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXTXM_MASK)
36649 #define DDRPHY_DX8SL2IOCR_DXIOM_MASK             (0x1C00000U)
36650 #define DDRPHY_DX8SL2IOCR_DXIOM_SHIFT            (22U)
36651 /*! DXIOM - DX IO Mode
36652  */
36653 #define DDRPHY_DX8SL2IOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXIOM_MASK)
36654 #define DDRPHY_DX8SL2IOCR_DXVREFIOM_MASK         (0xE000000U)
36655 #define DDRPHY_DX8SL2IOCR_DXVREFIOM_SHIFT        (25U)
36656 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
36657  */
36658 #define DDRPHY_DX8SL2IOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXVREFIOM_MASK)
36659 #define DDRPHY_DX8SL2IOCR_DXDACRANGE_MASK        (0x70000000U)
36660 #define DDRPHY_DX8SL2IOCR_DXDACRANGE_SHIFT       (28U)
36661 /*! DXDACRANGE - PVREF_DAC REFSEL range select
36662  */
36663 #define DDRPHY_DX8SL2IOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL2IOCR_DXDACRANGE_MASK)
36664 #define DDRPHY_DX8SL2IOCR_RESERVED_31_MASK       (0x80000000U)
36665 #define DDRPHY_DX8SL2IOCR_RESERVED_31_SHIFT      (31U)
36666 /*! RESERVED_31 - Reserved. Return zeroes on reads.
36667  */
36668 #define DDRPHY_DX8SL2IOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL2IOCR_RESERVED_31_MASK)
36669 /*! @} */
36670 
36671 /*! @name DX4SL2IOCR - DATX4 Slice 0-1 I/O Configuration Register */
36672 /*! @{ */
36673 #define DDRPHY_DX4SL2IOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
36674 #define DDRPHY_DX4SL2IOCR_RESERVED_31_0_SHIFT    (0U)
36675 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
36676  */
36677 #define DDRPHY_DX4SL2IOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL2IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL2IOCR_RESERVED_31_0_MASK)
36678 /*! @} */
36679 
36680 /*! @name DX8SL3OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
36681 /*! @{ */
36682 #define DDRPHY_DX8SL3OSC_OSCEN_MASK              (0x1U)
36683 #define DDRPHY_DX8SL3OSC_OSCEN_SHIFT             (0U)
36684 /*! OSCEN - Oscillator Enable
36685  */
36686 #define DDRPHY_DX8SL3OSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL3OSC_OSCEN_MASK)
36687 #define DDRPHY_DX8SL3OSC_OSCDIV_MASK             (0x1EU)
36688 #define DDRPHY_DX8SL3OSC_OSCDIV_SHIFT            (1U)
36689 /*! OSCDIV - Oscillator Mode Division
36690  */
36691 #define DDRPHY_DX8SL3OSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL3OSC_OSCDIV_MASK)
36692 #define DDRPHY_DX8SL3OSC_OSCWDL_MASK             (0x60U)
36693 #define DDRPHY_DX8SL3OSC_OSCWDL_SHIFT            (5U)
36694 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
36695  */
36696 #define DDRPHY_DX8SL3OSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL3OSC_OSCWDL_MASK)
36697 #define DDRPHY_DX8SL3OSC_RESERVED_8_7_MASK       (0x180U)
36698 #define DDRPHY_DX8SL3OSC_RESERVED_8_7_SHIFT      (7U)
36699 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
36700  */
36701 #define DDRPHY_DX8SL3OSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL3OSC_RESERVED_8_7_MASK)
36702 #define DDRPHY_DX8SL3OSC_OSCWDDL_MASK            (0x600U)
36703 #define DDRPHY_DX8SL3OSC_OSCWDDL_SHIFT           (9U)
36704 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
36705  */
36706 #define DDRPHY_DX8SL3OSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL3OSC_OSCWDDL_MASK)
36707 #define DDRPHY_DX8SL3OSC_RESERVED_12_11_MASK     (0x1800U)
36708 #define DDRPHY_DX8SL3OSC_RESERVED_12_11_SHIFT    (11U)
36709 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
36710  */
36711 #define DDRPHY_DX8SL3OSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL3OSC_RESERVED_12_11_MASK)
36712 #define DDRPHY_DX8SL3OSC_DLTMODE_MASK            (0x2000U)
36713 #define DDRPHY_DX8SL3OSC_DLTMODE_SHIFT           (13U)
36714 /*! DLTMODE - Delay Line Test Mode
36715  */
36716 #define DDRPHY_DX8SL3OSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL3OSC_DLTMODE_MASK)
36717 #define DDRPHY_DX8SL3OSC_DLTST_MASK              (0x4000U)
36718 #define DDRPHY_DX8SL3OSC_DLTST_SHIFT             (14U)
36719 /*! DLTST - Delay Line Test Start
36720  */
36721 #define DDRPHY_DX8SL3OSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_DLTST_SHIFT)) & DDRPHY_DX8SL3OSC_DLTST_MASK)
36722 #define DDRPHY_DX8SL3OSC_PHYFRST_MASK            (0x8000U)
36723 #define DDRPHY_DX8SL3OSC_PHYFRST_SHIFT           (15U)
36724 /*! PHYFRST - PHY FIFO Reset
36725  */
36726 #define DDRPHY_DX8SL3OSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL3OSC_PHYFRST_MASK)
36727 #define DDRPHY_DX8SL3OSC_PHYHRST_MASK            (0x10000U)
36728 #define DDRPHY_DX8SL3OSC_PHYHRST_SHIFT           (16U)
36729 /*! PHYHRST - PHY High-Speed Reset
36730  */
36731 #define DDRPHY_DX8SL3OSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL3OSC_PHYHRST_MASK)
36732 #define DDRPHY_DX8SL3OSC_LBDQSS_MASK             (0x20000U)
36733 #define DDRPHY_DX8SL3OSC_LBDQSS_SHIFT            (17U)
36734 /*! LBDQSS - Loopback DQS Shift
36735  */
36736 #define DDRPHY_DX8SL3OSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL3OSC_LBDQSS_MASK)
36737 #define DDRPHY_DX8SL3OSC_LBGDQS_MASK             (0xC0000U)
36738 #define DDRPHY_DX8SL3OSC_LBGDQS_SHIFT            (18U)
36739 /*! LBGDQS - Loopback DQS Gating
36740  */
36741 #define DDRPHY_DX8SL3OSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL3OSC_LBGDQS_MASK)
36742 #define DDRPHY_DX8SL3OSC_LBGSDQS_MASK            (0x100000U)
36743 #define DDRPHY_DX8SL3OSC_LBGSDQS_SHIFT           (20U)
36744 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
36745  */
36746 #define DDRPHY_DX8SL3OSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL3OSC_LBGSDQS_MASK)
36747 #define DDRPHY_DX8SL3OSC_LBMODE_MASK             (0x200000U)
36748 #define DDRPHY_DX8SL3OSC_LBMODE_SHIFT            (21U)
36749 /*! LBMODE - Loopback Mode
36750  */
36751 #define DDRPHY_DX8SL3OSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL3OSC_LBMODE_MASK)
36752 #define DDRPHY_DX8SL3OSC_CLKLEVEL_MASK           (0xC00000U)
36753 #define DDRPHY_DX8SL3OSC_CLKLEVEL_SHIFT          (22U)
36754 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
36755  */
36756 #define DDRPHY_DX8SL3OSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL3OSC_CLKLEVEL_MASK)
36757 #define DDRPHY_DX8SL3OSC_GATEDXCTLCLK_MASK       (0x3000000U)
36758 #define DDRPHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT      (24U)
36759 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
36760  */
36761 #define DDRPHY_DX8SL3OSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL3OSC_GATEDXCTLCLK_MASK)
36762 #define DDRPHY_DX8SL3OSC_GATEDXDDRCLK_MASK       (0xC000000U)
36763 #define DDRPHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT      (26U)
36764 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
36765  */
36766 #define DDRPHY_DX8SL3OSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL3OSC_GATEDXDDRCLK_MASK)
36767 #define DDRPHY_DX8SL3OSC_GATEDXRDCLK_MASK        (0x30000000U)
36768 #define DDRPHY_DX8SL3OSC_GATEDXRDCLK_SHIFT       (28U)
36769 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
36770  */
36771 #define DDRPHY_DX8SL3OSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL3OSC_GATEDXRDCLK_MASK)
36772 #define DDRPHY_DX8SL3OSC_RESERVED_31_30_MASK     (0xC0000000U)
36773 #define DDRPHY_DX8SL3OSC_RESERVED_31_30_SHIFT    (30U)
36774 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
36775  */
36776 #define DDRPHY_DX8SL3OSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL3OSC_RESERVED_31_30_MASK)
36777 /*! @} */
36778 
36779 /*! @name DX8SL3PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
36780 /*! @{ */
36781 #define DDRPHY_DX8SL3PLLCR0_DTC_MASK             (0xFU)
36782 #define DDRPHY_DX8SL3PLLCR0_DTC_SHIFT            (0U)
36783 /*! DTC - Digital Test Control
36784  */
36785 #define DDRPHY_DX8SL3PLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_DTC_MASK)
36786 #define DDRPHY_DX8SL3PLLCR0_ATC_MASK             (0xF0U)
36787 #define DDRPHY_DX8SL3PLLCR0_ATC_SHIFT            (4U)
36788 /*! ATC - Analog Test Control
36789  */
36790 #define DDRPHY_DX8SL3PLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_ATC_MASK)
36791 #define DDRPHY_DX8SL3PLLCR0_ATOEN_MASK           (0x100U)
36792 #define DDRPHY_DX8SL3PLLCR0_ATOEN_SHIFT          (8U)
36793 /*! ATOEN - Analog Test Enable (ATOEN)
36794  */
36795 #define DDRPHY_DX8SL3PLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL3PLLCR0_ATOEN_MASK)
36796 #define DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_MASK   (0xE00U)
36797 #define DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT  (9U)
36798 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
36799  */
36800 #define DDRPHY_DX8SL3PLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_MASK)
36801 #define DDRPHY_DX8SL3PLLCR0_GSHIFT_MASK          (0x1000U)
36802 #define DDRPHY_DX8SL3PLLCR0_GSHIFT_SHIFT         (12U)
36803 /*! GSHIFT - Gear Shift
36804  */
36805 #define DDRPHY_DX8SL3PLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL3PLLCR0_GSHIFT_MASK)
36806 #define DDRPHY_DX8SL3PLLCR0_CPIC_MASK            (0x1E000U)
36807 #define DDRPHY_DX8SL3PLLCR0_CPIC_SHIFT           (13U)
36808 /*! CPIC - Charge Pump Integrating Current Control
36809  */
36810 #define DDRPHY_DX8SL3PLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_CPIC_MASK)
36811 #define DDRPHY_DX8SL3PLLCR0_CPPC_MASK            (0x7E0000U)
36812 #define DDRPHY_DX8SL3PLLCR0_CPPC_SHIFT           (17U)
36813 /*! CPPC - Charge Pump Proportional Current Control
36814  */
36815 #define DDRPHY_DX8SL3PLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_CPPC_MASK)
36816 #define DDRPHY_DX8SL3PLLCR0_RLOCKM_MASK          (0x800000U)
36817 #define DDRPHY_DX8SL3PLLCR0_RLOCKM_SHIFT         (23U)
36818 /*! RLOCKM - Relock Mode
36819  */
36820 #define DDRPHY_DX8SL3PLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL3PLLCR0_RLOCKM_MASK)
36821 #define DDRPHY_DX8SL3PLLCR0_FRQSEL_MASK          (0xF000000U)
36822 #define DDRPHY_DX8SL3PLLCR0_FRQSEL_SHIFT         (24U)
36823 /*! FRQSEL - PLL Frequency Select
36824  */
36825 #define DDRPHY_DX8SL3PLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL3PLLCR0_FRQSEL_MASK)
36826 #define DDRPHY_DX8SL3PLLCR0_RSTOPM_MASK          (0x10000000U)
36827 #define DDRPHY_DX8SL3PLLCR0_RSTOPM_SHIFT         (28U)
36828 /*! RSTOPM - Reference Stop Mode
36829  */
36830 #define DDRPHY_DX8SL3PLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL3PLLCR0_RSTOPM_MASK)
36831 #define DDRPHY_DX8SL3PLLCR0_PLLPD_MASK           (0x20000000U)
36832 #define DDRPHY_DX8SL3PLLCR0_PLLPD_SHIFT          (29U)
36833 /*! PLLPD - PLL Power Down
36834  */
36835 #define DDRPHY_DX8SL3PLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL3PLLCR0_PLLPD_MASK)
36836 #define DDRPHY_DX8SL3PLLCR0_PLLRST_MASK          (0x40000000U)
36837 #define DDRPHY_DX8SL3PLLCR0_PLLRST_SHIFT         (30U)
36838 /*! PLLRST - PLL Reset
36839  */
36840 #define DDRPHY_DX8SL3PLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL3PLLCR0_PLLRST_MASK)
36841 #define DDRPHY_DX8SL3PLLCR0_PLLBYP_MASK          (0x80000000U)
36842 #define DDRPHY_DX8SL3PLLCR0_PLLBYP_SHIFT         (31U)
36843 /*! PLLBYP - PLL Bypass
36844  */
36845 #define DDRPHY_DX8SL3PLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL3PLLCR0_PLLBYP_MASK)
36846 /*! @} */
36847 
36848 /*! @name DX8SL3PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
36849 /*! @{ */
36850 #define DDRPHY_DX8SL3PLLCR1_LOCKDS_MASK          (0x1U)
36851 #define DDRPHY_DX8SL3PLLCR1_LOCKDS_SHIFT         (0U)
36852 /*! LOCKDS - Lock Detector Select
36853  */
36854 #define DDRPHY_DX8SL3PLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL3PLLCR1_LOCKDS_MASK)
36855 #define DDRPHY_DX8SL3PLLCR1_LOCKCS_MASK          (0x2U)
36856 #define DDRPHY_DX8SL3PLLCR1_LOCKCS_SHIFT         (1U)
36857 /*! LOCKCS - Lock Detector Counter Select
36858  */
36859 #define DDRPHY_DX8SL3PLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL3PLLCR1_LOCKCS_MASK)
36860 #define DDRPHY_DX8SL3PLLCR1_LOCKPS_MASK          (0x4U)
36861 #define DDRPHY_DX8SL3PLLCR1_LOCKPS_SHIFT         (2U)
36862 /*! LOCKPS - Lock Detector Phase Select
36863  */
36864 #define DDRPHY_DX8SL3PLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL3PLLCR1_LOCKPS_MASK)
36865 #define DDRPHY_DX8SL3PLLCR1_BYPVDD_MASK          (0x8U)
36866 #define DDRPHY_DX8SL3PLLCR1_BYPVDD_SHIFT         (3U)
36867 /*! BYPVDD - PLL VDD voltage level control
36868  */
36869 #define DDRPHY_DX8SL3PLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL3PLLCR1_BYPVDD_MASK)
36870 #define DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_MASK      (0x10U)
36871 #define DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_SHIFT     (4U)
36872 /*! BYPVREGDIG - Bypass PLL vreg_dig
36873  */
36874 #define DDRPHY_DX8SL3PLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_MASK)
36875 #define DDRPHY_DX8SL3PLLCR1_BYPVREGCP_MASK       (0x20U)
36876 #define DDRPHY_DX8SL3PLLCR1_BYPVREGCP_SHIFT      (5U)
36877 /*! BYPVREGCP - Bypass PLL vreg_cp
36878  */
36879 #define DDRPHY_DX8SL3PLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL3PLLCR1_BYPVREGCP_MASK)
36880 #define DDRPHY_DX8SL3PLLCR1_PLLPROG_MASK         (0x3FFFC0U)
36881 #define DDRPHY_DX8SL3PLLCR1_PLLPROG_SHIFT        (6U)
36882 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
36883  */
36884 #define DDRPHY_DX8SL3PLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL3PLLCR1_PLLPROG_MASK)
36885 #define DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
36886 #define DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_SHIFT (22U)
36887 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
36888  */
36889 #define DDRPHY_DX8SL3PLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_MASK)
36890 /*! @} */
36891 
36892 /*! @name DX8SL3PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
36893 /*! @{ */
36894 #define DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
36895 #define DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_SHIFT   (0U)
36896 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
36897  */
36898 #define DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_MASK)
36899 /*! @} */
36900 
36901 /*! @name DX8SL3PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
36902 /*! @{ */
36903 #define DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
36904 #define DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_SHIFT  (0U)
36905 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
36906  */
36907 #define DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_MASK)
36908 /*! @} */
36909 
36910 /*! @name DX8SL3PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
36911 /*! @{ */
36912 #define DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
36913 #define DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_SHIFT  (0U)
36914 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
36915  */
36916 #define DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_MASK)
36917 /*! @} */
36918 
36919 /*! @name DX8SL3PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
36920 /*! @{ */
36921 #define DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
36922 #define DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_SHIFT (0U)
36923 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
36924  */
36925 #define DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_MASK)
36926 #define DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
36927 #define DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_SHIFT  (8U)
36928 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
36929  */
36930 #define DDRPHY_DX8SL3PLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_MASK)
36931 /*! @} */
36932 
36933 /*! @name DX8SL3DQSCTL - DATX8 0-1 DQS Control Register */
36934 /*! @{ */
36935 #define DDRPHY_DX8SL3DQSCTL_DQSRES_MASK          (0xFU)
36936 #define DDRPHY_DX8SL3DQSCTL_DQSRES_SHIFT         (0U)
36937 /*! DQSRES - DQS Resistor
36938  */
36939 #define DDRPHY_DX8SL3DQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DQSRES_MASK)
36940 #define DDRPHY_DX8SL3DQSCTL_DQSNRES_MASK         (0xF0U)
36941 #define DDRPHY_DX8SL3DQSCTL_DQSNRES_SHIFT        (4U)
36942 /*! DQSNRES - DQS_N Resistor
36943  */
36944 #define DDRPHY_DX8SL3DQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DQSNRES_MASK)
36945 #define DDRPHY_DX8SL3DQSCTL_DXSR_MASK            (0x300U)
36946 #define DDRPHY_DX8SL3DQSCTL_DXSR_SHIFT           (8U)
36947 /*! DXSR - Data Slew Rate
36948  */
36949 #define DDRPHY_DX8SL3DQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DXSR_MASK)
36950 #define DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_MASK  (0x1C00U)
36951 #define DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT (10U)
36952 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
36953  */
36954 #define DDRPHY_DX8SL3DQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_MASK)
36955 #define DDRPHY_DX8SL3DQSCTL_UDQIOM_MASK          (0x2000U)
36956 #define DDRPHY_DX8SL3DQSCTL_UDQIOM_SHIFT         (13U)
36957 /*! UDQIOM - Unused DQ I/O Mode
36958  */
36959 #define DDRPHY_DX8SL3DQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL3DQSCTL_UDQIOM_MASK)
36960 #define DDRPHY_DX8SL3DQSCTL_QSCNTEN_MASK         (0x4000U)
36961 #define DDRPHY_DX8SL3DQSCTL_QSCNTEN_SHIFT        (14U)
36962 /*! QSCNTEN - QS Counter Enable
36963  */
36964 #define DDRPHY_DX8SL3DQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL3DQSCTL_QSCNTEN_MASK)
36965 #define DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_MASK  (0x18000U)
36966 #define DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT (15U)
36967 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
36968  */
36969 #define DDRPHY_DX8SL3DQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_MASK)
36970 #define DDRPHY_DX8SL3DQSCTL_LPIOPD_MASK          (0x20000U)
36971 #define DDRPHY_DX8SL3DQSCTL_LPIOPD_SHIFT         (17U)
36972 /*! LPIOPD - Low Power I/O Power Down
36973  */
36974 #define DDRPHY_DX8SL3DQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL3DQSCTL_LPIOPD_MASK)
36975 #define DDRPHY_DX8SL3DQSCTL_LPPLLPD_MASK         (0x40000U)
36976 #define DDRPHY_DX8SL3DQSCTL_LPPLLPD_SHIFT        (18U)
36977 /*! LPPLLPD - Low Power PLL Power Down
36978  */
36979 #define DDRPHY_DX8SL3DQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL3DQSCTL_LPPLLPD_MASK)
36980 #define DDRPHY_DX8SL3DQSCTL_DQSGX_MASK           (0x180000U)
36981 #define DDRPHY_DX8SL3DQSCTL_DQSGX_SHIFT          (19U)
36982 /*! DQSGX - DQS Gate Extension
36983  */
36984 #define DDRPHY_DX8SL3DQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DQSGX_MASK)
36985 #define DDRPHY_DX8SL3DQSCTL_WRRMODE_MASK         (0x200000U)
36986 #define DDRPHY_DX8SL3DQSCTL_WRRMODE_SHIFT        (21U)
36987 /*! WRRMODE - Write Path Rise-to-Rise Mode
36988  */
36989 #define DDRPHY_DX8SL3DQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL3DQSCTL_WRRMODE_MASK)
36990 #define DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_MASK  (0xC00000U)
36991 #define DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT (22U)
36992 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
36993  */
36994 #define DDRPHY_DX8SL3DQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_MASK)
36995 #define DDRPHY_DX8SL3DQSCTL_RRRMODE_MASK         (0x1000000U)
36996 #define DDRPHY_DX8SL3DQSCTL_RRRMODE_SHIFT        (24U)
36997 /*! RRRMODE - Read Path Rise-to-Rise Mode
36998  */
36999 #define DDRPHY_DX8SL3DQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RRRMODE_MASK)
37000 #define DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
37001 #define DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT (25U)
37002 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
37003  */
37004 #define DDRPHY_DX8SL3DQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_MASK)
37005 /*! @} */
37006 
37007 /*! @name DX8SL3TRNCTL - DATX8 0-1 Training Control Register */
37008 /*! @{ */
37009 #define DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
37010 #define DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_SHIFT  (0U)
37011 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
37012  */
37013 #define DDRPHY_DX8SL3TRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_MASK)
37014 /*! @} */
37015 
37016 /*! @name DX8SL3DDLCTL - DATX8 0-1 DDL Control Register */
37017 /*! @{ */
37018 #define DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_MASK      (0x3U)
37019 #define DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_SHIFT     (0U)
37020 /*! DDLBYPMODE - Controls DDL Bypass Mode
37021  */
37022 #define DDRPHY_DX8SL3DDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_MASK)
37023 #define DDRPHY_DX8SL3DDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
37024 #define DDRPHY_DX8SL3DDLCTL_DXDDLBYP_SHIFT       (2U)
37025 /*! DXDDLBYP - DATX8 DDL Bypass
37026  */
37027 #define DDRPHY_DX8SL3DDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DXDDLBYP_MASK)
37028 #define DDRPHY_DX8SL3DDLCTL_DXDDLLD_MASK         (0x7C0000U)
37029 #define DDRPHY_DX8SL3DDLCTL_DXDDLLD_SHIFT        (18U)
37030 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
37031  */
37032 #define DDRPHY_DX8SL3DDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DXDDLLD_MASK)
37033 #define DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_MASK  (0x1800000U)
37034 #define DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_SHIFT (23U)
37035 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
37036  */
37037 #define DDRPHY_DX8SL3DDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_MASK)
37038 #define DDRPHY_DX8SL3DDLCTL_DXDDLLDT_MASK        (0x2000000U)
37039 #define DDRPHY_DX8SL3DDLCTL_DXDDLLDT_SHIFT       (25U)
37040 /*! DXDDLLDT - DX DDL Load Type
37041  */
37042 #define DDRPHY_DX8SL3DDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DXDDLLDT_MASK)
37043 #define DDRPHY_DX8SL3DDLCTL_DLYLDTM_MASK         (0x4000000U)
37044 #define DDRPHY_DX8SL3DDLCTL_DLYLDTM_SHIFT        (26U)
37045 /*! DLYLDTM - Delay Load Timing
37046  */
37047 #define DDRPHY_DX8SL3DDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DLYLDTM_MASK)
37048 #define DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
37049 #define DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_SHIFT (27U)
37050 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
37051  */
37052 #define DDRPHY_DX8SL3DDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_MASK)
37053 /*! @} */
37054 
37055 /*! @name DX8SL3DXCTL1 - DATX8 0-1 DX Control Register 1 */
37056 /*! @{ */
37057 #define DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
37058 #define DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_SHIFT  (0U)
37059 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
37060  */
37061 #define DDRPHY_DX8SL3DXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_MASK)
37062 #define DDRPHY_DX8SL3DXCTL1_DXTMODE_MASK         (0x10000U)
37063 #define DDRPHY_DX8SL3DXCTL1_DXTMODE_SHIFT        (16U)
37064 /*! DXTMODE - DATX8 Test Mode
37065  */
37066 #define DDRPHY_DX8SL3DXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXTMODE_MASK)
37067 #define DDRPHY_DX8SL3DXCTL1_DXGDBYP_MASK         (0x20000U)
37068 #define DDRPHY_DX8SL3DXCTL1_DXGDBYP_SHIFT        (17U)
37069 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
37070  */
37071 #define DDRPHY_DX8SL3DXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXGDBYP_MASK)
37072 #define DDRPHY_DX8SL3DXCTL1_DXQSDBYP_MASK        (0x40000U)
37073 #define DDRPHY_DX8SL3DXCTL1_DXQSDBYP_SHIFT       (18U)
37074 /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
37075  */
37076 #define DDRPHY_DX8SL3DXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXQSDBYP_MASK)
37077 #define DDRPHY_DX8SL3DXCTL1_DXGSMD_MASK          (0x80000U)
37078 #define DDRPHY_DX8SL3DXCTL1_DXGSMD_SHIFT         (19U)
37079 /*! DXGSMD - Read DQS Gating Status Mode
37080  */
37081 #define DDRPHY_DX8SL3DXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXGSMD_MASK)
37082 #define DDRPHY_DX8SL3DXCTL1_DXDTOSEL_MASK        (0x300000U)
37083 #define DDRPHY_DX8SL3DXCTL1_DXDTOSEL_SHIFT       (20U)
37084 /*! DXDTOSEL - DATX8 Digital Test Output Select
37085  */
37086 #define DDRPHY_DX8SL3DXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXDTOSEL_MASK)
37087 #define DDRPHY_DX8SL3DXCTL1_RESERVED_22_MASK     (0x400000U)
37088 #define DDRPHY_DX8SL3DXCTL1_RESERVED_22_SHIFT    (22U)
37089 /*! RESERVED_22 - Reserved. Return zeroes on reads.
37090  */
37091 #define DDRPHY_DX8SL3DXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL3DXCTL1_RESERVED_22_MASK)
37092 #define DDRPHY_DX8SL3DXCTL1_DXRCLKMD_MASK        (0x800000U)
37093 #define DDRPHY_DX8SL3DXCTL1_DXRCLKMD_SHIFT       (23U)
37094 /*! DXRCLKMD - DATX8 Read Clock Mode
37095  */
37096 #define DDRPHY_DX8SL3DXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXRCLKMD_MASK)
37097 #define DDRPHY_DX8SL3DXCTL1_DXCALCLK_MASK        (0x1000000U)
37098 #define DDRPHY_DX8SL3DXCTL1_DXCALCLK_SHIFT       (24U)
37099 /*! DXCALCLK - DATX Calibration Clock Select
37100  */
37101 #define DDRPHY_DX8SL3DXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXCALCLK_MASK)
37102 #define DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
37103 #define DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_SHIFT (25U)
37104 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
37105  */
37106 #define DDRPHY_DX8SL3DXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_MASK)
37107 /*! @} */
37108 
37109 /*! @name DX8SL3DXCTL2 - DATX8 0-1 DX Control Register 2 */
37110 /*! @{ */
37111 #define DDRPHY_DX8SL3DXCTL2_RESERVED_0_MASK      (0x1U)
37112 #define DDRPHY_DX8SL3DXCTL2_RESERVED_0_SHIFT     (0U)
37113 /*! RESERVED_0 - Reserved. Return zeroes on reads.
37114  */
37115 #define DDRPHY_DX8SL3DXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_0_MASK)
37116 #define DDRPHY_DX8SL3DXCTL2_DQSGLB_MASK          (0x6U)
37117 #define DDRPHY_DX8SL3DXCTL2_DQSGLB_SHIFT         (1U)
37118 /*! DQSGLB - Read DQS Gate I/O Loopback
37119  */
37120 #define DDRPHY_DX8SL3DXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL3DXCTL2_DQSGLB_MASK)
37121 #define DDRPHY_DX8SL3DXCTL2_DISRST_MASK          (0x8U)
37122 #define DDRPHY_DX8SL3DXCTL2_DISRST_SHIFT         (3U)
37123 /*! DISRST - Disables the Read FIFO Reset
37124  */
37125 #define DDRPHY_DX8SL3DXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL3DXCTL2_DISRST_MASK)
37126 #define DDRPHY_DX8SL3DXCTL2_RDMODE_MASK          (0x30U)
37127 #define DDRPHY_DX8SL3DXCTL2_RDMODE_SHIFT         (4U)
37128 /*! RDMODE - DATX8 Receive FIFO Read Mode
37129  */
37130 #define DDRPHY_DX8SL3DXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RDMODE_MASK)
37131 #define DDRPHY_DX8SL3DXCTL2_PRFBYP_MASK          (0x40U)
37132 #define DDRPHY_DX8SL3DXCTL2_PRFBYP_SHIFT         (6U)
37133 /*! PRFBYP - PUB Read FIFO Bypass
37134  */
37135 #define DDRPHY_DX8SL3DXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL3DXCTL2_PRFBYP_MASK)
37136 #define DDRPHY_DX8SL3DXCTL2_WDBI_MASK            (0x80U)
37137 #define DDRPHY_DX8SL3DXCTL2_WDBI_SHIFT           (7U)
37138 /*! WDBI - Write Data Bus Inversion Enable
37139  */
37140 #define DDRPHY_DX8SL3DXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL3DXCTL2_WDBI_MASK)
37141 #define DDRPHY_DX8SL3DXCTL2_RDBI_MASK            (0x100U)
37142 #define DDRPHY_DX8SL3DXCTL2_RDBI_SHIFT           (8U)
37143 /*! RDBI - Read Data Bus Inversion Enable
37144  */
37145 #define DDRPHY_DX8SL3DXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RDBI_MASK)
37146 #define DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
37147 #define DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
37148 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
37149  */
37150 #define DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK)
37151 #define DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_MASK  (0x6000U)
37152 #define DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT (13U)
37153 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
37154  */
37155 #define DDRPHY_DX8SL3DXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_MASK)
37156 #define DDRPHY_DX8SL3DXCTL2_IOLB_MASK            (0x8000U)
37157 #define DDRPHY_DX8SL3DXCTL2_IOLB_SHIFT           (15U)
37158 /*! IOLB - I/O Loopback Select
37159  */
37160 #define DDRPHY_DX8SL3DXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL3DXCTL2_IOLB_MASK)
37161 #define DDRPHY_DX8SL3DXCTL2_IOAG_MASK            (0x10000U)
37162 #define DDRPHY_DX8SL3DXCTL2_IOAG_SHIFT           (16U)
37163 /*! IOAG - I/O Assisted Gate Select
37164  */
37165 #define DDRPHY_DX8SL3DXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL3DXCTL2_IOAG_MASK)
37166 #define DDRPHY_DX8SL3DXCTL2_RESERVED_17_MASK     (0x20000U)
37167 #define DDRPHY_DX8SL3DXCTL2_RESERVED_17_SHIFT    (17U)
37168 /*! RESERVED_17 - Reserved. Return zeroes on reads.
37169  */
37170 #define DDRPHY_DX8SL3DXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_17_MASK)
37171 #define DDRPHY_DX8SL3DXCTL2_PREOEX_MASK          (0xC0000U)
37172 #define DDRPHY_DX8SL3DXCTL2_PREOEX_SHIFT         (18U)
37173 /*! PREOEX - OE Extension during Pre-amble
37174  */
37175 #define DDRPHY_DX8SL3DXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL3DXCTL2_PREOEX_MASK)
37176 #define DDRPHY_DX8SL3DXCTL2_POSOEX_MASK          (0x700000U)
37177 #define DDRPHY_DX8SL3DXCTL2_POSOEX_SHIFT         (20U)
37178 /*! POSOEX - OX Extension during Post-amble
37179  */
37180 #define DDRPHY_DX8SL3DXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL3DXCTL2_POSOEX_MASK)
37181 #define DDRPHY_DX8SL3DXCTL2_CRDEN_MASK           (0x800000U)
37182 #define DDRPHY_DX8SL3DXCTL2_CRDEN_SHIFT          (23U)
37183 /*! CRDEN - Configurable Read Data Enable
37184  */
37185 #define DDRPHY_DX8SL3DXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL3DXCTL2_CRDEN_MASK)
37186 #define DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
37187 #define DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT (24U)
37188 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
37189  */
37190 #define DDRPHY_DX8SL3DXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_MASK)
37191 /*! @} */
37192 
37193 /*! @name DX8SL3IOCR - DATX8 0-1 I/O Configuration Register */
37194 /*! @{ */
37195 #define DDRPHY_DX8SL3IOCR_DXRXM_MASK             (0x7FFU)
37196 #define DDRPHY_DX8SL3IOCR_DXRXM_SHIFT            (0U)
37197 /*! DXRXM - DX IO Receiver Mode
37198  */
37199 #define DDRPHY_DX8SL3IOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXRXM_MASK)
37200 #define DDRPHY_DX8SL3IOCR_DXTXM_MASK             (0x3FF800U)
37201 #define DDRPHY_DX8SL3IOCR_DXTXM_SHIFT            (11U)
37202 /*! DXTXM - DX IO Transmitter Mode
37203  */
37204 #define DDRPHY_DX8SL3IOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXTXM_MASK)
37205 #define DDRPHY_DX8SL3IOCR_DXIOM_MASK             (0x1C00000U)
37206 #define DDRPHY_DX8SL3IOCR_DXIOM_SHIFT            (22U)
37207 /*! DXIOM - DX IO Mode
37208  */
37209 #define DDRPHY_DX8SL3IOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXIOM_MASK)
37210 #define DDRPHY_DX8SL3IOCR_DXVREFIOM_MASK         (0xE000000U)
37211 #define DDRPHY_DX8SL3IOCR_DXVREFIOM_SHIFT        (25U)
37212 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
37213  */
37214 #define DDRPHY_DX8SL3IOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXVREFIOM_MASK)
37215 #define DDRPHY_DX8SL3IOCR_DXDACRANGE_MASK        (0x70000000U)
37216 #define DDRPHY_DX8SL3IOCR_DXDACRANGE_SHIFT       (28U)
37217 /*! DXDACRANGE - PVREF_DAC REFSEL range select
37218  */
37219 #define DDRPHY_DX8SL3IOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL3IOCR_DXDACRANGE_MASK)
37220 #define DDRPHY_DX8SL3IOCR_RESERVED_31_MASK       (0x80000000U)
37221 #define DDRPHY_DX8SL3IOCR_RESERVED_31_SHIFT      (31U)
37222 /*! RESERVED_31 - Reserved. Return zeroes on reads.
37223  */
37224 #define DDRPHY_DX8SL3IOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL3IOCR_RESERVED_31_MASK)
37225 /*! @} */
37226 
37227 /*! @name DX4SL3IOCR - DATX4 Slice 0-1 I/O Configuration Register */
37228 /*! @{ */
37229 #define DDRPHY_DX4SL3IOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
37230 #define DDRPHY_DX4SL3IOCR_RESERVED_31_0_SHIFT    (0U)
37231 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
37232  */
37233 #define DDRPHY_DX4SL3IOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL3IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL3IOCR_RESERVED_31_0_MASK)
37234 /*! @} */
37235 
37236 /*! @name DX8SL4OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
37237 /*! @{ */
37238 #define DDRPHY_DX8SL4OSC_OSCEN_MASK              (0x1U)
37239 #define DDRPHY_DX8SL4OSC_OSCEN_SHIFT             (0U)
37240 /*! OSCEN - Oscillator Enable
37241  */
37242 #define DDRPHY_DX8SL4OSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL4OSC_OSCEN_MASK)
37243 #define DDRPHY_DX8SL4OSC_OSCDIV_MASK             (0x1EU)
37244 #define DDRPHY_DX8SL4OSC_OSCDIV_SHIFT            (1U)
37245 /*! OSCDIV - Oscillator Mode Division
37246  */
37247 #define DDRPHY_DX8SL4OSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL4OSC_OSCDIV_MASK)
37248 #define DDRPHY_DX8SL4OSC_OSCWDL_MASK             (0x60U)
37249 #define DDRPHY_DX8SL4OSC_OSCWDL_SHIFT            (5U)
37250 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
37251  */
37252 #define DDRPHY_DX8SL4OSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL4OSC_OSCWDL_MASK)
37253 #define DDRPHY_DX8SL4OSC_RESERVED_8_7_MASK       (0x180U)
37254 #define DDRPHY_DX8SL4OSC_RESERVED_8_7_SHIFT      (7U)
37255 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
37256  */
37257 #define DDRPHY_DX8SL4OSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL4OSC_RESERVED_8_7_MASK)
37258 #define DDRPHY_DX8SL4OSC_OSCWDDL_MASK            (0x600U)
37259 #define DDRPHY_DX8SL4OSC_OSCWDDL_SHIFT           (9U)
37260 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
37261  */
37262 #define DDRPHY_DX8SL4OSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL4OSC_OSCWDDL_MASK)
37263 #define DDRPHY_DX8SL4OSC_RESERVED_12_11_MASK     (0x1800U)
37264 #define DDRPHY_DX8SL4OSC_RESERVED_12_11_SHIFT    (11U)
37265 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
37266  */
37267 #define DDRPHY_DX8SL4OSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL4OSC_RESERVED_12_11_MASK)
37268 #define DDRPHY_DX8SL4OSC_DLTMODE_MASK            (0x2000U)
37269 #define DDRPHY_DX8SL4OSC_DLTMODE_SHIFT           (13U)
37270 /*! DLTMODE - Delay Line Test Mode
37271  */
37272 #define DDRPHY_DX8SL4OSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL4OSC_DLTMODE_MASK)
37273 #define DDRPHY_DX8SL4OSC_DLTST_MASK              (0x4000U)
37274 #define DDRPHY_DX8SL4OSC_DLTST_SHIFT             (14U)
37275 /*! DLTST - Delay Line Test Start
37276  */
37277 #define DDRPHY_DX8SL4OSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_DLTST_SHIFT)) & DDRPHY_DX8SL4OSC_DLTST_MASK)
37278 #define DDRPHY_DX8SL4OSC_PHYFRST_MASK            (0x8000U)
37279 #define DDRPHY_DX8SL4OSC_PHYFRST_SHIFT           (15U)
37280 /*! PHYFRST - PHY FIFO Reset
37281  */
37282 #define DDRPHY_DX8SL4OSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL4OSC_PHYFRST_MASK)
37283 #define DDRPHY_DX8SL4OSC_PHYHRST_MASK            (0x10000U)
37284 #define DDRPHY_DX8SL4OSC_PHYHRST_SHIFT           (16U)
37285 /*! PHYHRST - PHY High-Speed Reset
37286  */
37287 #define DDRPHY_DX8SL4OSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL4OSC_PHYHRST_MASK)
37288 #define DDRPHY_DX8SL4OSC_LBDQSS_MASK             (0x20000U)
37289 #define DDRPHY_DX8SL4OSC_LBDQSS_SHIFT            (17U)
37290 /*! LBDQSS - Loopback DQS Shift
37291  */
37292 #define DDRPHY_DX8SL4OSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL4OSC_LBDQSS_MASK)
37293 #define DDRPHY_DX8SL4OSC_LBGDQS_MASK             (0xC0000U)
37294 #define DDRPHY_DX8SL4OSC_LBGDQS_SHIFT            (18U)
37295 /*! LBGDQS - Loopback DQS Gating
37296  */
37297 #define DDRPHY_DX8SL4OSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL4OSC_LBGDQS_MASK)
37298 #define DDRPHY_DX8SL4OSC_LBGSDQS_MASK            (0x100000U)
37299 #define DDRPHY_DX8SL4OSC_LBGSDQS_SHIFT           (20U)
37300 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
37301  */
37302 #define DDRPHY_DX8SL4OSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL4OSC_LBGSDQS_MASK)
37303 #define DDRPHY_DX8SL4OSC_LBMODE_MASK             (0x200000U)
37304 #define DDRPHY_DX8SL4OSC_LBMODE_SHIFT            (21U)
37305 /*! LBMODE - Loopback Mode
37306  */
37307 #define DDRPHY_DX8SL4OSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL4OSC_LBMODE_MASK)
37308 #define DDRPHY_DX8SL4OSC_CLKLEVEL_MASK           (0xC00000U)
37309 #define DDRPHY_DX8SL4OSC_CLKLEVEL_SHIFT          (22U)
37310 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
37311  */
37312 #define DDRPHY_DX8SL4OSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL4OSC_CLKLEVEL_MASK)
37313 #define DDRPHY_DX8SL4OSC_GATEDXCTLCLK_MASK       (0x3000000U)
37314 #define DDRPHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT      (24U)
37315 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
37316  */
37317 #define DDRPHY_DX8SL4OSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL4OSC_GATEDXCTLCLK_MASK)
37318 #define DDRPHY_DX8SL4OSC_GATEDXDDRCLK_MASK       (0xC000000U)
37319 #define DDRPHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT      (26U)
37320 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
37321  */
37322 #define DDRPHY_DX8SL4OSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL4OSC_GATEDXDDRCLK_MASK)
37323 #define DDRPHY_DX8SL4OSC_GATEDXRDCLK_MASK        (0x30000000U)
37324 #define DDRPHY_DX8SL4OSC_GATEDXRDCLK_SHIFT       (28U)
37325 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
37326  */
37327 #define DDRPHY_DX8SL4OSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL4OSC_GATEDXRDCLK_MASK)
37328 #define DDRPHY_DX8SL4OSC_RESERVED_31_30_MASK     (0xC0000000U)
37329 #define DDRPHY_DX8SL4OSC_RESERVED_31_30_SHIFT    (30U)
37330 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
37331  */
37332 #define DDRPHY_DX8SL4OSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL4OSC_RESERVED_31_30_MASK)
37333 /*! @} */
37334 
37335 /*! @name DX8SL4PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
37336 /*! @{ */
37337 #define DDRPHY_DX8SL4PLLCR0_DTC_MASK             (0xFU)
37338 #define DDRPHY_DX8SL4PLLCR0_DTC_SHIFT            (0U)
37339 /*! DTC - Digital Test Control
37340  */
37341 #define DDRPHY_DX8SL4PLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_DTC_MASK)
37342 #define DDRPHY_DX8SL4PLLCR0_ATC_MASK             (0xF0U)
37343 #define DDRPHY_DX8SL4PLLCR0_ATC_SHIFT            (4U)
37344 /*! ATC - Analog Test Control
37345  */
37346 #define DDRPHY_DX8SL4PLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_ATC_MASK)
37347 #define DDRPHY_DX8SL4PLLCR0_ATOEN_MASK           (0x100U)
37348 #define DDRPHY_DX8SL4PLLCR0_ATOEN_SHIFT          (8U)
37349 /*! ATOEN - Analog Test Enable (ATOEN)
37350  */
37351 #define DDRPHY_DX8SL4PLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL4PLLCR0_ATOEN_MASK)
37352 #define DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_MASK   (0xE00U)
37353 #define DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT  (9U)
37354 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
37355  */
37356 #define DDRPHY_DX8SL4PLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_MASK)
37357 #define DDRPHY_DX8SL4PLLCR0_GSHIFT_MASK          (0x1000U)
37358 #define DDRPHY_DX8SL4PLLCR0_GSHIFT_SHIFT         (12U)
37359 /*! GSHIFT - Gear Shift
37360  */
37361 #define DDRPHY_DX8SL4PLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL4PLLCR0_GSHIFT_MASK)
37362 #define DDRPHY_DX8SL4PLLCR0_CPIC_MASK            (0x1E000U)
37363 #define DDRPHY_DX8SL4PLLCR0_CPIC_SHIFT           (13U)
37364 /*! CPIC - Charge Pump Integrating Current Control
37365  */
37366 #define DDRPHY_DX8SL4PLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_CPIC_MASK)
37367 #define DDRPHY_DX8SL4PLLCR0_CPPC_MASK            (0x7E0000U)
37368 #define DDRPHY_DX8SL4PLLCR0_CPPC_SHIFT           (17U)
37369 /*! CPPC - Charge Pump Proportional Current Control
37370  */
37371 #define DDRPHY_DX8SL4PLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_CPPC_MASK)
37372 #define DDRPHY_DX8SL4PLLCR0_RLOCKM_MASK          (0x800000U)
37373 #define DDRPHY_DX8SL4PLLCR0_RLOCKM_SHIFT         (23U)
37374 /*! RLOCKM - Relock Mode
37375  */
37376 #define DDRPHY_DX8SL4PLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL4PLLCR0_RLOCKM_MASK)
37377 #define DDRPHY_DX8SL4PLLCR0_FRQSEL_MASK          (0xF000000U)
37378 #define DDRPHY_DX8SL4PLLCR0_FRQSEL_SHIFT         (24U)
37379 /*! FRQSEL - PLL Frequency Select
37380  */
37381 #define DDRPHY_DX8SL4PLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL4PLLCR0_FRQSEL_MASK)
37382 #define DDRPHY_DX8SL4PLLCR0_RSTOPM_MASK          (0x10000000U)
37383 #define DDRPHY_DX8SL4PLLCR0_RSTOPM_SHIFT         (28U)
37384 /*! RSTOPM - Reference Stop Mode
37385  */
37386 #define DDRPHY_DX8SL4PLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL4PLLCR0_RSTOPM_MASK)
37387 #define DDRPHY_DX8SL4PLLCR0_PLLPD_MASK           (0x20000000U)
37388 #define DDRPHY_DX8SL4PLLCR0_PLLPD_SHIFT          (29U)
37389 /*! PLLPD - PLL Power Down
37390  */
37391 #define DDRPHY_DX8SL4PLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL4PLLCR0_PLLPD_MASK)
37392 #define DDRPHY_DX8SL4PLLCR0_PLLRST_MASK          (0x40000000U)
37393 #define DDRPHY_DX8SL4PLLCR0_PLLRST_SHIFT         (30U)
37394 /*! PLLRST - PLL Reset
37395  */
37396 #define DDRPHY_DX8SL4PLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL4PLLCR0_PLLRST_MASK)
37397 #define DDRPHY_DX8SL4PLLCR0_PLLBYP_MASK          (0x80000000U)
37398 #define DDRPHY_DX8SL4PLLCR0_PLLBYP_SHIFT         (31U)
37399 /*! PLLBYP - PLL Bypass
37400  */
37401 #define DDRPHY_DX8SL4PLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL4PLLCR0_PLLBYP_MASK)
37402 /*! @} */
37403 
37404 /*! @name DX8SL4PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
37405 /*! @{ */
37406 #define DDRPHY_DX8SL4PLLCR1_LOCKDS_MASK          (0x1U)
37407 #define DDRPHY_DX8SL4PLLCR1_LOCKDS_SHIFT         (0U)
37408 /*! LOCKDS - Lock Detector Select
37409  */
37410 #define DDRPHY_DX8SL4PLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL4PLLCR1_LOCKDS_MASK)
37411 #define DDRPHY_DX8SL4PLLCR1_LOCKCS_MASK          (0x2U)
37412 #define DDRPHY_DX8SL4PLLCR1_LOCKCS_SHIFT         (1U)
37413 /*! LOCKCS - Lock Detector Counter Select
37414  */
37415 #define DDRPHY_DX8SL4PLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL4PLLCR1_LOCKCS_MASK)
37416 #define DDRPHY_DX8SL4PLLCR1_LOCKPS_MASK          (0x4U)
37417 #define DDRPHY_DX8SL4PLLCR1_LOCKPS_SHIFT         (2U)
37418 /*! LOCKPS - Lock Detector Phase Select
37419  */
37420 #define DDRPHY_DX8SL4PLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL4PLLCR1_LOCKPS_MASK)
37421 #define DDRPHY_DX8SL4PLLCR1_BYPVDD_MASK          (0x8U)
37422 #define DDRPHY_DX8SL4PLLCR1_BYPVDD_SHIFT         (3U)
37423 /*! BYPVDD - PLL VDD voltage level control
37424  */
37425 #define DDRPHY_DX8SL4PLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL4PLLCR1_BYPVDD_MASK)
37426 #define DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_MASK      (0x10U)
37427 #define DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_SHIFT     (4U)
37428 /*! BYPVREGDIG - Bypass PLL vreg_dig
37429  */
37430 #define DDRPHY_DX8SL4PLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_MASK)
37431 #define DDRPHY_DX8SL4PLLCR1_BYPVREGCP_MASK       (0x20U)
37432 #define DDRPHY_DX8SL4PLLCR1_BYPVREGCP_SHIFT      (5U)
37433 /*! BYPVREGCP - Bypass PLL vreg_cp
37434  */
37435 #define DDRPHY_DX8SL4PLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL4PLLCR1_BYPVREGCP_MASK)
37436 #define DDRPHY_DX8SL4PLLCR1_PLLPROG_MASK         (0x3FFFC0U)
37437 #define DDRPHY_DX8SL4PLLCR1_PLLPROG_SHIFT        (6U)
37438 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
37439  */
37440 #define DDRPHY_DX8SL4PLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL4PLLCR1_PLLPROG_MASK)
37441 #define DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
37442 #define DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_SHIFT (22U)
37443 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
37444  */
37445 #define DDRPHY_DX8SL4PLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_MASK)
37446 /*! @} */
37447 
37448 /*! @name DX8SL4PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
37449 /*! @{ */
37450 #define DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
37451 #define DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_SHIFT   (0U)
37452 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
37453  */
37454 #define DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_MASK)
37455 /*! @} */
37456 
37457 /*! @name DX8SL4PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
37458 /*! @{ */
37459 #define DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
37460 #define DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_SHIFT  (0U)
37461 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
37462  */
37463 #define DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_MASK)
37464 /*! @} */
37465 
37466 /*! @name DX8SL4PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
37467 /*! @{ */
37468 #define DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
37469 #define DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_SHIFT  (0U)
37470 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
37471  */
37472 #define DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_MASK)
37473 /*! @} */
37474 
37475 /*! @name DX8SL4PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
37476 /*! @{ */
37477 #define DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
37478 #define DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_SHIFT (0U)
37479 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
37480  */
37481 #define DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_MASK)
37482 #define DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
37483 #define DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_SHIFT  (8U)
37484 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
37485  */
37486 #define DDRPHY_DX8SL4PLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_MASK)
37487 /*! @} */
37488 
37489 /*! @name DX8SL4DQSCTL - DATX8 0-1 DQS Control Register */
37490 /*! @{ */
37491 #define DDRPHY_DX8SL4DQSCTL_DQSRES_MASK          (0xFU)
37492 #define DDRPHY_DX8SL4DQSCTL_DQSRES_SHIFT         (0U)
37493 /*! DQSRES - DQS Resistor
37494  */
37495 #define DDRPHY_DX8SL4DQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DQSRES_MASK)
37496 #define DDRPHY_DX8SL4DQSCTL_DQSNRES_MASK         (0xF0U)
37497 #define DDRPHY_DX8SL4DQSCTL_DQSNRES_SHIFT        (4U)
37498 /*! DQSNRES - DQS_N Resistor
37499  */
37500 #define DDRPHY_DX8SL4DQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DQSNRES_MASK)
37501 #define DDRPHY_DX8SL4DQSCTL_DXSR_MASK            (0x300U)
37502 #define DDRPHY_DX8SL4DQSCTL_DXSR_SHIFT           (8U)
37503 /*! DXSR - Data Slew Rate
37504  */
37505 #define DDRPHY_DX8SL4DQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DXSR_MASK)
37506 #define DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_MASK  (0x1C00U)
37507 #define DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT (10U)
37508 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
37509  */
37510 #define DDRPHY_DX8SL4DQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_MASK)
37511 #define DDRPHY_DX8SL4DQSCTL_UDQIOM_MASK          (0x2000U)
37512 #define DDRPHY_DX8SL4DQSCTL_UDQIOM_SHIFT         (13U)
37513 /*! UDQIOM - Unused DQ I/O Mode
37514  */
37515 #define DDRPHY_DX8SL4DQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL4DQSCTL_UDQIOM_MASK)
37516 #define DDRPHY_DX8SL4DQSCTL_QSCNTEN_MASK         (0x4000U)
37517 #define DDRPHY_DX8SL4DQSCTL_QSCNTEN_SHIFT        (14U)
37518 /*! QSCNTEN - QS Counter Enable
37519  */
37520 #define DDRPHY_DX8SL4DQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL4DQSCTL_QSCNTEN_MASK)
37521 #define DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_MASK  (0x18000U)
37522 #define DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT (15U)
37523 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
37524  */
37525 #define DDRPHY_DX8SL4DQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_MASK)
37526 #define DDRPHY_DX8SL4DQSCTL_LPIOPD_MASK          (0x20000U)
37527 #define DDRPHY_DX8SL4DQSCTL_LPIOPD_SHIFT         (17U)
37528 /*! LPIOPD - Low Power I/O Power Down
37529  */
37530 #define DDRPHY_DX8SL4DQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL4DQSCTL_LPIOPD_MASK)
37531 #define DDRPHY_DX8SL4DQSCTL_LPPLLPD_MASK         (0x40000U)
37532 #define DDRPHY_DX8SL4DQSCTL_LPPLLPD_SHIFT        (18U)
37533 /*! LPPLLPD - Low Power PLL Power Down
37534  */
37535 #define DDRPHY_DX8SL4DQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL4DQSCTL_LPPLLPD_MASK)
37536 #define DDRPHY_DX8SL4DQSCTL_DQSGX_MASK           (0x180000U)
37537 #define DDRPHY_DX8SL4DQSCTL_DQSGX_SHIFT          (19U)
37538 /*! DQSGX - DQS Gate Extension
37539  */
37540 #define DDRPHY_DX8SL4DQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DQSGX_MASK)
37541 #define DDRPHY_DX8SL4DQSCTL_WRRMODE_MASK         (0x200000U)
37542 #define DDRPHY_DX8SL4DQSCTL_WRRMODE_SHIFT        (21U)
37543 /*! WRRMODE - Write Path Rise-to-Rise Mode
37544  */
37545 #define DDRPHY_DX8SL4DQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL4DQSCTL_WRRMODE_MASK)
37546 #define DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_MASK  (0xC00000U)
37547 #define DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT (22U)
37548 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
37549  */
37550 #define DDRPHY_DX8SL4DQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_MASK)
37551 #define DDRPHY_DX8SL4DQSCTL_RRRMODE_MASK         (0x1000000U)
37552 #define DDRPHY_DX8SL4DQSCTL_RRRMODE_SHIFT        (24U)
37553 /*! RRRMODE - Read Path Rise-to-Rise Mode
37554  */
37555 #define DDRPHY_DX8SL4DQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RRRMODE_MASK)
37556 #define DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
37557 #define DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT (25U)
37558 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
37559  */
37560 #define DDRPHY_DX8SL4DQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_MASK)
37561 /*! @} */
37562 
37563 /*! @name DX8SL4TRNCTL - DATX8 0-1 Training Control Register */
37564 /*! @{ */
37565 #define DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
37566 #define DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_SHIFT  (0U)
37567 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
37568  */
37569 #define DDRPHY_DX8SL4TRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_MASK)
37570 /*! @} */
37571 
37572 /*! @name DX8SL4DDLCTL - DATX8 0-1 DDL Control Register */
37573 /*! @{ */
37574 #define DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_MASK      (0x3U)
37575 #define DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_SHIFT     (0U)
37576 /*! DDLBYPMODE - Controls DDL Bypass Mode
37577  */
37578 #define DDRPHY_DX8SL4DDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_MASK)
37579 #define DDRPHY_DX8SL4DDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
37580 #define DDRPHY_DX8SL4DDLCTL_DXDDLBYP_SHIFT       (2U)
37581 /*! DXDDLBYP - DATX8 DDL Bypass
37582  */
37583 #define DDRPHY_DX8SL4DDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DXDDLBYP_MASK)
37584 #define DDRPHY_DX8SL4DDLCTL_DXDDLLD_MASK         (0x7C0000U)
37585 #define DDRPHY_DX8SL4DDLCTL_DXDDLLD_SHIFT        (18U)
37586 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
37587  */
37588 #define DDRPHY_DX8SL4DDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DXDDLLD_MASK)
37589 #define DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_MASK  (0x1800000U)
37590 #define DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_SHIFT (23U)
37591 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
37592  */
37593 #define DDRPHY_DX8SL4DDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_MASK)
37594 #define DDRPHY_DX8SL4DDLCTL_DXDDLLDT_MASK        (0x2000000U)
37595 #define DDRPHY_DX8SL4DDLCTL_DXDDLLDT_SHIFT       (25U)
37596 /*! DXDDLLDT - DX DDL Load Type
37597  */
37598 #define DDRPHY_DX8SL4DDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DXDDLLDT_MASK)
37599 #define DDRPHY_DX8SL4DDLCTL_DLYLDTM_MASK         (0x4000000U)
37600 #define DDRPHY_DX8SL4DDLCTL_DLYLDTM_SHIFT        (26U)
37601 /*! DLYLDTM - Delay Load Timing
37602  */
37603 #define DDRPHY_DX8SL4DDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DLYLDTM_MASK)
37604 #define DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
37605 #define DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_SHIFT (27U)
37606 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
37607  */
37608 #define DDRPHY_DX8SL4DDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_MASK)
37609 /*! @} */
37610 
37611 /*! @name DX8SL4DXCTL1 - DATX8 0-1 DX Control Register 1 */
37612 /*! @{ */
37613 #define DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
37614 #define DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_SHIFT  (0U)
37615 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
37616  */
37617 #define DDRPHY_DX8SL4DXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_MASK)
37618 #define DDRPHY_DX8SL4DXCTL1_DXTMODE_MASK         (0x10000U)
37619 #define DDRPHY_DX8SL4DXCTL1_DXTMODE_SHIFT        (16U)
37620 /*! DXTMODE - DATX8 Test Mode
37621  */
37622 #define DDRPHY_DX8SL4DXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXTMODE_MASK)
37623 #define DDRPHY_DX8SL4DXCTL1_DXGDBYP_MASK         (0x20000U)
37624 #define DDRPHY_DX8SL4DXCTL1_DXGDBYP_SHIFT        (17U)
37625 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
37626  */
37627 #define DDRPHY_DX8SL4DXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXGDBYP_MASK)
37628 #define DDRPHY_DX8SL4DXCTL1_DXQSDBYP_MASK        (0x40000U)
37629 #define DDRPHY_DX8SL4DXCTL1_DXQSDBYP_SHIFT       (18U)
37630 /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
37631  */
37632 #define DDRPHY_DX8SL4DXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXQSDBYP_MASK)
37633 #define DDRPHY_DX8SL4DXCTL1_DXGSMD_MASK          (0x80000U)
37634 #define DDRPHY_DX8SL4DXCTL1_DXGSMD_SHIFT         (19U)
37635 /*! DXGSMD - Read DQS Gating Status Mode
37636  */
37637 #define DDRPHY_DX8SL4DXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXGSMD_MASK)
37638 #define DDRPHY_DX8SL4DXCTL1_DXDTOSEL_MASK        (0x300000U)
37639 #define DDRPHY_DX8SL4DXCTL1_DXDTOSEL_SHIFT       (20U)
37640 /*! DXDTOSEL - DATX8 Digital Test Output Select
37641  */
37642 #define DDRPHY_DX8SL4DXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXDTOSEL_MASK)
37643 #define DDRPHY_DX8SL4DXCTL1_RESERVED_22_MASK     (0x400000U)
37644 #define DDRPHY_DX8SL4DXCTL1_RESERVED_22_SHIFT    (22U)
37645 /*! RESERVED_22 - Reserved. Return zeroes on reads.
37646  */
37647 #define DDRPHY_DX8SL4DXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL4DXCTL1_RESERVED_22_MASK)
37648 #define DDRPHY_DX8SL4DXCTL1_DXRCLKMD_MASK        (0x800000U)
37649 #define DDRPHY_DX8SL4DXCTL1_DXRCLKMD_SHIFT       (23U)
37650 /*! DXRCLKMD - DATX8 Read Clock Mode
37651  */
37652 #define DDRPHY_DX8SL4DXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXRCLKMD_MASK)
37653 #define DDRPHY_DX8SL4DXCTL1_DXCALCLK_MASK        (0x1000000U)
37654 #define DDRPHY_DX8SL4DXCTL1_DXCALCLK_SHIFT       (24U)
37655 /*! DXCALCLK - DATX Calibration Clock Select
37656  */
37657 #define DDRPHY_DX8SL4DXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXCALCLK_MASK)
37658 #define DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
37659 #define DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_SHIFT (25U)
37660 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
37661  */
37662 #define DDRPHY_DX8SL4DXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_MASK)
37663 /*! @} */
37664 
37665 /*! @name DX8SL4DXCTL2 - DATX8 0-1 DX Control Register 2 */
37666 /*! @{ */
37667 #define DDRPHY_DX8SL4DXCTL2_RESERVED_0_MASK      (0x1U)
37668 #define DDRPHY_DX8SL4DXCTL2_RESERVED_0_SHIFT     (0U)
37669 /*! RESERVED_0 - Reserved. Return zeroes on reads.
37670  */
37671 #define DDRPHY_DX8SL4DXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_0_MASK)
37672 #define DDRPHY_DX8SL4DXCTL2_DQSGLB_MASK          (0x6U)
37673 #define DDRPHY_DX8SL4DXCTL2_DQSGLB_SHIFT         (1U)
37674 /*! DQSGLB - Read DQS Gate I/O Loopback
37675  */
37676 #define DDRPHY_DX8SL4DXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL4DXCTL2_DQSGLB_MASK)
37677 #define DDRPHY_DX8SL4DXCTL2_DISRST_MASK          (0x8U)
37678 #define DDRPHY_DX8SL4DXCTL2_DISRST_SHIFT         (3U)
37679 /*! DISRST - Disables the Read FIFO Reset
37680  */
37681 #define DDRPHY_DX8SL4DXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL4DXCTL2_DISRST_MASK)
37682 #define DDRPHY_DX8SL4DXCTL2_RDMODE_MASK          (0x30U)
37683 #define DDRPHY_DX8SL4DXCTL2_RDMODE_SHIFT         (4U)
37684 /*! RDMODE - DATX8 Receive FIFO Read Mode
37685  */
37686 #define DDRPHY_DX8SL4DXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RDMODE_MASK)
37687 #define DDRPHY_DX8SL4DXCTL2_PRFBYP_MASK          (0x40U)
37688 #define DDRPHY_DX8SL4DXCTL2_PRFBYP_SHIFT         (6U)
37689 /*! PRFBYP - PUB Read FIFO Bypass
37690  */
37691 #define DDRPHY_DX8SL4DXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL4DXCTL2_PRFBYP_MASK)
37692 #define DDRPHY_DX8SL4DXCTL2_WDBI_MASK            (0x80U)
37693 #define DDRPHY_DX8SL4DXCTL2_WDBI_SHIFT           (7U)
37694 /*! WDBI - Write Data Bus Inversion Enable
37695  */
37696 #define DDRPHY_DX8SL4DXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL4DXCTL2_WDBI_MASK)
37697 #define DDRPHY_DX8SL4DXCTL2_RDBI_MASK            (0x100U)
37698 #define DDRPHY_DX8SL4DXCTL2_RDBI_SHIFT           (8U)
37699 /*! RDBI - Read Data Bus Inversion Enable
37700  */
37701 #define DDRPHY_DX8SL4DXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RDBI_MASK)
37702 #define DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
37703 #define DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
37704 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
37705  */
37706 #define DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK)
37707 #define DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_MASK  (0x6000U)
37708 #define DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT (13U)
37709 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
37710  */
37711 #define DDRPHY_DX8SL4DXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_MASK)
37712 #define DDRPHY_DX8SL4DXCTL2_IOLB_MASK            (0x8000U)
37713 #define DDRPHY_DX8SL4DXCTL2_IOLB_SHIFT           (15U)
37714 /*! IOLB - I/O Loopback Select
37715  */
37716 #define DDRPHY_DX8SL4DXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL4DXCTL2_IOLB_MASK)
37717 #define DDRPHY_DX8SL4DXCTL2_IOAG_MASK            (0x10000U)
37718 #define DDRPHY_DX8SL4DXCTL2_IOAG_SHIFT           (16U)
37719 /*! IOAG - I/O Assisted Gate Select
37720  */
37721 #define DDRPHY_DX8SL4DXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL4DXCTL2_IOAG_MASK)
37722 #define DDRPHY_DX8SL4DXCTL2_RESERVED_17_MASK     (0x20000U)
37723 #define DDRPHY_DX8SL4DXCTL2_RESERVED_17_SHIFT    (17U)
37724 /*! RESERVED_17 - Reserved. Return zeroes on reads.
37725  */
37726 #define DDRPHY_DX8SL4DXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_17_MASK)
37727 #define DDRPHY_DX8SL4DXCTL2_PREOEX_MASK          (0xC0000U)
37728 #define DDRPHY_DX8SL4DXCTL2_PREOEX_SHIFT         (18U)
37729 /*! PREOEX - OE Extension during Pre-amble
37730  */
37731 #define DDRPHY_DX8SL4DXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL4DXCTL2_PREOEX_MASK)
37732 #define DDRPHY_DX8SL4DXCTL2_POSOEX_MASK          (0x700000U)
37733 #define DDRPHY_DX8SL4DXCTL2_POSOEX_SHIFT         (20U)
37734 /*! POSOEX - OX Extension during Post-amble
37735  */
37736 #define DDRPHY_DX8SL4DXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL4DXCTL2_POSOEX_MASK)
37737 #define DDRPHY_DX8SL4DXCTL2_CRDEN_MASK           (0x800000U)
37738 #define DDRPHY_DX8SL4DXCTL2_CRDEN_SHIFT          (23U)
37739 /*! CRDEN - Configurable Read Data Enable
37740  */
37741 #define DDRPHY_DX8SL4DXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL4DXCTL2_CRDEN_MASK)
37742 #define DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
37743 #define DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT (24U)
37744 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
37745  */
37746 #define DDRPHY_DX8SL4DXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_MASK)
37747 /*! @} */
37748 
37749 /*! @name DX8SL4IOCR - DATX8 0-1 I/O Configuration Register */
37750 /*! @{ */
37751 #define DDRPHY_DX8SL4IOCR_DXRXM_MASK             (0x7FFU)
37752 #define DDRPHY_DX8SL4IOCR_DXRXM_SHIFT            (0U)
37753 /*! DXRXM - DX IO Receiver Mode
37754  */
37755 #define DDRPHY_DX8SL4IOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXRXM_MASK)
37756 #define DDRPHY_DX8SL4IOCR_DXTXM_MASK             (0x3FF800U)
37757 #define DDRPHY_DX8SL4IOCR_DXTXM_SHIFT            (11U)
37758 /*! DXTXM - DX IO Transmitter Mode
37759  */
37760 #define DDRPHY_DX8SL4IOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXTXM_MASK)
37761 #define DDRPHY_DX8SL4IOCR_DXIOM_MASK             (0x1C00000U)
37762 #define DDRPHY_DX8SL4IOCR_DXIOM_SHIFT            (22U)
37763 /*! DXIOM - DX IO Mode
37764  */
37765 #define DDRPHY_DX8SL4IOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXIOM_MASK)
37766 #define DDRPHY_DX8SL4IOCR_DXVREFIOM_MASK         (0xE000000U)
37767 #define DDRPHY_DX8SL4IOCR_DXVREFIOM_SHIFT        (25U)
37768 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
37769  */
37770 #define DDRPHY_DX8SL4IOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXVREFIOM_MASK)
37771 #define DDRPHY_DX8SL4IOCR_DXDACRANGE_MASK        (0x70000000U)
37772 #define DDRPHY_DX8SL4IOCR_DXDACRANGE_SHIFT       (28U)
37773 /*! DXDACRANGE - PVREF_DAC REFSEL range select
37774  */
37775 #define DDRPHY_DX8SL4IOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL4IOCR_DXDACRANGE_MASK)
37776 #define DDRPHY_DX8SL4IOCR_RESERVED_31_MASK       (0x80000000U)
37777 #define DDRPHY_DX8SL4IOCR_RESERVED_31_SHIFT      (31U)
37778 /*! RESERVED_31 - Reserved. Return zeroes on reads.
37779  */
37780 #define DDRPHY_DX8SL4IOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL4IOCR_RESERVED_31_MASK)
37781 /*! @} */
37782 
37783 /*! @name DX4SL4IOCR - DATX4 Slice 0-1 I/O Configuration Register */
37784 /*! @{ */
37785 #define DDRPHY_DX4SL4IOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
37786 #define DDRPHY_DX4SL4IOCR_RESERVED_31_0_SHIFT    (0U)
37787 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
37788  */
37789 #define DDRPHY_DX4SL4IOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL4IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL4IOCR_RESERVED_31_0_MASK)
37790 /*! @} */
37791 
37792 /*! @name DX8SL5OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
37793 /*! @{ */
37794 #define DDRPHY_DX8SL5OSC_OSCEN_MASK              (0x1U)
37795 #define DDRPHY_DX8SL5OSC_OSCEN_SHIFT             (0U)
37796 /*! OSCEN - Oscillator Enable
37797  */
37798 #define DDRPHY_DX8SL5OSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL5OSC_OSCEN_MASK)
37799 #define DDRPHY_DX8SL5OSC_OSCDIV_MASK             (0x1EU)
37800 #define DDRPHY_DX8SL5OSC_OSCDIV_SHIFT            (1U)
37801 /*! OSCDIV - Oscillator Mode Division
37802  */
37803 #define DDRPHY_DX8SL5OSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL5OSC_OSCDIV_MASK)
37804 #define DDRPHY_DX8SL5OSC_OSCWDL_MASK             (0x60U)
37805 #define DDRPHY_DX8SL5OSC_OSCWDL_SHIFT            (5U)
37806 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
37807  */
37808 #define DDRPHY_DX8SL5OSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL5OSC_OSCWDL_MASK)
37809 #define DDRPHY_DX8SL5OSC_RESERVED_8_7_MASK       (0x180U)
37810 #define DDRPHY_DX8SL5OSC_RESERVED_8_7_SHIFT      (7U)
37811 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
37812  */
37813 #define DDRPHY_DX8SL5OSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL5OSC_RESERVED_8_7_MASK)
37814 #define DDRPHY_DX8SL5OSC_OSCWDDL_MASK            (0x600U)
37815 #define DDRPHY_DX8SL5OSC_OSCWDDL_SHIFT           (9U)
37816 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
37817  */
37818 #define DDRPHY_DX8SL5OSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL5OSC_OSCWDDL_MASK)
37819 #define DDRPHY_DX8SL5OSC_RESERVED_12_11_MASK     (0x1800U)
37820 #define DDRPHY_DX8SL5OSC_RESERVED_12_11_SHIFT    (11U)
37821 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
37822  */
37823 #define DDRPHY_DX8SL5OSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL5OSC_RESERVED_12_11_MASK)
37824 #define DDRPHY_DX8SL5OSC_DLTMODE_MASK            (0x2000U)
37825 #define DDRPHY_DX8SL5OSC_DLTMODE_SHIFT           (13U)
37826 /*! DLTMODE - Delay Line Test Mode
37827  */
37828 #define DDRPHY_DX8SL5OSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL5OSC_DLTMODE_MASK)
37829 #define DDRPHY_DX8SL5OSC_DLTST_MASK              (0x4000U)
37830 #define DDRPHY_DX8SL5OSC_DLTST_SHIFT             (14U)
37831 /*! DLTST - Delay Line Test Start
37832  */
37833 #define DDRPHY_DX8SL5OSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_DLTST_SHIFT)) & DDRPHY_DX8SL5OSC_DLTST_MASK)
37834 #define DDRPHY_DX8SL5OSC_PHYFRST_MASK            (0x8000U)
37835 #define DDRPHY_DX8SL5OSC_PHYFRST_SHIFT           (15U)
37836 /*! PHYFRST - PHY FIFO Reset
37837  */
37838 #define DDRPHY_DX8SL5OSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL5OSC_PHYFRST_MASK)
37839 #define DDRPHY_DX8SL5OSC_PHYHRST_MASK            (0x10000U)
37840 #define DDRPHY_DX8SL5OSC_PHYHRST_SHIFT           (16U)
37841 /*! PHYHRST - PHY High-Speed Reset
37842  */
37843 #define DDRPHY_DX8SL5OSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL5OSC_PHYHRST_MASK)
37844 #define DDRPHY_DX8SL5OSC_LBDQSS_MASK             (0x20000U)
37845 #define DDRPHY_DX8SL5OSC_LBDQSS_SHIFT            (17U)
37846 /*! LBDQSS - Loopback DQS Shift
37847  */
37848 #define DDRPHY_DX8SL5OSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL5OSC_LBDQSS_MASK)
37849 #define DDRPHY_DX8SL5OSC_LBGDQS_MASK             (0xC0000U)
37850 #define DDRPHY_DX8SL5OSC_LBGDQS_SHIFT            (18U)
37851 /*! LBGDQS - Loopback DQS Gating
37852  */
37853 #define DDRPHY_DX8SL5OSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL5OSC_LBGDQS_MASK)
37854 #define DDRPHY_DX8SL5OSC_LBGSDQS_MASK            (0x100000U)
37855 #define DDRPHY_DX8SL5OSC_LBGSDQS_SHIFT           (20U)
37856 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
37857  */
37858 #define DDRPHY_DX8SL5OSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL5OSC_LBGSDQS_MASK)
37859 #define DDRPHY_DX8SL5OSC_LBMODE_MASK             (0x200000U)
37860 #define DDRPHY_DX8SL5OSC_LBMODE_SHIFT            (21U)
37861 /*! LBMODE - Loopback Mode
37862  */
37863 #define DDRPHY_DX8SL5OSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL5OSC_LBMODE_MASK)
37864 #define DDRPHY_DX8SL5OSC_CLKLEVEL_MASK           (0xC00000U)
37865 #define DDRPHY_DX8SL5OSC_CLKLEVEL_SHIFT          (22U)
37866 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
37867  */
37868 #define DDRPHY_DX8SL5OSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL5OSC_CLKLEVEL_MASK)
37869 #define DDRPHY_DX8SL5OSC_GATEDXCTLCLK_MASK       (0x3000000U)
37870 #define DDRPHY_DX8SL5OSC_GATEDXCTLCLK_SHIFT      (24U)
37871 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
37872  */
37873 #define DDRPHY_DX8SL5OSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL5OSC_GATEDXCTLCLK_MASK)
37874 #define DDRPHY_DX8SL5OSC_GATEDXDDRCLK_MASK       (0xC000000U)
37875 #define DDRPHY_DX8SL5OSC_GATEDXDDRCLK_SHIFT      (26U)
37876 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
37877  */
37878 #define DDRPHY_DX8SL5OSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL5OSC_GATEDXDDRCLK_MASK)
37879 #define DDRPHY_DX8SL5OSC_GATEDXRDCLK_MASK        (0x30000000U)
37880 #define DDRPHY_DX8SL5OSC_GATEDXRDCLK_SHIFT       (28U)
37881 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
37882  */
37883 #define DDRPHY_DX8SL5OSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL5OSC_GATEDXRDCLK_MASK)
37884 #define DDRPHY_DX8SL5OSC_RESERVED_31_30_MASK     (0xC0000000U)
37885 #define DDRPHY_DX8SL5OSC_RESERVED_31_30_SHIFT    (30U)
37886 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
37887  */
37888 #define DDRPHY_DX8SL5OSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL5OSC_RESERVED_31_30_MASK)
37889 /*! @} */
37890 
37891 /*! @name DX8SL5PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
37892 /*! @{ */
37893 #define DDRPHY_DX8SL5PLLCR0_DTC_MASK             (0xFU)
37894 #define DDRPHY_DX8SL5PLLCR0_DTC_SHIFT            (0U)
37895 /*! DTC - Digital Test Control
37896  */
37897 #define DDRPHY_DX8SL5PLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_DTC_MASK)
37898 #define DDRPHY_DX8SL5PLLCR0_ATC_MASK             (0xF0U)
37899 #define DDRPHY_DX8SL5PLLCR0_ATC_SHIFT            (4U)
37900 /*! ATC - Analog Test Control
37901  */
37902 #define DDRPHY_DX8SL5PLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_ATC_MASK)
37903 #define DDRPHY_DX8SL5PLLCR0_ATOEN_MASK           (0x100U)
37904 #define DDRPHY_DX8SL5PLLCR0_ATOEN_SHIFT          (8U)
37905 /*! ATOEN - Analog Test Enable (ATOEN)
37906  */
37907 #define DDRPHY_DX8SL5PLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL5PLLCR0_ATOEN_MASK)
37908 #define DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_MASK   (0xE00U)
37909 #define DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_SHIFT  (9U)
37910 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
37911  */
37912 #define DDRPHY_DX8SL5PLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_MASK)
37913 #define DDRPHY_DX8SL5PLLCR0_GSHIFT_MASK          (0x1000U)
37914 #define DDRPHY_DX8SL5PLLCR0_GSHIFT_SHIFT         (12U)
37915 /*! GSHIFT - Gear Shift
37916  */
37917 #define DDRPHY_DX8SL5PLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL5PLLCR0_GSHIFT_MASK)
37918 #define DDRPHY_DX8SL5PLLCR0_CPIC_MASK            (0x1E000U)
37919 #define DDRPHY_DX8SL5PLLCR0_CPIC_SHIFT           (13U)
37920 /*! CPIC - Charge Pump Integrating Current Control
37921  */
37922 #define DDRPHY_DX8SL5PLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_CPIC_MASK)
37923 #define DDRPHY_DX8SL5PLLCR0_CPPC_MASK            (0x7E0000U)
37924 #define DDRPHY_DX8SL5PLLCR0_CPPC_SHIFT           (17U)
37925 /*! CPPC - Charge Pump Proportional Current Control
37926  */
37927 #define DDRPHY_DX8SL5PLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_CPPC_MASK)
37928 #define DDRPHY_DX8SL5PLLCR0_RLOCKM_MASK          (0x800000U)
37929 #define DDRPHY_DX8SL5PLLCR0_RLOCKM_SHIFT         (23U)
37930 /*! RLOCKM - Relock Mode
37931  */
37932 #define DDRPHY_DX8SL5PLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL5PLLCR0_RLOCKM_MASK)
37933 #define DDRPHY_DX8SL5PLLCR0_FRQSEL_MASK          (0xF000000U)
37934 #define DDRPHY_DX8SL5PLLCR0_FRQSEL_SHIFT         (24U)
37935 /*! FRQSEL - PLL Frequency Select
37936  */
37937 #define DDRPHY_DX8SL5PLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL5PLLCR0_FRQSEL_MASK)
37938 #define DDRPHY_DX8SL5PLLCR0_RSTOPM_MASK          (0x10000000U)
37939 #define DDRPHY_DX8SL5PLLCR0_RSTOPM_SHIFT         (28U)
37940 /*! RSTOPM - Reference Stop Mode
37941  */
37942 #define DDRPHY_DX8SL5PLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL5PLLCR0_RSTOPM_MASK)
37943 #define DDRPHY_DX8SL5PLLCR0_PLLPD_MASK           (0x20000000U)
37944 #define DDRPHY_DX8SL5PLLCR0_PLLPD_SHIFT          (29U)
37945 /*! PLLPD - PLL Power Down
37946  */
37947 #define DDRPHY_DX8SL5PLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL5PLLCR0_PLLPD_MASK)
37948 #define DDRPHY_DX8SL5PLLCR0_PLLRST_MASK          (0x40000000U)
37949 #define DDRPHY_DX8SL5PLLCR0_PLLRST_SHIFT         (30U)
37950 /*! PLLRST - PLL Reset
37951  */
37952 #define DDRPHY_DX8SL5PLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL5PLLCR0_PLLRST_MASK)
37953 #define DDRPHY_DX8SL5PLLCR0_PLLBYP_MASK          (0x80000000U)
37954 #define DDRPHY_DX8SL5PLLCR0_PLLBYP_SHIFT         (31U)
37955 /*! PLLBYP - PLL Bypass
37956  */
37957 #define DDRPHY_DX8SL5PLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL5PLLCR0_PLLBYP_MASK)
37958 /*! @} */
37959 
37960 /*! @name DX8SL5PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
37961 /*! @{ */
37962 #define DDRPHY_DX8SL5PLLCR1_LOCKDS_MASK          (0x1U)
37963 #define DDRPHY_DX8SL5PLLCR1_LOCKDS_SHIFT         (0U)
37964 /*! LOCKDS - Lock Detector Select
37965  */
37966 #define DDRPHY_DX8SL5PLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL5PLLCR1_LOCKDS_MASK)
37967 #define DDRPHY_DX8SL5PLLCR1_LOCKCS_MASK          (0x2U)
37968 #define DDRPHY_DX8SL5PLLCR1_LOCKCS_SHIFT         (1U)
37969 /*! LOCKCS - Lock Detector Counter Select
37970  */
37971 #define DDRPHY_DX8SL5PLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL5PLLCR1_LOCKCS_MASK)
37972 #define DDRPHY_DX8SL5PLLCR1_LOCKPS_MASK          (0x4U)
37973 #define DDRPHY_DX8SL5PLLCR1_LOCKPS_SHIFT         (2U)
37974 /*! LOCKPS - Lock Detector Phase Select
37975  */
37976 #define DDRPHY_DX8SL5PLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL5PLLCR1_LOCKPS_MASK)
37977 #define DDRPHY_DX8SL5PLLCR1_BYPVDD_MASK          (0x8U)
37978 #define DDRPHY_DX8SL5PLLCR1_BYPVDD_SHIFT         (3U)
37979 /*! BYPVDD - PLL VDD voltage level control
37980  */
37981 #define DDRPHY_DX8SL5PLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL5PLLCR1_BYPVDD_MASK)
37982 #define DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_MASK      (0x10U)
37983 #define DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_SHIFT     (4U)
37984 /*! BYPVREGDIG - Bypass PLL vreg_dig
37985  */
37986 #define DDRPHY_DX8SL5PLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_MASK)
37987 #define DDRPHY_DX8SL5PLLCR1_BYPVREGCP_MASK       (0x20U)
37988 #define DDRPHY_DX8SL5PLLCR1_BYPVREGCP_SHIFT      (5U)
37989 /*! BYPVREGCP - Bypass PLL vreg_cp
37990  */
37991 #define DDRPHY_DX8SL5PLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL5PLLCR1_BYPVREGCP_MASK)
37992 #define DDRPHY_DX8SL5PLLCR1_PLLPROG_MASK         (0x3FFFC0U)
37993 #define DDRPHY_DX8SL5PLLCR1_PLLPROG_SHIFT        (6U)
37994 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
37995  */
37996 #define DDRPHY_DX8SL5PLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL5PLLCR1_PLLPROG_MASK)
37997 #define DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
37998 #define DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_SHIFT (22U)
37999 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
38000  */
38001 #define DDRPHY_DX8SL5PLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_MASK)
38002 /*! @} */
38003 
38004 /*! @name DX8SL5PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
38005 /*! @{ */
38006 #define DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
38007 #define DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_SHIFT   (0U)
38008 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
38009  */
38010 #define DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_MASK)
38011 /*! @} */
38012 
38013 /*! @name DX8SL5PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
38014 /*! @{ */
38015 #define DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
38016 #define DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_SHIFT  (0U)
38017 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
38018  */
38019 #define DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_MASK)
38020 /*! @} */
38021 
38022 /*! @name DX8SL5PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
38023 /*! @{ */
38024 #define DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
38025 #define DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_SHIFT  (0U)
38026 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
38027  */
38028 #define DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_MASK)
38029 /*! @} */
38030 
38031 /*! @name DX8SL5PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
38032 /*! @{ */
38033 #define DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
38034 #define DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_SHIFT (0U)
38035 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
38036  */
38037 #define DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_MASK)
38038 #define DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
38039 #define DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_SHIFT  (8U)
38040 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
38041  */
38042 #define DDRPHY_DX8SL5PLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_MASK)
38043 /*! @} */
38044 
38045 /*! @name DX8SL5DQSCTL - DATX8 0-1 DQS Control Register */
38046 /*! @{ */
38047 #define DDRPHY_DX8SL5DQSCTL_DQSRES_MASK          (0xFU)
38048 #define DDRPHY_DX8SL5DQSCTL_DQSRES_SHIFT         (0U)
38049 /*! DQSRES - DQS Resistor
38050  */
38051 #define DDRPHY_DX8SL5DQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DQSRES_MASK)
38052 #define DDRPHY_DX8SL5DQSCTL_DQSNRES_MASK         (0xF0U)
38053 #define DDRPHY_DX8SL5DQSCTL_DQSNRES_SHIFT        (4U)
38054 /*! DQSNRES - DQS_N Resistor
38055  */
38056 #define DDRPHY_DX8SL5DQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DQSNRES_MASK)
38057 #define DDRPHY_DX8SL5DQSCTL_DXSR_MASK            (0x300U)
38058 #define DDRPHY_DX8SL5DQSCTL_DXSR_SHIFT           (8U)
38059 /*! DXSR - Data Slew Rate
38060  */
38061 #define DDRPHY_DX8SL5DQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DXSR_MASK)
38062 #define DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_MASK  (0x1C00U)
38063 #define DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_SHIFT (10U)
38064 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
38065  */
38066 #define DDRPHY_DX8SL5DQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_MASK)
38067 #define DDRPHY_DX8SL5DQSCTL_UDQIOM_MASK          (0x2000U)
38068 #define DDRPHY_DX8SL5DQSCTL_UDQIOM_SHIFT         (13U)
38069 /*! UDQIOM - Unused DQ I/O Mode
38070  */
38071 #define DDRPHY_DX8SL5DQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL5DQSCTL_UDQIOM_MASK)
38072 #define DDRPHY_DX8SL5DQSCTL_QSCNTEN_MASK         (0x4000U)
38073 #define DDRPHY_DX8SL5DQSCTL_QSCNTEN_SHIFT        (14U)
38074 /*! QSCNTEN - QS Counter Enable
38075  */
38076 #define DDRPHY_DX8SL5DQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL5DQSCTL_QSCNTEN_MASK)
38077 #define DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_MASK  (0x18000U)
38078 #define DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_SHIFT (15U)
38079 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
38080  */
38081 #define DDRPHY_DX8SL5DQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_MASK)
38082 #define DDRPHY_DX8SL5DQSCTL_LPIOPD_MASK          (0x20000U)
38083 #define DDRPHY_DX8SL5DQSCTL_LPIOPD_SHIFT         (17U)
38084 /*! LPIOPD - Low Power I/O Power Down
38085  */
38086 #define DDRPHY_DX8SL5DQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL5DQSCTL_LPIOPD_MASK)
38087 #define DDRPHY_DX8SL5DQSCTL_LPPLLPD_MASK         (0x40000U)
38088 #define DDRPHY_DX8SL5DQSCTL_LPPLLPD_SHIFT        (18U)
38089 /*! LPPLLPD - Low Power PLL Power Down
38090  */
38091 #define DDRPHY_DX8SL5DQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL5DQSCTL_LPPLLPD_MASK)
38092 #define DDRPHY_DX8SL5DQSCTL_DQSGX_MASK           (0x180000U)
38093 #define DDRPHY_DX8SL5DQSCTL_DQSGX_SHIFT          (19U)
38094 /*! DQSGX - DQS Gate Extension
38095  */
38096 #define DDRPHY_DX8SL5DQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DQSGX_MASK)
38097 #define DDRPHY_DX8SL5DQSCTL_WRRMODE_MASK         (0x200000U)
38098 #define DDRPHY_DX8SL5DQSCTL_WRRMODE_SHIFT        (21U)
38099 /*! WRRMODE - Write Path Rise-to-Rise Mode
38100  */
38101 #define DDRPHY_DX8SL5DQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL5DQSCTL_WRRMODE_MASK)
38102 #define DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_MASK  (0xC00000U)
38103 #define DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_SHIFT (22U)
38104 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
38105  */
38106 #define DDRPHY_DX8SL5DQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_MASK)
38107 #define DDRPHY_DX8SL5DQSCTL_RRRMODE_MASK         (0x1000000U)
38108 #define DDRPHY_DX8SL5DQSCTL_RRRMODE_SHIFT        (24U)
38109 /*! RRRMODE - Read Path Rise-to-Rise Mode
38110  */
38111 #define DDRPHY_DX8SL5DQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RRRMODE_MASK)
38112 #define DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
38113 #define DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_SHIFT (25U)
38114 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
38115  */
38116 #define DDRPHY_DX8SL5DQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_MASK)
38117 /*! @} */
38118 
38119 /*! @name DX8SL5TRNCTL - DATX8 0-1 Training Control Register */
38120 /*! @{ */
38121 #define DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
38122 #define DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_SHIFT  (0U)
38123 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
38124  */
38125 #define DDRPHY_DX8SL5TRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_MASK)
38126 /*! @} */
38127 
38128 /*! @name DX8SL5DDLCTL - DATX8 0-1 DDL Control Register */
38129 /*! @{ */
38130 #define DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_MASK      (0x3U)
38131 #define DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_SHIFT     (0U)
38132 /*! DDLBYPMODE - Controls DDL Bypass Mode
38133  */
38134 #define DDRPHY_DX8SL5DDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_MASK)
38135 #define DDRPHY_DX8SL5DDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
38136 #define DDRPHY_DX8SL5DDLCTL_DXDDLBYP_SHIFT       (2U)
38137 /*! DXDDLBYP - DATX8 DDL Bypass
38138  */
38139 #define DDRPHY_DX8SL5DDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DXDDLBYP_MASK)
38140 #define DDRPHY_DX8SL5DDLCTL_DXDDLLD_MASK         (0x7C0000U)
38141 #define DDRPHY_DX8SL5DDLCTL_DXDDLLD_SHIFT        (18U)
38142 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
38143  */
38144 #define DDRPHY_DX8SL5DDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DXDDLLD_MASK)
38145 #define DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_MASK  (0x1800000U)
38146 #define DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_SHIFT (23U)
38147 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
38148  */
38149 #define DDRPHY_DX8SL5DDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_MASK)
38150 #define DDRPHY_DX8SL5DDLCTL_DXDDLLDT_MASK        (0x2000000U)
38151 #define DDRPHY_DX8SL5DDLCTL_DXDDLLDT_SHIFT       (25U)
38152 /*! DXDDLLDT - DX DDL Load Type
38153  */
38154 #define DDRPHY_DX8SL5DDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DXDDLLDT_MASK)
38155 #define DDRPHY_DX8SL5DDLCTL_DLYLDTM_MASK         (0x4000000U)
38156 #define DDRPHY_DX8SL5DDLCTL_DLYLDTM_SHIFT        (26U)
38157 /*! DLYLDTM - Delay Load Timing
38158  */
38159 #define DDRPHY_DX8SL5DDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DLYLDTM_MASK)
38160 #define DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
38161 #define DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_SHIFT (27U)
38162 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
38163  */
38164 #define DDRPHY_DX8SL5DDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_MASK)
38165 /*! @} */
38166 
38167 /*! @name DX8SL5DXCTL1 - DATX8 0-1 DX Control Register 1 */
38168 /*! @{ */
38169 #define DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
38170 #define DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_SHIFT  (0U)
38171 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
38172  */
38173 #define DDRPHY_DX8SL5DXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_MASK)
38174 #define DDRPHY_DX8SL5DXCTL1_DXTMODE_MASK         (0x10000U)
38175 #define DDRPHY_DX8SL5DXCTL1_DXTMODE_SHIFT        (16U)
38176 /*! DXTMODE - DATX8 Test Mode
38177  */
38178 #define DDRPHY_DX8SL5DXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXTMODE_MASK)
38179 #define DDRPHY_DX8SL5DXCTL1_DXGDBYP_MASK         (0x20000U)
38180 #define DDRPHY_DX8SL5DXCTL1_DXGDBYP_SHIFT        (17U)
38181 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
38182  */
38183 #define DDRPHY_DX8SL5DXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXGDBYP_MASK)
38184 #define DDRPHY_DX8SL5DXCTL1_DXQSDBYP_MASK        (0x40000U)
38185 #define DDRPHY_DX8SL5DXCTL1_DXQSDBYP_SHIFT       (18U)
38186 /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
38187  */
38188 #define DDRPHY_DX8SL5DXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXQSDBYP_MASK)
38189 #define DDRPHY_DX8SL5DXCTL1_DXGSMD_MASK          (0x80000U)
38190 #define DDRPHY_DX8SL5DXCTL1_DXGSMD_SHIFT         (19U)
38191 /*! DXGSMD - Read DQS Gating Status Mode
38192  */
38193 #define DDRPHY_DX8SL5DXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXGSMD_MASK)
38194 #define DDRPHY_DX8SL5DXCTL1_DXDTOSEL_MASK        (0x300000U)
38195 #define DDRPHY_DX8SL5DXCTL1_DXDTOSEL_SHIFT       (20U)
38196 /*! DXDTOSEL - DATX8 Digital Test Output Select
38197  */
38198 #define DDRPHY_DX8SL5DXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXDTOSEL_MASK)
38199 #define DDRPHY_DX8SL5DXCTL1_RESERVED_22_MASK     (0x400000U)
38200 #define DDRPHY_DX8SL5DXCTL1_RESERVED_22_SHIFT    (22U)
38201 /*! RESERVED_22 - Reserved. Return zeroes on reads.
38202  */
38203 #define DDRPHY_DX8SL5DXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL5DXCTL1_RESERVED_22_MASK)
38204 #define DDRPHY_DX8SL5DXCTL1_DXRCLKMD_MASK        (0x800000U)
38205 #define DDRPHY_DX8SL5DXCTL1_DXRCLKMD_SHIFT       (23U)
38206 /*! DXRCLKMD - DATX8 Read Clock Mode
38207  */
38208 #define DDRPHY_DX8SL5DXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXRCLKMD_MASK)
38209 #define DDRPHY_DX8SL5DXCTL1_DXCALCLK_MASK        (0x1000000U)
38210 #define DDRPHY_DX8SL5DXCTL1_DXCALCLK_SHIFT       (24U)
38211 /*! DXCALCLK - DATX Calibration Clock Select
38212  */
38213 #define DDRPHY_DX8SL5DXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXCALCLK_MASK)
38214 #define DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
38215 #define DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_SHIFT (25U)
38216 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
38217  */
38218 #define DDRPHY_DX8SL5DXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_MASK)
38219 /*! @} */
38220 
38221 /*! @name DX8SL5DXCTL2 - DATX8 0-1 DX Control Register 2 */
38222 /*! @{ */
38223 #define DDRPHY_DX8SL5DXCTL2_RESERVED_0_MASK      (0x1U)
38224 #define DDRPHY_DX8SL5DXCTL2_RESERVED_0_SHIFT     (0U)
38225 /*! RESERVED_0 - Reserved. Return zeroes on reads.
38226  */
38227 #define DDRPHY_DX8SL5DXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_0_MASK)
38228 #define DDRPHY_DX8SL5DXCTL2_DQSGLB_MASK          (0x6U)
38229 #define DDRPHY_DX8SL5DXCTL2_DQSGLB_SHIFT         (1U)
38230 /*! DQSGLB - Read DQS Gate I/O Loopback
38231  */
38232 #define DDRPHY_DX8SL5DXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL5DXCTL2_DQSGLB_MASK)
38233 #define DDRPHY_DX8SL5DXCTL2_DISRST_MASK          (0x8U)
38234 #define DDRPHY_DX8SL5DXCTL2_DISRST_SHIFT         (3U)
38235 /*! DISRST - Disables the Read FIFO Reset
38236  */
38237 #define DDRPHY_DX8SL5DXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL5DXCTL2_DISRST_MASK)
38238 #define DDRPHY_DX8SL5DXCTL2_RDMODE_MASK          (0x30U)
38239 #define DDRPHY_DX8SL5DXCTL2_RDMODE_SHIFT         (4U)
38240 /*! RDMODE - DATX8 Receive FIFO Read Mode
38241  */
38242 #define DDRPHY_DX8SL5DXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RDMODE_MASK)
38243 #define DDRPHY_DX8SL5DXCTL2_PRFBYP_MASK          (0x40U)
38244 #define DDRPHY_DX8SL5DXCTL2_PRFBYP_SHIFT         (6U)
38245 /*! PRFBYP - PUB Read FIFO Bypass
38246  */
38247 #define DDRPHY_DX8SL5DXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL5DXCTL2_PRFBYP_MASK)
38248 #define DDRPHY_DX8SL5DXCTL2_WDBI_MASK            (0x80U)
38249 #define DDRPHY_DX8SL5DXCTL2_WDBI_SHIFT           (7U)
38250 /*! WDBI - Write Data Bus Inversion Enable
38251  */
38252 #define DDRPHY_DX8SL5DXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL5DXCTL2_WDBI_MASK)
38253 #define DDRPHY_DX8SL5DXCTL2_RDBI_MASK            (0x100U)
38254 #define DDRPHY_DX8SL5DXCTL2_RDBI_SHIFT           (8U)
38255 /*! RDBI - Read Data Bus Inversion Enable
38256  */
38257 #define DDRPHY_DX8SL5DXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RDBI_MASK)
38258 #define DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
38259 #define DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
38260 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
38261  */
38262 #define DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_MASK)
38263 #define DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_MASK  (0x6000U)
38264 #define DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_SHIFT (13U)
38265 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
38266  */
38267 #define DDRPHY_DX8SL5DXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_MASK)
38268 #define DDRPHY_DX8SL5DXCTL2_IOLB_MASK            (0x8000U)
38269 #define DDRPHY_DX8SL5DXCTL2_IOLB_SHIFT           (15U)
38270 /*! IOLB - I/O Loopback Select
38271  */
38272 #define DDRPHY_DX8SL5DXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL5DXCTL2_IOLB_MASK)
38273 #define DDRPHY_DX8SL5DXCTL2_IOAG_MASK            (0x10000U)
38274 #define DDRPHY_DX8SL5DXCTL2_IOAG_SHIFT           (16U)
38275 /*! IOAG - I/O Assisted Gate Select
38276  */
38277 #define DDRPHY_DX8SL5DXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL5DXCTL2_IOAG_MASK)
38278 #define DDRPHY_DX8SL5DXCTL2_RESERVED_17_MASK     (0x20000U)
38279 #define DDRPHY_DX8SL5DXCTL2_RESERVED_17_SHIFT    (17U)
38280 /*! RESERVED_17 - Reserved. Return zeroes on reads.
38281  */
38282 #define DDRPHY_DX8SL5DXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_17_MASK)
38283 #define DDRPHY_DX8SL5DXCTL2_PREOEX_MASK          (0xC0000U)
38284 #define DDRPHY_DX8SL5DXCTL2_PREOEX_SHIFT         (18U)
38285 /*! PREOEX - OE Extension during Pre-amble
38286  */
38287 #define DDRPHY_DX8SL5DXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL5DXCTL2_PREOEX_MASK)
38288 #define DDRPHY_DX8SL5DXCTL2_POSOEX_MASK          (0x700000U)
38289 #define DDRPHY_DX8SL5DXCTL2_POSOEX_SHIFT         (20U)
38290 /*! POSOEX - OX Extension during Post-amble
38291  */
38292 #define DDRPHY_DX8SL5DXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL5DXCTL2_POSOEX_MASK)
38293 #define DDRPHY_DX8SL5DXCTL2_CRDEN_MASK           (0x800000U)
38294 #define DDRPHY_DX8SL5DXCTL2_CRDEN_SHIFT          (23U)
38295 /*! CRDEN - Configurable Read Data Enable
38296  */
38297 #define DDRPHY_DX8SL5DXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL5DXCTL2_CRDEN_MASK)
38298 #define DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
38299 #define DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_SHIFT (24U)
38300 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
38301  */
38302 #define DDRPHY_DX8SL5DXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_MASK)
38303 /*! @} */
38304 
38305 /*! @name DX8SL5IOCR - DATX8 0-1 I/O Configuration Register */
38306 /*! @{ */
38307 #define DDRPHY_DX8SL5IOCR_DXRXM_MASK             (0x7FFU)
38308 #define DDRPHY_DX8SL5IOCR_DXRXM_SHIFT            (0U)
38309 /*! DXRXM - DX IO Receiver Mode
38310  */
38311 #define DDRPHY_DX8SL5IOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXRXM_MASK)
38312 #define DDRPHY_DX8SL5IOCR_DXTXM_MASK             (0x3FF800U)
38313 #define DDRPHY_DX8SL5IOCR_DXTXM_SHIFT            (11U)
38314 /*! DXTXM - DX IO Transmitter Mode
38315  */
38316 #define DDRPHY_DX8SL5IOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXTXM_MASK)
38317 #define DDRPHY_DX8SL5IOCR_DXIOM_MASK             (0x1C00000U)
38318 #define DDRPHY_DX8SL5IOCR_DXIOM_SHIFT            (22U)
38319 /*! DXIOM - DX IO Mode
38320  */
38321 #define DDRPHY_DX8SL5IOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXIOM_MASK)
38322 #define DDRPHY_DX8SL5IOCR_DXVREFIOM_MASK         (0xE000000U)
38323 #define DDRPHY_DX8SL5IOCR_DXVREFIOM_SHIFT        (25U)
38324 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
38325  */
38326 #define DDRPHY_DX8SL5IOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXVREFIOM_MASK)
38327 #define DDRPHY_DX8SL5IOCR_DXDACRANGE_MASK        (0x70000000U)
38328 #define DDRPHY_DX8SL5IOCR_DXDACRANGE_SHIFT       (28U)
38329 /*! DXDACRANGE - PVREF_DAC REFSEL range select
38330  */
38331 #define DDRPHY_DX8SL5IOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL5IOCR_DXDACRANGE_MASK)
38332 #define DDRPHY_DX8SL5IOCR_RESERVED_31_MASK       (0x80000000U)
38333 #define DDRPHY_DX8SL5IOCR_RESERVED_31_SHIFT      (31U)
38334 /*! RESERVED_31 - Reserved. Return zeroes on reads.
38335  */
38336 #define DDRPHY_DX8SL5IOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL5IOCR_RESERVED_31_MASK)
38337 /*! @} */
38338 
38339 /*! @name DX4SL5IOCR - DATX4 Slice 0-1 I/O Configuration Register */
38340 /*! @{ */
38341 #define DDRPHY_DX4SL5IOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
38342 #define DDRPHY_DX4SL5IOCR_RESERVED_31_0_SHIFT    (0U)
38343 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
38344  */
38345 #define DDRPHY_DX4SL5IOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL5IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL5IOCR_RESERVED_31_0_MASK)
38346 /*! @} */
38347 
38348 /*! @name DX8SL6OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
38349 /*! @{ */
38350 #define DDRPHY_DX8SL6OSC_OSCEN_MASK              (0x1U)
38351 #define DDRPHY_DX8SL6OSC_OSCEN_SHIFT             (0U)
38352 /*! OSCEN - Oscillator Enable
38353  */
38354 #define DDRPHY_DX8SL6OSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL6OSC_OSCEN_MASK)
38355 #define DDRPHY_DX8SL6OSC_OSCDIV_MASK             (0x1EU)
38356 #define DDRPHY_DX8SL6OSC_OSCDIV_SHIFT            (1U)
38357 /*! OSCDIV - Oscillator Mode Division
38358  */
38359 #define DDRPHY_DX8SL6OSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL6OSC_OSCDIV_MASK)
38360 #define DDRPHY_DX8SL6OSC_OSCWDL_MASK             (0x60U)
38361 #define DDRPHY_DX8SL6OSC_OSCWDL_SHIFT            (5U)
38362 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
38363  */
38364 #define DDRPHY_DX8SL6OSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL6OSC_OSCWDL_MASK)
38365 #define DDRPHY_DX8SL6OSC_RESERVED_8_7_MASK       (0x180U)
38366 #define DDRPHY_DX8SL6OSC_RESERVED_8_7_SHIFT      (7U)
38367 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
38368  */
38369 #define DDRPHY_DX8SL6OSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL6OSC_RESERVED_8_7_MASK)
38370 #define DDRPHY_DX8SL6OSC_OSCWDDL_MASK            (0x600U)
38371 #define DDRPHY_DX8SL6OSC_OSCWDDL_SHIFT           (9U)
38372 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
38373  */
38374 #define DDRPHY_DX8SL6OSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL6OSC_OSCWDDL_MASK)
38375 #define DDRPHY_DX8SL6OSC_RESERVED_12_11_MASK     (0x1800U)
38376 #define DDRPHY_DX8SL6OSC_RESERVED_12_11_SHIFT    (11U)
38377 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
38378  */
38379 #define DDRPHY_DX8SL6OSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL6OSC_RESERVED_12_11_MASK)
38380 #define DDRPHY_DX8SL6OSC_DLTMODE_MASK            (0x2000U)
38381 #define DDRPHY_DX8SL6OSC_DLTMODE_SHIFT           (13U)
38382 /*! DLTMODE - Delay Line Test Mode
38383  */
38384 #define DDRPHY_DX8SL6OSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL6OSC_DLTMODE_MASK)
38385 #define DDRPHY_DX8SL6OSC_DLTST_MASK              (0x4000U)
38386 #define DDRPHY_DX8SL6OSC_DLTST_SHIFT             (14U)
38387 /*! DLTST - Delay Line Test Start
38388  */
38389 #define DDRPHY_DX8SL6OSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_DLTST_SHIFT)) & DDRPHY_DX8SL6OSC_DLTST_MASK)
38390 #define DDRPHY_DX8SL6OSC_PHYFRST_MASK            (0x8000U)
38391 #define DDRPHY_DX8SL6OSC_PHYFRST_SHIFT           (15U)
38392 /*! PHYFRST - PHY FIFO Reset
38393  */
38394 #define DDRPHY_DX8SL6OSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL6OSC_PHYFRST_MASK)
38395 #define DDRPHY_DX8SL6OSC_PHYHRST_MASK            (0x10000U)
38396 #define DDRPHY_DX8SL6OSC_PHYHRST_SHIFT           (16U)
38397 /*! PHYHRST - PHY High-Speed Reset
38398  */
38399 #define DDRPHY_DX8SL6OSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL6OSC_PHYHRST_MASK)
38400 #define DDRPHY_DX8SL6OSC_LBDQSS_MASK             (0x20000U)
38401 #define DDRPHY_DX8SL6OSC_LBDQSS_SHIFT            (17U)
38402 /*! LBDQSS - Loopback DQS Shift
38403  */
38404 #define DDRPHY_DX8SL6OSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL6OSC_LBDQSS_MASK)
38405 #define DDRPHY_DX8SL6OSC_LBGDQS_MASK             (0xC0000U)
38406 #define DDRPHY_DX8SL6OSC_LBGDQS_SHIFT            (18U)
38407 /*! LBGDQS - Loopback DQS Gating
38408  */
38409 #define DDRPHY_DX8SL6OSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL6OSC_LBGDQS_MASK)
38410 #define DDRPHY_DX8SL6OSC_LBGSDQS_MASK            (0x100000U)
38411 #define DDRPHY_DX8SL6OSC_LBGSDQS_SHIFT           (20U)
38412 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
38413  */
38414 #define DDRPHY_DX8SL6OSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL6OSC_LBGSDQS_MASK)
38415 #define DDRPHY_DX8SL6OSC_LBMODE_MASK             (0x200000U)
38416 #define DDRPHY_DX8SL6OSC_LBMODE_SHIFT            (21U)
38417 /*! LBMODE - Loopback Mode
38418  */
38419 #define DDRPHY_DX8SL6OSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL6OSC_LBMODE_MASK)
38420 #define DDRPHY_DX8SL6OSC_CLKLEVEL_MASK           (0xC00000U)
38421 #define DDRPHY_DX8SL6OSC_CLKLEVEL_SHIFT          (22U)
38422 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
38423  */
38424 #define DDRPHY_DX8SL6OSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL6OSC_CLKLEVEL_MASK)
38425 #define DDRPHY_DX8SL6OSC_GATEDXCTLCLK_MASK       (0x3000000U)
38426 #define DDRPHY_DX8SL6OSC_GATEDXCTLCLK_SHIFT      (24U)
38427 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
38428  */
38429 #define DDRPHY_DX8SL6OSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL6OSC_GATEDXCTLCLK_MASK)
38430 #define DDRPHY_DX8SL6OSC_GATEDXDDRCLK_MASK       (0xC000000U)
38431 #define DDRPHY_DX8SL6OSC_GATEDXDDRCLK_SHIFT      (26U)
38432 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
38433  */
38434 #define DDRPHY_DX8SL6OSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL6OSC_GATEDXDDRCLK_MASK)
38435 #define DDRPHY_DX8SL6OSC_GATEDXRDCLK_MASK        (0x30000000U)
38436 #define DDRPHY_DX8SL6OSC_GATEDXRDCLK_SHIFT       (28U)
38437 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
38438  */
38439 #define DDRPHY_DX8SL6OSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL6OSC_GATEDXRDCLK_MASK)
38440 #define DDRPHY_DX8SL6OSC_RESERVED_31_30_MASK     (0xC0000000U)
38441 #define DDRPHY_DX8SL6OSC_RESERVED_31_30_SHIFT    (30U)
38442 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
38443  */
38444 #define DDRPHY_DX8SL6OSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL6OSC_RESERVED_31_30_MASK)
38445 /*! @} */
38446 
38447 /*! @name DX8SL6PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
38448 /*! @{ */
38449 #define DDRPHY_DX8SL6PLLCR0_DTC_MASK             (0xFU)
38450 #define DDRPHY_DX8SL6PLLCR0_DTC_SHIFT            (0U)
38451 /*! DTC - Digital Test Control
38452  */
38453 #define DDRPHY_DX8SL6PLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_DTC_MASK)
38454 #define DDRPHY_DX8SL6PLLCR0_ATC_MASK             (0xF0U)
38455 #define DDRPHY_DX8SL6PLLCR0_ATC_SHIFT            (4U)
38456 /*! ATC - Analog Test Control
38457  */
38458 #define DDRPHY_DX8SL6PLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_ATC_MASK)
38459 #define DDRPHY_DX8SL6PLLCR0_ATOEN_MASK           (0x100U)
38460 #define DDRPHY_DX8SL6PLLCR0_ATOEN_SHIFT          (8U)
38461 /*! ATOEN - Analog Test Enable (ATOEN)
38462  */
38463 #define DDRPHY_DX8SL6PLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL6PLLCR0_ATOEN_MASK)
38464 #define DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_MASK   (0xE00U)
38465 #define DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_SHIFT  (9U)
38466 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
38467  */
38468 #define DDRPHY_DX8SL6PLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_MASK)
38469 #define DDRPHY_DX8SL6PLLCR0_GSHIFT_MASK          (0x1000U)
38470 #define DDRPHY_DX8SL6PLLCR0_GSHIFT_SHIFT         (12U)
38471 /*! GSHIFT - Gear Shift
38472  */
38473 #define DDRPHY_DX8SL6PLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL6PLLCR0_GSHIFT_MASK)
38474 #define DDRPHY_DX8SL6PLLCR0_CPIC_MASK            (0x1E000U)
38475 #define DDRPHY_DX8SL6PLLCR0_CPIC_SHIFT           (13U)
38476 /*! CPIC - Charge Pump Integrating Current Control
38477  */
38478 #define DDRPHY_DX8SL6PLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_CPIC_MASK)
38479 #define DDRPHY_DX8SL6PLLCR0_CPPC_MASK            (0x7E0000U)
38480 #define DDRPHY_DX8SL6PLLCR0_CPPC_SHIFT           (17U)
38481 /*! CPPC - Charge Pump Proportional Current Control
38482  */
38483 #define DDRPHY_DX8SL6PLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_CPPC_MASK)
38484 #define DDRPHY_DX8SL6PLLCR0_RLOCKM_MASK          (0x800000U)
38485 #define DDRPHY_DX8SL6PLLCR0_RLOCKM_SHIFT         (23U)
38486 /*! RLOCKM - Relock Mode
38487  */
38488 #define DDRPHY_DX8SL6PLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL6PLLCR0_RLOCKM_MASK)
38489 #define DDRPHY_DX8SL6PLLCR0_FRQSEL_MASK          (0xF000000U)
38490 #define DDRPHY_DX8SL6PLLCR0_FRQSEL_SHIFT         (24U)
38491 /*! FRQSEL - PLL Frequency Select
38492  */
38493 #define DDRPHY_DX8SL6PLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL6PLLCR0_FRQSEL_MASK)
38494 #define DDRPHY_DX8SL6PLLCR0_RSTOPM_MASK          (0x10000000U)
38495 #define DDRPHY_DX8SL6PLLCR0_RSTOPM_SHIFT         (28U)
38496 /*! RSTOPM - Reference Stop Mode
38497  */
38498 #define DDRPHY_DX8SL6PLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL6PLLCR0_RSTOPM_MASK)
38499 #define DDRPHY_DX8SL6PLLCR0_PLLPD_MASK           (0x20000000U)
38500 #define DDRPHY_DX8SL6PLLCR0_PLLPD_SHIFT          (29U)
38501 /*! PLLPD - PLL Power Down
38502  */
38503 #define DDRPHY_DX8SL6PLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL6PLLCR0_PLLPD_MASK)
38504 #define DDRPHY_DX8SL6PLLCR0_PLLRST_MASK          (0x40000000U)
38505 #define DDRPHY_DX8SL6PLLCR0_PLLRST_SHIFT         (30U)
38506 /*! PLLRST - PLL Reset
38507  */
38508 #define DDRPHY_DX8SL6PLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL6PLLCR0_PLLRST_MASK)
38509 #define DDRPHY_DX8SL6PLLCR0_PLLBYP_MASK          (0x80000000U)
38510 #define DDRPHY_DX8SL6PLLCR0_PLLBYP_SHIFT         (31U)
38511 /*! PLLBYP - PLL Bypass
38512  */
38513 #define DDRPHY_DX8SL6PLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL6PLLCR0_PLLBYP_MASK)
38514 /*! @} */
38515 
38516 /*! @name DX8SL6PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
38517 /*! @{ */
38518 #define DDRPHY_DX8SL6PLLCR1_LOCKDS_MASK          (0x1U)
38519 #define DDRPHY_DX8SL6PLLCR1_LOCKDS_SHIFT         (0U)
38520 /*! LOCKDS - Lock Detector Select
38521  */
38522 #define DDRPHY_DX8SL6PLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL6PLLCR1_LOCKDS_MASK)
38523 #define DDRPHY_DX8SL6PLLCR1_LOCKCS_MASK          (0x2U)
38524 #define DDRPHY_DX8SL6PLLCR1_LOCKCS_SHIFT         (1U)
38525 /*! LOCKCS - Lock Detector Counter Select
38526  */
38527 #define DDRPHY_DX8SL6PLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL6PLLCR1_LOCKCS_MASK)
38528 #define DDRPHY_DX8SL6PLLCR1_LOCKPS_MASK          (0x4U)
38529 #define DDRPHY_DX8SL6PLLCR1_LOCKPS_SHIFT         (2U)
38530 /*! LOCKPS - Lock Detector Phase Select
38531  */
38532 #define DDRPHY_DX8SL6PLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL6PLLCR1_LOCKPS_MASK)
38533 #define DDRPHY_DX8SL6PLLCR1_BYPVDD_MASK          (0x8U)
38534 #define DDRPHY_DX8SL6PLLCR1_BYPVDD_SHIFT         (3U)
38535 /*! BYPVDD - PLL VDD voltage level control
38536  */
38537 #define DDRPHY_DX8SL6PLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL6PLLCR1_BYPVDD_MASK)
38538 #define DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_MASK      (0x10U)
38539 #define DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_SHIFT     (4U)
38540 /*! BYPVREGDIG - Bypass PLL vreg_dig
38541  */
38542 #define DDRPHY_DX8SL6PLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_MASK)
38543 #define DDRPHY_DX8SL6PLLCR1_BYPVREGCP_MASK       (0x20U)
38544 #define DDRPHY_DX8SL6PLLCR1_BYPVREGCP_SHIFT      (5U)
38545 /*! BYPVREGCP - Bypass PLL vreg_cp
38546  */
38547 #define DDRPHY_DX8SL6PLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL6PLLCR1_BYPVREGCP_MASK)
38548 #define DDRPHY_DX8SL6PLLCR1_PLLPROG_MASK         (0x3FFFC0U)
38549 #define DDRPHY_DX8SL6PLLCR1_PLLPROG_SHIFT        (6U)
38550 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
38551  */
38552 #define DDRPHY_DX8SL6PLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL6PLLCR1_PLLPROG_MASK)
38553 #define DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
38554 #define DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_SHIFT (22U)
38555 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
38556  */
38557 #define DDRPHY_DX8SL6PLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_MASK)
38558 /*! @} */
38559 
38560 /*! @name DX8SL6PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
38561 /*! @{ */
38562 #define DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
38563 #define DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_SHIFT   (0U)
38564 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
38565  */
38566 #define DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_MASK)
38567 /*! @} */
38568 
38569 /*! @name DX8SL6PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
38570 /*! @{ */
38571 #define DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
38572 #define DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_SHIFT  (0U)
38573 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
38574  */
38575 #define DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_MASK)
38576 /*! @} */
38577 
38578 /*! @name DX8SL6PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
38579 /*! @{ */
38580 #define DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
38581 #define DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_SHIFT  (0U)
38582 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
38583  */
38584 #define DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_MASK)
38585 /*! @} */
38586 
38587 /*! @name DX8SL6PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
38588 /*! @{ */
38589 #define DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
38590 #define DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_SHIFT (0U)
38591 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
38592  */
38593 #define DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_MASK)
38594 #define DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
38595 #define DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_SHIFT  (8U)
38596 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
38597  */
38598 #define DDRPHY_DX8SL6PLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_MASK)
38599 /*! @} */
38600 
38601 /*! @name DX8SL6DQSCTL - DATX8 0-1 DQS Control Register */
38602 /*! @{ */
38603 #define DDRPHY_DX8SL6DQSCTL_DQSRES_MASK          (0xFU)
38604 #define DDRPHY_DX8SL6DQSCTL_DQSRES_SHIFT         (0U)
38605 /*! DQSRES - DQS Resistor
38606  */
38607 #define DDRPHY_DX8SL6DQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DQSRES_MASK)
38608 #define DDRPHY_DX8SL6DQSCTL_DQSNRES_MASK         (0xF0U)
38609 #define DDRPHY_DX8SL6DQSCTL_DQSNRES_SHIFT        (4U)
38610 /*! DQSNRES - DQS_N Resistor
38611  */
38612 #define DDRPHY_DX8SL6DQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DQSNRES_MASK)
38613 #define DDRPHY_DX8SL6DQSCTL_DXSR_MASK            (0x300U)
38614 #define DDRPHY_DX8SL6DQSCTL_DXSR_SHIFT           (8U)
38615 /*! DXSR - Data Slew Rate
38616  */
38617 #define DDRPHY_DX8SL6DQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DXSR_MASK)
38618 #define DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_MASK  (0x1C00U)
38619 #define DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_SHIFT (10U)
38620 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
38621  */
38622 #define DDRPHY_DX8SL6DQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_MASK)
38623 #define DDRPHY_DX8SL6DQSCTL_UDQIOM_MASK          (0x2000U)
38624 #define DDRPHY_DX8SL6DQSCTL_UDQIOM_SHIFT         (13U)
38625 /*! UDQIOM - Unused DQ I/O Mode
38626  */
38627 #define DDRPHY_DX8SL6DQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL6DQSCTL_UDQIOM_MASK)
38628 #define DDRPHY_DX8SL6DQSCTL_QSCNTEN_MASK         (0x4000U)
38629 #define DDRPHY_DX8SL6DQSCTL_QSCNTEN_SHIFT        (14U)
38630 /*! QSCNTEN - QS Counter Enable
38631  */
38632 #define DDRPHY_DX8SL6DQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL6DQSCTL_QSCNTEN_MASK)
38633 #define DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_MASK  (0x18000U)
38634 #define DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_SHIFT (15U)
38635 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
38636  */
38637 #define DDRPHY_DX8SL6DQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_MASK)
38638 #define DDRPHY_DX8SL6DQSCTL_LPIOPD_MASK          (0x20000U)
38639 #define DDRPHY_DX8SL6DQSCTL_LPIOPD_SHIFT         (17U)
38640 /*! LPIOPD - Low Power I/O Power Down
38641  */
38642 #define DDRPHY_DX8SL6DQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL6DQSCTL_LPIOPD_MASK)
38643 #define DDRPHY_DX8SL6DQSCTL_LPPLLPD_MASK         (0x40000U)
38644 #define DDRPHY_DX8SL6DQSCTL_LPPLLPD_SHIFT        (18U)
38645 /*! LPPLLPD - Low Power PLL Power Down
38646  */
38647 #define DDRPHY_DX8SL6DQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL6DQSCTL_LPPLLPD_MASK)
38648 #define DDRPHY_DX8SL6DQSCTL_DQSGX_MASK           (0x180000U)
38649 #define DDRPHY_DX8SL6DQSCTL_DQSGX_SHIFT          (19U)
38650 /*! DQSGX - DQS Gate Extension
38651  */
38652 #define DDRPHY_DX8SL6DQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DQSGX_MASK)
38653 #define DDRPHY_DX8SL6DQSCTL_WRRMODE_MASK         (0x200000U)
38654 #define DDRPHY_DX8SL6DQSCTL_WRRMODE_SHIFT        (21U)
38655 /*! WRRMODE - Write Path Rise-to-Rise Mode
38656  */
38657 #define DDRPHY_DX8SL6DQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL6DQSCTL_WRRMODE_MASK)
38658 #define DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_MASK  (0xC00000U)
38659 #define DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_SHIFT (22U)
38660 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
38661  */
38662 #define DDRPHY_DX8SL6DQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_MASK)
38663 #define DDRPHY_DX8SL6DQSCTL_RRRMODE_MASK         (0x1000000U)
38664 #define DDRPHY_DX8SL6DQSCTL_RRRMODE_SHIFT        (24U)
38665 /*! RRRMODE - Read Path Rise-to-Rise Mode
38666  */
38667 #define DDRPHY_DX8SL6DQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RRRMODE_MASK)
38668 #define DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
38669 #define DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_SHIFT (25U)
38670 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
38671  */
38672 #define DDRPHY_DX8SL6DQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_MASK)
38673 /*! @} */
38674 
38675 /*! @name DX8SL6TRNCTL - DATX8 0-1 Training Control Register */
38676 /*! @{ */
38677 #define DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
38678 #define DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_SHIFT  (0U)
38679 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
38680  */
38681 #define DDRPHY_DX8SL6TRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_MASK)
38682 /*! @} */
38683 
38684 /*! @name DX8SL6DDLCTL - DATX8 0-1 DDL Control Register */
38685 /*! @{ */
38686 #define DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_MASK      (0x3U)
38687 #define DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_SHIFT     (0U)
38688 /*! DDLBYPMODE - Controls DDL Bypass Mode
38689  */
38690 #define DDRPHY_DX8SL6DDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_MASK)
38691 #define DDRPHY_DX8SL6DDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
38692 #define DDRPHY_DX8SL6DDLCTL_DXDDLBYP_SHIFT       (2U)
38693 /*! DXDDLBYP - DATX8 DDL Bypass
38694  */
38695 #define DDRPHY_DX8SL6DDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DXDDLBYP_MASK)
38696 #define DDRPHY_DX8SL6DDLCTL_DXDDLLD_MASK         (0x7C0000U)
38697 #define DDRPHY_DX8SL6DDLCTL_DXDDLLD_SHIFT        (18U)
38698 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
38699  */
38700 #define DDRPHY_DX8SL6DDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DXDDLLD_MASK)
38701 #define DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_MASK  (0x1800000U)
38702 #define DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_SHIFT (23U)
38703 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
38704  */
38705 #define DDRPHY_DX8SL6DDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_MASK)
38706 #define DDRPHY_DX8SL6DDLCTL_DXDDLLDT_MASK        (0x2000000U)
38707 #define DDRPHY_DX8SL6DDLCTL_DXDDLLDT_SHIFT       (25U)
38708 /*! DXDDLLDT - DX DDL Load Type
38709  */
38710 #define DDRPHY_DX8SL6DDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DXDDLLDT_MASK)
38711 #define DDRPHY_DX8SL6DDLCTL_DLYLDTM_MASK         (0x4000000U)
38712 #define DDRPHY_DX8SL6DDLCTL_DLYLDTM_SHIFT        (26U)
38713 /*! DLYLDTM - Delay Load Timing
38714  */
38715 #define DDRPHY_DX8SL6DDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DLYLDTM_MASK)
38716 #define DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
38717 #define DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_SHIFT (27U)
38718 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
38719  */
38720 #define DDRPHY_DX8SL6DDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_MASK)
38721 /*! @} */
38722 
38723 /*! @name DX8SL6DXCTL1 - DATX8 0-1 DX Control Register 1 */
38724 /*! @{ */
38725 #define DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
38726 #define DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_SHIFT  (0U)
38727 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
38728  */
38729 #define DDRPHY_DX8SL6DXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_MASK)
38730 #define DDRPHY_DX8SL6DXCTL1_DXTMODE_MASK         (0x10000U)
38731 #define DDRPHY_DX8SL6DXCTL1_DXTMODE_SHIFT        (16U)
38732 /*! DXTMODE - DATX8 Test Mode
38733  */
38734 #define DDRPHY_DX8SL6DXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXTMODE_MASK)
38735 #define DDRPHY_DX8SL6DXCTL1_DXGDBYP_MASK         (0x20000U)
38736 #define DDRPHY_DX8SL6DXCTL1_DXGDBYP_SHIFT        (17U)
38737 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
38738  */
38739 #define DDRPHY_DX8SL6DXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXGDBYP_MASK)
38740 #define DDRPHY_DX8SL6DXCTL1_DXQSDBYP_MASK        (0x40000U)
38741 #define DDRPHY_DX8SL6DXCTL1_DXQSDBYP_SHIFT       (18U)
38742 /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
38743  */
38744 #define DDRPHY_DX8SL6DXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXQSDBYP_MASK)
38745 #define DDRPHY_DX8SL6DXCTL1_DXGSMD_MASK          (0x80000U)
38746 #define DDRPHY_DX8SL6DXCTL1_DXGSMD_SHIFT         (19U)
38747 /*! DXGSMD - Read DQS Gating Status Mode
38748  */
38749 #define DDRPHY_DX8SL6DXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXGSMD_MASK)
38750 #define DDRPHY_DX8SL6DXCTL1_DXDTOSEL_MASK        (0x300000U)
38751 #define DDRPHY_DX8SL6DXCTL1_DXDTOSEL_SHIFT       (20U)
38752 /*! DXDTOSEL - DATX8 Digital Test Output Select
38753  */
38754 #define DDRPHY_DX8SL6DXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXDTOSEL_MASK)
38755 #define DDRPHY_DX8SL6DXCTL1_RESERVED_22_MASK     (0x400000U)
38756 #define DDRPHY_DX8SL6DXCTL1_RESERVED_22_SHIFT    (22U)
38757 /*! RESERVED_22 - Reserved. Return zeroes on reads.
38758  */
38759 #define DDRPHY_DX8SL6DXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL6DXCTL1_RESERVED_22_MASK)
38760 #define DDRPHY_DX8SL6DXCTL1_DXRCLKMD_MASK        (0x800000U)
38761 #define DDRPHY_DX8SL6DXCTL1_DXRCLKMD_SHIFT       (23U)
38762 /*! DXRCLKMD - DATX8 Read Clock Mode
38763  */
38764 #define DDRPHY_DX8SL6DXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXRCLKMD_MASK)
38765 #define DDRPHY_DX8SL6DXCTL1_DXCALCLK_MASK        (0x1000000U)
38766 #define DDRPHY_DX8SL6DXCTL1_DXCALCLK_SHIFT       (24U)
38767 /*! DXCALCLK - DATX Calibration Clock Select
38768  */
38769 #define DDRPHY_DX8SL6DXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXCALCLK_MASK)
38770 #define DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
38771 #define DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_SHIFT (25U)
38772 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
38773  */
38774 #define DDRPHY_DX8SL6DXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_MASK)
38775 /*! @} */
38776 
38777 /*! @name DX8SL6DXCTL2 - DATX8 0-1 DX Control Register 2 */
38778 /*! @{ */
38779 #define DDRPHY_DX8SL6DXCTL2_RESERVED_0_MASK      (0x1U)
38780 #define DDRPHY_DX8SL6DXCTL2_RESERVED_0_SHIFT     (0U)
38781 /*! RESERVED_0 - Reserved. Return zeroes on reads.
38782  */
38783 #define DDRPHY_DX8SL6DXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_0_MASK)
38784 #define DDRPHY_DX8SL6DXCTL2_DQSGLB_MASK          (0x6U)
38785 #define DDRPHY_DX8SL6DXCTL2_DQSGLB_SHIFT         (1U)
38786 /*! DQSGLB - Read DQS Gate I/O Loopback
38787  */
38788 #define DDRPHY_DX8SL6DXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL6DXCTL2_DQSGLB_MASK)
38789 #define DDRPHY_DX8SL6DXCTL2_DISRST_MASK          (0x8U)
38790 #define DDRPHY_DX8SL6DXCTL2_DISRST_SHIFT         (3U)
38791 /*! DISRST - Disables the Read FIFO Reset
38792  */
38793 #define DDRPHY_DX8SL6DXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL6DXCTL2_DISRST_MASK)
38794 #define DDRPHY_DX8SL6DXCTL2_RDMODE_MASK          (0x30U)
38795 #define DDRPHY_DX8SL6DXCTL2_RDMODE_SHIFT         (4U)
38796 /*! RDMODE - DATX8 Receive FIFO Read Mode
38797  */
38798 #define DDRPHY_DX8SL6DXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RDMODE_MASK)
38799 #define DDRPHY_DX8SL6DXCTL2_PRFBYP_MASK          (0x40U)
38800 #define DDRPHY_DX8SL6DXCTL2_PRFBYP_SHIFT         (6U)
38801 /*! PRFBYP - PUB Read FIFO Bypass
38802  */
38803 #define DDRPHY_DX8SL6DXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL6DXCTL2_PRFBYP_MASK)
38804 #define DDRPHY_DX8SL6DXCTL2_WDBI_MASK            (0x80U)
38805 #define DDRPHY_DX8SL6DXCTL2_WDBI_SHIFT           (7U)
38806 /*! WDBI - Write Data Bus Inversion Enable
38807  */
38808 #define DDRPHY_DX8SL6DXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL6DXCTL2_WDBI_MASK)
38809 #define DDRPHY_DX8SL6DXCTL2_RDBI_MASK            (0x100U)
38810 #define DDRPHY_DX8SL6DXCTL2_RDBI_SHIFT           (8U)
38811 /*! RDBI - Read Data Bus Inversion Enable
38812  */
38813 #define DDRPHY_DX8SL6DXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RDBI_MASK)
38814 #define DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
38815 #define DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
38816 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
38817  */
38818 #define DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_MASK)
38819 #define DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_MASK  (0x6000U)
38820 #define DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_SHIFT (13U)
38821 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
38822  */
38823 #define DDRPHY_DX8SL6DXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_MASK)
38824 #define DDRPHY_DX8SL6DXCTL2_IOLB_MASK            (0x8000U)
38825 #define DDRPHY_DX8SL6DXCTL2_IOLB_SHIFT           (15U)
38826 /*! IOLB - I/O Loopback Select
38827  */
38828 #define DDRPHY_DX8SL6DXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL6DXCTL2_IOLB_MASK)
38829 #define DDRPHY_DX8SL6DXCTL2_IOAG_MASK            (0x10000U)
38830 #define DDRPHY_DX8SL6DXCTL2_IOAG_SHIFT           (16U)
38831 /*! IOAG - I/O Assisted Gate Select
38832  */
38833 #define DDRPHY_DX8SL6DXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL6DXCTL2_IOAG_MASK)
38834 #define DDRPHY_DX8SL6DXCTL2_RESERVED_17_MASK     (0x20000U)
38835 #define DDRPHY_DX8SL6DXCTL2_RESERVED_17_SHIFT    (17U)
38836 /*! RESERVED_17 - Reserved. Return zeroes on reads.
38837  */
38838 #define DDRPHY_DX8SL6DXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_17_MASK)
38839 #define DDRPHY_DX8SL6DXCTL2_PREOEX_MASK          (0xC0000U)
38840 #define DDRPHY_DX8SL6DXCTL2_PREOEX_SHIFT         (18U)
38841 /*! PREOEX - OE Extension during Pre-amble
38842  */
38843 #define DDRPHY_DX8SL6DXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL6DXCTL2_PREOEX_MASK)
38844 #define DDRPHY_DX8SL6DXCTL2_POSOEX_MASK          (0x700000U)
38845 #define DDRPHY_DX8SL6DXCTL2_POSOEX_SHIFT         (20U)
38846 /*! POSOEX - OX Extension during Post-amble
38847  */
38848 #define DDRPHY_DX8SL6DXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL6DXCTL2_POSOEX_MASK)
38849 #define DDRPHY_DX8SL6DXCTL2_CRDEN_MASK           (0x800000U)
38850 #define DDRPHY_DX8SL6DXCTL2_CRDEN_SHIFT          (23U)
38851 /*! CRDEN - Configurable Read Data Enable
38852  */
38853 #define DDRPHY_DX8SL6DXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL6DXCTL2_CRDEN_MASK)
38854 #define DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
38855 #define DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_SHIFT (24U)
38856 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
38857  */
38858 #define DDRPHY_DX8SL6DXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_MASK)
38859 /*! @} */
38860 
38861 /*! @name DX8SL6IOCR - DATX8 0-1 I/O Configuration Register */
38862 /*! @{ */
38863 #define DDRPHY_DX8SL6IOCR_DXRXM_MASK             (0x7FFU)
38864 #define DDRPHY_DX8SL6IOCR_DXRXM_SHIFT            (0U)
38865 /*! DXRXM - DX IO Receiver Mode
38866  */
38867 #define DDRPHY_DX8SL6IOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXRXM_MASK)
38868 #define DDRPHY_DX8SL6IOCR_DXTXM_MASK             (0x3FF800U)
38869 #define DDRPHY_DX8SL6IOCR_DXTXM_SHIFT            (11U)
38870 /*! DXTXM - DX IO Transmitter Mode
38871  */
38872 #define DDRPHY_DX8SL6IOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXTXM_MASK)
38873 #define DDRPHY_DX8SL6IOCR_DXIOM_MASK             (0x1C00000U)
38874 #define DDRPHY_DX8SL6IOCR_DXIOM_SHIFT            (22U)
38875 /*! DXIOM - DX IO Mode
38876  */
38877 #define DDRPHY_DX8SL6IOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXIOM_MASK)
38878 #define DDRPHY_DX8SL6IOCR_DXVREFIOM_MASK         (0xE000000U)
38879 #define DDRPHY_DX8SL6IOCR_DXVREFIOM_SHIFT        (25U)
38880 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
38881  */
38882 #define DDRPHY_DX8SL6IOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXVREFIOM_MASK)
38883 #define DDRPHY_DX8SL6IOCR_DXDACRANGE_MASK        (0x70000000U)
38884 #define DDRPHY_DX8SL6IOCR_DXDACRANGE_SHIFT       (28U)
38885 /*! DXDACRANGE - PVREF_DAC REFSEL range select
38886  */
38887 #define DDRPHY_DX8SL6IOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL6IOCR_DXDACRANGE_MASK)
38888 #define DDRPHY_DX8SL6IOCR_RESERVED_31_MASK       (0x80000000U)
38889 #define DDRPHY_DX8SL6IOCR_RESERVED_31_SHIFT      (31U)
38890 /*! RESERVED_31 - Reserved. Return zeroes on reads.
38891  */
38892 #define DDRPHY_DX8SL6IOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL6IOCR_RESERVED_31_MASK)
38893 /*! @} */
38894 
38895 /*! @name DX4SL6IOCR - DATX4 Slice 0-1 I/O Configuration Register */
38896 /*! @{ */
38897 #define DDRPHY_DX4SL6IOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
38898 #define DDRPHY_DX4SL6IOCR_RESERVED_31_0_SHIFT    (0U)
38899 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
38900  */
38901 #define DDRPHY_DX4SL6IOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL6IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL6IOCR_RESERVED_31_0_MASK)
38902 /*! @} */
38903 
38904 /*! @name DX8SL7OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
38905 /*! @{ */
38906 #define DDRPHY_DX8SL7OSC_OSCEN_MASK              (0x1U)
38907 #define DDRPHY_DX8SL7OSC_OSCEN_SHIFT             (0U)
38908 /*! OSCEN - Oscillator Enable
38909  */
38910 #define DDRPHY_DX8SL7OSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL7OSC_OSCEN_MASK)
38911 #define DDRPHY_DX8SL7OSC_OSCDIV_MASK             (0x1EU)
38912 #define DDRPHY_DX8SL7OSC_OSCDIV_SHIFT            (1U)
38913 /*! OSCDIV - Oscillator Mode Division
38914  */
38915 #define DDRPHY_DX8SL7OSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL7OSC_OSCDIV_MASK)
38916 #define DDRPHY_DX8SL7OSC_OSCWDL_MASK             (0x60U)
38917 #define DDRPHY_DX8SL7OSC_OSCWDL_SHIFT            (5U)
38918 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
38919  */
38920 #define DDRPHY_DX8SL7OSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL7OSC_OSCWDL_MASK)
38921 #define DDRPHY_DX8SL7OSC_RESERVED_8_7_MASK       (0x180U)
38922 #define DDRPHY_DX8SL7OSC_RESERVED_8_7_SHIFT      (7U)
38923 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
38924  */
38925 #define DDRPHY_DX8SL7OSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL7OSC_RESERVED_8_7_MASK)
38926 #define DDRPHY_DX8SL7OSC_OSCWDDL_MASK            (0x600U)
38927 #define DDRPHY_DX8SL7OSC_OSCWDDL_SHIFT           (9U)
38928 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
38929  */
38930 #define DDRPHY_DX8SL7OSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL7OSC_OSCWDDL_MASK)
38931 #define DDRPHY_DX8SL7OSC_RESERVED_12_11_MASK     (0x1800U)
38932 #define DDRPHY_DX8SL7OSC_RESERVED_12_11_SHIFT    (11U)
38933 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
38934  */
38935 #define DDRPHY_DX8SL7OSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL7OSC_RESERVED_12_11_MASK)
38936 #define DDRPHY_DX8SL7OSC_DLTMODE_MASK            (0x2000U)
38937 #define DDRPHY_DX8SL7OSC_DLTMODE_SHIFT           (13U)
38938 /*! DLTMODE - Delay Line Test Mode
38939  */
38940 #define DDRPHY_DX8SL7OSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL7OSC_DLTMODE_MASK)
38941 #define DDRPHY_DX8SL7OSC_DLTST_MASK              (0x4000U)
38942 #define DDRPHY_DX8SL7OSC_DLTST_SHIFT             (14U)
38943 /*! DLTST - Delay Line Test Start
38944  */
38945 #define DDRPHY_DX8SL7OSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_DLTST_SHIFT)) & DDRPHY_DX8SL7OSC_DLTST_MASK)
38946 #define DDRPHY_DX8SL7OSC_PHYFRST_MASK            (0x8000U)
38947 #define DDRPHY_DX8SL7OSC_PHYFRST_SHIFT           (15U)
38948 /*! PHYFRST - PHY FIFO Reset
38949  */
38950 #define DDRPHY_DX8SL7OSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL7OSC_PHYFRST_MASK)
38951 #define DDRPHY_DX8SL7OSC_PHYHRST_MASK            (0x10000U)
38952 #define DDRPHY_DX8SL7OSC_PHYHRST_SHIFT           (16U)
38953 /*! PHYHRST - PHY High-Speed Reset
38954  */
38955 #define DDRPHY_DX8SL7OSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL7OSC_PHYHRST_MASK)
38956 #define DDRPHY_DX8SL7OSC_LBDQSS_MASK             (0x20000U)
38957 #define DDRPHY_DX8SL7OSC_LBDQSS_SHIFT            (17U)
38958 /*! LBDQSS - Loopback DQS Shift
38959  */
38960 #define DDRPHY_DX8SL7OSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL7OSC_LBDQSS_MASK)
38961 #define DDRPHY_DX8SL7OSC_LBGDQS_MASK             (0xC0000U)
38962 #define DDRPHY_DX8SL7OSC_LBGDQS_SHIFT            (18U)
38963 /*! LBGDQS - Loopback DQS Gating
38964  */
38965 #define DDRPHY_DX8SL7OSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL7OSC_LBGDQS_MASK)
38966 #define DDRPHY_DX8SL7OSC_LBGSDQS_MASK            (0x100000U)
38967 #define DDRPHY_DX8SL7OSC_LBGSDQS_SHIFT           (20U)
38968 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
38969  */
38970 #define DDRPHY_DX8SL7OSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL7OSC_LBGSDQS_MASK)
38971 #define DDRPHY_DX8SL7OSC_LBMODE_MASK             (0x200000U)
38972 #define DDRPHY_DX8SL7OSC_LBMODE_SHIFT            (21U)
38973 /*! LBMODE - Loopback Mode
38974  */
38975 #define DDRPHY_DX8SL7OSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL7OSC_LBMODE_MASK)
38976 #define DDRPHY_DX8SL7OSC_CLKLEVEL_MASK           (0xC00000U)
38977 #define DDRPHY_DX8SL7OSC_CLKLEVEL_SHIFT          (22U)
38978 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
38979  */
38980 #define DDRPHY_DX8SL7OSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL7OSC_CLKLEVEL_MASK)
38981 #define DDRPHY_DX8SL7OSC_GATEDXCTLCLK_MASK       (0x3000000U)
38982 #define DDRPHY_DX8SL7OSC_GATEDXCTLCLK_SHIFT      (24U)
38983 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
38984  */
38985 #define DDRPHY_DX8SL7OSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL7OSC_GATEDXCTLCLK_MASK)
38986 #define DDRPHY_DX8SL7OSC_GATEDXDDRCLK_MASK       (0xC000000U)
38987 #define DDRPHY_DX8SL7OSC_GATEDXDDRCLK_SHIFT      (26U)
38988 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
38989  */
38990 #define DDRPHY_DX8SL7OSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL7OSC_GATEDXDDRCLK_MASK)
38991 #define DDRPHY_DX8SL7OSC_GATEDXRDCLK_MASK        (0x30000000U)
38992 #define DDRPHY_DX8SL7OSC_GATEDXRDCLK_SHIFT       (28U)
38993 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
38994  */
38995 #define DDRPHY_DX8SL7OSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL7OSC_GATEDXRDCLK_MASK)
38996 #define DDRPHY_DX8SL7OSC_RESERVED_31_30_MASK     (0xC0000000U)
38997 #define DDRPHY_DX8SL7OSC_RESERVED_31_30_SHIFT    (30U)
38998 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
38999  */
39000 #define DDRPHY_DX8SL7OSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL7OSC_RESERVED_31_30_MASK)
39001 /*! @} */
39002 
39003 /*! @name DX8SL7PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
39004 /*! @{ */
39005 #define DDRPHY_DX8SL7PLLCR0_DTC_MASK             (0xFU)
39006 #define DDRPHY_DX8SL7PLLCR0_DTC_SHIFT            (0U)
39007 /*! DTC - Digital Test Control
39008  */
39009 #define DDRPHY_DX8SL7PLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_DTC_MASK)
39010 #define DDRPHY_DX8SL7PLLCR0_ATC_MASK             (0xF0U)
39011 #define DDRPHY_DX8SL7PLLCR0_ATC_SHIFT            (4U)
39012 /*! ATC - Analog Test Control
39013  */
39014 #define DDRPHY_DX8SL7PLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_ATC_MASK)
39015 #define DDRPHY_DX8SL7PLLCR0_ATOEN_MASK           (0x100U)
39016 #define DDRPHY_DX8SL7PLLCR0_ATOEN_SHIFT          (8U)
39017 /*! ATOEN - Analog Test Enable (ATOEN)
39018  */
39019 #define DDRPHY_DX8SL7PLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL7PLLCR0_ATOEN_MASK)
39020 #define DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_MASK   (0xE00U)
39021 #define DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_SHIFT  (9U)
39022 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
39023  */
39024 #define DDRPHY_DX8SL7PLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_MASK)
39025 #define DDRPHY_DX8SL7PLLCR0_GSHIFT_MASK          (0x1000U)
39026 #define DDRPHY_DX8SL7PLLCR0_GSHIFT_SHIFT         (12U)
39027 /*! GSHIFT - Gear Shift
39028  */
39029 #define DDRPHY_DX8SL7PLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL7PLLCR0_GSHIFT_MASK)
39030 #define DDRPHY_DX8SL7PLLCR0_CPIC_MASK            (0x1E000U)
39031 #define DDRPHY_DX8SL7PLLCR0_CPIC_SHIFT           (13U)
39032 /*! CPIC - Charge Pump Integrating Current Control
39033  */
39034 #define DDRPHY_DX8SL7PLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_CPIC_MASK)
39035 #define DDRPHY_DX8SL7PLLCR0_CPPC_MASK            (0x7E0000U)
39036 #define DDRPHY_DX8SL7PLLCR0_CPPC_SHIFT           (17U)
39037 /*! CPPC - Charge Pump Proportional Current Control
39038  */
39039 #define DDRPHY_DX8SL7PLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_CPPC_MASK)
39040 #define DDRPHY_DX8SL7PLLCR0_RLOCKM_MASK          (0x800000U)
39041 #define DDRPHY_DX8SL7PLLCR0_RLOCKM_SHIFT         (23U)
39042 /*! RLOCKM - Relock Mode
39043  */
39044 #define DDRPHY_DX8SL7PLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL7PLLCR0_RLOCKM_MASK)
39045 #define DDRPHY_DX8SL7PLLCR0_FRQSEL_MASK          (0xF000000U)
39046 #define DDRPHY_DX8SL7PLLCR0_FRQSEL_SHIFT         (24U)
39047 /*! FRQSEL - PLL Frequency Select
39048  */
39049 #define DDRPHY_DX8SL7PLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL7PLLCR0_FRQSEL_MASK)
39050 #define DDRPHY_DX8SL7PLLCR0_RSTOPM_MASK          (0x10000000U)
39051 #define DDRPHY_DX8SL7PLLCR0_RSTOPM_SHIFT         (28U)
39052 /*! RSTOPM - Reference Stop Mode
39053  */
39054 #define DDRPHY_DX8SL7PLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL7PLLCR0_RSTOPM_MASK)
39055 #define DDRPHY_DX8SL7PLLCR0_PLLPD_MASK           (0x20000000U)
39056 #define DDRPHY_DX8SL7PLLCR0_PLLPD_SHIFT          (29U)
39057 /*! PLLPD - PLL Power Down
39058  */
39059 #define DDRPHY_DX8SL7PLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL7PLLCR0_PLLPD_MASK)
39060 #define DDRPHY_DX8SL7PLLCR0_PLLRST_MASK          (0x40000000U)
39061 #define DDRPHY_DX8SL7PLLCR0_PLLRST_SHIFT         (30U)
39062 /*! PLLRST - PLL Reset
39063  */
39064 #define DDRPHY_DX8SL7PLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL7PLLCR0_PLLRST_MASK)
39065 #define DDRPHY_DX8SL7PLLCR0_PLLBYP_MASK          (0x80000000U)
39066 #define DDRPHY_DX8SL7PLLCR0_PLLBYP_SHIFT         (31U)
39067 /*! PLLBYP - PLL Bypass
39068  */
39069 #define DDRPHY_DX8SL7PLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL7PLLCR0_PLLBYP_MASK)
39070 /*! @} */
39071 
39072 /*! @name DX8SL7PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
39073 /*! @{ */
39074 #define DDRPHY_DX8SL7PLLCR1_LOCKDS_MASK          (0x1U)
39075 #define DDRPHY_DX8SL7PLLCR1_LOCKDS_SHIFT         (0U)
39076 /*! LOCKDS - Lock Detector Select
39077  */
39078 #define DDRPHY_DX8SL7PLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL7PLLCR1_LOCKDS_MASK)
39079 #define DDRPHY_DX8SL7PLLCR1_LOCKCS_MASK          (0x2U)
39080 #define DDRPHY_DX8SL7PLLCR1_LOCKCS_SHIFT         (1U)
39081 /*! LOCKCS - Lock Detector Counter Select
39082  */
39083 #define DDRPHY_DX8SL7PLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL7PLLCR1_LOCKCS_MASK)
39084 #define DDRPHY_DX8SL7PLLCR1_LOCKPS_MASK          (0x4U)
39085 #define DDRPHY_DX8SL7PLLCR1_LOCKPS_SHIFT         (2U)
39086 /*! LOCKPS - Lock Detector Phase Select
39087  */
39088 #define DDRPHY_DX8SL7PLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL7PLLCR1_LOCKPS_MASK)
39089 #define DDRPHY_DX8SL7PLLCR1_BYPVDD_MASK          (0x8U)
39090 #define DDRPHY_DX8SL7PLLCR1_BYPVDD_SHIFT         (3U)
39091 /*! BYPVDD - PLL VDD voltage level control
39092  */
39093 #define DDRPHY_DX8SL7PLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL7PLLCR1_BYPVDD_MASK)
39094 #define DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_MASK      (0x10U)
39095 #define DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_SHIFT     (4U)
39096 /*! BYPVREGDIG - Bypass PLL vreg_dig
39097  */
39098 #define DDRPHY_DX8SL7PLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_MASK)
39099 #define DDRPHY_DX8SL7PLLCR1_BYPVREGCP_MASK       (0x20U)
39100 #define DDRPHY_DX8SL7PLLCR1_BYPVREGCP_SHIFT      (5U)
39101 /*! BYPVREGCP - Bypass PLL vreg_cp
39102  */
39103 #define DDRPHY_DX8SL7PLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL7PLLCR1_BYPVREGCP_MASK)
39104 #define DDRPHY_DX8SL7PLLCR1_PLLPROG_MASK         (0x3FFFC0U)
39105 #define DDRPHY_DX8SL7PLLCR1_PLLPROG_SHIFT        (6U)
39106 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
39107  */
39108 #define DDRPHY_DX8SL7PLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL7PLLCR1_PLLPROG_MASK)
39109 #define DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
39110 #define DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_SHIFT (22U)
39111 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
39112  */
39113 #define DDRPHY_DX8SL7PLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_MASK)
39114 /*! @} */
39115 
39116 /*! @name DX8SL7PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
39117 /*! @{ */
39118 #define DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
39119 #define DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_SHIFT   (0U)
39120 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
39121  */
39122 #define DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_MASK)
39123 /*! @} */
39124 
39125 /*! @name DX8SL7PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
39126 /*! @{ */
39127 #define DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
39128 #define DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_SHIFT  (0U)
39129 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
39130  */
39131 #define DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_MASK)
39132 /*! @} */
39133 
39134 /*! @name DX8SL7PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
39135 /*! @{ */
39136 #define DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
39137 #define DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_SHIFT  (0U)
39138 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
39139  */
39140 #define DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_MASK)
39141 /*! @} */
39142 
39143 /*! @name DX8SL7PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
39144 /*! @{ */
39145 #define DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
39146 #define DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_SHIFT (0U)
39147 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
39148  */
39149 #define DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_MASK)
39150 #define DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
39151 #define DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_SHIFT  (8U)
39152 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
39153  */
39154 #define DDRPHY_DX8SL7PLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_MASK)
39155 /*! @} */
39156 
39157 /*! @name DX8SL7DQSCTL - DATX8 0-1 DQS Control Register */
39158 /*! @{ */
39159 #define DDRPHY_DX8SL7DQSCTL_DQSRES_MASK          (0xFU)
39160 #define DDRPHY_DX8SL7DQSCTL_DQSRES_SHIFT         (0U)
39161 /*! DQSRES - DQS Resistor
39162  */
39163 #define DDRPHY_DX8SL7DQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DQSRES_MASK)
39164 #define DDRPHY_DX8SL7DQSCTL_DQSNRES_MASK         (0xF0U)
39165 #define DDRPHY_DX8SL7DQSCTL_DQSNRES_SHIFT        (4U)
39166 /*! DQSNRES - DQS_N Resistor
39167  */
39168 #define DDRPHY_DX8SL7DQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DQSNRES_MASK)
39169 #define DDRPHY_DX8SL7DQSCTL_DXSR_MASK            (0x300U)
39170 #define DDRPHY_DX8SL7DQSCTL_DXSR_SHIFT           (8U)
39171 /*! DXSR - Data Slew Rate
39172  */
39173 #define DDRPHY_DX8SL7DQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DXSR_MASK)
39174 #define DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_MASK  (0x1C00U)
39175 #define DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_SHIFT (10U)
39176 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
39177  */
39178 #define DDRPHY_DX8SL7DQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_MASK)
39179 #define DDRPHY_DX8SL7DQSCTL_UDQIOM_MASK          (0x2000U)
39180 #define DDRPHY_DX8SL7DQSCTL_UDQIOM_SHIFT         (13U)
39181 /*! UDQIOM - Unused DQ I/O Mode
39182  */
39183 #define DDRPHY_DX8SL7DQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL7DQSCTL_UDQIOM_MASK)
39184 #define DDRPHY_DX8SL7DQSCTL_QSCNTEN_MASK         (0x4000U)
39185 #define DDRPHY_DX8SL7DQSCTL_QSCNTEN_SHIFT        (14U)
39186 /*! QSCNTEN - QS Counter Enable
39187  */
39188 #define DDRPHY_DX8SL7DQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL7DQSCTL_QSCNTEN_MASK)
39189 #define DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_MASK  (0x18000U)
39190 #define DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_SHIFT (15U)
39191 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
39192  */
39193 #define DDRPHY_DX8SL7DQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_MASK)
39194 #define DDRPHY_DX8SL7DQSCTL_LPIOPD_MASK          (0x20000U)
39195 #define DDRPHY_DX8SL7DQSCTL_LPIOPD_SHIFT         (17U)
39196 /*! LPIOPD - Low Power I/O Power Down
39197  */
39198 #define DDRPHY_DX8SL7DQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL7DQSCTL_LPIOPD_MASK)
39199 #define DDRPHY_DX8SL7DQSCTL_LPPLLPD_MASK         (0x40000U)
39200 #define DDRPHY_DX8SL7DQSCTL_LPPLLPD_SHIFT        (18U)
39201 /*! LPPLLPD - Low Power PLL Power Down
39202  */
39203 #define DDRPHY_DX8SL7DQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL7DQSCTL_LPPLLPD_MASK)
39204 #define DDRPHY_DX8SL7DQSCTL_DQSGX_MASK           (0x180000U)
39205 #define DDRPHY_DX8SL7DQSCTL_DQSGX_SHIFT          (19U)
39206 /*! DQSGX - DQS Gate Extension
39207  */
39208 #define DDRPHY_DX8SL7DQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DQSGX_MASK)
39209 #define DDRPHY_DX8SL7DQSCTL_WRRMODE_MASK         (0x200000U)
39210 #define DDRPHY_DX8SL7DQSCTL_WRRMODE_SHIFT        (21U)
39211 /*! WRRMODE - Write Path Rise-to-Rise Mode
39212  */
39213 #define DDRPHY_DX8SL7DQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL7DQSCTL_WRRMODE_MASK)
39214 #define DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_MASK  (0xC00000U)
39215 #define DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_SHIFT (22U)
39216 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
39217  */
39218 #define DDRPHY_DX8SL7DQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_MASK)
39219 #define DDRPHY_DX8SL7DQSCTL_RRRMODE_MASK         (0x1000000U)
39220 #define DDRPHY_DX8SL7DQSCTL_RRRMODE_SHIFT        (24U)
39221 /*! RRRMODE - Read Path Rise-to-Rise Mode
39222  */
39223 #define DDRPHY_DX8SL7DQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RRRMODE_MASK)
39224 #define DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
39225 #define DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_SHIFT (25U)
39226 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
39227  */
39228 #define DDRPHY_DX8SL7DQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_MASK)
39229 /*! @} */
39230 
39231 /*! @name DX8SL7TRNCTL - DATX8 0-1 Training Control Register */
39232 /*! @{ */
39233 #define DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
39234 #define DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_SHIFT  (0U)
39235 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
39236  */
39237 #define DDRPHY_DX8SL7TRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_MASK)
39238 /*! @} */
39239 
39240 /*! @name DX8SL7DDLCTL - DATX8 0-1 DDL Control Register */
39241 /*! @{ */
39242 #define DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_MASK      (0x3U)
39243 #define DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_SHIFT     (0U)
39244 /*! DDLBYPMODE - Controls DDL Bypass Mode
39245  */
39246 #define DDRPHY_DX8SL7DDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_MASK)
39247 #define DDRPHY_DX8SL7DDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
39248 #define DDRPHY_DX8SL7DDLCTL_DXDDLBYP_SHIFT       (2U)
39249 /*! DXDDLBYP - DATX8 DDL Bypass
39250  */
39251 #define DDRPHY_DX8SL7DDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DXDDLBYP_MASK)
39252 #define DDRPHY_DX8SL7DDLCTL_DXDDLLD_MASK         (0x7C0000U)
39253 #define DDRPHY_DX8SL7DDLCTL_DXDDLLD_SHIFT        (18U)
39254 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
39255  */
39256 #define DDRPHY_DX8SL7DDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DXDDLLD_MASK)
39257 #define DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_MASK  (0x1800000U)
39258 #define DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_SHIFT (23U)
39259 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
39260  */
39261 #define DDRPHY_DX8SL7DDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_MASK)
39262 #define DDRPHY_DX8SL7DDLCTL_DXDDLLDT_MASK        (0x2000000U)
39263 #define DDRPHY_DX8SL7DDLCTL_DXDDLLDT_SHIFT       (25U)
39264 /*! DXDDLLDT - DX DDL Load Type
39265  */
39266 #define DDRPHY_DX8SL7DDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DXDDLLDT_MASK)
39267 #define DDRPHY_DX8SL7DDLCTL_DLYLDTM_MASK         (0x4000000U)
39268 #define DDRPHY_DX8SL7DDLCTL_DLYLDTM_SHIFT        (26U)
39269 /*! DLYLDTM - Delay Load Timing
39270  */
39271 #define DDRPHY_DX8SL7DDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DLYLDTM_MASK)
39272 #define DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
39273 #define DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_SHIFT (27U)
39274 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
39275  */
39276 #define DDRPHY_DX8SL7DDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_MASK)
39277 /*! @} */
39278 
39279 /*! @name DX8SL7DXCTL1 - DATX8 0-1 DX Control Register 1 */
39280 /*! @{ */
39281 #define DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
39282 #define DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_SHIFT  (0U)
39283 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
39284  */
39285 #define DDRPHY_DX8SL7DXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_MASK)
39286 #define DDRPHY_DX8SL7DXCTL1_DXTMODE_MASK         (0x10000U)
39287 #define DDRPHY_DX8SL7DXCTL1_DXTMODE_SHIFT        (16U)
39288 /*! DXTMODE - DATX8 Test Mode
39289  */
39290 #define DDRPHY_DX8SL7DXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXTMODE_MASK)
39291 #define DDRPHY_DX8SL7DXCTL1_DXGDBYP_MASK         (0x20000U)
39292 #define DDRPHY_DX8SL7DXCTL1_DXGDBYP_SHIFT        (17U)
39293 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
39294  */
39295 #define DDRPHY_DX8SL7DXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXGDBYP_MASK)
39296 #define DDRPHY_DX8SL7DXCTL1_DXQSDBYP_MASK        (0x40000U)
39297 #define DDRPHY_DX8SL7DXCTL1_DXQSDBYP_SHIFT       (18U)
39298 /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
39299  */
39300 #define DDRPHY_DX8SL7DXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXQSDBYP_MASK)
39301 #define DDRPHY_DX8SL7DXCTL1_DXGSMD_MASK          (0x80000U)
39302 #define DDRPHY_DX8SL7DXCTL1_DXGSMD_SHIFT         (19U)
39303 /*! DXGSMD - Read DQS Gating Status Mode
39304  */
39305 #define DDRPHY_DX8SL7DXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXGSMD_MASK)
39306 #define DDRPHY_DX8SL7DXCTL1_DXDTOSEL_MASK        (0x300000U)
39307 #define DDRPHY_DX8SL7DXCTL1_DXDTOSEL_SHIFT       (20U)
39308 /*! DXDTOSEL - DATX8 Digital Test Output Select
39309  */
39310 #define DDRPHY_DX8SL7DXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXDTOSEL_MASK)
39311 #define DDRPHY_DX8SL7DXCTL1_RESERVED_22_MASK     (0x400000U)
39312 #define DDRPHY_DX8SL7DXCTL1_RESERVED_22_SHIFT    (22U)
39313 /*! RESERVED_22 - Reserved. Return zeroes on reads.
39314  */
39315 #define DDRPHY_DX8SL7DXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL7DXCTL1_RESERVED_22_MASK)
39316 #define DDRPHY_DX8SL7DXCTL1_DXRCLKMD_MASK        (0x800000U)
39317 #define DDRPHY_DX8SL7DXCTL1_DXRCLKMD_SHIFT       (23U)
39318 /*! DXRCLKMD - DATX8 Read Clock Mode
39319  */
39320 #define DDRPHY_DX8SL7DXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXRCLKMD_MASK)
39321 #define DDRPHY_DX8SL7DXCTL1_DXCALCLK_MASK        (0x1000000U)
39322 #define DDRPHY_DX8SL7DXCTL1_DXCALCLK_SHIFT       (24U)
39323 /*! DXCALCLK - DATX Calibration Clock Select
39324  */
39325 #define DDRPHY_DX8SL7DXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXCALCLK_MASK)
39326 #define DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
39327 #define DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_SHIFT (25U)
39328 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
39329  */
39330 #define DDRPHY_DX8SL7DXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_MASK)
39331 /*! @} */
39332 
39333 /*! @name DX8SL7DXCTL2 - DATX8 0-1 DX Control Register 2 */
39334 /*! @{ */
39335 #define DDRPHY_DX8SL7DXCTL2_RESERVED_0_MASK      (0x1U)
39336 #define DDRPHY_DX8SL7DXCTL2_RESERVED_0_SHIFT     (0U)
39337 /*! RESERVED_0 - Reserved. Return zeroes on reads.
39338  */
39339 #define DDRPHY_DX8SL7DXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_0_MASK)
39340 #define DDRPHY_DX8SL7DXCTL2_DQSGLB_MASK          (0x6U)
39341 #define DDRPHY_DX8SL7DXCTL2_DQSGLB_SHIFT         (1U)
39342 /*! DQSGLB - Read DQS Gate I/O Loopback
39343  */
39344 #define DDRPHY_DX8SL7DXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL7DXCTL2_DQSGLB_MASK)
39345 #define DDRPHY_DX8SL7DXCTL2_DISRST_MASK          (0x8U)
39346 #define DDRPHY_DX8SL7DXCTL2_DISRST_SHIFT         (3U)
39347 /*! DISRST - Disables the Read FIFO Reset
39348  */
39349 #define DDRPHY_DX8SL7DXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL7DXCTL2_DISRST_MASK)
39350 #define DDRPHY_DX8SL7DXCTL2_RDMODE_MASK          (0x30U)
39351 #define DDRPHY_DX8SL7DXCTL2_RDMODE_SHIFT         (4U)
39352 /*! RDMODE - DATX8 Receive FIFO Read Mode
39353  */
39354 #define DDRPHY_DX8SL7DXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RDMODE_MASK)
39355 #define DDRPHY_DX8SL7DXCTL2_PRFBYP_MASK          (0x40U)
39356 #define DDRPHY_DX8SL7DXCTL2_PRFBYP_SHIFT         (6U)
39357 /*! PRFBYP - PUB Read FIFO Bypass
39358  */
39359 #define DDRPHY_DX8SL7DXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL7DXCTL2_PRFBYP_MASK)
39360 #define DDRPHY_DX8SL7DXCTL2_WDBI_MASK            (0x80U)
39361 #define DDRPHY_DX8SL7DXCTL2_WDBI_SHIFT           (7U)
39362 /*! WDBI - Write Data Bus Inversion Enable
39363  */
39364 #define DDRPHY_DX8SL7DXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL7DXCTL2_WDBI_MASK)
39365 #define DDRPHY_DX8SL7DXCTL2_RDBI_MASK            (0x100U)
39366 #define DDRPHY_DX8SL7DXCTL2_RDBI_SHIFT           (8U)
39367 /*! RDBI - Read Data Bus Inversion Enable
39368  */
39369 #define DDRPHY_DX8SL7DXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RDBI_MASK)
39370 #define DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
39371 #define DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
39372 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
39373  */
39374 #define DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_MASK)
39375 #define DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_MASK  (0x6000U)
39376 #define DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_SHIFT (13U)
39377 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
39378  */
39379 #define DDRPHY_DX8SL7DXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_MASK)
39380 #define DDRPHY_DX8SL7DXCTL2_IOLB_MASK            (0x8000U)
39381 #define DDRPHY_DX8SL7DXCTL2_IOLB_SHIFT           (15U)
39382 /*! IOLB - I/O Loopback Select
39383  */
39384 #define DDRPHY_DX8SL7DXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL7DXCTL2_IOLB_MASK)
39385 #define DDRPHY_DX8SL7DXCTL2_IOAG_MASK            (0x10000U)
39386 #define DDRPHY_DX8SL7DXCTL2_IOAG_SHIFT           (16U)
39387 /*! IOAG - I/O Assisted Gate Select
39388  */
39389 #define DDRPHY_DX8SL7DXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL7DXCTL2_IOAG_MASK)
39390 #define DDRPHY_DX8SL7DXCTL2_RESERVED_17_MASK     (0x20000U)
39391 #define DDRPHY_DX8SL7DXCTL2_RESERVED_17_SHIFT    (17U)
39392 /*! RESERVED_17 - Reserved. Return zeroes on reads.
39393  */
39394 #define DDRPHY_DX8SL7DXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_17_MASK)
39395 #define DDRPHY_DX8SL7DXCTL2_PREOEX_MASK          (0xC0000U)
39396 #define DDRPHY_DX8SL7DXCTL2_PREOEX_SHIFT         (18U)
39397 /*! PREOEX - OE Extension during Pre-amble
39398  */
39399 #define DDRPHY_DX8SL7DXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL7DXCTL2_PREOEX_MASK)
39400 #define DDRPHY_DX8SL7DXCTL2_POSOEX_MASK          (0x700000U)
39401 #define DDRPHY_DX8SL7DXCTL2_POSOEX_SHIFT         (20U)
39402 /*! POSOEX - OX Extension during Post-amble
39403  */
39404 #define DDRPHY_DX8SL7DXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL7DXCTL2_POSOEX_MASK)
39405 #define DDRPHY_DX8SL7DXCTL2_CRDEN_MASK           (0x800000U)
39406 #define DDRPHY_DX8SL7DXCTL2_CRDEN_SHIFT          (23U)
39407 /*! CRDEN - Configurable Read Data Enable
39408  */
39409 #define DDRPHY_DX8SL7DXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL7DXCTL2_CRDEN_MASK)
39410 #define DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
39411 #define DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_SHIFT (24U)
39412 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
39413  */
39414 #define DDRPHY_DX8SL7DXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_MASK)
39415 /*! @} */
39416 
39417 /*! @name DX8SL7IOCR - DATX8 0-1 I/O Configuration Register */
39418 /*! @{ */
39419 #define DDRPHY_DX8SL7IOCR_DXRXM_MASK             (0x7FFU)
39420 #define DDRPHY_DX8SL7IOCR_DXRXM_SHIFT            (0U)
39421 /*! DXRXM - DX IO Receiver Mode
39422  */
39423 #define DDRPHY_DX8SL7IOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXRXM_MASK)
39424 #define DDRPHY_DX8SL7IOCR_DXTXM_MASK             (0x3FF800U)
39425 #define DDRPHY_DX8SL7IOCR_DXTXM_SHIFT            (11U)
39426 /*! DXTXM - DX IO Transmitter Mode
39427  */
39428 #define DDRPHY_DX8SL7IOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXTXM_MASK)
39429 #define DDRPHY_DX8SL7IOCR_DXIOM_MASK             (0x1C00000U)
39430 #define DDRPHY_DX8SL7IOCR_DXIOM_SHIFT            (22U)
39431 /*! DXIOM - DX IO Mode
39432  */
39433 #define DDRPHY_DX8SL7IOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXIOM_MASK)
39434 #define DDRPHY_DX8SL7IOCR_DXVREFIOM_MASK         (0xE000000U)
39435 #define DDRPHY_DX8SL7IOCR_DXVREFIOM_SHIFT        (25U)
39436 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
39437  */
39438 #define DDRPHY_DX8SL7IOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXVREFIOM_MASK)
39439 #define DDRPHY_DX8SL7IOCR_DXDACRANGE_MASK        (0x70000000U)
39440 #define DDRPHY_DX8SL7IOCR_DXDACRANGE_SHIFT       (28U)
39441 /*! DXDACRANGE - PVREF_DAC REFSEL range select
39442  */
39443 #define DDRPHY_DX8SL7IOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL7IOCR_DXDACRANGE_MASK)
39444 #define DDRPHY_DX8SL7IOCR_RESERVED_31_MASK       (0x80000000U)
39445 #define DDRPHY_DX8SL7IOCR_RESERVED_31_SHIFT      (31U)
39446 /*! RESERVED_31 - Reserved. Return zeroes on reads.
39447  */
39448 #define DDRPHY_DX8SL7IOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL7IOCR_RESERVED_31_MASK)
39449 /*! @} */
39450 
39451 /*! @name DX4SL7IOCR - DATX4 Slice 0-1 I/O Configuration Register */
39452 /*! @{ */
39453 #define DDRPHY_DX4SL7IOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
39454 #define DDRPHY_DX4SL7IOCR_RESERVED_31_0_SHIFT    (0U)
39455 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
39456  */
39457 #define DDRPHY_DX4SL7IOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL7IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL7IOCR_RESERVED_31_0_MASK)
39458 /*! @} */
39459 
39460 /*! @name DX8SL8OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
39461 /*! @{ */
39462 #define DDRPHY_DX8SL8OSC_OSCEN_MASK              (0x1U)
39463 #define DDRPHY_DX8SL8OSC_OSCEN_SHIFT             (0U)
39464 /*! OSCEN - Oscillator Enable
39465  */
39466 #define DDRPHY_DX8SL8OSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL8OSC_OSCEN_MASK)
39467 #define DDRPHY_DX8SL8OSC_OSCDIV_MASK             (0x1EU)
39468 #define DDRPHY_DX8SL8OSC_OSCDIV_SHIFT            (1U)
39469 /*! OSCDIV - Oscillator Mode Division
39470  */
39471 #define DDRPHY_DX8SL8OSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL8OSC_OSCDIV_MASK)
39472 #define DDRPHY_DX8SL8OSC_OSCWDL_MASK             (0x60U)
39473 #define DDRPHY_DX8SL8OSC_OSCWDL_SHIFT            (5U)
39474 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
39475  */
39476 #define DDRPHY_DX8SL8OSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL8OSC_OSCWDL_MASK)
39477 #define DDRPHY_DX8SL8OSC_RESERVED_8_7_MASK       (0x180U)
39478 #define DDRPHY_DX8SL8OSC_RESERVED_8_7_SHIFT      (7U)
39479 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
39480  */
39481 #define DDRPHY_DX8SL8OSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL8OSC_RESERVED_8_7_MASK)
39482 #define DDRPHY_DX8SL8OSC_OSCWDDL_MASK            (0x600U)
39483 #define DDRPHY_DX8SL8OSC_OSCWDDL_SHIFT           (9U)
39484 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
39485  */
39486 #define DDRPHY_DX8SL8OSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL8OSC_OSCWDDL_MASK)
39487 #define DDRPHY_DX8SL8OSC_RESERVED_12_11_MASK     (0x1800U)
39488 #define DDRPHY_DX8SL8OSC_RESERVED_12_11_SHIFT    (11U)
39489 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
39490  */
39491 #define DDRPHY_DX8SL8OSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL8OSC_RESERVED_12_11_MASK)
39492 #define DDRPHY_DX8SL8OSC_DLTMODE_MASK            (0x2000U)
39493 #define DDRPHY_DX8SL8OSC_DLTMODE_SHIFT           (13U)
39494 /*! DLTMODE - Delay Line Test Mode
39495  */
39496 #define DDRPHY_DX8SL8OSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL8OSC_DLTMODE_MASK)
39497 #define DDRPHY_DX8SL8OSC_DLTST_MASK              (0x4000U)
39498 #define DDRPHY_DX8SL8OSC_DLTST_SHIFT             (14U)
39499 /*! DLTST - Delay Line Test Start
39500  */
39501 #define DDRPHY_DX8SL8OSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_DLTST_SHIFT)) & DDRPHY_DX8SL8OSC_DLTST_MASK)
39502 #define DDRPHY_DX8SL8OSC_PHYFRST_MASK            (0x8000U)
39503 #define DDRPHY_DX8SL8OSC_PHYFRST_SHIFT           (15U)
39504 /*! PHYFRST - PHY FIFO Reset
39505  */
39506 #define DDRPHY_DX8SL8OSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL8OSC_PHYFRST_MASK)
39507 #define DDRPHY_DX8SL8OSC_PHYHRST_MASK            (0x10000U)
39508 #define DDRPHY_DX8SL8OSC_PHYHRST_SHIFT           (16U)
39509 /*! PHYHRST - PHY High-Speed Reset
39510  */
39511 #define DDRPHY_DX8SL8OSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL8OSC_PHYHRST_MASK)
39512 #define DDRPHY_DX8SL8OSC_LBDQSS_MASK             (0x20000U)
39513 #define DDRPHY_DX8SL8OSC_LBDQSS_SHIFT            (17U)
39514 /*! LBDQSS - Loopback DQS Shift
39515  */
39516 #define DDRPHY_DX8SL8OSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL8OSC_LBDQSS_MASK)
39517 #define DDRPHY_DX8SL8OSC_LBGDQS_MASK             (0xC0000U)
39518 #define DDRPHY_DX8SL8OSC_LBGDQS_SHIFT            (18U)
39519 /*! LBGDQS - Loopback DQS Gating
39520  */
39521 #define DDRPHY_DX8SL8OSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL8OSC_LBGDQS_MASK)
39522 #define DDRPHY_DX8SL8OSC_LBGSDQS_MASK            (0x100000U)
39523 #define DDRPHY_DX8SL8OSC_LBGSDQS_SHIFT           (20U)
39524 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
39525  */
39526 #define DDRPHY_DX8SL8OSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL8OSC_LBGSDQS_MASK)
39527 #define DDRPHY_DX8SL8OSC_LBMODE_MASK             (0x200000U)
39528 #define DDRPHY_DX8SL8OSC_LBMODE_SHIFT            (21U)
39529 /*! LBMODE - Loopback Mode
39530  */
39531 #define DDRPHY_DX8SL8OSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL8OSC_LBMODE_MASK)
39532 #define DDRPHY_DX8SL8OSC_CLKLEVEL_MASK           (0xC00000U)
39533 #define DDRPHY_DX8SL8OSC_CLKLEVEL_SHIFT          (22U)
39534 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
39535  */
39536 #define DDRPHY_DX8SL8OSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL8OSC_CLKLEVEL_MASK)
39537 #define DDRPHY_DX8SL8OSC_GATEDXCTLCLK_MASK       (0x3000000U)
39538 #define DDRPHY_DX8SL8OSC_GATEDXCTLCLK_SHIFT      (24U)
39539 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
39540  */
39541 #define DDRPHY_DX8SL8OSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL8OSC_GATEDXCTLCLK_MASK)
39542 #define DDRPHY_DX8SL8OSC_GATEDXDDRCLK_MASK       (0xC000000U)
39543 #define DDRPHY_DX8SL8OSC_GATEDXDDRCLK_SHIFT      (26U)
39544 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
39545  */
39546 #define DDRPHY_DX8SL8OSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL8OSC_GATEDXDDRCLK_MASK)
39547 #define DDRPHY_DX8SL8OSC_GATEDXRDCLK_MASK        (0x30000000U)
39548 #define DDRPHY_DX8SL8OSC_GATEDXRDCLK_SHIFT       (28U)
39549 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
39550  */
39551 #define DDRPHY_DX8SL8OSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL8OSC_GATEDXRDCLK_MASK)
39552 #define DDRPHY_DX8SL8OSC_RESERVED_31_30_MASK     (0xC0000000U)
39553 #define DDRPHY_DX8SL8OSC_RESERVED_31_30_SHIFT    (30U)
39554 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
39555  */
39556 #define DDRPHY_DX8SL8OSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL8OSC_RESERVED_31_30_MASK)
39557 /*! @} */
39558 
39559 /*! @name DX8SL8PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
39560 /*! @{ */
39561 #define DDRPHY_DX8SL8PLLCR0_DTC_MASK             (0xFU)
39562 #define DDRPHY_DX8SL8PLLCR0_DTC_SHIFT            (0U)
39563 /*! DTC - Digital Test Control
39564  */
39565 #define DDRPHY_DX8SL8PLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_DTC_MASK)
39566 #define DDRPHY_DX8SL8PLLCR0_ATC_MASK             (0xF0U)
39567 #define DDRPHY_DX8SL8PLLCR0_ATC_SHIFT            (4U)
39568 /*! ATC - Analog Test Control
39569  */
39570 #define DDRPHY_DX8SL8PLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_ATC_MASK)
39571 #define DDRPHY_DX8SL8PLLCR0_ATOEN_MASK           (0x100U)
39572 #define DDRPHY_DX8SL8PLLCR0_ATOEN_SHIFT          (8U)
39573 /*! ATOEN - Analog Test Enable (ATOEN)
39574  */
39575 #define DDRPHY_DX8SL8PLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL8PLLCR0_ATOEN_MASK)
39576 #define DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_MASK   (0xE00U)
39577 #define DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_SHIFT  (9U)
39578 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
39579  */
39580 #define DDRPHY_DX8SL8PLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_MASK)
39581 #define DDRPHY_DX8SL8PLLCR0_GSHIFT_MASK          (0x1000U)
39582 #define DDRPHY_DX8SL8PLLCR0_GSHIFT_SHIFT         (12U)
39583 /*! GSHIFT - Gear Shift
39584  */
39585 #define DDRPHY_DX8SL8PLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL8PLLCR0_GSHIFT_MASK)
39586 #define DDRPHY_DX8SL8PLLCR0_CPIC_MASK            (0x1E000U)
39587 #define DDRPHY_DX8SL8PLLCR0_CPIC_SHIFT           (13U)
39588 /*! CPIC - Charge Pump Integrating Current Control
39589  */
39590 #define DDRPHY_DX8SL8PLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_CPIC_MASK)
39591 #define DDRPHY_DX8SL8PLLCR0_CPPC_MASK            (0x7E0000U)
39592 #define DDRPHY_DX8SL8PLLCR0_CPPC_SHIFT           (17U)
39593 /*! CPPC - Charge Pump Proportional Current Control
39594  */
39595 #define DDRPHY_DX8SL8PLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_CPPC_MASK)
39596 #define DDRPHY_DX8SL8PLLCR0_RLOCKM_MASK          (0x800000U)
39597 #define DDRPHY_DX8SL8PLLCR0_RLOCKM_SHIFT         (23U)
39598 /*! RLOCKM - Relock Mode
39599  */
39600 #define DDRPHY_DX8SL8PLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL8PLLCR0_RLOCKM_MASK)
39601 #define DDRPHY_DX8SL8PLLCR0_FRQSEL_MASK          (0xF000000U)
39602 #define DDRPHY_DX8SL8PLLCR0_FRQSEL_SHIFT         (24U)
39603 /*! FRQSEL - PLL Frequency Select
39604  */
39605 #define DDRPHY_DX8SL8PLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL8PLLCR0_FRQSEL_MASK)
39606 #define DDRPHY_DX8SL8PLLCR0_RSTOPM_MASK          (0x10000000U)
39607 #define DDRPHY_DX8SL8PLLCR0_RSTOPM_SHIFT         (28U)
39608 /*! RSTOPM - Reference Stop Mode
39609  */
39610 #define DDRPHY_DX8SL8PLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL8PLLCR0_RSTOPM_MASK)
39611 #define DDRPHY_DX8SL8PLLCR0_PLLPD_MASK           (0x20000000U)
39612 #define DDRPHY_DX8SL8PLLCR0_PLLPD_SHIFT          (29U)
39613 /*! PLLPD - PLL Power Down
39614  */
39615 #define DDRPHY_DX8SL8PLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL8PLLCR0_PLLPD_MASK)
39616 #define DDRPHY_DX8SL8PLLCR0_PLLRST_MASK          (0x40000000U)
39617 #define DDRPHY_DX8SL8PLLCR0_PLLRST_SHIFT         (30U)
39618 /*! PLLRST - PLL Reset
39619  */
39620 #define DDRPHY_DX8SL8PLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL8PLLCR0_PLLRST_MASK)
39621 #define DDRPHY_DX8SL8PLLCR0_PLLBYP_MASK          (0x80000000U)
39622 #define DDRPHY_DX8SL8PLLCR0_PLLBYP_SHIFT         (31U)
39623 /*! PLLBYP - PLL Bypass
39624  */
39625 #define DDRPHY_DX8SL8PLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL8PLLCR0_PLLBYP_MASK)
39626 /*! @} */
39627 
39628 /*! @name DX8SL8PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
39629 /*! @{ */
39630 #define DDRPHY_DX8SL8PLLCR1_LOCKDS_MASK          (0x1U)
39631 #define DDRPHY_DX8SL8PLLCR1_LOCKDS_SHIFT         (0U)
39632 /*! LOCKDS - Lock Detector Select
39633  */
39634 #define DDRPHY_DX8SL8PLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL8PLLCR1_LOCKDS_MASK)
39635 #define DDRPHY_DX8SL8PLLCR1_LOCKCS_MASK          (0x2U)
39636 #define DDRPHY_DX8SL8PLLCR1_LOCKCS_SHIFT         (1U)
39637 /*! LOCKCS - Lock Detector Counter Select
39638  */
39639 #define DDRPHY_DX8SL8PLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL8PLLCR1_LOCKCS_MASK)
39640 #define DDRPHY_DX8SL8PLLCR1_LOCKPS_MASK          (0x4U)
39641 #define DDRPHY_DX8SL8PLLCR1_LOCKPS_SHIFT         (2U)
39642 /*! LOCKPS - Lock Detector Phase Select
39643  */
39644 #define DDRPHY_DX8SL8PLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL8PLLCR1_LOCKPS_MASK)
39645 #define DDRPHY_DX8SL8PLLCR1_BYPVDD_MASK          (0x8U)
39646 #define DDRPHY_DX8SL8PLLCR1_BYPVDD_SHIFT         (3U)
39647 /*! BYPVDD - PLL VDD voltage level control
39648  */
39649 #define DDRPHY_DX8SL8PLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL8PLLCR1_BYPVDD_MASK)
39650 #define DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_MASK      (0x10U)
39651 #define DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_SHIFT     (4U)
39652 /*! BYPVREGDIG - Bypass PLL vreg_dig
39653  */
39654 #define DDRPHY_DX8SL8PLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_MASK)
39655 #define DDRPHY_DX8SL8PLLCR1_BYPVREGCP_MASK       (0x20U)
39656 #define DDRPHY_DX8SL8PLLCR1_BYPVREGCP_SHIFT      (5U)
39657 /*! BYPVREGCP - Bypass PLL vreg_cp
39658  */
39659 #define DDRPHY_DX8SL8PLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL8PLLCR1_BYPVREGCP_MASK)
39660 #define DDRPHY_DX8SL8PLLCR1_PLLPROG_MASK         (0x3FFFC0U)
39661 #define DDRPHY_DX8SL8PLLCR1_PLLPROG_SHIFT        (6U)
39662 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
39663  */
39664 #define DDRPHY_DX8SL8PLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL8PLLCR1_PLLPROG_MASK)
39665 #define DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
39666 #define DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_SHIFT (22U)
39667 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
39668  */
39669 #define DDRPHY_DX8SL8PLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_MASK)
39670 /*! @} */
39671 
39672 /*! @name DX8SL8PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
39673 /*! @{ */
39674 #define DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
39675 #define DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_SHIFT   (0U)
39676 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
39677  */
39678 #define DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_MASK)
39679 /*! @} */
39680 
39681 /*! @name DX8SL8PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
39682 /*! @{ */
39683 #define DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
39684 #define DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_SHIFT  (0U)
39685 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
39686  */
39687 #define DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_MASK)
39688 /*! @} */
39689 
39690 /*! @name DX8SL8PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
39691 /*! @{ */
39692 #define DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
39693 #define DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_SHIFT  (0U)
39694 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
39695  */
39696 #define DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_MASK)
39697 /*! @} */
39698 
39699 /*! @name DX8SL8PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
39700 /*! @{ */
39701 #define DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
39702 #define DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_SHIFT (0U)
39703 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
39704  */
39705 #define DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_MASK)
39706 #define DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
39707 #define DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_SHIFT  (8U)
39708 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
39709  */
39710 #define DDRPHY_DX8SL8PLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_MASK)
39711 /*! @} */
39712 
39713 /*! @name DX8SL8DQSCTL - DATX8 0-1 DQS Control Register */
39714 /*! @{ */
39715 #define DDRPHY_DX8SL8DQSCTL_DQSRES_MASK          (0xFU)
39716 #define DDRPHY_DX8SL8DQSCTL_DQSRES_SHIFT         (0U)
39717 /*! DQSRES - DQS Resistor
39718  */
39719 #define DDRPHY_DX8SL8DQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DQSRES_MASK)
39720 #define DDRPHY_DX8SL8DQSCTL_DQSNRES_MASK         (0xF0U)
39721 #define DDRPHY_DX8SL8DQSCTL_DQSNRES_SHIFT        (4U)
39722 /*! DQSNRES - DQS_N Resistor
39723  */
39724 #define DDRPHY_DX8SL8DQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DQSNRES_MASK)
39725 #define DDRPHY_DX8SL8DQSCTL_DXSR_MASK            (0x300U)
39726 #define DDRPHY_DX8SL8DQSCTL_DXSR_SHIFT           (8U)
39727 /*! DXSR - Data Slew Rate
39728  */
39729 #define DDRPHY_DX8SL8DQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DXSR_MASK)
39730 #define DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_MASK  (0x1C00U)
39731 #define DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_SHIFT (10U)
39732 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
39733  */
39734 #define DDRPHY_DX8SL8DQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_MASK)
39735 #define DDRPHY_DX8SL8DQSCTL_UDQIOM_MASK          (0x2000U)
39736 #define DDRPHY_DX8SL8DQSCTL_UDQIOM_SHIFT         (13U)
39737 /*! UDQIOM - Unused DQ I/O Mode
39738  */
39739 #define DDRPHY_DX8SL8DQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL8DQSCTL_UDQIOM_MASK)
39740 #define DDRPHY_DX8SL8DQSCTL_QSCNTEN_MASK         (0x4000U)
39741 #define DDRPHY_DX8SL8DQSCTL_QSCNTEN_SHIFT        (14U)
39742 /*! QSCNTEN - QS Counter Enable
39743  */
39744 #define DDRPHY_DX8SL8DQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL8DQSCTL_QSCNTEN_MASK)
39745 #define DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_MASK  (0x18000U)
39746 #define DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_SHIFT (15U)
39747 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
39748  */
39749 #define DDRPHY_DX8SL8DQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_MASK)
39750 #define DDRPHY_DX8SL8DQSCTL_LPIOPD_MASK          (0x20000U)
39751 #define DDRPHY_DX8SL8DQSCTL_LPIOPD_SHIFT         (17U)
39752 /*! LPIOPD - Low Power I/O Power Down
39753  */
39754 #define DDRPHY_DX8SL8DQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL8DQSCTL_LPIOPD_MASK)
39755 #define DDRPHY_DX8SL8DQSCTL_LPPLLPD_MASK         (0x40000U)
39756 #define DDRPHY_DX8SL8DQSCTL_LPPLLPD_SHIFT        (18U)
39757 /*! LPPLLPD - Low Power PLL Power Down
39758  */
39759 #define DDRPHY_DX8SL8DQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL8DQSCTL_LPPLLPD_MASK)
39760 #define DDRPHY_DX8SL8DQSCTL_DQSGX_MASK           (0x180000U)
39761 #define DDRPHY_DX8SL8DQSCTL_DQSGX_SHIFT          (19U)
39762 /*! DQSGX - DQS Gate Extension
39763  */
39764 #define DDRPHY_DX8SL8DQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DQSGX_MASK)
39765 #define DDRPHY_DX8SL8DQSCTL_WRRMODE_MASK         (0x200000U)
39766 #define DDRPHY_DX8SL8DQSCTL_WRRMODE_SHIFT        (21U)
39767 /*! WRRMODE - Write Path Rise-to-Rise Mode
39768  */
39769 #define DDRPHY_DX8SL8DQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL8DQSCTL_WRRMODE_MASK)
39770 #define DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_MASK  (0xC00000U)
39771 #define DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_SHIFT (22U)
39772 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
39773  */
39774 #define DDRPHY_DX8SL8DQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_MASK)
39775 #define DDRPHY_DX8SL8DQSCTL_RRRMODE_MASK         (0x1000000U)
39776 #define DDRPHY_DX8SL8DQSCTL_RRRMODE_SHIFT        (24U)
39777 /*! RRRMODE - Read Path Rise-to-Rise Mode
39778  */
39779 #define DDRPHY_DX8SL8DQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RRRMODE_MASK)
39780 #define DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
39781 #define DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_SHIFT (25U)
39782 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
39783  */
39784 #define DDRPHY_DX8SL8DQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_MASK)
39785 /*! @} */
39786 
39787 /*! @name DX8SL8TRNCTL - DATX8 0-1 Training Control Register */
39788 /*! @{ */
39789 #define DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
39790 #define DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_SHIFT  (0U)
39791 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
39792  */
39793 #define DDRPHY_DX8SL8TRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_MASK)
39794 /*! @} */
39795 
39796 /*! @name DX8SL8DDLCTL - DATX8 0-1 DDL Control Register */
39797 /*! @{ */
39798 #define DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_MASK      (0x3U)
39799 #define DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_SHIFT     (0U)
39800 /*! DDLBYPMODE - Controls DDL Bypass Mode
39801  */
39802 #define DDRPHY_DX8SL8DDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_MASK)
39803 #define DDRPHY_DX8SL8DDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
39804 #define DDRPHY_DX8SL8DDLCTL_DXDDLBYP_SHIFT       (2U)
39805 /*! DXDDLBYP - DATX8 DDL Bypass
39806  */
39807 #define DDRPHY_DX8SL8DDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DXDDLBYP_MASK)
39808 #define DDRPHY_DX8SL8DDLCTL_DXDDLLD_MASK         (0x7C0000U)
39809 #define DDRPHY_DX8SL8DDLCTL_DXDDLLD_SHIFT        (18U)
39810 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
39811  */
39812 #define DDRPHY_DX8SL8DDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DXDDLLD_MASK)
39813 #define DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_MASK  (0x1800000U)
39814 #define DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_SHIFT (23U)
39815 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
39816  */
39817 #define DDRPHY_DX8SL8DDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_MASK)
39818 #define DDRPHY_DX8SL8DDLCTL_DXDDLLDT_MASK        (0x2000000U)
39819 #define DDRPHY_DX8SL8DDLCTL_DXDDLLDT_SHIFT       (25U)
39820 /*! DXDDLLDT - DX DDL Load Type
39821  */
39822 #define DDRPHY_DX8SL8DDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DXDDLLDT_MASK)
39823 #define DDRPHY_DX8SL8DDLCTL_DLYLDTM_MASK         (0x4000000U)
39824 #define DDRPHY_DX8SL8DDLCTL_DLYLDTM_SHIFT        (26U)
39825 /*! DLYLDTM - Delay Load Timing
39826  */
39827 #define DDRPHY_DX8SL8DDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DLYLDTM_MASK)
39828 #define DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
39829 #define DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_SHIFT (27U)
39830 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
39831  */
39832 #define DDRPHY_DX8SL8DDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_MASK)
39833 /*! @} */
39834 
39835 /*! @name DX8SL8DXCTL1 - DATX8 0-1 DX Control Register 1 */
39836 /*! @{ */
39837 #define DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
39838 #define DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_SHIFT  (0U)
39839 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
39840  */
39841 #define DDRPHY_DX8SL8DXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_MASK)
39842 #define DDRPHY_DX8SL8DXCTL1_DXTMODE_MASK         (0x10000U)
39843 #define DDRPHY_DX8SL8DXCTL1_DXTMODE_SHIFT        (16U)
39844 /*! DXTMODE - DATX8 Test Mode
39845  */
39846 #define DDRPHY_DX8SL8DXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXTMODE_MASK)
39847 #define DDRPHY_DX8SL8DXCTL1_DXGDBYP_MASK         (0x20000U)
39848 #define DDRPHY_DX8SL8DXCTL1_DXGDBYP_SHIFT        (17U)
39849 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
39850  */
39851 #define DDRPHY_DX8SL8DXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXGDBYP_MASK)
39852 #define DDRPHY_DX8SL8DXCTL1_DXQSDBYP_MASK        (0x40000U)
39853 #define DDRPHY_DX8SL8DXCTL1_DXQSDBYP_SHIFT       (18U)
39854 /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
39855  */
39856 #define DDRPHY_DX8SL8DXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXQSDBYP_MASK)
39857 #define DDRPHY_DX8SL8DXCTL1_DXGSMD_MASK          (0x80000U)
39858 #define DDRPHY_DX8SL8DXCTL1_DXGSMD_SHIFT         (19U)
39859 /*! DXGSMD - Read DQS Gating Status Mode
39860  */
39861 #define DDRPHY_DX8SL8DXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXGSMD_MASK)
39862 #define DDRPHY_DX8SL8DXCTL1_DXDTOSEL_MASK        (0x300000U)
39863 #define DDRPHY_DX8SL8DXCTL1_DXDTOSEL_SHIFT       (20U)
39864 /*! DXDTOSEL - DATX8 Digital Test Output Select
39865  */
39866 #define DDRPHY_DX8SL8DXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXDTOSEL_MASK)
39867 #define DDRPHY_DX8SL8DXCTL1_RESERVED_22_MASK     (0x400000U)
39868 #define DDRPHY_DX8SL8DXCTL1_RESERVED_22_SHIFT    (22U)
39869 /*! RESERVED_22 - Reserved. Return zeroes on reads.
39870  */
39871 #define DDRPHY_DX8SL8DXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL8DXCTL1_RESERVED_22_MASK)
39872 #define DDRPHY_DX8SL8DXCTL1_DXRCLKMD_MASK        (0x800000U)
39873 #define DDRPHY_DX8SL8DXCTL1_DXRCLKMD_SHIFT       (23U)
39874 /*! DXRCLKMD - DATX8 Read Clock Mode
39875  */
39876 #define DDRPHY_DX8SL8DXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXRCLKMD_MASK)
39877 #define DDRPHY_DX8SL8DXCTL1_DXCALCLK_MASK        (0x1000000U)
39878 #define DDRPHY_DX8SL8DXCTL1_DXCALCLK_SHIFT       (24U)
39879 /*! DXCALCLK - DATX Calibration Clock Select
39880  */
39881 #define DDRPHY_DX8SL8DXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXCALCLK_MASK)
39882 #define DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
39883 #define DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_SHIFT (25U)
39884 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
39885  */
39886 #define DDRPHY_DX8SL8DXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_MASK)
39887 /*! @} */
39888 
39889 /*! @name DX8SL8DXCTL2 - DATX8 0-1 DX Control Register 2 */
39890 /*! @{ */
39891 #define DDRPHY_DX8SL8DXCTL2_RESERVED_0_MASK      (0x1U)
39892 #define DDRPHY_DX8SL8DXCTL2_RESERVED_0_SHIFT     (0U)
39893 /*! RESERVED_0 - Reserved. Return zeroes on reads.
39894  */
39895 #define DDRPHY_DX8SL8DXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_0_MASK)
39896 #define DDRPHY_DX8SL8DXCTL2_DQSGLB_MASK          (0x6U)
39897 #define DDRPHY_DX8SL8DXCTL2_DQSGLB_SHIFT         (1U)
39898 /*! DQSGLB - Read DQS Gate I/O Loopback
39899  */
39900 #define DDRPHY_DX8SL8DXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL8DXCTL2_DQSGLB_MASK)
39901 #define DDRPHY_DX8SL8DXCTL2_DISRST_MASK          (0x8U)
39902 #define DDRPHY_DX8SL8DXCTL2_DISRST_SHIFT         (3U)
39903 /*! DISRST - Disables the Read FIFO Reset
39904  */
39905 #define DDRPHY_DX8SL8DXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL8DXCTL2_DISRST_MASK)
39906 #define DDRPHY_DX8SL8DXCTL2_RDMODE_MASK          (0x30U)
39907 #define DDRPHY_DX8SL8DXCTL2_RDMODE_SHIFT         (4U)
39908 /*! RDMODE - DATX8 Receive FIFO Read Mode
39909  */
39910 #define DDRPHY_DX8SL8DXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RDMODE_MASK)
39911 #define DDRPHY_DX8SL8DXCTL2_PRFBYP_MASK          (0x40U)
39912 #define DDRPHY_DX8SL8DXCTL2_PRFBYP_SHIFT         (6U)
39913 /*! PRFBYP - PUB Read FIFO Bypass
39914  */
39915 #define DDRPHY_DX8SL8DXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL8DXCTL2_PRFBYP_MASK)
39916 #define DDRPHY_DX8SL8DXCTL2_WDBI_MASK            (0x80U)
39917 #define DDRPHY_DX8SL8DXCTL2_WDBI_SHIFT           (7U)
39918 /*! WDBI - Write Data Bus Inversion Enable
39919  */
39920 #define DDRPHY_DX8SL8DXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL8DXCTL2_WDBI_MASK)
39921 #define DDRPHY_DX8SL8DXCTL2_RDBI_MASK            (0x100U)
39922 #define DDRPHY_DX8SL8DXCTL2_RDBI_SHIFT           (8U)
39923 /*! RDBI - Read Data Bus Inversion Enable
39924  */
39925 #define DDRPHY_DX8SL8DXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RDBI_MASK)
39926 #define DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
39927 #define DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
39928 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
39929  */
39930 #define DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_MASK)
39931 #define DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_MASK  (0x6000U)
39932 #define DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_SHIFT (13U)
39933 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
39934  */
39935 #define DDRPHY_DX8SL8DXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_MASK)
39936 #define DDRPHY_DX8SL8DXCTL2_IOLB_MASK            (0x8000U)
39937 #define DDRPHY_DX8SL8DXCTL2_IOLB_SHIFT           (15U)
39938 /*! IOLB - I/O Loopback Select
39939  */
39940 #define DDRPHY_DX8SL8DXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL8DXCTL2_IOLB_MASK)
39941 #define DDRPHY_DX8SL8DXCTL2_IOAG_MASK            (0x10000U)
39942 #define DDRPHY_DX8SL8DXCTL2_IOAG_SHIFT           (16U)
39943 /*! IOAG - I/O Assisted Gate Select
39944  */
39945 #define DDRPHY_DX8SL8DXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL8DXCTL2_IOAG_MASK)
39946 #define DDRPHY_DX8SL8DXCTL2_RESERVED_17_MASK     (0x20000U)
39947 #define DDRPHY_DX8SL8DXCTL2_RESERVED_17_SHIFT    (17U)
39948 /*! RESERVED_17 - Reserved. Return zeroes on reads.
39949  */
39950 #define DDRPHY_DX8SL8DXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_17_MASK)
39951 #define DDRPHY_DX8SL8DXCTL2_PREOEX_MASK          (0xC0000U)
39952 #define DDRPHY_DX8SL8DXCTL2_PREOEX_SHIFT         (18U)
39953 /*! PREOEX - OE Extension during Pre-amble
39954  */
39955 #define DDRPHY_DX8SL8DXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL8DXCTL2_PREOEX_MASK)
39956 #define DDRPHY_DX8SL8DXCTL2_POSOEX_MASK          (0x700000U)
39957 #define DDRPHY_DX8SL8DXCTL2_POSOEX_SHIFT         (20U)
39958 /*! POSOEX - OX Extension during Post-amble
39959  */
39960 #define DDRPHY_DX8SL8DXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL8DXCTL2_POSOEX_MASK)
39961 #define DDRPHY_DX8SL8DXCTL2_CRDEN_MASK           (0x800000U)
39962 #define DDRPHY_DX8SL8DXCTL2_CRDEN_SHIFT          (23U)
39963 /*! CRDEN - Configurable Read Data Enable
39964  */
39965 #define DDRPHY_DX8SL8DXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL8DXCTL2_CRDEN_MASK)
39966 #define DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
39967 #define DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_SHIFT (24U)
39968 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
39969  */
39970 #define DDRPHY_DX8SL8DXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_MASK)
39971 /*! @} */
39972 
39973 /*! @name DX8SL8IOCR - DATX8 0-1 I/O Configuration Register */
39974 /*! @{ */
39975 #define DDRPHY_DX8SL8IOCR_DXRXM_MASK             (0x7FFU)
39976 #define DDRPHY_DX8SL8IOCR_DXRXM_SHIFT            (0U)
39977 /*! DXRXM - DX IO Receiver Mode
39978  */
39979 #define DDRPHY_DX8SL8IOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXRXM_MASK)
39980 #define DDRPHY_DX8SL8IOCR_DXTXM_MASK             (0x3FF800U)
39981 #define DDRPHY_DX8SL8IOCR_DXTXM_SHIFT            (11U)
39982 /*! DXTXM - DX IO Transmitter Mode
39983  */
39984 #define DDRPHY_DX8SL8IOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXTXM_MASK)
39985 #define DDRPHY_DX8SL8IOCR_DXIOM_MASK             (0x1C00000U)
39986 #define DDRPHY_DX8SL8IOCR_DXIOM_SHIFT            (22U)
39987 /*! DXIOM - DX IO Mode
39988  */
39989 #define DDRPHY_DX8SL8IOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXIOM_MASK)
39990 #define DDRPHY_DX8SL8IOCR_DXVREFIOM_MASK         (0xE000000U)
39991 #define DDRPHY_DX8SL8IOCR_DXVREFIOM_SHIFT        (25U)
39992 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
39993  */
39994 #define DDRPHY_DX8SL8IOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXVREFIOM_MASK)
39995 #define DDRPHY_DX8SL8IOCR_DXDACRANGE_MASK        (0x70000000U)
39996 #define DDRPHY_DX8SL8IOCR_DXDACRANGE_SHIFT       (28U)
39997 /*! DXDACRANGE - PVREF_DAC REFSEL range select
39998  */
39999 #define DDRPHY_DX8SL8IOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL8IOCR_DXDACRANGE_MASK)
40000 #define DDRPHY_DX8SL8IOCR_RESERVED_31_MASK       (0x80000000U)
40001 #define DDRPHY_DX8SL8IOCR_RESERVED_31_SHIFT      (31U)
40002 /*! RESERVED_31 - Reserved. Return zeroes on reads.
40003  */
40004 #define DDRPHY_DX8SL8IOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL8IOCR_RESERVED_31_MASK)
40005 /*! @} */
40006 
40007 /*! @name DX4SL8IOCR - DATX4 Slice 0-1 I/O Configuration Register */
40008 /*! @{ */
40009 #define DDRPHY_DX4SL8IOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
40010 #define DDRPHY_DX4SL8IOCR_RESERVED_31_0_SHIFT    (0U)
40011 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
40012  */
40013 #define DDRPHY_DX4SL8IOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL8IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL8IOCR_RESERVED_31_0_MASK)
40014 /*! @} */
40015 
40016 /*! @name DX8SLBOSC - DATX8 0-8 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
40017 /*! @{ */
40018 #define DDRPHY_DX8SLBOSC_OSCEN_MASK              (0x1U)
40019 #define DDRPHY_DX8SLBOSC_OSCEN_SHIFT             (0U)
40020 /*! OSCEN - Oscillator Enable
40021  */
40022 #define DDRPHY_DX8SLBOSC_OSCEN(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCEN_SHIFT)) & DDRPHY_DX8SLBOSC_OSCEN_MASK)
40023 #define DDRPHY_DX8SLBOSC_OSCDIV_MASK             (0x1EU)
40024 #define DDRPHY_DX8SLBOSC_OSCDIV_SHIFT            (1U)
40025 /*! OSCDIV - Oscillator Mode Division
40026  */
40027 #define DDRPHY_DX8SLBOSC_OSCDIV(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCDIV_SHIFT)) & DDRPHY_DX8SLBOSC_OSCDIV_MASK)
40028 #define DDRPHY_DX8SLBOSC_OSCWDL_MASK             (0x60U)
40029 #define DDRPHY_DX8SLBOSC_OSCWDL_SHIFT            (5U)
40030 /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
40031  */
40032 #define DDRPHY_DX8SLBOSC_OSCWDL(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCWDL_SHIFT)) & DDRPHY_DX8SLBOSC_OSCWDL_MASK)
40033 #define DDRPHY_DX8SLBOSC_RESERVED_8_7_MASK       (0x180U)
40034 #define DDRPHY_DX8SLBOSC_RESERVED_8_7_SHIFT      (7U)
40035 /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
40036  */
40037 #define DDRPHY_DX8SLBOSC_RESERVED_8_7(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SLBOSC_RESERVED_8_7_MASK)
40038 #define DDRPHY_DX8SLBOSC_OSCWDDL_MASK            (0x600U)
40039 #define DDRPHY_DX8SLBOSC_OSCWDDL_SHIFT           (9U)
40040 /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
40041  */
40042 #define DDRPHY_DX8SLBOSC_OSCWDDL(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SLBOSC_OSCWDDL_MASK)
40043 #define DDRPHY_DX8SLBOSC_RESERVED_12_11_MASK     (0x1800U)
40044 #define DDRPHY_DX8SLBOSC_RESERVED_12_11_SHIFT    (11U)
40045 /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
40046  */
40047 #define DDRPHY_DX8SLBOSC_RESERVED_12_11(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SLBOSC_RESERVED_12_11_MASK)
40048 #define DDRPHY_DX8SLBOSC_DLTMODE_MASK            (0x2000U)
40049 #define DDRPHY_DX8SLBOSC_DLTMODE_SHIFT           (13U)
40050 /*! DLTMODE - Delay Line Test Mode
40051  */
40052 #define DDRPHY_DX8SLBOSC_DLTMODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_DLTMODE_SHIFT)) & DDRPHY_DX8SLBOSC_DLTMODE_MASK)
40053 #define DDRPHY_DX8SLBOSC_DLTST_MASK              (0x4000U)
40054 #define DDRPHY_DX8SLBOSC_DLTST_SHIFT             (14U)
40055 /*! DLTST - Delay Line Test Start
40056  */
40057 #define DDRPHY_DX8SLBOSC_DLTST(x)                (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_DLTST_SHIFT)) & DDRPHY_DX8SLBOSC_DLTST_MASK)
40058 #define DDRPHY_DX8SLBOSC_PHYFRST_MASK            (0x8000U)
40059 #define DDRPHY_DX8SLBOSC_PHYFRST_SHIFT           (15U)
40060 /*! PHYFRST - PHY FIFO Reset
40061  */
40062 #define DDRPHY_DX8SLBOSC_PHYFRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_PHYFRST_SHIFT)) & DDRPHY_DX8SLBOSC_PHYFRST_MASK)
40063 #define DDRPHY_DX8SLBOSC_PHYHRST_MASK            (0x10000U)
40064 #define DDRPHY_DX8SLBOSC_PHYHRST_SHIFT           (16U)
40065 /*! PHYHRST - PHY High-Speed Reset
40066  */
40067 #define DDRPHY_DX8SLBOSC_PHYHRST(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_PHYHRST_SHIFT)) & DDRPHY_DX8SLBOSC_PHYHRST_MASK)
40068 #define DDRPHY_DX8SLBOSC_LBDQSS_MASK             (0x20000U)
40069 #define DDRPHY_DX8SLBOSC_LBDQSS_SHIFT            (17U)
40070 /*! LBDQSS - Loopback DQS Shift
40071  */
40072 #define DDRPHY_DX8SLBOSC_LBDQSS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBDQSS_SHIFT)) & DDRPHY_DX8SLBOSC_LBDQSS_MASK)
40073 #define DDRPHY_DX8SLBOSC_LBGDQS_MASK             (0xC0000U)
40074 #define DDRPHY_DX8SLBOSC_LBGDQS_SHIFT            (18U)
40075 /*! LBGDQS - Loopback DQS Gating
40076  */
40077 #define DDRPHY_DX8SLBOSC_LBGDQS(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBGDQS_SHIFT)) & DDRPHY_DX8SLBOSC_LBGDQS_MASK)
40078 #define DDRPHY_DX8SLBOSC_LBGSDQS_MASK            (0x100000U)
40079 #define DDRPHY_DX8SLBOSC_LBGSDQS_SHIFT           (20U)
40080 /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
40081  */
40082 #define DDRPHY_DX8SLBOSC_LBGSDQS(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SLBOSC_LBGSDQS_MASK)
40083 #define DDRPHY_DX8SLBOSC_LBMODE_MASK             (0x200000U)
40084 #define DDRPHY_DX8SLBOSC_LBMODE_SHIFT            (21U)
40085 /*! LBMODE - Loopback Mode
40086  */
40087 #define DDRPHY_DX8SLBOSC_LBMODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBMODE_SHIFT)) & DDRPHY_DX8SLBOSC_LBMODE_MASK)
40088 #define DDRPHY_DX8SLBOSC_CLKLEVEL_MASK           (0xC00000U)
40089 #define DDRPHY_DX8SLBOSC_CLKLEVEL_SHIFT          (22U)
40090 /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
40091  */
40092 #define DDRPHY_DX8SLBOSC_CLKLEVEL(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SLBOSC_CLKLEVEL_MASK)
40093 #define DDRPHY_DX8SLBOSC_GATEDXCTLCLK_MASK       (0x3000000U)
40094 #define DDRPHY_DX8SLBOSC_GATEDXCTLCLK_SHIFT      (24U)
40095 /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
40096  */
40097 #define DDRPHY_DX8SLBOSC_GATEDXCTLCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SLBOSC_GATEDXCTLCLK_MASK)
40098 #define DDRPHY_DX8SLBOSC_GATEDXDDRCLK_MASK       (0xC000000U)
40099 #define DDRPHY_DX8SLBOSC_GATEDXDDRCLK_SHIFT      (26U)
40100 /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
40101  */
40102 #define DDRPHY_DX8SLBOSC_GATEDXDDRCLK(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SLBOSC_GATEDXDDRCLK_MASK)
40103 #define DDRPHY_DX8SLBOSC_GATEDXRDCLK_MASK        (0x30000000U)
40104 #define DDRPHY_DX8SLBOSC_GATEDXRDCLK_SHIFT       (28U)
40105 /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
40106  */
40107 #define DDRPHY_DX8SLBOSC_GATEDXRDCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SLBOSC_GATEDXRDCLK_MASK)
40108 #define DDRPHY_DX8SLBOSC_RESERVED_31_30_MASK     (0xC0000000U)
40109 #define DDRPHY_DX8SLBOSC_RESERVED_31_30_SHIFT    (30U)
40110 /*! RESERVED_31_30 - Reserved. Return zeroes on reads.
40111  */
40112 #define DDRPHY_DX8SLBOSC_RESERVED_31_30(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SLBOSC_RESERVED_31_30_MASK)
40113 /*! @} */
40114 
40115 /*! @name DX8SLBPLLCR0 - DAXT8 0-8 PLL Control Register 0 */
40116 /*! @{ */
40117 #define DDRPHY_DX8SLBPLLCR0_DTC_MASK             (0xFU)
40118 #define DDRPHY_DX8SLBPLLCR0_DTC_SHIFT            (0U)
40119 /*! DTC - Digital Test Control
40120  */
40121 #define DDRPHY_DX8SLBPLLCR0_DTC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_DTC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_DTC_MASK)
40122 #define DDRPHY_DX8SLBPLLCR0_ATC_MASK             (0xF0U)
40123 #define DDRPHY_DX8SLBPLLCR0_ATC_SHIFT            (4U)
40124 /*! ATC - Analog Test Control
40125  */
40126 #define DDRPHY_DX8SLBPLLCR0_ATC(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_ATC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_ATC_MASK)
40127 #define DDRPHY_DX8SLBPLLCR0_ATOEN_MASK           (0x100U)
40128 #define DDRPHY_DX8SLBPLLCR0_ATOEN_SHIFT          (8U)
40129 /*! ATOEN - Analog Test Enable (ATOEN)
40130  */
40131 #define DDRPHY_DX8SLBPLLCR0_ATOEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SLBPLLCR0_ATOEN_MASK)
40132 #define DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_MASK   (0xE00U)
40133 #define DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT  (9U)
40134 /*! RESERVED_11_9 - Reserved. Return zeroes on reads.
40135  */
40136 #define DDRPHY_DX8SLBPLLCR0_RESERVED_11_9(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_MASK)
40137 #define DDRPHY_DX8SLBPLLCR0_GSHIFT_MASK          (0x1000U)
40138 #define DDRPHY_DX8SLBPLLCR0_GSHIFT_SHIFT         (12U)
40139 /*! GSHIFT - Gear Shift
40140  */
40141 #define DDRPHY_DX8SLBPLLCR0_GSHIFT(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SLBPLLCR0_GSHIFT_MASK)
40142 #define DDRPHY_DX8SLBPLLCR0_CPIC_MASK            (0x1E000U)
40143 #define DDRPHY_DX8SLBPLLCR0_CPIC_SHIFT           (13U)
40144 /*! CPIC - Charge Pump Integrating Current Control
40145  */
40146 #define DDRPHY_DX8SLBPLLCR0_CPIC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_CPIC_MASK)
40147 #define DDRPHY_DX8SLBPLLCR0_CPPC_MASK            (0x7E0000U)
40148 #define DDRPHY_DX8SLBPLLCR0_CPPC_SHIFT           (17U)
40149 /*! CPPC - Charge Pump Proportional Current Control
40150  */
40151 #define DDRPHY_DX8SLBPLLCR0_CPPC(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_CPPC_MASK)
40152 #define DDRPHY_DX8SLBPLLCR0_RLOCKM_MASK          (0x800000U)
40153 #define DDRPHY_DX8SLBPLLCR0_RLOCKM_SHIFT         (23U)
40154 /*! RLOCKM - Relock Mode
40155  */
40156 #define DDRPHY_DX8SLBPLLCR0_RLOCKM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SLBPLLCR0_RLOCKM_MASK)
40157 #define DDRPHY_DX8SLBPLLCR0_FRQSEL_MASK          (0xF000000U)
40158 #define DDRPHY_DX8SLBPLLCR0_FRQSEL_SHIFT         (24U)
40159 /*! FRQSEL - PLL Frequency Select
40160  */
40161 #define DDRPHY_DX8SLBPLLCR0_FRQSEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SLBPLLCR0_FRQSEL_MASK)
40162 #define DDRPHY_DX8SLBPLLCR0_RSTOPM_MASK          (0x10000000U)
40163 #define DDRPHY_DX8SLBPLLCR0_RSTOPM_SHIFT         (28U)
40164 /*! RSTOPM - Reference Stop Mode
40165  */
40166 #define DDRPHY_DX8SLBPLLCR0_RSTOPM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SLBPLLCR0_RSTOPM_MASK)
40167 #define DDRPHY_DX8SLBPLLCR0_PLLPD_MASK           (0x20000000U)
40168 #define DDRPHY_DX8SLBPLLCR0_PLLPD_SHIFT          (29U)
40169 /*! PLLPD - PLL Power Down
40170  */
40171 #define DDRPHY_DX8SLBPLLCR0_PLLPD(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SLBPLLCR0_PLLPD_MASK)
40172 #define DDRPHY_DX8SLBPLLCR0_PLLRST_MASK          (0x40000000U)
40173 #define DDRPHY_DX8SLBPLLCR0_PLLRST_SHIFT         (30U)
40174 /*! PLLRST - PLL Reset
40175  */
40176 #define DDRPHY_DX8SLBPLLCR0_PLLRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SLBPLLCR0_PLLRST_MASK)
40177 #define DDRPHY_DX8SLBPLLCR0_PLLBYP_MASK          (0x80000000U)
40178 #define DDRPHY_DX8SLBPLLCR0_PLLBYP_SHIFT         (31U)
40179 /*! PLLBYP - PLL Bypass
40180  */
40181 #define DDRPHY_DX8SLBPLLCR0_PLLBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SLBPLLCR0_PLLBYP_MASK)
40182 /*! @} */
40183 
40184 /*! @name DX8SLBPLLCR1 - DAXT8 0-8 PLL Control Register 1 (Type B PLL Only) */
40185 /*! @{ */
40186 #define DDRPHY_DX8SLBPLLCR1_LOCKDS_MASK          (0x1U)
40187 #define DDRPHY_DX8SLBPLLCR1_LOCKDS_SHIFT         (0U)
40188 /*! LOCKDS - Lock Detector Select
40189  */
40190 #define DDRPHY_DX8SLBPLLCR1_LOCKDS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SLBPLLCR1_LOCKDS_MASK)
40191 #define DDRPHY_DX8SLBPLLCR1_LOCKCS_MASK          (0x2U)
40192 #define DDRPHY_DX8SLBPLLCR1_LOCKCS_SHIFT         (1U)
40193 /*! LOCKCS - Lock Detector Counter Select
40194  */
40195 #define DDRPHY_DX8SLBPLLCR1_LOCKCS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SLBPLLCR1_LOCKCS_MASK)
40196 #define DDRPHY_DX8SLBPLLCR1_LOCKPS_MASK          (0x4U)
40197 #define DDRPHY_DX8SLBPLLCR1_LOCKPS_SHIFT         (2U)
40198 /*! LOCKPS - Lock Detector Phase Select
40199  */
40200 #define DDRPHY_DX8SLBPLLCR1_LOCKPS(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SLBPLLCR1_LOCKPS_MASK)
40201 #define DDRPHY_DX8SLBPLLCR1_BYPVDD_MASK          (0x8U)
40202 #define DDRPHY_DX8SLBPLLCR1_BYPVDD_SHIFT         (3U)
40203 /*! BYPVDD - PLL VDD voltage level control
40204  */
40205 #define DDRPHY_DX8SLBPLLCR1_BYPVDD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SLBPLLCR1_BYPVDD_MASK)
40206 #define DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_MASK      (0x10U)
40207 #define DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_SHIFT     (4U)
40208 /*! BYPVREGDIG - Bypass PLL vreg_dig
40209  */
40210 #define DDRPHY_DX8SLBPLLCR1_BYPVREGDIG(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_MASK)
40211 #define DDRPHY_DX8SLBPLLCR1_BYPVREGCP_MASK       (0x20U)
40212 #define DDRPHY_DX8SLBPLLCR1_BYPVREGCP_SHIFT      (5U)
40213 /*! BYPVREGCP - Bypass PLL vreg_cp
40214  */
40215 #define DDRPHY_DX8SLBPLLCR1_BYPVREGCP(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SLBPLLCR1_BYPVREGCP_MASK)
40216 #define DDRPHY_DX8SLBPLLCR1_PLLPROG_MASK         (0x3FFFC0U)
40217 #define DDRPHY_DX8SLBPLLCR1_PLLPROG_SHIFT        (6U)
40218 /*! PLLPROG - Connects to the PLL PLL_PROG bus.
40219  */
40220 #define DDRPHY_DX8SLBPLLCR1_PLLPROG(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SLBPLLCR1_PLLPROG_MASK)
40221 #define DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_MASK  (0xFFC00000U)
40222 #define DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_SHIFT (22U)
40223 /*! RESERVED_31_22 - Reserved. Return zeroes on reads.
40224  */
40225 #define DDRPHY_DX8SLBPLLCR1_RESERVED_31_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_MASK)
40226 /*! @} */
40227 
40228 /*! @name DX8SLBPLLCR2 - DAXT8 0-8 PLL Control Register 2 (Type B PLL Only) */
40229 /*! @{ */
40230 #define DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_MASK    (0xFFFFFFFFU)
40231 #define DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_SHIFT   (0U)
40232 /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
40233  */
40234 #define DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_MASK)
40235 /*! @} */
40236 
40237 /*! @name DX8SLBPLLCR3 - DAXT8 0-8 PLL Control Register 3 (Type B PLL Only) */
40238 /*! @{ */
40239 #define DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_MASK   (0xFFFFFFFFU)
40240 #define DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_SHIFT  (0U)
40241 /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
40242  */
40243 #define DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_MASK)
40244 /*! @} */
40245 
40246 /*! @name DX8SLBPLLCR4 - DAXT8 0-8 PLL Control Register 4 (Type B PLL Only) */
40247 /*! @{ */
40248 #define DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_MASK   (0xFFFFFFFFU)
40249 #define DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_SHIFT  (0U)
40250 /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
40251  */
40252 #define DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_MASK)
40253 /*! @} */
40254 
40255 /*! @name DX8SLBPLLCR5 - DAXT8 0-8 PLL Control Register 5 (Type B PLL Only) */
40256 /*! @{ */
40257 #define DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_MASK  (0xFFU)
40258 #define DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_SHIFT (0U)
40259 /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
40260  */
40261 #define DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_MASK)
40262 #define DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_MASK   (0xFFFFFF00U)
40263 #define DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_SHIFT  (8U)
40264 /*! RESERVED_31_8 - Reserved. Return zeroes on reads.
40265  */
40266 #define DDRPHY_DX8SLBPLLCR5_RESERVED_31_8(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_MASK)
40267 /*! @} */
40268 
40269 /*! @name DX8SLBDQSCTL - DATX8 0-8 DQS Control Register */
40270 /*! @{ */
40271 #define DDRPHY_DX8SLBDQSCTL_DQSRES_MASK          (0xFU)
40272 #define DDRPHY_DX8SLBDQSCTL_DQSRES_SHIFT         (0U)
40273 /*! DQSRES - DQS Resistor
40274  */
40275 #define DDRPHY_DX8SLBDQSCTL_DQSRES(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DQSRES_MASK)
40276 #define DDRPHY_DX8SLBDQSCTL_DQSNRES_MASK         (0xF0U)
40277 #define DDRPHY_DX8SLBDQSCTL_DQSNRES_SHIFT        (4U)
40278 /*! DQSNRES - DQS# Resistor
40279  */
40280 #define DDRPHY_DX8SLBDQSCTL_DQSNRES(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DQSNRES_MASK)
40281 #define DDRPHY_DX8SLBDQSCTL_DXSR_MASK            (0x300U)
40282 #define DDRPHY_DX8SLBDQSCTL_DXSR_SHIFT           (8U)
40283 /*! DXSR - Data Slew Rate
40284  */
40285 #define DDRPHY_DX8SLBDQSCTL_DXSR(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DXSR_MASK)
40286 #define DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_MASK  (0x1C00U)
40287 #define DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT (10U)
40288 /*! RESERVED_12_10 - Reserved. Return zeroes on reads.
40289  */
40290 #define DDRPHY_DX8SLBDQSCTL_RESERVED_12_10(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_MASK)
40291 #define DDRPHY_DX8SLBDQSCTL_UDQIOM_MASK          (0x2000U)
40292 #define DDRPHY_DX8SLBDQSCTL_UDQIOM_SHIFT         (13U)
40293 /*! UDQIOM - Unused DQ I/O Mode
40294  */
40295 #define DDRPHY_DX8SLBDQSCTL_UDQIOM(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SLBDQSCTL_UDQIOM_MASK)
40296 #define DDRPHY_DX8SLBDQSCTL_QSCNTEN_MASK         (0x4000U)
40297 #define DDRPHY_DX8SLBDQSCTL_QSCNTEN_SHIFT        (14U)
40298 /*! QSCNTEN - QS Counter Enable
40299  */
40300 #define DDRPHY_DX8SLBDQSCTL_QSCNTEN(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SLBDQSCTL_QSCNTEN_MASK)
40301 #define DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_MASK  (0x18000U)
40302 #define DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT (15U)
40303 /*! RESERVED_16_15 - Reserved. Return zeroes on reads.
40304  */
40305 #define DDRPHY_DX8SLBDQSCTL_RESERVED_16_15(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_MASK)
40306 #define DDRPHY_DX8SLBDQSCTL_LPIOPD_MASK          (0x20000U)
40307 #define DDRPHY_DX8SLBDQSCTL_LPIOPD_SHIFT         (17U)
40308 /*! LPIOPD - Low Power I/O Power Down
40309  */
40310 #define DDRPHY_DX8SLBDQSCTL_LPIOPD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SLBDQSCTL_LPIOPD_MASK)
40311 #define DDRPHY_DX8SLBDQSCTL_LPPLLPD_MASK         (0x40000U)
40312 #define DDRPHY_DX8SLBDQSCTL_LPPLLPD_SHIFT        (18U)
40313 /*! LPPLLPD - Low Power PLL Power Down
40314  */
40315 #define DDRPHY_DX8SLBDQSCTL_LPPLLPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SLBDQSCTL_LPPLLPD_MASK)
40316 #define DDRPHY_DX8SLBDQSCTL_DQSGX_MASK           (0x180000U)
40317 #define DDRPHY_DX8SLBDQSCTL_DQSGX_SHIFT          (19U)
40318 /*! DQSGX - DQS Gate Extension
40319  */
40320 #define DDRPHY_DX8SLBDQSCTL_DQSGX(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DQSGX_MASK)
40321 #define DDRPHY_DX8SLBDQSCTL_WRRMODE_MASK         (0x200000U)
40322 #define DDRPHY_DX8SLBDQSCTL_WRRMODE_SHIFT        (21U)
40323 /*! WRRMODE - Write Path Rise-to-Rise Mode
40324  */
40325 #define DDRPHY_DX8SLBDQSCTL_WRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SLBDQSCTL_WRRMODE_MASK)
40326 #define DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_MASK  (0xC00000U)
40327 #define DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT (22U)
40328 /*! RESERVED_23_22 - Reserved. Return zeroes on reads.
40329  */
40330 #define DDRPHY_DX8SLBDQSCTL_RESERVED_23_22(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_MASK)
40331 #define DDRPHY_DX8SLBDQSCTL_RRRMODE_MASK         (0x1000000U)
40332 #define DDRPHY_DX8SLBDQSCTL_RRRMODE_SHIFT        (24U)
40333 /*! RRRMODE - Read Path Rise-to-Rise Mode
40334  */
40335 #define DDRPHY_DX8SLBDQSCTL_RRRMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RRRMODE_MASK)
40336 #define DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_MASK  (0xFE000000U)
40337 #define DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT (25U)
40338 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
40339  */
40340 #define DDRPHY_DX8SLBDQSCTL_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_MASK)
40341 /*! @} */
40342 
40343 /*! @name DX8SLBTRNCTL - DATX8 0-8 Training Control Register */
40344 /*! @{ */
40345 #define DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_MASK   (0xFFFFFFFFU)
40346 #define DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_SHIFT  (0U)
40347 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
40348  */
40349 #define DDRPHY_DX8SLBTRNCTL_RESERVED_31_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_MASK)
40350 /*! @} */
40351 
40352 /*! @name DX8SLBDDLCTL - DATX8 0-8 DDL Control Register */
40353 /*! @{ */
40354 #define DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_MASK      (0x3U)
40355 #define DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_SHIFT     (0U)
40356 /*! DDLBYPMODE - Controls DDL Bypass Mode
40357  */
40358 #define DDRPHY_DX8SLBDDLCTL_DDLBYPMODE(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_MASK)
40359 #define DDRPHY_DX8SLBDDLCTL_DXDDLBYP_MASK        (0x3FFFCU)
40360 #define DDRPHY_DX8SLBDDLCTL_DXDDLBYP_SHIFT       (2U)
40361 /*! DXDDLBYP - DATX8 DDL Bypass
40362  */
40363 #define DDRPHY_DX8SLBDDLCTL_DXDDLBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DXDDLBYP_MASK)
40364 #define DDRPHY_DX8SLBDDLCTL_DXDDLLD_MASK         (0x7C0000U)
40365 #define DDRPHY_DX8SLBDDLCTL_DXDDLLD_SHIFT        (18U)
40366 /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
40367  */
40368 #define DDRPHY_DX8SLBDDLCTL_DXDDLLD(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DXDDLLD_MASK)
40369 #define DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_MASK  (0x1800000U)
40370 #define DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_SHIFT (23U)
40371 /*! RESERVED_24_23 - Reserved. Return zeroes on reads.
40372  */
40373 #define DDRPHY_DX8SLBDDLCTL_RESERVED_24_23(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_MASK)
40374 #define DDRPHY_DX8SLBDDLCTL_DXDDLLDT_MASK        (0x2000000U)
40375 #define DDRPHY_DX8SLBDDLCTL_DXDDLLDT_SHIFT       (25U)
40376 /*! DXDDLLDT - DX DDL Load Type
40377  */
40378 #define DDRPHY_DX8SLBDDLCTL_DXDDLLDT(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DXDDLLDT_MASK)
40379 #define DDRPHY_DX8SLBDDLCTL_DLYLDTM_MASK         (0x4000000U)
40380 #define DDRPHY_DX8SLBDDLCTL_DLYLDTM_SHIFT        (26U)
40381 /*! DLYLDTM - Delay Load Timing
40382  */
40383 #define DDRPHY_DX8SLBDDLCTL_DLYLDTM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DLYLDTM_MASK)
40384 #define DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_MASK  (0xF8000000U)
40385 #define DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_SHIFT (27U)
40386 /*! RESERVED_31_27 - Reserved. Return zeroes on reads.
40387  */
40388 #define DDRPHY_DX8SLBDDLCTL_RESERVED_31_27(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_MASK)
40389 /*! @} */
40390 
40391 /*! @name DX8SLBDXCTL1 - DATX8 0-8 DX Control Register 1 */
40392 /*! @{ */
40393 #define DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_MASK   (0xFFFFU)
40394 #define DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_SHIFT  (0U)
40395 /*! RESERVED_15_0 - Reserved. Return zeroes on reads.
40396  */
40397 #define DDRPHY_DX8SLBDXCTL1_RESERVED_15_0(x)     (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_MASK)
40398 #define DDRPHY_DX8SLBDXCTL1_DXTMODE_MASK         (0x10000U)
40399 #define DDRPHY_DX8SLBDXCTL1_DXTMODE_SHIFT        (16U)
40400 /*! DXTMODE - DATX8 Test Mode
40401  */
40402 #define DDRPHY_DX8SLBDXCTL1_DXTMODE(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXTMODE_MASK)
40403 #define DDRPHY_DX8SLBDXCTL1_DXGDBYP_MASK         (0x20000U)
40404 #define DDRPHY_DX8SLBDXCTL1_DXGDBYP_SHIFT        (17U)
40405 /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
40406  */
40407 #define DDRPHY_DX8SLBDXCTL1_DXGDBYP(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXGDBYP_MASK)
40408 #define DDRPHY_DX8SLBDXCTL1_DXQSDBYP_MASK        (0x40000U)
40409 #define DDRPHY_DX8SLBDXCTL1_DXQSDBYP_SHIFT       (18U)
40410 /*! DXQSDBYP - Read DQS/DQS# Delay Load Bypass Mode
40411  */
40412 #define DDRPHY_DX8SLBDXCTL1_DXQSDBYP(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXQSDBYP_MASK)
40413 #define DDRPHY_DX8SLBDXCTL1_DXGSMD_MASK          (0x80000U)
40414 #define DDRPHY_DX8SLBDXCTL1_DXGSMD_SHIFT         (19U)
40415 /*! DXGSMD - Read DQS Gating Status Mode
40416  */
40417 #define DDRPHY_DX8SLBDXCTL1_DXGSMD(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXGSMD_MASK)
40418 #define DDRPHY_DX8SLBDXCTL1_DXDTOSEL_MASK        (0x300000U)
40419 #define DDRPHY_DX8SLBDXCTL1_DXDTOSEL_SHIFT       (20U)
40420 /*! DXDTOSEL - DATX8 Digital Test Output Select
40421  */
40422 #define DDRPHY_DX8SLBDXCTL1_DXDTOSEL(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXDTOSEL_MASK)
40423 #define DDRPHY_DX8SLBDXCTL1_RESERVED_22_MASK     (0x400000U)
40424 #define DDRPHY_DX8SLBDXCTL1_RESERVED_22_SHIFT    (22U)
40425 /*! RESERVED_22 - Reserved. Return zeroes on reads.
40426  */
40427 #define DDRPHY_DX8SLBDXCTL1_RESERVED_22(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SLBDXCTL1_RESERVED_22_MASK)
40428 #define DDRPHY_DX8SLBDXCTL1_DXRCLKMD_MASK        (0x800000U)
40429 #define DDRPHY_DX8SLBDXCTL1_DXRCLKMD_SHIFT       (23U)
40430 /*! DXRCLKMD - DATX8 Read Clock Mode
40431  */
40432 #define DDRPHY_DX8SLBDXCTL1_DXRCLKMD(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXRCLKMD_MASK)
40433 #define DDRPHY_DX8SLBDXCTL1_DXCALCLK_MASK        (0x1000000U)
40434 #define DDRPHY_DX8SLBDXCTL1_DXCALCLK_SHIFT       (24U)
40435 /*! DXCALCLK - DATX Calibration Clock Select
40436  */
40437 #define DDRPHY_DX8SLBDXCTL1_DXCALCLK(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXCALCLK_MASK)
40438 #define DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_MASK  (0xFE000000U)
40439 #define DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_SHIFT (25U)
40440 /*! RESERVED_31_25 - Reserved. Return zeroes on reads.
40441  */
40442 #define DDRPHY_DX8SLBDXCTL1_RESERVED_31_25(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_MASK)
40443 /*! @} */
40444 
40445 /*! @name DX8SLBDXCTL2 - DATX8 0-8 DX Control Register 2 */
40446 /*! @{ */
40447 #define DDRPHY_DX8SLBDXCTL2_RESERVED_0_MASK      (0x1U)
40448 #define DDRPHY_DX8SLBDXCTL2_RESERVED_0_SHIFT     (0U)
40449 /*! RESERVED_0 - Reserved. Return zeroes on reads.
40450  */
40451 #define DDRPHY_DX8SLBDXCTL2_RESERVED_0(x)        (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_0_MASK)
40452 #define DDRPHY_DX8SLBDXCTL2_DQSGLB_MASK          (0x6U)
40453 #define DDRPHY_DX8SLBDXCTL2_DQSGLB_SHIFT         (1U)
40454 /*! DQSGLB - Read DQS Gate I/O Loopback
40455  */
40456 #define DDRPHY_DX8SLBDXCTL2_DQSGLB(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SLBDXCTL2_DQSGLB_MASK)
40457 #define DDRPHY_DX8SLBDXCTL2_DISRST_MASK          (0x8U)
40458 #define DDRPHY_DX8SLBDXCTL2_DISRST_SHIFT         (3U)
40459 /*! DISRST - Disables the Read FIFO Reset
40460  */
40461 #define DDRPHY_DX8SLBDXCTL2_DISRST(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SLBDXCTL2_DISRST_MASK)
40462 #define DDRPHY_DX8SLBDXCTL2_RDMODE_MASK          (0x30U)
40463 #define DDRPHY_DX8SLBDXCTL2_RDMODE_SHIFT         (4U)
40464 /*! RDMODE - DATX8 Receive FIFO Read Mode
40465  */
40466 #define DDRPHY_DX8SLBDXCTL2_RDMODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RDMODE_MASK)
40467 #define DDRPHY_DX8SLBDXCTL2_PRFBYP_MASK          (0x40U)
40468 #define DDRPHY_DX8SLBDXCTL2_PRFBYP_SHIFT         (6U)
40469 /*! PRFBYP - PUB Read FIFO Bypass
40470  */
40471 #define DDRPHY_DX8SLBDXCTL2_PRFBYP(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SLBDXCTL2_PRFBYP_MASK)
40472 #define DDRPHY_DX8SLBDXCTL2_WDBI_MASK            (0x80U)
40473 #define DDRPHY_DX8SLBDXCTL2_WDBI_SHIFT           (7U)
40474 /*! WDBI - Write Data Bus Inversion Enable
40475  */
40476 #define DDRPHY_DX8SLBDXCTL2_WDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SLBDXCTL2_WDBI_MASK)
40477 #define DDRPHY_DX8SLBDXCTL2_RDBI_MASK            (0x100U)
40478 #define DDRPHY_DX8SLBDXCTL2_RDBI_SHIFT           (8U)
40479 /*! RDBI - Read Data Bus Inversion Enable
40480  */
40481 #define DDRPHY_DX8SLBDXCTL2_RDBI(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RDBI_MASK)
40482 #define DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_MASK  (0x1E00U)
40483 #define DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
40484 /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
40485  */
40486 #define DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_MASK)
40487 #define DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_MASK  (0x6000U)
40488 #define DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_SHIFT (13U)
40489 /*! RESERVED_14_13 - Reserved. Return zeroes on reads.
40490  */
40491 #define DDRPHY_DX8SLBDXCTL2_RESERVED_14_13(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_MASK)
40492 #define DDRPHY_DX8SLBDXCTL2_IOLB_MASK            (0x8000U)
40493 #define DDRPHY_DX8SLBDXCTL2_IOLB_SHIFT           (15U)
40494 /*! IOLB - I/O Loopback Select
40495  */
40496 #define DDRPHY_DX8SLBDXCTL2_IOLB(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SLBDXCTL2_IOLB_MASK)
40497 #define DDRPHY_DX8SLBDXCTL2_IOAG_MASK            (0x10000U)
40498 #define DDRPHY_DX8SLBDXCTL2_IOAG_SHIFT           (16U)
40499 /*! IOAG - I/O Assisted Gate Select
40500  */
40501 #define DDRPHY_DX8SLBDXCTL2_IOAG(x)              (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SLBDXCTL2_IOAG_MASK)
40502 #define DDRPHY_DX8SLBDXCTL2_RESERVED_17_MASK     (0x20000U)
40503 #define DDRPHY_DX8SLBDXCTL2_RESERVED_17_SHIFT    (17U)
40504 /*! RESERVED_17 - Reserved. Return zeroes on reads.
40505  */
40506 #define DDRPHY_DX8SLBDXCTL2_RESERVED_17(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_17_MASK)
40507 #define DDRPHY_DX8SLBDXCTL2_PREOEX_MASK          (0xC0000U)
40508 #define DDRPHY_DX8SLBDXCTL2_PREOEX_SHIFT         (18U)
40509 /*! PREOEX - OE Extension during Pre-amble
40510  */
40511 #define DDRPHY_DX8SLBDXCTL2_PREOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SLBDXCTL2_PREOEX_MASK)
40512 #define DDRPHY_DX8SLBDXCTL2_POSOEX_MASK          (0x700000U)
40513 #define DDRPHY_DX8SLBDXCTL2_POSOEX_SHIFT         (20U)
40514 /*! POSOEX - OX Extension during Post-amble
40515  */
40516 #define DDRPHY_DX8SLBDXCTL2_POSOEX(x)            (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SLBDXCTL2_POSOEX_MASK)
40517 #define DDRPHY_DX8SLBDXCTL2_CRDEN_MASK           (0x800000U)
40518 #define DDRPHY_DX8SLBDXCTL2_CRDEN_SHIFT          (23U)
40519 /*! CRDEN - Configurable Read Data Enable
40520  */
40521 #define DDRPHY_DX8SLBDXCTL2_CRDEN(x)             (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SLBDXCTL2_CRDEN_MASK)
40522 #define DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_MASK  (0xFF000000U)
40523 #define DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_SHIFT (24U)
40524 /*! RESERVED_31_24 - Reserved. Return zeroes on reads.
40525  */
40526 #define DDRPHY_DX8SLBDXCTL2_RESERVED_31_24(x)    (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_MASK)
40527 /*! @} */
40528 
40529 /*! @name DX8SLBIOCR - DATX8 0-8 I/O Configuration Register */
40530 /*! @{ */
40531 #define DDRPHY_DX8SLBIOCR_DXRXM_MASK             (0x7FFU)
40532 #define DDRPHY_DX8SLBIOCR_DXRXM_SHIFT            (0U)
40533 /*! DXRXM - DX IO Receiver Mode
40534  */
40535 #define DDRPHY_DX8SLBIOCR_DXRXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXRXM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXRXM_MASK)
40536 #define DDRPHY_DX8SLBIOCR_DXTXM_MASK             (0x3FF800U)
40537 #define DDRPHY_DX8SLBIOCR_DXTXM_SHIFT            (11U)
40538 /*! DXTXM - DX IO Transmitter Mode
40539  */
40540 #define DDRPHY_DX8SLBIOCR_DXTXM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXTXM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXTXM_MASK)
40541 #define DDRPHY_DX8SLBIOCR_DXIOM_MASK             (0x1C00000U)
40542 #define DDRPHY_DX8SLBIOCR_DXIOM_SHIFT            (22U)
40543 /*! DXIOM - DX IO Mode
40544  */
40545 #define DDRPHY_DX8SLBIOCR_DXIOM(x)               (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXIOM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXIOM_MASK)
40546 #define DDRPHY_DX8SLBIOCR_DXVREFIOM_MASK         (0xE000000U)
40547 #define DDRPHY_DX8SLBIOCR_DXVREFIOM_SHIFT        (25U)
40548 /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
40549  */
40550 #define DDRPHY_DX8SLBIOCR_DXVREFIOM(x)           (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXVREFIOM_MASK)
40551 #define DDRPHY_DX8SLBIOCR_DXDACRANGE_MASK        (0x70000000U)
40552 #define DDRPHY_DX8SLBIOCR_DXDACRANGE_SHIFT       (28U)
40553 /*! DXDACRANGE - PVREF_DAC REFSEL range select
40554  */
40555 #define DDRPHY_DX8SLBIOCR_DXDACRANGE(x)          (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SLBIOCR_DXDACRANGE_MASK)
40556 #define DDRPHY_DX8SLBIOCR_RESERVED_31_MASK       (0x80000000U)
40557 #define DDRPHY_DX8SLBIOCR_RESERVED_31_SHIFT      (31U)
40558 /*! RESERVED_31 - Reserved. Return zeroes on reads.
40559  */
40560 #define DDRPHY_DX8SLBIOCR_RESERVED_31(x)         (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SLBIOCR_RESERVED_31_MASK)
40561 /*! @} */
40562 
40563 /*! @name DX4SLBIOCR - DATX4 0-8 I/O Configuration Register */
40564 /*! @{ */
40565 #define DDRPHY_DX4SLBIOCR_RESERVED_31_0_MASK     (0xFFFFFFFFU)
40566 #define DDRPHY_DX4SLBIOCR_RESERVED_31_0_SHIFT    (0U)
40567 /*! RESERVED_31_0 - Reserved. Return zeroes on reads.
40568  */
40569 #define DDRPHY_DX4SLBIOCR_RESERVED_31_0(x)       (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SLBIOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SLBIOCR_RESERVED_31_0_MASK)
40570 /*! @} */
40571 
40572 
40573 /*!
40574  * @}
40575  */ /* end of group DDRPHY_Register_Masks */
40576 
40577 
40578 /* DDRPHY - Peripheral instance base addresses */
40579 /** Peripheral DRC__DDR_PHY base address */
40580 #define DRC__DDR_PHY_BASE                        (0x5C010000u)
40581 /** Peripheral DRC__DDR_PHY base pointer */
40582 #define DRC__DDR_PHY                             ((DDRPHY_Type *)DRC__DDR_PHY_BASE)
40583 /** Array initializer of DDRPHY peripheral base addresses */
40584 #define DDRPHY_BASE_ADDRS                        { DRC__DDR_PHY_BASE }
40585 /** Array initializer of DDRPHY peripheral base pointers */
40586 #define DDRPHY_BASE_PTRS                         { DRC__DDR_PHY }
40587 
40588 /*!
40589  * @}
40590  */ /* end of group DDRPHY_Peripheral_Access_Layer */
40591 
40592 
40593 /* ----------------------------------------------------------------------------
40594    -- DMA Peripheral Access Layer
40595    ---------------------------------------------------------------------------- */
40596 
40597 /*!
40598  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
40599  * @{
40600  */
40601 
40602 /** DMA - Register Layout Typedef */
40603 typedef struct {
40604   __IO uint32_t MP_CSR;                            /**< Management Page Control Register, offset: 0x0 */
40605   __I  uint32_t MP_ES;                             /**< Management Page Error Status Register, offset: 0x4 */
40606        uint8_t RESERVED_0[4];
40607   __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status Register, offset: 0xC */
40608        uint8_t RESERVED_1[240];
40609   __IO uint32_t CH_GRPRI[32];                      /**< Channel Arbitration Group Register, array offset: 0x100, array step: 0x4 */
40610        uint8_t RESERVED_2[65152];
40611   struct {                                         /* offset: 0x10000, array step: 0x10000 */
40612     __IO uint32_t CH_CSR;                            /**< Channel Control and Status Register, array offset: 0x10000, array step: 0x10000 */
40613     __IO uint32_t CH_ES;                             /**< Channel Error Status Register, array offset: 0x10004, array step: 0x10000 */
40614     __IO uint32_t CH_INT;                            /**< Channel Interrupt Status Register, array offset: 0x10008, array step: 0x10000 */
40615     __IO uint32_t CH_SBR;                            /**< Channel System Bus Register, array offset: 0x1000C, array step: 0x10000 */
40616     __IO uint32_t CH_PRI;                            /**< Channel Priority Register, array offset: 0x10010, array step: 0x10000 */
40617     __IO uint32_t CH_MUX;                            /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
40618          uint8_t RESERVED_0[8];
40619     __IO uint32_t TCD_SADDR;                         /**< TCD Source Address Register, array offset: 0x10020, array step: 0x10000 */
40620     __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset Register, array offset: 0x10024, array step: 0x10000 */
40621     __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes Register, array offset: 0x10026, array step: 0x10000 */
40622     union {                                          /* offset: 0x10028, array step: 0x10000 */
40623       __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size without Minor Loop Offsets Register, array offset: 0x10028, array step: 0x10000 */
40624       __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets Register, array offset: 0x10028, array step: 0x10000 */
40625     };
40626     __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address Register, array offset: 0x1002C, array step: 0x10000 */
40627     __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address Register, array offset: 0x10030, array step: 0x10000 */
40628     __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset Register, array offset: 0x10034, array step: 0x10000 */
40629     union {                                          /* offset: 0x10036, array step: 0x10000 */
40630       __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x10036, array step: 0x10000 */
40631       __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x10036, array step: 0x10000 */
40632     };
40633     __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address Register, array offset: 0x10038, array step: 0x10000 */
40634     __IO uint16_t TCD_CSR;                           /**< TCD Control and Status Register, array offset: 0x1003C, array step: 0x10000 */
40635     union {                                          /* offset: 0x1003E, array step: 0x10000 */
40636       __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x1003E, array step: 0x10000 */
40637       __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x1003E, array step: 0x10000 */
40638     };
40639          uint8_t RESERVED_1[65472];
40640   } CH[32];
40641 } DMA_Type;
40642 
40643 /* ----------------------------------------------------------------------------
40644    -- DMA Register Masks
40645    ---------------------------------------------------------------------------- */
40646 
40647 /*!
40648  * @addtogroup DMA_Register_Masks DMA Register Masks
40649  * @{
40650  */
40651 
40652 /*! @name MP_CSR - Management Page Control Register */
40653 /*! @{ */
40654 #define DMA_MP_CSR_EBW_MASK                      (0x1U)
40655 #define DMA_MP_CSR_EBW_SHIFT                     (0U)
40656 /*! EBW - Enable Buffered Writes
40657  *  0b0..Buffered writes on the system bus are disabled.
40658  *  0b1..Buffered writes on the system bus are enabled.
40659  */
40660 #define DMA_MP_CSR_EBW(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EBW_SHIFT)) & DMA_MP_CSR_EBW_MASK)
40661 #define DMA_MP_CSR_EDBG_MASK                     (0x2U)
40662 #define DMA_MP_CSR_EDBG_SHIFT                    (1U)
40663 /*! EDBG - Enable Debug
40664  *  0b0..Debug mode is disabled.
40665  *  0b1..Debug mode is enabled.
40666  */
40667 #define DMA_MP_CSR_EDBG(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)
40668 #define DMA_MP_CSR_ERCA_MASK                     (0x4U)
40669 #define DMA_MP_CSR_ERCA_SHIFT                    (2U)
40670 /*! ERCA - Enable Round Robin Channel Arbitration
40671  *  0b0..Round robin channel arbitration is disabled.
40672  *  0b1..Round robin channel arbitration is enabled.
40673  */
40674 #define DMA_MP_CSR_ERCA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)
40675 #define DMA_MP_CSR_HAE_MASK                      (0x10U)
40676 #define DMA_MP_CSR_HAE_SHIFT                     (4U)
40677 /*! HAE - Halt After Error
40678  *  0b0..Normal operation
40679  *  0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
40680  */
40681 #define DMA_MP_CSR_HAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)
40682 #define DMA_MP_CSR_HALT_MASK                     (0x20U)
40683 #define DMA_MP_CSR_HALT_SHIFT                    (5U)
40684 /*! HALT - Halt DMA Operations
40685  *  0b0..Normal operation
40686  *  0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
40687  */
40688 #define DMA_MP_CSR_HALT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)
40689 #define DMA_MP_CSR_GCLC_MASK                     (0x40U)
40690 #define DMA_MP_CSR_GCLC_SHIFT                    (6U)
40691 /*! GCLC - Global Channel Linking Control
40692  *  0b0..Channel linking is disabled for all channels.
40693  *  0b1..Channel linking is available and controlled by each channel's link settings.
40694  */
40695 #define DMA_MP_CSR_GCLC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)
40696 #define DMA_MP_CSR_GMRC_MASK                     (0x80U)
40697 #define DMA_MP_CSR_GMRC_SHIFT                    (7U)
40698 /*! GMRC - Global Master ID Replication Control
40699  *  0b0..Master ID replication is disabled for all channels.
40700  *  0b1..Master ID replication is available and is controlled by each channel's CHn_SBR[EMI] setting.
40701  */
40702 #define DMA_MP_CSR_GMRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)
40703 #define DMA_MP_CSR_ECX_MASK                      (0x100U)
40704 #define DMA_MP_CSR_ECX_SHIFT                     (8U)
40705 /*! ECX - Cancel Transfer with Error
40706  *  0b0..Normal operation
40707  *  0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
40708  *       force the minor loop to finish. The cancel takes effect after the last write of the current read/write
40709  *       sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX
40710  *       treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an
40711  *       optional error interrupt.
40712  */
40713 #define DMA_MP_CSR_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)
40714 #define DMA_MP_CSR_CX_MASK                       (0x200U)
40715 #define DMA_MP_CSR_CX_SHIFT                      (9U)
40716 /*! CX - Cancel Transfer
40717  *  0b0..Normal operation
40718  *  0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
40719  *       cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
40720  *       the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
40721  */
40722 #define DMA_MP_CSR_CX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)
40723 #define DMA_MP_CSR_ACTIVE_ID_MASK                (0x1F000000U)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
40724 #define DMA_MP_CSR_ACTIVE_ID_SHIFT               (24U)
40725 /*! ACTIVE_ID - Active channel ID
40726  */
40727 #define DMA_MP_CSR_ACTIVE_ID(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
40728 #define DMA_MP_CSR_ACTIVE_MASK                   (0x80000000U)
40729 #define DMA_MP_CSR_ACTIVE_SHIFT                  (31U)
40730 /*! ACTIVE - DMA Active Status
40731  *  0b0..eDMA is idle.
40732  *  0b1..eDMA is executing a channel.
40733  */
40734 #define DMA_MP_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
40735 /*! @} */
40736 
40737 /*! @name MP_ES - Management Page Error Status Register */
40738 /*! @{ */
40739 #define DMA_MP_ES_DBE_MASK                       (0x1U)
40740 #define DMA_MP_ES_DBE_SHIFT                      (0U)
40741 /*! DBE - Destination Bus Error
40742  *  0b0..No destination bus error
40743  *  0b1..The last recorded error was a bus error on a destination write
40744  */
40745 #define DMA_MP_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)
40746 #define DMA_MP_ES_SBE_MASK                       (0x2U)
40747 #define DMA_MP_ES_SBE_SHIFT                      (1U)
40748 /*! SBE - Source Bus Error
40749  *  0b0..No source bus error
40750  *  0b1..The last recorded error was a bus error on a source read
40751  */
40752 #define DMA_MP_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)
40753 #define DMA_MP_ES_SGE_MASK                       (0x4U)
40754 #define DMA_MP_ES_SGE_SHIFT                      (2U)
40755 /*! SGE - Scatter/Gather Configuration Error
40756  *  0b0..No scatter/gather configuration error
40757  *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
40758  *       checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
40759  *       enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
40760  */
40761 #define DMA_MP_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)
40762 #define DMA_MP_ES_NCE_MASK                       (0x8U)
40763 #define DMA_MP_ES_NCE_SHIFT                      (3U)
40764 /*! NCE - NBYTES/CITER Configuration Error
40765  *  0b0..No NBYTES/CITER configuration error
40766  *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
40767  */
40768 #define DMA_MP_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)
40769 #define DMA_MP_ES_DOE_MASK                       (0x10U)
40770 #define DMA_MP_ES_DOE_SHIFT                      (4U)
40771 /*! DOE - Destination Offset Error
40772  *  0b0..No destination offset configuration error
40773  *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
40774  */
40775 #define DMA_MP_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)
40776 #define DMA_MP_ES_DAE_MASK                       (0x20U)
40777 #define DMA_MP_ES_DAE_SHIFT                      (5U)
40778 /*! DAE - Destination Address Error
40779  *  0b0..No destination address configuration error
40780  *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
40781  */
40782 #define DMA_MP_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)
40783 #define DMA_MP_ES_SOE_MASK                       (0x40U)
40784 #define DMA_MP_ES_SOE_SHIFT                      (6U)
40785 /*! SOE - Source Offset Error
40786  *  0b0..No source offset configuration error
40787  *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
40788  */
40789 #define DMA_MP_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)
40790 #define DMA_MP_ES_SAE_MASK                       (0x80U)
40791 #define DMA_MP_ES_SAE_SHIFT                      (7U)
40792 /*! SAE - Source Address Error
40793  *  0b0..No source address configuration error.
40794  *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
40795  */
40796 #define DMA_MP_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)
40797 #define DMA_MP_ES_ECX_MASK                       (0x100U)
40798 #define DMA_MP_ES_ECX_SHIFT                      (8U)
40799 /*! ECX - Transfer Canceled
40800  *  0b0..No canceled transfers
40801  *  0b1..The last recorded entry was a canceled transfer by the error cancel transfer input.
40802  */
40803 #define DMA_MP_ES_ECX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)
40804 #define DMA_MP_ES_ERRCHN_MASK                    (0x1F000000U)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
40805 #define DMA_MP_ES_ERRCHN_SHIFT                   (24U)
40806 /*! ERRCHN - Error Channel Number or Canceled Channel Number
40807  */
40808 #define DMA_MP_ES_ERRCHN(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
40809 #define DMA_MP_ES_VLD_MASK                       (0x80000000U)
40810 #define DMA_MP_ES_VLD_SHIFT                      (31U)
40811 /*! VLD - Valid
40812  *  0b0..No ERR bits are set.
40813  *  0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
40814  */
40815 #define DMA_MP_ES_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
40816 /*! @} */
40817 
40818 /*! @name MP_HRS - Management Page Hardware Request Status Register */
40819 /*! @{ */
40820 #define DMA_MP_HRS_HRS_MASK                      (0xFFFFFFFFU)
40821 #define DMA_MP_HRS_HRS_SHIFT                     (0U)
40822 /*! HRS - Hardware Request Status
40823  *  0b00000000000000000000000000000000..A hardware service request for the channel is not present
40824  *  0b00000000000000000000000000000001..A hardware service request for channel 0 is present
40825  */
40826 #define DMA_MP_HRS_HRS(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
40827 /*! @} */
40828 
40829 /*! @name CH_GRPRI - Channel Arbitration Group Register */
40830 /*! @{ */
40831 #define DMA_CH_GRPRI_GRPRI_MASK                  (0x1FU)
40832 #define DMA_CH_GRPRI_GRPRI_SHIFT                 (0U)
40833 /*! GRPRI - Arbitration Group for channel n.
40834  */
40835 #define DMA_CH_GRPRI_GRPRI(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
40836 /*! @} */
40837 
40838 /* The count of DMA_CH_GRPRI */
40839 #define DMA_CH_GRPRI_COUNT                       (32U)
40840 
40841 /*! @name CH_CSR - Channel Control and Status Register */
40842 /*! @{ */
40843 #define DMA_CH_CSR_ERQ_MASK                      (0x1U)
40844 #define DMA_CH_CSR_ERQ_SHIFT                     (0U)
40845 /*! ERQ - Enable DMA Request
40846  *  0b0..The DMA hardware request signal for the corresponding channel is disabled.
40847  *  0b1..The DMA hardware request signal for the corresponding channel is enabled.
40848  */
40849 #define DMA_CH_CSR_ERQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
40850 #define DMA_CH_CSR_EARQ_MASK                     (0x2U)
40851 #define DMA_CH_CSR_EARQ_SHIFT                    (1U)
40852 /*! EARQ - Enable Asynchronous DMA Request in stop mode for channel
40853  *  0b0..Disable asynchronous DMA request for the channel.
40854  *  0b1..Enable asynchronous DMA request for the channel.
40855  */
40856 #define DMA_CH_CSR_EARQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)
40857 #define DMA_CH_CSR_EEI_MASK                      (0x4U)
40858 #define DMA_CH_CSR_EEI_SHIFT                     (2U)
40859 /*! EEI - Enable Error Interrupt
40860  *  0b0..The error signal for corresponding channel does not generate an error interrupt
40861  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
40862  */
40863 #define DMA_CH_CSR_EEI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)
40864 #define DMA_CH_CSR_DONE_MASK                     (0x40000000U)
40865 #define DMA_CH_CSR_DONE_SHIFT                    (30U)
40866 /*! DONE - Channel Done
40867  */
40868 #define DMA_CH_CSR_DONE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)
40869 #define DMA_CH_CSR_ACTIVE_MASK                   (0x80000000U)
40870 #define DMA_CH_CSR_ACTIVE_SHIFT                  (31U)
40871 /*! ACTIVE - Channel Active
40872  */
40873 #define DMA_CH_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
40874 /*! @} */
40875 
40876 /* The count of DMA_CH_CSR */
40877 #define DMA_CH_CSR_COUNT                         (32U)
40878 
40879 /*! @name CH_ES - Channel Error Status Register */
40880 /*! @{ */
40881 #define DMA_CH_ES_DBE_MASK                       (0x1U)
40882 #define DMA_CH_ES_DBE_SHIFT                      (0U)
40883 /*! DBE - Destination Bus Error
40884  *  0b0..No destination bus error
40885  *  0b1..The last recorded error was a bus error on a destination write
40886  */
40887 #define DMA_CH_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)
40888 #define DMA_CH_ES_SBE_MASK                       (0x2U)
40889 #define DMA_CH_ES_SBE_SHIFT                      (1U)
40890 /*! SBE - Source Bus Error
40891  *  0b0..No source bus error
40892  *  0b1..The last recorded error was a bus error on a source read
40893  */
40894 #define DMA_CH_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)
40895 #define DMA_CH_ES_SGE_MASK                       (0x4U)
40896 #define DMA_CH_ES_SGE_SHIFT                      (2U)
40897 /*! SGE - Scatter/Gather Configuration Error
40898  *  0b0..No scatter/gather configuration error
40899  *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
40900  *       checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
40901  *       enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
40902  */
40903 #define DMA_CH_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)
40904 #define DMA_CH_ES_NCE_MASK                       (0x8U)
40905 #define DMA_CH_ES_NCE_SHIFT                      (3U)
40906 /*! NCE - NBYTES/CITER Configuration Error
40907  *  0b0..No NBYTES/CITER configuration error
40908  *  0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
40909  *       TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero,
40910  *       or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
40911  */
40912 #define DMA_CH_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)
40913 #define DMA_CH_ES_DOE_MASK                       (0x10U)
40914 #define DMA_CH_ES_DOE_SHIFT                      (4U)
40915 /*! DOE - Destination Offset Error
40916  *  0b0..No destination offset configuration error
40917  *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
40918  */
40919 #define DMA_CH_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)
40920 #define DMA_CH_ES_DAE_MASK                       (0x20U)
40921 #define DMA_CH_ES_DAE_SHIFT                      (5U)
40922 /*! DAE - Destination Address Error
40923  *  0b0..No destination address configuration error
40924  *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
40925  */
40926 #define DMA_CH_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)
40927 #define DMA_CH_ES_SOE_MASK                       (0x40U)
40928 #define DMA_CH_ES_SOE_SHIFT                      (6U)
40929 /*! SOE - Source Offset Error
40930  *  0b0..No source offset configuration error
40931  *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
40932  */
40933 #define DMA_CH_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)
40934 #define DMA_CH_ES_SAE_MASK                       (0x80U)
40935 #define DMA_CH_ES_SAE_SHIFT                      (7U)
40936 /*! SAE - Source Address Error
40937  *  0b0..No source address configuration error.
40938  *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
40939  */
40940 #define DMA_CH_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)
40941 #define DMA_CH_ES_ERR_MASK                       (0x80000000U)
40942 #define DMA_CH_ES_ERR_SHIFT                      (31U)
40943 /*! ERR - Error In Channel
40944  *  0b0..An error in this channel has not occurred
40945  *  0b1..An error in this channel has occurred
40946  */
40947 #define DMA_CH_ES_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
40948 /*! @} */
40949 
40950 /* The count of DMA_CH_ES */
40951 #define DMA_CH_ES_COUNT                          (32U)
40952 
40953 /*! @name CH_INT - Channel Interrupt Status Register */
40954 /*! @{ */
40955 #define DMA_CH_INT_INT_MASK                      (0x1U)
40956 #define DMA_CH_INT_INT_SHIFT                     (0U)
40957 /*! INT - Interrupt Request
40958  *  0b0..The interrupt request for corresponding channel is cleared
40959  *  0b1..The interrupt request for corresponding channel is active
40960  */
40961 #define DMA_CH_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
40962 /*! @} */
40963 
40964 /* The count of DMA_CH_INT */
40965 #define DMA_CH_INT_COUNT                         (32U)
40966 
40967 /*! @name CH_SBR - Channel System Bus Register */
40968 /*! @{ */
40969 #define DMA_CH_SBR_MID_MASK                      (0x1FU)
40970 #define DMA_CH_SBR_MID_SHIFT                     (0U)
40971 /*! MID - Master ID
40972  */
40973 #define DMA_CH_SBR_MID(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)
40974 #define DMA_CH_SBR_PAL_MASK                      (0x8000U)
40975 #define DMA_CH_SBR_PAL_SHIFT                     (15U)
40976 /*! PAL - Privileged Access Level
40977  *  0b0..User protection level for DMA transfers
40978  *  0b1..Privileged protection level for DMA transfers
40979  */
40980 #define DMA_CH_SBR_PAL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)
40981 #define DMA_CH_SBR_EMI_MASK                      (0x10000U)
40982 #define DMA_CH_SBR_EMI_SHIFT                     (16U)
40983 /*! EMI - Enable Master ID replication
40984  *  0b0..Master ID replication is disabled
40985  *  0b1..Master ID replication is enabled
40986  */
40987 #define DMA_CH_SBR_EMI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK)
40988 #define DMA_CH_SBR_ATTR_MASK                     (0x7E0000U)
40989 #define DMA_CH_SBR_ATTR_SHIFT                    (17U)
40990 /*! ATTR - Attribute Output
40991  */
40992 #define DMA_CH_SBR_ATTR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK)
40993 /*! @} */
40994 
40995 /* The count of DMA_CH_SBR */
40996 #define DMA_CH_SBR_COUNT                         (32U)
40997 
40998 /*! @name CH_PRI - Channel Priority Register */
40999 /*! @{ */
41000 #define DMA_CH_PRI_APL_MASK                      (0x7U)
41001 #define DMA_CH_PRI_APL_SHIFT                     (0U)
41002 /*! APL - Arbitration Priority Level
41003  */
41004 #define DMA_CH_PRI_APL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)
41005 #define DMA_CH_PRI_DPA_MASK                      (0x40000000U)
41006 #define DMA_CH_PRI_DPA_SHIFT                     (30U)
41007 /*! DPA - Disable Preempt Ability.
41008  *  0b0..The channel can suspend a lower priority channel.
41009  *  0b1..The channel cannot suspend any other channel, regardless of channel priority.
41010  */
41011 #define DMA_CH_PRI_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)
41012 #define DMA_CH_PRI_ECP_MASK                      (0x80000000U)
41013 #define DMA_CH_PRI_ECP_SHIFT                     (31U)
41014 /*! ECP - Enable Channel Preemption.
41015  *  0b0..The channel cannot be suspended by a higher priority channel's service request.
41016  *  0b1..The channel can be temporarily suspended by the service request of a higher priority channel.
41017  */
41018 #define DMA_CH_PRI_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
41019 /*! @} */
41020 
41021 /* The count of DMA_CH_PRI */
41022 #define DMA_CH_PRI_COUNT                         (32U)
41023 
41024 /*! @name CH_MUX - Channel Multiplexor Configuration */
41025 /*! @{ */
41026 #define DMA_CH_MUX_SRC_MASK                      (0x1FU)
41027 #define DMA_CH_MUX_SRC_SHIFT                     (0U)
41028 /*! SRC - Service Request Source
41029  */
41030 #define DMA_CH_MUX_SRC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK)
41031 /*! @} */
41032 
41033 /* The count of DMA_CH_MUX */
41034 #define DMA_CH_MUX_COUNT                         (32U)
41035 
41036 /*! @name TCD_SADDR - TCD Source Address Register */
41037 /*! @{ */
41038 #define DMA_TCD_SADDR_SADDR_MASK                 (0xFFFFFFFFU)
41039 #define DMA_TCD_SADDR_SADDR_SHIFT                (0U)
41040 /*! SADDR - Source Address
41041  */
41042 #define DMA_TCD_SADDR_SADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
41043 /*! @} */
41044 
41045 /* The count of DMA_TCD_SADDR */
41046 #define DMA_TCD_SADDR_COUNT                      (32U)
41047 
41048 /*! @name TCD_SOFF - TCD Signed Source Address Offset Register */
41049 /*! @{ */
41050 #define DMA_TCD_SOFF_SOFF_MASK                   (0xFFFFU)
41051 #define DMA_TCD_SOFF_SOFF_SHIFT                  (0U)
41052 /*! SOFF - Source address signed offset
41053  */
41054 #define DMA_TCD_SOFF_SOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
41055 /*! @} */
41056 
41057 /* The count of DMA_TCD_SOFF */
41058 #define DMA_TCD_SOFF_COUNT                       (32U)
41059 
41060 /*! @name TCD_ATTR - TCD Transfer Attributes Register */
41061 /*! @{ */
41062 #define DMA_TCD_ATTR_DSIZE_MASK                  (0x7U)
41063 #define DMA_TCD_ATTR_DSIZE_SHIFT                 (0U)
41064 /*! DSIZE - Destination data transfer size
41065  */
41066 #define DMA_TCD_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)
41067 #define DMA_TCD_ATTR_DMOD_MASK                   (0xF8U)
41068 #define DMA_TCD_ATTR_DMOD_SHIFT                  (3U)
41069 /*! DMOD - Destination address modulo
41070  */
41071 #define DMA_TCD_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)
41072 #define DMA_TCD_ATTR_SSIZE_MASK                  (0x700U)
41073 #define DMA_TCD_ATTR_SSIZE_SHIFT                 (8U)
41074 /*! SSIZE - Source data transfer size
41075  *  0b000..8-bit
41076  *  0b001..16-bit
41077  *  0b010..32-bit
41078  *  0b011..64-bit
41079  *  0b100..16-byte
41080  *  0b101..32-byte
41081  *  0b110..64-byte
41082  *  0b111..Reserved
41083  */
41084 #define DMA_TCD_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)
41085 #define DMA_TCD_ATTR_SMOD_MASK                   (0xF800U)
41086 #define DMA_TCD_ATTR_SMOD_SHIFT                  (11U)
41087 /*! SMOD - Source address modulo
41088  *  0b00000..Source address modulo feature is disabled
41089  *  0b00001..Source address modulo feature is enabled for any non-zero value [1-31]
41090  */
41091 #define DMA_TCD_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
41092 /*! @} */
41093 
41094 /* The count of DMA_TCD_ATTR */
41095 #define DMA_TCD_ATTR_COUNT                       (32U)
41096 
41097 /*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets Register */
41098 /*! @{ */
41099 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK       (0x3FFFFFFFU)
41100 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT      (0U)
41101 /*! NBYTES - Number of Bytes to transfer per service request
41102  */
41103 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
41104 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK        (0x40000000U)
41105 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT       (30U)
41106 /*! DMLOE - Destination Minor Loop Offset Enable
41107  *  0b0..The minor loop offset is not applied to the DADDR
41108  *  0b1..The minor loop offset is applied to the DADDR
41109  */
41110 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
41111 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK        (0x80000000U)
41112 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT       (31U)
41113 /*! SMLOE - Source Minor Loop Offset Enable
41114  *  0b0..The minor loop offset is not applied to the SADDR
41115  *  0b1..The minor loop offset is applied to the SADDR
41116  */
41117 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
41118 /*! @} */
41119 
41120 /* The count of DMA_TCD_NBYTES_MLOFFNO */
41121 #define DMA_TCD_NBYTES_MLOFFNO_COUNT             (32U)
41122 
41123 /*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets Register */
41124 /*! @{ */
41125 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK      (0x3FFU)
41126 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT     (0U)
41127 /*! NBYTES - Number of Bytes to transfer per service request
41128  */
41129 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)        (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
41130 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK       (0x3FFFFC00U)
41131 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT      (10U)
41132 /*! MLOFF - Minor Loop Offset
41133  */
41134 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
41135 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK       (0x40000000U)
41136 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT      (30U)
41137 /*! DMLOE - Destination Minor Loop Offset Enable
41138  *  0b0..The minor loop offset is not applied to the DADDR
41139  *  0b1..The minor loop offset is applied to the DADDR
41140  */
41141 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
41142 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK       (0x80000000U)
41143 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT      (31U)
41144 /*! SMLOE - Source Minor Loop Offset Enable
41145  *  0b0..The minor loop offset is not applied to the SADDR
41146  *  0b1..The minor loop offset is applied to the SADDR
41147  */
41148 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
41149 /*! @} */
41150 
41151 /* The count of DMA_TCD_NBYTES_MLOFFYES */
41152 #define DMA_TCD_NBYTES_MLOFFYES_COUNT            (32U)
41153 
41154 /*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address Register */
41155 /*! @{ */
41156 #define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK         (0xFFFFFFFFU)
41157 #define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT        (0U)
41158 /*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address
41159  */
41160 #define DMA_TCD_SLAST_SDA_SLAST_SDA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
41161 /*! @} */
41162 
41163 /* The count of DMA_TCD_SLAST_SDA */
41164 #define DMA_TCD_SLAST_SDA_COUNT                  (32U)
41165 
41166 /*! @name TCD_DADDR - TCD Destination Address Register */
41167 /*! @{ */
41168 #define DMA_TCD_DADDR_DADDR_MASK                 (0xFFFFFFFFU)
41169 #define DMA_TCD_DADDR_DADDR_SHIFT                (0U)
41170 /*! DADDR - Destination Address
41171  */
41172 #define DMA_TCD_DADDR_DADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
41173 /*! @} */
41174 
41175 /* The count of DMA_TCD_DADDR */
41176 #define DMA_TCD_DADDR_COUNT                      (32U)
41177 
41178 /*! @name TCD_DOFF - TCD Signed Destination Address Offset Register */
41179 /*! @{ */
41180 #define DMA_TCD_DOFF_DOFF_MASK                   (0xFFFFU)
41181 #define DMA_TCD_DOFF_DOFF_SHIFT                  (0U)
41182 /*! DOFF - Destination Address Signed Offset
41183  */
41184 #define DMA_TCD_DOFF_DOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
41185 /*! @} */
41186 
41187 /* The count of DMA_TCD_DOFF */
41188 #define DMA_TCD_DOFF_COUNT                       (32U)
41189 
41190 /*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register */
41191 /*! @{ */
41192 #define DMA_TCD_CITER_ELINKNO_CITER_MASK         (0x7FFFU)
41193 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT        (0U)
41194 /*! CITER - Current Major Iteration Count
41195  */
41196 #define DMA_TCD_CITER_ELINKNO_CITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)
41197 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK         (0x8000U)
41198 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT        (15U)
41199 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
41200  *  0b0..The channel-to-channel linking is disabled
41201  *  0b1..The channel-to-channel linking is enabled
41202  */
41203 #define DMA_TCD_CITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
41204 /*! @} */
41205 
41206 /* The count of DMA_TCD_CITER_ELINKNO */
41207 #define DMA_TCD_CITER_ELINKNO_COUNT              (32U)
41208 
41209 /*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register */
41210 /*! @{ */
41211 #define DMA_TCD_CITER_ELINKYES_CITER_MASK        (0x1FFU)
41212 #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT       (0U)
41213 /*! CITER - Current Major Iteration Count
41214  */
41215 #define DMA_TCD_CITER_ELINKYES_CITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)
41216 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK       (0x3E00U)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41217 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT      (9U)
41218 /*! LINKCH - Minor Loop Link Channel Number
41219  */
41220 #define DMA_TCD_CITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41221 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK        (0x8000U)
41222 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT       (15U)
41223 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
41224  *  0b0..The channel-to-channel linking is disabled
41225  *  0b1..The channel-to-channel linking is enabled
41226  */
41227 #define DMA_TCD_CITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
41228 /*! @} */
41229 
41230 /* The count of DMA_TCD_CITER_ELINKYES */
41231 #define DMA_TCD_CITER_ELINKYES_COUNT             (32U)
41232 
41233 /*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address Register */
41234 /*! @{ */
41235 #define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK         (0xFFFFFFFFU)
41236 #define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT        (0U)
41237 /*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address
41238  */
41239 #define DMA_TCD_DLAST_SGA_DLAST_SGA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
41240 /*! @} */
41241 
41242 /* The count of DMA_TCD_DLAST_SGA */
41243 #define DMA_TCD_DLAST_SGA_COUNT                  (32U)
41244 
41245 /*! @name TCD_CSR - TCD Control and Status Register */
41246 /*! @{ */
41247 #define DMA_TCD_CSR_START_MASK                   (0x1U)
41248 #define DMA_TCD_CSR_START_SHIFT                  (0U)
41249 /*! START - Channel Start
41250  *  0b0..The channel is not explicitly started.
41251  *  0b1..The channel is explicitly started via a software initiated service request.
41252  */
41253 #define DMA_TCD_CSR_START(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)
41254 #define DMA_TCD_CSR_INTMAJOR_MASK                (0x2U)
41255 #define DMA_TCD_CSR_INTMAJOR_SHIFT               (1U)
41256 /*! INTMAJOR - Enable an interrupt when major iteration count completes.
41257  *  0b0..The end-of-major loop interrupt is disabled.
41258  *  0b1..The end-of-major loop interrupt is enabled.
41259  */
41260 #define DMA_TCD_CSR_INTMAJOR(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)
41261 #define DMA_TCD_CSR_INTHALF_MASK                 (0x4U)
41262 #define DMA_TCD_CSR_INTHALF_SHIFT                (2U)
41263 /*! INTHALF - Enable an interrupt when major counter is half complete.
41264  *  0b0..The half-point interrupt is disabled.
41265  *  0b1..The half-point interrupt is enabled.
41266  */
41267 #define DMA_TCD_CSR_INTHALF(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)
41268 #define DMA_TCD_CSR_DREQ_MASK                    (0x8U)
41269 #define DMA_TCD_CSR_DREQ_SHIFT                   (3U)
41270 /*! DREQ - Disable request
41271  *  0b0..No operation
41272  *  0b1..Clear the ERQ bit upon major loop completion, thus disabling hardware service requests.
41273  */
41274 #define DMA_TCD_CSR_DREQ(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
41275 #define DMA_TCD_CSR_ESG_MASK                     (0x10U)
41276 #define DMA_TCD_CSR_ESG_SHIFT                    (4U)
41277 /*! ESG - Enable Scatter/Gather processing
41278  *  0b0..The current channel's TCD is normal format.
41279  *  0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer
41280  *       to the next TCD to be loaded into this channel after the major loop completes its execution.
41281  */
41282 #define DMA_TCD_CSR_ESG(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)
41283 #define DMA_TCD_CSR_MAJORELINK_MASK              (0x20U)
41284 #define DMA_TCD_CSR_MAJORELINK_SHIFT             (5U)
41285 /*! MAJORELINK - Enable channel-to-channel linking on major loop complete
41286  *  0b0..The channel-to-channel linking is disabled.
41287  *  0b1..The channel-to-channel linking is enabled.
41288  */
41289 #define DMA_TCD_CSR_MAJORELINK(x)                (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)
41290 #define DMA_TCD_CSR_EEOP_MASK                    (0x40U)
41291 #define DMA_TCD_CSR_EEOP_SHIFT                   (6U)
41292 /*! EEOP - Enable end-of-packet processing
41293  *  0b0..The end-of-packet operation is disabled.
41294  *  0b1..The end-of-packet hardware input signal is enabled.
41295  */
41296 #define DMA_TCD_CSR_EEOP(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)
41297 #define DMA_TCD_CSR_ESDA_MASK                    (0x80U)
41298 #define DMA_TCD_CSR_ESDA_SHIFT                   (7U)
41299 /*! ESDA - Enable store destination address
41300  *  0b0..The store destination address to system memory operation is disabled.
41301  *  0b1..The store destination address to system memory operation is enabled.
41302  */
41303 #define DMA_TCD_CSR_ESDA(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)
41304 #define DMA_TCD_CSR_MAJORLINKCH_MASK             (0x1F00U)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41305 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT            (8U)
41306 /*! MAJORLINKCH - Major loop link channel number
41307  */
41308 #define DMA_TCD_CSR_MAJORLINKCH(x)               (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41309 #define DMA_TCD_CSR_BWC_MASK                     (0xC000U)
41310 #define DMA_TCD_CSR_BWC_SHIFT                    (14U)
41311 /*! BWC - Bandwidth Control
41312  *  0b00..No eDMA engine stalls.
41313  *  0b01..Reserved
41314  *  0b10..eDMA engine stalls for 4 cycles after each R/W.
41315  *  0b11..eDMA engine stalls for 8 cycles after each R/W.
41316  */
41317 #define DMA_TCD_CSR_BWC(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
41318 /*! @} */
41319 
41320 /* The count of DMA_TCD_CSR */
41321 #define DMA_TCD_CSR_COUNT                        (32U)
41322 
41323 /*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register */
41324 /*! @{ */
41325 #define DMA_TCD_BITER_ELINKNO_BITER_MASK         (0x7FFFU)
41326 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT        (0U)
41327 /*! BITER - Starting Major Iteration Count
41328  */
41329 #define DMA_TCD_BITER_ELINKNO_BITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)
41330 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK         (0x8000U)
41331 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT        (15U)
41332 /*! ELINK - Enables channel-to-channel linking on minor loop complete
41333  *  0b0..The channel-to-channel linking is disabled
41334  *  0b1..The channel-to-channel linking is enabled
41335  */
41336 #define DMA_TCD_BITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
41337 /*! @} */
41338 
41339 /* The count of DMA_TCD_BITER_ELINKNO */
41340 #define DMA_TCD_BITER_ELINKNO_COUNT              (32U)
41341 
41342 /*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register */
41343 /*! @{ */
41344 #define DMA_TCD_BITER_ELINKYES_BITER_MASK        (0x1FFU)
41345 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT       (0U)
41346 /*! BITER - Starting major iteration count
41347  */
41348 #define DMA_TCD_BITER_ELINKYES_BITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)
41349 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK       (0x3E00U)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41350 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT      (9U)
41351 /*! LINKCH - Link Channel Number
41352  */
41353 #define DMA_TCD_BITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)  /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41354 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK        (0x8000U)
41355 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT       (15U)
41356 /*! ELINK - Enables channel-to-channel linking on minor loop complete
41357  *  0b0..The channel-to-channel linking is disabled
41358  *  0b1..The channel-to-channel linking is enabled
41359  */
41360 #define DMA_TCD_BITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
41361 /*! @} */
41362 
41363 /* The count of DMA_TCD_BITER_ELINKYES */
41364 #define DMA_TCD_BITER_ELINKYES_COUNT             (32U)
41365 
41366 
41367 /*!
41368  * @}
41369  */ /* end of group DMA_Register_Masks */
41370 
41371 
41372 /* DMA - Peripheral instance base addresses */
41373 /** Peripheral ADMA__EDMA0 base address */
41374 #define ADMA__EDMA0_BASE                         (0x591F0000u)
41375 /** Peripheral ADMA__EDMA0 base pointer */
41376 #define ADMA__EDMA0                              ((DMA_Type *)ADMA__EDMA0_BASE)
41377 /** Peripheral ADMA__EDMA1 base address */
41378 #define ADMA__EDMA1_BASE                         (0x599F0000u)
41379 /** Peripheral ADMA__EDMA1 base pointer */
41380 #define ADMA__EDMA1                              ((DMA_Type *)ADMA__EDMA1_BASE)
41381 /** Peripheral ADMA__EDMA2 base address */
41382 #define ADMA__EDMA2_BASE                         (0x5A1F0000u)
41383 /** Peripheral ADMA__EDMA2 base pointer */
41384 #define ADMA__EDMA2                              ((DMA_Type *)ADMA__EDMA2_BASE)
41385 /** Peripheral ADMA__EDMA3 base address */
41386 #define ADMA__EDMA3_BASE                         (0x5A9F0000u)
41387 /** Peripheral ADMA__EDMA3 base pointer */
41388 #define ADMA__EDMA3                              ((DMA_Type *)ADMA__EDMA3_BASE)
41389 /** Peripheral CONNECTIVITY__EDMA base address */
41390 #define CONNECTIVITY__EDMA_BASE                  (0x5B070000u)
41391 /** Peripheral CONNECTIVITY__EDMA base pointer */
41392 #define CONNECTIVITY__EDMA                       ((DMA_Type *)CONNECTIVITY__EDMA_BASE)
41393 /** Array initializer of DMA peripheral base addresses */
41394 #define DMA_BASE_ADDRS                           { ADMA__EDMA0_BASE, ADMA__EDMA1_BASE, ADMA__EDMA2_BASE, ADMA__EDMA3_BASE, CONNECTIVITY__EDMA_BASE }
41395 /** Array initializer of DMA peripheral base pointers */
41396 #define DMA_BASE_PTRS                            { ADMA__EDMA0, ADMA__EDMA1, ADMA__EDMA2, ADMA__EDMA3, CONNECTIVITY__EDMA }
41397 /** Interrupt vectors for the DMA peripheral type */
41398 #define DMA_IRQS                                 { { ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn }, \
41399                                                    { ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn }, \
41400                                                    { ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn }, \
41401                                                    { ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn }, \
41402                                                    { CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn } }
41403 #define DMA_ERROR_IRQS                           { ADMA_EDMA0_ERR_INT_IRQn, ADMA_EDMA1_ERR_INT_IRQn, ADMA_EDMA2_ERR_INT_IRQn, ADMA_EDMA3_ERR_INT_IRQn, CONNECTIVITY_DMA_ERR_INT_IRQn }
41404 
41405 /*!
41406  * @}
41407  */ /* end of group DMA_Peripheral_Access_Layer */
41408 
41409 
41410 /* ----------------------------------------------------------------------------
41411    -- ENET Peripheral Access Layer
41412    ---------------------------------------------------------------------------- */
41413 
41414 /*!
41415  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
41416  * @{
41417  */
41418 
41419 /** ENET - Register Layout Typedef */
41420 typedef struct {
41421        uint8_t RESERVED_0[4];
41422   __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
41423   __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
41424        uint8_t RESERVED_1[4];
41425   __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
41426   __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
41427        uint8_t RESERVED_2[12];
41428   __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
41429        uint8_t RESERVED_3[24];
41430   __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
41431   __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
41432        uint8_t RESERVED_4[28];
41433   __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
41434        uint8_t RESERVED_5[28];
41435   __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
41436        uint8_t RESERVED_6[60];
41437   __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
41438        uint8_t RESERVED_7[28];
41439   __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
41440   __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
41441   __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
41442   __IO uint32_t TXIC[3];                           /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
41443        uint8_t RESERVED_8[4];
41444   __IO uint32_t RXIC[3];                           /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
41445        uint8_t RESERVED_9[12];
41446   __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
41447   __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
41448   __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
41449   __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
41450        uint8_t RESERVED_10[28];
41451   __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
41452        uint8_t RESERVED_11[24];
41453   __IO uint32_t RDSR1;                             /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
41454   __IO uint32_t TDSR1;                             /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
41455   __IO uint32_t MRBR1;                             /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
41456   __IO uint32_t RDSR2;                             /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
41457   __IO uint32_t TDSR2;                             /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
41458   __IO uint32_t MRBR2;                             /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
41459        uint8_t RESERVED_12[8];
41460   __IO uint32_t RDSR;                              /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
41461   __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
41462   __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
41463        uint8_t RESERVED_13[4];
41464   __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
41465   __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
41466   __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
41467   __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
41468   __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
41469   __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
41470   __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
41471   __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
41472   __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
41473        uint8_t RESERVED_14[12];
41474   __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
41475   __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
41476   __IO uint32_t RCMR[2];                           /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
41477        uint8_t RESERVED_15[8];
41478   __IO uint32_t DMACFG[2];                         /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
41479   __IO uint32_t RDAR1;                             /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
41480   __IO uint32_t TDAR1;                             /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
41481   __IO uint32_t RDAR2;                             /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
41482   __IO uint32_t TDAR2;                             /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
41483   __IO uint32_t QOS;                               /**< QOS Scheme, offset: 0x1F0 */
41484        uint8_t RESERVED_16[12];
41485        uint32_t RMON_T_DROP;                       /**< Reserved Statistic Register, offset: 0x200 */
41486   __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
41487   __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
41488   __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
41489   __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
41490   __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
41491   __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
41492   __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
41493   __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
41494   __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
41495   __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
41496   __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
41497   __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
41498   __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
41499   __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
41500   __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
41501   __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
41502   __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
41503        uint32_t IEEE_T_DROP;                       /**< Reserved Statistic Register, offset: 0x248 */
41504   __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
41505   __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
41506   __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
41507   __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
41508   __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
41509   __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
41510   __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
41511   __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
41512   __I  uint32_t IEEE_T_SQE;                        /**< Reserved Statistic Register, offset: 0x26C */
41513   __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
41514   __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
41515        uint8_t RESERVED_17[12];
41516   __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
41517   __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
41518   __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
41519   __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
41520   __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
41521   __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
41522   __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
41523   __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
41524        uint32_t RMON_R_RESVD_0;                    /**< Reserved Statistic Register, offset: 0x2A4 */
41525   __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
41526   __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
41527   __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
41528   __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
41529   __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
41530   __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
41531   __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
41532   __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
41533   __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
41534   __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
41535   __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
41536   __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
41537   __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
41538   __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
41539   __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
41540        uint8_t RESERVED_18[284];
41541   __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
41542   __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
41543   __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
41544   __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
41545   __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
41546   __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
41547   __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
41548        uint8_t RESERVED_19[356];
41549   __IO uint32_t MDATA;                             /**< Pattern Match Data Register, offset: 0x580 */
41550   __IO uint32_t MMASK;                             /**< Match Entry Mask Register, offset: 0x584 */
41551   __IO uint32_t MCONFIG;                           /**< Match Entry Rules Configuration Register, offset: 0x588 */
41552   __IO uint32_t MENTRYRW;                          /**< Match Entry Read/Write Command Register, offset: 0x58C */
41553   __IO uint32_t RXPCTL;                            /**< Receive Parser Control Register, offset: 0x590 */
41554   __IO uint32_t MAXFRMOFF;                         /**< Maximum Frame Offset, offset: 0x594 */
41555   __I  uint32_t RXPARST;                           /**< Receive Parser Status, offset: 0x598 */
41556        uint8_t RESERVED_20[4];
41557   __I  uint32_t PARSDSCD;                          /**< Parser Discard Count, offset: 0x5A0 */
41558   __I  uint32_t PRSACPT0;                          /**< Parser Accept Count 0, offset: 0x5A4 */
41559   __I  uint32_t PRSRJCT0;                          /**< Parser Reject Count 0, offset: 0x5A8 */
41560   __I  uint32_t PRSACPT1;                          /**< Parser Accept Count 1, offset: 0x5AC */
41561   __I  uint32_t PRSRJCT1;                          /**< Parser Reject Count 1, offset: 0x5B0 */
41562   __I  uint32_t PRSACPT2;                          /**< Parser Accept Count 2, offset: 0x5B4 */
41563   __I  uint32_t PRSRJCT2;                          /**< Parser Reject Count 2, offset: 0x5B8 */
41564        uint8_t RESERVED_21[72];
41565   __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
41566   struct {                                         /* offset: 0x608, array step: 0x8 */
41567     __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
41568     __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
41569   } CHANNEL[4];
41570 } ENET_Type;
41571 
41572 /* ----------------------------------------------------------------------------
41573    -- ENET Register Masks
41574    ---------------------------------------------------------------------------- */
41575 
41576 /*!
41577  * @addtogroup ENET_Register_Masks ENET Register Masks
41578  * @{
41579  */
41580 
41581 /*! @name EIR - Interrupt Event Register */
41582 /*! @{ */
41583 #define ENET_EIR_RXB1_MASK                       (0x1U)
41584 #define ENET_EIR_RXB1_SHIFT                      (0U)
41585 /*! RXB1 - Receive buffer interrupt, class 1
41586  */
41587 #define ENET_EIR_RXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
41588 #define ENET_EIR_RXF1_MASK                       (0x2U)
41589 #define ENET_EIR_RXF1_SHIFT                      (1U)
41590 /*! RXF1 - Receive frame interrupt, class 1
41591  */
41592 #define ENET_EIR_RXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
41593 #define ENET_EIR_TXB1_MASK                       (0x4U)
41594 #define ENET_EIR_TXB1_SHIFT                      (2U)
41595 /*! TXB1 - Transmit buffer interrupt, class 1
41596  */
41597 #define ENET_EIR_TXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
41598 #define ENET_EIR_TXF1_MASK                       (0x8U)
41599 #define ENET_EIR_TXF1_SHIFT                      (3U)
41600 /*! TXF1 - Transmit frame interrupt, class 1
41601  */
41602 #define ENET_EIR_TXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
41603 #define ENET_EIR_RXB2_MASK                       (0x10U)
41604 #define ENET_EIR_RXB2_SHIFT                      (4U)
41605 /*! RXB2 - Receive buffer interrupt, class 2
41606  */
41607 #define ENET_EIR_RXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
41608 #define ENET_EIR_RXF2_MASK                       (0x20U)
41609 #define ENET_EIR_RXF2_SHIFT                      (5U)
41610 /*! RXF2 - Receive frame interrupt, class 2
41611  */
41612 #define ENET_EIR_RXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
41613 #define ENET_EIR_TXB2_MASK                       (0x40U)
41614 #define ENET_EIR_TXB2_SHIFT                      (6U)
41615 /*! TXB2 - Transmit buffer interrupt, class 2
41616  */
41617 #define ENET_EIR_TXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
41618 #define ENET_EIR_TXF2_MASK                       (0x80U)
41619 #define ENET_EIR_TXF2_SHIFT                      (7U)
41620 /*! TXF2 - Transmit frame interrupt, class 2
41621  */
41622 #define ENET_EIR_TXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
41623 #define ENET_EIR_PARSRF_MASK                     (0x200U)
41624 #define ENET_EIR_PARSRF_SHIFT                    (9U)
41625 #define ENET_EIR_PARSRF(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PARSRF_SHIFT)) & ENET_EIR_PARSRF_MASK)
41626 #define ENET_EIR_PARSERR_MASK                    (0x400U)
41627 #define ENET_EIR_PARSERR_SHIFT                   (10U)
41628 #define ENET_EIR_PARSERR(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PARSERR_SHIFT)) & ENET_EIR_PARSERR_MASK)
41629 #define ENET_EIR_RXFLUSH_0_MASK                  (0x1000U)
41630 #define ENET_EIR_RXFLUSH_0_SHIFT                 (12U)
41631 #define ENET_EIR_RXFLUSH_0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
41632 #define ENET_EIR_RXFLUSH_1_MASK                  (0x2000U)
41633 #define ENET_EIR_RXFLUSH_1_SHIFT                 (13U)
41634 #define ENET_EIR_RXFLUSH_1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
41635 #define ENET_EIR_RXFLUSH_2_MASK                  (0x4000U)
41636 #define ENET_EIR_RXFLUSH_2_SHIFT                 (14U)
41637 #define ENET_EIR_RXFLUSH_2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
41638 #define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
41639 #define ENET_EIR_TS_TIMER_SHIFT                  (15U)
41640 /*! TS_TIMER - Timestamp Timer
41641  */
41642 #define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
41643 #define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
41644 #define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
41645 /*! TS_AVAIL - Transmit Timestamp Available
41646  */
41647 #define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
41648 #define ENET_EIR_WAKEUP_MASK                     (0x20000U)
41649 #define ENET_EIR_WAKEUP_SHIFT                    (17U)
41650 /*! WAKEUP - Node Wakeup Request Indication
41651  */
41652 #define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
41653 #define ENET_EIR_PLR_MASK                        (0x40000U)
41654 #define ENET_EIR_PLR_SHIFT                       (18U)
41655 /*! PLR - Payload Receive Error
41656  */
41657 #define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
41658 #define ENET_EIR_UN_MASK                         (0x80000U)
41659 #define ENET_EIR_UN_SHIFT                        (19U)
41660 /*! UN - Transmit FIFO Underrun
41661  */
41662 #define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
41663 #define ENET_EIR_RL_MASK                         (0x100000U)
41664 #define ENET_EIR_RL_SHIFT                        (20U)
41665 /*! RL - Collision Retry Limit
41666  */
41667 #define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
41668 #define ENET_EIR_LC_MASK                         (0x200000U)
41669 #define ENET_EIR_LC_SHIFT                        (21U)
41670 /*! LC - Late Collision
41671  */
41672 #define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
41673 #define ENET_EIR_EBERR_MASK                      (0x400000U)
41674 #define ENET_EIR_EBERR_SHIFT                     (22U)
41675 /*! EBERR - Ethernet Bus Error
41676  */
41677 #define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
41678 #define ENET_EIR_MII_MASK                        (0x800000U)
41679 #define ENET_EIR_MII_SHIFT                       (23U)
41680 /*! MII - MII Interrupt.
41681  */
41682 #define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
41683 #define ENET_EIR_RXB_MASK                        (0x1000000U)
41684 #define ENET_EIR_RXB_SHIFT                       (24U)
41685 /*! RXB - Receive Buffer Interrupt
41686  */
41687 #define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
41688 #define ENET_EIR_RXF_MASK                        (0x2000000U)
41689 #define ENET_EIR_RXF_SHIFT                       (25U)
41690 /*! RXF - Receive Frame Interrupt
41691  */
41692 #define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
41693 #define ENET_EIR_TXB_MASK                        (0x4000000U)
41694 #define ENET_EIR_TXB_SHIFT                       (26U)
41695 /*! TXB - Transmit Buffer Interrupt
41696  */
41697 #define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
41698 #define ENET_EIR_TXF_MASK                        (0x8000000U)
41699 #define ENET_EIR_TXF_SHIFT                       (27U)
41700 /*! TXF - Transmit Frame Interrupt
41701  */
41702 #define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
41703 #define ENET_EIR_GRA_MASK                        (0x10000000U)
41704 #define ENET_EIR_GRA_SHIFT                       (28U)
41705 /*! GRA - Graceful Stop Complete
41706  */
41707 #define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
41708 #define ENET_EIR_BABT_MASK                       (0x20000000U)
41709 #define ENET_EIR_BABT_SHIFT                      (29U)
41710 /*! BABT - Babbling Transmit Error
41711  */
41712 #define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
41713 #define ENET_EIR_BABR_MASK                       (0x40000000U)
41714 #define ENET_EIR_BABR_SHIFT                      (30U)
41715 /*! BABR - Babbling Receive Error
41716  */
41717 #define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
41718 /*! @} */
41719 
41720 /*! @name EIMR - Interrupt Mask Register */
41721 /*! @{ */
41722 #define ENET_EIMR_RXB1_MASK                      (0x1U)
41723 #define ENET_EIMR_RXB1_SHIFT                     (0U)
41724 /*! RXB1 - Receive buffer interrupt, class 1
41725  */
41726 #define ENET_EIMR_RXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
41727 #define ENET_EIMR_RXF1_MASK                      (0x2U)
41728 #define ENET_EIMR_RXF1_SHIFT                     (1U)
41729 /*! RXF1 - Receive frame interrupt, class 1
41730  */
41731 #define ENET_EIMR_RXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
41732 #define ENET_EIMR_TXB1_MASK                      (0x4U)
41733 #define ENET_EIMR_TXB1_SHIFT                     (2U)
41734 /*! TXB1 - Transmit buffer interrupt, class 1
41735  */
41736 #define ENET_EIMR_TXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
41737 #define ENET_EIMR_TXF1_MASK                      (0x8U)
41738 #define ENET_EIMR_TXF1_SHIFT                     (3U)
41739 /*! TXF1 - Transmit frame interrupt, class 1
41740  */
41741 #define ENET_EIMR_TXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
41742 #define ENET_EIMR_RXB2_MASK                      (0x10U)
41743 #define ENET_EIMR_RXB2_SHIFT                     (4U)
41744 /*! RXB2 - Receive buffer interrupt, class 2
41745  */
41746 #define ENET_EIMR_RXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
41747 #define ENET_EIMR_RXF2_MASK                      (0x20U)
41748 #define ENET_EIMR_RXF2_SHIFT                     (5U)
41749 /*! RXF2 - Receive frame interrupt, class 2
41750  */
41751 #define ENET_EIMR_RXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
41752 #define ENET_EIMR_TXB2_MASK                      (0x40U)
41753 #define ENET_EIMR_TXB2_SHIFT                     (6U)
41754 /*! TXB2 - Transmit buffer interrupt, class 2
41755  */
41756 #define ENET_EIMR_TXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
41757 #define ENET_EIMR_TXF2_MASK                      (0x80U)
41758 #define ENET_EIMR_TXF2_SHIFT                     (7U)
41759 /*! TXF2 - Transmit frame interrupt, class 2
41760  */
41761 #define ENET_EIMR_TXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
41762 #define ENET_EIMR_PARSRF_MASK                    (0x200U)
41763 #define ENET_EIMR_PARSRF_SHIFT                   (9U)
41764 #define ENET_EIMR_PARSRF(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PARSRF_SHIFT)) & ENET_EIMR_PARSRF_MASK)
41765 #define ENET_EIMR_PARSERR_MASK                   (0x400U)
41766 #define ENET_EIMR_PARSERR_SHIFT                  (10U)
41767 #define ENET_EIMR_PARSERR(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PARSERR_SHIFT)) & ENET_EIMR_PARSERR_MASK)
41768 #define ENET_EIMR_RXFLUSH_0_MASK                 (0x1000U)
41769 #define ENET_EIMR_RXFLUSH_0_SHIFT                (12U)
41770 #define ENET_EIMR_RXFLUSH_0(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
41771 #define ENET_EIMR_RXFLUSH_1_MASK                 (0x2000U)
41772 #define ENET_EIMR_RXFLUSH_1_SHIFT                (13U)
41773 #define ENET_EIMR_RXFLUSH_1(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
41774 #define ENET_EIMR_RXFLUSH_2_MASK                 (0x4000U)
41775 #define ENET_EIMR_RXFLUSH_2_SHIFT                (14U)
41776 #define ENET_EIMR_RXFLUSH_2(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
41777 #define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
41778 #define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
41779 /*! TS_TIMER - TS_TIMER Interrupt Mask
41780  */
41781 #define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
41782 #define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
41783 #define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
41784 /*! TS_AVAIL - TS_AVAIL Interrupt Mask
41785  */
41786 #define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
41787 #define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
41788 #define ENET_EIMR_WAKEUP_SHIFT                   (17U)
41789 /*! WAKEUP - WAKEUP Interrupt Mask
41790  */
41791 #define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
41792 #define ENET_EIMR_PLR_MASK                       (0x40000U)
41793 #define ENET_EIMR_PLR_SHIFT                      (18U)
41794 /*! PLR - PLR Interrupt Mask
41795  */
41796 #define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
41797 #define ENET_EIMR_UN_MASK                        (0x80000U)
41798 #define ENET_EIMR_UN_SHIFT                       (19U)
41799 /*! UN - UN Interrupt Mask
41800  */
41801 #define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
41802 #define ENET_EIMR_RL_MASK                        (0x100000U)
41803 #define ENET_EIMR_RL_SHIFT                       (20U)
41804 /*! RL - RL Interrupt Mask
41805  */
41806 #define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
41807 #define ENET_EIMR_LC_MASK                        (0x200000U)
41808 #define ENET_EIMR_LC_SHIFT                       (21U)
41809 /*! LC - LC Interrupt Mask
41810  */
41811 #define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
41812 #define ENET_EIMR_EBERR_MASK                     (0x400000U)
41813 #define ENET_EIMR_EBERR_SHIFT                    (22U)
41814 /*! EBERR - EBERR Interrupt Mask
41815  */
41816 #define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
41817 #define ENET_EIMR_MII_MASK                       (0x800000U)
41818 #define ENET_EIMR_MII_SHIFT                      (23U)
41819 /*! MII - MII Interrupt Mask
41820  */
41821 #define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
41822 #define ENET_EIMR_RXB_MASK                       (0x1000000U)
41823 #define ENET_EIMR_RXB_SHIFT                      (24U)
41824 /*! RXB - RXB Interrupt Mask
41825  */
41826 #define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
41827 #define ENET_EIMR_RXF_MASK                       (0x2000000U)
41828 #define ENET_EIMR_RXF_SHIFT                      (25U)
41829 /*! RXF - RXF Interrupt Mask
41830  */
41831 #define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
41832 #define ENET_EIMR_TXB_MASK                       (0x4000000U)
41833 #define ENET_EIMR_TXB_SHIFT                      (26U)
41834 /*! TXB - TXB Interrupt Mask
41835  *  0b0..The corresponding interrupt source is masked.
41836  *  0b1..The corresponding interrupt source is not masked.
41837  */
41838 #define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
41839 #define ENET_EIMR_TXF_MASK                       (0x8000000U)
41840 #define ENET_EIMR_TXF_SHIFT                      (27U)
41841 /*! TXF - TXF Interrupt Mask
41842  *  0b0..The corresponding interrupt source is masked.
41843  *  0b1..The corresponding interrupt source is not masked.
41844  */
41845 #define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
41846 #define ENET_EIMR_GRA_MASK                       (0x10000000U)
41847 #define ENET_EIMR_GRA_SHIFT                      (28U)
41848 /*! GRA - GRA Interrupt Mask
41849  *  0b0..The corresponding interrupt source is masked.
41850  *  0b1..The corresponding interrupt source is not masked.
41851  */
41852 #define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
41853 #define ENET_EIMR_BABT_MASK                      (0x20000000U)
41854 #define ENET_EIMR_BABT_SHIFT                     (29U)
41855 /*! BABT - BABT Interrupt Mask
41856  *  0b0..The corresponding interrupt source is masked.
41857  *  0b1..The corresponding interrupt source is not masked.
41858  */
41859 #define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
41860 #define ENET_EIMR_BABR_MASK                      (0x40000000U)
41861 #define ENET_EIMR_BABR_SHIFT                     (30U)
41862 /*! BABR - BABR Interrupt Mask
41863  *  0b0..The corresponding interrupt source is masked.
41864  *  0b1..The corresponding interrupt source is not masked.
41865  */
41866 #define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
41867 /*! @} */
41868 
41869 /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
41870 /*! @{ */
41871 #define ENET_RDAR_RDAR_MASK                      (0x1000000U)
41872 #define ENET_RDAR_RDAR_SHIFT                     (24U)
41873 /*! RDAR - Receive Descriptor Active
41874  */
41875 #define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
41876 /*! @} */
41877 
41878 /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
41879 /*! @{ */
41880 #define ENET_TDAR_TDAR_MASK                      (0x1000000U)
41881 #define ENET_TDAR_TDAR_SHIFT                     (24U)
41882 /*! TDAR - Transmit Descriptor Active
41883  */
41884 #define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
41885 /*! @} */
41886 
41887 /*! @name ECR - Ethernet Control Register */
41888 /*! @{ */
41889 #define ENET_ECR_RESET_MASK                      (0x1U)
41890 #define ENET_ECR_RESET_SHIFT                     (0U)
41891 /*! RESET - Ethernet MAC Reset
41892  */
41893 #define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
41894 #define ENET_ECR_ETHEREN_MASK                    (0x2U)
41895 #define ENET_ECR_ETHEREN_SHIFT                   (1U)
41896 /*! ETHEREN - Ethernet Enable
41897  *  0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
41898  *  0b1..MAC is enabled, and reception and transmission are possible.
41899  */
41900 #define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
41901 #define ENET_ECR_MAGICEN_MASK                    (0x4U)
41902 #define ENET_ECR_MAGICEN_SHIFT                   (2U)
41903 /*! MAGICEN - Magic Packet Detection Enable
41904  *  0b0..Magic detection logic disabled.
41905  *  0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
41906  */
41907 #define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
41908 #define ENET_ECR_SLEEP_MASK                      (0x8U)
41909 #define ENET_ECR_SLEEP_SHIFT                     (3U)
41910 /*! SLEEP - Sleep Mode Enable
41911  *  0b0..Normal operating mode.
41912  *  0b1..Sleep mode.
41913  */
41914 #define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
41915 #define ENET_ECR_EN1588_MASK                     (0x10U)
41916 #define ENET_ECR_EN1588_SHIFT                    (4U)
41917 /*! EN1588 - EN1588 Enable
41918  *  0b0..Legacy FEC buffer descriptors and functions enabled.
41919  *  0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.
41920  */
41921 #define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
41922 #define ENET_ECR_SPEED_MASK                      (0x20U)
41923 #define ENET_ECR_SPEED_SHIFT                     (5U)
41924 /*! SPEED
41925  *  0b0..10/100-Mbit/s mode
41926  *  0b1..1000-Mbit/s mode
41927  */
41928 #define ENET_ECR_SPEED(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
41929 #define ENET_ECR_DBGEN_MASK                      (0x40U)
41930 #define ENET_ECR_DBGEN_SHIFT                     (6U)
41931 /*! DBGEN - Debug Enable
41932  *  0b0..MAC continues operation in debug mode.
41933  *  0b1..MAC enters hardware freeze mode when the processor is in debug mode.
41934  */
41935 #define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
41936 #define ENET_ECR_DBSWP_MASK                      (0x100U)
41937 #define ENET_ECR_DBSWP_SHIFT                     (8U)
41938 /*! DBSWP - Descriptor Byte Swapping Enable
41939  *  0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
41940  *  0b1..The buffer descriptor bytes are swapped to support little-endian devices.
41941  */
41942 #define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
41943 #define ENET_ECR_SVLANEN_MASK                    (0x200U)
41944 #define ENET_ECR_SVLANEN_SHIFT                   (9U)
41945 /*! SVLANEN - S-VLAN enable
41946  *  0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
41947  *  0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
41948  *       receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
41949  *       classification match comparators, RCMRn.
41950  */
41951 #define ENET_ECR_SVLANEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
41952 #define ENET_ECR_VLANUSE2ND_MASK                 (0x400U)
41953 #define ENET_ECR_VLANUSE2ND_SHIFT                (10U)
41954 /*! VLANUSE2ND - VLAN use second tag
41955  *  0b0..Always extract data from the first VLAN tag if it exists.
41956  *  0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
41957  *       double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
41958  *       second tag must be a C-VLAN
41959  */
41960 #define ENET_ECR_VLANUSE2ND(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
41961 #define ENET_ECR_SVLANDBL_MASK                   (0x800U)
41962 #define ENET_ECR_SVLANDBL_SHIFT                  (11U)
41963 /*! SVLANDBL - S-VLAN double tag
41964  */
41965 #define ENET_ECR_SVLANDBL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
41966 #define ENET_ECR_TXC_DLY_MASK                    (0x10000U)
41967 #define ENET_ECR_TXC_DLY_SHIFT                   (16U)
41968 /*! TXC_DLY - Transmit clock delay
41969  *  0b0..RGMII_TXC is not delayed.
41970  *  0b1..Generate delayed version of RGMII_TXC.
41971  */
41972 #define ENET_ECR_TXC_DLY(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)
41973 #define ENET_ECR_RXC_DLY_MASK                    (0x20000U)
41974 #define ENET_ECR_RXC_DLY_SHIFT                   (17U)
41975 /*! RXC_DLY - Receive clock delay
41976  *  0b0..Use non-delayed version of RGMII_RXC.
41977  *  0b1..Use delayed version of RGMII_RXC.
41978  */
41979 #define ENET_ECR_RXC_DLY(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RXC_DLY_SHIFT)) & ENET_ECR_RXC_DLY_MASK)
41980 /*! @} */
41981 
41982 /*! @name MMFR - MII Management Frame Register */
41983 /*! @{ */
41984 #define ENET_MMFR_DATA_MASK                      (0xFFFFU)
41985 #define ENET_MMFR_DATA_SHIFT                     (0U)
41986 /*! DATA - Management Frame Data
41987  */
41988 #define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
41989 #define ENET_MMFR_TA_MASK                        (0x30000U)
41990 #define ENET_MMFR_TA_SHIFT                       (16U)
41991 /*! TA - Turn Around
41992  */
41993 #define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
41994 #define ENET_MMFR_RA_MASK                        (0x7C0000U)
41995 #define ENET_MMFR_RA_SHIFT                       (18U)
41996 /*! RA - Register Address
41997  */
41998 #define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
41999 #define ENET_MMFR_PA_MASK                        (0xF800000U)
42000 #define ENET_MMFR_PA_SHIFT                       (23U)
42001 /*! PA - PHY Address
42002  */
42003 #define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
42004 #define ENET_MMFR_OP_MASK                        (0x30000000U)
42005 #define ENET_MMFR_OP_SHIFT                       (28U)
42006 /*! OP - Operation Code
42007  */
42008 #define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
42009 #define ENET_MMFR_ST_MASK                        (0xC0000000U)
42010 #define ENET_MMFR_ST_SHIFT                       (30U)
42011 /*! ST - Start Of Frame Delimiter
42012  */
42013 #define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
42014 /*! @} */
42015 
42016 /*! @name MSCR - MII Speed Control Register */
42017 /*! @{ */
42018 #define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
42019 #define ENET_MSCR_MII_SPEED_SHIFT                (1U)
42020 /*! MII_SPEED - MII Speed
42021  */
42022 #define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
42023 #define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
42024 #define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
42025 /*! DIS_PRE - Disable Preamble
42026  *  0b0..Preamble enabled.
42027  *  0b1..Preamble (32 ones) is not prepended to the MII management frame.
42028  */
42029 #define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
42030 #define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
42031 #define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
42032 /*! HOLDTIME - Hold time On MDIO Output
42033  *  0b000..1 internal module clock cycle
42034  *  0b001..2 internal module clock cycles
42035  *  0b010..3 internal module clock cycles
42036  *  0b111..8 internal module clock cycles
42037  */
42038 #define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
42039 /*! @} */
42040 
42041 /*! @name MIBC - MIB Control Register */
42042 /*! @{ */
42043 #define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
42044 #define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
42045 /*! MIB_CLEAR - MIB Clear
42046  *  0b0..See note above.
42047  *  0b1..All statistics counters are reset to 0.
42048  */
42049 #define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
42050 #define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
42051 #define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
42052 /*! MIB_IDLE - MIB Idle
42053  *  0b0..The MIB block is updating MIB counters.
42054  *  0b1..The MIB block is not currently updating any MIB counters.
42055  */
42056 #define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
42057 #define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
42058 #define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
42059 /*! MIB_DIS - Disable MIB Logic
42060  *  0b0..MIB logic is enabled.
42061  *  0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
42062  */
42063 #define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
42064 /*! @} */
42065 
42066 /*! @name RCR - Receive Control Register */
42067 /*! @{ */
42068 #define ENET_RCR_LOOP_MASK                       (0x1U)
42069 #define ENET_RCR_LOOP_SHIFT                      (0U)
42070 /*! LOOP - Internal Loopback
42071  *  0b0..Loopback disabled.
42072  *  0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
42073  */
42074 #define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
42075 #define ENET_RCR_DRT_MASK                        (0x2U)
42076 #define ENET_RCR_DRT_SHIFT                       (1U)
42077 /*! DRT - Disable Receive On Transmit
42078  *  0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
42079  *  0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
42080  */
42081 #define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
42082 #define ENET_RCR_MII_MODE_MASK                   (0x4U)
42083 #define ENET_RCR_MII_MODE_SHIFT                  (2U)
42084 /*! MII_MODE - Media Independent Interface Mode
42085  *  0b0..Reserved.
42086  *  0b1..MII or RMII mode, as indicated by the RMII_MODE field.
42087  */
42088 #define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
42089 #define ENET_RCR_PROM_MASK                       (0x8U)
42090 #define ENET_RCR_PROM_SHIFT                      (3U)
42091 /*! PROM - Promiscuous Mode
42092  *  0b0..Disabled.
42093  *  0b1..Enabled.
42094  */
42095 #define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
42096 #define ENET_RCR_BC_REJ_MASK                     (0x10U)
42097 #define ENET_RCR_BC_REJ_SHIFT                    (4U)
42098 /*! BC_REJ - Broadcast Frame Reject
42099  */
42100 #define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
42101 #define ENET_RCR_FCE_MASK                        (0x20U)
42102 #define ENET_RCR_FCE_SHIFT                       (5U)
42103 /*! FCE - Flow Control Enable
42104  */
42105 #define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
42106 #define ENET_RCR_RGMII_EN_MASK                   (0x40U)
42107 #define ENET_RCR_RGMII_EN_SHIFT                  (6U)
42108 /*! RGMII_EN - RGMII Mode Enable
42109  *  0b0..MAC configured for non-RGMII operation
42110  *  0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
42111  *       ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
42112  */
42113 #define ENET_RCR_RGMII_EN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
42114 #define ENET_RCR_RMII_MODE_MASK                  (0x100U)
42115 #define ENET_RCR_RMII_MODE_SHIFT                 (8U)
42116 /*! RMII_MODE - RMII Mode Enable
42117  *  0b0..MAC configured for MII mode.
42118  *  0b1..MAC configured for RMII operation.
42119  */
42120 #define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
42121 #define ENET_RCR_RMII_10T_MASK                   (0x200U)
42122 #define ENET_RCR_RMII_10T_SHIFT                  (9U)
42123 /*! RMII_10T
42124  *  0b0..100-Mbit/s operation.
42125  *  0b1..10-Mbit/s operation.
42126  */
42127 #define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
42128 #define ENET_RCR_PADEN_MASK                      (0x1000U)
42129 #define ENET_RCR_PADEN_SHIFT                     (12U)
42130 /*! PADEN - Enable Frame Padding Remove On Receive
42131  *  0b0..No padding is removed on receive by the MAC.
42132  *  0b1..Padding is removed from received frames.
42133  */
42134 #define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
42135 #define ENET_RCR_PAUFWD_MASK                     (0x2000U)
42136 #define ENET_RCR_PAUFWD_SHIFT                    (13U)
42137 /*! PAUFWD - Terminate/Forward Pause Frames
42138  *  0b0..Pause frames are terminated and discarded in the MAC.
42139  *  0b1..Pause frames are forwarded to the user application.
42140  */
42141 #define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
42142 #define ENET_RCR_CRCFWD_MASK                     (0x4000U)
42143 #define ENET_RCR_CRCFWD_SHIFT                    (14U)
42144 /*! CRCFWD - Terminate/Forward Received CRC
42145  *  0b0..The CRC field of received frames is transmitted to the user application.
42146  *  0b1..The CRC field is stripped from the frame.
42147  */
42148 #define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
42149 #define ENET_RCR_CFEN_MASK                       (0x8000U)
42150 #define ENET_RCR_CFEN_SHIFT                      (15U)
42151 /*! CFEN - MAC Control Frame Enable
42152  *  0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
42153  *  0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
42154  */
42155 #define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
42156 #define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
42157 #define ENET_RCR_MAX_FL_SHIFT                    (16U)
42158 /*! MAX_FL - Maximum Frame Length
42159  */
42160 #define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
42161 #define ENET_RCR_NLC_MASK                        (0x40000000U)
42162 #define ENET_RCR_NLC_SHIFT                       (30U)
42163 /*! NLC - Payload Length Check Disable
42164  *  0b0..The payload length check is disabled.
42165  *  0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
42166  */
42167 #define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
42168 #define ENET_RCR_GRS_MASK                        (0x80000000U)
42169 #define ENET_RCR_GRS_SHIFT                       (31U)
42170 /*! GRS - Graceful Receive Stopped
42171  */
42172 #define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
42173 /*! @} */
42174 
42175 /*! @name TCR - Transmit Control Register */
42176 /*! @{ */
42177 #define ENET_TCR_GTS_MASK                        (0x1U)
42178 #define ENET_TCR_GTS_SHIFT                       (0U)
42179 /*! GTS - Graceful Transmit Stop
42180  */
42181 #define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
42182 #define ENET_TCR_FDEN_MASK                       (0x4U)
42183 #define ENET_TCR_FDEN_SHIFT                      (2U)
42184 /*! FDEN - Full-Duplex Enable
42185  */
42186 #define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
42187 #define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
42188 #define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
42189 /*! TFC_PAUSE - Transmit Frame Control Pause
42190  *  0b0..No PAUSE frame transmitted.
42191  *  0b1..The MAC stops transmission of data frames after the current transmission is complete.
42192  */
42193 #define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
42194 #define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
42195 #define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
42196 /*! RFC_PAUSE - Receive Frame Control Pause
42197  */
42198 #define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
42199 #define ENET_TCR_ADDSEL_MASK                     (0xE0U)
42200 #define ENET_TCR_ADDSEL_SHIFT                    (5U)
42201 /*! ADDSEL - Source MAC Address Select On Transmit
42202  *  0b000..Node MAC address programmed on PADDR1/2 registers.
42203  *  0b100..Reserved.
42204  *  0b101..Reserved.
42205  *  0b110..Reserved.
42206  */
42207 #define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
42208 #define ENET_TCR_ADDINS_MASK                     (0x100U)
42209 #define ENET_TCR_ADDINS_SHIFT                    (8U)
42210 /*! ADDINS - Set MAC Address On Transmit
42211  *  0b0..The source MAC address is not modified by the MAC.
42212  *  0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
42213  */
42214 #define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
42215 #define ENET_TCR_CRCFWD_MASK                     (0x200U)
42216 #define ENET_TCR_CRCFWD_SHIFT                    (9U)
42217 /*! CRCFWD - Forward Frame From Application With CRC
42218  *  0b0..TxBD[TC] controls whether the frame has a CRC from the application.
42219  *  0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
42220  */
42221 #define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
42222 /*! @} */
42223 
42224 /*! @name PALR - Physical Address Lower Register */
42225 /*! @{ */
42226 #define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
42227 #define ENET_PALR_PADDR1_SHIFT                   (0U)
42228 /*! PADDR1 - Pause Address
42229  */
42230 #define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
42231 /*! @} */
42232 
42233 /*! @name PAUR - Physical Address Upper Register */
42234 /*! @{ */
42235 #define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
42236 #define ENET_PAUR_TYPE_SHIFT                     (0U)
42237 /*! TYPE - Type Field In PAUSE Frames
42238  */
42239 #define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
42240 #define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
42241 #define ENET_PAUR_PADDR2_SHIFT                   (16U)
42242 #define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
42243 /*! @} */
42244 
42245 /*! @name OPD - Opcode/Pause Duration Register */
42246 /*! @{ */
42247 #define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
42248 #define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
42249 /*! PAUSE_DUR - Pause Duration
42250  */
42251 #define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
42252 #define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
42253 #define ENET_OPD_OPCODE_SHIFT                    (16U)
42254 /*! OPCODE - Opcode Field In PAUSE Frames
42255  */
42256 #define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
42257 /*! @} */
42258 
42259 /*! @name TXIC - Transmit Interrupt Coalescing Register */
42260 /*! @{ */
42261 #define ENET_TXIC_ICTT_MASK                      (0xFFFFU)
42262 #define ENET_TXIC_ICTT_SHIFT                     (0U)
42263 /*! ICTT - Interrupt coalescing timer threshold
42264  */
42265 #define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
42266 #define ENET_TXIC_ICFT_MASK                      (0xFF00000U)
42267 #define ENET_TXIC_ICFT_SHIFT                     (20U)
42268 /*! ICFT - Interrupt coalescing frame count threshold
42269  */
42270 #define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
42271 #define ENET_TXIC_ICCS_MASK                      (0x40000000U)
42272 #define ENET_TXIC_ICCS_SHIFT                     (30U)
42273 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
42274  *  0b0..Use MII/GMII TX clocks.
42275  *  0b1..Use ENET system clock.
42276  */
42277 #define ENET_TXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
42278 #define ENET_TXIC_ICEN_MASK                      (0x80000000U)
42279 #define ENET_TXIC_ICEN_SHIFT                     (31U)
42280 /*! ICEN - Interrupt Coalescing Enable
42281  *  0b0..Disable Interrupt coalescing.
42282  *  0b1..Enable Interrupt coalescing.
42283  */
42284 #define ENET_TXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
42285 /*! @} */
42286 
42287 /* The count of ENET_TXIC */
42288 #define ENET_TXIC_COUNT                          (3U)
42289 
42290 /*! @name RXIC - Receive Interrupt Coalescing Register */
42291 /*! @{ */
42292 #define ENET_RXIC_ICTT_MASK                      (0xFFFFU)
42293 #define ENET_RXIC_ICTT_SHIFT                     (0U)
42294 /*! ICTT - Interrupt coalescing timer threshold
42295  */
42296 #define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
42297 #define ENET_RXIC_ICFT_MASK                      (0xFF00000U)
42298 #define ENET_RXIC_ICFT_SHIFT                     (20U)
42299 /*! ICFT - Interrupt coalescing frame count threshold
42300  */
42301 #define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
42302 #define ENET_RXIC_ICCS_MASK                      (0x40000000U)
42303 #define ENET_RXIC_ICCS_SHIFT                     (30U)
42304 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
42305  *  0b0..Use MII/GMII TX clocks.
42306  *  0b1..Use ENET system clock.
42307  */
42308 #define ENET_RXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
42309 #define ENET_RXIC_ICEN_MASK                      (0x80000000U)
42310 #define ENET_RXIC_ICEN_SHIFT                     (31U)
42311 /*! ICEN - Interrupt Coalescing Enable
42312  *  0b0..Disable Interrupt coalescing.
42313  *  0b1..Enable Interrupt coalescing.
42314  */
42315 #define ENET_RXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
42316 /*! @} */
42317 
42318 /* The count of ENET_RXIC */
42319 #define ENET_RXIC_COUNT                          (3U)
42320 
42321 /*! @name IAUR - Descriptor Individual Upper Address Register */
42322 /*! @{ */
42323 #define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
42324 #define ENET_IAUR_IADDR1_SHIFT                   (0U)
42325 #define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
42326 /*! @} */
42327 
42328 /*! @name IALR - Descriptor Individual Lower Address Register */
42329 /*! @{ */
42330 #define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
42331 #define ENET_IALR_IADDR2_SHIFT                   (0U)
42332 #define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
42333 /*! @} */
42334 
42335 /*! @name GAUR - Descriptor Group Upper Address Register */
42336 /*! @{ */
42337 #define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
42338 #define ENET_GAUR_GADDR1_SHIFT                   (0U)
42339 #define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
42340 /*! @} */
42341 
42342 /*! @name GALR - Descriptor Group Lower Address Register */
42343 /*! @{ */
42344 #define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
42345 #define ENET_GALR_GADDR2_SHIFT                   (0U)
42346 #define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
42347 /*! @} */
42348 
42349 /*! @name TFWR - Transmit FIFO Watermark Register */
42350 /*! @{ */
42351 #define ENET_TFWR_TFWR_MASK                      (0x3FU)
42352 #define ENET_TFWR_TFWR_SHIFT                     (0U)
42353 /*! TFWR - Transmit FIFO Write
42354  *  0b000000..64 bytes written.
42355  *  0b000001..64 bytes written.
42356  *  0b000010..128 bytes written.
42357  *  0b000011..192 bytes written.
42358  *  0b111111..4032 bytes written.
42359  */
42360 #define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
42361 #define ENET_TFWR_STRFWD_MASK                    (0x100U)
42362 #define ENET_TFWR_STRFWD_SHIFT                   (8U)
42363 /*! STRFWD - Store And Forward Enable
42364  *  0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
42365  *  0b1..Enabled.
42366  */
42367 #define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
42368 /*! @} */
42369 
42370 /*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
42371 /*! @{ */
42372 #define ENET_RDSR1_R_DES_START_MASK              (0xFFFFFFF8U)
42373 #define ENET_RDSR1_R_DES_START_SHIFT             (3U)
42374 #define ENET_RDSR1_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
42375 /*! @} */
42376 
42377 /*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
42378 /*! @{ */
42379 #define ENET_TDSR1_X_DES_START_MASK              (0xFFFFFFF8U)
42380 #define ENET_TDSR1_X_DES_START_SHIFT             (3U)
42381 #define ENET_TDSR1_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
42382 /*! @} */
42383 
42384 /*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
42385 /*! @{ */
42386 #define ENET_MRBR1_R_BUF_SIZE_MASK               (0x3FF0U)
42387 #define ENET_MRBR1_R_BUF_SIZE_SHIFT              (4U)
42388 #define ENET_MRBR1_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
42389 /*! @} */
42390 
42391 /*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
42392 /*! @{ */
42393 #define ENET_RDSR2_R_DES_START_MASK              (0xFFFFFFF8U)
42394 #define ENET_RDSR2_R_DES_START_SHIFT             (3U)
42395 #define ENET_RDSR2_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
42396 /*! @} */
42397 
42398 /*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
42399 /*! @{ */
42400 #define ENET_TDSR2_X_DES_START_MASK              (0xFFFFFFF8U)
42401 #define ENET_TDSR2_X_DES_START_SHIFT             (3U)
42402 #define ENET_TDSR2_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
42403 /*! @} */
42404 
42405 /*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
42406 /*! @{ */
42407 #define ENET_MRBR2_R_BUF_SIZE_MASK               (0x3FF0U)
42408 #define ENET_MRBR2_R_BUF_SIZE_SHIFT              (4U)
42409 #define ENET_MRBR2_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
42410 /*! @} */
42411 
42412 /*! @name RDSR - Receive Descriptor Ring 0 Start Register */
42413 /*! @{ */
42414 #define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
42415 #define ENET_RDSR_R_DES_START_SHIFT              (3U)
42416 #define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
42417 /*! @} */
42418 
42419 /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
42420 /*! @{ */
42421 #define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
42422 #define ENET_TDSR_X_DES_START_SHIFT              (3U)
42423 #define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
42424 /*! @} */
42425 
42426 /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
42427 /*! @{ */
42428 #define ENET_MRBR_R_BUF_SIZE_MASK                (0x3FF0U)
42429 #define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
42430 #define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
42431 /*! @} */
42432 
42433 /*! @name RSFL - Receive FIFO Section Full Threshold */
42434 /*! @{ */
42435 #define ENET_RSFL_RX_SECTION_FULL_MASK           (0x3FFU)
42436 #define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
42437 /*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold
42438  */
42439 #define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
42440 /*! @} */
42441 
42442 /*! @name RSEM - Receive FIFO Section Empty Threshold */
42443 /*! @{ */
42444 #define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0x3FFU)
42445 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
42446 /*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold
42447  */
42448 #define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
42449 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
42450 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
42451 /*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold
42452  */
42453 #define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
42454 /*! @} */
42455 
42456 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
42457 /*! @{ */
42458 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0x3FFU)
42459 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
42460 /*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold
42461  */
42462 #define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
42463 /*! @} */
42464 
42465 /*! @name RAFL - Receive FIFO Almost Full Threshold */
42466 /*! @{ */
42467 #define ENET_RAFL_RX_ALMOST_FULL_MASK            (0x3FFU)
42468 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
42469 /*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold
42470  */
42471 #define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
42472 /*! @} */
42473 
42474 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
42475 /*! @{ */
42476 #define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0x3FFU)
42477 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
42478 /*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold
42479  */
42480 #define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
42481 /*! @} */
42482 
42483 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
42484 /*! @{ */
42485 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0x3FFU)
42486 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
42487 /*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold
42488  */
42489 #define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
42490 /*! @} */
42491 
42492 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
42493 /*! @{ */
42494 #define ENET_TAFL_TX_ALMOST_FULL_MASK            (0x3FFU)
42495 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
42496 /*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold
42497  */
42498 #define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
42499 /*! @} */
42500 
42501 /*! @name TIPG - Transmit Inter-Packet Gap */
42502 /*! @{ */
42503 #define ENET_TIPG_IPG_MASK                       (0x1FU)
42504 #define ENET_TIPG_IPG_SHIFT                      (0U)
42505 /*! IPG - Transmit Inter-Packet Gap
42506  */
42507 #define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
42508 /*! @} */
42509 
42510 /*! @name FTRL - Frame Truncation Length */
42511 /*! @{ */
42512 #define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
42513 #define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
42514 /*! TRUNC_FL - Frame Truncation Length
42515  */
42516 #define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
42517 /*! @} */
42518 
42519 /*! @name TACC - Transmit Accelerator Function Configuration */
42520 /*! @{ */
42521 #define ENET_TACC_SHIFT16_MASK                   (0x1U)
42522 #define ENET_TACC_SHIFT16_SHIFT                  (0U)
42523 /*! SHIFT16 - TX FIFO Shift-16
42524  *  0b0..Disabled.
42525  *  0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
42526  *       frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
42527  *       function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
42528  *       extended to a 16-byte header.
42529  */
42530 #define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
42531 #define ENET_TACC_IPCHK_MASK                     (0x8U)
42532 #define ENET_TACC_IPCHK_SHIFT                    (3U)
42533 /*! IPCHK
42534  *  0b0..Checksum is not inserted.
42535  *  0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
42536  *       be cleared. If a non-IP frame is transmitted the frame is not modified.
42537  */
42538 #define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
42539 #define ENET_TACC_PROCHK_MASK                    (0x10U)
42540 #define ENET_TACC_PROCHK_SHIFT                   (4U)
42541 /*! PROCHK
42542  *  0b0..Checksum not inserted.
42543  *  0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
42544  *       frame. The checksum field must be cleared. The other frames are not modified.
42545  */
42546 #define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
42547 /*! @} */
42548 
42549 /*! @name RACC - Receive Accelerator Function Configuration */
42550 /*! @{ */
42551 #define ENET_RACC_PADREM_MASK                    (0x1U)
42552 #define ENET_RACC_PADREM_SHIFT                   (0U)
42553 /*! PADREM - Enable Padding Removal For Short IP Frames
42554  *  0b0..Padding not removed.
42555  *  0b1..Any bytes following the IP payload section of the frame are removed from the frame.
42556  */
42557 #define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
42558 #define ENET_RACC_IPDIS_MASK                     (0x2U)
42559 #define ENET_RACC_IPDIS_SHIFT                    (1U)
42560 /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
42561  *  0b0..Frames with wrong IPv4 header checksum are not discarded.
42562  *  0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
42563  *       header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
42564  *       store and forward mode (RSFL cleared).
42565  */
42566 #define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
42567 #define ENET_RACC_PRODIS_MASK                    (0x4U)
42568 #define ENET_RACC_PRODIS_SHIFT                   (2U)
42569 /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
42570  *  0b0..Frames with wrong checksum are not discarded.
42571  *  0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
42572  *       is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
42573  *       cleared).
42574  */
42575 #define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
42576 #define ENET_RACC_LINEDIS_MASK                   (0x40U)
42577 #define ENET_RACC_LINEDIS_SHIFT                  (6U)
42578 /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
42579  *  0b0..Frames with errors are not discarded.
42580  *  0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
42581  */
42582 #define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
42583 #define ENET_RACC_SHIFT16_MASK                   (0x80U)
42584 #define ENET_RACC_SHIFT16_SHIFT                  (7U)
42585 /*! SHIFT16 - RX FIFO Shift-16
42586  *  0b0..Disabled.
42587  *  0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
42588  */
42589 #define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
42590 /*! @} */
42591 
42592 /*! @name RCMR - Receive Classification Match Register for Class n */
42593 /*! @{ */
42594 #define ENET_RCMR_CMP0_MASK                      (0x7U)
42595 #define ENET_RCMR_CMP0_SHIFT                     (0U)
42596 /*! CMP0 - Compare 0
42597  */
42598 #define ENET_RCMR_CMP0(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
42599 #define ENET_RCMR_CMP1_MASK                      (0x70U)
42600 #define ENET_RCMR_CMP1_SHIFT                     (4U)
42601 /*! CMP1 - Compare 1
42602  */
42603 #define ENET_RCMR_CMP1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
42604 #define ENET_RCMR_CMP2_MASK                      (0x700U)
42605 #define ENET_RCMR_CMP2_SHIFT                     (8U)
42606 /*! CMP2 - Compare 2
42607  */
42608 #define ENET_RCMR_CMP2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
42609 #define ENET_RCMR_CMP3_MASK                      (0x7000U)
42610 #define ENET_RCMR_CMP3_SHIFT                     (12U)
42611 /*! CMP3 - Compare 3
42612  */
42613 #define ENET_RCMR_CMP3(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
42614 #define ENET_RCMR_MATCHEN_MASK                   (0x10000U)
42615 #define ENET_RCMR_MATCHEN_SHIFT                  (16U)
42616 /*! MATCHEN - Match Enable
42617  *  0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
42618  *  0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
42619  */
42620 #define ENET_RCMR_MATCHEN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
42621 /*! @} */
42622 
42623 /* The count of ENET_RCMR */
42624 #define ENET_RCMR_COUNT                          (2U)
42625 
42626 /*! @name DMACFG - DMA Class Based Configuration */
42627 /*! @{ */
42628 #define ENET_DMACFG_IDLE_SLOPE_MASK              (0xFFFFU)
42629 #define ENET_DMACFG_IDLE_SLOPE_SHIFT             (0U)
42630 /*! IDLE_SLOPE - Idle slope
42631  */
42632 #define ENET_DMACFG_IDLE_SLOPE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
42633 #define ENET_DMACFG_DMA_CLASS_EN_MASK            (0x10000U)
42634 #define ENET_DMACFG_DMA_CLASS_EN_SHIFT           (16U)
42635 /*! DMA_CLASS_EN - DMA class enable
42636  *  0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
42637  *       requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
42638  *       queues are disabled then their frames will be placed in queue 0.
42639  *  0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
42640  */
42641 #define ENET_DMACFG_DMA_CLASS_EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
42642 #define ENET_DMACFG_CALC_NOIPG_MASK              (0x20000U)
42643 #define ENET_DMACFG_CALC_NOIPG_SHIFT             (17U)
42644 /*! CALC_NOIPG - Calculate no IPG
42645  *  0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
42646  *       for a frame when doing bandwidth calculations. This is the default.
42647  *  0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
42648  *       when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
42649  *       frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
42650  *       will become more bandwidth than large frames due to the relation of data to IPG overhead).
42651  */
42652 #define ENET_DMACFG_CALC_NOIPG(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
42653 /*! @} */
42654 
42655 /* The count of ENET_DMACFG */
42656 #define ENET_DMACFG_COUNT                        (2U)
42657 
42658 /*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
42659 /*! @{ */
42660 #define ENET_RDAR1_RDAR_MASK                     (0x1000000U)
42661 #define ENET_RDAR1_RDAR_SHIFT                    (24U)
42662 /*! RDAR - Receive Descriptor Active
42663  */
42664 #define ENET_RDAR1_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
42665 /*! @} */
42666 
42667 /*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
42668 /*! @{ */
42669 #define ENET_TDAR1_TDAR_MASK                     (0x1000000U)
42670 #define ENET_TDAR1_TDAR_SHIFT                    (24U)
42671 /*! TDAR - Transmit Descriptor Active
42672  */
42673 #define ENET_TDAR1_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
42674 /*! @} */
42675 
42676 /*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
42677 /*! @{ */
42678 #define ENET_RDAR2_RDAR_MASK                     (0x1000000U)
42679 #define ENET_RDAR2_RDAR_SHIFT                    (24U)
42680 /*! RDAR - Receive Descriptor Active
42681  */
42682 #define ENET_RDAR2_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
42683 /*! @} */
42684 
42685 /*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
42686 /*! @{ */
42687 #define ENET_TDAR2_TDAR_MASK                     (0x1000000U)
42688 #define ENET_TDAR2_TDAR_SHIFT                    (24U)
42689 /*! TDAR - Transmit Descriptor Active
42690  */
42691 #define ENET_TDAR2_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
42692 /*! @} */
42693 
42694 /*! @name QOS - QOS Scheme */
42695 /*! @{ */
42696 #define ENET_QOS_TX_SCHEME_MASK                  (0x7U)
42697 #define ENET_QOS_TX_SCHEME_SHIFT                 (0U)
42698 /*! TX_SCHEME - TX scheme configuration
42699  *  0b000..Credit-based scheme
42700  *  0b001..Round-robin scheme
42701  *  0b010-0b111..Reserved
42702  */
42703 #define ENET_QOS_TX_SCHEME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
42704 #define ENET_QOS_RX_FLUSH0_MASK                  (0x8U)
42705 #define ENET_QOS_RX_FLUSH0_SHIFT                 (3U)
42706 /*! RX_FLUSH0 - RX Flush Ring 0
42707  *  0b0..Disable
42708  *  0b1..Enable
42709  */
42710 #define ENET_QOS_RX_FLUSH0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
42711 #define ENET_QOS_RX_FLUSH1_MASK                  (0x10U)
42712 #define ENET_QOS_RX_FLUSH1_SHIFT                 (4U)
42713 /*! RX_FLUSH1 - RX Flush Ring 1
42714  *  0b0..Disable
42715  *  0b1..Enable
42716  */
42717 #define ENET_QOS_RX_FLUSH1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
42718 #define ENET_QOS_RX_FLUSH2_MASK                  (0x20U)
42719 #define ENET_QOS_RX_FLUSH2_SHIFT                 (5U)
42720 /*! RX_FLUSH2 - RX Flush Ring 2
42721  *  0b0..Disable
42722  *  0b1..Enable
42723  */
42724 #define ENET_QOS_RX_FLUSH2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
42725 /*! @} */
42726 
42727 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
42728 /*! @{ */
42729 #define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
42730 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
42731 /*! TXPKTS - Packet count
42732  */
42733 #define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
42734 /*! @} */
42735 
42736 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
42737 /*! @{ */
42738 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
42739 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
42740 /*! TXPKTS - Broadcast packets
42741  */
42742 #define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
42743 /*! @} */
42744 
42745 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
42746 /*! @{ */
42747 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
42748 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
42749 /*! TXPKTS - Multicast packets
42750  */
42751 #define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
42752 /*! @} */
42753 
42754 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
42755 /*! @{ */
42756 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
42757 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
42758 /*! TXPKTS - Packets with CRC/align error
42759  */
42760 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
42761 /*! @} */
42762 
42763 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
42764 /*! @{ */
42765 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
42766 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
42767 /*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC
42768  */
42769 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
42770 /*! @} */
42771 
42772 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
42773 /*! @{ */
42774 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
42775 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
42776 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC
42777  */
42778 #define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
42779 /*! @} */
42780 
42781 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
42782 /*! @{ */
42783 #define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
42784 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
42785 /*! TXPKTS - Number of packets less than 64 bytes with bad CRC
42786  */
42787 #define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
42788 /*! @} */
42789 
42790 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
42791 /*! @{ */
42792 #define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
42793 #define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
42794 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC
42795  */
42796 #define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
42797 /*! @} */
42798 
42799 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
42800 /*! @{ */
42801 #define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
42802 #define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
42803 /*! TXPKTS - Number of transmit collisions
42804  */
42805 #define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
42806 /*! @} */
42807 
42808 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
42809 /*! @{ */
42810 #define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
42811 #define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
42812 /*! TXPKTS - Number of 64-byte transmit packets
42813  */
42814 #define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
42815 /*! @} */
42816 
42817 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
42818 /*! @{ */
42819 #define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
42820 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
42821 /*! TXPKTS - Number of 65- to 127-byte transmit packets
42822  */
42823 #define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
42824 /*! @} */
42825 
42826 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
42827 /*! @{ */
42828 #define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
42829 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
42830 /*! TXPKTS - Number of 128- to 255-byte transmit packets
42831  */
42832 #define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
42833 /*! @} */
42834 
42835 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
42836 /*! @{ */
42837 #define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
42838 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
42839 /*! TXPKTS - Number of 256- to 511-byte transmit packets
42840  */
42841 #define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
42842 /*! @} */
42843 
42844 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
42845 /*! @{ */
42846 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
42847 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
42848 /*! TXPKTS - Number of 512- to 1023-byte transmit packets
42849  */
42850 #define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
42851 /*! @} */
42852 
42853 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
42854 /*! @{ */
42855 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
42856 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
42857 /*! TXPKTS - Number of 1024- to 2047-byte transmit packets
42858  */
42859 #define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
42860 /*! @} */
42861 
42862 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
42863 /*! @{ */
42864 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
42865 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
42866 /*! TXPKTS - Number of transmit packets greater than 2048 bytes
42867  */
42868 #define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
42869 /*! @} */
42870 
42871 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
42872 /*! @{ */
42873 #define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
42874 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
42875 /*! TXOCTS - Number of transmit octets
42876  */
42877 #define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
42878 /*! @} */
42879 
42880 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
42881 /*! @{ */
42882 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
42883 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
42884 /*! COUNT - Number of frames transmitted OK
42885  */
42886 #define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
42887 /*! @} */
42888 
42889 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
42890 /*! @{ */
42891 #define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
42892 #define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
42893 /*! COUNT - Number of frames transmitted with one collision
42894  */
42895 #define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
42896 /*! @} */
42897 
42898 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
42899 /*! @{ */
42900 #define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
42901 #define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
42902 /*! COUNT - Number of frames transmitted with multiple collisions
42903  */
42904 #define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
42905 /*! @} */
42906 
42907 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
42908 /*! @{ */
42909 #define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
42910 #define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
42911 /*! COUNT - Number of frames transmitted with deferral delay
42912  */
42913 #define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
42914 /*! @} */
42915 
42916 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
42917 /*! @{ */
42918 #define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
42919 #define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
42920 /*! COUNT - Number of frames transmitted with late collision
42921  */
42922 #define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
42923 /*! @} */
42924 
42925 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
42926 /*! @{ */
42927 #define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
42928 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
42929 /*! COUNT - Number of frames transmitted with excessive collisions
42930  */
42931 #define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
42932 /*! @} */
42933 
42934 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
42935 /*! @{ */
42936 #define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
42937 #define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
42938 /*! COUNT - Number of frames transmitted with transmit FIFO underrun
42939  */
42940 #define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
42941 /*! @} */
42942 
42943 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
42944 /*! @{ */
42945 #define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
42946 #define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
42947 /*! COUNT - Number of frames transmitted with carrier sense error
42948  */
42949 #define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
42950 /*! @} */
42951 
42952 /*! @name IEEE_T_SQE - Reserved Statistic Register */
42953 /*! @{ */
42954 #define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
42955 #define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
42956 /*! COUNT - This read-only field is reserved and always has the value 0
42957  */
42958 #define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
42959 /*! @} */
42960 
42961 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
42962 /*! @{ */
42963 #define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
42964 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
42965 /*! COUNT - Number of flow-control pause frames transmitted
42966  */
42967 #define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
42968 /*! @} */
42969 
42970 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
42971 /*! @{ */
42972 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
42973 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
42974 /*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).
42975  */
42976 #define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
42977 /*! @} */
42978 
42979 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
42980 /*! @{ */
42981 #define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
42982 #define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
42983 /*! COUNT - Number of packets received
42984  */
42985 #define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
42986 /*! @} */
42987 
42988 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
42989 /*! @{ */
42990 #define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
42991 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
42992 /*! COUNT - Number of receive broadcast packets
42993  */
42994 #define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
42995 /*! @} */
42996 
42997 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
42998 /*! @{ */
42999 #define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
43000 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
43001 /*! COUNT - Number of receive multicast packets
43002  */
43003 #define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
43004 /*! @} */
43005 
43006 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
43007 /*! @{ */
43008 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
43009 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
43010 /*! COUNT - Number of receive packets with CRC or align error
43011  */
43012 #define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
43013 /*! @} */
43014 
43015 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
43016 /*! @{ */
43017 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
43018 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
43019 /*! COUNT - Number of receive packets with less than 64 bytes and good CRC
43020  */
43021 #define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
43022 /*! @} */
43023 
43024 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
43025 /*! @{ */
43026 #define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
43027 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
43028 /*! COUNT - Number of receive packets greater than MAX_FL and good CRC
43029  */
43030 #define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
43031 /*! @} */
43032 
43033 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
43034 /*! @{ */
43035 #define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
43036 #define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
43037 /*! COUNT - Number of receive packets with less than 64 bytes and bad CRC
43038  */
43039 #define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
43040 /*! @} */
43041 
43042 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
43043 /*! @{ */
43044 #define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
43045 #define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
43046 /*! COUNT - Number of receive packets greater than MAX_FL and bad CRC
43047  */
43048 #define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
43049 /*! @} */
43050 
43051 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
43052 /*! @{ */
43053 #define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
43054 #define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
43055 /*! COUNT - Number of 64-byte receive packets
43056  */
43057 #define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
43058 /*! @} */
43059 
43060 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
43061 /*! @{ */
43062 #define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
43063 #define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
43064 /*! COUNT - Number of 65- to 127-byte recieve packets
43065  */
43066 #define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
43067 /*! @} */
43068 
43069 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
43070 /*! @{ */
43071 #define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
43072 #define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
43073 /*! COUNT - Number of 128- to 255-byte recieve packets
43074  */
43075 #define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
43076 /*! @} */
43077 
43078 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
43079 /*! @{ */
43080 #define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
43081 #define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
43082 /*! COUNT - Number of 256- to 511-byte recieve packets
43083  */
43084 #define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
43085 /*! @} */
43086 
43087 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
43088 /*! @{ */
43089 #define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
43090 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
43091 /*! COUNT - Number of 512- to 1023-byte recieve packets
43092  */
43093 #define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
43094 /*! @} */
43095 
43096 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
43097 /*! @{ */
43098 #define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
43099 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
43100 /*! COUNT - Number of 1024- to 2047-byte recieve packets
43101  */
43102 #define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
43103 /*! @} */
43104 
43105 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
43106 /*! @{ */
43107 #define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
43108 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
43109 /*! COUNT - Number of greater-than-2048-byte recieve packets
43110  */
43111 #define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
43112 /*! @} */
43113 
43114 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
43115 /*! @{ */
43116 #define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
43117 #define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
43118 /*! COUNT - Number of receive octets
43119  */
43120 #define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
43121 /*! @} */
43122 
43123 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
43124 /*! @{ */
43125 #define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
43126 #define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
43127 /*! COUNT - Frame count
43128  */
43129 #define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
43130 /*! @} */
43131 
43132 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
43133 /*! @{ */
43134 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
43135 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
43136 /*! COUNT - Number of frames received OK
43137  */
43138 #define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
43139 /*! @} */
43140 
43141 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
43142 /*! @{ */
43143 #define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
43144 #define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
43145 /*! COUNT - Number of frames received with CRC error
43146  */
43147 #define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
43148 /*! @} */
43149 
43150 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
43151 /*! @{ */
43152 #define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
43153 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
43154 /*! COUNT - Number of frames received with alignment error
43155  */
43156 #define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
43157 /*! @} */
43158 
43159 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
43160 /*! @{ */
43161 #define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
43162 #define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
43163 /*! COUNT - Receive FIFO overflow count
43164  */
43165 #define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
43166 /*! @} */
43167 
43168 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
43169 /*! @{ */
43170 #define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
43171 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
43172 /*! COUNT - Number of flow-control pause frames received
43173  */
43174 #define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
43175 /*! @} */
43176 
43177 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
43178 /*! @{ */
43179 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
43180 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
43181 /*! COUNT - Number of octets for frames received without error
43182  */
43183 #define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
43184 /*! @} */
43185 
43186 /*! @name ATCR - Adjustable Timer Control Register */
43187 /*! @{ */
43188 #define ENET_ATCR_EN_MASK                        (0x1U)
43189 #define ENET_ATCR_EN_SHIFT                       (0U)
43190 /*! EN - Enable Timer
43191  *  0b0..The timer stops at the current value.
43192  *  0b1..The timer starts incrementing.
43193  */
43194 #define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
43195 #define ENET_ATCR_OFFEN_MASK                     (0x4U)
43196 #define ENET_ATCR_OFFEN_SHIFT                    (2U)
43197 /*! OFFEN - Enable One-Shot Offset Event
43198  *  0b0..Disable.
43199  *  0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
43200  *       when the offset event is reached, so no further event occurs until the field is set again. The timer
43201  *       offset value must be set before setting this field.
43202  */
43203 #define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
43204 #define ENET_ATCR_OFFRST_MASK                    (0x8U)
43205 #define ENET_ATCR_OFFRST_SHIFT                   (3U)
43206 /*! OFFRST - Reset Timer On Offset Event
43207  *  0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
43208  *  0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
43209  */
43210 #define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
43211 #define ENET_ATCR_PEREN_MASK                     (0x10U)
43212 #define ENET_ATCR_PEREN_SHIFT                    (4U)
43213 /*! PEREN - Enable Periodical Event
43214  *  0b0..Disable.
43215  *  0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
43216  *       the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
43217  *       setting this bit. Not all devices contain the event signal output. See the chip configuration details.
43218  */
43219 #define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
43220 #define ENET_ATCR_PINPER_MASK                    (0x80U)
43221 #define ENET_ATCR_PINPER_SHIFT                   (7U)
43222 /*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event
43223  *  0b0..Disable.
43224  *  0b1..Enable.
43225  */
43226 #define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
43227 #define ENET_ATCR_RESTART_MASK                   (0x200U)
43228 #define ENET_ATCR_RESTART_SHIFT                  (9U)
43229 /*! RESTART - Reset Timer
43230  */
43231 #define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
43232 #define ENET_ATCR_CAPTURE_MASK                   (0x800U)
43233 #define ENET_ATCR_CAPTURE_SHIFT                  (11U)
43234 /*! CAPTURE - Capture Timer Value
43235  *  0b0..No effect.
43236  *  0b1..The current time is captured and can be read from the ATVR register.
43237  */
43238 #define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
43239 #define ENET_ATCR_SLAVE_MASK                     (0x2000U)
43240 #define ENET_ATCR_SLAVE_SHIFT                    (13U)
43241 /*! SLAVE - Enable Timer Slave Mode
43242  *  0b0..The timer is active and all configuration fields in this register are relevant.
43243  *  0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
43244  *       CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
43245  */
43246 #define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
43247 /*! @} */
43248 
43249 /*! @name ATVR - Timer Value Register */
43250 /*! @{ */
43251 #define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
43252 #define ENET_ATVR_ATIME_SHIFT                    (0U)
43253 #define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
43254 /*! @} */
43255 
43256 /*! @name ATOFF - Timer Offset Register */
43257 /*! @{ */
43258 #define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
43259 #define ENET_ATOFF_OFFSET_SHIFT                  (0U)
43260 #define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
43261 /*! @} */
43262 
43263 /*! @name ATPER - Timer Period Register */
43264 /*! @{ */
43265 #define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
43266 #define ENET_ATPER_PERIOD_SHIFT                  (0U)
43267 /*! PERIOD - Value for generating periodic events
43268  */
43269 #define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
43270 /*! @} */
43271 
43272 /*! @name ATCOR - Timer Correction Register */
43273 /*! @{ */
43274 #define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
43275 #define ENET_ATCOR_COR_SHIFT                     (0U)
43276 /*! COR - Correction Counter Wrap-Around Value
43277  */
43278 #define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
43279 /*! @} */
43280 
43281 /*! @name ATINC - Time-Stamping Clock Period Register */
43282 /*! @{ */
43283 #define ENET_ATINC_INC_MASK                      (0x7FU)
43284 #define ENET_ATINC_INC_SHIFT                     (0U)
43285 /*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
43286  */
43287 #define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
43288 #define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
43289 #define ENET_ATINC_INC_CORR_SHIFT                (8U)
43290 /*! INC_CORR - Correction Increment Value
43291  */
43292 #define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
43293 /*! @} */
43294 
43295 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
43296 /*! @{ */
43297 #define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
43298 #define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
43299 /*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the
43300  *    ff_tx_ts_frm signal asserted from the user application
43301  */
43302 #define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
43303 /*! @} */
43304 
43305 /*! @name MDATA - Pattern Match Data Register */
43306 /*! @{ */
43307 #define ENET_MDATA_MATCHDATA_MASK                (0xFFFFFFFFU)
43308 #define ENET_MDATA_MATCHDATA_SHIFT               (0U)
43309 /*! MATCHDATA - Match Data
43310  */
43311 #define ENET_MDATA_MATCHDATA(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MDATA_MATCHDATA_SHIFT)) & ENET_MDATA_MATCHDATA_MASK)
43312 /*! @} */
43313 
43314 /*! @name MMASK - Match Entry Mask Register */
43315 /*! @{ */
43316 #define ENET_MMASK_MATCHMASK_MASK                (0xFFFFFFFFU)
43317 #define ENET_MMASK_MATCHMASK_SHIFT               (0U)
43318 /*! MATCHMASK - Match Mask
43319  */
43320 #define ENET_MMASK_MATCHMASK(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MMASK_MATCHMASK_SHIFT)) & ENET_MMASK_MATCHMASK_MASK)
43321 /*! @} */
43322 
43323 /*! @name MCONFIG - Match Entry Rules Configuration Register */
43324 /*! @{ */
43325 #define ENET_MCONFIG_FRMOFF_MASK                 (0xFCU)
43326 #define ENET_MCONFIG_FRMOFF_SHIFT                (2U)
43327 /*! FRMOFF - Frame Offset
43328  */
43329 #define ENET_MCONFIG_FRMOFF(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_FRMOFF_SHIFT)) & ENET_MCONFIG_FRMOFF_MASK)
43330 #define ENET_MCONFIG_OK_INDEX_MASK               (0xFF0000U)
43331 #define ENET_MCONFIG_OK_INDEX_SHIFT              (16U)
43332 /*! OK_INDEX - When AF = 0 and RF = 0, this value shows the next entry of the matching table to be
43333  *    used for comparison instead of using the next entry sequentially
43334  */
43335 #define ENET_MCONFIG_OK_INDEX(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_OK_INDEX_SHIFT)) & ENET_MCONFIG_OK_INDEX_MASK)
43336 #define ENET_MCONFIG_IM_MASK                     (0x20000000U)
43337 #define ENET_MCONFIG_IM_SHIFT                    (29U)
43338 /*! IM - Invert Match
43339  */
43340 #define ENET_MCONFIG_IM(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_IM_SHIFT)) & ENET_MCONFIG_IM_MASK)
43341 #define ENET_MCONFIG_RF_MASK                     (0x40000000U)
43342 #define ENET_MCONFIG_RF_SHIFT                    (30U)
43343 /*! RF - Reject Frame
43344  */
43345 #define ENET_MCONFIG_RF(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_RF_SHIFT)) & ENET_MCONFIG_RF_MASK)
43346 #define ENET_MCONFIG_AF_MASK                     (0x80000000U)
43347 #define ENET_MCONFIG_AF_SHIFT                    (31U)
43348 /*! AF - Accept Frame
43349  */
43350 #define ENET_MCONFIG_AF(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_AF_SHIFT)) & ENET_MCONFIG_AF_MASK)
43351 /*! @} */
43352 
43353 /*! @name MENTRYRW - Match Entry Read/Write Command Register */
43354 /*! @{ */
43355 #define ENET_MENTRYRW_ENTRYADD_MASK              (0xFFU)
43356 #define ENET_MENTRYRW_ENTRYADD_SHIFT             (0U)
43357 /*! ENTRYADD - Entry Address
43358  */
43359 #define ENET_MENTRYRW_ENTRYADD(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MENTRYRW_ENTRYADD_SHIFT)) & ENET_MENTRYRW_ENTRYADD_MASK)
43360 #define ENET_MENTRYRW_WR_MASK                    (0x100U)
43361 #define ENET_MENTRYRW_WR_SHIFT                   (8U)
43362 /*! WR - Entry write command
43363  */
43364 #define ENET_MENTRYRW_WR(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_MENTRYRW_WR_SHIFT)) & ENET_MENTRYRW_WR_MASK)
43365 #define ENET_MENTRYRW_RD_MASK                    (0x200U)
43366 #define ENET_MENTRYRW_RD_SHIFT                   (9U)
43367 /*! RD - Entry Read Command
43368  */
43369 #define ENET_MENTRYRW_RD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_MENTRYRW_RD_SHIFT)) & ENET_MENTRYRW_RD_MASK)
43370 /*! @} */
43371 
43372 /*! @name RXPCTL - Receive Parser Control Register */
43373 /*! @{ */
43374 #define ENET_RXPCTL_ENPARSER_MASK                (0x1U)
43375 #define ENET_RXPCTL_ENPARSER_SHIFT               (0U)
43376 /*! ENPARSER - Enable Receive Parser
43377  *  0b0..Parser is disabled.
43378  *  0b1..Parser is enabled.
43379  */
43380 #define ENET_RXPCTL_ENPARSER(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_ENPARSER_SHIFT)) & ENET_RXPCTL_ENPARSER_MASK)
43381 #define ENET_RXPCTL_INVBYTORD_MASK               (0x2U)
43382 #define ENET_RXPCTL_INVBYTORD_SHIFT              (1U)
43383 /*! INVBYTORD - Inverse Frame Byte Order
43384  */
43385 #define ENET_RXPCTL_INVBYTORD(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_INVBYTORD_SHIFT)) & ENET_RXPCTL_INVBYTORD_MASK)
43386 #define ENET_RXPCTL_PRSRSCLR_MASK                (0x10U)
43387 #define ENET_RXPCTL_PRSRSCLR_SHIFT               (4U)
43388 /*! PRSRSCLR - Clear Parser Statistics Counter
43389  */
43390 #define ENET_RXPCTL_PRSRSCLR(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_PRSRSCLR_SHIFT)) & ENET_RXPCTL_PRSRSCLR_MASK)
43391 #define ENET_RXPCTL_MAXINDEX_MASK                (0xFF00U)
43392 #define ENET_RXPCTL_MAXINDEX_SHIFT               (8U)
43393 /*! MAXINDEX - Maximum Index
43394  */
43395 #define ENET_RXPCTL_MAXINDEX(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_MAXINDEX_SHIFT)) & ENET_RXPCTL_MAXINDEX_MASK)
43396 #define ENET_RXPCTL_ENDERRQ_MASK                 (0xFF0000U)
43397 #define ENET_RXPCTL_ENDERRQ_SHIFT                (16U)
43398 /*! ENDERRQ - End Error Queue
43399  *  0b00000001..Place the frame in Queue 0
43400  *  0b00000010..Place the frame in Queue 1
43401  *  0b00000100..Place the frame in Queue 2
43402  */
43403 #define ENET_RXPCTL_ENDERRQ(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_ENDERRQ_SHIFT)) & ENET_RXPCTL_ENDERRQ_MASK)
43404 #define ENET_RXPCTL_ACPTEERR_MASK                (0x1000000U)
43405 #define ENET_RXPCTL_ACPTEERR_SHIFT               (24U)
43406 /*! ACPTEERR - Accept End Error
43407  */
43408 #define ENET_RXPCTL_ACPTEERR(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_ACPTEERR_SHIFT)) & ENET_RXPCTL_ACPTEERR_MASK)
43409 /*! @} */
43410 
43411 /*! @name MAXFRMOFF - Maximum Frame Offset */
43412 /*! @{ */
43413 #define ENET_MAXFRMOFF_MXFRMOFF_MASK             (0x3FU)
43414 #define ENET_MAXFRMOFF_MXFRMOFF_SHIFT            (0U)
43415 /*! MXFRMOFF - Max. Frame Offset
43416  */
43417 #define ENET_MAXFRMOFF_MXFRMOFF(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAXFRMOFF_MXFRMOFF_SHIFT)) & ENET_MAXFRMOFF_MXFRMOFF_MASK)
43418 /*! @} */
43419 
43420 /*! @name RXPARST - Receive Parser Status */
43421 /*! @{ */
43422 #define ENET_RXPARST_MXINDERR_MASK               (0x1U)
43423 #define ENET_RXPARST_MXINDERR_SHIFT              (0U)
43424 /*! MXINDERR - Maximum Index Error
43425  */
43426 #define ENET_RXPARST_MXINDERR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_MXINDERR_SHIFT)) & ENET_RXPARST_MXINDERR_MASK)
43427 #define ENET_RXPARST_TBLDPTERR_MASK              (0x2U)
43428 #define ENET_RXPARST_TBLDPTERR_SHIFT             (1U)
43429 /*! TBLDPTERR - Table Depth Error
43430  */
43431 #define ENET_RXPARST_TBLDPTERR(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_TBLDPTERR_SHIFT)) & ENET_RXPARST_TBLDPTERR_MASK)
43432 #define ENET_RXPARST_NOMTCERR_MASK               (0x4U)
43433 #define ENET_RXPARST_NOMTCERR_SHIFT              (2U)
43434 /*! NOMTCERR - No Match Error
43435  */
43436 #define ENET_RXPARST_NOMTCERR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_NOMTCERR_SHIFT)) & ENET_RXPARST_NOMTCERR_MASK)
43437 #define ENET_RXPARST_FMOFFERR_MASK               (0x8U)
43438 #define ENET_RXPARST_FMOFFERR_SHIFT              (3U)
43439 /*! FMOFFERR - Maximum Frame Offset Error
43440  */
43441 #define ENET_RXPARST_FMOFFERR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_FMOFFERR_SHIFT)) & ENET_RXPARST_FMOFFERR_MASK)
43442 #define ENET_RXPARST_PRSENDERR_MASK              (0x10U)
43443 #define ENET_RXPARST_PRSENDERR_SHIFT             (4U)
43444 /*! PRSENDERR - Parser End Error
43445  */
43446 #define ENET_RXPARST_PRSENDERR(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_PRSENDERR_SHIFT)) & ENET_RXPARST_PRSENDERR_MASK)
43447 #define ENET_RXPARST_INVMAXIDX_MASK              (0x20U)
43448 #define ENET_RXPARST_INVMAXIDX_SHIFT             (5U)
43449 /*! INVMAXIDX - Invalid Value of MAXINDEX
43450  */
43451 #define ENET_RXPARST_INVMAXIDX(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_INVMAXIDX_SHIFT)) & ENET_RXPARST_INVMAXIDX_MASK)
43452 #define ENET_RXPARST_RXPRSDN_MASK                (0x100U)
43453 #define ENET_RXPARST_RXPRSDN_SHIFT               (8U)
43454 /*! RXPRSDN - Receive Parser Done
43455  */
43456 #define ENET_RXPARST_RXPRSDN(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_RXPRSDN_SHIFT)) & ENET_RXPARST_RXPRSDN_MASK)
43457 /*! @} */
43458 
43459 /*! @name PARSDSCD - Parser Discard Count */
43460 /*! @{ */
43461 #define ENET_PARSDSCD_COUNT_MASK                 (0xFFFFFFFFU)
43462 #define ENET_PARSDSCD_COUNT_SHIFT                (0U)
43463 /*! COUNT - Count
43464  */
43465 #define ENET_PARSDSCD_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_PARSDSCD_COUNT_SHIFT)) & ENET_PARSDSCD_COUNT_MASK)
43466 /*! @} */
43467 
43468 /*! @name PRSACPT0 - Parser Accept Count 0 */
43469 /*! @{ */
43470 #define ENET_PRSACPT0_COUNT_MASK                 (0xFFFFFFFFU)
43471 #define ENET_PRSACPT0_COUNT_SHIFT                (0U)
43472 /*! COUNT - Count
43473  */
43474 #define ENET_PRSACPT0_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_PRSACPT0_COUNT_SHIFT)) & ENET_PRSACPT0_COUNT_MASK)
43475 /*! @} */
43476 
43477 /*! @name PRSRJCT0 - Parser Reject Count 0 */
43478 /*! @{ */
43479 #define ENET_PRSRJCT0_COUNT_MASK                 (0xFFFFFFFFU)
43480 #define ENET_PRSRJCT0_COUNT_SHIFT                (0U)
43481 /*! COUNT - Count
43482  */
43483 #define ENET_PRSRJCT0_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_PRSRJCT0_COUNT_SHIFT)) & ENET_PRSRJCT0_COUNT_MASK)
43484 /*! @} */
43485 
43486 /*! @name PRSACPT1 - Parser Accept Count 1 */
43487 /*! @{ */
43488 #define ENET_PRSACPT1_COUNT_MASK                 (0xFFFFFFFFU)
43489 #define ENET_PRSACPT1_COUNT_SHIFT                (0U)
43490 /*! COUNT - Count
43491  */
43492 #define ENET_PRSACPT1_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_PRSACPT1_COUNT_SHIFT)) & ENET_PRSACPT1_COUNT_MASK)
43493 /*! @} */
43494 
43495 /*! @name PRSRJCT1 - Parser Reject Count 1 */
43496 /*! @{ */
43497 #define ENET_PRSRJCT1_COUNT_MASK                 (0xFFFFFFFFU)
43498 #define ENET_PRSRJCT1_COUNT_SHIFT                (0U)
43499 /*! COUNT - Count
43500  */
43501 #define ENET_PRSRJCT1_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_PRSRJCT1_COUNT_SHIFT)) & ENET_PRSRJCT1_COUNT_MASK)
43502 /*! @} */
43503 
43504 /*! @name PRSACPT2 - Parser Accept Count 2 */
43505 /*! @{ */
43506 #define ENET_PRSACPT2_COUNT_MASK                 (0xFFFFFFFFU)
43507 #define ENET_PRSACPT2_COUNT_SHIFT                (0U)
43508 /*! COUNT - Count
43509  */
43510 #define ENET_PRSACPT2_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_PRSACPT2_COUNT_SHIFT)) & ENET_PRSACPT2_COUNT_MASK)
43511 /*! @} */
43512 
43513 /*! @name PRSRJCT2 - Parser Reject Count 2 */
43514 /*! @{ */
43515 #define ENET_PRSRJCT2_COUNT_MASK                 (0xFFFFFFFFU)
43516 #define ENET_PRSRJCT2_COUNT_SHIFT                (0U)
43517 /*! COUNT - Count
43518  */
43519 #define ENET_PRSRJCT2_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_PRSRJCT2_COUNT_SHIFT)) & ENET_PRSRJCT2_COUNT_MASK)
43520 /*! @} */
43521 
43522 /*! @name TGSR - Timer Global Status Register */
43523 /*! @{ */
43524 #define ENET_TGSR_TF0_MASK                       (0x1U)
43525 #define ENET_TGSR_TF0_SHIFT                      (0U)
43526 /*! TF0 - Copy Of Timer Flag For Channel 0
43527  *  0b0..Timer Flag for Channel 0 is clear
43528  *  0b1..Timer Flag for Channel 0 is set
43529  */
43530 #define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
43531 #define ENET_TGSR_TF1_MASK                       (0x2U)
43532 #define ENET_TGSR_TF1_SHIFT                      (1U)
43533 /*! TF1 - Copy Of Timer Flag For Channel 1
43534  *  0b0..Timer Flag for Channel 1 is clear
43535  *  0b1..Timer Flag for Channel 1 is set
43536  */
43537 #define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
43538 #define ENET_TGSR_TF2_MASK                       (0x4U)
43539 #define ENET_TGSR_TF2_SHIFT                      (2U)
43540 /*! TF2 - Copy Of Timer Flag For Channel 2
43541  *  0b0..Timer Flag for Channel 2 is clear
43542  *  0b1..Timer Flag for Channel 2 is set
43543  */
43544 #define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
43545 #define ENET_TGSR_TF3_MASK                       (0x8U)
43546 #define ENET_TGSR_TF3_SHIFT                      (3U)
43547 /*! TF3 - Copy Of Timer Flag For Channel 3
43548  *  0b0..Timer Flag for Channel 3 is clear
43549  *  0b1..Timer Flag for Channel 3 is set
43550  */
43551 #define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
43552 /*! @} */
43553 
43554 /*! @name TCSR - Timer Control Status Register */
43555 /*! @{ */
43556 #define ENET_TCSR_TDRE_MASK                      (0x1U)
43557 #define ENET_TCSR_TDRE_SHIFT                     (0U)
43558 /*! TDRE - Timer DMA Request Enable
43559  *  0b0..DMA request is disabled
43560  *  0b1..DMA request is enabled
43561  */
43562 #define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
43563 #define ENET_TCSR_TMODE_MASK                     (0x3CU)
43564 #define ENET_TCSR_TMODE_SHIFT                    (2U)
43565 /*! TMODE - Timer Mode
43566  *  0b0000..Timer Channel is disabled.
43567  *  0b0001..Timer Channel is configured for Input Capture on rising edge.
43568  *  0b0010..Timer Channel is configured for Input Capture on falling edge.
43569  *  0b0011..Timer Channel is configured for Input Capture on both edges.
43570  *  0b0100..Timer Channel is configured for Output Compare - software only.
43571  *  0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
43572  *  0b0110..Timer Channel is configured for Output Compare - clear output on compare.
43573  *  0b0111..Timer Channel is configured for Output Compare - set output on compare.
43574  *  0b1000..Reserved
43575  *  0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
43576  *  0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
43577  *  0b110x..Reserved
43578  *  0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
43579  *  0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
43580  */
43581 #define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
43582 #define ENET_TCSR_TIE_MASK                       (0x40U)
43583 #define ENET_TCSR_TIE_SHIFT                      (6U)
43584 /*! TIE - Timer Interrupt Enable
43585  *  0b0..Interrupt is disabled
43586  *  0b1..Interrupt is enabled
43587  */
43588 #define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
43589 #define ENET_TCSR_TF_MASK                        (0x80U)
43590 #define ENET_TCSR_TF_SHIFT                       (7U)
43591 /*! TF - Timer Flag
43592  *  0b0..Input Capture or Output Compare has not occurred.
43593  *  0b1..Input Capture or Output Compare has occurred.
43594  */
43595 #define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
43596 #define ENET_TCSR_TPWC_MASK                      (0xF800U)
43597 #define ENET_TCSR_TPWC_SHIFT                     (11U)
43598 /*! TPWC - Timer PulseWidth Control
43599  *  0b00000..Pulse width is one 1588-clock cycle.
43600  *  0b00001..Pulse width is two 1588-clock cycles.
43601  *  0b00010..Pulse width is three 1588-clock cycles.
43602  *  0b00011..Pulse width is four 1588-clock cycles.
43603  *  0b11111..Pulse width is 32 1588-clock cycles.
43604  */
43605 #define ENET_TCSR_TPWC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
43606 /*! @} */
43607 
43608 /* The count of ENET_TCSR */
43609 #define ENET_TCSR_COUNT                          (4U)
43610 
43611 /*! @name TCCR - Timer Compare Capture Register */
43612 /*! @{ */
43613 #define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
43614 #define ENET_TCCR_TCC_SHIFT                      (0U)
43615 /*! TCC - Timer Capture Compare
43616  */
43617 #define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
43618 /*! @} */
43619 
43620 /* The count of ENET_TCCR */
43621 #define ENET_TCCR_COUNT                          (4U)
43622 
43623 
43624 /*!
43625  * @}
43626  */ /* end of group ENET_Register_Masks */
43627 
43628 
43629 /* ENET - Peripheral instance base addresses */
43630 /** Peripheral CONNECTIVITY__ENET0 base address */
43631 #define CONNECTIVITY__ENET0_BASE                 (0x5B040000u)
43632 /** Peripheral CONNECTIVITY__ENET0 base pointer */
43633 #define CONNECTIVITY__ENET0                      ((ENET_Type *)CONNECTIVITY__ENET0_BASE)
43634 /** Peripheral CONNECTIVITY__ENET1 base address */
43635 #define CONNECTIVITY__ENET1_BASE                 (0x5B050000u)
43636 /** Peripheral CONNECTIVITY__ENET1 base pointer */
43637 #define CONNECTIVITY__ENET1                      ((ENET_Type *)CONNECTIVITY__ENET1_BASE)
43638 /** Array initializer of ENET peripheral base addresses */
43639 #define ENET_BASE_ADDRS                          { CONNECTIVITY__ENET0_BASE, CONNECTIVITY__ENET1_BASE }
43640 /** Array initializer of ENET peripheral base pointers */
43641 #define ENET_BASE_PTRS                           { CONNECTIVITY__ENET0, CONNECTIVITY__ENET1 }
43642 /* ENET Buffer Descriptor and Buffer Address Alignment. */
43643 #define ENET_BUFF_ALIGNMENT                      (64U)
43644 
43645 /* Interrupt vectors for the ENET peripheral type */
43646 #define ENET_Transmit_IRQS                       { NotAvail_IRQn, NotAvail_IRQn }
43647 #define ENET_Receive_IRQS                        { NotAvail_IRQn, NotAvail_IRQn }
43648 #define ENET_Error_IRQS                          { NotAvail_IRQn, NotAvail_IRQn }
43649 #define ENET_1588_Timer_IRQS                     { NotAvail_IRQn, NotAvail_IRQn }
43650 #define ENET_Ts_IRQS                             { NotAvail_IRQn, NotAvail_IRQn }
43651 
43652 
43653 /*!
43654  * @}
43655  */ /* end of group ENET_Peripheral_Access_Layer */
43656 
43657 
43658 /* ----------------------------------------------------------------------------
43659    -- ESAI Peripheral Access Layer
43660    ---------------------------------------------------------------------------- */
43661 
43662 /*!
43663  * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer
43664  * @{
43665  */
43666 
43667 /** ESAI - Register Layout Typedef */
43668 typedef struct {
43669   __O  uint32_t ETDR;                              /**< ESAI Transmit Data Register, offset: 0x0 */
43670   __I  uint32_t ERDR;                              /**< ESAI Receive Data Register, offset: 0x4 */
43671   __IO uint32_t ECR;                               /**< ESAI Control Register, offset: 0x8 */
43672   __I  uint32_t ESR;                               /**< ESAI Status Register, offset: 0xC */
43673   __IO uint32_t TFCR;                              /**< Transmit FIFO Configuration Register, offset: 0x10 */
43674   __I  uint32_t TFSR;                              /**< Transmit FIFO Status Register, offset: 0x14 */
43675   __IO uint32_t RFCR;                              /**< Receive FIFO Configuration Register, offset: 0x18 */
43676   __I  uint32_t RFSR;                              /**< Receive FIFO Status Register, offset: 0x1C */
43677        uint8_t RESERVED_0[96];
43678   __O  uint32_t TX[6];                             /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */
43679   __O  uint32_t TSR;                               /**< ESAI Transmit Slot Register, offset: 0x98 */
43680        uint8_t RESERVED_1[4];
43681   __I  uint32_t RX[4];                             /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */
43682        uint8_t RESERVED_2[28];
43683   __I  uint32_t SAISR;                             /**< Serial Audio Interface Status Register, offset: 0xCC */
43684   __IO uint32_t SAICR;                             /**< Serial Audio Interface Control Register, offset: 0xD0 */
43685   __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xD4 */
43686   __IO uint32_t TCCR;                              /**< Transmit Clock Control Register, offset: 0xD8 */
43687   __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0xDC */
43688   __IO uint32_t RCCR;                              /**< Receive Clock Control Register, offset: 0xE0 */
43689   __IO uint32_t TSMA;                              /**< Transmit Slot Mask Register A, offset: 0xE4 */
43690   __IO uint32_t TSMB;                              /**< Transmit Slot Mask Register B, offset: 0xE8 */
43691   __IO uint32_t RSMA;                              /**< Receive Slot Mask Register A, offset: 0xEC */
43692   __IO uint32_t RSMB;                              /**< Receive Slot Mask Register B, offset: 0xF0 */
43693        uint8_t RESERVED_3[4];
43694   __IO uint32_t PRRC;                              /**< Port C Direction Register, offset: 0xF8 */
43695   __IO uint32_t PCRC;                              /**< Port C Control Register, offset: 0xFC */
43696 } ESAI_Type;
43697 
43698 /* ----------------------------------------------------------------------------
43699    -- ESAI Register Masks
43700    ---------------------------------------------------------------------------- */
43701 
43702 /*!
43703  * @addtogroup ESAI_Register_Masks ESAI Register Masks
43704  * @{
43705  */
43706 
43707 /*! @name ETDR - ESAI Transmit Data Register */
43708 /*! @{ */
43709 #define ESAI_ETDR_ETDR_MASK                      (0xFFFFFFFFU)
43710 #define ESAI_ETDR_ETDR_SHIFT                     (0U)
43711 /*! ETDR - ETDR
43712  */
43713 #define ESAI_ETDR_ETDR(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_ETDR_ETDR_SHIFT)) & ESAI_ETDR_ETDR_MASK)
43714 /*! @} */
43715 
43716 /*! @name ERDR - ESAI Receive Data Register */
43717 /*! @{ */
43718 #define ESAI_ERDR_ERDR_MASK                      (0xFFFFFFFFU)
43719 #define ESAI_ERDR_ERDR_SHIFT                     (0U)
43720 /*! ERDR - ERDR
43721  */
43722 #define ESAI_ERDR_ERDR(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_ERDR_ERDR_SHIFT)) & ESAI_ERDR_ERDR_MASK)
43723 /*! @} */
43724 
43725 /*! @name ECR - ESAI Control Register */
43726 /*! @{ */
43727 #define ESAI_ECR_ESAIEN_MASK                     (0x1U)
43728 #define ESAI_ECR_ESAIEN_SHIFT                    (0U)
43729 /*! ESAIEN - ESAIEN
43730  *  0b0..ESAI disabled.
43731  *  0b1..ESAI enabled.
43732  */
43733 #define ESAI_ECR_ESAIEN(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ESAIEN_SHIFT)) & ESAI_ECR_ESAIEN_MASK)
43734 #define ESAI_ECR_ERST_MASK                       (0x2U)
43735 #define ESAI_ECR_ERST_SHIFT                      (1U)
43736 /*! ERST - ERST
43737  *  0b0..ESAI not reset.
43738  *  0b1..ESAI reset.
43739  */
43740 #define ESAI_ECR_ERST(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERST_SHIFT)) & ESAI_ECR_ERST_MASK)
43741 #define ESAI_ECR_ERO_MASK                        (0x10000U)
43742 #define ESAI_ECR_ERO_SHIFT                       (16U)
43743 /*! ERO - ERO
43744  *  0b0..HCKR pin has normal function.
43745  *  0b1..EXTAL driven onto HCKR pin.
43746  */
43747 #define ESAI_ECR_ERO(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERO_SHIFT)) & ESAI_ECR_ERO_MASK)
43748 #define ESAI_ECR_ERI_MASK                        (0x20000U)
43749 #define ESAI_ECR_ERI_SHIFT                       (17U)
43750 /*! ERI - ERI
43751  *  0b0..HCKR pin has normal function.
43752  *  0b1..EXTAL muxed into HCKR input.
43753  */
43754 #define ESAI_ECR_ERI(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERI_SHIFT)) & ESAI_ECR_ERI_MASK)
43755 #define ESAI_ECR_ETO_MASK                        (0x40000U)
43756 #define ESAI_ECR_ETO_SHIFT                       (18U)
43757 /*! ETO - ETO
43758  *  0b0..HCKT pin has normal function.
43759  *  0b1..EXTAL driven onto HCKT pin.
43760  */
43761 #define ESAI_ECR_ETO(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETO_SHIFT)) & ESAI_ECR_ETO_MASK)
43762 #define ESAI_ECR_ETI_MASK                        (0x80000U)
43763 #define ESAI_ECR_ETI_SHIFT                       (19U)
43764 /*! ETI - ETI
43765  *  0b0..HCKT pin has normal function.
43766  *  0b1..EXTAL muxed into HCKT input.
43767  */
43768 #define ESAI_ECR_ETI(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETI_SHIFT)) & ESAI_ECR_ETI_MASK)
43769 /*! @} */
43770 
43771 /*! @name ESR - ESAI Status Register */
43772 /*! @{ */
43773 #define ESAI_ESR_RD_MASK                         (0x1U)
43774 #define ESAI_ESR_RD_SHIFT                        (0U)
43775 /*! RD - RD
43776  *  0b0..RD is not the highest priority active interrupt.
43777  *  0b1..RD is the highest priority active interrupt.
43778  */
43779 #define ESAI_ESR_RD(x)                           (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RD_SHIFT)) & ESAI_ESR_RD_MASK)
43780 #define ESAI_ESR_RED_MASK                        (0x2U)
43781 #define ESAI_ESR_RED_SHIFT                       (1U)
43782 /*! RED - RED
43783  *  0b0..RED is not the highest priority active interrupt.
43784  *  0b1..RED is the highest priority active interrupt.
43785  */
43786 #define ESAI_ESR_RED(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RED_SHIFT)) & ESAI_ESR_RED_MASK)
43787 #define ESAI_ESR_RDE_MASK                        (0x4U)
43788 #define ESAI_ESR_RDE_SHIFT                       (2U)
43789 /*! RDE - RDE
43790  *  0b0..RDE is not the highest priority active interrupt.
43791  *  0b1..RDE is the highest priority active interrupt.
43792  */
43793 #define ESAI_ESR_RDE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RDE_SHIFT)) & ESAI_ESR_RDE_MASK)
43794 #define ESAI_ESR_RLS_MASK                        (0x8U)
43795 #define ESAI_ESR_RLS_SHIFT                       (3U)
43796 /*! RLS - RLS
43797  *  0b0..RLS is not the highest priority active interrupt.
43798  *  0b1..RLS is the highest priority active interrupt.
43799  */
43800 #define ESAI_ESR_RLS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RLS_SHIFT)) & ESAI_ESR_RLS_MASK)
43801 #define ESAI_ESR_TD_MASK                         (0x10U)
43802 #define ESAI_ESR_TD_SHIFT                        (4U)
43803 /*! TD - TD
43804  *  0b0..TD is not the highest priority active interrupt.
43805  *  0b1..TD is the highest priority active interrupt.
43806  */
43807 #define ESAI_ESR_TD(x)                           (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TD_SHIFT)) & ESAI_ESR_TD_MASK)
43808 #define ESAI_ESR_TED_MASK                        (0x20U)
43809 #define ESAI_ESR_TED_SHIFT                       (5U)
43810 /*! TED - TED
43811  *  0b0..TED is not the highest priority active interrupt.
43812  *  0b1..TED is the highest priority active interrupt.
43813  */
43814 #define ESAI_ESR_TED(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TED_SHIFT)) & ESAI_ESR_TED_MASK)
43815 #define ESAI_ESR_TDE_MASK                        (0x40U)
43816 #define ESAI_ESR_TDE_SHIFT                       (6U)
43817 /*! TDE - TDE
43818  *  0b0..TDE is not the highest priority active interrupt.
43819  *  0b1..TDE is the highest priority active interrupt.
43820  */
43821 #define ESAI_ESR_TDE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TDE_SHIFT)) & ESAI_ESR_TDE_MASK)
43822 #define ESAI_ESR_TLS_MASK                        (0x80U)
43823 #define ESAI_ESR_TLS_SHIFT                       (7U)
43824 /*! TLS - TLS
43825  *  0b0..TLS is not the highest priority active interrupt.
43826  *  0b1..TLS is the highest priority active interrupt.
43827  */
43828 #define ESAI_ESR_TLS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TLS_SHIFT)) & ESAI_ESR_TLS_MASK)
43829 #define ESAI_ESR_TFE_MASK                        (0x100U)
43830 #define ESAI_ESR_TFE_SHIFT                       (8U)
43831 /*! TFE - TFE
43832  *  0b0..Number of empty slots in Transmit FIFO less than Transmit FIFO watermark.
43833  *  0b1..Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark.
43834  */
43835 #define ESAI_ESR_TFE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TFE_SHIFT)) & ESAI_ESR_TFE_MASK)
43836 #define ESAI_ESR_RFF_MASK                        (0x200U)
43837 #define ESAI_ESR_RFF_SHIFT                       (9U)
43838 /*! RFF - RFF
43839  *  0b0..Number of words in Receive FIFO less than Receive FIFO watermark.
43840  *  0b1..Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark.
43841  */
43842 #define ESAI_ESR_RFF(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RFF_SHIFT)) & ESAI_ESR_RFF_MASK)
43843 #define ESAI_ESR_TINIT_MASK                      (0x400U)
43844 #define ESAI_ESR_TINIT_SHIFT                     (10U)
43845 /*! TINIT - TINIT
43846  *  0b0..Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or
43847  *       Transmit Initialization is not enabled).
43848  *  0b1..Transmitter has not finished initializing the Transmit Data Registers.
43849  */
43850 #define ESAI_ESR_TINIT(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TINIT_SHIFT)) & ESAI_ESR_TINIT_MASK)
43851 /*! @} */
43852 
43853 /*! @name TFCR - Transmit FIFO Configuration Register */
43854 /*! @{ */
43855 #define ESAI_TFCR_TFE_MASK                       (0x1U)
43856 #define ESAI_TFCR_TFE_SHIFT                      (0U)
43857 /*! TFE - TFE
43858  *  0b0..Transmit FIFO disabled.
43859  *  0b1..Transmit FIFO enabled.
43860  */
43861 #define ESAI_TFCR_TFE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFE_SHIFT)) & ESAI_TFCR_TFE_MASK)
43862 #define ESAI_TFCR_TFR_MASK                       (0x2U)
43863 #define ESAI_TFCR_TFR_SHIFT                      (1U)
43864 /*! TFR - TFR
43865  *  0b0..Transmit FIFO not reset.
43866  *  0b1..Transmit FIFO reset.
43867  */
43868 #define ESAI_TFCR_TFR(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFR_SHIFT)) & ESAI_TFCR_TFR_MASK)
43869 #define ESAI_TFCR_TE0_MASK                       (0x4U)
43870 #define ESAI_TFCR_TE0_SHIFT                      (2U)
43871 /*! TE0 - TE0
43872  *  0b0..Transmitter #0 is not using the Transmit FIFO.
43873  *  0b1..Transmitter #0 is using the Transmit FIFO.
43874  */
43875 #define ESAI_TFCR_TE0(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE0_SHIFT)) & ESAI_TFCR_TE0_MASK)
43876 #define ESAI_TFCR_TE1_MASK                       (0x8U)
43877 #define ESAI_TFCR_TE1_SHIFT                      (3U)
43878 /*! TE1 - TE1
43879  *  0b0..Transmitter #1 is not using the Transmit FIFO.
43880  *  0b1..Transmitter #1 is using the Transmit FIFO.
43881  */
43882 #define ESAI_TFCR_TE1(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE1_SHIFT)) & ESAI_TFCR_TE1_MASK)
43883 #define ESAI_TFCR_TE2_MASK                       (0x10U)
43884 #define ESAI_TFCR_TE2_SHIFT                      (4U)
43885 /*! TE2 - TE2
43886  *  0b0..Transmitter #2 is not using the Transmit FIFO.
43887  *  0b1..Transmitter #2 is using the Transmit FIFO.
43888  */
43889 #define ESAI_TFCR_TE2(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE2_SHIFT)) & ESAI_TFCR_TE2_MASK)
43890 #define ESAI_TFCR_TE3_MASK                       (0x20U)
43891 #define ESAI_TFCR_TE3_SHIFT                      (5U)
43892 /*! TE3 - TE3
43893  *  0b0..Transmitter #3 is not using the Transmit FIFO.
43894  *  0b1..Transmitter #3 is using the Transmit FIFO.
43895  */
43896 #define ESAI_TFCR_TE3(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE3_SHIFT)) & ESAI_TFCR_TE3_MASK)
43897 #define ESAI_TFCR_TE4_MASK                       (0x40U)
43898 #define ESAI_TFCR_TE4_SHIFT                      (6U)
43899 /*! TE4 - TE4
43900  *  0b0..Transmitter #4 is not using the Transmit FIFO.
43901  *  0b1..Transmitter #4 is using the Transmit FIFO.
43902  */
43903 #define ESAI_TFCR_TE4(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE4_SHIFT)) & ESAI_TFCR_TE4_MASK)
43904 #define ESAI_TFCR_TE5_MASK                       (0x80U)
43905 #define ESAI_TFCR_TE5_SHIFT                      (7U)
43906 /*! TE5 - TE5
43907  *  0b0..Transmitter #5 is not using the Transmit FIFO.
43908  *  0b1..Transmitter #5 is using the Transmit FIFO.
43909  */
43910 #define ESAI_TFCR_TE5(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE5_SHIFT)) & ESAI_TFCR_TE5_MASK)
43911 #define ESAI_TFCR_TFWM_MASK                      (0xFF00U)
43912 #define ESAI_TFCR_TFWM_SHIFT                     (8U)
43913 /*! TFWM - TFWM
43914  */
43915 #define ESAI_TFCR_TFWM(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFWM_SHIFT)) & ESAI_TFCR_TFWM_MASK)
43916 #define ESAI_TFCR_TWA_MASK                       (0x70000U)
43917 #define ESAI_TFCR_TWA_SHIFT                      (16U)
43918 /*! TWA - TWA
43919  *  0b000..MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register.
43920  *  0b001..MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register.
43921  *  0b010..MSB of data is bit 23.
43922  *  0b011..MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed.
43923  *  0b100..MSB of data is bit 15. Bottom 8 bits of transmit shift register are zeroed.
43924  *  0b101..MSB of data is bit 11. Bottom 12 bits of transmit shift register are zeroed.
43925  *  0b110..MSB of data is bit 7. Bottom 16 bits of transmit shift register are zeroed.
43926  *  0b111..MSB of data is bit 3. Bottom 20 bits of transmit shift register are zeroed.
43927  */
43928 #define ESAI_TFCR_TWA(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TWA_SHIFT)) & ESAI_TFCR_TWA_MASK)
43929 #define ESAI_TFCR_TIEN_MASK                      (0x80000U)
43930 #define ESAI_TFCR_TIEN_SHIFT                     (19U)
43931 /*! TIEN - TIEN
43932  *  0b0..Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software
43933  *       must manually initialize the Transmit Data Registers separately.
43934  *  0b1..Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled.
43935  */
43936 #define ESAI_TFCR_TIEN(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TIEN_SHIFT)) & ESAI_TFCR_TIEN_MASK)
43937 /*! @} */
43938 
43939 /*! @name TFSR - Transmit FIFO Status Register */
43940 /*! @{ */
43941 #define ESAI_TFSR_TFCNT_MASK                     (0xFFU)
43942 #define ESAI_TFSR_TFCNT_SHIFT                    (0U)
43943 /*! TFCNT - TFCNT
43944  */
43945 #define ESAI_TFSR_TFCNT(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_TFCNT_SHIFT)) & ESAI_TFSR_TFCNT_MASK)
43946 #define ESAI_TFSR_NTFI_MASK                      (0x700U)
43947 #define ESAI_TFSR_NTFI_SHIFT                     (8U)
43948 /*! NTFI - NTFI
43949  *  0b000..Transmitter #0 receives next word written to the Transmit FIFO.
43950  *  0b001..Transmitter #1 receives next word written to the Transmit FIFO.
43951  *  0b010..Transmitter #2 receives next word written to the Transmit FIFO.
43952  *  0b011..Transmitter #3 receives next word written to the Transmit FIFO.
43953  *  0b100..Transmitter #4 receives next word written to the Transmit FIFO.
43954  *  0b101..Transmitter #5 receives next word written to the Transmit FIFO.
43955  *  0b110..Reserved.
43956  *  0b111..Reserved.
43957  */
43958 #define ESAI_TFSR_NTFI(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFI_SHIFT)) & ESAI_TFSR_NTFI_MASK)
43959 #define ESAI_TFSR_NTFO_MASK                      (0x7000U)
43960 #define ESAI_TFSR_NTFO_SHIFT                     (12U)
43961 /*! NTFO - NTFO
43962  *  0b000..Transmitter #0 receives next word from the Transmit FIFO.
43963  *  0b001..Transmitter #1 receives next word from the Transmit FIFO.
43964  *  0b010..Transmitter #2 receives next word from the Transmit FIFO.
43965  *  0b011..Transmitter #3 receives next word from the Transmit FIFO.
43966  *  0b100..Transmitter #4 receives next word from the Transmit FIFO.
43967  *  0b101..Transmitter #5 receives next word from the Transmit FIFO.
43968  *  0b110..Reserved.
43969  *  0b111..Reserved.
43970  */
43971 #define ESAI_TFSR_NTFO(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFO_SHIFT)) & ESAI_TFSR_NTFO_MASK)
43972 /*! @} */
43973 
43974 /*! @name RFCR - Receive FIFO Configuration Register */
43975 /*! @{ */
43976 #define ESAI_RFCR_RFE_MASK                       (0x1U)
43977 #define ESAI_RFCR_RFE_SHIFT                      (0U)
43978 /*! RFE - RFE
43979  *  0b0..Receive FIFO disabled.
43980  *  0b1..Receive FIFO enabled.
43981  */
43982 #define ESAI_RFCR_RFE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFE_SHIFT)) & ESAI_RFCR_RFE_MASK)
43983 #define ESAI_RFCR_RFR_MASK                       (0x2U)
43984 #define ESAI_RFCR_RFR_SHIFT                      (1U)
43985 /*! RFR - RFR
43986  *  0b0..Receive FIFO not reset.
43987  *  0b1..Receive FIFO reset.
43988  */
43989 #define ESAI_RFCR_RFR(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFR_SHIFT)) & ESAI_RFCR_RFR_MASK)
43990 #define ESAI_RFCR_RE0_MASK                       (0x4U)
43991 #define ESAI_RFCR_RE0_SHIFT                      (2U)
43992 /*! RE0 - RE0
43993  *  0b0..Receiver #0 is not using the Receive FIFO.
43994  *  0b1..Receiver #0 is using the Receive FIFO.
43995  */
43996 #define ESAI_RFCR_RE0(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE0_SHIFT)) & ESAI_RFCR_RE0_MASK)
43997 #define ESAI_RFCR_RE1_MASK                       (0x8U)
43998 #define ESAI_RFCR_RE1_SHIFT                      (3U)
43999 /*! RE1 - RE1
44000  *  0b0..Receiver #1 is not using the Receive FIFO.
44001  *  0b1..Receiver #1 is using the Receive FIFO.
44002  */
44003 #define ESAI_RFCR_RE1(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE1_SHIFT)) & ESAI_RFCR_RE1_MASK)
44004 #define ESAI_RFCR_RE2_MASK                       (0x10U)
44005 #define ESAI_RFCR_RE2_SHIFT                      (4U)
44006 /*! RE2 - RE2
44007  *  0b0..Receiver #2 is not using the Receive FIFO.
44008  *  0b1..Receiver #2 is using the Receive FIFO.
44009  */
44010 #define ESAI_RFCR_RE2(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE2_SHIFT)) & ESAI_RFCR_RE2_MASK)
44011 #define ESAI_RFCR_RE3_MASK                       (0x20U)
44012 #define ESAI_RFCR_RE3_SHIFT                      (5U)
44013 /*! RE3 - RE3
44014  *  0b0..Receiver #3 is not using the Receive FIFO.
44015  *  0b1..Receiver #3 is using the Receive FIFO.
44016  */
44017 #define ESAI_RFCR_RE3(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE3_SHIFT)) & ESAI_RFCR_RE3_MASK)
44018 #define ESAI_RFCR_RFWM_MASK                      (0xFF00U)
44019 #define ESAI_RFCR_RFWM_SHIFT                     (8U)
44020 /*! RFWM - RFWM
44021  */
44022 #define ESAI_RFCR_RFWM(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFWM_SHIFT)) & ESAI_RFCR_RFWM_MASK)
44023 #define ESAI_RFCR_RWA_MASK                       (0x70000U)
44024 #define ESAI_RFCR_RWA_SHIFT                      (16U)
44025 /*! RWA - RWA
44026  *  0b000..MSB of data is at bit 31. Data bits 7-0 are zeroed.
44027  *  0b001..MSB of data is at bit 27. Data bits 3-0 are zeroed.
44028  *  0b010..MSB of data is at bit 23.
44029  *  0b011..MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored.
44030  *  0b100..MSB of data is at bit 15. Data bits 7-0 from receive shift register are ignored.
44031  *  0b101..MSB of data is at bit 11. Data bits 11-0 from receive shift register are ignored.
44032  *  0b110..MSB of data is at bit 7. Data bits 15-0 from receive shift register are ignored.
44033  *  0b111..MSB of data is at bit 3. Data bits 19-0 from receive shift register are ignored.
44034  */
44035 #define ESAI_RFCR_RWA(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RWA_SHIFT)) & ESAI_RFCR_RWA_MASK)
44036 #define ESAI_RFCR_REXT_MASK                      (0x80000U)
44037 #define ESAI_RFCR_REXT_SHIFT                     (19U)
44038 /*! REXT - REXT
44039  *  0b0..Receive data is zero extended.
44040  *  0b1..Receive data is sign extended.
44041  */
44042 #define ESAI_RFCR_REXT(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_REXT_SHIFT)) & ESAI_RFCR_REXT_MASK)
44043 /*! @} */
44044 
44045 /*! @name RFSR - Receive FIFO Status Register */
44046 /*! @{ */
44047 #define ESAI_RFSR_RFCNT_MASK                     (0xFFU)
44048 #define ESAI_RFSR_RFCNT_SHIFT                    (0U)
44049 /*! RFCNT - RFCNT
44050  */
44051 #define ESAI_RFSR_RFCNT(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_RFCNT_SHIFT)) & ESAI_RFSR_RFCNT_MASK)
44052 #define ESAI_RFSR_NRFO_MASK                      (0x300U)
44053 #define ESAI_RFSR_NRFO_SHIFT                     (8U)
44054 /*! NRFO - NRFO
44055  *  0b00..Receiver #0 returns next word from the Receive FIFO.
44056  *  0b01..Receiver #1 returns next word from the Receive FIFO.
44057  *  0b10..Receiver #2 returns next word from the Receive FIFO.
44058  *  0b11..Receiver #3 returns next word from the Receive FIFO.
44059  */
44060 #define ESAI_RFSR_NRFO(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFO_SHIFT)) & ESAI_RFSR_NRFO_MASK)
44061 #define ESAI_RFSR_NRFI_MASK                      (0x3000U)
44062 #define ESAI_RFSR_NRFI_SHIFT                     (12U)
44063 /*! NRFI - NRFI
44064  *  0b00..Receiver #0 returns next word to the Receive FIFO.
44065  *  0b01..Receiver #1 returns next word to the Receive FIFO.
44066  *  0b10..Receiver #2 returns next word to the Receive FIFO.
44067  *  0b11..Receiver #3 returns next word to the Receive FIFO.
44068  */
44069 #define ESAI_RFSR_NRFI(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFI_SHIFT)) & ESAI_RFSR_NRFI_MASK)
44070 /*! @} */
44071 
44072 /*! @name TX - Transmit Data Register n */
44073 /*! @{ */
44074 #define ESAI_TX_TXn_MASK                         (0xFFFFFFU)
44075 #define ESAI_TX_TXn_SHIFT                        (0U)
44076 /*! TXn - TXn
44077  */
44078 #define ESAI_TX_TXn(x)                           (((uint32_t)(((uint32_t)(x)) << ESAI_TX_TXn_SHIFT)) & ESAI_TX_TXn_MASK)
44079 /*! @} */
44080 
44081 /* The count of ESAI_TX */
44082 #define ESAI_TX_COUNT                            (6U)
44083 
44084 /*! @name TSR - ESAI Transmit Slot Register */
44085 /*! @{ */
44086 #define ESAI_TSR_TSR_MASK                        (0xFFFFFFU)
44087 #define ESAI_TSR_TSR_SHIFT                       (0U)
44088 /*! TSR - TSR
44089  */
44090 #define ESAI_TSR_TSR(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TSR_TSR_SHIFT)) & ESAI_TSR_TSR_MASK)
44091 /*! @} */
44092 
44093 /*! @name RX - Receive Data Register n */
44094 /*! @{ */
44095 #define ESAI_RX_RXn_MASK                         (0xFFFFFFU)
44096 #define ESAI_RX_RXn_SHIFT                        (0U)
44097 /*! RXn - RXn
44098  */
44099 #define ESAI_RX_RXn(x)                           (((uint32_t)(((uint32_t)(x)) << ESAI_RX_RXn_SHIFT)) & ESAI_RX_RXn_MASK)
44100 /*! @} */
44101 
44102 /* The count of ESAI_RX */
44103 #define ESAI_RX_COUNT                            (4U)
44104 
44105 /*! @name SAISR - Serial Audio Interface Status Register */
44106 /*! @{ */
44107 #define ESAI_SAISR_IF0_MASK                      (0x1U)
44108 #define ESAI_SAISR_IF0_SHIFT                     (0U)
44109 /*! IF0 - IF0
44110  */
44111 #define ESAI_SAISR_IF0(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF0_SHIFT)) & ESAI_SAISR_IF0_MASK)
44112 #define ESAI_SAISR_IF1_MASK                      (0x2U)
44113 #define ESAI_SAISR_IF1_SHIFT                     (1U)
44114 /*! IF1 - IF1
44115  */
44116 #define ESAI_SAISR_IF1(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF1_SHIFT)) & ESAI_SAISR_IF1_MASK)
44117 #define ESAI_SAISR_IF2_MASK                      (0x4U)
44118 #define ESAI_SAISR_IF2_SHIFT                     (2U)
44119 /*! IF2 - IF2
44120  */
44121 #define ESAI_SAISR_IF2(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF2_SHIFT)) & ESAI_SAISR_IF2_MASK)
44122 #define ESAI_SAISR_RFS_MASK                      (0x40U)
44123 #define ESAI_SAISR_RFS_SHIFT                     (6U)
44124 /*! RFS - RFS
44125  */
44126 #define ESAI_SAISR_RFS(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RFS_SHIFT)) & ESAI_SAISR_RFS_MASK)
44127 #define ESAI_SAISR_ROE_MASK                      (0x80U)
44128 #define ESAI_SAISR_ROE_SHIFT                     (7U)
44129 /*! ROE - ROE
44130  */
44131 #define ESAI_SAISR_ROE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_ROE_SHIFT)) & ESAI_SAISR_ROE_MASK)
44132 #define ESAI_SAISR_RDF_MASK                      (0x100U)
44133 #define ESAI_SAISR_RDF_SHIFT                     (8U)
44134 /*! RDF - RDF
44135  */
44136 #define ESAI_SAISR_RDF(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RDF_SHIFT)) & ESAI_SAISR_RDF_MASK)
44137 #define ESAI_SAISR_REDF_MASK                     (0x200U)
44138 #define ESAI_SAISR_REDF_SHIFT                    (9U)
44139 /*! REDF - REDF
44140  */
44141 #define ESAI_SAISR_REDF(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_REDF_SHIFT)) & ESAI_SAISR_REDF_MASK)
44142 #define ESAI_SAISR_RODF_MASK                     (0x400U)
44143 #define ESAI_SAISR_RODF_SHIFT                    (10U)
44144 /*! RODF - RODF
44145  */
44146 #define ESAI_SAISR_RODF(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RODF_SHIFT)) & ESAI_SAISR_RODF_MASK)
44147 #define ESAI_SAISR_TFS_MASK                      (0x2000U)
44148 #define ESAI_SAISR_TFS_SHIFT                     (13U)
44149 /*! TFS - TFS
44150  */
44151 #define ESAI_SAISR_TFS(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TFS_SHIFT)) & ESAI_SAISR_TFS_MASK)
44152 #define ESAI_SAISR_TUE_MASK                      (0x4000U)
44153 #define ESAI_SAISR_TUE_SHIFT                     (14U)
44154 /*! TUE - TUE
44155  */
44156 #define ESAI_SAISR_TUE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TUE_SHIFT)) & ESAI_SAISR_TUE_MASK)
44157 #define ESAI_SAISR_TDE_MASK                      (0x8000U)
44158 #define ESAI_SAISR_TDE_SHIFT                     (15U)
44159 /*! TDE - TDE
44160  */
44161 #define ESAI_SAISR_TDE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TDE_SHIFT)) & ESAI_SAISR_TDE_MASK)
44162 #define ESAI_SAISR_TEDE_MASK                     (0x10000U)
44163 #define ESAI_SAISR_TEDE_SHIFT                    (16U)
44164 /*! TEDE - TEDE
44165  */
44166 #define ESAI_SAISR_TEDE(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TEDE_SHIFT)) & ESAI_SAISR_TEDE_MASK)
44167 #define ESAI_SAISR_TODFE_MASK                    (0x20000U)
44168 #define ESAI_SAISR_TODFE_SHIFT                   (17U)
44169 /*! TODFE - TODFE
44170  */
44171 #define ESAI_SAISR_TODFE(x)                      (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TODFE_SHIFT)) & ESAI_SAISR_TODFE_MASK)
44172 /*! @} */
44173 
44174 /*! @name SAICR - Serial Audio Interface Control Register */
44175 /*! @{ */
44176 #define ESAI_SAICR_OF0_MASK                      (0x1U)
44177 #define ESAI_SAICR_OF0_SHIFT                     (0U)
44178 /*! OF0 - OF0
44179  */
44180 #define ESAI_SAICR_OF0(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF0_SHIFT)) & ESAI_SAICR_OF0_MASK)
44181 #define ESAI_SAICR_OF1_MASK                      (0x2U)
44182 #define ESAI_SAICR_OF1_SHIFT                     (1U)
44183 /*! OF1 - OF1
44184  */
44185 #define ESAI_SAICR_OF1(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF1_SHIFT)) & ESAI_SAICR_OF1_MASK)
44186 #define ESAI_SAICR_OF2_MASK                      (0x4U)
44187 #define ESAI_SAICR_OF2_SHIFT                     (2U)
44188 /*! OF2 - OF2
44189  */
44190 #define ESAI_SAICR_OF2(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF2_SHIFT)) & ESAI_SAICR_OF2_MASK)
44191 #define ESAI_SAICR_SYN_MASK                      (0x40U)
44192 #define ESAI_SAICR_SYN_SHIFT                     (6U)
44193 /*! SYN - SYN
44194  */
44195 #define ESAI_SAICR_SYN(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_SYN_SHIFT)) & ESAI_SAICR_SYN_MASK)
44196 #define ESAI_SAICR_TEBE_MASK                     (0x80U)
44197 #define ESAI_SAICR_TEBE_SHIFT                    (7U)
44198 /*! TEBE - TEBE
44199  */
44200 #define ESAI_SAICR_TEBE(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_TEBE_SHIFT)) & ESAI_SAICR_TEBE_MASK)
44201 #define ESAI_SAICR_ALC_MASK                      (0x100U)
44202 #define ESAI_SAICR_ALC_SHIFT                     (8U)
44203 /*! ALC - ALC
44204  */
44205 #define ESAI_SAICR_ALC(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_ALC_SHIFT)) & ESAI_SAICR_ALC_MASK)
44206 /*! @} */
44207 
44208 /*! @name TCR - Transmit Control Register */
44209 /*! @{ */
44210 #define ESAI_TCR_TE0_MASK                        (0x1U)
44211 #define ESAI_TCR_TE0_SHIFT                       (0U)
44212 /*! TE0 - TE0
44213  */
44214 #define ESAI_TCR_TE0(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE0_SHIFT)) & ESAI_TCR_TE0_MASK)
44215 #define ESAI_TCR_TE1_MASK                        (0x2U)
44216 #define ESAI_TCR_TE1_SHIFT                       (1U)
44217 /*! TE1 - TE1
44218  */
44219 #define ESAI_TCR_TE1(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE1_SHIFT)) & ESAI_TCR_TE1_MASK)
44220 #define ESAI_TCR_TE2_MASK                        (0x4U)
44221 #define ESAI_TCR_TE2_SHIFT                       (2U)
44222 /*! TE2 - TE2
44223  */
44224 #define ESAI_TCR_TE2(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE2_SHIFT)) & ESAI_TCR_TE2_MASK)
44225 #define ESAI_TCR_TE3_MASK                        (0x8U)
44226 #define ESAI_TCR_TE3_SHIFT                       (3U)
44227 /*! TE3 - TE3
44228  */
44229 #define ESAI_TCR_TE3(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE3_SHIFT)) & ESAI_TCR_TE3_MASK)
44230 #define ESAI_TCR_TE4_MASK                        (0x10U)
44231 #define ESAI_TCR_TE4_SHIFT                       (4U)
44232 /*! TE4 - TE4
44233  */
44234 #define ESAI_TCR_TE4(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE4_SHIFT)) & ESAI_TCR_TE4_MASK)
44235 #define ESAI_TCR_TE5_MASK                        (0x20U)
44236 #define ESAI_TCR_TE5_SHIFT                       (5U)
44237 /*! TE5 - TE5
44238  */
44239 #define ESAI_TCR_TE5(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE5_SHIFT)) & ESAI_TCR_TE5_MASK)
44240 #define ESAI_TCR_TSHFD_MASK                      (0x40U)
44241 #define ESAI_TCR_TSHFD_SHIFT                     (6U)
44242 /*! TSHFD - TSHFD
44243  */
44244 #define ESAI_TCR_TSHFD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSHFD_SHIFT)) & ESAI_TCR_TSHFD_MASK)
44245 #define ESAI_TCR_TWA_MASK                        (0x80U)
44246 #define ESAI_TCR_TWA_SHIFT                       (7U)
44247 /*! TWA - TWA
44248  */
44249 #define ESAI_TCR_TWA(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TWA_SHIFT)) & ESAI_TCR_TWA_MASK)
44250 #define ESAI_TCR_TMOD_MASK                       (0x300U)
44251 #define ESAI_TCR_TMOD_SHIFT                      (8U)
44252 /*! TMOD - TMOD
44253  */
44254 #define ESAI_TCR_TMOD(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TMOD_SHIFT)) & ESAI_TCR_TMOD_MASK)
44255 #define ESAI_TCR_TSWS_MASK                       (0x7C00U)
44256 #define ESAI_TCR_TSWS_SHIFT                      (10U)
44257 /*! TSWS - TSWS
44258  */
44259 #define ESAI_TCR_TSWS(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSWS_SHIFT)) & ESAI_TCR_TSWS_MASK)
44260 #define ESAI_TCR_TFSL_MASK                       (0x8000U)
44261 #define ESAI_TCR_TFSL_SHIFT                      (15U)
44262 /*! TFSL - TFSL
44263  */
44264 #define ESAI_TCR_TFSL(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSL_SHIFT)) & ESAI_TCR_TFSL_MASK)
44265 #define ESAI_TCR_TFSR_MASK                       (0x10000U)
44266 #define ESAI_TCR_TFSR_SHIFT                      (16U)
44267 /*! TFSR - TFSR
44268  */
44269 #define ESAI_TCR_TFSR(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSR_SHIFT)) & ESAI_TCR_TFSR_MASK)
44270 #define ESAI_TCR_PADC_MASK                       (0x20000U)
44271 #define ESAI_TCR_PADC_SHIFT                      (17U)
44272 /*! PADC - PADC
44273  */
44274 #define ESAI_TCR_PADC(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_PADC_SHIFT)) & ESAI_TCR_PADC_MASK)
44275 #define ESAI_TCR_TPR_MASK                        (0x80000U)
44276 #define ESAI_TCR_TPR_SHIFT                       (19U)
44277 /*! TPR - TPR
44278  */
44279 #define ESAI_TCR_TPR(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TPR_SHIFT)) & ESAI_TCR_TPR_MASK)
44280 #define ESAI_TCR_TEIE_MASK                       (0x100000U)
44281 #define ESAI_TCR_TEIE_SHIFT                      (20U)
44282 /*! TEIE - TEIE
44283  */
44284 #define ESAI_TCR_TEIE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEIE_SHIFT)) & ESAI_TCR_TEIE_MASK)
44285 #define ESAI_TCR_TEDIE_MASK                      (0x200000U)
44286 #define ESAI_TCR_TEDIE_SHIFT                     (21U)
44287 /*! TEDIE - TEDIE
44288  */
44289 #define ESAI_TCR_TEDIE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEDIE_SHIFT)) & ESAI_TCR_TEDIE_MASK)
44290 #define ESAI_TCR_TIE_MASK                        (0x400000U)
44291 #define ESAI_TCR_TIE_SHIFT                       (22U)
44292 /*! TIE - TIE
44293  */
44294 #define ESAI_TCR_TIE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TIE_SHIFT)) & ESAI_TCR_TIE_MASK)
44295 #define ESAI_TCR_TLIE_MASK                       (0x800000U)
44296 #define ESAI_TCR_TLIE_SHIFT                      (23U)
44297 /*! TLIE - TLIE
44298  */
44299 #define ESAI_TCR_TLIE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TLIE_SHIFT)) & ESAI_TCR_TLIE_MASK)
44300 /*! @} */
44301 
44302 /*! @name TCCR - Transmit Clock Control Register */
44303 /*! @{ */
44304 #define ESAI_TCCR_TPM_MASK                       (0xFFU)
44305 #define ESAI_TCCR_TPM_SHIFT                      (0U)
44306 /*! TPM - TPM
44307  */
44308 #define ESAI_TCCR_TPM(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPM_SHIFT)) & ESAI_TCCR_TPM_MASK)
44309 #define ESAI_TCCR_TPSR_MASK                      (0x100U)
44310 #define ESAI_TCCR_TPSR_SHIFT                     (8U)
44311 /*! TPSR - TPSR
44312  */
44313 #define ESAI_TCCR_TPSR(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPSR_SHIFT)) & ESAI_TCCR_TPSR_MASK)
44314 #define ESAI_TCCR_TDC_MASK                       (0x3E00U)
44315 #define ESAI_TCCR_TDC_SHIFT                      (9U)
44316 /*! TDC - TDC
44317  */
44318 #define ESAI_TCCR_TDC(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TDC_SHIFT)) & ESAI_TCCR_TDC_MASK)
44319 #define ESAI_TCCR_TFP_MASK                       (0x3C000U)
44320 #define ESAI_TCCR_TFP_SHIFT                      (14U)
44321 /*! TFP - TFP
44322  */
44323 #define ESAI_TCCR_TFP(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFP_SHIFT)) & ESAI_TCCR_TFP_MASK)
44324 #define ESAI_TCCR_TCKP_MASK                      (0x40000U)
44325 #define ESAI_TCCR_TCKP_SHIFT                     (18U)
44326 /*! TCKP - TCKP
44327  */
44328 #define ESAI_TCCR_TCKP(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKP_SHIFT)) & ESAI_TCCR_TCKP_MASK)
44329 #define ESAI_TCCR_TFSP_MASK                      (0x80000U)
44330 #define ESAI_TCCR_TFSP_SHIFT                     (19U)
44331 /*! TFSP - TFSP
44332  */
44333 #define ESAI_TCCR_TFSP(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSP_SHIFT)) & ESAI_TCCR_TFSP_MASK)
44334 #define ESAI_TCCR_THCKP_MASK                     (0x100000U)
44335 #define ESAI_TCCR_THCKP_SHIFT                    (20U)
44336 /*! THCKP - THCKP
44337  */
44338 #define ESAI_TCCR_THCKP(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKP_SHIFT)) & ESAI_TCCR_THCKP_MASK)
44339 #define ESAI_TCCR_TCKD_MASK                      (0x200000U)
44340 #define ESAI_TCCR_TCKD_SHIFT                     (21U)
44341 /*! TCKD - TCKD
44342  */
44343 #define ESAI_TCCR_TCKD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKD_SHIFT)) & ESAI_TCCR_TCKD_MASK)
44344 #define ESAI_TCCR_TFSD_MASK                      (0x400000U)
44345 #define ESAI_TCCR_TFSD_SHIFT                     (22U)
44346 /*! TFSD - TFSD
44347  */
44348 #define ESAI_TCCR_TFSD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSD_SHIFT)) & ESAI_TCCR_TFSD_MASK)
44349 #define ESAI_TCCR_THCKD_MASK                     (0x800000U)
44350 #define ESAI_TCCR_THCKD_SHIFT                    (23U)
44351 /*! THCKD - THCKD
44352  */
44353 #define ESAI_TCCR_THCKD(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKD_SHIFT)) & ESAI_TCCR_THCKD_MASK)
44354 /*! @} */
44355 
44356 /*! @name RCR - Receive Control Register */
44357 /*! @{ */
44358 #define ESAI_RCR_RE0_MASK                        (0x1U)
44359 #define ESAI_RCR_RE0_SHIFT                       (0U)
44360 /*! RE0 - RE0
44361  */
44362 #define ESAI_RCR_RE0(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE0_SHIFT)) & ESAI_RCR_RE0_MASK)
44363 #define ESAI_RCR_RE1_MASK                        (0x2U)
44364 #define ESAI_RCR_RE1_SHIFT                       (1U)
44365 /*! RE1 - RE1
44366  */
44367 #define ESAI_RCR_RE1(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE1_SHIFT)) & ESAI_RCR_RE1_MASK)
44368 #define ESAI_RCR_RE2_MASK                        (0x4U)
44369 #define ESAI_RCR_RE2_SHIFT                       (2U)
44370 /*! RE2 - RE2
44371  */
44372 #define ESAI_RCR_RE2(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE2_SHIFT)) & ESAI_RCR_RE2_MASK)
44373 #define ESAI_RCR_RE3_MASK                        (0x8U)
44374 #define ESAI_RCR_RE3_SHIFT                       (3U)
44375 /*! RE3 - RE3
44376  */
44377 #define ESAI_RCR_RE3(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE3_SHIFT)) & ESAI_RCR_RE3_MASK)
44378 #define ESAI_RCR_RSHFD_MASK                      (0x40U)
44379 #define ESAI_RCR_RSHFD_SHIFT                     (6U)
44380 /*! RSHFD - RSHFD
44381  */
44382 #define ESAI_RCR_RSHFD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSHFD_SHIFT)) & ESAI_RCR_RSHFD_MASK)
44383 #define ESAI_RCR_RWA_MASK                        (0x80U)
44384 #define ESAI_RCR_RWA_SHIFT                       (7U)
44385 /*! RWA - RWA
44386  */
44387 #define ESAI_RCR_RWA(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RWA_SHIFT)) & ESAI_RCR_RWA_MASK)
44388 #define ESAI_RCR_RMOD_MASK                       (0x300U)
44389 #define ESAI_RCR_RMOD_SHIFT                      (8U)
44390 /*! RMOD - RMOD
44391  */
44392 #define ESAI_RCR_RMOD(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RMOD_SHIFT)) & ESAI_RCR_RMOD_MASK)
44393 #define ESAI_RCR_RSWS_MASK                       (0x7C00U)
44394 #define ESAI_RCR_RSWS_SHIFT                      (10U)
44395 /*! RSWS - RSWS
44396  */
44397 #define ESAI_RCR_RSWS(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSWS_SHIFT)) & ESAI_RCR_RSWS_MASK)
44398 #define ESAI_RCR_RFSL_MASK                       (0x8000U)
44399 #define ESAI_RCR_RFSL_SHIFT                      (15U)
44400 /*! RFSL - RFSL
44401  */
44402 #define ESAI_RCR_RFSL(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSL_SHIFT)) & ESAI_RCR_RFSL_MASK)
44403 #define ESAI_RCR_RFSR_MASK                       (0x10000U)
44404 #define ESAI_RCR_RFSR_SHIFT                      (16U)
44405 /*! RFSR - RFSR
44406  */
44407 #define ESAI_RCR_RFSR(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSR_SHIFT)) & ESAI_RCR_RFSR_MASK)
44408 #define ESAI_RCR_RPR_MASK                        (0x80000U)
44409 #define ESAI_RCR_RPR_SHIFT                       (19U)
44410 /*! RPR - RPR
44411  */
44412 #define ESAI_RCR_RPR(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RPR_SHIFT)) & ESAI_RCR_RPR_MASK)
44413 #define ESAI_RCR_REIE_MASK                       (0x100000U)
44414 #define ESAI_RCR_REIE_SHIFT                      (20U)
44415 /*! REIE - REIE
44416  */
44417 #define ESAI_RCR_REIE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REIE_SHIFT)) & ESAI_RCR_REIE_MASK)
44418 #define ESAI_RCR_REDIE_MASK                      (0x200000U)
44419 #define ESAI_RCR_REDIE_SHIFT                     (21U)
44420 /*! REDIE - REDIE
44421  */
44422 #define ESAI_RCR_REDIE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REDIE_SHIFT)) & ESAI_RCR_REDIE_MASK)
44423 #define ESAI_RCR_RIE_MASK                        (0x400000U)
44424 #define ESAI_RCR_RIE_SHIFT                       (22U)
44425 /*! RIE - RIE
44426  */
44427 #define ESAI_RCR_RIE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RIE_SHIFT)) & ESAI_RCR_RIE_MASK)
44428 #define ESAI_RCR_RLIE_MASK                       (0x800000U)
44429 #define ESAI_RCR_RLIE_SHIFT                      (23U)
44430 /*! RLIE - RLIE
44431  */
44432 #define ESAI_RCR_RLIE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RLIE_SHIFT)) & ESAI_RCR_RLIE_MASK)
44433 /*! @} */
44434 
44435 /*! @name RCCR - Receive Clock Control Register */
44436 /*! @{ */
44437 #define ESAI_RCCR_RPM_MASK                       (0xFFU)
44438 #define ESAI_RCCR_RPM_SHIFT                      (0U)
44439 /*! RPM - RPM
44440  */
44441 #define ESAI_RCCR_RPM(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPM_SHIFT)) & ESAI_RCCR_RPM_MASK)
44442 #define ESAI_RCCR_RPSR_MASK                      (0x100U)
44443 #define ESAI_RCCR_RPSR_SHIFT                     (8U)
44444 /*! RPSR - RPSR
44445  */
44446 #define ESAI_RCCR_RPSR(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPSR_SHIFT)) & ESAI_RCCR_RPSR_MASK)
44447 #define ESAI_RCCR_RDC_MASK                       (0x3E00U)
44448 #define ESAI_RCCR_RDC_SHIFT                      (9U)
44449 /*! RDC - RDC
44450  */
44451 #define ESAI_RCCR_RDC(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RDC_SHIFT)) & ESAI_RCCR_RDC_MASK)
44452 #define ESAI_RCCR_RFP_MASK                       (0x3C000U)
44453 #define ESAI_RCCR_RFP_SHIFT                      (14U)
44454 /*! RFP - RFP
44455  */
44456 #define ESAI_RCCR_RFP(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFP_SHIFT)) & ESAI_RCCR_RFP_MASK)
44457 #define ESAI_RCCR_RCKP_MASK                      (0x40000U)
44458 #define ESAI_RCCR_RCKP_SHIFT                     (18U)
44459 /*! RCKP - RCKP
44460  */
44461 #define ESAI_RCCR_RCKP(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKP_SHIFT)) & ESAI_RCCR_RCKP_MASK)
44462 #define ESAI_RCCR_RFSP_MASK                      (0x80000U)
44463 #define ESAI_RCCR_RFSP_SHIFT                     (19U)
44464 /*! RFSP - RFSP
44465  */
44466 #define ESAI_RCCR_RFSP(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSP_SHIFT)) & ESAI_RCCR_RFSP_MASK)
44467 #define ESAI_RCCR_RHCKP_MASK                     (0x100000U)
44468 #define ESAI_RCCR_RHCKP_SHIFT                    (20U)
44469 /*! RHCKP - RHCKP
44470  */
44471 #define ESAI_RCCR_RHCKP(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKP_SHIFT)) & ESAI_RCCR_RHCKP_MASK)
44472 #define ESAI_RCCR_RCKD_MASK                      (0x200000U)
44473 #define ESAI_RCCR_RCKD_SHIFT                     (21U)
44474 /*! RCKD - RCKD
44475  */
44476 #define ESAI_RCCR_RCKD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKD_SHIFT)) & ESAI_RCCR_RCKD_MASK)
44477 #define ESAI_RCCR_RFSD_MASK                      (0x400000U)
44478 #define ESAI_RCCR_RFSD_SHIFT                     (22U)
44479 /*! RFSD - RFSD
44480  */
44481 #define ESAI_RCCR_RFSD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSD_SHIFT)) & ESAI_RCCR_RFSD_MASK)
44482 #define ESAI_RCCR_RHCKD_MASK                     (0x800000U)
44483 #define ESAI_RCCR_RHCKD_SHIFT                    (23U)
44484 /*! RHCKD - RHCKD
44485  */
44486 #define ESAI_RCCR_RHCKD(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKD_SHIFT)) & ESAI_RCCR_RHCKD_MASK)
44487 /*! @} */
44488 
44489 /*! @name TSMA - Transmit Slot Mask Register A */
44490 /*! @{ */
44491 #define ESAI_TSMA_TS_MASK                        (0xFFFFU)
44492 #define ESAI_TSMA_TS_SHIFT                       (0U)
44493 /*! TS - Lower 16 bits of TS
44494  */
44495 #define ESAI_TSMA_TS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TSMA_TS_SHIFT)) & ESAI_TSMA_TS_MASK)
44496 /*! @} */
44497 
44498 /*! @name TSMB - Transmit Slot Mask Register B */
44499 /*! @{ */
44500 #define ESAI_TSMB_TS_MASK                        (0xFFFFU)
44501 #define ESAI_TSMB_TS_SHIFT                       (0U)
44502 /*! TS - TS
44503  */
44504 #define ESAI_TSMB_TS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TSMB_TS_SHIFT)) & ESAI_TSMB_TS_MASK)
44505 /*! @} */
44506 
44507 /*! @name RSMA - Receive Slot Mask Register A */
44508 /*! @{ */
44509 #define ESAI_RSMA_RS_MASK                        (0xFFFFU)
44510 #define ESAI_RSMA_RS_SHIFT                       (0U)
44511 /*! RS - RS
44512  */
44513 #define ESAI_RSMA_RS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RSMA_RS_SHIFT)) & ESAI_RSMA_RS_MASK)
44514 /*! @} */
44515 
44516 /*! @name RSMB - Receive Slot Mask Register B */
44517 /*! @{ */
44518 #define ESAI_RSMB_RS_MASK                        (0xFFFFU)
44519 #define ESAI_RSMB_RS_SHIFT                       (0U)
44520 /*! RS - RS
44521  */
44522 #define ESAI_RSMB_RS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RSMB_RS_SHIFT)) & ESAI_RSMB_RS_MASK)
44523 /*! @} */
44524 
44525 /*! @name PRRC - Port C Direction Register */
44526 /*! @{ */
44527 #define ESAI_PRRC_PDC_MASK                       (0xFFFU)
44528 #define ESAI_PRRC_PDC_SHIFT                      (0U)
44529 /*! PDC - PDC
44530  */
44531 #define ESAI_PRRC_PDC(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_PRRC_PDC_SHIFT)) & ESAI_PRRC_PDC_MASK)
44532 /*! @} */
44533 
44534 /*! @name PCRC - Port C Control Register */
44535 /*! @{ */
44536 #define ESAI_PCRC_PC_MASK                        (0xFFFU)
44537 #define ESAI_PCRC_PC_SHIFT                       (0U)
44538 /*! PC - PC
44539  */
44540 #define ESAI_PCRC_PC(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_PCRC_PC_SHIFT)) & ESAI_PCRC_PC_MASK)
44541 /*! @} */
44542 
44543 
44544 /*!
44545  * @}
44546  */ /* end of group ESAI_Register_Masks */
44547 
44548 
44549 /* ESAI - Peripheral instance base addresses */
44550 /** Peripheral ADMA__ESAI0 base address */
44551 #define ADMA__ESAI0_BASE                         (0x59010000u)
44552 /** Peripheral ADMA__ESAI0 base pointer */
44553 #define ADMA__ESAI0                              ((ESAI_Type *)ADMA__ESAI0_BASE)
44554 /** Array initializer of ESAI peripheral base addresses */
44555 #define ESAI_BASE_ADDRS                          { ADMA__ESAI0_BASE }
44556 /** Array initializer of ESAI peripheral base pointers */
44557 #define ESAI_BASE_PTRS                           { ADMA__ESAI0 }
44558 /** Interrupt vectors for the ESAI peripheral type */
44559 #define ESAI_IRQS                                { ADMA_ESAI0_INT_IRQn }
44560 
44561 /*!
44562  * @}
44563  */ /* end of group ESAI_Peripheral_Access_Layer */
44564 
44565 
44566 /* ----------------------------------------------------------------------------
44567    -- FLEXSPI Peripheral Access Layer
44568    ---------------------------------------------------------------------------- */
44569 
44570 /*!
44571  * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
44572  * @{
44573  */
44574 
44575 /** FLEXSPI - Register Layout Typedef */
44576 typedef struct {
44577   __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
44578   __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
44579   __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
44580   __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
44581   __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
44582   __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
44583   __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
44584   __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
44585   __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
44586        uint8_t RESERVED_0[32];
44587   __IO uint32_t FLSHCR0[4];                        /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
44588   __IO uint32_t FLSHCR1[4];                        /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
44589   __IO uint32_t FLSHCR2[4];                        /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
44590        uint8_t RESERVED_1[4];
44591   __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
44592        uint8_t RESERVED_2[8];
44593   __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
44594   __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
44595        uint8_t RESERVED_3[8];
44596   __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
44597   __IO uint32_t DLPR;                              /**< Data Learn Pattern Register, offset: 0xB4 */
44598   __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
44599   __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
44600   __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
44601        uint8_t RESERVED_4[24];
44602   __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
44603   __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
44604   __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
44605   __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
44606   __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
44607   __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
44608        uint8_t RESERVED_5[8];
44609   __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
44610   __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
44611   __IO uint32_t LUT[128];                          /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */
44612 } FLEXSPI_Type;
44613 
44614 /* ----------------------------------------------------------------------------
44615    -- FLEXSPI Register Masks
44616    ---------------------------------------------------------------------------- */
44617 
44618 /*!
44619  * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
44620  * @{
44621  */
44622 
44623 /*! @name MCR0 - Module Control Register 0 */
44624 /*! @{ */
44625 #define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
44626 #define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
44627 /*! SWRESET - Software Reset
44628  */
44629 #define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
44630 #define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
44631 #define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
44632 /*! MDIS - Module Disable
44633  */
44634 #define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
44635 #define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
44636 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
44637 /*! RXCLKSRC - Sample Clock source selection for Flash Reading
44638  *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
44639  *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
44640  *  0b10..Reserved
44641  *  0b11..Flash provided Read strobe and input from DQS pad
44642  */
44643 #define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
44644 #define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
44645 #define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
44646 /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
44647  *  0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
44648  *  0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
44649  */
44650 #define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
44651 #define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
44652 #define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
44653 /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
44654  *  0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
44655  *  0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
44656  */
44657 #define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
44658 #define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
44659 #define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
44660 /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI wrapper. Refer Clocks chapter for more details on clocking.
44661  *  0b000..Divided by 1
44662  *  0b001..Divided by 2
44663  *  0b010..Divided by 3
44664  *  0b011..Divided by 4
44665  *  0b100..Divided by 5
44666  *  0b101..Divided by 6
44667  *  0b110..Divided by 7
44668  *  0b111..Divided by 8
44669  */
44670 #define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
44671 #define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
44672 #define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
44673 /*! HSEN - Half Speed Serial Flash access Enable.
44674  *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
44675  *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
44676  */
44677 #define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
44678 #define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
44679 #define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
44680 /*! DOZEEN - Doze mode enable bit
44681  *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
44682  *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
44683  */
44684 #define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
44685 #define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
44686 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
44687 /*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]).
44688  *  0b0..Disable.
44689  *  0b1..Enable.
44690  */
44691 #define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
44692 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
44693 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
44694 /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
44695  *    external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
44696  *    enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
44697  *  0b0..Disable.
44698  *  0b1..Enable.
44699  */
44700 #define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
44701 #define FLEXSPI_MCR0_LEARNEN_MASK                (0x8000U)
44702 #define FLEXSPI_MCR0_LEARNEN_SHIFT               (15U)
44703 /*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is
44704  *    disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction
44705  *    is correctly executed.
44706  *  0b0..Disable.
44707  *  0b1..Enable.
44708  */
44709 #define FLEXSPI_MCR0_LEARNEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)
44710 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
44711 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
44712 /*! IPGRANTWAIT - Time out wait cycle for IP command grant.
44713  */
44714 #define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
44715 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
44716 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
44717 /*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
44718  */
44719 #define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
44720 /*! @} */
44721 
44722 /*! @name MCR1 - Module Control Register 1 */
44723 /*! @{ */
44724 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
44725 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
44726 #define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
44727 #define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
44728 #define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
44729 #define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
44730 /*! @} */
44731 
44732 /*! @name MCR2 - Module Control Register 2 */
44733 /*! @{ */
44734 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
44735 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
44736 /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
44737  *    automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
44738  *    AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
44739  *    mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
44740  *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
44741  *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
44742  */
44743 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
44744 #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
44745 #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
44746 /*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
44747  *    written with 0x1. This bit will be auto-cleared immediately.
44748  */
44749 #define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
44750 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
44751 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
44752 /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
44753  *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
44754  *       A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
44755  *       FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
44756  *       ignored.
44757  *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
44758  */
44759 #define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
44760 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
44761 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
44762 /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
44763  *    A_SCLK). In this case, port B flash access is not available. After changing the value of this
44764  *    field, MCR0[SWRESET] should be set.
44765  *  0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
44766  *  0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
44767  */
44768 #define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
44769 #define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
44770 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
44771 /*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
44772  */
44773 #define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
44774 /*! @} */
44775 
44776 /*! @name AHBCR - AHB Bus Control Register */
44777 /*! @{ */
44778 #define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
44779 #define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
44780 /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
44781  *  0b0..Flash will be accessed in Individual mode.
44782  *  0b1..Flash will be accessed in Parallel mode.
44783  */
44784 #define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
44785 #define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
44786 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
44787 /*! CACHABLEEN - Enable AHB bus cachable read access support.
44788  *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
44789  *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
44790  */
44791 #define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
44792 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
44793 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
44794 /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
44795  *    of AHB write access, refer for more details about AHB bufferable write.
44796  *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
44797  *       ready after all data is transmitted to External device and AHB command finished.
44798  *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
44799  *       granted by arbitrator and will not wait for AHB command finished.
44800  */
44801 #define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
44802 #define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
44803 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
44804 /*! PREFETCHEN - AHB Read Prefetch Enable.
44805  */
44806 #define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
44807 #define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
44808 #define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
44809 /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
44810  *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
44811  *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
44812  *       burst required to meet the alignment requirement.
44813  */
44814 #define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
44815 /*! @} */
44816 
44817 /*! @name INTEN - Interrupt Enable Register */
44818 /*! @{ */
44819 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
44820 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
44821 /*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
44822  */
44823 #define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
44824 #define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
44825 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
44826 /*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
44827  */
44828 #define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
44829 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
44830 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
44831 /*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
44832  */
44833 #define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
44834 #define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
44835 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
44836 /*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
44837  */
44838 #define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
44839 #define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
44840 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
44841 /*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
44842  */
44843 #define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
44844 #define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
44845 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
44846 /*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
44847  */
44848 #define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
44849 #define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
44850 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
44851 /*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
44852  */
44853 #define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
44854 #define FLEXSPI_INTEN_DATALEARNFAILEN_MASK       (0x80U)
44855 #define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT      (7U)
44856 /*! DATALEARNFAILEN - Data Learning failed interrupt enable.
44857  */
44858 #define FLEXSPI_INTEN_DATALEARNFAILEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)
44859 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
44860 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
44861 /*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
44862  */
44863 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
44864 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
44865 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
44866 /*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
44867  */
44868 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
44869 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK       (0x400U)
44870 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT      (10U)
44871 /*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
44872  */
44873 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
44874 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
44875 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
44876 /*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
44877  */
44878 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
44879 /*! @} */
44880 
44881 /*! @name INTR - Interrupt Register */
44882 /*! @{ */
44883 #define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
44884 #define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
44885 /*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
44886  *    generated when there is IPCMDGE or IPCMDERR interrupt generated.
44887  */
44888 #define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
44889 #define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
44890 #define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
44891 /*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
44892  */
44893 #define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
44894 #define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
44895 #define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
44896 /*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
44897  */
44898 #define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
44899 #define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
44900 #define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
44901 /*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
44902  *    IP command, this command will be ignored and not executed at all.
44903  */
44904 #define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
44905 #define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
44906 #define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
44907 /*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
44908  *    AHB command, this command will be ignored and not executed at all.
44909  */
44910 #define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
44911 #define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
44912 #define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
44913 /*! IPRXWA - IP RX FIFO watermark available interrupt.
44914  */
44915 #define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
44916 #define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
44917 #define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
44918 /*! IPTXWE - IP TX FIFO watermark empty interrupt.
44919  */
44920 #define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
44921 #define FLEXSPI_INTR_DATALEARNFAIL_MASK          (0x80U)
44922 #define FLEXSPI_INTR_DATALEARNFAIL_SHIFT         (7U)
44923 /*! DATALEARNFAIL - Data Learning failed interrupt.
44924  */
44925 #define FLEXSPI_INTR_DATALEARNFAIL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)
44926 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
44927 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
44928 /*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
44929  */
44930 #define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
44931 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
44932 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
44933 /*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
44934  */
44935 #define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
44936 #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK          (0x400U)
44937 #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT         (10U)
44938 /*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
44939  */
44940 #define FLEXSPI_INTR_AHBBUSTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
44941 #define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
44942 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
44943 /*! SEQTIMEOUT - Sequence execution timeout interrupt.
44944  */
44945 #define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
44946 /*! @} */
44947 
44948 /*! @name LUTKEY - LUT Key Register */
44949 /*! @{ */
44950 #define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
44951 #define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
44952 /*! KEY - The Key to lock or unlock LUT.
44953  */
44954 #define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
44955 /*! @} */
44956 
44957 /*! @name LUTCR - LUT Control Register */
44958 /*! @{ */
44959 #define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
44960 #define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
44961 /*! LOCK - Lock LUT
44962  */
44963 #define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
44964 #define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
44965 #define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
44966 /*! UNLOCK - Unlock LUT
44967  */
44968 #define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
44969 /*! @} */
44970 
44971 /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
44972 /*! @{ */
44973 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0x1FFU)
44974 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
44975 /*! BUFSZ - AHB RX Buffer Size in 64 bits.
44976  */
44977 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
44978 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
44979 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
44980 /*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
44981  */
44982 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
44983 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
44984 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
44985 /*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned.
44986  */
44987 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
44988 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
44989 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
44990 /*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
44991  */
44992 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
44993 /*! @} */
44994 
44995 /* The count of FLEXSPI_AHBRXBUFCR0 */
44996 #define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)
44997 
44998 /*! @name FLSHCR0 - Flash Control Register 0 */
44999 /*! @{ */
45000 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
45001 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
45002 /*! FLSHSZ - Flash Size in KByte.
45003  */
45004 #define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
45005 /*! @} */
45006 
45007 /* The count of FLEXSPI_FLSHCR0 */
45008 #define FLEXSPI_FLSHCR0_COUNT                    (4U)
45009 
45010 /*! @name FLSHCR1 - Flash Control Register 1 */
45011 /*! @{ */
45012 #define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
45013 #define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
45014 /*! TCSS - Serial Flash CS setup time.
45015  */
45016 #define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
45017 #define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
45018 #define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
45019 /*! TCSH - Serial Flash CS Hold time.
45020  */
45021 #define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
45022 #define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
45023 #define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
45024 /*! WA - Word Addressable.
45025  */
45026 #define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
45027 #define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
45028 #define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
45029 /*! CAS - Column Address Size.
45030  */
45031 #define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
45032 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
45033 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
45034 /*! CSINTERVALUNIT - CS interval unit
45035  *  0b0..The CS interval unit is 1 serial clock cycle
45036  *  0b1..The CS interval unit is 256 serial clock cycle
45037  */
45038 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
45039 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
45040 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
45041 /*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
45042  *    deassertion and flash device Chip selection assertion. If external flash has a limitation on
45043  *    the interval between command sequences, this field should be set accordingly. If there is no
45044  *    limitation, set this field with value 0x0.
45045  */
45046 #define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
45047 /*! @} */
45048 
45049 /* The count of FLEXSPI_FLSHCR1 */
45050 #define FLEXSPI_FLSHCR1_COUNT                    (4U)
45051 
45052 /*! @name FLSHCR2 - Flash Control Register 2 */
45053 /*! @{ */
45054 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0x1FU)
45055 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
45056 /*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
45057  */
45058 #define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
45059 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
45060 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
45061 /*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
45062  */
45063 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
45064 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0x1F00U)
45065 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
45066 /*! AWRSEQID - Sequence Index for AHB Write triggered Command.
45067  */
45068 #define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
45069 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
45070 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
45071 /*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
45072  */
45073 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
45074 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
45075 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
45076 #define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
45077 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
45078 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
45079 /*! AWRWAITUNIT - AWRWAIT unit
45080  *  0b000..The AWRWAIT unit is 2 ahb clock cycle
45081  *  0b001..The AWRWAIT unit is 8 ahb clock cycle
45082  *  0b010..The AWRWAIT unit is 32 ahb clock cycle
45083  *  0b011..The AWRWAIT unit is 128 ahb clock cycle
45084  *  0b100..The AWRWAIT unit is 512 ahb clock cycle
45085  *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
45086  *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
45087  *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
45088  */
45089 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
45090 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
45091 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
45092 /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
45093  *    Refer Programmable Sequence Engine for details.
45094  */
45095 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
45096 /*! @} */
45097 
45098 /* The count of FLEXSPI_FLSHCR2 */
45099 #define FLEXSPI_FLSHCR2_COUNT                    (4U)
45100 
45101 /*! @name FLSHCR4 - Flash Control Register 4 */
45102 /*! @{ */
45103 #define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
45104 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
45105 /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
45106  *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
45107  *       burst start address alignment when flash is accessed in individual mode.
45108  *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
45109  *       burst start address alignment when flash is accessed in individual mode.
45110  */
45111 #define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
45112 #define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
45113 #define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
45114 /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
45115  *    memory device on port A, this bit must be set.
45116  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
45117  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
45118  */
45119 #define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
45120 #define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
45121 #define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
45122 /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
45123  *    memory device on port B, this bit must be set.
45124  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
45125  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
45126  */
45127 #define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
45128 /*! @} */
45129 
45130 /*! @name IPCR0 - IP Control Register 0 */
45131 /*! @{ */
45132 #define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
45133 #define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
45134 /*! SFAR - Serial Flash Address for IP command.
45135  */
45136 #define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
45137 /*! @} */
45138 
45139 /*! @name IPCR1 - IP Control Register 1 */
45140 /*! @{ */
45141 #define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
45142 #define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
45143 /*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
45144  */
45145 #define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
45146 #define FLEXSPI_IPCR1_ISEQID_MASK                (0x1F0000U)
45147 #define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
45148 /*! ISEQID - Sequence Index in LUT for IP command.
45149  */
45150 #define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
45151 #define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
45152 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
45153 /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
45154  */
45155 #define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
45156 #define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
45157 #define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
45158 /*! IPAREN - Parallel mode Enabled for IP command.
45159  *  0b0..Flash will be accessed in Individual mode.
45160  *  0b1..Flash will be accessed in Parallel mode.
45161  */
45162 #define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
45163 /*! @} */
45164 
45165 /*! @name IPCMD - IP Command Register */
45166 /*! @{ */
45167 #define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
45168 #define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
45169 /*! TRG - Setting this bit will trigger an IP Command.
45170  */
45171 #define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
45172 /*! @} */
45173 
45174 /*! @name DLPR - Data Learn Pattern Register */
45175 /*! @{ */
45176 #define FLEXSPI_DLPR_DLP_MASK                    (0xFFFFFFFFU)
45177 #define FLEXSPI_DLPR_DLP_SHIFT                   (0U)
45178 /*! DLP - Data Learning Pattern.
45179  */
45180 #define FLEXSPI_DLPR_DLP(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
45181 /*! @} */
45182 
45183 /*! @name IPRXFCR - IP RX FIFO Control Register */
45184 /*! @{ */
45185 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
45186 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
45187 /*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
45188  */
45189 #define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
45190 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
45191 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
45192 /*! RXDMAEN - IP RX FIFO reading by DMA enabled.
45193  *  0b0..IP RX FIFO would be read by processor.
45194  *  0b1..IP RX FIFO would be read by DMA.
45195  */
45196 #define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
45197 #define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0xFCU)
45198 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
45199 /*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
45200  */
45201 #define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
45202 /*! @} */
45203 
45204 /*! @name IPTXFCR - IP TX FIFO Control Register */
45205 /*! @{ */
45206 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
45207 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
45208 /*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
45209  */
45210 #define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
45211 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
45212 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
45213 /*! TXDMAEN - IP TX FIFO filling by DMA enabled.
45214  *  0b0..IP TX FIFO would be filled by processor.
45215  *  0b1..IP TX FIFO would be filled by DMA.
45216  */
45217 #define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
45218 #define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x1FCU)
45219 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
45220 /*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
45221  */
45222 #define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
45223 /*! @} */
45224 
45225 /*! @name DLLCR - DLL Control Register 0 */
45226 /*! @{ */
45227 #define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
45228 #define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
45229 /*! DLLEN - DLL calibration enable.
45230  */
45231 #define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
45232 #define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
45233 #define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
45234 /*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
45235  *    DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
45236  *    action is edge triggered, so software need to clear this bit after set this bit (no delay
45237  *    limitation).
45238  */
45239 #define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
45240 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
45241 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
45242 /*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock).
45243  */
45244 #define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
45245 #define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
45246 #define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
45247 /*! OVRDEN - Slave clock delay line delay cell number selection override enable.
45248  */
45249 #define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
45250 #define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
45251 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
45252 /*! OVRDVAL - Slave clock delay line delay cell number selection override value.
45253  */
45254 #define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
45255 /*! @} */
45256 
45257 /* The count of FLEXSPI_DLLCR */
45258 #define FLEXSPI_DLLCR_COUNT                      (2U)
45259 
45260 /*! @name STS0 - Status Register 0 */
45261 /*! @{ */
45262 #define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
45263 #define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
45264 /*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
45265  *    sequence executing on FlexSPI interface.
45266  */
45267 #define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
45268 #define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
45269 #define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
45270 /*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
45271  *    sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
45272  *    (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
45273  *    this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
45274  */
45275 #define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
45276 #define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
45277 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
45278 /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
45279  *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
45280  *  0b00..Triggered by AHB read command (triggered by AHB read).
45281  *  0b01..Triggered by AHB write command (triggered by AHB Write).
45282  *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
45283  *  0b11..Triggered by suspended command (resumed).
45284  */
45285 #define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
45286 #define FLEXSPI_STS0_DATALEARNPHASEA_MASK        (0xF0U)
45287 #define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT       (4U)
45288 /*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning.
45289  */
45290 #define FLEXSPI_STS0_DATALEARNPHASEA(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
45291 #define FLEXSPI_STS0_DATALEARNPHASEB_MASK        (0xF00U)
45292 #define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT       (8U)
45293 /*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning.
45294  */
45295 #define FLEXSPI_STS0_DATALEARNPHASEB(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
45296 /*! @} */
45297 
45298 /*! @name STS1 - Status Register 1 */
45299 /*! @{ */
45300 #define FLEXSPI_STS1_AHBCMDERRID_MASK            (0x1FU)
45301 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
45302 /*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
45303  *    will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
45304  */
45305 #define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
45306 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
45307 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
45308 /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
45309  *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
45310  *  0b0000..No error.
45311  *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
45312  *  0b0011..There is unknown instruction opcode in the sequence.
45313  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
45314  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
45315  *  0b1110..Sequence execution timeout.
45316  */
45317 #define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
45318 #define FLEXSPI_STS1_IPCMDERRID_MASK             (0x1F0000U)
45319 #define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
45320 /*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
45321  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
45322  */
45323 #define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
45324 #define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
45325 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
45326 /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
45327  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
45328  *  0b0000..No error.
45329  *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
45330  *  0b0011..There is unknown instruction opcode in the sequence.
45331  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
45332  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
45333  *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
45334  *  0b1110..Sequence execution timeout.
45335  *  0b1111..Flash boundary crossed.
45336  */
45337 #define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
45338 /*! @} */
45339 
45340 /*! @name STS2 - Status Register 2 */
45341 /*! @{ */
45342 #define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
45343 #define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
45344 /*! ASLVLOCK - Flash A sample clock slave delay line locked.
45345  */
45346 #define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
45347 #define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
45348 #define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
45349 /*! AREFLOCK - Flash A sample clock reference delay line locked.
45350  */
45351 #define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
45352 #define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
45353 #define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
45354 /*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
45355  */
45356 #define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
45357 #define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
45358 #define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
45359 /*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
45360  */
45361 #define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
45362 #define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
45363 #define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
45364 /*! BSLVLOCK - Flash B sample clock slave delay line locked.
45365  */
45366 #define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
45367 #define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
45368 #define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
45369 /*! BREFLOCK - Flash B sample clock reference delay line locked.
45370  */
45371 #define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
45372 #define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
45373 #define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
45374 /*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
45375  */
45376 #define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
45377 #define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
45378 #define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
45379 /*! BREFSEL - Flash B sample clock reference delay line delay cell number selection.
45380  */
45381 #define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
45382 /*! @} */
45383 
45384 /*! @name AHBSPNDSTS - AHB Suspend Status Register */
45385 /*! @{ */
45386 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
45387 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
45388 /*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
45389  */
45390 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
45391 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
45392 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
45393 /*! BUFID - AHB RX BUF ID for suspended command sequence.
45394  */
45395 #define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
45396 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
45397 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
45398 /*! DATLFT - Left Data size for suspended command sequence (in byte).
45399  */
45400 #define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
45401 /*! @} */
45402 
45403 /*! @name IPRXFSTS - IP RX FIFO Status Register */
45404 /*! @{ */
45405 #define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
45406 #define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
45407 /*! FILL - Fill level of IP RX FIFO.
45408  */
45409 #define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
45410 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
45411 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
45412 /*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
45413  */
45414 #define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
45415 /*! @} */
45416 
45417 /*! @name IPTXFSTS - IP TX FIFO Status Register */
45418 /*! @{ */
45419 #define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
45420 #define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
45421 /*! FILL - Fill level of IP TX FIFO.
45422  */
45423 #define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
45424 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
45425 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
45426 /*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
45427  */
45428 #define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
45429 /*! @} */
45430 
45431 /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
45432 /*! @{ */
45433 #define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
45434 #define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
45435 /*! RXDATA - RX Data
45436  */
45437 #define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
45438 /*! @} */
45439 
45440 /* The count of FLEXSPI_RFDR */
45441 #define FLEXSPI_RFDR_COUNT                       (32U)
45442 
45443 /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
45444 /*! @{ */
45445 #define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
45446 #define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
45447 /*! TXDATA - TX Data
45448  */
45449 #define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
45450 /*! @} */
45451 
45452 /* The count of FLEXSPI_TFDR */
45453 #define FLEXSPI_TFDR_COUNT                       (32U)
45454 
45455 /*! @name LUT - LUT 0..LUT 127 */
45456 /*! @{ */
45457 #define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
45458 #define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
45459 /*! OPERAND0 - OPERAND0
45460  */
45461 #define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
45462 #define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
45463 #define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
45464 /*! NUM_PADS0 - NUM_PADS0
45465  */
45466 #define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
45467 #define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
45468 #define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
45469 /*! OPCODE0 - OPCODE
45470  */
45471 #define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
45472 #define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
45473 #define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
45474 /*! OPERAND1 - OPERAND1
45475  */
45476 #define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
45477 #define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
45478 #define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
45479 /*! NUM_PADS1 - NUM_PADS1
45480  */
45481 #define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
45482 #define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
45483 #define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
45484 /*! OPCODE1 - OPCODE1
45485  */
45486 #define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
45487 /*! @} */
45488 
45489 /* The count of FLEXSPI_LUT */
45490 #define FLEXSPI_LUT_COUNT                        (128U)
45491 
45492 
45493 /*!
45494  * @}
45495  */ /* end of group FLEXSPI_Register_Masks */
45496 
45497 
45498 /* FLEXSPI - Peripheral instance base addresses */
45499 /** Peripheral LSIO__FLEXSPI0 base address */
45500 #define LSIO__FLEXSPI0_BASE                      (0x5D120000u)
45501 /** Peripheral LSIO__FLEXSPI0 base pointer */
45502 #define LSIO__FLEXSPI0                           ((FLEXSPI_Type *)LSIO__FLEXSPI0_BASE)
45503 /** Peripheral LSIO__FLEXSPI1 base address */
45504 #define LSIO__FLEXSPI1_BASE                      (0x5D130000u)
45505 /** Peripheral LSIO__FLEXSPI1 base pointer */
45506 #define LSIO__FLEXSPI1                           ((FLEXSPI_Type *)LSIO__FLEXSPI1_BASE)
45507 /** Array initializer of FLEXSPI peripheral base addresses */
45508 #define FLEXSPI_BASE_ADDRS                       { LSIO__FLEXSPI0_BASE, LSIO__FLEXSPI1_BASE }
45509 /** Array initializer of FLEXSPI peripheral base pointers */
45510 #define FLEXSPI_BASE_PTRS                        { LSIO__FLEXSPI0, LSIO__FLEXSPI1 }
45511 /** Interrupt vectors for the FLEXSPI peripheral type */
45512 #define FLEXSPI_IRQS                             { LSIO_OCTASPI0_INT_IRQn, LSIO_OCTASPI1_INT_IRQn }
45513 /* FlexSPI0 AMBA address. */
45514 #define FlexSPI0_AMBA_BASE                       (0x08000000U)
45515 
45516 
45517 /*!
45518  * @}
45519  */ /* end of group FLEXSPI_Peripheral_Access_Layer */
45520 
45521 
45522 /* ----------------------------------------------------------------------------
45523    -- FTM Peripheral Access Layer
45524    ---------------------------------------------------------------------------- */
45525 
45526 /*!
45527  * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
45528  * @{
45529  */
45530 
45531 /** FTM - Register Layout Typedef */
45532 typedef struct {
45533   __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
45534   __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
45535   __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
45536   struct {                                         /* offset: 0xC, array step: 0x8 */
45537     __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
45538     __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
45539   } CONTROLS[8];
45540   __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
45541   __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
45542   __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
45543   __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
45544   __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
45545   __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
45546   __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
45547   __IO uint32_t DEADTIME;                          /**< Deadtime Configuration, offset: 0x68 */
45548   __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
45549   __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
45550   __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
45551   __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
45552   __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
45553   __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
45554   __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
45555   __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
45556   __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
45557   __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
45558   __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
45559   __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
45560   __IO uint32_t HCR;                               /**< Half Cycle Register, offset: 0x9C */
45561        uint8_t RESERVED_0[352];
45562   __IO uint32_t MOD_MIRROR;                        /**< Mirror of Modulo Value, offset: 0x200 */
45563   __IO uint32_t CV_MIRROR[8];                      /**< Mirror of Channel (n) Match Value, array offset: 0x204, array step: 0x4 */
45564 } FTM_Type;
45565 
45566 /* ----------------------------------------------------------------------------
45567    -- FTM Register Masks
45568    ---------------------------------------------------------------------------- */
45569 
45570 /*!
45571  * @addtogroup FTM_Register_Masks FTM Register Masks
45572  * @{
45573  */
45574 
45575 /*! @name SC - Status And Control */
45576 /*! @{ */
45577 #define FTM_SC_PS_MASK                           (0x7U)
45578 #define FTM_SC_PS_SHIFT                          (0U)
45579 /*! PS - Prescale Factor Selection
45580  *  0b000..Divide by 1
45581  *  0b001..Divide by 2
45582  *  0b010..Divide by 4
45583  *  0b011..Divide by 8
45584  *  0b100..Divide by 16
45585  *  0b101..Divide by 32
45586  *  0b110..Divide by 64
45587  *  0b111..Divide by 128
45588  */
45589 #define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
45590 #define FTM_SC_CLKS_MASK                         (0x18U)
45591 #define FTM_SC_CLKS_SHIFT                        (3U)
45592 /*! CLKS - Clock Source Selection
45593  *  0b00..No clock selected. This in effect disables the FTM counter.
45594  *  0b01..FTM input clock
45595  *  0b10..Fixed frequency clock
45596  *  0b11..External clock
45597  */
45598 #define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
45599 #define FTM_SC_CPWMS_MASK                        (0x20U)
45600 #define FTM_SC_CPWMS_SHIFT                       (5U)
45601 /*! CPWMS - Center-Aligned PWM Select
45602  *  0b0..FTM counter operates in Up Counting mode.
45603  *  0b1..FTM counter operates in Up-Down Counting mode.
45604  */
45605 #define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
45606 #define FTM_SC_RIE_MASK                          (0x40U)
45607 #define FTM_SC_RIE_SHIFT                         (6U)
45608 /*! RIE - Reload Point Interrupt Enable
45609  *  0b0..Reload point interrupt is disabled.
45610  *  0b1..Reload point interrupt is enabled.
45611  */
45612 #define FTM_SC_RIE(x)                            (((uint32_t)(((uint32_t)(x)) << FTM_SC_RIE_SHIFT)) & FTM_SC_RIE_MASK)
45613 #define FTM_SC_RF_MASK                           (0x80U)
45614 #define FTM_SC_RF_SHIFT                          (7U)
45615 /*! RF - Reload Flag
45616  *  0b0..A selected reload point did not happen.
45617  *  0b1..A selected reload point happened.
45618  */
45619 #define FTM_SC_RF(x)                             (((uint32_t)(((uint32_t)(x)) << FTM_SC_RF_SHIFT)) & FTM_SC_RF_MASK)
45620 #define FTM_SC_TOIE_MASK                         (0x100U)
45621 #define FTM_SC_TOIE_SHIFT                        (8U)
45622 /*! TOIE - Timer Overflow Interrupt Enable
45623  *  0b0..Disable TOF interrupts. Use software polling.
45624  *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
45625  */
45626 #define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
45627 #define FTM_SC_TOF_MASK                          (0x200U)
45628 #define FTM_SC_TOF_SHIFT                         (9U)
45629 /*! TOF - Timer Overflow Flag
45630  *  0b0..FTM counter has not overflowed.
45631  *  0b1..FTM counter has overflowed.
45632  */
45633 #define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
45634 #define FTM_SC_PWMEN0_MASK                       (0x10000U)
45635 #define FTM_SC_PWMEN0_SHIFT                      (16U)
45636 /*! PWMEN0 - Channel 0 PWM enable bit
45637  *  0b0..Channel output port is disabled.
45638  *  0b1..Channel output port is enabled.
45639  */
45640 #define FTM_SC_PWMEN0(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN0_SHIFT)) & FTM_SC_PWMEN0_MASK)
45641 #define FTM_SC_PWMEN1_MASK                       (0x20000U)
45642 #define FTM_SC_PWMEN1_SHIFT                      (17U)
45643 /*! PWMEN1 - Channel 1 PWM enable bit
45644  *  0b0..Channel output port is disabled.
45645  *  0b1..Channel output port is enabled.
45646  */
45647 #define FTM_SC_PWMEN1(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN1_SHIFT)) & FTM_SC_PWMEN1_MASK)
45648 #define FTM_SC_PWMEN2_MASK                       (0x40000U)
45649 #define FTM_SC_PWMEN2_SHIFT                      (18U)
45650 /*! PWMEN2 - Channel 2 PWM enable bit
45651  *  0b0..Channel output port is disabled.
45652  *  0b1..Channel output port is enabled.
45653  */
45654 #define FTM_SC_PWMEN2(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN2_SHIFT)) & FTM_SC_PWMEN2_MASK)
45655 #define FTM_SC_PWMEN3_MASK                       (0x80000U)
45656 #define FTM_SC_PWMEN3_SHIFT                      (19U)
45657 /*! PWMEN3 - Channel 3 PWM enable bit
45658  *  0b0..Channel output port is disabled.
45659  *  0b1..Channel output port is enabled.
45660  */
45661 #define FTM_SC_PWMEN3(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN3_SHIFT)) & FTM_SC_PWMEN3_MASK)
45662 #define FTM_SC_PWMEN4_MASK                       (0x100000U)
45663 #define FTM_SC_PWMEN4_SHIFT                      (20U)
45664 /*! PWMEN4 - Channel 4 PWM enable bit
45665  *  0b0..Channel output port is disabled.
45666  *  0b1..Channel output port is enabled.
45667  */
45668 #define FTM_SC_PWMEN4(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN4_SHIFT)) & FTM_SC_PWMEN4_MASK)
45669 #define FTM_SC_PWMEN5_MASK                       (0x200000U)
45670 #define FTM_SC_PWMEN5_SHIFT                      (21U)
45671 /*! PWMEN5 - Channel 5 PWM enable bit
45672  *  0b0..Channel output port is disabled.
45673  *  0b1..Channel output port is enabled.
45674  */
45675 #define FTM_SC_PWMEN5(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN5_SHIFT)) & FTM_SC_PWMEN5_MASK)
45676 #define FTM_SC_PWMEN6_MASK                       (0x400000U)
45677 #define FTM_SC_PWMEN6_SHIFT                      (22U)
45678 /*! PWMEN6 - Channel 6 PWM enable bit
45679  *  0b0..Channel output port is disabled.
45680  *  0b1..Channel output port is enabled.
45681  */
45682 #define FTM_SC_PWMEN6(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN6_SHIFT)) & FTM_SC_PWMEN6_MASK)
45683 #define FTM_SC_PWMEN7_MASK                       (0x800000U)
45684 #define FTM_SC_PWMEN7_SHIFT                      (23U)
45685 /*! PWMEN7 - Channel 7 PWM enable bit
45686  *  0b0..Channel output port is disabled.
45687  *  0b1..Channel output port is enabled.
45688  */
45689 #define FTM_SC_PWMEN7(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN7_SHIFT)) & FTM_SC_PWMEN7_MASK)
45690 #define FTM_SC_FLTPS_MASK                        (0xF000000U)
45691 #define FTM_SC_FLTPS_SHIFT                       (24U)
45692 /*! FLTPS - Filter Prescaler
45693  *  0b0000..Divide by 1
45694  *  0b0001..Divide by 2
45695  *  0b0010..Divide by 3
45696  *  0b0011..Divide by 4
45697  *  0b0100..Divide by 5
45698  *  0b0101..Divide by 6
45699  *  0b0110..Divide by 7
45700  *  0b0111..Divide by 8
45701  *  0b1000..Divide by 9
45702  *  0b1001..Divide by 10
45703  *  0b1010..Divide by 11
45704  *  0b1011..Divide by 12
45705  *  0b1100..Divide by 13
45706  *  0b1101..Divide by 14
45707  *  0b1110..Divide by 15
45708  *  0b1111..Divide by 16
45709  */
45710 #define FTM_SC_FLTPS(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_SC_FLTPS_SHIFT)) & FTM_SC_FLTPS_MASK)
45711 /*! @} */
45712 
45713 /*! @name CNT - Counter */
45714 /*! @{ */
45715 #define FTM_CNT_COUNT_MASK                       (0xFFFFU)
45716 #define FTM_CNT_COUNT_SHIFT                      (0U)
45717 /*! COUNT - Counter Value
45718  */
45719 #define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
45720 /*! @} */
45721 
45722 /*! @name MOD - Modulo */
45723 /*! @{ */
45724 #define FTM_MOD_MOD_MASK                         (0xFFFFU)
45725 #define FTM_MOD_MOD_SHIFT                        (0U)
45726 /*! MOD - MOD
45727  */
45728 #define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
45729 /*! @} */
45730 
45731 /*! @name CnSC - Channel (n) Status And Control */
45732 /*! @{ */
45733 #define FTM_CnSC_DMA_MASK                        (0x1U)
45734 #define FTM_CnSC_DMA_SHIFT                       (0U)
45735 /*! DMA - DMA Enable
45736  *  0b0..Disable DMA transfers.
45737  *  0b1..Enable DMA transfers.
45738  */
45739 #define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
45740 #define FTM_CnSC_ICRST_MASK                      (0x2U)
45741 #define FTM_CnSC_ICRST_SHIFT                     (1U)
45742 /*! ICRST - FTM counter reset by the selected input capture event.
45743  *  0b0..FTM counter is not reset when the selected channel (n) input event is detected.
45744  *  0b1..FTM counter is reset when the selected channel (n) input event is detected.
45745  */
45746 #define FTM_CnSC_ICRST(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
45747 #define FTM_CnSC_ELSA_MASK                       (0x4U)
45748 #define FTM_CnSC_ELSA_SHIFT                      (2U)
45749 /*! ELSA - Channel (n) Edge or Level Select
45750  */
45751 #define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
45752 #define FTM_CnSC_ELSB_MASK                       (0x8U)
45753 #define FTM_CnSC_ELSB_SHIFT                      (3U)
45754 /*! ELSB - Channel (n) Edge or Level Select
45755  */
45756 #define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
45757 #define FTM_CnSC_MSA_MASK                        (0x10U)
45758 #define FTM_CnSC_MSA_SHIFT                       (4U)
45759 /*! MSA - Channel (n) Mode Select
45760  */
45761 #define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
45762 #define FTM_CnSC_MSB_MASK                        (0x20U)
45763 #define FTM_CnSC_MSB_SHIFT                       (5U)
45764 /*! MSB - Channel (n) Mode Select
45765  */
45766 #define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
45767 #define FTM_CnSC_CHIE_MASK                       (0x40U)
45768 #define FTM_CnSC_CHIE_SHIFT                      (6U)
45769 /*! CHIE - Channel (n) Interrupt Enable
45770  *  0b0..Disable channel (n) interrupt. Use software polling.
45771  *  0b1..Enable channel (n) interrupt.
45772  */
45773 #define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
45774 #define FTM_CnSC_CHF_MASK                        (0x80U)
45775 #define FTM_CnSC_CHF_SHIFT                       (7U)
45776 /*! CHF - Channel (n) Flag
45777  *  0b0..No channel (n) event has occurred.
45778  *  0b1..A channel (n) event has occurred.
45779  */
45780 #define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
45781 #define FTM_CnSC_TRIGMODE_MASK                   (0x100U)
45782 #define FTM_CnSC_TRIGMODE_SHIFT                  (8U)
45783 /*! TRIGMODE - Trigger mode control
45784  *  0b0..Channel outputs will generate the normal PWM outputs without generating a pulse.
45785  *  0b1..If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
45786  */
45787 #define FTM_CnSC_TRIGMODE(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_TRIGMODE_SHIFT)) & FTM_CnSC_TRIGMODE_MASK)
45788 #define FTM_CnSC_CHIS_MASK                       (0x200U)
45789 #define FTM_CnSC_CHIS_SHIFT                      (9U)
45790 /*! CHIS - Channel (n) Input State
45791  *  0b0..The channel (n) input is zero.
45792  *  0b1..The channel (n) input is one.
45793  */
45794 #define FTM_CnSC_CHIS(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIS_SHIFT)) & FTM_CnSC_CHIS_MASK)
45795 #define FTM_CnSC_CHOV_MASK                       (0x400U)
45796 #define FTM_CnSC_CHOV_SHIFT                      (10U)
45797 /*! CHOV - Channel (n) Output Value
45798  *  0b0..The channel (n) output is zero.
45799  *  0b1..The channel (n) output is one.
45800  */
45801 #define FTM_CnSC_CHOV(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHOV_SHIFT)) & FTM_CnSC_CHOV_MASK)
45802 /*! @} */
45803 
45804 /* The count of FTM_CnSC */
45805 #define FTM_CnSC_COUNT                           (8U)
45806 
45807 /*! @name CnV - Channel (n) Value */
45808 /*! @{ */
45809 #define FTM_CnV_VAL_MASK                         (0xFFFFU)
45810 #define FTM_CnV_VAL_SHIFT                        (0U)
45811 /*! VAL - Channel Value
45812  */
45813 #define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
45814 /*! @} */
45815 
45816 /* The count of FTM_CnV */
45817 #define FTM_CnV_COUNT                            (8U)
45818 
45819 /*! @name CNTIN - Counter Initial Value */
45820 /*! @{ */
45821 #define FTM_CNTIN_INIT_MASK                      (0xFFFFU)
45822 #define FTM_CNTIN_INIT_SHIFT                     (0U)
45823 /*! INIT - INIT
45824  */
45825 #define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
45826 /*! @} */
45827 
45828 /*! @name STATUS - Capture And Compare Status */
45829 /*! @{ */
45830 #define FTM_STATUS_CH0F_MASK                     (0x1U)
45831 #define FTM_STATUS_CH0F_SHIFT                    (0U)
45832 /*! CH0F - Channel 0 Flag
45833  *  0b0..No channel event has occurred.
45834  *  0b1..A channel event has occurred.
45835  */
45836 #define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
45837 #define FTM_STATUS_CH1F_MASK                     (0x2U)
45838 #define FTM_STATUS_CH1F_SHIFT                    (1U)
45839 /*! CH1F - Channel 1 Flag
45840  *  0b0..No channel event has occurred.
45841  *  0b1..A channel event has occurred.
45842  */
45843 #define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
45844 #define FTM_STATUS_CH2F_MASK                     (0x4U)
45845 #define FTM_STATUS_CH2F_SHIFT                    (2U)
45846 /*! CH2F - Channel 2 Flag
45847  *  0b0..No channel event has occurred.
45848  *  0b1..A channel event has occurred.
45849  */
45850 #define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
45851 #define FTM_STATUS_CH3F_MASK                     (0x8U)
45852 #define FTM_STATUS_CH3F_SHIFT                    (3U)
45853 /*! CH3F - Channel 3 Flag
45854  *  0b0..No channel event has occurred.
45855  *  0b1..A channel event has occurred.
45856  */
45857 #define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
45858 #define FTM_STATUS_CH4F_MASK                     (0x10U)
45859 #define FTM_STATUS_CH4F_SHIFT                    (4U)
45860 /*! CH4F - Channel 4 Flag
45861  *  0b0..No channel event has occurred.
45862  *  0b1..A channel event has occurred.
45863  */
45864 #define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
45865 #define FTM_STATUS_CH5F_MASK                     (0x20U)
45866 #define FTM_STATUS_CH5F_SHIFT                    (5U)
45867 /*! CH5F - Channel 5 Flag
45868  *  0b0..No channel event has occurred.
45869  *  0b1..A channel event has occurred.
45870  */
45871 #define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
45872 #define FTM_STATUS_CH6F_MASK                     (0x40U)
45873 #define FTM_STATUS_CH6F_SHIFT                    (6U)
45874 /*! CH6F - Channel 6 Flag
45875  *  0b0..No channel event has occurred.
45876  *  0b1..A channel event has occurred.
45877  */
45878 #define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
45879 #define FTM_STATUS_CH7F_MASK                     (0x80U)
45880 #define FTM_STATUS_CH7F_SHIFT                    (7U)
45881 /*! CH7F - Channel 7 Flag
45882  *  0b0..No channel event has occurred.
45883  *  0b1..A channel event has occurred.
45884  */
45885 #define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
45886 /*! @} */
45887 
45888 /*! @name MODE - Features Mode Selection */
45889 /*! @{ */
45890 #define FTM_MODE_FTMEN_MASK                      (0x1U)
45891 #define FTM_MODE_FTMEN_SHIFT                     (0U)
45892 /*! FTMEN - FTM Enable
45893  *  0b0..TPM compatibility. Free running counter and synchronization compatible with TPM.
45894  *  0b1..Free running counter and synchronization are different from TPM behavior.
45895  */
45896 #define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
45897 #define FTM_MODE_INIT_MASK                       (0x2U)
45898 #define FTM_MODE_INIT_SHIFT                      (1U)
45899 /*! INIT - Initialize The Channels Output
45900  */
45901 #define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
45902 #define FTM_MODE_WPDIS_MASK                      (0x4U)
45903 #define FTM_MODE_WPDIS_SHIFT                     (2U)
45904 /*! WPDIS - Write Protection Disable
45905  *  0b0..Write protection is enabled.
45906  *  0b1..Write protection is disabled.
45907  */
45908 #define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
45909 #define FTM_MODE_PWMSYNC_MASK                    (0x8U)
45910 #define FTM_MODE_PWMSYNC_SHIFT                   (3U)
45911 /*! PWMSYNC - PWM Synchronization Mode
45912  *  0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
45913  *  0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used
45914  *       by OUTMASK and FTM counter synchronization.
45915  */
45916 #define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
45917 #define FTM_MODE_CAPTEST_MASK                    (0x10U)
45918 #define FTM_MODE_CAPTEST_SHIFT                   (4U)
45919 /*! CAPTEST - Capture Test Mode Enable
45920  *  0b0..Capture test mode is disabled.
45921  *  0b1..Capture test mode is enabled.
45922  */
45923 #define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
45924 #define FTM_MODE_FAULTM_MASK                     (0x60U)
45925 #define FTM_MODE_FAULTM_SHIFT                    (5U)
45926 /*! FAULTM - Fault Control Mode
45927  *  0b00..Fault control is disabled for all channels.
45928  *  0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
45929  *  0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
45930  *  0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
45931  */
45932 #define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
45933 #define FTM_MODE_FAULTIE_MASK                    (0x80U)
45934 #define FTM_MODE_FAULTIE_SHIFT                   (7U)
45935 /*! FAULTIE - Fault Interrupt Enable
45936  *  0b0..Fault control interrupt is disabled.
45937  *  0b1..Fault control interrupt is enabled.
45938  */
45939 #define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
45940 /*! @} */
45941 
45942 /*! @name SYNC - Synchronization */
45943 /*! @{ */
45944 #define FTM_SYNC_CNTMIN_MASK                     (0x1U)
45945 #define FTM_SYNC_CNTMIN_SHIFT                    (0U)
45946 /*! CNTMIN - Minimum Loading Point Enable
45947  *  0b0..The minimum loading point is disabled.
45948  *  0b1..The minimum loading point is enabled.
45949  */
45950 #define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
45951 #define FTM_SYNC_CNTMAX_MASK                     (0x2U)
45952 #define FTM_SYNC_CNTMAX_SHIFT                    (1U)
45953 /*! CNTMAX - Maximum Loading Point Enable
45954  *  0b0..The maximum loading point is disabled.
45955  *  0b1..The maximum loading point is enabled.
45956  */
45957 #define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
45958 #define FTM_SYNC_REINIT_MASK                     (0x4U)
45959 #define FTM_SYNC_REINIT_SHIFT                    (2U)
45960 /*! REINIT - FTM Counter Reinitialization by Synchronization
45961  *  0b0..FTM counter continues to count normally.
45962  *  0b1..FTM counter is updated with its initial value when the selected trigger is detected.
45963  */
45964 #define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
45965 #define FTM_SYNC_SYNCHOM_MASK                    (0x8U)
45966 #define FTM_SYNC_SYNCHOM_SHIFT                   (3U)
45967 /*! SYNCHOM - Output Mask Synchronization
45968  *  0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock.
45969  *  0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
45970  */
45971 #define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
45972 #define FTM_SYNC_TRIG0_MASK                      (0x10U)
45973 #define FTM_SYNC_TRIG0_SHIFT                     (4U)
45974 /*! TRIG0 - PWM Synchronization Hardware Trigger 0
45975  *  0b0..Trigger is disabled.
45976  *  0b1..Trigger is enabled.
45977  */
45978 #define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
45979 #define FTM_SYNC_TRIG1_MASK                      (0x20U)
45980 #define FTM_SYNC_TRIG1_SHIFT                     (5U)
45981 /*! TRIG1 - PWM Synchronization Hardware Trigger 1
45982  *  0b0..Trigger is disabled.
45983  *  0b1..Trigger is enabled.
45984  */
45985 #define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
45986 #define FTM_SYNC_TRIG2_MASK                      (0x40U)
45987 #define FTM_SYNC_TRIG2_SHIFT                     (6U)
45988 /*! TRIG2 - PWM Synchronization Hardware Trigger 2
45989  *  0b0..Trigger is disabled.
45990  *  0b1..Trigger is enabled.
45991  */
45992 #define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
45993 #define FTM_SYNC_SWSYNC_MASK                     (0x80U)
45994 #define FTM_SYNC_SWSYNC_SHIFT                    (7U)
45995 /*! SWSYNC - PWM Synchronization Software Trigger
45996  *  0b0..Software trigger is not selected.
45997  *  0b1..Software trigger is selected.
45998  */
45999 #define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
46000 /*! @} */
46001 
46002 /*! @name OUTINIT - Initial State For Channels Output */
46003 /*! @{ */
46004 #define FTM_OUTINIT_CH0OI_MASK                   (0x1U)
46005 #define FTM_OUTINIT_CH0OI_SHIFT                  (0U)
46006 /*! CH0OI - Channel 0 Output Initialization Value
46007  *  0b0..The initialization value is 0.
46008  *  0b1..The initialization value is 1.
46009  */
46010 #define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
46011 #define FTM_OUTINIT_CH1OI_MASK                   (0x2U)
46012 #define FTM_OUTINIT_CH1OI_SHIFT                  (1U)
46013 /*! CH1OI - Channel 1 Output Initialization Value
46014  *  0b0..The initialization value is 0.
46015  *  0b1..The initialization value is 1.
46016  */
46017 #define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
46018 #define FTM_OUTINIT_CH2OI_MASK                   (0x4U)
46019 #define FTM_OUTINIT_CH2OI_SHIFT                  (2U)
46020 /*! CH2OI - Channel 2 Output Initialization Value
46021  *  0b0..The initialization value is 0.
46022  *  0b1..The initialization value is 1.
46023  */
46024 #define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
46025 #define FTM_OUTINIT_CH3OI_MASK                   (0x8U)
46026 #define FTM_OUTINIT_CH3OI_SHIFT                  (3U)
46027 /*! CH3OI - Channel 3 Output Initialization Value
46028  *  0b0..The initialization value is 0.
46029  *  0b1..The initialization value is 1.
46030  */
46031 #define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
46032 #define FTM_OUTINIT_CH4OI_MASK                   (0x10U)
46033 #define FTM_OUTINIT_CH4OI_SHIFT                  (4U)
46034 /*! CH4OI - Channel 4 Output Initialization Value
46035  *  0b0..The initialization value is 0.
46036  *  0b1..The initialization value is 1.
46037  */
46038 #define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
46039 #define FTM_OUTINIT_CH5OI_MASK                   (0x20U)
46040 #define FTM_OUTINIT_CH5OI_SHIFT                  (5U)
46041 /*! CH5OI - Channel 5 Output Initialization Value
46042  *  0b0..The initialization value is 0.
46043  *  0b1..The initialization value is 1.
46044  */
46045 #define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
46046 #define FTM_OUTINIT_CH6OI_MASK                   (0x40U)
46047 #define FTM_OUTINIT_CH6OI_SHIFT                  (6U)
46048 /*! CH6OI - Channel 6 Output Initialization Value
46049  *  0b0..The initialization value is 0.
46050  *  0b1..The initialization value is 1.
46051  */
46052 #define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
46053 #define FTM_OUTINIT_CH7OI_MASK                   (0x80U)
46054 #define FTM_OUTINIT_CH7OI_SHIFT                  (7U)
46055 /*! CH7OI - Channel 7 Output Initialization Value
46056  *  0b0..The initialization value is 0.
46057  *  0b1..The initialization value is 1.
46058  */
46059 #define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
46060 /*! @} */
46061 
46062 /*! @name OUTMASK - Output Mask */
46063 /*! @{ */
46064 #define FTM_OUTMASK_CH0OM_MASK                   (0x1U)
46065 #define FTM_OUTMASK_CH0OM_SHIFT                  (0U)
46066 /*! CH0OM - Channel 0 Output Mask
46067  *  0b0..Channel output is not masked. It continues to operate normally.
46068  *  0b1..Channel output is masked. It is forced to its inactive state.
46069  */
46070 #define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
46071 #define FTM_OUTMASK_CH1OM_MASK                   (0x2U)
46072 #define FTM_OUTMASK_CH1OM_SHIFT                  (1U)
46073 /*! CH1OM - Channel 1 Output Mask
46074  *  0b0..Channel output is not masked. It continues to operate normally.
46075  *  0b1..Channel output is masked. It is forced to its inactive state.
46076  */
46077 #define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
46078 #define FTM_OUTMASK_CH2OM_MASK                   (0x4U)
46079 #define FTM_OUTMASK_CH2OM_SHIFT                  (2U)
46080 /*! CH2OM - Channel 2 Output Mask
46081  *  0b0..Channel output is not masked. It continues to operate normally.
46082  *  0b1..Channel output is masked. It is forced to its inactive state.
46083  */
46084 #define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
46085 #define FTM_OUTMASK_CH3OM_MASK                   (0x8U)
46086 #define FTM_OUTMASK_CH3OM_SHIFT                  (3U)
46087 /*! CH3OM - Channel 3 Output Mask
46088  *  0b0..Channel output is not masked. It continues to operate normally.
46089  *  0b1..Channel output is masked. It is forced to its inactive state.
46090  */
46091 #define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
46092 #define FTM_OUTMASK_CH4OM_MASK                   (0x10U)
46093 #define FTM_OUTMASK_CH4OM_SHIFT                  (4U)
46094 /*! CH4OM - Channel 4 Output Mask
46095  *  0b0..Channel output is not masked. It continues to operate normally.
46096  *  0b1..Channel output is masked. It is forced to its inactive state.
46097  */
46098 #define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
46099 #define FTM_OUTMASK_CH5OM_MASK                   (0x20U)
46100 #define FTM_OUTMASK_CH5OM_SHIFT                  (5U)
46101 /*! CH5OM - Channel 5 Output Mask
46102  *  0b0..Channel output is not masked. It continues to operate normally.
46103  *  0b1..Channel output is masked. It is forced to its inactive state.
46104  */
46105 #define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
46106 #define FTM_OUTMASK_CH6OM_MASK                   (0x40U)
46107 #define FTM_OUTMASK_CH6OM_SHIFT                  (6U)
46108 /*! CH6OM - Channel 6 Output Mask
46109  *  0b0..Channel output is not masked. It continues to operate normally.
46110  *  0b1..Channel output is masked. It is forced to its inactive state.
46111  */
46112 #define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
46113 #define FTM_OUTMASK_CH7OM_MASK                   (0x80U)
46114 #define FTM_OUTMASK_CH7OM_SHIFT                  (7U)
46115 /*! CH7OM - Channel 7 Output Mask
46116  *  0b0..Channel output is not masked. It continues to operate normally.
46117  *  0b1..Channel output is masked. It is forced to its inactive state.
46118  */
46119 #define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
46120 /*! @} */
46121 
46122 /*! @name COMBINE - Function For Linked Channels */
46123 /*! @{ */
46124 #define FTM_COMBINE_COMBINE0_MASK                (0x1U)
46125 #define FTM_COMBINE_COMBINE0_SHIFT               (0U)
46126 /*! COMBINE0 - Combine Channels For n = 0
46127  */
46128 #define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
46129 #define FTM_COMBINE_COMP0_MASK                   (0x2U)
46130 #define FTM_COMBINE_COMP0_SHIFT                  (1U)
46131 /*! COMP0 - Complement Of Channel (n) For n = 0
46132  *  0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output
46133  *       is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the
46134  *       channel (n+1) output is independent from channel (n) output.
46135  *  0b1..The channel (n+1) output is the complement of the channel (n) output.
46136  */
46137 #define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
46138 #define FTM_COMBINE_DECAPEN0_MASK                (0x4U)
46139 #define FTM_COMBINE_DECAPEN0_SHIFT               (2U)
46140 /*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0
46141  */
46142 #define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
46143 #define FTM_COMBINE_DECAP0_MASK                  (0x8U)
46144 #define FTM_COMBINE_DECAP0_SHIFT                 (3U)
46145 /*! DECAP0 - Dual Edge Capture Mode Captures For n = 0
46146  *  0b0..The dual edge captures are inactive.
46147  *  0b1..The dual edge captures are active.
46148  */
46149 #define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
46150 #define FTM_COMBINE_DTEN0_MASK                   (0x10U)
46151 #define FTM_COMBINE_DTEN0_SHIFT                  (4U)
46152 /*! DTEN0 - Deadtime Enable For n = 0
46153  *  0b0..The deadtime insertion in this pair of channels is disabled.
46154  *  0b1..The deadtime insertion in this pair of channels is enabled.
46155  */
46156 #define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
46157 #define FTM_COMBINE_SYNCEN0_MASK                 (0x20U)
46158 #define FTM_COMBINE_SYNCEN0_SHIFT                (5U)
46159 /*! SYNCEN0 - Synchronization Enable For n = 0
46160  *  0b0..The PWM synchronization in this pair of channels is disabled.
46161  *  0b1..The PWM synchronization in this pair of channels is enabled.
46162  */
46163 #define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
46164 #define FTM_COMBINE_FAULTEN0_MASK                (0x40U)
46165 #define FTM_COMBINE_FAULTEN0_SHIFT               (6U)
46166 /*! FAULTEN0 - Fault Control Enable For n = 0
46167  *  0b0..The fault control in this pair of channels is disabled.
46168  *  0b1..The fault control in this pair of channels is enabled.
46169  */
46170 #define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
46171 #define FTM_COMBINE_MCOMBINE0_MASK               (0x80U)
46172 #define FTM_COMBINE_MCOMBINE0_SHIFT              (7U)
46173 /*! MCOMBINE0 - Modified Combine Mode For n = 0
46174  */
46175 #define FTM_COMBINE_MCOMBINE0(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE0_SHIFT)) & FTM_COMBINE_MCOMBINE0_MASK)
46176 #define FTM_COMBINE_COMBINE1_MASK                (0x100U)
46177 #define FTM_COMBINE_COMBINE1_SHIFT               (8U)
46178 /*! COMBINE1 - Combine Channels For n = 2
46179  */
46180 #define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
46181 #define FTM_COMBINE_COMP1_MASK                   (0x200U)
46182 #define FTM_COMBINE_COMP1_SHIFT                  (9U)
46183 /*! COMP1 - Complement Of Channel (n) For n = 2
46184  *  0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output
46185  *       is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the
46186  *       channel (n+1) output is independent from channel (n) output.
46187  *  0b1..The channel (n+1) output is the complement of the channel (n) output.
46188  */
46189 #define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
46190 #define FTM_COMBINE_DECAPEN1_MASK                (0x400U)
46191 #define FTM_COMBINE_DECAPEN1_SHIFT               (10U)
46192 /*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2
46193  */
46194 #define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
46195 #define FTM_COMBINE_DECAP1_MASK                  (0x800U)
46196 #define FTM_COMBINE_DECAP1_SHIFT                 (11U)
46197 /*! DECAP1 - Dual Edge Capture Mode Captures For n = 2
46198  *  0b0..The dual edge captures are inactive.
46199  *  0b1..The dual edge captures are active.
46200  */
46201 #define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
46202 #define FTM_COMBINE_DTEN1_MASK                   (0x1000U)
46203 #define FTM_COMBINE_DTEN1_SHIFT                  (12U)
46204 /*! DTEN1 - Deadtime Enable For n = 2
46205  *  0b0..The deadtime insertion in this pair of channels is disabled.
46206  *  0b1..The deadtime insertion in this pair of channels is enabled.
46207  */
46208 #define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
46209 #define FTM_COMBINE_SYNCEN1_MASK                 (0x2000U)
46210 #define FTM_COMBINE_SYNCEN1_SHIFT                (13U)
46211 /*! SYNCEN1 - Synchronization Enable For n = 2
46212  *  0b0..The PWM synchronization in this pair of channels is disabled.
46213  *  0b1..The PWM synchronization in this pair of channels is enabled.
46214  */
46215 #define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
46216 #define FTM_COMBINE_FAULTEN1_MASK                (0x4000U)
46217 #define FTM_COMBINE_FAULTEN1_SHIFT               (14U)
46218 /*! FAULTEN1 - Fault Control Enable For n = 2
46219  *  0b0..The fault control in this pair of channels is disabled.
46220  *  0b1..The fault control in this pair of channels is enabled.
46221  */
46222 #define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
46223 #define FTM_COMBINE_MCOMBINE1_MASK               (0x8000U)
46224 #define FTM_COMBINE_MCOMBINE1_SHIFT              (15U)
46225 /*! MCOMBINE1 - Modified Combine Mode For n = 2
46226  */
46227 #define FTM_COMBINE_MCOMBINE1(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE1_SHIFT)) & FTM_COMBINE_MCOMBINE1_MASK)
46228 #define FTM_COMBINE_COMBINE2_MASK                (0x10000U)
46229 #define FTM_COMBINE_COMBINE2_SHIFT               (16U)
46230 /*! COMBINE2 - Combine Channels For n = 4
46231  */
46232 #define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
46233 #define FTM_COMBINE_COMP2_MASK                   (0x20000U)
46234 #define FTM_COMBINE_COMP2_SHIFT                  (17U)
46235 /*! COMP2 - Complement Of Channel (n) For n = 4
46236  *  0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output
46237  *       is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the
46238  *       channel (n+1) output is independent from channel (n) output.
46239  *  0b1..The channel (n+1) output is the complement of the channel (n) output.
46240  */
46241 #define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
46242 #define FTM_COMBINE_DECAPEN2_MASK                (0x40000U)
46243 #define FTM_COMBINE_DECAPEN2_SHIFT               (18U)
46244 /*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4
46245  */
46246 #define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
46247 #define FTM_COMBINE_DECAP2_MASK                  (0x80000U)
46248 #define FTM_COMBINE_DECAP2_SHIFT                 (19U)
46249 /*! DECAP2 - Dual Edge Capture Mode Captures For n = 4
46250  *  0b0..The dual edge captures are inactive.
46251  *  0b1..The dual edge captures are active.
46252  */
46253 #define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
46254 #define FTM_COMBINE_DTEN2_MASK                   (0x100000U)
46255 #define FTM_COMBINE_DTEN2_SHIFT                  (20U)
46256 /*! DTEN2 - Deadtime Enable For n = 4
46257  *  0b0..The deadtime insertion in this pair of channels is disabled.
46258  *  0b1..The deadtime insertion in this pair of channels is enabled.
46259  */
46260 #define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
46261 #define FTM_COMBINE_SYNCEN2_MASK                 (0x200000U)
46262 #define FTM_COMBINE_SYNCEN2_SHIFT                (21U)
46263 /*! SYNCEN2 - Synchronization Enable For n = 4
46264  *  0b0..The PWM synchronization in this pair of channels is disabled.
46265  *  0b1..The PWM synchronization in this pair of channels is enabled.
46266  */
46267 #define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
46268 #define FTM_COMBINE_FAULTEN2_MASK                (0x400000U)
46269 #define FTM_COMBINE_FAULTEN2_SHIFT               (22U)
46270 /*! FAULTEN2 - Fault Control Enable For n = 4
46271  *  0b0..The fault control in this pair of channels is disabled.
46272  *  0b1..The fault control in this pair of channels is enabled.
46273  */
46274 #define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
46275 #define FTM_COMBINE_MCOMBINE2_MASK               (0x800000U)
46276 #define FTM_COMBINE_MCOMBINE2_SHIFT              (23U)
46277 /*! MCOMBINE2 - Modified Combine Mode For n = 4
46278  */
46279 #define FTM_COMBINE_MCOMBINE2(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE2_SHIFT)) & FTM_COMBINE_MCOMBINE2_MASK)
46280 #define FTM_COMBINE_COMBINE3_MASK                (0x1000000U)
46281 #define FTM_COMBINE_COMBINE3_SHIFT               (24U)
46282 /*! COMBINE3 - Combine Channels For n = 6
46283  */
46284 #define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
46285 #define FTM_COMBINE_COMP3_MASK                   (0x2000000U)
46286 #define FTM_COMBINE_COMP3_SHIFT                  (25U)
46287 /*! COMP3 - Complement Of Channel (n) for n = 6
46288  *  0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output
46289  *       is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the
46290  *       channel (n+1) output is independent from channel (n) output.
46291  *  0b1..The channel (n+1) output is the complement of the channel (n) output.
46292  */
46293 #define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
46294 #define FTM_COMBINE_DECAPEN3_MASK                (0x4000000U)
46295 #define FTM_COMBINE_DECAPEN3_SHIFT               (26U)
46296 /*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6
46297  */
46298 #define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
46299 #define FTM_COMBINE_DECAP3_MASK                  (0x8000000U)
46300 #define FTM_COMBINE_DECAP3_SHIFT                 (27U)
46301 /*! DECAP3 - Dual Edge Capture Mode Captures For n = 6
46302  *  0b0..The dual edge captures are inactive.
46303  *  0b1..The dual edge captures are active.
46304  */
46305 #define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
46306 #define FTM_COMBINE_DTEN3_MASK                   (0x10000000U)
46307 #define FTM_COMBINE_DTEN3_SHIFT                  (28U)
46308 /*! DTEN3 - Deadtime Enable For n = 6
46309  *  0b0..The deadtime insertion in this pair of channels is disabled.
46310  *  0b1..The deadtime insertion in this pair of channels is enabled.
46311  */
46312 #define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
46313 #define FTM_COMBINE_SYNCEN3_MASK                 (0x20000000U)
46314 #define FTM_COMBINE_SYNCEN3_SHIFT                (29U)
46315 /*! SYNCEN3 - Synchronization Enable For n = 6
46316  *  0b0..The PWM synchronization in this pair of channels is disabled.
46317  *  0b1..The PWM synchronization in this pair of channels is enabled.
46318  */
46319 #define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
46320 #define FTM_COMBINE_FAULTEN3_MASK                (0x40000000U)
46321 #define FTM_COMBINE_FAULTEN3_SHIFT               (30U)
46322 /*! FAULTEN3 - Fault Control Enable For n = 6
46323  *  0b0..The fault control in this pair of channels is disabled.
46324  *  0b1..The fault control in this pair of channels is enabled.
46325  */
46326 #define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
46327 #define FTM_COMBINE_MCOMBINE3_MASK               (0x80000000U)
46328 #define FTM_COMBINE_MCOMBINE3_SHIFT              (31U)
46329 /*! MCOMBINE3 - Modified Combine Mode For n = 6
46330  */
46331 #define FTM_COMBINE_MCOMBINE3(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE3_SHIFT)) & FTM_COMBINE_MCOMBINE3_MASK)
46332 /*! @} */
46333 
46334 /*! @name DEADTIME - Deadtime Configuration */
46335 /*! @{ */
46336 #define FTM_DEADTIME_DTVAL_MASK                  (0x3FU)
46337 #define FTM_DEADTIME_DTVAL_SHIFT                 (0U)
46338 /*! DTVAL - Deadtime Value
46339  */
46340 #define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
46341 #define FTM_DEADTIME_DTPS_MASK                   (0xC0U)
46342 #define FTM_DEADTIME_DTPS_SHIFT                  (6U)
46343 /*! DTPS - Deadtime Prescaler Value
46344  *  0b0x..Divide the FTM input clock by 1.
46345  *  0b10..Divide the FTM input clock by 4.
46346  *  0b11..Divide the FTM input clock by 16.
46347  */
46348 #define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
46349 #define FTM_DEADTIME_DTVALEX_MASK                (0xF0000U)
46350 #define FTM_DEADTIME_DTVALEX_SHIFT               (16U)
46351 /*! DTVALEX - Extended Deadtime Value
46352  */
46353 #define FTM_DEADTIME_DTVALEX(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVALEX_SHIFT)) & FTM_DEADTIME_DTVALEX_MASK)
46354 /*! @} */
46355 
46356 /*! @name EXTTRIG - FTM External Trigger */
46357 /*! @{ */
46358 #define FTM_EXTTRIG_CH2TRIG_MASK                 (0x1U)
46359 #define FTM_EXTTRIG_CH2TRIG_SHIFT                (0U)
46360 /*! CH2TRIG - Channel 2 External Trigger Enable
46361  *  0b0..The generation of this external trigger is disabled.
46362  *  0b1..The generation of this external trigger is enabled.
46363  */
46364 #define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
46365 #define FTM_EXTTRIG_CH3TRIG_MASK                 (0x2U)
46366 #define FTM_EXTTRIG_CH3TRIG_SHIFT                (1U)
46367 /*! CH3TRIG - Channel 3 External Trigger Enable
46368  *  0b0..The generation of this external trigger is disabled.
46369  *  0b1..The generation of this external trigger is enabled.
46370  */
46371 #define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
46372 #define FTM_EXTTRIG_CH4TRIG_MASK                 (0x4U)
46373 #define FTM_EXTTRIG_CH4TRIG_SHIFT                (2U)
46374 /*! CH4TRIG - Channel 4 External Trigger Enable
46375  *  0b0..The generation of this external trigger is disabled.
46376  *  0b1..The generation of this external trigger is enabled.
46377  */
46378 #define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
46379 #define FTM_EXTTRIG_CH5TRIG_MASK                 (0x8U)
46380 #define FTM_EXTTRIG_CH5TRIG_SHIFT                (3U)
46381 /*! CH5TRIG - Channel 5 External Trigger Enable
46382  *  0b0..The generation of this external trigger is disabled.
46383  *  0b1..The generation of this external trigger is enabled.
46384  */
46385 #define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
46386 #define FTM_EXTTRIG_CH0TRIG_MASK                 (0x10U)
46387 #define FTM_EXTTRIG_CH0TRIG_SHIFT                (4U)
46388 /*! CH0TRIG - Channel 0 External Trigger Enable
46389  *  0b0..The generation of this external trigger is disabled.
46390  *  0b1..The generation of this external trigger is enabled.
46391  */
46392 #define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
46393 #define FTM_EXTTRIG_CH1TRIG_MASK                 (0x20U)
46394 #define FTM_EXTTRIG_CH1TRIG_SHIFT                (5U)
46395 /*! CH1TRIG - Channel 1 External Trigger Enable
46396  *  0b0..The generation of this external trigger is disabled.
46397  *  0b1..The generation of this external trigger is enabled.
46398  */
46399 #define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
46400 #define FTM_EXTTRIG_INITTRIGEN_MASK              (0x40U)
46401 #define FTM_EXTTRIG_INITTRIGEN_SHIFT             (6U)
46402 /*! INITTRIGEN - Initialization Trigger Enable
46403  *  0b0..The generation of initialization trigger is disabled.
46404  *  0b1..The generation of initialization trigger is enabled.
46405  */
46406 #define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
46407 #define FTM_EXTTRIG_TRIGF_MASK                   (0x80U)
46408 #define FTM_EXTTRIG_TRIGF_SHIFT                  (7U)
46409 /*! TRIGF - Channel Trigger Flag
46410  *  0b0..No channel trigger was generated.
46411  *  0b1..A channel trigger was generated.
46412  */
46413 #define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
46414 #define FTM_EXTTRIG_CH6TRIG_MASK                 (0x100U)
46415 #define FTM_EXTTRIG_CH6TRIG_SHIFT                (8U)
46416 /*! CH6TRIG - Channel 6 External Trigger Enable
46417  *  0b0..The generation of this external trigger is disabled.
46418  *  0b1..The generation of this external trigger is enabled.
46419  */
46420 #define FTM_EXTTRIG_CH6TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH6TRIG_SHIFT)) & FTM_EXTTRIG_CH6TRIG_MASK)
46421 #define FTM_EXTTRIG_CH7TRIG_MASK                 (0x200U)
46422 #define FTM_EXTTRIG_CH7TRIG_SHIFT                (9U)
46423 /*! CH7TRIG - Channel 7 External Trigger Enable
46424  *  0b0..The generation of this external trigger is disabled.
46425  *  0b1..The generation of this external trigger is enabled.
46426  */
46427 #define FTM_EXTTRIG_CH7TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH7TRIG_SHIFT)) & FTM_EXTTRIG_CH7TRIG_MASK)
46428 /*! @} */
46429 
46430 /*! @name POL - Channels Polarity */
46431 /*! @{ */
46432 #define FTM_POL_POL0_MASK                        (0x1U)
46433 #define FTM_POL_POL0_SHIFT                       (0U)
46434 /*! POL0 - Channel 0 Polarity
46435  *  0b0..The channel polarity is active high.
46436  *  0b1..The channel polarity is active low.
46437  */
46438 #define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
46439 #define FTM_POL_POL1_MASK                        (0x2U)
46440 #define FTM_POL_POL1_SHIFT                       (1U)
46441 /*! POL1 - Channel 1 Polarity
46442  *  0b0..The channel polarity is active high.
46443  *  0b1..The channel polarity is active low.
46444  */
46445 #define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
46446 #define FTM_POL_POL2_MASK                        (0x4U)
46447 #define FTM_POL_POL2_SHIFT                       (2U)
46448 /*! POL2 - Channel 2 Polarity
46449  *  0b0..The channel polarity is active high.
46450  *  0b1..The channel polarity is active low.
46451  */
46452 #define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
46453 #define FTM_POL_POL3_MASK                        (0x8U)
46454 #define FTM_POL_POL3_SHIFT                       (3U)
46455 /*! POL3 - Channel 3 Polarity
46456  *  0b0..The channel polarity is active high.
46457  *  0b1..The channel polarity is active low.
46458  */
46459 #define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
46460 #define FTM_POL_POL4_MASK                        (0x10U)
46461 #define FTM_POL_POL4_SHIFT                       (4U)
46462 /*! POL4 - Channel 4 Polarity
46463  *  0b0..The channel polarity is active high.
46464  *  0b1..The channel polarity is active low.
46465  */
46466 #define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
46467 #define FTM_POL_POL5_MASK                        (0x20U)
46468 #define FTM_POL_POL5_SHIFT                       (5U)
46469 /*! POL5 - Channel 5 Polarity
46470  *  0b0..The channel polarity is active high.
46471  *  0b1..The channel polarity is active low.
46472  */
46473 #define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
46474 #define FTM_POL_POL6_MASK                        (0x40U)
46475 #define FTM_POL_POL6_SHIFT                       (6U)
46476 /*! POL6 - Channel 6 Polarity
46477  *  0b0..The channel polarity is active high.
46478  *  0b1..The channel polarity is active low.
46479  */
46480 #define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
46481 #define FTM_POL_POL7_MASK                        (0x80U)
46482 #define FTM_POL_POL7_SHIFT                       (7U)
46483 /*! POL7 - Channel 7 Polarity
46484  *  0b0..The channel polarity is active high.
46485  *  0b1..The channel polarity is active low.
46486  */
46487 #define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
46488 /*! @} */
46489 
46490 /*! @name FMS - Fault Mode Status */
46491 /*! @{ */
46492 #define FTM_FMS_FAULTF0_MASK                     (0x1U)
46493 #define FTM_FMS_FAULTF0_SHIFT                    (0U)
46494 /*! FAULTF0 - Fault Detection Flag 0
46495  *  0b0..No fault condition was detected at the fault input.
46496  *  0b1..A fault condition was detected at the fault input.
46497  */
46498 #define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
46499 #define FTM_FMS_FAULTF1_MASK                     (0x2U)
46500 #define FTM_FMS_FAULTF1_SHIFT                    (1U)
46501 /*! FAULTF1 - Fault Detection Flag 1
46502  *  0b0..No fault condition was detected at the fault input.
46503  *  0b1..A fault condition was detected at the fault input.
46504  */
46505 #define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
46506 #define FTM_FMS_FAULTF2_MASK                     (0x4U)
46507 #define FTM_FMS_FAULTF2_SHIFT                    (2U)
46508 /*! FAULTF2 - Fault Detection Flag 2
46509  *  0b0..No fault condition was detected at the fault input.
46510  *  0b1..A fault condition was detected at the fault input.
46511  */
46512 #define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
46513 #define FTM_FMS_FAULTF3_MASK                     (0x8U)
46514 #define FTM_FMS_FAULTF3_SHIFT                    (3U)
46515 /*! FAULTF3 - Fault Detection Flag 3
46516  *  0b0..No fault condition was detected at the fault input.
46517  *  0b1..A fault condition was detected at the fault input.
46518  */
46519 #define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
46520 #define FTM_FMS_FAULTIN_MASK                     (0x20U)
46521 #define FTM_FMS_FAULTIN_SHIFT                    (5U)
46522 /*! FAULTIN - Fault Inputs
46523  *  0b0..The logic OR of the enabled fault inputs is 0.
46524  *  0b1..The logic OR of the enabled fault inputs is 1.
46525  */
46526 #define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
46527 #define FTM_FMS_WPEN_MASK                        (0x40U)
46528 #define FTM_FMS_WPEN_SHIFT                       (6U)
46529 /*! WPEN - Write Protection Enable
46530  *  0b0..Write protection is disabled. Write protected bits can be written.
46531  *  0b1..Write protection is enabled. Write protected bits cannot be written.
46532  */
46533 #define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
46534 #define FTM_FMS_FAULTF_MASK                      (0x80U)
46535 #define FTM_FMS_FAULTF_SHIFT                     (7U)
46536 /*! FAULTF - Fault Detection Flag
46537  *  0b0..No fault condition was detected.
46538  *  0b1..A fault condition was detected.
46539  */
46540 #define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
46541 /*! @} */
46542 
46543 /*! @name FILTER - Input Capture Filter Control */
46544 /*! @{ */
46545 #define FTM_FILTER_CH0FVAL_MASK                  (0xFU)
46546 #define FTM_FILTER_CH0FVAL_SHIFT                 (0U)
46547 /*! CH0FVAL - Channel 0 Input Filter
46548  */
46549 #define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
46550 #define FTM_FILTER_CH1FVAL_MASK                  (0xF0U)
46551 #define FTM_FILTER_CH1FVAL_SHIFT                 (4U)
46552 /*! CH1FVAL - Channel 1 Input Filter
46553  */
46554 #define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
46555 #define FTM_FILTER_CH2FVAL_MASK                  (0xF00U)
46556 #define FTM_FILTER_CH2FVAL_SHIFT                 (8U)
46557 /*! CH2FVAL - Channel 2 Input Filter
46558  */
46559 #define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
46560 #define FTM_FILTER_CH3FVAL_MASK                  (0xF000U)
46561 #define FTM_FILTER_CH3FVAL_SHIFT                 (12U)
46562 /*! CH3FVAL - Channel 3 Input Filter
46563  */
46564 #define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
46565 /*! @} */
46566 
46567 /*! @name FLTCTRL - Fault Control */
46568 /*! @{ */
46569 #define FTM_FLTCTRL_FAULT0EN_MASK                (0x1U)
46570 #define FTM_FLTCTRL_FAULT0EN_SHIFT               (0U)
46571 /*! FAULT0EN - Fault Input 0 Enable
46572  *  0b0..Fault input is disabled.
46573  *  0b1..Fault input is enabled.
46574  */
46575 #define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
46576 #define FTM_FLTCTRL_FAULT1EN_MASK                (0x2U)
46577 #define FTM_FLTCTRL_FAULT1EN_SHIFT               (1U)
46578 /*! FAULT1EN - Fault Input 1 Enable
46579  *  0b0..Fault input is disabled.
46580  *  0b1..Fault input is enabled.
46581  */
46582 #define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
46583 #define FTM_FLTCTRL_FAULT2EN_MASK                (0x4U)
46584 #define FTM_FLTCTRL_FAULT2EN_SHIFT               (2U)
46585 /*! FAULT2EN - Fault Input 2 Enable
46586  *  0b0..Fault input is disabled.
46587  *  0b1..Fault input is enabled.
46588  */
46589 #define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
46590 #define FTM_FLTCTRL_FAULT3EN_MASK                (0x8U)
46591 #define FTM_FLTCTRL_FAULT3EN_SHIFT               (3U)
46592 /*! FAULT3EN - Fault Input 3 Enable
46593  *  0b0..Fault input is disabled.
46594  *  0b1..Fault input is enabled.
46595  */
46596 #define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
46597 #define FTM_FLTCTRL_FFLTR0EN_MASK                (0x10U)
46598 #define FTM_FLTCTRL_FFLTR0EN_SHIFT               (4U)
46599 /*! FFLTR0EN - Fault Input 0 Filter Enable
46600  *  0b0..Fault input filter is disabled.
46601  *  0b1..Fault input filter is enabled.
46602  */
46603 #define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
46604 #define FTM_FLTCTRL_FFLTR1EN_MASK                (0x20U)
46605 #define FTM_FLTCTRL_FFLTR1EN_SHIFT               (5U)
46606 /*! FFLTR1EN - Fault Input 1 Filter Enable
46607  *  0b0..Fault input filter is disabled.
46608  *  0b1..Fault input filter is enabled.
46609  */
46610 #define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
46611 #define FTM_FLTCTRL_FFLTR2EN_MASK                (0x40U)
46612 #define FTM_FLTCTRL_FFLTR2EN_SHIFT               (6U)
46613 /*! FFLTR2EN - Fault Input 2 Filter Enable
46614  *  0b0..Fault input filter is disabled.
46615  *  0b1..Fault input filter is enabled.
46616  */
46617 #define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
46618 #define FTM_FLTCTRL_FFLTR3EN_MASK                (0x80U)
46619 #define FTM_FLTCTRL_FFLTR3EN_SHIFT               (7U)
46620 /*! FFLTR3EN - Fault Input 3 Filter Enable
46621  *  0b0..Fault input filter is disabled.
46622  *  0b1..Fault input filter is enabled.
46623  */
46624 #define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
46625 #define FTM_FLTCTRL_FFVAL_MASK                   (0xF00U)
46626 #define FTM_FLTCTRL_FFVAL_SHIFT                  (8U)
46627 /*! FFVAL - Fault Input Filter
46628  */
46629 #define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
46630 #define FTM_FLTCTRL_FSTATE_MASK                  (0x8000U)
46631 #define FTM_FLTCTRL_FSTATE_SHIFT                 (15U)
46632 /*! FSTATE - Fault output state
46633  *  0b0..FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).
46634  *  0b1..FTM outputs will be tri-stated when fault event is ongoing
46635  */
46636 #define FTM_FLTCTRL_FSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FSTATE_SHIFT)) & FTM_FLTCTRL_FSTATE_MASK)
46637 /*! @} */
46638 
46639 /*! @name QDCTRL - Quadrature Decoder Control And Status */
46640 /*! @{ */
46641 #define FTM_QDCTRL_QUADEN_MASK                   (0x1U)
46642 #define FTM_QDCTRL_QUADEN_SHIFT                  (0U)
46643 /*! QUADEN - Quadrature Decoder Mode Enable
46644  *  0b0..Quadrature Decoder mode is disabled.
46645  *  0b1..Quadrature Decoder mode is enabled.
46646  */
46647 #define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
46648 #define FTM_QDCTRL_TOFDIR_MASK                   (0x2U)
46649 #define FTM_QDCTRL_TOFDIR_SHIFT                  (1U)
46650 /*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode
46651  *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes
46652  *       from its minimum value (CNTIN register) to its maximum value (MOD register).
46653  *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from
46654  *       its maximum value (MOD register) to its minimum value (CNTIN register).
46655  */
46656 #define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
46657 #define FTM_QDCTRL_QUADIR_MASK                   (0x4U)
46658 #define FTM_QDCTRL_QUADIR_SHIFT                  (2U)
46659 /*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode
46660  *  0b0..Counting direction is decreasing (FTM counter decrement).
46661  *  0b1..Counting direction is increasing (FTM counter increment).
46662  */
46663 #define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
46664 #define FTM_QDCTRL_QUADMODE_MASK                 (0x8U)
46665 #define FTM_QDCTRL_QUADMODE_SHIFT                (3U)
46666 /*! QUADMODE - Quadrature Decoder Mode
46667  *  0b0..Phase A and phase B encoding mode.
46668  *  0b1..Count and direction encoding mode.
46669  */
46670 #define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
46671 #define FTM_QDCTRL_PHBPOL_MASK                   (0x10U)
46672 #define FTM_QDCTRL_PHBPOL_SHIFT                  (4U)
46673 /*! PHBPOL - Phase B Input Polarity
46674  *  0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
46675  *  0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
46676  */
46677 #define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
46678 #define FTM_QDCTRL_PHAPOL_MASK                   (0x20U)
46679 #define FTM_QDCTRL_PHAPOL_SHIFT                  (5U)
46680 /*! PHAPOL - Phase A Input Polarity
46681  *  0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
46682  *  0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
46683  */
46684 #define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
46685 #define FTM_QDCTRL_PHBFLTREN_MASK                (0x40U)
46686 #define FTM_QDCTRL_PHBFLTREN_SHIFT               (6U)
46687 /*! PHBFLTREN - Phase B Input Filter Enable
46688  *  0b0..Phase B input filter is disabled.
46689  *  0b1..Phase B input filter is enabled.
46690  */
46691 #define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
46692 #define FTM_QDCTRL_PHAFLTREN_MASK                (0x80U)
46693 #define FTM_QDCTRL_PHAFLTREN_SHIFT               (7U)
46694 /*! PHAFLTREN - Phase A Input Filter Enable
46695  *  0b0..Phase A input filter is disabled.
46696  *  0b1..Phase A input filter is enabled.
46697  */
46698 #define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
46699 /*! @} */
46700 
46701 /*! @name CONF - Configuration */
46702 /*! @{ */
46703 #define FTM_CONF_LDFQ_MASK                       (0x1FU)
46704 #define FTM_CONF_LDFQ_SHIFT                      (0U)
46705 /*! LDFQ - Frequency of the Reload Opportunities
46706  */
46707 #define FTM_CONF_LDFQ(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CONF_LDFQ_SHIFT)) & FTM_CONF_LDFQ_MASK)
46708 #define FTM_CONF_BDMMODE_MASK                    (0xC0U)
46709 #define FTM_CONF_BDMMODE_SHIFT                   (6U)
46710 /*! BDMMODE - BDM Mode
46711  */
46712 #define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
46713 #define FTM_CONF_GTBEEN_MASK                     (0x200U)
46714 #define FTM_CONF_GTBEEN_SHIFT                    (9U)
46715 /*! GTBEEN - Global Time Base Enable
46716  *  0b0..Use of an external global time base is disabled.
46717  *  0b1..Use of an external global time base is enabled.
46718  */
46719 #define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
46720 #define FTM_CONF_GTBEOUT_MASK                    (0x400U)
46721 #define FTM_CONF_GTBEOUT_SHIFT                   (10U)
46722 /*! GTBEOUT - Global Time Base Output
46723  *  0b0..A global time base signal generation is disabled.
46724  *  0b1..A global time base signal generation is enabled.
46725  */
46726 #define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
46727 #define FTM_CONF_ITRIGR_MASK                     (0x800U)
46728 #define FTM_CONF_ITRIGR_SHIFT                    (11U)
46729 /*! ITRIGR - Initialization trigger on Reload Point
46730  *  0b0..Initialization trigger is generated on counter wrap events.
46731  *  0b1..Initialization trigger is generated when a reload point is reached.
46732  */
46733 #define FTM_CONF_ITRIGR(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_ITRIGR_SHIFT)) & FTM_CONF_ITRIGR_MASK)
46734 /*! @} */
46735 
46736 /*! @name FLTPOL - FTM Fault Input Polarity */
46737 /*! @{ */
46738 #define FTM_FLTPOL_FLT0POL_MASK                  (0x1U)
46739 #define FTM_FLTPOL_FLT0POL_SHIFT                 (0U)
46740 /*! FLT0POL - Fault Input 0 Polarity
46741  *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
46742  *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
46743  */
46744 #define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
46745 #define FTM_FLTPOL_FLT1POL_MASK                  (0x2U)
46746 #define FTM_FLTPOL_FLT1POL_SHIFT                 (1U)
46747 /*! FLT1POL - Fault Input 1 Polarity
46748  *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
46749  *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
46750  */
46751 #define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
46752 #define FTM_FLTPOL_FLT2POL_MASK                  (0x4U)
46753 #define FTM_FLTPOL_FLT2POL_SHIFT                 (2U)
46754 /*! FLT2POL - Fault Input 2 Polarity
46755  *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
46756  *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
46757  */
46758 #define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
46759 #define FTM_FLTPOL_FLT3POL_MASK                  (0x8U)
46760 #define FTM_FLTPOL_FLT3POL_SHIFT                 (3U)
46761 /*! FLT3POL - Fault Input 3 Polarity
46762  *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
46763  *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
46764  */
46765 #define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
46766 /*! @} */
46767 
46768 /*! @name SYNCONF - Synchronization Configuration */
46769 /*! @{ */
46770 #define FTM_SYNCONF_HWTRIGMODE_MASK              (0x1U)
46771 #define FTM_SYNCONF_HWTRIGMODE_SHIFT             (0U)
46772 /*! HWTRIGMODE - Hardware Trigger Mode
46773  *  0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
46774  *  0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
46775  */
46776 #define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
46777 #define FTM_SYNCONF_CNTINC_MASK                  (0x4U)
46778 #define FTM_SYNCONF_CNTINC_SHIFT                 (2U)
46779 /*! CNTINC - CNTIN Register Synchronization
46780  *  0b0..CNTIN register is updated with its buffer value at all rising edges of FTM input clock.
46781  *  0b1..CNTIN register is updated with its buffer value by the PWM synchronization.
46782  */
46783 #define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
46784 #define FTM_SYNCONF_INVC_MASK                    (0x10U)
46785 #define FTM_SYNCONF_INVC_SHIFT                   (4U)
46786 /*! INVC - INVCTRL Register Synchronization
46787  *  0b0..INVCTRL register is updated with its buffer value at all rising edges of FTM input clock.
46788  *  0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.
46789  */
46790 #define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
46791 #define FTM_SYNCONF_SWOC_MASK                    (0x20U)
46792 #define FTM_SYNCONF_SWOC_SHIFT                   (5U)
46793 /*! SWOC - SWOCTRL Register Synchronization
46794  *  0b0..SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock.
46795  *  0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.
46796  */
46797 #define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
46798 #define FTM_SYNCONF_SYNCMODE_MASK                (0x80U)
46799 #define FTM_SYNCONF_SYNCMODE_SHIFT               (7U)
46800 /*! SYNCMODE - Synchronization Mode
46801  *  0b0..Legacy PWM synchronization is selected.
46802  *  0b1..Enhanced PWM synchronization is selected.
46803  */
46804 #define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
46805 #define FTM_SYNCONF_SWRSTCNT_MASK                (0x100U)
46806 #define FTM_SYNCONF_SWRSTCNT_SHIFT               (8U)
46807 /*! SWRSTCNT - FTM counter synchronization is activated by the software trigger
46808  *  0b0..The software trigger does not activate the FTM counter synchronization.
46809  *  0b1..The software trigger activates the FTM counter synchronization.
46810  */
46811 #define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
46812 #define FTM_SYNCONF_SWWRBUF_MASK                 (0x200U)
46813 #define FTM_SYNCONF_SWWRBUF_SHIFT                (9U)
46814 /*! SWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger
46815  *  0b0..The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
46816  *  0b1..The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
46817  */
46818 #define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
46819 #define FTM_SYNCONF_SWOM_MASK                    (0x400U)
46820 #define FTM_SYNCONF_SWOM_SHIFT                   (10U)
46821 /*! SWOM - Output mask synchronization is activated by the software trigger
46822  *  0b0..The software trigger does not activate the OUTMASK register synchronization.
46823  *  0b1..The software trigger activates the OUTMASK register synchronization.
46824  */
46825 #define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
46826 #define FTM_SYNCONF_SWINVC_MASK                  (0x800U)
46827 #define FTM_SYNCONF_SWINVC_SHIFT                 (11U)
46828 /*! SWINVC - Inverting control synchronization is activated by the software trigger
46829  *  0b0..The software trigger does not activate the INVCTRL register synchronization.
46830  *  0b1..The software trigger activates the INVCTRL register synchronization.
46831  */
46832 #define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
46833 #define FTM_SYNCONF_SWSOC_MASK                   (0x1000U)
46834 #define FTM_SYNCONF_SWSOC_SHIFT                  (12U)
46835 /*! SWSOC - Software output control synchronization is activated by the software trigger
46836  *  0b0..The software trigger does not activate the SWOCTRL register synchronization.
46837  *  0b1..The software trigger activates the SWOCTRL register synchronization.
46838  */
46839 #define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
46840 #define FTM_SYNCONF_HWRSTCNT_MASK                (0x10000U)
46841 #define FTM_SYNCONF_HWRSTCNT_SHIFT               (16U)
46842 /*! HWRSTCNT - FTM counter synchronization is activated by a hardware trigger
46843  *  0b0..A hardware trigger does not activate the FTM counter synchronization.
46844  *  0b1..A hardware trigger activates the FTM counter synchronization.
46845  */
46846 #define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
46847 #define FTM_SYNCONF_HWWRBUF_MASK                 (0x20000U)
46848 #define FTM_SYNCONF_HWWRBUF_SHIFT                (17U)
46849 /*! HWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger
46850  *  0b0..A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
46851  *  0b1..A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
46852  */
46853 #define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
46854 #define FTM_SYNCONF_HWOM_MASK                    (0x40000U)
46855 #define FTM_SYNCONF_HWOM_SHIFT                   (18U)
46856 /*! HWOM - Output mask synchronization is activated by a hardware trigger
46857  *  0b0..A hardware trigger does not activate the OUTMASK register synchronization.
46858  *  0b1..A hardware trigger activates the OUTMASK register synchronization.
46859  */
46860 #define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
46861 #define FTM_SYNCONF_HWINVC_MASK                  (0x80000U)
46862 #define FTM_SYNCONF_HWINVC_SHIFT                 (19U)
46863 /*! HWINVC - Inverting control synchronization is activated by a hardware trigger
46864  *  0b0..A hardware trigger does not activate the INVCTRL register synchronization.
46865  *  0b1..A hardware trigger activates the INVCTRL register synchronization.
46866  */
46867 #define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
46868 #define FTM_SYNCONF_HWSOC_MASK                   (0x100000U)
46869 #define FTM_SYNCONF_HWSOC_SHIFT                  (20U)
46870 /*! HWSOC - Software output control synchronization is activated by a hardware trigger
46871  *  0b0..A hardware trigger does not activate the SWOCTRL register synchronization.
46872  *  0b1..A hardware trigger activates the SWOCTRL register synchronization.
46873  */
46874 #define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
46875 /*! @} */
46876 
46877 /*! @name INVCTRL - FTM Inverting Control */
46878 /*! @{ */
46879 #define FTM_INVCTRL_INV0EN_MASK                  (0x1U)
46880 #define FTM_INVCTRL_INV0EN_SHIFT                 (0U)
46881 /*! INV0EN - Pair Channels 0 Inverting Enable
46882  *  0b0..Inverting is disabled.
46883  *  0b1..Inverting is enabled.
46884  */
46885 #define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
46886 #define FTM_INVCTRL_INV1EN_MASK                  (0x2U)
46887 #define FTM_INVCTRL_INV1EN_SHIFT                 (1U)
46888 /*! INV1EN - Pair Channels 1 Inverting Enable
46889  *  0b0..Inverting is disabled.
46890  *  0b1..Inverting is enabled.
46891  */
46892 #define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
46893 #define FTM_INVCTRL_INV2EN_MASK                  (0x4U)
46894 #define FTM_INVCTRL_INV2EN_SHIFT                 (2U)
46895 /*! INV2EN - Pair Channels 2 Inverting Enable
46896  *  0b0..Inverting is disabled.
46897  *  0b1..Inverting is enabled.
46898  */
46899 #define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
46900 #define FTM_INVCTRL_INV3EN_MASK                  (0x8U)
46901 #define FTM_INVCTRL_INV3EN_SHIFT                 (3U)
46902 /*! INV3EN - Pair Channels 3 Inverting Enable
46903  *  0b0..Inverting is disabled.
46904  *  0b1..Inverting is enabled.
46905  */
46906 #define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
46907 /*! @} */
46908 
46909 /*! @name SWOCTRL - FTM Software Output Control */
46910 /*! @{ */
46911 #define FTM_SWOCTRL_CH0OC_MASK                   (0x1U)
46912 #define FTM_SWOCTRL_CH0OC_SHIFT                  (0U)
46913 /*! CH0OC - Channel 0 Software Output Control Enable
46914  *  0b0..The channel output is not affected by software output control.
46915  *  0b1..The channel output is affected by software output control.
46916  */
46917 #define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
46918 #define FTM_SWOCTRL_CH1OC_MASK                   (0x2U)
46919 #define FTM_SWOCTRL_CH1OC_SHIFT                  (1U)
46920 /*! CH1OC - Channel 1 Software Output Control Enable
46921  *  0b0..The channel output is not affected by software output control.
46922  *  0b1..The channel output is affected by software output control.
46923  */
46924 #define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
46925 #define FTM_SWOCTRL_CH2OC_MASK                   (0x4U)
46926 #define FTM_SWOCTRL_CH2OC_SHIFT                  (2U)
46927 /*! CH2OC - Channel 2 Software Output Control Enable
46928  *  0b0..The channel output is not affected by software output control.
46929  *  0b1..The channel output is affected by software output control.
46930  */
46931 #define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
46932 #define FTM_SWOCTRL_CH3OC_MASK                   (0x8U)
46933 #define FTM_SWOCTRL_CH3OC_SHIFT                  (3U)
46934 /*! CH3OC - Channel 3 Software Output Control Enable
46935  *  0b0..The channel output is not affected by software output control.
46936  *  0b1..The channel output is affected by software output control.
46937  */
46938 #define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
46939 #define FTM_SWOCTRL_CH4OC_MASK                   (0x10U)
46940 #define FTM_SWOCTRL_CH4OC_SHIFT                  (4U)
46941 /*! CH4OC - Channel 4 Software Output Control Enable
46942  *  0b0..The channel output is not affected by software output control.
46943  *  0b1..The channel output is affected by software output control.
46944  */
46945 #define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
46946 #define FTM_SWOCTRL_CH5OC_MASK                   (0x20U)
46947 #define FTM_SWOCTRL_CH5OC_SHIFT                  (5U)
46948 /*! CH5OC - Channel 5 Software Output Control Enable
46949  *  0b0..The channel output is not affected by software output control.
46950  *  0b1..The channel output is affected by software output control.
46951  */
46952 #define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
46953 #define FTM_SWOCTRL_CH6OC_MASK                   (0x40U)
46954 #define FTM_SWOCTRL_CH6OC_SHIFT                  (6U)
46955 /*! CH6OC - Channel 6 Software Output Control Enable
46956  *  0b0..The channel output is not affected by software output control.
46957  *  0b1..The channel output is affected by software output control.
46958  */
46959 #define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
46960 #define FTM_SWOCTRL_CH7OC_MASK                   (0x80U)
46961 #define FTM_SWOCTRL_CH7OC_SHIFT                  (7U)
46962 /*! CH7OC - Channel 7 Software Output Control Enable
46963  *  0b0..The channel output is not affected by software output control.
46964  *  0b1..The channel output is affected by software output control.
46965  */
46966 #define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
46967 #define FTM_SWOCTRL_CH0OCV_MASK                  (0x100U)
46968 #define FTM_SWOCTRL_CH0OCV_SHIFT                 (8U)
46969 /*! CH0OCV - Channel 0 Software Output Control Value
46970  *  0b0..The software output control forces 0 to the channel output.
46971  *  0b1..The software output control forces 1 to the channel output.
46972  */
46973 #define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
46974 #define FTM_SWOCTRL_CH1OCV_MASK                  (0x200U)
46975 #define FTM_SWOCTRL_CH1OCV_SHIFT                 (9U)
46976 /*! CH1OCV - Channel 1 Software Output Control Value
46977  *  0b0..The software output control forces 0 to the channel output.
46978  *  0b1..The software output control forces 1 to the channel output.
46979  */
46980 #define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
46981 #define FTM_SWOCTRL_CH2OCV_MASK                  (0x400U)
46982 #define FTM_SWOCTRL_CH2OCV_SHIFT                 (10U)
46983 /*! CH2OCV - Channel 2 Software Output Control Value
46984  *  0b0..The software output control forces 0 to the channel output.
46985  *  0b1..The software output control forces 1 to the channel output.
46986  */
46987 #define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
46988 #define FTM_SWOCTRL_CH3OCV_MASK                  (0x800U)
46989 #define FTM_SWOCTRL_CH3OCV_SHIFT                 (11U)
46990 /*! CH3OCV - Channel 3 Software Output Control Value
46991  *  0b0..The software output control forces 0 to the channel output.
46992  *  0b1..The software output control forces 1 to the channel output.
46993  */
46994 #define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
46995 #define FTM_SWOCTRL_CH4OCV_MASK                  (0x1000U)
46996 #define FTM_SWOCTRL_CH4OCV_SHIFT                 (12U)
46997 /*! CH4OCV - Channel 4 Software Output Control Value
46998  *  0b0..The software output control forces 0 to the channel output.
46999  *  0b1..The software output control forces 1 to the channel output.
47000  */
47001 #define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
47002 #define FTM_SWOCTRL_CH5OCV_MASK                  (0x2000U)
47003 #define FTM_SWOCTRL_CH5OCV_SHIFT                 (13U)
47004 /*! CH5OCV - Channel 5 Software Output Control Value
47005  *  0b0..The software output control forces 0 to the channel output.
47006  *  0b1..The software output control forces 1 to the channel output.
47007  */
47008 #define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
47009 #define FTM_SWOCTRL_CH6OCV_MASK                  (0x4000U)
47010 #define FTM_SWOCTRL_CH6OCV_SHIFT                 (14U)
47011 /*! CH6OCV - Channel 6 Software Output Control Value
47012  *  0b0..The software output control forces 0 to the channel output.
47013  *  0b1..The software output control forces 1 to the channel output.
47014  */
47015 #define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
47016 #define FTM_SWOCTRL_CH7OCV_MASK                  (0x8000U)
47017 #define FTM_SWOCTRL_CH7OCV_SHIFT                 (15U)
47018 /*! CH7OCV - Channel 7 Software Output Control Value
47019  *  0b0..The software output control forces 0 to the channel output.
47020  *  0b1..The software output control forces 1 to the channel output.
47021  */
47022 #define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
47023 /*! @} */
47024 
47025 /*! @name PWMLOAD - FTM PWM Load */
47026 /*! @{ */
47027 #define FTM_PWMLOAD_CH0SEL_MASK                  (0x1U)
47028 #define FTM_PWMLOAD_CH0SEL_SHIFT                 (0U)
47029 /*! CH0SEL - Channel 0 Select
47030  *  0b0..Channel match is not included as a reload opportunity.
47031  *  0b1..Channel match is included as a reload opportunity.
47032  */
47033 #define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
47034 #define FTM_PWMLOAD_CH1SEL_MASK                  (0x2U)
47035 #define FTM_PWMLOAD_CH1SEL_SHIFT                 (1U)
47036 /*! CH1SEL - Channel 1 Select
47037  *  0b0..Channel match is not included as a reload opportunity.
47038  *  0b1..Channel match is included as a reload opportunity.
47039  */
47040 #define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
47041 #define FTM_PWMLOAD_CH2SEL_MASK                  (0x4U)
47042 #define FTM_PWMLOAD_CH2SEL_SHIFT                 (2U)
47043 /*! CH2SEL - Channel 2 Select
47044  *  0b0..Channel match is not included as a reload opportunity.
47045  *  0b1..Channel match is included as a reload opportunity.
47046  */
47047 #define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
47048 #define FTM_PWMLOAD_CH3SEL_MASK                  (0x8U)
47049 #define FTM_PWMLOAD_CH3SEL_SHIFT                 (3U)
47050 /*! CH3SEL - Channel 3 Select
47051  *  0b0..Channel match is not included as a reload opportunity.
47052  *  0b1..Channel match is included as a reload opportunity.
47053  */
47054 #define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
47055 #define FTM_PWMLOAD_CH4SEL_MASK                  (0x10U)
47056 #define FTM_PWMLOAD_CH4SEL_SHIFT                 (4U)
47057 /*! CH4SEL - Channel 4 Select
47058  *  0b0..Channel match is not included as a reload opportunity.
47059  *  0b1..Channel match is included as a reload opportunity.
47060  */
47061 #define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
47062 #define FTM_PWMLOAD_CH5SEL_MASK                  (0x20U)
47063 #define FTM_PWMLOAD_CH5SEL_SHIFT                 (5U)
47064 /*! CH5SEL - Channel 5 Select
47065  *  0b0..Channel match is not included as a reload opportunity.
47066  *  0b1..Channel match is included as a reload opportunity.
47067  */
47068 #define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
47069 #define FTM_PWMLOAD_CH6SEL_MASK                  (0x40U)
47070 #define FTM_PWMLOAD_CH6SEL_SHIFT                 (6U)
47071 /*! CH6SEL - Channel 6 Select
47072  *  0b0..Channel match is not included as a reload opportunity.
47073  *  0b1..Channel match is included as a reload opportunity.
47074  */
47075 #define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
47076 #define FTM_PWMLOAD_CH7SEL_MASK                  (0x80U)
47077 #define FTM_PWMLOAD_CH7SEL_SHIFT                 (7U)
47078 /*! CH7SEL - Channel 7 Select
47079  *  0b0..Channel match is not included as a reload opportunity.
47080  *  0b1..Channel match is included as a reload opportunity.
47081  */
47082 #define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
47083 #define FTM_PWMLOAD_HCSEL_MASK                   (0x100U)
47084 #define FTM_PWMLOAD_HCSEL_SHIFT                  (8U)
47085 /*! HCSEL - Half Cycle Select
47086  *  0b0..Half cycle reload is disabled and it is not considered as a reload opportunity.
47087  *  0b1..Half cycle reload is enabled and it is considered as a reload opportunity.
47088  */
47089 #define FTM_PWMLOAD_HCSEL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_HCSEL_SHIFT)) & FTM_PWMLOAD_HCSEL_MASK)
47090 #define FTM_PWMLOAD_LDOK_MASK                    (0x200U)
47091 #define FTM_PWMLOAD_LDOK_SHIFT                   (9U)
47092 /*! LDOK - Load Enable
47093  *  0b0..Loading updated values is disabled.
47094  *  0b1..Loading updated values is enabled.
47095  */
47096 #define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
47097 #define FTM_PWMLOAD_GLEN_MASK                    (0x400U)
47098 #define FTM_PWMLOAD_GLEN_SHIFT                   (10U)
47099 /*! GLEN - Global Load Enable
47100  *  0b0..Global Load Ok disabled.
47101  *  0b1..Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.
47102  */
47103 #define FTM_PWMLOAD_GLEN(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLEN_SHIFT)) & FTM_PWMLOAD_GLEN_MASK)
47104 #define FTM_PWMLOAD_GLDOK_MASK                   (0x800U)
47105 #define FTM_PWMLOAD_GLDOK_SHIFT                  (11U)
47106 /*! GLDOK - Global Load OK
47107  *  0b0..No action.
47108  *  0b1..LDOK bit is set.
47109  */
47110 #define FTM_PWMLOAD_GLDOK(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLDOK_SHIFT)) & FTM_PWMLOAD_GLDOK_MASK)
47111 /*! @} */
47112 
47113 /*! @name HCR - Half Cycle Register */
47114 /*! @{ */
47115 #define FTM_HCR_HCVAL_MASK                       (0xFFFFU)
47116 #define FTM_HCR_HCVAL_SHIFT                      (0U)
47117 /*! HCVAL - Half Cycle Value
47118  */
47119 #define FTM_HCR_HCVAL(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_HCR_HCVAL_SHIFT)) & FTM_HCR_HCVAL_MASK)
47120 /*! @} */
47121 
47122 /*! @name MOD_MIRROR - Mirror of Modulo Value */
47123 /*! @{ */
47124 #define FTM_MOD_MIRROR_FRACMOD_MASK              (0xF800U)
47125 #define FTM_MOD_MIRROR_FRACMOD_SHIFT             (11U)
47126 /*! FRACMOD - Modulo Fractional Value
47127  */
47128 #define FTM_MOD_MIRROR_FRACMOD(x)                (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_FRACMOD_SHIFT)) & FTM_MOD_MIRROR_FRACMOD_MASK)
47129 #define FTM_MOD_MIRROR_MOD_MASK                  (0xFFFF0000U)
47130 #define FTM_MOD_MIRROR_MOD_SHIFT                 (16U)
47131 /*! MOD - Mirror of the Modulo Integer Value
47132  */
47133 #define FTM_MOD_MIRROR_MOD(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_MOD_SHIFT)) & FTM_MOD_MIRROR_MOD_MASK)
47134 /*! @} */
47135 
47136 /*! @name CV_MIRROR - Mirror of Channel (n) Match Value */
47137 /*! @{ */
47138 #define FTM_CV_MIRROR_FRACVAL_MASK               (0xF800U)
47139 #define FTM_CV_MIRROR_FRACVAL_SHIFT              (11U)
47140 /*! FRACVAL - Channel (n) Match Fractional Value
47141  */
47142 #define FTM_CV_MIRROR_FRACVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_FRACVAL_SHIFT)) & FTM_CV_MIRROR_FRACVAL_MASK)
47143 #define FTM_CV_MIRROR_VAL_MASK                   (0xFFFF0000U)
47144 #define FTM_CV_MIRROR_VAL_SHIFT                  (16U)
47145 /*! VAL - Mirror of the Channel (n) Match Integer Value
47146  */
47147 #define FTM_CV_MIRROR_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_VAL_SHIFT)) & FTM_CV_MIRROR_VAL_MASK)
47148 /*! @} */
47149 
47150 /* The count of FTM_CV_MIRROR */
47151 #define FTM_CV_MIRROR_COUNT                      (8U)
47152 
47153 
47154 /*!
47155  * @}
47156  */ /* end of group FTM_Register_Masks */
47157 
47158 
47159 /* FTM - Peripheral instance base addresses */
47160 /** Peripheral ADMA__FTM0 base address */
47161 #define ADMA__FTM0_BASE                          (0x5A8A0000u)
47162 /** Peripheral ADMA__FTM0 base pointer */
47163 #define ADMA__FTM0                               ((FTM_Type *)ADMA__FTM0_BASE)
47164 /** Peripheral ADMA__FTM1 base address */
47165 #define ADMA__FTM1_BASE                          (0x5A8B0000u)
47166 /** Peripheral ADMA__FTM1 base pointer */
47167 #define ADMA__FTM1                               ((FTM_Type *)ADMA__FTM1_BASE)
47168 /** Array initializer of FTM peripheral base addresses */
47169 #define FTM_BASE_ADDRS                           { ADMA__FTM0_BASE, ADMA__FTM1_BASE }
47170 /** Array initializer of FTM peripheral base pointers */
47171 #define FTM_BASE_PTRS                            { ADMA__FTM0, ADMA__FTM1 }
47172 /** Interrupt vectors for the FTM peripheral type */
47173 #define FTM_IRQS                                 { ADMA_FTM0_INT_IRQn, ADMA_FTM1_INT_IRQn }
47174 
47175 /*!
47176  * @}
47177  */ /* end of group FTM_Peripheral_Access_Layer */
47178 
47179 
47180 /* ----------------------------------------------------------------------------
47181    -- GPIO Peripheral Access Layer
47182    ---------------------------------------------------------------------------- */
47183 
47184 /*!
47185  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
47186  * @{
47187  */
47188 
47189 /** GPIO - Register Layout Typedef */
47190 typedef struct {
47191   __IO uint32_t DR;                                /**< GPIO data register, offset: 0x0 */
47192   __IO uint32_t GDIR;                              /**< GPIO direction register, offset: 0x4 */
47193   __I  uint32_t PSR;                               /**< GPIO pad status register, offset: 0x8 */
47194   __IO uint32_t ICR1;                              /**< GPIO interrupt configuration register1, offset: 0xC */
47195   __IO uint32_t ICR2;                              /**< GPIO interrupt configuration register2, offset: 0x10 */
47196   __IO uint32_t IMR;                               /**< GPIO interrupt mask register, offset: 0x14 */
47197   __IO uint32_t ISR;                               /**< GPIO interrupt status register, offset: 0x18 */
47198   __IO uint32_t EDGE_SEL;                          /**< GPIO edge select register, offset: 0x1C */
47199        uint8_t RESERVED_0[100];
47200   __O  uint32_t DR_SET;                            /**< GPIO data register SET, offset: 0x84 */
47201   __O  uint32_t DR_CLEAR;                          /**< GPIO data register CLEAR, offset: 0x88 */
47202   __O  uint32_t DR_TOGGLE;                         /**< GPIO data register TOGGLE, offset: 0x8C */
47203 } GPIO_Type;
47204 
47205 /* ----------------------------------------------------------------------------
47206    -- GPIO Register Masks
47207    ---------------------------------------------------------------------------- */
47208 
47209 /*!
47210  * @addtogroup GPIO_Register_Masks GPIO Register Masks
47211  * @{
47212  */
47213 
47214 /*! @name DR - GPIO data register */
47215 /*! @{ */
47216 #define GPIO_DR_DR_MASK                          (0xFFFFFFFFU)
47217 #define GPIO_DR_DR_SHIFT                         (0U)
47218 /*! DR - DR
47219  */
47220 #define GPIO_DR_DR(x)                            (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
47221 /*! @} */
47222 
47223 /*! @name GDIR - GPIO direction register */
47224 /*! @{ */
47225 #define GPIO_GDIR_GDIR_MASK                      (0xFFFFFFFFU)
47226 #define GPIO_GDIR_GDIR_SHIFT                     (0U)
47227 /*! GDIR - GDIR
47228  */
47229 #define GPIO_GDIR_GDIR(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
47230 /*! @} */
47231 
47232 /*! @name PSR - GPIO pad status register */
47233 /*! @{ */
47234 #define GPIO_PSR_PSR_MASK                        (0xFFFFFFFFU)
47235 #define GPIO_PSR_PSR_SHIFT                       (0U)
47236 /*! PSR - PSR
47237  */
47238 #define GPIO_PSR_PSR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
47239 /*! @} */
47240 
47241 /*! @name ICR1 - GPIO interrupt configuration register1 */
47242 /*! @{ */
47243 #define GPIO_ICR1_ICR0_MASK                      (0x3U)
47244 #define GPIO_ICR1_ICR0_SHIFT                     (0U)
47245 /*! ICR0 - ICR0
47246  *  0b00..Interrupt n is low-level sensitive.
47247  *  0b01..Interrupt n is high-level sensitive.
47248  *  0b10..Interrupt n is rising-edge sensitive.
47249  *  0b11..Interrupt n is falling-edge sensitive.
47250  */
47251 #define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
47252 #define GPIO_ICR1_ICR1_MASK                      (0xCU)
47253 #define GPIO_ICR1_ICR1_SHIFT                     (2U)
47254 /*! ICR1 - ICR1
47255  *  0b00..Interrupt n is low-level sensitive.
47256  *  0b01..Interrupt n is high-level sensitive.
47257  *  0b10..Interrupt n is rising-edge sensitive.
47258  *  0b11..Interrupt n is falling-edge sensitive.
47259  */
47260 #define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
47261 #define GPIO_ICR1_ICR2_MASK                      (0x30U)
47262 #define GPIO_ICR1_ICR2_SHIFT                     (4U)
47263 /*! ICR2 - ICR2
47264  *  0b00..Interrupt n is low-level sensitive.
47265  *  0b01..Interrupt n is high-level sensitive.
47266  *  0b10..Interrupt n is rising-edge sensitive.
47267  *  0b11..Interrupt n is falling-edge sensitive.
47268  */
47269 #define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
47270 #define GPIO_ICR1_ICR3_MASK                      (0xC0U)
47271 #define GPIO_ICR1_ICR3_SHIFT                     (6U)
47272 /*! ICR3 - ICR3
47273  *  0b00..Interrupt n is low-level sensitive.
47274  *  0b01..Interrupt n is high-level sensitive.
47275  *  0b10..Interrupt n is rising-edge sensitive.
47276  *  0b11..Interrupt n is falling-edge sensitive.
47277  */
47278 #define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
47279 #define GPIO_ICR1_ICR4_MASK                      (0x300U)
47280 #define GPIO_ICR1_ICR4_SHIFT                     (8U)
47281 /*! ICR4 - ICR4
47282  *  0b00..Interrupt n is low-level sensitive.
47283  *  0b01..Interrupt n is high-level sensitive.
47284  *  0b10..Interrupt n is rising-edge sensitive.
47285  *  0b11..Interrupt n is falling-edge sensitive.
47286  */
47287 #define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
47288 #define GPIO_ICR1_ICR5_MASK                      (0xC00U)
47289 #define GPIO_ICR1_ICR5_SHIFT                     (10U)
47290 /*! ICR5 - ICR5
47291  *  0b00..Interrupt n is low-level sensitive.
47292  *  0b01..Interrupt n is high-level sensitive.
47293  *  0b10..Interrupt n is rising-edge sensitive.
47294  *  0b11..Interrupt n is falling-edge sensitive.
47295  */
47296 #define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
47297 #define GPIO_ICR1_ICR6_MASK                      (0x3000U)
47298 #define GPIO_ICR1_ICR6_SHIFT                     (12U)
47299 /*! ICR6 - ICR6
47300  *  0b00..Interrupt n is low-level sensitive.
47301  *  0b01..Interrupt n is high-level sensitive.
47302  *  0b10..Interrupt n is rising-edge sensitive.
47303  *  0b11..Interrupt n is falling-edge sensitive.
47304  */
47305 #define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
47306 #define GPIO_ICR1_ICR7_MASK                      (0xC000U)
47307 #define GPIO_ICR1_ICR7_SHIFT                     (14U)
47308 /*! ICR7 - ICR7
47309  *  0b00..Interrupt n is low-level sensitive.
47310  *  0b01..Interrupt n is high-level sensitive.
47311  *  0b10..Interrupt n is rising-edge sensitive.
47312  *  0b11..Interrupt n is falling-edge sensitive.
47313  */
47314 #define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
47315 #define GPIO_ICR1_ICR8_MASK                      (0x30000U)
47316 #define GPIO_ICR1_ICR8_SHIFT                     (16U)
47317 /*! ICR8 - ICR8
47318  *  0b00..Interrupt n is low-level sensitive.
47319  *  0b01..Interrupt n is high-level sensitive.
47320  *  0b10..Interrupt n is rising-edge sensitive.
47321  *  0b11..Interrupt n is falling-edge sensitive.
47322  */
47323 #define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
47324 #define GPIO_ICR1_ICR9_MASK                      (0xC0000U)
47325 #define GPIO_ICR1_ICR9_SHIFT                     (18U)
47326 /*! ICR9 - ICR9
47327  *  0b00..Interrupt n is low-level sensitive.
47328  *  0b01..Interrupt n is high-level sensitive.
47329  *  0b10..Interrupt n is rising-edge sensitive.
47330  *  0b11..Interrupt n is falling-edge sensitive.
47331  */
47332 #define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
47333 #define GPIO_ICR1_ICR10_MASK                     (0x300000U)
47334 #define GPIO_ICR1_ICR10_SHIFT                    (20U)
47335 /*! ICR10 - ICR10
47336  *  0b00..Interrupt n is low-level sensitive.
47337  *  0b01..Interrupt n is high-level sensitive.
47338  *  0b10..Interrupt n is rising-edge sensitive.
47339  *  0b11..Interrupt n is falling-edge sensitive.
47340  */
47341 #define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
47342 #define GPIO_ICR1_ICR11_MASK                     (0xC00000U)
47343 #define GPIO_ICR1_ICR11_SHIFT                    (22U)
47344 /*! ICR11 - ICR11
47345  *  0b00..Interrupt n is low-level sensitive.
47346  *  0b01..Interrupt n is high-level sensitive.
47347  *  0b10..Interrupt n is rising-edge sensitive.
47348  *  0b11..Interrupt n is falling-edge sensitive.
47349  */
47350 #define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
47351 #define GPIO_ICR1_ICR12_MASK                     (0x3000000U)
47352 #define GPIO_ICR1_ICR12_SHIFT                    (24U)
47353 /*! ICR12 - ICR12
47354  *  0b00..Interrupt n is low-level sensitive.
47355  *  0b01..Interrupt n is high-level sensitive.
47356  *  0b10..Interrupt n is rising-edge sensitive.
47357  *  0b11..Interrupt n is falling-edge sensitive.
47358  */
47359 #define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
47360 #define GPIO_ICR1_ICR13_MASK                     (0xC000000U)
47361 #define GPIO_ICR1_ICR13_SHIFT                    (26U)
47362 /*! ICR13 - ICR13
47363  *  0b00..Interrupt n is low-level sensitive.
47364  *  0b01..Interrupt n is high-level sensitive.
47365  *  0b10..Interrupt n is rising-edge sensitive.
47366  *  0b11..Interrupt n is falling-edge sensitive.
47367  */
47368 #define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
47369 #define GPIO_ICR1_ICR14_MASK                     (0x30000000U)
47370 #define GPIO_ICR1_ICR14_SHIFT                    (28U)
47371 /*! ICR14 - ICR14
47372  *  0b00..Interrupt n is low-level sensitive.
47373  *  0b01..Interrupt n is high-level sensitive.
47374  *  0b10..Interrupt n is rising-edge sensitive.
47375  *  0b11..Interrupt n is falling-edge sensitive.
47376  */
47377 #define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
47378 #define GPIO_ICR1_ICR15_MASK                     (0xC0000000U)
47379 #define GPIO_ICR1_ICR15_SHIFT                    (30U)
47380 /*! ICR15 - ICR15
47381  *  0b00..Interrupt n is low-level sensitive.
47382  *  0b01..Interrupt n is high-level sensitive.
47383  *  0b10..Interrupt n is rising-edge sensitive.
47384  *  0b11..Interrupt n is falling-edge sensitive.
47385  */
47386 #define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
47387 /*! @} */
47388 
47389 /*! @name ICR2 - GPIO interrupt configuration register2 */
47390 /*! @{ */
47391 #define GPIO_ICR2_ICR16_MASK                     (0x3U)
47392 #define GPIO_ICR2_ICR16_SHIFT                    (0U)
47393 /*! ICR16 - ICR16
47394  *  0b00..Interrupt n is low-level sensitive.
47395  *  0b01..Interrupt n is high-level sensitive.
47396  *  0b10..Interrupt n is rising-edge sensitive.
47397  *  0b11..Interrupt n is falling-edge sensitive.
47398  */
47399 #define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
47400 #define GPIO_ICR2_ICR17_MASK                     (0xCU)
47401 #define GPIO_ICR2_ICR17_SHIFT                    (2U)
47402 /*! ICR17 - ICR17
47403  *  0b00..Interrupt n is low-level sensitive.
47404  *  0b01..Interrupt n is high-level sensitive.
47405  *  0b10..Interrupt n is rising-edge sensitive.
47406  *  0b11..Interrupt n is falling-edge sensitive.
47407  */
47408 #define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
47409 #define GPIO_ICR2_ICR18_MASK                     (0x30U)
47410 #define GPIO_ICR2_ICR18_SHIFT                    (4U)
47411 /*! ICR18 - ICR18
47412  *  0b00..Interrupt n is low-level sensitive.
47413  *  0b01..Interrupt n is high-level sensitive.
47414  *  0b10..Interrupt n is rising-edge sensitive.
47415  *  0b11..Interrupt n is falling-edge sensitive.
47416  */
47417 #define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
47418 #define GPIO_ICR2_ICR19_MASK                     (0xC0U)
47419 #define GPIO_ICR2_ICR19_SHIFT                    (6U)
47420 /*! ICR19 - ICR19
47421  *  0b00..Interrupt n is low-level sensitive.
47422  *  0b01..Interrupt n is high-level sensitive.
47423  *  0b10..Interrupt n is rising-edge sensitive.
47424  *  0b11..Interrupt n is falling-edge sensitive.
47425  */
47426 #define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
47427 #define GPIO_ICR2_ICR20_MASK                     (0x300U)
47428 #define GPIO_ICR2_ICR20_SHIFT                    (8U)
47429 /*! ICR20 - ICR20
47430  *  0b00..Interrupt n is low-level sensitive.
47431  *  0b01..Interrupt n is high-level sensitive.
47432  *  0b10..Interrupt n is rising-edge sensitive.
47433  *  0b11..Interrupt n is falling-edge sensitive.
47434  */
47435 #define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
47436 #define GPIO_ICR2_ICR21_MASK                     (0xC00U)
47437 #define GPIO_ICR2_ICR21_SHIFT                    (10U)
47438 /*! ICR21 - ICR21
47439  *  0b00..Interrupt n is low-level sensitive.
47440  *  0b01..Interrupt n is high-level sensitive.
47441  *  0b10..Interrupt n is rising-edge sensitive.
47442  *  0b11..Interrupt n is falling-edge sensitive.
47443  */
47444 #define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
47445 #define GPIO_ICR2_ICR22_MASK                     (0x3000U)
47446 #define GPIO_ICR2_ICR22_SHIFT                    (12U)
47447 /*! ICR22 - ICR22
47448  *  0b00..Interrupt n is low-level sensitive.
47449  *  0b01..Interrupt n is high-level sensitive.
47450  *  0b10..Interrupt n is rising-edge sensitive.
47451  *  0b11..Interrupt n is falling-edge sensitive.
47452  */
47453 #define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
47454 #define GPIO_ICR2_ICR23_MASK                     (0xC000U)
47455 #define GPIO_ICR2_ICR23_SHIFT                    (14U)
47456 /*! ICR23 - ICR23
47457  *  0b00..Interrupt n is low-level sensitive.
47458  *  0b01..Interrupt n is high-level sensitive.
47459  *  0b10..Interrupt n is rising-edge sensitive.
47460  *  0b11..Interrupt n is falling-edge sensitive.
47461  */
47462 #define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
47463 #define GPIO_ICR2_ICR24_MASK                     (0x30000U)
47464 #define GPIO_ICR2_ICR24_SHIFT                    (16U)
47465 /*! ICR24 - ICR24
47466  *  0b00..Interrupt n is low-level sensitive.
47467  *  0b01..Interrupt n is high-level sensitive.
47468  *  0b10..Interrupt n is rising-edge sensitive.
47469  *  0b11..Interrupt n is falling-edge sensitive.
47470  */
47471 #define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
47472 #define GPIO_ICR2_ICR25_MASK                     (0xC0000U)
47473 #define GPIO_ICR2_ICR25_SHIFT                    (18U)
47474 /*! ICR25 - ICR25
47475  *  0b00..Interrupt n is low-level sensitive.
47476  *  0b01..Interrupt n is high-level sensitive.
47477  *  0b10..Interrupt n is rising-edge sensitive.
47478  *  0b11..Interrupt n is falling-edge sensitive.
47479  */
47480 #define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
47481 #define GPIO_ICR2_ICR26_MASK                     (0x300000U)
47482 #define GPIO_ICR2_ICR26_SHIFT                    (20U)
47483 /*! ICR26 - ICR26
47484  *  0b00..Interrupt n is low-level sensitive.
47485  *  0b01..Interrupt n is high-level sensitive.
47486  *  0b10..Interrupt n is rising-edge sensitive.
47487  *  0b11..Interrupt n is falling-edge sensitive.
47488  */
47489 #define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
47490 #define GPIO_ICR2_ICR27_MASK                     (0xC00000U)
47491 #define GPIO_ICR2_ICR27_SHIFT                    (22U)
47492 /*! ICR27 - ICR27
47493  *  0b00..Interrupt n is low-level sensitive.
47494  *  0b01..Interrupt n is high-level sensitive.
47495  *  0b10..Interrupt n is rising-edge sensitive.
47496  *  0b11..Interrupt n is falling-edge sensitive.
47497  */
47498 #define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
47499 #define GPIO_ICR2_ICR28_MASK                     (0x3000000U)
47500 #define GPIO_ICR2_ICR28_SHIFT                    (24U)
47501 /*! ICR28 - ICR28
47502  *  0b00..Interrupt n is low-level sensitive.
47503  *  0b01..Interrupt n is high-level sensitive.
47504  *  0b10..Interrupt n is rising-edge sensitive.
47505  *  0b11..Interrupt n is falling-edge sensitive.
47506  */
47507 #define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
47508 #define GPIO_ICR2_ICR29_MASK                     (0xC000000U)
47509 #define GPIO_ICR2_ICR29_SHIFT                    (26U)
47510 /*! ICR29 - ICR29
47511  *  0b00..Interrupt n is low-level sensitive.
47512  *  0b01..Interrupt n is high-level sensitive.
47513  *  0b10..Interrupt n is rising-edge sensitive.
47514  *  0b11..Interrupt n is falling-edge sensitive.
47515  */
47516 #define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
47517 #define GPIO_ICR2_ICR30_MASK                     (0x30000000U)
47518 #define GPIO_ICR2_ICR30_SHIFT                    (28U)
47519 /*! ICR30 - ICR30
47520  *  0b00..Interrupt n is low-level sensitive.
47521  *  0b01..Interrupt n is high-level sensitive.
47522  *  0b10..Interrupt n is rising-edge sensitive.
47523  *  0b11..Interrupt n is falling-edge sensitive.
47524  */
47525 #define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
47526 #define GPIO_ICR2_ICR31_MASK                     (0xC0000000U)
47527 #define GPIO_ICR2_ICR31_SHIFT                    (30U)
47528 /*! ICR31 - ICR31
47529  *  0b00..Interrupt n is low-level sensitive.
47530  *  0b01..Interrupt n is high-level sensitive.
47531  *  0b10..Interrupt n is rising-edge sensitive.
47532  *  0b11..Interrupt n is falling-edge sensitive.
47533  */
47534 #define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
47535 /*! @} */
47536 
47537 /*! @name IMR - GPIO interrupt mask register */
47538 /*! @{ */
47539 #define GPIO_IMR_IMR_MASK                        (0xFFFFFFFFU)
47540 #define GPIO_IMR_IMR_SHIFT                       (0U)
47541 /*! IMR - IMR
47542  */
47543 #define GPIO_IMR_IMR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
47544 /*! @} */
47545 
47546 /*! @name ISR - GPIO interrupt status register */
47547 /*! @{ */
47548 #define GPIO_ISR_ISR_MASK                        (0xFFFFFFFFU)
47549 #define GPIO_ISR_ISR_SHIFT                       (0U)
47550 /*! ISR - ISR
47551  */
47552 #define GPIO_ISR_ISR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
47553 /*! @} */
47554 
47555 /*! @name EDGE_SEL - GPIO edge select register */
47556 /*! @{ */
47557 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK         (0xFFFFFFFFU)
47558 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT        (0U)
47559 /*! GPIO_EDGE_SEL - GPIO_EDGE_SEL
47560  */
47561 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
47562 /*! @} */
47563 
47564 /*! @name DR_SET - GPIO data register SET */
47565 /*! @{ */
47566 #define GPIO_DR_SET_DR_SET_MASK                  (0xFFFFFFFFU)
47567 #define GPIO_DR_SET_DR_SET_SHIFT                 (0U)
47568 /*! DR_SET - DR_SET
47569  */
47570 #define GPIO_DR_SET_DR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
47571 /*! @} */
47572 
47573 /*! @name DR_CLEAR - GPIO data register CLEAR */
47574 /*! @{ */
47575 #define GPIO_DR_CLEAR_DR_CLEAR_MASK              (0xFFFFFFFFU)
47576 #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT             (0U)
47577 /*! DR_CLEAR - DR_CLEAR
47578  */
47579 #define GPIO_DR_CLEAR_DR_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
47580 /*! @} */
47581 
47582 /*! @name DR_TOGGLE - GPIO data register TOGGLE */
47583 /*! @{ */
47584 #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK            (0xFFFFFFFFU)
47585 #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT           (0U)
47586 /*! DR_TOGGLE - DR_TOGGLE
47587  */
47588 #define GPIO_DR_TOGGLE_DR_TOGGLE(x)              (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
47589 /*! @} */
47590 
47591 
47592 /*!
47593  * @}
47594  */ /* end of group GPIO_Register_Masks */
47595 
47596 
47597 /* GPIO - Peripheral instance base addresses */
47598 /** Peripheral CI_PI__GPIO base address */
47599 #define CI_PI__GPIO_BASE                         (0x58262000u)
47600 /** Peripheral CI_PI__GPIO base pointer */
47601 #define CI_PI__GPIO                              ((GPIO_Type *)CI_PI__GPIO_BASE)
47602 /** Peripheral DI_MIPI_DSI_LVDS_0__GPIO base address */
47603 #define DI_MIPI_DSI_LVDS_0__GPIO_BASE            (0x56222000u)
47604 /** Peripheral DI_MIPI_DSI_LVDS_0__GPIO base pointer */
47605 #define DI_MIPI_DSI_LVDS_0__GPIO                 ((GPIO_Type *)DI_MIPI_DSI_LVDS_0__GPIO_BASE)
47606 /** Peripheral DI_MIPI_DSI_LVDS_1__GPIO base address */
47607 #define DI_MIPI_DSI_LVDS_1__GPIO_BASE            (0x56242000u)
47608 /** Peripheral DI_MIPI_DSI_LVDS_1__GPIO base pointer */
47609 #define DI_MIPI_DSI_LVDS_1__GPIO                 ((GPIO_Type *)DI_MIPI_DSI_LVDS_1__GPIO_BASE)
47610 /** Peripheral HSIO__GPIO base address */
47611 #define HSIO__GPIO_BASE                          (0x5F170000u)
47612 /** Peripheral HSIO__GPIO base pointer */
47613 #define HSIO__GPIO                               ((GPIO_Type *)HSIO__GPIO_BASE)
47614 /** Peripheral LSIO__GPIO0 base address */
47615 #define LSIO__GPIO0_BASE                         (0x5D080000u)
47616 /** Peripheral LSIO__GPIO0 base pointer */
47617 #define LSIO__GPIO0                              ((GPIO_Type *)LSIO__GPIO0_BASE)
47618 /** Peripheral LSIO__GPIO1 base address */
47619 #define LSIO__GPIO1_BASE                         (0x5D090000u)
47620 /** Peripheral LSIO__GPIO1 base pointer */
47621 #define LSIO__GPIO1                              ((GPIO_Type *)LSIO__GPIO1_BASE)
47622 /** Peripheral LSIO__GPIO2 base address */
47623 #define LSIO__GPIO2_BASE                         (0x5D0A0000u)
47624 /** Peripheral LSIO__GPIO2 base pointer */
47625 #define LSIO__GPIO2                              ((GPIO_Type *)LSIO__GPIO2_BASE)
47626 /** Peripheral LSIO__GPIO3 base address */
47627 #define LSIO__GPIO3_BASE                         (0x5D0B0000u)
47628 /** Peripheral LSIO__GPIO3 base pointer */
47629 #define LSIO__GPIO3                              ((GPIO_Type *)LSIO__GPIO3_BASE)
47630 /** Peripheral LSIO__GPIO4 base address */
47631 #define LSIO__GPIO4_BASE                         (0x5D0C0000u)
47632 /** Peripheral LSIO__GPIO4 base pointer */
47633 #define LSIO__GPIO4                              ((GPIO_Type *)LSIO__GPIO4_BASE)
47634 /** Peripheral LSIO__GPIO5 base address */
47635 #define LSIO__GPIO5_BASE                         (0x5D0D0000u)
47636 /** Peripheral LSIO__GPIO5 base pointer */
47637 #define LSIO__GPIO5                              ((GPIO_Type *)LSIO__GPIO5_BASE)
47638 /** Peripheral LSIO__GPIO6 base address */
47639 #define LSIO__GPIO6_BASE                         (0x5D0E0000u)
47640 /** Peripheral LSIO__GPIO6 base pointer */
47641 #define LSIO__GPIO6                              ((GPIO_Type *)LSIO__GPIO6_BASE)
47642 /** Peripheral LSIO__GPIO7 base address */
47643 #define LSIO__GPIO7_BASE                         (0x5D0F0000u)
47644 /** Peripheral LSIO__GPIO7 base pointer */
47645 #define LSIO__GPIO7                              ((GPIO_Type *)LSIO__GPIO7_BASE)
47646 /** Peripheral MIPI_CSI__GPIO base address */
47647 #define MIPI_CSI__GPIO_BASE                      (0x58222000u)
47648 /** Peripheral MIPI_CSI__GPIO base pointer */
47649 #define MIPI_CSI__GPIO                           ((GPIO_Type *)MIPI_CSI__GPIO_BASE)
47650 /** Array initializer of GPIO peripheral base addresses */
47651 #define GPIO_BASE_ADDRS                          { CI_PI__GPIO_BASE, DI_MIPI_DSI_LVDS_0__GPIO_BASE, DI_MIPI_DSI_LVDS_1__GPIO_BASE, HSIO__GPIO_BASE, LSIO__GPIO0_BASE, LSIO__GPIO1_BASE, LSIO__GPIO2_BASE, LSIO__GPIO3_BASE, LSIO__GPIO4_BASE, LSIO__GPIO5_BASE, LSIO__GPIO6_BASE, LSIO__GPIO7_BASE, MIPI_CSI__GPIO_BASE }
47652 /** Array initializer of GPIO peripheral base pointers */
47653 #define GPIO_BASE_PTRS                           { CI_PI__GPIO, DI_MIPI_DSI_LVDS_0__GPIO, DI_MIPI_DSI_LVDS_1__GPIO, HSIO__GPIO, LSIO__GPIO0, LSIO__GPIO1, LSIO__GPIO2, LSIO__GPIO3, LSIO__GPIO4, LSIO__GPIO5, LSIO__GPIO6, LSIO__GPIO7, MIPI_CSI__GPIO }
47654 /** Interrupt vectors for the GPIO peripheral type */
47655 #define GPIO_IRQS                                { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LSIO_GPIO_INT0_IRQn, LSIO_GPIO_INT1_IRQn, LSIO_GPIO_INT2_IRQn, LSIO_GPIO_INT3_IRQn, LSIO_GPIO_INT4_IRQn, LSIO_GPIO_INT5_IRQn, LSIO_GPIO_INT6_IRQn, LSIO_GPIO_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
47656 
47657 /*!
47658  * @}
47659  */ /* end of group GPIO_Peripheral_Access_Layer */
47660 
47661 
47662 /* ----------------------------------------------------------------------------
47663    -- GPMI Peripheral Access Layer
47664    ---------------------------------------------------------------------------- */
47665 
47666 /*!
47667  * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer
47668  * @{
47669  */
47670 
47671 /** GPMI - Register Layout Typedef */
47672 typedef struct {
47673   struct {                                         /* offset: 0x0 */
47674     __IO uint32_t RW;                                /**< GPMI Control Register 0 Description, offset: 0x0 */
47675     __IO uint32_t SET;                               /**< GPMI Control Register 0 Description, offset: 0x4 */
47676     __IO uint32_t CLR;                               /**< GPMI Control Register 0 Description, offset: 0x8 */
47677     __IO uint32_t TOG;                               /**< GPMI Control Register 0 Description, offset: 0xC */
47678   } CTRL0;
47679   __IO uint32_t COMPARE;                           /**< GPMI Compare Register Description, offset: 0x10 */
47680        uint8_t RESERVED_0[12];
47681   struct {                                         /* offset: 0x20 */
47682     __IO uint32_t RW;                                /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */
47683     __IO uint32_t SET;                               /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */
47684     __IO uint32_t CLR;                               /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */
47685     __IO uint32_t TOG;                               /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */
47686   } ECCCTRL;
47687   __IO uint32_t ECCCOUNT;                          /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */
47688        uint8_t RESERVED_1[12];
47689   __IO uint32_t PAYLOAD;                           /**< GPMI Payload Address Register Description, offset: 0x40 */
47690        uint8_t RESERVED_2[12];
47691   __IO uint32_t AUXILIARY;                         /**< GPMI Auxiliary Address Register Description, offset: 0x50 */
47692        uint8_t RESERVED_3[12];
47693   struct {                                         /* offset: 0x60 */
47694     __IO uint32_t RW;                                /**< GPMI Control Register 1 Description, offset: 0x60 */
47695     __IO uint32_t SET;                               /**< GPMI Control Register 1 Description, offset: 0x64 */
47696     __IO uint32_t CLR;                               /**< GPMI Control Register 1 Description, offset: 0x68 */
47697     __IO uint32_t TOG;                               /**< GPMI Control Register 1 Description, offset: 0x6C */
47698   } CTRL1;
47699   __IO uint32_t TIMING0;                           /**< GPMI Timing Register 0 Description, offset: 0x70 */
47700        uint8_t RESERVED_4[12];
47701   __IO uint32_t TIMING1;                           /**< GPMI Timing Register 1 Description, offset: 0x80 */
47702        uint8_t RESERVED_5[12];
47703   __IO uint32_t TIMING2;                           /**< GPMI Timing Register 2 Description, offset: 0x90 */
47704        uint8_t RESERVED_6[12];
47705   __IO uint32_t DATA;                              /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */
47706        uint8_t RESERVED_7[12];
47707   __I  uint32_t STAT;                              /**< GPMI Status Register Description, offset: 0xB0 */
47708        uint8_t RESERVED_8[12];
47709   __I  uint32_t DEBUGr;                            /**< GPMI Debug Information Register Description, offset: 0xC0 */
47710        uint8_t RESERVED_9[12];
47711   __I  uint32_t VERSION;                           /**< GPMI Version Register Description, offset: 0xD0 */
47712        uint8_t RESERVED_10[12];
47713   __IO uint32_t DEBUG2;                            /**< GPMI Debug2 Information Register Description, offset: 0xE0 */
47714        uint8_t RESERVED_11[12];
47715   __I  uint32_t DEBUG3;                            /**< GPMI Debug3 Information Register Description, offset: 0xF0 */
47716        uint8_t RESERVED_12[12];
47717   __IO uint32_t READ_DDR_DLL_CTRL;                 /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */
47718        uint8_t RESERVED_13[12];
47719   __IO uint32_t WRITE_DDR_DLL_CTRL;                /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */
47720        uint8_t RESERVED_14[12];
47721   __I  uint32_t READ_DDR_DLL_STS;                  /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */
47722        uint8_t RESERVED_15[12];
47723   __I  uint32_t WRITE_DDR_DLL_STS;                 /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */
47724        uint8_t RESERVED_16[12];
47725   __IO uint32_t TIMING3;                           /**< GPMI Timing Register 3 Description, offset: 0x140 */
47726        uint8_t RESERVED_17[12];
47727   __IO uint32_t CTRL2;                             /**< GPMI Control Register 2 Description, offset: 0x150 */
47728 } GPMI_Type;
47729 
47730 /* ----------------------------------------------------------------------------
47731    -- GPMI Register Masks
47732    ---------------------------------------------------------------------------- */
47733 
47734 /*!
47735  * @addtogroup GPMI_Register_Masks GPMI Register Masks
47736  * @{
47737  */
47738 
47739 /*! @name CTRL0 - GPMI Control Register 0 Description */
47740 /*! @{ */
47741 #define GPMI_CTRL0_XFER_COUNT_MASK               (0xFFFFU)
47742 #define GPMI_CTRL0_XFER_COUNT_SHIFT              (0U)
47743 /*! XFER_COUNT - XFER_COUNT
47744  */
47745 #define GPMI_CTRL0_XFER_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK)
47746 #define GPMI_CTRL0_ADDRESS_INCREMENT_MASK        (0x10000U)
47747 #define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT       (16U)
47748 /*! ADDRESS_INCREMENT - ADDRESS_INCREMENT
47749  */
47750 #define GPMI_CTRL0_ADDRESS_INCREMENT(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK)
47751 #define GPMI_CTRL0_ADDRESS_MASK                  (0xE0000U)
47752 #define GPMI_CTRL0_ADDRESS_SHIFT                 (17U)
47753 /*! ADDRESS - ADDRESS
47754  */
47755 #define GPMI_CTRL0_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK)
47756 #define GPMI_CTRL0_CS_MASK                       (0x700000U)
47757 #define GPMI_CTRL0_CS_SHIFT                      (20U)
47758 /*! CS - CS
47759  */
47760 #define GPMI_CTRL0_CS(x)                         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK)
47761 #define GPMI_CTRL0_WORD_LENGTH_MASK              (0x800000U)
47762 #define GPMI_CTRL0_WORD_LENGTH_SHIFT             (23U)
47763 /*! WORD_LENGTH - WORD_LENGTH
47764  *  0b0..Reserved.
47765  *  0b1..8-bit Data Bus mode.
47766  */
47767 #define GPMI_CTRL0_WORD_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK)
47768 #define GPMI_CTRL0_COMMAND_MODE_MASK             (0x3000000U)
47769 #define GPMI_CTRL0_COMMAND_MODE_SHIFT            (24U)
47770 /*! COMMAND_MODE - COMMAND_MODE
47771  *  0b00..Write mode.
47772  *  0b01..Read Mode.
47773  *  0b10..Read and Compare Mode (setting sense flop).
47774  *  0b11..Wait for Ready.
47775  */
47776 #define GPMI_CTRL0_COMMAND_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK)
47777 #define GPMI_CTRL0_UDMA_MASK                     (0x4000000U)
47778 #define GPMI_CTRL0_UDMA_SHIFT                    (26U)
47779 /*! UDMA - UDMA
47780  *  0b0..Use ATA-PIO mode on the external bus.
47781  *  0b1..Use ATA-Ultra DMA mode on the external bus.
47782  */
47783 #define GPMI_CTRL0_UDMA(x)                       (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK)
47784 #define GPMI_CTRL0_LOCK_CS_MASK                  (0x8000000U)
47785 #define GPMI_CTRL0_LOCK_CS_SHIFT                 (27U)
47786 /*! LOCK_CS - LOCK_CS
47787  */
47788 #define GPMI_CTRL0_LOCK_CS(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK)
47789 #define GPMI_CTRL0_WR_DATA_EN_MASK               (0x10000000U)
47790 #define GPMI_CTRL0_WR_DATA_EN_SHIFT              (28U)
47791 /*! WR_DATA_EN - WR_DATA_EN
47792  */
47793 #define GPMI_CTRL0_WR_DATA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WR_DATA_EN_SHIFT)) & GPMI_CTRL0_WR_DATA_EN_MASK)
47794 #define GPMI_CTRL0_RUN_MASK                      (0x20000000U)
47795 #define GPMI_CTRL0_RUN_SHIFT                     (29U)
47796 /*! RUN - RUN
47797  */
47798 #define GPMI_CTRL0_RUN(x)                        (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK)
47799 #define GPMI_CTRL0_CLKGATE_MASK                  (0x40000000U)
47800 #define GPMI_CTRL0_CLKGATE_SHIFT                 (30U)
47801 /*! CLKGATE - CLKGATE
47802  */
47803 #define GPMI_CTRL0_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK)
47804 #define GPMI_CTRL0_SFTRST_MASK                   (0x80000000U)
47805 #define GPMI_CTRL0_SFTRST_SHIFT                  (31U)
47806 /*! SFTRST - SFTRST
47807  */
47808 #define GPMI_CTRL0_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK)
47809 /*! @} */
47810 
47811 /*! @name COMPARE - GPMI Compare Register Description */
47812 /*! @{ */
47813 #define GPMI_COMPARE_REFERENCE_MASK              (0xFFFFU)
47814 #define GPMI_COMPARE_REFERENCE_SHIFT             (0U)
47815 /*! REFERENCE - REFERENCE
47816  */
47817 #define GPMI_COMPARE_REFERENCE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK)
47818 #define GPMI_COMPARE_MASK_MASK                   (0xFFFF0000U)
47819 #define GPMI_COMPARE_MASK_SHIFT                  (16U)
47820 /*! MASK - MASK
47821  */
47822 #define GPMI_COMPARE_MASK(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK)
47823 /*! @} */
47824 
47825 /*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */
47826 /*! @{ */
47827 #define GPMI_ECCCTRL_BUFFER_MASK_MASK            (0x1FFU)
47828 #define GPMI_ECCCTRL_BUFFER_MASK_SHIFT           (0U)
47829 /*! BUFFER_MASK - BUFFER_MASK
47830  */
47831 #define GPMI_ECCCTRL_BUFFER_MASK(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK)
47832 #define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK        (0x600U)
47833 #define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT       (9U)
47834 /*! RANDOMIZER_TYPE - RANDOMIZER_TYPE
47835  *  0b00..Type 0
47836  *  0b01..Type 1
47837  *  0b10..Type 2
47838  */
47839 #define GPMI_ECCCTRL_RANDOMIZER_TYPE(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK)
47840 #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK      (0x800U)
47841 #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT     (11U)
47842 /*! RANDOMIZER_ENABLE - RANDOMIZER_ENABLE
47843  *  0b0..disable
47844  *  0b1..enable
47845  */
47846 #define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK)
47847 #define GPMI_ECCCTRL_ENABLE_ECC_MASK             (0x1000U)
47848 #define GPMI_ECCCTRL_ENABLE_ECC_SHIFT            (12U)
47849 /*! ENABLE_ECC - ENABLE_ECC
47850  */
47851 #define GPMI_ECCCTRL_ENABLE_ECC(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK)
47852 #define GPMI_ECCCTRL_ECC_CMD_MASK                (0x6000U)
47853 #define GPMI_ECCCTRL_ECC_CMD_SHIFT               (13U)
47854 /*! ECC_CMD - ECC_CMD
47855  */
47856 #define GPMI_ECCCTRL_ECC_CMD(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK)
47857 #define GPMI_ECCCTRL_RSVD2_MASK                  (0x8000U)
47858 #define GPMI_ECCCTRL_RSVD2_SHIFT                 (15U)
47859 /*! RSVD2 - RSVD2
47860  */
47861 #define GPMI_ECCCTRL_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK)
47862 #define GPMI_ECCCTRL_HANDLE_MASK                 (0xFFFF0000U)
47863 #define GPMI_ECCCTRL_HANDLE_SHIFT                (16U)
47864 /*! HANDLE - HANDLE
47865  */
47866 #define GPMI_ECCCTRL_HANDLE(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK)
47867 /*! @} */
47868 
47869 /*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */
47870 /*! @{ */
47871 #define GPMI_ECCCOUNT_COUNT_MASK                 (0xFFFFU)
47872 #define GPMI_ECCCOUNT_COUNT_SHIFT                (0U)
47873 /*! COUNT - COUNT
47874  */
47875 #define GPMI_ECCCOUNT_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK)
47876 #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK       (0xFF0000U)
47877 #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT      (16U)
47878 /*! RANDOMIZER_PAGE - RANDOMIZER_PAGE
47879  */
47880 #define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK)
47881 /*! @} */
47882 
47883 /*! @name PAYLOAD - GPMI Payload Address Register Description */
47884 /*! @{ */
47885 #define GPMI_PAYLOAD_RSVD0_MASK                  (0x3U)
47886 #define GPMI_PAYLOAD_RSVD0_SHIFT                 (0U)
47887 /*! RSVD0 - RSVD0
47888  */
47889 #define GPMI_PAYLOAD_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK)
47890 #define GPMI_PAYLOAD_ADDRESS_MASK                (0xFFFFFFFCU)
47891 #define GPMI_PAYLOAD_ADDRESS_SHIFT               (2U)
47892 /*! ADDRESS - ADDRESS
47893  */
47894 #define GPMI_PAYLOAD_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK)
47895 /*! @} */
47896 
47897 /*! @name AUXILIARY - GPMI Auxiliary Address Register Description */
47898 /*! @{ */
47899 #define GPMI_AUXILIARY_RSVD0_MASK                (0x3U)
47900 #define GPMI_AUXILIARY_RSVD0_SHIFT               (0U)
47901 /*! RSVD0 - RSVD0
47902  */
47903 #define GPMI_AUXILIARY_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK)
47904 #define GPMI_AUXILIARY_ADDRESS_MASK              (0xFFFFFFFCU)
47905 #define GPMI_AUXILIARY_ADDRESS_SHIFT             (2U)
47906 /*! ADDRESS - ADDRESS
47907  */
47908 #define GPMI_AUXILIARY_ADDRESS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK)
47909 /*! @} */
47910 
47911 /*! @name CTRL1 - GPMI Control Register 1 Description */
47912 /*! @{ */
47913 #define GPMI_CTRL1_GPMI_MODE_MASK                (0x1U)
47914 #define GPMI_CTRL1_GPMI_MODE_SHIFT               (0U)
47915 /*! GPMI_MODE - GPMI_MODE
47916  *  0b0..NAND mode.
47917  *  0b1..ATA mode.
47918  */
47919 #define GPMI_CTRL1_GPMI_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK)
47920 #define GPMI_CTRL1_CAMERA_MODE_MASK              (0x2U)
47921 #define GPMI_CTRL1_CAMERA_MODE_SHIFT             (1U)
47922 /*! CAMERA_MODE - CAMERA_MODE
47923  */
47924 #define GPMI_CTRL1_CAMERA_MODE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK)
47925 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK      (0x4U)
47926 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT     (2U)
47927 /*! ATA_IRQRDY_POLARITY - ATA_IRQRDY_POLARITY
47928  *  0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
47929  *  0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
47930  */
47931 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK)
47932 #define GPMI_CTRL1_DEV_RESET_MASK                (0x8U)
47933 #define GPMI_CTRL1_DEV_RESET_SHIFT               (3U)
47934 /*! DEV_RESET - DEV_RESET
47935  *  0b0..NANDF_WP_B pin is held low (asserted).
47936  *  0b1..NANDF_WP_B pin is held high (de-asserted).
47937  */
47938 #define GPMI_CTRL1_DEV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK)
47939 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
47940 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
47941 /*! ABORT_WAIT_FOR_READY_CHANNEL - ABORT_WAIT_FOR_READY_CHANNEL
47942  */
47943 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
47944 #define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK       (0x80U)
47945 #define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT      (7U)
47946 /*! ABORT_WAIT_REQUEST - ABORT_WAIT_REQUEST
47947  */
47948 #define GPMI_CTRL1_ABORT_WAIT_REQUEST(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK)
47949 #define GPMI_CTRL1_BURST_EN_MASK                 (0x100U)
47950 #define GPMI_CTRL1_BURST_EN_SHIFT                (8U)
47951 /*! BURST_EN - BURST_EN
47952  */
47953 #define GPMI_CTRL1_BURST_EN(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK)
47954 #define GPMI_CTRL1_TIMEOUT_IRQ_MASK              (0x200U)
47955 #define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT             (9U)
47956 /*! TIMEOUT_IRQ - TIMEOUT_IRQ
47957  */
47958 #define GPMI_CTRL1_TIMEOUT_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK)
47959 #define GPMI_CTRL1_DEV_IRQ_MASK                  (0x400U)
47960 #define GPMI_CTRL1_DEV_IRQ_SHIFT                 (10U)
47961 /*! DEV_IRQ - DEV_IRQ
47962  */
47963 #define GPMI_CTRL1_DEV_IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK)
47964 #define GPMI_CTRL1_DMA2ECC_MODE_MASK             (0x800U)
47965 #define GPMI_CTRL1_DMA2ECC_MODE_SHIFT            (11U)
47966 /*! DMA2ECC_MODE - DMA2ECC_MODE
47967  */
47968 #define GPMI_CTRL1_DMA2ECC_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK)
47969 #define GPMI_CTRL1_RDN_DELAY_MASK                (0xF000U)
47970 #define GPMI_CTRL1_RDN_DELAY_SHIFT               (12U)
47971 /*! RDN_DELAY - RDN_DELAY
47972  */
47973 #define GPMI_CTRL1_RDN_DELAY(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK)
47974 #define GPMI_CTRL1_HALF_PERIOD_MASK              (0x10000U)
47975 #define GPMI_CTRL1_HALF_PERIOD_SHIFT             (16U)
47976 /*! HALF_PERIOD - HALF_PERIOD
47977  */
47978 #define GPMI_CTRL1_HALF_PERIOD(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK)
47979 #define GPMI_CTRL1_DLL_ENABLE_MASK               (0x20000U)
47980 #define GPMI_CTRL1_DLL_ENABLE_SHIFT              (17U)
47981 /*! DLL_ENABLE - DLL_ENABLE
47982  */
47983 #define GPMI_CTRL1_DLL_ENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK)
47984 #define GPMI_CTRL1_BCH_MODE_MASK                 (0x40000U)
47985 #define GPMI_CTRL1_BCH_MODE_SHIFT                (18U)
47986 /*! BCH_MODE - BCH_MODE
47987  */
47988 #define GPMI_CTRL1_BCH_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK)
47989 #define GPMI_CTRL1_GANGED_RDYBUSY_MASK           (0x80000U)
47990 #define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT          (19U)
47991 /*! GANGED_RDYBUSY - GANGED_RDYBUSY
47992  */
47993 #define GPMI_CTRL1_GANGED_RDYBUSY(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK)
47994 #define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK           (0x100000U)
47995 #define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT          (20U)
47996 /*! TIMEOUT_IRQ_EN - TIMEOUT_IRQ_EN
47997  */
47998 #define GPMI_CTRL1_TIMEOUT_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK)
47999 #define GPMI_CTRL1_RSVD1_MASK                    (0x200000U)
48000 #define GPMI_CTRL1_RSVD1_SHIFT                   (21U)
48001 /*! RSVD1 - RSVD1
48002  */
48003 #define GPMI_CTRL1_RSVD1(x)                      (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RSVD1_SHIFT)) & GPMI_CTRL1_RSVD1_MASK)
48004 #define GPMI_CTRL1_WRN_DLY_SEL_MASK              (0xC00000U)
48005 #define GPMI_CTRL1_WRN_DLY_SEL_SHIFT             (22U)
48006 /*! WRN_DLY_SEL - WRN_DLY_SEL
48007  */
48008 #define GPMI_CTRL1_WRN_DLY_SEL(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK)
48009 #define GPMI_CTRL1_DECOUPLE_CS_MASK              (0x1000000U)
48010 #define GPMI_CTRL1_DECOUPLE_CS_SHIFT             (24U)
48011 /*! DECOUPLE_CS - DECOUPLE_CS
48012  */
48013 #define GPMI_CTRL1_DECOUPLE_CS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK)
48014 #define GPMI_CTRL1_SSYNCMODE_MASK                (0x2000000U)
48015 #define GPMI_CTRL1_SSYNCMODE_SHIFT               (25U)
48016 /*! SSYNCMODE - SSYNCMODE
48017  */
48018 #define GPMI_CTRL1_SSYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK)
48019 #define GPMI_CTRL1_UPDATE_CS_MASK                (0x4000000U)
48020 #define GPMI_CTRL1_UPDATE_CS_SHIFT               (26U)
48021 /*! UPDATE_CS - UPDATE_CS
48022  */
48023 #define GPMI_CTRL1_UPDATE_CS(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK)
48024 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK         (0x8000000U)
48025 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT        (27U)
48026 /*! GPMI_CLK_DIV2_EN - GPMI_CLK_DIV2_EN
48027  *  0b0..internal factor-2 clock divider is disabled
48028  *  0b1..internal factor-2 clock divider is enabled.
48029  */
48030 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK)
48031 #define GPMI_CTRL1_TOGGLE_MODE_MASK              (0x10000000U)
48032 #define GPMI_CTRL1_TOGGLE_MODE_SHIFT             (28U)
48033 /*! TOGGLE_MODE - TOGGLE_MODE
48034  */
48035 #define GPMI_CTRL1_TOGGLE_MODE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK)
48036 #define GPMI_CTRL1_WRITE_CLK_STOP_MASK           (0x20000000U)
48037 #define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT          (29U)
48038 /*! WRITE_CLK_STOP - WRITE_CLK_STOP
48039  */
48040 #define GPMI_CTRL1_WRITE_CLK_STOP(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK)
48041 #define GPMI_CTRL1_SSYNC_CLK_STOP_MASK           (0x40000000U)
48042 #define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT          (30U)
48043 /*! SSYNC_CLK_STOP - SSYNC_CLK_STOP
48044  */
48045 #define GPMI_CTRL1_SSYNC_CLK_STOP(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK)
48046 #define GPMI_CTRL1_DEV_CLK_STOP_MASK             (0x80000000U)
48047 #define GPMI_CTRL1_DEV_CLK_STOP_SHIFT            (31U)
48048 /*! DEV_CLK_STOP - DEV_CLK_STOP
48049  */
48050 #define GPMI_CTRL1_DEV_CLK_STOP(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK)
48051 /*! @} */
48052 
48053 /*! @name TIMING0 - GPMI Timing Register 0 Description */
48054 /*! @{ */
48055 #define GPMI_TIMING0_DATA_SETUP_MASK             (0xFFU)
48056 #define GPMI_TIMING0_DATA_SETUP_SHIFT            (0U)
48057 /*! DATA_SETUP - DATA_SETUP
48058  */
48059 #define GPMI_TIMING0_DATA_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK)
48060 #define GPMI_TIMING0_DATA_HOLD_MASK              (0xFF00U)
48061 #define GPMI_TIMING0_DATA_HOLD_SHIFT             (8U)
48062 /*! DATA_HOLD - DATA_HOLD
48063  */
48064 #define GPMI_TIMING0_DATA_HOLD(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK)
48065 #define GPMI_TIMING0_ADDRESS_SETUP_MASK          (0xFF0000U)
48066 #define GPMI_TIMING0_ADDRESS_SETUP_SHIFT         (16U)
48067 /*! ADDRESS_SETUP - ADDRESS_SETUP
48068  */
48069 #define GPMI_TIMING0_ADDRESS_SETUP(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK)
48070 #define GPMI_TIMING0_RSVD1_MASK                  (0xFF000000U)
48071 #define GPMI_TIMING0_RSVD1_SHIFT                 (24U)
48072 /*! RSVD1 - RSVD1
48073  */
48074 #define GPMI_TIMING0_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK)
48075 /*! @} */
48076 
48077 /*! @name TIMING1 - GPMI Timing Register 1 Description */
48078 /*! @{ */
48079 #define GPMI_TIMING1_RSVD1_MASK                  (0xFFFFU)
48080 #define GPMI_TIMING1_RSVD1_SHIFT                 (0U)
48081 /*! RSVD1 - RSVD1
48082  */
48083 #define GPMI_TIMING1_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK)
48084 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK    (0xFFFF0000U)
48085 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT   (16U)
48086 /*! DEVICE_BUSY_TIMEOUT - DEVICE_BUSY_TIMEOUT
48087  */
48088 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK)
48089 /*! @} */
48090 
48091 /*! @name TIMING2 - GPMI Timing Register 2 Description */
48092 /*! @{ */
48093 #define GPMI_TIMING2_DATA_PAUSE_MASK             (0xFU)
48094 #define GPMI_TIMING2_DATA_PAUSE_SHIFT            (0U)
48095 /*! DATA_PAUSE - DATA_PAUSE
48096  */
48097 #define GPMI_TIMING2_DATA_PAUSE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK)
48098 #define GPMI_TIMING2_CMDADD_PAUSE_MASK           (0xF0U)
48099 #define GPMI_TIMING2_CMDADD_PAUSE_SHIFT          (4U)
48100 /*! CMDADD_PAUSE - CMDADD_PAUSE
48101  */
48102 #define GPMI_TIMING2_CMDADD_PAUSE(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK)
48103 #define GPMI_TIMING2_POSTAMBLE_DELAY_MASK        (0xF00U)
48104 #define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT       (8U)
48105 /*! POSTAMBLE_DELAY - POSTAMBLE_DELAY
48106  */
48107 #define GPMI_TIMING2_POSTAMBLE_DELAY(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK)
48108 #define GPMI_TIMING2_PREAMBLE_DELAY_MASK         (0xF000U)
48109 #define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT        (12U)
48110 /*! PREAMBLE_DELAY - PREAMBLE_DELAY
48111  */
48112 #define GPMI_TIMING2_PREAMBLE_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK)
48113 #define GPMI_TIMING2_CE_DELAY_MASK               (0x1F0000U)
48114 #define GPMI_TIMING2_CE_DELAY_SHIFT              (16U)
48115 /*! CE_DELAY - CE_DELAY
48116  */
48117 #define GPMI_TIMING2_CE_DELAY(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK)
48118 #define GPMI_TIMING2_RSVD0_MASK                  (0xE00000U)
48119 #define GPMI_TIMING2_RSVD0_SHIFT                 (21U)
48120 /*! RSVD0 - RSVD0
48121  */
48122 #define GPMI_TIMING2_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK)
48123 #define GPMI_TIMING2_READ_LATENCY_MASK           (0x7000000U)
48124 #define GPMI_TIMING2_READ_LATENCY_SHIFT          (24U)
48125 /*! READ_LATENCY - READ_LATENCY
48126  *  0b000..READ LATENCY is 0
48127  *  0b001..READ LATENCY is 1
48128  *  0b010..READ LATENCY is 2
48129  *  0b011..READ LATENCY is 3
48130  *  0b100..READ LATENCY is 4
48131  *  0b101..READ LATENCY is 5
48132  */
48133 #define GPMI_TIMING2_READ_LATENCY(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK)
48134 #define GPMI_TIMING2_TCR_MASK                    (0x18000000U)
48135 #define GPMI_TIMING2_TCR_SHIFT                   (27U)
48136 /*! TCR - TCR
48137  */
48138 #define GPMI_TIMING2_TCR(x)                      (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK)
48139 #define GPMI_TIMING2_TRPSTH_MASK                 (0xE0000000U)
48140 #define GPMI_TIMING2_TRPSTH_SHIFT                (29U)
48141 /*! TRPSTH - TRPSTH
48142  */
48143 #define GPMI_TIMING2_TRPSTH(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK)
48144 /*! @} */
48145 
48146 /*! @name DATA - GPMI DMA Data Transfer Register Description */
48147 /*! @{ */
48148 #define GPMI_DATA_DATA_MASK                      (0xFFFFFFFFU)
48149 #define GPMI_DATA_DATA_SHIFT                     (0U)
48150 /*! DATA - DATA
48151  */
48152 #define GPMI_DATA_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK)
48153 /*! @} */
48154 
48155 /*! @name STAT - GPMI Status Register Description */
48156 /*! @{ */
48157 #define GPMI_STAT_PRESENT_MASK                   (0x1U)
48158 #define GPMI_STAT_PRESENT_SHIFT                  (0U)
48159 /*! PRESENT - PRESENT
48160  *  0b0..GPMI is not present in this product.
48161  *  0b1..GPMI is present is in this product.
48162  */
48163 #define GPMI_STAT_PRESENT(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK)
48164 #define GPMI_STAT_FIFO_FULL_MASK                 (0x2U)
48165 #define GPMI_STAT_FIFO_FULL_SHIFT                (1U)
48166 /*! FIFO_FULL - FIFO_FULL
48167  *  0b0..FIFO is not full.
48168  *  0b1..FIFO is full.
48169  */
48170 #define GPMI_STAT_FIFO_FULL(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK)
48171 #define GPMI_STAT_FIFO_EMPTY_MASK                (0x4U)
48172 #define GPMI_STAT_FIFO_EMPTY_SHIFT               (2U)
48173 /*! FIFO_EMPTY - FIFO_EMPTY
48174  *  0b0..FIFO is not empty.
48175  *  0b1..FIFO is empty.
48176  */
48177 #define GPMI_STAT_FIFO_EMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK)
48178 #define GPMI_STAT_INVALID_BUFFER_MASK_MASK       (0x8U)
48179 #define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT      (3U)
48180 /*! INVALID_BUFFER_MASK - INVALID_BUFFER_MASK
48181  *  0b0..ECC Buffer Mask is not invalid.
48182  *  0b1..ECC Buffer Mask is invalid.
48183  */
48184 #define GPMI_STAT_INVALID_BUFFER_MASK(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK)
48185 #define GPMI_STAT_ATA_IRQ_MASK                   (0x10U)
48186 #define GPMI_STAT_ATA_IRQ_SHIFT                  (4U)
48187 /*! ATA_IRQ - ATA_IRQ
48188  */
48189 #define GPMI_STAT_ATA_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK)
48190 #define GPMI_STAT_RSVD1_MASK                     (0xE0U)
48191 #define GPMI_STAT_RSVD1_SHIFT                    (5U)
48192 /*! RSVD1 - RSVD1
48193  */
48194 #define GPMI_STAT_RSVD1(x)                       (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK)
48195 #define GPMI_STAT_DEV0_ERROR_MASK                (0x100U)
48196 #define GPMI_STAT_DEV0_ERROR_SHIFT               (8U)
48197 /*! DEV0_ERROR - DEV0_ERROR
48198  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0.
48199  *  0b1..An Error has occurred on ATA/NAND Device accessed by
48200  */
48201 #define GPMI_STAT_DEV0_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK)
48202 #define GPMI_STAT_DEV1_ERROR_MASK                (0x200U)
48203 #define GPMI_STAT_DEV1_ERROR_SHIFT               (9U)
48204 /*! DEV1_ERROR - DEV1_ERROR
48205  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1.
48206  *  0b1..An Error has occurred on ATA/NAND Device accessed by
48207  */
48208 #define GPMI_STAT_DEV1_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK)
48209 #define GPMI_STAT_DEV2_ERROR_MASK                (0x400U)
48210 #define GPMI_STAT_DEV2_ERROR_SHIFT               (10U)
48211 /*! DEV2_ERROR - DEV2_ERROR
48212  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2.
48213  *  0b1..An Error has occurred on ATA/NAND Device accessed by
48214  */
48215 #define GPMI_STAT_DEV2_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK)
48216 #define GPMI_STAT_DEV3_ERROR_MASK                (0x800U)
48217 #define GPMI_STAT_DEV3_ERROR_SHIFT               (11U)
48218 /*! DEV3_ERROR - DEV3_ERROR
48219  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3.
48220  *  0b1..An Error has occurred on ATA/NAND Device accessed by
48221  */
48222 #define GPMI_STAT_DEV3_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK)
48223 #define GPMI_STAT_DEV4_ERROR_MASK                (0x1000U)
48224 #define GPMI_STAT_DEV4_ERROR_SHIFT               (12U)
48225 /*! DEV4_ERROR - DEV4_ERROR
48226  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4.
48227  *  0b1..An Error has occurred on ATA/NAND Device accessed by
48228  */
48229 #define GPMI_STAT_DEV4_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK)
48230 #define GPMI_STAT_DEV5_ERROR_MASK                (0x2000U)
48231 #define GPMI_STAT_DEV5_ERROR_SHIFT               (13U)
48232 /*! DEV5_ERROR - DEV5_ERROR
48233  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5.
48234  *  0b1..An Error has occurred on ATA/NAND Device accessed by
48235  */
48236 #define GPMI_STAT_DEV5_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK)
48237 #define GPMI_STAT_DEV6_ERROR_MASK                (0x4000U)
48238 #define GPMI_STAT_DEV6_ERROR_SHIFT               (14U)
48239 /*! DEV6_ERROR - DEV6_ERROR
48240  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6.
48241  *  0b1..An Error has occurred on ATA/NAND Device accessed by
48242  */
48243 #define GPMI_STAT_DEV6_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK)
48244 #define GPMI_STAT_DEV7_ERROR_MASK                (0x8000U)
48245 #define GPMI_STAT_DEV7_ERROR_SHIFT               (15U)
48246 /*! DEV7_ERROR - DEV7_ERROR
48247  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7.
48248  *  0b1..An Error has occurred on ATA/NAND Device accessed by
48249  */
48250 #define GPMI_STAT_DEV7_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK)
48251 #define GPMI_STAT_RDY_TIMEOUT_MASK               (0xFF0000U)
48252 #define GPMI_STAT_RDY_TIMEOUT_SHIFT              (16U)
48253 /*! RDY_TIMEOUT - RDY_TIMEOUT
48254  */
48255 #define GPMI_STAT_RDY_TIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK)
48256 #define GPMI_STAT_READY_BUSY_MASK                (0xFF000000U)
48257 #define GPMI_STAT_READY_BUSY_SHIFT               (24U)
48258 /*! READY_BUSY - READY_BUSY
48259  */
48260 #define GPMI_STAT_READY_BUSY(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK)
48261 /*! @} */
48262 
48263 /*! @name DEBUG - GPMI Debug Information Register Description */
48264 /*! @{ */
48265 #define GPMI_DEBUG_CMD_END_MASK                  (0xFFU)
48266 #define GPMI_DEBUG_CMD_END_SHIFT                 (0U)
48267 /*! CMD_END - CMD_END
48268  */
48269 #define GPMI_DEBUG_CMD_END(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK)
48270 #define GPMI_DEBUG_DMAREQ_MASK                   (0xFF00U)
48271 #define GPMI_DEBUG_DMAREQ_SHIFT                  (8U)
48272 /*! DMAREQ - DMAREQ
48273  */
48274 #define GPMI_DEBUG_DMAREQ(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK)
48275 #define GPMI_DEBUG_DMA_SENSE_MASK                (0xFF0000U)
48276 #define GPMI_DEBUG_DMA_SENSE_SHIFT               (16U)
48277 /*! DMA_SENSE - DMA_SENSE
48278  */
48279 #define GPMI_DEBUG_DMA_SENSE(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK)
48280 #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK       (0xFF000000U)
48281 #define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT      (24U)
48282 /*! WAIT_FOR_READY_END - WAIT_FOR_READY_END
48283  */
48284 #define GPMI_DEBUG_WAIT_FOR_READY_END(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK)
48285 /*! @} */
48286 
48287 /*! @name VERSION - GPMI Version Register Description */
48288 /*! @{ */
48289 #define GPMI_VERSION_STEP_MASK                   (0xFFFFU)
48290 #define GPMI_VERSION_STEP_SHIFT                  (0U)
48291 /*! STEP - STEP
48292  */
48293 #define GPMI_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK)
48294 #define GPMI_VERSION_MINOR_MASK                  (0xFF0000U)
48295 #define GPMI_VERSION_MINOR_SHIFT                 (16U)
48296 /*! MINOR - MINOR
48297  */
48298 #define GPMI_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK)
48299 #define GPMI_VERSION_MAJOR_MASK                  (0xFF000000U)
48300 #define GPMI_VERSION_MAJOR_SHIFT                 (24U)
48301 /*! MAJOR - MAJOR
48302  */
48303 #define GPMI_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK)
48304 /*! @} */
48305 
48306 /*! @name DEBUG2 - GPMI Debug2 Information Register Description */
48307 /*! @{ */
48308 #define GPMI_DEBUG2_RDN_TAP_MASK                 (0x3FU)
48309 #define GPMI_DEBUG2_RDN_TAP_SHIFT                (0U)
48310 /*! RDN_TAP - RDN_TAP
48311  */
48312 #define GPMI_DEBUG2_RDN_TAP(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK)
48313 #define GPMI_DEBUG2_UPDATE_WINDOW_MASK           (0x40U)
48314 #define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT          (6U)
48315 /*! UPDATE_WINDOW - UPDATE_WINDOW
48316  */
48317 #define GPMI_DEBUG2_UPDATE_WINDOW(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK)
48318 #define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK        (0x80U)
48319 #define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT       (7U)
48320 /*! VIEW_DELAYED_RDN - VIEW_DELAYED_RDN
48321  */
48322 #define GPMI_DEBUG2_VIEW_DELAYED_RDN(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK)
48323 #define GPMI_DEBUG2_SYND2GPMI_READY_MASK         (0x100U)
48324 #define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT        (8U)
48325 /*! SYND2GPMI_READY - SYND2GPMI_READY
48326  */
48327 #define GPMI_DEBUG2_SYND2GPMI_READY(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK)
48328 #define GPMI_DEBUG2_SYND2GPMI_VALID_MASK         (0x200U)
48329 #define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT        (9U)
48330 /*! SYND2GPMI_VALID - SYND2GPMI_VALID
48331  */
48332 #define GPMI_DEBUG2_SYND2GPMI_VALID(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK)
48333 #define GPMI_DEBUG2_GPMI2SYND_READY_MASK         (0x400U)
48334 #define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT        (10U)
48335 /*! GPMI2SYND_READY - GPMI2SYND_READY
48336  */
48337 #define GPMI_DEBUG2_GPMI2SYND_READY(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK)
48338 #define GPMI_DEBUG2_GPMI2SYND_VALID_MASK         (0x800U)
48339 #define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT        (11U)
48340 /*! GPMI2SYND_VALID - GPMI2SYND_VALID
48341  */
48342 #define GPMI_DEBUG2_GPMI2SYND_VALID(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK)
48343 #define GPMI_DEBUG2_SYND2GPMI_BE_MASK            (0xF000U)
48344 #define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT           (12U)
48345 /*! SYND2GPMI_BE - SYND2GPMI_BE
48346  */
48347 #define GPMI_DEBUG2_SYND2GPMI_BE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK)
48348 #define GPMI_DEBUG2_MAIN_STATE_MASK              (0xF0000U)
48349 #define GPMI_DEBUG2_MAIN_STATE_SHIFT             (16U)
48350 /*! MAIN_STATE - MAIN_STATE
48351  */
48352 #define GPMI_DEBUG2_MAIN_STATE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK)
48353 #define GPMI_DEBUG2_PIN_STATE_MASK               (0x700000U)
48354 #define GPMI_DEBUG2_PIN_STATE_SHIFT              (20U)
48355 /*! PIN_STATE - PIN_STATE
48356  */
48357 #define GPMI_DEBUG2_PIN_STATE(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK)
48358 #define GPMI_DEBUG2_BUSY_MASK                    (0x800000U)
48359 #define GPMI_DEBUG2_BUSY_SHIFT                   (23U)
48360 /*! BUSY - BUSY
48361  */
48362 #define GPMI_DEBUG2_BUSY(x)                      (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK)
48363 #define GPMI_DEBUG2_UDMA_STATE_MASK              (0xF000000U)
48364 #define GPMI_DEBUG2_UDMA_STATE_SHIFT             (24U)
48365 /*! UDMA_STATE - UDMA_STATE
48366  */
48367 #define GPMI_DEBUG2_UDMA_STATE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK)
48368 #define GPMI_DEBUG2_RSVD1_MASK                   (0xF0000000U)
48369 #define GPMI_DEBUG2_RSVD1_SHIFT                  (28U)
48370 /*! RSVD1 - RSVD1
48371  */
48372 #define GPMI_DEBUG2_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK)
48373 /*! @} */
48374 
48375 /*! @name DEBUG3 - GPMI Debug3 Information Register Description */
48376 /*! @{ */
48377 #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK           (0xFFFFU)
48378 #define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT          (0U)
48379 /*! DEV_WORD_CNTR - DEV_WORD_CNTR
48380  */
48381 #define GPMI_DEBUG3_DEV_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK)
48382 #define GPMI_DEBUG3_APB_WORD_CNTR_MASK           (0xFFFF0000U)
48383 #define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT          (16U)
48384 /*! APB_WORD_CNTR - APB_WORD_CNTR
48385  */
48386 #define GPMI_DEBUG3_APB_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK)
48387 /*! @} */
48388 
48389 /*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */
48390 /*! @{ */
48391 #define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK       (0x1U)
48392 #define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT      (0U)
48393 /*! ENABLE - ENABLE
48394  */
48395 #define GPMI_READ_DDR_DLL_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK)
48396 #define GPMI_READ_DDR_DLL_CTRL_RESET_MASK        (0x2U)
48397 #define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT       (1U)
48398 /*! RESET - RESET
48399  */
48400 #define GPMI_READ_DDR_DLL_CTRL_RESET(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK)
48401 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
48402 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
48403 /*! SLV_FORCE_UPD - SLV_FORCE_UPD
48404  */
48405 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x)  (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
48406 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
48407 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
48408 /*! SLV_DLY_TARGET - SLV_DLY_TARGET
48409  */
48410 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
48411 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK  (0x80U)
48412 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
48413 /*! GATE_UPDATE - GATE_UPDATE
48414  */
48415 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x)    (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK)
48416 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK    (0x100U)
48417 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT   (8U)
48418 /*! REFCLK_ON - REFCLK_ON
48419  */
48420 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK)
48421 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
48422 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
48423 /*! SLV_OVERRIDE - SLV_OVERRIDE
48424  */
48425 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
48426 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
48427 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
48428 /*! SLV_OVERRIDE_VAL - SLV_OVERRIDE_VAL
48429  */
48430 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
48431 #define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK        (0xC0000U)
48432 #define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT       (18U)
48433 /*! RSVD1 - RSVD1
48434  */
48435 #define GPMI_READ_DDR_DLL_CTRL_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK)
48436 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
48437 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
48438 /*! SLV_UPDATE_INT - SLV_UPDATE_INT
48439  */
48440 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
48441 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
48442 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
48443 /*! REF_UPDATE_INT - REF_UPDATE_INT
48444  */
48445 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
48446 /*! @} */
48447 
48448 /*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */
48449 /*! @{ */
48450 #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK      (0x1U)
48451 #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT     (0U)
48452 /*! ENABLE - ENABLE
48453  */
48454 #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK)
48455 #define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK       (0x2U)
48456 #define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT      (1U)
48457 /*! RESET - RESET
48458  */
48459 #define GPMI_WRITE_DDR_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK)
48460 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
48461 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
48462 /*! SLV_FORCE_UPD - SLV_FORCE_UPD
48463  */
48464 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
48465 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
48466 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
48467 /*! SLV_DLY_TARGET - SLV_DLY_TARGET
48468  */
48469 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
48470 #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
48471 #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
48472 /*! GATE_UPDATE - GATE_UPDATE
48473  */
48474 #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK)
48475 #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK   (0x100U)
48476 #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT  (8U)
48477 /*! REFCLK_ON - REFCLK_ON
48478  */
48479 #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x)     (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK)
48480 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
48481 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
48482 /*! SLV_OVERRIDE - SLV_OVERRIDE
48483  */
48484 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
48485 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
48486 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
48487 /*! SLV_OVERRIDE_VAL - SLV_OVERRIDE_VAL
48488  */
48489 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
48490 #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK       (0xC0000U)
48491 #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT      (18U)
48492 /*! RSVD1 - RSVD1
48493  */
48494 #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK)
48495 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
48496 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
48497 /*! SLV_UPDATE_INT - SLV_UPDATE_INT
48498  */
48499 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
48500 #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
48501 #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
48502 /*! REF_UPDATE_INT - REF_UPDATE_INT
48503  */
48504 #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
48505 /*! @} */
48506 
48507 /*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */
48508 /*! @{ */
48509 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK      (0x1U)
48510 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT     (0U)
48511 /*! SLV_LOCK - SLV_LOCK
48512  */
48513 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK)
48514 #define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK       (0x1FEU)
48515 #define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT      (1U)
48516 /*! SLV_SEL - SLV_SEL
48517  */
48518 #define GPMI_READ_DDR_DLL_STS_SLV_SEL(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK)
48519 #define GPMI_READ_DDR_DLL_STS_RSVD0_MASK         (0xFE00U)
48520 #define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT        (9U)
48521 /*! RSVD0 - RSVD0
48522  */
48523 #define GPMI_READ_DDR_DLL_STS_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK)
48524 #define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK      (0x10000U)
48525 #define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT     (16U)
48526 /*! REF_LOCK - REF_LOCK
48527  */
48528 #define GPMI_READ_DDR_DLL_STS_REF_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK)
48529 #define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK       (0x1FE0000U)
48530 #define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT      (17U)
48531 /*! REF_SEL - REF_SEL
48532  */
48533 #define GPMI_READ_DDR_DLL_STS_REF_SEL(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK)
48534 #define GPMI_READ_DDR_DLL_STS_RSVD1_MASK         (0xFE000000U)
48535 #define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT        (25U)
48536 /*! RSVD1 - RSVD1
48537  */
48538 #define GPMI_READ_DDR_DLL_STS_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK)
48539 /*! @} */
48540 
48541 /*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */
48542 /*! @{ */
48543 #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK     (0x1U)
48544 #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT    (0U)
48545 /*! SLV_LOCK - SLV_LOCK
48546  */
48547 #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK)
48548 #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK      (0x1FEU)
48549 #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT     (1U)
48550 /*! SLV_SEL - SLV_SEL
48551  */
48552 #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK)
48553 #define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK        (0xFE00U)
48554 #define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT       (9U)
48555 /*! RSVD0 - RSVD0
48556  */
48557 #define GPMI_WRITE_DDR_DLL_STS_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK)
48558 #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK     (0x10000U)
48559 #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT    (16U)
48560 /*! REF_LOCK - REF_LOCK
48561  */
48562 #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK)
48563 #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK      (0x1FE0000U)
48564 #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT     (17U)
48565 /*! REF_SEL - REF_SEL
48566  */
48567 #define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK)
48568 #define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK        (0xFE000000U)
48569 #define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT       (25U)
48570 /*! RSVD1 - RSVD1
48571  */
48572 #define GPMI_WRITE_DDR_DLL_STS_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK)
48573 /*! @} */
48574 
48575 /*! @name TIMING3 - GPMI Timing Register 3 Description */
48576 /*! @{ */
48577 #define GPMI_TIMING3_TWWARMUP_MASK               (0x1FU)
48578 #define GPMI_TIMING3_TWWARMUP_SHIFT              (0U)
48579 /*! TWWARMUP - TWWARMUP
48580  */
48581 #define GPMI_TIMING3_TWWARMUP(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_TWWARMUP_SHIFT)) & GPMI_TIMING3_TWWARMUP_MASK)
48582 #define GPMI_TIMING3_RSVD0_MASK                  (0xE0U)
48583 #define GPMI_TIMING3_RSVD0_SHIFT                 (5U)
48584 /*! RSVD0 - RSVD0
48585  */
48586 #define GPMI_TIMING3_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_RSVD0_SHIFT)) & GPMI_TIMING3_RSVD0_MASK)
48587 #define GPMI_TIMING3_TRWARMUP_MASK               (0x1F00U)
48588 #define GPMI_TIMING3_TRWARMUP_SHIFT              (8U)
48589 /*! TRWARMUP - TRWARMUP
48590  */
48591 #define GPMI_TIMING3_TRWARMUP(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_TRWARMUP_SHIFT)) & GPMI_TIMING3_TRWARMUP_MASK)
48592 #define GPMI_TIMING3_RSVD1_MASK                  (0xFFFFE000U)
48593 #define GPMI_TIMING3_RSVD1_SHIFT                 (13U)
48594 /*! RSVD1 - RSVD1
48595  */
48596 #define GPMI_TIMING3_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_RSVD1_SHIFT)) & GPMI_TIMING3_RSVD1_MASK)
48597 /*! @} */
48598 
48599 /*! @name CTRL2 - GPMI Control Register 2 Description */
48600 /*! @{ */
48601 #define GPMI_CTRL2_NVDDR2_MODE_MASK              (0x1U)
48602 #define GPMI_CTRL2_NVDDR2_MODE_SHIFT             (0U)
48603 /*! NVDDR2_MODE - NVDDR2_MODE
48604  */
48605 #define GPMI_CTRL2_NVDDR2_MODE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_NVDDR2_MODE_SHIFT)) & GPMI_CTRL2_NVDDR2_MODE_MASK)
48606 #define GPMI_CTRL2_TOGGLE20_MODE_MASK            (0x2U)
48607 #define GPMI_CTRL2_TOGGLE20_MODE_SHIFT           (1U)
48608 /*! TOGGLE20_MODE - TOGGLE20_MODE
48609  */
48610 #define GPMI_CTRL2_TOGGLE20_MODE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_TOGGLE20_MODE_SHIFT)) & GPMI_CTRL2_TOGGLE20_MODE_MASK)
48611 #define GPMI_CTRL2_WARMUP_EN_MASK                (0x4U)
48612 #define GPMI_CTRL2_WARMUP_EN_SHIFT               (2U)
48613 /*! WARMUP_EN - WARMUP_EN
48614  */
48615 #define GPMI_CTRL2_WARMUP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_WARMUP_EN_SHIFT)) & GPMI_CTRL2_WARMUP_EN_MASK)
48616 #define GPMI_CTRL2_CEN_REDUCTION_MASK            (0x8U)
48617 #define GPMI_CTRL2_CEN_REDUCTION_SHIFT           (3U)
48618 /*! CEN_REDUCTION - CEN_REDUCTION
48619  */
48620 #define GPMI_CTRL2_CEN_REDUCTION(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_CEN_REDUCTION_SHIFT)) & GPMI_CTRL2_CEN_REDUCTION_MASK)
48621 #define GPMI_CTRL2_RSVD0_MASK                    (0xFFFFFFF0U)
48622 #define GPMI_CTRL2_RSVD0_SHIFT                   (4U)
48623 /*! RSVD0 - RSVD0
48624  */
48625 #define GPMI_CTRL2_RSVD0(x)                      (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_RSVD0_SHIFT)) & GPMI_CTRL2_RSVD0_MASK)
48626 /*! @} */
48627 
48628 
48629 /*!
48630  * @}
48631  */ /* end of group GPMI_Register_Masks */
48632 
48633 
48634 /* GPMI - Peripheral instance base addresses */
48635 /** Peripheral CONNECTIVITY__GPMI base address */
48636 #define CONNECTIVITY__GPMI_BASE                  (0x5B812000u)
48637 /** Peripheral CONNECTIVITY__GPMI base pointer */
48638 #define CONNECTIVITY__GPMI                       ((GPMI_Type *)CONNECTIVITY__GPMI_BASE)
48639 /** Array initializer of GPMI peripheral base addresses */
48640 #define GPMI_BASE_ADDRS                          { CONNECTIVITY__GPMI_BASE }
48641 /** Array initializer of GPMI peripheral base pointers */
48642 #define GPMI_BASE_PTRS                           { CONNECTIVITY__GPMI }
48643 
48644 /*!
48645  * @}
48646  */ /* end of group GPMI_Peripheral_Access_Layer */
48647 
48648 
48649 /* ----------------------------------------------------------------------------
48650    -- GPT Peripheral Access Layer
48651    ---------------------------------------------------------------------------- */
48652 
48653 /*!
48654  * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
48655  * @{
48656  */
48657 
48658 /** GPT - Register Layout Typedef */
48659 typedef struct {
48660   __IO uint32_t CR;                                /**< GPT Control Register, offset: 0x0 */
48661   __IO uint32_t PR;                                /**< GPT Prescaler Register, offset: 0x4 */
48662   __IO uint32_t SR;                                /**< GPT Status Register, offset: 0x8 */
48663   __IO uint32_t IR;                                /**< GPT Interrupt Register, offset: 0xC */
48664   __IO uint32_t OCR[3];                            /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */
48665   __I  uint32_t ICR[2];                            /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
48666   __I  uint32_t CNT;                               /**< GPT Counter Register, offset: 0x24 */
48667 } GPT_Type;
48668 
48669 /* ----------------------------------------------------------------------------
48670    -- GPT Register Masks
48671    ---------------------------------------------------------------------------- */
48672 
48673 /*!
48674  * @addtogroup GPT_Register_Masks GPT Register Masks
48675  * @{
48676  */
48677 
48678 /*! @name CR - GPT Control Register */
48679 /*! @{ */
48680 #define GPT_CR_EN_MASK                           (0x1U)
48681 #define GPT_CR_EN_SHIFT                          (0U)
48682 /*! EN - EN
48683  *  0b0..GPT is disabled.
48684  *  0b1..GPT is enabled.
48685  */
48686 #define GPT_CR_EN(x)                             (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
48687 #define GPT_CR_ENMOD_MASK                        (0x2U)
48688 #define GPT_CR_ENMOD_SHIFT                       (1U)
48689 /*! ENMOD - ENMOD
48690  *  0b0..GPT counter will retain its value when it is disabled.
48691  *  0b1..GPT counter value is reset to 0 when it is disabled.
48692  */
48693 #define GPT_CR_ENMOD(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
48694 #define GPT_CR_DBGEN_MASK                        (0x4U)
48695 #define GPT_CR_DBGEN_SHIFT                       (2U)
48696 /*! DBGEN - DBGEN
48697  *  0b0..GPT is disabled in debug mode.
48698  *  0b1..GPT is enabled in debug mode.
48699  */
48700 #define GPT_CR_DBGEN(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
48701 #define GPT_CR_WAITEN_MASK                       (0x8U)
48702 #define GPT_CR_WAITEN_SHIFT                      (3U)
48703 /*! WAITEN - WAITEN
48704  *  0b0..GPT is disabled in wait mode.
48705  *  0b1..GPT is enabled in wait mode.
48706  */
48707 #define GPT_CR_WAITEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
48708 #define GPT_CR_DOZEEN_MASK                       (0x10U)
48709 #define GPT_CR_DOZEEN_SHIFT                      (4U)
48710 /*! DOZEEN - DOZEEN
48711  *  0b0..GPT is disabled in doze mode.
48712  *  0b1..GPT is enabled in doze mode.
48713  */
48714 #define GPT_CR_DOZEEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
48715 #define GPT_CR_STOPEN_MASK                       (0x20U)
48716 #define GPT_CR_STOPEN_SHIFT                      (5U)
48717 /*! STOPEN - STOPEN
48718  *  0b0..GPT is disabled in Stop mode.
48719  *  0b1..GPT is enabled in Stop mode.
48720  */
48721 #define GPT_CR_STOPEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
48722 #define GPT_CR_CLKSRC_MASK                       (0x1C0U)
48723 #define GPT_CR_CLKSRC_SHIFT                      (6U)
48724 /*! CLKSRC - CLKSRC
48725  *  0b000..No clock
48726  *  0b001..Peripheral Clock (ipg_clk)
48727  *  0b010..High Frequency Reference Clock (ipg_clk_highfreq)
48728  *  0b011..External Clock
48729  *  0b100..Low Frequency Reference Clock (ipg_clk_32k)
48730  *  0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
48731  */
48732 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
48733 #define GPT_CR_FRR_MASK                          (0x200U)
48734 #define GPT_CR_FRR_SHIFT                         (9U)
48735 /*! FRR - FRR
48736  *  0b0..Restart mode
48737  *  0b1..Free-Run mode
48738  */
48739 #define GPT_CR_FRR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
48740 #define GPT_CR_EN_24M_MASK                       (0x400U)
48741 #define GPT_CR_EN_24M_SHIFT                      (10U)
48742 /*! EN_24M - EN_24M
48743  *  0b0..24M clock disabled
48744  *  0b1..24M clock enabled
48745  */
48746 #define GPT_CR_EN_24M(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
48747 #define GPT_CR_SWR_MASK                          (0x8000U)
48748 #define GPT_CR_SWR_SHIFT                         (15U)
48749 /*! SWR - SWR
48750  *  0b0..GPT is not in reset state
48751  *  0b1..GPT is in reset state
48752  */
48753 #define GPT_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
48754 #define GPT_CR_IM1_MASK                          (0x30000U)
48755 #define GPT_CR_IM1_SHIFT                         (16U)
48756 /*! IM1 - IM1
48757  */
48758 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
48759 #define GPT_CR_IM2_MASK                          (0xC0000U)
48760 #define GPT_CR_IM2_SHIFT                         (18U)
48761 /*! IM2 - IM2
48762  *  0b00..capture disabled
48763  *  0b01..capture on rising edge only
48764  *  0b10..capture on falling edge only
48765  *  0b11..capture on both edges
48766  */
48767 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
48768 #define GPT_CR_OM1_MASK                          (0x700000U)
48769 #define GPT_CR_OM1_SHIFT                         (20U)
48770 /*! OM1 - OM1
48771  */
48772 #define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
48773 #define GPT_CR_OM2_MASK                          (0x3800000U)
48774 #define GPT_CR_OM2_SHIFT                         (23U)
48775 /*! OM2 - OM2
48776  */
48777 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
48778 #define GPT_CR_OM3_MASK                          (0x1C000000U)
48779 #define GPT_CR_OM3_SHIFT                         (26U)
48780 /*! OM3 - OM3
48781  *  0b000..Output disconnected. No response on pin.
48782  *  0b001..Toggle output pin
48783  *  0b010..Clear output pin
48784  *  0b011..Set output pin
48785  *  0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
48786  */
48787 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
48788 #define GPT_CR_FO1_MASK                          (0x20000000U)
48789 #define GPT_CR_FO1_SHIFT                         (29U)
48790 /*! FO1 - FO1
48791  */
48792 #define GPT_CR_FO1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
48793 #define GPT_CR_FO2_MASK                          (0x40000000U)
48794 #define GPT_CR_FO2_SHIFT                         (30U)
48795 /*! FO2 - FO2
48796  */
48797 #define GPT_CR_FO2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
48798 #define GPT_CR_FO3_MASK                          (0x80000000U)
48799 #define GPT_CR_FO3_SHIFT                         (31U)
48800 /*! FO3 - FO3
48801  *  0b0..Writing a 0 has no effect.
48802  *  0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
48803  */
48804 #define GPT_CR_FO3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
48805 /*! @} */
48806 
48807 /*! @name PR - GPT Prescaler Register */
48808 /*! @{ */
48809 #define GPT_PR_PRESCALER_MASK                    (0xFFFU)
48810 #define GPT_PR_PRESCALER_SHIFT                   (0U)
48811 /*! PRESCALER - PRESCALER
48812  *  0b000000000000..Divide by 1
48813  *  0b000000000001..Divide by 2
48814  *  0b111111111111..Divide by 4096
48815  */
48816 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
48817 #define GPT_PR_PRESCALER24M_MASK                 (0xF000U)
48818 #define GPT_PR_PRESCALER24M_SHIFT                (12U)
48819 /*! PRESCALER24M - PRESCALER24M
48820  *  0b0000..Divide by 1
48821  *  0b0001..Divide by 2
48822  *  0b1111..Divide by 16
48823  */
48824 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
48825 /*! @} */
48826 
48827 /*! @name SR - GPT Status Register */
48828 /*! @{ */
48829 #define GPT_SR_OF1_MASK                          (0x1U)
48830 #define GPT_SR_OF1_SHIFT                         (0U)
48831 /*! OF1 - OF1
48832  */
48833 #define GPT_SR_OF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
48834 #define GPT_SR_OF2_MASK                          (0x2U)
48835 #define GPT_SR_OF2_SHIFT                         (1U)
48836 /*! OF2 - OF2
48837  */
48838 #define GPT_SR_OF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
48839 #define GPT_SR_OF3_MASK                          (0x4U)
48840 #define GPT_SR_OF3_SHIFT                         (2U)
48841 /*! OF3 - OF3
48842  *  0b0..Compare event has not occurred.
48843  *  0b1..Compare event has occurred.
48844  */
48845 #define GPT_SR_OF3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
48846 #define GPT_SR_IF1_MASK                          (0x8U)
48847 #define GPT_SR_IF1_SHIFT                         (3U)
48848 /*! IF1 - IF1
48849  */
48850 #define GPT_SR_IF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
48851 #define GPT_SR_IF2_MASK                          (0x10U)
48852 #define GPT_SR_IF2_SHIFT                         (4U)
48853 /*! IF2 - IF2
48854  *  0b0..Capture event has not occurred.
48855  *  0b1..Capture event has occurred.
48856  */
48857 #define GPT_SR_IF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
48858 #define GPT_SR_ROV_MASK                          (0x20U)
48859 #define GPT_SR_ROV_SHIFT                         (5U)
48860 /*! ROV - ROV
48861  *  0b0..Rollover has not occurred.
48862  *  0b1..Rollover has occurred.
48863  */
48864 #define GPT_SR_ROV(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
48865 /*! @} */
48866 
48867 /*! @name IR - GPT Interrupt Register */
48868 /*! @{ */
48869 #define GPT_IR_OF1IE_MASK                        (0x1U)
48870 #define GPT_IR_OF1IE_SHIFT                       (0U)
48871 /*! OF1IE - OF1IE
48872  */
48873 #define GPT_IR_OF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
48874 #define GPT_IR_OF2IE_MASK                        (0x2U)
48875 #define GPT_IR_OF2IE_SHIFT                       (1U)
48876 /*! OF2IE - OF2IE
48877  */
48878 #define GPT_IR_OF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
48879 #define GPT_IR_OF3IE_MASK                        (0x4U)
48880 #define GPT_IR_OF3IE_SHIFT                       (2U)
48881 /*! OF3IE - OF3IE
48882  *  0b0..Output Compare Channel n interrupt is disabled.
48883  *  0b1..Output Compare Channel n interrupt is enabled.
48884  */
48885 #define GPT_IR_OF3IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
48886 #define GPT_IR_IF1IE_MASK                        (0x8U)
48887 #define GPT_IR_IF1IE_SHIFT                       (3U)
48888 /*! IF1IE - IF1IE
48889  */
48890 #define GPT_IR_IF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
48891 #define GPT_IR_IF2IE_MASK                        (0x10U)
48892 #define GPT_IR_IF2IE_SHIFT                       (4U)
48893 /*! IF2IE - IF2IE
48894  *  0b0..IF2IE Input Capture n Interrupt Enable is disabled.
48895  *  0b1..IF2IE Input Capture n Interrupt Enable is enabled.
48896  */
48897 #define GPT_IR_IF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
48898 #define GPT_IR_ROVIE_MASK                        (0x20U)
48899 #define GPT_IR_ROVIE_SHIFT                       (5U)
48900 /*! ROVIE - ROVIE
48901  *  0b0..Rollover interrupt is disabled.
48902  *  0b1..Rollover interrupt enabled.
48903  */
48904 #define GPT_IR_ROVIE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
48905 /*! @} */
48906 
48907 /*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
48908 /*! @{ */
48909 #define GPT_OCR_COMP_MASK                        (0xFFFFFFFFU)
48910 #define GPT_OCR_COMP_SHIFT                       (0U)
48911 /*! COMP - COMP
48912  */
48913 #define GPT_OCR_COMP(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
48914 /*! @} */
48915 
48916 /* The count of GPT_OCR */
48917 #define GPT_OCR_COUNT                            (3U)
48918 
48919 /*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
48920 /*! @{ */
48921 #define GPT_ICR_CAPT_MASK                        (0xFFFFFFFFU)
48922 #define GPT_ICR_CAPT_SHIFT                       (0U)
48923 /*! CAPT - CAPT
48924  */
48925 #define GPT_ICR_CAPT(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
48926 /*! @} */
48927 
48928 /* The count of GPT_ICR */
48929 #define GPT_ICR_COUNT                            (2U)
48930 
48931 /*! @name CNT - GPT Counter Register */
48932 /*! @{ */
48933 #define GPT_CNT_COUNT_MASK                       (0xFFFFFFFFU)
48934 #define GPT_CNT_COUNT_SHIFT                      (0U)
48935 /*! COUNT - COUNT
48936  */
48937 #define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
48938 /*! @} */
48939 
48940 
48941 /*!
48942  * @}
48943  */ /* end of group GPT_Register_Masks */
48944 
48945 
48946 /* GPT - Peripheral instance base addresses */
48947 /** Peripheral ADMA__GPT0 base address */
48948 #define ADMA__GPT0_BASE                          (0x590B0000u)
48949 /** Peripheral ADMA__GPT0 base pointer */
48950 #define ADMA__GPT0                               ((GPT_Type *)ADMA__GPT0_BASE)
48951 /** Peripheral ADMA__GPT1 base address */
48952 #define ADMA__GPT1_BASE                          (0x590C0000u)
48953 /** Peripheral ADMA__GPT1 base pointer */
48954 #define ADMA__GPT1                               ((GPT_Type *)ADMA__GPT1_BASE)
48955 /** Peripheral ADMA__GPT2 base address */
48956 #define ADMA__GPT2_BASE                          (0x590D0000u)
48957 /** Peripheral ADMA__GPT2 base pointer */
48958 #define ADMA__GPT2                               ((GPT_Type *)ADMA__GPT2_BASE)
48959 /** Peripheral ADMA__GPT3 base address */
48960 #define ADMA__GPT3_BASE                          (0x590E0000u)
48961 /** Peripheral ADMA__GPT3 base pointer */
48962 #define ADMA__GPT3                               ((GPT_Type *)ADMA__GPT3_BASE)
48963 /** Peripheral ADMA__GPT4 base address */
48964 #define ADMA__GPT4_BASE                          (0x590F0000u)
48965 /** Peripheral ADMA__GPT4 base pointer */
48966 #define ADMA__GPT4                               ((GPT_Type *)ADMA__GPT4_BASE)
48967 /** Peripheral ADMA__GPT5 base address */
48968 #define ADMA__GPT5_BASE                          (0x59100000u)
48969 /** Peripheral ADMA__GPT5 base pointer */
48970 #define ADMA__GPT5                               ((GPT_Type *)ADMA__GPT5_BASE)
48971 /** Peripheral LSIO__GPT0 base address */
48972 #define LSIO__GPT0_BASE                          (0x5D140000u)
48973 /** Peripheral LSIO__GPT0 base pointer */
48974 #define LSIO__GPT0                               ((GPT_Type *)LSIO__GPT0_BASE)
48975 /** Peripheral LSIO__GPT1 base address */
48976 #define LSIO__GPT1_BASE                          (0x5D150000u)
48977 /** Peripheral LSIO__GPT1 base pointer */
48978 #define LSIO__GPT1                               ((GPT_Type *)LSIO__GPT1_BASE)
48979 /** Peripheral LSIO__GPT2 base address */
48980 #define LSIO__GPT2_BASE                          (0x5D160000u)
48981 /** Peripheral LSIO__GPT2 base pointer */
48982 #define LSIO__GPT2                               ((GPT_Type *)LSIO__GPT2_BASE)
48983 /** Peripheral LSIO__GPT3 base address */
48984 #define LSIO__GPT3_BASE                          (0x5D170000u)
48985 /** Peripheral LSIO__GPT3 base pointer */
48986 #define LSIO__GPT3                               ((GPT_Type *)LSIO__GPT3_BASE)
48987 /** Peripheral LSIO__GPT4 base address */
48988 #define LSIO__GPT4_BASE                          (0x5D180000u)
48989 /** Peripheral LSIO__GPT4 base pointer */
48990 #define LSIO__GPT4                               ((GPT_Type *)LSIO__GPT4_BASE)
48991 /** Array initializer of GPT peripheral base addresses */
48992 #define GPT_BASE_ADDRS                           { ADMA__GPT0_BASE, ADMA__GPT1_BASE, ADMA__GPT2_BASE, ADMA__GPT3_BASE, ADMA__GPT4_BASE, ADMA__GPT5_BASE, LSIO__GPT0_BASE, LSIO__GPT1_BASE, LSIO__GPT2_BASE, LSIO__GPT3_BASE, LSIO__GPT4_BASE }
48993 /** Array initializer of GPT peripheral base pointers */
48994 #define GPT_BASE_PTRS                            { ADMA__GPT0, ADMA__GPT1, ADMA__GPT2, ADMA__GPT3, ADMA__GPT4, ADMA__GPT5, LSIO__GPT0, LSIO__GPT1, LSIO__GPT2, LSIO__GPT3, LSIO__GPT4 }
48995 /** Interrupt vectors for the GPT peripheral type */
48996 #define GPT_IRQS                                 { ADMA_GPT0_INT_IRQn, ADMA_GPT1_INT_IRQn, ADMA_GPT2_INT_IRQn, ADMA_GPT3_INT_IRQn, ADMA_GPT4_INT_IRQn, ADMA_GPT5_INT_IRQn, LSIO_GPT0_INT_IRQn, LSIO_GPT1_INT_IRQn, LSIO_GPT2_INT_IRQn, LSIO_GPT3_INT_IRQn, LSIO_GPT4_INT_IRQn }
48997 
48998 /*!
48999  * @}
49000  */ /* end of group GPT_Peripheral_Access_Layer */
49001 
49002 
49003 /* ----------------------------------------------------------------------------
49004    -- HSIO_CSR Peripheral Access Layer
49005    ---------------------------------------------------------------------------- */
49006 
49007 /*!
49008  * @addtogroup HSIO_CSR_Peripheral_Access_Layer HSIO_CSR Peripheral Access Layer
49009  * @{
49010  */
49011 
49012 /** HSIO_CSR - Register Layout Typedef */
49013 typedef struct {
49014   __IO uint32_t PHYX1_CTRL0;                       /**< , offset: 0x0 */
49015   __I  uint32_t PHYX1_STTS0;                       /**< , offset: 0x4 */
49016        uint8_t RESERVED_0[131064];
49017   __IO uint32_t PCIEX1_CTRL0;                      /**< , offset: 0x20000 */
49018   __IO uint32_t PCIEX1_CTRL1;                      /**< , offset: 0x20004 */
49019   __IO uint32_t PCIEX1_CTRL2;                      /**< , offset: 0x20008 */
49020   __I  uint32_t PCIEX1_STTS0;                      /**< , offset: 0x2000C */
49021   __I  uint32_t PCIEX1_STTS1;                      /**< , offset: 0x20010 */
49022   __I  uint32_t PCIEX1_STTS2;                      /**< , offset: 0x20014 */
49023        uint8_t RESERVED_1[131048];
49024   __IO uint32_t MISC_CTRL0;                        /**< , offset: 0x40000 */
49025        uint32_t MISC_STTS0;                        /**< , offset: 0x40004 */
49026 } HSIO_CSR_Type;
49027 
49028 /* ----------------------------------------------------------------------------
49029    -- HSIO_CSR Register Masks
49030    ---------------------------------------------------------------------------- */
49031 
49032 /*!
49033  * @addtogroup HSIO_CSR_Register_Masks HSIO_CSR Register Masks
49034  * @{
49035  */
49036 
49037 /*! @name PHYX1_CTRL0 -  */
49038 /*! @{ */
49039 #define HSIO_CSR_PHYX1_CTRL0_APB_RSTN_MASK       (0x1U)
49040 #define HSIO_CSR_PHYX1_CTRL0_APB_RSTN_SHIFT      (0U)
49041 #define HSIO_CSR_PHYX1_CTRL0_APB_RSTN(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_APB_RSTN_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_APB_RSTN_MASK)
49042 #define HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_MASK        (0x400U)
49043 #define HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_SHIFT       (10U)
49044 #define HSIO_CSR_PHYX1_CTRL0_AIDDQ_0(x)          (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_MASK)
49045 #define HSIO_CSR_PHYX1_CTRL0_PHY_MODE_MASK       (0x1E0000U)
49046 #define HSIO_CSR_PHYX1_CTRL0_PHY_MODE_SHIFT      (17U)
49047 #define HSIO_CSR_PHYX1_CTRL0_PHY_MODE(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_PHY_MODE_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_PHY_MODE_MASK)
49048 #define HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_MASK (0x200000U)
49049 #define HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_SHIFT (21U)
49050 #define HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_MASK)
49051 #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_MASK    (0x1000000U)
49052 #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_SHIFT   (24U)
49053 #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0(x)      (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_MASK)
49054 #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_MASK (0x2000000U)
49055 #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_SHIFT (25U)
49056 #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_MASK)
49057 /*! @} */
49058 
49059 /*! @name PHYX1_STTS0 -  */
49060 /*! @{ */
49061 #define HSIO_CSR_PHYX1_STTS0_TEST_OUT_MASK       (0xFFU)
49062 #define HSIO_CSR_PHYX1_STTS0_TEST_OUT_SHIFT      (0U)
49063 /*! TEST_OUT - TEST_OUT[7:0]
49064  */
49065 #define HSIO_CSR_PHYX1_STTS0_TEST_OUT(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_STTS0_TEST_OUT_SHIFT)) & HSIO_CSR_PHYX1_STTS0_TEST_OUT_MASK)
49066 #define HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_MASK (0x10000U)
49067 #define HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_SHIFT (16U)
49068 #define HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK(x)   (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_SHIFT)) & HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_MASK)
49069 #define HSIO_CSR_PHYX1_STTS0_EPCS_READY_MASK     (0x40000U)
49070 #define HSIO_CSR_PHYX1_STTS0_EPCS_READY_SHIFT    (18U)
49071 #define HSIO_CSR_PHYX1_STTS0_EPCS_READY(x)       (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_STTS0_EPCS_READY_SHIFT)) & HSIO_CSR_PHYX1_STTS0_EPCS_READY_MASK)
49072 /*! @} */
49073 
49074 /*! @name PCIEX1_CTRL0 -  */
49075 /*! @{ */
49076 #define HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_MASK  (0xFFFFU)
49077 #define HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_SHIFT (0U)
49078 #define HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID(x)    (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_MASK)
49079 #define HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_MASK (0xFF0000U)
49080 #define HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_SHIFT (16U)
49081 #define HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID(x)  (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_MASK)
49082 #define HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_MASK   (0xF000000U)
49083 #define HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_SHIFT  (24U)
49084 #define HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE(x)     (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_SHIFT)) & HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_MASK)
49085 /*! @} */
49086 
49087 /*! @name PCIEX1_CTRL1 -  */
49088 /*! @{ */
49089 #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_MASK (0x3FU)
49090 #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_SHIFT (0U)
49091 #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_MASK)
49092 #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_MASK (0x3C0U)
49093 #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_SHIFT (6U)
49094 #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_MASK)
49095 #define HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_MASK (0x400U)
49096 #define HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_SHIFT (10U)
49097 #define HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_MASK)
49098 #define HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_MASK (0x800U)
49099 #define HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_SHIFT (11U)
49100 #define HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_MASK)
49101 #define HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_MASK (0x4000U)
49102 #define HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_SHIFT (14U)
49103 #define HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_MASK)
49104 /*! @} */
49105 
49106 /*! @name PCIEX1_CTRL2 -  */
49107 /*! @{ */
49108 #define HSIO_CSR_PCIEX1_CTRL2_SYS_INT_MASK       (0x3U)
49109 #define HSIO_CSR_PCIEX1_CTRL2_SYS_INT_SHIFT      (0U)
49110 #define HSIO_CSR_PCIEX1_CTRL2_SYS_INT(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_SYS_INT_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_SYS_INT_MASK)
49111 #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_MASK (0x4U)
49112 #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_SHIFT (2U)
49113 #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N(x)   (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_MASK)
49114 #define HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_MASK  (0x8U)
49115 #define HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_SHIFT (3U)
49116 #define HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST(x)    (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_MASK)
49117 #define HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_MASK (0x10U)
49118 #define HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_SHIFT (4U)
49119 #define HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_MASK)
49120 #define HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_MASK (0x20U)
49121 #define HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_SHIFT (5U)
49122 #define HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_MASK)
49123 #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_MASK (0x40U)
49124 #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_SHIFT (6U)
49125 #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_MASK)
49126 #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_MASK (0x80U)
49127 #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_SHIFT (7U)
49128 #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_MASK)
49129 #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_MASK (0x100U)
49130 #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_SHIFT (8U)
49131 #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_MASK)
49132 #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_MASK (0x200U)
49133 #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_SHIFT (9U)
49134 #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_MASK)
49135 #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_MASK (0x400U)
49136 #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_SHIFT (10U)
49137 #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN(x)   (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_MASK)
49138 #define HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_MASK (0x800U)
49139 #define HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_SHIFT (11U)
49140 #define HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_MASK)
49141 #define HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_MASK (0x1E000U)
49142 #define HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_SHIFT (13U)
49143 #define HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_MASK)
49144 #define HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_MASK (0xE0000U)
49145 #define HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_SHIFT (17U)
49146 #define HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS(x)   (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_MASK)
49147 #define HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_MASK  (0x200000U)
49148 #define HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_SHIFT (21U)
49149 #define HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N(x)    (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_MASK)
49150 #define HSIO_CSR_PCIEX1_CTRL2_PERST_N_MASK       (0x400000U)
49151 #define HSIO_CSR_PCIEX1_CTRL2_PERST_N_SHIFT      (22U)
49152 #define HSIO_CSR_PCIEX1_CTRL2_PERST_N(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_PERST_N_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_PERST_N_MASK)
49153 #define HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__MASK (0x800000U)
49154 #define HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__SHIFT (23U)
49155 #define HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N_(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__MASK)
49156 #define HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_MASK (0x4000000U)
49157 #define HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_SHIFT (26U)
49158 #define HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_MASK)
49159 /*! @} */
49160 
49161 /*! @name PCIEX1_STTS0 -  */
49162 /*! @{ */
49163 #define HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_MASK (0x3FU)
49164 #define HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_SHIFT (0U)
49165 #define HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_MASK)
49166 #define HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_MASK  (0x40U)
49167 #define HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_SHIFT (6U)
49168 #define HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN(x)    (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_MASK)
49169 #define HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_MASK     (0x380U)
49170 #define HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_SHIFT    (7U)
49171 #define HSIO_CSR_PCIEX1_STTS0_PM_DSTATE(x)       (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_MASK)
49172 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_MASK (0x400U)
49173 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_SHIFT (10U)
49174 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_MASK)
49175 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_MASK (0x800U)
49176 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_SHIFT (11U)
49177 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_MASK)
49178 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_MASK (0x1000U)
49179 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_SHIFT (12U)
49180 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_MASK)
49181 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_MASK (0x2000U)
49182 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_SHIFT (13U)
49183 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_MASK)
49184 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_MASK (0x4000U)
49185 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_SHIFT (14U)
49186 #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_MASK)
49187 #define HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_MASK (0x8000U)
49188 #define HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_SHIFT (15U)
49189 #define HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_MASK)
49190 #define HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_MASK (0x10000U)
49191 #define HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_SHIFT (16U)
49192 #define HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_MASK)
49193 #define HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_MASK (0x20000U)
49194 #define HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_SHIFT (17U)
49195 #define HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_MASK)
49196 #define HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_MASK (0x40000U)
49197 #define HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_SHIFT (18U)
49198 #define HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_MASK)
49199 #define HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_MASK (0x80000U)
49200 #define HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_SHIFT (19U)
49201 #define HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_MASK)
49202 #define HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_MASK  (0x400000U)
49203 #define HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_SHIFT (22U)
49204 #define HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD(x)    (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_MASK)
49205 /*! @} */
49206 
49207 /*! @name PCIEX1_STTS1 -  */
49208 /*! @{ */
49209 #define HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_MASK (0xFFFFU)
49210 #define HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_SHIFT (0U)
49211 #define HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_SHIFT)) & HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_MASK)
49212 /*! @} */
49213 
49214 /*! @name PCIEX1_STTS2 -  */
49215 /*! @{ */
49216 #define HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_MASK (0xFFFFFFFFU)
49217 #define HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_SHIFT (0U)
49218 #define HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_SHIFT)) & HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_MASK)
49219 /*! @} */
49220 
49221 /*! @name MISC_CTRL0 -  */
49222 /*! @{ */
49223 #define HSIO_CSR_MISC_CTRL0_IOB_RXENA_MASK       (0x1U)
49224 #define HSIO_CSR_MISC_CTRL0_IOB_RXENA_SHIFT      (0U)
49225 #define HSIO_CSR_MISC_CTRL0_IOB_RXENA(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_RXENA_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_RXENA_MASK)
49226 #define HSIO_CSR_MISC_CTRL0_IOB_TXENA_MASK       (0x2U)
49227 #define HSIO_CSR_MISC_CTRL0_IOB_TXENA_SHIFT      (1U)
49228 #define HSIO_CSR_MISC_CTRL0_IOB_TXENA(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_TXENA_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_TXENA_MASK)
49229 #define HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_MASK    (0x4U)
49230 #define HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_SHIFT   (2U)
49231 #define HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE(x)      (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_MASK)
49232 #define HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_MASK    (0x18U)
49233 #define HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_SHIFT   (3U)
49234 #define HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0(x)      (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_MASK)
49235 #define HSIO_CSR_MISC_CTRL0_FAST_INIT_MASK       (0x800U)
49236 #define HSIO_CSR_MISC_CTRL0_FAST_INIT_SHIFT      (11U)
49237 #define HSIO_CSR_MISC_CTRL0_FAST_INIT(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_FAST_INIT_SHIFT)) & HSIO_CSR_MISC_CTRL0_FAST_INIT_MASK)
49238 #define HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_MASK (0x1000U)
49239 #define HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_SHIFT (12U)
49240 /*! PHY_X1_EPCS_SEL - PHY_X1_EPCS_SEL will be used for ECO for PCIe controller bug fix.
49241  */
49242 #define HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL(x)   (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_SHIFT)) & HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_MASK)
49243 #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_MASK   (0x400000U)
49244 #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_SHIFT  (22U)
49245 #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1(x)     (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_MASK)
49246 #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_MASK (0x1000000U)
49247 #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_SHIFT (24U)
49248 #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_MASK)
49249 #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_MASK    (0x4000000U)
49250 #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_SHIFT   (26U)
49251 #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1(x)      (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_MASK)
49252 #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_MASK (0x10000000U)
49253 #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_SHIFT (28U)
49254 #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_MASK)
49255 /*! @} */
49256 
49257 
49258 /*!
49259  * @}
49260  */ /* end of group HSIO_CSR_Register_Masks */
49261 
49262 
49263 /* HSIO_CSR - Peripheral instance base addresses */
49264 /** Peripheral HSIO_CSR base address */
49265 #define HSIO_CSR_BASE                            (0x5F120000u)
49266 /** Peripheral HSIO_CSR base pointer */
49267 #define HSIO_CSR                                 ((HSIO_CSR_Type *)HSIO_CSR_BASE)
49268 /** Array initializer of HSIO_CSR peripheral base addresses */
49269 #define HSIO_CSR_BASE_ADDRS                      { HSIO_CSR_BASE }
49270 /** Array initializer of HSIO_CSR peripheral base pointers */
49271 #define HSIO_CSR_BASE_PTRS                       { HSIO_CSR }
49272 
49273 /*!
49274  * @}
49275  */ /* end of group HSIO_CSR_Peripheral_Access_Layer */
49276 
49277 
49278 /* ----------------------------------------------------------------------------
49279    -- I2S Peripheral Access Layer
49280    ---------------------------------------------------------------------------- */
49281 
49282 /*!
49283  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
49284  * @{
49285  */
49286 
49287 /** I2S - Register Layout Typedef */
49288 typedef struct {
49289   __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
49290   __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
49291   __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
49292   __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
49293   __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
49294   __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
49295        uint8_t RESERVED_0[8];
49296   __O  uint32_t TDR[1];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
49297        uint8_t RESERVED_1[28];
49298   __I  uint32_t TFR[1];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
49299        uint8_t RESERVED_2[28];
49300   __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
49301        uint8_t RESERVED_3[28];
49302   __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
49303   __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
49304   __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
49305   __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
49306   __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
49307   __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
49308        uint8_t RESERVED_4[8];
49309   __I  uint32_t RDR[1];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
49310        uint8_t RESERVED_5[28];
49311   __I  uint32_t RFR[1];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
49312        uint8_t RESERVED_6[28];
49313   __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
49314 } I2S_Type;
49315 
49316 /* ----------------------------------------------------------------------------
49317    -- I2S Register Masks
49318    ---------------------------------------------------------------------------- */
49319 
49320 /*!
49321  * @addtogroup I2S_Register_Masks I2S Register Masks
49322  * @{
49323  */
49324 
49325 /*! @name TCSR - SAI Transmit Control Register */
49326 /*! @{ */
49327 #define I2S_TCSR_FRDE_MASK                       (0x1U)
49328 #define I2S_TCSR_FRDE_SHIFT                      (0U)
49329 /*! FRDE - FIFO Request DMA Enable
49330  *  0b0..Disables the DMA request.
49331  *  0b1..Enables the DMA request.
49332  */
49333 #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
49334 #define I2S_TCSR_FWDE_MASK                       (0x2U)
49335 #define I2S_TCSR_FWDE_SHIFT                      (1U)
49336 /*! FWDE - FIFO Warning DMA Enable
49337  *  0b0..Disables the DMA request.
49338  *  0b1..Enables the DMA request.
49339  */
49340 #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
49341 #define I2S_TCSR_FRIE_MASK                       (0x100U)
49342 #define I2S_TCSR_FRIE_SHIFT                      (8U)
49343 /*! FRIE - FIFO Request Interrupt Enable
49344  *  0b0..Disables the interrupt.
49345  *  0b1..Enables the interrupt.
49346  */
49347 #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
49348 #define I2S_TCSR_FWIE_MASK                       (0x200U)
49349 #define I2S_TCSR_FWIE_SHIFT                      (9U)
49350 /*! FWIE - FIFO Warning Interrupt Enable
49351  *  0b0..Disables the interrupt.
49352  *  0b1..Enables the interrupt.
49353  */
49354 #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
49355 #define I2S_TCSR_FEIE_MASK                       (0x400U)
49356 #define I2S_TCSR_FEIE_SHIFT                      (10U)
49357 /*! FEIE - FIFO Error Interrupt Enable
49358  *  0b0..Disables the interrupt.
49359  *  0b1..Enables the interrupt.
49360  */
49361 #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
49362 #define I2S_TCSR_SEIE_MASK                       (0x800U)
49363 #define I2S_TCSR_SEIE_SHIFT                      (11U)
49364 /*! SEIE - Sync Error Interrupt Enable
49365  *  0b0..Disables interrupt.
49366  *  0b1..Enables interrupt.
49367  */
49368 #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
49369 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
49370 #define I2S_TCSR_WSIE_SHIFT                      (12U)
49371 /*! WSIE - Word Start Interrupt Enable
49372  *  0b0..Disables interrupt.
49373  *  0b1..Enables interrupt.
49374  */
49375 #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
49376 #define I2S_TCSR_FRF_MASK                        (0x10000U)
49377 #define I2S_TCSR_FRF_SHIFT                       (16U)
49378 /*! FRF - FIFO Request Flag
49379  *  0b0..Transmit FIFO watermark has not been reached.
49380  *  0b1..Transmit FIFO watermark has been reached.
49381  */
49382 #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
49383 #define I2S_TCSR_FWF_MASK                        (0x20000U)
49384 #define I2S_TCSR_FWF_SHIFT                       (17U)
49385 /*! FWF - FIFO Warning Flag
49386  *  0b0..No enabled transmit FIFO is empty.
49387  *  0b1..Enabled transmit FIFO is empty.
49388  */
49389 #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
49390 #define I2S_TCSR_FEF_MASK                        (0x40000U)
49391 #define I2S_TCSR_FEF_SHIFT                       (18U)
49392 /*! FEF - FIFO Error Flag
49393  *  0b0..Transmit underrun not detected.
49394  *  0b1..Transmit underrun detected.
49395  */
49396 #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
49397 #define I2S_TCSR_SEF_MASK                        (0x80000U)
49398 #define I2S_TCSR_SEF_SHIFT                       (19U)
49399 /*! SEF - Sync Error Flag
49400  *  0b0..Sync error not detected.
49401  *  0b1..Frame sync error detected.
49402  */
49403 #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
49404 #define I2S_TCSR_WSF_MASK                        (0x100000U)
49405 #define I2S_TCSR_WSF_SHIFT                       (20U)
49406 /*! WSF - Word Start Flag
49407  *  0b0..Start of word not detected.
49408  *  0b1..Start of word detected.
49409  */
49410 #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
49411 #define I2S_TCSR_SR_MASK                         (0x1000000U)
49412 #define I2S_TCSR_SR_SHIFT                        (24U)
49413 /*! SR - Software Reset
49414  *  0b0..No effect.
49415  *  0b1..Software reset.
49416  */
49417 #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
49418 #define I2S_TCSR_FR_MASK                         (0x2000000U)
49419 #define I2S_TCSR_FR_SHIFT                        (25U)
49420 /*! FR - FIFO Reset
49421  *  0b0..No effect.
49422  *  0b1..FIFO reset.
49423  */
49424 #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
49425 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
49426 #define I2S_TCSR_BCE_SHIFT                       (28U)
49427 /*! BCE - Bit Clock Enable
49428  *  0b0..Transmit bit clock is disabled.
49429  *  0b1..Transmit bit clock is enabled.
49430  */
49431 #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
49432 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
49433 #define I2S_TCSR_DBGE_SHIFT                      (29U)
49434 /*! DBGE - Debug Enable
49435  *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
49436  *  0b1..Transmitter is enabled in Debug mode.
49437  */
49438 #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
49439 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
49440 #define I2S_TCSR_STOPE_SHIFT                     (30U)
49441 /*! STOPE - Stop Enable
49442  *  0b0..Transmitter disabled in Stop mode.
49443  *  0b1..Transmitter enabled in Stop mode.
49444  */
49445 #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
49446 #define I2S_TCSR_TE_MASK                         (0x80000000U)
49447 #define I2S_TCSR_TE_SHIFT                        (31U)
49448 /*! TE - Transmitter Enable
49449  *  0b0..Transmitter is disabled.
49450  *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
49451  */
49452 #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
49453 /*! @} */
49454 
49455 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
49456 /*! @{ */
49457 #define I2S_TCR1_TFW_MASK                        (0x3FU)
49458 #define I2S_TCR1_TFW_SHIFT                       (0U)
49459 /*! TFW - Transmit FIFO Watermark
49460  */
49461 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
49462 /*! @} */
49463 
49464 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
49465 /*! @{ */
49466 #define I2S_TCR2_DIV_MASK                        (0xFFU)
49467 #define I2S_TCR2_DIV_SHIFT                       (0U)
49468 /*! DIV - Bit Clock Divide
49469  */
49470 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
49471 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
49472 #define I2S_TCR2_BCD_SHIFT                       (24U)
49473 /*! BCD - Bit Clock Direction
49474  *  0b0..Bit clock is generated externally in Slave mode.
49475  *  0b1..Bit clock is generated internally in Master mode.
49476  */
49477 #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
49478 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
49479 #define I2S_TCR2_BCP_SHIFT                       (25U)
49480 /*! BCP - Bit Clock Polarity
49481  *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
49482  *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
49483  */
49484 #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
49485 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
49486 #define I2S_TCR2_MSEL_SHIFT                      (26U)
49487 /*! MSEL - MCLK Select
49488  *  0b00..Bus Clock selected.
49489  *  0b01..Master Clock (MCLK) 1 option selected.
49490  *  0b10..Master Clock (MCLK) 2 option selected.
49491  *  0b11..Master Clock (MCLK) 3 option selected.
49492  */
49493 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
49494 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
49495 #define I2S_TCR2_BCI_SHIFT                       (28U)
49496 /*! BCI - Bit Clock Input
49497  *  0b0..No effect.
49498  *  0b1..Internal logic is clocked as if bit clock was externally generated.
49499  */
49500 #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
49501 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
49502 #define I2S_TCR2_BCS_SHIFT                       (29U)
49503 /*! BCS - Bit Clock Swap
49504  *  0b0..Use the normal bit clock source.
49505  *  0b1..Swap the bit clock source.
49506  */
49507 #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
49508 #define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
49509 #define I2S_TCR2_SYNC_SHIFT                      (30U)
49510 /*! SYNC - Synchronous Mode
49511  *  0b00..Asynchronous mode.
49512  *  0b01..Synchronous with receiver.
49513  *  0b10..Synchronous with another SAI transmitter.
49514  *  0b11..Synchronous with another SAI receiver.
49515  */
49516 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
49517 /*! @} */
49518 
49519 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
49520 /*! @{ */
49521 #define I2S_TCR3_WDFL_MASK                       (0x1FU)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
49522 #define I2S_TCR3_WDFL_SHIFT                      (0U)
49523 /*! WDFL - Word Flag Configuration
49524  */
49525 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
49526 #define I2S_TCR3_TCE_MASK                        (0x10000U)
49527 #define I2S_TCR3_TCE_SHIFT                       (16U)
49528 /*! TCE - Transmit Channel Enable
49529  */
49530 #define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
49531 /*! @} */
49532 
49533 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
49534 /*! @{ */
49535 #define I2S_TCR4_FSD_MASK                        (0x1U)
49536 #define I2S_TCR4_FSD_SHIFT                       (0U)
49537 /*! FSD - Frame Sync Direction
49538  *  0b0..Frame sync is generated externally in Slave mode.
49539  *  0b1..Frame sync is generated internally in Master mode.
49540  */
49541 #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
49542 #define I2S_TCR4_FSP_MASK                        (0x2U)
49543 #define I2S_TCR4_FSP_SHIFT                       (1U)
49544 /*! FSP - Frame Sync Polarity
49545  *  0b0..Frame sync is active high.
49546  *  0b1..Frame sync is active low.
49547  */
49548 #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
49549 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
49550 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
49551 /*! ONDEM - On Demand Mode
49552  *  0b0..Internal frame sync is generated continuously.
49553  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
49554  */
49555 #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
49556 #define I2S_TCR4_FSE_MASK                        (0x8U)
49557 #define I2S_TCR4_FSE_SHIFT                       (3U)
49558 /*! FSE - Frame Sync Early
49559  *  0b0..Frame sync asserts with the first bit of the frame.
49560  *  0b1..Frame sync asserts one bit before the first bit of the frame.
49561  */
49562 #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
49563 #define I2S_TCR4_MF_MASK                         (0x10U)
49564 #define I2S_TCR4_MF_SHIFT                        (4U)
49565 /*! MF - MSB First
49566  *  0b0..LSB is transmitted first.
49567  *  0b1..MSB is transmitted first.
49568  */
49569 #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
49570 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
49571 #define I2S_TCR4_SYWD_SHIFT                      (8U)
49572 /*! SYWD - Sync Width
49573  */
49574 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
49575 #define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
49576 #define I2S_TCR4_FRSZ_SHIFT                      (16U)
49577 /*! FRSZ - Frame size
49578  */
49579 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
49580 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
49581 #define I2S_TCR4_FPACK_SHIFT                     (24U)
49582 /*! FPACK - FIFO Packing Mode
49583  *  0b00..FIFO packing is disabled
49584  *  0b01..Reserved
49585  *  0b10..8-bit FIFO packing is enabled
49586  *  0b11..16-bit FIFO packing is enabled
49587  */
49588 #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
49589 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
49590 #define I2S_TCR4_FCONT_SHIFT                     (28U)
49591 /*! FCONT - FIFO Continue on Error
49592  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
49593  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
49594  */
49595 #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
49596 /*! @} */
49597 
49598 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
49599 /*! @{ */
49600 #define I2S_TCR5_FBT_MASK                        (0x1F00U)
49601 #define I2S_TCR5_FBT_SHIFT                       (8U)
49602 /*! FBT - First Bit Shifted
49603  */
49604 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
49605 #define I2S_TCR5_W0W_MASK                        (0x1F0000U)
49606 #define I2S_TCR5_W0W_SHIFT                       (16U)
49607 /*! W0W - Word 0 Width
49608  */
49609 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
49610 #define I2S_TCR5_WNW_MASK                        (0x1F000000U)
49611 #define I2S_TCR5_WNW_SHIFT                       (24U)
49612 /*! WNW - Word N Width
49613  */
49614 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
49615 /*! @} */
49616 
49617 /*! @name TDR - SAI Transmit Data Register */
49618 /*! @{ */
49619 #define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
49620 #define I2S_TDR_TDR_SHIFT                        (0U)
49621 /*! TDR - Transmit Data Register
49622  */
49623 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
49624 /*! @} */
49625 
49626 /* The count of I2S_TDR */
49627 #define I2S_TDR_COUNT                            (1U)
49628 
49629 /*! @name TFR - SAI Transmit FIFO Register */
49630 /*! @{ */
49631 #define I2S_TFR_RFP_MASK                         (0x7FU)
49632 #define I2S_TFR_RFP_SHIFT                        (0U)
49633 /*! RFP - Read FIFO Pointer
49634  */
49635 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
49636 #define I2S_TFR_WFP_MASK                         (0x7F0000U)
49637 #define I2S_TFR_WFP_SHIFT                        (16U)
49638 /*! WFP - Write FIFO Pointer
49639  */
49640 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
49641 /*! @} */
49642 
49643 /* The count of I2S_TFR */
49644 #define I2S_TFR_COUNT                            (1U)
49645 
49646 /*! @name TMR - SAI Transmit Mask Register */
49647 /*! @{ */
49648 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)  /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
49649 #define I2S_TMR_TWM_SHIFT                        (0U)
49650 /*! TWM - Transmit Word Mask
49651  *  0b00000000000000000000000000000000..Word N is enabled.
49652  *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.
49653  */
49654 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)  /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
49655 /*! @} */
49656 
49657 /*! @name RCSR - SAI Receive Control Register */
49658 /*! @{ */
49659 #define I2S_RCSR_FRDE_MASK                       (0x1U)
49660 #define I2S_RCSR_FRDE_SHIFT                      (0U)
49661 /*! FRDE - FIFO Request DMA Enable
49662  *  0b0..Disables the DMA request.
49663  *  0b1..Enables the DMA request.
49664  */
49665 #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
49666 #define I2S_RCSR_FWDE_MASK                       (0x2U)
49667 #define I2S_RCSR_FWDE_SHIFT                      (1U)
49668 /*! FWDE - FIFO Warning DMA Enable
49669  *  0b0..Disables the DMA request.
49670  *  0b1..Enables the DMA request.
49671  */
49672 #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
49673 #define I2S_RCSR_FRIE_MASK                       (0x100U)
49674 #define I2S_RCSR_FRIE_SHIFT                      (8U)
49675 /*! FRIE - FIFO Request Interrupt Enable
49676  *  0b0..Disables the interrupt.
49677  *  0b1..Enables the interrupt.
49678  */
49679 #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
49680 #define I2S_RCSR_FWIE_MASK                       (0x200U)
49681 #define I2S_RCSR_FWIE_SHIFT                      (9U)
49682 /*! FWIE - FIFO Warning Interrupt Enable
49683  *  0b0..Disables the interrupt.
49684  *  0b1..Enables the interrupt.
49685  */
49686 #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
49687 #define I2S_RCSR_FEIE_MASK                       (0x400U)
49688 #define I2S_RCSR_FEIE_SHIFT                      (10U)
49689 /*! FEIE - FIFO Error Interrupt Enable
49690  *  0b0..Disables the interrupt.
49691  *  0b1..Enables the interrupt.
49692  */
49693 #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
49694 #define I2S_RCSR_SEIE_MASK                       (0x800U)
49695 #define I2S_RCSR_SEIE_SHIFT                      (11U)
49696 /*! SEIE - Sync Error Interrupt Enable
49697  *  0b0..Disables interrupt.
49698  *  0b1..Enables interrupt.
49699  */
49700 #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
49701 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
49702 #define I2S_RCSR_WSIE_SHIFT                      (12U)
49703 /*! WSIE - Word Start Interrupt Enable
49704  *  0b0..Disables interrupt.
49705  *  0b1..Enables interrupt.
49706  */
49707 #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
49708 #define I2S_RCSR_FRF_MASK                        (0x10000U)
49709 #define I2S_RCSR_FRF_SHIFT                       (16U)
49710 /*! FRF - FIFO Request Flag
49711  *  0b0..Receive FIFO watermark not reached.
49712  *  0b1..Receive FIFO watermark has been reached.
49713  */
49714 #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
49715 #define I2S_RCSR_FWF_MASK                        (0x20000U)
49716 #define I2S_RCSR_FWF_SHIFT                       (17U)
49717 /*! FWF - FIFO Warning Flag
49718  *  0b0..No enabled receive FIFO is full.
49719  *  0b1..Enabled receive FIFO is full.
49720  */
49721 #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
49722 #define I2S_RCSR_FEF_MASK                        (0x40000U)
49723 #define I2S_RCSR_FEF_SHIFT                       (18U)
49724 /*! FEF - FIFO Error Flag
49725  *  0b0..Receive overflow not detected.
49726  *  0b1..Receive overflow detected.
49727  */
49728 #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
49729 #define I2S_RCSR_SEF_MASK                        (0x80000U)
49730 #define I2S_RCSR_SEF_SHIFT                       (19U)
49731 /*! SEF - Sync Error Flag
49732  *  0b0..Sync error not detected.
49733  *  0b1..Frame sync error detected.
49734  */
49735 #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
49736 #define I2S_RCSR_WSF_MASK                        (0x100000U)
49737 #define I2S_RCSR_WSF_SHIFT                       (20U)
49738 /*! WSF - Word Start Flag
49739  *  0b0..Start of word not detected.
49740  *  0b1..Start of word detected.
49741  */
49742 #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
49743 #define I2S_RCSR_SR_MASK                         (0x1000000U)
49744 #define I2S_RCSR_SR_SHIFT                        (24U)
49745 /*! SR - Software Reset
49746  *  0b0..No effect.
49747  *  0b1..Software reset.
49748  */
49749 #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
49750 #define I2S_RCSR_FR_MASK                         (0x2000000U)
49751 #define I2S_RCSR_FR_SHIFT                        (25U)
49752 /*! FR - FIFO Reset
49753  *  0b0..No effect.
49754  *  0b1..FIFO reset.
49755  */
49756 #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
49757 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
49758 #define I2S_RCSR_BCE_SHIFT                       (28U)
49759 /*! BCE - Bit Clock Enable
49760  *  0b0..Receive bit clock is disabled.
49761  *  0b1..Receive bit clock is enabled.
49762  */
49763 #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
49764 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
49765 #define I2S_RCSR_DBGE_SHIFT                      (29U)
49766 /*! DBGE - Debug Enable
49767  *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
49768  *  0b1..Receiver is enabled in Debug mode.
49769  */
49770 #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
49771 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
49772 #define I2S_RCSR_STOPE_SHIFT                     (30U)
49773 /*! STOPE - Stop Enable
49774  *  0b0..Receiver disabled in Stop mode.
49775  *  0b1..Receiver enabled in Stop mode.
49776  */
49777 #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
49778 #define I2S_RCSR_RE_MASK                         (0x80000000U)
49779 #define I2S_RCSR_RE_SHIFT                        (31U)
49780 /*! RE - Receiver Enable
49781  *  0b0..Receiver is disabled.
49782  *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
49783  */
49784 #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
49785 /*! @} */
49786 
49787 /*! @name RCR1 - SAI Receive Configuration 1 Register */
49788 /*! @{ */
49789 #define I2S_RCR1_RFW_MASK                        (0x3FU)
49790 #define I2S_RCR1_RFW_SHIFT                       (0U)
49791 /*! RFW - Receive FIFO Watermark
49792  */
49793 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
49794 /*! @} */
49795 
49796 /*! @name RCR2 - SAI Receive Configuration 2 Register */
49797 /*! @{ */
49798 #define I2S_RCR2_DIV_MASK                        (0xFFU)
49799 #define I2S_RCR2_DIV_SHIFT                       (0U)
49800 /*! DIV - Bit Clock Divide
49801  */
49802 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
49803 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
49804 #define I2S_RCR2_BCD_SHIFT                       (24U)
49805 /*! BCD - Bit Clock Direction
49806  *  0b0..Bit clock is generated externally in Slave mode.
49807  *  0b1..Bit clock is generated internally in Master mode.
49808  */
49809 #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
49810 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
49811 #define I2S_RCR2_BCP_SHIFT                       (25U)
49812 /*! BCP - Bit Clock Polarity
49813  *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
49814  *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
49815  */
49816 #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
49817 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
49818 #define I2S_RCR2_MSEL_SHIFT                      (26U)
49819 /*! MSEL - MCLK Select
49820  *  0b00..Bus Clock selected.
49821  *  0b01..Master Clock (MCLK) 1 option selected.
49822  *  0b10..Master Clock (MCLK) 2 option selected.
49823  *  0b11..Master Clock (MCLK) 3 option selected.
49824  */
49825 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
49826 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
49827 #define I2S_RCR2_BCI_SHIFT                       (28U)
49828 /*! BCI - Bit Clock Input
49829  *  0b0..No effect.
49830  *  0b1..Internal logic is clocked as if bit clock was externally generated.
49831  */
49832 #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
49833 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
49834 #define I2S_RCR2_BCS_SHIFT                       (29U)
49835 /*! BCS - Bit Clock Swap
49836  *  0b0..Use the normal bit clock source.
49837  *  0b1..Swap the bit clock source.
49838  */
49839 #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
49840 #define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
49841 #define I2S_RCR2_SYNC_SHIFT                      (30U)
49842 /*! SYNC - Synchronous Mode
49843  *  0b00..Asynchronous mode.
49844  *  0b01..Synchronous with transmitter.
49845  *  0b10..Synchronous with another SAI receiver.
49846  *  0b11..Synchronous with another SAI transmitter.
49847  */
49848 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
49849 /*! @} */
49850 
49851 /*! @name RCR3 - SAI Receive Configuration 3 Register */
49852 /*! @{ */
49853 #define I2S_RCR3_WDFL_MASK                       (0x1FU)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
49854 #define I2S_RCR3_WDFL_SHIFT                      (0U)
49855 /*! WDFL - Word Flag Configuration
49856  */
49857 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
49858 #define I2S_RCR3_RCE_MASK                        (0x10000U)
49859 #define I2S_RCR3_RCE_SHIFT                       (16U)
49860 /*! RCE - Receive Channel Enable
49861  */
49862 #define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
49863 /*! @} */
49864 
49865 /*! @name RCR4 - SAI Receive Configuration 4 Register */
49866 /*! @{ */
49867 #define I2S_RCR4_FSD_MASK                        (0x1U)
49868 #define I2S_RCR4_FSD_SHIFT                       (0U)
49869 /*! FSD - Frame Sync Direction
49870  *  0b0..Frame Sync is generated externally in Slave mode.
49871  *  0b1..Frame Sync is generated internally in Master mode.
49872  */
49873 #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
49874 #define I2S_RCR4_FSP_MASK                        (0x2U)
49875 #define I2S_RCR4_FSP_SHIFT                       (1U)
49876 /*! FSP - Frame Sync Polarity
49877  *  0b0..Frame sync is active high.
49878  *  0b1..Frame sync is active low.
49879  */
49880 #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
49881 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
49882 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
49883 /*! ONDEM - On Demand Mode
49884  *  0b0..Internal frame sync is generated continuously.
49885  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
49886  */
49887 #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
49888 #define I2S_RCR4_FSE_MASK                        (0x8U)
49889 #define I2S_RCR4_FSE_SHIFT                       (3U)
49890 /*! FSE - Frame Sync Early
49891  *  0b0..Frame sync asserts with the first bit of the frame.
49892  *  0b1..Frame sync asserts one bit before the first bit of the frame.
49893  */
49894 #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
49895 #define I2S_RCR4_MF_MASK                         (0x10U)
49896 #define I2S_RCR4_MF_SHIFT                        (4U)
49897 /*! MF - MSB First
49898  *  0b0..LSB is received first.
49899  *  0b1..MSB is received first.
49900  */
49901 #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
49902 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
49903 #define I2S_RCR4_SYWD_SHIFT                      (8U)
49904 /*! SYWD - Sync Width
49905  */
49906 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
49907 #define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
49908 #define I2S_RCR4_FRSZ_SHIFT                      (16U)
49909 /*! FRSZ - Frame Size
49910  */
49911 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
49912 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
49913 #define I2S_RCR4_FPACK_SHIFT                     (24U)
49914 /*! FPACK - FIFO Packing Mode
49915  *  0b00..FIFO packing is disabled
49916  *  0b01..Reserved.
49917  *  0b10..8-bit FIFO packing is enabled
49918  *  0b11..16-bit FIFO packing is enabled
49919  */
49920 #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
49921 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
49922 #define I2S_RCR4_FCONT_SHIFT                     (28U)
49923 /*! FCONT - FIFO Continue on Error
49924  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
49925  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
49926  */
49927 #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
49928 /*! @} */
49929 
49930 /*! @name RCR5 - SAI Receive Configuration 5 Register */
49931 /*! @{ */
49932 #define I2S_RCR5_FBT_MASK                        (0x1F00U)
49933 #define I2S_RCR5_FBT_SHIFT                       (8U)
49934 /*! FBT - First Bit Shifted
49935  */
49936 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
49937 #define I2S_RCR5_W0W_MASK                        (0x1F0000U)
49938 #define I2S_RCR5_W0W_SHIFT                       (16U)
49939 /*! W0W - Word 0 Width
49940  */
49941 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
49942 #define I2S_RCR5_WNW_MASK                        (0x1F000000U)
49943 #define I2S_RCR5_WNW_SHIFT                       (24U)
49944 /*! WNW - Word N Width
49945  */
49946 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
49947 /*! @} */
49948 
49949 /*! @name RDR - SAI Receive Data Register */
49950 /*! @{ */
49951 #define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
49952 #define I2S_RDR_RDR_SHIFT                        (0U)
49953 /*! RDR - Receive Data Register
49954  */
49955 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
49956 /*! @} */
49957 
49958 /* The count of I2S_RDR */
49959 #define I2S_RDR_COUNT                            (1U)
49960 
49961 /*! @name RFR - SAI Receive FIFO Register */
49962 /*! @{ */
49963 #define I2S_RFR_RFP_MASK                         (0x7FU)
49964 #define I2S_RFR_RFP_SHIFT                        (0U)
49965 /*! RFP - Read FIFO Pointer
49966  */
49967 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
49968 #define I2S_RFR_WFP_MASK                         (0x7F0000U)
49969 #define I2S_RFR_WFP_SHIFT                        (16U)
49970 /*! WFP - Write FIFO Pointer
49971  */
49972 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
49973 /*! @} */
49974 
49975 /* The count of I2S_RFR */
49976 #define I2S_RFR_COUNT                            (1U)
49977 
49978 /*! @name RMR - SAI Receive Mask Register */
49979 /*! @{ */
49980 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)  /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
49981 #define I2S_RMR_RWM_SHIFT                        (0U)
49982 /*! RWM - Receive Word Mask
49983  *  0b00000000000000000000000000000000..Word N is enabled.
49984  *  0b00000000000000000000000000000001..Word N is masked.
49985  */
49986 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)  /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
49987 /*! @} */
49988 
49989 
49990 /*!
49991  * @}
49992  */ /* end of group I2S_Register_Masks */
49993 
49994 
49995 /* I2S - Peripheral instance base addresses */
49996 /** Peripheral ADMA__SAI0 base address */
49997 #define ADMA__SAI0_BASE                          (0x59040000u)
49998 /** Peripheral ADMA__SAI0 base pointer */
49999 #define ADMA__SAI0                               ((I2S_Type *)ADMA__SAI0_BASE)
50000 /** Peripheral ADMA__SAI1 base address */
50001 #define ADMA__SAI1_BASE                          (0x59050000u)
50002 /** Peripheral ADMA__SAI1 base pointer */
50003 #define ADMA__SAI1                               ((I2S_Type *)ADMA__SAI1_BASE)
50004 /** Peripheral ADMA__SAI2 base address */
50005 #define ADMA__SAI2_BASE                          (0x59060000u)
50006 /** Peripheral ADMA__SAI2 base pointer */
50007 #define ADMA__SAI2                               ((I2S_Type *)ADMA__SAI2_BASE)
50008 /** Peripheral ADMA__SAI3 base address */
50009 #define ADMA__SAI3_BASE                          (0x59070000u)
50010 /** Peripheral ADMA__SAI3 base pointer */
50011 #define ADMA__SAI3                               ((I2S_Type *)ADMA__SAI3_BASE)
50012 /** Peripheral ADMA__SAI4 base address */
50013 #define ADMA__SAI4_BASE                          (0x59820000u)
50014 /** Peripheral ADMA__SAI4 base pointer */
50015 #define ADMA__SAI4                               ((I2S_Type *)ADMA__SAI4_BASE)
50016 /** Peripheral ADMA__SAI5 base address */
50017 #define ADMA__SAI5_BASE                          (0x59830000u)
50018 /** Peripheral ADMA__SAI5 base pointer */
50019 #define ADMA__SAI5                               ((I2S_Type *)ADMA__SAI5_BASE)
50020 /** Array initializer of I2S peripheral base addresses */
50021 #define I2S_BASE_ADDRS                           { ADMA__SAI0_BASE, ADMA__SAI1_BASE, ADMA__SAI2_BASE, ADMA__SAI3_BASE, ADMA__SAI4_BASE, ADMA__SAI5_BASE }
50022 /** Array initializer of I2S peripheral base pointers */
50023 #define I2S_BASE_PTRS                            { ADMA__SAI0, ADMA__SAI1, ADMA__SAI2, ADMA__SAI3, ADMA__SAI4, ADMA__SAI5 }
50024 /** Interrupt vectors for the I2S peripheral type */
50025 #define I2S_RX_IRQS                              { ADMA_SAI0_INT_IRQn, ADMA_SAI1_INT_IRQn, ADMA_SAI2_INT_IRQn, ADMA_SAI3_INT_IRQn, ADMA_SAI4_INT_IRQn, ADMA_SAI5_INT_IRQn }
50026 #define I2S_TX_IRQS                              { ADMA_SAI0_INT_IRQn, ADMA_SAI1_INT_IRQn, ADMA_SAI2_INT_IRQn, ADMA_SAI3_INT_IRQn, ADMA_SAI4_INT_IRQn, ADMA_SAI5_INT_IRQn }
50027 
50028 /*!
50029  * @}
50030  */ /* end of group I2S_Peripheral_Access_Layer */
50031 
50032 
50033 /* ----------------------------------------------------------------------------
50034    -- IMAGING_LPCG_MJPEG_COMMON_DEC Peripheral Access Layer
50035    ---------------------------------------------------------------------------- */
50036 
50037 /*!
50038  * @addtogroup IMAGING_LPCG_MJPEG_COMMON_DEC_Peripheral_Access_Layer IMAGING_LPCG_MJPEG_COMMON_DEC Peripheral Access Layer
50039  * @{
50040  */
50041 
50042 /** IMAGING_LPCG_MJPEG_COMMON_DEC - Register Layout Typedef */
50043 typedef struct {
50044   __IO uint32_t LPCG_MJPEG_COMMON_DEC_0;           /**< na, offset: 0x0 */
50045 } IMAGING_LPCG_MJPEG_COMMON_DEC_Type;
50046 
50047 /* ----------------------------------------------------------------------------
50048    -- IMAGING_LPCG_MJPEG_COMMON_DEC Register Masks
50049    ---------------------------------------------------------------------------- */
50050 
50051 /*!
50052  * @addtogroup IMAGING_LPCG_MJPEG_COMMON_DEC_Register_Masks IMAGING_LPCG_MJPEG_COMMON_DEC Register Masks
50053  * @{
50054  */
50055 
50056 /*! @name LPCG_MJPEG_COMMON_DEC_0 - na */
50057 /*! @{ */
50058 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_MASK (0x1U)
50059 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_SHIFT (0U)
50060 /*! decode_jpeg_clk_HWEN - Hardware Enable
50061  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50062  *  0b1..Enable HW automatic gating
50063  */
50064 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_MASK)
50065 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_MASK (0x2U)
50066 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_SHIFT (1U)
50067 /*! decode_jpeg_clk_SWEN - Software Enable
50068  *  0b0..Disable SW clock regardless of HWEN
50069  *  0b1..Enable SW clock gating
50070  */
50071 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_MASK)
50072 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_MASK (0x4U)
50073 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_SHIFT (2U)
50074 /*! LPCG_MJPEG_Common_Dec_0_reserved_2_2 - reserved
50075  */
50076 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_MASK)
50077 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_MASK (0x8U)
50078 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_SHIFT (3U)
50079 /*! decode_jpeg_clk_STOP - show clock root status, 1 means clock stopped
50080  */
50081 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_MASK)
50082 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_MASK (0x1FFF0U)
50083 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_SHIFT (4U)
50084 /*! LPCG_MJPEG_Common_Dec_0_reserved_4_16 - reserved
50085  */
50086 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_MASK)
50087 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_MASK (0x20000U)
50088 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_SHIFT (17U)
50089 /*! decode_ips_clk_SWEN - Software Enable
50090  *  0b0..Disable SW clock regardless of HWEN
50091  *  0b1..Enable SW clock gating
50092  */
50093 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_MASK)
50094 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_MASK (0x40000U)
50095 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_SHIFT (18U)
50096 /*! LPCG_MJPEG_Common_Dec_0_reserved_18_18 - reserved
50097  */
50098 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_MASK)
50099 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_MASK (0x80000U)
50100 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_SHIFT (19U)
50101 /*! decode_ips_clk_STOP - show clock root status, 1 means clock stopped
50102  */
50103 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_MASK)
50104 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_MASK (0xFFF00000U)
50105 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_SHIFT (20U)
50106 /*! LPCG_MJPEG_Common_Dec_0_reserved_20_31 - reserved
50107  */
50108 #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_MASK)
50109 /*! @} */
50110 
50111 
50112 /*!
50113  * @}
50114  */ /* end of group IMAGING_LPCG_MJPEG_COMMON_DEC_Register_Masks */
50115 
50116 
50117 /* IMAGING_LPCG_MJPEG_COMMON_DEC - Peripheral instance base addresses */
50118 /** Peripheral IMAGING__LPCG_DECODE_IPS_CLK base address */
50119 #define IMAGING__LPCG_DECODE_IPS_CLK_BASE        (0x585D0000u)
50120 /** Peripheral IMAGING__LPCG_DECODE_IPS_CLK base pointer */
50121 #define IMAGING__LPCG_DECODE_IPS_CLK             ((IMAGING_LPCG_MJPEG_COMMON_DEC_Type *)IMAGING__LPCG_DECODE_IPS_CLK_BASE)
50122 /** Peripheral IMAGING__LPCG_DECODE_JPEG_CLK base address */
50123 #define IMAGING__LPCG_DECODE_JPEG_CLK_BASE       (0x585D0000u)
50124 /** Peripheral IMAGING__LPCG_DECODE_JPEG_CLK base pointer */
50125 #define IMAGING__LPCG_DECODE_JPEG_CLK            ((IMAGING_LPCG_MJPEG_COMMON_DEC_Type *)IMAGING__LPCG_DECODE_JPEG_CLK_BASE)
50126 /** Array initializer of IMAGING_LPCG_MJPEG_COMMON_DEC peripheral base addresses
50127  * */
50128 #define IMAGING_LPCG_MJPEG_COMMON_DEC_BASE_ADDRS { IMAGING__LPCG_DECODE_IPS_CLK_BASE, IMAGING__LPCG_DECODE_JPEG_CLK_BASE }
50129 /** Array initializer of IMAGING_LPCG_MJPEG_COMMON_DEC peripheral base pointers
50130  * */
50131 #define IMAGING_LPCG_MJPEG_COMMON_DEC_BASE_PTRS  { IMAGING__LPCG_DECODE_IPS_CLK, IMAGING__LPCG_DECODE_JPEG_CLK }
50132 
50133 /*!
50134  * @}
50135  */ /* end of group IMAGING_LPCG_MJPEG_COMMON_DEC_Peripheral_Access_Layer */
50136 
50137 
50138 /* ----------------------------------------------------------------------------
50139    -- IMAGING_LPCG_MJPEG_COMMON_ENC Peripheral Access Layer
50140    ---------------------------------------------------------------------------- */
50141 
50142 /*!
50143  * @addtogroup IMAGING_LPCG_MJPEG_COMMON_ENC_Peripheral_Access_Layer IMAGING_LPCG_MJPEG_COMMON_ENC Peripheral Access Layer
50144  * @{
50145  */
50146 
50147 /** IMAGING_LPCG_MJPEG_COMMON_ENC - Register Layout Typedef */
50148 typedef struct {
50149   __IO uint32_t LPCG_MJPEG_COMMON_ENC_0;           /**< na, offset: 0x0 */
50150 } IMAGING_LPCG_MJPEG_COMMON_ENC_Type;
50151 
50152 /* ----------------------------------------------------------------------------
50153    -- IMAGING_LPCG_MJPEG_COMMON_ENC Register Masks
50154    ---------------------------------------------------------------------------- */
50155 
50156 /*!
50157  * @addtogroup IMAGING_LPCG_MJPEG_COMMON_ENC_Register_Masks IMAGING_LPCG_MJPEG_COMMON_ENC Register Masks
50158  * @{
50159  */
50160 
50161 /*! @name LPCG_MJPEG_COMMON_ENC_0 - na */
50162 /*! @{ */
50163 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_MASK (0x1U)
50164 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_SHIFT (0U)
50165 /*! encode_jpeg_clk_HWEN - Hardware Enable
50166  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50167  *  0b1..Enable HW automatic gating
50168  */
50169 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_MASK)
50170 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_MASK (0x2U)
50171 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_SHIFT (1U)
50172 /*! encode_jpeg_clk_SWEN - Software Enable
50173  *  0b0..Disable SW clock regardless of HWEN
50174  *  0b1..Enable SW clock gating
50175  */
50176 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_MASK)
50177 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_MASK (0x4U)
50178 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_SHIFT (2U)
50179 /*! LPCG_MJPEG_Common_Enc_0_reserved_2_2 - reserved
50180  */
50181 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_MASK)
50182 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_MASK (0x8U)
50183 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_SHIFT (3U)
50184 /*! encode_jpeg_clk_STOP - show clock root status, 1 means clock stopped
50185  */
50186 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_MASK)
50187 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_MASK (0x1FFF0U)
50188 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_SHIFT (4U)
50189 /*! LPCG_MJPEG_Common_Enc_0_reserved_4_16 - reserved
50190  */
50191 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_MASK)
50192 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_MASK (0x20000U)
50193 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_SHIFT (17U)
50194 /*! encode_ips_clk_SWEN - Software Enable
50195  *  0b0..Disable SW clock regardless of HWEN
50196  *  0b1..Enable SW clock gating
50197  */
50198 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_MASK)
50199 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_MASK (0x40000U)
50200 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_SHIFT (18U)
50201 /*! LPCG_MJPEG_Common_Enc_0_reserved_18_18 - reserved
50202  */
50203 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_MASK)
50204 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_MASK (0x80000U)
50205 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_SHIFT (19U)
50206 /*! encode_ips_clk_STOP - show clock root status, 1 means clock stopped
50207  */
50208 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_MASK)
50209 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_MASK (0xFFF00000U)
50210 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_SHIFT (20U)
50211 /*! LPCG_MJPEG_Common_Enc_0_reserved_20_31 - reserved
50212  */
50213 #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_MASK)
50214 /*! @} */
50215 
50216 
50217 /*!
50218  * @}
50219  */ /* end of group IMAGING_LPCG_MJPEG_COMMON_ENC_Register_Masks */
50220 
50221 
50222 /* IMAGING_LPCG_MJPEG_COMMON_ENC - Peripheral instance base addresses */
50223 /** Peripheral IMAGING__LPCG_ENCODE_IPS_CLK base address */
50224 #define IMAGING__LPCG_ENCODE_IPS_CLK_BASE        (0x585F0000u)
50225 /** Peripheral IMAGING__LPCG_ENCODE_IPS_CLK base pointer */
50226 #define IMAGING__LPCG_ENCODE_IPS_CLK             ((IMAGING_LPCG_MJPEG_COMMON_ENC_Type *)IMAGING__LPCG_ENCODE_IPS_CLK_BASE)
50227 /** Peripheral IMAGING__LPCG_ENCODE_JPEG_CLK base address */
50228 #define IMAGING__LPCG_ENCODE_JPEG_CLK_BASE       (0x585F0000u)
50229 /** Peripheral IMAGING__LPCG_ENCODE_JPEG_CLK base pointer */
50230 #define IMAGING__LPCG_ENCODE_JPEG_CLK            ((IMAGING_LPCG_MJPEG_COMMON_ENC_Type *)IMAGING__LPCG_ENCODE_JPEG_CLK_BASE)
50231 /** Array initializer of IMAGING_LPCG_MJPEG_COMMON_ENC peripheral base addresses
50232  * */
50233 #define IMAGING_LPCG_MJPEG_COMMON_ENC_BASE_ADDRS { IMAGING__LPCG_ENCODE_IPS_CLK_BASE, IMAGING__LPCG_ENCODE_JPEG_CLK_BASE }
50234 /** Array initializer of IMAGING_LPCG_MJPEG_COMMON_ENC peripheral base pointers
50235  * */
50236 #define IMAGING_LPCG_MJPEG_COMMON_ENC_BASE_PTRS  { IMAGING__LPCG_ENCODE_IPS_CLK, IMAGING__LPCG_ENCODE_JPEG_CLK }
50237 
50238 /*!
50239  * @}
50240  */ /* end of group IMAGING_LPCG_MJPEG_COMMON_ENC_Peripheral_Access_Layer */
50241 
50242 
50243 /* ----------------------------------------------------------------------------
50244    -- IMAGING_LPCG_PDMA0 Peripheral Access Layer
50245    ---------------------------------------------------------------------------- */
50246 
50247 /*!
50248  * @addtogroup IMAGING_LPCG_PDMA0_Peripheral_Access_Layer IMAGING_LPCG_PDMA0 Peripheral Access Layer
50249  * @{
50250  */
50251 
50252 /** IMAGING_LPCG_PDMA0 - Register Layout Typedef */
50253 typedef struct {
50254   __IO uint32_t LPCG_PDMA0_0;                      /**< na, offset: 0x0 */
50255 } IMAGING_LPCG_PDMA0_Type;
50256 
50257 /* ----------------------------------------------------------------------------
50258    -- IMAGING_LPCG_PDMA0 Register Masks
50259    ---------------------------------------------------------------------------- */
50260 
50261 /*!
50262  * @addtogroup IMAGING_LPCG_PDMA0_Register_Masks IMAGING_LPCG_PDMA0 Register Masks
50263  * @{
50264  */
50265 
50266 /*! @name LPCG_PDMA0_0 - na */
50267 /*! @{ */
50268 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_MASK (0x1U)
50269 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_SHIFT (0U)
50270 /*! isi_ipg_proc_clk_0_HWEN - Hardware Enable
50271  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50272  *  0b1..Enable HW automatic gating
50273  */
50274 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_MASK)
50275 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_MASK (0x2U)
50276 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_SHIFT (1U)
50277 /*! isi_ipg_proc_clk_0_SWEN - Software Enable
50278  *  0b0..Disable SW clock regardless of HWEN
50279  *  0b1..Enable SW clock gating
50280  */
50281 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_MASK)
50282 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_MASK (0x4U)
50283 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_SHIFT (2U)
50284 /*! LPCG_PDMA0_0_reserved_2_2 - reserved
50285  */
50286 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_MASK)
50287 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_MASK (0x8U)
50288 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_SHIFT (3U)
50289 /*! isi_ipg_proc_clk_0_STOP - show clock root status, 1 means clock stopped
50290  */
50291 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_MASK)
50292 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_MASK (0xFFFFFFF0U)
50293 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_SHIFT (4U)
50294 /*! LPCG_PDMA0_0_reserved_4_31 - reserved
50295  */
50296 #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_MASK)
50297 /*! @} */
50298 
50299 
50300 /*!
50301  * @}
50302  */ /* end of group IMAGING_LPCG_PDMA0_Register_Masks */
50303 
50304 
50305 /* IMAGING_LPCG_PDMA0 - Peripheral instance base addresses */
50306 /** Peripheral IMAGING__LPCG_PROC_CLK_0 base address */
50307 #define IMAGING__LPCG_PROC_CLK_0_BASE            (0x58500000u)
50308 /** Peripheral IMAGING__LPCG_PROC_CLK_0 base pointer */
50309 #define IMAGING__LPCG_PROC_CLK_0                 ((IMAGING_LPCG_PDMA0_Type *)IMAGING__LPCG_PROC_CLK_0_BASE)
50310 /** Array initializer of IMAGING_LPCG_PDMA0 peripheral base addresses */
50311 #define IMAGING_LPCG_PDMA0_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_0_BASE }
50312 /** Array initializer of IMAGING_LPCG_PDMA0 peripheral base pointers */
50313 #define IMAGING_LPCG_PDMA0_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_0 }
50314 
50315 /*!
50316  * @}
50317  */ /* end of group IMAGING_LPCG_PDMA0_Peripheral_Access_Layer */
50318 
50319 
50320 /* ----------------------------------------------------------------------------
50321    -- IMAGING_LPCG_PDMA1 Peripheral Access Layer
50322    ---------------------------------------------------------------------------- */
50323 
50324 /*!
50325  * @addtogroup IMAGING_LPCG_PDMA1_Peripheral_Access_Layer IMAGING_LPCG_PDMA1 Peripheral Access Layer
50326  * @{
50327  */
50328 
50329 /** IMAGING_LPCG_PDMA1 - Register Layout Typedef */
50330 typedef struct {
50331   __IO uint32_t LPCG_PDMA1_0;                      /**< na, offset: 0x0 */
50332 } IMAGING_LPCG_PDMA1_Type;
50333 
50334 /* ----------------------------------------------------------------------------
50335    -- IMAGING_LPCG_PDMA1 Register Masks
50336    ---------------------------------------------------------------------------- */
50337 
50338 /*!
50339  * @addtogroup IMAGING_LPCG_PDMA1_Register_Masks IMAGING_LPCG_PDMA1 Register Masks
50340  * @{
50341  */
50342 
50343 /*! @name LPCG_PDMA1_0 - na */
50344 /*! @{ */
50345 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_MASK (0x1U)
50346 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_SHIFT (0U)
50347 /*! isi_ipg_proc_clk_1_HWEN - Hardware Enable
50348  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50349  *  0b1..Enable HW automatic gating
50350  */
50351 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_MASK)
50352 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_MASK (0x2U)
50353 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_SHIFT (1U)
50354 /*! isi_ipg_proc_clk_1_SWEN - Software Enable
50355  *  0b0..Disable SW clock regardless of HWEN
50356  *  0b1..Enable SW clock gating
50357  */
50358 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_MASK)
50359 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_MASK (0x4U)
50360 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_SHIFT (2U)
50361 /*! LPCG_PDMA1_0_reserved_2_2 - reserved
50362  */
50363 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_MASK)
50364 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_MASK (0x8U)
50365 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_SHIFT (3U)
50366 /*! isi_ipg_proc_clk_1_STOP - show clock root status, 1 means clock stopped
50367  */
50368 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_MASK)
50369 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_MASK (0xFFFFFFF0U)
50370 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_SHIFT (4U)
50371 /*! LPCG_PDMA1_0_reserved_4_31 - reserved
50372  */
50373 #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_MASK)
50374 /*! @} */
50375 
50376 
50377 /*!
50378  * @}
50379  */ /* end of group IMAGING_LPCG_PDMA1_Register_Masks */
50380 
50381 
50382 /* IMAGING_LPCG_PDMA1 - Peripheral instance base addresses */
50383 /** Peripheral IMAGING__LPCG_PROC_CLK_1 base address */
50384 #define IMAGING__LPCG_PROC_CLK_1_BASE            (0x58510000u)
50385 /** Peripheral IMAGING__LPCG_PROC_CLK_1 base pointer */
50386 #define IMAGING__LPCG_PROC_CLK_1                 ((IMAGING_LPCG_PDMA1_Type *)IMAGING__LPCG_PROC_CLK_1_BASE)
50387 /** Array initializer of IMAGING_LPCG_PDMA1 peripheral base addresses */
50388 #define IMAGING_LPCG_PDMA1_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_1_BASE }
50389 /** Array initializer of IMAGING_LPCG_PDMA1 peripheral base pointers */
50390 #define IMAGING_LPCG_PDMA1_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_1 }
50391 
50392 /*!
50393  * @}
50394  */ /* end of group IMAGING_LPCG_PDMA1_Peripheral_Access_Layer */
50395 
50396 
50397 /* ----------------------------------------------------------------------------
50398    -- IMAGING_LPCG_PDMA2 Peripheral Access Layer
50399    ---------------------------------------------------------------------------- */
50400 
50401 /*!
50402  * @addtogroup IMAGING_LPCG_PDMA2_Peripheral_Access_Layer IMAGING_LPCG_PDMA2 Peripheral Access Layer
50403  * @{
50404  */
50405 
50406 /** IMAGING_LPCG_PDMA2 - Register Layout Typedef */
50407 typedef struct {
50408   __IO uint32_t LPCG_PDMA2_0;                      /**< na, offset: 0x0 */
50409 } IMAGING_LPCG_PDMA2_Type;
50410 
50411 /* ----------------------------------------------------------------------------
50412    -- IMAGING_LPCG_PDMA2 Register Masks
50413    ---------------------------------------------------------------------------- */
50414 
50415 /*!
50416  * @addtogroup IMAGING_LPCG_PDMA2_Register_Masks IMAGING_LPCG_PDMA2 Register Masks
50417  * @{
50418  */
50419 
50420 /*! @name LPCG_PDMA2_0 - na */
50421 /*! @{ */
50422 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_MASK (0x1U)
50423 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_SHIFT (0U)
50424 /*! isi_ipg_proc_clk_2_HWEN - Hardware Enable
50425  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50426  *  0b1..Enable HW automatic gating
50427  */
50428 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_MASK)
50429 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_MASK (0x2U)
50430 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_SHIFT (1U)
50431 /*! isi_ipg_proc_clk_2_SWEN - Software Enable
50432  *  0b0..Disable SW clock regardless of HWEN
50433  *  0b1..Enable SW clock gating
50434  */
50435 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_MASK)
50436 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_MASK (0x4U)
50437 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_SHIFT (2U)
50438 /*! LPCG_PDMA2_0_reserved_2_2 - reserved
50439  */
50440 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_MASK)
50441 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_MASK (0x8U)
50442 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_SHIFT (3U)
50443 /*! isi_ipg_proc_clk_2_STOP - show clock root status, 1 means clock stopped
50444  */
50445 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_MASK)
50446 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_MASK (0xFFFFFFF0U)
50447 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_SHIFT (4U)
50448 /*! LPCG_PDMA2_0_reserved_4_31 - reserved
50449  */
50450 #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_MASK)
50451 /*! @} */
50452 
50453 
50454 /*!
50455  * @}
50456  */ /* end of group IMAGING_LPCG_PDMA2_Register_Masks */
50457 
50458 
50459 /* IMAGING_LPCG_PDMA2 - Peripheral instance base addresses */
50460 /** Peripheral IMAGING__LPCG_PROC_CLK_2 base address */
50461 #define IMAGING__LPCG_PROC_CLK_2_BASE            (0x58520000u)
50462 /** Peripheral IMAGING__LPCG_PROC_CLK_2 base pointer */
50463 #define IMAGING__LPCG_PROC_CLK_2                 ((IMAGING_LPCG_PDMA2_Type *)IMAGING__LPCG_PROC_CLK_2_BASE)
50464 /** Array initializer of IMAGING_LPCG_PDMA2 peripheral base addresses */
50465 #define IMAGING_LPCG_PDMA2_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_2_BASE }
50466 /** Array initializer of IMAGING_LPCG_PDMA2 peripheral base pointers */
50467 #define IMAGING_LPCG_PDMA2_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_2 }
50468 
50469 /*!
50470  * @}
50471  */ /* end of group IMAGING_LPCG_PDMA2_Peripheral_Access_Layer */
50472 
50473 
50474 /* ----------------------------------------------------------------------------
50475    -- IMAGING_LPCG_PDMA3 Peripheral Access Layer
50476    ---------------------------------------------------------------------------- */
50477 
50478 /*!
50479  * @addtogroup IMAGING_LPCG_PDMA3_Peripheral_Access_Layer IMAGING_LPCG_PDMA3 Peripheral Access Layer
50480  * @{
50481  */
50482 
50483 /** IMAGING_LPCG_PDMA3 - Register Layout Typedef */
50484 typedef struct {
50485   __IO uint32_t LPCG_PDMA3_0;                      /**< na, offset: 0x0 */
50486 } IMAGING_LPCG_PDMA3_Type;
50487 
50488 /* ----------------------------------------------------------------------------
50489    -- IMAGING_LPCG_PDMA3 Register Masks
50490    ---------------------------------------------------------------------------- */
50491 
50492 /*!
50493  * @addtogroup IMAGING_LPCG_PDMA3_Register_Masks IMAGING_LPCG_PDMA3 Register Masks
50494  * @{
50495  */
50496 
50497 /*! @name LPCG_PDMA3_0 - na */
50498 /*! @{ */
50499 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_MASK (0x1U)
50500 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_SHIFT (0U)
50501 /*! isi_ipg_proc_clk_3_HWEN - Hardware Enable
50502  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50503  *  0b1..Enable HW automatic gating
50504  */
50505 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_MASK)
50506 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_MASK (0x2U)
50507 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_SHIFT (1U)
50508 /*! isi_ipg_proc_clk_3_SWEN - Software Enable
50509  *  0b0..Disable SW clock regardless of HWEN
50510  *  0b1..Enable SW clock gating
50511  */
50512 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_MASK)
50513 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_MASK (0x4U)
50514 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_SHIFT (2U)
50515 /*! LPCG_PDMA3_0_reserved_2_2 - reserved
50516  */
50517 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_MASK)
50518 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_MASK (0x8U)
50519 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_SHIFT (3U)
50520 /*! isi_ipg_proc_clk_3_STOP - show clock root status, 1 means clock stopped
50521  */
50522 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_MASK)
50523 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_MASK (0xFFFFFFF0U)
50524 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_SHIFT (4U)
50525 /*! LPCG_PDMA3_0_reserved_4_31 - reserved
50526  */
50527 #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_MASK)
50528 /*! @} */
50529 
50530 
50531 /*!
50532  * @}
50533  */ /* end of group IMAGING_LPCG_PDMA3_Register_Masks */
50534 
50535 
50536 /* IMAGING_LPCG_PDMA3 - Peripheral instance base addresses */
50537 /** Peripheral IMAGING__LPCG_PROC_CLK_3 base address */
50538 #define IMAGING__LPCG_PROC_CLK_3_BASE            (0x58530000u)
50539 /** Peripheral IMAGING__LPCG_PROC_CLK_3 base pointer */
50540 #define IMAGING__LPCG_PROC_CLK_3                 ((IMAGING_LPCG_PDMA3_Type *)IMAGING__LPCG_PROC_CLK_3_BASE)
50541 /** Array initializer of IMAGING_LPCG_PDMA3 peripheral base addresses */
50542 #define IMAGING_LPCG_PDMA3_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_3_BASE }
50543 /** Array initializer of IMAGING_LPCG_PDMA3 peripheral base pointers */
50544 #define IMAGING_LPCG_PDMA3_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_3 }
50545 
50546 /*!
50547  * @}
50548  */ /* end of group IMAGING_LPCG_PDMA3_Peripheral_Access_Layer */
50549 
50550 
50551 /* ----------------------------------------------------------------------------
50552    -- IMAGING_LPCG_PDMA4 Peripheral Access Layer
50553    ---------------------------------------------------------------------------- */
50554 
50555 /*!
50556  * @addtogroup IMAGING_LPCG_PDMA4_Peripheral_Access_Layer IMAGING_LPCG_PDMA4 Peripheral Access Layer
50557  * @{
50558  */
50559 
50560 /** IMAGING_LPCG_PDMA4 - Register Layout Typedef */
50561 typedef struct {
50562   __IO uint32_t LPCG_PDMA4_0;                      /**< na, offset: 0x0 */
50563 } IMAGING_LPCG_PDMA4_Type;
50564 
50565 /* ----------------------------------------------------------------------------
50566    -- IMAGING_LPCG_PDMA4 Register Masks
50567    ---------------------------------------------------------------------------- */
50568 
50569 /*!
50570  * @addtogroup IMAGING_LPCG_PDMA4_Register_Masks IMAGING_LPCG_PDMA4 Register Masks
50571  * @{
50572  */
50573 
50574 /*! @name LPCG_PDMA4_0 - na */
50575 /*! @{ */
50576 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_MASK (0x1U)
50577 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_SHIFT (0U)
50578 /*! isi_ipg_proc_clk_4_HWEN - Hardware Enable
50579  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50580  *  0b1..Enable HW automatic gating
50581  */
50582 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_MASK)
50583 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_MASK (0x2U)
50584 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_SHIFT (1U)
50585 /*! isi_ipg_proc_clk_4_SWEN - Software Enable
50586  *  0b0..Disable SW clock regardless of HWEN
50587  *  0b1..Enable SW clock gating
50588  */
50589 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_MASK)
50590 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_MASK (0x4U)
50591 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_SHIFT (2U)
50592 /*! LPCG_PDMA4_0_reserved_2_2 - reserved
50593  */
50594 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_MASK)
50595 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_MASK (0x8U)
50596 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_SHIFT (3U)
50597 /*! isi_ipg_proc_clk_4_STOP - show clock root status, 1 means clock stopped
50598  */
50599 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_MASK)
50600 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_MASK (0xFFFFFFF0U)
50601 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_SHIFT (4U)
50602 /*! LPCG_PDMA4_0_reserved_4_31 - reserved
50603  */
50604 #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_MASK)
50605 /*! @} */
50606 
50607 
50608 /*!
50609  * @}
50610  */ /* end of group IMAGING_LPCG_PDMA4_Register_Masks */
50611 
50612 
50613 /* IMAGING_LPCG_PDMA4 - Peripheral instance base addresses */
50614 /** Peripheral IMAGING__LPCG_PROC_CLK_4 base address */
50615 #define IMAGING__LPCG_PROC_CLK_4_BASE            (0x58540000u)
50616 /** Peripheral IMAGING__LPCG_PROC_CLK_4 base pointer */
50617 #define IMAGING__LPCG_PROC_CLK_4                 ((IMAGING_LPCG_PDMA4_Type *)IMAGING__LPCG_PROC_CLK_4_BASE)
50618 /** Array initializer of IMAGING_LPCG_PDMA4 peripheral base addresses */
50619 #define IMAGING_LPCG_PDMA4_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_4_BASE }
50620 /** Array initializer of IMAGING_LPCG_PDMA4 peripheral base pointers */
50621 #define IMAGING_LPCG_PDMA4_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_4 }
50622 
50623 /*!
50624  * @}
50625  */ /* end of group IMAGING_LPCG_PDMA4_Peripheral_Access_Layer */
50626 
50627 
50628 /* ----------------------------------------------------------------------------
50629    -- IMAGING_LPCG_PDMA5 Peripheral Access Layer
50630    ---------------------------------------------------------------------------- */
50631 
50632 /*!
50633  * @addtogroup IMAGING_LPCG_PDMA5_Peripheral_Access_Layer IMAGING_LPCG_PDMA5 Peripheral Access Layer
50634  * @{
50635  */
50636 
50637 /** IMAGING_LPCG_PDMA5 - Register Layout Typedef */
50638 typedef struct {
50639   __IO uint32_t LPCG_PDMA5_0;                      /**< na, offset: 0x0 */
50640 } IMAGING_LPCG_PDMA5_Type;
50641 
50642 /* ----------------------------------------------------------------------------
50643    -- IMAGING_LPCG_PDMA5 Register Masks
50644    ---------------------------------------------------------------------------- */
50645 
50646 /*!
50647  * @addtogroup IMAGING_LPCG_PDMA5_Register_Masks IMAGING_LPCG_PDMA5 Register Masks
50648  * @{
50649  */
50650 
50651 /*! @name LPCG_PDMA5_0 - na */
50652 /*! @{ */
50653 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_MASK (0x1U)
50654 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_SHIFT (0U)
50655 /*! isi_ipg_proc_clk_5_HWEN - Hardware Enable
50656  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50657  *  0b1..Enable HW automatic gating
50658  */
50659 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_MASK)
50660 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_MASK (0x2U)
50661 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_SHIFT (1U)
50662 /*! isi_ipg_proc_clk_5_SWEN - Software Enable
50663  *  0b0..Disable SW clock regardless of HWEN
50664  *  0b1..Enable SW clock gating
50665  */
50666 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_MASK)
50667 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_MASK (0x4U)
50668 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_SHIFT (2U)
50669 /*! LPCG_PDMA5_0_reserved_2_2 - reserved
50670  */
50671 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_MASK)
50672 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_MASK (0x8U)
50673 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_SHIFT (3U)
50674 /*! isi_ipg_proc_clk_5_STOP - show clock root status, 1 means clock stopped
50675  */
50676 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_MASK)
50677 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_MASK (0xFFFFFFF0U)
50678 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_SHIFT (4U)
50679 /*! LPCG_PDMA5_0_reserved_4_31 - reserved
50680  */
50681 #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_MASK)
50682 /*! @} */
50683 
50684 
50685 /*!
50686  * @}
50687  */ /* end of group IMAGING_LPCG_PDMA5_Register_Masks */
50688 
50689 
50690 /* IMAGING_LPCG_PDMA5 - Peripheral instance base addresses */
50691 /** Peripheral IMAGING__LPCG_PROC_CLK_5 base address */
50692 #define IMAGING__LPCG_PROC_CLK_5_BASE            (0x58550000u)
50693 /** Peripheral IMAGING__LPCG_PROC_CLK_5 base pointer */
50694 #define IMAGING__LPCG_PROC_CLK_5                 ((IMAGING_LPCG_PDMA5_Type *)IMAGING__LPCG_PROC_CLK_5_BASE)
50695 /** Array initializer of IMAGING_LPCG_PDMA5 peripheral base addresses */
50696 #define IMAGING_LPCG_PDMA5_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_5_BASE }
50697 /** Array initializer of IMAGING_LPCG_PDMA5 peripheral base pointers */
50698 #define IMAGING_LPCG_PDMA5_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_5 }
50699 
50700 /*!
50701  * @}
50702  */ /* end of group IMAGING_LPCG_PDMA5_Peripheral_Access_Layer */
50703 
50704 
50705 /* ----------------------------------------------------------------------------
50706    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Peripheral Access Layer
50707    ---------------------------------------------------------------------------- */
50708 
50709 /*!
50710  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Peripheral Access Layer
50711  * @{
50712  */
50713 
50714 /** IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 - Register Layout Typedef */
50715 typedef struct {
50716   __IO uint32_t LPCG_PIXEL_LINK_SLAVE_CSI1_0;      /**< na, offset: 0x0 */
50717 } IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Type;
50718 
50719 /* ----------------------------------------------------------------------------
50720    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Register Masks
50721    ---------------------------------------------------------------------------- */
50722 
50723 /*!
50724  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Register Masks
50725  * @{
50726  */
50727 
50728 /*! @name LPCG_PIXEL_LINK_SLAVE_CSI1_0 - na */
50729 /*! @{ */
50730 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_MASK (0x1U)
50731 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_SHIFT (0U)
50732 /*! LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0 - reserved
50733  */
50734 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_MASK)
50735 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_MASK (0x2U)
50736 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_SHIFT (1U)
50737 /*! pixel_link_slv_csi1_ingress_clk_SWEN - Software Enable
50738  *  0b0..Disable SW clock regardless of HWEN
50739  *  0b1..Enable SW clock gating
50740  */
50741 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_MASK)
50742 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_MASK (0x4U)
50743 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_SHIFT (2U)
50744 /*! LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2 - reserved
50745  */
50746 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_MASK)
50747 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_MASK (0x8U)
50748 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_SHIFT (3U)
50749 /*! pixel_link_slv_csi1_ingress_clk_STOP - show clock root status, 1 means clock stopped
50750  */
50751 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_MASK)
50752 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_MASK (0xFFFFFFF0U)
50753 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_SHIFT (4U)
50754 /*! LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31 - reserved
50755  */
50756 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_MASK)
50757 /*! @} */
50758 
50759 
50760 /*!
50761  * @}
50762  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Register_Masks */
50763 
50764 
50765 /* IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 - Peripheral instance base addresses */
50766 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 base address */
50767 #define IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE   (0x58580000u)
50768 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 base pointer */
50769 #define IMAGING__LPCG_PIXEL_LINK_SLV_CSI0        ((IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE)
50770 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 peripheral base
50771  * addresses */
50772 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE }
50773 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 peripheral base
50774  * pointers */
50775 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 }
50776 
50777 /*!
50778  * @}
50779  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Peripheral_Access_Layer */
50780 
50781 
50782 /* ----------------------------------------------------------------------------
50783    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Peripheral Access Layer
50784    ---------------------------------------------------------------------------- */
50785 
50786 /*!
50787  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Peripheral Access Layer
50788  * @{
50789  */
50790 
50791 /** IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 - Register Layout Typedef */
50792 typedef struct {
50793   __IO uint32_t LPCG_PIXEL_LINK_SLAVE_CSI2_0;      /**< na, offset: 0x0 */
50794 } IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Type;
50795 
50796 /* ----------------------------------------------------------------------------
50797    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Register Masks
50798    ---------------------------------------------------------------------------- */
50799 
50800 /*!
50801  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Register Masks
50802  * @{
50803  */
50804 
50805 /*! @name LPCG_PIXEL_LINK_SLAVE_CSI2_0 - na */
50806 /*! @{ */
50807 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_MASK (0x1U)
50808 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_SHIFT (0U)
50809 /*! LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0 - reserved
50810  */
50811 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_MASK)
50812 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_MASK (0x2U)
50813 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_SHIFT (1U)
50814 /*! pixel_link_slv_csi2_ingress_clk_SWEN - Software Enable
50815  *  0b0..Disable SW clock regardless of HWEN
50816  *  0b1..Enable SW clock gating
50817  */
50818 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_MASK)
50819 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_MASK (0x4U)
50820 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_SHIFT (2U)
50821 /*! LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2 - reserved
50822  */
50823 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_MASK)
50824 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_MASK (0x8U)
50825 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_SHIFT (3U)
50826 /*! pixel_link_slv_csi2_ingress_clk_STOP - show clock root status, 1 means clock stopped
50827  */
50828 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_MASK)
50829 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_MASK (0xFFFFFFF0U)
50830 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_SHIFT (4U)
50831 /*! LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31 - reserved
50832  */
50833 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_MASK)
50834 /*! @} */
50835 
50836 
50837 /*!
50838  * @}
50839  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Register_Masks */
50840 
50841 
50842 /* IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 - Peripheral instance base addresses */
50843 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 base address */
50844 #define IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE   (0x58590000u)
50845 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 base pointer */
50846 #define IMAGING__LPCG_PIXEL_LINK_SLV_CSI1        ((IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE)
50847 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 peripheral base
50848  * addresses */
50849 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE }
50850 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 peripheral base
50851  * pointers */
50852 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 }
50853 
50854 /*!
50855  * @}
50856  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Peripheral_Access_Layer */
50857 
50858 
50859 /* ----------------------------------------------------------------------------
50860    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Peripheral Access Layer
50861    ---------------------------------------------------------------------------- */
50862 
50863 /*!
50864  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Peripheral Access Layer
50865  * @{
50866  */
50867 
50868 /** IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 - Register Layout Typedef */
50869 typedef struct {
50870   __IO uint32_t LPCG_PIXEL_LINK_SLAVE_DC0_0;       /**< na, offset: 0x0 */
50871 } IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Type;
50872 
50873 /* ----------------------------------------------------------------------------
50874    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Register Masks
50875    ---------------------------------------------------------------------------- */
50876 
50877 /*!
50878  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Register Masks
50879  * @{
50880  */
50881 
50882 /*! @name LPCG_PIXEL_LINK_SLAVE_DC0_0 - na */
50883 /*! @{ */
50884 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_MASK (0x1U)
50885 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_SHIFT (0U)
50886 /*! LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0 - reserved
50887  */
50888 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_MASK)
50889 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_MASK (0x2U)
50890 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_SHIFT (1U)
50891 /*! pixel_link_slv_dc0_ingress_clk_SWEN - Software Enable
50892  *  0b0..Disable SW clock regardless of HWEN
50893  *  0b1..Enable SW clock gating
50894  */
50895 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_MASK)
50896 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_MASK (0x4U)
50897 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_SHIFT (2U)
50898 /*! LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2 - reserved
50899  */
50900 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_MASK)
50901 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_MASK (0x8U)
50902 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_SHIFT (3U)
50903 /*! pixel_link_slv_dc0_ingress_clk_STOP - show clock root status, 1 means clock stopped
50904  */
50905 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_MASK)
50906 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_MASK (0xFFFFFFF0U)
50907 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_SHIFT (4U)
50908 /*! LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31 - reserved
50909  */
50910 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_MASK)
50911 /*! @} */
50912 
50913 
50914 /*!
50915  * @}
50916  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Register_Masks */
50917 
50918 
50919 /* IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 - Peripheral instance base addresses */
50920 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK base address */
50921 #define IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE (0x585C0000u)
50922 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK base pointer */
50923 #define IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE)
50924 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 peripheral base
50925  * addresses */
50926 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE }
50927 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 peripheral base
50928  * pointers */
50929 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK }
50930 
50931 /*!
50932  * @}
50933  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Peripheral_Access_Layer */
50934 
50935 
50936 /* ----------------------------------------------------------------------------
50937    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Peripheral Access Layer
50938    ---------------------------------------------------------------------------- */
50939 
50940 /*!
50941  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Peripheral Access Layer
50942  * @{
50943  */
50944 
50945 /** IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 - Register Layout Typedef */
50946 typedef struct {
50947   __IO uint32_t LPCG_PIXEL_LINK_SLAVE_DC1_0;       /**< na, offset: 0x0 */
50948 } IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Type;
50949 
50950 /* ----------------------------------------------------------------------------
50951    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Register Masks
50952    ---------------------------------------------------------------------------- */
50953 
50954 /*!
50955  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Register Masks
50956  * @{
50957  */
50958 
50959 /*! @name LPCG_PIXEL_LINK_SLAVE_DC1_0 - na */
50960 /*! @{ */
50961 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_MASK (0x1U)
50962 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_SHIFT (0U)
50963 /*! LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0 - reserved
50964  */
50965 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_MASK)
50966 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_MASK (0x2U)
50967 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_SHIFT (1U)
50968 /*! pixel_link_slv_dc1_ingress_clk_SWEN - Software Enable
50969  *  0b0..Disable SW clock regardless of HWEN
50970  *  0b1..Enable SW clock gating
50971  */
50972 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_MASK)
50973 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_MASK (0x4U)
50974 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_SHIFT (2U)
50975 /*! LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2 - reserved
50976  */
50977 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_MASK)
50978 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_MASK (0x8U)
50979 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_SHIFT (3U)
50980 /*! pixel_link_slv_dc1_ingress_clk_STOP - show clock root status, 1 means clock stopped
50981  */
50982 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_MASK)
50983 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_MASK (0xFFFFFFF0U)
50984 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_SHIFT (4U)
50985 /*! LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31 - reserved
50986  */
50987 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_MASK)
50988 /*! @} */
50989 
50990 
50991 /*!
50992  * @}
50993  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Register_Masks */
50994 
50995 
50996 /* IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 - Peripheral instance base addresses */
50997 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK base address */
50998 #define IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE (0x585E0000u)
50999 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK base pointer */
51000 #define IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE)
51001 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 peripheral base
51002  * addresses */
51003 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE }
51004 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 peripheral base
51005  * pointers */
51006 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK }
51007 
51008 /*!
51009  * @}
51010  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Peripheral_Access_Layer */
51011 
51012 
51013 /* ----------------------------------------------------------------------------
51014    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Peripheral Access Layer
51015    ---------------------------------------------------------------------------- */
51016 
51017 /*!
51018  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Peripheral Access Layer
51019  * @{
51020  */
51021 
51022 /** IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN - Register Layout Typedef */
51023 typedef struct {
51024   __IO uint32_t LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0;   /**< na, offset: 0x0 */
51025 } IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Type;
51026 
51027 /* ----------------------------------------------------------------------------
51028    -- IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Register Masks
51029    ---------------------------------------------------------------------------- */
51030 
51031 /*!
51032  * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Register Masks
51033  * @{
51034  */
51035 
51036 /*! @name LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0 - na */
51037 /*! @{ */
51038 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_MASK (0x1U)
51039 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_SHIFT (0U)
51040 /*! LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0 - reserved
51041  */
51042 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_MASK)
51043 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_MASK (0x2U)
51044 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_SHIFT (1U)
51045 /*! pixel_link_slv_hdmi_in_ingress_clk_SWEN - Software Enable
51046  *  0b0..Disable SW clock regardless of HWEN
51047  *  0b1..Enable SW clock gating
51048  */
51049 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_MASK)
51050 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_MASK (0x4U)
51051 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_SHIFT (2U)
51052 /*! LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2 - reserved
51053  */
51054 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_MASK)
51055 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_MASK (0x8U)
51056 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_SHIFT (3U)
51057 /*! pixel_link_slv_hdmi_in_ingress_clk_STOP - show clock root status, 1 means clock stopped
51058  */
51059 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_MASK)
51060 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_MASK (0xFFFFFFF0U)
51061 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_SHIFT (4U)
51062 /*! LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31 - reserved
51063  */
51064 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_MASK)
51065 /*! @} */
51066 
51067 
51068 /*!
51069  * @}
51070  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Register_Masks */
51071 
51072 
51073 /* IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN - Peripheral instance base addresses */
51074 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK base address */
51075 #define IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE (0x585A0000u)
51076 /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK base pointer */
51077 #define IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE)
51078 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN peripheral base
51079  * addresses */
51080 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE }
51081 /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN peripheral base
51082  * pointers */
51083 #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK }
51084 
51085 /*!
51086  * @}
51087  */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Peripheral_Access_Layer */
51088 
51089 
51090 /* ----------------------------------------------------------------------------
51091    -- INTMUX Peripheral Access Layer
51092    ---------------------------------------------------------------------------- */
51093 
51094 /*!
51095  * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer
51096  * @{
51097  */
51098 
51099 /** INTMUX - Register Layout Typedef */
51100 typedef struct {
51101   struct {                                         /* offset: 0x0, array step: 0x40 */
51102     __IO uint32_t CHn_CSR;                           /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */
51103     __I  uint32_t CHn_VEC;                           /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */
51104          uint8_t RESERVED_0[8];
51105     __IO uint32_t CHn_IER_31_0;                      /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */
51106          uint8_t RESERVED_1[12];
51107     __I  uint32_t CHn_IPR_31_0;                      /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */
51108          uint8_t RESERVED_2[28];
51109   } CHANNEL[8];
51110 } INTMUX_Type;
51111 
51112 /* ----------------------------------------------------------------------------
51113    -- INTMUX Register Masks
51114    ---------------------------------------------------------------------------- */
51115 
51116 /*!
51117  * @addtogroup INTMUX_Register_Masks INTMUX Register Masks
51118  * @{
51119  */
51120 
51121 /*! @name CHn_CSR - Channel n Control Status Register */
51122 /*! @{ */
51123 #define INTMUX_CHn_CSR_RST_MASK                  (0x1U)
51124 #define INTMUX_CHn_CSR_RST_SHIFT                 (0U)
51125 /*! RST - Software Reset
51126  *  0b0..No operation.
51127  *  0b1..Perform a software reset on this channel.
51128  */
51129 #define INTMUX_CHn_CSR_RST(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK)
51130 #define INTMUX_CHn_CSR_AND_MASK                  (0x2U)
51131 #define INTMUX_CHn_CSR_AND_SHIFT                 (1U)
51132 /*! AND - Logic AND
51133  *  0b0..Logic OR all enabled interrupt inputs.
51134  *  0b1..Logic AND all enabled interrupt inputs.
51135  */
51136 #define INTMUX_CHn_CSR_AND(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK)
51137 #define INTMUX_CHn_CSR_IRQN_MASK                 (0x30U)
51138 #define INTMUX_CHn_CSR_IRQN_SHIFT                (4U)
51139 /*! IRQN - Channel Input Number
51140  *  0b00..32 interrupt inputs
51141  *  0b01..Reserved
51142  *  0b10..Reserved
51143  *  0b11..Reserved
51144  */
51145 #define INTMUX_CHn_CSR_IRQN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK)
51146 #define INTMUX_CHn_CSR_CHIN_MASK                 (0xF00U)
51147 #define INTMUX_CHn_CSR_CHIN_SHIFT                (8U)
51148 /*! CHIN - Channel Instance Number
51149  */
51150 #define INTMUX_CHn_CSR_CHIN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK)
51151 #define INTMUX_CHn_CSR_IRQP_MASK                 (0x80000000U)
51152 #define INTMUX_CHn_CSR_IRQP_SHIFT                (31U)
51153 /*! IRQP - Channel Interrupt Request Pending
51154  *  0b0..No interrupt is pending.
51155  *  0b1..The interrupt output of this channel is pending.
51156  */
51157 #define INTMUX_CHn_CSR_IRQP(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)
51158 /*! @} */
51159 
51160 /* The count of INTMUX_CHn_CSR */
51161 #define INTMUX_CHn_CSR_COUNT                     (8U)
51162 
51163 /*! @name CHn_VEC - Channel n Vector Number Register */
51164 /*! @{ */
51165 #define INTMUX_CHn_VEC_VECN_MASK                 (0x3FFCU)
51166 #define INTMUX_CHn_VEC_VECN_SHIFT                (2U)
51167 /*! VECN - Vector Number
51168  */
51169 #define INTMUX_CHn_VEC_VECN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK)
51170 /*! @} */
51171 
51172 /* The count of INTMUX_CHn_VEC */
51173 #define INTMUX_CHn_VEC_COUNT                     (8U)
51174 
51175 /*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */
51176 /*! @{ */
51177 #define INTMUX_CHn_IER_31_0_INTE_MASK            (0xFFFFFFFFU)
51178 #define INTMUX_CHn_IER_31_0_INTE_SHIFT           (0U)
51179 /*! INTE - Interrupt Enable
51180  */
51181 #define INTMUX_CHn_IER_31_0_INTE(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK)
51182 /*! @} */
51183 
51184 /* The count of INTMUX_CHn_IER_31_0 */
51185 #define INTMUX_CHn_IER_31_0_COUNT                (8U)
51186 
51187 /*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */
51188 /*! @{ */
51189 #define INTMUX_CHn_IPR_31_0_INTP_MASK            (0xFFFFFFFFU)
51190 #define INTMUX_CHn_IPR_31_0_INTP_SHIFT           (0U)
51191 /*! INTP - Interrupt Pending
51192  */
51193 #define INTMUX_CHn_IPR_31_0_INTP(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK)
51194 /*! @} */
51195 
51196 /* The count of INTMUX_CHn_IPR_31_0 */
51197 #define INTMUX_CHn_IPR_31_0_COUNT                (8U)
51198 
51199 
51200 /*!
51201  * @}
51202  */ /* end of group INTMUX_Register_Masks */
51203 
51204 
51205 /* INTMUX - Peripheral instance base addresses */
51206 /** Peripheral CM4__INTMUX base address */
51207 #define CM4__INTMUX_BASE                         (0x41400000u)
51208 /** Peripheral CM4__INTMUX base pointer */
51209 #define CM4__INTMUX                              ((INTMUX_Type *)CM4__INTMUX_BASE)
51210 /** Peripheral SCU__INTMUX base address */
51211 #define SCU__INTMUX_BASE                         (0x33400000u)
51212 /** Peripheral SCU__INTMUX base pointer */
51213 #define SCU__INTMUX                              ((INTMUX_Type *)SCU__INTMUX_BASE)
51214 /** Array initializer of INTMUX peripheral base addresses */
51215 #define INTMUX_BASE_ADDRS                        { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
51216 /** Array initializer of INTMUX peripheral base pointers */
51217 #define INTMUX_BASE_PTRS                         { CM4__INTMUX, SCU__INTMUX }
51218 
51219 /*!
51220  * @}
51221  */ /* end of group INTMUX_Peripheral_Access_Layer */
51222 
51223 
51224 /* ----------------------------------------------------------------------------
51225    -- IOMUXD Peripheral Access Layer
51226    ---------------------------------------------------------------------------- */
51227 
51228 /*!
51229  * @addtogroup IOMUXD_Peripheral_Access_Layer IOMUXD Peripheral Access Layer
51230  * @{
51231  */
51232 
51233 /** IOMUXD - Register Layout Typedef */
51234 typedef struct {
51235   __IO uint32_t PCIE_CTRL0_PERST_B;                /**< PCIE_CTRL0_PERST_B, offset: 0x0 */
51236        uint8_t RESERVED_0[60];
51237   __IO uint32_t PCIE_CTRL0_CLKREQ_B;               /**< PCIE_CTRL0_CLKREQ_B, offset: 0x40 */
51238        uint8_t RESERVED_1[60];
51239   __IO uint32_t PCIE_CTRL0_WAKE_B;                 /**< PCIE_CTRL0_WAKE_B, offset: 0x80 */
51240        uint8_t RESERVED_2[60];
51241   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP, offset: 0xC0 */
51242        uint8_t RESERVED_3[60];
51243   __IO uint32_t USB_SS3_TC0;                       /**< USB_SS3_TC0, offset: 0x100 */
51244        uint8_t RESERVED_4[60];
51245   __IO uint32_t USB_SS3_TC1;                       /**< USB_SS3_TC1, offset: 0x140 */
51246        uint8_t RESERVED_5[60];
51247   __IO uint32_t USB_SS3_TC2;                       /**< USB_SS3_TC2, offset: 0x180 */
51248        uint8_t RESERVED_6[60];
51249   __IO uint32_t USB_SS3_TC3;                       /**< USB_SS3_TC3, offset: 0x1C0 */
51250        uint8_t RESERVED_7[60];
51251   __IO uint32_t IOMUXD_COMP_CTL_GPIO_3V3_USB3IO;   /**< IOMUXD_COMP_CTL_GPIO_3V3_USB3IO, offset: 0x200 */
51252        uint8_t RESERVED_8[508];
51253   __I  uint32_t IOMUXD_GROUP_0_0;                  /**< na, offset: 0x400 */
51254        uint8_t RESERVED_9[130044];
51255   __IO uint32_t EMMC0_CLK;                         /**< EMMC0_CLK, offset: 0x20000 */
51256        uint8_t RESERVED_10[60];
51257   __IO uint32_t EMMC0_CMD;                         /**< EMMC0_CMD, offset: 0x20040 */
51258        uint8_t RESERVED_11[60];
51259   __IO uint32_t EMMC0_DATA0;                       /**< EMMC0_DATA0, offset: 0x20080 */
51260        uint8_t RESERVED_12[60];
51261   __IO uint32_t EMMC0_DATA1;                       /**< EMMC0_DATA1, offset: 0x200C0 */
51262        uint8_t RESERVED_13[60];
51263   __IO uint32_t EMMC0_DATA2;                       /**< EMMC0_DATA2, offset: 0x20100 */
51264        uint8_t RESERVED_14[60];
51265   __IO uint32_t EMMC0_DATA3;                       /**< EMMC0_DATA3, offset: 0x20140 */
51266        uint8_t RESERVED_15[60];
51267   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0, offset: 0x20180 */
51268        uint8_t RESERVED_16[60];
51269   __IO uint32_t EMMC0_DATA4;                       /**< EMMC0_DATA4, offset: 0x201C0 */
51270        uint8_t RESERVED_17[60];
51271   __IO uint32_t EMMC0_DATA5;                       /**< EMMC0_DATA5, offset: 0x20200 */
51272        uint8_t RESERVED_18[60];
51273   __IO uint32_t EMMC0_DATA6;                       /**< EMMC0_DATA6, offset: 0x20240 */
51274        uint8_t RESERVED_19[60];
51275   __IO uint32_t EMMC0_DATA7;                       /**< EMMC0_DATA7, offset: 0x20280 */
51276        uint8_t RESERVED_20[60];
51277   __IO uint32_t EMMC0_STROBE;                      /**< EMMC0_STROBE, offset: 0x202C0 */
51278        uint8_t RESERVED_21[60];
51279   __IO uint32_t EMMC0_RESET_B;                     /**< EMMC0_RESET_B, offset: 0x20300 */
51280        uint8_t RESERVED_22[60];
51281   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1, offset: 0x20340 */
51282        uint8_t RESERVED_23[60];
51283   __IO uint32_t USDHC1_RESET_B;                    /**< USDHC1_RESET_B, offset: 0x20380 */
51284        uint8_t RESERVED_24[124];
51285   __I  uint32_t IOMUXD_GROUP_1_0;                  /**< na, offset: 0x20400 */
51286        uint8_t RESERVED_25[3068];
51287   __IO uint32_t USDHC1_VSELECT;                    /**< USDHC1_VSELECT, offset: 0x21000 */
51288        uint8_t RESERVED_26[60];
51289   __IO uint32_t IOMUXD_CTL_NAND_RE_P_N;            /**< IOMUXD_CTL_NAND_RE_P_N, offset: 0x21040 */
51290        uint8_t RESERVED_27[60];
51291   __IO uint32_t USDHC1_WP;                         /**< USDHC1_WP, offset: 0x21080 */
51292        uint8_t RESERVED_28[60];
51293   __IO uint32_t USDHC1_CD_B;                       /**< USDHC1_CD_B, offset: 0x210C0 */
51294        uint8_t RESERVED_29[60];
51295   __IO uint32_t IOMUXD_CTL_NAND_DQS_P_N;           /**< IOMUXD_CTL_NAND_DQS_P_N, offset: 0x21100 */
51296        uint8_t RESERVED_30[60];
51297   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP, offset: 0x21140 */
51298        uint8_t RESERVED_31[60];
51299   __IO uint32_t USDHC1_CLK;                        /**< USDHC1_CLK, offset: 0x21180 */
51300        uint8_t RESERVED_32[60];
51301   __IO uint32_t USDHC1_CMD;                        /**< USDHC1_CMD, offset: 0x211C0 */
51302        uint8_t RESERVED_33[60];
51303   __IO uint32_t USDHC1_DATA0;                      /**< USDHC1_DATA0, offset: 0x21200 */
51304        uint8_t RESERVED_34[60];
51305   __IO uint32_t USDHC1_DATA1;                      /**< USDHC1_DATA1, offset: 0x21240 */
51306        uint8_t RESERVED_35[60];
51307   __IO uint32_t USDHC1_DATA2;                      /**< USDHC1_DATA2, offset: 0x21280 */
51308        uint8_t RESERVED_36[60];
51309   __IO uint32_t USDHC1_DATA3;                      /**< USDHC1_DATA3, offset: 0x212C0 */
51310        uint8_t RESERVED_37[60];
51311   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3, offset: 0x21300 */
51312        uint8_t RESERVED_38[60];
51313   __IO uint32_t ENET0_RGMII_TXC;                   /**< ENET0_RGMII_TXC, offset: 0x21340 */
51314        uint8_t RESERVED_39[60];
51315   __IO uint32_t ENET0_RGMII_TX_CTL;                /**< ENET0_RGMII_TX_CTL, offset: 0x21380 */
51316        uint8_t RESERVED_40[124];
51317   __I  uint32_t IOMUXD_GROUP_1_1;                  /**< na, offset: 0x21400 */
51318        uint8_t RESERVED_41[3068];
51319   __IO uint32_t ENET0_RGMII_TXD0;                  /**< ENET0_RGMII_TXD0, offset: 0x22000 */
51320        uint8_t RESERVED_42[60];
51321   __IO uint32_t ENET0_RGMII_TXD1;                  /**< ENET0_RGMII_TXD1, offset: 0x22040 */
51322        uint8_t RESERVED_43[60];
51323   __IO uint32_t ENET0_RGMII_TXD2;                  /**< ENET0_RGMII_TXD2, offset: 0x22080 */
51324        uint8_t RESERVED_44[60];
51325   __IO uint32_t ENET0_RGMII_TXD3;                  /**< ENET0_RGMII_TXD3, offset: 0x220C0 */
51326        uint8_t RESERVED_45[60];
51327   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0, offset: 0x22100 */
51328        uint8_t RESERVED_46[60];
51329   __IO uint32_t ENET0_RGMII_RXC;                   /**< ENET0_RGMII_RXC, offset: 0x22140 */
51330        uint8_t RESERVED_47[60];
51331   __IO uint32_t ENET0_RGMII_RX_CTL;                /**< ENET0_RGMII_RX_CTL, offset: 0x22180 */
51332        uint8_t RESERVED_48[60];
51333   __IO uint32_t ENET0_RGMII_RXD0;                  /**< ENET0_RGMII_RXD0, offset: 0x221C0 */
51334        uint8_t RESERVED_49[60];
51335   __IO uint32_t ENET0_RGMII_RXD1;                  /**< ENET0_RGMII_RXD1, offset: 0x22200 */
51336        uint8_t RESERVED_50[60];
51337   __IO uint32_t ENET0_RGMII_RXD2;                  /**< ENET0_RGMII_RXD2, offset: 0x22240 */
51338        uint8_t RESERVED_51[60];
51339   __IO uint32_t ENET0_RGMII_RXD3;                  /**< ENET0_RGMII_RXD3, offset: 0x22280 */
51340        uint8_t RESERVED_52[60];
51341   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1, offset: 0x222C0 */
51342        uint8_t RESERVED_53[60];
51343   __IO uint32_t ENET0_REFCLK_125M_25M;             /**< ENET0_REFCLK_125M_25M, offset: 0x22300 */
51344        uint8_t RESERVED_54[252];
51345   __I  uint32_t IOMUXD_GROUP_1_2;                  /**< na, offset: 0x22400 */
51346        uint8_t RESERVED_55[3068];
51347   __IO uint32_t ENET0_MDIO;                        /**< ENET0_MDIO, offset: 0x23000 */
51348        uint8_t RESERVED_56[60];
51349   __IO uint32_t ENET0_MDC;                         /**< ENET0_MDC, offset: 0x23040 */
51350        uint8_t RESERVED_57[60];
51351   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT, offset: 0x23080 */
51352        uint8_t RESERVED_58[60];
51353   __IO uint32_t ESAI0_FSR;                         /**< ESAI0_FSR, offset: 0x230C0 */
51354        uint8_t RESERVED_59[60];
51355   __IO uint32_t ESAI0_FST;                         /**< ESAI0_FST, offset: 0x23100 */
51356        uint8_t RESERVED_60[60];
51357   __IO uint32_t ESAI0_SCKR;                        /**< ESAI0_SCKR, offset: 0x23140 */
51358        uint8_t RESERVED_61[60];
51359   __IO uint32_t ESAI0_SCKT;                        /**< ESAI0_SCKT, offset: 0x23180 */
51360        uint8_t RESERVED_62[60];
51361   __IO uint32_t ESAI0_TX0;                         /**< ESAI0_TX0, offset: 0x231C0 */
51362        uint8_t RESERVED_63[60];
51363   __IO uint32_t ESAI0_TX1;                         /**< ESAI0_TX1, offset: 0x23200 */
51364        uint8_t RESERVED_64[60];
51365   __IO uint32_t ESAI0_TX2_RX3;                     /**< ESAI0_TX2_RX3, offset: 0x23240 */
51366        uint8_t RESERVED_65[60];
51367   __IO uint32_t ESAI0_TX3_RX2;                     /**< ESAI0_TX3_RX2, offset: 0x23280 */
51368        uint8_t RESERVED_66[60];
51369   __IO uint32_t ESAI0_TX4_RX1;                     /**< ESAI0_TX4_RX1, offset: 0x232C0 */
51370        uint8_t RESERVED_67[60];
51371   __IO uint32_t ESAI0_TX5_RX0;                     /**< ESAI0_TX5_RX0, offset: 0x23300 */
51372        uint8_t RESERVED_68[60];
51373   __IO uint32_t SPDIF0_RX;                         /**< SPDIF0_RX, offset: 0x23340 */
51374        uint8_t RESERVED_69[60];
51375   __IO uint32_t SPDIF0_TX;                         /**< SPDIF0_TX, offset: 0x23380 */
51376        uint8_t RESERVED_70[124];
51377   __I  uint32_t IOMUXD_GROUP_1_3;                  /**< na, offset: 0x23400 */
51378        uint8_t RESERVED_71[3068];
51379   __IO uint32_t SPDIF0_EXT_CLK;                    /**< SPDIF0_EXT_CLK, offset: 0x24000 */
51380        uint8_t RESERVED_72[60];
51381   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB, offset: 0x24040 */
51382        uint8_t RESERVED_73[60];
51383   __IO uint32_t SPI3_SCK;                          /**< SPI3_SCK, offset: 0x24080 */
51384        uint8_t RESERVED_74[60];
51385   __IO uint32_t SPI3_SDO;                          /**< SPI3_SDO, offset: 0x240C0 */
51386        uint8_t RESERVED_75[60];
51387   __IO uint32_t SPI3_SDI;                          /**< SPI3_SDI, offset: 0x24100 */
51388        uint8_t RESERVED_76[60];
51389   __IO uint32_t SPI3_CS0;                          /**< SPI3_CS0, offset: 0x24140 */
51390        uint8_t RESERVED_77[60];
51391   __IO uint32_t SPI3_CS1;                          /**< SPI3_CS1, offset: 0x24180 */
51392        uint8_t RESERVED_78[60];
51393   __IO uint32_t MCLK_IN1;                          /**< MCLK_IN1, offset: 0x241C0 */
51394        uint8_t RESERVED_79[60];
51395   __IO uint32_t MCLK_IN0;                          /**< MCLK_IN0, offset: 0x24200 */
51396        uint8_t RESERVED_80[60];
51397   __IO uint32_t MCLK_OUT0;                         /**< MCLK_OUT0, offset: 0x24240 */
51398        uint8_t RESERVED_81[60];
51399   __IO uint32_t UART1_TX;                          /**< UART1_TX, offset: 0x24280 */
51400        uint8_t RESERVED_82[60];
51401   __IO uint32_t UART1_RX;                          /**< UART1_RX, offset: 0x242C0 */
51402        uint8_t RESERVED_83[60];
51403   __IO uint32_t UART1_RTS_B;                       /**< UART1_RTS_B, offset: 0x24300 */
51404        uint8_t RESERVED_84[60];
51405   __IO uint32_t UART1_CTS_B;                       /**< UART1_CTS_B, offset: 0x24340 */
51406        uint8_t RESERVED_85[60];
51407   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK, offset: 0x24380 */
51408        uint8_t RESERVED_86[124];
51409   __I  uint32_t IOMUXD_GROUP_1_4;                  /**< na, offset: 0x24400 */
51410        uint8_t RESERVED_87[113660];
51411   __IO uint32_t SAI0_TXD;                          /**< SAI0_TXD, offset: 0x40000 */
51412        uint8_t RESERVED_88[60];
51413   __IO uint32_t SAI0_TXC;                          /**< SAI0_TXC, offset: 0x40040 */
51414        uint8_t RESERVED_89[60];
51415   __IO uint32_t SAI0_RXD;                          /**< SAI0_RXD, offset: 0x40080 */
51416        uint8_t RESERVED_90[60];
51417   __IO uint32_t SAI0_TXFS;                         /**< SAI0_TXFS, offset: 0x400C0 */
51418        uint8_t RESERVED_91[60];
51419   __IO uint32_t SAI1_RXD;                          /**< SAI1_RXD, offset: 0x40100 */
51420        uint8_t RESERVED_92[60];
51421   __IO uint32_t SAI1_RXC;                          /**< SAI1_RXC, offset: 0x40140 */
51422        uint8_t RESERVED_93[60];
51423   __IO uint32_t SAI1_RXFS;                         /**< SAI1_RXFS, offset: 0x40180 */
51424        uint8_t RESERVED_94[60];
51425   __IO uint32_t SPI2_CS0;                          /**< SPI2_CS0, offset: 0x401C0 */
51426        uint8_t RESERVED_95[60];
51427   __IO uint32_t SPI2_SDO;                          /**< SPI2_SDO, offset: 0x40200 */
51428        uint8_t RESERVED_96[60];
51429   __IO uint32_t SPI2_SDI;                          /**< SPI2_SDI, offset: 0x40240 */
51430        uint8_t RESERVED_97[60];
51431   __IO uint32_t SPI2_SCK;                          /**< SPI2_SCK, offset: 0x40280 */
51432        uint8_t RESERVED_98[60];
51433   __IO uint32_t SPI0_SCK;                          /**< SPI0_SCK, offset: 0x402C0 */
51434        uint8_t RESERVED_99[60];
51435   __IO uint32_t SPI0_SDI;                          /**< SPI0_SDI, offset: 0x40300 */
51436        uint8_t RESERVED_100[60];
51437   __IO uint32_t SPI0_SDO;                          /**< SPI0_SDO, offset: 0x40340 */
51438        uint8_t RESERVED_101[60];
51439   __IO uint32_t SPI0_CS1;                          /**< SPI0_CS1, offset: 0x40380 */
51440        uint8_t RESERVED_102[124];
51441   __I  uint32_t IOMUXD_GROUP_2_0;                  /**< na, offset: 0x40400 */
51442        uint8_t RESERVED_103[3068];
51443   __IO uint32_t SPI0_CS0;                          /**< SPI0_CS0, offset: 0x41000 */
51444        uint8_t RESERVED_104[60];
51445   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT, offset: 0x41040 */
51446        uint8_t RESERVED_105[60];
51447   __IO uint32_t ADC_IN1;                           /**< ADC_IN1, offset: 0x41080 */
51448        uint8_t RESERVED_106[60];
51449   __IO uint32_t ADC_IN0;                           /**< ADC_IN0, offset: 0x410C0 */
51450        uint8_t RESERVED_107[60];
51451   __IO uint32_t ADC_IN3;                           /**< ADC_IN3, offset: 0x41100 */
51452        uint8_t RESERVED_108[60];
51453   __IO uint32_t ADC_IN2;                           /**< ADC_IN2, offset: 0x41140 */
51454        uint8_t RESERVED_109[60];
51455   __IO uint32_t ADC_IN5;                           /**< ADC_IN5, offset: 0x41180 */
51456        uint8_t RESERVED_110[60];
51457   __IO uint32_t ADC_IN4;                           /**< ADC_IN4, offset: 0x411C0 */
51458        uint8_t RESERVED_111[60];
51459   __IO uint32_t FLEXCAN0_RX;                       /**< FLEXCAN0_RX, offset: 0x41200 */
51460        uint8_t RESERVED_112[60];
51461   __IO uint32_t FLEXCAN0_TX;                       /**< FLEXCAN0_TX, offset: 0x41240 */
51462        uint8_t RESERVED_113[60];
51463   __IO uint32_t FLEXCAN1_RX;                       /**< FLEXCAN1_RX, offset: 0x41280 */
51464        uint8_t RESERVED_114[60];
51465   __IO uint32_t FLEXCAN1_TX;                       /**< FLEXCAN1_TX, offset: 0x412C0 */
51466        uint8_t RESERVED_115[60];
51467   __IO uint32_t FLEXCAN2_RX;                       /**< FLEXCAN2_RX, offset: 0x41300 */
51468        uint8_t RESERVED_116[60];
51469   __IO uint32_t FLEXCAN2_TX;                       /**< FLEXCAN2_TX, offset: 0x41340 */
51470        uint8_t RESERVED_117[60];
51471   __IO uint32_t UART0_RX;                          /**< UART0_RX, offset: 0x41380 */
51472        uint8_t RESERVED_118[124];
51473   __I  uint32_t IOMUXD_GROUP_2_1;                  /**< na, offset: 0x41400 */
51474        uint8_t RESERVED_119[3068];
51475   __IO uint32_t UART0_TX;                          /**< UART0_TX, offset: 0x42000 */
51476        uint8_t RESERVED_120[60];
51477   __IO uint32_t UART2_TX;                          /**< UART2_TX, offset: 0x42040 */
51478        uint8_t RESERVED_121[60];
51479   __IO uint32_t UART2_RX;                          /**< UART2_RX, offset: 0x42080 */
51480        uint8_t RESERVED_122[60];
51481   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH, offset: 0x420C0 */
51482        uint8_t RESERVED_123[60];
51483   __IO uint32_t MIPI_DSI0_I2C0_SCL;                /**< MIPI_DSI0_I2C0_SCL, offset: 0x42100 */
51484        uint8_t RESERVED_124[60];
51485   __IO uint32_t MIPI_DSI0_I2C0_SDA;                /**< MIPI_DSI0_I2C0_SDA, offset: 0x42140 */
51486        uint8_t RESERVED_125[60];
51487   __IO uint32_t MIPI_DSI0_GPIO0_00;                /**< MIPI_DSI0_GPIO0_00, offset: 0x42180 */
51488        uint8_t RESERVED_126[60];
51489   __IO uint32_t MIPI_DSI0_GPIO0_01;                /**< MIPI_DSI0_GPIO0_01, offset: 0x421C0 */
51490        uint8_t RESERVED_127[60];
51491   __IO uint32_t MIPI_DSI1_I2C0_SCL;                /**< MIPI_DSI1_I2C0_SCL, offset: 0x42200 */
51492        uint8_t RESERVED_128[60];
51493   __IO uint32_t MIPI_DSI1_I2C0_SDA;                /**< MIPI_DSI1_I2C0_SDA, offset: 0x42240 */
51494        uint8_t RESERVED_129[60];
51495   __IO uint32_t MIPI_DSI1_GPIO0_00;                /**< MIPI_DSI1_GPIO0_00, offset: 0x42280 */
51496        uint8_t RESERVED_130[60];
51497   __IO uint32_t MIPI_DSI1_GPIO0_01;                /**< MIPI_DSI1_GPIO0_01, offset: 0x422C0 */
51498        uint8_t RESERVED_131[60];
51499   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO, offset: 0x42300 */
51500        uint8_t RESERVED_132[60];
51501   __IO uint32_t SCU_WDOG_OUT;                      /**< SCU_WDOG_OUT, offset: 0x42340 */
51502        uint8_t RESERVED_133[60];
51503   __IO uint32_t PMIC_I2C_SCL;                      /**< PMIC_I2C_SCL, offset: 0x42380 */
51504        uint8_t RESERVED_134[124];
51505   __I  uint32_t IOMUXD_GROUP_2_2;                  /**< na, offset: 0x42400 */
51506        uint8_t RESERVED_135[3068];
51507   __IO uint32_t PMIC_I2C_SDA;                      /**< PMIC_I2C_SDA, offset: 0x43000 */
51508        uint8_t RESERVED_136[60];
51509   __IO uint32_t PMIC_INT_B;                        /**< PMIC_INT_B, offset: 0x43040 */
51510        uint8_t RESERVED_137[60];
51511   __IO uint32_t SCU_GPIO0_00;                      /**< SCU_GPIO0_00, offset: 0x43080 */
51512        uint8_t RESERVED_138[60];
51513   __IO uint32_t SCU_GPIO0_01;                      /**< SCU_GPIO0_01, offset: 0x430C0 */
51514        uint8_t RESERVED_139[60];
51515   __IO uint32_t SCU_PMIC_STANDBY;                  /**< SCU_PMIC_STANDBY, offset: 0x43100 */
51516        uint8_t RESERVED_140[60];
51517   __IO uint32_t SCU_BOOT_MODE0;                    /**< SCU_BOOT_MODE0, offset: 0x43140 */
51518        uint8_t RESERVED_141[60];
51519   __IO uint32_t SCU_BOOT_MODE1;                    /**< SCU_BOOT_MODE1, offset: 0x43180 */
51520        uint8_t RESERVED_142[60];
51521   __IO uint32_t SCU_BOOT_MODE2;                    /**< SCU_BOOT_MODE2, offset: 0x431C0 */
51522        uint8_t RESERVED_143[60];
51523   __IO uint32_t SCU_BOOT_MODE3;                    /**< SCU_BOOT_MODE3, offset: 0x43200 */
51524        uint8_t RESERVED_144[60];
51525   __IO uint32_t CSI_DIG_D00;                       /**< CSI_DIG_D00, offset: 0x43240 */
51526        uint8_t RESERVED_145[60];
51527   __IO uint32_t CSI_DIG_D01;                       /**< CSI_DIG_D01, offset: 0x43280 */
51528        uint8_t RESERVED_146[60];
51529   __IO uint32_t CSI_DIG_D02;                       /**< CSI_DIG_D02, offset: 0x432C0 */
51530        uint8_t RESERVED_147[60];
51531   __IO uint32_t CSI_DIG_D03;                       /**< CSI_DIG_D03, offset: 0x43300 */
51532        uint8_t RESERVED_148[60];
51533   __IO uint32_t CSI_DIG_D04;                       /**< CSI_DIG_D04, offset: 0x43340 */
51534        uint8_t RESERVED_149[60];
51535   __IO uint32_t CSI_DIG_D05;                       /**< CSI_DIG_D05, offset: 0x43380 */
51536        uint8_t RESERVED_150[124];
51537   __I  uint32_t IOMUXD_GROUP_2_3;                  /**< na, offset: 0x43400 */
51538        uint8_t RESERVED_151[3068];
51539   __IO uint32_t CSI_DIG_D06;                       /**< CSI_DIG_D06, offset: 0x44000 */
51540        uint8_t RESERVED_152[60];
51541   __IO uint32_t CSI_DIG_D07;                       /**< CSI_DIG_D07, offset: 0x44040 */
51542        uint8_t RESERVED_153[60];
51543   __IO uint32_t CSI_DIG_HSYNC;                     /**< CSI_DIG_HSYNC, offset: 0x44080 */
51544        uint8_t RESERVED_154[60];
51545   __IO uint32_t CSI_DIG_VSYNC;                     /**< CSI_DIG_VSYNC, offset: 0x440C0 */
51546        uint8_t RESERVED_155[60];
51547   __IO uint32_t CSI_PCLK;                          /**< CSI_PCLK, offset: 0x44100 */
51548        uint8_t RESERVED_156[60];
51549   __IO uint32_t CSI_MCLK;                          /**< CSI_MCLK, offset: 0x44140 */
51550        uint8_t RESERVED_157[60];
51551   __IO uint32_t CSI_EN;                            /**< CSI_EN, offset: 0x44180 */
51552        uint8_t RESERVED_158[60];
51553   __IO uint32_t CSI_RESET;                         /**< CSI_RESET, offset: 0x441C0 */
51554        uint8_t RESERVED_159[60];
51555   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD, offset: 0x44200 */
51556        uint8_t RESERVED_160[60];
51557   __IO uint32_t MIPI_CSI0_MCLK_OUT;                /**< MIPI_CSI0_MCLK_OUT, offset: 0x44240 */
51558        uint8_t RESERVED_161[60];
51559   __IO uint32_t MIPI_CSI0_I2C0_SCL;                /**< MIPI_CSI0_I2C0_SCL, offset: 0x44280 */
51560        uint8_t RESERVED_162[60];
51561   __IO uint32_t MIPI_CSI0_I2C0_SDA;                /**< MIPI_CSI0_I2C0_SDA, offset: 0x442C0 */
51562        uint8_t RESERVED_163[60];
51563   __IO uint32_t MIPI_CSI0_GPIO0_01;                /**< MIPI_CSI0_GPIO0_01, offset: 0x44300 */
51564        uint8_t RESERVED_164[60];
51565   __IO uint32_t MIPI_CSI0_GPIO0_00;                /**< MIPI_CSI0_GPIO0_00, offset: 0x44340 */
51566        uint8_t RESERVED_165[188];
51567   __I  uint32_t IOMUXD_GROUP_2_4;                  /**< na, offset: 0x44400 */
51568        uint8_t RESERVED_166[113660];
51569   __IO uint32_t QSPI0A_DATA0;                      /**< QSPI0A_DATA0, offset: 0x60000 */
51570        uint8_t RESERVED_167[60];
51571   __IO uint32_t QSPI0A_DATA1;                      /**< QSPI0A_DATA1, offset: 0x60040 */
51572        uint8_t RESERVED_168[60];
51573   __IO uint32_t QSPI0A_DATA2;                      /**< QSPI0A_DATA2, offset: 0x60080 */
51574        uint8_t RESERVED_169[60];
51575   __IO uint32_t QSPI0A_DATA3;                      /**< QSPI0A_DATA3, offset: 0x600C0 */
51576        uint8_t RESERVED_170[60];
51577   __IO uint32_t QSPI0A_DQS;                        /**< QSPI0A_DQS, offset: 0x60100 */
51578        uint8_t RESERVED_171[60];
51579   __IO uint32_t QSPI0A_SS0_B;                      /**< QSPI0A_SS0_B, offset: 0x60140 */
51580        uint8_t RESERVED_172[60];
51581   __IO uint32_t QSPI0A_SS1_B;                      /**< QSPI0A_SS1_B, offset: 0x60180 */
51582        uint8_t RESERVED_173[60];
51583   __IO uint32_t QSPI0A_SCLK;                       /**< QSPI0A_SCLK, offset: 0x601C0 */
51584        uint8_t RESERVED_174[60];
51585   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A, offset: 0x60200 */
51586        uint8_t RESERVED_175[60];
51587   __IO uint32_t QSPI0B_SCLK;                       /**< QSPI0B_SCLK, offset: 0x60240 */
51588        uint8_t RESERVED_176[60];
51589   __IO uint32_t QSPI0B_DATA0;                      /**< QSPI0B_DATA0, offset: 0x60280 */
51590        uint8_t RESERVED_177[60];
51591   __IO uint32_t QSPI0B_DATA1;                      /**< QSPI0B_DATA1, offset: 0x602C0 */
51592        uint8_t RESERVED_178[60];
51593   __IO uint32_t QSPI0B_DATA2;                      /**< QSPI0B_DATA2, offset: 0x60300 */
51594        uint8_t RESERVED_179[60];
51595   __IO uint32_t QSPI0B_DATA3;                      /**< QSPI0B_DATA3, offset: 0x60340 */
51596        uint8_t RESERVED_180[60];
51597   __IO uint32_t QSPI0B_DQS;                        /**< QSPI0B_DQS, offset: 0x60380 */
51598        uint8_t RESERVED_181[124];
51599   __I  uint32_t IOMUXD_GROUP_3_0;                  /**< na, offset: 0x60400 */
51600        uint8_t RESERVED_182[3068];
51601   __IO uint32_t QSPI0B_SS0_B;                      /**< QSPI0B_SS0_B, offset: 0x61000 */
51602        uint8_t RESERVED_183[60];
51603   __IO uint32_t QSPI0B_SS1_B;                      /**< QSPI0B_SS1_B, offset: 0x61040 */
51604        uint8_t RESERVED_184[60];
51605   __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B, offset: 0x61080 */
51606        uint8_t RESERVED_185[892];
51607   __I  uint32_t IOMUXD_GROUP_3_1;                  /**< na, offset: 0x61400 */
51608 } IOMUXD_Type;
51609 
51610 /* ----------------------------------------------------------------------------
51611    -- IOMUXD Register Masks
51612    ---------------------------------------------------------------------------- */
51613 
51614 /*!
51615  * @addtogroup IOMUXD_Register_Masks IOMUXD Register Masks
51616  * @{
51617  */
51618 
51619 /*! @name PCIE_CTRL0_PERST_B - PCIE_CTRL0_PERST_B */
51620 /*! @{ */
51621 #define IOMUXD_PCIE_CTRL0_PERST_B_PDRV_MASK      (0x1U)
51622 #define IOMUXD_PCIE_CTRL0_PERST_B_PDRV_SHIFT     (0U)
51623 /*! PDRV - Drive
51624  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
51625  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
51626  */
51627 #define IOMUXD_PCIE_CTRL0_PERST_B_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PDRV_MASK)
51628 #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_MASK (0x1EU)
51629 #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_SHIFT (1U)
51630 /*! PCIE_CTRL0_PERST_B_reserved_1_4 - reserved
51631  */
51632 #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_MASK)
51633 #define IOMUXD_PCIE_CTRL0_PERST_B_PULL_MASK      (0x60U)
51634 #define IOMUXD_PCIE_CTRL0_PERST_B_PULL_SHIFT     (5U)
51635 /*! PULL - Pull Down Pull Up
51636  *  0b10..pull down
51637  *  0b01..pull up
51638  *  0b00..Prohibited
51639  *  0b11..pull disabled
51640  */
51641 #define IOMUXD_PCIE_CTRL0_PERST_B_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PULL_MASK)
51642 #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_MASK (0x7FF80U)
51643 #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_SHIFT (7U)
51644 /*! PCIE_CTRL0_PERST_B_reserved_7_18 - reserved
51645  */
51646 #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_MASK)
51647 #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_MASK (0x380000U)
51648 #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_SHIFT (19U)
51649 /*! WAKEUP_CTRL - wakeup control
51650  *  0b000..OFF
51651  *  0b001..RESAMPLE
51652  *  0b100..LOW
51653  *  0b111..HIGH
51654  *  0b110..RISE
51655  *  0b101..FALL
51656  */
51657 #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_MASK)
51658 #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_MASK (0x400000U)
51659 #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_SHIFT (22U)
51660 /*! WAKEUP_MASK - wakeup mask
51661  */
51662 #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_MASK)
51663 #define IOMUXD_PCIE_CTRL0_PERST_B_lp_config_MASK (0x1800000U)
51664 #define IOMUXD_PCIE_CTRL0_PERST_B_lp_config_SHIFT (23U)
51665 /*! lp_config - lower power configuration
51666  *  0b01..EARLY_ISO
51667  *  0b10..LATE_ISO
51668  *  0b11..LATCH
51669  *  0b00..PASS
51670  */
51671 #define IOMUXD_PCIE_CTRL0_PERST_B_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_lp_config_MASK)
51672 #define IOMUXD_PCIE_CTRL0_PERST_B_sw_config_MASK (0x6000000U)
51673 #define IOMUXD_PCIE_CTRL0_PERST_B_sw_config_SHIFT (25U)
51674 /*! sw_config - output and input configuration
51675  *  0b01..OPEN_DRAIN
51676  *  0b10..OPEN_DRAIN_INPUT
51677  *  0b11..INOUT
51678  *  0b00..DEFAULT
51679  */
51680 #define IOMUXD_PCIE_CTRL0_PERST_B_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_sw_config_MASK)
51681 #define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_MASK  (0x38000000U)
51682 #define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_SHIFT (27U)
51683 /*! mux_mode - mux_mode
51684  *  0b000..HSIO.PCIE0.PERST_B
51685  *  0b100..LSIO.GPIO4.IO00
51686  */
51687 #define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_MASK)
51688 #define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_MASK (0x40000000U)
51689 #define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_SHIFT (30U)
51690 /*! update_pad_ctl - update lock for pad control
51691  */
51692 #define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_MASK)
51693 #define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_MASK (0x80000000U)
51694 #define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_SHIFT (31U)
51695 /*! update_mux_mode - update lock for mux control
51696  */
51697 #define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_MASK)
51698 /*! @} */
51699 
51700 /*! @name PCIE_CTRL0_CLKREQ_B - PCIE_CTRL0_CLKREQ_B */
51701 /*! @{ */
51702 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_MASK     (0x1U)
51703 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_SHIFT    (0U)
51704 /*! PDRV - Drive
51705  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
51706  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
51707  */
51708 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_MASK)
51709 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_MASK (0x1EU)
51710 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_SHIFT (1U)
51711 /*! PCIE_CTRL0_CLKREQ_B_reserved_1_4 - reserved
51712  */
51713 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_MASK)
51714 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_MASK     (0x60U)
51715 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_SHIFT    (5U)
51716 /*! PULL - Pull Down Pull Up
51717  *  0b10..pull down
51718  *  0b01..pull up
51719  *  0b00..Prohibited
51720  *  0b11..pull disabled
51721  */
51722 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_MASK)
51723 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_MASK (0x7FF80U)
51724 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_SHIFT (7U)
51725 /*! PCIE_CTRL0_CLKREQ_B_reserved_7_18 - reserved
51726  */
51727 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_MASK)
51728 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_MASK (0x380000U)
51729 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_SHIFT (19U)
51730 /*! WAKEUP_CTRL - wakeup control
51731  *  0b000..OFF
51732  *  0b001..RESAMPLE
51733  *  0b100..LOW
51734  *  0b111..HIGH
51735  *  0b110..RISE
51736  *  0b101..FALL
51737  */
51738 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_MASK)
51739 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_MASK (0x400000U)
51740 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_SHIFT (22U)
51741 /*! WAKEUP_MASK - wakeup mask
51742  */
51743 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_MASK)
51744 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_MASK (0x1800000U)
51745 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_SHIFT (23U)
51746 /*! lp_config - lower power configuration
51747  *  0b01..EARLY_ISO
51748  *  0b10..LATE_ISO
51749  *  0b11..LATCH
51750  *  0b00..PASS
51751  */
51752 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_MASK)
51753 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_MASK (0x6000000U)
51754 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_SHIFT (25U)
51755 /*! sw_config - output and input configuration
51756  *  0b01..OPEN_DRAIN
51757  *  0b10..OPEN_DRAIN_INPUT
51758  *  0b11..INOUT
51759  *  0b00..DEFAULT
51760  */
51761 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_MASK)
51762 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_MASK (0x38000000U)
51763 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_SHIFT (27U)
51764 /*! mux_mode - mux_mode
51765  *  0b000..HSIO.PCIE0.CLKREQ_B
51766  *  0b100..LSIO.GPIO4.IO01
51767  */
51768 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_MASK)
51769 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_MASK (0x40000000U)
51770 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_SHIFT (30U)
51771 /*! update_pad_ctl - update lock for pad control
51772  */
51773 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_MASK)
51774 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_MASK (0x80000000U)
51775 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_SHIFT (31U)
51776 /*! update_mux_mode - update lock for mux control
51777  */
51778 #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_MASK)
51779 /*! @} */
51780 
51781 /*! @name PCIE_CTRL0_WAKE_B - PCIE_CTRL0_WAKE_B */
51782 /*! @{ */
51783 #define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_MASK       (0x1U)
51784 #define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_SHIFT      (0U)
51785 /*! PDRV - Drive
51786  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
51787  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
51788  */
51789 #define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_MASK)
51790 #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_MASK (0x1EU)
51791 #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_SHIFT (1U)
51792 /*! PCIE_CTRL0_WAKE_B_reserved_1_4 - reserved
51793  */
51794 #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_MASK)
51795 #define IOMUXD_PCIE_CTRL0_WAKE_B_PULL_MASK       (0x60U)
51796 #define IOMUXD_PCIE_CTRL0_WAKE_B_PULL_SHIFT      (5U)
51797 /*! PULL - Pull Down Pull Up
51798  *  0b10..pull down
51799  *  0b01..pull up
51800  *  0b00..Prohibited
51801  *  0b11..pull disabled
51802  */
51803 #define IOMUXD_PCIE_CTRL0_WAKE_B_PULL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PULL_MASK)
51804 #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_MASK (0x7FF80U)
51805 #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_SHIFT (7U)
51806 /*! PCIE_CTRL0_WAKE_B_reserved_7_18 - reserved
51807  */
51808 #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_MASK)
51809 #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_MASK (0x380000U)
51810 #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_SHIFT (19U)
51811 /*! WAKEUP_CTRL - wakeup control
51812  *  0b000..OFF
51813  *  0b001..RESAMPLE
51814  *  0b100..LOW
51815  *  0b111..HIGH
51816  *  0b110..RISE
51817  *  0b101..FALL
51818  */
51819 #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_MASK)
51820 #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_MASK (0x400000U)
51821 #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_SHIFT (22U)
51822 /*! WAKEUP_MASK - wakeup mask
51823  */
51824 #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_MASK)
51825 #define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_MASK  (0x1800000U)
51826 #define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_SHIFT (23U)
51827 /*! lp_config - lower power configuration
51828  *  0b01..EARLY_ISO
51829  *  0b10..LATE_ISO
51830  *  0b11..LATCH
51831  *  0b00..PASS
51832  */
51833 #define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_MASK)
51834 #define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_MASK  (0x6000000U)
51835 #define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_SHIFT (25U)
51836 /*! sw_config - output and input configuration
51837  *  0b01..OPEN_DRAIN
51838  *  0b10..OPEN_DRAIN_INPUT
51839  *  0b11..INOUT
51840  *  0b00..DEFAULT
51841  */
51842 #define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_MASK)
51843 #define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_MASK   (0x38000000U)
51844 #define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_SHIFT  (27U)
51845 /*! mux_mode - mux_mode
51846  *  0b000..HSIO.PCIE0.WAKE_B
51847  *  0b100..LSIO.GPIO4.IO02
51848  */
51849 #define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_MASK)
51850 #define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_MASK (0x40000000U)
51851 #define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_SHIFT (30U)
51852 /*! update_pad_ctl - update lock for pad control
51853  */
51854 #define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_MASK)
51855 #define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_MASK (0x80000000U)
51856 #define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_SHIFT (31U)
51857 /*! update_mux_mode - update lock for mux control
51858  */
51859 #define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_MASK)
51860 /*! @} */
51861 
51862 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP - IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP */
51863 /*! @{ */
51864 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_MASK (0x7U)
51865 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_SHIFT (0U)
51866 /*! COMP - COMP
51867  *  0b010..Fixed code mode
51868  *  0b100..High impedance mode
51869  *  0b110..Read mode
51870  *  0b000..Normal Mode
51871  *  0b001..Freeze Mode
51872  */
51873 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_MASK)
51874 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_MASK (0x8U)
51875 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_SHIFT (3U)
51876 /*! FASTFRZ_EN - FASTFRZ_EN
51877  *  0b1..FASTFRZ signal is driven by output of subsystem
51878  *  0b0..FASTFRZ signal is gated to 0
51879  */
51880 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_MASK)
51881 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_MASK (0x10U)
51882 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_SHIFT (4U)
51883 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4 - reserved
51884  */
51885 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_MASK)
51886 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_MASK (0x1E0U)
51887 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_SHIFT (5U)
51888 /*! RASRCP - RASRCP
51889  *  0b0101..Reset Value
51890  */
51891 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_MASK)
51892 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_MASK (0x1E00U)
51893 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_SHIFT (9U)
51894 /*! RASRCN - RASRCN
51895  *  0b1010..Reset Value
51896  */
51897 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_MASK)
51898 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_MASK (0x2000U)
51899 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_SHIFT (13U)
51900 /*! SELECT_NASRC - SELECT_NASRC
51901  *  0b1..NASRCN value
51902  *  0b0..NASRCP value
51903  */
51904 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_MASK)
51905 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_MASK (0x4000U)
51906 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_SHIFT (14U)
51907 /*! COMPOK - COMPOK
51908  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
51909  *  0b1..compensation cell in Normal mode and tracking PVT
51910  */
51911 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_MASK)
51912 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_MASK (0x78000U)
51913 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_SHIFT (15U)
51914 /*! READ_NASRC - READ_NASRC
51915  *  0b0000..READ Only
51916  */
51917 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_MASK)
51918 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_MASK (0x780000U)
51919 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_SHIFT (19U)
51920 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22 - reserved
51921  */
51922 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_MASK)
51923 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_MASK (0x1800000U)
51924 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_SHIFT (23U)
51925 /*! SLEEP - SLEEP
51926  *  0b11..Force into sleep mode
51927  *  0b00..NO
51928  *  0b01..EARLY
51929  *  0b10..LATE
51930  */
51931 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_MASK)
51932 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_MASK (0x3E000000U)
51933 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_SHIFT (25U)
51934 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29 - reserved
51935  */
51936 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_MASK)
51937 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_MASK (0x40000000U)
51938 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_SHIFT (30U)
51939 /*! update_pad_ctl - update lock for pad control
51940  */
51941 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_MASK)
51942 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_MASK (0x80000000U)
51943 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_SHIFT (31U)
51944 /*! update_mux_mode - update lock for mux control
51945  */
51946 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_MASK)
51947 /*! @} */
51948 
51949 /*! @name USB_SS3_TC0 - USB_SS3_TC0 */
51950 /*! @{ */
51951 #define IOMUXD_USB_SS3_TC0_DSE_MASK              (0x3U)
51952 #define IOMUXD_USB_SS3_TC0_DSE_SHIFT             (0U)
51953 /*! DSE - Drive
51954  *  0b00..Drive select 2mA
51955  *  0b11..Drive select 12mA
51956  *  0b01..Drive select 4mA
51957  *  0b10..Drive select 8mA
51958  */
51959 #define IOMUXD_USB_SS3_TC0_DSE(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_DSE_SHIFT)) & IOMUXD_USB_SS3_TC0_DSE_MASK)
51960 #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_MASK (0x1CU)
51961 #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_SHIFT (2U)
51962 /*! USB_SS3_TC0_reserved_2_4 - reserved
51963  */
51964 #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_MASK)
51965 #define IOMUXD_USB_SS3_TC0_PULL_MASK             (0x60U)
51966 #define IOMUXD_USB_SS3_TC0_PULL_SHIFT            (5U)
51967 /*! PULL - Pull Down Pull Up
51968  *  0b00..Bus-Keeper
51969  *  0b10..pull down
51970  *  0b01..pull up
51971  *  0b11..No Pull
51972  */
51973 #define IOMUXD_USB_SS3_TC0_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_PULL_SHIFT)) & IOMUXD_USB_SS3_TC0_PULL_MASK)
51974 #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_MASK (0x7FF80U)
51975 #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_SHIFT (7U)
51976 /*! USB_SS3_TC0_reserved_7_18 - reserved
51977  */
51978 #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_MASK)
51979 #define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_MASK      (0x380000U)
51980 #define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_SHIFT     (19U)
51981 /*! WAKEUP_CTRL - wakeup control
51982  *  0b000..OFF
51983  *  0b001..RESAMPLE
51984  *  0b100..LOW
51985  *  0b111..HIGH
51986  *  0b110..RISE
51987  *  0b101..FALL
51988  */
51989 #define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_MASK)
51990 #define IOMUXD_USB_SS3_TC0_WAKEUP_MASK_MASK      (0x400000U)
51991 #define IOMUXD_USB_SS3_TC0_WAKEUP_MASK_SHIFT     (22U)
51992 /*! WAKEUP_MASK - wakeup mask
51993  */
51994 #define IOMUXD_USB_SS3_TC0_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC0_WAKEUP_MASK_MASK)
51995 #define IOMUXD_USB_SS3_TC0_lp_config_MASK        (0x1800000U)
51996 #define IOMUXD_USB_SS3_TC0_lp_config_SHIFT       (23U)
51997 /*! lp_config - lower power configuration
51998  *  0b01..EARLY_ISO
51999  *  0b10..LATE_ISO
52000  *  0b11..LATCH
52001  *  0b00..PASS
52002  */
52003 #define IOMUXD_USB_SS3_TC0_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC0_lp_config_MASK)
52004 #define IOMUXD_USB_SS3_TC0_sw_config_MASK        (0x6000000U)
52005 #define IOMUXD_USB_SS3_TC0_sw_config_SHIFT       (25U)
52006 /*! sw_config - output and input configuration
52007  *  0b01..OPEN_DRAIN
52008  *  0b10..OPEN_DRAIN_INPUT
52009  *  0b11..INOUT
52010  *  0b00..DEFAULT
52011  */
52012 #define IOMUXD_USB_SS3_TC0_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC0_sw_config_MASK)
52013 #define IOMUXD_USB_SS3_TC0_mux_mode_MASK         (0x38000000U)
52014 #define IOMUXD_USB_SS3_TC0_mux_mode_SHIFT        (27U)
52015 /*! mux_mode - mux_mode
52016  *  0b000..ADMA.I2C1.SCL
52017  *  0b001..CONN.USB_OTG1.PWR
52018  *  0b010..CONN.USB_OTG2.PWR
52019  *  0b100..LSIO.GPIO4.IO03
52020  */
52021 #define IOMUXD_USB_SS3_TC0_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC0_mux_mode_MASK)
52022 #define IOMUXD_USB_SS3_TC0_update_pad_ctl_MASK   (0x40000000U)
52023 #define IOMUXD_USB_SS3_TC0_update_pad_ctl_SHIFT  (30U)
52024 /*! update_pad_ctl - update lock for pad control
52025  */
52026 #define IOMUXD_USB_SS3_TC0_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC0_update_pad_ctl_MASK)
52027 #define IOMUXD_USB_SS3_TC0_update_mux_mode_MASK  (0x80000000U)
52028 #define IOMUXD_USB_SS3_TC0_update_mux_mode_SHIFT (31U)
52029 /*! update_mux_mode - update lock for mux control
52030  */
52031 #define IOMUXD_USB_SS3_TC0_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC0_update_mux_mode_MASK)
52032 /*! @} */
52033 
52034 /*! @name USB_SS3_TC1 - USB_SS3_TC1 */
52035 /*! @{ */
52036 #define IOMUXD_USB_SS3_TC1_DSE_MASK              (0x3U)
52037 #define IOMUXD_USB_SS3_TC1_DSE_SHIFT             (0U)
52038 /*! DSE - Drive
52039  *  0b00..Drive select 2mA
52040  *  0b11..Drive select 12mA
52041  *  0b01..Drive select 4mA
52042  *  0b10..Drive select 8mA
52043  */
52044 #define IOMUXD_USB_SS3_TC1_DSE(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_DSE_SHIFT)) & IOMUXD_USB_SS3_TC1_DSE_MASK)
52045 #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_MASK (0x1CU)
52046 #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_SHIFT (2U)
52047 /*! USB_SS3_TC1_reserved_2_4 - reserved
52048  */
52049 #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_MASK)
52050 #define IOMUXD_USB_SS3_TC1_PULL_MASK             (0x60U)
52051 #define IOMUXD_USB_SS3_TC1_PULL_SHIFT            (5U)
52052 /*! PULL - Pull Down Pull Up
52053  *  0b00..Bus-Keeper
52054  *  0b10..pull down
52055  *  0b01..pull up
52056  *  0b11..No Pull
52057  */
52058 #define IOMUXD_USB_SS3_TC1_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_PULL_SHIFT)) & IOMUXD_USB_SS3_TC1_PULL_MASK)
52059 #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_MASK (0x7FF80U)
52060 #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_SHIFT (7U)
52061 /*! USB_SS3_TC1_reserved_7_18 - reserved
52062  */
52063 #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_MASK)
52064 #define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_MASK      (0x380000U)
52065 #define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_SHIFT     (19U)
52066 /*! WAKEUP_CTRL - wakeup control
52067  *  0b000..OFF
52068  *  0b001..RESAMPLE
52069  *  0b100..LOW
52070  *  0b111..HIGH
52071  *  0b110..RISE
52072  *  0b101..FALL
52073  */
52074 #define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_MASK)
52075 #define IOMUXD_USB_SS3_TC1_WAKEUP_MASK_MASK      (0x400000U)
52076 #define IOMUXD_USB_SS3_TC1_WAKEUP_MASK_SHIFT     (22U)
52077 /*! WAKEUP_MASK - wakeup mask
52078  */
52079 #define IOMUXD_USB_SS3_TC1_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC1_WAKEUP_MASK_MASK)
52080 #define IOMUXD_USB_SS3_TC1_lp_config_MASK        (0x1800000U)
52081 #define IOMUXD_USB_SS3_TC1_lp_config_SHIFT       (23U)
52082 /*! lp_config - lower power configuration
52083  *  0b01..EARLY_ISO
52084  *  0b10..LATE_ISO
52085  *  0b11..LATCH
52086  *  0b00..PASS
52087  */
52088 #define IOMUXD_USB_SS3_TC1_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC1_lp_config_MASK)
52089 #define IOMUXD_USB_SS3_TC1_sw_config_MASK        (0x6000000U)
52090 #define IOMUXD_USB_SS3_TC1_sw_config_SHIFT       (25U)
52091 /*! sw_config - output and input configuration
52092  *  0b01..OPEN_DRAIN
52093  *  0b10..OPEN_DRAIN_INPUT
52094  *  0b11..INOUT
52095  *  0b00..DEFAULT
52096  */
52097 #define IOMUXD_USB_SS3_TC1_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC1_sw_config_MASK)
52098 #define IOMUXD_USB_SS3_TC1_mux_mode_MASK         (0x38000000U)
52099 #define IOMUXD_USB_SS3_TC1_mux_mode_SHIFT        (27U)
52100 /*! mux_mode - mux_mode
52101  *  0b000..ADMA.I2C1.SCL
52102  *  0b001..CONN.USB_OTG2.PWR
52103  *  0b100..LSIO.GPIO4.IO04
52104  */
52105 #define IOMUXD_USB_SS3_TC1_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC1_mux_mode_MASK)
52106 #define IOMUXD_USB_SS3_TC1_update_pad_ctl_MASK   (0x40000000U)
52107 #define IOMUXD_USB_SS3_TC1_update_pad_ctl_SHIFT  (30U)
52108 /*! update_pad_ctl - update lock for pad control
52109  */
52110 #define IOMUXD_USB_SS3_TC1_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC1_update_pad_ctl_MASK)
52111 #define IOMUXD_USB_SS3_TC1_update_mux_mode_MASK  (0x80000000U)
52112 #define IOMUXD_USB_SS3_TC1_update_mux_mode_SHIFT (31U)
52113 /*! update_mux_mode - update lock for mux control
52114  */
52115 #define IOMUXD_USB_SS3_TC1_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC1_update_mux_mode_MASK)
52116 /*! @} */
52117 
52118 /*! @name USB_SS3_TC2 - USB_SS3_TC2 */
52119 /*! @{ */
52120 #define IOMUXD_USB_SS3_TC2_DSE_MASK              (0x3U)
52121 #define IOMUXD_USB_SS3_TC2_DSE_SHIFT             (0U)
52122 /*! DSE - Drive
52123  *  0b00..Drive select 2mA
52124  *  0b11..Drive select 12mA
52125  *  0b01..Drive select 4mA
52126  *  0b10..Drive select 8mA
52127  */
52128 #define IOMUXD_USB_SS3_TC2_DSE(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_DSE_SHIFT)) & IOMUXD_USB_SS3_TC2_DSE_MASK)
52129 #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_MASK (0x1CU)
52130 #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_SHIFT (2U)
52131 /*! USB_SS3_TC2_reserved_2_4 - reserved
52132  */
52133 #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_MASK)
52134 #define IOMUXD_USB_SS3_TC2_PULL_MASK             (0x60U)
52135 #define IOMUXD_USB_SS3_TC2_PULL_SHIFT            (5U)
52136 /*! PULL - Pull Down Pull Up
52137  *  0b00..Bus-Keeper
52138  *  0b10..pull down
52139  *  0b01..pull up
52140  *  0b11..No Pull
52141  */
52142 #define IOMUXD_USB_SS3_TC2_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_PULL_SHIFT)) & IOMUXD_USB_SS3_TC2_PULL_MASK)
52143 #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_MASK (0x7FF80U)
52144 #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_SHIFT (7U)
52145 /*! USB_SS3_TC2_reserved_7_18 - reserved
52146  */
52147 #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_MASK)
52148 #define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_MASK      (0x380000U)
52149 #define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_SHIFT     (19U)
52150 /*! WAKEUP_CTRL - wakeup control
52151  *  0b000..OFF
52152  *  0b001..RESAMPLE
52153  *  0b100..LOW
52154  *  0b111..HIGH
52155  *  0b110..RISE
52156  *  0b101..FALL
52157  */
52158 #define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_MASK)
52159 #define IOMUXD_USB_SS3_TC2_WAKEUP_MASK_MASK      (0x400000U)
52160 #define IOMUXD_USB_SS3_TC2_WAKEUP_MASK_SHIFT     (22U)
52161 /*! WAKEUP_MASK - wakeup mask
52162  */
52163 #define IOMUXD_USB_SS3_TC2_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC2_WAKEUP_MASK_MASK)
52164 #define IOMUXD_USB_SS3_TC2_lp_config_MASK        (0x1800000U)
52165 #define IOMUXD_USB_SS3_TC2_lp_config_SHIFT       (23U)
52166 /*! lp_config - lower power configuration
52167  *  0b01..EARLY_ISO
52168  *  0b10..LATE_ISO
52169  *  0b11..LATCH
52170  *  0b00..PASS
52171  */
52172 #define IOMUXD_USB_SS3_TC2_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC2_lp_config_MASK)
52173 #define IOMUXD_USB_SS3_TC2_sw_config_MASK        (0x6000000U)
52174 #define IOMUXD_USB_SS3_TC2_sw_config_SHIFT       (25U)
52175 /*! sw_config - output and input configuration
52176  *  0b01..OPEN_DRAIN
52177  *  0b10..OPEN_DRAIN_INPUT
52178  *  0b11..INOUT
52179  *  0b00..DEFAULT
52180  */
52181 #define IOMUXD_USB_SS3_TC2_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC2_sw_config_MASK)
52182 #define IOMUXD_USB_SS3_TC2_mux_mode_MASK         (0x38000000U)
52183 #define IOMUXD_USB_SS3_TC2_mux_mode_SHIFT        (27U)
52184 /*! mux_mode - mux_mode
52185  *  0b000..ADMA.I2C1.SDA
52186  *  0b001..CONN.USB_OTG1.OC
52187  *  0b010..CONN.USB_OTG2.OC
52188  *  0b100..LSIO.GPIO4.IO05
52189  */
52190 #define IOMUXD_USB_SS3_TC2_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC2_mux_mode_MASK)
52191 #define IOMUXD_USB_SS3_TC2_update_pad_ctl_MASK   (0x40000000U)
52192 #define IOMUXD_USB_SS3_TC2_update_pad_ctl_SHIFT  (30U)
52193 /*! update_pad_ctl - update lock for pad control
52194  */
52195 #define IOMUXD_USB_SS3_TC2_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC2_update_pad_ctl_MASK)
52196 #define IOMUXD_USB_SS3_TC2_update_mux_mode_MASK  (0x80000000U)
52197 #define IOMUXD_USB_SS3_TC2_update_mux_mode_SHIFT (31U)
52198 /*! update_mux_mode - update lock for mux control
52199  */
52200 #define IOMUXD_USB_SS3_TC2_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC2_update_mux_mode_MASK)
52201 /*! @} */
52202 
52203 /*! @name USB_SS3_TC3 - USB_SS3_TC3 */
52204 /*! @{ */
52205 #define IOMUXD_USB_SS3_TC3_DSE_MASK              (0x3U)
52206 #define IOMUXD_USB_SS3_TC3_DSE_SHIFT             (0U)
52207 /*! DSE - Drive
52208  *  0b00..Drive select 2mA
52209  *  0b11..Drive select 12mA
52210  *  0b01..Drive select 4mA
52211  *  0b10..Drive select 8mA
52212  */
52213 #define IOMUXD_USB_SS3_TC3_DSE(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_DSE_SHIFT)) & IOMUXD_USB_SS3_TC3_DSE_MASK)
52214 #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_MASK (0x1CU)
52215 #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_SHIFT (2U)
52216 /*! USB_SS3_TC3_reserved_2_4 - reserved
52217  */
52218 #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_MASK)
52219 #define IOMUXD_USB_SS3_TC3_PULL_MASK             (0x60U)
52220 #define IOMUXD_USB_SS3_TC3_PULL_SHIFT            (5U)
52221 /*! PULL - Pull Down Pull Up
52222  *  0b00..Bus-Keeper
52223  *  0b10..pull down
52224  *  0b01..pull up
52225  *  0b11..No Pull
52226  */
52227 #define IOMUXD_USB_SS3_TC3_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_PULL_SHIFT)) & IOMUXD_USB_SS3_TC3_PULL_MASK)
52228 #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_MASK (0x7FF80U)
52229 #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_SHIFT (7U)
52230 /*! USB_SS3_TC3_reserved_7_18 - reserved
52231  */
52232 #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_MASK)
52233 #define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_MASK      (0x380000U)
52234 #define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_SHIFT     (19U)
52235 /*! WAKEUP_CTRL - wakeup control
52236  *  0b000..OFF
52237  *  0b001..RESAMPLE
52238  *  0b100..LOW
52239  *  0b111..HIGH
52240  *  0b110..RISE
52241  *  0b101..FALL
52242  */
52243 #define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_MASK)
52244 #define IOMUXD_USB_SS3_TC3_WAKEUP_MASK_MASK      (0x400000U)
52245 #define IOMUXD_USB_SS3_TC3_WAKEUP_MASK_SHIFT     (22U)
52246 /*! WAKEUP_MASK - wakeup mask
52247  */
52248 #define IOMUXD_USB_SS3_TC3_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC3_WAKEUP_MASK_MASK)
52249 #define IOMUXD_USB_SS3_TC3_lp_config_MASK        (0x1800000U)
52250 #define IOMUXD_USB_SS3_TC3_lp_config_SHIFT       (23U)
52251 /*! lp_config - lower power configuration
52252  *  0b01..EARLY_ISO
52253  *  0b10..LATE_ISO
52254  *  0b11..LATCH
52255  *  0b00..PASS
52256  */
52257 #define IOMUXD_USB_SS3_TC3_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC3_lp_config_MASK)
52258 #define IOMUXD_USB_SS3_TC3_sw_config_MASK        (0x6000000U)
52259 #define IOMUXD_USB_SS3_TC3_sw_config_SHIFT       (25U)
52260 /*! sw_config - output and input configuration
52261  *  0b01..OPEN_DRAIN
52262  *  0b10..OPEN_DRAIN_INPUT
52263  *  0b11..INOUT
52264  *  0b00..DEFAULT
52265  */
52266 #define IOMUXD_USB_SS3_TC3_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC3_sw_config_MASK)
52267 #define IOMUXD_USB_SS3_TC3_mux_mode_MASK         (0x38000000U)
52268 #define IOMUXD_USB_SS3_TC3_mux_mode_SHIFT        (27U)
52269 /*! mux_mode - mux_mode
52270  *  0b000..ADMA.I2C1.SDA
52271  *  0b001..CONN.USB_OTG2.OC
52272  *  0b100..LSIO.GPIO4.IO06
52273  */
52274 #define IOMUXD_USB_SS3_TC3_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC3_mux_mode_MASK)
52275 #define IOMUXD_USB_SS3_TC3_update_pad_ctl_MASK   (0x40000000U)
52276 #define IOMUXD_USB_SS3_TC3_update_pad_ctl_SHIFT  (30U)
52277 /*! update_pad_ctl - update lock for pad control
52278  */
52279 #define IOMUXD_USB_SS3_TC3_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC3_update_pad_ctl_MASK)
52280 #define IOMUXD_USB_SS3_TC3_update_mux_mode_MASK  (0x80000000U)
52281 #define IOMUXD_USB_SS3_TC3_update_mux_mode_SHIFT (31U)
52282 /*! update_mux_mode - update lock for mux control
52283  */
52284 #define IOMUXD_USB_SS3_TC3_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC3_update_mux_mode_MASK)
52285 /*! @} */
52286 
52287 /*! @name IOMUXD_COMP_CTL_GPIO_3V3_USB3IO - IOMUXD_COMP_CTL_GPIO_3V3_USB3IO */
52288 /*! @{ */
52289 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_MASK (0x7FFFFFU)
52290 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_SHIFT (0U)
52291 /*! IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22 - reserved
52292  */
52293 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_MASK)
52294 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_MASK (0x1800000U)
52295 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_SHIFT (23U)
52296 /*! SLEEP - SLEEP
52297  *  0b11..LAST
52298  *  0b00..NO
52299  *  0b01..EARLY
52300  *  0b10..LATE
52301  */
52302 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_MASK)
52303 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_MASK (0x3E000000U)
52304 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_SHIFT (25U)
52305 /*! IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29 - reserved
52306  */
52307 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_MASK)
52308 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_MASK (0x40000000U)
52309 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_SHIFT (30U)
52310 /*! update_pad_ctl - update lock for pad control
52311  */
52312 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_MASK)
52313 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_MASK (0x80000000U)
52314 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_SHIFT (31U)
52315 /*! update_mux_mode - update lock for mux control
52316  */
52317 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_MASK)
52318 /*! @} */
52319 
52320 /*! @name IOMUXD_GROUP_0_0 - na */
52321 /*! @{ */
52322 #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_MASK (0x1U)
52323 #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_SHIFT (0U)
52324 /*! PCIE_CTRL0_PERST_B - wakeup from PCIE_CTRL0_PERST_B
52325  */
52326 #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_MASK)
52327 #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_MASK (0x2U)
52328 #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_SHIFT (1U)
52329 /*! PCIE_CTRL0_CLKREQ_B - wakeup from PCIE_CTRL0_CLKREQ_B
52330  */
52331 #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_MASK)
52332 #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_MASK (0x4U)
52333 #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_SHIFT (2U)
52334 /*! PCIE_CTRL0_WAKE_B - wakeup from PCIE_CTRL0_WAKE_B
52335  */
52336 #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_MASK)
52337 #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_MASK (0x8U)
52338 #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_SHIFT (3U)
52339 /*! iomuxd_group_0_0_reserved_3_3 - reserved
52340  */
52341 #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_MASK)
52342 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_MASK (0x10U)
52343 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_SHIFT (4U)
52344 /*! USB_SS3_TC0 - wakeup from USB_SS3_TC0
52345  */
52346 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_MASK)
52347 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_MASK (0x20U)
52348 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_SHIFT (5U)
52349 /*! USB_SS3_TC1 - wakeup from USB_SS3_TC1
52350  */
52351 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_MASK)
52352 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_MASK (0x40U)
52353 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_SHIFT (6U)
52354 /*! USB_SS3_TC2 - wakeup from USB_SS3_TC2
52355  */
52356 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_MASK)
52357 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_MASK (0x80U)
52358 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_SHIFT (7U)
52359 /*! USB_SS3_TC3 - wakeup from USB_SS3_TC3
52360  */
52361 #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_MASK)
52362 #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_MASK (0xFFFFFF00U)
52363 #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_SHIFT (8U)
52364 /*! iomuxd_group_0_0_reserved_8_31 - reserved
52365  */
52366 #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_MASK)
52367 /*! @} */
52368 
52369 /*! @name EMMC0_CLK - EMMC0_CLK */
52370 /*! @{ */
52371 #define IOMUXD_EMMC0_CLK_PDRV_MASK               (0x1U)
52372 #define IOMUXD_EMMC0_CLK_PDRV_SHIFT              (0U)
52373 /*! PDRV - Drive
52374  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52375  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52376  */
52377 #define IOMUXD_EMMC0_CLK_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_PDRV_SHIFT)) & IOMUXD_EMMC0_CLK_PDRV_MASK)
52378 #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_MASK (0x1EU)
52379 #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_SHIFT (1U)
52380 /*! EMMC0_CLK_reserved_1_4 - reserved
52381  */
52382 #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_MASK)
52383 #define IOMUXD_EMMC0_CLK_PULL_MASK               (0x60U)
52384 #define IOMUXD_EMMC0_CLK_PULL_SHIFT              (5U)
52385 /*! PULL - Pull Down Pull Up
52386  *  0b10..pull down
52387  *  0b01..pull up
52388  *  0b00..Prohibited
52389  *  0b11..pull disabled
52390  */
52391 #define IOMUXD_EMMC0_CLK_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_PULL_SHIFT)) & IOMUXD_EMMC0_CLK_PULL_MASK)
52392 #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_MASK (0x7FF80U)
52393 #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_SHIFT (7U)
52394 /*! EMMC0_CLK_reserved_7_18 - reserved
52395  */
52396 #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_MASK)
52397 #define IOMUXD_EMMC0_CLK_WAKEUP_CTRL_MASK        (0x380000U)
52398 #define IOMUXD_EMMC0_CLK_WAKEUP_CTRL_SHIFT       (19U)
52399 /*! WAKEUP_CTRL - wakeup control
52400  *  0b000..OFF
52401  *  0b001..RESAMPLE
52402  *  0b100..LOW
52403  *  0b111..HIGH
52404  *  0b110..RISE
52405  *  0b101..FALL
52406  */
52407 #define IOMUXD_EMMC0_CLK_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_CLK_WAKEUP_CTRL_MASK)
52408 #define IOMUXD_EMMC0_CLK_WAKEUP_MASK_MASK        (0x400000U)
52409 #define IOMUXD_EMMC0_CLK_WAKEUP_MASK_SHIFT       (22U)
52410 /*! WAKEUP_MASK - wakeup mask
52411  */
52412 #define IOMUXD_EMMC0_CLK_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_CLK_WAKEUP_MASK_MASK)
52413 #define IOMUXD_EMMC0_CLK_lp_config_MASK          (0x1800000U)
52414 #define IOMUXD_EMMC0_CLK_lp_config_SHIFT         (23U)
52415 /*! lp_config - lower power configuration
52416  *  0b01..EARLY_ISO
52417  *  0b10..LATE_ISO
52418  *  0b11..LATCH
52419  *  0b00..PASS
52420  */
52421 #define IOMUXD_EMMC0_CLK_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_lp_config_SHIFT)) & IOMUXD_EMMC0_CLK_lp_config_MASK)
52422 #define IOMUXD_EMMC0_CLK_sw_config_MASK          (0x6000000U)
52423 #define IOMUXD_EMMC0_CLK_sw_config_SHIFT         (25U)
52424 /*! sw_config - output and input configuration
52425  *  0b01..OPEN_DRAIN
52426  *  0b10..OPEN_DRAIN_INPUT
52427  *  0b11..INOUT
52428  *  0b00..DEFAULT
52429  */
52430 #define IOMUXD_EMMC0_CLK_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_sw_config_SHIFT)) & IOMUXD_EMMC0_CLK_sw_config_MASK)
52431 #define IOMUXD_EMMC0_CLK_mux_mode_MASK           (0x38000000U)
52432 #define IOMUXD_EMMC0_CLK_mux_mode_SHIFT          (27U)
52433 /*! mux_mode - mux_mode
52434  *  0b000..CONN.EMMC0.CLK
52435  *  0b001..CONN.NAND.READY_B
52436  *  0b100..LSIO.GPIO4.IO07
52437  */
52438 #define IOMUXD_EMMC0_CLK_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_mux_mode_SHIFT)) & IOMUXD_EMMC0_CLK_mux_mode_MASK)
52439 #define IOMUXD_EMMC0_CLK_update_pad_ctl_MASK     (0x40000000U)
52440 #define IOMUXD_EMMC0_CLK_update_pad_ctl_SHIFT    (30U)
52441 /*! update_pad_ctl - update lock for pad control
52442  */
52443 #define IOMUXD_EMMC0_CLK_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_CLK_update_pad_ctl_MASK)
52444 #define IOMUXD_EMMC0_CLK_update_mux_mode_MASK    (0x80000000U)
52445 #define IOMUXD_EMMC0_CLK_update_mux_mode_SHIFT   (31U)
52446 /*! update_mux_mode - update lock for mux control
52447  */
52448 #define IOMUXD_EMMC0_CLK_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_CLK_update_mux_mode_MASK)
52449 /*! @} */
52450 
52451 /*! @name EMMC0_CMD - EMMC0_CMD */
52452 /*! @{ */
52453 #define IOMUXD_EMMC0_CMD_PDRV_MASK               (0x1U)
52454 #define IOMUXD_EMMC0_CMD_PDRV_SHIFT              (0U)
52455 /*! PDRV - Drive
52456  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52457  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52458  */
52459 #define IOMUXD_EMMC0_CMD_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_PDRV_SHIFT)) & IOMUXD_EMMC0_CMD_PDRV_MASK)
52460 #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_MASK (0x1EU)
52461 #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_SHIFT (1U)
52462 /*! EMMC0_CMD_reserved_1_4 - reserved
52463  */
52464 #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_MASK)
52465 #define IOMUXD_EMMC0_CMD_PULL_MASK               (0x60U)
52466 #define IOMUXD_EMMC0_CMD_PULL_SHIFT              (5U)
52467 /*! PULL - Pull Down Pull Up
52468  *  0b10..pull down
52469  *  0b01..pull up
52470  *  0b00..Prohibited
52471  *  0b11..pull disabled
52472  */
52473 #define IOMUXD_EMMC0_CMD_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_PULL_SHIFT)) & IOMUXD_EMMC0_CMD_PULL_MASK)
52474 #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_MASK (0x7FF80U)
52475 #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_SHIFT (7U)
52476 /*! EMMC0_CMD_reserved_7_18 - reserved
52477  */
52478 #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_MASK)
52479 #define IOMUXD_EMMC0_CMD_WAKEUP_CTRL_MASK        (0x380000U)
52480 #define IOMUXD_EMMC0_CMD_WAKEUP_CTRL_SHIFT       (19U)
52481 /*! WAKEUP_CTRL - wakeup control
52482  *  0b000..OFF
52483  *  0b001..RESAMPLE
52484  *  0b100..LOW
52485  *  0b111..HIGH
52486  *  0b110..RISE
52487  *  0b101..FALL
52488  */
52489 #define IOMUXD_EMMC0_CMD_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_CMD_WAKEUP_CTRL_MASK)
52490 #define IOMUXD_EMMC0_CMD_WAKEUP_MASK_MASK        (0x400000U)
52491 #define IOMUXD_EMMC0_CMD_WAKEUP_MASK_SHIFT       (22U)
52492 /*! WAKEUP_MASK - wakeup mask
52493  */
52494 #define IOMUXD_EMMC0_CMD_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_CMD_WAKEUP_MASK_MASK)
52495 #define IOMUXD_EMMC0_CMD_lp_config_MASK          (0x1800000U)
52496 #define IOMUXD_EMMC0_CMD_lp_config_SHIFT         (23U)
52497 /*! lp_config - lower power configuration
52498  *  0b01..EARLY_ISO
52499  *  0b10..LATE_ISO
52500  *  0b11..LATCH
52501  *  0b00..PASS
52502  */
52503 #define IOMUXD_EMMC0_CMD_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_lp_config_SHIFT)) & IOMUXD_EMMC0_CMD_lp_config_MASK)
52504 #define IOMUXD_EMMC0_CMD_sw_config_MASK          (0x6000000U)
52505 #define IOMUXD_EMMC0_CMD_sw_config_SHIFT         (25U)
52506 /*! sw_config - output and input configuration
52507  *  0b01..OPEN_DRAIN
52508  *  0b10..OPEN_DRAIN_INPUT
52509  *  0b11..INOUT
52510  *  0b00..DEFAULT
52511  */
52512 #define IOMUXD_EMMC0_CMD_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_sw_config_SHIFT)) & IOMUXD_EMMC0_CMD_sw_config_MASK)
52513 #define IOMUXD_EMMC0_CMD_mux_mode_MASK           (0x38000000U)
52514 #define IOMUXD_EMMC0_CMD_mux_mode_SHIFT          (27U)
52515 /*! mux_mode - mux_mode
52516  *  0b000..CONN.EMMC0.CMD
52517  *  0b001..CONN.NAND.DQS
52518  *  0b100..LSIO.GPIO4.IO08
52519  */
52520 #define IOMUXD_EMMC0_CMD_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_mux_mode_SHIFT)) & IOMUXD_EMMC0_CMD_mux_mode_MASK)
52521 #define IOMUXD_EMMC0_CMD_update_pad_ctl_MASK     (0x40000000U)
52522 #define IOMUXD_EMMC0_CMD_update_pad_ctl_SHIFT    (30U)
52523 /*! update_pad_ctl - update lock for pad control
52524  */
52525 #define IOMUXD_EMMC0_CMD_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_CMD_update_pad_ctl_MASK)
52526 #define IOMUXD_EMMC0_CMD_update_mux_mode_MASK    (0x80000000U)
52527 #define IOMUXD_EMMC0_CMD_update_mux_mode_SHIFT   (31U)
52528 /*! update_mux_mode - update lock for mux control
52529  */
52530 #define IOMUXD_EMMC0_CMD_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_CMD_update_mux_mode_MASK)
52531 /*! @} */
52532 
52533 /*! @name EMMC0_DATA0 - EMMC0_DATA0 */
52534 /*! @{ */
52535 #define IOMUXD_EMMC0_DATA0_PDRV_MASK             (0x1U)
52536 #define IOMUXD_EMMC0_DATA0_PDRV_SHIFT            (0U)
52537 /*! PDRV - Drive
52538  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52539  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52540  */
52541 #define IOMUXD_EMMC0_DATA0_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA0_PDRV_MASK)
52542 #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_MASK (0x1EU)
52543 #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_SHIFT (1U)
52544 /*! EMMC0_DATA0_reserved_1_4 - reserved
52545  */
52546 #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_MASK)
52547 #define IOMUXD_EMMC0_DATA0_PULL_MASK             (0x60U)
52548 #define IOMUXD_EMMC0_DATA0_PULL_SHIFT            (5U)
52549 /*! PULL - Pull Down Pull Up
52550  *  0b10..pull down
52551  *  0b01..pull up
52552  *  0b00..Prohibited
52553  *  0b11..pull disabled
52554  */
52555 #define IOMUXD_EMMC0_DATA0_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_PULL_SHIFT)) & IOMUXD_EMMC0_DATA0_PULL_MASK)
52556 #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_MASK (0x7FF80U)
52557 #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_SHIFT (7U)
52558 /*! EMMC0_DATA0_reserved_7_18 - reserved
52559  */
52560 #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_MASK)
52561 #define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_MASK      (0x380000U)
52562 #define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_SHIFT     (19U)
52563 /*! WAKEUP_CTRL - wakeup control
52564  *  0b000..OFF
52565  *  0b001..RESAMPLE
52566  *  0b100..LOW
52567  *  0b111..HIGH
52568  *  0b110..RISE
52569  *  0b101..FALL
52570  */
52571 #define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_MASK)
52572 #define IOMUXD_EMMC0_DATA0_WAKEUP_MASK_MASK      (0x400000U)
52573 #define IOMUXD_EMMC0_DATA0_WAKEUP_MASK_SHIFT     (22U)
52574 /*! WAKEUP_MASK - wakeup mask
52575  */
52576 #define IOMUXD_EMMC0_DATA0_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA0_WAKEUP_MASK_MASK)
52577 #define IOMUXD_EMMC0_DATA0_lp_config_MASK        (0x1800000U)
52578 #define IOMUXD_EMMC0_DATA0_lp_config_SHIFT       (23U)
52579 /*! lp_config - lower power configuration
52580  *  0b01..EARLY_ISO
52581  *  0b10..LATE_ISO
52582  *  0b11..LATCH
52583  *  0b00..PASS
52584  */
52585 #define IOMUXD_EMMC0_DATA0_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA0_lp_config_MASK)
52586 #define IOMUXD_EMMC0_DATA0_sw_config_MASK        (0x6000000U)
52587 #define IOMUXD_EMMC0_DATA0_sw_config_SHIFT       (25U)
52588 /*! sw_config - output and input configuration
52589  *  0b01..OPEN_DRAIN
52590  *  0b10..OPEN_DRAIN_INPUT
52591  *  0b11..INOUT
52592  *  0b00..DEFAULT
52593  */
52594 #define IOMUXD_EMMC0_DATA0_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA0_sw_config_MASK)
52595 #define IOMUXD_EMMC0_DATA0_mux_mode_MASK         (0x38000000U)
52596 #define IOMUXD_EMMC0_DATA0_mux_mode_SHIFT        (27U)
52597 /*! mux_mode - mux_mode
52598  *  0b000..CONN.EMMC0.DATA0
52599  *  0b001..CONN.NAND.DATA00
52600  *  0b100..LSIO.GPIO4.IO09
52601  */
52602 #define IOMUXD_EMMC0_DATA0_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA0_mux_mode_MASK)
52603 #define IOMUXD_EMMC0_DATA0_update_pad_ctl_MASK   (0x40000000U)
52604 #define IOMUXD_EMMC0_DATA0_update_pad_ctl_SHIFT  (30U)
52605 /*! update_pad_ctl - update lock for pad control
52606  */
52607 #define IOMUXD_EMMC0_DATA0_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA0_update_pad_ctl_MASK)
52608 #define IOMUXD_EMMC0_DATA0_update_mux_mode_MASK  (0x80000000U)
52609 #define IOMUXD_EMMC0_DATA0_update_mux_mode_SHIFT (31U)
52610 /*! update_mux_mode - update lock for mux control
52611  */
52612 #define IOMUXD_EMMC0_DATA0_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA0_update_mux_mode_MASK)
52613 /*! @} */
52614 
52615 /*! @name EMMC0_DATA1 - EMMC0_DATA1 */
52616 /*! @{ */
52617 #define IOMUXD_EMMC0_DATA1_PDRV_MASK             (0x1U)
52618 #define IOMUXD_EMMC0_DATA1_PDRV_SHIFT            (0U)
52619 /*! PDRV - Drive
52620  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52621  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52622  */
52623 #define IOMUXD_EMMC0_DATA1_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA1_PDRV_MASK)
52624 #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_MASK (0x1EU)
52625 #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_SHIFT (1U)
52626 /*! EMMC0_DATA1_reserved_1_4 - reserved
52627  */
52628 #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_MASK)
52629 #define IOMUXD_EMMC0_DATA1_PULL_MASK             (0x60U)
52630 #define IOMUXD_EMMC0_DATA1_PULL_SHIFT            (5U)
52631 /*! PULL - Pull Down Pull Up
52632  *  0b10..pull down
52633  *  0b01..pull up
52634  *  0b00..Prohibited
52635  *  0b11..pull disabled
52636  */
52637 #define IOMUXD_EMMC0_DATA1_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_PULL_SHIFT)) & IOMUXD_EMMC0_DATA1_PULL_MASK)
52638 #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_MASK (0x7FF80U)
52639 #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_SHIFT (7U)
52640 /*! EMMC0_DATA1_reserved_7_18 - reserved
52641  */
52642 #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_MASK)
52643 #define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_MASK      (0x380000U)
52644 #define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_SHIFT     (19U)
52645 /*! WAKEUP_CTRL - wakeup control
52646  *  0b000..OFF
52647  *  0b001..RESAMPLE
52648  *  0b100..LOW
52649  *  0b111..HIGH
52650  *  0b110..RISE
52651  *  0b101..FALL
52652  */
52653 #define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_MASK)
52654 #define IOMUXD_EMMC0_DATA1_WAKEUP_MASK_MASK      (0x400000U)
52655 #define IOMUXD_EMMC0_DATA1_WAKEUP_MASK_SHIFT     (22U)
52656 /*! WAKEUP_MASK - wakeup mask
52657  */
52658 #define IOMUXD_EMMC0_DATA1_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA1_WAKEUP_MASK_MASK)
52659 #define IOMUXD_EMMC0_DATA1_lp_config_MASK        (0x1800000U)
52660 #define IOMUXD_EMMC0_DATA1_lp_config_SHIFT       (23U)
52661 /*! lp_config - lower power configuration
52662  *  0b01..EARLY_ISO
52663  *  0b10..LATE_ISO
52664  *  0b11..LATCH
52665  *  0b00..PASS
52666  */
52667 #define IOMUXD_EMMC0_DATA1_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA1_lp_config_MASK)
52668 #define IOMUXD_EMMC0_DATA1_sw_config_MASK        (0x6000000U)
52669 #define IOMUXD_EMMC0_DATA1_sw_config_SHIFT       (25U)
52670 /*! sw_config - output and input configuration
52671  *  0b01..OPEN_DRAIN
52672  *  0b10..OPEN_DRAIN_INPUT
52673  *  0b11..INOUT
52674  *  0b00..DEFAULT
52675  */
52676 #define IOMUXD_EMMC0_DATA1_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA1_sw_config_MASK)
52677 #define IOMUXD_EMMC0_DATA1_mux_mode_MASK         (0x38000000U)
52678 #define IOMUXD_EMMC0_DATA1_mux_mode_SHIFT        (27U)
52679 /*! mux_mode - mux_mode
52680  *  0b000..CONN.EMMC0.DATA1
52681  *  0b001..CONN.NAND.DATA01
52682  *  0b100..LSIO.GPIO4.IO10
52683  */
52684 #define IOMUXD_EMMC0_DATA1_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA1_mux_mode_MASK)
52685 #define IOMUXD_EMMC0_DATA1_update_pad_ctl_MASK   (0x40000000U)
52686 #define IOMUXD_EMMC0_DATA1_update_pad_ctl_SHIFT  (30U)
52687 /*! update_pad_ctl - update lock for pad control
52688  */
52689 #define IOMUXD_EMMC0_DATA1_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA1_update_pad_ctl_MASK)
52690 #define IOMUXD_EMMC0_DATA1_update_mux_mode_MASK  (0x80000000U)
52691 #define IOMUXD_EMMC0_DATA1_update_mux_mode_SHIFT (31U)
52692 /*! update_mux_mode - update lock for mux control
52693  */
52694 #define IOMUXD_EMMC0_DATA1_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA1_update_mux_mode_MASK)
52695 /*! @} */
52696 
52697 /*! @name EMMC0_DATA2 - EMMC0_DATA2 */
52698 /*! @{ */
52699 #define IOMUXD_EMMC0_DATA2_PDRV_MASK             (0x1U)
52700 #define IOMUXD_EMMC0_DATA2_PDRV_SHIFT            (0U)
52701 /*! PDRV - Drive
52702  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52703  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52704  */
52705 #define IOMUXD_EMMC0_DATA2_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA2_PDRV_MASK)
52706 #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_MASK (0x1EU)
52707 #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_SHIFT (1U)
52708 /*! EMMC0_DATA2_reserved_1_4 - reserved
52709  */
52710 #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_MASK)
52711 #define IOMUXD_EMMC0_DATA2_PULL_MASK             (0x60U)
52712 #define IOMUXD_EMMC0_DATA2_PULL_SHIFT            (5U)
52713 /*! PULL - Pull Down Pull Up
52714  *  0b10..pull down
52715  *  0b01..pull up
52716  *  0b00..Prohibited
52717  *  0b11..pull disabled
52718  */
52719 #define IOMUXD_EMMC0_DATA2_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_PULL_SHIFT)) & IOMUXD_EMMC0_DATA2_PULL_MASK)
52720 #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_MASK (0x7FF80U)
52721 #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_SHIFT (7U)
52722 /*! EMMC0_DATA2_reserved_7_18 - reserved
52723  */
52724 #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_MASK)
52725 #define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_MASK      (0x380000U)
52726 #define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_SHIFT     (19U)
52727 /*! WAKEUP_CTRL - wakeup control
52728  *  0b000..OFF
52729  *  0b001..RESAMPLE
52730  *  0b100..LOW
52731  *  0b111..HIGH
52732  *  0b110..RISE
52733  *  0b101..FALL
52734  */
52735 #define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_MASK)
52736 #define IOMUXD_EMMC0_DATA2_WAKEUP_MASK_MASK      (0x400000U)
52737 #define IOMUXD_EMMC0_DATA2_WAKEUP_MASK_SHIFT     (22U)
52738 /*! WAKEUP_MASK - wakeup mask
52739  */
52740 #define IOMUXD_EMMC0_DATA2_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA2_WAKEUP_MASK_MASK)
52741 #define IOMUXD_EMMC0_DATA2_lp_config_MASK        (0x1800000U)
52742 #define IOMUXD_EMMC0_DATA2_lp_config_SHIFT       (23U)
52743 /*! lp_config - lower power configuration
52744  *  0b01..EARLY_ISO
52745  *  0b10..LATE_ISO
52746  *  0b11..LATCH
52747  *  0b00..PASS
52748  */
52749 #define IOMUXD_EMMC0_DATA2_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA2_lp_config_MASK)
52750 #define IOMUXD_EMMC0_DATA2_sw_config_MASK        (0x6000000U)
52751 #define IOMUXD_EMMC0_DATA2_sw_config_SHIFT       (25U)
52752 /*! sw_config - output and input configuration
52753  *  0b01..OPEN_DRAIN
52754  *  0b10..OPEN_DRAIN_INPUT
52755  *  0b11..INOUT
52756  *  0b00..DEFAULT
52757  */
52758 #define IOMUXD_EMMC0_DATA2_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA2_sw_config_MASK)
52759 #define IOMUXD_EMMC0_DATA2_mux_mode_MASK         (0x38000000U)
52760 #define IOMUXD_EMMC0_DATA2_mux_mode_SHIFT        (27U)
52761 /*! mux_mode - mux_mode
52762  *  0b000..CONN.EMMC0.DATA2
52763  *  0b001..CONN.NAND.DATA02
52764  *  0b100..LSIO.GPIO4.IO11
52765  */
52766 #define IOMUXD_EMMC0_DATA2_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA2_mux_mode_MASK)
52767 #define IOMUXD_EMMC0_DATA2_update_pad_ctl_MASK   (0x40000000U)
52768 #define IOMUXD_EMMC0_DATA2_update_pad_ctl_SHIFT  (30U)
52769 /*! update_pad_ctl - update lock for pad control
52770  */
52771 #define IOMUXD_EMMC0_DATA2_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA2_update_pad_ctl_MASK)
52772 #define IOMUXD_EMMC0_DATA2_update_mux_mode_MASK  (0x80000000U)
52773 #define IOMUXD_EMMC0_DATA2_update_mux_mode_SHIFT (31U)
52774 /*! update_mux_mode - update lock for mux control
52775  */
52776 #define IOMUXD_EMMC0_DATA2_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA2_update_mux_mode_MASK)
52777 /*! @} */
52778 
52779 /*! @name EMMC0_DATA3 - EMMC0_DATA3 */
52780 /*! @{ */
52781 #define IOMUXD_EMMC0_DATA3_PDRV_MASK             (0x1U)
52782 #define IOMUXD_EMMC0_DATA3_PDRV_SHIFT            (0U)
52783 /*! PDRV - Drive
52784  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52785  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52786  */
52787 #define IOMUXD_EMMC0_DATA3_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA3_PDRV_MASK)
52788 #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_MASK (0x1EU)
52789 #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_SHIFT (1U)
52790 /*! EMMC0_DATA3_reserved_1_4 - reserved
52791  */
52792 #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_MASK)
52793 #define IOMUXD_EMMC0_DATA3_PULL_MASK             (0x60U)
52794 #define IOMUXD_EMMC0_DATA3_PULL_SHIFT            (5U)
52795 /*! PULL - Pull Down Pull Up
52796  *  0b10..pull down
52797  *  0b01..pull up
52798  *  0b00..Prohibited
52799  *  0b11..pull disabled
52800  */
52801 #define IOMUXD_EMMC0_DATA3_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_PULL_SHIFT)) & IOMUXD_EMMC0_DATA3_PULL_MASK)
52802 #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_MASK (0x7FF80U)
52803 #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_SHIFT (7U)
52804 /*! EMMC0_DATA3_reserved_7_18 - reserved
52805  */
52806 #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_MASK)
52807 #define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_MASK      (0x380000U)
52808 #define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_SHIFT     (19U)
52809 /*! WAKEUP_CTRL - wakeup control
52810  *  0b000..OFF
52811  *  0b001..RESAMPLE
52812  *  0b100..LOW
52813  *  0b111..HIGH
52814  *  0b110..RISE
52815  *  0b101..FALL
52816  */
52817 #define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_MASK)
52818 #define IOMUXD_EMMC0_DATA3_WAKEUP_MASK_MASK      (0x400000U)
52819 #define IOMUXD_EMMC0_DATA3_WAKEUP_MASK_SHIFT     (22U)
52820 /*! WAKEUP_MASK - wakeup mask
52821  */
52822 #define IOMUXD_EMMC0_DATA3_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA3_WAKEUP_MASK_MASK)
52823 #define IOMUXD_EMMC0_DATA3_lp_config_MASK        (0x1800000U)
52824 #define IOMUXD_EMMC0_DATA3_lp_config_SHIFT       (23U)
52825 /*! lp_config - lower power configuration
52826  *  0b01..EARLY_ISO
52827  *  0b10..LATE_ISO
52828  *  0b11..LATCH
52829  *  0b00..PASS
52830  */
52831 #define IOMUXD_EMMC0_DATA3_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA3_lp_config_MASK)
52832 #define IOMUXD_EMMC0_DATA3_sw_config_MASK        (0x6000000U)
52833 #define IOMUXD_EMMC0_DATA3_sw_config_SHIFT       (25U)
52834 /*! sw_config - output and input configuration
52835  *  0b01..OPEN_DRAIN
52836  *  0b10..OPEN_DRAIN_INPUT
52837  *  0b11..INOUT
52838  *  0b00..DEFAULT
52839  */
52840 #define IOMUXD_EMMC0_DATA3_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA3_sw_config_MASK)
52841 #define IOMUXD_EMMC0_DATA3_mux_mode_MASK         (0x38000000U)
52842 #define IOMUXD_EMMC0_DATA3_mux_mode_SHIFT        (27U)
52843 /*! mux_mode - mux_mode
52844  *  0b000..CONN.EMMC0.DATA3
52845  *  0b001..CONN.NAND.DATA03
52846  *  0b100..LSIO.GPIO4.IO12
52847  */
52848 #define IOMUXD_EMMC0_DATA3_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA3_mux_mode_MASK)
52849 #define IOMUXD_EMMC0_DATA3_update_pad_ctl_MASK   (0x40000000U)
52850 #define IOMUXD_EMMC0_DATA3_update_pad_ctl_SHIFT  (30U)
52851 /*! update_pad_ctl - update lock for pad control
52852  */
52853 #define IOMUXD_EMMC0_DATA3_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA3_update_pad_ctl_MASK)
52854 #define IOMUXD_EMMC0_DATA3_update_mux_mode_MASK  (0x80000000U)
52855 #define IOMUXD_EMMC0_DATA3_update_mux_mode_SHIFT (31U)
52856 /*! update_mux_mode - update lock for mux control
52857  */
52858 #define IOMUXD_EMMC0_DATA3_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA3_update_mux_mode_MASK)
52859 /*! @} */
52860 
52861 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 */
52862 /*! @{ */
52863 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_MASK (0x7U)
52864 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_SHIFT (0U)
52865 /*! COMP - COMP
52866  *  0b010..Fixed code mode
52867  *  0b100..High impedance mode
52868  *  0b110..Read mode
52869  *  0b000..Normal Mode
52870  *  0b001..Freeze Mode
52871  */
52872 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_MASK)
52873 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_MASK (0x8U)
52874 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_SHIFT (3U)
52875 /*! FASTFRZ_EN - FASTFRZ_EN
52876  *  0b1..FASTFRZ signal is driven by output of subsystem
52877  *  0b0..FASTFRZ signal is gated to 0
52878  */
52879 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_MASK)
52880 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_MASK (0x10U)
52881 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_SHIFT (4U)
52882 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4 - reserved
52883  */
52884 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_MASK)
52885 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_MASK (0x1E0U)
52886 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_SHIFT (5U)
52887 /*! RASRCP - RASRCP
52888  *  0b0101..Reset Value
52889  */
52890 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_MASK)
52891 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_MASK (0x1E00U)
52892 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_SHIFT (9U)
52893 /*! RASRCN - RASRCN
52894  *  0b1010..Reset Value
52895  */
52896 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_MASK)
52897 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_MASK (0x2000U)
52898 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_SHIFT (13U)
52899 /*! SELECT_NASRC - SELECT_NASRC
52900  *  0b1..NASRCN value
52901  *  0b0..NASRCP value
52902  */
52903 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_MASK)
52904 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_MASK (0x4000U)
52905 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_SHIFT (14U)
52906 /*! COMPOK - COMPOK
52907  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
52908  *  0b1..compensation cell in Normal mode and tracking PVT
52909  */
52910 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_MASK)
52911 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_MASK (0x78000U)
52912 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_SHIFT (15U)
52913 /*! READ_NASRC - READ_NASRC
52914  *  0b0000..READ Only
52915  */
52916 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_MASK)
52917 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_MASK (0x780000U)
52918 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_SHIFT (19U)
52919 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22 - reserved
52920  */
52921 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_MASK)
52922 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_MASK (0x1800000U)
52923 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_SHIFT (23U)
52924 /*! SLEEP - SLEEP
52925  *  0b11..Force into sleep mode
52926  *  0b00..NO
52927  *  0b01..EARLY
52928  *  0b10..LATE
52929  */
52930 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_MASK)
52931 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_MASK (0x3E000000U)
52932 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_SHIFT (25U)
52933 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29 - reserved
52934  */
52935 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_MASK)
52936 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_MASK (0x40000000U)
52937 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_SHIFT (30U)
52938 /*! update_pad_ctl - update lock for pad control
52939  */
52940 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_MASK)
52941 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_MASK (0x80000000U)
52942 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_SHIFT (31U)
52943 /*! update_mux_mode - update lock for mux control
52944  */
52945 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_MASK)
52946 /*! @} */
52947 
52948 /*! @name EMMC0_DATA4 - EMMC0_DATA4 */
52949 /*! @{ */
52950 #define IOMUXD_EMMC0_DATA4_PDRV_MASK             (0x1U)
52951 #define IOMUXD_EMMC0_DATA4_PDRV_SHIFT            (0U)
52952 /*! PDRV - Drive
52953  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52954  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52955  */
52956 #define IOMUXD_EMMC0_DATA4_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA4_PDRV_MASK)
52957 #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_MASK (0x1EU)
52958 #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_SHIFT (1U)
52959 /*! EMMC0_DATA4_reserved_1_4 - reserved
52960  */
52961 #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_MASK)
52962 #define IOMUXD_EMMC0_DATA4_PULL_MASK             (0x60U)
52963 #define IOMUXD_EMMC0_DATA4_PULL_SHIFT            (5U)
52964 /*! PULL - Pull Down Pull Up
52965  *  0b10..pull down
52966  *  0b01..pull up
52967  *  0b00..Prohibited
52968  *  0b11..pull disabled
52969  */
52970 #define IOMUXD_EMMC0_DATA4_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_PULL_SHIFT)) & IOMUXD_EMMC0_DATA4_PULL_MASK)
52971 #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_MASK (0x7FF80U)
52972 #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_SHIFT (7U)
52973 /*! EMMC0_DATA4_reserved_7_18 - reserved
52974  */
52975 #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_MASK)
52976 #define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_MASK      (0x380000U)
52977 #define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_SHIFT     (19U)
52978 /*! WAKEUP_CTRL - wakeup control
52979  *  0b000..OFF
52980  *  0b001..RESAMPLE
52981  *  0b100..LOW
52982  *  0b111..HIGH
52983  *  0b110..RISE
52984  *  0b101..FALL
52985  */
52986 #define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_MASK)
52987 #define IOMUXD_EMMC0_DATA4_WAKEUP_MASK_MASK      (0x400000U)
52988 #define IOMUXD_EMMC0_DATA4_WAKEUP_MASK_SHIFT     (22U)
52989 /*! WAKEUP_MASK - wakeup mask
52990  */
52991 #define IOMUXD_EMMC0_DATA4_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA4_WAKEUP_MASK_MASK)
52992 #define IOMUXD_EMMC0_DATA4_lp_config_MASK        (0x1800000U)
52993 #define IOMUXD_EMMC0_DATA4_lp_config_SHIFT       (23U)
52994 /*! lp_config - lower power configuration
52995  *  0b01..EARLY_ISO
52996  *  0b10..LATE_ISO
52997  *  0b11..LATCH
52998  *  0b00..PASS
52999  */
53000 #define IOMUXD_EMMC0_DATA4_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA4_lp_config_MASK)
53001 #define IOMUXD_EMMC0_DATA4_sw_config_MASK        (0x6000000U)
53002 #define IOMUXD_EMMC0_DATA4_sw_config_SHIFT       (25U)
53003 /*! sw_config - output and input configuration
53004  *  0b01..OPEN_DRAIN
53005  *  0b10..OPEN_DRAIN_INPUT
53006  *  0b11..INOUT
53007  *  0b00..DEFAULT
53008  */
53009 #define IOMUXD_EMMC0_DATA4_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA4_sw_config_MASK)
53010 #define IOMUXD_EMMC0_DATA4_mux_mode_MASK         (0x38000000U)
53011 #define IOMUXD_EMMC0_DATA4_mux_mode_SHIFT        (27U)
53012 /*! mux_mode - mux_mode
53013  *  0b000..CONN.EMMC0.DATA4
53014  *  0b001..CONN.NAND.DATA04
53015  *  0b011..CONN.EMMC0.WP
53016  *  0b100..LSIO.GPIO4.IO13
53017  */
53018 #define IOMUXD_EMMC0_DATA4_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA4_mux_mode_MASK)
53019 #define IOMUXD_EMMC0_DATA4_update_pad_ctl_MASK   (0x40000000U)
53020 #define IOMUXD_EMMC0_DATA4_update_pad_ctl_SHIFT  (30U)
53021 /*! update_pad_ctl - update lock for pad control
53022  */
53023 #define IOMUXD_EMMC0_DATA4_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA4_update_pad_ctl_MASK)
53024 #define IOMUXD_EMMC0_DATA4_update_mux_mode_MASK  (0x80000000U)
53025 #define IOMUXD_EMMC0_DATA4_update_mux_mode_SHIFT (31U)
53026 /*! update_mux_mode - update lock for mux control
53027  */
53028 #define IOMUXD_EMMC0_DATA4_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA4_update_mux_mode_MASK)
53029 /*! @} */
53030 
53031 /*! @name EMMC0_DATA5 - EMMC0_DATA5 */
53032 /*! @{ */
53033 #define IOMUXD_EMMC0_DATA5_PDRV_MASK             (0x1U)
53034 #define IOMUXD_EMMC0_DATA5_PDRV_SHIFT            (0U)
53035 /*! PDRV - Drive
53036  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53037  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53038  */
53039 #define IOMUXD_EMMC0_DATA5_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA5_PDRV_MASK)
53040 #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_MASK (0x1EU)
53041 #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_SHIFT (1U)
53042 /*! EMMC0_DATA5_reserved_1_4 - reserved
53043  */
53044 #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_MASK)
53045 #define IOMUXD_EMMC0_DATA5_PULL_MASK             (0x60U)
53046 #define IOMUXD_EMMC0_DATA5_PULL_SHIFT            (5U)
53047 /*! PULL - Pull Down Pull Up
53048  *  0b10..pull down
53049  *  0b01..pull up
53050  *  0b00..Prohibited
53051  *  0b11..pull disabled
53052  */
53053 #define IOMUXD_EMMC0_DATA5_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_PULL_SHIFT)) & IOMUXD_EMMC0_DATA5_PULL_MASK)
53054 #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_MASK (0x7FF80U)
53055 #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_SHIFT (7U)
53056 /*! EMMC0_DATA5_reserved_7_18 - reserved
53057  */
53058 #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_MASK)
53059 #define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_MASK      (0x380000U)
53060 #define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_SHIFT     (19U)
53061 /*! WAKEUP_CTRL - wakeup control
53062  *  0b000..OFF
53063  *  0b001..RESAMPLE
53064  *  0b100..LOW
53065  *  0b111..HIGH
53066  *  0b110..RISE
53067  *  0b101..FALL
53068  */
53069 #define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_MASK)
53070 #define IOMUXD_EMMC0_DATA5_WAKEUP_MASK_MASK      (0x400000U)
53071 #define IOMUXD_EMMC0_DATA5_WAKEUP_MASK_SHIFT     (22U)
53072 /*! WAKEUP_MASK - wakeup mask
53073  */
53074 #define IOMUXD_EMMC0_DATA5_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA5_WAKEUP_MASK_MASK)
53075 #define IOMUXD_EMMC0_DATA5_lp_config_MASK        (0x1800000U)
53076 #define IOMUXD_EMMC0_DATA5_lp_config_SHIFT       (23U)
53077 /*! lp_config - lower power configuration
53078  *  0b01..EARLY_ISO
53079  *  0b10..LATE_ISO
53080  *  0b11..LATCH
53081  *  0b00..PASS
53082  */
53083 #define IOMUXD_EMMC0_DATA5_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA5_lp_config_MASK)
53084 #define IOMUXD_EMMC0_DATA5_sw_config_MASK        (0x6000000U)
53085 #define IOMUXD_EMMC0_DATA5_sw_config_SHIFT       (25U)
53086 /*! sw_config - output and input configuration
53087  *  0b01..OPEN_DRAIN
53088  *  0b10..OPEN_DRAIN_INPUT
53089  *  0b11..INOUT
53090  *  0b00..DEFAULT
53091  */
53092 #define IOMUXD_EMMC0_DATA5_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA5_sw_config_MASK)
53093 #define IOMUXD_EMMC0_DATA5_mux_mode_MASK         (0x38000000U)
53094 #define IOMUXD_EMMC0_DATA5_mux_mode_SHIFT        (27U)
53095 /*! mux_mode - mux_mode
53096  *  0b000..CONN.EMMC0.DATA5
53097  *  0b001..CONN.NAND.DATA05
53098  *  0b011..CONN.EMMC0.VSELECT
53099  *  0b100..LSIO.GPIO4.IO14
53100  */
53101 #define IOMUXD_EMMC0_DATA5_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA5_mux_mode_MASK)
53102 #define IOMUXD_EMMC0_DATA5_update_pad_ctl_MASK   (0x40000000U)
53103 #define IOMUXD_EMMC0_DATA5_update_pad_ctl_SHIFT  (30U)
53104 /*! update_pad_ctl - update lock for pad control
53105  */
53106 #define IOMUXD_EMMC0_DATA5_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA5_update_pad_ctl_MASK)
53107 #define IOMUXD_EMMC0_DATA5_update_mux_mode_MASK  (0x80000000U)
53108 #define IOMUXD_EMMC0_DATA5_update_mux_mode_SHIFT (31U)
53109 /*! update_mux_mode - update lock for mux control
53110  */
53111 #define IOMUXD_EMMC0_DATA5_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA5_update_mux_mode_MASK)
53112 /*! @} */
53113 
53114 /*! @name EMMC0_DATA6 - EMMC0_DATA6 */
53115 /*! @{ */
53116 #define IOMUXD_EMMC0_DATA6_PDRV_MASK             (0x1U)
53117 #define IOMUXD_EMMC0_DATA6_PDRV_SHIFT            (0U)
53118 /*! PDRV - Drive
53119  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53120  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53121  */
53122 #define IOMUXD_EMMC0_DATA6_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA6_PDRV_MASK)
53123 #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_MASK (0x1EU)
53124 #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_SHIFT (1U)
53125 /*! EMMC0_DATA6_reserved_1_4 - reserved
53126  */
53127 #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_MASK)
53128 #define IOMUXD_EMMC0_DATA6_PULL_MASK             (0x60U)
53129 #define IOMUXD_EMMC0_DATA6_PULL_SHIFT            (5U)
53130 /*! PULL - Pull Down Pull Up
53131  *  0b10..pull down
53132  *  0b01..pull up
53133  *  0b00..Prohibited
53134  *  0b11..pull disabled
53135  */
53136 #define IOMUXD_EMMC0_DATA6_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_PULL_SHIFT)) & IOMUXD_EMMC0_DATA6_PULL_MASK)
53137 #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_MASK (0x7FF80U)
53138 #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_SHIFT (7U)
53139 /*! EMMC0_DATA6_reserved_7_18 - reserved
53140  */
53141 #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_MASK)
53142 #define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_MASK      (0x380000U)
53143 #define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_SHIFT     (19U)
53144 /*! WAKEUP_CTRL - wakeup control
53145  *  0b000..OFF
53146  *  0b001..RESAMPLE
53147  *  0b100..LOW
53148  *  0b111..HIGH
53149  *  0b110..RISE
53150  *  0b101..FALL
53151  */
53152 #define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_MASK)
53153 #define IOMUXD_EMMC0_DATA6_WAKEUP_MASK_MASK      (0x400000U)
53154 #define IOMUXD_EMMC0_DATA6_WAKEUP_MASK_SHIFT     (22U)
53155 /*! WAKEUP_MASK - wakeup mask
53156  */
53157 #define IOMUXD_EMMC0_DATA6_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA6_WAKEUP_MASK_MASK)
53158 #define IOMUXD_EMMC0_DATA6_lp_config_MASK        (0x1800000U)
53159 #define IOMUXD_EMMC0_DATA6_lp_config_SHIFT       (23U)
53160 /*! lp_config - lower power configuration
53161  *  0b01..EARLY_ISO
53162  *  0b10..LATE_ISO
53163  *  0b11..LATCH
53164  *  0b00..PASS
53165  */
53166 #define IOMUXD_EMMC0_DATA6_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA6_lp_config_MASK)
53167 #define IOMUXD_EMMC0_DATA6_sw_config_MASK        (0x6000000U)
53168 #define IOMUXD_EMMC0_DATA6_sw_config_SHIFT       (25U)
53169 /*! sw_config - output and input configuration
53170  *  0b01..OPEN_DRAIN
53171  *  0b10..OPEN_DRAIN_INPUT
53172  *  0b11..INOUT
53173  *  0b00..DEFAULT
53174  */
53175 #define IOMUXD_EMMC0_DATA6_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA6_sw_config_MASK)
53176 #define IOMUXD_EMMC0_DATA6_mux_mode_MASK         (0x38000000U)
53177 #define IOMUXD_EMMC0_DATA6_mux_mode_SHIFT        (27U)
53178 /*! mux_mode - mux_mode
53179  *  0b000..CONN.EMMC0.DATA6
53180  *  0b001..CONN.NAND.DATA06
53181  *  0b011..CONN.MLB.CLK
53182  *  0b100..LSIO.GPIO4.IO15
53183  */
53184 #define IOMUXD_EMMC0_DATA6_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA6_mux_mode_MASK)
53185 #define IOMUXD_EMMC0_DATA6_update_pad_ctl_MASK   (0x40000000U)
53186 #define IOMUXD_EMMC0_DATA6_update_pad_ctl_SHIFT  (30U)
53187 /*! update_pad_ctl - update lock for pad control
53188  */
53189 #define IOMUXD_EMMC0_DATA6_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA6_update_pad_ctl_MASK)
53190 #define IOMUXD_EMMC0_DATA6_update_mux_mode_MASK  (0x80000000U)
53191 #define IOMUXD_EMMC0_DATA6_update_mux_mode_SHIFT (31U)
53192 /*! update_mux_mode - update lock for mux control
53193  */
53194 #define IOMUXD_EMMC0_DATA6_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA6_update_mux_mode_MASK)
53195 /*! @} */
53196 
53197 /*! @name EMMC0_DATA7 - EMMC0_DATA7 */
53198 /*! @{ */
53199 #define IOMUXD_EMMC0_DATA7_PDRV_MASK             (0x1U)
53200 #define IOMUXD_EMMC0_DATA7_PDRV_SHIFT            (0U)
53201 /*! PDRV - Drive
53202  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53203  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53204  */
53205 #define IOMUXD_EMMC0_DATA7_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA7_PDRV_MASK)
53206 #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_MASK (0x1EU)
53207 #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_SHIFT (1U)
53208 /*! EMMC0_DATA7_reserved_1_4 - reserved
53209  */
53210 #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_MASK)
53211 #define IOMUXD_EMMC0_DATA7_PULL_MASK             (0x60U)
53212 #define IOMUXD_EMMC0_DATA7_PULL_SHIFT            (5U)
53213 /*! PULL - Pull Down Pull Up
53214  *  0b10..pull down
53215  *  0b01..pull up
53216  *  0b00..Prohibited
53217  *  0b11..pull disabled
53218  */
53219 #define IOMUXD_EMMC0_DATA7_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_PULL_SHIFT)) & IOMUXD_EMMC0_DATA7_PULL_MASK)
53220 #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_MASK (0x7FF80U)
53221 #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_SHIFT (7U)
53222 /*! EMMC0_DATA7_reserved_7_18 - reserved
53223  */
53224 #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_MASK)
53225 #define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_MASK      (0x380000U)
53226 #define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_SHIFT     (19U)
53227 /*! WAKEUP_CTRL - wakeup control
53228  *  0b000..OFF
53229  *  0b001..RESAMPLE
53230  *  0b100..LOW
53231  *  0b111..HIGH
53232  *  0b110..RISE
53233  *  0b101..FALL
53234  */
53235 #define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_MASK)
53236 #define IOMUXD_EMMC0_DATA7_WAKEUP_MASK_MASK      (0x400000U)
53237 #define IOMUXD_EMMC0_DATA7_WAKEUP_MASK_SHIFT     (22U)
53238 /*! WAKEUP_MASK - wakeup mask
53239  */
53240 #define IOMUXD_EMMC0_DATA7_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA7_WAKEUP_MASK_MASK)
53241 #define IOMUXD_EMMC0_DATA7_lp_config_MASK        (0x1800000U)
53242 #define IOMUXD_EMMC0_DATA7_lp_config_SHIFT       (23U)
53243 /*! lp_config - lower power configuration
53244  *  0b01..EARLY_ISO
53245  *  0b10..LATE_ISO
53246  *  0b11..LATCH
53247  *  0b00..PASS
53248  */
53249 #define IOMUXD_EMMC0_DATA7_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA7_lp_config_MASK)
53250 #define IOMUXD_EMMC0_DATA7_sw_config_MASK        (0x6000000U)
53251 #define IOMUXD_EMMC0_DATA7_sw_config_SHIFT       (25U)
53252 /*! sw_config - output and input configuration
53253  *  0b01..OPEN_DRAIN
53254  *  0b10..OPEN_DRAIN_INPUT
53255  *  0b11..INOUT
53256  *  0b00..DEFAULT
53257  */
53258 #define IOMUXD_EMMC0_DATA7_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA7_sw_config_MASK)
53259 #define IOMUXD_EMMC0_DATA7_mux_mode_MASK         (0x38000000U)
53260 #define IOMUXD_EMMC0_DATA7_mux_mode_SHIFT        (27U)
53261 /*! mux_mode - mux_mode
53262  *  0b000..CONN.EMMC0.DATA7
53263  *  0b001..CONN.NAND.DATA07
53264  *  0b011..CONN.MLB.SIG
53265  *  0b100..LSIO.GPIO4.IO16
53266  */
53267 #define IOMUXD_EMMC0_DATA7_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA7_mux_mode_MASK)
53268 #define IOMUXD_EMMC0_DATA7_update_pad_ctl_MASK   (0x40000000U)
53269 #define IOMUXD_EMMC0_DATA7_update_pad_ctl_SHIFT  (30U)
53270 /*! update_pad_ctl - update lock for pad control
53271  */
53272 #define IOMUXD_EMMC0_DATA7_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA7_update_pad_ctl_MASK)
53273 #define IOMUXD_EMMC0_DATA7_update_mux_mode_MASK  (0x80000000U)
53274 #define IOMUXD_EMMC0_DATA7_update_mux_mode_SHIFT (31U)
53275 /*! update_mux_mode - update lock for mux control
53276  */
53277 #define IOMUXD_EMMC0_DATA7_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA7_update_mux_mode_MASK)
53278 /*! @} */
53279 
53280 /*! @name EMMC0_STROBE - EMMC0_STROBE */
53281 /*! @{ */
53282 #define IOMUXD_EMMC0_STROBE_PDRV_MASK            (0x1U)
53283 #define IOMUXD_EMMC0_STROBE_PDRV_SHIFT           (0U)
53284 /*! PDRV - Drive
53285  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53286  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53287  */
53288 #define IOMUXD_EMMC0_STROBE_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_PDRV_SHIFT)) & IOMUXD_EMMC0_STROBE_PDRV_MASK)
53289 #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_MASK (0x1EU)
53290 #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_SHIFT (1U)
53291 /*! EMMC0_STROBE_reserved_1_4 - reserved
53292  */
53293 #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_MASK)
53294 #define IOMUXD_EMMC0_STROBE_PULL_MASK            (0x60U)
53295 #define IOMUXD_EMMC0_STROBE_PULL_SHIFT           (5U)
53296 /*! PULL - Pull Down Pull Up
53297  *  0b10..pull down
53298  *  0b01..pull up
53299  *  0b00..Prohibited
53300  *  0b11..pull disabled
53301  */
53302 #define IOMUXD_EMMC0_STROBE_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_PULL_SHIFT)) & IOMUXD_EMMC0_STROBE_PULL_MASK)
53303 #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_MASK (0x7FF80U)
53304 #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_SHIFT (7U)
53305 /*! EMMC0_STROBE_reserved_7_18 - reserved
53306  */
53307 #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_MASK)
53308 #define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_MASK     (0x380000U)
53309 #define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_SHIFT    (19U)
53310 /*! WAKEUP_CTRL - wakeup control
53311  *  0b000..OFF
53312  *  0b001..RESAMPLE
53313  *  0b100..LOW
53314  *  0b111..HIGH
53315  *  0b110..RISE
53316  *  0b101..FALL
53317  */
53318 #define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_MASK)
53319 #define IOMUXD_EMMC0_STROBE_WAKEUP_MASK_MASK     (0x400000U)
53320 #define IOMUXD_EMMC0_STROBE_WAKEUP_MASK_SHIFT    (22U)
53321 /*! WAKEUP_MASK - wakeup mask
53322  */
53323 #define IOMUXD_EMMC0_STROBE_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_STROBE_WAKEUP_MASK_MASK)
53324 #define IOMUXD_EMMC0_STROBE_lp_config_MASK       (0x1800000U)
53325 #define IOMUXD_EMMC0_STROBE_lp_config_SHIFT      (23U)
53326 /*! lp_config - lower power configuration
53327  *  0b01..EARLY_ISO
53328  *  0b10..LATE_ISO
53329  *  0b11..LATCH
53330  *  0b00..PASS
53331  */
53332 #define IOMUXD_EMMC0_STROBE_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_lp_config_SHIFT)) & IOMUXD_EMMC0_STROBE_lp_config_MASK)
53333 #define IOMUXD_EMMC0_STROBE_sw_config_MASK       (0x6000000U)
53334 #define IOMUXD_EMMC0_STROBE_sw_config_SHIFT      (25U)
53335 /*! sw_config - output and input configuration
53336  *  0b01..OPEN_DRAIN
53337  *  0b10..OPEN_DRAIN_INPUT
53338  *  0b11..INOUT
53339  *  0b00..DEFAULT
53340  */
53341 #define IOMUXD_EMMC0_STROBE_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_sw_config_SHIFT)) & IOMUXD_EMMC0_STROBE_sw_config_MASK)
53342 #define IOMUXD_EMMC0_STROBE_mux_mode_MASK        (0x38000000U)
53343 #define IOMUXD_EMMC0_STROBE_mux_mode_SHIFT       (27U)
53344 /*! mux_mode - mux_mode
53345  *  0b000..CONN.EMMC0.STROBE
53346  *  0b001..CONN.NAND.CLE
53347  *  0b011..CONN.MLB.DATA
53348  *  0b100..LSIO.GPIO4.IO17
53349  */
53350 #define IOMUXD_EMMC0_STROBE_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_mux_mode_SHIFT)) & IOMUXD_EMMC0_STROBE_mux_mode_MASK)
53351 #define IOMUXD_EMMC0_STROBE_update_pad_ctl_MASK  (0x40000000U)
53352 #define IOMUXD_EMMC0_STROBE_update_pad_ctl_SHIFT (30U)
53353 /*! update_pad_ctl - update lock for pad control
53354  */
53355 #define IOMUXD_EMMC0_STROBE_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_STROBE_update_pad_ctl_MASK)
53356 #define IOMUXD_EMMC0_STROBE_update_mux_mode_MASK (0x80000000U)
53357 #define IOMUXD_EMMC0_STROBE_update_mux_mode_SHIFT (31U)
53358 /*! update_mux_mode - update lock for mux control
53359  */
53360 #define IOMUXD_EMMC0_STROBE_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_STROBE_update_mux_mode_MASK)
53361 /*! @} */
53362 
53363 /*! @name EMMC0_RESET_B - EMMC0_RESET_B */
53364 /*! @{ */
53365 #define IOMUXD_EMMC0_RESET_B_PDRV_MASK           (0x1U)
53366 #define IOMUXD_EMMC0_RESET_B_PDRV_SHIFT          (0U)
53367 /*! PDRV - Drive
53368  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53369  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53370  */
53371 #define IOMUXD_EMMC0_RESET_B_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_PDRV_SHIFT)) & IOMUXD_EMMC0_RESET_B_PDRV_MASK)
53372 #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_MASK (0x1EU)
53373 #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_SHIFT (1U)
53374 /*! EMMC0_RESET_B_reserved_1_4 - reserved
53375  */
53376 #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_MASK)
53377 #define IOMUXD_EMMC0_RESET_B_PULL_MASK           (0x60U)
53378 #define IOMUXD_EMMC0_RESET_B_PULL_SHIFT          (5U)
53379 /*! PULL - Pull Down Pull Up
53380  *  0b10..pull down
53381  *  0b01..pull up
53382  *  0b00..Prohibited
53383  *  0b11..pull disabled
53384  */
53385 #define IOMUXD_EMMC0_RESET_B_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_PULL_SHIFT)) & IOMUXD_EMMC0_RESET_B_PULL_MASK)
53386 #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_MASK (0x7FF80U)
53387 #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_SHIFT (7U)
53388 /*! EMMC0_RESET_B_reserved_7_18 - reserved
53389  */
53390 #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_MASK)
53391 #define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_MASK    (0x380000U)
53392 #define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_SHIFT   (19U)
53393 /*! WAKEUP_CTRL - wakeup control
53394  *  0b000..OFF
53395  *  0b001..RESAMPLE
53396  *  0b100..LOW
53397  *  0b111..HIGH
53398  *  0b110..RISE
53399  *  0b101..FALL
53400  */
53401 #define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_MASK)
53402 #define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_MASK    (0x400000U)
53403 #define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_SHIFT   (22U)
53404 /*! WAKEUP_MASK - wakeup mask
53405  */
53406 #define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_MASK)
53407 #define IOMUXD_EMMC0_RESET_B_lp_config_MASK      (0x1800000U)
53408 #define IOMUXD_EMMC0_RESET_B_lp_config_SHIFT     (23U)
53409 /*! lp_config - lower power configuration
53410  *  0b01..EARLY_ISO
53411  *  0b10..LATE_ISO
53412  *  0b11..LATCH
53413  *  0b00..PASS
53414  */
53415 #define IOMUXD_EMMC0_RESET_B_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_lp_config_SHIFT)) & IOMUXD_EMMC0_RESET_B_lp_config_MASK)
53416 #define IOMUXD_EMMC0_RESET_B_sw_config_MASK      (0x6000000U)
53417 #define IOMUXD_EMMC0_RESET_B_sw_config_SHIFT     (25U)
53418 /*! sw_config - output and input configuration
53419  *  0b01..OPEN_DRAIN
53420  *  0b10..OPEN_DRAIN_INPUT
53421  *  0b11..INOUT
53422  *  0b00..DEFAULT
53423  */
53424 #define IOMUXD_EMMC0_RESET_B_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_sw_config_SHIFT)) & IOMUXD_EMMC0_RESET_B_sw_config_MASK)
53425 #define IOMUXD_EMMC0_RESET_B_mux_mode_MASK       (0x38000000U)
53426 #define IOMUXD_EMMC0_RESET_B_mux_mode_SHIFT      (27U)
53427 /*! mux_mode - mux_mode
53428  *  0b000..CONN.EMMC0.RESET_B
53429  *  0b001..CONN.NAND.WP_B
53430  *  0b100..LSIO.GPIO4.IO18
53431  */
53432 #define IOMUXD_EMMC0_RESET_B_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_mux_mode_SHIFT)) & IOMUXD_EMMC0_RESET_B_mux_mode_MASK)
53433 #define IOMUXD_EMMC0_RESET_B_update_pad_ctl_MASK (0x40000000U)
53434 #define IOMUXD_EMMC0_RESET_B_update_pad_ctl_SHIFT (30U)
53435 /*! update_pad_ctl - update lock for pad control
53436  */
53437 #define IOMUXD_EMMC0_RESET_B_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_RESET_B_update_pad_ctl_MASK)
53438 #define IOMUXD_EMMC0_RESET_B_update_mux_mode_MASK (0x80000000U)
53439 #define IOMUXD_EMMC0_RESET_B_update_mux_mode_SHIFT (31U)
53440 /*! update_mux_mode - update lock for mux control
53441  */
53442 #define IOMUXD_EMMC0_RESET_B_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_RESET_B_update_mux_mode_MASK)
53443 /*! @} */
53444 
53445 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 */
53446 /*! @{ */
53447 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_MASK (0x7U)
53448 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_SHIFT (0U)
53449 /*! COMP - COMP
53450  *  0b010..Fixed code mode
53451  *  0b100..High impedance mode
53452  *  0b110..Read mode
53453  *  0b000..Normal Mode
53454  *  0b001..Freeze Mode
53455  */
53456 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_MASK)
53457 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_MASK (0x8U)
53458 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_SHIFT (3U)
53459 /*! FASTFRZ_EN - FASTFRZ_EN
53460  *  0b1..FASTFRZ signal is driven by output of subsystem
53461  *  0b0..FASTFRZ signal is gated to 0
53462  */
53463 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_MASK)
53464 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_MASK (0x10U)
53465 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_SHIFT (4U)
53466 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4 - reserved
53467  */
53468 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_MASK)
53469 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_MASK (0x1E0U)
53470 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_SHIFT (5U)
53471 /*! RASRCP - RASRCP
53472  *  0b0101..Reset Value
53473  */
53474 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_MASK)
53475 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_MASK (0x1E00U)
53476 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_SHIFT (9U)
53477 /*! RASRCN - RASRCN
53478  *  0b1010..Reset Value
53479  */
53480 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_MASK)
53481 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_MASK (0x2000U)
53482 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_SHIFT (13U)
53483 /*! SELECT_NASRC - SELECT_NASRC
53484  *  0b1..NASRCN value
53485  *  0b0..NASRCP value
53486  */
53487 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_MASK)
53488 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_MASK (0x4000U)
53489 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_SHIFT (14U)
53490 /*! COMPOK - COMPOK
53491  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
53492  *  0b1..compensation cell in Normal mode and tracking PVT
53493  */
53494 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_MASK)
53495 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_MASK (0x78000U)
53496 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_SHIFT (15U)
53497 /*! READ_NASRC - READ_NASRC
53498  *  0b0000..READ Only
53499  */
53500 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_MASK)
53501 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_MASK (0x780000U)
53502 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_SHIFT (19U)
53503 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22 - reserved
53504  */
53505 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_MASK)
53506 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_MASK (0x1800000U)
53507 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_SHIFT (23U)
53508 /*! SLEEP - SLEEP
53509  *  0b11..Force into sleep mode
53510  *  0b00..NO
53511  *  0b01..EARLY
53512  *  0b10..LATE
53513  */
53514 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_MASK)
53515 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_MASK (0x3E000000U)
53516 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_SHIFT (25U)
53517 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29 - reserved
53518  */
53519 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_MASK)
53520 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_MASK (0x40000000U)
53521 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_SHIFT (30U)
53522 /*! update_pad_ctl - update lock for pad control
53523  */
53524 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_MASK)
53525 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_MASK (0x80000000U)
53526 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_SHIFT (31U)
53527 /*! update_mux_mode - update lock for mux control
53528  */
53529 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_MASK)
53530 /*! @} */
53531 
53532 /*! @name USDHC1_RESET_B - USDHC1_RESET_B */
53533 /*! @{ */
53534 #define IOMUXD_USDHC1_RESET_B_PDRV_MASK          (0x1U)
53535 #define IOMUXD_USDHC1_RESET_B_PDRV_SHIFT         (0U)
53536 /*! PDRV - Drive
53537  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53538  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53539  */
53540 #define IOMUXD_USDHC1_RESET_B_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_PDRV_SHIFT)) & IOMUXD_USDHC1_RESET_B_PDRV_MASK)
53541 #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_MASK (0x1EU)
53542 #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_SHIFT (1U)
53543 /*! USDHC1_RESET_B_reserved_1_4 - reserved
53544  */
53545 #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_MASK)
53546 #define IOMUXD_USDHC1_RESET_B_PULL_MASK          (0x60U)
53547 #define IOMUXD_USDHC1_RESET_B_PULL_SHIFT         (5U)
53548 /*! PULL - Pull Down Pull Up
53549  *  0b10..pull down
53550  *  0b01..pull up
53551  *  0b00..Prohibited
53552  *  0b11..pull disabled
53553  */
53554 #define IOMUXD_USDHC1_RESET_B_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_PULL_SHIFT)) & IOMUXD_USDHC1_RESET_B_PULL_MASK)
53555 #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_MASK (0x7FF80U)
53556 #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_SHIFT (7U)
53557 /*! USDHC1_RESET_B_reserved_7_18 - reserved
53558  */
53559 #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_MASK)
53560 #define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_MASK   (0x380000U)
53561 #define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_SHIFT  (19U)
53562 /*! WAKEUP_CTRL - wakeup control
53563  *  0b000..OFF
53564  *  0b001..RESAMPLE
53565  *  0b100..LOW
53566  *  0b111..HIGH
53567  *  0b110..RISE
53568  *  0b101..FALL
53569  */
53570 #define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_MASK)
53571 #define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_MASK   (0x400000U)
53572 #define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_SHIFT  (22U)
53573 /*! WAKEUP_MASK - wakeup mask
53574  */
53575 #define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_MASK)
53576 #define IOMUXD_USDHC1_RESET_B_lp_config_MASK     (0x1800000U)
53577 #define IOMUXD_USDHC1_RESET_B_lp_config_SHIFT    (23U)
53578 /*! lp_config - lower power configuration
53579  *  0b01..EARLY_ISO
53580  *  0b10..LATE_ISO
53581  *  0b11..LATCH
53582  *  0b00..PASS
53583  */
53584 #define IOMUXD_USDHC1_RESET_B_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_lp_config_SHIFT)) & IOMUXD_USDHC1_RESET_B_lp_config_MASK)
53585 #define IOMUXD_USDHC1_RESET_B_sw_config_MASK     (0x6000000U)
53586 #define IOMUXD_USDHC1_RESET_B_sw_config_SHIFT    (25U)
53587 /*! sw_config - output and input configuration
53588  *  0b01..OPEN_DRAIN
53589  *  0b10..OPEN_DRAIN_INPUT
53590  *  0b11..INOUT
53591  *  0b00..DEFAULT
53592  */
53593 #define IOMUXD_USDHC1_RESET_B_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_sw_config_SHIFT)) & IOMUXD_USDHC1_RESET_B_sw_config_MASK)
53594 #define IOMUXD_USDHC1_RESET_B_mux_mode_MASK      (0x38000000U)
53595 #define IOMUXD_USDHC1_RESET_B_mux_mode_SHIFT     (27U)
53596 /*! mux_mode - mux_mode
53597  *  0b000..CONN.USDHC1.RESET_B
53598  *  0b001..CONN.NAND.RE_N
53599  *  0b010..ADMA.SPI2.SCK
53600  *  0b100..LSIO.GPIO4.IO19
53601  */
53602 #define IOMUXD_USDHC1_RESET_B_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_mux_mode_SHIFT)) & IOMUXD_USDHC1_RESET_B_mux_mode_MASK)
53603 #define IOMUXD_USDHC1_RESET_B_update_pad_ctl_MASK (0x40000000U)
53604 #define IOMUXD_USDHC1_RESET_B_update_pad_ctl_SHIFT (30U)
53605 /*! update_pad_ctl - update lock for pad control
53606  */
53607 #define IOMUXD_USDHC1_RESET_B_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_RESET_B_update_pad_ctl_MASK)
53608 #define IOMUXD_USDHC1_RESET_B_update_mux_mode_MASK (0x80000000U)
53609 #define IOMUXD_USDHC1_RESET_B_update_mux_mode_SHIFT (31U)
53610 /*! update_mux_mode - update lock for mux control
53611  */
53612 #define IOMUXD_USDHC1_RESET_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_RESET_B_update_mux_mode_MASK)
53613 /*! @} */
53614 
53615 /*! @name IOMUXD_GROUP_1_0 - na */
53616 /*! @{ */
53617 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_MASK   (0x1U)
53618 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_SHIFT  (0U)
53619 /*! EMMC0_CLK - wakeup from EMMC0_CLK
53620  */
53621 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_MASK)
53622 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_MASK   (0x2U)
53623 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_SHIFT  (1U)
53624 /*! EMMC0_CMD - wakeup from EMMC0_CMD
53625  */
53626 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_MASK)
53627 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_MASK (0x4U)
53628 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_SHIFT (2U)
53629 /*! EMMC0_DATA0 - wakeup from EMMC0_DATA0
53630  */
53631 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_MASK)
53632 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_MASK (0x8U)
53633 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_SHIFT (3U)
53634 /*! EMMC0_DATA1 - wakeup from EMMC0_DATA1
53635  */
53636 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_MASK)
53637 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_MASK (0x10U)
53638 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_SHIFT (4U)
53639 /*! EMMC0_DATA2 - wakeup from EMMC0_DATA2
53640  */
53641 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_MASK)
53642 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_MASK (0x20U)
53643 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_SHIFT (5U)
53644 /*! EMMC0_DATA3 - wakeup from EMMC0_DATA3
53645  */
53646 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_MASK)
53647 #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_MASK (0x40U)
53648 #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_SHIFT (6U)
53649 /*! iomuxd_group_1_0_reserved_6_6 - reserved
53650  */
53651 #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_MASK)
53652 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_MASK (0x80U)
53653 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_SHIFT (7U)
53654 /*! EMMC0_DATA4 - wakeup from EMMC0_DATA4
53655  */
53656 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_MASK)
53657 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_MASK (0x100U)
53658 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_SHIFT (8U)
53659 /*! EMMC0_DATA5 - wakeup from EMMC0_DATA5
53660  */
53661 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_MASK)
53662 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_MASK (0x200U)
53663 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_SHIFT (9U)
53664 /*! EMMC0_DATA6 - wakeup from EMMC0_DATA6
53665  */
53666 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_MASK)
53667 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_MASK (0x400U)
53668 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_SHIFT (10U)
53669 /*! EMMC0_DATA7 - wakeup from EMMC0_DATA7
53670  */
53671 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_MASK)
53672 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_MASK (0x800U)
53673 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_SHIFT (11U)
53674 /*! EMMC0_STROBE - wakeup from EMMC0_STROBE
53675  */
53676 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_MASK)
53677 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_MASK (0x1000U)
53678 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_SHIFT (12U)
53679 /*! EMMC0_RESET_B - wakeup from EMMC0_RESET_B
53680  */
53681 #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_MASK)
53682 #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_MASK (0x2000U)
53683 #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_SHIFT (13U)
53684 /*! iomuxd_group_1_0_reserved_13_13 - reserved
53685  */
53686 #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_MASK)
53687 #define IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_MASK (0x4000U)
53688 #define IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_SHIFT (14U)
53689 /*! USDHC1_RESET_B - wakeup from USDHC1_RESET_B
53690  */
53691 #define IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_MASK)
53692 #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_MASK (0xFFFF8000U)
53693 #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_SHIFT (15U)
53694 /*! iomuxd_group_1_0_reserved_15_31 - reserved
53695  */
53696 #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_MASK)
53697 /*! @} */
53698 
53699 /*! @name USDHC1_VSELECT - USDHC1_VSELECT */
53700 /*! @{ */
53701 #define IOMUXD_USDHC1_VSELECT_PDRV_MASK          (0x1U)
53702 #define IOMUXD_USDHC1_VSELECT_PDRV_SHIFT         (0U)
53703 /*! PDRV - Drive
53704  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53705  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53706  */
53707 #define IOMUXD_USDHC1_VSELECT_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_PDRV_SHIFT)) & IOMUXD_USDHC1_VSELECT_PDRV_MASK)
53708 #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_MASK (0x1EU)
53709 #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_SHIFT (1U)
53710 /*! USDHC1_VSELECT_reserved_1_4 - reserved
53711  */
53712 #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_MASK)
53713 #define IOMUXD_USDHC1_VSELECT_PULL_MASK          (0x60U)
53714 #define IOMUXD_USDHC1_VSELECT_PULL_SHIFT         (5U)
53715 /*! PULL - Pull Down Pull Up
53716  *  0b10..pull down
53717  *  0b01..pull up
53718  *  0b00..Prohibited
53719  *  0b11..pull disabled
53720  */
53721 #define IOMUXD_USDHC1_VSELECT_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_PULL_SHIFT)) & IOMUXD_USDHC1_VSELECT_PULL_MASK)
53722 #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_MASK (0x7FF80U)
53723 #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_SHIFT (7U)
53724 /*! USDHC1_VSELECT_reserved_7_18 - reserved
53725  */
53726 #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_MASK)
53727 #define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_MASK   (0x380000U)
53728 #define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_SHIFT  (19U)
53729 /*! WAKEUP_CTRL - wakeup control
53730  *  0b000..OFF
53731  *  0b001..RESAMPLE
53732  *  0b100..LOW
53733  *  0b111..HIGH
53734  *  0b110..RISE
53735  *  0b101..FALL
53736  */
53737 #define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_MASK)
53738 #define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_MASK   (0x400000U)
53739 #define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_SHIFT  (22U)
53740 /*! WAKEUP_MASK - wakeup mask
53741  */
53742 #define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_MASK)
53743 #define IOMUXD_USDHC1_VSELECT_lp_config_MASK     (0x1800000U)
53744 #define IOMUXD_USDHC1_VSELECT_lp_config_SHIFT    (23U)
53745 /*! lp_config - lower power configuration
53746  *  0b01..EARLY_ISO
53747  *  0b10..LATE_ISO
53748  *  0b11..LATCH
53749  *  0b00..PASS
53750  */
53751 #define IOMUXD_USDHC1_VSELECT_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_lp_config_SHIFT)) & IOMUXD_USDHC1_VSELECT_lp_config_MASK)
53752 #define IOMUXD_USDHC1_VSELECT_sw_config_MASK     (0x6000000U)
53753 #define IOMUXD_USDHC1_VSELECT_sw_config_SHIFT    (25U)
53754 /*! sw_config - output and input configuration
53755  *  0b01..OPEN_DRAIN
53756  *  0b10..OPEN_DRAIN_INPUT
53757  *  0b11..INOUT
53758  *  0b00..DEFAULT
53759  */
53760 #define IOMUXD_USDHC1_VSELECT_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_sw_config_SHIFT)) & IOMUXD_USDHC1_VSELECT_sw_config_MASK)
53761 #define IOMUXD_USDHC1_VSELECT_mux_mode_MASK      (0x38000000U)
53762 #define IOMUXD_USDHC1_VSELECT_mux_mode_SHIFT     (27U)
53763 /*! mux_mode - mux_mode
53764  *  0b000..CONN.USDHC1.VSELECT
53765  *  0b001..CONN.NAND.RE_P
53766  *  0b010..ADMA.SPI2.SDO
53767  *  0b011..CONN.NAND.RE_B
53768  *  0b100..LSIO.GPIO4.IO20
53769  */
53770 #define IOMUXD_USDHC1_VSELECT_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_mux_mode_SHIFT)) & IOMUXD_USDHC1_VSELECT_mux_mode_MASK)
53771 #define IOMUXD_USDHC1_VSELECT_update_pad_ctl_MASK (0x40000000U)
53772 #define IOMUXD_USDHC1_VSELECT_update_pad_ctl_SHIFT (30U)
53773 /*! update_pad_ctl - update lock for pad control
53774  */
53775 #define IOMUXD_USDHC1_VSELECT_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_VSELECT_update_pad_ctl_MASK)
53776 #define IOMUXD_USDHC1_VSELECT_update_mux_mode_MASK (0x80000000U)
53777 #define IOMUXD_USDHC1_VSELECT_update_mux_mode_SHIFT (31U)
53778 /*! update_mux_mode - update lock for mux control
53779  */
53780 #define IOMUXD_USDHC1_VSELECT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_VSELECT_update_mux_mode_MASK)
53781 /*! @} */
53782 
53783 /*! @name IOMUXD_CTL_NAND_RE_P_N - IOMUXD_CTL_NAND_RE_P_N */
53784 /*! @{ */
53785 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_MASK (0x1U)
53786 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_SHIFT (0U)
53787 /*! P_N_SELECT - P_N_SELECT
53788  *  0b0..
53789  *  0b1..
53790  */
53791 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_MASK)
53792 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_MASK (0x3FFFFFFEU)
53793 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_SHIFT (1U)
53794 /*! IOMUXD_CTL_NAND_RE_P_N_reserved_1_29 - reserved
53795  */
53796 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_MASK)
53797 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_MASK (0x40000000U)
53798 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_SHIFT (30U)
53799 /*! update_pad_ctl - update lock for pad control
53800  */
53801 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_MASK)
53802 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_MASK (0x80000000U)
53803 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_SHIFT (31U)
53804 /*! update_mux_mode - update lock for mux control
53805  */
53806 #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_MASK)
53807 /*! @} */
53808 
53809 /*! @name USDHC1_WP - USDHC1_WP */
53810 /*! @{ */
53811 #define IOMUXD_USDHC1_WP_PDRV_MASK               (0x1U)
53812 #define IOMUXD_USDHC1_WP_PDRV_SHIFT              (0U)
53813 /*! PDRV - Drive
53814  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53815  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53816  */
53817 #define IOMUXD_USDHC1_WP_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_PDRV_SHIFT)) & IOMUXD_USDHC1_WP_PDRV_MASK)
53818 #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_MASK (0x1EU)
53819 #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_SHIFT (1U)
53820 /*! USDHC1_WP_reserved_1_4 - reserved
53821  */
53822 #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_MASK)
53823 #define IOMUXD_USDHC1_WP_PULL_MASK               (0x60U)
53824 #define IOMUXD_USDHC1_WP_PULL_SHIFT              (5U)
53825 /*! PULL - Pull Down Pull Up
53826  *  0b10..pull down
53827  *  0b01..pull up
53828  *  0b00..Prohibited
53829  *  0b11..pull disabled
53830  */
53831 #define IOMUXD_USDHC1_WP_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_PULL_SHIFT)) & IOMUXD_USDHC1_WP_PULL_MASK)
53832 #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_MASK (0x7FF80U)
53833 #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_SHIFT (7U)
53834 /*! USDHC1_WP_reserved_7_18 - reserved
53835  */
53836 #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_MASK)
53837 #define IOMUXD_USDHC1_WP_WAKEUP_CTRL_MASK        (0x380000U)
53838 #define IOMUXD_USDHC1_WP_WAKEUP_CTRL_SHIFT       (19U)
53839 /*! WAKEUP_CTRL - wakeup control
53840  *  0b000..OFF
53841  *  0b001..RESAMPLE
53842  *  0b100..LOW
53843  *  0b111..HIGH
53844  *  0b110..RISE
53845  *  0b101..FALL
53846  */
53847 #define IOMUXD_USDHC1_WP_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_WP_WAKEUP_CTRL_MASK)
53848 #define IOMUXD_USDHC1_WP_WAKEUP_MASK_MASK        (0x400000U)
53849 #define IOMUXD_USDHC1_WP_WAKEUP_MASK_SHIFT       (22U)
53850 /*! WAKEUP_MASK - wakeup mask
53851  */
53852 #define IOMUXD_USDHC1_WP_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_WP_WAKEUP_MASK_MASK)
53853 #define IOMUXD_USDHC1_WP_lp_config_MASK          (0x1800000U)
53854 #define IOMUXD_USDHC1_WP_lp_config_SHIFT         (23U)
53855 /*! lp_config - lower power configuration
53856  *  0b01..EARLY_ISO
53857  *  0b10..LATE_ISO
53858  *  0b11..LATCH
53859  *  0b00..PASS
53860  */
53861 #define IOMUXD_USDHC1_WP_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_lp_config_SHIFT)) & IOMUXD_USDHC1_WP_lp_config_MASK)
53862 #define IOMUXD_USDHC1_WP_sw_config_MASK          (0x6000000U)
53863 #define IOMUXD_USDHC1_WP_sw_config_SHIFT         (25U)
53864 /*! sw_config - output and input configuration
53865  *  0b01..OPEN_DRAIN
53866  *  0b10..OPEN_DRAIN_INPUT
53867  *  0b11..INOUT
53868  *  0b00..DEFAULT
53869  */
53870 #define IOMUXD_USDHC1_WP_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_sw_config_SHIFT)) & IOMUXD_USDHC1_WP_sw_config_MASK)
53871 #define IOMUXD_USDHC1_WP_mux_mode_MASK           (0x38000000U)
53872 #define IOMUXD_USDHC1_WP_mux_mode_SHIFT          (27U)
53873 /*! mux_mode - mux_mode
53874  *  0b000..CONN.USDHC1.WP
53875  *  0b001..CONN.NAND.DQS_N
53876  *  0b010..ADMA.SPI2.SDI
53877  *  0b100..LSIO.GPIO4.IO21
53878  */
53879 #define IOMUXD_USDHC1_WP_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_mux_mode_SHIFT)) & IOMUXD_USDHC1_WP_mux_mode_MASK)
53880 #define IOMUXD_USDHC1_WP_update_pad_ctl_MASK     (0x40000000U)
53881 #define IOMUXD_USDHC1_WP_update_pad_ctl_SHIFT    (30U)
53882 /*! update_pad_ctl - update lock for pad control
53883  */
53884 #define IOMUXD_USDHC1_WP_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_WP_update_pad_ctl_MASK)
53885 #define IOMUXD_USDHC1_WP_update_mux_mode_MASK    (0x80000000U)
53886 #define IOMUXD_USDHC1_WP_update_mux_mode_SHIFT   (31U)
53887 /*! update_mux_mode - update lock for mux control
53888  */
53889 #define IOMUXD_USDHC1_WP_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_WP_update_mux_mode_MASK)
53890 /*! @} */
53891 
53892 /*! @name USDHC1_CD_B - USDHC1_CD_B */
53893 /*! @{ */
53894 #define IOMUXD_USDHC1_CD_B_PDRV_MASK             (0x1U)
53895 #define IOMUXD_USDHC1_CD_B_PDRV_SHIFT            (0U)
53896 /*! PDRV - Drive
53897  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53898  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53899  */
53900 #define IOMUXD_USDHC1_CD_B_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_PDRV_SHIFT)) & IOMUXD_USDHC1_CD_B_PDRV_MASK)
53901 #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_MASK (0x1EU)
53902 #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_SHIFT (1U)
53903 /*! USDHC1_CD_B_reserved_1_4 - reserved
53904  */
53905 #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_MASK)
53906 #define IOMUXD_USDHC1_CD_B_PULL_MASK             (0x60U)
53907 #define IOMUXD_USDHC1_CD_B_PULL_SHIFT            (5U)
53908 /*! PULL - Pull Down Pull Up
53909  *  0b10..pull down
53910  *  0b01..pull up
53911  *  0b00..Prohibited
53912  *  0b11..pull disabled
53913  */
53914 #define IOMUXD_USDHC1_CD_B_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_PULL_SHIFT)) & IOMUXD_USDHC1_CD_B_PULL_MASK)
53915 #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_MASK (0x7FF80U)
53916 #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_SHIFT (7U)
53917 /*! USDHC1_CD_B_reserved_7_18 - reserved
53918  */
53919 #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_MASK)
53920 #define IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_MASK      (0x380000U)
53921 #define IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_SHIFT     (19U)
53922 /*! WAKEUP_CTRL - wakeup control
53923  *  0b000..OFF
53924  *  0b001..RESAMPLE
53925  *  0b100..LOW
53926  *  0b111..HIGH
53927  *  0b110..RISE
53928  *  0b101..FALL
53929  */
53930 #define IOMUXD_USDHC1_CD_B_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_MASK)
53931 #define IOMUXD_USDHC1_CD_B_WAKEUP_MASK_MASK      (0x400000U)
53932 #define IOMUXD_USDHC1_CD_B_WAKEUP_MASK_SHIFT     (22U)
53933 /*! WAKEUP_MASK - wakeup mask
53934  */
53935 #define IOMUXD_USDHC1_CD_B_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CD_B_WAKEUP_MASK_MASK)
53936 #define IOMUXD_USDHC1_CD_B_lp_config_MASK        (0x1800000U)
53937 #define IOMUXD_USDHC1_CD_B_lp_config_SHIFT       (23U)
53938 /*! lp_config - lower power configuration
53939  *  0b01..EARLY_ISO
53940  *  0b10..LATE_ISO
53941  *  0b11..LATCH
53942  *  0b00..PASS
53943  */
53944 #define IOMUXD_USDHC1_CD_B_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_lp_config_SHIFT)) & IOMUXD_USDHC1_CD_B_lp_config_MASK)
53945 #define IOMUXD_USDHC1_CD_B_sw_config_MASK        (0x6000000U)
53946 #define IOMUXD_USDHC1_CD_B_sw_config_SHIFT       (25U)
53947 /*! sw_config - output and input configuration
53948  *  0b01..OPEN_DRAIN
53949  *  0b10..OPEN_DRAIN_INPUT
53950  *  0b11..INOUT
53951  *  0b00..DEFAULT
53952  */
53953 #define IOMUXD_USDHC1_CD_B_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_sw_config_SHIFT)) & IOMUXD_USDHC1_CD_B_sw_config_MASK)
53954 #define IOMUXD_USDHC1_CD_B_mux_mode_MASK         (0x38000000U)
53955 #define IOMUXD_USDHC1_CD_B_mux_mode_SHIFT        (27U)
53956 /*! mux_mode - mux_mode
53957  *  0b000..CONN.USDHC1.CD_B
53958  *  0b001..CONN.NAND.DQS_P
53959  *  0b010..ADMA.SPI2.CS0
53960  *  0b011..CONN.NAND.DQS
53961  *  0b100..LSIO.GPIO4.IO22
53962  */
53963 #define IOMUXD_USDHC1_CD_B_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_mux_mode_SHIFT)) & IOMUXD_USDHC1_CD_B_mux_mode_MASK)
53964 #define IOMUXD_USDHC1_CD_B_update_pad_ctl_MASK   (0x40000000U)
53965 #define IOMUXD_USDHC1_CD_B_update_pad_ctl_SHIFT  (30U)
53966 /*! update_pad_ctl - update lock for pad control
53967  */
53968 #define IOMUXD_USDHC1_CD_B_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CD_B_update_pad_ctl_MASK)
53969 #define IOMUXD_USDHC1_CD_B_update_mux_mode_MASK  (0x80000000U)
53970 #define IOMUXD_USDHC1_CD_B_update_mux_mode_SHIFT (31U)
53971 /*! update_mux_mode - update lock for mux control
53972  */
53973 #define IOMUXD_USDHC1_CD_B_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CD_B_update_mux_mode_MASK)
53974 /*! @} */
53975 
53976 /*! @name IOMUXD_CTL_NAND_DQS_P_N - IOMUXD_CTL_NAND_DQS_P_N */
53977 /*! @{ */
53978 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_MASK (0x1U)
53979 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_SHIFT (0U)
53980 /*! P_N_SELECT - P_N_SELECT
53981  *  0b0..
53982  *  0b1..
53983  */
53984 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_MASK)
53985 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_MASK (0x3FFFFFFEU)
53986 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_SHIFT (1U)
53987 /*! IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29 - reserved
53988  */
53989 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_MASK)
53990 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_MASK (0x40000000U)
53991 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_SHIFT (30U)
53992 /*! update_pad_ctl - update lock for pad control
53993  */
53994 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_MASK)
53995 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_MASK (0x80000000U)
53996 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_SHIFT (31U)
53997 /*! update_mux_mode - update lock for mux control
53998  */
53999 #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_MASK)
54000 /*! @} */
54001 
54002 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP - IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP */
54003 /*! @{ */
54004 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_MASK (0x7U)
54005 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_SHIFT (0U)
54006 /*! COMP - COMP
54007  *  0b010..Fixed code mode
54008  *  0b100..High impedance mode
54009  *  0b110..Read mode
54010  *  0b000..Normal Mode
54011  *  0b001..Freeze Mode
54012  */
54013 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_MASK)
54014 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_MASK (0x8U)
54015 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_SHIFT (3U)
54016 /*! FASTFRZ_EN - FASTFRZ_EN
54017  *  0b1..FASTFRZ signal is driven by output of subsystem
54018  *  0b0..FASTFRZ signal is gated to 0
54019  */
54020 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_MASK)
54021 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_MASK (0x10U)
54022 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_SHIFT (4U)
54023 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4 - reserved
54024  */
54025 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_MASK)
54026 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_MASK (0x1E0U)
54027 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_SHIFT (5U)
54028 /*! RASRCP - RASRCP
54029  *  0b0101..Reset Value
54030  */
54031 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_MASK)
54032 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_MASK (0x1E00U)
54033 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_SHIFT (9U)
54034 /*! RASRCN - RASRCN
54035  *  0b1010..Reset Value
54036  */
54037 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_MASK)
54038 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_MASK (0x2000U)
54039 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_SHIFT (13U)
54040 /*! SELECT_NASRC - SELECT_NASRC
54041  *  0b1..NASRCN value
54042  *  0b0..NASRCP value
54043  */
54044 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_MASK)
54045 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_MASK (0x4000U)
54046 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_SHIFT (14U)
54047 /*! COMPOK - COMPOK
54048  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
54049  *  0b1..compensation cell in Normal mode and tracking PVT
54050  */
54051 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_MASK)
54052 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_MASK (0x78000U)
54053 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_SHIFT (15U)
54054 /*! READ_NASRC - READ_NASRC
54055  *  0b0000..READ Only
54056  */
54057 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_MASK)
54058 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_MASK (0x780000U)
54059 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_SHIFT (19U)
54060 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22 - reserved
54061  */
54062 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_MASK)
54063 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_MASK (0x1800000U)
54064 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_SHIFT (23U)
54065 /*! SLEEP - SLEEP
54066  *  0b11..Force into sleep mode
54067  *  0b00..NO
54068  *  0b01..EARLY
54069  *  0b10..LATE
54070  */
54071 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_MASK)
54072 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_MASK (0x3E000000U)
54073 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_SHIFT (25U)
54074 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29 - reserved
54075  */
54076 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_MASK)
54077 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_MASK (0x40000000U)
54078 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_SHIFT (30U)
54079 /*! update_pad_ctl - update lock for pad control
54080  */
54081 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_MASK)
54082 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_MASK (0x80000000U)
54083 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_SHIFT (31U)
54084 /*! update_mux_mode - update lock for mux control
54085  */
54086 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_MASK)
54087 /*! @} */
54088 
54089 /*! @name USDHC1_CLK - USDHC1_CLK */
54090 /*! @{ */
54091 #define IOMUXD_USDHC1_CLK_PDRV_MASK              (0x1U)
54092 #define IOMUXD_USDHC1_CLK_PDRV_SHIFT             (0U)
54093 /*! PDRV - Drive
54094  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54095  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54096  */
54097 #define IOMUXD_USDHC1_CLK_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_PDRV_SHIFT)) & IOMUXD_USDHC1_CLK_PDRV_MASK)
54098 #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_MASK (0x1EU)
54099 #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_SHIFT (1U)
54100 /*! USDHC1_CLK_reserved_1_4 - reserved
54101  */
54102 #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_MASK)
54103 #define IOMUXD_USDHC1_CLK_PULL_MASK              (0x60U)
54104 #define IOMUXD_USDHC1_CLK_PULL_SHIFT             (5U)
54105 /*! PULL - Pull Down Pull Up
54106  *  0b10..pull down
54107  *  0b01..pull up
54108  *  0b00..Prohibited
54109  *  0b11..pull disabled
54110  */
54111 #define IOMUXD_USDHC1_CLK_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_PULL_SHIFT)) & IOMUXD_USDHC1_CLK_PULL_MASK)
54112 #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_MASK (0x7FF80U)
54113 #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_SHIFT (7U)
54114 /*! USDHC1_CLK_reserved_7_18 - reserved
54115  */
54116 #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_MASK)
54117 #define IOMUXD_USDHC1_CLK_WAKEUP_CTRL_MASK       (0x380000U)
54118 #define IOMUXD_USDHC1_CLK_WAKEUP_CTRL_SHIFT      (19U)
54119 /*! WAKEUP_CTRL - wakeup control
54120  *  0b000..OFF
54121  *  0b001..RESAMPLE
54122  *  0b100..LOW
54123  *  0b111..HIGH
54124  *  0b110..RISE
54125  *  0b101..FALL
54126  */
54127 #define IOMUXD_USDHC1_CLK_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CLK_WAKEUP_CTRL_MASK)
54128 #define IOMUXD_USDHC1_CLK_WAKEUP_MASK_MASK       (0x400000U)
54129 #define IOMUXD_USDHC1_CLK_WAKEUP_MASK_SHIFT      (22U)
54130 /*! WAKEUP_MASK - wakeup mask
54131  */
54132 #define IOMUXD_USDHC1_CLK_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CLK_WAKEUP_MASK_MASK)
54133 #define IOMUXD_USDHC1_CLK_lp_config_MASK         (0x1800000U)
54134 #define IOMUXD_USDHC1_CLK_lp_config_SHIFT        (23U)
54135 /*! lp_config - lower power configuration
54136  *  0b01..EARLY_ISO
54137  *  0b10..LATE_ISO
54138  *  0b11..LATCH
54139  *  0b00..PASS
54140  */
54141 #define IOMUXD_USDHC1_CLK_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_lp_config_SHIFT)) & IOMUXD_USDHC1_CLK_lp_config_MASK)
54142 #define IOMUXD_USDHC1_CLK_sw_config_MASK         (0x6000000U)
54143 #define IOMUXD_USDHC1_CLK_sw_config_SHIFT        (25U)
54144 /*! sw_config - output and input configuration
54145  *  0b01..OPEN_DRAIN
54146  *  0b10..OPEN_DRAIN_INPUT
54147  *  0b11..INOUT
54148  *  0b00..DEFAULT
54149  */
54150 #define IOMUXD_USDHC1_CLK_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_sw_config_SHIFT)) & IOMUXD_USDHC1_CLK_sw_config_MASK)
54151 #define IOMUXD_USDHC1_CLK_mux_mode_MASK          (0x38000000U)
54152 #define IOMUXD_USDHC1_CLK_mux_mode_SHIFT         (27U)
54153 /*! mux_mode - mux_mode
54154  *  0b000..CONN.USDHC1.CLK
54155  *  0b010..ADMA.UART3.RX
54156  *  0b100..LSIO.GPIO4.IO23
54157  */
54158 #define IOMUXD_USDHC1_CLK_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_mux_mode_SHIFT)) & IOMUXD_USDHC1_CLK_mux_mode_MASK)
54159 #define IOMUXD_USDHC1_CLK_update_pad_ctl_MASK    (0x40000000U)
54160 #define IOMUXD_USDHC1_CLK_update_pad_ctl_SHIFT   (30U)
54161 /*! update_pad_ctl - update lock for pad control
54162  */
54163 #define IOMUXD_USDHC1_CLK_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CLK_update_pad_ctl_MASK)
54164 #define IOMUXD_USDHC1_CLK_update_mux_mode_MASK   (0x80000000U)
54165 #define IOMUXD_USDHC1_CLK_update_mux_mode_SHIFT  (31U)
54166 /*! update_mux_mode - update lock for mux control
54167  */
54168 #define IOMUXD_USDHC1_CLK_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CLK_update_mux_mode_MASK)
54169 /*! @} */
54170 
54171 /*! @name USDHC1_CMD - USDHC1_CMD */
54172 /*! @{ */
54173 #define IOMUXD_USDHC1_CMD_PDRV_MASK              (0x1U)
54174 #define IOMUXD_USDHC1_CMD_PDRV_SHIFT             (0U)
54175 /*! PDRV - Drive
54176  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54177  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54178  */
54179 #define IOMUXD_USDHC1_CMD_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_PDRV_SHIFT)) & IOMUXD_USDHC1_CMD_PDRV_MASK)
54180 #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_MASK (0x1EU)
54181 #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_SHIFT (1U)
54182 /*! USDHC1_CMD_reserved_1_4 - reserved
54183  */
54184 #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_MASK)
54185 #define IOMUXD_USDHC1_CMD_PULL_MASK              (0x60U)
54186 #define IOMUXD_USDHC1_CMD_PULL_SHIFT             (5U)
54187 /*! PULL - Pull Down Pull Up
54188  *  0b10..pull down
54189  *  0b01..pull up
54190  *  0b00..Prohibited
54191  *  0b11..pull disabled
54192  */
54193 #define IOMUXD_USDHC1_CMD_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_PULL_SHIFT)) & IOMUXD_USDHC1_CMD_PULL_MASK)
54194 #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_MASK (0x7FF80U)
54195 #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_SHIFT (7U)
54196 /*! USDHC1_CMD_reserved_7_18 - reserved
54197  */
54198 #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_MASK)
54199 #define IOMUXD_USDHC1_CMD_WAKEUP_CTRL_MASK       (0x380000U)
54200 #define IOMUXD_USDHC1_CMD_WAKEUP_CTRL_SHIFT      (19U)
54201 /*! WAKEUP_CTRL - wakeup control
54202  *  0b000..OFF
54203  *  0b001..RESAMPLE
54204  *  0b100..LOW
54205  *  0b111..HIGH
54206  *  0b110..RISE
54207  *  0b101..FALL
54208  */
54209 #define IOMUXD_USDHC1_CMD_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CMD_WAKEUP_CTRL_MASK)
54210 #define IOMUXD_USDHC1_CMD_WAKEUP_MASK_MASK       (0x400000U)
54211 #define IOMUXD_USDHC1_CMD_WAKEUP_MASK_SHIFT      (22U)
54212 /*! WAKEUP_MASK - wakeup mask
54213  */
54214 #define IOMUXD_USDHC1_CMD_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CMD_WAKEUP_MASK_MASK)
54215 #define IOMUXD_USDHC1_CMD_lp_config_MASK         (0x1800000U)
54216 #define IOMUXD_USDHC1_CMD_lp_config_SHIFT        (23U)
54217 /*! lp_config - lower power configuration
54218  *  0b01..EARLY_ISO
54219  *  0b10..LATE_ISO
54220  *  0b11..LATCH
54221  *  0b00..PASS
54222  */
54223 #define IOMUXD_USDHC1_CMD_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_lp_config_SHIFT)) & IOMUXD_USDHC1_CMD_lp_config_MASK)
54224 #define IOMUXD_USDHC1_CMD_sw_config_MASK         (0x6000000U)
54225 #define IOMUXD_USDHC1_CMD_sw_config_SHIFT        (25U)
54226 /*! sw_config - output and input configuration
54227  *  0b01..OPEN_DRAIN
54228  *  0b10..OPEN_DRAIN_INPUT
54229  *  0b11..INOUT
54230  *  0b00..DEFAULT
54231  */
54232 #define IOMUXD_USDHC1_CMD_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_sw_config_SHIFT)) & IOMUXD_USDHC1_CMD_sw_config_MASK)
54233 #define IOMUXD_USDHC1_CMD_mux_mode_MASK          (0x38000000U)
54234 #define IOMUXD_USDHC1_CMD_mux_mode_SHIFT         (27U)
54235 /*! mux_mode - mux_mode
54236  *  0b000..CONN.USDHC1.CMD
54237  *  0b001..CONN.NAND.CE0_B
54238  *  0b010..ADMA.MQS.R
54239  *  0b100..LSIO.GPIO4.IO24
54240  */
54241 #define IOMUXD_USDHC1_CMD_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_mux_mode_SHIFT)) & IOMUXD_USDHC1_CMD_mux_mode_MASK)
54242 #define IOMUXD_USDHC1_CMD_update_pad_ctl_MASK    (0x40000000U)
54243 #define IOMUXD_USDHC1_CMD_update_pad_ctl_SHIFT   (30U)
54244 /*! update_pad_ctl - update lock for pad control
54245  */
54246 #define IOMUXD_USDHC1_CMD_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CMD_update_pad_ctl_MASK)
54247 #define IOMUXD_USDHC1_CMD_update_mux_mode_MASK   (0x80000000U)
54248 #define IOMUXD_USDHC1_CMD_update_mux_mode_SHIFT  (31U)
54249 /*! update_mux_mode - update lock for mux control
54250  */
54251 #define IOMUXD_USDHC1_CMD_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CMD_update_mux_mode_MASK)
54252 /*! @} */
54253 
54254 /*! @name USDHC1_DATA0 - USDHC1_DATA0 */
54255 /*! @{ */
54256 #define IOMUXD_USDHC1_DATA0_PDRV_MASK            (0x1U)
54257 #define IOMUXD_USDHC1_DATA0_PDRV_SHIFT           (0U)
54258 /*! PDRV - Drive
54259  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54260  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54261  */
54262 #define IOMUXD_USDHC1_DATA0_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA0_PDRV_MASK)
54263 #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_MASK (0x1EU)
54264 #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_SHIFT (1U)
54265 /*! USDHC1_DATA0_reserved_1_4 - reserved
54266  */
54267 #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_MASK)
54268 #define IOMUXD_USDHC1_DATA0_PULL_MASK            (0x60U)
54269 #define IOMUXD_USDHC1_DATA0_PULL_SHIFT           (5U)
54270 /*! PULL - Pull Down Pull Up
54271  *  0b10..pull down
54272  *  0b01..pull up
54273  *  0b00..Prohibited
54274  *  0b11..pull disabled
54275  */
54276 #define IOMUXD_USDHC1_DATA0_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_PULL_SHIFT)) & IOMUXD_USDHC1_DATA0_PULL_MASK)
54277 #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_MASK (0x7FF80U)
54278 #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_SHIFT (7U)
54279 /*! USDHC1_DATA0_reserved_7_18 - reserved
54280  */
54281 #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_MASK)
54282 #define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_MASK     (0x380000U)
54283 #define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_SHIFT    (19U)
54284 /*! WAKEUP_CTRL - wakeup control
54285  *  0b000..OFF
54286  *  0b001..RESAMPLE
54287  *  0b100..LOW
54288  *  0b111..HIGH
54289  *  0b110..RISE
54290  *  0b101..FALL
54291  */
54292 #define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_MASK)
54293 #define IOMUXD_USDHC1_DATA0_WAKEUP_MASK_MASK     (0x400000U)
54294 #define IOMUXD_USDHC1_DATA0_WAKEUP_MASK_SHIFT    (22U)
54295 /*! WAKEUP_MASK - wakeup mask
54296  */
54297 #define IOMUXD_USDHC1_DATA0_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA0_WAKEUP_MASK_MASK)
54298 #define IOMUXD_USDHC1_DATA0_lp_config_MASK       (0x1800000U)
54299 #define IOMUXD_USDHC1_DATA0_lp_config_SHIFT      (23U)
54300 /*! lp_config - lower power configuration
54301  *  0b01..EARLY_ISO
54302  *  0b10..LATE_ISO
54303  *  0b11..LATCH
54304  *  0b00..PASS
54305  */
54306 #define IOMUXD_USDHC1_DATA0_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA0_lp_config_MASK)
54307 #define IOMUXD_USDHC1_DATA0_sw_config_MASK       (0x6000000U)
54308 #define IOMUXD_USDHC1_DATA0_sw_config_SHIFT      (25U)
54309 /*! sw_config - output and input configuration
54310  *  0b01..OPEN_DRAIN
54311  *  0b10..OPEN_DRAIN_INPUT
54312  *  0b11..INOUT
54313  *  0b00..DEFAULT
54314  */
54315 #define IOMUXD_USDHC1_DATA0_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA0_sw_config_MASK)
54316 #define IOMUXD_USDHC1_DATA0_mux_mode_MASK        (0x38000000U)
54317 #define IOMUXD_USDHC1_DATA0_mux_mode_SHIFT       (27U)
54318 /*! mux_mode - mux_mode
54319  *  0b000..CONN.USDHC1.DATA0
54320  *  0b001..CONN.NAND.CE1_B
54321  *  0b010..ADMA.MQS.L
54322  *  0b100..LSIO.GPIO4.IO25
54323  */
54324 #define IOMUXD_USDHC1_DATA0_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA0_mux_mode_MASK)
54325 #define IOMUXD_USDHC1_DATA0_update_pad_ctl_MASK  (0x40000000U)
54326 #define IOMUXD_USDHC1_DATA0_update_pad_ctl_SHIFT (30U)
54327 /*! update_pad_ctl - update lock for pad control
54328  */
54329 #define IOMUXD_USDHC1_DATA0_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA0_update_pad_ctl_MASK)
54330 #define IOMUXD_USDHC1_DATA0_update_mux_mode_MASK (0x80000000U)
54331 #define IOMUXD_USDHC1_DATA0_update_mux_mode_SHIFT (31U)
54332 /*! update_mux_mode - update lock for mux control
54333  */
54334 #define IOMUXD_USDHC1_DATA0_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA0_update_mux_mode_MASK)
54335 /*! @} */
54336 
54337 /*! @name USDHC1_DATA1 - USDHC1_DATA1 */
54338 /*! @{ */
54339 #define IOMUXD_USDHC1_DATA1_PDRV_MASK            (0x1U)
54340 #define IOMUXD_USDHC1_DATA1_PDRV_SHIFT           (0U)
54341 /*! PDRV - Drive
54342  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54343  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54344  */
54345 #define IOMUXD_USDHC1_DATA1_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA1_PDRV_MASK)
54346 #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_MASK (0x1EU)
54347 #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_SHIFT (1U)
54348 /*! USDHC1_DATA1_reserved_1_4 - reserved
54349  */
54350 #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_MASK)
54351 #define IOMUXD_USDHC1_DATA1_PULL_MASK            (0x60U)
54352 #define IOMUXD_USDHC1_DATA1_PULL_SHIFT           (5U)
54353 /*! PULL - Pull Down Pull Up
54354  *  0b10..pull down
54355  *  0b01..pull up
54356  *  0b00..Prohibited
54357  *  0b11..pull disabled
54358  */
54359 #define IOMUXD_USDHC1_DATA1_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_PULL_SHIFT)) & IOMUXD_USDHC1_DATA1_PULL_MASK)
54360 #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_MASK (0x7FF80U)
54361 #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_SHIFT (7U)
54362 /*! USDHC1_DATA1_reserved_7_18 - reserved
54363  */
54364 #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_MASK)
54365 #define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_MASK     (0x380000U)
54366 #define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_SHIFT    (19U)
54367 /*! WAKEUP_CTRL - wakeup control
54368  *  0b000..OFF
54369  *  0b001..RESAMPLE
54370  *  0b100..LOW
54371  *  0b111..HIGH
54372  *  0b110..RISE
54373  *  0b101..FALL
54374  */
54375 #define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_MASK)
54376 #define IOMUXD_USDHC1_DATA1_WAKEUP_MASK_MASK     (0x400000U)
54377 #define IOMUXD_USDHC1_DATA1_WAKEUP_MASK_SHIFT    (22U)
54378 /*! WAKEUP_MASK - wakeup mask
54379  */
54380 #define IOMUXD_USDHC1_DATA1_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA1_WAKEUP_MASK_MASK)
54381 #define IOMUXD_USDHC1_DATA1_lp_config_MASK       (0x1800000U)
54382 #define IOMUXD_USDHC1_DATA1_lp_config_SHIFT      (23U)
54383 /*! lp_config - lower power configuration
54384  *  0b01..EARLY_ISO
54385  *  0b10..LATE_ISO
54386  *  0b11..LATCH
54387  *  0b00..PASS
54388  */
54389 #define IOMUXD_USDHC1_DATA1_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA1_lp_config_MASK)
54390 #define IOMUXD_USDHC1_DATA1_sw_config_MASK       (0x6000000U)
54391 #define IOMUXD_USDHC1_DATA1_sw_config_SHIFT      (25U)
54392 /*! sw_config - output and input configuration
54393  *  0b01..OPEN_DRAIN
54394  *  0b10..OPEN_DRAIN_INPUT
54395  *  0b11..INOUT
54396  *  0b00..DEFAULT
54397  */
54398 #define IOMUXD_USDHC1_DATA1_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA1_sw_config_MASK)
54399 #define IOMUXD_USDHC1_DATA1_mux_mode_MASK        (0x38000000U)
54400 #define IOMUXD_USDHC1_DATA1_mux_mode_SHIFT       (27U)
54401 /*! mux_mode - mux_mode
54402  *  0b000..CONN.USDHC1.DATA1
54403  *  0b001..CONN.NAND.RE_B
54404  *  0b010..ADMA.UART3.TX
54405  *  0b100..LSIO.GPIO4.IO26
54406  */
54407 #define IOMUXD_USDHC1_DATA1_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA1_mux_mode_MASK)
54408 #define IOMUXD_USDHC1_DATA1_update_pad_ctl_MASK  (0x40000000U)
54409 #define IOMUXD_USDHC1_DATA1_update_pad_ctl_SHIFT (30U)
54410 /*! update_pad_ctl - update lock for pad control
54411  */
54412 #define IOMUXD_USDHC1_DATA1_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA1_update_pad_ctl_MASK)
54413 #define IOMUXD_USDHC1_DATA1_update_mux_mode_MASK (0x80000000U)
54414 #define IOMUXD_USDHC1_DATA1_update_mux_mode_SHIFT (31U)
54415 /*! update_mux_mode - update lock for mux control
54416  */
54417 #define IOMUXD_USDHC1_DATA1_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA1_update_mux_mode_MASK)
54418 /*! @} */
54419 
54420 /*! @name USDHC1_DATA2 - USDHC1_DATA2 */
54421 /*! @{ */
54422 #define IOMUXD_USDHC1_DATA2_PDRV_MASK            (0x1U)
54423 #define IOMUXD_USDHC1_DATA2_PDRV_SHIFT           (0U)
54424 /*! PDRV - Drive
54425  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54426  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54427  */
54428 #define IOMUXD_USDHC1_DATA2_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA2_PDRV_MASK)
54429 #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_MASK (0x1EU)
54430 #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_SHIFT (1U)
54431 /*! USDHC1_DATA2_reserved_1_4 - reserved
54432  */
54433 #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_MASK)
54434 #define IOMUXD_USDHC1_DATA2_PULL_MASK            (0x60U)
54435 #define IOMUXD_USDHC1_DATA2_PULL_SHIFT           (5U)
54436 /*! PULL - Pull Down Pull Up
54437  *  0b10..pull down
54438  *  0b01..pull up
54439  *  0b00..Prohibited
54440  *  0b11..pull disabled
54441  */
54442 #define IOMUXD_USDHC1_DATA2_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_PULL_SHIFT)) & IOMUXD_USDHC1_DATA2_PULL_MASK)
54443 #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_MASK (0x7FF80U)
54444 #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_SHIFT (7U)
54445 /*! USDHC1_DATA2_reserved_7_18 - reserved
54446  */
54447 #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_MASK)
54448 #define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_MASK     (0x380000U)
54449 #define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_SHIFT    (19U)
54450 /*! WAKEUP_CTRL - wakeup control
54451  *  0b000..OFF
54452  *  0b001..RESAMPLE
54453  *  0b100..LOW
54454  *  0b111..HIGH
54455  *  0b110..RISE
54456  *  0b101..FALL
54457  */
54458 #define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_MASK)
54459 #define IOMUXD_USDHC1_DATA2_WAKEUP_MASK_MASK     (0x400000U)
54460 #define IOMUXD_USDHC1_DATA2_WAKEUP_MASK_SHIFT    (22U)
54461 /*! WAKEUP_MASK - wakeup mask
54462  */
54463 #define IOMUXD_USDHC1_DATA2_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA2_WAKEUP_MASK_MASK)
54464 #define IOMUXD_USDHC1_DATA2_lp_config_MASK       (0x1800000U)
54465 #define IOMUXD_USDHC1_DATA2_lp_config_SHIFT      (23U)
54466 /*! lp_config - lower power configuration
54467  *  0b01..EARLY_ISO
54468  *  0b10..LATE_ISO
54469  *  0b11..LATCH
54470  *  0b00..PASS
54471  */
54472 #define IOMUXD_USDHC1_DATA2_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA2_lp_config_MASK)
54473 #define IOMUXD_USDHC1_DATA2_sw_config_MASK       (0x6000000U)
54474 #define IOMUXD_USDHC1_DATA2_sw_config_SHIFT      (25U)
54475 /*! sw_config - output and input configuration
54476  *  0b01..OPEN_DRAIN
54477  *  0b10..OPEN_DRAIN_INPUT
54478  *  0b11..INOUT
54479  *  0b00..DEFAULT
54480  */
54481 #define IOMUXD_USDHC1_DATA2_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA2_sw_config_MASK)
54482 #define IOMUXD_USDHC1_DATA2_mux_mode_MASK        (0x38000000U)
54483 #define IOMUXD_USDHC1_DATA2_mux_mode_SHIFT       (27U)
54484 /*! mux_mode - mux_mode
54485  *  0b000..CONN.USDHC1.DATA2
54486  *  0b001..CONN.NAND.WE_B
54487  *  0b010..ADMA.UART3.CTS_B
54488  *  0b100..LSIO.GPIO4.IO27
54489  */
54490 #define IOMUXD_USDHC1_DATA2_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA2_mux_mode_MASK)
54491 #define IOMUXD_USDHC1_DATA2_update_pad_ctl_MASK  (0x40000000U)
54492 #define IOMUXD_USDHC1_DATA2_update_pad_ctl_SHIFT (30U)
54493 /*! update_pad_ctl - update lock for pad control
54494  */
54495 #define IOMUXD_USDHC1_DATA2_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA2_update_pad_ctl_MASK)
54496 #define IOMUXD_USDHC1_DATA2_update_mux_mode_MASK (0x80000000U)
54497 #define IOMUXD_USDHC1_DATA2_update_mux_mode_SHIFT (31U)
54498 /*! update_mux_mode - update lock for mux control
54499  */
54500 #define IOMUXD_USDHC1_DATA2_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA2_update_mux_mode_MASK)
54501 /*! @} */
54502 
54503 /*! @name USDHC1_DATA3 - USDHC1_DATA3 */
54504 /*! @{ */
54505 #define IOMUXD_USDHC1_DATA3_PDRV_MASK            (0x1U)
54506 #define IOMUXD_USDHC1_DATA3_PDRV_SHIFT           (0U)
54507 /*! PDRV - Drive
54508  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54509  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54510  */
54511 #define IOMUXD_USDHC1_DATA3_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA3_PDRV_MASK)
54512 #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_MASK (0x1EU)
54513 #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_SHIFT (1U)
54514 /*! USDHC1_DATA3_reserved_1_4 - reserved
54515  */
54516 #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_MASK)
54517 #define IOMUXD_USDHC1_DATA3_PULL_MASK            (0x60U)
54518 #define IOMUXD_USDHC1_DATA3_PULL_SHIFT           (5U)
54519 /*! PULL - Pull Down Pull Up
54520  *  0b10..pull down
54521  *  0b01..pull up
54522  *  0b00..Prohibited
54523  *  0b11..pull disabled
54524  */
54525 #define IOMUXD_USDHC1_DATA3_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_PULL_SHIFT)) & IOMUXD_USDHC1_DATA3_PULL_MASK)
54526 #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_MASK (0x7FF80U)
54527 #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_SHIFT (7U)
54528 /*! USDHC1_DATA3_reserved_7_18 - reserved
54529  */
54530 #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_MASK)
54531 #define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_MASK     (0x380000U)
54532 #define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_SHIFT    (19U)
54533 /*! WAKEUP_CTRL - wakeup control
54534  *  0b000..OFF
54535  *  0b001..RESAMPLE
54536  *  0b100..LOW
54537  *  0b111..HIGH
54538  *  0b110..RISE
54539  *  0b101..FALL
54540  */
54541 #define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_MASK)
54542 #define IOMUXD_USDHC1_DATA3_WAKEUP_MASK_MASK     (0x400000U)
54543 #define IOMUXD_USDHC1_DATA3_WAKEUP_MASK_SHIFT    (22U)
54544 /*! WAKEUP_MASK - wakeup mask
54545  */
54546 #define IOMUXD_USDHC1_DATA3_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA3_WAKEUP_MASK_MASK)
54547 #define IOMUXD_USDHC1_DATA3_lp_config_MASK       (0x1800000U)
54548 #define IOMUXD_USDHC1_DATA3_lp_config_SHIFT      (23U)
54549 /*! lp_config - lower power configuration
54550  *  0b01..EARLY_ISO
54551  *  0b10..LATE_ISO
54552  *  0b11..LATCH
54553  *  0b00..PASS
54554  */
54555 #define IOMUXD_USDHC1_DATA3_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA3_lp_config_MASK)
54556 #define IOMUXD_USDHC1_DATA3_sw_config_MASK       (0x6000000U)
54557 #define IOMUXD_USDHC1_DATA3_sw_config_SHIFT      (25U)
54558 /*! sw_config - output and input configuration
54559  *  0b01..OPEN_DRAIN
54560  *  0b10..OPEN_DRAIN_INPUT
54561  *  0b11..INOUT
54562  *  0b00..DEFAULT
54563  */
54564 #define IOMUXD_USDHC1_DATA3_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA3_sw_config_MASK)
54565 #define IOMUXD_USDHC1_DATA3_mux_mode_MASK        (0x38000000U)
54566 #define IOMUXD_USDHC1_DATA3_mux_mode_SHIFT       (27U)
54567 /*! mux_mode - mux_mode
54568  *  0b000..CONN.USDHC1.DATA3
54569  *  0b001..CONN.NAND.ALE
54570  *  0b010..ADMA.UART3.RTS_B
54571  *  0b100..LSIO.GPIO4.IO28
54572  */
54573 #define IOMUXD_USDHC1_DATA3_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA3_mux_mode_MASK)
54574 #define IOMUXD_USDHC1_DATA3_update_pad_ctl_MASK  (0x40000000U)
54575 #define IOMUXD_USDHC1_DATA3_update_pad_ctl_SHIFT (30U)
54576 /*! update_pad_ctl - update lock for pad control
54577  */
54578 #define IOMUXD_USDHC1_DATA3_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA3_update_pad_ctl_MASK)
54579 #define IOMUXD_USDHC1_DATA3_update_mux_mode_MASK (0x80000000U)
54580 #define IOMUXD_USDHC1_DATA3_update_mux_mode_SHIFT (31U)
54581 /*! update_mux_mode - update lock for mux control
54582  */
54583 #define IOMUXD_USDHC1_DATA3_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA3_update_mux_mode_MASK)
54584 /*! @} */
54585 
54586 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 */
54587 /*! @{ */
54588 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_MASK (0x7U)
54589 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_SHIFT (0U)
54590 /*! COMP - COMP
54591  *  0b010..Fixed code mode
54592  *  0b100..High impedance mode
54593  *  0b110..Read mode
54594  *  0b000..Normal Mode
54595  *  0b001..Freeze Mode
54596  */
54597 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_MASK)
54598 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_MASK (0x8U)
54599 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_SHIFT (3U)
54600 /*! FASTFRZ_EN - FASTFRZ_EN
54601  *  0b1..FASTFRZ signal is driven by output of subsystem
54602  *  0b0..FASTFRZ signal is gated to 0
54603  */
54604 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_MASK)
54605 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_MASK (0x10U)
54606 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_SHIFT (4U)
54607 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4 - reserved
54608  */
54609 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_MASK)
54610 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_MASK (0x1E0U)
54611 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_SHIFT (5U)
54612 /*! RASRCP - RASRCP
54613  *  0b0101..Reset Value
54614  */
54615 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_MASK)
54616 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_MASK (0x1E00U)
54617 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_SHIFT (9U)
54618 /*! RASRCN - RASRCN
54619  *  0b1010..Reset Value
54620  */
54621 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_MASK)
54622 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_MASK (0x2000U)
54623 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_SHIFT (13U)
54624 /*! SELECT_NASRC - SELECT_NASRC
54625  *  0b1..NASRCN value
54626  *  0b0..NASRCP value
54627  */
54628 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_MASK)
54629 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_MASK (0x4000U)
54630 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_SHIFT (14U)
54631 /*! COMPOK - COMPOK
54632  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
54633  *  0b1..compensation cell in Normal mode and tracking PVT
54634  */
54635 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_MASK)
54636 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_MASK (0x78000U)
54637 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_SHIFT (15U)
54638 /*! READ_NASRC - READ_NASRC
54639  *  0b0000..READ Only
54640  */
54641 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_MASK)
54642 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_MASK (0x780000U)
54643 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_SHIFT (19U)
54644 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22 - reserved
54645  */
54646 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_MASK)
54647 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_MASK (0x1800000U)
54648 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_SHIFT (23U)
54649 /*! SLEEP - SLEEP
54650  *  0b11..Force into sleep mode
54651  *  0b00..NO
54652  *  0b01..EARLY
54653  *  0b10..LATE
54654  */
54655 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_MASK)
54656 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_MASK (0x3E000000U)
54657 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_SHIFT (25U)
54658 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29 - reserved
54659  */
54660 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_MASK)
54661 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_MASK (0x40000000U)
54662 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_SHIFT (30U)
54663 /*! update_pad_ctl - update lock for pad control
54664  */
54665 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_MASK)
54666 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_MASK (0x80000000U)
54667 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_SHIFT (31U)
54668 /*! update_mux_mode - update lock for mux control
54669  */
54670 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_MASK)
54671 /*! @} */
54672 
54673 /*! @name ENET0_RGMII_TXC - ENET0_RGMII_TXC */
54674 /*! @{ */
54675 #define IOMUXD_ENET0_RGMII_TXC_PDRV_MASK         (0x1U)
54676 #define IOMUXD_ENET0_RGMII_TXC_PDRV_SHIFT        (0U)
54677 /*! PDRV - Drive
54678  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54679  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54680  */
54681 #define IOMUXD_ENET0_RGMII_TXC_PDRV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_PDRV_MASK)
54682 #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_MASK (0x1EU)
54683 #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_SHIFT (1U)
54684 /*! ENET0_RGMII_TXC_reserved_1_4 - reserved
54685  */
54686 #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_MASK)
54687 #define IOMUXD_ENET0_RGMII_TXC_PULL_MASK         (0x60U)
54688 #define IOMUXD_ENET0_RGMII_TXC_PULL_SHIFT        (5U)
54689 /*! PULL - Pull Down Pull Up
54690  *  0b10..pull down
54691  *  0b01..pull up
54692  *  0b00..Prohibited
54693  *  0b11..pull disabled
54694  */
54695 #define IOMUXD_ENET0_RGMII_TXC_PULL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_PULL_MASK)
54696 #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_MASK (0x7FF80U)
54697 #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_SHIFT (7U)
54698 /*! ENET0_RGMII_TXC_reserved_7_18 - reserved
54699  */
54700 #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_MASK)
54701 #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_MASK  (0x380000U)
54702 #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_SHIFT (19U)
54703 /*! WAKEUP_CTRL - wakeup control
54704  *  0b000..OFF
54705  *  0b001..RESAMPLE
54706  *  0b100..LOW
54707  *  0b111..HIGH
54708  *  0b110..RISE
54709  *  0b101..FALL
54710  */
54711 #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_MASK)
54712 #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_MASK  (0x400000U)
54713 #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_SHIFT (22U)
54714 /*! WAKEUP_MASK - wakeup mask
54715  */
54716 #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_MASK)
54717 #define IOMUXD_ENET0_RGMII_TXC_lp_config_MASK    (0x1800000U)
54718 #define IOMUXD_ENET0_RGMII_TXC_lp_config_SHIFT   (23U)
54719 /*! lp_config - lower power configuration
54720  *  0b01..EARLY_ISO
54721  *  0b10..LATE_ISO
54722  *  0b11..LATCH
54723  *  0b00..PASS
54724  */
54725 #define IOMUXD_ENET0_RGMII_TXC_lp_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_lp_config_MASK)
54726 #define IOMUXD_ENET0_RGMII_TXC_sw_config_MASK    (0x6000000U)
54727 #define IOMUXD_ENET0_RGMII_TXC_sw_config_SHIFT   (25U)
54728 /*! sw_config - output and input configuration
54729  *  0b01..OPEN_DRAIN
54730  *  0b10..OPEN_DRAIN_INPUT
54731  *  0b11..INOUT
54732  *  0b00..DEFAULT
54733  */
54734 #define IOMUXD_ENET0_RGMII_TXC_sw_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_sw_config_MASK)
54735 #define IOMUXD_ENET0_RGMII_TXC_mux_mode_MASK     (0x38000000U)
54736 #define IOMUXD_ENET0_RGMII_TXC_mux_mode_SHIFT    (27U)
54737 /*! mux_mode - mux_mode
54738  *  0b000..CONN.ENET0.RGMII_TXC
54739  *  0b001..CONN.ENET0.RCLK50M_OUT
54740  *  0b010..CONN.ENET0.RCLK50M_IN
54741  *  0b011..CONN.NAND.CE1_B
54742  *  0b100..LSIO.GPIO4.IO29
54743  */
54744 #define IOMUXD_ENET0_RGMII_TXC_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_mux_mode_MASK)
54745 #define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_MASK (0x40000000U)
54746 #define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_SHIFT (30U)
54747 /*! update_pad_ctl - update lock for pad control
54748  */
54749 #define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_MASK)
54750 #define IOMUXD_ENET0_RGMII_TXC_update_mux_mode_MASK (0x80000000U)
54751 #define IOMUXD_ENET0_RGMII_TXC_update_mux_mode_SHIFT (31U)
54752 /*! update_mux_mode - update lock for mux control
54753  */
54754 #define IOMUXD_ENET0_RGMII_TXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_update_mux_mode_MASK)
54755 /*! @} */
54756 
54757 /*! @name ENET0_RGMII_TX_CTL - ENET0_RGMII_TX_CTL */
54758 /*! @{ */
54759 #define IOMUXD_ENET0_RGMII_TX_CTL_PDRV_MASK      (0x1U)
54760 #define IOMUXD_ENET0_RGMII_TX_CTL_PDRV_SHIFT     (0U)
54761 /*! PDRV - Drive
54762  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54763  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54764  */
54765 #define IOMUXD_ENET0_RGMII_TX_CTL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_PDRV_MASK)
54766 #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_MASK (0x1EU)
54767 #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_SHIFT (1U)
54768 /*! ENET0_RGMII_TX_CTL_reserved_1_4 - reserved
54769  */
54770 #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_MASK)
54771 #define IOMUXD_ENET0_RGMII_TX_CTL_PULL_MASK      (0x60U)
54772 #define IOMUXD_ENET0_RGMII_TX_CTL_PULL_SHIFT     (5U)
54773 /*! PULL - Pull Down Pull Up
54774  *  0b10..pull down
54775  *  0b01..pull up
54776  *  0b00..Prohibited
54777  *  0b11..pull disabled
54778  */
54779 #define IOMUXD_ENET0_RGMII_TX_CTL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_PULL_MASK)
54780 #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_MASK (0x7FF80U)
54781 #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_SHIFT (7U)
54782 /*! ENET0_RGMII_TX_CTL_reserved_7_18 - reserved
54783  */
54784 #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_MASK)
54785 #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_MASK (0x380000U)
54786 #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT (19U)
54787 /*! WAKEUP_CTRL - wakeup control
54788  *  0b000..OFF
54789  *  0b001..RESAMPLE
54790  *  0b100..LOW
54791  *  0b111..HIGH
54792  *  0b110..RISE
54793  *  0b101..FALL
54794  */
54795 #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_MASK)
54796 #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_MASK (0x400000U)
54797 #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_SHIFT (22U)
54798 /*! WAKEUP_MASK - wakeup mask
54799  */
54800 #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_MASK)
54801 #define IOMUXD_ENET0_RGMII_TX_CTL_lp_config_MASK (0x1800000U)
54802 #define IOMUXD_ENET0_RGMII_TX_CTL_lp_config_SHIFT (23U)
54803 /*! lp_config - lower power configuration
54804  *  0b01..EARLY_ISO
54805  *  0b10..LATE_ISO
54806  *  0b11..LATCH
54807  *  0b00..PASS
54808  */
54809 #define IOMUXD_ENET0_RGMII_TX_CTL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_lp_config_MASK)
54810 #define IOMUXD_ENET0_RGMII_TX_CTL_sw_config_MASK (0x6000000U)
54811 #define IOMUXD_ENET0_RGMII_TX_CTL_sw_config_SHIFT (25U)
54812 /*! sw_config - output and input configuration
54813  *  0b01..OPEN_DRAIN
54814  *  0b10..OPEN_DRAIN_INPUT
54815  *  0b11..INOUT
54816  *  0b00..DEFAULT
54817  */
54818 #define IOMUXD_ENET0_RGMII_TX_CTL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_sw_config_MASK)
54819 #define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_MASK  (0x38000000U)
54820 #define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_SHIFT (27U)
54821 /*! mux_mode - mux_mode
54822  *  0b000..CONN.ENET0.RGMII_TX_CTL
54823  *  0b011..CONN.USDHC1.RESET_B
54824  *  0b100..LSIO.GPIO4.IO30
54825  */
54826 #define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_MASK)
54827 #define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_MASK (0x40000000U)
54828 #define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_SHIFT (30U)
54829 /*! update_pad_ctl - update lock for pad control
54830  */
54831 #define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_MASK)
54832 #define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_MASK (0x80000000U)
54833 #define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_SHIFT (31U)
54834 /*! update_mux_mode - update lock for mux control
54835  */
54836 #define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_MASK)
54837 /*! @} */
54838 
54839 /*! @name IOMUXD_GROUP_1_1 - na */
54840 /*! @{ */
54841 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_MASK (0x1U)
54842 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_SHIFT (0U)
54843 /*! USDHC1_VSELECT - wakeup from USDHC1_VSELECT
54844  */
54845 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_MASK)
54846 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_MASK (0x2U)
54847 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_SHIFT (1U)
54848 /*! iomuxd_group_1_1_reserved_1_1 - reserved
54849  */
54850 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_MASK)
54851 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_MASK   (0x4U)
54852 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_SHIFT  (2U)
54853 /*! USDHC1_WP - wakeup from USDHC1_WP
54854  */
54855 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_MASK)
54856 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_MASK (0x8U)
54857 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_SHIFT (3U)
54858 /*! USDHC1_CD_B - wakeup from USDHC1_CD_B
54859  */
54860 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_MASK)
54861 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_MASK (0x30U)
54862 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_SHIFT (4U)
54863 /*! iomuxd_group_1_1_reserved_4_5 - reserved
54864  */
54865 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_MASK)
54866 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_MASK  (0x40U)
54867 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_SHIFT (6U)
54868 /*! USDHC1_CLK - wakeup from USDHC1_CLK
54869  */
54870 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_MASK)
54871 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_MASK  (0x80U)
54872 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_SHIFT (7U)
54873 /*! USDHC1_CMD - wakeup from USDHC1_CMD
54874  */
54875 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_MASK)
54876 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_MASK (0x100U)
54877 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_SHIFT (8U)
54878 /*! USDHC1_DATA0 - wakeup from USDHC1_DATA0
54879  */
54880 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_MASK)
54881 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_MASK (0x200U)
54882 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_SHIFT (9U)
54883 /*! USDHC1_DATA1 - wakeup from USDHC1_DATA1
54884  */
54885 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_MASK)
54886 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_MASK (0x400U)
54887 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_SHIFT (10U)
54888 /*! USDHC1_DATA2 - wakeup from USDHC1_DATA2
54889  */
54890 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_MASK)
54891 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_MASK (0x800U)
54892 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_SHIFT (11U)
54893 /*! USDHC1_DATA3 - wakeup from USDHC1_DATA3
54894  */
54895 #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_MASK)
54896 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_MASK (0x1000U)
54897 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_SHIFT (12U)
54898 /*! iomuxd_group_1_1_reserved_12_12 - reserved
54899  */
54900 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_MASK)
54901 #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_MASK (0x2000U)
54902 #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_SHIFT (13U)
54903 /*! ENET0_RGMII_TXC - wakeup from ENET0_RGMII_TXC
54904  */
54905 #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_MASK)
54906 #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_MASK (0x4000U)
54907 #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_SHIFT (14U)
54908 /*! ENET0_RGMII_TX_CTL - wakeup from ENET0_RGMII_TX_CTL
54909  */
54910 #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_MASK)
54911 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_MASK (0xFFFF8000U)
54912 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_SHIFT (15U)
54913 /*! iomuxd_group_1_1_reserved_15_31 - reserved
54914  */
54915 #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_MASK)
54916 /*! @} */
54917 
54918 /*! @name ENET0_RGMII_TXD0 - ENET0_RGMII_TXD0 */
54919 /*! @{ */
54920 #define IOMUXD_ENET0_RGMII_TXD0_PDRV_MASK        (0x1U)
54921 #define IOMUXD_ENET0_RGMII_TXD0_PDRV_SHIFT       (0U)
54922 /*! PDRV - Drive
54923  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54924  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54925  */
54926 #define IOMUXD_ENET0_RGMII_TXD0_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_PDRV_MASK)
54927 #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_MASK (0x1EU)
54928 #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_SHIFT (1U)
54929 /*! ENET0_RGMII_TXD0_reserved_1_4 - reserved
54930  */
54931 #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_MASK)
54932 #define IOMUXD_ENET0_RGMII_TXD0_PULL_MASK        (0x60U)
54933 #define IOMUXD_ENET0_RGMII_TXD0_PULL_SHIFT       (5U)
54934 /*! PULL - Pull Down Pull Up
54935  *  0b10..pull down
54936  *  0b01..pull up
54937  *  0b00..Prohibited
54938  *  0b11..pull disabled
54939  */
54940 #define IOMUXD_ENET0_RGMII_TXD0_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_PULL_MASK)
54941 #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_MASK (0x7FF80U)
54942 #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_SHIFT (7U)
54943 /*! ENET0_RGMII_TXD0_reserved_7_18 - reserved
54944  */
54945 #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_MASK)
54946 #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_MASK (0x380000U)
54947 #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_SHIFT (19U)
54948 /*! WAKEUP_CTRL - wakeup control
54949  *  0b000..OFF
54950  *  0b001..RESAMPLE
54951  *  0b100..LOW
54952  *  0b111..HIGH
54953  *  0b110..RISE
54954  *  0b101..FALL
54955  */
54956 #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_MASK)
54957 #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_MASK (0x400000U)
54958 #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_SHIFT (22U)
54959 /*! WAKEUP_MASK - wakeup mask
54960  */
54961 #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_MASK)
54962 #define IOMUXD_ENET0_RGMII_TXD0_lp_config_MASK   (0x1800000U)
54963 #define IOMUXD_ENET0_RGMII_TXD0_lp_config_SHIFT  (23U)
54964 /*! lp_config - lower power configuration
54965  *  0b01..EARLY_ISO
54966  *  0b10..LATE_ISO
54967  *  0b11..LATCH
54968  *  0b00..PASS
54969  */
54970 #define IOMUXD_ENET0_RGMII_TXD0_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_lp_config_MASK)
54971 #define IOMUXD_ENET0_RGMII_TXD0_sw_config_MASK   (0x6000000U)
54972 #define IOMUXD_ENET0_RGMII_TXD0_sw_config_SHIFT  (25U)
54973 /*! sw_config - output and input configuration
54974  *  0b01..OPEN_DRAIN
54975  *  0b10..OPEN_DRAIN_INPUT
54976  *  0b11..INOUT
54977  *  0b00..DEFAULT
54978  */
54979 #define IOMUXD_ENET0_RGMII_TXD0_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_sw_config_MASK)
54980 #define IOMUXD_ENET0_RGMII_TXD0_mux_mode_MASK    (0x38000000U)
54981 #define IOMUXD_ENET0_RGMII_TXD0_mux_mode_SHIFT   (27U)
54982 /*! mux_mode - mux_mode
54983  *  0b000..CONN.ENET0.RGMII_TXD0
54984  *  0b011..CONN.USDHC1.VSELECT
54985  *  0b100..LSIO.GPIO4.IO31
54986  */
54987 #define IOMUXD_ENET0_RGMII_TXD0_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_mux_mode_MASK)
54988 #define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_MASK (0x40000000U)
54989 #define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_SHIFT (30U)
54990 /*! update_pad_ctl - update lock for pad control
54991  */
54992 #define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_MASK)
54993 #define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_MASK (0x80000000U)
54994 #define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_SHIFT (31U)
54995 /*! update_mux_mode - update lock for mux control
54996  */
54997 #define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_MASK)
54998 /*! @} */
54999 
55000 /*! @name ENET0_RGMII_TXD1 - ENET0_RGMII_TXD1 */
55001 /*! @{ */
55002 #define IOMUXD_ENET0_RGMII_TXD1_PDRV_MASK        (0x1U)
55003 #define IOMUXD_ENET0_RGMII_TXD1_PDRV_SHIFT       (0U)
55004 /*! PDRV - Drive
55005  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55006  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55007  */
55008 #define IOMUXD_ENET0_RGMII_TXD1_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_PDRV_MASK)
55009 #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_MASK (0x1EU)
55010 #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_SHIFT (1U)
55011 /*! ENET0_RGMII_TXD1_reserved_1_4 - reserved
55012  */
55013 #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_MASK)
55014 #define IOMUXD_ENET0_RGMII_TXD1_PULL_MASK        (0x60U)
55015 #define IOMUXD_ENET0_RGMII_TXD1_PULL_SHIFT       (5U)
55016 /*! PULL - Pull Down Pull Up
55017  *  0b10..pull down
55018  *  0b01..pull up
55019  *  0b00..Prohibited
55020  *  0b11..pull disabled
55021  */
55022 #define IOMUXD_ENET0_RGMII_TXD1_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_PULL_MASK)
55023 #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_MASK (0x7FF80U)
55024 #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_SHIFT (7U)
55025 /*! ENET0_RGMII_TXD1_reserved_7_18 - reserved
55026  */
55027 #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_MASK)
55028 #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_MASK (0x380000U)
55029 #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_SHIFT (19U)
55030 /*! WAKEUP_CTRL - wakeup control
55031  *  0b000..OFF
55032  *  0b001..RESAMPLE
55033  *  0b100..LOW
55034  *  0b111..HIGH
55035  *  0b110..RISE
55036  *  0b101..FALL
55037  */
55038 #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_MASK)
55039 #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_MASK (0x400000U)
55040 #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_SHIFT (22U)
55041 /*! WAKEUP_MASK - wakeup mask
55042  */
55043 #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_MASK)
55044 #define IOMUXD_ENET0_RGMII_TXD1_lp_config_MASK   (0x1800000U)
55045 #define IOMUXD_ENET0_RGMII_TXD1_lp_config_SHIFT  (23U)
55046 /*! lp_config - lower power configuration
55047  *  0b01..EARLY_ISO
55048  *  0b10..LATE_ISO
55049  *  0b11..LATCH
55050  *  0b00..PASS
55051  */
55052 #define IOMUXD_ENET0_RGMII_TXD1_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_lp_config_MASK)
55053 #define IOMUXD_ENET0_RGMII_TXD1_sw_config_MASK   (0x6000000U)
55054 #define IOMUXD_ENET0_RGMII_TXD1_sw_config_SHIFT  (25U)
55055 /*! sw_config - output and input configuration
55056  *  0b01..OPEN_DRAIN
55057  *  0b10..OPEN_DRAIN_INPUT
55058  *  0b11..INOUT
55059  *  0b00..DEFAULT
55060  */
55061 #define IOMUXD_ENET0_RGMII_TXD1_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_sw_config_MASK)
55062 #define IOMUXD_ENET0_RGMII_TXD1_mux_mode_MASK    (0x38000000U)
55063 #define IOMUXD_ENET0_RGMII_TXD1_mux_mode_SHIFT   (27U)
55064 /*! mux_mode - mux_mode
55065  *  0b000..CONN.ENET0.RGMII_TXD1
55066  *  0b011..CONN.USDHC1.WP
55067  *  0b100..LSIO.GPIO5.IO00
55068  */
55069 #define IOMUXD_ENET0_RGMII_TXD1_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_mux_mode_MASK)
55070 #define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_MASK (0x40000000U)
55071 #define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_SHIFT (30U)
55072 /*! update_pad_ctl - update lock for pad control
55073  */
55074 #define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_MASK)
55075 #define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_MASK (0x80000000U)
55076 #define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_SHIFT (31U)
55077 /*! update_mux_mode - update lock for mux control
55078  */
55079 #define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_MASK)
55080 /*! @} */
55081 
55082 /*! @name ENET0_RGMII_TXD2 - ENET0_RGMII_TXD2 */
55083 /*! @{ */
55084 #define IOMUXD_ENET0_RGMII_TXD2_PDRV_MASK        (0x1U)
55085 #define IOMUXD_ENET0_RGMII_TXD2_PDRV_SHIFT       (0U)
55086 /*! PDRV - Drive
55087  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55088  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55089  */
55090 #define IOMUXD_ENET0_RGMII_TXD2_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_PDRV_MASK)
55091 #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_MASK (0x1EU)
55092 #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_SHIFT (1U)
55093 /*! ENET0_RGMII_TXD2_reserved_1_4 - reserved
55094  */
55095 #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_MASK)
55096 #define IOMUXD_ENET0_RGMII_TXD2_PULL_MASK        (0x60U)
55097 #define IOMUXD_ENET0_RGMII_TXD2_PULL_SHIFT       (5U)
55098 /*! PULL - Pull Down Pull Up
55099  *  0b10..pull down
55100  *  0b01..pull up
55101  *  0b00..Prohibited
55102  *  0b11..pull disabled
55103  */
55104 #define IOMUXD_ENET0_RGMII_TXD2_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_PULL_MASK)
55105 #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_MASK (0x7FF80U)
55106 #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_SHIFT (7U)
55107 /*! ENET0_RGMII_TXD2_reserved_7_18 - reserved
55108  */
55109 #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_MASK)
55110 #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_MASK (0x380000U)
55111 #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_SHIFT (19U)
55112 /*! WAKEUP_CTRL - wakeup control
55113  *  0b000..OFF
55114  *  0b001..RESAMPLE
55115  *  0b100..LOW
55116  *  0b111..HIGH
55117  *  0b110..RISE
55118  *  0b101..FALL
55119  */
55120 #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_MASK)
55121 #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_MASK (0x400000U)
55122 #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_SHIFT (22U)
55123 /*! WAKEUP_MASK - wakeup mask
55124  */
55125 #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_MASK)
55126 #define IOMUXD_ENET0_RGMII_TXD2_lp_config_MASK   (0x1800000U)
55127 #define IOMUXD_ENET0_RGMII_TXD2_lp_config_SHIFT  (23U)
55128 /*! lp_config - lower power configuration
55129  *  0b01..EARLY_ISO
55130  *  0b10..LATE_ISO
55131  *  0b11..LATCH
55132  *  0b00..PASS
55133  */
55134 #define IOMUXD_ENET0_RGMII_TXD2_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_lp_config_MASK)
55135 #define IOMUXD_ENET0_RGMII_TXD2_sw_config_MASK   (0x6000000U)
55136 #define IOMUXD_ENET0_RGMII_TXD2_sw_config_SHIFT  (25U)
55137 /*! sw_config - output and input configuration
55138  *  0b01..OPEN_DRAIN
55139  *  0b10..OPEN_DRAIN_INPUT
55140  *  0b11..INOUT
55141  *  0b00..DEFAULT
55142  */
55143 #define IOMUXD_ENET0_RGMII_TXD2_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_sw_config_MASK)
55144 #define IOMUXD_ENET0_RGMII_TXD2_mux_mode_MASK    (0x38000000U)
55145 #define IOMUXD_ENET0_RGMII_TXD2_mux_mode_SHIFT   (27U)
55146 /*! mux_mode - mux_mode
55147  *  0b000..CONN.ENET0.RGMII_TXD2
55148  *  0b001..CONN.MLB.CLK
55149  *  0b010..CONN.NAND.CE0_B
55150  *  0b011..CONN.USDHC1.CD_B
55151  *  0b100..LSIO.GPIO5.IO01
55152  */
55153 #define IOMUXD_ENET0_RGMII_TXD2_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_mux_mode_MASK)
55154 #define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_MASK (0x40000000U)
55155 #define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_SHIFT (30U)
55156 /*! update_pad_ctl - update lock for pad control
55157  */
55158 #define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_MASK)
55159 #define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_MASK (0x80000000U)
55160 #define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_SHIFT (31U)
55161 /*! update_mux_mode - update lock for mux control
55162  */
55163 #define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_MASK)
55164 /*! @} */
55165 
55166 /*! @name ENET0_RGMII_TXD3 - ENET0_RGMII_TXD3 */
55167 /*! @{ */
55168 #define IOMUXD_ENET0_RGMII_TXD3_PDRV_MASK        (0x1U)
55169 #define IOMUXD_ENET0_RGMII_TXD3_PDRV_SHIFT       (0U)
55170 /*! PDRV - Drive
55171  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55172  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55173  */
55174 #define IOMUXD_ENET0_RGMII_TXD3_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_PDRV_MASK)
55175 #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_MASK (0x1EU)
55176 #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_SHIFT (1U)
55177 /*! ENET0_RGMII_TXD3_reserved_1_4 - reserved
55178  */
55179 #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_MASK)
55180 #define IOMUXD_ENET0_RGMII_TXD3_PULL_MASK        (0x60U)
55181 #define IOMUXD_ENET0_RGMII_TXD3_PULL_SHIFT       (5U)
55182 /*! PULL - Pull Down Pull Up
55183  *  0b10..pull down
55184  *  0b01..pull up
55185  *  0b00..Prohibited
55186  *  0b11..pull disabled
55187  */
55188 #define IOMUXD_ENET0_RGMII_TXD3_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_PULL_MASK)
55189 #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_MASK (0x7FF80U)
55190 #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_SHIFT (7U)
55191 /*! ENET0_RGMII_TXD3_reserved_7_18 - reserved
55192  */
55193 #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_MASK)
55194 #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_MASK (0x380000U)
55195 #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_SHIFT (19U)
55196 /*! WAKEUP_CTRL - wakeup control
55197  *  0b000..OFF
55198  *  0b001..RESAMPLE
55199  *  0b100..LOW
55200  *  0b111..HIGH
55201  *  0b110..RISE
55202  *  0b101..FALL
55203  */
55204 #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_MASK)
55205 #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_MASK (0x400000U)
55206 #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_SHIFT (22U)
55207 /*! WAKEUP_MASK - wakeup mask
55208  */
55209 #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_MASK)
55210 #define IOMUXD_ENET0_RGMII_TXD3_lp_config_MASK   (0x1800000U)
55211 #define IOMUXD_ENET0_RGMII_TXD3_lp_config_SHIFT  (23U)
55212 /*! lp_config - lower power configuration
55213  *  0b01..EARLY_ISO
55214  *  0b10..LATE_ISO
55215  *  0b11..LATCH
55216  *  0b00..PASS
55217  */
55218 #define IOMUXD_ENET0_RGMII_TXD3_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_lp_config_MASK)
55219 #define IOMUXD_ENET0_RGMII_TXD3_sw_config_MASK   (0x6000000U)
55220 #define IOMUXD_ENET0_RGMII_TXD3_sw_config_SHIFT  (25U)
55221 /*! sw_config - output and input configuration
55222  *  0b01..OPEN_DRAIN
55223  *  0b10..OPEN_DRAIN_INPUT
55224  *  0b11..INOUT
55225  *  0b00..DEFAULT
55226  */
55227 #define IOMUXD_ENET0_RGMII_TXD3_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_sw_config_MASK)
55228 #define IOMUXD_ENET0_RGMII_TXD3_mux_mode_MASK    (0x38000000U)
55229 #define IOMUXD_ENET0_RGMII_TXD3_mux_mode_SHIFT   (27U)
55230 /*! mux_mode - mux_mode
55231  *  0b000..CONN.ENET0.RGMII_TXD3
55232  *  0b001..CONN.MLB.SIG
55233  *  0b010..CONN.NAND.RE_B
55234  *  0b100..LSIO.GPIO5.IO02
55235  */
55236 #define IOMUXD_ENET0_RGMII_TXD3_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_mux_mode_MASK)
55237 #define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_MASK (0x40000000U)
55238 #define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_SHIFT (30U)
55239 /*! update_pad_ctl - update lock for pad control
55240  */
55241 #define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_MASK)
55242 #define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_MASK (0x80000000U)
55243 #define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_SHIFT (31U)
55244 /*! update_mux_mode - update lock for mux control
55245  */
55246 #define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_MASK)
55247 /*! @} */
55248 
55249 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 */
55250 /*! @{ */
55251 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_MASK (0x7U)
55252 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_SHIFT (0U)
55253 /*! COMP - COMP
55254  *  0b010..Fixed code mode
55255  *  0b100..High impedance mode
55256  *  0b110..Read mode
55257  *  0b000..Normal Mode
55258  *  0b001..Freeze Mode
55259  */
55260 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_MASK)
55261 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_MASK (0x8U)
55262 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_SHIFT (3U)
55263 /*! FASTFRZ_EN - FASTFRZ_EN
55264  *  0b1..FASTFRZ signal is driven by output of subsystem
55265  *  0b0..FASTFRZ signal is gated to 0
55266  */
55267 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_MASK)
55268 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_MASK (0x10U)
55269 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_SHIFT (4U)
55270 /*! PSW_OVR - PSW_OVR
55271  *  0b1..override output of voltage detector when using 2.5V IO operation
55272  *  0b0..selection coming from voltage detector cell for 1.8V or 3.3V IO operation
55273  */
55274 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_MASK)
55275 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_MASK (0x1E0U)
55276 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_SHIFT (5U)
55277 /*! RASRCP - RASRCP
55278  *  0b0101..Reset Value
55279  */
55280 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_MASK)
55281 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_MASK (0x1E00U)
55282 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_SHIFT (9U)
55283 /*! RASRCN - RASRCN
55284  *  0b1010..Reset Value
55285  */
55286 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_MASK)
55287 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_MASK (0x2000U)
55288 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_SHIFT (13U)
55289 /*! SELECT_NASRC - SELECT_NASRC
55290  *  0b1..NASRCN value
55291  *  0b0..NASRCP value
55292  */
55293 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_MASK)
55294 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_MASK (0x4000U)
55295 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_SHIFT (14U)
55296 /*! COMPOK - COMPOK
55297  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
55298  *  0b1..compensation cell in Normal mode and tracking PVT
55299  */
55300 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_MASK)
55301 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_MASK (0x78000U)
55302 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_SHIFT (15U)
55303 /*! READ_NASRC - READ_NASRC
55304  *  0b0000..READ Only
55305  */
55306 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_MASK)
55307 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_MASK (0x780000U)
55308 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_SHIFT (19U)
55309 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22 - reserved
55310  */
55311 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_MASK)
55312 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_MASK (0x1800000U)
55313 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_SHIFT (23U)
55314 /*! SLEEP - SLEEP
55315  *  0b11..LAST
55316  *  0b00..NO
55317  *  0b01..EARLY
55318  *  0b10..LATE
55319  */
55320 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_MASK)
55321 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_MASK (0x3E000000U)
55322 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_SHIFT (25U)
55323 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29 - reserved
55324  */
55325 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_MASK)
55326 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_MASK (0x40000000U)
55327 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_SHIFT (30U)
55328 /*! update_pad_ctl - update lock for pad control
55329  */
55330 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_MASK)
55331 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_MASK (0x80000000U)
55332 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_SHIFT (31U)
55333 /*! update_mux_mode - update lock for mux control
55334  */
55335 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_MASK)
55336 /*! @} */
55337 
55338 /*! @name ENET0_RGMII_RXC - ENET0_RGMII_RXC */
55339 /*! @{ */
55340 #define IOMUXD_ENET0_RGMII_RXC_PDRV_MASK         (0x1U)
55341 #define IOMUXD_ENET0_RGMII_RXC_PDRV_SHIFT        (0U)
55342 /*! PDRV - Drive
55343  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55344  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55345  */
55346 #define IOMUXD_ENET0_RGMII_RXC_PDRV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_PDRV_MASK)
55347 #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_MASK (0x1EU)
55348 #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_SHIFT (1U)
55349 /*! ENET0_RGMII_RXC_reserved_1_4 - reserved
55350  */
55351 #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_MASK)
55352 #define IOMUXD_ENET0_RGMII_RXC_PULL_MASK         (0x60U)
55353 #define IOMUXD_ENET0_RGMII_RXC_PULL_SHIFT        (5U)
55354 /*! PULL - Pull Down Pull Up
55355  *  0b10..pull down
55356  *  0b01..pull up
55357  *  0b00..Prohibited
55358  *  0b11..pull disabled
55359  */
55360 #define IOMUXD_ENET0_RGMII_RXC_PULL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_PULL_MASK)
55361 #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_MASK (0x7FF80U)
55362 #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_SHIFT (7U)
55363 /*! ENET0_RGMII_RXC_reserved_7_18 - reserved
55364  */
55365 #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_MASK)
55366 #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_MASK  (0x380000U)
55367 #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_SHIFT (19U)
55368 /*! WAKEUP_CTRL - wakeup control
55369  *  0b000..OFF
55370  *  0b001..RESAMPLE
55371  *  0b100..LOW
55372  *  0b111..HIGH
55373  *  0b110..RISE
55374  *  0b101..FALL
55375  */
55376 #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_MASK)
55377 #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_MASK  (0x400000U)
55378 #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_SHIFT (22U)
55379 /*! WAKEUP_MASK - wakeup mask
55380  */
55381 #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_MASK)
55382 #define IOMUXD_ENET0_RGMII_RXC_lp_config_MASK    (0x1800000U)
55383 #define IOMUXD_ENET0_RGMII_RXC_lp_config_SHIFT   (23U)
55384 /*! lp_config - lower power configuration
55385  *  0b01..EARLY_ISO
55386  *  0b10..LATE_ISO
55387  *  0b11..LATCH
55388  *  0b00..PASS
55389  */
55390 #define IOMUXD_ENET0_RGMII_RXC_lp_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_lp_config_MASK)
55391 #define IOMUXD_ENET0_RGMII_RXC_sw_config_MASK    (0x6000000U)
55392 #define IOMUXD_ENET0_RGMII_RXC_sw_config_SHIFT   (25U)
55393 /*! sw_config - output and input configuration
55394  *  0b01..OPEN_DRAIN
55395  *  0b10..OPEN_DRAIN_INPUT
55396  *  0b11..INOUT
55397  *  0b00..DEFAULT
55398  */
55399 #define IOMUXD_ENET0_RGMII_RXC_sw_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_sw_config_MASK)
55400 #define IOMUXD_ENET0_RGMII_RXC_mux_mode_MASK     (0x38000000U)
55401 #define IOMUXD_ENET0_RGMII_RXC_mux_mode_SHIFT    (27U)
55402 /*! mux_mode - mux_mode
55403  *  0b000..CONN.ENET0.RGMII_RXC
55404  *  0b001..CONN.MLB.DATA
55405  *  0b010..CONN.NAND.WE_B
55406  *  0b011..CONN.USDHC1.CLK
55407  *  0b100..LSIO.GPIO5.IO03
55408  */
55409 #define IOMUXD_ENET0_RGMII_RXC_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_mux_mode_MASK)
55410 #define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_MASK (0x40000000U)
55411 #define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_SHIFT (30U)
55412 /*! update_pad_ctl - update lock for pad control
55413  */
55414 #define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_MASK)
55415 #define IOMUXD_ENET0_RGMII_RXC_update_mux_mode_MASK (0x80000000U)
55416 #define IOMUXD_ENET0_RGMII_RXC_update_mux_mode_SHIFT (31U)
55417 /*! update_mux_mode - update lock for mux control
55418  */
55419 #define IOMUXD_ENET0_RGMII_RXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_update_mux_mode_MASK)
55420 /*! @} */
55421 
55422 /*! @name ENET0_RGMII_RX_CTL - ENET0_RGMII_RX_CTL */
55423 /*! @{ */
55424 #define IOMUXD_ENET0_RGMII_RX_CTL_PDRV_MASK      (0x1U)
55425 #define IOMUXD_ENET0_RGMII_RX_CTL_PDRV_SHIFT     (0U)
55426 /*! PDRV - Drive
55427  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55428  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55429  */
55430 #define IOMUXD_ENET0_RGMII_RX_CTL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_PDRV_MASK)
55431 #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_MASK (0x1EU)
55432 #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_SHIFT (1U)
55433 /*! ENET0_RGMII_RX_CTL_reserved_1_4 - reserved
55434  */
55435 #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_MASK)
55436 #define IOMUXD_ENET0_RGMII_RX_CTL_PULL_MASK      (0x60U)
55437 #define IOMUXD_ENET0_RGMII_RX_CTL_PULL_SHIFT     (5U)
55438 /*! PULL - Pull Down Pull Up
55439  *  0b10..pull down
55440  *  0b01..pull up
55441  *  0b00..Prohibited
55442  *  0b11..pull disabled
55443  */
55444 #define IOMUXD_ENET0_RGMII_RX_CTL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_PULL_MASK)
55445 #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_MASK (0x7FF80U)
55446 #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_SHIFT (7U)
55447 /*! ENET0_RGMII_RX_CTL_reserved_7_18 - reserved
55448  */
55449 #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_MASK)
55450 #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_MASK (0x380000U)
55451 #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT (19U)
55452 /*! WAKEUP_CTRL - wakeup control
55453  *  0b000..OFF
55454  *  0b001..RESAMPLE
55455  *  0b100..LOW
55456  *  0b111..HIGH
55457  *  0b110..RISE
55458  *  0b101..FALL
55459  */
55460 #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_MASK)
55461 #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_MASK (0x400000U)
55462 #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_SHIFT (22U)
55463 /*! WAKEUP_MASK - wakeup mask
55464  */
55465 #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_MASK)
55466 #define IOMUXD_ENET0_RGMII_RX_CTL_lp_config_MASK (0x1800000U)
55467 #define IOMUXD_ENET0_RGMII_RX_CTL_lp_config_SHIFT (23U)
55468 /*! lp_config - lower power configuration
55469  *  0b01..EARLY_ISO
55470  *  0b10..LATE_ISO
55471  *  0b11..LATCH
55472  *  0b00..PASS
55473  */
55474 #define IOMUXD_ENET0_RGMII_RX_CTL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_lp_config_MASK)
55475 #define IOMUXD_ENET0_RGMII_RX_CTL_sw_config_MASK (0x6000000U)
55476 #define IOMUXD_ENET0_RGMII_RX_CTL_sw_config_SHIFT (25U)
55477 /*! sw_config - output and input configuration
55478  *  0b01..OPEN_DRAIN
55479  *  0b10..OPEN_DRAIN_INPUT
55480  *  0b11..INOUT
55481  *  0b00..DEFAULT
55482  */
55483 #define IOMUXD_ENET0_RGMII_RX_CTL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_sw_config_MASK)
55484 #define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_MASK  (0x38000000U)
55485 #define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_SHIFT (27U)
55486 /*! mux_mode - mux_mode
55487  *  0b000..CONN.ENET0.RGMII_RX_CTL
55488  *  0b011..CONN.USDHC1.CMD
55489  *  0b100..LSIO.GPIO5.IO04
55490  */
55491 #define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_MASK)
55492 #define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_MASK (0x40000000U)
55493 #define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_SHIFT (30U)
55494 /*! update_pad_ctl - update lock for pad control
55495  */
55496 #define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_MASK)
55497 #define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_MASK (0x80000000U)
55498 #define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_SHIFT (31U)
55499 /*! update_mux_mode - update lock for mux control
55500  */
55501 #define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_MASK)
55502 /*! @} */
55503 
55504 /*! @name ENET0_RGMII_RXD0 - ENET0_RGMII_RXD0 */
55505 /*! @{ */
55506 #define IOMUXD_ENET0_RGMII_RXD0_PDRV_MASK        (0x1U)
55507 #define IOMUXD_ENET0_RGMII_RXD0_PDRV_SHIFT       (0U)
55508 /*! PDRV - Drive
55509  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55510  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55511  */
55512 #define IOMUXD_ENET0_RGMII_RXD0_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_PDRV_MASK)
55513 #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_MASK (0x1EU)
55514 #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_SHIFT (1U)
55515 /*! ENET0_RGMII_RXD0_reserved_1_4 - reserved
55516  */
55517 #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_MASK)
55518 #define IOMUXD_ENET0_RGMII_RXD0_PULL_MASK        (0x60U)
55519 #define IOMUXD_ENET0_RGMII_RXD0_PULL_SHIFT       (5U)
55520 /*! PULL - Pull Down Pull Up
55521  *  0b10..pull down
55522  *  0b01..pull up
55523  *  0b00..Prohibited
55524  *  0b11..pull disabled
55525  */
55526 #define IOMUXD_ENET0_RGMII_RXD0_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_PULL_MASK)
55527 #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_MASK (0x7FF80U)
55528 #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_SHIFT (7U)
55529 /*! ENET0_RGMII_RXD0_reserved_7_18 - reserved
55530  */
55531 #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_MASK)
55532 #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_MASK (0x380000U)
55533 #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_SHIFT (19U)
55534 /*! WAKEUP_CTRL - wakeup control
55535  *  0b000..OFF
55536  *  0b001..RESAMPLE
55537  *  0b100..LOW
55538  *  0b111..HIGH
55539  *  0b110..RISE
55540  *  0b101..FALL
55541  */
55542 #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_MASK)
55543 #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_MASK (0x400000U)
55544 #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_SHIFT (22U)
55545 /*! WAKEUP_MASK - wakeup mask
55546  */
55547 #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_MASK)
55548 #define IOMUXD_ENET0_RGMII_RXD0_lp_config_MASK   (0x1800000U)
55549 #define IOMUXD_ENET0_RGMII_RXD0_lp_config_SHIFT  (23U)
55550 /*! lp_config - lower power configuration
55551  *  0b01..EARLY_ISO
55552  *  0b10..LATE_ISO
55553  *  0b11..LATCH
55554  *  0b00..PASS
55555  */
55556 #define IOMUXD_ENET0_RGMII_RXD0_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_lp_config_MASK)
55557 #define IOMUXD_ENET0_RGMII_RXD0_sw_config_MASK   (0x6000000U)
55558 #define IOMUXD_ENET0_RGMII_RXD0_sw_config_SHIFT  (25U)
55559 /*! sw_config - output and input configuration
55560  *  0b01..OPEN_DRAIN
55561  *  0b10..OPEN_DRAIN_INPUT
55562  *  0b11..INOUT
55563  *  0b00..DEFAULT
55564  */
55565 #define IOMUXD_ENET0_RGMII_RXD0_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_sw_config_MASK)
55566 #define IOMUXD_ENET0_RGMII_RXD0_mux_mode_MASK    (0x38000000U)
55567 #define IOMUXD_ENET0_RGMII_RXD0_mux_mode_SHIFT   (27U)
55568 /*! mux_mode - mux_mode
55569  *  0b000..CONN.ENET0.RGMII_RXD0
55570  *  0b011..CONN.USDHC1.DATA0
55571  *  0b100..LSIO.GPIO5.IO05
55572  */
55573 #define IOMUXD_ENET0_RGMII_RXD0_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_mux_mode_MASK)
55574 #define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_MASK (0x40000000U)
55575 #define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_SHIFT (30U)
55576 /*! update_pad_ctl - update lock for pad control
55577  */
55578 #define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_MASK)
55579 #define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_MASK (0x80000000U)
55580 #define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_SHIFT (31U)
55581 /*! update_mux_mode - update lock for mux control
55582  */
55583 #define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_MASK)
55584 /*! @} */
55585 
55586 /*! @name ENET0_RGMII_RXD1 - ENET0_RGMII_RXD1 */
55587 /*! @{ */
55588 #define IOMUXD_ENET0_RGMII_RXD1_PDRV_MASK        (0x1U)
55589 #define IOMUXD_ENET0_RGMII_RXD1_PDRV_SHIFT       (0U)
55590 /*! PDRV - Drive
55591  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55592  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55593  */
55594 #define IOMUXD_ENET0_RGMII_RXD1_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_PDRV_MASK)
55595 #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_MASK (0x1EU)
55596 #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_SHIFT (1U)
55597 /*! ENET0_RGMII_RXD1_reserved_1_4 - reserved
55598  */
55599 #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_MASK)
55600 #define IOMUXD_ENET0_RGMII_RXD1_PULL_MASK        (0x60U)
55601 #define IOMUXD_ENET0_RGMII_RXD1_PULL_SHIFT       (5U)
55602 /*! PULL - Pull Down Pull Up
55603  *  0b10..pull down
55604  *  0b01..pull up
55605  *  0b00..Prohibited
55606  *  0b11..pull disabled
55607  */
55608 #define IOMUXD_ENET0_RGMII_RXD1_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_PULL_MASK)
55609 #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_MASK (0x7FF80U)
55610 #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_SHIFT (7U)
55611 /*! ENET0_RGMII_RXD1_reserved_7_18 - reserved
55612  */
55613 #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_MASK)
55614 #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_MASK (0x380000U)
55615 #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_SHIFT (19U)
55616 /*! WAKEUP_CTRL - wakeup control
55617  *  0b000..OFF
55618  *  0b001..RESAMPLE
55619  *  0b100..LOW
55620  *  0b111..HIGH
55621  *  0b110..RISE
55622  *  0b101..FALL
55623  */
55624 #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_MASK)
55625 #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_MASK (0x400000U)
55626 #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_SHIFT (22U)
55627 /*! WAKEUP_MASK - wakeup mask
55628  */
55629 #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_MASK)
55630 #define IOMUXD_ENET0_RGMII_RXD1_lp_config_MASK   (0x1800000U)
55631 #define IOMUXD_ENET0_RGMII_RXD1_lp_config_SHIFT  (23U)
55632 /*! lp_config - lower power configuration
55633  *  0b01..EARLY_ISO
55634  *  0b10..LATE_ISO
55635  *  0b11..LATCH
55636  *  0b00..PASS
55637  */
55638 #define IOMUXD_ENET0_RGMII_RXD1_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_lp_config_MASK)
55639 #define IOMUXD_ENET0_RGMII_RXD1_sw_config_MASK   (0x6000000U)
55640 #define IOMUXD_ENET0_RGMII_RXD1_sw_config_SHIFT  (25U)
55641 /*! sw_config - output and input configuration
55642  *  0b01..OPEN_DRAIN
55643  *  0b10..OPEN_DRAIN_INPUT
55644  *  0b11..INOUT
55645  *  0b00..DEFAULT
55646  */
55647 #define IOMUXD_ENET0_RGMII_RXD1_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_sw_config_MASK)
55648 #define IOMUXD_ENET0_RGMII_RXD1_mux_mode_MASK    (0x38000000U)
55649 #define IOMUXD_ENET0_RGMII_RXD1_mux_mode_SHIFT   (27U)
55650 /*! mux_mode - mux_mode
55651  *  0b000..CONN.ENET0.RGMII_RXD1
55652  *  0b011..CONN.USDHC1.DATA1
55653  *  0b100..LSIO.GPIO5.IO06
55654  */
55655 #define IOMUXD_ENET0_RGMII_RXD1_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_mux_mode_MASK)
55656 #define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_MASK (0x40000000U)
55657 #define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_SHIFT (30U)
55658 /*! update_pad_ctl - update lock for pad control
55659  */
55660 #define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_MASK)
55661 #define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_MASK (0x80000000U)
55662 #define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_SHIFT (31U)
55663 /*! update_mux_mode - update lock for mux control
55664  */
55665 #define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_MASK)
55666 /*! @} */
55667 
55668 /*! @name ENET0_RGMII_RXD2 - ENET0_RGMII_RXD2 */
55669 /*! @{ */
55670 #define IOMUXD_ENET0_RGMII_RXD2_PDRV_MASK        (0x1U)
55671 #define IOMUXD_ENET0_RGMII_RXD2_PDRV_SHIFT       (0U)
55672 /*! PDRV - Drive
55673  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55674  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55675  */
55676 #define IOMUXD_ENET0_RGMII_RXD2_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_PDRV_MASK)
55677 #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_MASK (0x1EU)
55678 #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_SHIFT (1U)
55679 /*! ENET0_RGMII_RXD2_reserved_1_4 - reserved
55680  */
55681 #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_MASK)
55682 #define IOMUXD_ENET0_RGMII_RXD2_PULL_MASK        (0x60U)
55683 #define IOMUXD_ENET0_RGMII_RXD2_PULL_SHIFT       (5U)
55684 /*! PULL - Pull Down Pull Up
55685  *  0b10..pull down
55686  *  0b01..pull up
55687  *  0b00..Prohibited
55688  *  0b11..pull disabled
55689  */
55690 #define IOMUXD_ENET0_RGMII_RXD2_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_PULL_MASK)
55691 #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_MASK (0x7FF80U)
55692 #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_SHIFT (7U)
55693 /*! ENET0_RGMII_RXD2_reserved_7_18 - reserved
55694  */
55695 #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_MASK)
55696 #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_MASK (0x380000U)
55697 #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_SHIFT (19U)
55698 /*! WAKEUP_CTRL - wakeup control
55699  *  0b000..OFF
55700  *  0b001..RESAMPLE
55701  *  0b100..LOW
55702  *  0b111..HIGH
55703  *  0b110..RISE
55704  *  0b101..FALL
55705  */
55706 #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_MASK)
55707 #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_MASK (0x400000U)
55708 #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_SHIFT (22U)
55709 /*! WAKEUP_MASK - wakeup mask
55710  */
55711 #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_MASK)
55712 #define IOMUXD_ENET0_RGMII_RXD2_lp_config_MASK   (0x1800000U)
55713 #define IOMUXD_ENET0_RGMII_RXD2_lp_config_SHIFT  (23U)
55714 /*! lp_config - lower power configuration
55715  *  0b01..EARLY_ISO
55716  *  0b10..LATE_ISO
55717  *  0b11..LATCH
55718  *  0b00..PASS
55719  */
55720 #define IOMUXD_ENET0_RGMII_RXD2_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_lp_config_MASK)
55721 #define IOMUXD_ENET0_RGMII_RXD2_sw_config_MASK   (0x6000000U)
55722 #define IOMUXD_ENET0_RGMII_RXD2_sw_config_SHIFT  (25U)
55723 /*! sw_config - output and input configuration
55724  *  0b01..OPEN_DRAIN
55725  *  0b10..OPEN_DRAIN_INPUT
55726  *  0b11..INOUT
55727  *  0b00..DEFAULT
55728  */
55729 #define IOMUXD_ENET0_RGMII_RXD2_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_sw_config_MASK)
55730 #define IOMUXD_ENET0_RGMII_RXD2_mux_mode_MASK    (0x38000000U)
55731 #define IOMUXD_ENET0_RGMII_RXD2_mux_mode_SHIFT   (27U)
55732 /*! mux_mode - mux_mode
55733  *  0b000..CONN.ENET0.RGMII_RXD2
55734  *  0b001..CONN.ENET0.RMII_RX_ER
55735  *  0b011..CONN.USDHC1.DATA2
55736  *  0b100..LSIO.GPIO5.IO07
55737  */
55738 #define IOMUXD_ENET0_RGMII_RXD2_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_mux_mode_MASK)
55739 #define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_MASK (0x40000000U)
55740 #define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_SHIFT (30U)
55741 /*! update_pad_ctl - update lock for pad control
55742  */
55743 #define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_MASK)
55744 #define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_MASK (0x80000000U)
55745 #define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_SHIFT (31U)
55746 /*! update_mux_mode - update lock for mux control
55747  */
55748 #define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_MASK)
55749 /*! @} */
55750 
55751 /*! @name ENET0_RGMII_RXD3 - ENET0_RGMII_RXD3 */
55752 /*! @{ */
55753 #define IOMUXD_ENET0_RGMII_RXD3_PDRV_MASK        (0x1U)
55754 #define IOMUXD_ENET0_RGMII_RXD3_PDRV_SHIFT       (0U)
55755 /*! PDRV - Drive
55756  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55757  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55758  */
55759 #define IOMUXD_ENET0_RGMII_RXD3_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_PDRV_MASK)
55760 #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_MASK (0x1EU)
55761 #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_SHIFT (1U)
55762 /*! ENET0_RGMII_RXD3_reserved_1_4 - reserved
55763  */
55764 #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_MASK)
55765 #define IOMUXD_ENET0_RGMII_RXD3_PULL_MASK        (0x60U)
55766 #define IOMUXD_ENET0_RGMII_RXD3_PULL_SHIFT       (5U)
55767 /*! PULL - Pull Down Pull Up
55768  *  0b10..pull down
55769  *  0b01..pull up
55770  *  0b00..Prohibited
55771  *  0b11..pull disabled
55772  */
55773 #define IOMUXD_ENET0_RGMII_RXD3_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_PULL_MASK)
55774 #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_MASK (0x7FF80U)
55775 #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_SHIFT (7U)
55776 /*! ENET0_RGMII_RXD3_reserved_7_18 - reserved
55777  */
55778 #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_MASK)
55779 #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_MASK (0x380000U)
55780 #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_SHIFT (19U)
55781 /*! WAKEUP_CTRL - wakeup control
55782  *  0b000..OFF
55783  *  0b001..RESAMPLE
55784  *  0b100..LOW
55785  *  0b111..HIGH
55786  *  0b110..RISE
55787  *  0b101..FALL
55788  */
55789 #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_MASK)
55790 #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_MASK (0x400000U)
55791 #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_SHIFT (22U)
55792 /*! WAKEUP_MASK - wakeup mask
55793  */
55794 #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_MASK)
55795 #define IOMUXD_ENET0_RGMII_RXD3_lp_config_MASK   (0x1800000U)
55796 #define IOMUXD_ENET0_RGMII_RXD3_lp_config_SHIFT  (23U)
55797 /*! lp_config - lower power configuration
55798  *  0b01..EARLY_ISO
55799  *  0b10..LATE_ISO
55800  *  0b11..LATCH
55801  *  0b00..PASS
55802  */
55803 #define IOMUXD_ENET0_RGMII_RXD3_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_lp_config_MASK)
55804 #define IOMUXD_ENET0_RGMII_RXD3_sw_config_MASK   (0x6000000U)
55805 #define IOMUXD_ENET0_RGMII_RXD3_sw_config_SHIFT  (25U)
55806 /*! sw_config - output and input configuration
55807  *  0b01..OPEN_DRAIN
55808  *  0b10..OPEN_DRAIN_INPUT
55809  *  0b11..INOUT
55810  *  0b00..DEFAULT
55811  */
55812 #define IOMUXD_ENET0_RGMII_RXD3_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_sw_config_MASK)
55813 #define IOMUXD_ENET0_RGMII_RXD3_mux_mode_MASK    (0x38000000U)
55814 #define IOMUXD_ENET0_RGMII_RXD3_mux_mode_SHIFT   (27U)
55815 /*! mux_mode - mux_mode
55816  *  0b000..CONN.ENET0.RGMII_RXD3
55817  *  0b010..CONN.NAND.ALE
55818  *  0b011..CONN.USDHC1.DATA3
55819  *  0b100..LSIO.GPIO5.IO08
55820  */
55821 #define IOMUXD_ENET0_RGMII_RXD3_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_mux_mode_MASK)
55822 #define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_MASK (0x40000000U)
55823 #define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_SHIFT (30U)
55824 /*! update_pad_ctl - update lock for pad control
55825  */
55826 #define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_MASK)
55827 #define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_MASK (0x80000000U)
55828 #define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_SHIFT (31U)
55829 /*! update_mux_mode - update lock for mux control
55830  */
55831 #define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_MASK)
55832 /*! @} */
55833 
55834 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 */
55835 /*! @{ */
55836 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_MASK (0x7U)
55837 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_SHIFT (0U)
55838 /*! COMP - COMP
55839  *  0b010..Fixed code mode
55840  *  0b100..High impedance mode
55841  *  0b110..Read mode
55842  *  0b000..Normal Mode
55843  *  0b001..Freeze Mode
55844  */
55845 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_MASK)
55846 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_MASK (0x8U)
55847 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_SHIFT (3U)
55848 /*! FASTFRZ_EN - FASTFRZ_EN
55849  *  0b1..FASTFRZ signal is driven by output of subsystem
55850  *  0b0..FASTFRZ signal is gated to 0
55851  */
55852 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_MASK)
55853 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_MASK (0x10U)
55854 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_SHIFT (4U)
55855 /*! PSW_OVR - PSW_OVR
55856  *  0b1..override output of voltage detector when using 2.5V IO operation
55857  *  0b0..selection coming from voltage detector cell for 1.8V or 3.3V IO operation
55858  */
55859 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_MASK)
55860 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_MASK (0x1E0U)
55861 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_SHIFT (5U)
55862 /*! RASRCP - RASRCP
55863  *  0b0101..Reset Value
55864  */
55865 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_MASK)
55866 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_MASK (0x1E00U)
55867 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_SHIFT (9U)
55868 /*! RASRCN - RASRCN
55869  *  0b1010..Reset Value
55870  */
55871 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_MASK)
55872 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_MASK (0x2000U)
55873 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_SHIFT (13U)
55874 /*! SELECT_NASRC - SELECT_NASRC
55875  *  0b1..NASRCN value
55876  *  0b0..NASRCP value
55877  */
55878 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_MASK)
55879 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_MASK (0x4000U)
55880 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_SHIFT (14U)
55881 /*! COMPOK - COMPOK
55882  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
55883  *  0b1..compensation cell in Normal mode and tracking PVT
55884  */
55885 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_MASK)
55886 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_MASK (0x78000U)
55887 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_SHIFT (15U)
55888 /*! READ_NASRC - READ_NASRC
55889  *  0b0000..READ Only
55890  */
55891 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_MASK)
55892 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_MASK (0x780000U)
55893 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_SHIFT (19U)
55894 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22 - reserved
55895  */
55896 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_MASK)
55897 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_MASK (0x1800000U)
55898 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_SHIFT (23U)
55899 /*! SLEEP - SLEEP
55900  *  0b11..LAST
55901  *  0b00..NO
55902  *  0b01..EARLY
55903  *  0b10..LATE
55904  */
55905 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_MASK)
55906 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_MASK (0x3E000000U)
55907 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_SHIFT (25U)
55908 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29 - reserved
55909  */
55910 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_MASK)
55911 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_MASK (0x40000000U)
55912 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_SHIFT (30U)
55913 /*! update_pad_ctl - update lock for pad control
55914  */
55915 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_MASK)
55916 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_MASK (0x80000000U)
55917 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_SHIFT (31U)
55918 /*! update_mux_mode - update lock for mux control
55919  */
55920 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_MASK)
55921 /*! @} */
55922 
55923 /*! @name ENET0_REFCLK_125M_25M - ENET0_REFCLK_125M_25M */
55924 /*! @{ */
55925 #define IOMUXD_ENET0_REFCLK_125M_25M_PDRV_MASK   (0x1U)
55926 #define IOMUXD_ENET0_REFCLK_125M_25M_PDRV_SHIFT  (0U)
55927 /*! PDRV - Drive
55928  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55929  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55930  */
55931 #define IOMUXD_ENET0_REFCLK_125M_25M_PDRV(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_PDRV_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_PDRV_MASK)
55932 #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_MASK (0x1EU)
55933 #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_SHIFT (1U)
55934 /*! ENET0_REFCLK_125M_25M_reserved_1_4 - reserved
55935  */
55936 #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_MASK)
55937 #define IOMUXD_ENET0_REFCLK_125M_25M_PULL_MASK   (0x60U)
55938 #define IOMUXD_ENET0_REFCLK_125M_25M_PULL_SHIFT  (5U)
55939 /*! PULL - Pull Down Pull Up
55940  *  0b10..pull down
55941  *  0b01..pull up
55942  *  0b00..Prohibited
55943  *  0b11..pull disabled
55944  */
55945 #define IOMUXD_ENET0_REFCLK_125M_25M_PULL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_PULL_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_PULL_MASK)
55946 #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_MASK (0x7FF80U)
55947 #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_SHIFT (7U)
55948 /*! ENET0_REFCLK_125M_25M_reserved_7_18 - reserved
55949  */
55950 #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_MASK)
55951 #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_MASK (0x380000U)
55952 #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT (19U)
55953 /*! WAKEUP_CTRL - wakeup control
55954  *  0b000..OFF
55955  *  0b001..RESAMPLE
55956  *  0b100..LOW
55957  *  0b111..HIGH
55958  *  0b110..RISE
55959  *  0b101..FALL
55960  */
55961 #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_MASK)
55962 #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_MASK (0x400000U)
55963 #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_SHIFT (22U)
55964 /*! WAKEUP_MASK - wakeup mask
55965  */
55966 #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_MASK)
55967 #define IOMUXD_ENET0_REFCLK_125M_25M_lp_config_MASK (0x1800000U)
55968 #define IOMUXD_ENET0_REFCLK_125M_25M_lp_config_SHIFT (23U)
55969 /*! lp_config - lower power configuration
55970  *  0b01..EARLY_ISO
55971  *  0b10..LATE_ISO
55972  *  0b11..LATCH
55973  *  0b00..PASS
55974  */
55975 #define IOMUXD_ENET0_REFCLK_125M_25M_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_lp_config_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_lp_config_MASK)
55976 #define IOMUXD_ENET0_REFCLK_125M_25M_sw_config_MASK (0x6000000U)
55977 #define IOMUXD_ENET0_REFCLK_125M_25M_sw_config_SHIFT (25U)
55978 /*! sw_config - output and input configuration
55979  *  0b01..OPEN_DRAIN
55980  *  0b10..OPEN_DRAIN_INPUT
55981  *  0b11..INOUT
55982  *  0b00..DEFAULT
55983  */
55984 #define IOMUXD_ENET0_REFCLK_125M_25M_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_sw_config_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_sw_config_MASK)
55985 #define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_MASK (0x38000000U)
55986 #define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_SHIFT (27U)
55987 /*! mux_mode - mux_mode
55988  *  0b000..CONN.ENET0.REFCLK_125M_25M
55989  *  0b001..CONN.ENET0.PPS
55990  *  0b010..CONN.ENET1.PPS
55991  *  0b100..LSIO.GPIO5.IO09
55992  */
55993 #define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_MASK)
55994 #define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_MASK (0x40000000U)
55995 #define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_SHIFT (30U)
55996 /*! update_pad_ctl - update lock for pad control
55997  */
55998 #define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_MASK)
55999 #define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_MASK (0x80000000U)
56000 #define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_SHIFT (31U)
56001 /*! update_mux_mode - update lock for mux control
56002  */
56003 #define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_MASK)
56004 /*! @} */
56005 
56006 /*! @name IOMUXD_GROUP_1_2 - na */
56007 /*! @{ */
56008 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_MASK (0x1U)
56009 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_SHIFT (0U)
56010 /*! ENET0_RGMII_TXD0 - wakeup from ENET0_RGMII_TXD0
56011  */
56012 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_MASK)
56013 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_MASK (0x2U)
56014 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_SHIFT (1U)
56015 /*! ENET0_RGMII_TXD1 - wakeup from ENET0_RGMII_TXD1
56016  */
56017 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_MASK)
56018 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_MASK (0x4U)
56019 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_SHIFT (2U)
56020 /*! ENET0_RGMII_TXD2 - wakeup from ENET0_RGMII_TXD2
56021  */
56022 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_MASK)
56023 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_MASK (0x8U)
56024 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_SHIFT (3U)
56025 /*! ENET0_RGMII_TXD3 - wakeup from ENET0_RGMII_TXD3
56026  */
56027 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_MASK)
56028 #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_MASK (0x10U)
56029 #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_SHIFT (4U)
56030 /*! iomuxd_group_1_2_reserved_4_4 - reserved
56031  */
56032 #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_MASK)
56033 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_MASK (0x20U)
56034 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_SHIFT (5U)
56035 /*! ENET0_RGMII_RXC - wakeup from ENET0_RGMII_RXC
56036  */
56037 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_MASK)
56038 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_MASK (0x40U)
56039 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_SHIFT (6U)
56040 /*! ENET0_RGMII_RX_CTL - wakeup from ENET0_RGMII_RX_CTL
56041  */
56042 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_MASK)
56043 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_MASK (0x80U)
56044 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_SHIFT (7U)
56045 /*! ENET0_RGMII_RXD0 - wakeup from ENET0_RGMII_RXD0
56046  */
56047 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_MASK)
56048 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_MASK (0x100U)
56049 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_SHIFT (8U)
56050 /*! ENET0_RGMII_RXD1 - wakeup from ENET0_RGMII_RXD1
56051  */
56052 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_MASK)
56053 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_MASK (0x200U)
56054 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_SHIFT (9U)
56055 /*! ENET0_RGMII_RXD2 - wakeup from ENET0_RGMII_RXD2
56056  */
56057 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_MASK)
56058 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_MASK (0x400U)
56059 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_SHIFT (10U)
56060 /*! ENET0_RGMII_RXD3 - wakeup from ENET0_RGMII_RXD3
56061  */
56062 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_MASK)
56063 #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_MASK (0x800U)
56064 #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_SHIFT (11U)
56065 /*! iomuxd_group_1_2_reserved_11_11 - reserved
56066  */
56067 #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_MASK)
56068 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_MASK (0x1000U)
56069 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_SHIFT (12U)
56070 /*! ENET0_REFCLK_125M_25M - wakeup from ENET0_REFCLK_125M_25M
56071  */
56072 #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_MASK)
56073 #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_MASK (0xFFFFE000U)
56074 #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_SHIFT (13U)
56075 /*! iomuxd_group_1_2_reserved_13_31 - reserved
56076  */
56077 #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_MASK)
56078 /*! @} */
56079 
56080 /*! @name ENET0_MDIO - ENET0_MDIO */
56081 /*! @{ */
56082 #define IOMUXD_ENET0_MDIO_PDRV_MASK              (0x1U)
56083 #define IOMUXD_ENET0_MDIO_PDRV_SHIFT             (0U)
56084 /*! PDRV - Drive
56085  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56086  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56087  */
56088 #define IOMUXD_ENET0_MDIO_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_PDRV_SHIFT)) & IOMUXD_ENET0_MDIO_PDRV_MASK)
56089 #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_MASK (0x1EU)
56090 #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_SHIFT (1U)
56091 /*! ENET0_MDIO_reserved_1_4 - reserved
56092  */
56093 #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_SHIFT)) & IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_MASK)
56094 #define IOMUXD_ENET0_MDIO_PULL_MASK              (0x60U)
56095 #define IOMUXD_ENET0_MDIO_PULL_SHIFT             (5U)
56096 /*! PULL - Pull Down Pull Up
56097  *  0b10..pull down
56098  *  0b01..pull up
56099  *  0b00..Prohibited
56100  *  0b11..pull disabled
56101  */
56102 #define IOMUXD_ENET0_MDIO_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_PULL_SHIFT)) & IOMUXD_ENET0_MDIO_PULL_MASK)
56103 #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_MASK (0x7FF80U)
56104 #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_SHIFT (7U)
56105 /*! ENET0_MDIO_reserved_7_18 - reserved
56106  */
56107 #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_SHIFT)) & IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_MASK)
56108 #define IOMUXD_ENET0_MDIO_WAKEUP_CTRL_MASK       (0x380000U)
56109 #define IOMUXD_ENET0_MDIO_WAKEUP_CTRL_SHIFT      (19U)
56110 /*! WAKEUP_CTRL - wakeup control
56111  *  0b000..OFF
56112  *  0b001..RESAMPLE
56113  *  0b100..LOW
56114  *  0b111..HIGH
56115  *  0b110..RISE
56116  *  0b101..FALL
56117  */
56118 #define IOMUXD_ENET0_MDIO_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_MDIO_WAKEUP_CTRL_MASK)
56119 #define IOMUXD_ENET0_MDIO_WAKEUP_MASK_MASK       (0x400000U)
56120 #define IOMUXD_ENET0_MDIO_WAKEUP_MASK_SHIFT      (22U)
56121 /*! WAKEUP_MASK - wakeup mask
56122  */
56123 #define IOMUXD_ENET0_MDIO_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_MDIO_WAKEUP_MASK_MASK)
56124 #define IOMUXD_ENET0_MDIO_lp_config_MASK         (0x1800000U)
56125 #define IOMUXD_ENET0_MDIO_lp_config_SHIFT        (23U)
56126 /*! lp_config - lower power configuration
56127  *  0b01..EARLY_ISO
56128  *  0b10..LATE_ISO
56129  *  0b11..LATCH
56130  *  0b00..PASS
56131  */
56132 #define IOMUXD_ENET0_MDIO_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_lp_config_SHIFT)) & IOMUXD_ENET0_MDIO_lp_config_MASK)
56133 #define IOMUXD_ENET0_MDIO_sw_config_MASK         (0x6000000U)
56134 #define IOMUXD_ENET0_MDIO_sw_config_SHIFT        (25U)
56135 /*! sw_config - output and input configuration
56136  *  0b01..OPEN_DRAIN
56137  *  0b10..OPEN_DRAIN_INPUT
56138  *  0b11..INOUT
56139  *  0b00..DEFAULT
56140  */
56141 #define IOMUXD_ENET0_MDIO_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_sw_config_SHIFT)) & IOMUXD_ENET0_MDIO_sw_config_MASK)
56142 #define IOMUXD_ENET0_MDIO_mux_mode_MASK          (0x38000000U)
56143 #define IOMUXD_ENET0_MDIO_mux_mode_SHIFT         (27U)
56144 /*! mux_mode - mux_mode
56145  *  0b000..CONN.ENET0.MDIO
56146  *  0b001..ADMA.I2C3.SDA
56147  *  0b010..CONN.ENET1.MDIO
56148  *  0b100..LSIO.GPIO5.IO10
56149  */
56150 #define IOMUXD_ENET0_MDIO_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_mux_mode_SHIFT)) & IOMUXD_ENET0_MDIO_mux_mode_MASK)
56151 #define IOMUXD_ENET0_MDIO_update_pad_ctl_MASK    (0x40000000U)
56152 #define IOMUXD_ENET0_MDIO_update_pad_ctl_SHIFT   (30U)
56153 /*! update_pad_ctl - update lock for pad control
56154  */
56155 #define IOMUXD_ENET0_MDIO_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_MDIO_update_pad_ctl_MASK)
56156 #define IOMUXD_ENET0_MDIO_update_mux_mode_MASK   (0x80000000U)
56157 #define IOMUXD_ENET0_MDIO_update_mux_mode_SHIFT  (31U)
56158 /*! update_mux_mode - update lock for mux control
56159  */
56160 #define IOMUXD_ENET0_MDIO_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_update_mux_mode_SHIFT)) & IOMUXD_ENET0_MDIO_update_mux_mode_MASK)
56161 /*! @} */
56162 
56163 /*! @name ENET0_MDC - ENET0_MDC */
56164 /*! @{ */
56165 #define IOMUXD_ENET0_MDC_PDRV_MASK               (0x1U)
56166 #define IOMUXD_ENET0_MDC_PDRV_SHIFT              (0U)
56167 /*! PDRV - Drive
56168  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56169  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56170  */
56171 #define IOMUXD_ENET0_MDC_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_PDRV_SHIFT)) & IOMUXD_ENET0_MDC_PDRV_MASK)
56172 #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_MASK (0x1EU)
56173 #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_SHIFT (1U)
56174 /*! ENET0_MDC_reserved_1_4 - reserved
56175  */
56176 #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_MASK)
56177 #define IOMUXD_ENET0_MDC_PULL_MASK               (0x60U)
56178 #define IOMUXD_ENET0_MDC_PULL_SHIFT              (5U)
56179 /*! PULL - Pull Down Pull Up
56180  *  0b10..pull down
56181  *  0b01..pull up
56182  *  0b00..Prohibited
56183  *  0b11..pull disabled
56184  */
56185 #define IOMUXD_ENET0_MDC_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_PULL_SHIFT)) & IOMUXD_ENET0_MDC_PULL_MASK)
56186 #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_MASK (0x7FF80U)
56187 #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_SHIFT (7U)
56188 /*! ENET0_MDC_reserved_7_18 - reserved
56189  */
56190 #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_MASK)
56191 #define IOMUXD_ENET0_MDC_WAKEUP_CTRL_MASK        (0x380000U)
56192 #define IOMUXD_ENET0_MDC_WAKEUP_CTRL_SHIFT       (19U)
56193 /*! WAKEUP_CTRL - wakeup control
56194  *  0b000..OFF
56195  *  0b001..RESAMPLE
56196  *  0b100..LOW
56197  *  0b111..HIGH
56198  *  0b110..RISE
56199  *  0b101..FALL
56200  */
56201 #define IOMUXD_ENET0_MDC_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_MDC_WAKEUP_CTRL_MASK)
56202 #define IOMUXD_ENET0_MDC_WAKEUP_MASK_MASK        (0x400000U)
56203 #define IOMUXD_ENET0_MDC_WAKEUP_MASK_SHIFT       (22U)
56204 /*! WAKEUP_MASK - wakeup mask
56205  */
56206 #define IOMUXD_ENET0_MDC_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_MDC_WAKEUP_MASK_MASK)
56207 #define IOMUXD_ENET0_MDC_lp_config_MASK          (0x1800000U)
56208 #define IOMUXD_ENET0_MDC_lp_config_SHIFT         (23U)
56209 /*! lp_config - lower power configuration
56210  *  0b01..EARLY_ISO
56211  *  0b10..LATE_ISO
56212  *  0b11..LATCH
56213  *  0b00..PASS
56214  */
56215 #define IOMUXD_ENET0_MDC_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_lp_config_SHIFT)) & IOMUXD_ENET0_MDC_lp_config_MASK)
56216 #define IOMUXD_ENET0_MDC_sw_config_MASK          (0x6000000U)
56217 #define IOMUXD_ENET0_MDC_sw_config_SHIFT         (25U)
56218 /*! sw_config - output and input configuration
56219  *  0b01..OPEN_DRAIN
56220  *  0b10..OPEN_DRAIN_INPUT
56221  *  0b11..INOUT
56222  *  0b00..DEFAULT
56223  */
56224 #define IOMUXD_ENET0_MDC_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_sw_config_SHIFT)) & IOMUXD_ENET0_MDC_sw_config_MASK)
56225 #define IOMUXD_ENET0_MDC_mux_mode_MASK           (0x38000000U)
56226 #define IOMUXD_ENET0_MDC_mux_mode_SHIFT          (27U)
56227 /*! mux_mode - mux_mode
56228  *  0b000..CONN.ENET0.MDC
56229  *  0b001..ADMA.I2C3.SCL
56230  *  0b010..CONN.ENET1.MDC
56231  *  0b100..LSIO.GPIO5.IO11
56232  */
56233 #define IOMUXD_ENET0_MDC_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_mux_mode_SHIFT)) & IOMUXD_ENET0_MDC_mux_mode_MASK)
56234 #define IOMUXD_ENET0_MDC_update_pad_ctl_MASK     (0x40000000U)
56235 #define IOMUXD_ENET0_MDC_update_pad_ctl_SHIFT    (30U)
56236 /*! update_pad_ctl - update lock for pad control
56237  */
56238 #define IOMUXD_ENET0_MDC_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_MDC_update_pad_ctl_MASK)
56239 #define IOMUXD_ENET0_MDC_update_mux_mode_MASK    (0x80000000U)
56240 #define IOMUXD_ENET0_MDC_update_mux_mode_SHIFT   (31U)
56241 /*! update_mux_mode - update lock for mux control
56242  */
56243 #define IOMUXD_ENET0_MDC_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_MDC_update_mux_mode_MASK)
56244 /*! @} */
56245 
56246 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT */
56247 /*! @{ */
56248 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_MASK (0x7U)
56249 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_SHIFT (0U)
56250 /*! COMP - COMP
56251  *  0b010..Fixed code mode
56252  *  0b100..High impedance mode
56253  *  0b110..Read mode
56254  *  0b000..Normal Mode
56255  *  0b001..Freeze Mode
56256  */
56257 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_MASK)
56258 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_MASK (0x8U)
56259 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_SHIFT (3U)
56260 /*! FASTFRZ_EN - FASTFRZ_EN
56261  *  0b1..FASTFRZ signal is driven by output of subsystem
56262  *  0b0..FASTFRZ signal is gated to 0
56263  */
56264 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_MASK)
56265 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_MASK (0x10U)
56266 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_SHIFT (4U)
56267 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4 - reserved
56268  */
56269 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_MASK)
56270 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_MASK (0x1E0U)
56271 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_SHIFT (5U)
56272 /*! RASRCP - RASRCP
56273  *  0b0101..Reset Value
56274  */
56275 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_MASK)
56276 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_MASK (0x1E00U)
56277 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_SHIFT (9U)
56278 /*! RASRCN - RASRCN
56279  *  0b1010..Reset Value
56280  */
56281 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_MASK)
56282 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_MASK (0x2000U)
56283 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_SHIFT (13U)
56284 /*! SELECT_NASRC - SELECT_NASRC
56285  *  0b1..NASRCN value
56286  *  0b0..NASRCP value
56287  */
56288 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_MASK)
56289 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_MASK (0x4000U)
56290 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_SHIFT (14U)
56291 /*! COMPOK - COMPOK
56292  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
56293  *  0b1..compensation cell in Normal mode and tracking PVT
56294  */
56295 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_MASK)
56296 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_MASK (0x78000U)
56297 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_SHIFT (15U)
56298 /*! READ_NASRC - READ_NASRC
56299  *  0b0000..READ Only
56300  */
56301 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_MASK)
56302 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_MASK (0x780000U)
56303 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_SHIFT (19U)
56304 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22 - reserved
56305  */
56306 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_MASK)
56307 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_MASK (0x1800000U)
56308 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_SHIFT (23U)
56309 /*! SLEEP - SLEEP
56310  *  0b11..Force into sleep mode
56311  *  0b00..NO
56312  *  0b01..EARLY
56313  *  0b10..LATE
56314  */
56315 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_MASK)
56316 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_MASK (0x3E000000U)
56317 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_SHIFT (25U)
56318 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29 - reserved
56319  */
56320 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_MASK)
56321 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_MASK (0x40000000U)
56322 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_SHIFT (30U)
56323 /*! update_pad_ctl - update lock for pad control
56324  */
56325 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_MASK)
56326 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_MASK (0x80000000U)
56327 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_SHIFT (31U)
56328 /*! update_mux_mode - update lock for mux control
56329  */
56330 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_MASK)
56331 /*! @} */
56332 
56333 /*! @name ESAI0_FSR - ESAI0_FSR */
56334 /*! @{ */
56335 #define IOMUXD_ESAI0_FSR_PDRV_MASK               (0x1U)
56336 #define IOMUXD_ESAI0_FSR_PDRV_SHIFT              (0U)
56337 /*! PDRV - Drive
56338  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56339  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56340  */
56341 #define IOMUXD_ESAI0_FSR_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_PDRV_SHIFT)) & IOMUXD_ESAI0_FSR_PDRV_MASK)
56342 #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_MASK (0x1EU)
56343 #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_SHIFT (1U)
56344 /*! ESAI0_FSR_reserved_1_4 - reserved
56345  */
56346 #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_MASK)
56347 #define IOMUXD_ESAI0_FSR_PULL_MASK               (0x60U)
56348 #define IOMUXD_ESAI0_FSR_PULL_SHIFT              (5U)
56349 /*! PULL - Pull Down Pull Up
56350  *  0b10..pull down
56351  *  0b01..pull up
56352  *  0b00..Prohibited
56353  *  0b11..pull disabled
56354  */
56355 #define IOMUXD_ESAI0_FSR_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_PULL_SHIFT)) & IOMUXD_ESAI0_FSR_PULL_MASK)
56356 #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_MASK (0x7FF80U)
56357 #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_SHIFT (7U)
56358 /*! ESAI0_FSR_reserved_7_18 - reserved
56359  */
56360 #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_MASK)
56361 #define IOMUXD_ESAI0_FSR_WAKEUP_CTRL_MASK        (0x380000U)
56362 #define IOMUXD_ESAI0_FSR_WAKEUP_CTRL_SHIFT       (19U)
56363 /*! WAKEUP_CTRL - wakeup control
56364  *  0b000..OFF
56365  *  0b001..RESAMPLE
56366  *  0b100..LOW
56367  *  0b111..HIGH
56368  *  0b110..RISE
56369  *  0b101..FALL
56370  */
56371 #define IOMUXD_ESAI0_FSR_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_FSR_WAKEUP_CTRL_MASK)
56372 #define IOMUXD_ESAI0_FSR_WAKEUP_MASK_MASK        (0x400000U)
56373 #define IOMUXD_ESAI0_FSR_WAKEUP_MASK_SHIFT       (22U)
56374 /*! WAKEUP_MASK - wakeup mask
56375  */
56376 #define IOMUXD_ESAI0_FSR_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_FSR_WAKEUP_MASK_MASK)
56377 #define IOMUXD_ESAI0_FSR_lp_config_MASK          (0x1800000U)
56378 #define IOMUXD_ESAI0_FSR_lp_config_SHIFT         (23U)
56379 /*! lp_config - lower power configuration
56380  *  0b01..EARLY_ISO
56381  *  0b10..LATE_ISO
56382  *  0b11..LATCH
56383  *  0b00..PASS
56384  */
56385 #define IOMUXD_ESAI0_FSR_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_lp_config_SHIFT)) & IOMUXD_ESAI0_FSR_lp_config_MASK)
56386 #define IOMUXD_ESAI0_FSR_sw_config_MASK          (0x6000000U)
56387 #define IOMUXD_ESAI0_FSR_sw_config_SHIFT         (25U)
56388 /*! sw_config - output and input configuration
56389  *  0b01..OPEN_DRAIN
56390  *  0b10..OPEN_DRAIN_INPUT
56391  *  0b11..INOUT
56392  *  0b00..DEFAULT
56393  */
56394 #define IOMUXD_ESAI0_FSR_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_sw_config_SHIFT)) & IOMUXD_ESAI0_FSR_sw_config_MASK)
56395 #define IOMUXD_ESAI0_FSR_mux_mode_MASK           (0x38000000U)
56396 #define IOMUXD_ESAI0_FSR_mux_mode_SHIFT          (27U)
56397 /*! mux_mode - mux_mode
56398  *  0b000..ADMA.ESAI0.FSR
56399  *  0b001..CONN.ENET1.RCLK50M_OUT
56400  *  0b010..ADMA.LCDIF.D00
56401  *  0b011..CONN.ENET1.RGMII_TXC
56402  *  0b100..CONN.ENET1.RCLK50M_IN
56403  */
56404 #define IOMUXD_ESAI0_FSR_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_mux_mode_SHIFT)) & IOMUXD_ESAI0_FSR_mux_mode_MASK)
56405 #define IOMUXD_ESAI0_FSR_update_pad_ctl_MASK     (0x40000000U)
56406 #define IOMUXD_ESAI0_FSR_update_pad_ctl_SHIFT    (30U)
56407 /*! update_pad_ctl - update lock for pad control
56408  */
56409 #define IOMUXD_ESAI0_FSR_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_FSR_update_pad_ctl_MASK)
56410 #define IOMUXD_ESAI0_FSR_update_mux_mode_MASK    (0x80000000U)
56411 #define IOMUXD_ESAI0_FSR_update_mux_mode_SHIFT   (31U)
56412 /*! update_mux_mode - update lock for mux control
56413  */
56414 #define IOMUXD_ESAI0_FSR_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_FSR_update_mux_mode_MASK)
56415 /*! @} */
56416 
56417 /*! @name ESAI0_FST - ESAI0_FST */
56418 /*! @{ */
56419 #define IOMUXD_ESAI0_FST_PDRV_MASK               (0x1U)
56420 #define IOMUXD_ESAI0_FST_PDRV_SHIFT              (0U)
56421 /*! PDRV - Drive
56422  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56423  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56424  */
56425 #define IOMUXD_ESAI0_FST_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_PDRV_SHIFT)) & IOMUXD_ESAI0_FST_PDRV_MASK)
56426 #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_MASK (0x1EU)
56427 #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_SHIFT (1U)
56428 /*! ESAI0_FST_reserved_1_4 - reserved
56429  */
56430 #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_MASK)
56431 #define IOMUXD_ESAI0_FST_PULL_MASK               (0x60U)
56432 #define IOMUXD_ESAI0_FST_PULL_SHIFT              (5U)
56433 /*! PULL - Pull Down Pull Up
56434  *  0b10..pull down
56435  *  0b01..pull up
56436  *  0b00..Prohibited
56437  *  0b11..pull disabled
56438  */
56439 #define IOMUXD_ESAI0_FST_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_PULL_SHIFT)) & IOMUXD_ESAI0_FST_PULL_MASK)
56440 #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_MASK (0x7FF80U)
56441 #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_SHIFT (7U)
56442 /*! ESAI0_FST_reserved_7_18 - reserved
56443  */
56444 #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_MASK)
56445 #define IOMUXD_ESAI0_FST_WAKEUP_CTRL_MASK        (0x380000U)
56446 #define IOMUXD_ESAI0_FST_WAKEUP_CTRL_SHIFT       (19U)
56447 /*! WAKEUP_CTRL - wakeup control
56448  *  0b000..OFF
56449  *  0b001..RESAMPLE
56450  *  0b100..LOW
56451  *  0b111..HIGH
56452  *  0b110..RISE
56453  *  0b101..FALL
56454  */
56455 #define IOMUXD_ESAI0_FST_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_FST_WAKEUP_CTRL_MASK)
56456 #define IOMUXD_ESAI0_FST_WAKEUP_MASK_MASK        (0x400000U)
56457 #define IOMUXD_ESAI0_FST_WAKEUP_MASK_SHIFT       (22U)
56458 /*! WAKEUP_MASK - wakeup mask
56459  */
56460 #define IOMUXD_ESAI0_FST_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_FST_WAKEUP_MASK_MASK)
56461 #define IOMUXD_ESAI0_FST_lp_config_MASK          (0x1800000U)
56462 #define IOMUXD_ESAI0_FST_lp_config_SHIFT         (23U)
56463 /*! lp_config - lower power configuration
56464  *  0b01..EARLY_ISO
56465  *  0b10..LATE_ISO
56466  *  0b11..LATCH
56467  *  0b00..PASS
56468  */
56469 #define IOMUXD_ESAI0_FST_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_lp_config_SHIFT)) & IOMUXD_ESAI0_FST_lp_config_MASK)
56470 #define IOMUXD_ESAI0_FST_sw_config_MASK          (0x6000000U)
56471 #define IOMUXD_ESAI0_FST_sw_config_SHIFT         (25U)
56472 /*! sw_config - output and input configuration
56473  *  0b01..OPEN_DRAIN
56474  *  0b10..OPEN_DRAIN_INPUT
56475  *  0b11..INOUT
56476  *  0b00..DEFAULT
56477  */
56478 #define IOMUXD_ESAI0_FST_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_sw_config_SHIFT)) & IOMUXD_ESAI0_FST_sw_config_MASK)
56479 #define IOMUXD_ESAI0_FST_mux_mode_MASK           (0x38000000U)
56480 #define IOMUXD_ESAI0_FST_mux_mode_SHIFT          (27U)
56481 /*! mux_mode - mux_mode
56482  *  0b000..ADMA.ESAI0.FST
56483  *  0b001..CONN.MLB.CLK
56484  *  0b010..ADMA.LCDIF.D01
56485  *  0b011..CONN.ENET1.RGMII_TXD2
56486  *  0b100..LSIO.GPIO0.IO01
56487  */
56488 #define IOMUXD_ESAI0_FST_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_mux_mode_SHIFT)) & IOMUXD_ESAI0_FST_mux_mode_MASK)
56489 #define IOMUXD_ESAI0_FST_update_pad_ctl_MASK     (0x40000000U)
56490 #define IOMUXD_ESAI0_FST_update_pad_ctl_SHIFT    (30U)
56491 /*! update_pad_ctl - update lock for pad control
56492  */
56493 #define IOMUXD_ESAI0_FST_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_FST_update_pad_ctl_MASK)
56494 #define IOMUXD_ESAI0_FST_update_mux_mode_MASK    (0x80000000U)
56495 #define IOMUXD_ESAI0_FST_update_mux_mode_SHIFT   (31U)
56496 /*! update_mux_mode - update lock for mux control
56497  */
56498 #define IOMUXD_ESAI0_FST_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_FST_update_mux_mode_MASK)
56499 /*! @} */
56500 
56501 /*! @name ESAI0_SCKR - ESAI0_SCKR */
56502 /*! @{ */
56503 #define IOMUXD_ESAI0_SCKR_PDRV_MASK              (0x1U)
56504 #define IOMUXD_ESAI0_SCKR_PDRV_SHIFT             (0U)
56505 /*! PDRV - Drive
56506  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56507  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56508  */
56509 #define IOMUXD_ESAI0_SCKR_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_PDRV_SHIFT)) & IOMUXD_ESAI0_SCKR_PDRV_MASK)
56510 #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_MASK (0x1EU)
56511 #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_SHIFT (1U)
56512 /*! ESAI0_SCKR_reserved_1_4 - reserved
56513  */
56514 #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_MASK)
56515 #define IOMUXD_ESAI0_SCKR_PULL_MASK              (0x60U)
56516 #define IOMUXD_ESAI0_SCKR_PULL_SHIFT             (5U)
56517 /*! PULL - Pull Down Pull Up
56518  *  0b10..pull down
56519  *  0b01..pull up
56520  *  0b00..Prohibited
56521  *  0b11..pull disabled
56522  */
56523 #define IOMUXD_ESAI0_SCKR_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_PULL_SHIFT)) & IOMUXD_ESAI0_SCKR_PULL_MASK)
56524 #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_MASK (0x7FF80U)
56525 #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_SHIFT (7U)
56526 /*! ESAI0_SCKR_reserved_7_18 - reserved
56527  */
56528 #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_MASK)
56529 #define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_MASK       (0x380000U)
56530 #define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_SHIFT      (19U)
56531 /*! WAKEUP_CTRL - wakeup control
56532  *  0b000..OFF
56533  *  0b001..RESAMPLE
56534  *  0b100..LOW
56535  *  0b111..HIGH
56536  *  0b110..RISE
56537  *  0b101..FALL
56538  */
56539 #define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_MASK)
56540 #define IOMUXD_ESAI0_SCKR_WAKEUP_MASK_MASK       (0x400000U)
56541 #define IOMUXD_ESAI0_SCKR_WAKEUP_MASK_SHIFT      (22U)
56542 /*! WAKEUP_MASK - wakeup mask
56543  */
56544 #define IOMUXD_ESAI0_SCKR_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_SCKR_WAKEUP_MASK_MASK)
56545 #define IOMUXD_ESAI0_SCKR_lp_config_MASK         (0x1800000U)
56546 #define IOMUXD_ESAI0_SCKR_lp_config_SHIFT        (23U)
56547 /*! lp_config - lower power configuration
56548  *  0b01..EARLY_ISO
56549  *  0b10..LATE_ISO
56550  *  0b11..LATCH
56551  *  0b00..PASS
56552  */
56553 #define IOMUXD_ESAI0_SCKR_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_lp_config_SHIFT)) & IOMUXD_ESAI0_SCKR_lp_config_MASK)
56554 #define IOMUXD_ESAI0_SCKR_sw_config_MASK         (0x6000000U)
56555 #define IOMUXD_ESAI0_SCKR_sw_config_SHIFT        (25U)
56556 /*! sw_config - output and input configuration
56557  *  0b01..OPEN_DRAIN
56558  *  0b10..OPEN_DRAIN_INPUT
56559  *  0b11..INOUT
56560  *  0b00..DEFAULT
56561  */
56562 #define IOMUXD_ESAI0_SCKR_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_sw_config_SHIFT)) & IOMUXD_ESAI0_SCKR_sw_config_MASK)
56563 #define IOMUXD_ESAI0_SCKR_mux_mode_MASK          (0x38000000U)
56564 #define IOMUXD_ESAI0_SCKR_mux_mode_SHIFT         (27U)
56565 /*! mux_mode - mux_mode
56566  *  0b000..ADMA.ESAI0.SCKR
56567  *  0b010..ADMA.LCDIF.D02
56568  *  0b011..CONN.ENET1.RGMII_TX_CTL
56569  *  0b100..LSIO.GPIO0.IO02
56570  */
56571 #define IOMUXD_ESAI0_SCKR_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKR_mux_mode_MASK)
56572 #define IOMUXD_ESAI0_SCKR_update_pad_ctl_MASK    (0x40000000U)
56573 #define IOMUXD_ESAI0_SCKR_update_pad_ctl_SHIFT   (30U)
56574 /*! update_pad_ctl - update lock for pad control
56575  */
56576 #define IOMUXD_ESAI0_SCKR_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_SCKR_update_pad_ctl_MASK)
56577 #define IOMUXD_ESAI0_SCKR_update_mux_mode_MASK   (0x80000000U)
56578 #define IOMUXD_ESAI0_SCKR_update_mux_mode_SHIFT  (31U)
56579 /*! update_mux_mode - update lock for mux control
56580  */
56581 #define IOMUXD_ESAI0_SCKR_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKR_update_mux_mode_MASK)
56582 /*! @} */
56583 
56584 /*! @name ESAI0_SCKT - ESAI0_SCKT */
56585 /*! @{ */
56586 #define IOMUXD_ESAI0_SCKT_PDRV_MASK              (0x1U)
56587 #define IOMUXD_ESAI0_SCKT_PDRV_SHIFT             (0U)
56588 /*! PDRV - Drive
56589  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56590  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56591  */
56592 #define IOMUXD_ESAI0_SCKT_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_PDRV_SHIFT)) & IOMUXD_ESAI0_SCKT_PDRV_MASK)
56593 #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_MASK (0x1EU)
56594 #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_SHIFT (1U)
56595 /*! ESAI0_SCKT_reserved_1_4 - reserved
56596  */
56597 #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_MASK)
56598 #define IOMUXD_ESAI0_SCKT_PULL_MASK              (0x60U)
56599 #define IOMUXD_ESAI0_SCKT_PULL_SHIFT             (5U)
56600 /*! PULL - Pull Down Pull Up
56601  *  0b10..pull down
56602  *  0b01..pull up
56603  *  0b00..Prohibited
56604  *  0b11..pull disabled
56605  */
56606 #define IOMUXD_ESAI0_SCKT_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_PULL_SHIFT)) & IOMUXD_ESAI0_SCKT_PULL_MASK)
56607 #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_MASK (0x7FF80U)
56608 #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_SHIFT (7U)
56609 /*! ESAI0_SCKT_reserved_7_18 - reserved
56610  */
56611 #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_MASK)
56612 #define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_MASK       (0x380000U)
56613 #define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_SHIFT      (19U)
56614 /*! WAKEUP_CTRL - wakeup control
56615  *  0b000..OFF
56616  *  0b001..RESAMPLE
56617  *  0b100..LOW
56618  *  0b111..HIGH
56619  *  0b110..RISE
56620  *  0b101..FALL
56621  */
56622 #define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_MASK)
56623 #define IOMUXD_ESAI0_SCKT_WAKEUP_MASK_MASK       (0x400000U)
56624 #define IOMUXD_ESAI0_SCKT_WAKEUP_MASK_SHIFT      (22U)
56625 /*! WAKEUP_MASK - wakeup mask
56626  */
56627 #define IOMUXD_ESAI0_SCKT_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_SCKT_WAKEUP_MASK_MASK)
56628 #define IOMUXD_ESAI0_SCKT_lp_config_MASK         (0x1800000U)
56629 #define IOMUXD_ESAI0_SCKT_lp_config_SHIFT        (23U)
56630 /*! lp_config - lower power configuration
56631  *  0b01..EARLY_ISO
56632  *  0b10..LATE_ISO
56633  *  0b11..LATCH
56634  *  0b00..PASS
56635  */
56636 #define IOMUXD_ESAI0_SCKT_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_lp_config_SHIFT)) & IOMUXD_ESAI0_SCKT_lp_config_MASK)
56637 #define IOMUXD_ESAI0_SCKT_sw_config_MASK         (0x6000000U)
56638 #define IOMUXD_ESAI0_SCKT_sw_config_SHIFT        (25U)
56639 /*! sw_config - output and input configuration
56640  *  0b01..OPEN_DRAIN
56641  *  0b10..OPEN_DRAIN_INPUT
56642  *  0b11..INOUT
56643  *  0b00..DEFAULT
56644  */
56645 #define IOMUXD_ESAI0_SCKT_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_sw_config_SHIFT)) & IOMUXD_ESAI0_SCKT_sw_config_MASK)
56646 #define IOMUXD_ESAI0_SCKT_mux_mode_MASK          (0x38000000U)
56647 #define IOMUXD_ESAI0_SCKT_mux_mode_SHIFT         (27U)
56648 /*! mux_mode - mux_mode
56649  *  0b000..ADMA.ESAI0.SCKT
56650  *  0b001..CONN.MLB.SIG
56651  *  0b010..ADMA.LCDIF.D03
56652  *  0b011..CONN.ENET1.RGMII_TXD3
56653  *  0b100..LSIO.GPIO0.IO03
56654  */
56655 #define IOMUXD_ESAI0_SCKT_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKT_mux_mode_MASK)
56656 #define IOMUXD_ESAI0_SCKT_update_pad_ctl_MASK    (0x40000000U)
56657 #define IOMUXD_ESAI0_SCKT_update_pad_ctl_SHIFT   (30U)
56658 /*! update_pad_ctl - update lock for pad control
56659  */
56660 #define IOMUXD_ESAI0_SCKT_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_SCKT_update_pad_ctl_MASK)
56661 #define IOMUXD_ESAI0_SCKT_update_mux_mode_MASK   (0x80000000U)
56662 #define IOMUXD_ESAI0_SCKT_update_mux_mode_SHIFT  (31U)
56663 /*! update_mux_mode - update lock for mux control
56664  */
56665 #define IOMUXD_ESAI0_SCKT_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKT_update_mux_mode_MASK)
56666 /*! @} */
56667 
56668 /*! @name ESAI0_TX0 - ESAI0_TX0 */
56669 /*! @{ */
56670 #define IOMUXD_ESAI0_TX0_PDRV_MASK               (0x1U)
56671 #define IOMUXD_ESAI0_TX0_PDRV_SHIFT              (0U)
56672 /*! PDRV - Drive
56673  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56674  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56675  */
56676 #define IOMUXD_ESAI0_TX0_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_PDRV_SHIFT)) & IOMUXD_ESAI0_TX0_PDRV_MASK)
56677 #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_MASK (0x1EU)
56678 #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_SHIFT (1U)
56679 /*! ESAI0_TX0_reserved_1_4 - reserved
56680  */
56681 #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_MASK)
56682 #define IOMUXD_ESAI0_TX0_PULL_MASK               (0x60U)
56683 #define IOMUXD_ESAI0_TX0_PULL_SHIFT              (5U)
56684 /*! PULL - Pull Down Pull Up
56685  *  0b10..pull down
56686  *  0b01..pull up
56687  *  0b00..Prohibited
56688  *  0b11..pull disabled
56689  */
56690 #define IOMUXD_ESAI0_TX0_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_PULL_SHIFT)) & IOMUXD_ESAI0_TX0_PULL_MASK)
56691 #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_MASK (0x7FF80U)
56692 #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_SHIFT (7U)
56693 /*! ESAI0_TX0_reserved_7_18 - reserved
56694  */
56695 #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_MASK)
56696 #define IOMUXD_ESAI0_TX0_WAKEUP_CTRL_MASK        (0x380000U)
56697 #define IOMUXD_ESAI0_TX0_WAKEUP_CTRL_SHIFT       (19U)
56698 /*! WAKEUP_CTRL - wakeup control
56699  *  0b000..OFF
56700  *  0b001..RESAMPLE
56701  *  0b100..LOW
56702  *  0b111..HIGH
56703  *  0b110..RISE
56704  *  0b101..FALL
56705  */
56706 #define IOMUXD_ESAI0_TX0_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX0_WAKEUP_CTRL_MASK)
56707 #define IOMUXD_ESAI0_TX0_WAKEUP_MASK_MASK        (0x400000U)
56708 #define IOMUXD_ESAI0_TX0_WAKEUP_MASK_SHIFT       (22U)
56709 /*! WAKEUP_MASK - wakeup mask
56710  */
56711 #define IOMUXD_ESAI0_TX0_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX0_WAKEUP_MASK_MASK)
56712 #define IOMUXD_ESAI0_TX0_lp_config_MASK          (0x1800000U)
56713 #define IOMUXD_ESAI0_TX0_lp_config_SHIFT         (23U)
56714 /*! lp_config - lower power configuration
56715  *  0b01..EARLY_ISO
56716  *  0b10..LATE_ISO
56717  *  0b11..LATCH
56718  *  0b00..PASS
56719  */
56720 #define IOMUXD_ESAI0_TX0_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_lp_config_SHIFT)) & IOMUXD_ESAI0_TX0_lp_config_MASK)
56721 #define IOMUXD_ESAI0_TX0_sw_config_MASK          (0x6000000U)
56722 #define IOMUXD_ESAI0_TX0_sw_config_SHIFT         (25U)
56723 /*! sw_config - output and input configuration
56724  *  0b01..OPEN_DRAIN
56725  *  0b10..OPEN_DRAIN_INPUT
56726  *  0b11..INOUT
56727  *  0b00..DEFAULT
56728  */
56729 #define IOMUXD_ESAI0_TX0_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_sw_config_SHIFT)) & IOMUXD_ESAI0_TX0_sw_config_MASK)
56730 #define IOMUXD_ESAI0_TX0_mux_mode_MASK           (0x38000000U)
56731 #define IOMUXD_ESAI0_TX0_mux_mode_SHIFT          (27U)
56732 /*! mux_mode - mux_mode
56733  *  0b000..ADMA.ESAI0.TX0
56734  *  0b001..CONN.MLB.DATA
56735  *  0b010..ADMA.LCDIF.D04
56736  *  0b011..CONN.ENET1.RGMII_RXC
56737  *  0b100..LSIO.GPIO0.IO04
56738  */
56739 #define IOMUXD_ESAI0_TX0_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX0_mux_mode_MASK)
56740 #define IOMUXD_ESAI0_TX0_update_pad_ctl_MASK     (0x40000000U)
56741 #define IOMUXD_ESAI0_TX0_update_pad_ctl_SHIFT    (30U)
56742 /*! update_pad_ctl - update lock for pad control
56743  */
56744 #define IOMUXD_ESAI0_TX0_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX0_update_pad_ctl_MASK)
56745 #define IOMUXD_ESAI0_TX0_update_mux_mode_MASK    (0x80000000U)
56746 #define IOMUXD_ESAI0_TX0_update_mux_mode_SHIFT   (31U)
56747 /*! update_mux_mode - update lock for mux control
56748  */
56749 #define IOMUXD_ESAI0_TX0_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX0_update_mux_mode_MASK)
56750 /*! @} */
56751 
56752 /*! @name ESAI0_TX1 - ESAI0_TX1 */
56753 /*! @{ */
56754 #define IOMUXD_ESAI0_TX1_PDRV_MASK               (0x1U)
56755 #define IOMUXD_ESAI0_TX1_PDRV_SHIFT              (0U)
56756 /*! PDRV - Drive
56757  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56758  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56759  */
56760 #define IOMUXD_ESAI0_TX1_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_PDRV_SHIFT)) & IOMUXD_ESAI0_TX1_PDRV_MASK)
56761 #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_MASK (0x1EU)
56762 #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_SHIFT (1U)
56763 /*! ESAI0_TX1_reserved_1_4 - reserved
56764  */
56765 #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_MASK)
56766 #define IOMUXD_ESAI0_TX1_PULL_MASK               (0x60U)
56767 #define IOMUXD_ESAI0_TX1_PULL_SHIFT              (5U)
56768 /*! PULL - Pull Down Pull Up
56769  *  0b10..pull down
56770  *  0b01..pull up
56771  *  0b00..Prohibited
56772  *  0b11..pull disabled
56773  */
56774 #define IOMUXD_ESAI0_TX1_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_PULL_SHIFT)) & IOMUXD_ESAI0_TX1_PULL_MASK)
56775 #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_MASK (0x7FF80U)
56776 #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_SHIFT (7U)
56777 /*! ESAI0_TX1_reserved_7_18 - reserved
56778  */
56779 #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_MASK)
56780 #define IOMUXD_ESAI0_TX1_WAKEUP_CTRL_MASK        (0x380000U)
56781 #define IOMUXD_ESAI0_TX1_WAKEUP_CTRL_SHIFT       (19U)
56782 /*! WAKEUP_CTRL - wakeup control
56783  *  0b000..OFF
56784  *  0b001..RESAMPLE
56785  *  0b100..LOW
56786  *  0b111..HIGH
56787  *  0b110..RISE
56788  *  0b101..FALL
56789  */
56790 #define IOMUXD_ESAI0_TX1_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX1_WAKEUP_CTRL_MASK)
56791 #define IOMUXD_ESAI0_TX1_WAKEUP_MASK_MASK        (0x400000U)
56792 #define IOMUXD_ESAI0_TX1_WAKEUP_MASK_SHIFT       (22U)
56793 /*! WAKEUP_MASK - wakeup mask
56794  */
56795 #define IOMUXD_ESAI0_TX1_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX1_WAKEUP_MASK_MASK)
56796 #define IOMUXD_ESAI0_TX1_lp_config_MASK          (0x1800000U)
56797 #define IOMUXD_ESAI0_TX1_lp_config_SHIFT         (23U)
56798 /*! lp_config - lower power configuration
56799  *  0b01..EARLY_ISO
56800  *  0b10..LATE_ISO
56801  *  0b11..LATCH
56802  *  0b00..PASS
56803  */
56804 #define IOMUXD_ESAI0_TX1_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_lp_config_SHIFT)) & IOMUXD_ESAI0_TX1_lp_config_MASK)
56805 #define IOMUXD_ESAI0_TX1_sw_config_MASK          (0x6000000U)
56806 #define IOMUXD_ESAI0_TX1_sw_config_SHIFT         (25U)
56807 /*! sw_config - output and input configuration
56808  *  0b01..OPEN_DRAIN
56809  *  0b10..OPEN_DRAIN_INPUT
56810  *  0b11..INOUT
56811  *  0b00..DEFAULT
56812  */
56813 #define IOMUXD_ESAI0_TX1_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_sw_config_SHIFT)) & IOMUXD_ESAI0_TX1_sw_config_MASK)
56814 #define IOMUXD_ESAI0_TX1_mux_mode_MASK           (0x38000000U)
56815 #define IOMUXD_ESAI0_TX1_mux_mode_SHIFT          (27U)
56816 /*! mux_mode - mux_mode
56817  *  0b000..ADMA.ESAI0.TX1
56818  *  0b010..ADMA.LCDIF.D05
56819  *  0b011..CONN.ENET1.RGMII_RXD3
56820  *  0b100..LSIO.GPIO0.IO05
56821  */
56822 #define IOMUXD_ESAI0_TX1_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX1_mux_mode_MASK)
56823 #define IOMUXD_ESAI0_TX1_update_pad_ctl_MASK     (0x40000000U)
56824 #define IOMUXD_ESAI0_TX1_update_pad_ctl_SHIFT    (30U)
56825 /*! update_pad_ctl - update lock for pad control
56826  */
56827 #define IOMUXD_ESAI0_TX1_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX1_update_pad_ctl_MASK)
56828 #define IOMUXD_ESAI0_TX1_update_mux_mode_MASK    (0x80000000U)
56829 #define IOMUXD_ESAI0_TX1_update_mux_mode_SHIFT   (31U)
56830 /*! update_mux_mode - update lock for mux control
56831  */
56832 #define IOMUXD_ESAI0_TX1_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX1_update_mux_mode_MASK)
56833 /*! @} */
56834 
56835 /*! @name ESAI0_TX2_RX3 - ESAI0_TX2_RX3 */
56836 /*! @{ */
56837 #define IOMUXD_ESAI0_TX2_RX3_PDRV_MASK           (0x1U)
56838 #define IOMUXD_ESAI0_TX2_RX3_PDRV_SHIFT          (0U)
56839 /*! PDRV - Drive
56840  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56841  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56842  */
56843 #define IOMUXD_ESAI0_TX2_RX3_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_PDRV_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_PDRV_MASK)
56844 #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_MASK (0x1EU)
56845 #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_SHIFT (1U)
56846 /*! ESAI0_TX2_RX3_reserved_1_4 - reserved
56847  */
56848 #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_MASK)
56849 #define IOMUXD_ESAI0_TX2_RX3_PULL_MASK           (0x60U)
56850 #define IOMUXD_ESAI0_TX2_RX3_PULL_SHIFT          (5U)
56851 /*! PULL - Pull Down Pull Up
56852  *  0b10..pull down
56853  *  0b01..pull up
56854  *  0b00..Prohibited
56855  *  0b11..pull disabled
56856  */
56857 #define IOMUXD_ESAI0_TX2_RX3_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_PULL_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_PULL_MASK)
56858 #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_MASK (0x7FF80U)
56859 #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_SHIFT (7U)
56860 /*! ESAI0_TX2_RX3_reserved_7_18 - reserved
56861  */
56862 #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_MASK)
56863 #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_MASK    (0x380000U)
56864 #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_SHIFT   (19U)
56865 /*! WAKEUP_CTRL - wakeup control
56866  *  0b000..OFF
56867  *  0b001..RESAMPLE
56868  *  0b100..LOW
56869  *  0b111..HIGH
56870  *  0b110..RISE
56871  *  0b101..FALL
56872  */
56873 #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_MASK)
56874 #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_MASK    (0x400000U)
56875 #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_SHIFT   (22U)
56876 /*! WAKEUP_MASK - wakeup mask
56877  */
56878 #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_MASK)
56879 #define IOMUXD_ESAI0_TX2_RX3_lp_config_MASK      (0x1800000U)
56880 #define IOMUXD_ESAI0_TX2_RX3_lp_config_SHIFT     (23U)
56881 /*! lp_config - lower power configuration
56882  *  0b01..EARLY_ISO
56883  *  0b10..LATE_ISO
56884  *  0b11..LATCH
56885  *  0b00..PASS
56886  */
56887 #define IOMUXD_ESAI0_TX2_RX3_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_lp_config_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_lp_config_MASK)
56888 #define IOMUXD_ESAI0_TX2_RX3_sw_config_MASK      (0x6000000U)
56889 #define IOMUXD_ESAI0_TX2_RX3_sw_config_SHIFT     (25U)
56890 /*! sw_config - output and input configuration
56891  *  0b01..OPEN_DRAIN
56892  *  0b10..OPEN_DRAIN_INPUT
56893  *  0b11..INOUT
56894  *  0b00..DEFAULT
56895  */
56896 #define IOMUXD_ESAI0_TX2_RX3_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_sw_config_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_sw_config_MASK)
56897 #define IOMUXD_ESAI0_TX2_RX3_mux_mode_MASK       (0x38000000U)
56898 #define IOMUXD_ESAI0_TX2_RX3_mux_mode_SHIFT      (27U)
56899 /*! mux_mode - mux_mode
56900  *  0b000..ADMA.ESAI0.TX2_RX3
56901  *  0b001..CONN.ENET1.RMII_RX_ER
56902  *  0b010..ADMA.LCDIF.D06
56903  *  0b011..CONN.ENET1.RGMII_RXD2
56904  *  0b100..LSIO.GPIO0.IO06
56905  */
56906 #define IOMUXD_ESAI0_TX2_RX3_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_mux_mode_MASK)
56907 #define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_MASK (0x40000000U)
56908 #define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_SHIFT (30U)
56909 /*! update_pad_ctl - update lock for pad control
56910  */
56911 #define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_MASK)
56912 #define IOMUXD_ESAI0_TX2_RX3_update_mux_mode_MASK (0x80000000U)
56913 #define IOMUXD_ESAI0_TX2_RX3_update_mux_mode_SHIFT (31U)
56914 /*! update_mux_mode - update lock for mux control
56915  */
56916 #define IOMUXD_ESAI0_TX2_RX3_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_update_mux_mode_MASK)
56917 /*! @} */
56918 
56919 /*! @name ESAI0_TX3_RX2 - ESAI0_TX3_RX2 */
56920 /*! @{ */
56921 #define IOMUXD_ESAI0_TX3_RX2_PDRV_MASK           (0x1U)
56922 #define IOMUXD_ESAI0_TX3_RX2_PDRV_SHIFT          (0U)
56923 /*! PDRV - Drive
56924  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56925  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56926  */
56927 #define IOMUXD_ESAI0_TX3_RX2_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_PDRV_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_PDRV_MASK)
56928 #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_MASK (0x1EU)
56929 #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_SHIFT (1U)
56930 /*! ESAI0_TX3_RX2_reserved_1_4 - reserved
56931  */
56932 #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_MASK)
56933 #define IOMUXD_ESAI0_TX3_RX2_PULL_MASK           (0x60U)
56934 #define IOMUXD_ESAI0_TX3_RX2_PULL_SHIFT          (5U)
56935 /*! PULL - Pull Down Pull Up
56936  *  0b10..pull down
56937  *  0b01..pull up
56938  *  0b00..Prohibited
56939  *  0b11..pull disabled
56940  */
56941 #define IOMUXD_ESAI0_TX3_RX2_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_PULL_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_PULL_MASK)
56942 #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_MASK (0x7FF80U)
56943 #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_SHIFT (7U)
56944 /*! ESAI0_TX3_RX2_reserved_7_18 - reserved
56945  */
56946 #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_MASK)
56947 #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_MASK    (0x380000U)
56948 #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_SHIFT   (19U)
56949 /*! WAKEUP_CTRL - wakeup control
56950  *  0b000..OFF
56951  *  0b001..RESAMPLE
56952  *  0b100..LOW
56953  *  0b111..HIGH
56954  *  0b110..RISE
56955  *  0b101..FALL
56956  */
56957 #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_MASK)
56958 #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_MASK    (0x400000U)
56959 #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_SHIFT   (22U)
56960 /*! WAKEUP_MASK - wakeup mask
56961  */
56962 #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_MASK)
56963 #define IOMUXD_ESAI0_TX3_RX2_lp_config_MASK      (0x1800000U)
56964 #define IOMUXD_ESAI0_TX3_RX2_lp_config_SHIFT     (23U)
56965 /*! lp_config - lower power configuration
56966  *  0b01..EARLY_ISO
56967  *  0b10..LATE_ISO
56968  *  0b11..LATCH
56969  *  0b00..PASS
56970  */
56971 #define IOMUXD_ESAI0_TX3_RX2_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_lp_config_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_lp_config_MASK)
56972 #define IOMUXD_ESAI0_TX3_RX2_sw_config_MASK      (0x6000000U)
56973 #define IOMUXD_ESAI0_TX3_RX2_sw_config_SHIFT     (25U)
56974 /*! sw_config - output and input configuration
56975  *  0b01..OPEN_DRAIN
56976  *  0b10..OPEN_DRAIN_INPUT
56977  *  0b11..INOUT
56978  *  0b00..DEFAULT
56979  */
56980 #define IOMUXD_ESAI0_TX3_RX2_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_sw_config_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_sw_config_MASK)
56981 #define IOMUXD_ESAI0_TX3_RX2_mux_mode_MASK       (0x38000000U)
56982 #define IOMUXD_ESAI0_TX3_RX2_mux_mode_SHIFT      (27U)
56983 /*! mux_mode - mux_mode
56984  *  0b000..ADMA.ESAI0.TX3_RX2
56985  *  0b010..ADMA.LCDIF.D07
56986  *  0b011..CONN.ENET1.RGMII_RXD1
56987  *  0b100..LSIO.GPIO0.IO07
56988  */
56989 #define IOMUXD_ESAI0_TX3_RX2_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_mux_mode_MASK)
56990 #define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_MASK (0x40000000U)
56991 #define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_SHIFT (30U)
56992 /*! update_pad_ctl - update lock for pad control
56993  */
56994 #define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_MASK)
56995 #define IOMUXD_ESAI0_TX3_RX2_update_mux_mode_MASK (0x80000000U)
56996 #define IOMUXD_ESAI0_TX3_RX2_update_mux_mode_SHIFT (31U)
56997 /*! update_mux_mode - update lock for mux control
56998  */
56999 #define IOMUXD_ESAI0_TX3_RX2_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_update_mux_mode_MASK)
57000 /*! @} */
57001 
57002 /*! @name ESAI0_TX4_RX1 - ESAI0_TX4_RX1 */
57003 /*! @{ */
57004 #define IOMUXD_ESAI0_TX4_RX1_PDRV_MASK           (0x1U)
57005 #define IOMUXD_ESAI0_TX4_RX1_PDRV_SHIFT          (0U)
57006 /*! PDRV - Drive
57007  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57008  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57009  */
57010 #define IOMUXD_ESAI0_TX4_RX1_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_PDRV_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_PDRV_MASK)
57011 #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_MASK (0x1EU)
57012 #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_SHIFT (1U)
57013 /*! ESAI0_TX4_RX1_reserved_1_4 - reserved
57014  */
57015 #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_MASK)
57016 #define IOMUXD_ESAI0_TX4_RX1_PULL_MASK           (0x60U)
57017 #define IOMUXD_ESAI0_TX4_RX1_PULL_SHIFT          (5U)
57018 /*! PULL - Pull Down Pull Up
57019  *  0b10..pull down
57020  *  0b01..pull up
57021  *  0b00..Prohibited
57022  *  0b11..pull disabled
57023  */
57024 #define IOMUXD_ESAI0_TX4_RX1_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_PULL_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_PULL_MASK)
57025 #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_MASK (0x7FF80U)
57026 #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_SHIFT (7U)
57027 /*! ESAI0_TX4_RX1_reserved_7_18 - reserved
57028  */
57029 #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_MASK)
57030 #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_MASK    (0x380000U)
57031 #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_SHIFT   (19U)
57032 /*! WAKEUP_CTRL - wakeup control
57033  *  0b000..OFF
57034  *  0b001..RESAMPLE
57035  *  0b100..LOW
57036  *  0b111..HIGH
57037  *  0b110..RISE
57038  *  0b101..FALL
57039  */
57040 #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_MASK)
57041 #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_MASK    (0x400000U)
57042 #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_SHIFT   (22U)
57043 /*! WAKEUP_MASK - wakeup mask
57044  */
57045 #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_MASK)
57046 #define IOMUXD_ESAI0_TX4_RX1_lp_config_MASK      (0x1800000U)
57047 #define IOMUXD_ESAI0_TX4_RX1_lp_config_SHIFT     (23U)
57048 /*! lp_config - lower power configuration
57049  *  0b01..EARLY_ISO
57050  *  0b10..LATE_ISO
57051  *  0b11..LATCH
57052  *  0b00..PASS
57053  */
57054 #define IOMUXD_ESAI0_TX4_RX1_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_lp_config_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_lp_config_MASK)
57055 #define IOMUXD_ESAI0_TX4_RX1_sw_config_MASK      (0x6000000U)
57056 #define IOMUXD_ESAI0_TX4_RX1_sw_config_SHIFT     (25U)
57057 /*! sw_config - output and input configuration
57058  *  0b01..OPEN_DRAIN
57059  *  0b10..OPEN_DRAIN_INPUT
57060  *  0b11..INOUT
57061  *  0b00..DEFAULT
57062  */
57063 #define IOMUXD_ESAI0_TX4_RX1_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_sw_config_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_sw_config_MASK)
57064 #define IOMUXD_ESAI0_TX4_RX1_mux_mode_MASK       (0x38000000U)
57065 #define IOMUXD_ESAI0_TX4_RX1_mux_mode_SHIFT      (27U)
57066 /*! mux_mode - mux_mode
57067  *  0b000..ADMA.ESAI0.TX4_RX1
57068  *  0b010..ADMA.LCDIF.D08
57069  *  0b011..CONN.ENET1.RGMII_TXD0
57070  *  0b100..LSIO.GPIO0.IO08
57071  */
57072 #define IOMUXD_ESAI0_TX4_RX1_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_mux_mode_MASK)
57073 #define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_MASK (0x40000000U)
57074 #define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_SHIFT (30U)
57075 /*! update_pad_ctl - update lock for pad control
57076  */
57077 #define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_MASK)
57078 #define IOMUXD_ESAI0_TX4_RX1_update_mux_mode_MASK (0x80000000U)
57079 #define IOMUXD_ESAI0_TX4_RX1_update_mux_mode_SHIFT (31U)
57080 /*! update_mux_mode - update lock for mux control
57081  */
57082 #define IOMUXD_ESAI0_TX4_RX1_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_update_mux_mode_MASK)
57083 /*! @} */
57084 
57085 /*! @name ESAI0_TX5_RX0 - ESAI0_TX5_RX0 */
57086 /*! @{ */
57087 #define IOMUXD_ESAI0_TX5_RX0_PDRV_MASK           (0x1U)
57088 #define IOMUXD_ESAI0_TX5_RX0_PDRV_SHIFT          (0U)
57089 /*! PDRV - Drive
57090  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57091  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57092  */
57093 #define IOMUXD_ESAI0_TX5_RX0_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_PDRV_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_PDRV_MASK)
57094 #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_MASK (0x1EU)
57095 #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_SHIFT (1U)
57096 /*! ESAI0_TX5_RX0_reserved_1_4 - reserved
57097  */
57098 #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_MASK)
57099 #define IOMUXD_ESAI0_TX5_RX0_PULL_MASK           (0x60U)
57100 #define IOMUXD_ESAI0_TX5_RX0_PULL_SHIFT          (5U)
57101 /*! PULL - Pull Down Pull Up
57102  *  0b10..pull down
57103  *  0b01..pull up
57104  *  0b00..Prohibited
57105  *  0b11..pull disabled
57106  */
57107 #define IOMUXD_ESAI0_TX5_RX0_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_PULL_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_PULL_MASK)
57108 #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_MASK (0x7FF80U)
57109 #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_SHIFT (7U)
57110 /*! ESAI0_TX5_RX0_reserved_7_18 - reserved
57111  */
57112 #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_MASK)
57113 #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_MASK    (0x380000U)
57114 #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_SHIFT   (19U)
57115 /*! WAKEUP_CTRL - wakeup control
57116  *  0b000..OFF
57117  *  0b001..RESAMPLE
57118  *  0b100..LOW
57119  *  0b111..HIGH
57120  *  0b110..RISE
57121  *  0b101..FALL
57122  */
57123 #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_MASK)
57124 #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_MASK    (0x400000U)
57125 #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_SHIFT   (22U)
57126 /*! WAKEUP_MASK - wakeup mask
57127  */
57128 #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_MASK)
57129 #define IOMUXD_ESAI0_TX5_RX0_lp_config_MASK      (0x1800000U)
57130 #define IOMUXD_ESAI0_TX5_RX0_lp_config_SHIFT     (23U)
57131 /*! lp_config - lower power configuration
57132  *  0b01..EARLY_ISO
57133  *  0b10..LATE_ISO
57134  *  0b11..LATCH
57135  *  0b00..PASS
57136  */
57137 #define IOMUXD_ESAI0_TX5_RX0_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_lp_config_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_lp_config_MASK)
57138 #define IOMUXD_ESAI0_TX5_RX0_sw_config_MASK      (0x6000000U)
57139 #define IOMUXD_ESAI0_TX5_RX0_sw_config_SHIFT     (25U)
57140 /*! sw_config - output and input configuration
57141  *  0b01..OPEN_DRAIN
57142  *  0b10..OPEN_DRAIN_INPUT
57143  *  0b11..INOUT
57144  *  0b00..DEFAULT
57145  */
57146 #define IOMUXD_ESAI0_TX5_RX0_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_sw_config_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_sw_config_MASK)
57147 #define IOMUXD_ESAI0_TX5_RX0_mux_mode_MASK       (0x38000000U)
57148 #define IOMUXD_ESAI0_TX5_RX0_mux_mode_SHIFT      (27U)
57149 /*! mux_mode - mux_mode
57150  *  0b000..ADMA.ESAI0.TX5_RX0
57151  *  0b010..ADMA.LCDIF.D09
57152  *  0b011..CONN.ENET1.RGMII_TXD1
57153  *  0b100..LSIO.GPIO0.IO09
57154  */
57155 #define IOMUXD_ESAI0_TX5_RX0_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_mux_mode_MASK)
57156 #define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_MASK (0x40000000U)
57157 #define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_SHIFT (30U)
57158 /*! update_pad_ctl - update lock for pad control
57159  */
57160 #define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_MASK)
57161 #define IOMUXD_ESAI0_TX5_RX0_update_mux_mode_MASK (0x80000000U)
57162 #define IOMUXD_ESAI0_TX5_RX0_update_mux_mode_SHIFT (31U)
57163 /*! update_mux_mode - update lock for mux control
57164  */
57165 #define IOMUXD_ESAI0_TX5_RX0_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_update_mux_mode_MASK)
57166 /*! @} */
57167 
57168 /*! @name SPDIF0_RX - SPDIF0_RX */
57169 /*! @{ */
57170 #define IOMUXD_SPDIF0_RX_PDRV_MASK               (0x1U)
57171 #define IOMUXD_SPDIF0_RX_PDRV_SHIFT              (0U)
57172 /*! PDRV - Drive
57173  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57174  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57175  */
57176 #define IOMUXD_SPDIF0_RX_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_PDRV_SHIFT)) & IOMUXD_SPDIF0_RX_PDRV_MASK)
57177 #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_MASK (0x1EU)
57178 #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_SHIFT (1U)
57179 /*! SPDIF0_RX_reserved_1_4 - reserved
57180  */
57181 #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_MASK)
57182 #define IOMUXD_SPDIF0_RX_PULL_MASK               (0x60U)
57183 #define IOMUXD_SPDIF0_RX_PULL_SHIFT              (5U)
57184 /*! PULL - Pull Down Pull Up
57185  *  0b10..pull down
57186  *  0b01..pull up
57187  *  0b00..Prohibited
57188  *  0b11..pull disabled
57189  */
57190 #define IOMUXD_SPDIF0_RX_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_PULL_SHIFT)) & IOMUXD_SPDIF0_RX_PULL_MASK)
57191 #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_MASK (0x7FF80U)
57192 #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_SHIFT (7U)
57193 /*! SPDIF0_RX_reserved_7_18 - reserved
57194  */
57195 #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_MASK)
57196 #define IOMUXD_SPDIF0_RX_WAKEUP_CTRL_MASK        (0x380000U)
57197 #define IOMUXD_SPDIF0_RX_WAKEUP_CTRL_SHIFT       (19U)
57198 /*! WAKEUP_CTRL - wakeup control
57199  *  0b000..OFF
57200  *  0b001..RESAMPLE
57201  *  0b100..LOW
57202  *  0b111..HIGH
57203  *  0b110..RISE
57204  *  0b101..FALL
57205  */
57206 #define IOMUXD_SPDIF0_RX_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_RX_WAKEUP_CTRL_MASK)
57207 #define IOMUXD_SPDIF0_RX_WAKEUP_MASK_MASK        (0x400000U)
57208 #define IOMUXD_SPDIF0_RX_WAKEUP_MASK_SHIFT       (22U)
57209 /*! WAKEUP_MASK - wakeup mask
57210  */
57211 #define IOMUXD_SPDIF0_RX_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_RX_WAKEUP_MASK_MASK)
57212 #define IOMUXD_SPDIF0_RX_lp_config_MASK          (0x1800000U)
57213 #define IOMUXD_SPDIF0_RX_lp_config_SHIFT         (23U)
57214 /*! lp_config - lower power configuration
57215  *  0b01..EARLY_ISO
57216  *  0b10..LATE_ISO
57217  *  0b11..LATCH
57218  *  0b00..PASS
57219  */
57220 #define IOMUXD_SPDIF0_RX_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_lp_config_SHIFT)) & IOMUXD_SPDIF0_RX_lp_config_MASK)
57221 #define IOMUXD_SPDIF0_RX_sw_config_MASK          (0x6000000U)
57222 #define IOMUXD_SPDIF0_RX_sw_config_SHIFT         (25U)
57223 /*! sw_config - output and input configuration
57224  *  0b01..OPEN_DRAIN
57225  *  0b10..OPEN_DRAIN_INPUT
57226  *  0b11..INOUT
57227  *  0b00..DEFAULT
57228  */
57229 #define IOMUXD_SPDIF0_RX_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_sw_config_SHIFT)) & IOMUXD_SPDIF0_RX_sw_config_MASK)
57230 #define IOMUXD_SPDIF0_RX_mux_mode_MASK           (0x38000000U)
57231 #define IOMUXD_SPDIF0_RX_mux_mode_SHIFT          (27U)
57232 /*! mux_mode - mux_mode
57233  *  0b000..ADMA.SPDIF0.RX
57234  *  0b001..ADMA.MQS.R
57235  *  0b010..ADMA.LCDIF.D10
57236  *  0b011..CONN.ENET1.RGMII_RXD0
57237  *  0b100..LSIO.GPIO0.IO10
57238  */
57239 #define IOMUXD_SPDIF0_RX_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_mux_mode_SHIFT)) & IOMUXD_SPDIF0_RX_mux_mode_MASK)
57240 #define IOMUXD_SPDIF0_RX_update_pad_ctl_MASK     (0x40000000U)
57241 #define IOMUXD_SPDIF0_RX_update_pad_ctl_SHIFT    (30U)
57242 /*! update_pad_ctl - update lock for pad control
57243  */
57244 #define IOMUXD_SPDIF0_RX_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_RX_update_pad_ctl_MASK)
57245 #define IOMUXD_SPDIF0_RX_update_mux_mode_MASK    (0x80000000U)
57246 #define IOMUXD_SPDIF0_RX_update_mux_mode_SHIFT   (31U)
57247 /*! update_mux_mode - update lock for mux control
57248  */
57249 #define IOMUXD_SPDIF0_RX_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_RX_update_mux_mode_MASK)
57250 /*! @} */
57251 
57252 /*! @name SPDIF0_TX - SPDIF0_TX */
57253 /*! @{ */
57254 #define IOMUXD_SPDIF0_TX_PDRV_MASK               (0x1U)
57255 #define IOMUXD_SPDIF0_TX_PDRV_SHIFT              (0U)
57256 /*! PDRV - Drive
57257  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57258  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57259  */
57260 #define IOMUXD_SPDIF0_TX_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_PDRV_SHIFT)) & IOMUXD_SPDIF0_TX_PDRV_MASK)
57261 #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_MASK (0x1EU)
57262 #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_SHIFT (1U)
57263 /*! SPDIF0_TX_reserved_1_4 - reserved
57264  */
57265 #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_MASK)
57266 #define IOMUXD_SPDIF0_TX_PULL_MASK               (0x60U)
57267 #define IOMUXD_SPDIF0_TX_PULL_SHIFT              (5U)
57268 /*! PULL - Pull Down Pull Up
57269  *  0b10..pull down
57270  *  0b01..pull up
57271  *  0b00..Prohibited
57272  *  0b11..pull disabled
57273  */
57274 #define IOMUXD_SPDIF0_TX_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_PULL_SHIFT)) & IOMUXD_SPDIF0_TX_PULL_MASK)
57275 #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_MASK (0x7FF80U)
57276 #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_SHIFT (7U)
57277 /*! SPDIF0_TX_reserved_7_18 - reserved
57278  */
57279 #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_MASK)
57280 #define IOMUXD_SPDIF0_TX_WAKEUP_CTRL_MASK        (0x380000U)
57281 #define IOMUXD_SPDIF0_TX_WAKEUP_CTRL_SHIFT       (19U)
57282 /*! WAKEUP_CTRL - wakeup control
57283  *  0b000..OFF
57284  *  0b001..RESAMPLE
57285  *  0b100..LOW
57286  *  0b111..HIGH
57287  *  0b110..RISE
57288  *  0b101..FALL
57289  */
57290 #define IOMUXD_SPDIF0_TX_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_TX_WAKEUP_CTRL_MASK)
57291 #define IOMUXD_SPDIF0_TX_WAKEUP_MASK_MASK        (0x400000U)
57292 #define IOMUXD_SPDIF0_TX_WAKEUP_MASK_SHIFT       (22U)
57293 /*! WAKEUP_MASK - wakeup mask
57294  */
57295 #define IOMUXD_SPDIF0_TX_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_TX_WAKEUP_MASK_MASK)
57296 #define IOMUXD_SPDIF0_TX_lp_config_MASK          (0x1800000U)
57297 #define IOMUXD_SPDIF0_TX_lp_config_SHIFT         (23U)
57298 /*! lp_config - lower power configuration
57299  *  0b01..EARLY_ISO
57300  *  0b10..LATE_ISO
57301  *  0b11..LATCH
57302  *  0b00..PASS
57303  */
57304 #define IOMUXD_SPDIF0_TX_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_lp_config_SHIFT)) & IOMUXD_SPDIF0_TX_lp_config_MASK)
57305 #define IOMUXD_SPDIF0_TX_sw_config_MASK          (0x6000000U)
57306 #define IOMUXD_SPDIF0_TX_sw_config_SHIFT         (25U)
57307 /*! sw_config - output and input configuration
57308  *  0b01..OPEN_DRAIN
57309  *  0b10..OPEN_DRAIN_INPUT
57310  *  0b11..INOUT
57311  *  0b00..DEFAULT
57312  */
57313 #define IOMUXD_SPDIF0_TX_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_sw_config_SHIFT)) & IOMUXD_SPDIF0_TX_sw_config_MASK)
57314 #define IOMUXD_SPDIF0_TX_mux_mode_MASK           (0x38000000U)
57315 #define IOMUXD_SPDIF0_TX_mux_mode_SHIFT          (27U)
57316 /*! mux_mode - mux_mode
57317  *  0b000..ADMA.SPDIF0.TX
57318  *  0b001..ADMA.MQS.L
57319  *  0b010..ADMA.LCDIF.D11
57320  *  0b011..CONN.ENET1.RGMII_RX_CTL
57321  *  0b100..LSIO.GPIO0.IO11
57322  */
57323 #define IOMUXD_SPDIF0_TX_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_mux_mode_SHIFT)) & IOMUXD_SPDIF0_TX_mux_mode_MASK)
57324 #define IOMUXD_SPDIF0_TX_update_pad_ctl_MASK     (0x40000000U)
57325 #define IOMUXD_SPDIF0_TX_update_pad_ctl_SHIFT    (30U)
57326 /*! update_pad_ctl - update lock for pad control
57327  */
57328 #define IOMUXD_SPDIF0_TX_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_TX_update_pad_ctl_MASK)
57329 #define IOMUXD_SPDIF0_TX_update_mux_mode_MASK    (0x80000000U)
57330 #define IOMUXD_SPDIF0_TX_update_mux_mode_SHIFT   (31U)
57331 /*! update_mux_mode - update lock for mux control
57332  */
57333 #define IOMUXD_SPDIF0_TX_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_TX_update_mux_mode_MASK)
57334 /*! @} */
57335 
57336 /*! @name IOMUXD_GROUP_1_3 - na */
57337 /*! @{ */
57338 #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_MASK  (0x1U)
57339 #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_SHIFT (0U)
57340 /*! ENET0_MDIO - wakeup from ENET0_MDIO
57341  */
57342 #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_MASK)
57343 #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_MASK   (0x2U)
57344 #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_SHIFT  (1U)
57345 /*! ENET0_MDC - wakeup from ENET0_MDC
57346  */
57347 #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_MASK)
57348 #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_MASK (0x4U)
57349 #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_SHIFT (2U)
57350 /*! iomuxd_group_1_3_reserved_2_2 - reserved
57351  */
57352 #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_MASK)
57353 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_MASK   (0x8U)
57354 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_SHIFT  (3U)
57355 /*! ESAI0_FSR - wakeup from ESAI0_FSR
57356  */
57357 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_MASK)
57358 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_MASK   (0x10U)
57359 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_SHIFT  (4U)
57360 /*! ESAI0_FST - wakeup from ESAI0_FST
57361  */
57362 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_MASK)
57363 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_MASK  (0x20U)
57364 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_SHIFT (5U)
57365 /*! ESAI0_SCKR - wakeup from ESAI0_SCKR
57366  */
57367 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_MASK)
57368 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_MASK  (0x40U)
57369 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_SHIFT (6U)
57370 /*! ESAI0_SCKT - wakeup from ESAI0_SCKT
57371  */
57372 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_MASK)
57373 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_MASK   (0x80U)
57374 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_SHIFT  (7U)
57375 /*! ESAI0_TX0 - wakeup from ESAI0_TX0
57376  */
57377 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_MASK)
57378 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_MASK   (0x100U)
57379 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_SHIFT  (8U)
57380 /*! ESAI0_TX1 - wakeup from ESAI0_TX1
57381  */
57382 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_MASK)
57383 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_MASK (0x200U)
57384 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_SHIFT (9U)
57385 /*! ESAI0_TX2_RX3 - wakeup from ESAI0_TX2_RX3
57386  */
57387 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_MASK)
57388 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_MASK (0x400U)
57389 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_SHIFT (10U)
57390 /*! ESAI0_TX3_RX2 - wakeup from ESAI0_TX3_RX2
57391  */
57392 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_MASK)
57393 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_MASK (0x800U)
57394 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_SHIFT (11U)
57395 /*! ESAI0_TX4_RX1 - wakeup from ESAI0_TX4_RX1
57396  */
57397 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_MASK)
57398 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_MASK (0x1000U)
57399 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_SHIFT (12U)
57400 /*! ESAI0_TX5_RX0 - wakeup from ESAI0_TX5_RX0
57401  */
57402 #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_MASK)
57403 #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_MASK   (0x2000U)
57404 #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_SHIFT  (13U)
57405 /*! SPDIF0_RX - wakeup from SPDIF0_RX
57406  */
57407 #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_MASK)
57408 #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_MASK   (0x4000U)
57409 #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_SHIFT  (14U)
57410 /*! SPDIF0_TX - wakeup from SPDIF0_TX
57411  */
57412 #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_MASK)
57413 #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_MASK (0xFFFF8000U)
57414 #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_SHIFT (15U)
57415 /*! iomuxd_group_1_3_reserved_15_31 - reserved
57416  */
57417 #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_MASK)
57418 /*! @} */
57419 
57420 /*! @name SPDIF0_EXT_CLK - SPDIF0_EXT_CLK */
57421 /*! @{ */
57422 #define IOMUXD_SPDIF0_EXT_CLK_PDRV_MASK          (0x1U)
57423 #define IOMUXD_SPDIF0_EXT_CLK_PDRV_SHIFT         (0U)
57424 /*! PDRV - Drive
57425  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57426  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57427  */
57428 #define IOMUXD_SPDIF0_EXT_CLK_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_PDRV_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_PDRV_MASK)
57429 #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_MASK (0x1EU)
57430 #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_SHIFT (1U)
57431 /*! SPDIF0_EXT_CLK_reserved_1_4 - reserved
57432  */
57433 #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_MASK)
57434 #define IOMUXD_SPDIF0_EXT_CLK_PULL_MASK          (0x60U)
57435 #define IOMUXD_SPDIF0_EXT_CLK_PULL_SHIFT         (5U)
57436 /*! PULL - Pull Down Pull Up
57437  *  0b10..pull down
57438  *  0b01..pull up
57439  *  0b00..Prohibited
57440  *  0b11..pull disabled
57441  */
57442 #define IOMUXD_SPDIF0_EXT_CLK_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_PULL_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_PULL_MASK)
57443 #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_MASK (0x7FF80U)
57444 #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_SHIFT (7U)
57445 /*! SPDIF0_EXT_CLK_reserved_7_18 - reserved
57446  */
57447 #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_MASK)
57448 #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_MASK   (0x380000U)
57449 #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_SHIFT  (19U)
57450 /*! WAKEUP_CTRL - wakeup control
57451  *  0b000..OFF
57452  *  0b001..RESAMPLE
57453  *  0b100..LOW
57454  *  0b111..HIGH
57455  *  0b110..RISE
57456  *  0b101..FALL
57457  */
57458 #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_MASK)
57459 #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_MASK   (0x400000U)
57460 #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_SHIFT  (22U)
57461 /*! WAKEUP_MASK - wakeup mask
57462  */
57463 #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_MASK)
57464 #define IOMUXD_SPDIF0_EXT_CLK_lp_config_MASK     (0x1800000U)
57465 #define IOMUXD_SPDIF0_EXT_CLK_lp_config_SHIFT    (23U)
57466 /*! lp_config - lower power configuration
57467  *  0b01..EARLY_ISO
57468  *  0b10..LATE_ISO
57469  *  0b11..LATCH
57470  *  0b00..PASS
57471  */
57472 #define IOMUXD_SPDIF0_EXT_CLK_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_lp_config_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_lp_config_MASK)
57473 #define IOMUXD_SPDIF0_EXT_CLK_sw_config_MASK     (0x6000000U)
57474 #define IOMUXD_SPDIF0_EXT_CLK_sw_config_SHIFT    (25U)
57475 /*! sw_config - output and input configuration
57476  *  0b01..OPEN_DRAIN
57477  *  0b10..OPEN_DRAIN_INPUT
57478  *  0b11..INOUT
57479  *  0b00..DEFAULT
57480  */
57481 #define IOMUXD_SPDIF0_EXT_CLK_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_sw_config_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_sw_config_MASK)
57482 #define IOMUXD_SPDIF0_EXT_CLK_mux_mode_MASK      (0x38000000U)
57483 #define IOMUXD_SPDIF0_EXT_CLK_mux_mode_SHIFT     (27U)
57484 /*! mux_mode - mux_mode
57485  *  0b000..ADMA.SPDIF0.EXT_CLK
57486  *  0b010..ADMA.LCDIF.D12
57487  *  0b011..CONN.ENET1.REFCLK_125M_25M
57488  *  0b100..LSIO.GPIO0.IO12
57489  */
57490 #define IOMUXD_SPDIF0_EXT_CLK_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_mux_mode_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_mux_mode_MASK)
57491 #define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_MASK (0x40000000U)
57492 #define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_SHIFT (30U)
57493 /*! update_pad_ctl - update lock for pad control
57494  */
57495 #define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_MASK)
57496 #define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_MASK (0x80000000U)
57497 #define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_SHIFT (31U)
57498 /*! update_mux_mode - update lock for mux control
57499  */
57500 #define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_MASK)
57501 /*! @} */
57502 
57503 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB */
57504 /*! @{ */
57505 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_MASK (0x7U)
57506 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_SHIFT (0U)
57507 /*! COMP - COMP
57508  *  0b010..Fixed code mode
57509  *  0b100..High impedance mode
57510  *  0b110..Read mode
57511  *  0b000..Normal Mode
57512  *  0b001..Freeze Mode
57513  */
57514 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_MASK)
57515 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_MASK (0x8U)
57516 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_SHIFT (3U)
57517 /*! FASTFRZ_EN - FASTFRZ_EN
57518  *  0b1..FASTFRZ signal is driven by output of subsystem
57519  *  0b0..FASTFRZ signal is gated to 0
57520  */
57521 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_MASK)
57522 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_MASK (0x10U)
57523 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_SHIFT (4U)
57524 /*! PSW_OVR - PSW_OVR
57525  *  0b1..override output of voltage detector when using 2.5V IO operation
57526  *  0b0..selection coming from voltage detector cell for 1.8V or 3.3V IO operation
57527  */
57528 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_MASK)
57529 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_MASK (0x1E0U)
57530 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_SHIFT (5U)
57531 /*! RASRCP - RASRCP
57532  *  0b0101..Reset Value
57533  */
57534 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_MASK)
57535 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_MASK (0x1E00U)
57536 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_SHIFT (9U)
57537 /*! RASRCN - RASRCN
57538  *  0b1010..Reset Value
57539  */
57540 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_MASK)
57541 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_MASK (0x2000U)
57542 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_SHIFT (13U)
57543 /*! SELECT_NASRC - SELECT_NASRC
57544  *  0b1..NASRCN value
57545  *  0b0..NASRCP value
57546  */
57547 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_MASK)
57548 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_MASK (0x4000U)
57549 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_SHIFT (14U)
57550 /*! COMPOK - COMPOK
57551  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
57552  *  0b1..compensation cell in Normal mode and tracking PVT
57553  */
57554 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_MASK)
57555 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_MASK (0x78000U)
57556 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_SHIFT (15U)
57557 /*! READ_NASRC - READ_NASRC
57558  *  0b0000..READ Only
57559  */
57560 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_MASK)
57561 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_MASK (0x780000U)
57562 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_SHIFT (19U)
57563 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22 - reserved
57564  */
57565 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_MASK)
57566 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_MASK (0x1800000U)
57567 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_SHIFT (23U)
57568 /*! SLEEP - SLEEP
57569  *  0b11..LAST
57570  *  0b00..NO
57571  *  0b01..EARLY
57572  *  0b10..LATE
57573  */
57574 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_MASK)
57575 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_MASK (0x3E000000U)
57576 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_SHIFT (25U)
57577 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29 - reserved
57578  */
57579 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_MASK)
57580 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_MASK (0x40000000U)
57581 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_SHIFT (30U)
57582 /*! update_pad_ctl - update lock for pad control
57583  */
57584 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_MASK)
57585 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_MASK (0x80000000U)
57586 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_SHIFT (31U)
57587 /*! update_mux_mode - update lock for mux control
57588  */
57589 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_MASK)
57590 /*! @} */
57591 
57592 /*! @name SPI3_SCK - SPI3_SCK */
57593 /*! @{ */
57594 #define IOMUXD_SPI3_SCK_PDRV_MASK                (0x1U)
57595 #define IOMUXD_SPI3_SCK_PDRV_SHIFT               (0U)
57596 /*! PDRV - Drive
57597  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57598  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57599  */
57600 #define IOMUXD_SPI3_SCK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_PDRV_SHIFT)) & IOMUXD_SPI3_SCK_PDRV_MASK)
57601 #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_MASK (0x1EU)
57602 #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_SHIFT (1U)
57603 /*! SPI3_SCK_reserved_1_4 - reserved
57604  */
57605 #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_MASK)
57606 #define IOMUXD_SPI3_SCK_PULL_MASK                (0x60U)
57607 #define IOMUXD_SPI3_SCK_PULL_SHIFT               (5U)
57608 /*! PULL - Pull Down Pull Up
57609  *  0b10..pull down
57610  *  0b01..pull up
57611  *  0b00..Prohibited
57612  *  0b11..pull disabled
57613  */
57614 #define IOMUXD_SPI3_SCK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_PULL_SHIFT)) & IOMUXD_SPI3_SCK_PULL_MASK)
57615 #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_MASK (0x7FF80U)
57616 #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_SHIFT (7U)
57617 /*! SPI3_SCK_reserved_7_18 - reserved
57618  */
57619 #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_MASK)
57620 #define IOMUXD_SPI3_SCK_WAKEUP_CTRL_MASK         (0x380000U)
57621 #define IOMUXD_SPI3_SCK_WAKEUP_CTRL_SHIFT        (19U)
57622 /*! WAKEUP_CTRL - wakeup control
57623  *  0b000..OFF
57624  *  0b001..RESAMPLE
57625  *  0b100..LOW
57626  *  0b111..HIGH
57627  *  0b110..RISE
57628  *  0b101..FALL
57629  */
57630 #define IOMUXD_SPI3_SCK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SCK_WAKEUP_CTRL_MASK)
57631 #define IOMUXD_SPI3_SCK_WAKEUP_MASK_MASK         (0x400000U)
57632 #define IOMUXD_SPI3_SCK_WAKEUP_MASK_SHIFT        (22U)
57633 /*! WAKEUP_MASK - wakeup mask
57634  */
57635 #define IOMUXD_SPI3_SCK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SCK_WAKEUP_MASK_MASK)
57636 #define IOMUXD_SPI3_SCK_lp_config_MASK           (0x1800000U)
57637 #define IOMUXD_SPI3_SCK_lp_config_SHIFT          (23U)
57638 /*! lp_config - lower power configuration
57639  *  0b01..EARLY_ISO
57640  *  0b10..LATE_ISO
57641  *  0b11..LATCH
57642  *  0b00..PASS
57643  */
57644 #define IOMUXD_SPI3_SCK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_lp_config_SHIFT)) & IOMUXD_SPI3_SCK_lp_config_MASK)
57645 #define IOMUXD_SPI3_SCK_sw_config_MASK           (0x6000000U)
57646 #define IOMUXD_SPI3_SCK_sw_config_SHIFT          (25U)
57647 /*! sw_config - output and input configuration
57648  *  0b01..OPEN_DRAIN
57649  *  0b10..OPEN_DRAIN_INPUT
57650  *  0b11..INOUT
57651  *  0b00..DEFAULT
57652  */
57653 #define IOMUXD_SPI3_SCK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_sw_config_SHIFT)) & IOMUXD_SPI3_SCK_sw_config_MASK)
57654 #define IOMUXD_SPI3_SCK_mux_mode_MASK            (0x38000000U)
57655 #define IOMUXD_SPI3_SCK_mux_mode_SHIFT           (27U)
57656 /*! mux_mode - mux_mode
57657  *  0b000..ADMA.SPI3.SCK
57658  *  0b010..ADMA.LCDIF.D13
57659  *  0b100..LSIO.GPIO0.IO13
57660  */
57661 #define IOMUXD_SPI3_SCK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_mux_mode_SHIFT)) & IOMUXD_SPI3_SCK_mux_mode_MASK)
57662 #define IOMUXD_SPI3_SCK_update_pad_ctl_MASK      (0x40000000U)
57663 #define IOMUXD_SPI3_SCK_update_pad_ctl_SHIFT     (30U)
57664 /*! update_pad_ctl - update lock for pad control
57665  */
57666 #define IOMUXD_SPI3_SCK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SCK_update_pad_ctl_MASK)
57667 #define IOMUXD_SPI3_SCK_update_mux_mode_MASK     (0x80000000U)
57668 #define IOMUXD_SPI3_SCK_update_mux_mode_SHIFT    (31U)
57669 /*! update_mux_mode - update lock for mux control
57670  */
57671 #define IOMUXD_SPI3_SCK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SCK_update_mux_mode_MASK)
57672 /*! @} */
57673 
57674 /*! @name SPI3_SDO - SPI3_SDO */
57675 /*! @{ */
57676 #define IOMUXD_SPI3_SDO_PDRV_MASK                (0x1U)
57677 #define IOMUXD_SPI3_SDO_PDRV_SHIFT               (0U)
57678 /*! PDRV - Drive
57679  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57680  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57681  */
57682 #define IOMUXD_SPI3_SDO_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_PDRV_SHIFT)) & IOMUXD_SPI3_SDO_PDRV_MASK)
57683 #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_MASK (0x1EU)
57684 #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_SHIFT (1U)
57685 /*! SPI3_SDO_reserved_1_4 - reserved
57686  */
57687 #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_MASK)
57688 #define IOMUXD_SPI3_SDO_PULL_MASK                (0x60U)
57689 #define IOMUXD_SPI3_SDO_PULL_SHIFT               (5U)
57690 /*! PULL - Pull Down Pull Up
57691  *  0b10..pull down
57692  *  0b01..pull up
57693  *  0b00..Prohibited
57694  *  0b11..pull disabled
57695  */
57696 #define IOMUXD_SPI3_SDO_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_PULL_SHIFT)) & IOMUXD_SPI3_SDO_PULL_MASK)
57697 #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_MASK (0x7FF80U)
57698 #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_SHIFT (7U)
57699 /*! SPI3_SDO_reserved_7_18 - reserved
57700  */
57701 #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_MASK)
57702 #define IOMUXD_SPI3_SDO_WAKEUP_CTRL_MASK         (0x380000U)
57703 #define IOMUXD_SPI3_SDO_WAKEUP_CTRL_SHIFT        (19U)
57704 /*! WAKEUP_CTRL - wakeup control
57705  *  0b000..OFF
57706  *  0b001..RESAMPLE
57707  *  0b100..LOW
57708  *  0b111..HIGH
57709  *  0b110..RISE
57710  *  0b101..FALL
57711  */
57712 #define IOMUXD_SPI3_SDO_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SDO_WAKEUP_CTRL_MASK)
57713 #define IOMUXD_SPI3_SDO_WAKEUP_MASK_MASK         (0x400000U)
57714 #define IOMUXD_SPI3_SDO_WAKEUP_MASK_SHIFT        (22U)
57715 /*! WAKEUP_MASK - wakeup mask
57716  */
57717 #define IOMUXD_SPI3_SDO_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SDO_WAKEUP_MASK_MASK)
57718 #define IOMUXD_SPI3_SDO_lp_config_MASK           (0x1800000U)
57719 #define IOMUXD_SPI3_SDO_lp_config_SHIFT          (23U)
57720 /*! lp_config - lower power configuration
57721  *  0b01..EARLY_ISO
57722  *  0b10..LATE_ISO
57723  *  0b11..LATCH
57724  *  0b00..PASS
57725  */
57726 #define IOMUXD_SPI3_SDO_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_lp_config_SHIFT)) & IOMUXD_SPI3_SDO_lp_config_MASK)
57727 #define IOMUXD_SPI3_SDO_sw_config_MASK           (0x6000000U)
57728 #define IOMUXD_SPI3_SDO_sw_config_SHIFT          (25U)
57729 /*! sw_config - output and input configuration
57730  *  0b01..OPEN_DRAIN
57731  *  0b10..OPEN_DRAIN_INPUT
57732  *  0b11..INOUT
57733  *  0b00..DEFAULT
57734  */
57735 #define IOMUXD_SPI3_SDO_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_sw_config_SHIFT)) & IOMUXD_SPI3_SDO_sw_config_MASK)
57736 #define IOMUXD_SPI3_SDO_mux_mode_MASK            (0x38000000U)
57737 #define IOMUXD_SPI3_SDO_mux_mode_SHIFT           (27U)
57738 /*! mux_mode - mux_mode
57739  *  0b000..ADMA.SPI3.SDO
57740  *  0b010..ADMA.LCDIF.D14
57741  *  0b100..LSIO.GPIO0.IO14
57742  */
57743 #define IOMUXD_SPI3_SDO_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_mux_mode_SHIFT)) & IOMUXD_SPI3_SDO_mux_mode_MASK)
57744 #define IOMUXD_SPI3_SDO_update_pad_ctl_MASK      (0x40000000U)
57745 #define IOMUXD_SPI3_SDO_update_pad_ctl_SHIFT     (30U)
57746 /*! update_pad_ctl - update lock for pad control
57747  */
57748 #define IOMUXD_SPI3_SDO_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SDO_update_pad_ctl_MASK)
57749 #define IOMUXD_SPI3_SDO_update_mux_mode_MASK     (0x80000000U)
57750 #define IOMUXD_SPI3_SDO_update_mux_mode_SHIFT    (31U)
57751 /*! update_mux_mode - update lock for mux control
57752  */
57753 #define IOMUXD_SPI3_SDO_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SDO_update_mux_mode_MASK)
57754 /*! @} */
57755 
57756 /*! @name SPI3_SDI - SPI3_SDI */
57757 /*! @{ */
57758 #define IOMUXD_SPI3_SDI_PDRV_MASK                (0x1U)
57759 #define IOMUXD_SPI3_SDI_PDRV_SHIFT               (0U)
57760 /*! PDRV - Drive
57761  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57762  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57763  */
57764 #define IOMUXD_SPI3_SDI_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_PDRV_SHIFT)) & IOMUXD_SPI3_SDI_PDRV_MASK)
57765 #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_MASK (0x1EU)
57766 #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_SHIFT (1U)
57767 /*! SPI3_SDI_reserved_1_4 - reserved
57768  */
57769 #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_MASK)
57770 #define IOMUXD_SPI3_SDI_PULL_MASK                (0x60U)
57771 #define IOMUXD_SPI3_SDI_PULL_SHIFT               (5U)
57772 /*! PULL - Pull Down Pull Up
57773  *  0b10..pull down
57774  *  0b01..pull up
57775  *  0b00..Prohibited
57776  *  0b11..pull disabled
57777  */
57778 #define IOMUXD_SPI3_SDI_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_PULL_SHIFT)) & IOMUXD_SPI3_SDI_PULL_MASK)
57779 #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_MASK (0x7FF80U)
57780 #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_SHIFT (7U)
57781 /*! SPI3_SDI_reserved_7_18 - reserved
57782  */
57783 #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_MASK)
57784 #define IOMUXD_SPI3_SDI_WAKEUP_CTRL_MASK         (0x380000U)
57785 #define IOMUXD_SPI3_SDI_WAKEUP_CTRL_SHIFT        (19U)
57786 /*! WAKEUP_CTRL - wakeup control
57787  *  0b000..OFF
57788  *  0b001..RESAMPLE
57789  *  0b100..LOW
57790  *  0b111..HIGH
57791  *  0b110..RISE
57792  *  0b101..FALL
57793  */
57794 #define IOMUXD_SPI3_SDI_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SDI_WAKEUP_CTRL_MASK)
57795 #define IOMUXD_SPI3_SDI_WAKEUP_MASK_MASK         (0x400000U)
57796 #define IOMUXD_SPI3_SDI_WAKEUP_MASK_SHIFT        (22U)
57797 /*! WAKEUP_MASK - wakeup mask
57798  */
57799 #define IOMUXD_SPI3_SDI_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SDI_WAKEUP_MASK_MASK)
57800 #define IOMUXD_SPI3_SDI_lp_config_MASK           (0x1800000U)
57801 #define IOMUXD_SPI3_SDI_lp_config_SHIFT          (23U)
57802 /*! lp_config - lower power configuration
57803  *  0b01..EARLY_ISO
57804  *  0b10..LATE_ISO
57805  *  0b11..LATCH
57806  *  0b00..PASS
57807  */
57808 #define IOMUXD_SPI3_SDI_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_lp_config_SHIFT)) & IOMUXD_SPI3_SDI_lp_config_MASK)
57809 #define IOMUXD_SPI3_SDI_sw_config_MASK           (0x6000000U)
57810 #define IOMUXD_SPI3_SDI_sw_config_SHIFT          (25U)
57811 /*! sw_config - output and input configuration
57812  *  0b01..OPEN_DRAIN
57813  *  0b10..OPEN_DRAIN_INPUT
57814  *  0b11..INOUT
57815  *  0b00..DEFAULT
57816  */
57817 #define IOMUXD_SPI3_SDI_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_sw_config_SHIFT)) & IOMUXD_SPI3_SDI_sw_config_MASK)
57818 #define IOMUXD_SPI3_SDI_mux_mode_MASK            (0x38000000U)
57819 #define IOMUXD_SPI3_SDI_mux_mode_SHIFT           (27U)
57820 /*! mux_mode - mux_mode
57821  *  0b000..ADMA.SPI3.SDI
57822  *  0b010..ADMA.LCDIF.D15
57823  *  0b100..LSIO.GPIO0.IO15
57824  */
57825 #define IOMUXD_SPI3_SDI_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_mux_mode_SHIFT)) & IOMUXD_SPI3_SDI_mux_mode_MASK)
57826 #define IOMUXD_SPI3_SDI_update_pad_ctl_MASK      (0x40000000U)
57827 #define IOMUXD_SPI3_SDI_update_pad_ctl_SHIFT     (30U)
57828 /*! update_pad_ctl - update lock for pad control
57829  */
57830 #define IOMUXD_SPI3_SDI_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SDI_update_pad_ctl_MASK)
57831 #define IOMUXD_SPI3_SDI_update_mux_mode_MASK     (0x80000000U)
57832 #define IOMUXD_SPI3_SDI_update_mux_mode_SHIFT    (31U)
57833 /*! update_mux_mode - update lock for mux control
57834  */
57835 #define IOMUXD_SPI3_SDI_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SDI_update_mux_mode_MASK)
57836 /*! @} */
57837 
57838 /*! @name SPI3_CS0 - SPI3_CS0 */
57839 /*! @{ */
57840 #define IOMUXD_SPI3_CS0_PDRV_MASK                (0x1U)
57841 #define IOMUXD_SPI3_CS0_PDRV_SHIFT               (0U)
57842 /*! PDRV - Drive
57843  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57844  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57845  */
57846 #define IOMUXD_SPI3_CS0_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_PDRV_SHIFT)) & IOMUXD_SPI3_CS0_PDRV_MASK)
57847 #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_MASK (0x1EU)
57848 #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_SHIFT (1U)
57849 /*! SPI3_CS0_reserved_1_4 - reserved
57850  */
57851 #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_MASK)
57852 #define IOMUXD_SPI3_CS0_PULL_MASK                (0x60U)
57853 #define IOMUXD_SPI3_CS0_PULL_SHIFT               (5U)
57854 /*! PULL - Pull Down Pull Up
57855  *  0b10..pull down
57856  *  0b01..pull up
57857  *  0b00..Prohibited
57858  *  0b11..pull disabled
57859  */
57860 #define IOMUXD_SPI3_CS0_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_PULL_SHIFT)) & IOMUXD_SPI3_CS0_PULL_MASK)
57861 #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_MASK (0x7FF80U)
57862 #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_SHIFT (7U)
57863 /*! SPI3_CS0_reserved_7_18 - reserved
57864  */
57865 #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_MASK)
57866 #define IOMUXD_SPI3_CS0_WAKEUP_CTRL_MASK         (0x380000U)
57867 #define IOMUXD_SPI3_CS0_WAKEUP_CTRL_SHIFT        (19U)
57868 /*! WAKEUP_CTRL - wakeup control
57869  *  0b000..OFF
57870  *  0b001..RESAMPLE
57871  *  0b100..LOW
57872  *  0b111..HIGH
57873  *  0b110..RISE
57874  *  0b101..FALL
57875  */
57876 #define IOMUXD_SPI3_CS0_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_CS0_WAKEUP_CTRL_MASK)
57877 #define IOMUXD_SPI3_CS0_WAKEUP_MASK_MASK         (0x400000U)
57878 #define IOMUXD_SPI3_CS0_WAKEUP_MASK_SHIFT        (22U)
57879 /*! WAKEUP_MASK - wakeup mask
57880  */
57881 #define IOMUXD_SPI3_CS0_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_CS0_WAKEUP_MASK_MASK)
57882 #define IOMUXD_SPI3_CS0_lp_config_MASK           (0x1800000U)
57883 #define IOMUXD_SPI3_CS0_lp_config_SHIFT          (23U)
57884 /*! lp_config - lower power configuration
57885  *  0b01..EARLY_ISO
57886  *  0b10..LATE_ISO
57887  *  0b11..LATCH
57888  *  0b00..PASS
57889  */
57890 #define IOMUXD_SPI3_CS0_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_lp_config_SHIFT)) & IOMUXD_SPI3_CS0_lp_config_MASK)
57891 #define IOMUXD_SPI3_CS0_sw_config_MASK           (0x6000000U)
57892 #define IOMUXD_SPI3_CS0_sw_config_SHIFT          (25U)
57893 /*! sw_config - output and input configuration
57894  *  0b01..OPEN_DRAIN
57895  *  0b10..OPEN_DRAIN_INPUT
57896  *  0b11..INOUT
57897  *  0b00..DEFAULT
57898  */
57899 #define IOMUXD_SPI3_CS0_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_sw_config_SHIFT)) & IOMUXD_SPI3_CS0_sw_config_MASK)
57900 #define IOMUXD_SPI3_CS0_mux_mode_MASK            (0x38000000U)
57901 #define IOMUXD_SPI3_CS0_mux_mode_SHIFT           (27U)
57902 /*! mux_mode - mux_mode
57903  *  0b000..ADMA.SPI3.CS0
57904  *  0b001..ADMA.ACM.MCLK_OUT1
57905  *  0b010..ADMA.LCDIF.HSYNC
57906  *  0b100..LSIO.GPIO0.IO16
57907  */
57908 #define IOMUXD_SPI3_CS0_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_mux_mode_SHIFT)) & IOMUXD_SPI3_CS0_mux_mode_MASK)
57909 #define IOMUXD_SPI3_CS0_update_pad_ctl_MASK      (0x40000000U)
57910 #define IOMUXD_SPI3_CS0_update_pad_ctl_SHIFT     (30U)
57911 /*! update_pad_ctl - update lock for pad control
57912  */
57913 #define IOMUXD_SPI3_CS0_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_CS0_update_pad_ctl_MASK)
57914 #define IOMUXD_SPI3_CS0_update_mux_mode_MASK     (0x80000000U)
57915 #define IOMUXD_SPI3_CS0_update_mux_mode_SHIFT    (31U)
57916 /*! update_mux_mode - update lock for mux control
57917  */
57918 #define IOMUXD_SPI3_CS0_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI3_CS0_update_mux_mode_MASK)
57919 /*! @} */
57920 
57921 /*! @name SPI3_CS1 - SPI3_CS1 */
57922 /*! @{ */
57923 #define IOMUXD_SPI3_CS1_PDRV_MASK                (0x1U)
57924 #define IOMUXD_SPI3_CS1_PDRV_SHIFT               (0U)
57925 /*! PDRV - Drive
57926  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57927  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57928  */
57929 #define IOMUXD_SPI3_CS1_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_PDRV_SHIFT)) & IOMUXD_SPI3_CS1_PDRV_MASK)
57930 #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_MASK (0x1EU)
57931 #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_SHIFT (1U)
57932 /*! SPI3_CS1_reserved_1_4 - reserved
57933  */
57934 #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_SHIFT)) & IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_MASK)
57935 #define IOMUXD_SPI3_CS1_PULL_MASK                (0x60U)
57936 #define IOMUXD_SPI3_CS1_PULL_SHIFT               (5U)
57937 /*! PULL - Pull Down Pull Up
57938  *  0b10..pull down
57939  *  0b01..pull up
57940  *  0b00..Prohibited
57941  *  0b11..pull disabled
57942  */
57943 #define IOMUXD_SPI3_CS1_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_PULL_SHIFT)) & IOMUXD_SPI3_CS1_PULL_MASK)
57944 #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_MASK (0x7FF80U)
57945 #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_SHIFT (7U)
57946 /*! SPI3_CS1_reserved_7_18 - reserved
57947  */
57948 #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_SHIFT)) & IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_MASK)
57949 #define IOMUXD_SPI3_CS1_WAKEUP_CTRL_MASK         (0x380000U)
57950 #define IOMUXD_SPI3_CS1_WAKEUP_CTRL_SHIFT        (19U)
57951 /*! WAKEUP_CTRL - wakeup control
57952  *  0b000..OFF
57953  *  0b001..RESAMPLE
57954  *  0b100..LOW
57955  *  0b111..HIGH
57956  *  0b110..RISE
57957  *  0b101..FALL
57958  */
57959 #define IOMUXD_SPI3_CS1_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_CS1_WAKEUP_CTRL_MASK)
57960 #define IOMUXD_SPI3_CS1_WAKEUP_MASK_MASK         (0x400000U)
57961 #define IOMUXD_SPI3_CS1_WAKEUP_MASK_SHIFT        (22U)
57962 /*! WAKEUP_MASK - wakeup mask
57963  */
57964 #define IOMUXD_SPI3_CS1_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_CS1_WAKEUP_MASK_MASK)
57965 #define IOMUXD_SPI3_CS1_lp_config_MASK           (0x1800000U)
57966 #define IOMUXD_SPI3_CS1_lp_config_SHIFT          (23U)
57967 /*! lp_config - lower power configuration
57968  *  0b01..EARLY_ISO
57969  *  0b10..LATE_ISO
57970  *  0b11..LATCH
57971  *  0b00..PASS
57972  */
57973 #define IOMUXD_SPI3_CS1_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_lp_config_SHIFT)) & IOMUXD_SPI3_CS1_lp_config_MASK)
57974 #define IOMUXD_SPI3_CS1_sw_config_MASK           (0x6000000U)
57975 #define IOMUXD_SPI3_CS1_sw_config_SHIFT          (25U)
57976 /*! sw_config - output and input configuration
57977  *  0b01..OPEN_DRAIN
57978  *  0b10..OPEN_DRAIN_INPUT
57979  *  0b11..INOUT
57980  *  0b00..DEFAULT
57981  */
57982 #define IOMUXD_SPI3_CS1_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_sw_config_SHIFT)) & IOMUXD_SPI3_CS1_sw_config_MASK)
57983 #define IOMUXD_SPI3_CS1_mux_mode_MASK            (0x38000000U)
57984 #define IOMUXD_SPI3_CS1_mux_mode_SHIFT           (27U)
57985 /*! mux_mode - mux_mode
57986  *  0b000..ADMA.SPI3.CS1
57987  *  0b001..ADMA.I2C3.SCL
57988  *  0b010..ADMA.LCDIF.RESET
57989  *  0b011..ADMA.SPI2.CS0
57990  *  0b100..ADMA.LCDIF.D16
57991  */
57992 #define IOMUXD_SPI3_CS1_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_mux_mode_SHIFT)) & IOMUXD_SPI3_CS1_mux_mode_MASK)
57993 #define IOMUXD_SPI3_CS1_update_pad_ctl_MASK      (0x40000000U)
57994 #define IOMUXD_SPI3_CS1_update_pad_ctl_SHIFT     (30U)
57995 /*! update_pad_ctl - update lock for pad control
57996  */
57997 #define IOMUXD_SPI3_CS1_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_CS1_update_pad_ctl_MASK)
57998 #define IOMUXD_SPI3_CS1_update_mux_mode_MASK     (0x80000000U)
57999 #define IOMUXD_SPI3_CS1_update_mux_mode_SHIFT    (31U)
58000 /*! update_mux_mode - update lock for mux control
58001  */
58002 #define IOMUXD_SPI3_CS1_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_update_mux_mode_SHIFT)) & IOMUXD_SPI3_CS1_update_mux_mode_MASK)
58003 /*! @} */
58004 
58005 /*! @name MCLK_IN1 - MCLK_IN1 */
58006 /*! @{ */
58007 #define IOMUXD_MCLK_IN1_PDRV_MASK                (0x1U)
58008 #define IOMUXD_MCLK_IN1_PDRV_SHIFT               (0U)
58009 /*! PDRV - Drive
58010  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58011  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58012  */
58013 #define IOMUXD_MCLK_IN1_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_PDRV_SHIFT)) & IOMUXD_MCLK_IN1_PDRV_MASK)
58014 #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_MASK (0x1EU)
58015 #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_SHIFT (1U)
58016 /*! MCLK_IN1_reserved_1_4 - reserved
58017  */
58018 #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_SHIFT)) & IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_MASK)
58019 #define IOMUXD_MCLK_IN1_PULL_MASK                (0x60U)
58020 #define IOMUXD_MCLK_IN1_PULL_SHIFT               (5U)
58021 /*! PULL - Pull Down Pull Up
58022  *  0b10..pull down
58023  *  0b01..pull up
58024  *  0b00..Prohibited
58025  *  0b11..pull disabled
58026  */
58027 #define IOMUXD_MCLK_IN1_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_PULL_SHIFT)) & IOMUXD_MCLK_IN1_PULL_MASK)
58028 #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_MASK (0x7FF80U)
58029 #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_SHIFT (7U)
58030 /*! MCLK_IN1_reserved_7_18 - reserved
58031  */
58032 #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_SHIFT)) & IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_MASK)
58033 #define IOMUXD_MCLK_IN1_WAKEUP_CTRL_MASK         (0x380000U)
58034 #define IOMUXD_MCLK_IN1_WAKEUP_CTRL_SHIFT        (19U)
58035 /*! WAKEUP_CTRL - wakeup control
58036  *  0b000..OFF
58037  *  0b001..RESAMPLE
58038  *  0b100..LOW
58039  *  0b111..HIGH
58040  *  0b110..RISE
58041  *  0b101..FALL
58042  */
58043 #define IOMUXD_MCLK_IN1_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_IN1_WAKEUP_CTRL_MASK)
58044 #define IOMUXD_MCLK_IN1_WAKEUP_MASK_MASK         (0x400000U)
58045 #define IOMUXD_MCLK_IN1_WAKEUP_MASK_SHIFT        (22U)
58046 /*! WAKEUP_MASK - wakeup mask
58047  */
58048 #define IOMUXD_MCLK_IN1_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_IN1_WAKEUP_MASK_MASK)
58049 #define IOMUXD_MCLK_IN1_lp_config_MASK           (0x1800000U)
58050 #define IOMUXD_MCLK_IN1_lp_config_SHIFT          (23U)
58051 /*! lp_config - lower power configuration
58052  *  0b01..EARLY_ISO
58053  *  0b10..LATE_ISO
58054  *  0b11..LATCH
58055  *  0b00..PASS
58056  */
58057 #define IOMUXD_MCLK_IN1_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_lp_config_SHIFT)) & IOMUXD_MCLK_IN1_lp_config_MASK)
58058 #define IOMUXD_MCLK_IN1_sw_config_MASK           (0x6000000U)
58059 #define IOMUXD_MCLK_IN1_sw_config_SHIFT          (25U)
58060 /*! sw_config - output and input configuration
58061  *  0b01..OPEN_DRAIN
58062  *  0b10..OPEN_DRAIN_INPUT
58063  *  0b11..INOUT
58064  *  0b00..DEFAULT
58065  */
58066 #define IOMUXD_MCLK_IN1_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_sw_config_SHIFT)) & IOMUXD_MCLK_IN1_sw_config_MASK)
58067 #define IOMUXD_MCLK_IN1_mux_mode_MASK            (0x38000000U)
58068 #define IOMUXD_MCLK_IN1_mux_mode_SHIFT           (27U)
58069 /*! mux_mode - mux_mode
58070  *  0b000..ADMA.ACM.MCLK_IN1
58071  *  0b001..ADMA.I2C3.SDA
58072  *  0b010..ADMA.LCDIF.EN
58073  *  0b011..ADMA.SPI2.SCK
58074  *  0b100..ADMA.LCDIF.D17
58075  */
58076 #define IOMUXD_MCLK_IN1_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_mux_mode_SHIFT)) & IOMUXD_MCLK_IN1_mux_mode_MASK)
58077 #define IOMUXD_MCLK_IN1_update_pad_ctl_MASK      (0x40000000U)
58078 #define IOMUXD_MCLK_IN1_update_pad_ctl_SHIFT     (30U)
58079 /*! update_pad_ctl - update lock for pad control
58080  */
58081 #define IOMUXD_MCLK_IN1_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_IN1_update_pad_ctl_MASK)
58082 #define IOMUXD_MCLK_IN1_update_mux_mode_MASK     (0x80000000U)
58083 #define IOMUXD_MCLK_IN1_update_mux_mode_SHIFT    (31U)
58084 /*! update_mux_mode - update lock for mux control
58085  */
58086 #define IOMUXD_MCLK_IN1_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_update_mux_mode_SHIFT)) & IOMUXD_MCLK_IN1_update_mux_mode_MASK)
58087 /*! @} */
58088 
58089 /*! @name MCLK_IN0 - MCLK_IN0 */
58090 /*! @{ */
58091 #define IOMUXD_MCLK_IN0_PDRV_MASK                (0x1U)
58092 #define IOMUXD_MCLK_IN0_PDRV_SHIFT               (0U)
58093 /*! PDRV - Drive
58094  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58095  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58096  */
58097 #define IOMUXD_MCLK_IN0_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_PDRV_SHIFT)) & IOMUXD_MCLK_IN0_PDRV_MASK)
58098 #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_MASK (0x1EU)
58099 #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_SHIFT (1U)
58100 /*! MCLK_IN0_reserved_1_4 - reserved
58101  */
58102 #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_SHIFT)) & IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_MASK)
58103 #define IOMUXD_MCLK_IN0_PULL_MASK                (0x60U)
58104 #define IOMUXD_MCLK_IN0_PULL_SHIFT               (5U)
58105 /*! PULL - Pull Down Pull Up
58106  *  0b10..pull down
58107  *  0b01..pull up
58108  *  0b00..Prohibited
58109  *  0b11..pull disabled
58110  */
58111 #define IOMUXD_MCLK_IN0_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_PULL_SHIFT)) & IOMUXD_MCLK_IN0_PULL_MASK)
58112 #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_MASK (0x7FF80U)
58113 #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_SHIFT (7U)
58114 /*! MCLK_IN0_reserved_7_18 - reserved
58115  */
58116 #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_SHIFT)) & IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_MASK)
58117 #define IOMUXD_MCLK_IN0_WAKEUP_CTRL_MASK         (0x380000U)
58118 #define IOMUXD_MCLK_IN0_WAKEUP_CTRL_SHIFT        (19U)
58119 /*! WAKEUP_CTRL - wakeup control
58120  *  0b000..OFF
58121  *  0b001..RESAMPLE
58122  *  0b100..LOW
58123  *  0b111..HIGH
58124  *  0b110..RISE
58125  *  0b101..FALL
58126  */
58127 #define IOMUXD_MCLK_IN0_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_IN0_WAKEUP_CTRL_MASK)
58128 #define IOMUXD_MCLK_IN0_WAKEUP_MASK_MASK         (0x400000U)
58129 #define IOMUXD_MCLK_IN0_WAKEUP_MASK_SHIFT        (22U)
58130 /*! WAKEUP_MASK - wakeup mask
58131  */
58132 #define IOMUXD_MCLK_IN0_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_IN0_WAKEUP_MASK_MASK)
58133 #define IOMUXD_MCLK_IN0_lp_config_MASK           (0x1800000U)
58134 #define IOMUXD_MCLK_IN0_lp_config_SHIFT          (23U)
58135 /*! lp_config - lower power configuration
58136  *  0b01..EARLY_ISO
58137  *  0b10..LATE_ISO
58138  *  0b11..LATCH
58139  *  0b00..PASS
58140  */
58141 #define IOMUXD_MCLK_IN0_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_lp_config_SHIFT)) & IOMUXD_MCLK_IN0_lp_config_MASK)
58142 #define IOMUXD_MCLK_IN0_sw_config_MASK           (0x6000000U)
58143 #define IOMUXD_MCLK_IN0_sw_config_SHIFT          (25U)
58144 /*! sw_config - output and input configuration
58145  *  0b01..OPEN_DRAIN
58146  *  0b10..OPEN_DRAIN_INPUT
58147  *  0b11..INOUT
58148  *  0b00..DEFAULT
58149  */
58150 #define IOMUXD_MCLK_IN0_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_sw_config_SHIFT)) & IOMUXD_MCLK_IN0_sw_config_MASK)
58151 #define IOMUXD_MCLK_IN0_mux_mode_MASK            (0x38000000U)
58152 #define IOMUXD_MCLK_IN0_mux_mode_SHIFT           (27U)
58153 /*! mux_mode - mux_mode
58154  *  0b000..ADMA.ACM.MCLK_IN0
58155  *  0b001..ADMA.ESAI0.RX_HF_CLK
58156  *  0b010..ADMA.LCDIF.VSYNC
58157  *  0b011..ADMA.SPI2.SDI
58158  *  0b100..LSIO.GPIO0.IO19
58159  */
58160 #define IOMUXD_MCLK_IN0_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_mux_mode_SHIFT)) & IOMUXD_MCLK_IN0_mux_mode_MASK)
58161 #define IOMUXD_MCLK_IN0_update_pad_ctl_MASK      (0x40000000U)
58162 #define IOMUXD_MCLK_IN0_update_pad_ctl_SHIFT     (30U)
58163 /*! update_pad_ctl - update lock for pad control
58164  */
58165 #define IOMUXD_MCLK_IN0_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_IN0_update_pad_ctl_MASK)
58166 #define IOMUXD_MCLK_IN0_update_mux_mode_MASK     (0x80000000U)
58167 #define IOMUXD_MCLK_IN0_update_mux_mode_SHIFT    (31U)
58168 /*! update_mux_mode - update lock for mux control
58169  */
58170 #define IOMUXD_MCLK_IN0_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_update_mux_mode_SHIFT)) & IOMUXD_MCLK_IN0_update_mux_mode_MASK)
58171 /*! @} */
58172 
58173 /*! @name MCLK_OUT0 - MCLK_OUT0 */
58174 /*! @{ */
58175 #define IOMUXD_MCLK_OUT0_PDRV_MASK               (0x1U)
58176 #define IOMUXD_MCLK_OUT0_PDRV_SHIFT              (0U)
58177 /*! PDRV - Drive
58178  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58179  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58180  */
58181 #define IOMUXD_MCLK_OUT0_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_PDRV_SHIFT)) & IOMUXD_MCLK_OUT0_PDRV_MASK)
58182 #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_MASK (0x1EU)
58183 #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_SHIFT (1U)
58184 /*! MCLK_OUT0_reserved_1_4 - reserved
58185  */
58186 #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_SHIFT)) & IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_MASK)
58187 #define IOMUXD_MCLK_OUT0_PULL_MASK               (0x60U)
58188 #define IOMUXD_MCLK_OUT0_PULL_SHIFT              (5U)
58189 /*! PULL - Pull Down Pull Up
58190  *  0b10..pull down
58191  *  0b01..pull up
58192  *  0b00..Prohibited
58193  *  0b11..pull disabled
58194  */
58195 #define IOMUXD_MCLK_OUT0_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_PULL_SHIFT)) & IOMUXD_MCLK_OUT0_PULL_MASK)
58196 #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_MASK (0x7FF80U)
58197 #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_SHIFT (7U)
58198 /*! MCLK_OUT0_reserved_7_18 - reserved
58199  */
58200 #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_SHIFT)) & IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_MASK)
58201 #define IOMUXD_MCLK_OUT0_WAKEUP_CTRL_MASK        (0x380000U)
58202 #define IOMUXD_MCLK_OUT0_WAKEUP_CTRL_SHIFT       (19U)
58203 /*! WAKEUP_CTRL - wakeup control
58204  *  0b000..OFF
58205  *  0b001..RESAMPLE
58206  *  0b100..LOW
58207  *  0b111..HIGH
58208  *  0b110..RISE
58209  *  0b101..FALL
58210  */
58211 #define IOMUXD_MCLK_OUT0_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_OUT0_WAKEUP_CTRL_MASK)
58212 #define IOMUXD_MCLK_OUT0_WAKEUP_MASK_MASK        (0x400000U)
58213 #define IOMUXD_MCLK_OUT0_WAKEUP_MASK_SHIFT       (22U)
58214 /*! WAKEUP_MASK - wakeup mask
58215  */
58216 #define IOMUXD_MCLK_OUT0_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_OUT0_WAKEUP_MASK_MASK)
58217 #define IOMUXD_MCLK_OUT0_lp_config_MASK          (0x1800000U)
58218 #define IOMUXD_MCLK_OUT0_lp_config_SHIFT         (23U)
58219 /*! lp_config - lower power configuration
58220  *  0b01..EARLY_ISO
58221  *  0b10..LATE_ISO
58222  *  0b11..LATCH
58223  *  0b00..PASS
58224  */
58225 #define IOMUXD_MCLK_OUT0_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_lp_config_SHIFT)) & IOMUXD_MCLK_OUT0_lp_config_MASK)
58226 #define IOMUXD_MCLK_OUT0_sw_config_MASK          (0x6000000U)
58227 #define IOMUXD_MCLK_OUT0_sw_config_SHIFT         (25U)
58228 /*! sw_config - output and input configuration
58229  *  0b01..OPEN_DRAIN
58230  *  0b10..OPEN_DRAIN_INPUT
58231  *  0b11..INOUT
58232  *  0b00..DEFAULT
58233  */
58234 #define IOMUXD_MCLK_OUT0_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_sw_config_SHIFT)) & IOMUXD_MCLK_OUT0_sw_config_MASK)
58235 #define IOMUXD_MCLK_OUT0_mux_mode_MASK           (0x38000000U)
58236 #define IOMUXD_MCLK_OUT0_mux_mode_SHIFT          (27U)
58237 /*! mux_mode - mux_mode
58238  *  0b000..ADMA.ACM.MCLK_OUT0
58239  *  0b001..ADMA.ESAI0.TX_HF_CLK
58240  *  0b010..ADMA.LCDIF.CLK
58241  *  0b011..ADMA.SPI2.SDO
58242  *  0b100..LSIO.GPIO0.IO20
58243  */
58244 #define IOMUXD_MCLK_OUT0_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_mux_mode_SHIFT)) & IOMUXD_MCLK_OUT0_mux_mode_MASK)
58245 #define IOMUXD_MCLK_OUT0_update_pad_ctl_MASK     (0x40000000U)
58246 #define IOMUXD_MCLK_OUT0_update_pad_ctl_SHIFT    (30U)
58247 /*! update_pad_ctl - update lock for pad control
58248  */
58249 #define IOMUXD_MCLK_OUT0_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_OUT0_update_pad_ctl_MASK)
58250 #define IOMUXD_MCLK_OUT0_update_mux_mode_MASK    (0x80000000U)
58251 #define IOMUXD_MCLK_OUT0_update_mux_mode_SHIFT   (31U)
58252 /*! update_mux_mode - update lock for mux control
58253  */
58254 #define IOMUXD_MCLK_OUT0_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_update_mux_mode_SHIFT)) & IOMUXD_MCLK_OUT0_update_mux_mode_MASK)
58255 /*! @} */
58256 
58257 /*! @name UART1_TX - UART1_TX */
58258 /*! @{ */
58259 #define IOMUXD_UART1_TX_PDRV_MASK                (0x1U)
58260 #define IOMUXD_UART1_TX_PDRV_SHIFT               (0U)
58261 /*! PDRV - Drive
58262  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58263  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58264  */
58265 #define IOMUXD_UART1_TX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_PDRV_SHIFT)) & IOMUXD_UART1_TX_PDRV_MASK)
58266 #define IOMUXD_UART1_TX_UART1_TX_reserved_1_4_MASK (0x1EU)
58267 #define IOMUXD_UART1_TX_UART1_TX_reserved_1_4_SHIFT (1U)
58268 /*! UART1_TX_reserved_1_4 - reserved
58269  */
58270 #define IOMUXD_UART1_TX_UART1_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_UART1_TX_reserved_1_4_SHIFT)) & IOMUXD_UART1_TX_UART1_TX_reserved_1_4_MASK)
58271 #define IOMUXD_UART1_TX_PULL_MASK                (0x60U)
58272 #define IOMUXD_UART1_TX_PULL_SHIFT               (5U)
58273 /*! PULL - Pull Down Pull Up
58274  *  0b10..pull down
58275  *  0b01..pull up
58276  *  0b00..Prohibited
58277  *  0b11..pull disabled
58278  */
58279 #define IOMUXD_UART1_TX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_PULL_SHIFT)) & IOMUXD_UART1_TX_PULL_MASK)
58280 #define IOMUXD_UART1_TX_UART1_TX_reserved_7_18_MASK (0x7FF80U)
58281 #define IOMUXD_UART1_TX_UART1_TX_reserved_7_18_SHIFT (7U)
58282 /*! UART1_TX_reserved_7_18 - reserved
58283  */
58284 #define IOMUXD_UART1_TX_UART1_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_UART1_TX_reserved_7_18_SHIFT)) & IOMUXD_UART1_TX_UART1_TX_reserved_7_18_MASK)
58285 #define IOMUXD_UART1_TX_WAKEUP_CTRL_MASK         (0x380000U)
58286 #define IOMUXD_UART1_TX_WAKEUP_CTRL_SHIFT        (19U)
58287 /*! WAKEUP_CTRL - wakeup control
58288  *  0b000..OFF
58289  *  0b001..RESAMPLE
58290  *  0b100..LOW
58291  *  0b111..HIGH
58292  *  0b110..RISE
58293  *  0b101..FALL
58294  */
58295 #define IOMUXD_UART1_TX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_TX_WAKEUP_CTRL_MASK)
58296 #define IOMUXD_UART1_TX_WAKEUP_MASK_MASK         (0x400000U)
58297 #define IOMUXD_UART1_TX_WAKEUP_MASK_SHIFT        (22U)
58298 /*! WAKEUP_MASK - wakeup mask
58299  */
58300 #define IOMUXD_UART1_TX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_TX_WAKEUP_MASK_MASK)
58301 #define IOMUXD_UART1_TX_lp_config_MASK           (0x1800000U)
58302 #define IOMUXD_UART1_TX_lp_config_SHIFT          (23U)
58303 /*! lp_config - lower power configuration
58304  *  0b01..EARLY_ISO
58305  *  0b10..LATE_ISO
58306  *  0b11..LATCH
58307  *  0b00..PASS
58308  */
58309 #define IOMUXD_UART1_TX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_lp_config_SHIFT)) & IOMUXD_UART1_TX_lp_config_MASK)
58310 #define IOMUXD_UART1_TX_sw_config_MASK           (0x6000000U)
58311 #define IOMUXD_UART1_TX_sw_config_SHIFT          (25U)
58312 /*! sw_config - output and input configuration
58313  *  0b01..OPEN_DRAIN
58314  *  0b10..OPEN_DRAIN_INPUT
58315  *  0b11..INOUT
58316  *  0b00..DEFAULT
58317  */
58318 #define IOMUXD_UART1_TX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_sw_config_SHIFT)) & IOMUXD_UART1_TX_sw_config_MASK)
58319 #define IOMUXD_UART1_TX_mux_mode_MASK            (0x38000000U)
58320 #define IOMUXD_UART1_TX_mux_mode_SHIFT           (27U)
58321 /*! mux_mode - mux_mode
58322  *  0b000..ADMA.UART1.TX
58323  *  0b001..LSIO.PWM0.OUT
58324  *  0b010..LSIO.GPT0.CAPTURE
58325  *  0b100..LSIO.GPIO0.IO21
58326  */
58327 #define IOMUXD_UART1_TX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_mux_mode_SHIFT)) & IOMUXD_UART1_TX_mux_mode_MASK)
58328 #define IOMUXD_UART1_TX_update_pad_ctl_MASK      (0x40000000U)
58329 #define IOMUXD_UART1_TX_update_pad_ctl_SHIFT     (30U)
58330 /*! update_pad_ctl - update lock for pad control
58331  */
58332 #define IOMUXD_UART1_TX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART1_TX_update_pad_ctl_MASK)
58333 #define IOMUXD_UART1_TX_update_mux_mode_MASK     (0x80000000U)
58334 #define IOMUXD_UART1_TX_update_mux_mode_SHIFT    (31U)
58335 /*! update_mux_mode - update lock for mux control
58336  */
58337 #define IOMUXD_UART1_TX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_update_mux_mode_SHIFT)) & IOMUXD_UART1_TX_update_mux_mode_MASK)
58338 /*! @} */
58339 
58340 /*! @name UART1_RX - UART1_RX */
58341 /*! @{ */
58342 #define IOMUXD_UART1_RX_PDRV_MASK                (0x1U)
58343 #define IOMUXD_UART1_RX_PDRV_SHIFT               (0U)
58344 /*! PDRV - Drive
58345  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58346  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58347  */
58348 #define IOMUXD_UART1_RX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_PDRV_SHIFT)) & IOMUXD_UART1_RX_PDRV_MASK)
58349 #define IOMUXD_UART1_RX_UART1_RX_reserved_1_4_MASK (0x1EU)
58350 #define IOMUXD_UART1_RX_UART1_RX_reserved_1_4_SHIFT (1U)
58351 /*! UART1_RX_reserved_1_4 - reserved
58352  */
58353 #define IOMUXD_UART1_RX_UART1_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_UART1_RX_reserved_1_4_SHIFT)) & IOMUXD_UART1_RX_UART1_RX_reserved_1_4_MASK)
58354 #define IOMUXD_UART1_RX_PULL_MASK                (0x60U)
58355 #define IOMUXD_UART1_RX_PULL_SHIFT               (5U)
58356 /*! PULL - Pull Down Pull Up
58357  *  0b10..pull down
58358  *  0b01..pull up
58359  *  0b00..Prohibited
58360  *  0b11..pull disabled
58361  */
58362 #define IOMUXD_UART1_RX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_PULL_SHIFT)) & IOMUXD_UART1_RX_PULL_MASK)
58363 #define IOMUXD_UART1_RX_UART1_RX_reserved_7_18_MASK (0x7FF80U)
58364 #define IOMUXD_UART1_RX_UART1_RX_reserved_7_18_SHIFT (7U)
58365 /*! UART1_RX_reserved_7_18 - reserved
58366  */
58367 #define IOMUXD_UART1_RX_UART1_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_UART1_RX_reserved_7_18_SHIFT)) & IOMUXD_UART1_RX_UART1_RX_reserved_7_18_MASK)
58368 #define IOMUXD_UART1_RX_WAKEUP_CTRL_MASK         (0x380000U)
58369 #define IOMUXD_UART1_RX_WAKEUP_CTRL_SHIFT        (19U)
58370 /*! WAKEUP_CTRL - wakeup control
58371  *  0b000..OFF
58372  *  0b001..RESAMPLE
58373  *  0b100..LOW
58374  *  0b111..HIGH
58375  *  0b110..RISE
58376  *  0b101..FALL
58377  */
58378 #define IOMUXD_UART1_RX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_RX_WAKEUP_CTRL_MASK)
58379 #define IOMUXD_UART1_RX_WAKEUP_MASK_MASK         (0x400000U)
58380 #define IOMUXD_UART1_RX_WAKEUP_MASK_SHIFT        (22U)
58381 /*! WAKEUP_MASK - wakeup mask
58382  */
58383 #define IOMUXD_UART1_RX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_RX_WAKEUP_MASK_MASK)
58384 #define IOMUXD_UART1_RX_lp_config_MASK           (0x1800000U)
58385 #define IOMUXD_UART1_RX_lp_config_SHIFT          (23U)
58386 /*! lp_config - lower power configuration
58387  *  0b01..EARLY_ISO
58388  *  0b10..LATE_ISO
58389  *  0b11..LATCH
58390  *  0b00..PASS
58391  */
58392 #define IOMUXD_UART1_RX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_lp_config_SHIFT)) & IOMUXD_UART1_RX_lp_config_MASK)
58393 #define IOMUXD_UART1_RX_sw_config_MASK           (0x6000000U)
58394 #define IOMUXD_UART1_RX_sw_config_SHIFT          (25U)
58395 /*! sw_config - output and input configuration
58396  *  0b01..OPEN_DRAIN
58397  *  0b10..OPEN_DRAIN_INPUT
58398  *  0b11..INOUT
58399  *  0b00..DEFAULT
58400  */
58401 #define IOMUXD_UART1_RX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_sw_config_SHIFT)) & IOMUXD_UART1_RX_sw_config_MASK)
58402 #define IOMUXD_UART1_RX_mux_mode_MASK            (0x38000000U)
58403 #define IOMUXD_UART1_RX_mux_mode_SHIFT           (27U)
58404 /*! mux_mode - mux_mode
58405  *  0b000..ADMA.UART1.RX
58406  *  0b001..LSIO.PWM1.OUT
58407  *  0b010..LSIO.GPT0.COMPARE
58408  *  0b011..LSIO.GPT1.CLK
58409  *  0b100..LSIO.GPIO0.IO22
58410  */
58411 #define IOMUXD_UART1_RX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_mux_mode_SHIFT)) & IOMUXD_UART1_RX_mux_mode_MASK)
58412 #define IOMUXD_UART1_RX_update_pad_ctl_MASK      (0x40000000U)
58413 #define IOMUXD_UART1_RX_update_pad_ctl_SHIFT     (30U)
58414 /*! update_pad_ctl - update lock for pad control
58415  */
58416 #define IOMUXD_UART1_RX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART1_RX_update_pad_ctl_MASK)
58417 #define IOMUXD_UART1_RX_update_mux_mode_MASK     (0x80000000U)
58418 #define IOMUXD_UART1_RX_update_mux_mode_SHIFT    (31U)
58419 /*! update_mux_mode - update lock for mux control
58420  */
58421 #define IOMUXD_UART1_RX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_update_mux_mode_SHIFT)) & IOMUXD_UART1_RX_update_mux_mode_MASK)
58422 /*! @} */
58423 
58424 /*! @name UART1_RTS_B - UART1_RTS_B */
58425 /*! @{ */
58426 #define IOMUXD_UART1_RTS_B_PDRV_MASK             (0x1U)
58427 #define IOMUXD_UART1_RTS_B_PDRV_SHIFT            (0U)
58428 /*! PDRV - Drive
58429  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58430  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58431  */
58432 #define IOMUXD_UART1_RTS_B_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_PDRV_SHIFT)) & IOMUXD_UART1_RTS_B_PDRV_MASK)
58433 #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_MASK (0x1EU)
58434 #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_SHIFT (1U)
58435 /*! UART1_RTS_B_reserved_1_4 - reserved
58436  */
58437 #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_MASK)
58438 #define IOMUXD_UART1_RTS_B_PULL_MASK             (0x60U)
58439 #define IOMUXD_UART1_RTS_B_PULL_SHIFT            (5U)
58440 /*! PULL - Pull Down Pull Up
58441  *  0b10..pull down
58442  *  0b01..pull up
58443  *  0b00..Prohibited
58444  *  0b11..pull disabled
58445  */
58446 #define IOMUXD_UART1_RTS_B_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_PULL_SHIFT)) & IOMUXD_UART1_RTS_B_PULL_MASK)
58447 #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_MASK (0x7FF80U)
58448 #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_SHIFT (7U)
58449 /*! UART1_RTS_B_reserved_7_18 - reserved
58450  */
58451 #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_MASK)
58452 #define IOMUXD_UART1_RTS_B_WAKEUP_CTRL_MASK      (0x380000U)
58453 #define IOMUXD_UART1_RTS_B_WAKEUP_CTRL_SHIFT     (19U)
58454 /*! WAKEUP_CTRL - wakeup control
58455  *  0b000..OFF
58456  *  0b001..RESAMPLE
58457  *  0b100..LOW
58458  *  0b111..HIGH
58459  *  0b110..RISE
58460  *  0b101..FALL
58461  */
58462 #define IOMUXD_UART1_RTS_B_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_RTS_B_WAKEUP_CTRL_MASK)
58463 #define IOMUXD_UART1_RTS_B_WAKEUP_MASK_MASK      (0x400000U)
58464 #define IOMUXD_UART1_RTS_B_WAKEUP_MASK_SHIFT     (22U)
58465 /*! WAKEUP_MASK - wakeup mask
58466  */
58467 #define IOMUXD_UART1_RTS_B_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_RTS_B_WAKEUP_MASK_MASK)
58468 #define IOMUXD_UART1_RTS_B_lp_config_MASK        (0x1800000U)
58469 #define IOMUXD_UART1_RTS_B_lp_config_SHIFT       (23U)
58470 /*! lp_config - lower power configuration
58471  *  0b01..EARLY_ISO
58472  *  0b10..LATE_ISO
58473  *  0b11..LATCH
58474  *  0b00..PASS
58475  */
58476 #define IOMUXD_UART1_RTS_B_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_lp_config_SHIFT)) & IOMUXD_UART1_RTS_B_lp_config_MASK)
58477 #define IOMUXD_UART1_RTS_B_sw_config_MASK        (0x6000000U)
58478 #define IOMUXD_UART1_RTS_B_sw_config_SHIFT       (25U)
58479 /*! sw_config - output and input configuration
58480  *  0b01..OPEN_DRAIN
58481  *  0b10..OPEN_DRAIN_INPUT
58482  *  0b11..INOUT
58483  *  0b00..DEFAULT
58484  */
58485 #define IOMUXD_UART1_RTS_B_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_sw_config_SHIFT)) & IOMUXD_UART1_RTS_B_sw_config_MASK)
58486 #define IOMUXD_UART1_RTS_B_mux_mode_MASK         (0x38000000U)
58487 #define IOMUXD_UART1_RTS_B_mux_mode_SHIFT        (27U)
58488 /*! mux_mode - mux_mode
58489  *  0b000..ADMA.UART1.RTS_B
58490  *  0b001..LSIO.PWM2.OUT
58491  *  0b010..ADMA.LCDIF.D16
58492  *  0b011..LSIO.GPT1.CAPTURE
58493  *  0b100..LSIO.GPT0.CLK
58494  */
58495 #define IOMUXD_UART1_RTS_B_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_mux_mode_SHIFT)) & IOMUXD_UART1_RTS_B_mux_mode_MASK)
58496 #define IOMUXD_UART1_RTS_B_update_pad_ctl_MASK   (0x40000000U)
58497 #define IOMUXD_UART1_RTS_B_update_pad_ctl_SHIFT  (30U)
58498 /*! update_pad_ctl - update lock for pad control
58499  */
58500 #define IOMUXD_UART1_RTS_B_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART1_RTS_B_update_pad_ctl_MASK)
58501 #define IOMUXD_UART1_RTS_B_update_mux_mode_MASK  (0x80000000U)
58502 #define IOMUXD_UART1_RTS_B_update_mux_mode_SHIFT (31U)
58503 /*! update_mux_mode - update lock for mux control
58504  */
58505 #define IOMUXD_UART1_RTS_B_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART1_RTS_B_update_mux_mode_MASK)
58506 /*! @} */
58507 
58508 /*! @name UART1_CTS_B - UART1_CTS_B */
58509 /*! @{ */
58510 #define IOMUXD_UART1_CTS_B_PDRV_MASK             (0x1U)
58511 #define IOMUXD_UART1_CTS_B_PDRV_SHIFT            (0U)
58512 /*! PDRV - Drive
58513  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58514  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58515  */
58516 #define IOMUXD_UART1_CTS_B_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_PDRV_SHIFT)) & IOMUXD_UART1_CTS_B_PDRV_MASK)
58517 #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_MASK (0x1EU)
58518 #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_SHIFT (1U)
58519 /*! UART1_CTS_B_reserved_1_4 - reserved
58520  */
58521 #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_MASK)
58522 #define IOMUXD_UART1_CTS_B_PULL_MASK             (0x60U)
58523 #define IOMUXD_UART1_CTS_B_PULL_SHIFT            (5U)
58524 /*! PULL - Pull Down Pull Up
58525  *  0b10..pull down
58526  *  0b01..pull up
58527  *  0b00..Prohibited
58528  *  0b11..pull disabled
58529  */
58530 #define IOMUXD_UART1_CTS_B_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_PULL_SHIFT)) & IOMUXD_UART1_CTS_B_PULL_MASK)
58531 #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_MASK (0x7FF80U)
58532 #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_SHIFT (7U)
58533 /*! UART1_CTS_B_reserved_7_18 - reserved
58534  */
58535 #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_MASK)
58536 #define IOMUXD_UART1_CTS_B_WAKEUP_CTRL_MASK      (0x380000U)
58537 #define IOMUXD_UART1_CTS_B_WAKEUP_CTRL_SHIFT     (19U)
58538 /*! WAKEUP_CTRL - wakeup control
58539  *  0b000..OFF
58540  *  0b001..RESAMPLE
58541  *  0b100..LOW
58542  *  0b111..HIGH
58543  *  0b110..RISE
58544  *  0b101..FALL
58545  */
58546 #define IOMUXD_UART1_CTS_B_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_CTS_B_WAKEUP_CTRL_MASK)
58547 #define IOMUXD_UART1_CTS_B_WAKEUP_MASK_MASK      (0x400000U)
58548 #define IOMUXD_UART1_CTS_B_WAKEUP_MASK_SHIFT     (22U)
58549 /*! WAKEUP_MASK - wakeup mask
58550  */
58551 #define IOMUXD_UART1_CTS_B_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_CTS_B_WAKEUP_MASK_MASK)
58552 #define IOMUXD_UART1_CTS_B_lp_config_MASK        (0x1800000U)
58553 #define IOMUXD_UART1_CTS_B_lp_config_SHIFT       (23U)
58554 /*! lp_config - lower power configuration
58555  *  0b01..EARLY_ISO
58556  *  0b10..LATE_ISO
58557  *  0b11..LATCH
58558  *  0b00..PASS
58559  */
58560 #define IOMUXD_UART1_CTS_B_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_lp_config_SHIFT)) & IOMUXD_UART1_CTS_B_lp_config_MASK)
58561 #define IOMUXD_UART1_CTS_B_sw_config_MASK        (0x6000000U)
58562 #define IOMUXD_UART1_CTS_B_sw_config_SHIFT       (25U)
58563 /*! sw_config - output and input configuration
58564  *  0b01..OPEN_DRAIN
58565  *  0b10..OPEN_DRAIN_INPUT
58566  *  0b11..INOUT
58567  *  0b00..DEFAULT
58568  */
58569 #define IOMUXD_UART1_CTS_B_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_sw_config_SHIFT)) & IOMUXD_UART1_CTS_B_sw_config_MASK)
58570 #define IOMUXD_UART1_CTS_B_mux_mode_MASK         (0x38000000U)
58571 #define IOMUXD_UART1_CTS_B_mux_mode_SHIFT        (27U)
58572 /*! mux_mode - mux_mode
58573  *  0b000..ADMA.UART1.CTS_B
58574  *  0b001..LSIO.PWM3.OUT
58575  *  0b010..ADMA.LCDIF.D17
58576  *  0b011..LSIO.GPT1.COMPARE
58577  *  0b100..LSIO.GPIO0.IO24
58578  */
58579 #define IOMUXD_UART1_CTS_B_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_mux_mode_SHIFT)) & IOMUXD_UART1_CTS_B_mux_mode_MASK)
58580 #define IOMUXD_UART1_CTS_B_update_pad_ctl_MASK   (0x40000000U)
58581 #define IOMUXD_UART1_CTS_B_update_pad_ctl_SHIFT  (30U)
58582 /*! update_pad_ctl - update lock for pad control
58583  */
58584 #define IOMUXD_UART1_CTS_B_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART1_CTS_B_update_pad_ctl_MASK)
58585 #define IOMUXD_UART1_CTS_B_update_mux_mode_MASK  (0x80000000U)
58586 #define IOMUXD_UART1_CTS_B_update_mux_mode_SHIFT (31U)
58587 /*! update_mux_mode - update lock for mux control
58588  */
58589 #define IOMUXD_UART1_CTS_B_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART1_CTS_B_update_mux_mode_MASK)
58590 /*! @} */
58591 
58592 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK */
58593 /*! @{ */
58594 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_MASK (0x7U)
58595 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_SHIFT (0U)
58596 /*! COMP - COMP
58597  *  0b010..Fixed code mode
58598  *  0b100..High impedance mode
58599  *  0b110..Read mode
58600  *  0b000..Normal Mode
58601  *  0b001..Freeze Mode
58602  */
58603 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_MASK)
58604 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_MASK (0x8U)
58605 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_SHIFT (3U)
58606 /*! FASTFRZ_EN - FASTFRZ_EN
58607  *  0b1..FASTFRZ signal is driven by output of subsystem
58608  *  0b0..FASTFRZ signal is gated to 0
58609  */
58610 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_MASK)
58611 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_MASK (0x10U)
58612 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_SHIFT (4U)
58613 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4 - reserved
58614  */
58615 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_MASK)
58616 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_MASK (0x1E0U)
58617 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_SHIFT (5U)
58618 /*! RASRCP - RASRCP
58619  *  0b0101..Reset Value
58620  */
58621 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_MASK)
58622 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_MASK (0x1E00U)
58623 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_SHIFT (9U)
58624 /*! RASRCN - RASRCN
58625  *  0b1010..Reset Value
58626  */
58627 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_MASK)
58628 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_MASK (0x2000U)
58629 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_SHIFT (13U)
58630 /*! SELECT_NASRC - SELECT_NASRC
58631  *  0b1..NASRCN value
58632  *  0b0..NASRCP value
58633  */
58634 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_MASK)
58635 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_MASK (0x4000U)
58636 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_SHIFT (14U)
58637 /*! COMPOK - COMPOK
58638  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
58639  *  0b1..compensation cell in Normal mode and tracking PVT
58640  */
58641 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_MASK)
58642 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_MASK (0x78000U)
58643 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_SHIFT (15U)
58644 /*! READ_NASRC - READ_NASRC
58645  *  0b0000..READ Only
58646  */
58647 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_MASK)
58648 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_MASK (0x780000U)
58649 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_SHIFT (19U)
58650 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22 - reserved
58651  */
58652 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_MASK)
58653 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_MASK (0x1800000U)
58654 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_SHIFT (23U)
58655 /*! SLEEP - SLEEP
58656  *  0b11..Force into sleep mode
58657  *  0b00..NO
58658  *  0b01..EARLY
58659  *  0b10..LATE
58660  */
58661 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_MASK)
58662 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_MASK (0x3E000000U)
58663 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_SHIFT (25U)
58664 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29 - reserved
58665  */
58666 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_MASK)
58667 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_MASK (0x40000000U)
58668 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_SHIFT (30U)
58669 /*! update_pad_ctl - update lock for pad control
58670  */
58671 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_MASK)
58672 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_MASK (0x80000000U)
58673 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_SHIFT (31U)
58674 /*! update_mux_mode - update lock for mux control
58675  */
58676 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_MASK)
58677 /*! @} */
58678 
58679 /*! @name IOMUXD_GROUP_1_4 - na */
58680 /*! @{ */
58681 #define IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_MASK (0x1U)
58682 #define IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_SHIFT (0U)
58683 /*! SPDIF0_EXT_CLK - wakeup from SPDIF0_EXT_CLK
58684  */
58685 #define IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_MASK)
58686 #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_MASK (0x2U)
58687 #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_SHIFT (1U)
58688 /*! iomuxd_group_1_4_reserved_1_1 - reserved
58689  */
58690 #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_MASK)
58691 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_MASK    (0x4U)
58692 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_SHIFT   (2U)
58693 /*! SPI3_SCK - wakeup from SPI3_SCK
58694  */
58695 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_MASK)
58696 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_MASK    (0x8U)
58697 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_SHIFT   (3U)
58698 /*! SPI3_SDO - wakeup from SPI3_SDO
58699  */
58700 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_MASK)
58701 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_MASK    (0x10U)
58702 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_SHIFT   (4U)
58703 /*! SPI3_SDI - wakeup from SPI3_SDI
58704  */
58705 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_MASK)
58706 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_MASK    (0x20U)
58707 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_SHIFT   (5U)
58708 /*! SPI3_CS0 - wakeup from SPI3_CS0
58709  */
58710 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_MASK)
58711 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_MASK    (0x40U)
58712 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_SHIFT   (6U)
58713 /*! SPI3_CS1 - wakeup from SPI3_CS1
58714  */
58715 #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_MASK)
58716 #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_MASK    (0x80U)
58717 #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_SHIFT   (7U)
58718 /*! MCLK_IN1 - wakeup from MCLK_IN1
58719  */
58720 #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_MASK)
58721 #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_MASK    (0x100U)
58722 #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_SHIFT   (8U)
58723 /*! MCLK_IN0 - wakeup from MCLK_IN0
58724  */
58725 #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_MASK)
58726 #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_MASK   (0x200U)
58727 #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_SHIFT  (9U)
58728 /*! MCLK_OUT0 - wakeup from MCLK_OUT0
58729  */
58730 #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_MASK)
58731 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_MASK    (0x400U)
58732 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_SHIFT   (10U)
58733 /*! UART1_TX - wakeup from UART1_TX
58734  */
58735 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_TX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_MASK)
58736 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_MASK    (0x800U)
58737 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_SHIFT   (11U)
58738 /*! UART1_RX - wakeup from UART1_RX
58739  */
58740 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_MASK)
58741 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_MASK (0x1000U)
58742 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_SHIFT (12U)
58743 /*! UART1_RTS_B - wakeup from UART1_RTS_B
58744  */
58745 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_MASK)
58746 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_MASK (0x2000U)
58747 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_SHIFT (13U)
58748 /*! UART1_CTS_B - wakeup from UART1_CTS_B
58749  */
58750 #define IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_MASK)
58751 #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_MASK (0xFFFFC000U)
58752 #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_SHIFT (14U)
58753 /*! iomuxd_group_1_4_reserved_14_31 - reserved
58754  */
58755 #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_MASK)
58756 /*! @} */
58757 
58758 /*! @name SAI0_TXD - SAI0_TXD */
58759 /*! @{ */
58760 #define IOMUXD_SAI0_TXD_PDRV_MASK                (0x1U)
58761 #define IOMUXD_SAI0_TXD_PDRV_SHIFT               (0U)
58762 /*! PDRV - Drive
58763  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58764  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58765  */
58766 #define IOMUXD_SAI0_TXD_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_PDRV_SHIFT)) & IOMUXD_SAI0_TXD_PDRV_MASK)
58767 #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_MASK (0x1EU)
58768 #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_SHIFT (1U)
58769 /*! SAI0_TXD_reserved_1_4 - reserved
58770  */
58771 #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_SHIFT)) & IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_MASK)
58772 #define IOMUXD_SAI0_TXD_PULL_MASK                (0x60U)
58773 #define IOMUXD_SAI0_TXD_PULL_SHIFT               (5U)
58774 /*! PULL - Pull Down Pull Up
58775  *  0b10..pull down
58776  *  0b01..pull up
58777  *  0b00..Prohibited
58778  *  0b11..pull disabled
58779  */
58780 #define IOMUXD_SAI0_TXD_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_PULL_SHIFT)) & IOMUXD_SAI0_TXD_PULL_MASK)
58781 #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_MASK (0x7FF80U)
58782 #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_SHIFT (7U)
58783 /*! SAI0_TXD_reserved_7_18 - reserved
58784  */
58785 #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_SHIFT)) & IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_MASK)
58786 #define IOMUXD_SAI0_TXD_WAKEUP_CTRL_MASK         (0x380000U)
58787 #define IOMUXD_SAI0_TXD_WAKEUP_CTRL_SHIFT        (19U)
58788 /*! WAKEUP_CTRL - wakeup control
58789  *  0b000..OFF
58790  *  0b001..RESAMPLE
58791  *  0b100..LOW
58792  *  0b111..HIGH
58793  *  0b110..RISE
58794  *  0b101..FALL
58795  */
58796 #define IOMUXD_SAI0_TXD_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_TXD_WAKEUP_CTRL_MASK)
58797 #define IOMUXD_SAI0_TXD_WAKEUP_MASK_MASK         (0x400000U)
58798 #define IOMUXD_SAI0_TXD_WAKEUP_MASK_SHIFT        (22U)
58799 /*! WAKEUP_MASK - wakeup mask
58800  */
58801 #define IOMUXD_SAI0_TXD_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_TXD_WAKEUP_MASK_MASK)
58802 #define IOMUXD_SAI0_TXD_lp_config_MASK           (0x1800000U)
58803 #define IOMUXD_SAI0_TXD_lp_config_SHIFT          (23U)
58804 /*! lp_config - lower power configuration
58805  *  0b01..EARLY_ISO
58806  *  0b10..LATE_ISO
58807  *  0b11..LATCH
58808  *  0b00..PASS
58809  */
58810 #define IOMUXD_SAI0_TXD_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_lp_config_SHIFT)) & IOMUXD_SAI0_TXD_lp_config_MASK)
58811 #define IOMUXD_SAI0_TXD_sw_config_MASK           (0x6000000U)
58812 #define IOMUXD_SAI0_TXD_sw_config_SHIFT          (25U)
58813 /*! sw_config - output and input configuration
58814  *  0b01..OPEN_DRAIN
58815  *  0b10..OPEN_DRAIN_INPUT
58816  *  0b11..INOUT
58817  *  0b00..DEFAULT
58818  */
58819 #define IOMUXD_SAI0_TXD_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_sw_config_SHIFT)) & IOMUXD_SAI0_TXD_sw_config_MASK)
58820 #define IOMUXD_SAI0_TXD_mux_mode_MASK            (0x38000000U)
58821 #define IOMUXD_SAI0_TXD_mux_mode_SHIFT           (27U)
58822 /*! mux_mode - mux_mode
58823  *  0b000..ADMA.SAI0.TXD
58824  *  0b001..ADMA.SAI1.RXC
58825  *  0b010..ADMA.SPI1.SDO
58826  *  0b011..ADMA.LCDIF.D18
58827  *  0b100..LSIO.GPIO0.IO25
58828  */
58829 #define IOMUXD_SAI0_TXD_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_mux_mode_SHIFT)) & IOMUXD_SAI0_TXD_mux_mode_MASK)
58830 #define IOMUXD_SAI0_TXD_update_pad_ctl_MASK      (0x40000000U)
58831 #define IOMUXD_SAI0_TXD_update_pad_ctl_SHIFT     (30U)
58832 /*! update_pad_ctl - update lock for pad control
58833  */
58834 #define IOMUXD_SAI0_TXD_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_TXD_update_pad_ctl_MASK)
58835 #define IOMUXD_SAI0_TXD_update_mux_mode_MASK     (0x80000000U)
58836 #define IOMUXD_SAI0_TXD_update_mux_mode_SHIFT    (31U)
58837 /*! update_mux_mode - update lock for mux control
58838  */
58839 #define IOMUXD_SAI0_TXD_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_update_mux_mode_SHIFT)) & IOMUXD_SAI0_TXD_update_mux_mode_MASK)
58840 /*! @} */
58841 
58842 /*! @name SAI0_TXC - SAI0_TXC */
58843 /*! @{ */
58844 #define IOMUXD_SAI0_TXC_PDRV_MASK                (0x1U)
58845 #define IOMUXD_SAI0_TXC_PDRV_SHIFT               (0U)
58846 /*! PDRV - Drive
58847  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58848  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58849  */
58850 #define IOMUXD_SAI0_TXC_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_PDRV_SHIFT)) & IOMUXD_SAI0_TXC_PDRV_MASK)
58851 #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_MASK (0x1EU)
58852 #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_SHIFT (1U)
58853 /*! SAI0_TXC_reserved_1_4 - reserved
58854  */
58855 #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_SHIFT)) & IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_MASK)
58856 #define IOMUXD_SAI0_TXC_PULL_MASK                (0x60U)
58857 #define IOMUXD_SAI0_TXC_PULL_SHIFT               (5U)
58858 /*! PULL - Pull Down Pull Up
58859  *  0b10..pull down
58860  *  0b01..pull up
58861  *  0b00..Prohibited
58862  *  0b11..pull disabled
58863  */
58864 #define IOMUXD_SAI0_TXC_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_PULL_SHIFT)) & IOMUXD_SAI0_TXC_PULL_MASK)
58865 #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_MASK (0x7FF80U)
58866 #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_SHIFT (7U)
58867 /*! SAI0_TXC_reserved_7_18 - reserved
58868  */
58869 #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_SHIFT)) & IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_MASK)
58870 #define IOMUXD_SAI0_TXC_WAKEUP_CTRL_MASK         (0x380000U)
58871 #define IOMUXD_SAI0_TXC_WAKEUP_CTRL_SHIFT        (19U)
58872 /*! WAKEUP_CTRL - wakeup control
58873  *  0b000..OFF
58874  *  0b001..RESAMPLE
58875  *  0b100..LOW
58876  *  0b111..HIGH
58877  *  0b110..RISE
58878  *  0b101..FALL
58879  */
58880 #define IOMUXD_SAI0_TXC_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_TXC_WAKEUP_CTRL_MASK)
58881 #define IOMUXD_SAI0_TXC_WAKEUP_MASK_MASK         (0x400000U)
58882 #define IOMUXD_SAI0_TXC_WAKEUP_MASK_SHIFT        (22U)
58883 /*! WAKEUP_MASK - wakeup mask
58884  */
58885 #define IOMUXD_SAI0_TXC_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_TXC_WAKEUP_MASK_MASK)
58886 #define IOMUXD_SAI0_TXC_lp_config_MASK           (0x1800000U)
58887 #define IOMUXD_SAI0_TXC_lp_config_SHIFT          (23U)
58888 /*! lp_config - lower power configuration
58889  *  0b01..EARLY_ISO
58890  *  0b10..LATE_ISO
58891  *  0b11..LATCH
58892  *  0b00..PASS
58893  */
58894 #define IOMUXD_SAI0_TXC_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_lp_config_SHIFT)) & IOMUXD_SAI0_TXC_lp_config_MASK)
58895 #define IOMUXD_SAI0_TXC_sw_config_MASK           (0x6000000U)
58896 #define IOMUXD_SAI0_TXC_sw_config_SHIFT          (25U)
58897 /*! sw_config - output and input configuration
58898  *  0b01..OPEN_DRAIN
58899  *  0b10..OPEN_DRAIN_INPUT
58900  *  0b11..INOUT
58901  *  0b00..DEFAULT
58902  */
58903 #define IOMUXD_SAI0_TXC_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_sw_config_SHIFT)) & IOMUXD_SAI0_TXC_sw_config_MASK)
58904 #define IOMUXD_SAI0_TXC_mux_mode_MASK            (0x38000000U)
58905 #define IOMUXD_SAI0_TXC_mux_mode_SHIFT           (27U)
58906 /*! mux_mode - mux_mode
58907  *  0b000..ADMA.SAI0.TXC
58908  *  0b001..ADMA.SAI1.TXD
58909  *  0b010..ADMA.SPI1.SDI
58910  *  0b011..ADMA.LCDIF.D19
58911  *  0b100..LSIO.GPIO0.IO26
58912  */
58913 #define IOMUXD_SAI0_TXC_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_mux_mode_SHIFT)) & IOMUXD_SAI0_TXC_mux_mode_MASK)
58914 #define IOMUXD_SAI0_TXC_update_pad_ctl_MASK      (0x40000000U)
58915 #define IOMUXD_SAI0_TXC_update_pad_ctl_SHIFT     (30U)
58916 /*! update_pad_ctl - update lock for pad control
58917  */
58918 #define IOMUXD_SAI0_TXC_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_TXC_update_pad_ctl_MASK)
58919 #define IOMUXD_SAI0_TXC_update_mux_mode_MASK     (0x80000000U)
58920 #define IOMUXD_SAI0_TXC_update_mux_mode_SHIFT    (31U)
58921 /*! update_mux_mode - update lock for mux control
58922  */
58923 #define IOMUXD_SAI0_TXC_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_update_mux_mode_SHIFT)) & IOMUXD_SAI0_TXC_update_mux_mode_MASK)
58924 /*! @} */
58925 
58926 /*! @name SAI0_RXD - SAI0_RXD */
58927 /*! @{ */
58928 #define IOMUXD_SAI0_RXD_PDRV_MASK                (0x1U)
58929 #define IOMUXD_SAI0_RXD_PDRV_SHIFT               (0U)
58930 /*! PDRV - Drive
58931  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58932  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58933  */
58934 #define IOMUXD_SAI0_RXD_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_PDRV_SHIFT)) & IOMUXD_SAI0_RXD_PDRV_MASK)
58935 #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_MASK (0x1EU)
58936 #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_SHIFT (1U)
58937 /*! SAI0_RXD_reserved_1_4 - reserved
58938  */
58939 #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_SHIFT)) & IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_MASK)
58940 #define IOMUXD_SAI0_RXD_PULL_MASK                (0x60U)
58941 #define IOMUXD_SAI0_RXD_PULL_SHIFT               (5U)
58942 /*! PULL - Pull Down Pull Up
58943  *  0b10..pull down
58944  *  0b01..pull up
58945  *  0b00..Prohibited
58946  *  0b11..pull disabled
58947  */
58948 #define IOMUXD_SAI0_RXD_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_PULL_SHIFT)) & IOMUXD_SAI0_RXD_PULL_MASK)
58949 #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_MASK (0x7FF80U)
58950 #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_SHIFT (7U)
58951 /*! SAI0_RXD_reserved_7_18 - reserved
58952  */
58953 #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_SHIFT)) & IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_MASK)
58954 #define IOMUXD_SAI0_RXD_WAKEUP_CTRL_MASK         (0x380000U)
58955 #define IOMUXD_SAI0_RXD_WAKEUP_CTRL_SHIFT        (19U)
58956 /*! WAKEUP_CTRL - wakeup control
58957  *  0b000..OFF
58958  *  0b001..RESAMPLE
58959  *  0b100..LOW
58960  *  0b111..HIGH
58961  *  0b110..RISE
58962  *  0b101..FALL
58963  */
58964 #define IOMUXD_SAI0_RXD_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_RXD_WAKEUP_CTRL_MASK)
58965 #define IOMUXD_SAI0_RXD_WAKEUP_MASK_MASK         (0x400000U)
58966 #define IOMUXD_SAI0_RXD_WAKEUP_MASK_SHIFT        (22U)
58967 /*! WAKEUP_MASK - wakeup mask
58968  */
58969 #define IOMUXD_SAI0_RXD_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_RXD_WAKEUP_MASK_MASK)
58970 #define IOMUXD_SAI0_RXD_lp_config_MASK           (0x1800000U)
58971 #define IOMUXD_SAI0_RXD_lp_config_SHIFT          (23U)
58972 /*! lp_config - lower power configuration
58973  *  0b01..EARLY_ISO
58974  *  0b10..LATE_ISO
58975  *  0b11..LATCH
58976  *  0b00..PASS
58977  */
58978 #define IOMUXD_SAI0_RXD_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_lp_config_SHIFT)) & IOMUXD_SAI0_RXD_lp_config_MASK)
58979 #define IOMUXD_SAI0_RXD_sw_config_MASK           (0x6000000U)
58980 #define IOMUXD_SAI0_RXD_sw_config_SHIFT          (25U)
58981 /*! sw_config - output and input configuration
58982  *  0b01..OPEN_DRAIN
58983  *  0b10..OPEN_DRAIN_INPUT
58984  *  0b11..INOUT
58985  *  0b00..DEFAULT
58986  */
58987 #define IOMUXD_SAI0_RXD_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_sw_config_SHIFT)) & IOMUXD_SAI0_RXD_sw_config_MASK)
58988 #define IOMUXD_SAI0_RXD_mux_mode_MASK            (0x38000000U)
58989 #define IOMUXD_SAI0_RXD_mux_mode_SHIFT           (27U)
58990 /*! mux_mode - mux_mode
58991  *  0b000..ADMA.SAI0.RXD
58992  *  0b001..ADMA.SAI1.RXFS
58993  *  0b010..ADMA.SPI1.CS0
58994  *  0b011..ADMA.LCDIF.D20
58995  *  0b100..LSIO.GPIO0.IO27
58996  */
58997 #define IOMUXD_SAI0_RXD_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_mux_mode_SHIFT)) & IOMUXD_SAI0_RXD_mux_mode_MASK)
58998 #define IOMUXD_SAI0_RXD_update_pad_ctl_MASK      (0x40000000U)
58999 #define IOMUXD_SAI0_RXD_update_pad_ctl_SHIFT     (30U)
59000 /*! update_pad_ctl - update lock for pad control
59001  */
59002 #define IOMUXD_SAI0_RXD_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_RXD_update_pad_ctl_MASK)
59003 #define IOMUXD_SAI0_RXD_update_mux_mode_MASK     (0x80000000U)
59004 #define IOMUXD_SAI0_RXD_update_mux_mode_SHIFT    (31U)
59005 /*! update_mux_mode - update lock for mux control
59006  */
59007 #define IOMUXD_SAI0_RXD_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_update_mux_mode_SHIFT)) & IOMUXD_SAI0_RXD_update_mux_mode_MASK)
59008 /*! @} */
59009 
59010 /*! @name SAI0_TXFS - SAI0_TXFS */
59011 /*! @{ */
59012 #define IOMUXD_SAI0_TXFS_PDRV_MASK               (0x1U)
59013 #define IOMUXD_SAI0_TXFS_PDRV_SHIFT              (0U)
59014 /*! PDRV - Drive
59015  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59016  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59017  */
59018 #define IOMUXD_SAI0_TXFS_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_PDRV_SHIFT)) & IOMUXD_SAI0_TXFS_PDRV_MASK)
59019 #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_MASK (0x1EU)
59020 #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_SHIFT (1U)
59021 /*! SAI0_TXFS_reserved_1_4 - reserved
59022  */
59023 #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_SHIFT)) & IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_MASK)
59024 #define IOMUXD_SAI0_TXFS_PULL_MASK               (0x60U)
59025 #define IOMUXD_SAI0_TXFS_PULL_SHIFT              (5U)
59026 /*! PULL - Pull Down Pull Up
59027  *  0b10..pull down
59028  *  0b01..pull up
59029  *  0b00..Prohibited
59030  *  0b11..pull disabled
59031  */
59032 #define IOMUXD_SAI0_TXFS_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_PULL_SHIFT)) & IOMUXD_SAI0_TXFS_PULL_MASK)
59033 #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_MASK (0x7FF80U)
59034 #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_SHIFT (7U)
59035 /*! SAI0_TXFS_reserved_7_18 - reserved
59036  */
59037 #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_SHIFT)) & IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_MASK)
59038 #define IOMUXD_SAI0_TXFS_WAKEUP_CTRL_MASK        (0x380000U)
59039 #define IOMUXD_SAI0_TXFS_WAKEUP_CTRL_SHIFT       (19U)
59040 /*! WAKEUP_CTRL - wakeup control
59041  *  0b000..OFF
59042  *  0b001..RESAMPLE
59043  *  0b100..LOW
59044  *  0b111..HIGH
59045  *  0b110..RISE
59046  *  0b101..FALL
59047  */
59048 #define IOMUXD_SAI0_TXFS_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_TXFS_WAKEUP_CTRL_MASK)
59049 #define IOMUXD_SAI0_TXFS_WAKEUP_MASK_MASK        (0x400000U)
59050 #define IOMUXD_SAI0_TXFS_WAKEUP_MASK_SHIFT       (22U)
59051 /*! WAKEUP_MASK - wakeup mask
59052  */
59053 #define IOMUXD_SAI0_TXFS_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_TXFS_WAKEUP_MASK_MASK)
59054 #define IOMUXD_SAI0_TXFS_lp_config_MASK          (0x1800000U)
59055 #define IOMUXD_SAI0_TXFS_lp_config_SHIFT         (23U)
59056 /*! lp_config - lower power configuration
59057  *  0b01..EARLY_ISO
59058  *  0b10..LATE_ISO
59059  *  0b11..LATCH
59060  *  0b00..PASS
59061  */
59062 #define IOMUXD_SAI0_TXFS_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_lp_config_SHIFT)) & IOMUXD_SAI0_TXFS_lp_config_MASK)
59063 #define IOMUXD_SAI0_TXFS_sw_config_MASK          (0x6000000U)
59064 #define IOMUXD_SAI0_TXFS_sw_config_SHIFT         (25U)
59065 /*! sw_config - output and input configuration
59066  *  0b01..OPEN_DRAIN
59067  *  0b10..OPEN_DRAIN_INPUT
59068  *  0b11..INOUT
59069  *  0b00..DEFAULT
59070  */
59071 #define IOMUXD_SAI0_TXFS_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_sw_config_SHIFT)) & IOMUXD_SAI0_TXFS_sw_config_MASK)
59072 #define IOMUXD_SAI0_TXFS_mux_mode_MASK           (0x38000000U)
59073 #define IOMUXD_SAI0_TXFS_mux_mode_SHIFT          (27U)
59074 /*! mux_mode - mux_mode
59075  *  0b000..ADMA.SAI0.TXFS
59076  *  0b001..ADMA.SPI2.CS1
59077  *  0b010..ADMA.SPI1.SCK
59078  *  0b100..LSIO.GPIO0.IO28
59079  */
59080 #define IOMUXD_SAI0_TXFS_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_mux_mode_SHIFT)) & IOMUXD_SAI0_TXFS_mux_mode_MASK)
59081 #define IOMUXD_SAI0_TXFS_update_pad_ctl_MASK     (0x40000000U)
59082 #define IOMUXD_SAI0_TXFS_update_pad_ctl_SHIFT    (30U)
59083 /*! update_pad_ctl - update lock for pad control
59084  */
59085 #define IOMUXD_SAI0_TXFS_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_TXFS_update_pad_ctl_MASK)
59086 #define IOMUXD_SAI0_TXFS_update_mux_mode_MASK    (0x80000000U)
59087 #define IOMUXD_SAI0_TXFS_update_mux_mode_SHIFT   (31U)
59088 /*! update_mux_mode - update lock for mux control
59089  */
59090 #define IOMUXD_SAI0_TXFS_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_update_mux_mode_SHIFT)) & IOMUXD_SAI0_TXFS_update_mux_mode_MASK)
59091 /*! @} */
59092 
59093 /*! @name SAI1_RXD - SAI1_RXD */
59094 /*! @{ */
59095 #define IOMUXD_SAI1_RXD_PDRV_MASK                (0x1U)
59096 #define IOMUXD_SAI1_RXD_PDRV_SHIFT               (0U)
59097 /*! PDRV - Drive
59098  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59099  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59100  */
59101 #define IOMUXD_SAI1_RXD_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_PDRV_SHIFT)) & IOMUXD_SAI1_RXD_PDRV_MASK)
59102 #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_MASK (0x1EU)
59103 #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_SHIFT (1U)
59104 /*! SAI1_RXD_reserved_1_4 - reserved
59105  */
59106 #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_MASK)
59107 #define IOMUXD_SAI1_RXD_PULL_MASK                (0x60U)
59108 #define IOMUXD_SAI1_RXD_PULL_SHIFT               (5U)
59109 /*! PULL - Pull Down Pull Up
59110  *  0b10..pull down
59111  *  0b01..pull up
59112  *  0b00..Prohibited
59113  *  0b11..pull disabled
59114  */
59115 #define IOMUXD_SAI1_RXD_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_PULL_SHIFT)) & IOMUXD_SAI1_RXD_PULL_MASK)
59116 #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_MASK (0x7FF80U)
59117 #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_SHIFT (7U)
59118 /*! SAI1_RXD_reserved_7_18 - reserved
59119  */
59120 #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_MASK)
59121 #define IOMUXD_SAI1_RXD_WAKEUP_CTRL_MASK         (0x380000U)
59122 #define IOMUXD_SAI1_RXD_WAKEUP_CTRL_SHIFT        (19U)
59123 /*! WAKEUP_CTRL - wakeup control
59124  *  0b000..OFF
59125  *  0b001..RESAMPLE
59126  *  0b100..LOW
59127  *  0b111..HIGH
59128  *  0b110..RISE
59129  *  0b101..FALL
59130  */
59131 #define IOMUXD_SAI1_RXD_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXD_WAKEUP_CTRL_MASK)
59132 #define IOMUXD_SAI1_RXD_WAKEUP_MASK_MASK         (0x400000U)
59133 #define IOMUXD_SAI1_RXD_WAKEUP_MASK_SHIFT        (22U)
59134 /*! WAKEUP_MASK - wakeup mask
59135  */
59136 #define IOMUXD_SAI1_RXD_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXD_WAKEUP_MASK_MASK)
59137 #define IOMUXD_SAI1_RXD_lp_config_MASK           (0x1800000U)
59138 #define IOMUXD_SAI1_RXD_lp_config_SHIFT          (23U)
59139 /*! lp_config - lower power configuration
59140  *  0b01..EARLY_ISO
59141  *  0b10..LATE_ISO
59142  *  0b11..LATCH
59143  *  0b00..PASS
59144  */
59145 #define IOMUXD_SAI1_RXD_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_lp_config_SHIFT)) & IOMUXD_SAI1_RXD_lp_config_MASK)
59146 #define IOMUXD_SAI1_RXD_sw_config_MASK           (0x6000000U)
59147 #define IOMUXD_SAI1_RXD_sw_config_SHIFT          (25U)
59148 /*! sw_config - output and input configuration
59149  *  0b01..OPEN_DRAIN
59150  *  0b10..OPEN_DRAIN_INPUT
59151  *  0b11..INOUT
59152  *  0b00..DEFAULT
59153  */
59154 #define IOMUXD_SAI1_RXD_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_sw_config_SHIFT)) & IOMUXD_SAI1_RXD_sw_config_MASK)
59155 #define IOMUXD_SAI1_RXD_mux_mode_MASK            (0x38000000U)
59156 #define IOMUXD_SAI1_RXD_mux_mode_SHIFT           (27U)
59157 /*! mux_mode - mux_mode
59158  *  0b000..ADMA.SAI1.RXD
59159  *  0b001..ADMA.SAI0.RXFS
59160  *  0b010..ADMA.SPI1.CS1
59161  *  0b011..ADMA.LCDIF.D21
59162  *  0b100..LSIO.GPIO0.IO29
59163  */
59164 #define IOMUXD_SAI1_RXD_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_mux_mode_SHIFT)) & IOMUXD_SAI1_RXD_mux_mode_MASK)
59165 #define IOMUXD_SAI1_RXD_update_pad_ctl_MASK      (0x40000000U)
59166 #define IOMUXD_SAI1_RXD_update_pad_ctl_SHIFT     (30U)
59167 /*! update_pad_ctl - update lock for pad control
59168  */
59169 #define IOMUXD_SAI1_RXD_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXD_update_pad_ctl_MASK)
59170 #define IOMUXD_SAI1_RXD_update_mux_mode_MASK     (0x80000000U)
59171 #define IOMUXD_SAI1_RXD_update_mux_mode_SHIFT    (31U)
59172 /*! update_mux_mode - update lock for mux control
59173  */
59174 #define IOMUXD_SAI1_RXD_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXD_update_mux_mode_MASK)
59175 /*! @} */
59176 
59177 /*! @name SAI1_RXC - SAI1_RXC */
59178 /*! @{ */
59179 #define IOMUXD_SAI1_RXC_PDRV_MASK                (0x1U)
59180 #define IOMUXD_SAI1_RXC_PDRV_SHIFT               (0U)
59181 /*! PDRV - Drive
59182  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59183  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59184  */
59185 #define IOMUXD_SAI1_RXC_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_PDRV_SHIFT)) & IOMUXD_SAI1_RXC_PDRV_MASK)
59186 #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_MASK (0x1EU)
59187 #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_SHIFT (1U)
59188 /*! SAI1_RXC_reserved_1_4 - reserved
59189  */
59190 #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_MASK)
59191 #define IOMUXD_SAI1_RXC_PULL_MASK                (0x60U)
59192 #define IOMUXD_SAI1_RXC_PULL_SHIFT               (5U)
59193 /*! PULL - Pull Down Pull Up
59194  *  0b10..pull down
59195  *  0b01..pull up
59196  *  0b00..Prohibited
59197  *  0b11..pull disabled
59198  */
59199 #define IOMUXD_SAI1_RXC_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_PULL_SHIFT)) & IOMUXD_SAI1_RXC_PULL_MASK)
59200 #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_MASK (0x7FF80U)
59201 #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_SHIFT (7U)
59202 /*! SAI1_RXC_reserved_7_18 - reserved
59203  */
59204 #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_MASK)
59205 #define IOMUXD_SAI1_RXC_WAKEUP_CTRL_MASK         (0x380000U)
59206 #define IOMUXD_SAI1_RXC_WAKEUP_CTRL_SHIFT        (19U)
59207 /*! WAKEUP_CTRL - wakeup control
59208  *  0b000..OFF
59209  *  0b001..RESAMPLE
59210  *  0b100..LOW
59211  *  0b111..HIGH
59212  *  0b110..RISE
59213  *  0b101..FALL
59214  */
59215 #define IOMUXD_SAI1_RXC_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXC_WAKEUP_CTRL_MASK)
59216 #define IOMUXD_SAI1_RXC_WAKEUP_MASK_MASK         (0x400000U)
59217 #define IOMUXD_SAI1_RXC_WAKEUP_MASK_SHIFT        (22U)
59218 /*! WAKEUP_MASK - wakeup mask
59219  */
59220 #define IOMUXD_SAI1_RXC_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXC_WAKEUP_MASK_MASK)
59221 #define IOMUXD_SAI1_RXC_lp_config_MASK           (0x1800000U)
59222 #define IOMUXD_SAI1_RXC_lp_config_SHIFT          (23U)
59223 /*! lp_config - lower power configuration
59224  *  0b01..EARLY_ISO
59225  *  0b10..LATE_ISO
59226  *  0b11..LATCH
59227  *  0b00..PASS
59228  */
59229 #define IOMUXD_SAI1_RXC_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_lp_config_SHIFT)) & IOMUXD_SAI1_RXC_lp_config_MASK)
59230 #define IOMUXD_SAI1_RXC_sw_config_MASK           (0x6000000U)
59231 #define IOMUXD_SAI1_RXC_sw_config_SHIFT          (25U)
59232 /*! sw_config - output and input configuration
59233  *  0b01..OPEN_DRAIN
59234  *  0b10..OPEN_DRAIN_INPUT
59235  *  0b11..INOUT
59236  *  0b00..DEFAULT
59237  */
59238 #define IOMUXD_SAI1_RXC_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_sw_config_SHIFT)) & IOMUXD_SAI1_RXC_sw_config_MASK)
59239 #define IOMUXD_SAI1_RXC_mux_mode_MASK            (0x38000000U)
59240 #define IOMUXD_SAI1_RXC_mux_mode_SHIFT           (27U)
59241 /*! mux_mode - mux_mode
59242  *  0b000..ADMA.SAI1.RXC
59243  *  0b001..ADMA.SAI1.TXC
59244  *  0b011..ADMA.LCDIF.D22
59245  *  0b100..LSIO.GPIO0.IO30
59246  */
59247 #define IOMUXD_SAI1_RXC_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_mux_mode_SHIFT)) & IOMUXD_SAI1_RXC_mux_mode_MASK)
59248 #define IOMUXD_SAI1_RXC_update_pad_ctl_MASK      (0x40000000U)
59249 #define IOMUXD_SAI1_RXC_update_pad_ctl_SHIFT     (30U)
59250 /*! update_pad_ctl - update lock for pad control
59251  */
59252 #define IOMUXD_SAI1_RXC_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXC_update_pad_ctl_MASK)
59253 #define IOMUXD_SAI1_RXC_update_mux_mode_MASK     (0x80000000U)
59254 #define IOMUXD_SAI1_RXC_update_mux_mode_SHIFT    (31U)
59255 /*! update_mux_mode - update lock for mux control
59256  */
59257 #define IOMUXD_SAI1_RXC_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXC_update_mux_mode_MASK)
59258 /*! @} */
59259 
59260 /*! @name SAI1_RXFS - SAI1_RXFS */
59261 /*! @{ */
59262 #define IOMUXD_SAI1_RXFS_PDRV_MASK               (0x1U)
59263 #define IOMUXD_SAI1_RXFS_PDRV_SHIFT              (0U)
59264 /*! PDRV - Drive
59265  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59266  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59267  */
59268 #define IOMUXD_SAI1_RXFS_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_PDRV_SHIFT)) & IOMUXD_SAI1_RXFS_PDRV_MASK)
59269 #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_MASK (0x1EU)
59270 #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_SHIFT (1U)
59271 /*! SAI1_RXFS_reserved_1_4 - reserved
59272  */
59273 #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_MASK)
59274 #define IOMUXD_SAI1_RXFS_PULL_MASK               (0x60U)
59275 #define IOMUXD_SAI1_RXFS_PULL_SHIFT              (5U)
59276 /*! PULL - Pull Down Pull Up
59277  *  0b10..pull down
59278  *  0b01..pull up
59279  *  0b00..Prohibited
59280  *  0b11..pull disabled
59281  */
59282 #define IOMUXD_SAI1_RXFS_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_PULL_SHIFT)) & IOMUXD_SAI1_RXFS_PULL_MASK)
59283 #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_MASK (0x7FF80U)
59284 #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_SHIFT (7U)
59285 /*! SAI1_RXFS_reserved_7_18 - reserved
59286  */
59287 #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_MASK)
59288 #define IOMUXD_SAI1_RXFS_WAKEUP_CTRL_MASK        (0x380000U)
59289 #define IOMUXD_SAI1_RXFS_WAKEUP_CTRL_SHIFT       (19U)
59290 /*! WAKEUP_CTRL - wakeup control
59291  *  0b000..OFF
59292  *  0b001..RESAMPLE
59293  *  0b100..LOW
59294  *  0b111..HIGH
59295  *  0b110..RISE
59296  *  0b101..FALL
59297  */
59298 #define IOMUXD_SAI1_RXFS_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXFS_WAKEUP_CTRL_MASK)
59299 #define IOMUXD_SAI1_RXFS_WAKEUP_MASK_MASK        (0x400000U)
59300 #define IOMUXD_SAI1_RXFS_WAKEUP_MASK_SHIFT       (22U)
59301 /*! WAKEUP_MASK - wakeup mask
59302  */
59303 #define IOMUXD_SAI1_RXFS_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXFS_WAKEUP_MASK_MASK)
59304 #define IOMUXD_SAI1_RXFS_lp_config_MASK          (0x1800000U)
59305 #define IOMUXD_SAI1_RXFS_lp_config_SHIFT         (23U)
59306 /*! lp_config - lower power configuration
59307  *  0b01..EARLY_ISO
59308  *  0b10..LATE_ISO
59309  *  0b11..LATCH
59310  *  0b00..PASS
59311  */
59312 #define IOMUXD_SAI1_RXFS_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_lp_config_SHIFT)) & IOMUXD_SAI1_RXFS_lp_config_MASK)
59313 #define IOMUXD_SAI1_RXFS_sw_config_MASK          (0x6000000U)
59314 #define IOMUXD_SAI1_RXFS_sw_config_SHIFT         (25U)
59315 /*! sw_config - output and input configuration
59316  *  0b01..OPEN_DRAIN
59317  *  0b10..OPEN_DRAIN_INPUT
59318  *  0b11..INOUT
59319  *  0b00..DEFAULT
59320  */
59321 #define IOMUXD_SAI1_RXFS_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_sw_config_SHIFT)) & IOMUXD_SAI1_RXFS_sw_config_MASK)
59322 #define IOMUXD_SAI1_RXFS_mux_mode_MASK           (0x38000000U)
59323 #define IOMUXD_SAI1_RXFS_mux_mode_SHIFT          (27U)
59324 /*! mux_mode - mux_mode
59325  *  0b000..ADMA.SAI1.RXFS
59326  *  0b001..ADMA.SAI1.TXFS
59327  *  0b011..ADMA.LCDIF.D23
59328  *  0b100..LSIO.GPIO0.IO31
59329  */
59330 #define IOMUXD_SAI1_RXFS_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_mux_mode_SHIFT)) & IOMUXD_SAI1_RXFS_mux_mode_MASK)
59331 #define IOMUXD_SAI1_RXFS_update_pad_ctl_MASK     (0x40000000U)
59332 #define IOMUXD_SAI1_RXFS_update_pad_ctl_SHIFT    (30U)
59333 /*! update_pad_ctl - update lock for pad control
59334  */
59335 #define IOMUXD_SAI1_RXFS_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXFS_update_pad_ctl_MASK)
59336 #define IOMUXD_SAI1_RXFS_update_mux_mode_MASK    (0x80000000U)
59337 #define IOMUXD_SAI1_RXFS_update_mux_mode_SHIFT   (31U)
59338 /*! update_mux_mode - update lock for mux control
59339  */
59340 #define IOMUXD_SAI1_RXFS_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXFS_update_mux_mode_MASK)
59341 /*! @} */
59342 
59343 /*! @name SPI2_CS0 - SPI2_CS0 */
59344 /*! @{ */
59345 #define IOMUXD_SPI2_CS0_PDRV_MASK                (0x1U)
59346 #define IOMUXD_SPI2_CS0_PDRV_SHIFT               (0U)
59347 /*! PDRV - Drive
59348  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59349  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59350  */
59351 #define IOMUXD_SPI2_CS0_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_PDRV_SHIFT)) & IOMUXD_SPI2_CS0_PDRV_MASK)
59352 #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_MASK (0x1EU)
59353 #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_SHIFT (1U)
59354 /*! SPI2_CS0_reserved_1_4 - reserved
59355  */
59356 #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_MASK)
59357 #define IOMUXD_SPI2_CS0_PULL_MASK                (0x60U)
59358 #define IOMUXD_SPI2_CS0_PULL_SHIFT               (5U)
59359 /*! PULL - Pull Down Pull Up
59360  *  0b10..pull down
59361  *  0b01..pull up
59362  *  0b00..Prohibited
59363  *  0b11..pull disabled
59364  */
59365 #define IOMUXD_SPI2_CS0_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_PULL_SHIFT)) & IOMUXD_SPI2_CS0_PULL_MASK)
59366 #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_MASK (0x7FF80U)
59367 #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_SHIFT (7U)
59368 /*! SPI2_CS0_reserved_7_18 - reserved
59369  */
59370 #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_MASK)
59371 #define IOMUXD_SPI2_CS0_WAKEUP_CTRL_MASK         (0x380000U)
59372 #define IOMUXD_SPI2_CS0_WAKEUP_CTRL_SHIFT        (19U)
59373 /*! WAKEUP_CTRL - wakeup control
59374  *  0b000..OFF
59375  *  0b001..RESAMPLE
59376  *  0b100..LOW
59377  *  0b111..HIGH
59378  *  0b110..RISE
59379  *  0b101..FALL
59380  */
59381 #define IOMUXD_SPI2_CS0_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_CS0_WAKEUP_CTRL_MASK)
59382 #define IOMUXD_SPI2_CS0_WAKEUP_MASK_MASK         (0x400000U)
59383 #define IOMUXD_SPI2_CS0_WAKEUP_MASK_SHIFT        (22U)
59384 /*! WAKEUP_MASK - wakeup mask
59385  */
59386 #define IOMUXD_SPI2_CS0_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_CS0_WAKEUP_MASK_MASK)
59387 #define IOMUXD_SPI2_CS0_lp_config_MASK           (0x1800000U)
59388 #define IOMUXD_SPI2_CS0_lp_config_SHIFT          (23U)
59389 /*! lp_config - lower power configuration
59390  *  0b01..EARLY_ISO
59391  *  0b10..LATE_ISO
59392  *  0b11..LATCH
59393  *  0b00..PASS
59394  */
59395 #define IOMUXD_SPI2_CS0_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_lp_config_SHIFT)) & IOMUXD_SPI2_CS0_lp_config_MASK)
59396 #define IOMUXD_SPI2_CS0_sw_config_MASK           (0x6000000U)
59397 #define IOMUXD_SPI2_CS0_sw_config_SHIFT          (25U)
59398 /*! sw_config - output and input configuration
59399  *  0b01..OPEN_DRAIN
59400  *  0b10..OPEN_DRAIN_INPUT
59401  *  0b11..INOUT
59402  *  0b00..DEFAULT
59403  */
59404 #define IOMUXD_SPI2_CS0_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_sw_config_SHIFT)) & IOMUXD_SPI2_CS0_sw_config_MASK)
59405 #define IOMUXD_SPI2_CS0_mux_mode_MASK            (0x38000000U)
59406 #define IOMUXD_SPI2_CS0_mux_mode_SHIFT           (27U)
59407 /*! mux_mode - mux_mode
59408  *  0b000..ADMA.SPI2.CS0
59409  *  0b100..LSIO.GPIO1.IO00
59410  */
59411 #define IOMUXD_SPI2_CS0_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_mux_mode_SHIFT)) & IOMUXD_SPI2_CS0_mux_mode_MASK)
59412 #define IOMUXD_SPI2_CS0_update_pad_ctl_MASK      (0x40000000U)
59413 #define IOMUXD_SPI2_CS0_update_pad_ctl_SHIFT     (30U)
59414 /*! update_pad_ctl - update lock for pad control
59415  */
59416 #define IOMUXD_SPI2_CS0_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_CS0_update_pad_ctl_MASK)
59417 #define IOMUXD_SPI2_CS0_update_mux_mode_MASK     (0x80000000U)
59418 #define IOMUXD_SPI2_CS0_update_mux_mode_SHIFT    (31U)
59419 /*! update_mux_mode - update lock for mux control
59420  */
59421 #define IOMUXD_SPI2_CS0_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI2_CS0_update_mux_mode_MASK)
59422 /*! @} */
59423 
59424 /*! @name SPI2_SDO - SPI2_SDO */
59425 /*! @{ */
59426 #define IOMUXD_SPI2_SDO_PDRV_MASK                (0x1U)
59427 #define IOMUXD_SPI2_SDO_PDRV_SHIFT               (0U)
59428 /*! PDRV - Drive
59429  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59430  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59431  */
59432 #define IOMUXD_SPI2_SDO_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_PDRV_SHIFT)) & IOMUXD_SPI2_SDO_PDRV_MASK)
59433 #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_MASK (0x1EU)
59434 #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_SHIFT (1U)
59435 /*! SPI2_SDO_reserved_1_4 - reserved
59436  */
59437 #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_MASK)
59438 #define IOMUXD_SPI2_SDO_PULL_MASK                (0x60U)
59439 #define IOMUXD_SPI2_SDO_PULL_SHIFT               (5U)
59440 /*! PULL - Pull Down Pull Up
59441  *  0b10..pull down
59442  *  0b01..pull up
59443  *  0b00..Prohibited
59444  *  0b11..pull disabled
59445  */
59446 #define IOMUXD_SPI2_SDO_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_PULL_SHIFT)) & IOMUXD_SPI2_SDO_PULL_MASK)
59447 #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_MASK (0x7FF80U)
59448 #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_SHIFT (7U)
59449 /*! SPI2_SDO_reserved_7_18 - reserved
59450  */
59451 #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_MASK)
59452 #define IOMUXD_SPI2_SDO_WAKEUP_CTRL_MASK         (0x380000U)
59453 #define IOMUXD_SPI2_SDO_WAKEUP_CTRL_SHIFT        (19U)
59454 /*! WAKEUP_CTRL - wakeup control
59455  *  0b000..OFF
59456  *  0b001..RESAMPLE
59457  *  0b100..LOW
59458  *  0b111..HIGH
59459  *  0b110..RISE
59460  *  0b101..FALL
59461  */
59462 #define IOMUXD_SPI2_SDO_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SDO_WAKEUP_CTRL_MASK)
59463 #define IOMUXD_SPI2_SDO_WAKEUP_MASK_MASK         (0x400000U)
59464 #define IOMUXD_SPI2_SDO_WAKEUP_MASK_SHIFT        (22U)
59465 /*! WAKEUP_MASK - wakeup mask
59466  */
59467 #define IOMUXD_SPI2_SDO_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SDO_WAKEUP_MASK_MASK)
59468 #define IOMUXD_SPI2_SDO_lp_config_MASK           (0x1800000U)
59469 #define IOMUXD_SPI2_SDO_lp_config_SHIFT          (23U)
59470 /*! lp_config - lower power configuration
59471  *  0b01..EARLY_ISO
59472  *  0b10..LATE_ISO
59473  *  0b11..LATCH
59474  *  0b00..PASS
59475  */
59476 #define IOMUXD_SPI2_SDO_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_lp_config_SHIFT)) & IOMUXD_SPI2_SDO_lp_config_MASK)
59477 #define IOMUXD_SPI2_SDO_sw_config_MASK           (0x6000000U)
59478 #define IOMUXD_SPI2_SDO_sw_config_SHIFT          (25U)
59479 /*! sw_config - output and input configuration
59480  *  0b01..OPEN_DRAIN
59481  *  0b10..OPEN_DRAIN_INPUT
59482  *  0b11..INOUT
59483  *  0b00..DEFAULT
59484  */
59485 #define IOMUXD_SPI2_SDO_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_sw_config_SHIFT)) & IOMUXD_SPI2_SDO_sw_config_MASK)
59486 #define IOMUXD_SPI2_SDO_mux_mode_MASK            (0x38000000U)
59487 #define IOMUXD_SPI2_SDO_mux_mode_SHIFT           (27U)
59488 /*! mux_mode - mux_mode
59489  *  0b000..ADMA.SPI2.SDO
59490  *  0b100..LSIO.GPIO1.IO01
59491  */
59492 #define IOMUXD_SPI2_SDO_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_mux_mode_SHIFT)) & IOMUXD_SPI2_SDO_mux_mode_MASK)
59493 #define IOMUXD_SPI2_SDO_update_pad_ctl_MASK      (0x40000000U)
59494 #define IOMUXD_SPI2_SDO_update_pad_ctl_SHIFT     (30U)
59495 /*! update_pad_ctl - update lock for pad control
59496  */
59497 #define IOMUXD_SPI2_SDO_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SDO_update_pad_ctl_MASK)
59498 #define IOMUXD_SPI2_SDO_update_mux_mode_MASK     (0x80000000U)
59499 #define IOMUXD_SPI2_SDO_update_mux_mode_SHIFT    (31U)
59500 /*! update_mux_mode - update lock for mux control
59501  */
59502 #define IOMUXD_SPI2_SDO_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SDO_update_mux_mode_MASK)
59503 /*! @} */
59504 
59505 /*! @name SPI2_SDI - SPI2_SDI */
59506 /*! @{ */
59507 #define IOMUXD_SPI2_SDI_PDRV_MASK                (0x1U)
59508 #define IOMUXD_SPI2_SDI_PDRV_SHIFT               (0U)
59509 /*! PDRV - Drive
59510  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59511  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59512  */
59513 #define IOMUXD_SPI2_SDI_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_PDRV_SHIFT)) & IOMUXD_SPI2_SDI_PDRV_MASK)
59514 #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_MASK (0x1EU)
59515 #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_SHIFT (1U)
59516 /*! SPI2_SDI_reserved_1_4 - reserved
59517  */
59518 #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_MASK)
59519 #define IOMUXD_SPI2_SDI_PULL_MASK                (0x60U)
59520 #define IOMUXD_SPI2_SDI_PULL_SHIFT               (5U)
59521 /*! PULL - Pull Down Pull Up
59522  *  0b10..pull down
59523  *  0b01..pull up
59524  *  0b00..Prohibited
59525  *  0b11..pull disabled
59526  */
59527 #define IOMUXD_SPI2_SDI_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_PULL_SHIFT)) & IOMUXD_SPI2_SDI_PULL_MASK)
59528 #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_MASK (0x7FF80U)
59529 #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_SHIFT (7U)
59530 /*! SPI2_SDI_reserved_7_18 - reserved
59531  */
59532 #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_MASK)
59533 #define IOMUXD_SPI2_SDI_WAKEUP_CTRL_MASK         (0x380000U)
59534 #define IOMUXD_SPI2_SDI_WAKEUP_CTRL_SHIFT        (19U)
59535 /*! WAKEUP_CTRL - wakeup control
59536  *  0b000..OFF
59537  *  0b001..RESAMPLE
59538  *  0b100..LOW
59539  *  0b111..HIGH
59540  *  0b110..RISE
59541  *  0b101..FALL
59542  */
59543 #define IOMUXD_SPI2_SDI_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SDI_WAKEUP_CTRL_MASK)
59544 #define IOMUXD_SPI2_SDI_WAKEUP_MASK_MASK         (0x400000U)
59545 #define IOMUXD_SPI2_SDI_WAKEUP_MASK_SHIFT        (22U)
59546 /*! WAKEUP_MASK - wakeup mask
59547  */
59548 #define IOMUXD_SPI2_SDI_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SDI_WAKEUP_MASK_MASK)
59549 #define IOMUXD_SPI2_SDI_lp_config_MASK           (0x1800000U)
59550 #define IOMUXD_SPI2_SDI_lp_config_SHIFT          (23U)
59551 /*! lp_config - lower power configuration
59552  *  0b01..EARLY_ISO
59553  *  0b10..LATE_ISO
59554  *  0b11..LATCH
59555  *  0b00..PASS
59556  */
59557 #define IOMUXD_SPI2_SDI_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_lp_config_SHIFT)) & IOMUXD_SPI2_SDI_lp_config_MASK)
59558 #define IOMUXD_SPI2_SDI_sw_config_MASK           (0x6000000U)
59559 #define IOMUXD_SPI2_SDI_sw_config_SHIFT          (25U)
59560 /*! sw_config - output and input configuration
59561  *  0b01..OPEN_DRAIN
59562  *  0b10..OPEN_DRAIN_INPUT
59563  *  0b11..INOUT
59564  *  0b00..DEFAULT
59565  */
59566 #define IOMUXD_SPI2_SDI_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_sw_config_SHIFT)) & IOMUXD_SPI2_SDI_sw_config_MASK)
59567 #define IOMUXD_SPI2_SDI_mux_mode_MASK            (0x38000000U)
59568 #define IOMUXD_SPI2_SDI_mux_mode_SHIFT           (27U)
59569 /*! mux_mode - mux_mode
59570  *  0b000..ADMA.SPI2.SDI
59571  *  0b100..LSIO.GPIO1.IO02
59572  */
59573 #define IOMUXD_SPI2_SDI_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_mux_mode_SHIFT)) & IOMUXD_SPI2_SDI_mux_mode_MASK)
59574 #define IOMUXD_SPI2_SDI_update_pad_ctl_MASK      (0x40000000U)
59575 #define IOMUXD_SPI2_SDI_update_pad_ctl_SHIFT     (30U)
59576 /*! update_pad_ctl - update lock for pad control
59577  */
59578 #define IOMUXD_SPI2_SDI_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SDI_update_pad_ctl_MASK)
59579 #define IOMUXD_SPI2_SDI_update_mux_mode_MASK     (0x80000000U)
59580 #define IOMUXD_SPI2_SDI_update_mux_mode_SHIFT    (31U)
59581 /*! update_mux_mode - update lock for mux control
59582  */
59583 #define IOMUXD_SPI2_SDI_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SDI_update_mux_mode_MASK)
59584 /*! @} */
59585 
59586 /*! @name SPI2_SCK - SPI2_SCK */
59587 /*! @{ */
59588 #define IOMUXD_SPI2_SCK_PDRV_MASK                (0x1U)
59589 #define IOMUXD_SPI2_SCK_PDRV_SHIFT               (0U)
59590 /*! PDRV - Drive
59591  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59592  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59593  */
59594 #define IOMUXD_SPI2_SCK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_PDRV_SHIFT)) & IOMUXD_SPI2_SCK_PDRV_MASK)
59595 #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_MASK (0x1EU)
59596 #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_SHIFT (1U)
59597 /*! SPI2_SCK_reserved_1_4 - reserved
59598  */
59599 #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_MASK)
59600 #define IOMUXD_SPI2_SCK_PULL_MASK                (0x60U)
59601 #define IOMUXD_SPI2_SCK_PULL_SHIFT               (5U)
59602 /*! PULL - Pull Down Pull Up
59603  *  0b10..pull down
59604  *  0b01..pull up
59605  *  0b00..Prohibited
59606  *  0b11..pull disabled
59607  */
59608 #define IOMUXD_SPI2_SCK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_PULL_SHIFT)) & IOMUXD_SPI2_SCK_PULL_MASK)
59609 #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_MASK (0x7FF80U)
59610 #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_SHIFT (7U)
59611 /*! SPI2_SCK_reserved_7_18 - reserved
59612  */
59613 #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_MASK)
59614 #define IOMUXD_SPI2_SCK_WAKEUP_CTRL_MASK         (0x380000U)
59615 #define IOMUXD_SPI2_SCK_WAKEUP_CTRL_SHIFT        (19U)
59616 /*! WAKEUP_CTRL - wakeup control
59617  *  0b000..OFF
59618  *  0b001..RESAMPLE
59619  *  0b100..LOW
59620  *  0b111..HIGH
59621  *  0b110..RISE
59622  *  0b101..FALL
59623  */
59624 #define IOMUXD_SPI2_SCK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SCK_WAKEUP_CTRL_MASK)
59625 #define IOMUXD_SPI2_SCK_WAKEUP_MASK_MASK         (0x400000U)
59626 #define IOMUXD_SPI2_SCK_WAKEUP_MASK_SHIFT        (22U)
59627 /*! WAKEUP_MASK - wakeup mask
59628  */
59629 #define IOMUXD_SPI2_SCK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SCK_WAKEUP_MASK_MASK)
59630 #define IOMUXD_SPI2_SCK_lp_config_MASK           (0x1800000U)
59631 #define IOMUXD_SPI2_SCK_lp_config_SHIFT          (23U)
59632 /*! lp_config - lower power configuration
59633  *  0b01..EARLY_ISO
59634  *  0b10..LATE_ISO
59635  *  0b11..LATCH
59636  *  0b00..PASS
59637  */
59638 #define IOMUXD_SPI2_SCK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_lp_config_SHIFT)) & IOMUXD_SPI2_SCK_lp_config_MASK)
59639 #define IOMUXD_SPI2_SCK_sw_config_MASK           (0x6000000U)
59640 #define IOMUXD_SPI2_SCK_sw_config_SHIFT          (25U)
59641 /*! sw_config - output and input configuration
59642  *  0b01..OPEN_DRAIN
59643  *  0b10..OPEN_DRAIN_INPUT
59644  *  0b11..INOUT
59645  *  0b00..DEFAULT
59646  */
59647 #define IOMUXD_SPI2_SCK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_sw_config_SHIFT)) & IOMUXD_SPI2_SCK_sw_config_MASK)
59648 #define IOMUXD_SPI2_SCK_mux_mode_MASK            (0x38000000U)
59649 #define IOMUXD_SPI2_SCK_mux_mode_SHIFT           (27U)
59650 /*! mux_mode - mux_mode
59651  *  0b000..ADMA.SPI2.SCK
59652  *  0b100..LSIO.GPIO1.IO03
59653  */
59654 #define IOMUXD_SPI2_SCK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_mux_mode_SHIFT)) & IOMUXD_SPI2_SCK_mux_mode_MASK)
59655 #define IOMUXD_SPI2_SCK_update_pad_ctl_MASK      (0x40000000U)
59656 #define IOMUXD_SPI2_SCK_update_pad_ctl_SHIFT     (30U)
59657 /*! update_pad_ctl - update lock for pad control
59658  */
59659 #define IOMUXD_SPI2_SCK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SCK_update_pad_ctl_MASK)
59660 #define IOMUXD_SPI2_SCK_update_mux_mode_MASK     (0x80000000U)
59661 #define IOMUXD_SPI2_SCK_update_mux_mode_SHIFT    (31U)
59662 /*! update_mux_mode - update lock for mux control
59663  */
59664 #define IOMUXD_SPI2_SCK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SCK_update_mux_mode_MASK)
59665 /*! @} */
59666 
59667 /*! @name SPI0_SCK - SPI0_SCK */
59668 /*! @{ */
59669 #define IOMUXD_SPI0_SCK_PDRV_MASK                (0x1U)
59670 #define IOMUXD_SPI0_SCK_PDRV_SHIFT               (0U)
59671 /*! PDRV - Drive
59672  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59673  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59674  */
59675 #define IOMUXD_SPI0_SCK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_PDRV_SHIFT)) & IOMUXD_SPI0_SCK_PDRV_MASK)
59676 #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_MASK (0x1EU)
59677 #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_SHIFT (1U)
59678 /*! SPI0_SCK_reserved_1_4 - reserved
59679  */
59680 #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_MASK)
59681 #define IOMUXD_SPI0_SCK_PULL_MASK                (0x60U)
59682 #define IOMUXD_SPI0_SCK_PULL_SHIFT               (5U)
59683 /*! PULL - Pull Down Pull Up
59684  *  0b10..pull down
59685  *  0b01..pull up
59686  *  0b00..Prohibited
59687  *  0b11..pull disabled
59688  */
59689 #define IOMUXD_SPI0_SCK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_PULL_SHIFT)) & IOMUXD_SPI0_SCK_PULL_MASK)
59690 #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_MASK (0x7FF80U)
59691 #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_SHIFT (7U)
59692 /*! SPI0_SCK_reserved_7_18 - reserved
59693  */
59694 #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_MASK)
59695 #define IOMUXD_SPI0_SCK_WAKEUP_CTRL_MASK         (0x380000U)
59696 #define IOMUXD_SPI0_SCK_WAKEUP_CTRL_SHIFT        (19U)
59697 /*! WAKEUP_CTRL - wakeup control
59698  *  0b000..OFF
59699  *  0b001..RESAMPLE
59700  *  0b100..LOW
59701  *  0b111..HIGH
59702  *  0b110..RISE
59703  *  0b101..FALL
59704  */
59705 #define IOMUXD_SPI0_SCK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SCK_WAKEUP_CTRL_MASK)
59706 #define IOMUXD_SPI0_SCK_WAKEUP_MASK_MASK         (0x400000U)
59707 #define IOMUXD_SPI0_SCK_WAKEUP_MASK_SHIFT        (22U)
59708 /*! WAKEUP_MASK - wakeup mask
59709  */
59710 #define IOMUXD_SPI0_SCK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SCK_WAKEUP_MASK_MASK)
59711 #define IOMUXD_SPI0_SCK_lp_config_MASK           (0x1800000U)
59712 #define IOMUXD_SPI0_SCK_lp_config_SHIFT          (23U)
59713 /*! lp_config - lower power configuration
59714  *  0b01..EARLY_ISO
59715  *  0b10..LATE_ISO
59716  *  0b11..LATCH
59717  *  0b00..PASS
59718  */
59719 #define IOMUXD_SPI0_SCK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_lp_config_SHIFT)) & IOMUXD_SPI0_SCK_lp_config_MASK)
59720 #define IOMUXD_SPI0_SCK_sw_config_MASK           (0x6000000U)
59721 #define IOMUXD_SPI0_SCK_sw_config_SHIFT          (25U)
59722 /*! sw_config - output and input configuration
59723  *  0b01..OPEN_DRAIN
59724  *  0b10..OPEN_DRAIN_INPUT
59725  *  0b11..INOUT
59726  *  0b00..DEFAULT
59727  */
59728 #define IOMUXD_SPI0_SCK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_sw_config_SHIFT)) & IOMUXD_SPI0_SCK_sw_config_MASK)
59729 #define IOMUXD_SPI0_SCK_mux_mode_MASK            (0x38000000U)
59730 #define IOMUXD_SPI0_SCK_mux_mode_SHIFT           (27U)
59731 /*! mux_mode - mux_mode
59732  *  0b000..ADMA.SPI0.SCK
59733  *  0b001..ADMA.SAI0.TXC
59734  *  0b010..M40.I2C0.SCL
59735  *  0b011..M40.GPIO0.IO00
59736  *  0b100..LSIO.GPIO1.IO04
59737  */
59738 #define IOMUXD_SPI0_SCK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_mux_mode_SHIFT)) & IOMUXD_SPI0_SCK_mux_mode_MASK)
59739 #define IOMUXD_SPI0_SCK_update_pad_ctl_MASK      (0x40000000U)
59740 #define IOMUXD_SPI0_SCK_update_pad_ctl_SHIFT     (30U)
59741 /*! update_pad_ctl - update lock for pad control
59742  */
59743 #define IOMUXD_SPI0_SCK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SCK_update_pad_ctl_MASK)
59744 #define IOMUXD_SPI0_SCK_update_mux_mode_MASK     (0x80000000U)
59745 #define IOMUXD_SPI0_SCK_update_mux_mode_SHIFT    (31U)
59746 /*! update_mux_mode - update lock for mux control
59747  */
59748 #define IOMUXD_SPI0_SCK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SCK_update_mux_mode_MASK)
59749 /*! @} */
59750 
59751 /*! @name SPI0_SDI - SPI0_SDI */
59752 /*! @{ */
59753 #define IOMUXD_SPI0_SDI_PDRV_MASK                (0x1U)
59754 #define IOMUXD_SPI0_SDI_PDRV_SHIFT               (0U)
59755 /*! PDRV - Drive
59756  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59757  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59758  */
59759 #define IOMUXD_SPI0_SDI_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_PDRV_SHIFT)) & IOMUXD_SPI0_SDI_PDRV_MASK)
59760 #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_MASK (0x1EU)
59761 #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_SHIFT (1U)
59762 /*! SPI0_SDI_reserved_1_4 - reserved
59763  */
59764 #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_MASK)
59765 #define IOMUXD_SPI0_SDI_PULL_MASK                (0x60U)
59766 #define IOMUXD_SPI0_SDI_PULL_SHIFT               (5U)
59767 /*! PULL - Pull Down Pull Up
59768  *  0b10..pull down
59769  *  0b01..pull up
59770  *  0b00..Prohibited
59771  *  0b11..pull disabled
59772  */
59773 #define IOMUXD_SPI0_SDI_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_PULL_SHIFT)) & IOMUXD_SPI0_SDI_PULL_MASK)
59774 #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_MASK (0x7FF80U)
59775 #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_SHIFT (7U)
59776 /*! SPI0_SDI_reserved_7_18 - reserved
59777  */
59778 #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_MASK)
59779 #define IOMUXD_SPI0_SDI_WAKEUP_CTRL_MASK         (0x380000U)
59780 #define IOMUXD_SPI0_SDI_WAKEUP_CTRL_SHIFT        (19U)
59781 /*! WAKEUP_CTRL - wakeup control
59782  *  0b000..OFF
59783  *  0b001..RESAMPLE
59784  *  0b100..LOW
59785  *  0b111..HIGH
59786  *  0b110..RISE
59787  *  0b101..FALL
59788  */
59789 #define IOMUXD_SPI0_SDI_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SDI_WAKEUP_CTRL_MASK)
59790 #define IOMUXD_SPI0_SDI_WAKEUP_MASK_MASK         (0x400000U)
59791 #define IOMUXD_SPI0_SDI_WAKEUP_MASK_SHIFT        (22U)
59792 /*! WAKEUP_MASK - wakeup mask
59793  */
59794 #define IOMUXD_SPI0_SDI_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SDI_WAKEUP_MASK_MASK)
59795 #define IOMUXD_SPI0_SDI_lp_config_MASK           (0x1800000U)
59796 #define IOMUXD_SPI0_SDI_lp_config_SHIFT          (23U)
59797 /*! lp_config - lower power configuration
59798  *  0b01..EARLY_ISO
59799  *  0b10..LATE_ISO
59800  *  0b11..LATCH
59801  *  0b00..PASS
59802  */
59803 #define IOMUXD_SPI0_SDI_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_lp_config_SHIFT)) & IOMUXD_SPI0_SDI_lp_config_MASK)
59804 #define IOMUXD_SPI0_SDI_sw_config_MASK           (0x6000000U)
59805 #define IOMUXD_SPI0_SDI_sw_config_SHIFT          (25U)
59806 /*! sw_config - output and input configuration
59807  *  0b01..OPEN_DRAIN
59808  *  0b10..OPEN_DRAIN_INPUT
59809  *  0b11..INOUT
59810  *  0b00..DEFAULT
59811  */
59812 #define IOMUXD_SPI0_SDI_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_sw_config_SHIFT)) & IOMUXD_SPI0_SDI_sw_config_MASK)
59813 #define IOMUXD_SPI0_SDI_mux_mode_MASK            (0x38000000U)
59814 #define IOMUXD_SPI0_SDI_mux_mode_SHIFT           (27U)
59815 /*! mux_mode - mux_mode
59816  *  0b000..ADMA.SPI0.SDI
59817  *  0b001..ADMA.SAI0.TXD
59818  *  0b010..M40.TPM0.CH0
59819  *  0b011..M40.GPIO0.IO02
59820  *  0b100..LSIO.GPIO1.IO05
59821  */
59822 #define IOMUXD_SPI0_SDI_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_mux_mode_SHIFT)) & IOMUXD_SPI0_SDI_mux_mode_MASK)
59823 #define IOMUXD_SPI0_SDI_update_pad_ctl_MASK      (0x40000000U)
59824 #define IOMUXD_SPI0_SDI_update_pad_ctl_SHIFT     (30U)
59825 /*! update_pad_ctl - update lock for pad control
59826  */
59827 #define IOMUXD_SPI0_SDI_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SDI_update_pad_ctl_MASK)
59828 #define IOMUXD_SPI0_SDI_update_mux_mode_MASK     (0x80000000U)
59829 #define IOMUXD_SPI0_SDI_update_mux_mode_SHIFT    (31U)
59830 /*! update_mux_mode - update lock for mux control
59831  */
59832 #define IOMUXD_SPI0_SDI_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SDI_update_mux_mode_MASK)
59833 /*! @} */
59834 
59835 /*! @name SPI0_SDO - SPI0_SDO */
59836 /*! @{ */
59837 #define IOMUXD_SPI0_SDO_PDRV_MASK                (0x1U)
59838 #define IOMUXD_SPI0_SDO_PDRV_SHIFT               (0U)
59839 /*! PDRV - Drive
59840  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59841  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59842  */
59843 #define IOMUXD_SPI0_SDO_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_PDRV_SHIFT)) & IOMUXD_SPI0_SDO_PDRV_MASK)
59844 #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_MASK (0x1EU)
59845 #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_SHIFT (1U)
59846 /*! SPI0_SDO_reserved_1_4 - reserved
59847  */
59848 #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_MASK)
59849 #define IOMUXD_SPI0_SDO_PULL_MASK                (0x60U)
59850 #define IOMUXD_SPI0_SDO_PULL_SHIFT               (5U)
59851 /*! PULL - Pull Down Pull Up
59852  *  0b10..pull down
59853  *  0b01..pull up
59854  *  0b00..Prohibited
59855  *  0b11..pull disabled
59856  */
59857 #define IOMUXD_SPI0_SDO_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_PULL_SHIFT)) & IOMUXD_SPI0_SDO_PULL_MASK)
59858 #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_MASK (0x7FF80U)
59859 #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_SHIFT (7U)
59860 /*! SPI0_SDO_reserved_7_18 - reserved
59861  */
59862 #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_MASK)
59863 #define IOMUXD_SPI0_SDO_WAKEUP_CTRL_MASK         (0x380000U)
59864 #define IOMUXD_SPI0_SDO_WAKEUP_CTRL_SHIFT        (19U)
59865 /*! WAKEUP_CTRL - wakeup control
59866  *  0b000..OFF
59867  *  0b001..RESAMPLE
59868  *  0b100..LOW
59869  *  0b111..HIGH
59870  *  0b110..RISE
59871  *  0b101..FALL
59872  */
59873 #define IOMUXD_SPI0_SDO_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SDO_WAKEUP_CTRL_MASK)
59874 #define IOMUXD_SPI0_SDO_WAKEUP_MASK_MASK         (0x400000U)
59875 #define IOMUXD_SPI0_SDO_WAKEUP_MASK_SHIFT        (22U)
59876 /*! WAKEUP_MASK - wakeup mask
59877  */
59878 #define IOMUXD_SPI0_SDO_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SDO_WAKEUP_MASK_MASK)
59879 #define IOMUXD_SPI0_SDO_lp_config_MASK           (0x1800000U)
59880 #define IOMUXD_SPI0_SDO_lp_config_SHIFT          (23U)
59881 /*! lp_config - lower power configuration
59882  *  0b01..EARLY_ISO
59883  *  0b10..LATE_ISO
59884  *  0b11..LATCH
59885  *  0b00..PASS
59886  */
59887 #define IOMUXD_SPI0_SDO_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_lp_config_SHIFT)) & IOMUXD_SPI0_SDO_lp_config_MASK)
59888 #define IOMUXD_SPI0_SDO_sw_config_MASK           (0x6000000U)
59889 #define IOMUXD_SPI0_SDO_sw_config_SHIFT          (25U)
59890 /*! sw_config - output and input configuration
59891  *  0b01..OPEN_DRAIN
59892  *  0b10..OPEN_DRAIN_INPUT
59893  *  0b11..INOUT
59894  *  0b00..DEFAULT
59895  */
59896 #define IOMUXD_SPI0_SDO_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_sw_config_SHIFT)) & IOMUXD_SPI0_SDO_sw_config_MASK)
59897 #define IOMUXD_SPI0_SDO_mux_mode_MASK            (0x38000000U)
59898 #define IOMUXD_SPI0_SDO_mux_mode_SHIFT           (27U)
59899 /*! mux_mode - mux_mode
59900  *  0b000..ADMA.SPI0.SDO
59901  *  0b001..ADMA.SAI0.TXFS
59902  *  0b010..M40.I2C0.SDA
59903  *  0b011..M40.GPIO0.IO01
59904  *  0b100..LSIO.GPIO1.IO06
59905  */
59906 #define IOMUXD_SPI0_SDO_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_mux_mode_SHIFT)) & IOMUXD_SPI0_SDO_mux_mode_MASK)
59907 #define IOMUXD_SPI0_SDO_update_pad_ctl_MASK      (0x40000000U)
59908 #define IOMUXD_SPI0_SDO_update_pad_ctl_SHIFT     (30U)
59909 /*! update_pad_ctl - update lock for pad control
59910  */
59911 #define IOMUXD_SPI0_SDO_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SDO_update_pad_ctl_MASK)
59912 #define IOMUXD_SPI0_SDO_update_mux_mode_MASK     (0x80000000U)
59913 #define IOMUXD_SPI0_SDO_update_mux_mode_SHIFT    (31U)
59914 /*! update_mux_mode - update lock for mux control
59915  */
59916 #define IOMUXD_SPI0_SDO_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SDO_update_mux_mode_MASK)
59917 /*! @} */
59918 
59919 /*! @name SPI0_CS1 - SPI0_CS1 */
59920 /*! @{ */
59921 #define IOMUXD_SPI0_CS1_PDRV_MASK                (0x1U)
59922 #define IOMUXD_SPI0_CS1_PDRV_SHIFT               (0U)
59923 /*! PDRV - Drive
59924  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59925  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59926  */
59927 #define IOMUXD_SPI0_CS1_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_PDRV_SHIFT)) & IOMUXD_SPI0_CS1_PDRV_MASK)
59928 #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_MASK (0x1EU)
59929 #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_SHIFT (1U)
59930 /*! SPI0_CS1_reserved_1_4 - reserved
59931  */
59932 #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_SHIFT)) & IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_MASK)
59933 #define IOMUXD_SPI0_CS1_PULL_MASK                (0x60U)
59934 #define IOMUXD_SPI0_CS1_PULL_SHIFT               (5U)
59935 /*! PULL - Pull Down Pull Up
59936  *  0b10..pull down
59937  *  0b01..pull up
59938  *  0b00..Prohibited
59939  *  0b11..pull disabled
59940  */
59941 #define IOMUXD_SPI0_CS1_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_PULL_SHIFT)) & IOMUXD_SPI0_CS1_PULL_MASK)
59942 #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_MASK (0x7FF80U)
59943 #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_SHIFT (7U)
59944 /*! SPI0_CS1_reserved_7_18 - reserved
59945  */
59946 #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_SHIFT)) & IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_MASK)
59947 #define IOMUXD_SPI0_CS1_WAKEUP_CTRL_MASK         (0x380000U)
59948 #define IOMUXD_SPI0_CS1_WAKEUP_CTRL_SHIFT        (19U)
59949 /*! WAKEUP_CTRL - wakeup control
59950  *  0b000..OFF
59951  *  0b001..RESAMPLE
59952  *  0b100..LOW
59953  *  0b111..HIGH
59954  *  0b110..RISE
59955  *  0b101..FALL
59956  */
59957 #define IOMUXD_SPI0_CS1_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_CS1_WAKEUP_CTRL_MASK)
59958 #define IOMUXD_SPI0_CS1_WAKEUP_MASK_MASK         (0x400000U)
59959 #define IOMUXD_SPI0_CS1_WAKEUP_MASK_SHIFT        (22U)
59960 /*! WAKEUP_MASK - wakeup mask
59961  */
59962 #define IOMUXD_SPI0_CS1_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_CS1_WAKEUP_MASK_MASK)
59963 #define IOMUXD_SPI0_CS1_lp_config_MASK           (0x1800000U)
59964 #define IOMUXD_SPI0_CS1_lp_config_SHIFT          (23U)
59965 /*! lp_config - lower power configuration
59966  *  0b01..EARLY_ISO
59967  *  0b10..LATE_ISO
59968  *  0b11..LATCH
59969  *  0b00..PASS
59970  */
59971 #define IOMUXD_SPI0_CS1_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_lp_config_SHIFT)) & IOMUXD_SPI0_CS1_lp_config_MASK)
59972 #define IOMUXD_SPI0_CS1_sw_config_MASK           (0x6000000U)
59973 #define IOMUXD_SPI0_CS1_sw_config_SHIFT          (25U)
59974 /*! sw_config - output and input configuration
59975  *  0b01..OPEN_DRAIN
59976  *  0b10..OPEN_DRAIN_INPUT
59977  *  0b11..INOUT
59978  *  0b00..DEFAULT
59979  */
59980 #define IOMUXD_SPI0_CS1_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_sw_config_SHIFT)) & IOMUXD_SPI0_CS1_sw_config_MASK)
59981 #define IOMUXD_SPI0_CS1_mux_mode_MASK            (0x38000000U)
59982 #define IOMUXD_SPI0_CS1_mux_mode_SHIFT           (27U)
59983 /*! mux_mode - mux_mode
59984  *  0b000..ADMA.SPI0.CS1
59985  *  0b001..ADMA.SAI0.RXC
59986  *  0b010..ADMA.SAI1.TXD
59987  *  0b011..ADMA.LCD_PWM0.OUT
59988  *  0b100..LSIO.GPIO1.IO07
59989  */
59990 #define IOMUXD_SPI0_CS1_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_mux_mode_SHIFT)) & IOMUXD_SPI0_CS1_mux_mode_MASK)
59991 #define IOMUXD_SPI0_CS1_update_pad_ctl_MASK      (0x40000000U)
59992 #define IOMUXD_SPI0_CS1_update_pad_ctl_SHIFT     (30U)
59993 /*! update_pad_ctl - update lock for pad control
59994  */
59995 #define IOMUXD_SPI0_CS1_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_CS1_update_pad_ctl_MASK)
59996 #define IOMUXD_SPI0_CS1_update_mux_mode_MASK     (0x80000000U)
59997 #define IOMUXD_SPI0_CS1_update_mux_mode_SHIFT    (31U)
59998 /*! update_mux_mode - update lock for mux control
59999  */
60000 #define IOMUXD_SPI0_CS1_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_update_mux_mode_SHIFT)) & IOMUXD_SPI0_CS1_update_mux_mode_MASK)
60001 /*! @} */
60002 
60003 /*! @name IOMUXD_GROUP_2_0 - na */
60004 /*! @{ */
60005 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_MASK    (0x1U)
60006 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_SHIFT   (0U)
60007 /*! SAI0_TXD - wakeup from SAI0_TXD
60008  */
60009 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_MASK)
60010 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_MASK    (0x2U)
60011 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_SHIFT   (1U)
60012 /*! SAI0_TXC - wakeup from SAI0_TXC
60013  */
60014 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_MASK)
60015 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_MASK    (0x4U)
60016 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_SHIFT   (2U)
60017 /*! SAI0_RXD - wakeup from SAI0_RXD
60018  */
60019 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_MASK)
60020 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_MASK   (0x8U)
60021 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_SHIFT  (3U)
60022 /*! SAI0_TXFS - wakeup from SAI0_TXFS
60023  */
60024 #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_MASK)
60025 #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_MASK    (0x10U)
60026 #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_SHIFT   (4U)
60027 /*! SAI1_RXD - wakeup from SAI1_RXD
60028  */
60029 #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_MASK)
60030 #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_MASK    (0x20U)
60031 #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_SHIFT   (5U)
60032 /*! SAI1_RXC - wakeup from SAI1_RXC
60033  */
60034 #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_MASK)
60035 #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_MASK   (0x40U)
60036 #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_SHIFT  (6U)
60037 /*! SAI1_RXFS - wakeup from SAI1_RXFS
60038  */
60039 #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_MASK)
60040 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_MASK    (0x80U)
60041 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_SHIFT   (7U)
60042 /*! SPI2_CS0 - wakeup from SPI2_CS0
60043  */
60044 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_MASK)
60045 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_MASK    (0x100U)
60046 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_SHIFT   (8U)
60047 /*! SPI2_SDO - wakeup from SPI2_SDO
60048  */
60049 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_MASK)
60050 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_MASK    (0x200U)
60051 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_SHIFT   (9U)
60052 /*! SPI2_SDI - wakeup from SPI2_SDI
60053  */
60054 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_MASK)
60055 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_MASK    (0x400U)
60056 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_SHIFT   (10U)
60057 /*! SPI2_SCK - wakeup from SPI2_SCK
60058  */
60059 #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_MASK)
60060 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_MASK    (0x800U)
60061 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_SHIFT   (11U)
60062 /*! SPI0_SCK - wakeup from SPI0_SCK
60063  */
60064 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_MASK)
60065 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_MASK    (0x1000U)
60066 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_SHIFT   (12U)
60067 /*! SPI0_SDI - wakeup from SPI0_SDI
60068  */
60069 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_MASK)
60070 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_MASK    (0x2000U)
60071 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_SHIFT   (13U)
60072 /*! SPI0_SDO - wakeup from SPI0_SDO
60073  */
60074 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_MASK)
60075 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_MASK    (0x4000U)
60076 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_SHIFT   (14U)
60077 /*! SPI0_CS1 - wakeup from SPI0_CS1
60078  */
60079 #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_MASK)
60080 #define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_MASK (0xFFFF8000U)
60081 #define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_SHIFT (15U)
60082 /*! iomuxd_group_2_0_reserved_15_31 - reserved
60083  */
60084 #define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_MASK)
60085 /*! @} */
60086 
60087 /*! @name SPI0_CS0 - SPI0_CS0 */
60088 /*! @{ */
60089 #define IOMUXD_SPI0_CS0_PDRV_MASK                (0x1U)
60090 #define IOMUXD_SPI0_CS0_PDRV_SHIFT               (0U)
60091 /*! PDRV - Drive
60092  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60093  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60094  */
60095 #define IOMUXD_SPI0_CS0_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_PDRV_SHIFT)) & IOMUXD_SPI0_CS0_PDRV_MASK)
60096 #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_MASK (0x1EU)
60097 #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_SHIFT (1U)
60098 /*! SPI0_CS0_reserved_1_4 - reserved
60099  */
60100 #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_MASK)
60101 #define IOMUXD_SPI0_CS0_PULL_MASK                (0x60U)
60102 #define IOMUXD_SPI0_CS0_PULL_SHIFT               (5U)
60103 /*! PULL - Pull Down Pull Up
60104  *  0b10..pull down
60105  *  0b01..pull up
60106  *  0b00..Prohibited
60107  *  0b11..pull disabled
60108  */
60109 #define IOMUXD_SPI0_CS0_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_PULL_SHIFT)) & IOMUXD_SPI0_CS0_PULL_MASK)
60110 #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_MASK (0x7FF80U)
60111 #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_SHIFT (7U)
60112 /*! SPI0_CS0_reserved_7_18 - reserved
60113  */
60114 #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_MASK)
60115 #define IOMUXD_SPI0_CS0_WAKEUP_CTRL_MASK         (0x380000U)
60116 #define IOMUXD_SPI0_CS0_WAKEUP_CTRL_SHIFT        (19U)
60117 /*! WAKEUP_CTRL - wakeup control
60118  *  0b000..OFF
60119  *  0b001..RESAMPLE
60120  *  0b100..LOW
60121  *  0b111..HIGH
60122  *  0b110..RISE
60123  *  0b101..FALL
60124  */
60125 #define IOMUXD_SPI0_CS0_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_CS0_WAKEUP_CTRL_MASK)
60126 #define IOMUXD_SPI0_CS0_WAKEUP_MASK_MASK         (0x400000U)
60127 #define IOMUXD_SPI0_CS0_WAKEUP_MASK_SHIFT        (22U)
60128 /*! WAKEUP_MASK - wakeup mask
60129  */
60130 #define IOMUXD_SPI0_CS0_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_CS0_WAKEUP_MASK_MASK)
60131 #define IOMUXD_SPI0_CS0_lp_config_MASK           (0x1800000U)
60132 #define IOMUXD_SPI0_CS0_lp_config_SHIFT          (23U)
60133 /*! lp_config - lower power configuration
60134  *  0b01..EARLY_ISO
60135  *  0b10..LATE_ISO
60136  *  0b11..LATCH
60137  *  0b00..PASS
60138  */
60139 #define IOMUXD_SPI0_CS0_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_lp_config_SHIFT)) & IOMUXD_SPI0_CS0_lp_config_MASK)
60140 #define IOMUXD_SPI0_CS0_sw_config_MASK           (0x6000000U)
60141 #define IOMUXD_SPI0_CS0_sw_config_SHIFT          (25U)
60142 /*! sw_config - output and input configuration
60143  *  0b01..OPEN_DRAIN
60144  *  0b10..OPEN_DRAIN_INPUT
60145  *  0b11..INOUT
60146  *  0b00..DEFAULT
60147  */
60148 #define IOMUXD_SPI0_CS0_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_sw_config_SHIFT)) & IOMUXD_SPI0_CS0_sw_config_MASK)
60149 #define IOMUXD_SPI0_CS0_mux_mode_MASK            (0x38000000U)
60150 #define IOMUXD_SPI0_CS0_mux_mode_SHIFT           (27U)
60151 /*! mux_mode - mux_mode
60152  *  0b000..ADMA.SPI0.CS0
60153  *  0b001..ADMA.SAI0.RXD
60154  *  0b010..M40.TPM0.CH1
60155  *  0b011..M40.GPIO0.IO03
60156  *  0b100..LSIO.GPIO1.IO08
60157  */
60158 #define IOMUXD_SPI0_CS0_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_mux_mode_SHIFT)) & IOMUXD_SPI0_CS0_mux_mode_MASK)
60159 #define IOMUXD_SPI0_CS0_update_pad_ctl_MASK      (0x40000000U)
60160 #define IOMUXD_SPI0_CS0_update_pad_ctl_SHIFT     (30U)
60161 /*! update_pad_ctl - update lock for pad control
60162  */
60163 #define IOMUXD_SPI0_CS0_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_CS0_update_pad_ctl_MASK)
60164 #define IOMUXD_SPI0_CS0_update_mux_mode_MASK     (0x80000000U)
60165 #define IOMUXD_SPI0_CS0_update_mux_mode_SHIFT    (31U)
60166 /*! update_mux_mode - update lock for mux control
60167  */
60168 #define IOMUXD_SPI0_CS0_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI0_CS0_update_mux_mode_MASK)
60169 /*! @} */
60170 
60171 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT */
60172 /*! @{ */
60173 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_MASK (0x7U)
60174 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_SHIFT (0U)
60175 /*! COMP - COMP
60176  *  0b010..Fixed code mode
60177  *  0b100..High impedance mode
60178  *  0b110..Read mode
60179  *  0b000..Normal Mode
60180  *  0b001..Freeze Mode
60181  */
60182 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_MASK)
60183 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_MASK (0x8U)
60184 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_SHIFT (3U)
60185 /*! FASTFRZ_EN - FASTFRZ_EN
60186  *  0b1..FASTFRZ signal is driven by output of subsystem
60187  *  0b0..FASTFRZ signal is gated to 0
60188  */
60189 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_MASK)
60190 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_MASK (0x10U)
60191 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_SHIFT (4U)
60192 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4 - reserved
60193  */
60194 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_MASK)
60195 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_MASK (0x1E0U)
60196 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_SHIFT (5U)
60197 /*! RASRCP - RASRCP
60198  *  0b0101..Reset Value
60199  */
60200 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_MASK)
60201 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_MASK (0x1E00U)
60202 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_SHIFT (9U)
60203 /*! RASRCN - RASRCN
60204  *  0b1010..Reset Value
60205  */
60206 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_MASK)
60207 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_MASK (0x2000U)
60208 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_SHIFT (13U)
60209 /*! SELECT_NASRC - SELECT_NASRC
60210  *  0b1..NASRCN value
60211  *  0b0..NASRCP value
60212  */
60213 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_MASK)
60214 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_MASK (0x4000U)
60215 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_SHIFT (14U)
60216 /*! COMPOK - COMPOK
60217  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
60218  *  0b1..compensation cell in Normal mode and tracking PVT
60219  */
60220 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_MASK)
60221 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_MASK (0x78000U)
60222 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_SHIFT (15U)
60223 /*! READ_NASRC - READ_NASRC
60224  *  0b0000..READ Only
60225  */
60226 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_MASK)
60227 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_MASK (0x780000U)
60228 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_SHIFT (19U)
60229 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22 - reserved
60230  */
60231 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_MASK)
60232 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_MASK (0x1800000U)
60233 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_SHIFT (23U)
60234 /*! SLEEP - SLEEP
60235  *  0b11..Force into sleep mode
60236  *  0b00..NO
60237  *  0b01..EARLY
60238  *  0b10..LATE
60239  */
60240 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_MASK)
60241 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_MASK (0x3E000000U)
60242 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_SHIFT (25U)
60243 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29 - reserved
60244  */
60245 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_MASK)
60246 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_MASK (0x40000000U)
60247 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_SHIFT (30U)
60248 /*! update_pad_ctl - update lock for pad control
60249  */
60250 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_MASK)
60251 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_MASK (0x80000000U)
60252 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_SHIFT (31U)
60253 /*! update_mux_mode - update lock for mux control
60254  */
60255 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_MASK)
60256 /*! @} */
60257 
60258 /*! @name ADC_IN1 - ADC_IN1 */
60259 /*! @{ */
60260 #define IOMUXD_ADC_IN1_DSE_MASK                  (0x7U)
60261 #define IOMUXD_ADC_IN1_DSE_SHIFT                 (0U)
60262 /*! DSE - Drive
60263  *  0b001..Drive select 2mA
60264  *  0b011..Drive select 6mA
60265  *  0b111..High Speed
60266  *  0b110..Drive select 12mA
60267  *  0b010..Drive select 4mA
60268  *  0b100..Drive select 8mA
60269  *  0b000..Drive select 1mA
60270  *  0b101..Drive select 10mA
60271  */
60272 #define IOMUXD_ADC_IN1_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_DSE_SHIFT)) & IOMUXD_ADC_IN1_DSE_MASK)
60273 #define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_MASK (0x18U)
60274 #define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_SHIFT (3U)
60275 /*! ADC_IN1_reserved_3_4 - reserved
60276  */
60277 #define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_MASK)
60278 #define IOMUXD_ADC_IN1_PULL_MASK                 (0x60U)
60279 #define IOMUXD_ADC_IN1_PULL_SHIFT                (5U)
60280 /*! PULL - Pull Down Pull Up
60281  *  0b00..Bus-Keeper
60282  *  0b10..pull down
60283  *  0b01..pull up
60284  *  0b11..No Pull
60285  */
60286 #define IOMUXD_ADC_IN1_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_PULL_SHIFT)) & IOMUXD_ADC_IN1_PULL_MASK)
60287 #define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_MASK (0x7FF80U)
60288 #define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_SHIFT (7U)
60289 /*! ADC_IN1_reserved_7_18 - reserved
60290  */
60291 #define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_MASK)
60292 #define IOMUXD_ADC_IN1_WAKEUP_CTRL_MASK          (0x380000U)
60293 #define IOMUXD_ADC_IN1_WAKEUP_CTRL_SHIFT         (19U)
60294 /*! WAKEUP_CTRL - wakeup control
60295  *  0b000..OFF
60296  *  0b001..RESAMPLE
60297  *  0b100..LOW
60298  *  0b111..HIGH
60299  *  0b110..RISE
60300  *  0b101..FALL
60301  */
60302 #define IOMUXD_ADC_IN1_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN1_WAKEUP_CTRL_MASK)
60303 #define IOMUXD_ADC_IN1_WAKEUP_MASK_MASK          (0x400000U)
60304 #define IOMUXD_ADC_IN1_WAKEUP_MASK_SHIFT         (22U)
60305 /*! WAKEUP_MASK - wakeup mask
60306  */
60307 #define IOMUXD_ADC_IN1_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN1_WAKEUP_MASK_MASK)
60308 #define IOMUXD_ADC_IN1_lp_config_MASK            (0x1800000U)
60309 #define IOMUXD_ADC_IN1_lp_config_SHIFT           (23U)
60310 /*! lp_config - lower power configuration
60311  *  0b01..EARLY_ISO
60312  *  0b10..LATE_ISO
60313  *  0b11..LATCH
60314  *  0b00..PASS
60315  */
60316 #define IOMUXD_ADC_IN1_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_lp_config_SHIFT)) & IOMUXD_ADC_IN1_lp_config_MASK)
60317 #define IOMUXD_ADC_IN1_sw_config_MASK            (0x6000000U)
60318 #define IOMUXD_ADC_IN1_sw_config_SHIFT           (25U)
60319 /*! sw_config - output and input configuration
60320  *  0b01..OPEN_DRAIN
60321  *  0b10..OPEN_DRAIN_INPUT
60322  *  0b11..INOUT
60323  *  0b00..DEFAULT
60324  */
60325 #define IOMUXD_ADC_IN1_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_sw_config_SHIFT)) & IOMUXD_ADC_IN1_sw_config_MASK)
60326 #define IOMUXD_ADC_IN1_mux_mode_MASK             (0x38000000U)
60327 #define IOMUXD_ADC_IN1_mux_mode_SHIFT            (27U)
60328 /*! mux_mode - mux_mode
60329  *  0b000..ADMA.ADC.IN1
60330  *  0b001..M40.I2C0.SDA
60331  *  0b010..M40.GPIO0.IO01
60332  *  0b100..LSIO.GPIO1.IO09
60333  */
60334 #define IOMUXD_ADC_IN1_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_mux_mode_SHIFT)) & IOMUXD_ADC_IN1_mux_mode_MASK)
60335 #define IOMUXD_ADC_IN1_update_pad_ctl_MASK       (0x40000000U)
60336 #define IOMUXD_ADC_IN1_update_pad_ctl_SHIFT      (30U)
60337 /*! update_pad_ctl - update lock for pad control
60338  */
60339 #define IOMUXD_ADC_IN1_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN1_update_pad_ctl_MASK)
60340 #define IOMUXD_ADC_IN1_update_mux_mode_MASK      (0x80000000U)
60341 #define IOMUXD_ADC_IN1_update_mux_mode_SHIFT     (31U)
60342 /*! update_mux_mode - update lock for mux control
60343  */
60344 #define IOMUXD_ADC_IN1_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN1_update_mux_mode_MASK)
60345 /*! @} */
60346 
60347 /*! @name ADC_IN0 - ADC_IN0 */
60348 /*! @{ */
60349 #define IOMUXD_ADC_IN0_DSE_MASK                  (0x7U)
60350 #define IOMUXD_ADC_IN0_DSE_SHIFT                 (0U)
60351 /*! DSE - Drive
60352  *  0b001..Drive select 2mA
60353  *  0b011..Drive select 6mA
60354  *  0b111..High Speed
60355  *  0b110..Drive select 12mA
60356  *  0b010..Drive select 4mA
60357  *  0b100..Drive select 8mA
60358  *  0b000..Drive select 1mA
60359  *  0b101..Drive select 10mA
60360  */
60361 #define IOMUXD_ADC_IN0_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_DSE_SHIFT)) & IOMUXD_ADC_IN0_DSE_MASK)
60362 #define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_MASK (0x18U)
60363 #define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_SHIFT (3U)
60364 /*! ADC_IN0_reserved_3_4 - reserved
60365  */
60366 #define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_MASK)
60367 #define IOMUXD_ADC_IN0_PULL_MASK                 (0x60U)
60368 #define IOMUXD_ADC_IN0_PULL_SHIFT                (5U)
60369 /*! PULL - Pull Down Pull Up
60370  *  0b00..Bus-Keeper
60371  *  0b10..pull down
60372  *  0b01..pull up
60373  *  0b11..No Pull
60374  */
60375 #define IOMUXD_ADC_IN0_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_PULL_SHIFT)) & IOMUXD_ADC_IN0_PULL_MASK)
60376 #define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_MASK (0x7FF80U)
60377 #define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_SHIFT (7U)
60378 /*! ADC_IN0_reserved_7_18 - reserved
60379  */
60380 #define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_MASK)
60381 #define IOMUXD_ADC_IN0_WAKEUP_CTRL_MASK          (0x380000U)
60382 #define IOMUXD_ADC_IN0_WAKEUP_CTRL_SHIFT         (19U)
60383 /*! WAKEUP_CTRL - wakeup control
60384  *  0b000..OFF
60385  *  0b001..RESAMPLE
60386  *  0b100..LOW
60387  *  0b111..HIGH
60388  *  0b110..RISE
60389  *  0b101..FALL
60390  */
60391 #define IOMUXD_ADC_IN0_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN0_WAKEUP_CTRL_MASK)
60392 #define IOMUXD_ADC_IN0_WAKEUP_MASK_MASK          (0x400000U)
60393 #define IOMUXD_ADC_IN0_WAKEUP_MASK_SHIFT         (22U)
60394 /*! WAKEUP_MASK - wakeup mask
60395  */
60396 #define IOMUXD_ADC_IN0_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN0_WAKEUP_MASK_MASK)
60397 #define IOMUXD_ADC_IN0_lp_config_MASK            (0x1800000U)
60398 #define IOMUXD_ADC_IN0_lp_config_SHIFT           (23U)
60399 /*! lp_config - lower power configuration
60400  *  0b01..EARLY_ISO
60401  *  0b10..LATE_ISO
60402  *  0b11..LATCH
60403  *  0b00..PASS
60404  */
60405 #define IOMUXD_ADC_IN0_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_lp_config_SHIFT)) & IOMUXD_ADC_IN0_lp_config_MASK)
60406 #define IOMUXD_ADC_IN0_sw_config_MASK            (0x6000000U)
60407 #define IOMUXD_ADC_IN0_sw_config_SHIFT           (25U)
60408 /*! sw_config - output and input configuration
60409  *  0b01..OPEN_DRAIN
60410  *  0b10..OPEN_DRAIN_INPUT
60411  *  0b11..INOUT
60412  *  0b00..DEFAULT
60413  */
60414 #define IOMUXD_ADC_IN0_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_sw_config_SHIFT)) & IOMUXD_ADC_IN0_sw_config_MASK)
60415 #define IOMUXD_ADC_IN0_mux_mode_MASK             (0x38000000U)
60416 #define IOMUXD_ADC_IN0_mux_mode_SHIFT            (27U)
60417 /*! mux_mode - mux_mode
60418  *  0b000..ADMA.ADC.IN0
60419  *  0b001..M40.I2C0.SCL
60420  *  0b010..M40.GPIO0.IO00
60421  *  0b100..LSIO.GPIO1.IO10
60422  */
60423 #define IOMUXD_ADC_IN0_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_mux_mode_SHIFT)) & IOMUXD_ADC_IN0_mux_mode_MASK)
60424 #define IOMUXD_ADC_IN0_update_pad_ctl_MASK       (0x40000000U)
60425 #define IOMUXD_ADC_IN0_update_pad_ctl_SHIFT      (30U)
60426 /*! update_pad_ctl - update lock for pad control
60427  */
60428 #define IOMUXD_ADC_IN0_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN0_update_pad_ctl_MASK)
60429 #define IOMUXD_ADC_IN0_update_mux_mode_MASK      (0x80000000U)
60430 #define IOMUXD_ADC_IN0_update_mux_mode_SHIFT     (31U)
60431 /*! update_mux_mode - update lock for mux control
60432  */
60433 #define IOMUXD_ADC_IN0_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN0_update_mux_mode_MASK)
60434 /*! @} */
60435 
60436 /*! @name ADC_IN3 - ADC_IN3 */
60437 /*! @{ */
60438 #define IOMUXD_ADC_IN3_DSE_MASK                  (0x7U)
60439 #define IOMUXD_ADC_IN3_DSE_SHIFT                 (0U)
60440 /*! DSE - Drive
60441  *  0b001..Drive select 2mA
60442  *  0b011..Drive select 6mA
60443  *  0b111..High Speed
60444  *  0b110..Drive select 12mA
60445  *  0b010..Drive select 4mA
60446  *  0b100..Drive select 8mA
60447  *  0b000..Drive select 1mA
60448  *  0b101..Drive select 10mA
60449  */
60450 #define IOMUXD_ADC_IN3_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_DSE_SHIFT)) & IOMUXD_ADC_IN3_DSE_MASK)
60451 #define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_MASK (0x18U)
60452 #define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_SHIFT (3U)
60453 /*! ADC_IN3_reserved_3_4 - reserved
60454  */
60455 #define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_MASK)
60456 #define IOMUXD_ADC_IN3_PULL_MASK                 (0x60U)
60457 #define IOMUXD_ADC_IN3_PULL_SHIFT                (5U)
60458 /*! PULL - Pull Down Pull Up
60459  *  0b00..Bus-Keeper
60460  *  0b10..pull down
60461  *  0b01..pull up
60462  *  0b11..No Pull
60463  */
60464 #define IOMUXD_ADC_IN3_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_PULL_SHIFT)) & IOMUXD_ADC_IN3_PULL_MASK)
60465 #define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_MASK (0x7FF80U)
60466 #define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_SHIFT (7U)
60467 /*! ADC_IN3_reserved_7_18 - reserved
60468  */
60469 #define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_MASK)
60470 #define IOMUXD_ADC_IN3_WAKEUP_CTRL_MASK          (0x380000U)
60471 #define IOMUXD_ADC_IN3_WAKEUP_CTRL_SHIFT         (19U)
60472 /*! WAKEUP_CTRL - wakeup control
60473  *  0b000..OFF
60474  *  0b001..RESAMPLE
60475  *  0b100..LOW
60476  *  0b111..HIGH
60477  *  0b110..RISE
60478  *  0b101..FALL
60479  */
60480 #define IOMUXD_ADC_IN3_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN3_WAKEUP_CTRL_MASK)
60481 #define IOMUXD_ADC_IN3_WAKEUP_MASK_MASK          (0x400000U)
60482 #define IOMUXD_ADC_IN3_WAKEUP_MASK_SHIFT         (22U)
60483 /*! WAKEUP_MASK - wakeup mask
60484  */
60485 #define IOMUXD_ADC_IN3_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN3_WAKEUP_MASK_MASK)
60486 #define IOMUXD_ADC_IN3_lp_config_MASK            (0x1800000U)
60487 #define IOMUXD_ADC_IN3_lp_config_SHIFT           (23U)
60488 /*! lp_config - lower power configuration
60489  *  0b01..EARLY_ISO
60490  *  0b10..LATE_ISO
60491  *  0b11..LATCH
60492  *  0b00..PASS
60493  */
60494 #define IOMUXD_ADC_IN3_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_lp_config_SHIFT)) & IOMUXD_ADC_IN3_lp_config_MASK)
60495 #define IOMUXD_ADC_IN3_sw_config_MASK            (0x6000000U)
60496 #define IOMUXD_ADC_IN3_sw_config_SHIFT           (25U)
60497 /*! sw_config - output and input configuration
60498  *  0b01..OPEN_DRAIN
60499  *  0b10..OPEN_DRAIN_INPUT
60500  *  0b11..INOUT
60501  *  0b00..DEFAULT
60502  */
60503 #define IOMUXD_ADC_IN3_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_sw_config_SHIFT)) & IOMUXD_ADC_IN3_sw_config_MASK)
60504 #define IOMUXD_ADC_IN3_mux_mode_MASK             (0x38000000U)
60505 #define IOMUXD_ADC_IN3_mux_mode_SHIFT            (27U)
60506 /*! mux_mode - mux_mode
60507  *  0b000..ADMA.ADC.IN3
60508  *  0b001..M40.UART0.TX
60509  *  0b010..M40.GPIO0.IO03
60510  *  0b011..ADMA.ACM.MCLK_OUT0
60511  *  0b100..LSIO.GPIO1.IO11
60512  */
60513 #define IOMUXD_ADC_IN3_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_mux_mode_SHIFT)) & IOMUXD_ADC_IN3_mux_mode_MASK)
60514 #define IOMUXD_ADC_IN3_update_pad_ctl_MASK       (0x40000000U)
60515 #define IOMUXD_ADC_IN3_update_pad_ctl_SHIFT      (30U)
60516 /*! update_pad_ctl - update lock for pad control
60517  */
60518 #define IOMUXD_ADC_IN3_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN3_update_pad_ctl_MASK)
60519 #define IOMUXD_ADC_IN3_update_mux_mode_MASK      (0x80000000U)
60520 #define IOMUXD_ADC_IN3_update_mux_mode_SHIFT     (31U)
60521 /*! update_mux_mode - update lock for mux control
60522  */
60523 #define IOMUXD_ADC_IN3_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN3_update_mux_mode_MASK)
60524 /*! @} */
60525 
60526 /*! @name ADC_IN2 - ADC_IN2 */
60527 /*! @{ */
60528 #define IOMUXD_ADC_IN2_DSE_MASK                  (0x7U)
60529 #define IOMUXD_ADC_IN2_DSE_SHIFT                 (0U)
60530 /*! DSE - Drive
60531  *  0b001..Drive select 2mA
60532  *  0b011..Drive select 6mA
60533  *  0b111..High Speed
60534  *  0b110..Drive select 12mA
60535  *  0b010..Drive select 4mA
60536  *  0b100..Drive select 8mA
60537  *  0b000..Drive select 1mA
60538  *  0b101..Drive select 10mA
60539  */
60540 #define IOMUXD_ADC_IN2_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_DSE_SHIFT)) & IOMUXD_ADC_IN2_DSE_MASK)
60541 #define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_MASK (0x18U)
60542 #define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_SHIFT (3U)
60543 /*! ADC_IN2_reserved_3_4 - reserved
60544  */
60545 #define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_MASK)
60546 #define IOMUXD_ADC_IN2_PULL_MASK                 (0x60U)
60547 #define IOMUXD_ADC_IN2_PULL_SHIFT                (5U)
60548 /*! PULL - Pull Down Pull Up
60549  *  0b00..Bus-Keeper
60550  *  0b10..pull down
60551  *  0b01..pull up
60552  *  0b11..No Pull
60553  */
60554 #define IOMUXD_ADC_IN2_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_PULL_SHIFT)) & IOMUXD_ADC_IN2_PULL_MASK)
60555 #define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_MASK (0x7FF80U)
60556 #define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_SHIFT (7U)
60557 /*! ADC_IN2_reserved_7_18 - reserved
60558  */
60559 #define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_MASK)
60560 #define IOMUXD_ADC_IN2_WAKEUP_CTRL_MASK          (0x380000U)
60561 #define IOMUXD_ADC_IN2_WAKEUP_CTRL_SHIFT         (19U)
60562 /*! WAKEUP_CTRL - wakeup control
60563  *  0b000..OFF
60564  *  0b001..RESAMPLE
60565  *  0b100..LOW
60566  *  0b111..HIGH
60567  *  0b110..RISE
60568  *  0b101..FALL
60569  */
60570 #define IOMUXD_ADC_IN2_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN2_WAKEUP_CTRL_MASK)
60571 #define IOMUXD_ADC_IN2_WAKEUP_MASK_MASK          (0x400000U)
60572 #define IOMUXD_ADC_IN2_WAKEUP_MASK_SHIFT         (22U)
60573 /*! WAKEUP_MASK - wakeup mask
60574  */
60575 #define IOMUXD_ADC_IN2_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN2_WAKEUP_MASK_MASK)
60576 #define IOMUXD_ADC_IN2_lp_config_MASK            (0x1800000U)
60577 #define IOMUXD_ADC_IN2_lp_config_SHIFT           (23U)
60578 /*! lp_config - lower power configuration
60579  *  0b01..EARLY_ISO
60580  *  0b10..LATE_ISO
60581  *  0b11..LATCH
60582  *  0b00..PASS
60583  */
60584 #define IOMUXD_ADC_IN2_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_lp_config_SHIFT)) & IOMUXD_ADC_IN2_lp_config_MASK)
60585 #define IOMUXD_ADC_IN2_sw_config_MASK            (0x6000000U)
60586 #define IOMUXD_ADC_IN2_sw_config_SHIFT           (25U)
60587 /*! sw_config - output and input configuration
60588  *  0b01..OPEN_DRAIN
60589  *  0b10..OPEN_DRAIN_INPUT
60590  *  0b11..INOUT
60591  *  0b00..DEFAULT
60592  */
60593 #define IOMUXD_ADC_IN2_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_sw_config_SHIFT)) & IOMUXD_ADC_IN2_sw_config_MASK)
60594 #define IOMUXD_ADC_IN2_mux_mode_MASK             (0x38000000U)
60595 #define IOMUXD_ADC_IN2_mux_mode_SHIFT            (27U)
60596 /*! mux_mode - mux_mode
60597  *  0b000..ADMA.ADC.IN2
60598  *  0b001..M40.UART0.RX
60599  *  0b010..M40.GPIO0.IO02
60600  *  0b011..ADMA.ACM.MCLK_IN0
60601  *  0b100..LSIO.GPIO1.IO12
60602  */
60603 #define IOMUXD_ADC_IN2_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_mux_mode_SHIFT)) & IOMUXD_ADC_IN2_mux_mode_MASK)
60604 #define IOMUXD_ADC_IN2_update_pad_ctl_MASK       (0x40000000U)
60605 #define IOMUXD_ADC_IN2_update_pad_ctl_SHIFT      (30U)
60606 /*! update_pad_ctl - update lock for pad control
60607  */
60608 #define IOMUXD_ADC_IN2_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN2_update_pad_ctl_MASK)
60609 #define IOMUXD_ADC_IN2_update_mux_mode_MASK      (0x80000000U)
60610 #define IOMUXD_ADC_IN2_update_mux_mode_SHIFT     (31U)
60611 /*! update_mux_mode - update lock for mux control
60612  */
60613 #define IOMUXD_ADC_IN2_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN2_update_mux_mode_MASK)
60614 /*! @} */
60615 
60616 /*! @name ADC_IN5 - ADC_IN5 */
60617 /*! @{ */
60618 #define IOMUXD_ADC_IN5_DSE_MASK                  (0x7U)
60619 #define IOMUXD_ADC_IN5_DSE_SHIFT                 (0U)
60620 /*! DSE - Drive
60621  *  0b001..Drive select 2mA
60622  *  0b011..Drive select 6mA
60623  *  0b111..High Speed
60624  *  0b110..Drive select 12mA
60625  *  0b010..Drive select 4mA
60626  *  0b100..Drive select 8mA
60627  *  0b000..Drive select 1mA
60628  *  0b101..Drive select 10mA
60629  */
60630 #define IOMUXD_ADC_IN5_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_DSE_SHIFT)) & IOMUXD_ADC_IN5_DSE_MASK)
60631 #define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_MASK (0x18U)
60632 #define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_SHIFT (3U)
60633 /*! ADC_IN5_reserved_3_4 - reserved
60634  */
60635 #define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_MASK)
60636 #define IOMUXD_ADC_IN5_PULL_MASK                 (0x60U)
60637 #define IOMUXD_ADC_IN5_PULL_SHIFT                (5U)
60638 /*! PULL - Pull Down Pull Up
60639  *  0b00..Bus-Keeper
60640  *  0b10..pull down
60641  *  0b01..pull up
60642  *  0b11..No Pull
60643  */
60644 #define IOMUXD_ADC_IN5_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_PULL_SHIFT)) & IOMUXD_ADC_IN5_PULL_MASK)
60645 #define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_MASK (0x7FF80U)
60646 #define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_SHIFT (7U)
60647 /*! ADC_IN5_reserved_7_18 - reserved
60648  */
60649 #define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_MASK)
60650 #define IOMUXD_ADC_IN5_WAKEUP_CTRL_MASK          (0x380000U)
60651 #define IOMUXD_ADC_IN5_WAKEUP_CTRL_SHIFT         (19U)
60652 /*! WAKEUP_CTRL - wakeup control
60653  *  0b000..OFF
60654  *  0b001..RESAMPLE
60655  *  0b100..LOW
60656  *  0b111..HIGH
60657  *  0b110..RISE
60658  *  0b101..FALL
60659  */
60660 #define IOMUXD_ADC_IN5_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN5_WAKEUP_CTRL_MASK)
60661 #define IOMUXD_ADC_IN5_WAKEUP_MASK_MASK          (0x400000U)
60662 #define IOMUXD_ADC_IN5_WAKEUP_MASK_SHIFT         (22U)
60663 /*! WAKEUP_MASK - wakeup mask
60664  */
60665 #define IOMUXD_ADC_IN5_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN5_WAKEUP_MASK_MASK)
60666 #define IOMUXD_ADC_IN5_lp_config_MASK            (0x1800000U)
60667 #define IOMUXD_ADC_IN5_lp_config_SHIFT           (23U)
60668 /*! lp_config - lower power configuration
60669  *  0b01..EARLY_ISO
60670  *  0b10..LATE_ISO
60671  *  0b11..LATCH
60672  *  0b00..PASS
60673  */
60674 #define IOMUXD_ADC_IN5_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_lp_config_SHIFT)) & IOMUXD_ADC_IN5_lp_config_MASK)
60675 #define IOMUXD_ADC_IN5_sw_config_MASK            (0x6000000U)
60676 #define IOMUXD_ADC_IN5_sw_config_SHIFT           (25U)
60677 /*! sw_config - output and input configuration
60678  *  0b01..OPEN_DRAIN
60679  *  0b10..OPEN_DRAIN_INPUT
60680  *  0b11..INOUT
60681  *  0b00..DEFAULT
60682  */
60683 #define IOMUXD_ADC_IN5_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_sw_config_SHIFT)) & IOMUXD_ADC_IN5_sw_config_MASK)
60684 #define IOMUXD_ADC_IN5_mux_mode_MASK             (0x38000000U)
60685 #define IOMUXD_ADC_IN5_mux_mode_SHIFT            (27U)
60686 /*! mux_mode - mux_mode
60687  *  0b000..ADMA.ADC.IN5
60688  *  0b001..M40.TPM0.CH1
60689  *  0b010..M40.GPIO0.IO05
60690  *  0b100..LSIO.GPIO1.IO13
60691  */
60692 #define IOMUXD_ADC_IN5_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_mux_mode_SHIFT)) & IOMUXD_ADC_IN5_mux_mode_MASK)
60693 #define IOMUXD_ADC_IN5_update_pad_ctl_MASK       (0x40000000U)
60694 #define IOMUXD_ADC_IN5_update_pad_ctl_SHIFT      (30U)
60695 /*! update_pad_ctl - update lock for pad control
60696  */
60697 #define IOMUXD_ADC_IN5_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN5_update_pad_ctl_MASK)
60698 #define IOMUXD_ADC_IN5_update_mux_mode_MASK      (0x80000000U)
60699 #define IOMUXD_ADC_IN5_update_mux_mode_SHIFT     (31U)
60700 /*! update_mux_mode - update lock for mux control
60701  */
60702 #define IOMUXD_ADC_IN5_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN5_update_mux_mode_MASK)
60703 /*! @} */
60704 
60705 /*! @name ADC_IN4 - ADC_IN4 */
60706 /*! @{ */
60707 #define IOMUXD_ADC_IN4_DSE_MASK                  (0x7U)
60708 #define IOMUXD_ADC_IN4_DSE_SHIFT                 (0U)
60709 /*! DSE - Drive
60710  *  0b001..Drive select 2mA
60711  *  0b011..Drive select 6mA
60712  *  0b111..High Speed
60713  *  0b110..Drive select 12mA
60714  *  0b010..Drive select 4mA
60715  *  0b100..Drive select 8mA
60716  *  0b000..Drive select 1mA
60717  *  0b101..Drive select 10mA
60718  */
60719 #define IOMUXD_ADC_IN4_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_DSE_SHIFT)) & IOMUXD_ADC_IN4_DSE_MASK)
60720 #define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_MASK (0x18U)
60721 #define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_SHIFT (3U)
60722 /*! ADC_IN4_reserved_3_4 - reserved
60723  */
60724 #define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_MASK)
60725 #define IOMUXD_ADC_IN4_PULL_MASK                 (0x60U)
60726 #define IOMUXD_ADC_IN4_PULL_SHIFT                (5U)
60727 /*! PULL - Pull Down Pull Up
60728  *  0b00..Bus-Keeper
60729  *  0b10..pull down
60730  *  0b01..pull up
60731  *  0b11..No Pull
60732  */
60733 #define IOMUXD_ADC_IN4_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_PULL_SHIFT)) & IOMUXD_ADC_IN4_PULL_MASK)
60734 #define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_MASK (0x7FF80U)
60735 #define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_SHIFT (7U)
60736 /*! ADC_IN4_reserved_7_18 - reserved
60737  */
60738 #define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_MASK)
60739 #define IOMUXD_ADC_IN4_WAKEUP_CTRL_MASK          (0x380000U)
60740 #define IOMUXD_ADC_IN4_WAKEUP_CTRL_SHIFT         (19U)
60741 /*! WAKEUP_CTRL - wakeup control
60742  *  0b000..OFF
60743  *  0b001..RESAMPLE
60744  *  0b100..LOW
60745  *  0b111..HIGH
60746  *  0b110..RISE
60747  *  0b101..FALL
60748  */
60749 #define IOMUXD_ADC_IN4_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN4_WAKEUP_CTRL_MASK)
60750 #define IOMUXD_ADC_IN4_WAKEUP_MASK_MASK          (0x400000U)
60751 #define IOMUXD_ADC_IN4_WAKEUP_MASK_SHIFT         (22U)
60752 /*! WAKEUP_MASK - wakeup mask
60753  */
60754 #define IOMUXD_ADC_IN4_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN4_WAKEUP_MASK_MASK)
60755 #define IOMUXD_ADC_IN4_lp_config_MASK            (0x1800000U)
60756 #define IOMUXD_ADC_IN4_lp_config_SHIFT           (23U)
60757 /*! lp_config - lower power configuration
60758  *  0b01..EARLY_ISO
60759  *  0b10..LATE_ISO
60760  *  0b11..LATCH
60761  *  0b00..PASS
60762  */
60763 #define IOMUXD_ADC_IN4_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_lp_config_SHIFT)) & IOMUXD_ADC_IN4_lp_config_MASK)
60764 #define IOMUXD_ADC_IN4_sw_config_MASK            (0x6000000U)
60765 #define IOMUXD_ADC_IN4_sw_config_SHIFT           (25U)
60766 /*! sw_config - output and input configuration
60767  *  0b01..OPEN_DRAIN
60768  *  0b10..OPEN_DRAIN_INPUT
60769  *  0b11..INOUT
60770  *  0b00..DEFAULT
60771  */
60772 #define IOMUXD_ADC_IN4_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_sw_config_SHIFT)) & IOMUXD_ADC_IN4_sw_config_MASK)
60773 #define IOMUXD_ADC_IN4_mux_mode_MASK             (0x38000000U)
60774 #define IOMUXD_ADC_IN4_mux_mode_SHIFT            (27U)
60775 /*! mux_mode - mux_mode
60776  *  0b000..ADMA.ADC.IN4
60777  *  0b001..M40.TPM0.CH0
60778  *  0b010..M40.GPIO0.IO04
60779  *  0b100..LSIO.GPIO1.IO14
60780  */
60781 #define IOMUXD_ADC_IN4_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_mux_mode_SHIFT)) & IOMUXD_ADC_IN4_mux_mode_MASK)
60782 #define IOMUXD_ADC_IN4_update_pad_ctl_MASK       (0x40000000U)
60783 #define IOMUXD_ADC_IN4_update_pad_ctl_SHIFT      (30U)
60784 /*! update_pad_ctl - update lock for pad control
60785  */
60786 #define IOMUXD_ADC_IN4_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN4_update_pad_ctl_MASK)
60787 #define IOMUXD_ADC_IN4_update_mux_mode_MASK      (0x80000000U)
60788 #define IOMUXD_ADC_IN4_update_mux_mode_SHIFT     (31U)
60789 /*! update_mux_mode - update lock for mux control
60790  */
60791 #define IOMUXD_ADC_IN4_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN4_update_mux_mode_MASK)
60792 /*! @} */
60793 
60794 /*! @name FLEXCAN0_RX - FLEXCAN0_RX */
60795 /*! @{ */
60796 #define IOMUXD_FLEXCAN0_RX_PDRV_MASK             (0x1U)
60797 #define IOMUXD_FLEXCAN0_RX_PDRV_SHIFT            (0U)
60798 /*! PDRV - Drive
60799  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60800  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60801  */
60802 #define IOMUXD_FLEXCAN0_RX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN0_RX_PDRV_MASK)
60803 #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_MASK (0x1EU)
60804 #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_SHIFT (1U)
60805 /*! FLEXCAN0_RX_reserved_1_4 - reserved
60806  */
60807 #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_MASK)
60808 #define IOMUXD_FLEXCAN0_RX_PULL_MASK             (0x60U)
60809 #define IOMUXD_FLEXCAN0_RX_PULL_SHIFT            (5U)
60810 /*! PULL - Pull Down Pull Up
60811  *  0b10..pull down
60812  *  0b01..pull up
60813  *  0b00..Prohibited
60814  *  0b11..pull disabled
60815  */
60816 #define IOMUXD_FLEXCAN0_RX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN0_RX_PULL_MASK)
60817 #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_MASK (0x7FF80U)
60818 #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_SHIFT (7U)
60819 /*! FLEXCAN0_RX_reserved_7_18 - reserved
60820  */
60821 #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_MASK)
60822 #define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_MASK      (0x380000U)
60823 #define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_SHIFT     (19U)
60824 /*! WAKEUP_CTRL - wakeup control
60825  *  0b000..OFF
60826  *  0b001..RESAMPLE
60827  *  0b100..LOW
60828  *  0b111..HIGH
60829  *  0b110..RISE
60830  *  0b101..FALL
60831  */
60832 #define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_MASK)
60833 #define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_MASK      (0x400000U)
60834 #define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_SHIFT     (22U)
60835 /*! WAKEUP_MASK - wakeup mask
60836  */
60837 #define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_MASK)
60838 #define IOMUXD_FLEXCAN0_RX_lp_config_MASK        (0x1800000U)
60839 #define IOMUXD_FLEXCAN0_RX_lp_config_SHIFT       (23U)
60840 /*! lp_config - lower power configuration
60841  *  0b01..EARLY_ISO
60842  *  0b10..LATE_ISO
60843  *  0b11..LATCH
60844  *  0b00..PASS
60845  */
60846 #define IOMUXD_FLEXCAN0_RX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN0_RX_lp_config_MASK)
60847 #define IOMUXD_FLEXCAN0_RX_sw_config_MASK        (0x6000000U)
60848 #define IOMUXD_FLEXCAN0_RX_sw_config_SHIFT       (25U)
60849 /*! sw_config - output and input configuration
60850  *  0b01..OPEN_DRAIN
60851  *  0b10..OPEN_DRAIN_INPUT
60852  *  0b11..INOUT
60853  *  0b00..DEFAULT
60854  */
60855 #define IOMUXD_FLEXCAN0_RX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN0_RX_sw_config_MASK)
60856 #define IOMUXD_FLEXCAN0_RX_mux_mode_MASK         (0x38000000U)
60857 #define IOMUXD_FLEXCAN0_RX_mux_mode_SHIFT        (27U)
60858 /*! mux_mode - mux_mode
60859  *  0b000..ADMA.FLEXCAN0.RX
60860  *  0b001..ADMA.SAI2.RXC
60861  *  0b010..ADMA.UART0.RTS_B
60862  *  0b011..ADMA.SAI1.TXC
60863  *  0b100..LSIO.GPIO1.IO15
60864  */
60865 #define IOMUXD_FLEXCAN0_RX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_RX_mux_mode_MASK)
60866 #define IOMUXD_FLEXCAN0_RX_update_pad_ctl_MASK   (0x40000000U)
60867 #define IOMUXD_FLEXCAN0_RX_update_pad_ctl_SHIFT  (30U)
60868 /*! update_pad_ctl - update lock for pad control
60869  */
60870 #define IOMUXD_FLEXCAN0_RX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN0_RX_update_pad_ctl_MASK)
60871 #define IOMUXD_FLEXCAN0_RX_update_mux_mode_MASK  (0x80000000U)
60872 #define IOMUXD_FLEXCAN0_RX_update_mux_mode_SHIFT (31U)
60873 /*! update_mux_mode - update lock for mux control
60874  */
60875 #define IOMUXD_FLEXCAN0_RX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_RX_update_mux_mode_MASK)
60876 /*! @} */
60877 
60878 /*! @name FLEXCAN0_TX - FLEXCAN0_TX */
60879 /*! @{ */
60880 #define IOMUXD_FLEXCAN0_TX_PDRV_MASK             (0x1U)
60881 #define IOMUXD_FLEXCAN0_TX_PDRV_SHIFT            (0U)
60882 /*! PDRV - Drive
60883  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60884  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60885  */
60886 #define IOMUXD_FLEXCAN0_TX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN0_TX_PDRV_MASK)
60887 #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_MASK (0x1EU)
60888 #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_SHIFT (1U)
60889 /*! FLEXCAN0_TX_reserved_1_4 - reserved
60890  */
60891 #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_MASK)
60892 #define IOMUXD_FLEXCAN0_TX_PULL_MASK             (0x60U)
60893 #define IOMUXD_FLEXCAN0_TX_PULL_SHIFT            (5U)
60894 /*! PULL - Pull Down Pull Up
60895  *  0b10..pull down
60896  *  0b01..pull up
60897  *  0b00..Prohibited
60898  *  0b11..pull disabled
60899  */
60900 #define IOMUXD_FLEXCAN0_TX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN0_TX_PULL_MASK)
60901 #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_MASK (0x7FF80U)
60902 #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_SHIFT (7U)
60903 /*! FLEXCAN0_TX_reserved_7_18 - reserved
60904  */
60905 #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_MASK)
60906 #define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_MASK      (0x380000U)
60907 #define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_SHIFT     (19U)
60908 /*! WAKEUP_CTRL - wakeup control
60909  *  0b000..OFF
60910  *  0b001..RESAMPLE
60911  *  0b100..LOW
60912  *  0b111..HIGH
60913  *  0b110..RISE
60914  *  0b101..FALL
60915  */
60916 #define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_MASK)
60917 #define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_MASK      (0x400000U)
60918 #define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_SHIFT     (22U)
60919 /*! WAKEUP_MASK - wakeup mask
60920  */
60921 #define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_MASK)
60922 #define IOMUXD_FLEXCAN0_TX_lp_config_MASK        (0x1800000U)
60923 #define IOMUXD_FLEXCAN0_TX_lp_config_SHIFT       (23U)
60924 /*! lp_config - lower power configuration
60925  *  0b01..EARLY_ISO
60926  *  0b10..LATE_ISO
60927  *  0b11..LATCH
60928  *  0b00..PASS
60929  */
60930 #define IOMUXD_FLEXCAN0_TX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN0_TX_lp_config_MASK)
60931 #define IOMUXD_FLEXCAN0_TX_sw_config_MASK        (0x6000000U)
60932 #define IOMUXD_FLEXCAN0_TX_sw_config_SHIFT       (25U)
60933 /*! sw_config - output and input configuration
60934  *  0b01..OPEN_DRAIN
60935  *  0b10..OPEN_DRAIN_INPUT
60936  *  0b11..INOUT
60937  *  0b00..DEFAULT
60938  */
60939 #define IOMUXD_FLEXCAN0_TX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN0_TX_sw_config_MASK)
60940 #define IOMUXD_FLEXCAN0_TX_mux_mode_MASK         (0x38000000U)
60941 #define IOMUXD_FLEXCAN0_TX_mux_mode_SHIFT        (27U)
60942 /*! mux_mode - mux_mode
60943  *  0b000..ADMA.FLEXCAN0.TX
60944  *  0b001..ADMA.SAI2.RXD
60945  *  0b010..ADMA.UART0.CTS_B
60946  *  0b011..ADMA.SAI1.TXFS
60947  *  0b100..LSIO.GPIO1.IO16
60948  */
60949 #define IOMUXD_FLEXCAN0_TX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_TX_mux_mode_MASK)
60950 #define IOMUXD_FLEXCAN0_TX_update_pad_ctl_MASK   (0x40000000U)
60951 #define IOMUXD_FLEXCAN0_TX_update_pad_ctl_SHIFT  (30U)
60952 /*! update_pad_ctl - update lock for pad control
60953  */
60954 #define IOMUXD_FLEXCAN0_TX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN0_TX_update_pad_ctl_MASK)
60955 #define IOMUXD_FLEXCAN0_TX_update_mux_mode_MASK  (0x80000000U)
60956 #define IOMUXD_FLEXCAN0_TX_update_mux_mode_SHIFT (31U)
60957 /*! update_mux_mode - update lock for mux control
60958  */
60959 #define IOMUXD_FLEXCAN0_TX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_TX_update_mux_mode_MASK)
60960 /*! @} */
60961 
60962 /*! @name FLEXCAN1_RX - FLEXCAN1_RX */
60963 /*! @{ */
60964 #define IOMUXD_FLEXCAN1_RX_PDRV_MASK             (0x1U)
60965 #define IOMUXD_FLEXCAN1_RX_PDRV_SHIFT            (0U)
60966 /*! PDRV - Drive
60967  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60968  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60969  */
60970 #define IOMUXD_FLEXCAN1_RX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN1_RX_PDRV_MASK)
60971 #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_MASK (0x1EU)
60972 #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_SHIFT (1U)
60973 /*! FLEXCAN1_RX_reserved_1_4 - reserved
60974  */
60975 #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_MASK)
60976 #define IOMUXD_FLEXCAN1_RX_PULL_MASK             (0x60U)
60977 #define IOMUXD_FLEXCAN1_RX_PULL_SHIFT            (5U)
60978 /*! PULL - Pull Down Pull Up
60979  *  0b10..pull down
60980  *  0b01..pull up
60981  *  0b00..Prohibited
60982  *  0b11..pull disabled
60983  */
60984 #define IOMUXD_FLEXCAN1_RX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN1_RX_PULL_MASK)
60985 #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_MASK (0x7FF80U)
60986 #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_SHIFT (7U)
60987 /*! FLEXCAN1_RX_reserved_7_18 - reserved
60988  */
60989 #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_MASK)
60990 #define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_MASK      (0x380000U)
60991 #define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_SHIFT     (19U)
60992 /*! WAKEUP_CTRL - wakeup control
60993  *  0b000..OFF
60994  *  0b001..RESAMPLE
60995  *  0b100..LOW
60996  *  0b111..HIGH
60997  *  0b110..RISE
60998  *  0b101..FALL
60999  */
61000 #define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_MASK)
61001 #define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_MASK      (0x400000U)
61002 #define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_SHIFT     (22U)
61003 /*! WAKEUP_MASK - wakeup mask
61004  */
61005 #define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_MASK)
61006 #define IOMUXD_FLEXCAN1_RX_lp_config_MASK        (0x1800000U)
61007 #define IOMUXD_FLEXCAN1_RX_lp_config_SHIFT       (23U)
61008 /*! lp_config - lower power configuration
61009  *  0b01..EARLY_ISO
61010  *  0b10..LATE_ISO
61011  *  0b11..LATCH
61012  *  0b00..PASS
61013  */
61014 #define IOMUXD_FLEXCAN1_RX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN1_RX_lp_config_MASK)
61015 #define IOMUXD_FLEXCAN1_RX_sw_config_MASK        (0x6000000U)
61016 #define IOMUXD_FLEXCAN1_RX_sw_config_SHIFT       (25U)
61017 /*! sw_config - output and input configuration
61018  *  0b01..OPEN_DRAIN
61019  *  0b10..OPEN_DRAIN_INPUT
61020  *  0b11..INOUT
61021  *  0b00..DEFAULT
61022  */
61023 #define IOMUXD_FLEXCAN1_RX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN1_RX_sw_config_MASK)
61024 #define IOMUXD_FLEXCAN1_RX_mux_mode_MASK         (0x38000000U)
61025 #define IOMUXD_FLEXCAN1_RX_mux_mode_SHIFT        (27U)
61026 /*! mux_mode - mux_mode
61027  *  0b000..ADMA.FLEXCAN1.RX
61028  *  0b001..ADMA.SAI2.RXFS
61029  *  0b010..ADMA.FTM.CH2
61030  *  0b011..ADMA.SAI1.TXD
61031  *  0b100..LSIO.GPIO1.IO17
61032  */
61033 #define IOMUXD_FLEXCAN1_RX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_RX_mux_mode_MASK)
61034 #define IOMUXD_FLEXCAN1_RX_update_pad_ctl_MASK   (0x40000000U)
61035 #define IOMUXD_FLEXCAN1_RX_update_pad_ctl_SHIFT  (30U)
61036 /*! update_pad_ctl - update lock for pad control
61037  */
61038 #define IOMUXD_FLEXCAN1_RX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN1_RX_update_pad_ctl_MASK)
61039 #define IOMUXD_FLEXCAN1_RX_update_mux_mode_MASK  (0x80000000U)
61040 #define IOMUXD_FLEXCAN1_RX_update_mux_mode_SHIFT (31U)
61041 /*! update_mux_mode - update lock for mux control
61042  */
61043 #define IOMUXD_FLEXCAN1_RX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_RX_update_mux_mode_MASK)
61044 /*! @} */
61045 
61046 /*! @name FLEXCAN1_TX - FLEXCAN1_TX */
61047 /*! @{ */
61048 #define IOMUXD_FLEXCAN1_TX_PDRV_MASK             (0x1U)
61049 #define IOMUXD_FLEXCAN1_TX_PDRV_SHIFT            (0U)
61050 /*! PDRV - Drive
61051  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61052  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61053  */
61054 #define IOMUXD_FLEXCAN1_TX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN1_TX_PDRV_MASK)
61055 #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_MASK (0x1EU)
61056 #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_SHIFT (1U)
61057 /*! FLEXCAN1_TX_reserved_1_4 - reserved
61058  */
61059 #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_MASK)
61060 #define IOMUXD_FLEXCAN1_TX_PULL_MASK             (0x60U)
61061 #define IOMUXD_FLEXCAN1_TX_PULL_SHIFT            (5U)
61062 /*! PULL - Pull Down Pull Up
61063  *  0b10..pull down
61064  *  0b01..pull up
61065  *  0b00..Prohibited
61066  *  0b11..pull disabled
61067  */
61068 #define IOMUXD_FLEXCAN1_TX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN1_TX_PULL_MASK)
61069 #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_MASK (0x7FF80U)
61070 #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_SHIFT (7U)
61071 /*! FLEXCAN1_TX_reserved_7_18 - reserved
61072  */
61073 #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_MASK)
61074 #define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_MASK      (0x380000U)
61075 #define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_SHIFT     (19U)
61076 /*! WAKEUP_CTRL - wakeup control
61077  *  0b000..OFF
61078  *  0b001..RESAMPLE
61079  *  0b100..LOW
61080  *  0b111..HIGH
61081  *  0b110..RISE
61082  *  0b101..FALL
61083  */
61084 #define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_MASK)
61085 #define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_MASK      (0x400000U)
61086 #define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_SHIFT     (22U)
61087 /*! WAKEUP_MASK - wakeup mask
61088  */
61089 #define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_MASK)
61090 #define IOMUXD_FLEXCAN1_TX_lp_config_MASK        (0x1800000U)
61091 #define IOMUXD_FLEXCAN1_TX_lp_config_SHIFT       (23U)
61092 /*! lp_config - lower power configuration
61093  *  0b01..EARLY_ISO
61094  *  0b10..LATE_ISO
61095  *  0b11..LATCH
61096  *  0b00..PASS
61097  */
61098 #define IOMUXD_FLEXCAN1_TX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN1_TX_lp_config_MASK)
61099 #define IOMUXD_FLEXCAN1_TX_sw_config_MASK        (0x6000000U)
61100 #define IOMUXD_FLEXCAN1_TX_sw_config_SHIFT       (25U)
61101 /*! sw_config - output and input configuration
61102  *  0b01..OPEN_DRAIN
61103  *  0b10..OPEN_DRAIN_INPUT
61104  *  0b11..INOUT
61105  *  0b00..DEFAULT
61106  */
61107 #define IOMUXD_FLEXCAN1_TX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN1_TX_sw_config_MASK)
61108 #define IOMUXD_FLEXCAN1_TX_mux_mode_MASK         (0x38000000U)
61109 #define IOMUXD_FLEXCAN1_TX_mux_mode_SHIFT        (27U)
61110 /*! mux_mode - mux_mode
61111  *  0b000..ADMA.FLEXCAN1.TX
61112  *  0b001..ADMA.SAI3.RXC
61113  *  0b010..ADMA.DMA0.REQ_IN0
61114  *  0b011..ADMA.SAI1.RXD
61115  *  0b100..LSIO.GPIO1.IO18
61116  */
61117 #define IOMUXD_FLEXCAN1_TX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_TX_mux_mode_MASK)
61118 #define IOMUXD_FLEXCAN1_TX_update_pad_ctl_MASK   (0x40000000U)
61119 #define IOMUXD_FLEXCAN1_TX_update_pad_ctl_SHIFT  (30U)
61120 /*! update_pad_ctl - update lock for pad control
61121  */
61122 #define IOMUXD_FLEXCAN1_TX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN1_TX_update_pad_ctl_MASK)
61123 #define IOMUXD_FLEXCAN1_TX_update_mux_mode_MASK  (0x80000000U)
61124 #define IOMUXD_FLEXCAN1_TX_update_mux_mode_SHIFT (31U)
61125 /*! update_mux_mode - update lock for mux control
61126  */
61127 #define IOMUXD_FLEXCAN1_TX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_TX_update_mux_mode_MASK)
61128 /*! @} */
61129 
61130 /*! @name FLEXCAN2_RX - FLEXCAN2_RX */
61131 /*! @{ */
61132 #define IOMUXD_FLEXCAN2_RX_PDRV_MASK             (0x1U)
61133 #define IOMUXD_FLEXCAN2_RX_PDRV_SHIFT            (0U)
61134 /*! PDRV - Drive
61135  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61136  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61137  */
61138 #define IOMUXD_FLEXCAN2_RX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN2_RX_PDRV_MASK)
61139 #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_MASK (0x1EU)
61140 #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_SHIFT (1U)
61141 /*! FLEXCAN2_RX_reserved_1_4 - reserved
61142  */
61143 #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_MASK)
61144 #define IOMUXD_FLEXCAN2_RX_PULL_MASK             (0x60U)
61145 #define IOMUXD_FLEXCAN2_RX_PULL_SHIFT            (5U)
61146 /*! PULL - Pull Down Pull Up
61147  *  0b10..pull down
61148  *  0b01..pull up
61149  *  0b00..Prohibited
61150  *  0b11..pull disabled
61151  */
61152 #define IOMUXD_FLEXCAN2_RX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN2_RX_PULL_MASK)
61153 #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_MASK (0x7FF80U)
61154 #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_SHIFT (7U)
61155 /*! FLEXCAN2_RX_reserved_7_18 - reserved
61156  */
61157 #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_MASK)
61158 #define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_MASK      (0x380000U)
61159 #define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_SHIFT     (19U)
61160 /*! WAKEUP_CTRL - wakeup control
61161  *  0b000..OFF
61162  *  0b001..RESAMPLE
61163  *  0b100..LOW
61164  *  0b111..HIGH
61165  *  0b110..RISE
61166  *  0b101..FALL
61167  */
61168 #define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_MASK)
61169 #define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_MASK      (0x400000U)
61170 #define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_SHIFT     (22U)
61171 /*! WAKEUP_MASK - wakeup mask
61172  */
61173 #define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_MASK)
61174 #define IOMUXD_FLEXCAN2_RX_lp_config_MASK        (0x1800000U)
61175 #define IOMUXD_FLEXCAN2_RX_lp_config_SHIFT       (23U)
61176 /*! lp_config - lower power configuration
61177  *  0b01..EARLY_ISO
61178  *  0b10..LATE_ISO
61179  *  0b11..LATCH
61180  *  0b00..PASS
61181  */
61182 #define IOMUXD_FLEXCAN2_RX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN2_RX_lp_config_MASK)
61183 #define IOMUXD_FLEXCAN2_RX_sw_config_MASK        (0x6000000U)
61184 #define IOMUXD_FLEXCAN2_RX_sw_config_SHIFT       (25U)
61185 /*! sw_config - output and input configuration
61186  *  0b01..OPEN_DRAIN
61187  *  0b10..OPEN_DRAIN_INPUT
61188  *  0b11..INOUT
61189  *  0b00..DEFAULT
61190  */
61191 #define IOMUXD_FLEXCAN2_RX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN2_RX_sw_config_MASK)
61192 #define IOMUXD_FLEXCAN2_RX_mux_mode_MASK         (0x38000000U)
61193 #define IOMUXD_FLEXCAN2_RX_mux_mode_SHIFT        (27U)
61194 /*! mux_mode - mux_mode
61195  *  0b000..ADMA.FLEXCAN2.RX
61196  *  0b001..ADMA.SAI3.RXD
61197  *  0b010..ADMA.UART3.RX
61198  *  0b011..ADMA.SAI1.RXFS
61199  *  0b100..LSIO.GPIO1.IO19
61200  */
61201 #define IOMUXD_FLEXCAN2_RX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_RX_mux_mode_MASK)
61202 #define IOMUXD_FLEXCAN2_RX_update_pad_ctl_MASK   (0x40000000U)
61203 #define IOMUXD_FLEXCAN2_RX_update_pad_ctl_SHIFT  (30U)
61204 /*! update_pad_ctl - update lock for pad control
61205  */
61206 #define IOMUXD_FLEXCAN2_RX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN2_RX_update_pad_ctl_MASK)
61207 #define IOMUXD_FLEXCAN2_RX_update_mux_mode_MASK  (0x80000000U)
61208 #define IOMUXD_FLEXCAN2_RX_update_mux_mode_SHIFT (31U)
61209 /*! update_mux_mode - update lock for mux control
61210  */
61211 #define IOMUXD_FLEXCAN2_RX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_RX_update_mux_mode_MASK)
61212 /*! @} */
61213 
61214 /*! @name FLEXCAN2_TX - FLEXCAN2_TX */
61215 /*! @{ */
61216 #define IOMUXD_FLEXCAN2_TX_PDRV_MASK             (0x1U)
61217 #define IOMUXD_FLEXCAN2_TX_PDRV_SHIFT            (0U)
61218 /*! PDRV - Drive
61219  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61220  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61221  */
61222 #define IOMUXD_FLEXCAN2_TX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN2_TX_PDRV_MASK)
61223 #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_MASK (0x1EU)
61224 #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_SHIFT (1U)
61225 /*! FLEXCAN2_TX_reserved_1_4 - reserved
61226  */
61227 #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_MASK)
61228 #define IOMUXD_FLEXCAN2_TX_PULL_MASK             (0x60U)
61229 #define IOMUXD_FLEXCAN2_TX_PULL_SHIFT            (5U)
61230 /*! PULL - Pull Down Pull Up
61231  *  0b10..pull down
61232  *  0b01..pull up
61233  *  0b00..Prohibited
61234  *  0b11..pull disabled
61235  */
61236 #define IOMUXD_FLEXCAN2_TX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN2_TX_PULL_MASK)
61237 #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_MASK (0x7FF80U)
61238 #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_SHIFT (7U)
61239 /*! FLEXCAN2_TX_reserved_7_18 - reserved
61240  */
61241 #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_MASK)
61242 #define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_MASK      (0x380000U)
61243 #define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_SHIFT     (19U)
61244 /*! WAKEUP_CTRL - wakeup control
61245  *  0b000..OFF
61246  *  0b001..RESAMPLE
61247  *  0b100..LOW
61248  *  0b111..HIGH
61249  *  0b110..RISE
61250  *  0b101..FALL
61251  */
61252 #define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_MASK)
61253 #define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_MASK      (0x400000U)
61254 #define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_SHIFT     (22U)
61255 /*! WAKEUP_MASK - wakeup mask
61256  */
61257 #define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_MASK)
61258 #define IOMUXD_FLEXCAN2_TX_lp_config_MASK        (0x1800000U)
61259 #define IOMUXD_FLEXCAN2_TX_lp_config_SHIFT       (23U)
61260 /*! lp_config - lower power configuration
61261  *  0b01..EARLY_ISO
61262  *  0b10..LATE_ISO
61263  *  0b11..LATCH
61264  *  0b00..PASS
61265  */
61266 #define IOMUXD_FLEXCAN2_TX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN2_TX_lp_config_MASK)
61267 #define IOMUXD_FLEXCAN2_TX_sw_config_MASK        (0x6000000U)
61268 #define IOMUXD_FLEXCAN2_TX_sw_config_SHIFT       (25U)
61269 /*! sw_config - output and input configuration
61270  *  0b01..OPEN_DRAIN
61271  *  0b10..OPEN_DRAIN_INPUT
61272  *  0b11..INOUT
61273  *  0b00..DEFAULT
61274  */
61275 #define IOMUXD_FLEXCAN2_TX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN2_TX_sw_config_MASK)
61276 #define IOMUXD_FLEXCAN2_TX_mux_mode_MASK         (0x38000000U)
61277 #define IOMUXD_FLEXCAN2_TX_mux_mode_SHIFT        (27U)
61278 /*! mux_mode - mux_mode
61279  *  0b000..ADMA.FLEXCAN2.TX
61280  *  0b001..ADMA.SAI3.RXFS
61281  *  0b010..ADMA.UART3.TX
61282  *  0b011..ADMA.SAI1.RXC
61283  *  0b100..LSIO.GPIO1.IO20
61284  */
61285 #define IOMUXD_FLEXCAN2_TX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_TX_mux_mode_MASK)
61286 #define IOMUXD_FLEXCAN2_TX_update_pad_ctl_MASK   (0x40000000U)
61287 #define IOMUXD_FLEXCAN2_TX_update_pad_ctl_SHIFT  (30U)
61288 /*! update_pad_ctl - update lock for pad control
61289  */
61290 #define IOMUXD_FLEXCAN2_TX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN2_TX_update_pad_ctl_MASK)
61291 #define IOMUXD_FLEXCAN2_TX_update_mux_mode_MASK  (0x80000000U)
61292 #define IOMUXD_FLEXCAN2_TX_update_mux_mode_SHIFT (31U)
61293 /*! update_mux_mode - update lock for mux control
61294  */
61295 #define IOMUXD_FLEXCAN2_TX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_TX_update_mux_mode_MASK)
61296 /*! @} */
61297 
61298 /*! @name UART0_RX - UART0_RX */
61299 /*! @{ */
61300 #define IOMUXD_UART0_RX_PDRV_MASK                (0x1U)
61301 #define IOMUXD_UART0_RX_PDRV_SHIFT               (0U)
61302 /*! PDRV - Drive
61303  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61304  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61305  */
61306 #define IOMUXD_UART0_RX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_PDRV_SHIFT)) & IOMUXD_UART0_RX_PDRV_MASK)
61307 #define IOMUXD_UART0_RX_UART0_RX_reserved_1_4_MASK (0x1EU)
61308 #define IOMUXD_UART0_RX_UART0_RX_reserved_1_4_SHIFT (1U)
61309 /*! UART0_RX_reserved_1_4 - reserved
61310  */
61311 #define IOMUXD_UART0_RX_UART0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_UART0_RX_reserved_1_4_SHIFT)) & IOMUXD_UART0_RX_UART0_RX_reserved_1_4_MASK)
61312 #define IOMUXD_UART0_RX_PULL_MASK                (0x60U)
61313 #define IOMUXD_UART0_RX_PULL_SHIFT               (5U)
61314 /*! PULL - Pull Down Pull Up
61315  *  0b10..pull down
61316  *  0b01..pull up
61317  *  0b00..Prohibited
61318  *  0b11..pull disabled
61319  */
61320 #define IOMUXD_UART0_RX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_PULL_SHIFT)) & IOMUXD_UART0_RX_PULL_MASK)
61321 #define IOMUXD_UART0_RX_UART0_RX_reserved_7_18_MASK (0x7FF80U)
61322 #define IOMUXD_UART0_RX_UART0_RX_reserved_7_18_SHIFT (7U)
61323 /*! UART0_RX_reserved_7_18 - reserved
61324  */
61325 #define IOMUXD_UART0_RX_UART0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_UART0_RX_reserved_7_18_SHIFT)) & IOMUXD_UART0_RX_UART0_RX_reserved_7_18_MASK)
61326 #define IOMUXD_UART0_RX_WAKEUP_CTRL_MASK         (0x380000U)
61327 #define IOMUXD_UART0_RX_WAKEUP_CTRL_SHIFT        (19U)
61328 /*! WAKEUP_CTRL - wakeup control
61329  *  0b000..OFF
61330  *  0b001..RESAMPLE
61331  *  0b100..LOW
61332  *  0b111..HIGH
61333  *  0b110..RISE
61334  *  0b101..FALL
61335  */
61336 #define IOMUXD_UART0_RX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_RX_WAKEUP_CTRL_MASK)
61337 #define IOMUXD_UART0_RX_WAKEUP_MASK_MASK         (0x400000U)
61338 #define IOMUXD_UART0_RX_WAKEUP_MASK_SHIFT        (22U)
61339 /*! WAKEUP_MASK - wakeup mask
61340  */
61341 #define IOMUXD_UART0_RX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_RX_WAKEUP_MASK_MASK)
61342 #define IOMUXD_UART0_RX_lp_config_MASK           (0x1800000U)
61343 #define IOMUXD_UART0_RX_lp_config_SHIFT          (23U)
61344 /*! lp_config - lower power configuration
61345  *  0b01..EARLY_ISO
61346  *  0b10..LATE_ISO
61347  *  0b11..LATCH
61348  *  0b00..PASS
61349  */
61350 #define IOMUXD_UART0_RX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_lp_config_SHIFT)) & IOMUXD_UART0_RX_lp_config_MASK)
61351 #define IOMUXD_UART0_RX_sw_config_MASK           (0x6000000U)
61352 #define IOMUXD_UART0_RX_sw_config_SHIFT          (25U)
61353 /*! sw_config - output and input configuration
61354  *  0b01..OPEN_DRAIN
61355  *  0b10..OPEN_DRAIN_INPUT
61356  *  0b11..INOUT
61357  *  0b00..DEFAULT
61358  */
61359 #define IOMUXD_UART0_RX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_sw_config_SHIFT)) & IOMUXD_UART0_RX_sw_config_MASK)
61360 #define IOMUXD_UART0_RX_mux_mode_MASK            (0x38000000U)
61361 #define IOMUXD_UART0_RX_mux_mode_SHIFT           (27U)
61362 /*! mux_mode - mux_mode
61363  *  0b000..ADMA.UART0.RX
61364  *  0b001..ADMA.MQS.R
61365  *  0b010..ADMA.FLEXCAN0.RX
61366  *  0b011..SCU.UART0.RX
61367  *  0b100..LSIO.GPIO1.IO21
61368  */
61369 #define IOMUXD_UART0_RX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_mux_mode_SHIFT)) & IOMUXD_UART0_RX_mux_mode_MASK)
61370 #define IOMUXD_UART0_RX_update_pad_ctl_MASK      (0x40000000U)
61371 #define IOMUXD_UART0_RX_update_pad_ctl_SHIFT     (30U)
61372 /*! update_pad_ctl - update lock for pad control
61373  */
61374 #define IOMUXD_UART0_RX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART0_RX_update_pad_ctl_MASK)
61375 #define IOMUXD_UART0_RX_update_mux_mode_MASK     (0x80000000U)
61376 #define IOMUXD_UART0_RX_update_mux_mode_SHIFT    (31U)
61377 /*! update_mux_mode - update lock for mux control
61378  */
61379 #define IOMUXD_UART0_RX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_update_mux_mode_SHIFT)) & IOMUXD_UART0_RX_update_mux_mode_MASK)
61380 /*! @} */
61381 
61382 /*! @name IOMUXD_GROUP_2_1 - na */
61383 /*! @{ */
61384 #define IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_MASK    (0x1U)
61385 #define IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_SHIFT   (0U)
61386 /*! SPI0_CS0 - wakeup from SPI0_CS0
61387  */
61388 #define IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_MASK)
61389 #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_MASK (0x2U)
61390 #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_SHIFT (1U)
61391 /*! iomuxd_group_2_1_reserved_1_1 - reserved
61392  */
61393 #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_MASK)
61394 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_MASK     (0x4U)
61395 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_SHIFT    (2U)
61396 /*! ADC_IN1 - wakeup from ADC_IN1
61397  */
61398 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_MASK)
61399 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_MASK     (0x8U)
61400 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_SHIFT    (3U)
61401 /*! ADC_IN0 - wakeup from ADC_IN0
61402  */
61403 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_MASK)
61404 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_MASK     (0x10U)
61405 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_SHIFT    (4U)
61406 /*! ADC_IN3 - wakeup from ADC_IN3
61407  */
61408 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_MASK)
61409 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_MASK     (0x20U)
61410 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_SHIFT    (5U)
61411 /*! ADC_IN2 - wakeup from ADC_IN2
61412  */
61413 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_MASK)
61414 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_MASK     (0x40U)
61415 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_SHIFT    (6U)
61416 /*! ADC_IN5 - wakeup from ADC_IN5
61417  */
61418 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_MASK)
61419 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_MASK     (0x80U)
61420 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_SHIFT    (7U)
61421 /*! ADC_IN4 - wakeup from ADC_IN4
61422  */
61423 #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_MASK)
61424 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_MASK (0x100U)
61425 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_SHIFT (8U)
61426 /*! FLEXCAN0_RX - wakeup from FLEXCAN0_RX
61427  */
61428 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_MASK)
61429 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_MASK (0x200U)
61430 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_SHIFT (9U)
61431 /*! FLEXCAN0_TX - wakeup from FLEXCAN0_TX
61432  */
61433 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_MASK)
61434 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_MASK (0x400U)
61435 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_SHIFT (10U)
61436 /*! FLEXCAN1_RX - wakeup from FLEXCAN1_RX
61437  */
61438 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_MASK)
61439 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_MASK (0x800U)
61440 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_SHIFT (11U)
61441 /*! FLEXCAN1_TX - wakeup from FLEXCAN1_TX
61442  */
61443 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_MASK)
61444 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_MASK (0x1000U)
61445 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_SHIFT (12U)
61446 /*! FLEXCAN2_RX - wakeup from FLEXCAN2_RX
61447  */
61448 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_MASK)
61449 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_MASK (0x2000U)
61450 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_SHIFT (13U)
61451 /*! FLEXCAN2_TX - wakeup from FLEXCAN2_TX
61452  */
61453 #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_MASK)
61454 #define IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_MASK    (0x4000U)
61455 #define IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_SHIFT   (14U)
61456 /*! UART0_RX - wakeup from UART0_RX
61457  */
61458 #define IOMUXD_IOMUXD_GROUP_2_1_UART0_RX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_MASK)
61459 #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_MASK (0xFFFF8000U)
61460 #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_SHIFT (15U)
61461 /*! iomuxd_group_2_1_reserved_15_31 - reserved
61462  */
61463 #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_MASK)
61464 /*! @} */
61465 
61466 /*! @name UART0_TX - UART0_TX */
61467 /*! @{ */
61468 #define IOMUXD_UART0_TX_PDRV_MASK                (0x1U)
61469 #define IOMUXD_UART0_TX_PDRV_SHIFT               (0U)
61470 /*! PDRV - Drive
61471  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61472  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61473  */
61474 #define IOMUXD_UART0_TX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_PDRV_SHIFT)) & IOMUXD_UART0_TX_PDRV_MASK)
61475 #define IOMUXD_UART0_TX_UART0_TX_reserved_1_4_MASK (0x1EU)
61476 #define IOMUXD_UART0_TX_UART0_TX_reserved_1_4_SHIFT (1U)
61477 /*! UART0_TX_reserved_1_4 - reserved
61478  */
61479 #define IOMUXD_UART0_TX_UART0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_UART0_TX_reserved_1_4_SHIFT)) & IOMUXD_UART0_TX_UART0_TX_reserved_1_4_MASK)
61480 #define IOMUXD_UART0_TX_PULL_MASK                (0x60U)
61481 #define IOMUXD_UART0_TX_PULL_SHIFT               (5U)
61482 /*! PULL - Pull Down Pull Up
61483  *  0b10..pull down
61484  *  0b01..pull up
61485  *  0b00..Prohibited
61486  *  0b11..pull disabled
61487  */
61488 #define IOMUXD_UART0_TX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_PULL_SHIFT)) & IOMUXD_UART0_TX_PULL_MASK)
61489 #define IOMUXD_UART0_TX_UART0_TX_reserved_7_18_MASK (0x7FF80U)
61490 #define IOMUXD_UART0_TX_UART0_TX_reserved_7_18_SHIFT (7U)
61491 /*! UART0_TX_reserved_7_18 - reserved
61492  */
61493 #define IOMUXD_UART0_TX_UART0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_UART0_TX_reserved_7_18_SHIFT)) & IOMUXD_UART0_TX_UART0_TX_reserved_7_18_MASK)
61494 #define IOMUXD_UART0_TX_WAKEUP_CTRL_MASK         (0x380000U)
61495 #define IOMUXD_UART0_TX_WAKEUP_CTRL_SHIFT        (19U)
61496 /*! WAKEUP_CTRL - wakeup control
61497  *  0b000..OFF
61498  *  0b001..RESAMPLE
61499  *  0b100..LOW
61500  *  0b111..HIGH
61501  *  0b110..RISE
61502  *  0b101..FALL
61503  */
61504 #define IOMUXD_UART0_TX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_TX_WAKEUP_CTRL_MASK)
61505 #define IOMUXD_UART0_TX_WAKEUP_MASK_MASK         (0x400000U)
61506 #define IOMUXD_UART0_TX_WAKEUP_MASK_SHIFT        (22U)
61507 /*! WAKEUP_MASK - wakeup mask
61508  */
61509 #define IOMUXD_UART0_TX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_TX_WAKEUP_MASK_MASK)
61510 #define IOMUXD_UART0_TX_lp_config_MASK           (0x1800000U)
61511 #define IOMUXD_UART0_TX_lp_config_SHIFT          (23U)
61512 /*! lp_config - lower power configuration
61513  *  0b01..EARLY_ISO
61514  *  0b10..LATE_ISO
61515  *  0b11..LATCH
61516  *  0b00..PASS
61517  */
61518 #define IOMUXD_UART0_TX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_lp_config_SHIFT)) & IOMUXD_UART0_TX_lp_config_MASK)
61519 #define IOMUXD_UART0_TX_sw_config_MASK           (0x6000000U)
61520 #define IOMUXD_UART0_TX_sw_config_SHIFT          (25U)
61521 /*! sw_config - output and input configuration
61522  *  0b01..OPEN_DRAIN
61523  *  0b10..OPEN_DRAIN_INPUT
61524  *  0b11..INOUT
61525  *  0b00..DEFAULT
61526  */
61527 #define IOMUXD_UART0_TX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_sw_config_SHIFT)) & IOMUXD_UART0_TX_sw_config_MASK)
61528 #define IOMUXD_UART0_TX_mux_mode_MASK            (0x38000000U)
61529 #define IOMUXD_UART0_TX_mux_mode_SHIFT           (27U)
61530 /*! mux_mode - mux_mode
61531  *  0b000..ADMA.UART0.TX
61532  *  0b001..ADMA.MQS.L
61533  *  0b010..ADMA.FLEXCAN0.TX
61534  *  0b011..SCU.UART0.TX
61535  *  0b100..LSIO.GPIO1.IO22
61536  */
61537 #define IOMUXD_UART0_TX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_mux_mode_SHIFT)) & IOMUXD_UART0_TX_mux_mode_MASK)
61538 #define IOMUXD_UART0_TX_update_pad_ctl_MASK      (0x40000000U)
61539 #define IOMUXD_UART0_TX_update_pad_ctl_SHIFT     (30U)
61540 /*! update_pad_ctl - update lock for pad control
61541  */
61542 #define IOMUXD_UART0_TX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART0_TX_update_pad_ctl_MASK)
61543 #define IOMUXD_UART0_TX_update_mux_mode_MASK     (0x80000000U)
61544 #define IOMUXD_UART0_TX_update_mux_mode_SHIFT    (31U)
61545 /*! update_mux_mode - update lock for mux control
61546  */
61547 #define IOMUXD_UART0_TX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_update_mux_mode_SHIFT)) & IOMUXD_UART0_TX_update_mux_mode_MASK)
61548 /*! @} */
61549 
61550 /*! @name UART2_TX - UART2_TX */
61551 /*! @{ */
61552 #define IOMUXD_UART2_TX_PDRV_MASK                (0x1U)
61553 #define IOMUXD_UART2_TX_PDRV_SHIFT               (0U)
61554 /*! PDRV - Drive
61555  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61556  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61557  */
61558 #define IOMUXD_UART2_TX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_PDRV_SHIFT)) & IOMUXD_UART2_TX_PDRV_MASK)
61559 #define IOMUXD_UART2_TX_UART2_TX_reserved_1_4_MASK (0x1EU)
61560 #define IOMUXD_UART2_TX_UART2_TX_reserved_1_4_SHIFT (1U)
61561 /*! UART2_TX_reserved_1_4 - reserved
61562  */
61563 #define IOMUXD_UART2_TX_UART2_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_UART2_TX_reserved_1_4_SHIFT)) & IOMUXD_UART2_TX_UART2_TX_reserved_1_4_MASK)
61564 #define IOMUXD_UART2_TX_PULL_MASK                (0x60U)
61565 #define IOMUXD_UART2_TX_PULL_SHIFT               (5U)
61566 /*! PULL - Pull Down Pull Up
61567  *  0b10..pull down
61568  *  0b01..pull up
61569  *  0b00..Prohibited
61570  *  0b11..pull disabled
61571  */
61572 #define IOMUXD_UART2_TX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_PULL_SHIFT)) & IOMUXD_UART2_TX_PULL_MASK)
61573 #define IOMUXD_UART2_TX_UART2_TX_reserved_7_18_MASK (0x7FF80U)
61574 #define IOMUXD_UART2_TX_UART2_TX_reserved_7_18_SHIFT (7U)
61575 /*! UART2_TX_reserved_7_18 - reserved
61576  */
61577 #define IOMUXD_UART2_TX_UART2_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_UART2_TX_reserved_7_18_SHIFT)) & IOMUXD_UART2_TX_UART2_TX_reserved_7_18_MASK)
61578 #define IOMUXD_UART2_TX_WAKEUP_CTRL_MASK         (0x380000U)
61579 #define IOMUXD_UART2_TX_WAKEUP_CTRL_SHIFT        (19U)
61580 /*! WAKEUP_CTRL - wakeup control
61581  *  0b000..OFF
61582  *  0b001..RESAMPLE
61583  *  0b100..LOW
61584  *  0b111..HIGH
61585  *  0b110..RISE
61586  *  0b101..FALL
61587  */
61588 #define IOMUXD_UART2_TX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART2_TX_WAKEUP_CTRL_MASK)
61589 #define IOMUXD_UART2_TX_WAKEUP_MASK_MASK         (0x400000U)
61590 #define IOMUXD_UART2_TX_WAKEUP_MASK_SHIFT        (22U)
61591 /*! WAKEUP_MASK - wakeup mask
61592  */
61593 #define IOMUXD_UART2_TX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART2_TX_WAKEUP_MASK_MASK)
61594 #define IOMUXD_UART2_TX_lp_config_MASK           (0x1800000U)
61595 #define IOMUXD_UART2_TX_lp_config_SHIFT          (23U)
61596 /*! lp_config - lower power configuration
61597  *  0b01..EARLY_ISO
61598  *  0b10..LATE_ISO
61599  *  0b11..LATCH
61600  *  0b00..PASS
61601  */
61602 #define IOMUXD_UART2_TX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_lp_config_SHIFT)) & IOMUXD_UART2_TX_lp_config_MASK)
61603 #define IOMUXD_UART2_TX_sw_config_MASK           (0x6000000U)
61604 #define IOMUXD_UART2_TX_sw_config_SHIFT          (25U)
61605 /*! sw_config - output and input configuration
61606  *  0b01..OPEN_DRAIN
61607  *  0b10..OPEN_DRAIN_INPUT
61608  *  0b11..INOUT
61609  *  0b00..DEFAULT
61610  */
61611 #define IOMUXD_UART2_TX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_sw_config_SHIFT)) & IOMUXD_UART2_TX_sw_config_MASK)
61612 #define IOMUXD_UART2_TX_mux_mode_MASK            (0x38000000U)
61613 #define IOMUXD_UART2_TX_mux_mode_SHIFT           (27U)
61614 /*! mux_mode - mux_mode
61615  *  0b000..ADMA.UART2.TX
61616  *  0b001..ADMA.FTM.CH1
61617  *  0b010..ADMA.FLEXCAN1.TX
61618  *  0b100..LSIO.GPIO1.IO23
61619  */
61620 #define IOMUXD_UART2_TX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_mux_mode_SHIFT)) & IOMUXD_UART2_TX_mux_mode_MASK)
61621 #define IOMUXD_UART2_TX_update_pad_ctl_MASK      (0x40000000U)
61622 #define IOMUXD_UART2_TX_update_pad_ctl_SHIFT     (30U)
61623 /*! update_pad_ctl - update lock for pad control
61624  */
61625 #define IOMUXD_UART2_TX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART2_TX_update_pad_ctl_MASK)
61626 #define IOMUXD_UART2_TX_update_mux_mode_MASK     (0x80000000U)
61627 #define IOMUXD_UART2_TX_update_mux_mode_SHIFT    (31U)
61628 /*! update_mux_mode - update lock for mux control
61629  */
61630 #define IOMUXD_UART2_TX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_update_mux_mode_SHIFT)) & IOMUXD_UART2_TX_update_mux_mode_MASK)
61631 /*! @} */
61632 
61633 /*! @name UART2_RX - UART2_RX */
61634 /*! @{ */
61635 #define IOMUXD_UART2_RX_PDRV_MASK                (0x1U)
61636 #define IOMUXD_UART2_RX_PDRV_SHIFT               (0U)
61637 /*! PDRV - Drive
61638  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61639  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61640  */
61641 #define IOMUXD_UART2_RX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_PDRV_SHIFT)) & IOMUXD_UART2_RX_PDRV_MASK)
61642 #define IOMUXD_UART2_RX_UART2_RX_reserved_1_4_MASK (0x1EU)
61643 #define IOMUXD_UART2_RX_UART2_RX_reserved_1_4_SHIFT (1U)
61644 /*! UART2_RX_reserved_1_4 - reserved
61645  */
61646 #define IOMUXD_UART2_RX_UART2_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_UART2_RX_reserved_1_4_SHIFT)) & IOMUXD_UART2_RX_UART2_RX_reserved_1_4_MASK)
61647 #define IOMUXD_UART2_RX_PULL_MASK                (0x60U)
61648 #define IOMUXD_UART2_RX_PULL_SHIFT               (5U)
61649 /*! PULL - Pull Down Pull Up
61650  *  0b10..pull down
61651  *  0b01..pull up
61652  *  0b00..Prohibited
61653  *  0b11..pull disabled
61654  */
61655 #define IOMUXD_UART2_RX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_PULL_SHIFT)) & IOMUXD_UART2_RX_PULL_MASK)
61656 #define IOMUXD_UART2_RX_UART2_RX_reserved_7_18_MASK (0x7FF80U)
61657 #define IOMUXD_UART2_RX_UART2_RX_reserved_7_18_SHIFT (7U)
61658 /*! UART2_RX_reserved_7_18 - reserved
61659  */
61660 #define IOMUXD_UART2_RX_UART2_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_UART2_RX_reserved_7_18_SHIFT)) & IOMUXD_UART2_RX_UART2_RX_reserved_7_18_MASK)
61661 #define IOMUXD_UART2_RX_WAKEUP_CTRL_MASK         (0x380000U)
61662 #define IOMUXD_UART2_RX_WAKEUP_CTRL_SHIFT        (19U)
61663 /*! WAKEUP_CTRL - wakeup control
61664  *  0b000..OFF
61665  *  0b001..RESAMPLE
61666  *  0b100..LOW
61667  *  0b111..HIGH
61668  *  0b110..RISE
61669  *  0b101..FALL
61670  */
61671 #define IOMUXD_UART2_RX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART2_RX_WAKEUP_CTRL_MASK)
61672 #define IOMUXD_UART2_RX_WAKEUP_MASK_MASK         (0x400000U)
61673 #define IOMUXD_UART2_RX_WAKEUP_MASK_SHIFT        (22U)
61674 /*! WAKEUP_MASK - wakeup mask
61675  */
61676 #define IOMUXD_UART2_RX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART2_RX_WAKEUP_MASK_MASK)
61677 #define IOMUXD_UART2_RX_lp_config_MASK           (0x1800000U)
61678 #define IOMUXD_UART2_RX_lp_config_SHIFT          (23U)
61679 /*! lp_config - lower power configuration
61680  *  0b01..EARLY_ISO
61681  *  0b10..LATE_ISO
61682  *  0b11..LATCH
61683  *  0b00..PASS
61684  */
61685 #define IOMUXD_UART2_RX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_lp_config_SHIFT)) & IOMUXD_UART2_RX_lp_config_MASK)
61686 #define IOMUXD_UART2_RX_sw_config_MASK           (0x6000000U)
61687 #define IOMUXD_UART2_RX_sw_config_SHIFT          (25U)
61688 /*! sw_config - output and input configuration
61689  *  0b01..OPEN_DRAIN
61690  *  0b10..OPEN_DRAIN_INPUT
61691  *  0b11..INOUT
61692  *  0b00..DEFAULT
61693  */
61694 #define IOMUXD_UART2_RX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_sw_config_SHIFT)) & IOMUXD_UART2_RX_sw_config_MASK)
61695 #define IOMUXD_UART2_RX_mux_mode_MASK            (0x38000000U)
61696 #define IOMUXD_UART2_RX_mux_mode_SHIFT           (27U)
61697 /*! mux_mode - mux_mode
61698  *  0b000..ADMA.UART2.RX
61699  *  0b001..ADMA.FTM.CH0
61700  *  0b010..ADMA.FLEXCAN1.RX
61701  *  0b100..LSIO.GPIO1.IO24
61702  */
61703 #define IOMUXD_UART2_RX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_mux_mode_SHIFT)) & IOMUXD_UART2_RX_mux_mode_MASK)
61704 #define IOMUXD_UART2_RX_update_pad_ctl_MASK      (0x40000000U)
61705 #define IOMUXD_UART2_RX_update_pad_ctl_SHIFT     (30U)
61706 /*! update_pad_ctl - update lock for pad control
61707  */
61708 #define IOMUXD_UART2_RX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART2_RX_update_pad_ctl_MASK)
61709 #define IOMUXD_UART2_RX_update_mux_mode_MASK     (0x80000000U)
61710 #define IOMUXD_UART2_RX_update_mux_mode_SHIFT    (31U)
61711 /*! update_mux_mode - update lock for mux control
61712  */
61713 #define IOMUXD_UART2_RX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_update_mux_mode_SHIFT)) & IOMUXD_UART2_RX_update_mux_mode_MASK)
61714 /*! @} */
61715 
61716 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH */
61717 /*! @{ */
61718 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_MASK (0x7U)
61719 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_SHIFT (0U)
61720 /*! COMP - COMP
61721  *  0b010..Fixed code mode
61722  *  0b100..High impedance mode
61723  *  0b110..Read mode
61724  *  0b000..Normal Mode
61725  *  0b001..Freeze Mode
61726  */
61727 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_MASK)
61728 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_MASK (0x8U)
61729 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_SHIFT (3U)
61730 /*! FASTFRZ_EN - FASTFRZ_EN
61731  *  0b1..FASTFRZ signal is driven by output of subsystem
61732  *  0b0..FASTFRZ signal is gated to 0
61733  */
61734 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_MASK)
61735 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_MASK (0x10U)
61736 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_SHIFT (4U)
61737 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4 - reserved
61738  */
61739 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_MASK)
61740 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_MASK (0x1E0U)
61741 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_SHIFT (5U)
61742 /*! RASRCP - RASRCP
61743  *  0b0101..Reset Value
61744  */
61745 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_MASK)
61746 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_MASK (0x1E00U)
61747 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_SHIFT (9U)
61748 /*! RASRCN - RASRCN
61749  *  0b1010..Reset Value
61750  */
61751 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_MASK)
61752 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_MASK (0x2000U)
61753 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_SHIFT (13U)
61754 /*! SELECT_NASRC - SELECT_NASRC
61755  *  0b1..NASRCN value
61756  *  0b0..NASRCP value
61757  */
61758 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_MASK)
61759 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_MASK (0x4000U)
61760 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_SHIFT (14U)
61761 /*! COMPOK - COMPOK
61762  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
61763  *  0b1..compensation cell in Normal mode and tracking PVT
61764  */
61765 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_MASK)
61766 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_MASK (0x78000U)
61767 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_SHIFT (15U)
61768 /*! READ_NASRC - READ_NASRC
61769  *  0b0000..READ Only
61770  */
61771 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_MASK)
61772 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_MASK (0x780000U)
61773 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_SHIFT (19U)
61774 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22 - reserved
61775  */
61776 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_MASK)
61777 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_MASK (0x1800000U)
61778 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_SHIFT (23U)
61779 /*! SLEEP - SLEEP
61780  *  0b11..Force into sleep mode
61781  *  0b00..NO
61782  *  0b01..EARLY
61783  *  0b10..LATE
61784  */
61785 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_MASK)
61786 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_MASK (0x3E000000U)
61787 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_SHIFT (25U)
61788 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29 - reserved
61789  */
61790 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_MASK)
61791 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_MASK (0x40000000U)
61792 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_SHIFT (30U)
61793 /*! update_pad_ctl - update lock for pad control
61794  */
61795 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_MASK)
61796 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_MASK (0x80000000U)
61797 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_SHIFT (31U)
61798 /*! update_mux_mode - update lock for mux control
61799  */
61800 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_MASK)
61801 /*! @} */
61802 
61803 /*! @name MIPI_DSI0_I2C0_SCL - MIPI_DSI0_I2C0_SCL */
61804 /*! @{ */
61805 #define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_MASK      (0x1U)
61806 #define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_SHIFT     (0U)
61807 /*! PDRV - Drive
61808  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61809  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61810  */
61811 #define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_MASK)
61812 #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_MASK (0x1EU)
61813 #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_SHIFT (1U)
61814 /*! MIPI_DSI0_I2C0_SCL_reserved_1_4 - reserved
61815  */
61816 #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_MASK)
61817 #define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_MASK      (0x60U)
61818 #define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_SHIFT     (5U)
61819 /*! PULL - Pull Down Pull Up
61820  *  0b10..pull down
61821  *  0b01..pull up
61822  *  0b00..Prohibited
61823  *  0b11..pull disabled
61824  */
61825 #define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_MASK)
61826 #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
61827 #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_SHIFT (7U)
61828 /*! MIPI_DSI0_I2C0_SCL_reserved_7_18 - reserved
61829  */
61830 #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_MASK)
61831 #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
61832 #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
61833 /*! WAKEUP_CTRL - wakeup control
61834  *  0b000..OFF
61835  *  0b001..RESAMPLE
61836  *  0b100..LOW
61837  *  0b111..HIGH
61838  *  0b110..RISE
61839  *  0b101..FALL
61840  */
61841 #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_MASK)
61842 #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
61843 #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
61844 /*! WAKEUP_MASK - wakeup mask
61845  */
61846 #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_MASK)
61847 #define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_MASK (0x1800000U)
61848 #define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_SHIFT (23U)
61849 /*! lp_config - lower power configuration
61850  *  0b01..EARLY_ISO
61851  *  0b10..LATE_ISO
61852  *  0b11..LATCH
61853  *  0b00..PASS
61854  */
61855 #define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_MASK)
61856 #define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_MASK (0x6000000U)
61857 #define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_SHIFT (25U)
61858 /*! sw_config - output and input configuration
61859  *  0b01..OPEN_DRAIN
61860  *  0b10..OPEN_DRAIN_INPUT
61861  *  0b11..INOUT
61862  *  0b00..DEFAULT
61863  */
61864 #define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_MASK)
61865 #define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_MASK  (0x38000000U)
61866 #define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_SHIFT (27U)
61867 /*! mux_mode - mux_mode
61868  *  0b000..MIPI_DSI0.I2C0.SCL
61869  *  0b001..MIPI_DSI1.GPIO0.IO02
61870  *  0b100..LSIO.GPIO1.IO25
61871  */
61872 #define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_MASK)
61873 #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
61874 #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_SHIFT (30U)
61875 /*! update_pad_ctl - update lock for pad control
61876  */
61877 #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_MASK)
61878 #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
61879 #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_SHIFT (31U)
61880 /*! update_mux_mode - update lock for mux control
61881  */
61882 #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_MASK)
61883 /*! @} */
61884 
61885 /*! @name MIPI_DSI0_I2C0_SDA - MIPI_DSI0_I2C0_SDA */
61886 /*! @{ */
61887 #define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_MASK      (0x1U)
61888 #define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_SHIFT     (0U)
61889 /*! PDRV - Drive
61890  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61891  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61892  */
61893 #define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_MASK)
61894 #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_MASK (0x1EU)
61895 #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_SHIFT (1U)
61896 /*! MIPI_DSI0_I2C0_SDA_reserved_1_4 - reserved
61897  */
61898 #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_MASK)
61899 #define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_MASK      (0x60U)
61900 #define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_SHIFT     (5U)
61901 /*! PULL - Pull Down Pull Up
61902  *  0b10..pull down
61903  *  0b01..pull up
61904  *  0b00..Prohibited
61905  *  0b11..pull disabled
61906  */
61907 #define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_MASK)
61908 #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
61909 #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_SHIFT (7U)
61910 /*! MIPI_DSI0_I2C0_SDA_reserved_7_18 - reserved
61911  */
61912 #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_MASK)
61913 #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
61914 #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
61915 /*! WAKEUP_CTRL - wakeup control
61916  *  0b000..OFF
61917  *  0b001..RESAMPLE
61918  *  0b100..LOW
61919  *  0b111..HIGH
61920  *  0b110..RISE
61921  *  0b101..FALL
61922  */
61923 #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_MASK)
61924 #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
61925 #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
61926 /*! WAKEUP_MASK - wakeup mask
61927  */
61928 #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_MASK)
61929 #define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_MASK (0x1800000U)
61930 #define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_SHIFT (23U)
61931 /*! lp_config - lower power configuration
61932  *  0b01..EARLY_ISO
61933  *  0b10..LATE_ISO
61934  *  0b11..LATCH
61935  *  0b00..PASS
61936  */
61937 #define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_MASK)
61938 #define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_MASK (0x6000000U)
61939 #define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_SHIFT (25U)
61940 /*! sw_config - output and input configuration
61941  *  0b01..OPEN_DRAIN
61942  *  0b10..OPEN_DRAIN_INPUT
61943  *  0b11..INOUT
61944  *  0b00..DEFAULT
61945  */
61946 #define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_MASK)
61947 #define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_MASK  (0x38000000U)
61948 #define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_SHIFT (27U)
61949 /*! mux_mode - mux_mode
61950  *  0b000..MIPI_DSI0.I2C0.SDA
61951  *  0b001..MIPI_DSI1.GPIO0.IO03
61952  *  0b100..LSIO.GPIO1.IO26
61953  */
61954 #define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_MASK)
61955 #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
61956 #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_SHIFT (30U)
61957 /*! update_pad_ctl - update lock for pad control
61958  */
61959 #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_MASK)
61960 #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
61961 #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_SHIFT (31U)
61962 /*! update_mux_mode - update lock for mux control
61963  */
61964 #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_MASK)
61965 /*! @} */
61966 
61967 /*! @name MIPI_DSI0_GPIO0_00 - MIPI_DSI0_GPIO0_00 */
61968 /*! @{ */
61969 #define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_MASK      (0x1U)
61970 #define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_SHIFT     (0U)
61971 /*! PDRV - Drive
61972  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61973  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61974  */
61975 #define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_MASK)
61976 #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_MASK (0x1EU)
61977 #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_SHIFT (1U)
61978 /*! MIPI_DSI0_GPIO0_00_reserved_1_4 - reserved
61979  */
61980 #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_MASK)
61981 #define IOMUXD_MIPI_DSI0_GPIO0_00_PULL_MASK      (0x60U)
61982 #define IOMUXD_MIPI_DSI0_GPIO0_00_PULL_SHIFT     (5U)
61983 /*! PULL - Pull Down Pull Up
61984  *  0b10..pull down
61985  *  0b01..pull up
61986  *  0b00..Prohibited
61987  *  0b11..pull disabled
61988  */
61989 #define IOMUXD_MIPI_DSI0_GPIO0_00_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_PULL_MASK)
61990 #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
61991 #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_SHIFT (7U)
61992 /*! MIPI_DSI0_GPIO0_00_reserved_7_18 - reserved
61993  */
61994 #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_MASK)
61995 #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
61996 #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
61997 /*! WAKEUP_CTRL - wakeup control
61998  *  0b000..OFF
61999  *  0b001..RESAMPLE
62000  *  0b100..LOW
62001  *  0b111..HIGH
62002  *  0b110..RISE
62003  *  0b101..FALL
62004  */
62005 #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_MASK)
62006 #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
62007 #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
62008 /*! WAKEUP_MASK - wakeup mask
62009  */
62010 #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_MASK)
62011 #define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_MASK (0x1800000U)
62012 #define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_SHIFT (23U)
62013 /*! lp_config - lower power configuration
62014  *  0b01..EARLY_ISO
62015  *  0b10..LATE_ISO
62016  *  0b11..LATCH
62017  *  0b00..PASS
62018  */
62019 #define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_MASK)
62020 #define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_MASK (0x6000000U)
62021 #define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_SHIFT (25U)
62022 /*! sw_config - output and input configuration
62023  *  0b01..OPEN_DRAIN
62024  *  0b10..OPEN_DRAIN_INPUT
62025  *  0b11..INOUT
62026  *  0b00..DEFAULT
62027  */
62028 #define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_MASK)
62029 #define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_MASK  (0x38000000U)
62030 #define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_SHIFT (27U)
62031 /*! mux_mode - mux_mode
62032  *  0b000..MIPI_DSI0.GPIO0.IO00
62033  *  0b001..ADMA.I2C1.SCL
62034  *  0b010..MIPI_DSI0.PWM0.OUT
62035  *  0b100..LSIO.GPIO1.IO27
62036  */
62037 #define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_MASK)
62038 #define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
62039 #define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_SHIFT (30U)
62040 /*! update_pad_ctl - update lock for pad control
62041  */
62042 #define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_MASK)
62043 #define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_MASK (0x80000000U)
62044 #define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_SHIFT (31U)
62045 /*! update_mux_mode - update lock for mux control
62046  */
62047 #define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_MASK)
62048 /*! @} */
62049 
62050 /*! @name MIPI_DSI0_GPIO0_01 - MIPI_DSI0_GPIO0_01 */
62051 /*! @{ */
62052 #define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_MASK      (0x1U)
62053 #define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_SHIFT     (0U)
62054 /*! PDRV - Drive
62055  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62056  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62057  */
62058 #define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_MASK)
62059 #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_MASK (0x1EU)
62060 #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_SHIFT (1U)
62061 /*! MIPI_DSI0_GPIO0_01_reserved_1_4 - reserved
62062  */
62063 #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_MASK)
62064 #define IOMUXD_MIPI_DSI0_GPIO0_01_PULL_MASK      (0x60U)
62065 #define IOMUXD_MIPI_DSI0_GPIO0_01_PULL_SHIFT     (5U)
62066 /*! PULL - Pull Down Pull Up
62067  *  0b10..pull down
62068  *  0b01..pull up
62069  *  0b00..Prohibited
62070  *  0b11..pull disabled
62071  */
62072 #define IOMUXD_MIPI_DSI0_GPIO0_01_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_PULL_MASK)
62073 #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
62074 #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_SHIFT (7U)
62075 /*! MIPI_DSI0_GPIO0_01_reserved_7_18 - reserved
62076  */
62077 #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_MASK)
62078 #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
62079 #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
62080 /*! WAKEUP_CTRL - wakeup control
62081  *  0b000..OFF
62082  *  0b001..RESAMPLE
62083  *  0b100..LOW
62084  *  0b111..HIGH
62085  *  0b110..RISE
62086  *  0b101..FALL
62087  */
62088 #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_MASK)
62089 #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
62090 #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
62091 /*! WAKEUP_MASK - wakeup mask
62092  */
62093 #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_MASK)
62094 #define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_MASK (0x1800000U)
62095 #define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_SHIFT (23U)
62096 /*! lp_config - lower power configuration
62097  *  0b01..EARLY_ISO
62098  *  0b10..LATE_ISO
62099  *  0b11..LATCH
62100  *  0b00..PASS
62101  */
62102 #define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_MASK)
62103 #define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_MASK (0x6000000U)
62104 #define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_SHIFT (25U)
62105 /*! sw_config - output and input configuration
62106  *  0b01..OPEN_DRAIN
62107  *  0b10..OPEN_DRAIN_INPUT
62108  *  0b11..INOUT
62109  *  0b00..DEFAULT
62110  */
62111 #define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_MASK)
62112 #define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_MASK  (0x38000000U)
62113 #define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_SHIFT (27U)
62114 /*! mux_mode - mux_mode
62115  *  0b000..MIPI_DSI0.GPIO0.IO01
62116  *  0b001..ADMA.I2C1.SDA
62117  *  0b100..LSIO.GPIO1.IO28
62118  */
62119 #define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_MASK)
62120 #define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
62121 #define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_SHIFT (30U)
62122 /*! update_pad_ctl - update lock for pad control
62123  */
62124 #define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_MASK)
62125 #define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_MASK (0x80000000U)
62126 #define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_SHIFT (31U)
62127 /*! update_mux_mode - update lock for mux control
62128  */
62129 #define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_MASK)
62130 /*! @} */
62131 
62132 /*! @name MIPI_DSI1_I2C0_SCL - MIPI_DSI1_I2C0_SCL */
62133 /*! @{ */
62134 #define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_MASK      (0x1U)
62135 #define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_SHIFT     (0U)
62136 /*! PDRV - Drive
62137  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62138  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62139  */
62140 #define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_MASK)
62141 #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_MASK (0x1EU)
62142 #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_SHIFT (1U)
62143 /*! MIPI_DSI1_I2C0_SCL_reserved_1_4 - reserved
62144  */
62145 #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_MASK)
62146 #define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_MASK      (0x60U)
62147 #define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_SHIFT     (5U)
62148 /*! PULL - Pull Down Pull Up
62149  *  0b10..pull down
62150  *  0b01..pull up
62151  *  0b00..Prohibited
62152  *  0b11..pull disabled
62153  */
62154 #define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_MASK)
62155 #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
62156 #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_SHIFT (7U)
62157 /*! MIPI_DSI1_I2C0_SCL_reserved_7_18 - reserved
62158  */
62159 #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_MASK)
62160 #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
62161 #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
62162 /*! WAKEUP_CTRL - wakeup control
62163  *  0b000..OFF
62164  *  0b001..RESAMPLE
62165  *  0b100..LOW
62166  *  0b111..HIGH
62167  *  0b110..RISE
62168  *  0b101..FALL
62169  */
62170 #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_MASK)
62171 #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
62172 #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
62173 /*! WAKEUP_MASK - wakeup mask
62174  */
62175 #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_MASK)
62176 #define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_MASK (0x1800000U)
62177 #define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_SHIFT (23U)
62178 /*! lp_config - lower power configuration
62179  *  0b01..EARLY_ISO
62180  *  0b10..LATE_ISO
62181  *  0b11..LATCH
62182  *  0b00..PASS
62183  */
62184 #define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_MASK)
62185 #define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_MASK (0x6000000U)
62186 #define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_SHIFT (25U)
62187 /*! sw_config - output and input configuration
62188  *  0b01..OPEN_DRAIN
62189  *  0b10..OPEN_DRAIN_INPUT
62190  *  0b11..INOUT
62191  *  0b00..DEFAULT
62192  */
62193 #define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_MASK)
62194 #define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_MASK  (0x38000000U)
62195 #define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_SHIFT (27U)
62196 /*! mux_mode - mux_mode
62197  *  0b000..MIPI_DSI1.I2C0.SCL
62198  *  0b001..MIPI_DSI0.GPIO0.IO02
62199  *  0b100..LSIO.GPIO1.IO29
62200  */
62201 #define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_MASK)
62202 #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
62203 #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_SHIFT (30U)
62204 /*! update_pad_ctl - update lock for pad control
62205  */
62206 #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_MASK)
62207 #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
62208 #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_SHIFT (31U)
62209 /*! update_mux_mode - update lock for mux control
62210  */
62211 #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_MASK)
62212 /*! @} */
62213 
62214 /*! @name MIPI_DSI1_I2C0_SDA - MIPI_DSI1_I2C0_SDA */
62215 /*! @{ */
62216 #define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_MASK      (0x1U)
62217 #define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_SHIFT     (0U)
62218 /*! PDRV - Drive
62219  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62220  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62221  */
62222 #define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_MASK)
62223 #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_MASK (0x1EU)
62224 #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_SHIFT (1U)
62225 /*! MIPI_DSI1_I2C0_SDA_reserved_1_4 - reserved
62226  */
62227 #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_MASK)
62228 #define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_MASK      (0x60U)
62229 #define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_SHIFT     (5U)
62230 /*! PULL - Pull Down Pull Up
62231  *  0b10..pull down
62232  *  0b01..pull up
62233  *  0b00..Prohibited
62234  *  0b11..pull disabled
62235  */
62236 #define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_MASK)
62237 #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
62238 #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_SHIFT (7U)
62239 /*! MIPI_DSI1_I2C0_SDA_reserved_7_18 - reserved
62240  */
62241 #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_MASK)
62242 #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
62243 #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
62244 /*! WAKEUP_CTRL - wakeup control
62245  *  0b000..OFF
62246  *  0b001..RESAMPLE
62247  *  0b100..LOW
62248  *  0b111..HIGH
62249  *  0b110..RISE
62250  *  0b101..FALL
62251  */
62252 #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_MASK)
62253 #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
62254 #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
62255 /*! WAKEUP_MASK - wakeup mask
62256  */
62257 #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_MASK)
62258 #define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_MASK (0x1800000U)
62259 #define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_SHIFT (23U)
62260 /*! lp_config - lower power configuration
62261  *  0b01..EARLY_ISO
62262  *  0b10..LATE_ISO
62263  *  0b11..LATCH
62264  *  0b00..PASS
62265  */
62266 #define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_MASK)
62267 #define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_MASK (0x6000000U)
62268 #define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_SHIFT (25U)
62269 /*! sw_config - output and input configuration
62270  *  0b01..OPEN_DRAIN
62271  *  0b10..OPEN_DRAIN_INPUT
62272  *  0b11..INOUT
62273  *  0b00..DEFAULT
62274  */
62275 #define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_MASK)
62276 #define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_MASK  (0x38000000U)
62277 #define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_SHIFT (27U)
62278 /*! mux_mode - mux_mode
62279  *  0b000..MIPI_DSI1.I2C0.SDA
62280  *  0b001..MIPI_DSI0.GPIO0.IO03
62281  *  0b100..LSIO.GPIO1.IO30
62282  */
62283 #define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_MASK)
62284 #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
62285 #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_SHIFT (30U)
62286 /*! update_pad_ctl - update lock for pad control
62287  */
62288 #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_MASK)
62289 #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
62290 #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_SHIFT (31U)
62291 /*! update_mux_mode - update lock for mux control
62292  */
62293 #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_MASK)
62294 /*! @} */
62295 
62296 /*! @name MIPI_DSI1_GPIO0_00 - MIPI_DSI1_GPIO0_00 */
62297 /*! @{ */
62298 #define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_MASK      (0x1U)
62299 #define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_SHIFT     (0U)
62300 /*! PDRV - Drive
62301  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62302  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62303  */
62304 #define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_MASK)
62305 #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_MASK (0x1EU)
62306 #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_SHIFT (1U)
62307 /*! MIPI_DSI1_GPIO0_00_reserved_1_4 - reserved
62308  */
62309 #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_MASK)
62310 #define IOMUXD_MIPI_DSI1_GPIO0_00_PULL_MASK      (0x60U)
62311 #define IOMUXD_MIPI_DSI1_GPIO0_00_PULL_SHIFT     (5U)
62312 /*! PULL - Pull Down Pull Up
62313  *  0b10..pull down
62314  *  0b01..pull up
62315  *  0b00..Prohibited
62316  *  0b11..pull disabled
62317  */
62318 #define IOMUXD_MIPI_DSI1_GPIO0_00_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_PULL_MASK)
62319 #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
62320 #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_SHIFT (7U)
62321 /*! MIPI_DSI1_GPIO0_00_reserved_7_18 - reserved
62322  */
62323 #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_MASK)
62324 #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
62325 #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
62326 /*! WAKEUP_CTRL - wakeup control
62327  *  0b000..OFF
62328  *  0b001..RESAMPLE
62329  *  0b100..LOW
62330  *  0b111..HIGH
62331  *  0b110..RISE
62332  *  0b101..FALL
62333  */
62334 #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_MASK)
62335 #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
62336 #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
62337 /*! WAKEUP_MASK - wakeup mask
62338  */
62339 #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_MASK)
62340 #define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_MASK (0x1800000U)
62341 #define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_SHIFT (23U)
62342 /*! lp_config - lower power configuration
62343  *  0b01..EARLY_ISO
62344  *  0b10..LATE_ISO
62345  *  0b11..LATCH
62346  *  0b00..PASS
62347  */
62348 #define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_MASK)
62349 #define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_MASK (0x6000000U)
62350 #define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_SHIFT (25U)
62351 /*! sw_config - output and input configuration
62352  *  0b01..OPEN_DRAIN
62353  *  0b10..OPEN_DRAIN_INPUT
62354  *  0b11..INOUT
62355  *  0b00..DEFAULT
62356  */
62357 #define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_MASK)
62358 #define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_MASK  (0x38000000U)
62359 #define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_SHIFT (27U)
62360 /*! mux_mode - mux_mode
62361  *  0b000..MIPI_DSI1.GPIO0.IO00
62362  *  0b001..ADMA.I2C2.SCL
62363  *  0b010..MIPI_DSI1.PWM0.OUT
62364  *  0b100..LSIO.GPIO1.IO31
62365  */
62366 #define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_MASK)
62367 #define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
62368 #define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_SHIFT (30U)
62369 /*! update_pad_ctl - update lock for pad control
62370  */
62371 #define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_MASK)
62372 #define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_MASK (0x80000000U)
62373 #define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_SHIFT (31U)
62374 /*! update_mux_mode - update lock for mux control
62375  */
62376 #define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_MASK)
62377 /*! @} */
62378 
62379 /*! @name MIPI_DSI1_GPIO0_01 - MIPI_DSI1_GPIO0_01 */
62380 /*! @{ */
62381 #define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_MASK      (0x1U)
62382 #define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_SHIFT     (0U)
62383 /*! PDRV - Drive
62384  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62385  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62386  */
62387 #define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_MASK)
62388 #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_MASK (0x1EU)
62389 #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_SHIFT (1U)
62390 /*! MIPI_DSI1_GPIO0_01_reserved_1_4 - reserved
62391  */
62392 #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_MASK)
62393 #define IOMUXD_MIPI_DSI1_GPIO0_01_PULL_MASK      (0x60U)
62394 #define IOMUXD_MIPI_DSI1_GPIO0_01_PULL_SHIFT     (5U)
62395 /*! PULL - Pull Down Pull Up
62396  *  0b10..pull down
62397  *  0b01..pull up
62398  *  0b00..Prohibited
62399  *  0b11..pull disabled
62400  */
62401 #define IOMUXD_MIPI_DSI1_GPIO0_01_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_PULL_MASK)
62402 #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
62403 #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_SHIFT (7U)
62404 /*! MIPI_DSI1_GPIO0_01_reserved_7_18 - reserved
62405  */
62406 #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_MASK)
62407 #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
62408 #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
62409 /*! WAKEUP_CTRL - wakeup control
62410  *  0b000..OFF
62411  *  0b001..RESAMPLE
62412  *  0b100..LOW
62413  *  0b111..HIGH
62414  *  0b110..RISE
62415  *  0b101..FALL
62416  */
62417 #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_MASK)
62418 #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
62419 #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
62420 /*! WAKEUP_MASK - wakeup mask
62421  */
62422 #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_MASK)
62423 #define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_MASK (0x1800000U)
62424 #define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_SHIFT (23U)
62425 /*! lp_config - lower power configuration
62426  *  0b01..EARLY_ISO
62427  *  0b10..LATE_ISO
62428  *  0b11..LATCH
62429  *  0b00..PASS
62430  */
62431 #define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_MASK)
62432 #define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_MASK (0x6000000U)
62433 #define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_SHIFT (25U)
62434 /*! sw_config - output and input configuration
62435  *  0b01..OPEN_DRAIN
62436  *  0b10..OPEN_DRAIN_INPUT
62437  *  0b11..INOUT
62438  *  0b00..DEFAULT
62439  */
62440 #define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_MASK)
62441 #define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_MASK  (0x38000000U)
62442 #define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_SHIFT (27U)
62443 /*! mux_mode - mux_mode
62444  *  0b000..MIPI_DSI1.GPIO0.IO01
62445  *  0b001..ADMA.I2C2.SDA
62446  *  0b100..LSIO.GPIO2.IO00
62447  */
62448 #define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_MASK)
62449 #define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
62450 #define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_SHIFT (30U)
62451 /*! update_pad_ctl - update lock for pad control
62452  */
62453 #define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_MASK)
62454 #define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_MASK (0x80000000U)
62455 #define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_SHIFT (31U)
62456 /*! update_mux_mode - update lock for mux control
62457  */
62458 #define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_MASK)
62459 /*! @} */
62460 
62461 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO - IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO */
62462 /*! @{ */
62463 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_MASK (0x7U)
62464 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_SHIFT (0U)
62465 /*! COMP - COMP
62466  *  0b010..Fixed code mode
62467  *  0b100..High impedance mode
62468  *  0b110..Read mode
62469  *  0b000..Normal Mode
62470  *  0b001..Freeze Mode
62471  */
62472 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_MASK)
62473 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_MASK (0x8U)
62474 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_SHIFT (3U)
62475 /*! FASTFRZ_EN - FASTFRZ_EN
62476  *  0b1..FASTFRZ signal is driven by output of subsystem
62477  *  0b0..FASTFRZ signal is gated to 0
62478  */
62479 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_MASK)
62480 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_MASK (0x10U)
62481 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_SHIFT (4U)
62482 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4 - reserved
62483  */
62484 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_MASK)
62485 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_MASK (0x1E0U)
62486 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_SHIFT (5U)
62487 /*! RASRCP - RASRCP
62488  *  0b0101..Reset Value
62489  */
62490 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_MASK)
62491 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_MASK (0x1E00U)
62492 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_SHIFT (9U)
62493 /*! RASRCN - RASRCN
62494  *  0b1010..Reset Value
62495  */
62496 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_MASK)
62497 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_MASK (0x2000U)
62498 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_SHIFT (13U)
62499 /*! SELECT_NASRC - SELECT_NASRC
62500  *  0b1..NASRCN value
62501  *  0b0..NASRCP value
62502  */
62503 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_MASK)
62504 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_MASK (0x4000U)
62505 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_SHIFT (14U)
62506 /*! COMPOK - COMPOK
62507  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
62508  *  0b1..compensation cell in Normal mode and tracking PVT
62509  */
62510 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_MASK)
62511 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_MASK (0x78000U)
62512 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_SHIFT (15U)
62513 /*! READ_NASRC - READ_NASRC
62514  *  0b0000..READ Only
62515  */
62516 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_MASK)
62517 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_MASK (0x780000U)
62518 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_SHIFT (19U)
62519 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22 - reserved
62520  */
62521 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_MASK)
62522 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_MASK (0x1800000U)
62523 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_SHIFT (23U)
62524 /*! SLEEP - SLEEP
62525  *  0b11..Force into sleep mode
62526  *  0b00..NO
62527  *  0b01..EARLY
62528  *  0b10..LATE
62529  */
62530 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_MASK)
62531 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_MASK (0x3E000000U)
62532 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_SHIFT (25U)
62533 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29 - reserved
62534  */
62535 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_MASK)
62536 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_MASK (0x40000000U)
62537 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_SHIFT (30U)
62538 /*! update_pad_ctl - update lock for pad control
62539  */
62540 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_MASK)
62541 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_MASK (0x80000000U)
62542 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_SHIFT (31U)
62543 /*! update_mux_mode - update lock for mux control
62544  */
62545 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_MASK)
62546 /*! @} */
62547 
62548 /*! @name SCU_WDOG_OUT - SCU_WDOG_OUT */
62549 /*! @{ */
62550 #define IOMUXD_SCU_WDOG_OUT_DSE_MASK             (0x7U)
62551 #define IOMUXD_SCU_WDOG_OUT_DSE_SHIFT            (0U)
62552 /*! DSE - Drive
62553  *  0b001..Drive select 2mA
62554  *  0b011..Drive select 6mA
62555  *  0b111..High Speed
62556  *  0b110..Drive select 12mA
62557  *  0b010..Drive select 4mA
62558  *  0b100..Drive select 8mA
62559  *  0b000..Drive select 1mA
62560  *  0b101..Drive select 10mA
62561  */
62562 #define IOMUXD_SCU_WDOG_OUT_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_DSE_SHIFT)) & IOMUXD_SCU_WDOG_OUT_DSE_MASK)
62563 #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_MASK (0x18U)
62564 #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_SHIFT (3U)
62565 /*! SCU_WDOG_OUT_reserved_3_4 - reserved
62566  */
62567 #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_SHIFT)) & IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_MASK)
62568 #define IOMUXD_SCU_WDOG_OUT_PULL_MASK            (0x60U)
62569 #define IOMUXD_SCU_WDOG_OUT_PULL_SHIFT           (5U)
62570 /*! PULL - Pull Down Pull Up
62571  *  0b00..Bus-Keeper
62572  *  0b10..pull down
62573  *  0b01..pull up
62574  *  0b11..No Pull
62575  */
62576 #define IOMUXD_SCU_WDOG_OUT_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_PULL_SHIFT)) & IOMUXD_SCU_WDOG_OUT_PULL_MASK)
62577 #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_MASK (0x7FF80U)
62578 #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_SHIFT (7U)
62579 /*! SCU_WDOG_OUT_reserved_7_18 - reserved
62580  */
62581 #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_SHIFT)) & IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_MASK)
62582 #define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_MASK     (0x380000U)
62583 #define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_SHIFT    (19U)
62584 /*! WAKEUP_CTRL - wakeup control
62585  *  0b000..OFF
62586  *  0b001..RESAMPLE
62587  *  0b100..LOW
62588  *  0b111..HIGH
62589  *  0b110..RISE
62590  *  0b101..FALL
62591  */
62592 #define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_MASK)
62593 #define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_MASK     (0x400000U)
62594 #define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_SHIFT    (22U)
62595 /*! WAKEUP_MASK - wakeup mask
62596  */
62597 #define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_MASK)
62598 #define IOMUXD_SCU_WDOG_OUT_lp_config_MASK       (0x1800000U)
62599 #define IOMUXD_SCU_WDOG_OUT_lp_config_SHIFT      (23U)
62600 /*! lp_config - lower power configuration
62601  *  0b01..EARLY_ISO
62602  *  0b10..LATE_ISO
62603  *  0b11..LATCH
62604  *  0b00..PASS
62605  */
62606 #define IOMUXD_SCU_WDOG_OUT_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_lp_config_SHIFT)) & IOMUXD_SCU_WDOG_OUT_lp_config_MASK)
62607 #define IOMUXD_SCU_WDOG_OUT_sw_config_MASK       (0x6000000U)
62608 #define IOMUXD_SCU_WDOG_OUT_sw_config_SHIFT      (25U)
62609 /*! sw_config - output and input configuration
62610  *  0b01..OPEN_DRAIN
62611  *  0b10..OPEN_DRAIN_INPUT
62612  *  0b11..INOUT
62613  *  0b00..DEFAULT
62614  */
62615 #define IOMUXD_SCU_WDOG_OUT_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_sw_config_SHIFT)) & IOMUXD_SCU_WDOG_OUT_sw_config_MASK)
62616 #define IOMUXD_SCU_WDOG_OUT_mux_mode_MASK        (0x38000000U)
62617 #define IOMUXD_SCU_WDOG_OUT_mux_mode_SHIFT       (27U)
62618 /*! mux_mode - mux_mode
62619  *  0b001..SCU.WDOG0.WDOG_OUT
62620  */
62621 #define IOMUXD_SCU_WDOG_OUT_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_mux_mode_SHIFT)) & IOMUXD_SCU_WDOG_OUT_mux_mode_MASK)
62622 #define IOMUXD_SCU_WDOG_OUT_update_pad_ctl_MASK  (0x40000000U)
62623 #define IOMUXD_SCU_WDOG_OUT_update_pad_ctl_SHIFT (30U)
62624 /*! update_pad_ctl - update lock for pad control
62625  */
62626 #define IOMUXD_SCU_WDOG_OUT_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_update_pad_ctl_SHIFT)) & IOMUXD_SCU_WDOG_OUT_update_pad_ctl_MASK)
62627 #define IOMUXD_SCU_WDOG_OUT_update_mux_mode_MASK (0x80000000U)
62628 #define IOMUXD_SCU_WDOG_OUT_update_mux_mode_SHIFT (31U)
62629 /*! update_mux_mode - update lock for mux control
62630  */
62631 #define IOMUXD_SCU_WDOG_OUT_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_update_mux_mode_SHIFT)) & IOMUXD_SCU_WDOG_OUT_update_mux_mode_MASK)
62632 /*! @} */
62633 
62634 /*! @name PMIC_I2C_SCL - PMIC_I2C_SCL */
62635 /*! @{ */
62636 #define IOMUXD_PMIC_I2C_SCL_DSE_MASK             (0x7U)
62637 #define IOMUXD_PMIC_I2C_SCL_DSE_SHIFT            (0U)
62638 /*! DSE - Drive
62639  *  0b001..Drive select 2mA
62640  *  0b011..Drive select 6mA
62641  *  0b111..High Speed
62642  *  0b110..Drive select 12mA
62643  *  0b010..Drive select 4mA
62644  *  0b100..Drive select 8mA
62645  *  0b000..Drive select 1mA
62646  *  0b101..Drive select 10mA
62647  */
62648 #define IOMUXD_PMIC_I2C_SCL_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_DSE_SHIFT)) & IOMUXD_PMIC_I2C_SCL_DSE_MASK)
62649 #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_MASK (0x18U)
62650 #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_SHIFT (3U)
62651 /*! PMIC_I2C_SCL_reserved_3_4 - reserved
62652  */
62653 #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_MASK)
62654 #define IOMUXD_PMIC_I2C_SCL_PULL_MASK            (0x60U)
62655 #define IOMUXD_PMIC_I2C_SCL_PULL_SHIFT           (5U)
62656 /*! PULL - Pull Down Pull Up
62657  *  0b00..Bus-Keeper
62658  *  0b10..pull down
62659  *  0b01..pull up
62660  *  0b11..No Pull
62661  */
62662 #define IOMUXD_PMIC_I2C_SCL_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PULL_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PULL_MASK)
62663 #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_MASK (0x7FF80U)
62664 #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_SHIFT (7U)
62665 /*! PMIC_I2C_SCL_reserved_7_18 - reserved
62666  */
62667 #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_MASK)
62668 #define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_MASK     (0x380000U)
62669 #define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_SHIFT    (19U)
62670 /*! WAKEUP_CTRL - wakeup control
62671  *  0b000..OFF
62672  *  0b001..RESAMPLE
62673  *  0b100..LOW
62674  *  0b111..HIGH
62675  *  0b110..RISE
62676  *  0b101..FALL
62677  */
62678 #define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_MASK)
62679 #define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_MASK     (0x400000U)
62680 #define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_SHIFT    (22U)
62681 /*! WAKEUP_MASK - wakeup mask
62682  */
62683 #define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_MASK)
62684 #define IOMUXD_PMIC_I2C_SCL_lp_config_MASK       (0x1800000U)
62685 #define IOMUXD_PMIC_I2C_SCL_lp_config_SHIFT      (23U)
62686 /*! lp_config - lower power configuration
62687  *  0b01..EARLY_ISO
62688  *  0b10..LATE_ISO
62689  *  0b11..LATCH
62690  *  0b00..PASS
62691  */
62692 #define IOMUXD_PMIC_I2C_SCL_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_lp_config_SHIFT)) & IOMUXD_PMIC_I2C_SCL_lp_config_MASK)
62693 #define IOMUXD_PMIC_I2C_SCL_sw_config_MASK       (0x6000000U)
62694 #define IOMUXD_PMIC_I2C_SCL_sw_config_SHIFT      (25U)
62695 /*! sw_config - output and input configuration
62696  *  0b01..OPEN_DRAIN
62697  *  0b10..OPEN_DRAIN_INPUT
62698  *  0b11..INOUT
62699  *  0b00..DEFAULT
62700  */
62701 #define IOMUXD_PMIC_I2C_SCL_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_sw_config_SHIFT)) & IOMUXD_PMIC_I2C_SCL_sw_config_MASK)
62702 #define IOMUXD_PMIC_I2C_SCL_mux_mode_MASK        (0x38000000U)
62703 #define IOMUXD_PMIC_I2C_SCL_mux_mode_SHIFT       (27U)
62704 /*! mux_mode - mux_mode
62705  *  0b000..SCU.PMIC_I2C.SCL
62706  *  0b001..SCU.GPIO0.IOXX_PMIC_A35_ON
62707  *  0b100..LSIO.GPIO2.IO01
62708  */
62709 #define IOMUXD_PMIC_I2C_SCL_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SCL_mux_mode_MASK)
62710 #define IOMUXD_PMIC_I2C_SCL_update_pad_ctl_MASK  (0x40000000U)
62711 #define IOMUXD_PMIC_I2C_SCL_update_pad_ctl_SHIFT (30U)
62712 /*! update_pad_ctl - update lock for pad control
62713  */
62714 #define IOMUXD_PMIC_I2C_SCL_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_I2C_SCL_update_pad_ctl_MASK)
62715 #define IOMUXD_PMIC_I2C_SCL_update_mux_mode_MASK (0x80000000U)
62716 #define IOMUXD_PMIC_I2C_SCL_update_mux_mode_SHIFT (31U)
62717 /*! update_mux_mode - update lock for mux control
62718  */
62719 #define IOMUXD_PMIC_I2C_SCL_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_update_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SCL_update_mux_mode_MASK)
62720 /*! @} */
62721 
62722 /*! @name IOMUXD_GROUP_2_2 - na */
62723 /*! @{ */
62724 #define IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_MASK    (0x1U)
62725 #define IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_SHIFT   (0U)
62726 /*! UART0_TX - wakeup from UART0_TX
62727  */
62728 #define IOMUXD_IOMUXD_GROUP_2_2_UART0_TX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_MASK)
62729 #define IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_MASK    (0x2U)
62730 #define IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_SHIFT   (1U)
62731 /*! UART2_TX - wakeup from UART2_TX
62732  */
62733 #define IOMUXD_IOMUXD_GROUP_2_2_UART2_TX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_MASK)
62734 #define IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_MASK    (0x4U)
62735 #define IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_SHIFT   (2U)
62736 /*! UART2_RX - wakeup from UART2_RX
62737  */
62738 #define IOMUXD_IOMUXD_GROUP_2_2_UART2_RX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_MASK)
62739 #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_MASK (0x8U)
62740 #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_SHIFT (3U)
62741 /*! iomuxd_group_2_2_reserved_3_3 - reserved
62742  */
62743 #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_MASK)
62744 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_MASK (0x10U)
62745 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_SHIFT (4U)
62746 /*! MIPI_DSI0_I2C0_SCL - wakeup from MIPI_DSI0_I2C0_SCL
62747  */
62748 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_MASK)
62749 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_MASK (0x20U)
62750 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_SHIFT (5U)
62751 /*! MIPI_DSI0_I2C0_SDA - wakeup from MIPI_DSI0_I2C0_SDA
62752  */
62753 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_MASK)
62754 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_MASK (0x40U)
62755 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_SHIFT (6U)
62756 /*! MIPI_DSI0_GPIO0_00 - wakeup from MIPI_DSI0_GPIO0_00
62757  */
62758 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_MASK)
62759 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_MASK (0x80U)
62760 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_SHIFT (7U)
62761 /*! MIPI_DSI0_GPIO0_01 - wakeup from MIPI_DSI0_GPIO0_01
62762  */
62763 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_MASK)
62764 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_MASK (0x100U)
62765 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_SHIFT (8U)
62766 /*! MIPI_DSI1_I2C0_SCL - wakeup from MIPI_DSI1_I2C0_SCL
62767  */
62768 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_MASK)
62769 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_MASK (0x200U)
62770 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_SHIFT (9U)
62771 /*! MIPI_DSI1_I2C0_SDA - wakeup from MIPI_DSI1_I2C0_SDA
62772  */
62773 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_MASK)
62774 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_MASK (0x400U)
62775 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_SHIFT (10U)
62776 /*! MIPI_DSI1_GPIO0_00 - wakeup from MIPI_DSI1_GPIO0_00
62777  */
62778 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_MASK)
62779 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_MASK (0x800U)
62780 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_SHIFT (11U)
62781 /*! MIPI_DSI1_GPIO0_01 - wakeup from MIPI_DSI1_GPIO0_01
62782  */
62783 #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_MASK)
62784 #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_MASK (0x1000U)
62785 #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_SHIFT (12U)
62786 /*! iomuxd_group_2_2_reserved_12_12 - reserved
62787  */
62788 #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_MASK)
62789 #define IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_MASK (0x2000U)
62790 #define IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_SHIFT (13U)
62791 /*! SCU_WDOG_OUT - wakeup from SCU_WDOG_OUT
62792  */
62793 #define IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_MASK)
62794 #define IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_MASK (0x4000U)
62795 #define IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_SHIFT (14U)
62796 /*! PMIC_I2C_SCL - wakeup from PMIC_I2C_SCL
62797  */
62798 #define IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_MASK)
62799 #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_MASK (0xFFFF8000U)
62800 #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_SHIFT (15U)
62801 /*! iomuxd_group_2_2_reserved_15_31 - reserved
62802  */
62803 #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_MASK)
62804 /*! @} */
62805 
62806 /*! @name PMIC_I2C_SDA - PMIC_I2C_SDA */
62807 /*! @{ */
62808 #define IOMUXD_PMIC_I2C_SDA_DSE_MASK             (0x7U)
62809 #define IOMUXD_PMIC_I2C_SDA_DSE_SHIFT            (0U)
62810 /*! DSE - Drive
62811  *  0b001..Drive select 2mA
62812  *  0b011..Drive select 6mA
62813  *  0b111..High Speed
62814  *  0b110..Drive select 12mA
62815  *  0b010..Drive select 4mA
62816  *  0b100..Drive select 8mA
62817  *  0b000..Drive select 1mA
62818  *  0b101..Drive select 10mA
62819  */
62820 #define IOMUXD_PMIC_I2C_SDA_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_DSE_SHIFT)) & IOMUXD_PMIC_I2C_SDA_DSE_MASK)
62821 #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_MASK (0x18U)
62822 #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_SHIFT (3U)
62823 /*! PMIC_I2C_SDA_reserved_3_4 - reserved
62824  */
62825 #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_MASK)
62826 #define IOMUXD_PMIC_I2C_SDA_PULL_MASK            (0x60U)
62827 #define IOMUXD_PMIC_I2C_SDA_PULL_SHIFT           (5U)
62828 /*! PULL - Pull Down Pull Up
62829  *  0b00..Bus-Keeper
62830  *  0b10..pull down
62831  *  0b01..pull up
62832  *  0b11..No Pull
62833  */
62834 #define IOMUXD_PMIC_I2C_SDA_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PULL_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PULL_MASK)
62835 #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_MASK (0x7FF80U)
62836 #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_SHIFT (7U)
62837 /*! PMIC_I2C_SDA_reserved_7_18 - reserved
62838  */
62839 #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_MASK)
62840 #define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_MASK     (0x380000U)
62841 #define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_SHIFT    (19U)
62842 /*! WAKEUP_CTRL - wakeup control
62843  *  0b000..OFF
62844  *  0b001..RESAMPLE
62845  *  0b100..LOW
62846  *  0b111..HIGH
62847  *  0b110..RISE
62848  *  0b101..FALL
62849  */
62850 #define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_MASK)
62851 #define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_MASK     (0x400000U)
62852 #define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_SHIFT    (22U)
62853 /*! WAKEUP_MASK - wakeup mask
62854  */
62855 #define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_MASK)
62856 #define IOMUXD_PMIC_I2C_SDA_lp_config_MASK       (0x1800000U)
62857 #define IOMUXD_PMIC_I2C_SDA_lp_config_SHIFT      (23U)
62858 /*! lp_config - lower power configuration
62859  *  0b01..EARLY_ISO
62860  *  0b10..LATE_ISO
62861  *  0b11..LATCH
62862  *  0b00..PASS
62863  */
62864 #define IOMUXD_PMIC_I2C_SDA_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_lp_config_SHIFT)) & IOMUXD_PMIC_I2C_SDA_lp_config_MASK)
62865 #define IOMUXD_PMIC_I2C_SDA_sw_config_MASK       (0x6000000U)
62866 #define IOMUXD_PMIC_I2C_SDA_sw_config_SHIFT      (25U)
62867 /*! sw_config - output and input configuration
62868  *  0b01..OPEN_DRAIN
62869  *  0b10..OPEN_DRAIN_INPUT
62870  *  0b11..INOUT
62871  *  0b00..DEFAULT
62872  */
62873 #define IOMUXD_PMIC_I2C_SDA_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_sw_config_SHIFT)) & IOMUXD_PMIC_I2C_SDA_sw_config_MASK)
62874 #define IOMUXD_PMIC_I2C_SDA_mux_mode_MASK        (0x38000000U)
62875 #define IOMUXD_PMIC_I2C_SDA_mux_mode_SHIFT       (27U)
62876 /*! mux_mode - mux_mode
62877  *  0b000..SCU.PMIC_I2C.SDA
62878  *  0b001..SCU.GPIO0.IOXX_PMIC_GPU_ON
62879  *  0b100..LSIO.GPIO2.IO02
62880  */
62881 #define IOMUXD_PMIC_I2C_SDA_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SDA_mux_mode_MASK)
62882 #define IOMUXD_PMIC_I2C_SDA_update_pad_ctl_MASK  (0x40000000U)
62883 #define IOMUXD_PMIC_I2C_SDA_update_pad_ctl_SHIFT (30U)
62884 /*! update_pad_ctl - update lock for pad control
62885  */
62886 #define IOMUXD_PMIC_I2C_SDA_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_I2C_SDA_update_pad_ctl_MASK)
62887 #define IOMUXD_PMIC_I2C_SDA_update_mux_mode_MASK (0x80000000U)
62888 #define IOMUXD_PMIC_I2C_SDA_update_mux_mode_SHIFT (31U)
62889 /*! update_mux_mode - update lock for mux control
62890  */
62891 #define IOMUXD_PMIC_I2C_SDA_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_update_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SDA_update_mux_mode_MASK)
62892 /*! @} */
62893 
62894 /*! @name PMIC_INT_B - PMIC_INT_B */
62895 /*! @{ */
62896 #define IOMUXD_PMIC_INT_B_DSE_MASK               (0x7U)
62897 #define IOMUXD_PMIC_INT_B_DSE_SHIFT              (0U)
62898 /*! DSE - Drive
62899  *  0b001..Drive select 2mA
62900  *  0b011..Drive select 6mA
62901  *  0b111..High Speed
62902  *  0b110..Drive select 12mA
62903  *  0b010..Drive select 4mA
62904  *  0b100..Drive select 8mA
62905  *  0b000..Drive select 1mA
62906  *  0b101..Drive select 10mA
62907  */
62908 #define IOMUXD_PMIC_INT_B_DSE(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_DSE_SHIFT)) & IOMUXD_PMIC_INT_B_DSE_MASK)
62909 #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_MASK (0x18U)
62910 #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_SHIFT (3U)
62911 /*! PMIC_INT_B_reserved_3_4 - reserved
62912  */
62913 #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_SHIFT)) & IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_MASK)
62914 #define IOMUXD_PMIC_INT_B_PULL_MASK              (0x60U)
62915 #define IOMUXD_PMIC_INT_B_PULL_SHIFT             (5U)
62916 /*! PULL - Pull Down Pull Up
62917  *  0b00..Bus-Keeper
62918  *  0b10..pull down
62919  *  0b01..pull up
62920  *  0b11..No Pull
62921  */
62922 #define IOMUXD_PMIC_INT_B_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PULL_SHIFT)) & IOMUXD_PMIC_INT_B_PULL_MASK)
62923 #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_MASK (0x7FF80U)
62924 #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_SHIFT (7U)
62925 /*! PMIC_INT_B_reserved_7_18 - reserved
62926  */
62927 #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_SHIFT)) & IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_MASK)
62928 #define IOMUXD_PMIC_INT_B_WAKEUP_CTRL_MASK       (0x380000U)
62929 #define IOMUXD_PMIC_INT_B_WAKEUP_CTRL_SHIFT      (19U)
62930 /*! WAKEUP_CTRL - wakeup control
62931  *  0b000..OFF
62932  *  0b001..RESAMPLE
62933  *  0b100..LOW
62934  *  0b111..HIGH
62935  *  0b110..RISE
62936  *  0b101..FALL
62937  */
62938 #define IOMUXD_PMIC_INT_B_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_INT_B_WAKEUP_CTRL_MASK)
62939 #define IOMUXD_PMIC_INT_B_WAKEUP_MASK_MASK       (0x400000U)
62940 #define IOMUXD_PMIC_INT_B_WAKEUP_MASK_SHIFT      (22U)
62941 /*! WAKEUP_MASK - wakeup mask
62942  */
62943 #define IOMUXD_PMIC_INT_B_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_INT_B_WAKEUP_MASK_MASK)
62944 #define IOMUXD_PMIC_INT_B_lp_config_MASK         (0x1800000U)
62945 #define IOMUXD_PMIC_INT_B_lp_config_SHIFT        (23U)
62946 /*! lp_config - lower power configuration
62947  *  0b01..EARLY_ISO
62948  *  0b10..LATE_ISO
62949  *  0b11..LATCH
62950  *  0b00..PASS
62951  */
62952 #define IOMUXD_PMIC_INT_B_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_lp_config_SHIFT)) & IOMUXD_PMIC_INT_B_lp_config_MASK)
62953 #define IOMUXD_PMIC_INT_B_sw_config_MASK         (0x6000000U)
62954 #define IOMUXD_PMIC_INT_B_sw_config_SHIFT        (25U)
62955 /*! sw_config - output and input configuration
62956  *  0b01..OPEN_DRAIN
62957  *  0b10..OPEN_DRAIN_INPUT
62958  *  0b11..INOUT
62959  *  0b00..DEFAULT
62960  */
62961 #define IOMUXD_PMIC_INT_B_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_sw_config_SHIFT)) & IOMUXD_PMIC_INT_B_sw_config_MASK)
62962 #define IOMUXD_PMIC_INT_B_mux_mode_MASK          (0x38000000U)
62963 #define IOMUXD_PMIC_INT_B_mux_mode_SHIFT         (27U)
62964 /*! mux_mode - mux_mode
62965  *  0b000..SCU.DSC.PMIC_INT_B
62966  */
62967 #define IOMUXD_PMIC_INT_B_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_mux_mode_SHIFT)) & IOMUXD_PMIC_INT_B_mux_mode_MASK)
62968 #define IOMUXD_PMIC_INT_B_update_pad_ctl_MASK    (0x40000000U)
62969 #define IOMUXD_PMIC_INT_B_update_pad_ctl_SHIFT   (30U)
62970 /*! update_pad_ctl - update lock for pad control
62971  */
62972 #define IOMUXD_PMIC_INT_B_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_INT_B_update_pad_ctl_MASK)
62973 #define IOMUXD_PMIC_INT_B_update_mux_mode_MASK   (0x80000000U)
62974 #define IOMUXD_PMIC_INT_B_update_mux_mode_SHIFT  (31U)
62975 /*! update_mux_mode - update lock for mux control
62976  */
62977 #define IOMUXD_PMIC_INT_B_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_update_mux_mode_SHIFT)) & IOMUXD_PMIC_INT_B_update_mux_mode_MASK)
62978 /*! @} */
62979 
62980 /*! @name SCU_GPIO0_00 - SCU_GPIO0_00 */
62981 /*! @{ */
62982 #define IOMUXD_SCU_GPIO0_00_DSE_MASK             (0x7U)
62983 #define IOMUXD_SCU_GPIO0_00_DSE_SHIFT            (0U)
62984 /*! DSE - Drive
62985  *  0b001..Drive select 2mA
62986  *  0b011..Drive select 6mA
62987  *  0b111..High Speed
62988  *  0b110..Drive select 12mA
62989  *  0b010..Drive select 4mA
62990  *  0b100..Drive select 8mA
62991  *  0b000..Drive select 1mA
62992  *  0b101..Drive select 10mA
62993  */
62994 #define IOMUXD_SCU_GPIO0_00_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_00_DSE_MASK)
62995 #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_MASK (0x18U)
62996 #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_SHIFT (3U)
62997 /*! SCU_GPIO0_00_reserved_3_4 - reserved
62998  */
62999 #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_MASK)
63000 #define IOMUXD_SCU_GPIO0_00_PULL_MASK            (0x60U)
63001 #define IOMUXD_SCU_GPIO0_00_PULL_SHIFT           (5U)
63002 /*! PULL - Pull Down Pull Up
63003  *  0b00..Bus-Keeper
63004  *  0b10..pull down
63005  *  0b01..pull up
63006  *  0b11..No Pull
63007  */
63008 #define IOMUXD_SCU_GPIO0_00_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_00_PULL_MASK)
63009 #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
63010 #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_SHIFT (7U)
63011 /*! SCU_GPIO0_00_reserved_7_18 - reserved
63012  */
63013 #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_MASK)
63014 #define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_MASK     (0x380000U)
63015 #define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_SHIFT    (19U)
63016 /*! WAKEUP_CTRL - wakeup control
63017  *  0b000..OFF
63018  *  0b001..RESAMPLE
63019  *  0b100..LOW
63020  *  0b111..HIGH
63021  *  0b110..RISE
63022  *  0b101..FALL
63023  */
63024 #define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_MASK)
63025 #define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_MASK     (0x400000U)
63026 #define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_SHIFT    (22U)
63027 /*! WAKEUP_MASK - wakeup mask
63028  */
63029 #define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_MASK)
63030 #define IOMUXD_SCU_GPIO0_00_lp_config_MASK       (0x1800000U)
63031 #define IOMUXD_SCU_GPIO0_00_lp_config_SHIFT      (23U)
63032 /*! lp_config - lower power configuration
63033  *  0b01..EARLY_ISO
63034  *  0b10..LATE_ISO
63035  *  0b11..LATCH
63036  *  0b00..PASS
63037  */
63038 #define IOMUXD_SCU_GPIO0_00_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_00_lp_config_MASK)
63039 #define IOMUXD_SCU_GPIO0_00_sw_config_MASK       (0x6000000U)
63040 #define IOMUXD_SCU_GPIO0_00_sw_config_SHIFT      (25U)
63041 /*! sw_config - output and input configuration
63042  *  0b01..OPEN_DRAIN
63043  *  0b10..OPEN_DRAIN_INPUT
63044  *  0b11..INOUT
63045  *  0b00..DEFAULT
63046  */
63047 #define IOMUXD_SCU_GPIO0_00_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_00_sw_config_MASK)
63048 #define IOMUXD_SCU_GPIO0_00_mux_mode_MASK        (0x38000000U)
63049 #define IOMUXD_SCU_GPIO0_00_mux_mode_SHIFT       (27U)
63050 /*! mux_mode - mux_mode
63051  *  0b000..SCU.GPIO0.IO00
63052  *  0b001..SCU.UART0.RX
63053  *  0b010..M40.UART0.RX
63054  *  0b011..ADMA.UART3.RX
63055  *  0b100..LSIO.GPIO2.IO03
63056  */
63057 #define IOMUXD_SCU_GPIO0_00_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_00_mux_mode_MASK)
63058 #define IOMUXD_SCU_GPIO0_00_update_pad_ctl_MASK  (0x40000000U)
63059 #define IOMUXD_SCU_GPIO0_00_update_pad_ctl_SHIFT (30U)
63060 /*! update_pad_ctl - update lock for pad control
63061  */
63062 #define IOMUXD_SCU_GPIO0_00_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_00_update_pad_ctl_MASK)
63063 #define IOMUXD_SCU_GPIO0_00_update_mux_mode_MASK (0x80000000U)
63064 #define IOMUXD_SCU_GPIO0_00_update_mux_mode_SHIFT (31U)
63065 /*! update_mux_mode - update lock for mux control
63066  */
63067 #define IOMUXD_SCU_GPIO0_00_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_00_update_mux_mode_MASK)
63068 /*! @} */
63069 
63070 /*! @name SCU_GPIO0_01 - SCU_GPIO0_01 */
63071 /*! @{ */
63072 #define IOMUXD_SCU_GPIO0_01_DSE_MASK             (0x7U)
63073 #define IOMUXD_SCU_GPIO0_01_DSE_SHIFT            (0U)
63074 /*! DSE - Drive
63075  *  0b001..Drive select 2mA
63076  *  0b011..Drive select 6mA
63077  *  0b111..High Speed
63078  *  0b110..Drive select 12mA
63079  *  0b010..Drive select 4mA
63080  *  0b100..Drive select 8mA
63081  *  0b000..Drive select 1mA
63082  *  0b101..Drive select 10mA
63083  */
63084 #define IOMUXD_SCU_GPIO0_01_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_01_DSE_MASK)
63085 #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_MASK (0x18U)
63086 #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_SHIFT (3U)
63087 /*! SCU_GPIO0_01_reserved_3_4 - reserved
63088  */
63089 #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_MASK)
63090 #define IOMUXD_SCU_GPIO0_01_PULL_MASK            (0x60U)
63091 #define IOMUXD_SCU_GPIO0_01_PULL_SHIFT           (5U)
63092 /*! PULL - Pull Down Pull Up
63093  *  0b00..Bus-Keeper
63094  *  0b10..pull down
63095  *  0b01..pull up
63096  *  0b11..No Pull
63097  */
63098 #define IOMUXD_SCU_GPIO0_01_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_01_PULL_MASK)
63099 #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
63100 #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_SHIFT (7U)
63101 /*! SCU_GPIO0_01_reserved_7_18 - reserved
63102  */
63103 #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_MASK)
63104 #define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_MASK     (0x380000U)
63105 #define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_SHIFT    (19U)
63106 /*! WAKEUP_CTRL - wakeup control
63107  *  0b000..OFF
63108  *  0b001..RESAMPLE
63109  *  0b100..LOW
63110  *  0b111..HIGH
63111  *  0b110..RISE
63112  *  0b101..FALL
63113  */
63114 #define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_MASK)
63115 #define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_MASK     (0x400000U)
63116 #define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_SHIFT    (22U)
63117 /*! WAKEUP_MASK - wakeup mask
63118  */
63119 #define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_MASK)
63120 #define IOMUXD_SCU_GPIO0_01_lp_config_MASK       (0x1800000U)
63121 #define IOMUXD_SCU_GPIO0_01_lp_config_SHIFT      (23U)
63122 /*! lp_config - lower power configuration
63123  *  0b01..EARLY_ISO
63124  *  0b10..LATE_ISO
63125  *  0b11..LATCH
63126  *  0b00..PASS
63127  */
63128 #define IOMUXD_SCU_GPIO0_01_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_01_lp_config_MASK)
63129 #define IOMUXD_SCU_GPIO0_01_sw_config_MASK       (0x6000000U)
63130 #define IOMUXD_SCU_GPIO0_01_sw_config_SHIFT      (25U)
63131 /*! sw_config - output and input configuration
63132  *  0b01..OPEN_DRAIN
63133  *  0b10..OPEN_DRAIN_INPUT
63134  *  0b11..INOUT
63135  *  0b00..DEFAULT
63136  */
63137 #define IOMUXD_SCU_GPIO0_01_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_01_sw_config_MASK)
63138 #define IOMUXD_SCU_GPIO0_01_mux_mode_MASK        (0x38000000U)
63139 #define IOMUXD_SCU_GPIO0_01_mux_mode_SHIFT       (27U)
63140 /*! mux_mode - mux_mode
63141  *  0b000..SCU.GPIO0.IO01
63142  *  0b001..SCU.UART0.TX
63143  *  0b010..M40.UART0.TX
63144  *  0b011..ADMA.UART3.TX
63145  *  0b100..SCU.WDOG0.WDOG_OUT
63146  */
63147 #define IOMUXD_SCU_GPIO0_01_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_01_mux_mode_MASK)
63148 #define IOMUXD_SCU_GPIO0_01_update_pad_ctl_MASK  (0x40000000U)
63149 #define IOMUXD_SCU_GPIO0_01_update_pad_ctl_SHIFT (30U)
63150 /*! update_pad_ctl - update lock for pad control
63151  */
63152 #define IOMUXD_SCU_GPIO0_01_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_01_update_pad_ctl_MASK)
63153 #define IOMUXD_SCU_GPIO0_01_update_mux_mode_MASK (0x80000000U)
63154 #define IOMUXD_SCU_GPIO0_01_update_mux_mode_SHIFT (31U)
63155 /*! update_mux_mode - update lock for mux control
63156  */
63157 #define IOMUXD_SCU_GPIO0_01_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_01_update_mux_mode_MASK)
63158 /*! @} */
63159 
63160 /*! @name SCU_PMIC_STANDBY - SCU_PMIC_STANDBY */
63161 /*! @{ */
63162 #define IOMUXD_SCU_PMIC_STANDBY_DSE_MASK         (0x7U)
63163 #define IOMUXD_SCU_PMIC_STANDBY_DSE_SHIFT        (0U)
63164 /*! DSE - Drive
63165  *  0b001..Drive select 2mA
63166  *  0b011..Drive select 6mA
63167  *  0b111..High Speed
63168  *  0b110..Drive select 12mA
63169  *  0b010..Drive select 4mA
63170  *  0b100..Drive select 8mA
63171  *  0b000..Drive select 1mA
63172  *  0b101..Drive select 10mA
63173  */
63174 #define IOMUXD_SCU_PMIC_STANDBY_DSE(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_DSE_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_DSE_MASK)
63175 #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_MASK (0x18U)
63176 #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_SHIFT (3U)
63177 /*! SCU_PMIC_STANDBY_reserved_3_4 - reserved
63178  */
63179 #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_MASK)
63180 #define IOMUXD_SCU_PMIC_STANDBY_PULL_MASK        (0x60U)
63181 #define IOMUXD_SCU_PMIC_STANDBY_PULL_SHIFT       (5U)
63182 /*! PULL - Pull Down Pull Up
63183  *  0b00..Bus-Keeper
63184  *  0b10..pull down
63185  *  0b01..pull up
63186  *  0b11..No Pull
63187  */
63188 #define IOMUXD_SCU_PMIC_STANDBY_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_PULL_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_PULL_MASK)
63189 #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_MASK (0x7FF80U)
63190 #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_SHIFT (7U)
63191 /*! SCU_PMIC_STANDBY_reserved_7_18 - reserved
63192  */
63193 #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_MASK)
63194 #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_MASK (0x380000U)
63195 #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_SHIFT (19U)
63196 /*! WAKEUP_CTRL - wakeup control
63197  *  0b000..OFF
63198  *  0b001..RESAMPLE
63199  *  0b100..LOW
63200  *  0b111..HIGH
63201  *  0b110..RISE
63202  *  0b101..FALL
63203  */
63204 #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_MASK)
63205 #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_MASK (0x400000U)
63206 #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_SHIFT (22U)
63207 /*! WAKEUP_MASK - wakeup mask
63208  */
63209 #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_MASK)
63210 #define IOMUXD_SCU_PMIC_STANDBY_lp_config_MASK   (0x1800000U)
63211 #define IOMUXD_SCU_PMIC_STANDBY_lp_config_SHIFT  (23U)
63212 /*! lp_config - lower power configuration
63213  *  0b01..EARLY_ISO
63214  *  0b10..LATE_ISO
63215  *  0b11..LATCH
63216  *  0b00..PASS
63217  */
63218 #define IOMUXD_SCU_PMIC_STANDBY_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_lp_config_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_lp_config_MASK)
63219 #define IOMUXD_SCU_PMIC_STANDBY_sw_config_MASK   (0x6000000U)
63220 #define IOMUXD_SCU_PMIC_STANDBY_sw_config_SHIFT  (25U)
63221 /*! sw_config - output and input configuration
63222  *  0b01..OPEN_DRAIN
63223  *  0b10..OPEN_DRAIN_INPUT
63224  *  0b11..INOUT
63225  *  0b00..DEFAULT
63226  */
63227 #define IOMUXD_SCU_PMIC_STANDBY_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_sw_config_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_sw_config_MASK)
63228 #define IOMUXD_SCU_PMIC_STANDBY_mux_mode_MASK    (0x38000000U)
63229 #define IOMUXD_SCU_PMIC_STANDBY_mux_mode_SHIFT   (27U)
63230 /*! mux_mode - mux_mode
63231  *  0b000..SCU.DSC.PMIC_STANDBY
63232  */
63233 #define IOMUXD_SCU_PMIC_STANDBY_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_mux_mode_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_mux_mode_MASK)
63234 #define IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_MASK (0x40000000U)
63235 #define IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_SHIFT (30U)
63236 /*! update_pad_ctl - update lock for pad control
63237  */
63238 #define IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_MASK)
63239 #define IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_MASK (0x80000000U)
63240 #define IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_SHIFT (31U)
63241 /*! update_mux_mode - update lock for mux control
63242  */
63243 #define IOMUXD_SCU_PMIC_STANDBY_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_MASK)
63244 /*! @} */
63245 
63246 /*! @name SCU_BOOT_MODE0 - SCU_BOOT_MODE0 */
63247 /*! @{ */
63248 #define IOMUXD_SCU_BOOT_MODE0_DSE_MASK           (0x7U)
63249 #define IOMUXD_SCU_BOOT_MODE0_DSE_SHIFT          (0U)
63250 /*! DSE - Drive
63251  *  0b001..Drive select 2mA
63252  *  0b011..Drive select 6mA
63253  *  0b111..High Speed
63254  *  0b110..Drive select 12mA
63255  *  0b010..Drive select 4mA
63256  *  0b100..Drive select 8mA
63257  *  0b000..Drive select 1mA
63258  *  0b101..Drive select 10mA
63259  */
63260 #define IOMUXD_SCU_BOOT_MODE0_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_DSE_MASK)
63261 #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_MASK (0x18U)
63262 #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_SHIFT (3U)
63263 /*! SCU_BOOT_MODE0_reserved_3_4 - reserved
63264  */
63265 #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_MASK)
63266 #define IOMUXD_SCU_BOOT_MODE0_PULL_MASK          (0x60U)
63267 #define IOMUXD_SCU_BOOT_MODE0_PULL_SHIFT         (5U)
63268 /*! PULL - Pull Down Pull Up
63269  *  0b00..Bus-Keeper
63270  *  0b10..pull down
63271  *  0b01..pull up
63272  *  0b11..No Pull
63273  */
63274 #define IOMUXD_SCU_BOOT_MODE0_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_PULL_MASK)
63275 #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_MASK (0x7FF80U)
63276 #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_SHIFT (7U)
63277 /*! SCU_BOOT_MODE0_reserved_7_18 - reserved
63278  */
63279 #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_MASK)
63280 #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_MASK   (0x380000U)
63281 #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_SHIFT  (19U)
63282 /*! WAKEUP_CTRL - wakeup control
63283  *  0b000..OFF
63284  *  0b001..RESAMPLE
63285  *  0b100..LOW
63286  *  0b111..HIGH
63287  *  0b110..RISE
63288  *  0b101..FALL
63289  */
63290 #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_MASK)
63291 #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_MASK   (0x400000U)
63292 #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_SHIFT  (22U)
63293 /*! WAKEUP_MASK - wakeup mask
63294  */
63295 #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_MASK)
63296 #define IOMUXD_SCU_BOOT_MODE0_lp_config_MASK     (0x1800000U)
63297 #define IOMUXD_SCU_BOOT_MODE0_lp_config_SHIFT    (23U)
63298 /*! lp_config - lower power configuration
63299  *  0b01..EARLY_ISO
63300  *  0b10..LATE_ISO
63301  *  0b11..LATCH
63302  *  0b00..PASS
63303  */
63304 #define IOMUXD_SCU_BOOT_MODE0_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_lp_config_MASK)
63305 #define IOMUXD_SCU_BOOT_MODE0_sw_config_MASK     (0x6000000U)
63306 #define IOMUXD_SCU_BOOT_MODE0_sw_config_SHIFT    (25U)
63307 /*! sw_config - output and input configuration
63308  *  0b01..OPEN_DRAIN
63309  *  0b10..OPEN_DRAIN_INPUT
63310  *  0b11..INOUT
63311  *  0b00..DEFAULT
63312  */
63313 #define IOMUXD_SCU_BOOT_MODE0_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_sw_config_MASK)
63314 #define IOMUXD_SCU_BOOT_MODE0_mux_mode_MASK      (0x38000000U)
63315 #define IOMUXD_SCU_BOOT_MODE0_mux_mode_SHIFT     (27U)
63316 /*! mux_mode - mux_mode
63317  *  0b000..SCU.DSC.BOOT_MODE0
63318  */
63319 #define IOMUXD_SCU_BOOT_MODE0_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_mux_mode_MASK)
63320 #define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_MASK (0x40000000U)
63321 #define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_SHIFT (30U)
63322 /*! update_pad_ctl - update lock for pad control
63323  */
63324 #define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_MASK)
63325 #define IOMUXD_SCU_BOOT_MODE0_update_mux_mode_MASK (0x80000000U)
63326 #define IOMUXD_SCU_BOOT_MODE0_update_mux_mode_SHIFT (31U)
63327 /*! update_mux_mode - update lock for mux control
63328  */
63329 #define IOMUXD_SCU_BOOT_MODE0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_update_mux_mode_MASK)
63330 /*! @} */
63331 
63332 /*! @name SCU_BOOT_MODE1 - SCU_BOOT_MODE1 */
63333 /*! @{ */
63334 #define IOMUXD_SCU_BOOT_MODE1_DSE_MASK           (0x7U)
63335 #define IOMUXD_SCU_BOOT_MODE1_DSE_SHIFT          (0U)
63336 /*! DSE - Drive
63337  *  0b001..Drive select 2mA
63338  *  0b011..Drive select 6mA
63339  *  0b111..High Speed
63340  *  0b110..Drive select 12mA
63341  *  0b010..Drive select 4mA
63342  *  0b100..Drive select 8mA
63343  *  0b000..Drive select 1mA
63344  *  0b101..Drive select 10mA
63345  */
63346 #define IOMUXD_SCU_BOOT_MODE1_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_DSE_MASK)
63347 #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_MASK (0x18U)
63348 #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_SHIFT (3U)
63349 /*! SCU_BOOT_MODE1_reserved_3_4 - reserved
63350  */
63351 #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_MASK)
63352 #define IOMUXD_SCU_BOOT_MODE1_PULL_MASK          (0x60U)
63353 #define IOMUXD_SCU_BOOT_MODE1_PULL_SHIFT         (5U)
63354 /*! PULL - Pull Down Pull Up
63355  *  0b00..Bus-Keeper
63356  *  0b10..pull down
63357  *  0b01..pull up
63358  *  0b11..No Pull
63359  */
63360 #define IOMUXD_SCU_BOOT_MODE1_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_PULL_MASK)
63361 #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_MASK (0x7FF80U)
63362 #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_SHIFT (7U)
63363 /*! SCU_BOOT_MODE1_reserved_7_18 - reserved
63364  */
63365 #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_MASK)
63366 #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_MASK   (0x380000U)
63367 #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_SHIFT  (19U)
63368 /*! WAKEUP_CTRL - wakeup control
63369  *  0b000..OFF
63370  *  0b001..RESAMPLE
63371  *  0b100..LOW
63372  *  0b111..HIGH
63373  *  0b110..RISE
63374  *  0b101..FALL
63375  */
63376 #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_MASK)
63377 #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_MASK   (0x400000U)
63378 #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_SHIFT  (22U)
63379 /*! WAKEUP_MASK - wakeup mask
63380  */
63381 #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_MASK)
63382 #define IOMUXD_SCU_BOOT_MODE1_lp_config_MASK     (0x1800000U)
63383 #define IOMUXD_SCU_BOOT_MODE1_lp_config_SHIFT    (23U)
63384 /*! lp_config - lower power configuration
63385  *  0b01..EARLY_ISO
63386  *  0b10..LATE_ISO
63387  *  0b11..LATCH
63388  *  0b00..PASS
63389  */
63390 #define IOMUXD_SCU_BOOT_MODE1_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_lp_config_MASK)
63391 #define IOMUXD_SCU_BOOT_MODE1_sw_config_MASK     (0x6000000U)
63392 #define IOMUXD_SCU_BOOT_MODE1_sw_config_SHIFT    (25U)
63393 /*! sw_config - output and input configuration
63394  *  0b01..OPEN_DRAIN
63395  *  0b10..OPEN_DRAIN_INPUT
63396  *  0b11..INOUT
63397  *  0b00..DEFAULT
63398  */
63399 #define IOMUXD_SCU_BOOT_MODE1_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_sw_config_MASK)
63400 #define IOMUXD_SCU_BOOT_MODE1_mux_mode_MASK      (0x38000000U)
63401 #define IOMUXD_SCU_BOOT_MODE1_mux_mode_SHIFT     (27U)
63402 /*! mux_mode - mux_mode
63403  *  0b000..SCU.DSC.BOOT_MODE1
63404  */
63405 #define IOMUXD_SCU_BOOT_MODE1_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_mux_mode_MASK)
63406 #define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_MASK (0x40000000U)
63407 #define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_SHIFT (30U)
63408 /*! update_pad_ctl - update lock for pad control
63409  */
63410 #define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_MASK)
63411 #define IOMUXD_SCU_BOOT_MODE1_update_mux_mode_MASK (0x80000000U)
63412 #define IOMUXD_SCU_BOOT_MODE1_update_mux_mode_SHIFT (31U)
63413 /*! update_mux_mode - update lock for mux control
63414  */
63415 #define IOMUXD_SCU_BOOT_MODE1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_update_mux_mode_MASK)
63416 /*! @} */
63417 
63418 /*! @name SCU_BOOT_MODE2 - SCU_BOOT_MODE2 */
63419 /*! @{ */
63420 #define IOMUXD_SCU_BOOT_MODE2_DSE_MASK           (0x7U)
63421 #define IOMUXD_SCU_BOOT_MODE2_DSE_SHIFT          (0U)
63422 /*! DSE - Drive
63423  *  0b001..Drive select 2mA
63424  *  0b011..Drive select 6mA
63425  *  0b111..High Speed
63426  *  0b110..Drive select 12mA
63427  *  0b010..Drive select 4mA
63428  *  0b100..Drive select 8mA
63429  *  0b000..Drive select 1mA
63430  *  0b101..Drive select 10mA
63431  */
63432 #define IOMUXD_SCU_BOOT_MODE2_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_DSE_MASK)
63433 #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_MASK (0x18U)
63434 #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_SHIFT (3U)
63435 /*! SCU_BOOT_MODE2_reserved_3_4 - reserved
63436  */
63437 #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_MASK)
63438 #define IOMUXD_SCU_BOOT_MODE2_PULL_MASK          (0x60U)
63439 #define IOMUXD_SCU_BOOT_MODE2_PULL_SHIFT         (5U)
63440 /*! PULL - Pull Down Pull Up
63441  *  0b00..Bus-Keeper
63442  *  0b10..pull down
63443  *  0b01..pull up
63444  *  0b11..No Pull
63445  */
63446 #define IOMUXD_SCU_BOOT_MODE2_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_PULL_MASK)
63447 #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_MASK (0x7FF80U)
63448 #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_SHIFT (7U)
63449 /*! SCU_BOOT_MODE2_reserved_7_18 - reserved
63450  */
63451 #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_MASK)
63452 #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_MASK   (0x380000U)
63453 #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_SHIFT  (19U)
63454 /*! WAKEUP_CTRL - wakeup control
63455  *  0b000..OFF
63456  *  0b001..RESAMPLE
63457  *  0b100..LOW
63458  *  0b111..HIGH
63459  *  0b110..RISE
63460  *  0b101..FALL
63461  */
63462 #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_MASK)
63463 #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_MASK   (0x400000U)
63464 #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_SHIFT  (22U)
63465 /*! WAKEUP_MASK - wakeup mask
63466  */
63467 #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_MASK)
63468 #define IOMUXD_SCU_BOOT_MODE2_lp_config_MASK     (0x1800000U)
63469 #define IOMUXD_SCU_BOOT_MODE2_lp_config_SHIFT    (23U)
63470 /*! lp_config - lower power configuration
63471  *  0b01..EARLY_ISO
63472  *  0b10..LATE_ISO
63473  *  0b11..LATCH
63474  *  0b00..PASS
63475  */
63476 #define IOMUXD_SCU_BOOT_MODE2_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_lp_config_MASK)
63477 #define IOMUXD_SCU_BOOT_MODE2_sw_config_MASK     (0x6000000U)
63478 #define IOMUXD_SCU_BOOT_MODE2_sw_config_SHIFT    (25U)
63479 /*! sw_config - output and input configuration
63480  *  0b01..OPEN_DRAIN
63481  *  0b10..OPEN_DRAIN_INPUT
63482  *  0b11..INOUT
63483  *  0b00..DEFAULT
63484  */
63485 #define IOMUXD_SCU_BOOT_MODE2_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_sw_config_MASK)
63486 #define IOMUXD_SCU_BOOT_MODE2_mux_mode_MASK      (0x38000000U)
63487 #define IOMUXD_SCU_BOOT_MODE2_mux_mode_SHIFT     (27U)
63488 /*! mux_mode - mux_mode
63489  *  0b000..SCU.DSC.BOOT_MODE2
63490  *  0b001..SCU.PMIC_I2C.SDA
63491  */
63492 #define IOMUXD_SCU_BOOT_MODE2_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_mux_mode_MASK)
63493 #define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_MASK (0x40000000U)
63494 #define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_SHIFT (30U)
63495 /*! update_pad_ctl - update lock for pad control
63496  */
63497 #define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_MASK)
63498 #define IOMUXD_SCU_BOOT_MODE2_update_mux_mode_MASK (0x80000000U)
63499 #define IOMUXD_SCU_BOOT_MODE2_update_mux_mode_SHIFT (31U)
63500 /*! update_mux_mode - update lock for mux control
63501  */
63502 #define IOMUXD_SCU_BOOT_MODE2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_update_mux_mode_MASK)
63503 /*! @} */
63504 
63505 /*! @name SCU_BOOT_MODE3 - SCU_BOOT_MODE3 */
63506 /*! @{ */
63507 #define IOMUXD_SCU_BOOT_MODE3_DSE_MASK           (0x7U)
63508 #define IOMUXD_SCU_BOOT_MODE3_DSE_SHIFT          (0U)
63509 /*! DSE - Drive
63510  *  0b001..Drive select 2mA
63511  *  0b011..Drive select 6mA
63512  *  0b111..High Speed
63513  *  0b110..Drive select 12mA
63514  *  0b010..Drive select 4mA
63515  *  0b100..Drive select 8mA
63516  *  0b000..Drive select 1mA
63517  *  0b101..Drive select 10mA
63518  */
63519 #define IOMUXD_SCU_BOOT_MODE3_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_DSE_MASK)
63520 #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_MASK (0x18U)
63521 #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_SHIFT (3U)
63522 /*! SCU_BOOT_MODE3_reserved_3_4 - reserved
63523  */
63524 #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_MASK)
63525 #define IOMUXD_SCU_BOOT_MODE3_PULL_MASK          (0x60U)
63526 #define IOMUXD_SCU_BOOT_MODE3_PULL_SHIFT         (5U)
63527 /*! PULL - Pull Down Pull Up
63528  *  0b00..Bus-Keeper
63529  *  0b10..pull down
63530  *  0b01..pull up
63531  *  0b11..No Pull
63532  */
63533 #define IOMUXD_SCU_BOOT_MODE3_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_PULL_MASK)
63534 #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_MASK (0x7FF80U)
63535 #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_SHIFT (7U)
63536 /*! SCU_BOOT_MODE3_reserved_7_18 - reserved
63537  */
63538 #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_MASK)
63539 #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_MASK   (0x380000U)
63540 #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_SHIFT  (19U)
63541 /*! WAKEUP_CTRL - wakeup control
63542  *  0b000..OFF
63543  *  0b001..RESAMPLE
63544  *  0b100..LOW
63545  *  0b111..HIGH
63546  *  0b110..RISE
63547  *  0b101..FALL
63548  */
63549 #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_MASK)
63550 #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_MASK   (0x400000U)
63551 #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_SHIFT  (22U)
63552 /*! WAKEUP_MASK - wakeup mask
63553  */
63554 #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_MASK)
63555 #define IOMUXD_SCU_BOOT_MODE3_lp_config_MASK     (0x1800000U)
63556 #define IOMUXD_SCU_BOOT_MODE3_lp_config_SHIFT    (23U)
63557 /*! lp_config - lower power configuration
63558  *  0b01..EARLY_ISO
63559  *  0b10..LATE_ISO
63560  *  0b11..LATCH
63561  *  0b00..PASS
63562  */
63563 #define IOMUXD_SCU_BOOT_MODE3_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_lp_config_MASK)
63564 #define IOMUXD_SCU_BOOT_MODE3_sw_config_MASK     (0x6000000U)
63565 #define IOMUXD_SCU_BOOT_MODE3_sw_config_SHIFT    (25U)
63566 /*! sw_config - output and input configuration
63567  *  0b01..OPEN_DRAIN
63568  *  0b10..OPEN_DRAIN_INPUT
63569  *  0b11..INOUT
63570  *  0b00..DEFAULT
63571  */
63572 #define IOMUXD_SCU_BOOT_MODE3_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_sw_config_MASK)
63573 #define IOMUXD_SCU_BOOT_MODE3_mux_mode_MASK      (0x38000000U)
63574 #define IOMUXD_SCU_BOOT_MODE3_mux_mode_SHIFT     (27U)
63575 /*! mux_mode - mux_mode
63576  *  0b000..SCU.DSC.BOOT_MODE3
63577  *  0b001..SCU.PMIC_I2C.SCL
63578  *  0b011..SCU.DSC.RTC_CLOCK_OUTPUT_32K
63579  */
63580 #define IOMUXD_SCU_BOOT_MODE3_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_mux_mode_MASK)
63581 #define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_MASK (0x40000000U)
63582 #define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_SHIFT (30U)
63583 /*! update_pad_ctl - update lock for pad control
63584  */
63585 #define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_MASK)
63586 #define IOMUXD_SCU_BOOT_MODE3_update_mux_mode_MASK (0x80000000U)
63587 #define IOMUXD_SCU_BOOT_MODE3_update_mux_mode_SHIFT (31U)
63588 /*! update_mux_mode - update lock for mux control
63589  */
63590 #define IOMUXD_SCU_BOOT_MODE3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_update_mux_mode_MASK)
63591 /*! @} */
63592 
63593 /*! @name CSI_DIG_D00 - CSI_DIG_D00 */
63594 /*! @{ */
63595 #define IOMUXD_CSI_DIG_D00_PDRV_MASK             (0x1U)
63596 #define IOMUXD_CSI_DIG_D00_PDRV_SHIFT            (0U)
63597 /*! PDRV - Drive
63598  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
63599  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
63600  */
63601 #define IOMUXD_CSI_DIG_D00_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D00_PDRV_MASK)
63602 #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_MASK (0x1EU)
63603 #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_SHIFT (1U)
63604 /*! CSI_DIG_D00_reserved_1_4 - reserved
63605  */
63606 #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_MASK)
63607 #define IOMUXD_CSI_DIG_D00_PULL_MASK             (0x60U)
63608 #define IOMUXD_CSI_DIG_D00_PULL_SHIFT            (5U)
63609 /*! PULL - Pull Down Pull Up
63610  *  0b10..pull down
63611  *  0b01..pull up
63612  *  0b00..Prohibited
63613  *  0b11..pull disabled
63614  */
63615 #define IOMUXD_CSI_DIG_D00_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_PULL_SHIFT)) & IOMUXD_CSI_DIG_D00_PULL_MASK)
63616 #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_MASK (0x7FF80U)
63617 #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_SHIFT (7U)
63618 /*! CSI_DIG_D00_reserved_7_18 - reserved
63619  */
63620 #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_MASK)
63621 #define IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_MASK      (0x380000U)
63622 #define IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_SHIFT     (19U)
63623 /*! WAKEUP_CTRL - wakeup control
63624  *  0b000..OFF
63625  *  0b001..RESAMPLE
63626  *  0b100..LOW
63627  *  0b111..HIGH
63628  *  0b110..RISE
63629  *  0b101..FALL
63630  */
63631 #define IOMUXD_CSI_DIG_D00_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_MASK)
63632 #define IOMUXD_CSI_DIG_D00_WAKEUP_MASK_MASK      (0x400000U)
63633 #define IOMUXD_CSI_DIG_D00_WAKEUP_MASK_SHIFT     (22U)
63634 /*! WAKEUP_MASK - wakeup mask
63635  */
63636 #define IOMUXD_CSI_DIG_D00_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D00_WAKEUP_MASK_MASK)
63637 #define IOMUXD_CSI_DIG_D00_lp_config_MASK        (0x1800000U)
63638 #define IOMUXD_CSI_DIG_D00_lp_config_SHIFT       (23U)
63639 /*! lp_config - lower power configuration
63640  *  0b01..EARLY_ISO
63641  *  0b10..LATE_ISO
63642  *  0b11..LATCH
63643  *  0b00..PASS
63644  */
63645 #define IOMUXD_CSI_DIG_D00_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D00_lp_config_MASK)
63646 #define IOMUXD_CSI_DIG_D00_sw_config_MASK        (0x6000000U)
63647 #define IOMUXD_CSI_DIG_D00_sw_config_SHIFT       (25U)
63648 /*! sw_config - output and input configuration
63649  *  0b01..OPEN_DRAIN
63650  *  0b10..OPEN_DRAIN_INPUT
63651  *  0b11..INOUT
63652  *  0b00..DEFAULT
63653  */
63654 #define IOMUXD_CSI_DIG_D00_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D00_sw_config_MASK)
63655 #define IOMUXD_CSI_DIG_D00_mux_mode_MASK         (0x38000000U)
63656 #define IOMUXD_CSI_DIG_D00_mux_mode_SHIFT        (27U)
63657 /*! mux_mode - mux_mode
63658  *  0b000..CI_PI.D02
63659  *  0b010..ADMA.SAI0.RXC
63660  */
63661 #define IOMUXD_CSI_DIG_D00_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D00_mux_mode_MASK)
63662 #define IOMUXD_CSI_DIG_D00_update_pad_ctl_MASK   (0x40000000U)
63663 #define IOMUXD_CSI_DIG_D00_update_pad_ctl_SHIFT  (30U)
63664 /*! update_pad_ctl - update lock for pad control
63665  */
63666 #define IOMUXD_CSI_DIG_D00_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D00_update_pad_ctl_MASK)
63667 #define IOMUXD_CSI_DIG_D00_update_mux_mode_MASK  (0x80000000U)
63668 #define IOMUXD_CSI_DIG_D00_update_mux_mode_SHIFT (31U)
63669 /*! update_mux_mode - update lock for mux control
63670  */
63671 #define IOMUXD_CSI_DIG_D00_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D00_update_mux_mode_MASK)
63672 /*! @} */
63673 
63674 /*! @name CSI_DIG_D01 - CSI_DIG_D01 */
63675 /*! @{ */
63676 #define IOMUXD_CSI_DIG_D01_PDRV_MASK             (0x1U)
63677 #define IOMUXD_CSI_DIG_D01_PDRV_SHIFT            (0U)
63678 /*! PDRV - Drive
63679  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
63680  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
63681  */
63682 #define IOMUXD_CSI_DIG_D01_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D01_PDRV_MASK)
63683 #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_MASK (0x1EU)
63684 #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_SHIFT (1U)
63685 /*! CSI_DIG_D01_reserved_1_4 - reserved
63686  */
63687 #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_MASK)
63688 #define IOMUXD_CSI_DIG_D01_PULL_MASK             (0x60U)
63689 #define IOMUXD_CSI_DIG_D01_PULL_SHIFT            (5U)
63690 /*! PULL - Pull Down Pull Up
63691  *  0b10..pull down
63692  *  0b01..pull up
63693  *  0b00..Prohibited
63694  *  0b11..pull disabled
63695  */
63696 #define IOMUXD_CSI_DIG_D01_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_PULL_SHIFT)) & IOMUXD_CSI_DIG_D01_PULL_MASK)
63697 #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_MASK (0x7FF80U)
63698 #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_SHIFT (7U)
63699 /*! CSI_DIG_D01_reserved_7_18 - reserved
63700  */
63701 #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_MASK)
63702 #define IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_MASK      (0x380000U)
63703 #define IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_SHIFT     (19U)
63704 /*! WAKEUP_CTRL - wakeup control
63705  *  0b000..OFF
63706  *  0b001..RESAMPLE
63707  *  0b100..LOW
63708  *  0b111..HIGH
63709  *  0b110..RISE
63710  *  0b101..FALL
63711  */
63712 #define IOMUXD_CSI_DIG_D01_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_MASK)
63713 #define IOMUXD_CSI_DIG_D01_WAKEUP_MASK_MASK      (0x400000U)
63714 #define IOMUXD_CSI_DIG_D01_WAKEUP_MASK_SHIFT     (22U)
63715 /*! WAKEUP_MASK - wakeup mask
63716  */
63717 #define IOMUXD_CSI_DIG_D01_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D01_WAKEUP_MASK_MASK)
63718 #define IOMUXD_CSI_DIG_D01_lp_config_MASK        (0x1800000U)
63719 #define IOMUXD_CSI_DIG_D01_lp_config_SHIFT       (23U)
63720 /*! lp_config - lower power configuration
63721  *  0b01..EARLY_ISO
63722  *  0b10..LATE_ISO
63723  *  0b11..LATCH
63724  *  0b00..PASS
63725  */
63726 #define IOMUXD_CSI_DIG_D01_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D01_lp_config_MASK)
63727 #define IOMUXD_CSI_DIG_D01_sw_config_MASK        (0x6000000U)
63728 #define IOMUXD_CSI_DIG_D01_sw_config_SHIFT       (25U)
63729 /*! sw_config - output and input configuration
63730  *  0b01..OPEN_DRAIN
63731  *  0b10..OPEN_DRAIN_INPUT
63732  *  0b11..INOUT
63733  *  0b00..DEFAULT
63734  */
63735 #define IOMUXD_CSI_DIG_D01_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D01_sw_config_MASK)
63736 #define IOMUXD_CSI_DIG_D01_mux_mode_MASK         (0x38000000U)
63737 #define IOMUXD_CSI_DIG_D01_mux_mode_SHIFT        (27U)
63738 /*! mux_mode - mux_mode
63739  *  0b000..CI_PI.D03
63740  *  0b010..ADMA.SAI0.RXD
63741  */
63742 #define IOMUXD_CSI_DIG_D01_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D01_mux_mode_MASK)
63743 #define IOMUXD_CSI_DIG_D01_update_pad_ctl_MASK   (0x40000000U)
63744 #define IOMUXD_CSI_DIG_D01_update_pad_ctl_SHIFT  (30U)
63745 /*! update_pad_ctl - update lock for pad control
63746  */
63747 #define IOMUXD_CSI_DIG_D01_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D01_update_pad_ctl_MASK)
63748 #define IOMUXD_CSI_DIG_D01_update_mux_mode_MASK  (0x80000000U)
63749 #define IOMUXD_CSI_DIG_D01_update_mux_mode_SHIFT (31U)
63750 /*! update_mux_mode - update lock for mux control
63751  */
63752 #define IOMUXD_CSI_DIG_D01_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D01_update_mux_mode_MASK)
63753 /*! @} */
63754 
63755 /*! @name CSI_DIG_D02 - CSI_DIG_D02 */
63756 /*! @{ */
63757 #define IOMUXD_CSI_DIG_D02_PDRV_MASK             (0x1U)
63758 #define IOMUXD_CSI_DIG_D02_PDRV_SHIFT            (0U)
63759 /*! PDRV - Drive
63760  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
63761  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
63762  */
63763 #define IOMUXD_CSI_DIG_D02_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D02_PDRV_MASK)
63764 #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_MASK (0x1EU)
63765 #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_SHIFT (1U)
63766 /*! CSI_DIG_D02_reserved_1_4 - reserved
63767  */
63768 #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_MASK)
63769 #define IOMUXD_CSI_DIG_D02_PULL_MASK             (0x60U)
63770 #define IOMUXD_CSI_DIG_D02_PULL_SHIFT            (5U)
63771 /*! PULL - Pull Down Pull Up
63772  *  0b10..pull down
63773  *  0b01..pull up
63774  *  0b00..Prohibited
63775  *  0b11..pull disabled
63776  */
63777 #define IOMUXD_CSI_DIG_D02_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_PULL_SHIFT)) & IOMUXD_CSI_DIG_D02_PULL_MASK)
63778 #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_MASK (0x7FF80U)
63779 #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_SHIFT (7U)
63780 /*! CSI_DIG_D02_reserved_7_18 - reserved
63781  */
63782 #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_MASK)
63783 #define IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_MASK      (0x380000U)
63784 #define IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_SHIFT     (19U)
63785 /*! WAKEUP_CTRL - wakeup control
63786  *  0b000..OFF
63787  *  0b001..RESAMPLE
63788  *  0b100..LOW
63789  *  0b111..HIGH
63790  *  0b110..RISE
63791  *  0b101..FALL
63792  */
63793 #define IOMUXD_CSI_DIG_D02_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_MASK)
63794 #define IOMUXD_CSI_DIG_D02_WAKEUP_MASK_MASK      (0x400000U)
63795 #define IOMUXD_CSI_DIG_D02_WAKEUP_MASK_SHIFT     (22U)
63796 /*! WAKEUP_MASK - wakeup mask
63797  */
63798 #define IOMUXD_CSI_DIG_D02_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D02_WAKEUP_MASK_MASK)
63799 #define IOMUXD_CSI_DIG_D02_lp_config_MASK        (0x1800000U)
63800 #define IOMUXD_CSI_DIG_D02_lp_config_SHIFT       (23U)
63801 /*! lp_config - lower power configuration
63802  *  0b01..EARLY_ISO
63803  *  0b10..LATE_ISO
63804  *  0b11..LATCH
63805  *  0b00..PASS
63806  */
63807 #define IOMUXD_CSI_DIG_D02_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D02_lp_config_MASK)
63808 #define IOMUXD_CSI_DIG_D02_sw_config_MASK        (0x6000000U)
63809 #define IOMUXD_CSI_DIG_D02_sw_config_SHIFT       (25U)
63810 /*! sw_config - output and input configuration
63811  *  0b01..OPEN_DRAIN
63812  *  0b10..OPEN_DRAIN_INPUT
63813  *  0b11..INOUT
63814  *  0b00..DEFAULT
63815  */
63816 #define IOMUXD_CSI_DIG_D02_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D02_sw_config_MASK)
63817 #define IOMUXD_CSI_DIG_D02_mux_mode_MASK         (0x38000000U)
63818 #define IOMUXD_CSI_DIG_D02_mux_mode_SHIFT        (27U)
63819 /*! mux_mode - mux_mode
63820  *  0b000..CI_PI.D04
63821  *  0b010..ADMA.SAI0.RXFS
63822  */
63823 #define IOMUXD_CSI_DIG_D02_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D02_mux_mode_MASK)
63824 #define IOMUXD_CSI_DIG_D02_update_pad_ctl_MASK   (0x40000000U)
63825 #define IOMUXD_CSI_DIG_D02_update_pad_ctl_SHIFT  (30U)
63826 /*! update_pad_ctl - update lock for pad control
63827  */
63828 #define IOMUXD_CSI_DIG_D02_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D02_update_pad_ctl_MASK)
63829 #define IOMUXD_CSI_DIG_D02_update_mux_mode_MASK  (0x80000000U)
63830 #define IOMUXD_CSI_DIG_D02_update_mux_mode_SHIFT (31U)
63831 /*! update_mux_mode - update lock for mux control
63832  */
63833 #define IOMUXD_CSI_DIG_D02_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D02_update_mux_mode_MASK)
63834 /*! @} */
63835 
63836 /*! @name CSI_DIG_D03 - CSI_DIG_D03 */
63837 /*! @{ */
63838 #define IOMUXD_CSI_DIG_D03_PDRV_MASK             (0x1U)
63839 #define IOMUXD_CSI_DIG_D03_PDRV_SHIFT            (0U)
63840 /*! PDRV - Drive
63841  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
63842  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
63843  */
63844 #define IOMUXD_CSI_DIG_D03_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D03_PDRV_MASK)
63845 #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_MASK (0x1EU)
63846 #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_SHIFT (1U)
63847 /*! CSI_DIG_D03_reserved_1_4 - reserved
63848  */
63849 #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_MASK)
63850 #define IOMUXD_CSI_DIG_D03_PULL_MASK             (0x60U)
63851 #define IOMUXD_CSI_DIG_D03_PULL_SHIFT            (5U)
63852 /*! PULL - Pull Down Pull Up
63853  *  0b10..pull down
63854  *  0b01..pull up
63855  *  0b00..Prohibited
63856  *  0b11..pull disabled
63857  */
63858 #define IOMUXD_CSI_DIG_D03_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_PULL_SHIFT)) & IOMUXD_CSI_DIG_D03_PULL_MASK)
63859 #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_MASK (0x7FF80U)
63860 #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_SHIFT (7U)
63861 /*! CSI_DIG_D03_reserved_7_18 - reserved
63862  */
63863 #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_MASK)
63864 #define IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_MASK      (0x380000U)
63865 #define IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_SHIFT     (19U)
63866 /*! WAKEUP_CTRL - wakeup control
63867  *  0b000..OFF
63868  *  0b001..RESAMPLE
63869  *  0b100..LOW
63870  *  0b111..HIGH
63871  *  0b110..RISE
63872  *  0b101..FALL
63873  */
63874 #define IOMUXD_CSI_DIG_D03_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_MASK)
63875 #define IOMUXD_CSI_DIG_D03_WAKEUP_MASK_MASK      (0x400000U)
63876 #define IOMUXD_CSI_DIG_D03_WAKEUP_MASK_SHIFT     (22U)
63877 /*! WAKEUP_MASK - wakeup mask
63878  */
63879 #define IOMUXD_CSI_DIG_D03_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D03_WAKEUP_MASK_MASK)
63880 #define IOMUXD_CSI_DIG_D03_lp_config_MASK        (0x1800000U)
63881 #define IOMUXD_CSI_DIG_D03_lp_config_SHIFT       (23U)
63882 /*! lp_config - lower power configuration
63883  *  0b01..EARLY_ISO
63884  *  0b10..LATE_ISO
63885  *  0b11..LATCH
63886  *  0b00..PASS
63887  */
63888 #define IOMUXD_CSI_DIG_D03_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D03_lp_config_MASK)
63889 #define IOMUXD_CSI_DIG_D03_sw_config_MASK        (0x6000000U)
63890 #define IOMUXD_CSI_DIG_D03_sw_config_SHIFT       (25U)
63891 /*! sw_config - output and input configuration
63892  *  0b01..OPEN_DRAIN
63893  *  0b10..OPEN_DRAIN_INPUT
63894  *  0b11..INOUT
63895  *  0b00..DEFAULT
63896  */
63897 #define IOMUXD_CSI_DIG_D03_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D03_sw_config_MASK)
63898 #define IOMUXD_CSI_DIG_D03_mux_mode_MASK         (0x38000000U)
63899 #define IOMUXD_CSI_DIG_D03_mux_mode_SHIFT        (27U)
63900 /*! mux_mode - mux_mode
63901  *  0b000..CI_PI.D05
63902  *  0b010..ADMA.SAI2.RXC
63903  */
63904 #define IOMUXD_CSI_DIG_D03_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D03_mux_mode_MASK)
63905 #define IOMUXD_CSI_DIG_D03_update_pad_ctl_MASK   (0x40000000U)
63906 #define IOMUXD_CSI_DIG_D03_update_pad_ctl_SHIFT  (30U)
63907 /*! update_pad_ctl - update lock for pad control
63908  */
63909 #define IOMUXD_CSI_DIG_D03_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D03_update_pad_ctl_MASK)
63910 #define IOMUXD_CSI_DIG_D03_update_mux_mode_MASK  (0x80000000U)
63911 #define IOMUXD_CSI_DIG_D03_update_mux_mode_SHIFT (31U)
63912 /*! update_mux_mode - update lock for mux control
63913  */
63914 #define IOMUXD_CSI_DIG_D03_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D03_update_mux_mode_MASK)
63915 /*! @} */
63916 
63917 /*! @name CSI_DIG_D04 - CSI_DIG_D04 */
63918 /*! @{ */
63919 #define IOMUXD_CSI_DIG_D04_PDRV_MASK             (0x1U)
63920 #define IOMUXD_CSI_DIG_D04_PDRV_SHIFT            (0U)
63921 /*! PDRV - Drive
63922  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
63923  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
63924  */
63925 #define IOMUXD_CSI_DIG_D04_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D04_PDRV_MASK)
63926 #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_MASK (0x1EU)
63927 #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_SHIFT (1U)
63928 /*! CSI_DIG_D04_reserved_1_4 - reserved
63929  */
63930 #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_MASK)
63931 #define IOMUXD_CSI_DIG_D04_PULL_MASK             (0x60U)
63932 #define IOMUXD_CSI_DIG_D04_PULL_SHIFT            (5U)
63933 /*! PULL - Pull Down Pull Up
63934  *  0b10..pull down
63935  *  0b01..pull up
63936  *  0b00..Prohibited
63937  *  0b11..pull disabled
63938  */
63939 #define IOMUXD_CSI_DIG_D04_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_PULL_SHIFT)) & IOMUXD_CSI_DIG_D04_PULL_MASK)
63940 #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_MASK (0x7FF80U)
63941 #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_SHIFT (7U)
63942 /*! CSI_DIG_D04_reserved_7_18 - reserved
63943  */
63944 #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_MASK)
63945 #define IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_MASK      (0x380000U)
63946 #define IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_SHIFT     (19U)
63947 /*! WAKEUP_CTRL - wakeup control
63948  *  0b000..OFF
63949  *  0b001..RESAMPLE
63950  *  0b100..LOW
63951  *  0b111..HIGH
63952  *  0b110..RISE
63953  *  0b101..FALL
63954  */
63955 #define IOMUXD_CSI_DIG_D04_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_MASK)
63956 #define IOMUXD_CSI_DIG_D04_WAKEUP_MASK_MASK      (0x400000U)
63957 #define IOMUXD_CSI_DIG_D04_WAKEUP_MASK_SHIFT     (22U)
63958 /*! WAKEUP_MASK - wakeup mask
63959  */
63960 #define IOMUXD_CSI_DIG_D04_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D04_WAKEUP_MASK_MASK)
63961 #define IOMUXD_CSI_DIG_D04_lp_config_MASK        (0x1800000U)
63962 #define IOMUXD_CSI_DIG_D04_lp_config_SHIFT       (23U)
63963 /*! lp_config - lower power configuration
63964  *  0b01..EARLY_ISO
63965  *  0b10..LATE_ISO
63966  *  0b11..LATCH
63967  *  0b00..PASS
63968  */
63969 #define IOMUXD_CSI_DIG_D04_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D04_lp_config_MASK)
63970 #define IOMUXD_CSI_DIG_D04_sw_config_MASK        (0x6000000U)
63971 #define IOMUXD_CSI_DIG_D04_sw_config_SHIFT       (25U)
63972 /*! sw_config - output and input configuration
63973  *  0b01..OPEN_DRAIN
63974  *  0b10..OPEN_DRAIN_INPUT
63975  *  0b11..INOUT
63976  *  0b00..DEFAULT
63977  */
63978 #define IOMUXD_CSI_DIG_D04_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D04_sw_config_MASK)
63979 #define IOMUXD_CSI_DIG_D04_mux_mode_MASK         (0x38000000U)
63980 #define IOMUXD_CSI_DIG_D04_mux_mode_SHIFT        (27U)
63981 /*! mux_mode - mux_mode
63982  *  0b000..CI_PI.D06
63983  *  0b010..ADMA.SAI2.RXD
63984  */
63985 #define IOMUXD_CSI_DIG_D04_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D04_mux_mode_MASK)
63986 #define IOMUXD_CSI_DIG_D04_update_pad_ctl_MASK   (0x40000000U)
63987 #define IOMUXD_CSI_DIG_D04_update_pad_ctl_SHIFT  (30U)
63988 /*! update_pad_ctl - update lock for pad control
63989  */
63990 #define IOMUXD_CSI_DIG_D04_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D04_update_pad_ctl_MASK)
63991 #define IOMUXD_CSI_DIG_D04_update_mux_mode_MASK  (0x80000000U)
63992 #define IOMUXD_CSI_DIG_D04_update_mux_mode_SHIFT (31U)
63993 /*! update_mux_mode - update lock for mux control
63994  */
63995 #define IOMUXD_CSI_DIG_D04_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D04_update_mux_mode_MASK)
63996 /*! @} */
63997 
63998 /*! @name CSI_DIG_D05 - CSI_DIG_D05 */
63999 /*! @{ */
64000 #define IOMUXD_CSI_DIG_D05_PDRV_MASK             (0x1U)
64001 #define IOMUXD_CSI_DIG_D05_PDRV_SHIFT            (0U)
64002 /*! PDRV - Drive
64003  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64004  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64005  */
64006 #define IOMUXD_CSI_DIG_D05_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D05_PDRV_MASK)
64007 #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_MASK (0x1EU)
64008 #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_SHIFT (1U)
64009 /*! CSI_DIG_D05_reserved_1_4 - reserved
64010  */
64011 #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_MASK)
64012 #define IOMUXD_CSI_DIG_D05_PULL_MASK             (0x60U)
64013 #define IOMUXD_CSI_DIG_D05_PULL_SHIFT            (5U)
64014 /*! PULL - Pull Down Pull Up
64015  *  0b10..pull down
64016  *  0b01..pull up
64017  *  0b00..Prohibited
64018  *  0b11..pull disabled
64019  */
64020 #define IOMUXD_CSI_DIG_D05_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_PULL_SHIFT)) & IOMUXD_CSI_DIG_D05_PULL_MASK)
64021 #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_MASK (0x7FF80U)
64022 #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_SHIFT (7U)
64023 /*! CSI_DIG_D05_reserved_7_18 - reserved
64024  */
64025 #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_MASK)
64026 #define IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_MASK      (0x380000U)
64027 #define IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_SHIFT     (19U)
64028 /*! WAKEUP_CTRL - wakeup control
64029  *  0b000..OFF
64030  *  0b001..RESAMPLE
64031  *  0b100..LOW
64032  *  0b111..HIGH
64033  *  0b110..RISE
64034  *  0b101..FALL
64035  */
64036 #define IOMUXD_CSI_DIG_D05_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_MASK)
64037 #define IOMUXD_CSI_DIG_D05_WAKEUP_MASK_MASK      (0x400000U)
64038 #define IOMUXD_CSI_DIG_D05_WAKEUP_MASK_SHIFT     (22U)
64039 /*! WAKEUP_MASK - wakeup mask
64040  */
64041 #define IOMUXD_CSI_DIG_D05_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D05_WAKEUP_MASK_MASK)
64042 #define IOMUXD_CSI_DIG_D05_lp_config_MASK        (0x1800000U)
64043 #define IOMUXD_CSI_DIG_D05_lp_config_SHIFT       (23U)
64044 /*! lp_config - lower power configuration
64045  *  0b01..EARLY_ISO
64046  *  0b10..LATE_ISO
64047  *  0b11..LATCH
64048  *  0b00..PASS
64049  */
64050 #define IOMUXD_CSI_DIG_D05_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D05_lp_config_MASK)
64051 #define IOMUXD_CSI_DIG_D05_sw_config_MASK        (0x6000000U)
64052 #define IOMUXD_CSI_DIG_D05_sw_config_SHIFT       (25U)
64053 /*! sw_config - output and input configuration
64054  *  0b01..OPEN_DRAIN
64055  *  0b10..OPEN_DRAIN_INPUT
64056  *  0b11..INOUT
64057  *  0b00..DEFAULT
64058  */
64059 #define IOMUXD_CSI_DIG_D05_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D05_sw_config_MASK)
64060 #define IOMUXD_CSI_DIG_D05_mux_mode_MASK         (0x38000000U)
64061 #define IOMUXD_CSI_DIG_D05_mux_mode_SHIFT        (27U)
64062 /*! mux_mode - mux_mode
64063  *  0b000..CI_PI.D07
64064  *  0b010..ADMA.SAI2.RXFS
64065  */
64066 #define IOMUXD_CSI_DIG_D05_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D05_mux_mode_MASK)
64067 #define IOMUXD_CSI_DIG_D05_update_pad_ctl_MASK   (0x40000000U)
64068 #define IOMUXD_CSI_DIG_D05_update_pad_ctl_SHIFT  (30U)
64069 /*! update_pad_ctl - update lock for pad control
64070  */
64071 #define IOMUXD_CSI_DIG_D05_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D05_update_pad_ctl_MASK)
64072 #define IOMUXD_CSI_DIG_D05_update_mux_mode_MASK  (0x80000000U)
64073 #define IOMUXD_CSI_DIG_D05_update_mux_mode_SHIFT (31U)
64074 /*! update_mux_mode - update lock for mux control
64075  */
64076 #define IOMUXD_CSI_DIG_D05_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D05_update_mux_mode_MASK)
64077 /*! @} */
64078 
64079 /*! @name IOMUXD_GROUP_2_3 - na */
64080 /*! @{ */
64081 #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_MASK (0x1U)
64082 #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_SHIFT (0U)
64083 /*! PMIC_I2C_SDA - wakeup from PMIC_I2C_SDA
64084  */
64085 #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_MASK)
64086 #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_MASK  (0x2U)
64087 #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_SHIFT (1U)
64088 /*! PMIC_INT_B - wakeup from PMIC_INT_B
64089  */
64090 #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_MASK)
64091 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_MASK (0x4U)
64092 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_SHIFT (2U)
64093 /*! SCU_GPIO0_00 - wakeup from SCU_GPIO0_00
64094  */
64095 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_MASK)
64096 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_MASK (0x8U)
64097 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_SHIFT (3U)
64098 /*! SCU_GPIO0_01 - wakeup from SCU_GPIO0_01
64099  */
64100 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_MASK)
64101 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_MASK (0x10U)
64102 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_SHIFT (4U)
64103 /*! SCU_PMIC_STANDBY - wakeup from SCU_PMIC_STANDBY
64104  */
64105 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_MASK)
64106 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_MASK (0x20U)
64107 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_SHIFT (5U)
64108 /*! SCU_BOOT_MODE0 - wakeup from SCU_BOOT_MODE0
64109  */
64110 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_MASK)
64111 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_MASK (0x40U)
64112 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_SHIFT (6U)
64113 /*! SCU_BOOT_MODE1 - wakeup from SCU_BOOT_MODE1
64114  */
64115 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_MASK)
64116 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_MASK (0x80U)
64117 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_SHIFT (7U)
64118 /*! SCU_BOOT_MODE2 - wakeup from SCU_BOOT_MODE2
64119  */
64120 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_MASK)
64121 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_MASK (0x100U)
64122 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_SHIFT (8U)
64123 /*! SCU_BOOT_MODE3 - wakeup from SCU_BOOT_MODE3
64124  */
64125 #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_MASK)
64126 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_MASK (0x200U)
64127 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_SHIFT (9U)
64128 /*! CSI_DIG_D00 - wakeup from CSI_DIG_D00
64129  */
64130 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_MASK)
64131 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_MASK (0x400U)
64132 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_SHIFT (10U)
64133 /*! CSI_DIG_D01 - wakeup from CSI_DIG_D01
64134  */
64135 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_MASK)
64136 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_MASK (0x800U)
64137 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_SHIFT (11U)
64138 /*! CSI_DIG_D02 - wakeup from CSI_DIG_D02
64139  */
64140 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_MASK)
64141 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_MASK (0x1000U)
64142 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_SHIFT (12U)
64143 /*! CSI_DIG_D03 - wakeup from CSI_DIG_D03
64144  */
64145 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_MASK)
64146 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_MASK (0x2000U)
64147 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_SHIFT (13U)
64148 /*! CSI_DIG_D04 - wakeup from CSI_DIG_D04
64149  */
64150 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_MASK)
64151 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_MASK (0x4000U)
64152 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_SHIFT (14U)
64153 /*! CSI_DIG_D05 - wakeup from CSI_DIG_D05
64154  */
64155 #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_MASK)
64156 #define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_MASK (0xFFFF8000U)
64157 #define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_SHIFT (15U)
64158 /*! iomuxd_group_2_3_reserved_15_31 - reserved
64159  */
64160 #define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_MASK)
64161 /*! @} */
64162 
64163 /*! @name CSI_DIG_D06 - CSI_DIG_D06 */
64164 /*! @{ */
64165 #define IOMUXD_CSI_DIG_D06_PDRV_MASK             (0x1U)
64166 #define IOMUXD_CSI_DIG_D06_PDRV_SHIFT            (0U)
64167 /*! PDRV - Drive
64168  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64169  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64170  */
64171 #define IOMUXD_CSI_DIG_D06_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D06_PDRV_MASK)
64172 #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_MASK (0x1EU)
64173 #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_SHIFT (1U)
64174 /*! CSI_DIG_D06_reserved_1_4 - reserved
64175  */
64176 #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_MASK)
64177 #define IOMUXD_CSI_DIG_D06_PULL_MASK             (0x60U)
64178 #define IOMUXD_CSI_DIG_D06_PULL_SHIFT            (5U)
64179 /*! PULL - Pull Down Pull Up
64180  *  0b10..pull down
64181  *  0b01..pull up
64182  *  0b00..Prohibited
64183  *  0b11..pull disabled
64184  */
64185 #define IOMUXD_CSI_DIG_D06_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_PULL_SHIFT)) & IOMUXD_CSI_DIG_D06_PULL_MASK)
64186 #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_MASK (0x7FF80U)
64187 #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_SHIFT (7U)
64188 /*! CSI_DIG_D06_reserved_7_18 - reserved
64189  */
64190 #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_MASK)
64191 #define IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_MASK      (0x380000U)
64192 #define IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_SHIFT     (19U)
64193 /*! WAKEUP_CTRL - wakeup control
64194  *  0b000..OFF
64195  *  0b001..RESAMPLE
64196  *  0b100..LOW
64197  *  0b111..HIGH
64198  *  0b110..RISE
64199  *  0b101..FALL
64200  */
64201 #define IOMUXD_CSI_DIG_D06_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_MASK)
64202 #define IOMUXD_CSI_DIG_D06_WAKEUP_MASK_MASK      (0x400000U)
64203 #define IOMUXD_CSI_DIG_D06_WAKEUP_MASK_SHIFT     (22U)
64204 /*! WAKEUP_MASK - wakeup mask
64205  */
64206 #define IOMUXD_CSI_DIG_D06_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D06_WAKEUP_MASK_MASK)
64207 #define IOMUXD_CSI_DIG_D06_lp_config_MASK        (0x1800000U)
64208 #define IOMUXD_CSI_DIG_D06_lp_config_SHIFT       (23U)
64209 /*! lp_config - lower power configuration
64210  *  0b01..EARLY_ISO
64211  *  0b10..LATE_ISO
64212  *  0b11..LATCH
64213  *  0b00..PASS
64214  */
64215 #define IOMUXD_CSI_DIG_D06_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D06_lp_config_MASK)
64216 #define IOMUXD_CSI_DIG_D06_sw_config_MASK        (0x6000000U)
64217 #define IOMUXD_CSI_DIG_D06_sw_config_SHIFT       (25U)
64218 /*! sw_config - output and input configuration
64219  *  0b01..OPEN_DRAIN
64220  *  0b10..OPEN_DRAIN_INPUT
64221  *  0b11..INOUT
64222  *  0b00..DEFAULT
64223  */
64224 #define IOMUXD_CSI_DIG_D06_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D06_sw_config_MASK)
64225 #define IOMUXD_CSI_DIG_D06_mux_mode_MASK         (0x38000000U)
64226 #define IOMUXD_CSI_DIG_D06_mux_mode_SHIFT        (27U)
64227 /*! mux_mode - mux_mode
64228  *  0b000..CI_PI.D08
64229  *  0b010..ADMA.SAI3.RXC
64230  */
64231 #define IOMUXD_CSI_DIG_D06_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D06_mux_mode_MASK)
64232 #define IOMUXD_CSI_DIG_D06_update_pad_ctl_MASK   (0x40000000U)
64233 #define IOMUXD_CSI_DIG_D06_update_pad_ctl_SHIFT  (30U)
64234 /*! update_pad_ctl - update lock for pad control
64235  */
64236 #define IOMUXD_CSI_DIG_D06_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D06_update_pad_ctl_MASK)
64237 #define IOMUXD_CSI_DIG_D06_update_mux_mode_MASK  (0x80000000U)
64238 #define IOMUXD_CSI_DIG_D06_update_mux_mode_SHIFT (31U)
64239 /*! update_mux_mode - update lock for mux control
64240  */
64241 #define IOMUXD_CSI_DIG_D06_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D06_update_mux_mode_MASK)
64242 /*! @} */
64243 
64244 /*! @name CSI_DIG_D07 - CSI_DIG_D07 */
64245 /*! @{ */
64246 #define IOMUXD_CSI_DIG_D07_PDRV_MASK             (0x1U)
64247 #define IOMUXD_CSI_DIG_D07_PDRV_SHIFT            (0U)
64248 /*! PDRV - Drive
64249  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64250  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64251  */
64252 #define IOMUXD_CSI_DIG_D07_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D07_PDRV_MASK)
64253 #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_MASK (0x1EU)
64254 #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_SHIFT (1U)
64255 /*! CSI_DIG_D07_reserved_1_4 - reserved
64256  */
64257 #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_MASK)
64258 #define IOMUXD_CSI_DIG_D07_PULL_MASK             (0x60U)
64259 #define IOMUXD_CSI_DIG_D07_PULL_SHIFT            (5U)
64260 /*! PULL - Pull Down Pull Up
64261  *  0b10..pull down
64262  *  0b01..pull up
64263  *  0b00..Prohibited
64264  *  0b11..pull disabled
64265  */
64266 #define IOMUXD_CSI_DIG_D07_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_PULL_SHIFT)) & IOMUXD_CSI_DIG_D07_PULL_MASK)
64267 #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_MASK (0x7FF80U)
64268 #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_SHIFT (7U)
64269 /*! CSI_DIG_D07_reserved_7_18 - reserved
64270  */
64271 #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_MASK)
64272 #define IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_MASK      (0x380000U)
64273 #define IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_SHIFT     (19U)
64274 /*! WAKEUP_CTRL - wakeup control
64275  *  0b000..OFF
64276  *  0b001..RESAMPLE
64277  *  0b100..LOW
64278  *  0b111..HIGH
64279  *  0b110..RISE
64280  *  0b101..FALL
64281  */
64282 #define IOMUXD_CSI_DIG_D07_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_MASK)
64283 #define IOMUXD_CSI_DIG_D07_WAKEUP_MASK_MASK      (0x400000U)
64284 #define IOMUXD_CSI_DIG_D07_WAKEUP_MASK_SHIFT     (22U)
64285 /*! WAKEUP_MASK - wakeup mask
64286  */
64287 #define IOMUXD_CSI_DIG_D07_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D07_WAKEUP_MASK_MASK)
64288 #define IOMUXD_CSI_DIG_D07_lp_config_MASK        (0x1800000U)
64289 #define IOMUXD_CSI_DIG_D07_lp_config_SHIFT       (23U)
64290 /*! lp_config - lower power configuration
64291  *  0b01..EARLY_ISO
64292  *  0b10..LATE_ISO
64293  *  0b11..LATCH
64294  *  0b00..PASS
64295  */
64296 #define IOMUXD_CSI_DIG_D07_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D07_lp_config_MASK)
64297 #define IOMUXD_CSI_DIG_D07_sw_config_MASK        (0x6000000U)
64298 #define IOMUXD_CSI_DIG_D07_sw_config_SHIFT       (25U)
64299 /*! sw_config - output and input configuration
64300  *  0b01..OPEN_DRAIN
64301  *  0b10..OPEN_DRAIN_INPUT
64302  *  0b11..INOUT
64303  *  0b00..DEFAULT
64304  */
64305 #define IOMUXD_CSI_DIG_D07_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D07_sw_config_MASK)
64306 #define IOMUXD_CSI_DIG_D07_mux_mode_MASK         (0x38000000U)
64307 #define IOMUXD_CSI_DIG_D07_mux_mode_SHIFT        (27U)
64308 /*! mux_mode - mux_mode
64309  *  0b000..CI_PI.D09
64310  *  0b010..ADMA.SAI3.RXD
64311  */
64312 #define IOMUXD_CSI_DIG_D07_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D07_mux_mode_MASK)
64313 #define IOMUXD_CSI_DIG_D07_update_pad_ctl_MASK   (0x40000000U)
64314 #define IOMUXD_CSI_DIG_D07_update_pad_ctl_SHIFT  (30U)
64315 /*! update_pad_ctl - update lock for pad control
64316  */
64317 #define IOMUXD_CSI_DIG_D07_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D07_update_pad_ctl_MASK)
64318 #define IOMUXD_CSI_DIG_D07_update_mux_mode_MASK  (0x80000000U)
64319 #define IOMUXD_CSI_DIG_D07_update_mux_mode_SHIFT (31U)
64320 /*! update_mux_mode - update lock for mux control
64321  */
64322 #define IOMUXD_CSI_DIG_D07_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D07_update_mux_mode_MASK)
64323 /*! @} */
64324 
64325 /*! @name CSI_DIG_HSYNC - CSI_DIG_HSYNC */
64326 /*! @{ */
64327 #define IOMUXD_CSI_DIG_HSYNC_PDRV_MASK           (0x1U)
64328 #define IOMUXD_CSI_DIG_HSYNC_PDRV_SHIFT          (0U)
64329 /*! PDRV - Drive
64330  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64331  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64332  */
64333 #define IOMUXD_CSI_DIG_HSYNC_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_PDRV_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_PDRV_MASK)
64334 #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_MASK (0x1EU)
64335 #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_SHIFT (1U)
64336 /*! CSI_DIG_HSYNC_reserved_1_4 - reserved
64337  */
64338 #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_MASK)
64339 #define IOMUXD_CSI_DIG_HSYNC_PULL_MASK           (0x60U)
64340 #define IOMUXD_CSI_DIG_HSYNC_PULL_SHIFT          (5U)
64341 /*! PULL - Pull Down Pull Up
64342  *  0b10..pull down
64343  *  0b01..pull up
64344  *  0b00..Prohibited
64345  *  0b11..pull disabled
64346  */
64347 #define IOMUXD_CSI_DIG_HSYNC_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_PULL_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_PULL_MASK)
64348 #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_MASK (0x7FF80U)
64349 #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_SHIFT (7U)
64350 /*! CSI_DIG_HSYNC_reserved_7_18 - reserved
64351  */
64352 #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_MASK)
64353 #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_MASK    (0x380000U)
64354 #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_SHIFT   (19U)
64355 /*! WAKEUP_CTRL - wakeup control
64356  *  0b000..OFF
64357  *  0b001..RESAMPLE
64358  *  0b100..LOW
64359  *  0b111..HIGH
64360  *  0b110..RISE
64361  *  0b101..FALL
64362  */
64363 #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_MASK)
64364 #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_MASK    (0x400000U)
64365 #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_SHIFT   (22U)
64366 /*! WAKEUP_MASK - wakeup mask
64367  */
64368 #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_MASK)
64369 #define IOMUXD_CSI_DIG_HSYNC_lp_config_MASK      (0x1800000U)
64370 #define IOMUXD_CSI_DIG_HSYNC_lp_config_SHIFT     (23U)
64371 /*! lp_config - lower power configuration
64372  *  0b01..EARLY_ISO
64373  *  0b10..LATE_ISO
64374  *  0b11..LATCH
64375  *  0b00..PASS
64376  */
64377 #define IOMUXD_CSI_DIG_HSYNC_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_lp_config_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_lp_config_MASK)
64378 #define IOMUXD_CSI_DIG_HSYNC_sw_config_MASK      (0x6000000U)
64379 #define IOMUXD_CSI_DIG_HSYNC_sw_config_SHIFT     (25U)
64380 /*! sw_config - output and input configuration
64381  *  0b01..OPEN_DRAIN
64382  *  0b10..OPEN_DRAIN_INPUT
64383  *  0b11..INOUT
64384  *  0b00..DEFAULT
64385  */
64386 #define IOMUXD_CSI_DIG_HSYNC_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_sw_config_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_sw_config_MASK)
64387 #define IOMUXD_CSI_DIG_HSYNC_mux_mode_MASK       (0x38000000U)
64388 #define IOMUXD_CSI_DIG_HSYNC_mux_mode_SHIFT      (27U)
64389 /*! mux_mode - mux_mode
64390  *  0b000..CI_PI.HSYNC
64391  *  0b001..CI_PI.D00
64392  *  0b010..ADMA.SAI3.RXFS
64393  */
64394 #define IOMUXD_CSI_DIG_HSYNC_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_mux_mode_MASK)
64395 #define IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_MASK (0x40000000U)
64396 #define IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_SHIFT (30U)
64397 /*! update_pad_ctl - update lock for pad control
64398  */
64399 #define IOMUXD_CSI_DIG_HSYNC_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_MASK)
64400 #define IOMUXD_CSI_DIG_HSYNC_update_mux_mode_MASK (0x80000000U)
64401 #define IOMUXD_CSI_DIG_HSYNC_update_mux_mode_SHIFT (31U)
64402 /*! update_mux_mode - update lock for mux control
64403  */
64404 #define IOMUXD_CSI_DIG_HSYNC_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_update_mux_mode_MASK)
64405 /*! @} */
64406 
64407 /*! @name CSI_DIG_VSYNC - CSI_DIG_VSYNC */
64408 /*! @{ */
64409 #define IOMUXD_CSI_DIG_VSYNC_PDRV_MASK           (0x1U)
64410 #define IOMUXD_CSI_DIG_VSYNC_PDRV_SHIFT          (0U)
64411 /*! PDRV - Drive
64412  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64413  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64414  */
64415 #define IOMUXD_CSI_DIG_VSYNC_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_PDRV_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_PDRV_MASK)
64416 #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_MASK (0x1EU)
64417 #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_SHIFT (1U)
64418 /*! CSI_DIG_VSYNC_reserved_1_4 - reserved
64419  */
64420 #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_MASK)
64421 #define IOMUXD_CSI_DIG_VSYNC_PULL_MASK           (0x60U)
64422 #define IOMUXD_CSI_DIG_VSYNC_PULL_SHIFT          (5U)
64423 /*! PULL - Pull Down Pull Up
64424  *  0b10..pull down
64425  *  0b01..pull up
64426  *  0b00..Prohibited
64427  *  0b11..pull disabled
64428  */
64429 #define IOMUXD_CSI_DIG_VSYNC_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_PULL_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_PULL_MASK)
64430 #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_MASK (0x7FF80U)
64431 #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_SHIFT (7U)
64432 /*! CSI_DIG_VSYNC_reserved_7_18 - reserved
64433  */
64434 #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_MASK)
64435 #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_MASK    (0x380000U)
64436 #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_SHIFT   (19U)
64437 /*! WAKEUP_CTRL - wakeup control
64438  *  0b000..OFF
64439  *  0b001..RESAMPLE
64440  *  0b100..LOW
64441  *  0b111..HIGH
64442  *  0b110..RISE
64443  *  0b101..FALL
64444  */
64445 #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_MASK)
64446 #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_MASK    (0x400000U)
64447 #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_SHIFT   (22U)
64448 /*! WAKEUP_MASK - wakeup mask
64449  */
64450 #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_MASK)
64451 #define IOMUXD_CSI_DIG_VSYNC_lp_config_MASK      (0x1800000U)
64452 #define IOMUXD_CSI_DIG_VSYNC_lp_config_SHIFT     (23U)
64453 /*! lp_config - lower power configuration
64454  *  0b01..EARLY_ISO
64455  *  0b10..LATE_ISO
64456  *  0b11..LATCH
64457  *  0b00..PASS
64458  */
64459 #define IOMUXD_CSI_DIG_VSYNC_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_lp_config_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_lp_config_MASK)
64460 #define IOMUXD_CSI_DIG_VSYNC_sw_config_MASK      (0x6000000U)
64461 #define IOMUXD_CSI_DIG_VSYNC_sw_config_SHIFT     (25U)
64462 /*! sw_config - output and input configuration
64463  *  0b01..OPEN_DRAIN
64464  *  0b10..OPEN_DRAIN_INPUT
64465  *  0b11..INOUT
64466  *  0b00..DEFAULT
64467  */
64468 #define IOMUXD_CSI_DIG_VSYNC_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_sw_config_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_sw_config_MASK)
64469 #define IOMUXD_CSI_DIG_VSYNC_mux_mode_MASK       (0x38000000U)
64470 #define IOMUXD_CSI_DIG_VSYNC_mux_mode_SHIFT      (27U)
64471 /*! mux_mode - mux_mode
64472  *  0b000..CI_PI.VSYNC
64473  *  0b001..CI_PI.D01
64474  */
64475 #define IOMUXD_CSI_DIG_VSYNC_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_mux_mode_MASK)
64476 #define IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_MASK (0x40000000U)
64477 #define IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_SHIFT (30U)
64478 /*! update_pad_ctl - update lock for pad control
64479  */
64480 #define IOMUXD_CSI_DIG_VSYNC_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_MASK)
64481 #define IOMUXD_CSI_DIG_VSYNC_update_mux_mode_MASK (0x80000000U)
64482 #define IOMUXD_CSI_DIG_VSYNC_update_mux_mode_SHIFT (31U)
64483 /*! update_mux_mode - update lock for mux control
64484  */
64485 #define IOMUXD_CSI_DIG_VSYNC_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_update_mux_mode_MASK)
64486 /*! @} */
64487 
64488 /*! @name CSI_PCLK - CSI_PCLK */
64489 /*! @{ */
64490 #define IOMUXD_CSI_PCLK_PDRV_MASK                (0x1U)
64491 #define IOMUXD_CSI_PCLK_PDRV_SHIFT               (0U)
64492 /*! PDRV - Drive
64493  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64494  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64495  */
64496 #define IOMUXD_CSI_PCLK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_PDRV_SHIFT)) & IOMUXD_CSI_PCLK_PDRV_MASK)
64497 #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_MASK (0x1EU)
64498 #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_SHIFT (1U)
64499 /*! CSI_PCLK_reserved_1_4 - reserved
64500  */
64501 #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_SHIFT)) & IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_MASK)
64502 #define IOMUXD_CSI_PCLK_PULL_MASK                (0x60U)
64503 #define IOMUXD_CSI_PCLK_PULL_SHIFT               (5U)
64504 /*! PULL - Pull Down Pull Up
64505  *  0b10..pull down
64506  *  0b01..pull up
64507  *  0b00..Prohibited
64508  *  0b11..pull disabled
64509  */
64510 #define IOMUXD_CSI_PCLK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_PULL_SHIFT)) & IOMUXD_CSI_PCLK_PULL_MASK)
64511 #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_MASK (0x7FF80U)
64512 #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_SHIFT (7U)
64513 /*! CSI_PCLK_reserved_7_18 - reserved
64514  */
64515 #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_SHIFT)) & IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_MASK)
64516 #define IOMUXD_CSI_PCLK_WAKEUP_CTRL_MASK         (0x380000U)
64517 #define IOMUXD_CSI_PCLK_WAKEUP_CTRL_SHIFT        (19U)
64518 /*! WAKEUP_CTRL - wakeup control
64519  *  0b000..OFF
64520  *  0b001..RESAMPLE
64521  *  0b100..LOW
64522  *  0b111..HIGH
64523  *  0b110..RISE
64524  *  0b101..FALL
64525  */
64526 #define IOMUXD_CSI_PCLK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_PCLK_WAKEUP_CTRL_MASK)
64527 #define IOMUXD_CSI_PCLK_WAKEUP_MASK_MASK         (0x400000U)
64528 #define IOMUXD_CSI_PCLK_WAKEUP_MASK_SHIFT        (22U)
64529 /*! WAKEUP_MASK - wakeup mask
64530  */
64531 #define IOMUXD_CSI_PCLK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_PCLK_WAKEUP_MASK_MASK)
64532 #define IOMUXD_CSI_PCLK_lp_config_MASK           (0x1800000U)
64533 #define IOMUXD_CSI_PCLK_lp_config_SHIFT          (23U)
64534 /*! lp_config - lower power configuration
64535  *  0b01..EARLY_ISO
64536  *  0b10..LATE_ISO
64537  *  0b11..LATCH
64538  *  0b00..PASS
64539  */
64540 #define IOMUXD_CSI_PCLK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_lp_config_SHIFT)) & IOMUXD_CSI_PCLK_lp_config_MASK)
64541 #define IOMUXD_CSI_PCLK_sw_config_MASK           (0x6000000U)
64542 #define IOMUXD_CSI_PCLK_sw_config_SHIFT          (25U)
64543 /*! sw_config - output and input configuration
64544  *  0b01..OPEN_DRAIN
64545  *  0b10..OPEN_DRAIN_INPUT
64546  *  0b11..INOUT
64547  *  0b00..DEFAULT
64548  */
64549 #define IOMUXD_CSI_PCLK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_sw_config_SHIFT)) & IOMUXD_CSI_PCLK_sw_config_MASK)
64550 #define IOMUXD_CSI_PCLK_mux_mode_MASK            (0x38000000U)
64551 #define IOMUXD_CSI_PCLK_mux_mode_SHIFT           (27U)
64552 /*! mux_mode - mux_mode
64553  *  0b000..CI_PI.PCLK
64554  *  0b001..MIPI_CSI0.I2C0.SCL
64555  *  0b011..ADMA.SPI1.SCK
64556  *  0b100..LSIO.GPIO3.IO00
64557  */
64558 #define IOMUXD_CSI_PCLK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_mux_mode_SHIFT)) & IOMUXD_CSI_PCLK_mux_mode_MASK)
64559 #define IOMUXD_CSI_PCLK_update_pad_ctl_MASK      (0x40000000U)
64560 #define IOMUXD_CSI_PCLK_update_pad_ctl_SHIFT     (30U)
64561 /*! update_pad_ctl - update lock for pad control
64562  */
64563 #define IOMUXD_CSI_PCLK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_update_pad_ctl_SHIFT)) & IOMUXD_CSI_PCLK_update_pad_ctl_MASK)
64564 #define IOMUXD_CSI_PCLK_update_mux_mode_MASK     (0x80000000U)
64565 #define IOMUXD_CSI_PCLK_update_mux_mode_SHIFT    (31U)
64566 /*! update_mux_mode - update lock for mux control
64567  */
64568 #define IOMUXD_CSI_PCLK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_update_mux_mode_SHIFT)) & IOMUXD_CSI_PCLK_update_mux_mode_MASK)
64569 /*! @} */
64570 
64571 /*! @name CSI_MCLK - CSI_MCLK */
64572 /*! @{ */
64573 #define IOMUXD_CSI_MCLK_PDRV_MASK                (0x1U)
64574 #define IOMUXD_CSI_MCLK_PDRV_SHIFT               (0U)
64575 /*! PDRV - Drive
64576  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64577  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64578  */
64579 #define IOMUXD_CSI_MCLK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_PDRV_SHIFT)) & IOMUXD_CSI_MCLK_PDRV_MASK)
64580 #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_MASK (0x1EU)
64581 #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_SHIFT (1U)
64582 /*! CSI_MCLK_reserved_1_4 - reserved
64583  */
64584 #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_SHIFT)) & IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_MASK)
64585 #define IOMUXD_CSI_MCLK_PULL_MASK                (0x60U)
64586 #define IOMUXD_CSI_MCLK_PULL_SHIFT               (5U)
64587 /*! PULL - Pull Down Pull Up
64588  *  0b10..pull down
64589  *  0b01..pull up
64590  *  0b00..Prohibited
64591  *  0b11..pull disabled
64592  */
64593 #define IOMUXD_CSI_MCLK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_PULL_SHIFT)) & IOMUXD_CSI_MCLK_PULL_MASK)
64594 #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_MASK (0x7FF80U)
64595 #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_SHIFT (7U)
64596 /*! CSI_MCLK_reserved_7_18 - reserved
64597  */
64598 #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_SHIFT)) & IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_MASK)
64599 #define IOMUXD_CSI_MCLK_WAKEUP_CTRL_MASK         (0x380000U)
64600 #define IOMUXD_CSI_MCLK_WAKEUP_CTRL_SHIFT        (19U)
64601 /*! WAKEUP_CTRL - wakeup control
64602  *  0b000..OFF
64603  *  0b001..RESAMPLE
64604  *  0b100..LOW
64605  *  0b111..HIGH
64606  *  0b110..RISE
64607  *  0b101..FALL
64608  */
64609 #define IOMUXD_CSI_MCLK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_MCLK_WAKEUP_CTRL_MASK)
64610 #define IOMUXD_CSI_MCLK_WAKEUP_MASK_MASK         (0x400000U)
64611 #define IOMUXD_CSI_MCLK_WAKEUP_MASK_SHIFT        (22U)
64612 /*! WAKEUP_MASK - wakeup mask
64613  */
64614 #define IOMUXD_CSI_MCLK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_MCLK_WAKEUP_MASK_MASK)
64615 #define IOMUXD_CSI_MCLK_lp_config_MASK           (0x1800000U)
64616 #define IOMUXD_CSI_MCLK_lp_config_SHIFT          (23U)
64617 /*! lp_config - lower power configuration
64618  *  0b01..EARLY_ISO
64619  *  0b10..LATE_ISO
64620  *  0b11..LATCH
64621  *  0b00..PASS
64622  */
64623 #define IOMUXD_CSI_MCLK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_lp_config_SHIFT)) & IOMUXD_CSI_MCLK_lp_config_MASK)
64624 #define IOMUXD_CSI_MCLK_sw_config_MASK           (0x6000000U)
64625 #define IOMUXD_CSI_MCLK_sw_config_SHIFT          (25U)
64626 /*! sw_config - output and input configuration
64627  *  0b01..OPEN_DRAIN
64628  *  0b10..OPEN_DRAIN_INPUT
64629  *  0b11..INOUT
64630  *  0b00..DEFAULT
64631  */
64632 #define IOMUXD_CSI_MCLK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_sw_config_SHIFT)) & IOMUXD_CSI_MCLK_sw_config_MASK)
64633 #define IOMUXD_CSI_MCLK_mux_mode_MASK            (0x38000000U)
64634 #define IOMUXD_CSI_MCLK_mux_mode_SHIFT           (27U)
64635 /*! mux_mode - mux_mode
64636  *  0b000..CI_PI.MCLK
64637  *  0b001..MIPI_CSI0.I2C0.SDA
64638  *  0b011..ADMA.SPI1.SDO
64639  *  0b100..LSIO.GPIO3.IO01
64640  */
64641 #define IOMUXD_CSI_MCLK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_mux_mode_SHIFT)) & IOMUXD_CSI_MCLK_mux_mode_MASK)
64642 #define IOMUXD_CSI_MCLK_update_pad_ctl_MASK      (0x40000000U)
64643 #define IOMUXD_CSI_MCLK_update_pad_ctl_SHIFT     (30U)
64644 /*! update_pad_ctl - update lock for pad control
64645  */
64646 #define IOMUXD_CSI_MCLK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_update_pad_ctl_SHIFT)) & IOMUXD_CSI_MCLK_update_pad_ctl_MASK)
64647 #define IOMUXD_CSI_MCLK_update_mux_mode_MASK     (0x80000000U)
64648 #define IOMUXD_CSI_MCLK_update_mux_mode_SHIFT    (31U)
64649 /*! update_mux_mode - update lock for mux control
64650  */
64651 #define IOMUXD_CSI_MCLK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_update_mux_mode_SHIFT)) & IOMUXD_CSI_MCLK_update_mux_mode_MASK)
64652 /*! @} */
64653 
64654 /*! @name CSI_EN - CSI_EN */
64655 /*! @{ */
64656 #define IOMUXD_CSI_EN_PDRV_MASK                  (0x1U)
64657 #define IOMUXD_CSI_EN_PDRV_SHIFT                 (0U)
64658 /*! PDRV - Drive
64659  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64660  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64661  */
64662 #define IOMUXD_CSI_EN_PDRV(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_PDRV_SHIFT)) & IOMUXD_CSI_EN_PDRV_MASK)
64663 #define IOMUXD_CSI_EN_CSI_EN_reserved_1_4_MASK   (0x1EU)
64664 #define IOMUXD_CSI_EN_CSI_EN_reserved_1_4_SHIFT  (1U)
64665 /*! CSI_EN_reserved_1_4 - reserved
64666  */
64667 #define IOMUXD_CSI_EN_CSI_EN_reserved_1_4(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_CSI_EN_reserved_1_4_SHIFT)) & IOMUXD_CSI_EN_CSI_EN_reserved_1_4_MASK)
64668 #define IOMUXD_CSI_EN_PULL_MASK                  (0x60U)
64669 #define IOMUXD_CSI_EN_PULL_SHIFT                 (5U)
64670 /*! PULL - Pull Down Pull Up
64671  *  0b10..pull down
64672  *  0b01..pull up
64673  *  0b00..Prohibited
64674  *  0b11..pull disabled
64675  */
64676 #define IOMUXD_CSI_EN_PULL(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_PULL_SHIFT)) & IOMUXD_CSI_EN_PULL_MASK)
64677 #define IOMUXD_CSI_EN_CSI_EN_reserved_7_18_MASK  (0x7FF80U)
64678 #define IOMUXD_CSI_EN_CSI_EN_reserved_7_18_SHIFT (7U)
64679 /*! CSI_EN_reserved_7_18 - reserved
64680  */
64681 #define IOMUXD_CSI_EN_CSI_EN_reserved_7_18(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_CSI_EN_reserved_7_18_SHIFT)) & IOMUXD_CSI_EN_CSI_EN_reserved_7_18_MASK)
64682 #define IOMUXD_CSI_EN_WAKEUP_CTRL_MASK           (0x380000U)
64683 #define IOMUXD_CSI_EN_WAKEUP_CTRL_SHIFT          (19U)
64684 /*! WAKEUP_CTRL - wakeup control
64685  *  0b000..OFF
64686  *  0b001..RESAMPLE
64687  *  0b100..LOW
64688  *  0b111..HIGH
64689  *  0b110..RISE
64690  *  0b101..FALL
64691  */
64692 #define IOMUXD_CSI_EN_WAKEUP_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_EN_WAKEUP_CTRL_MASK)
64693 #define IOMUXD_CSI_EN_WAKEUP_MASK_MASK           (0x400000U)
64694 #define IOMUXD_CSI_EN_WAKEUP_MASK_SHIFT          (22U)
64695 /*! WAKEUP_MASK - wakeup mask
64696  */
64697 #define IOMUXD_CSI_EN_WAKEUP_MASK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_EN_WAKEUP_MASK_MASK)
64698 #define IOMUXD_CSI_EN_lp_config_MASK             (0x1800000U)
64699 #define IOMUXD_CSI_EN_lp_config_SHIFT            (23U)
64700 /*! lp_config - lower power configuration
64701  *  0b01..EARLY_ISO
64702  *  0b10..LATE_ISO
64703  *  0b11..LATCH
64704  *  0b00..PASS
64705  */
64706 #define IOMUXD_CSI_EN_lp_config(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_lp_config_SHIFT)) & IOMUXD_CSI_EN_lp_config_MASK)
64707 #define IOMUXD_CSI_EN_sw_config_MASK             (0x6000000U)
64708 #define IOMUXD_CSI_EN_sw_config_SHIFT            (25U)
64709 /*! sw_config - output and input configuration
64710  *  0b01..OPEN_DRAIN
64711  *  0b10..OPEN_DRAIN_INPUT
64712  *  0b11..INOUT
64713  *  0b00..DEFAULT
64714  */
64715 #define IOMUXD_CSI_EN_sw_config(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_sw_config_SHIFT)) & IOMUXD_CSI_EN_sw_config_MASK)
64716 #define IOMUXD_CSI_EN_mux_mode_MASK              (0x38000000U)
64717 #define IOMUXD_CSI_EN_mux_mode_SHIFT             (27U)
64718 /*! mux_mode - mux_mode
64719  *  0b000..CI_PI.EN
64720  *  0b001..CI_PI.I2C.SCL
64721  *  0b010..ADMA.I2C3.SCL
64722  *  0b011..ADMA.SPI1.SDI
64723  *  0b100..LSIO.GPIO3.IO02
64724  */
64725 #define IOMUXD_CSI_EN_mux_mode(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_mux_mode_SHIFT)) & IOMUXD_CSI_EN_mux_mode_MASK)
64726 #define IOMUXD_CSI_EN_update_pad_ctl_MASK        (0x40000000U)
64727 #define IOMUXD_CSI_EN_update_pad_ctl_SHIFT       (30U)
64728 /*! update_pad_ctl - update lock for pad control
64729  */
64730 #define IOMUXD_CSI_EN_update_pad_ctl(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_update_pad_ctl_SHIFT)) & IOMUXD_CSI_EN_update_pad_ctl_MASK)
64731 #define IOMUXD_CSI_EN_update_mux_mode_MASK       (0x80000000U)
64732 #define IOMUXD_CSI_EN_update_mux_mode_SHIFT      (31U)
64733 /*! update_mux_mode - update lock for mux control
64734  */
64735 #define IOMUXD_CSI_EN_update_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_update_mux_mode_SHIFT)) & IOMUXD_CSI_EN_update_mux_mode_MASK)
64736 /*! @} */
64737 
64738 /*! @name CSI_RESET - CSI_RESET */
64739 /*! @{ */
64740 #define IOMUXD_CSI_RESET_PDRV_MASK               (0x1U)
64741 #define IOMUXD_CSI_RESET_PDRV_SHIFT              (0U)
64742 /*! PDRV - Drive
64743  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64744  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64745  */
64746 #define IOMUXD_CSI_RESET_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_PDRV_SHIFT)) & IOMUXD_CSI_RESET_PDRV_MASK)
64747 #define IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_MASK (0x1EU)
64748 #define IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_SHIFT (1U)
64749 /*! CSI_RESET_reserved_1_4 - reserved
64750  */
64751 #define IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_SHIFT)) & IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_MASK)
64752 #define IOMUXD_CSI_RESET_PULL_MASK               (0x60U)
64753 #define IOMUXD_CSI_RESET_PULL_SHIFT              (5U)
64754 /*! PULL - Pull Down Pull Up
64755  *  0b10..pull down
64756  *  0b01..pull up
64757  *  0b00..Prohibited
64758  *  0b11..pull disabled
64759  */
64760 #define IOMUXD_CSI_RESET_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_PULL_SHIFT)) & IOMUXD_CSI_RESET_PULL_MASK)
64761 #define IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_MASK (0x7FF80U)
64762 #define IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_SHIFT (7U)
64763 /*! CSI_RESET_reserved_7_18 - reserved
64764  */
64765 #define IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_SHIFT)) & IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_MASK)
64766 #define IOMUXD_CSI_RESET_WAKEUP_CTRL_MASK        (0x380000U)
64767 #define IOMUXD_CSI_RESET_WAKEUP_CTRL_SHIFT       (19U)
64768 /*! WAKEUP_CTRL - wakeup control
64769  *  0b000..OFF
64770  *  0b001..RESAMPLE
64771  *  0b100..LOW
64772  *  0b111..HIGH
64773  *  0b110..RISE
64774  *  0b101..FALL
64775  */
64776 #define IOMUXD_CSI_RESET_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_RESET_WAKEUP_CTRL_MASK)
64777 #define IOMUXD_CSI_RESET_WAKEUP_MASK_MASK        (0x400000U)
64778 #define IOMUXD_CSI_RESET_WAKEUP_MASK_SHIFT       (22U)
64779 /*! WAKEUP_MASK - wakeup mask
64780  */
64781 #define IOMUXD_CSI_RESET_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_RESET_WAKEUP_MASK_MASK)
64782 #define IOMUXD_CSI_RESET_lp_config_MASK          (0x1800000U)
64783 #define IOMUXD_CSI_RESET_lp_config_SHIFT         (23U)
64784 /*! lp_config - lower power configuration
64785  *  0b01..EARLY_ISO
64786  *  0b10..LATE_ISO
64787  *  0b11..LATCH
64788  *  0b00..PASS
64789  */
64790 #define IOMUXD_CSI_RESET_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_lp_config_SHIFT)) & IOMUXD_CSI_RESET_lp_config_MASK)
64791 #define IOMUXD_CSI_RESET_sw_config_MASK          (0x6000000U)
64792 #define IOMUXD_CSI_RESET_sw_config_SHIFT         (25U)
64793 /*! sw_config - output and input configuration
64794  *  0b01..OPEN_DRAIN
64795  *  0b10..OPEN_DRAIN_INPUT
64796  *  0b11..INOUT
64797  *  0b00..DEFAULT
64798  */
64799 #define IOMUXD_CSI_RESET_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_sw_config_SHIFT)) & IOMUXD_CSI_RESET_sw_config_MASK)
64800 #define IOMUXD_CSI_RESET_mux_mode_MASK           (0x38000000U)
64801 #define IOMUXD_CSI_RESET_mux_mode_SHIFT          (27U)
64802 /*! mux_mode - mux_mode
64803  *  0b000..CI_PI.RESET
64804  *  0b001..CI_PI.I2C.SDA
64805  *  0b010..ADMA.I2C3.SDA
64806  *  0b011..ADMA.SPI1.CS0
64807  *  0b100..LSIO.GPIO3.IO03
64808  */
64809 #define IOMUXD_CSI_RESET_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_mux_mode_SHIFT)) & IOMUXD_CSI_RESET_mux_mode_MASK)
64810 #define IOMUXD_CSI_RESET_update_pad_ctl_MASK     (0x40000000U)
64811 #define IOMUXD_CSI_RESET_update_pad_ctl_SHIFT    (30U)
64812 /*! update_pad_ctl - update lock for pad control
64813  */
64814 #define IOMUXD_CSI_RESET_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_update_pad_ctl_SHIFT)) & IOMUXD_CSI_RESET_update_pad_ctl_MASK)
64815 #define IOMUXD_CSI_RESET_update_mux_mode_MASK    (0x80000000U)
64816 #define IOMUXD_CSI_RESET_update_mux_mode_SHIFT   (31U)
64817 /*! update_mux_mode - update lock for mux control
64818  */
64819 #define IOMUXD_CSI_RESET_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_update_mux_mode_SHIFT)) & IOMUXD_CSI_RESET_update_mux_mode_MASK)
64820 /*! @} */
64821 
64822 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD */
64823 /*! @{ */
64824 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_MASK (0x7U)
64825 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_SHIFT (0U)
64826 /*! COMP - COMP
64827  *  0b010..Fixed code mode
64828  *  0b100..High impedance mode
64829  *  0b110..Read mode
64830  *  0b000..Normal Mode
64831  *  0b001..Freeze Mode
64832  */
64833 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_MASK)
64834 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_MASK (0x8U)
64835 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_SHIFT (3U)
64836 /*! FASTFRZ_EN - FASTFRZ_EN
64837  *  0b1..FASTFRZ signal is driven by output of subsystem
64838  *  0b0..FASTFRZ signal is gated to 0
64839  */
64840 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_MASK)
64841 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_MASK (0x10U)
64842 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_SHIFT (4U)
64843 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4 - reserved
64844  */
64845 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_MASK)
64846 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_MASK (0x1E0U)
64847 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_SHIFT (5U)
64848 /*! RASRCP - RASRCP
64849  *  0b0101..Reset Value
64850  */
64851 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_MASK)
64852 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_MASK (0x1E00U)
64853 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_SHIFT (9U)
64854 /*! RASRCN - RASRCN
64855  *  0b1010..Reset Value
64856  */
64857 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_MASK)
64858 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_MASK (0x2000U)
64859 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_SHIFT (13U)
64860 /*! SELECT_NASRC - SELECT_NASRC
64861  *  0b1..NASRCN value
64862  *  0b0..NASRCP value
64863  */
64864 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_MASK)
64865 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_MASK (0x4000U)
64866 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_SHIFT (14U)
64867 /*! COMPOK - COMPOK
64868  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
64869  *  0b1..compensation cell in Normal mode and tracking PVT
64870  */
64871 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_MASK)
64872 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_MASK (0x78000U)
64873 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_SHIFT (15U)
64874 /*! READ_NASRC - READ_NASRC
64875  *  0b0000..READ Only
64876  */
64877 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_MASK)
64878 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_MASK (0x780000U)
64879 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_SHIFT (19U)
64880 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22 - reserved
64881  */
64882 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_MASK)
64883 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_MASK (0x1800000U)
64884 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_SHIFT (23U)
64885 /*! SLEEP - SLEEP
64886  *  0b11..Force into sleep mode
64887  *  0b00..NO
64888  *  0b01..EARLY
64889  *  0b10..LATE
64890  */
64891 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_MASK)
64892 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_MASK (0x3E000000U)
64893 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_SHIFT (25U)
64894 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29 - reserved
64895  */
64896 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_MASK)
64897 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_MASK (0x40000000U)
64898 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_SHIFT (30U)
64899 /*! update_pad_ctl - update lock for pad control
64900  */
64901 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_MASK)
64902 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_MASK (0x80000000U)
64903 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_SHIFT (31U)
64904 /*! update_mux_mode - update lock for mux control
64905  */
64906 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_MASK)
64907 /*! @} */
64908 
64909 /*! @name MIPI_CSI0_MCLK_OUT - MIPI_CSI0_MCLK_OUT */
64910 /*! @{ */
64911 #define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_MASK       (0x7U)
64912 #define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_SHIFT      (0U)
64913 /*! DSE - Drive
64914  *  0b001..Drive select 2mA
64915  *  0b011..Drive select 6mA
64916  *  0b111..High Speed
64917  *  0b110..Drive select 12mA
64918  *  0b010..Drive select 4mA
64919  *  0b100..Drive select 8mA
64920  *  0b000..Drive select 1mA
64921  *  0b101..Drive select 10mA
64922  */
64923 #define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_MASK)
64924 #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_MASK (0x18U)
64925 #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_SHIFT (3U)
64926 /*! MIPI_CSI0_MCLK_OUT_reserved_3_4 - reserved
64927  */
64928 #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_MASK)
64929 #define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_MASK      (0x60U)
64930 #define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_SHIFT     (5U)
64931 /*! PULL - Pull Down Pull Up
64932  *  0b00..Bus-Keeper
64933  *  0b10..pull down
64934  *  0b01..pull up
64935  *  0b11..No Pull
64936  */
64937 #define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_MASK)
64938 #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_MASK (0x7FF80U)
64939 #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_SHIFT (7U)
64940 /*! MIPI_CSI0_MCLK_OUT_reserved_7_18 - reserved
64941  */
64942 #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_MASK)
64943 #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_MASK (0x380000U)
64944 #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_SHIFT (19U)
64945 /*! WAKEUP_CTRL - wakeup control
64946  *  0b000..OFF
64947  *  0b001..RESAMPLE
64948  *  0b100..LOW
64949  *  0b111..HIGH
64950  *  0b110..RISE
64951  *  0b101..FALL
64952  */
64953 #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_MASK)
64954 #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_MASK (0x400000U)
64955 #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_SHIFT (22U)
64956 /*! WAKEUP_MASK - wakeup mask
64957  */
64958 #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_MASK)
64959 #define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_MASK (0x1800000U)
64960 #define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_SHIFT (23U)
64961 /*! lp_config - lower power configuration
64962  *  0b01..EARLY_ISO
64963  *  0b10..LATE_ISO
64964  *  0b11..LATCH
64965  *  0b00..PASS
64966  */
64967 #define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_MASK)
64968 #define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_MASK (0x6000000U)
64969 #define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_SHIFT (25U)
64970 /*! sw_config - output and input configuration
64971  *  0b01..OPEN_DRAIN
64972  *  0b10..OPEN_DRAIN_INPUT
64973  *  0b11..INOUT
64974  *  0b00..DEFAULT
64975  */
64976 #define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_MASK)
64977 #define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_MASK  (0x38000000U)
64978 #define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_SHIFT (27U)
64979 /*! mux_mode - mux_mode
64980  *  0b000..MIPI_CSI0.ACM.MCLK_OUT
64981  *  0b100..LSIO.GPIO3.IO04
64982  */
64983 #define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_MASK)
64984 #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_MASK (0x40000000U)
64985 #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_SHIFT (30U)
64986 /*! update_pad_ctl - update lock for pad control
64987  */
64988 #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_MASK)
64989 #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_MASK (0x80000000U)
64990 #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_SHIFT (31U)
64991 /*! update_mux_mode - update lock for mux control
64992  */
64993 #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_MASK)
64994 /*! @} */
64995 
64996 /*! @name MIPI_CSI0_I2C0_SCL - MIPI_CSI0_I2C0_SCL */
64997 /*! @{ */
64998 #define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_MASK       (0x7U)
64999 #define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_SHIFT      (0U)
65000 /*! DSE - Drive
65001  *  0b001..Drive select 2mA
65002  *  0b011..Drive select 6mA
65003  *  0b111..High Speed
65004  *  0b110..Drive select 12mA
65005  *  0b010..Drive select 4mA
65006  *  0b100..Drive select 8mA
65007  *  0b000..Drive select 1mA
65008  *  0b101..Drive select 10mA
65009  */
65010 #define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_MASK)
65011 #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_MASK (0x18U)
65012 #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_SHIFT (3U)
65013 /*! MIPI_CSI0_I2C0_SCL_reserved_3_4 - reserved
65014  */
65015 #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_MASK)
65016 #define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_MASK      (0x60U)
65017 #define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_SHIFT     (5U)
65018 /*! PULL - Pull Down Pull Up
65019  *  0b00..Bus-Keeper
65020  *  0b10..pull down
65021  *  0b01..pull up
65022  *  0b11..No Pull
65023  */
65024 #define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_MASK)
65025 #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
65026 #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_SHIFT (7U)
65027 /*! MIPI_CSI0_I2C0_SCL_reserved_7_18 - reserved
65028  */
65029 #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_MASK)
65030 #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
65031 #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
65032 /*! WAKEUP_CTRL - wakeup control
65033  *  0b000..OFF
65034  *  0b001..RESAMPLE
65035  *  0b100..LOW
65036  *  0b111..HIGH
65037  *  0b110..RISE
65038  *  0b101..FALL
65039  */
65040 #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_MASK)
65041 #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
65042 #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
65043 /*! WAKEUP_MASK - wakeup mask
65044  */
65045 #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_MASK)
65046 #define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_MASK (0x1800000U)
65047 #define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_SHIFT (23U)
65048 /*! lp_config - lower power configuration
65049  *  0b01..EARLY_ISO
65050  *  0b10..LATE_ISO
65051  *  0b11..LATCH
65052  *  0b00..PASS
65053  */
65054 #define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_MASK)
65055 #define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_MASK (0x6000000U)
65056 #define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_SHIFT (25U)
65057 /*! sw_config - output and input configuration
65058  *  0b01..OPEN_DRAIN
65059  *  0b10..OPEN_DRAIN_INPUT
65060  *  0b11..INOUT
65061  *  0b00..DEFAULT
65062  */
65063 #define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_MASK)
65064 #define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_MASK  (0x38000000U)
65065 #define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_SHIFT (27U)
65066 /*! mux_mode - mux_mode
65067  *  0b000..MIPI_CSI0.I2C0.SCL
65068  *  0b001..MIPI_CSI0.GPIO0.IO02
65069  *  0b100..LSIO.GPIO3.IO05
65070  */
65071 #define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_MASK)
65072 #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
65073 #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_SHIFT (30U)
65074 /*! update_pad_ctl - update lock for pad control
65075  */
65076 #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_MASK)
65077 #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
65078 #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_SHIFT (31U)
65079 /*! update_mux_mode - update lock for mux control
65080  */
65081 #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_MASK)
65082 /*! @} */
65083 
65084 /*! @name MIPI_CSI0_I2C0_SDA - MIPI_CSI0_I2C0_SDA */
65085 /*! @{ */
65086 #define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_MASK       (0x7U)
65087 #define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_SHIFT      (0U)
65088 /*! DSE - Drive
65089  *  0b001..Drive select 2mA
65090  *  0b011..Drive select 6mA
65091  *  0b111..High Speed
65092  *  0b110..Drive select 12mA
65093  *  0b010..Drive select 4mA
65094  *  0b100..Drive select 8mA
65095  *  0b000..Drive select 1mA
65096  *  0b101..Drive select 10mA
65097  */
65098 #define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_MASK)
65099 #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_MASK (0x18U)
65100 #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_SHIFT (3U)
65101 /*! MIPI_CSI0_I2C0_SDA_reserved_3_4 - reserved
65102  */
65103 #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_MASK)
65104 #define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_MASK      (0x60U)
65105 #define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_SHIFT     (5U)
65106 /*! PULL - Pull Down Pull Up
65107  *  0b00..Bus-Keeper
65108  *  0b10..pull down
65109  *  0b01..pull up
65110  *  0b11..No Pull
65111  */
65112 #define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_MASK)
65113 #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
65114 #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_SHIFT (7U)
65115 /*! MIPI_CSI0_I2C0_SDA_reserved_7_18 - reserved
65116  */
65117 #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_MASK)
65118 #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
65119 #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
65120 /*! WAKEUP_CTRL - wakeup control
65121  *  0b000..OFF
65122  *  0b001..RESAMPLE
65123  *  0b100..LOW
65124  *  0b111..HIGH
65125  *  0b110..RISE
65126  *  0b101..FALL
65127  */
65128 #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_MASK)
65129 #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
65130 #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
65131 /*! WAKEUP_MASK - wakeup mask
65132  */
65133 #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_MASK)
65134 #define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_MASK (0x1800000U)
65135 #define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_SHIFT (23U)
65136 /*! lp_config - lower power configuration
65137  *  0b01..EARLY_ISO
65138  *  0b10..LATE_ISO
65139  *  0b11..LATCH
65140  *  0b00..PASS
65141  */
65142 #define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_MASK)
65143 #define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_MASK (0x6000000U)
65144 #define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_SHIFT (25U)
65145 /*! sw_config - output and input configuration
65146  *  0b01..OPEN_DRAIN
65147  *  0b10..OPEN_DRAIN_INPUT
65148  *  0b11..INOUT
65149  *  0b00..DEFAULT
65150  */
65151 #define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_MASK)
65152 #define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_MASK  (0x38000000U)
65153 #define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_SHIFT (27U)
65154 /*! mux_mode - mux_mode
65155  *  0b000..MIPI_CSI0.I2C0.SDA
65156  *  0b001..MIPI_CSI0.GPIO0.IO03
65157  *  0b100..LSIO.GPIO3.IO06
65158  */
65159 #define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_MASK)
65160 #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
65161 #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_SHIFT (30U)
65162 /*! update_pad_ctl - update lock for pad control
65163  */
65164 #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_MASK)
65165 #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
65166 #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_SHIFT (31U)
65167 /*! update_mux_mode - update lock for mux control
65168  */
65169 #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_MASK)
65170 /*! @} */
65171 
65172 /*! @name MIPI_CSI0_GPIO0_01 - MIPI_CSI0_GPIO0_01 */
65173 /*! @{ */
65174 #define IOMUXD_MIPI_CSI0_GPIO0_01_DSE_MASK       (0x7U)
65175 #define IOMUXD_MIPI_CSI0_GPIO0_01_DSE_SHIFT      (0U)
65176 /*! DSE - Drive
65177  *  0b001..Drive select 2mA
65178  *  0b011..Drive select 6mA
65179  *  0b111..High Speed
65180  *  0b110..Drive select 12mA
65181  *  0b010..Drive select 4mA
65182  *  0b100..Drive select 8mA
65183  *  0b000..Drive select 1mA
65184  *  0b101..Drive select 10mA
65185  */
65186 #define IOMUXD_MIPI_CSI0_GPIO0_01_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_DSE_MASK)
65187 #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_MASK (0x18U)
65188 #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_SHIFT (3U)
65189 /*! MIPI_CSI0_GPIO0_01_reserved_3_4 - reserved
65190  */
65191 #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_MASK)
65192 #define IOMUXD_MIPI_CSI0_GPIO0_01_PULL_MASK      (0x60U)
65193 #define IOMUXD_MIPI_CSI0_GPIO0_01_PULL_SHIFT     (5U)
65194 /*! PULL - Pull Down Pull Up
65195  *  0b00..Bus-Keeper
65196  *  0b10..pull down
65197  *  0b01..pull up
65198  *  0b11..No Pull
65199  */
65200 #define IOMUXD_MIPI_CSI0_GPIO0_01_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_PULL_MASK)
65201 #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
65202 #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_SHIFT (7U)
65203 /*! MIPI_CSI0_GPIO0_01_reserved_7_18 - reserved
65204  */
65205 #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_MASK)
65206 #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
65207 #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
65208 /*! WAKEUP_CTRL - wakeup control
65209  *  0b000..OFF
65210  *  0b001..RESAMPLE
65211  *  0b100..LOW
65212  *  0b111..HIGH
65213  *  0b110..RISE
65214  *  0b101..FALL
65215  */
65216 #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_MASK)
65217 #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
65218 #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
65219 /*! WAKEUP_MASK - wakeup mask
65220  */
65221 #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_MASK)
65222 #define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_MASK (0x1800000U)
65223 #define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_SHIFT (23U)
65224 /*! lp_config - lower power configuration
65225  *  0b01..EARLY_ISO
65226  *  0b10..LATE_ISO
65227  *  0b11..LATCH
65228  *  0b00..PASS
65229  */
65230 #define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_MASK)
65231 #define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_MASK (0x6000000U)
65232 #define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_SHIFT (25U)
65233 /*! sw_config - output and input configuration
65234  *  0b01..OPEN_DRAIN
65235  *  0b10..OPEN_DRAIN_INPUT
65236  *  0b11..INOUT
65237  *  0b00..DEFAULT
65238  */
65239 #define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_MASK)
65240 #define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_MASK  (0x38000000U)
65241 #define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_SHIFT (27U)
65242 /*! mux_mode - mux_mode
65243  *  0b000..MIPI_CSI0.GPIO0.IO01
65244  *  0b001..ADMA.I2C0.SDA
65245  *  0b100..LSIO.GPIO3.IO07
65246  */
65247 #define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_MASK)
65248 #define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
65249 #define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_SHIFT (30U)
65250 /*! update_pad_ctl - update lock for pad control
65251  */
65252 #define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_MASK)
65253 #define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_MASK (0x80000000U)
65254 #define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_SHIFT (31U)
65255 /*! update_mux_mode - update lock for mux control
65256  */
65257 #define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_MASK)
65258 /*! @} */
65259 
65260 /*! @name MIPI_CSI0_GPIO0_00 - MIPI_CSI0_GPIO0_00 */
65261 /*! @{ */
65262 #define IOMUXD_MIPI_CSI0_GPIO0_00_DSE_MASK       (0x7U)
65263 #define IOMUXD_MIPI_CSI0_GPIO0_00_DSE_SHIFT      (0U)
65264 /*! DSE - Drive
65265  *  0b001..Drive select 2mA
65266  *  0b011..Drive select 6mA
65267  *  0b111..High Speed
65268  *  0b110..Drive select 12mA
65269  *  0b010..Drive select 4mA
65270  *  0b100..Drive select 8mA
65271  *  0b000..Drive select 1mA
65272  *  0b101..Drive select 10mA
65273  */
65274 #define IOMUXD_MIPI_CSI0_GPIO0_00_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_DSE_MASK)
65275 #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_MASK (0x18U)
65276 #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_SHIFT (3U)
65277 /*! MIPI_CSI0_GPIO0_00_reserved_3_4 - reserved
65278  */
65279 #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_MASK)
65280 #define IOMUXD_MIPI_CSI0_GPIO0_00_PULL_MASK      (0x60U)
65281 #define IOMUXD_MIPI_CSI0_GPIO0_00_PULL_SHIFT     (5U)
65282 /*! PULL - Pull Down Pull Up
65283  *  0b00..Bus-Keeper
65284  *  0b10..pull down
65285  *  0b01..pull up
65286  *  0b11..No Pull
65287  */
65288 #define IOMUXD_MIPI_CSI0_GPIO0_00_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_PULL_MASK)
65289 #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
65290 #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_SHIFT (7U)
65291 /*! MIPI_CSI0_GPIO0_00_reserved_7_18 - reserved
65292  */
65293 #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_MASK)
65294 #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
65295 #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
65296 /*! WAKEUP_CTRL - wakeup control
65297  *  0b000..OFF
65298  *  0b001..RESAMPLE
65299  *  0b100..LOW
65300  *  0b111..HIGH
65301  *  0b110..RISE
65302  *  0b101..FALL
65303  */
65304 #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_MASK)
65305 #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
65306 #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
65307 /*! WAKEUP_MASK - wakeup mask
65308  */
65309 #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_MASK)
65310 #define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_MASK (0x1800000U)
65311 #define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_SHIFT (23U)
65312 /*! lp_config - lower power configuration
65313  *  0b01..EARLY_ISO
65314  *  0b10..LATE_ISO
65315  *  0b11..LATCH
65316  *  0b00..PASS
65317  */
65318 #define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_MASK)
65319 #define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_MASK (0x6000000U)
65320 #define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_SHIFT (25U)
65321 /*! sw_config - output and input configuration
65322  *  0b01..OPEN_DRAIN
65323  *  0b10..OPEN_DRAIN_INPUT
65324  *  0b11..INOUT
65325  *  0b00..DEFAULT
65326  */
65327 #define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_MASK)
65328 #define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_MASK  (0x38000000U)
65329 #define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_SHIFT (27U)
65330 /*! mux_mode - mux_mode
65331  *  0b000..MIPI_CSI0.GPIO0.IO00
65332  *  0b001..ADMA.I2C0.SCL
65333  *  0b100..LSIO.GPIO3.IO08
65334  */
65335 #define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_MASK)
65336 #define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
65337 #define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_SHIFT (30U)
65338 /*! update_pad_ctl - update lock for pad control
65339  */
65340 #define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_MASK)
65341 #define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_MASK (0x80000000U)
65342 #define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_SHIFT (31U)
65343 /*! update_mux_mode - update lock for mux control
65344  */
65345 #define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_MASK)
65346 /*! @} */
65347 
65348 /*! @name IOMUXD_GROUP_2_4 - na */
65349 /*! @{ */
65350 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_MASK (0x1U)
65351 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_SHIFT (0U)
65352 /*! CSI_DIG_D06 - wakeup from CSI_DIG_D06
65353  */
65354 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_MASK)
65355 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_MASK (0x2U)
65356 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_SHIFT (1U)
65357 /*! CSI_DIG_D07 - wakeup from CSI_DIG_D07
65358  */
65359 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_MASK)
65360 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_MASK (0x4U)
65361 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_SHIFT (2U)
65362 /*! CSI_DIG_HSYNC - wakeup from CSI_DIG_HSYNC
65363  */
65364 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_MASK)
65365 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_MASK (0x8U)
65366 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_SHIFT (3U)
65367 /*! CSI_DIG_VSYNC - wakeup from CSI_DIG_VSYNC
65368  */
65369 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_MASK)
65370 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_MASK    (0x10U)
65371 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_SHIFT   (4U)
65372 /*! CSI_PCLK - wakeup from CSI_PCLK
65373  */
65374 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_MASK)
65375 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_MASK    (0x20U)
65376 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_SHIFT   (5U)
65377 /*! CSI_MCLK - wakeup from CSI_MCLK
65378  */
65379 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_MASK)
65380 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_MASK      (0x40U)
65381 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_SHIFT     (6U)
65382 /*! CSI_EN - wakeup from CSI_EN
65383  */
65384 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_EN(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_MASK)
65385 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_MASK   (0x80U)
65386 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_SHIFT  (7U)
65387 /*! CSI_RESET - wakeup from CSI_RESET
65388  */
65389 #define IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_MASK)
65390 #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_MASK (0x100U)
65391 #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_SHIFT (8U)
65392 /*! iomuxd_group_2_4_reserved_8_8 - reserved
65393  */
65394 #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_MASK)
65395 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_MASK (0x200U)
65396 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_SHIFT (9U)
65397 /*! MIPI_CSI0_MCLK_OUT - wakeup from MIPI_CSI0_MCLK_OUT
65398  */
65399 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_MASK)
65400 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_MASK (0x400U)
65401 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_SHIFT (10U)
65402 /*! MIPI_CSI0_I2C0_SCL - wakeup from MIPI_CSI0_I2C0_SCL
65403  */
65404 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_MASK)
65405 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_MASK (0x800U)
65406 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_SHIFT (11U)
65407 /*! MIPI_CSI0_I2C0_SDA - wakeup from MIPI_CSI0_I2C0_SDA
65408  */
65409 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_MASK)
65410 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_MASK (0x1000U)
65411 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_SHIFT (12U)
65412 /*! MIPI_CSI0_GPIO0_01 - wakeup from MIPI_CSI0_GPIO0_01
65413  */
65414 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_MASK)
65415 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_MASK (0x2000U)
65416 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_SHIFT (13U)
65417 /*! MIPI_CSI0_GPIO0_00 - wakeup from MIPI_CSI0_GPIO0_00
65418  */
65419 #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_MASK)
65420 #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_MASK (0xFFFFC000U)
65421 #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_SHIFT (14U)
65422 /*! iomuxd_group_2_4_reserved_14_31 - reserved
65423  */
65424 #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_MASK)
65425 /*! @} */
65426 
65427 /*! @name QSPI0A_DATA0 - QSPI0A_DATA0 */
65428 /*! @{ */
65429 #define IOMUXD_QSPI0A_DATA0_PDRV_MASK            (0x1U)
65430 #define IOMUXD_QSPI0A_DATA0_PDRV_SHIFT           (0U)
65431 /*! PDRV - Drive
65432  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65433  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65434  */
65435 #define IOMUXD_QSPI0A_DATA0_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA0_PDRV_MASK)
65436 #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_MASK (0x1EU)
65437 #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_SHIFT (1U)
65438 /*! QSPI0A_DATA0_reserved_1_4 - reserved
65439  */
65440 #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_MASK)
65441 #define IOMUXD_QSPI0A_DATA0_PULL_MASK            (0x60U)
65442 #define IOMUXD_QSPI0A_DATA0_PULL_SHIFT           (5U)
65443 /*! PULL - Pull Down Pull Up
65444  *  0b10..pull down
65445  *  0b01..pull up
65446  *  0b00..Prohibited
65447  *  0b11..pull disabled
65448  */
65449 #define IOMUXD_QSPI0A_DATA0_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA0_PULL_MASK)
65450 #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_MASK (0x7FF80U)
65451 #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_SHIFT (7U)
65452 /*! QSPI0A_DATA0_reserved_7_18 - reserved
65453  */
65454 #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_MASK)
65455 #define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_MASK     (0x380000U)
65456 #define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_SHIFT    (19U)
65457 /*! WAKEUP_CTRL - wakeup control
65458  *  0b000..OFF
65459  *  0b001..RESAMPLE
65460  *  0b100..LOW
65461  *  0b111..HIGH
65462  *  0b110..RISE
65463  *  0b101..FALL
65464  */
65465 #define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_MASK)
65466 #define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_MASK     (0x400000U)
65467 #define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_SHIFT    (22U)
65468 /*! WAKEUP_MASK - wakeup mask
65469  */
65470 #define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_MASK)
65471 #define IOMUXD_QSPI0A_DATA0_lp_config_MASK       (0x1800000U)
65472 #define IOMUXD_QSPI0A_DATA0_lp_config_SHIFT      (23U)
65473 /*! lp_config - lower power configuration
65474  *  0b01..EARLY_ISO
65475  *  0b10..LATE_ISO
65476  *  0b11..LATCH
65477  *  0b00..PASS
65478  */
65479 #define IOMUXD_QSPI0A_DATA0_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA0_lp_config_MASK)
65480 #define IOMUXD_QSPI0A_DATA0_sw_config_MASK       (0x6000000U)
65481 #define IOMUXD_QSPI0A_DATA0_sw_config_SHIFT      (25U)
65482 /*! sw_config - output and input configuration
65483  *  0b01..OPEN_DRAIN
65484  *  0b10..OPEN_DRAIN_INPUT
65485  *  0b11..INOUT
65486  *  0b00..DEFAULT
65487  */
65488 #define IOMUXD_QSPI0A_DATA0_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA0_sw_config_MASK)
65489 #define IOMUXD_QSPI0A_DATA0_mux_mode_MASK        (0x38000000U)
65490 #define IOMUXD_QSPI0A_DATA0_mux_mode_SHIFT       (27U)
65491 /*! mux_mode - mux_mode
65492  *  0b000..LSIO.QSPI0A.DATA0
65493  *  0b100..LSIO.GPIO3.IO09
65494  */
65495 #define IOMUXD_QSPI0A_DATA0_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA0_mux_mode_MASK)
65496 #define IOMUXD_QSPI0A_DATA0_update_pad_ctl_MASK  (0x40000000U)
65497 #define IOMUXD_QSPI0A_DATA0_update_pad_ctl_SHIFT (30U)
65498 /*! update_pad_ctl - update lock for pad control
65499  */
65500 #define IOMUXD_QSPI0A_DATA0_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA0_update_pad_ctl_MASK)
65501 #define IOMUXD_QSPI0A_DATA0_update_mux_mode_MASK (0x80000000U)
65502 #define IOMUXD_QSPI0A_DATA0_update_mux_mode_SHIFT (31U)
65503 /*! update_mux_mode - update lock for mux control
65504  */
65505 #define IOMUXD_QSPI0A_DATA0_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA0_update_mux_mode_MASK)
65506 /*! @} */
65507 
65508 /*! @name QSPI0A_DATA1 - QSPI0A_DATA1 */
65509 /*! @{ */
65510 #define IOMUXD_QSPI0A_DATA1_PDRV_MASK            (0x1U)
65511 #define IOMUXD_QSPI0A_DATA1_PDRV_SHIFT           (0U)
65512 /*! PDRV - Drive
65513  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65514  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65515  */
65516 #define IOMUXD_QSPI0A_DATA1_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA1_PDRV_MASK)
65517 #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_MASK (0x1EU)
65518 #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_SHIFT (1U)
65519 /*! QSPI0A_DATA1_reserved_1_4 - reserved
65520  */
65521 #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_MASK)
65522 #define IOMUXD_QSPI0A_DATA1_PULL_MASK            (0x60U)
65523 #define IOMUXD_QSPI0A_DATA1_PULL_SHIFT           (5U)
65524 /*! PULL - Pull Down Pull Up
65525  *  0b10..pull down
65526  *  0b01..pull up
65527  *  0b00..Prohibited
65528  *  0b11..pull disabled
65529  */
65530 #define IOMUXD_QSPI0A_DATA1_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA1_PULL_MASK)
65531 #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_MASK (0x7FF80U)
65532 #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_SHIFT (7U)
65533 /*! QSPI0A_DATA1_reserved_7_18 - reserved
65534  */
65535 #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_MASK)
65536 #define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_MASK     (0x380000U)
65537 #define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_SHIFT    (19U)
65538 /*! WAKEUP_CTRL - wakeup control
65539  *  0b000..OFF
65540  *  0b001..RESAMPLE
65541  *  0b100..LOW
65542  *  0b111..HIGH
65543  *  0b110..RISE
65544  *  0b101..FALL
65545  */
65546 #define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_MASK)
65547 #define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_MASK     (0x400000U)
65548 #define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_SHIFT    (22U)
65549 /*! WAKEUP_MASK - wakeup mask
65550  */
65551 #define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_MASK)
65552 #define IOMUXD_QSPI0A_DATA1_lp_config_MASK       (0x1800000U)
65553 #define IOMUXD_QSPI0A_DATA1_lp_config_SHIFT      (23U)
65554 /*! lp_config - lower power configuration
65555  *  0b01..EARLY_ISO
65556  *  0b10..LATE_ISO
65557  *  0b11..LATCH
65558  *  0b00..PASS
65559  */
65560 #define IOMUXD_QSPI0A_DATA1_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA1_lp_config_MASK)
65561 #define IOMUXD_QSPI0A_DATA1_sw_config_MASK       (0x6000000U)
65562 #define IOMUXD_QSPI0A_DATA1_sw_config_SHIFT      (25U)
65563 /*! sw_config - output and input configuration
65564  *  0b01..OPEN_DRAIN
65565  *  0b10..OPEN_DRAIN_INPUT
65566  *  0b11..INOUT
65567  *  0b00..DEFAULT
65568  */
65569 #define IOMUXD_QSPI0A_DATA1_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA1_sw_config_MASK)
65570 #define IOMUXD_QSPI0A_DATA1_mux_mode_MASK        (0x38000000U)
65571 #define IOMUXD_QSPI0A_DATA1_mux_mode_SHIFT       (27U)
65572 /*! mux_mode - mux_mode
65573  *  0b000..LSIO.QSPI0A.DATA1
65574  *  0b100..LSIO.GPIO3.IO10
65575  */
65576 #define IOMUXD_QSPI0A_DATA1_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA1_mux_mode_MASK)
65577 #define IOMUXD_QSPI0A_DATA1_update_pad_ctl_MASK  (0x40000000U)
65578 #define IOMUXD_QSPI0A_DATA1_update_pad_ctl_SHIFT (30U)
65579 /*! update_pad_ctl - update lock for pad control
65580  */
65581 #define IOMUXD_QSPI0A_DATA1_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA1_update_pad_ctl_MASK)
65582 #define IOMUXD_QSPI0A_DATA1_update_mux_mode_MASK (0x80000000U)
65583 #define IOMUXD_QSPI0A_DATA1_update_mux_mode_SHIFT (31U)
65584 /*! update_mux_mode - update lock for mux control
65585  */
65586 #define IOMUXD_QSPI0A_DATA1_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA1_update_mux_mode_MASK)
65587 /*! @} */
65588 
65589 /*! @name QSPI0A_DATA2 - QSPI0A_DATA2 */
65590 /*! @{ */
65591 #define IOMUXD_QSPI0A_DATA2_PDRV_MASK            (0x1U)
65592 #define IOMUXD_QSPI0A_DATA2_PDRV_SHIFT           (0U)
65593 /*! PDRV - Drive
65594  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65595  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65596  */
65597 #define IOMUXD_QSPI0A_DATA2_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA2_PDRV_MASK)
65598 #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_MASK (0x1EU)
65599 #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_SHIFT (1U)
65600 /*! QSPI0A_DATA2_reserved_1_4 - reserved
65601  */
65602 #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_MASK)
65603 #define IOMUXD_QSPI0A_DATA2_PULL_MASK            (0x60U)
65604 #define IOMUXD_QSPI0A_DATA2_PULL_SHIFT           (5U)
65605 /*! PULL - Pull Down Pull Up
65606  *  0b10..pull down
65607  *  0b01..pull up
65608  *  0b00..Prohibited
65609  *  0b11..pull disabled
65610  */
65611 #define IOMUXD_QSPI0A_DATA2_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA2_PULL_MASK)
65612 #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_MASK (0x7FF80U)
65613 #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_SHIFT (7U)
65614 /*! QSPI0A_DATA2_reserved_7_18 - reserved
65615  */
65616 #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_MASK)
65617 #define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_MASK     (0x380000U)
65618 #define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_SHIFT    (19U)
65619 /*! WAKEUP_CTRL - wakeup control
65620  *  0b000..OFF
65621  *  0b001..RESAMPLE
65622  *  0b100..LOW
65623  *  0b111..HIGH
65624  *  0b110..RISE
65625  *  0b101..FALL
65626  */
65627 #define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_MASK)
65628 #define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_MASK     (0x400000U)
65629 #define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_SHIFT    (22U)
65630 /*! WAKEUP_MASK - wakeup mask
65631  */
65632 #define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_MASK)
65633 #define IOMUXD_QSPI0A_DATA2_lp_config_MASK       (0x1800000U)
65634 #define IOMUXD_QSPI0A_DATA2_lp_config_SHIFT      (23U)
65635 /*! lp_config - lower power configuration
65636  *  0b01..EARLY_ISO
65637  *  0b10..LATE_ISO
65638  *  0b11..LATCH
65639  *  0b00..PASS
65640  */
65641 #define IOMUXD_QSPI0A_DATA2_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA2_lp_config_MASK)
65642 #define IOMUXD_QSPI0A_DATA2_sw_config_MASK       (0x6000000U)
65643 #define IOMUXD_QSPI0A_DATA2_sw_config_SHIFT      (25U)
65644 /*! sw_config - output and input configuration
65645  *  0b01..OPEN_DRAIN
65646  *  0b10..OPEN_DRAIN_INPUT
65647  *  0b11..INOUT
65648  *  0b00..DEFAULT
65649  */
65650 #define IOMUXD_QSPI0A_DATA2_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA2_sw_config_MASK)
65651 #define IOMUXD_QSPI0A_DATA2_mux_mode_MASK        (0x38000000U)
65652 #define IOMUXD_QSPI0A_DATA2_mux_mode_SHIFT       (27U)
65653 /*! mux_mode - mux_mode
65654  *  0b000..LSIO.QSPI0A.DATA2
65655  *  0b100..LSIO.GPIO3.IO11
65656  */
65657 #define IOMUXD_QSPI0A_DATA2_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA2_mux_mode_MASK)
65658 #define IOMUXD_QSPI0A_DATA2_update_pad_ctl_MASK  (0x40000000U)
65659 #define IOMUXD_QSPI0A_DATA2_update_pad_ctl_SHIFT (30U)
65660 /*! update_pad_ctl - update lock for pad control
65661  */
65662 #define IOMUXD_QSPI0A_DATA2_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA2_update_pad_ctl_MASK)
65663 #define IOMUXD_QSPI0A_DATA2_update_mux_mode_MASK (0x80000000U)
65664 #define IOMUXD_QSPI0A_DATA2_update_mux_mode_SHIFT (31U)
65665 /*! update_mux_mode - update lock for mux control
65666  */
65667 #define IOMUXD_QSPI0A_DATA2_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA2_update_mux_mode_MASK)
65668 /*! @} */
65669 
65670 /*! @name QSPI0A_DATA3 - QSPI0A_DATA3 */
65671 /*! @{ */
65672 #define IOMUXD_QSPI0A_DATA3_PDRV_MASK            (0x1U)
65673 #define IOMUXD_QSPI0A_DATA3_PDRV_SHIFT           (0U)
65674 /*! PDRV - Drive
65675  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65676  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65677  */
65678 #define IOMUXD_QSPI0A_DATA3_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA3_PDRV_MASK)
65679 #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_MASK (0x1EU)
65680 #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_SHIFT (1U)
65681 /*! QSPI0A_DATA3_reserved_1_4 - reserved
65682  */
65683 #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_MASK)
65684 #define IOMUXD_QSPI0A_DATA3_PULL_MASK            (0x60U)
65685 #define IOMUXD_QSPI0A_DATA3_PULL_SHIFT           (5U)
65686 /*! PULL - Pull Down Pull Up
65687  *  0b10..pull down
65688  *  0b01..pull up
65689  *  0b00..Prohibited
65690  *  0b11..pull disabled
65691  */
65692 #define IOMUXD_QSPI0A_DATA3_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA3_PULL_MASK)
65693 #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_MASK (0x7FF80U)
65694 #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_SHIFT (7U)
65695 /*! QSPI0A_DATA3_reserved_7_18 - reserved
65696  */
65697 #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_MASK)
65698 #define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_MASK     (0x380000U)
65699 #define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_SHIFT    (19U)
65700 /*! WAKEUP_CTRL - wakeup control
65701  *  0b000..OFF
65702  *  0b001..RESAMPLE
65703  *  0b100..LOW
65704  *  0b111..HIGH
65705  *  0b110..RISE
65706  *  0b101..FALL
65707  */
65708 #define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_MASK)
65709 #define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_MASK     (0x400000U)
65710 #define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_SHIFT    (22U)
65711 /*! WAKEUP_MASK - wakeup mask
65712  */
65713 #define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_MASK)
65714 #define IOMUXD_QSPI0A_DATA3_lp_config_MASK       (0x1800000U)
65715 #define IOMUXD_QSPI0A_DATA3_lp_config_SHIFT      (23U)
65716 /*! lp_config - lower power configuration
65717  *  0b01..EARLY_ISO
65718  *  0b10..LATE_ISO
65719  *  0b11..LATCH
65720  *  0b00..PASS
65721  */
65722 #define IOMUXD_QSPI0A_DATA3_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA3_lp_config_MASK)
65723 #define IOMUXD_QSPI0A_DATA3_sw_config_MASK       (0x6000000U)
65724 #define IOMUXD_QSPI0A_DATA3_sw_config_SHIFT      (25U)
65725 /*! sw_config - output and input configuration
65726  *  0b01..OPEN_DRAIN
65727  *  0b10..OPEN_DRAIN_INPUT
65728  *  0b11..INOUT
65729  *  0b00..DEFAULT
65730  */
65731 #define IOMUXD_QSPI0A_DATA3_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA3_sw_config_MASK)
65732 #define IOMUXD_QSPI0A_DATA3_mux_mode_MASK        (0x38000000U)
65733 #define IOMUXD_QSPI0A_DATA3_mux_mode_SHIFT       (27U)
65734 /*! mux_mode - mux_mode
65735  *  0b000..LSIO.QSPI0A.DATA3
65736  *  0b100..LSIO.GPIO3.IO12
65737  */
65738 #define IOMUXD_QSPI0A_DATA3_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA3_mux_mode_MASK)
65739 #define IOMUXD_QSPI0A_DATA3_update_pad_ctl_MASK  (0x40000000U)
65740 #define IOMUXD_QSPI0A_DATA3_update_pad_ctl_SHIFT (30U)
65741 /*! update_pad_ctl - update lock for pad control
65742  */
65743 #define IOMUXD_QSPI0A_DATA3_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA3_update_pad_ctl_MASK)
65744 #define IOMUXD_QSPI0A_DATA3_update_mux_mode_MASK (0x80000000U)
65745 #define IOMUXD_QSPI0A_DATA3_update_mux_mode_SHIFT (31U)
65746 /*! update_mux_mode - update lock for mux control
65747  */
65748 #define IOMUXD_QSPI0A_DATA3_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA3_update_mux_mode_MASK)
65749 /*! @} */
65750 
65751 /*! @name QSPI0A_DQS - QSPI0A_DQS */
65752 /*! @{ */
65753 #define IOMUXD_QSPI0A_DQS_PDRV_MASK              (0x1U)
65754 #define IOMUXD_QSPI0A_DQS_PDRV_SHIFT             (0U)
65755 /*! PDRV - Drive
65756  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65757  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65758  */
65759 #define IOMUXD_QSPI0A_DQS_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_PDRV_SHIFT)) & IOMUXD_QSPI0A_DQS_PDRV_MASK)
65760 #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_MASK (0x1EU)
65761 #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_SHIFT (1U)
65762 /*! QSPI0A_DQS_reserved_1_4 - reserved
65763  */
65764 #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_MASK)
65765 #define IOMUXD_QSPI0A_DQS_PULL_MASK              (0x60U)
65766 #define IOMUXD_QSPI0A_DQS_PULL_SHIFT             (5U)
65767 /*! PULL - Pull Down Pull Up
65768  *  0b10..pull down
65769  *  0b01..pull up
65770  *  0b00..Prohibited
65771  *  0b11..pull disabled
65772  */
65773 #define IOMUXD_QSPI0A_DQS_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_PULL_SHIFT)) & IOMUXD_QSPI0A_DQS_PULL_MASK)
65774 #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_MASK (0x7FF80U)
65775 #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_SHIFT (7U)
65776 /*! QSPI0A_DQS_reserved_7_18 - reserved
65777  */
65778 #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_MASK)
65779 #define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_MASK       (0x380000U)
65780 #define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_SHIFT      (19U)
65781 /*! WAKEUP_CTRL - wakeup control
65782  *  0b000..OFF
65783  *  0b001..RESAMPLE
65784  *  0b100..LOW
65785  *  0b111..HIGH
65786  *  0b110..RISE
65787  *  0b101..FALL
65788  */
65789 #define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_MASK)
65790 #define IOMUXD_QSPI0A_DQS_WAKEUP_MASK_MASK       (0x400000U)
65791 #define IOMUXD_QSPI0A_DQS_WAKEUP_MASK_SHIFT      (22U)
65792 /*! WAKEUP_MASK - wakeup mask
65793  */
65794 #define IOMUXD_QSPI0A_DQS_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DQS_WAKEUP_MASK_MASK)
65795 #define IOMUXD_QSPI0A_DQS_lp_config_MASK         (0x1800000U)
65796 #define IOMUXD_QSPI0A_DQS_lp_config_SHIFT        (23U)
65797 /*! lp_config - lower power configuration
65798  *  0b01..EARLY_ISO
65799  *  0b10..LATE_ISO
65800  *  0b11..LATCH
65801  *  0b00..PASS
65802  */
65803 #define IOMUXD_QSPI0A_DQS_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_lp_config_SHIFT)) & IOMUXD_QSPI0A_DQS_lp_config_MASK)
65804 #define IOMUXD_QSPI0A_DQS_sw_config_MASK         (0x6000000U)
65805 #define IOMUXD_QSPI0A_DQS_sw_config_SHIFT        (25U)
65806 /*! sw_config - output and input configuration
65807  *  0b01..OPEN_DRAIN
65808  *  0b10..OPEN_DRAIN_INPUT
65809  *  0b11..INOUT
65810  *  0b00..DEFAULT
65811  */
65812 #define IOMUXD_QSPI0A_DQS_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_sw_config_SHIFT)) & IOMUXD_QSPI0A_DQS_sw_config_MASK)
65813 #define IOMUXD_QSPI0A_DQS_mux_mode_MASK          (0x38000000U)
65814 #define IOMUXD_QSPI0A_DQS_mux_mode_SHIFT         (27U)
65815 /*! mux_mode - mux_mode
65816  *  0b000..LSIO.QSPI0A.DQS
65817  *  0b100..LSIO.GPIO3.IO13
65818  */
65819 #define IOMUXD_QSPI0A_DQS_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DQS_mux_mode_MASK)
65820 #define IOMUXD_QSPI0A_DQS_update_pad_ctl_MASK    (0x40000000U)
65821 #define IOMUXD_QSPI0A_DQS_update_pad_ctl_SHIFT   (30U)
65822 /*! update_pad_ctl - update lock for pad control
65823  */
65824 #define IOMUXD_QSPI0A_DQS_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DQS_update_pad_ctl_MASK)
65825 #define IOMUXD_QSPI0A_DQS_update_mux_mode_MASK   (0x80000000U)
65826 #define IOMUXD_QSPI0A_DQS_update_mux_mode_SHIFT  (31U)
65827 /*! update_mux_mode - update lock for mux control
65828  */
65829 #define IOMUXD_QSPI0A_DQS_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DQS_update_mux_mode_MASK)
65830 /*! @} */
65831 
65832 /*! @name QSPI0A_SS0_B - QSPI0A_SS0_B */
65833 /*! @{ */
65834 #define IOMUXD_QSPI0A_SS0_B_PDRV_MASK            (0x1U)
65835 #define IOMUXD_QSPI0A_SS0_B_PDRV_SHIFT           (0U)
65836 /*! PDRV - Drive
65837  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65838  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65839  */
65840 #define IOMUXD_QSPI0A_SS0_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_PDRV_SHIFT)) & IOMUXD_QSPI0A_SS0_B_PDRV_MASK)
65841 #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_MASK (0x1EU)
65842 #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_SHIFT (1U)
65843 /*! QSPI0A_SS0_B_reserved_1_4 - reserved
65844  */
65845 #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_MASK)
65846 #define IOMUXD_QSPI0A_SS0_B_PULL_MASK            (0x60U)
65847 #define IOMUXD_QSPI0A_SS0_B_PULL_SHIFT           (5U)
65848 /*! PULL - Pull Down Pull Up
65849  *  0b10..pull down
65850  *  0b01..pull up
65851  *  0b00..Prohibited
65852  *  0b11..pull disabled
65853  */
65854 #define IOMUXD_QSPI0A_SS0_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_PULL_SHIFT)) & IOMUXD_QSPI0A_SS0_B_PULL_MASK)
65855 #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_MASK (0x7FF80U)
65856 #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_SHIFT (7U)
65857 /*! QSPI0A_SS0_B_reserved_7_18 - reserved
65858  */
65859 #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_MASK)
65860 #define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_MASK     (0x380000U)
65861 #define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_SHIFT    (19U)
65862 /*! WAKEUP_CTRL - wakeup control
65863  *  0b000..OFF
65864  *  0b001..RESAMPLE
65865  *  0b100..LOW
65866  *  0b111..HIGH
65867  *  0b110..RISE
65868  *  0b101..FALL
65869  */
65870 #define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_MASK)
65871 #define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_MASK     (0x400000U)
65872 #define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_SHIFT    (22U)
65873 /*! WAKEUP_MASK - wakeup mask
65874  */
65875 #define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_MASK)
65876 #define IOMUXD_QSPI0A_SS0_B_lp_config_MASK       (0x1800000U)
65877 #define IOMUXD_QSPI0A_SS0_B_lp_config_SHIFT      (23U)
65878 /*! lp_config - lower power configuration
65879  *  0b01..EARLY_ISO
65880  *  0b10..LATE_ISO
65881  *  0b11..LATCH
65882  *  0b00..PASS
65883  */
65884 #define IOMUXD_QSPI0A_SS0_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_lp_config_SHIFT)) & IOMUXD_QSPI0A_SS0_B_lp_config_MASK)
65885 #define IOMUXD_QSPI0A_SS0_B_sw_config_MASK       (0x6000000U)
65886 #define IOMUXD_QSPI0A_SS0_B_sw_config_SHIFT      (25U)
65887 /*! sw_config - output and input configuration
65888  *  0b01..OPEN_DRAIN
65889  *  0b10..OPEN_DRAIN_INPUT
65890  *  0b11..INOUT
65891  *  0b00..DEFAULT
65892  */
65893 #define IOMUXD_QSPI0A_SS0_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_sw_config_SHIFT)) & IOMUXD_QSPI0A_SS0_B_sw_config_MASK)
65894 #define IOMUXD_QSPI0A_SS0_B_mux_mode_MASK        (0x38000000U)
65895 #define IOMUXD_QSPI0A_SS0_B_mux_mode_SHIFT       (27U)
65896 /*! mux_mode - mux_mode
65897  *  0b000..LSIO.QSPI0A.SS0_B
65898  *  0b100..LSIO.GPIO3.IO14
65899  */
65900 #define IOMUXD_QSPI0A_SS0_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS0_B_mux_mode_MASK)
65901 #define IOMUXD_QSPI0A_SS0_B_update_pad_ctl_MASK  (0x40000000U)
65902 #define IOMUXD_QSPI0A_SS0_B_update_pad_ctl_SHIFT (30U)
65903 /*! update_pad_ctl - update lock for pad control
65904  */
65905 #define IOMUXD_QSPI0A_SS0_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SS0_B_update_pad_ctl_MASK)
65906 #define IOMUXD_QSPI0A_SS0_B_update_mux_mode_MASK (0x80000000U)
65907 #define IOMUXD_QSPI0A_SS0_B_update_mux_mode_SHIFT (31U)
65908 /*! update_mux_mode - update lock for mux control
65909  */
65910 #define IOMUXD_QSPI0A_SS0_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS0_B_update_mux_mode_MASK)
65911 /*! @} */
65912 
65913 /*! @name QSPI0A_SS1_B - QSPI0A_SS1_B */
65914 /*! @{ */
65915 #define IOMUXD_QSPI0A_SS1_B_PDRV_MASK            (0x1U)
65916 #define IOMUXD_QSPI0A_SS1_B_PDRV_SHIFT           (0U)
65917 /*! PDRV - Drive
65918  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65919  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65920  */
65921 #define IOMUXD_QSPI0A_SS1_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI0A_SS1_B_PDRV_MASK)
65922 #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_MASK (0x1EU)
65923 #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_SHIFT (1U)
65924 /*! QSPI0A_SS1_B_reserved_1_4 - reserved
65925  */
65926 #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_MASK)
65927 #define IOMUXD_QSPI0A_SS1_B_PULL_MASK            (0x60U)
65928 #define IOMUXD_QSPI0A_SS1_B_PULL_SHIFT           (5U)
65929 /*! PULL - Pull Down Pull Up
65930  *  0b10..pull down
65931  *  0b01..pull up
65932  *  0b00..Prohibited
65933  *  0b11..pull disabled
65934  */
65935 #define IOMUXD_QSPI0A_SS1_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_PULL_SHIFT)) & IOMUXD_QSPI0A_SS1_B_PULL_MASK)
65936 #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_MASK (0x7FF80U)
65937 #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_SHIFT (7U)
65938 /*! QSPI0A_SS1_B_reserved_7_18 - reserved
65939  */
65940 #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_MASK)
65941 #define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_MASK     (0x380000U)
65942 #define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_SHIFT    (19U)
65943 /*! WAKEUP_CTRL - wakeup control
65944  *  0b000..OFF
65945  *  0b001..RESAMPLE
65946  *  0b100..LOW
65947  *  0b111..HIGH
65948  *  0b110..RISE
65949  *  0b101..FALL
65950  */
65951 #define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_MASK)
65952 #define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_MASK     (0x400000U)
65953 #define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_SHIFT    (22U)
65954 /*! WAKEUP_MASK - wakeup mask
65955  */
65956 #define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_MASK)
65957 #define IOMUXD_QSPI0A_SS1_B_lp_config_MASK       (0x1800000U)
65958 #define IOMUXD_QSPI0A_SS1_B_lp_config_SHIFT      (23U)
65959 /*! lp_config - lower power configuration
65960  *  0b01..EARLY_ISO
65961  *  0b10..LATE_ISO
65962  *  0b11..LATCH
65963  *  0b00..PASS
65964  */
65965 #define IOMUXD_QSPI0A_SS1_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_lp_config_SHIFT)) & IOMUXD_QSPI0A_SS1_B_lp_config_MASK)
65966 #define IOMUXD_QSPI0A_SS1_B_sw_config_MASK       (0x6000000U)
65967 #define IOMUXD_QSPI0A_SS1_B_sw_config_SHIFT      (25U)
65968 /*! sw_config - output and input configuration
65969  *  0b01..OPEN_DRAIN
65970  *  0b10..OPEN_DRAIN_INPUT
65971  *  0b11..INOUT
65972  *  0b00..DEFAULT
65973  */
65974 #define IOMUXD_QSPI0A_SS1_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_sw_config_SHIFT)) & IOMUXD_QSPI0A_SS1_B_sw_config_MASK)
65975 #define IOMUXD_QSPI0A_SS1_B_mux_mode_MASK        (0x38000000U)
65976 #define IOMUXD_QSPI0A_SS1_B_mux_mode_SHIFT       (27U)
65977 /*! mux_mode - mux_mode
65978  *  0b000..LSIO.QSPI0A.SS1_B
65979  *  0b100..LSIO.GPIO3.IO15
65980  */
65981 #define IOMUXD_QSPI0A_SS1_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS1_B_mux_mode_MASK)
65982 #define IOMUXD_QSPI0A_SS1_B_update_pad_ctl_MASK  (0x40000000U)
65983 #define IOMUXD_QSPI0A_SS1_B_update_pad_ctl_SHIFT (30U)
65984 /*! update_pad_ctl - update lock for pad control
65985  */
65986 #define IOMUXD_QSPI0A_SS1_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SS1_B_update_pad_ctl_MASK)
65987 #define IOMUXD_QSPI0A_SS1_B_update_mux_mode_MASK (0x80000000U)
65988 #define IOMUXD_QSPI0A_SS1_B_update_mux_mode_SHIFT (31U)
65989 /*! update_mux_mode - update lock for mux control
65990  */
65991 #define IOMUXD_QSPI0A_SS1_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS1_B_update_mux_mode_MASK)
65992 /*! @} */
65993 
65994 /*! @name QSPI0A_SCLK - QSPI0A_SCLK */
65995 /*! @{ */
65996 #define IOMUXD_QSPI0A_SCLK_PDRV_MASK             (0x1U)
65997 #define IOMUXD_QSPI0A_SCLK_PDRV_SHIFT            (0U)
65998 /*! PDRV - Drive
65999  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66000  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66001  */
66002 #define IOMUXD_QSPI0A_SCLK_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_PDRV_SHIFT)) & IOMUXD_QSPI0A_SCLK_PDRV_MASK)
66003 #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_MASK (0x1EU)
66004 #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_SHIFT (1U)
66005 /*! QSPI0A_SCLK_reserved_1_4 - reserved
66006  */
66007 #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_MASK)
66008 #define IOMUXD_QSPI0A_SCLK_PULL_MASK             (0x60U)
66009 #define IOMUXD_QSPI0A_SCLK_PULL_SHIFT            (5U)
66010 /*! PULL - Pull Down Pull Up
66011  *  0b10..pull down
66012  *  0b01..pull up
66013  *  0b00..Prohibited
66014  *  0b11..pull disabled
66015  */
66016 #define IOMUXD_QSPI0A_SCLK_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_PULL_SHIFT)) & IOMUXD_QSPI0A_SCLK_PULL_MASK)
66017 #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_MASK (0x7FF80U)
66018 #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_SHIFT (7U)
66019 /*! QSPI0A_SCLK_reserved_7_18 - reserved
66020  */
66021 #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_MASK)
66022 #define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_MASK      (0x380000U)
66023 #define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_SHIFT     (19U)
66024 /*! WAKEUP_CTRL - wakeup control
66025  *  0b000..OFF
66026  *  0b001..RESAMPLE
66027  *  0b100..LOW
66028  *  0b111..HIGH
66029  *  0b110..RISE
66030  *  0b101..FALL
66031  */
66032 #define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_MASK)
66033 #define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_MASK      (0x400000U)
66034 #define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_SHIFT     (22U)
66035 /*! WAKEUP_MASK - wakeup mask
66036  */
66037 #define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_MASK)
66038 #define IOMUXD_QSPI0A_SCLK_lp_config_MASK        (0x1800000U)
66039 #define IOMUXD_QSPI0A_SCLK_lp_config_SHIFT       (23U)
66040 /*! lp_config - lower power configuration
66041  *  0b01..EARLY_ISO
66042  *  0b10..LATE_ISO
66043  *  0b11..LATCH
66044  *  0b00..PASS
66045  */
66046 #define IOMUXD_QSPI0A_SCLK_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_lp_config_SHIFT)) & IOMUXD_QSPI0A_SCLK_lp_config_MASK)
66047 #define IOMUXD_QSPI0A_SCLK_sw_config_MASK        (0x6000000U)
66048 #define IOMUXD_QSPI0A_SCLK_sw_config_SHIFT       (25U)
66049 /*! sw_config - output and input configuration
66050  *  0b01..OPEN_DRAIN
66051  *  0b10..OPEN_DRAIN_INPUT
66052  *  0b11..INOUT
66053  *  0b00..DEFAULT
66054  */
66055 #define IOMUXD_QSPI0A_SCLK_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_sw_config_SHIFT)) & IOMUXD_QSPI0A_SCLK_sw_config_MASK)
66056 #define IOMUXD_QSPI0A_SCLK_mux_mode_MASK         (0x38000000U)
66057 #define IOMUXD_QSPI0A_SCLK_mux_mode_SHIFT        (27U)
66058 /*! mux_mode - mux_mode
66059  *  0b000..LSIO.QSPI0A.SCLK
66060  *  0b100..LSIO.GPIO3.IO16
66061  */
66062 #define IOMUXD_QSPI0A_SCLK_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SCLK_mux_mode_MASK)
66063 #define IOMUXD_QSPI0A_SCLK_update_pad_ctl_MASK   (0x40000000U)
66064 #define IOMUXD_QSPI0A_SCLK_update_pad_ctl_SHIFT  (30U)
66065 /*! update_pad_ctl - update lock for pad control
66066  */
66067 #define IOMUXD_QSPI0A_SCLK_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SCLK_update_pad_ctl_MASK)
66068 #define IOMUXD_QSPI0A_SCLK_update_mux_mode_MASK  (0x80000000U)
66069 #define IOMUXD_QSPI0A_SCLK_update_mux_mode_SHIFT (31U)
66070 /*! update_mux_mode - update lock for mux control
66071  */
66072 #define IOMUXD_QSPI0A_SCLK_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SCLK_update_mux_mode_MASK)
66073 /*! @} */
66074 
66075 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A - IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A */
66076 /*! @{ */
66077 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_MASK (0x7U)
66078 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_SHIFT (0U)
66079 /*! COMP - COMP
66080  *  0b010..Fixed code mode
66081  *  0b100..High impedance mode
66082  *  0b110..Read mode
66083  *  0b000..Normal Mode
66084  *  0b001..Freeze Mode
66085  */
66086 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_MASK)
66087 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_MASK (0x8U)
66088 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_SHIFT (3U)
66089 /*! FASTFRZ_EN - FASTFRZ_EN
66090  *  0b1..FASTFRZ signal is driven by output of subsystem
66091  *  0b0..FASTFRZ signal is gated to 0
66092  */
66093 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_MASK)
66094 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_MASK (0x10U)
66095 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_SHIFT (4U)
66096 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4 - reserved
66097  */
66098 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_MASK)
66099 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_MASK (0x1E0U)
66100 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_SHIFT (5U)
66101 /*! RASRCP - RASRCP
66102  *  0b0101..Reset Value
66103  */
66104 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_MASK)
66105 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_MASK (0x1E00U)
66106 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_SHIFT (9U)
66107 /*! RASRCN - RASRCN
66108  *  0b1010..Reset Value
66109  */
66110 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_MASK)
66111 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_MASK (0x2000U)
66112 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_SHIFT (13U)
66113 /*! SELECT_NASRC - SELECT_NASRC
66114  *  0b1..NASRCN value
66115  *  0b0..NASRCP value
66116  */
66117 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_MASK)
66118 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_MASK (0x4000U)
66119 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_SHIFT (14U)
66120 /*! COMPOK - COMPOK
66121  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
66122  *  0b1..compensation cell in Normal mode and tracking PVT
66123  */
66124 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_MASK)
66125 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_MASK (0x78000U)
66126 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_SHIFT (15U)
66127 /*! READ_NASRC - READ_NASRC
66128  *  0b0000..READ Only
66129  */
66130 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_MASK)
66131 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_MASK (0x780000U)
66132 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_SHIFT (19U)
66133 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22 - reserved
66134  */
66135 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_MASK)
66136 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_MASK (0x1800000U)
66137 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_SHIFT (23U)
66138 /*! SLEEP - SLEEP
66139  *  0b11..Force into sleep mode
66140  *  0b00..NO
66141  *  0b01..EARLY
66142  *  0b10..LATE
66143  */
66144 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_MASK)
66145 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_MASK (0x3E000000U)
66146 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_SHIFT (25U)
66147 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29 - reserved
66148  */
66149 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_MASK)
66150 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_MASK (0x40000000U)
66151 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_SHIFT (30U)
66152 /*! update_pad_ctl - update lock for pad control
66153  */
66154 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_MASK)
66155 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_MASK (0x80000000U)
66156 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_SHIFT (31U)
66157 /*! update_mux_mode - update lock for mux control
66158  */
66159 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_MASK)
66160 /*! @} */
66161 
66162 /*! @name QSPI0B_SCLK - QSPI0B_SCLK */
66163 /*! @{ */
66164 #define IOMUXD_QSPI0B_SCLK_PDRV_MASK             (0x1U)
66165 #define IOMUXD_QSPI0B_SCLK_PDRV_SHIFT            (0U)
66166 /*! PDRV - Drive
66167  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66168  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66169  */
66170 #define IOMUXD_QSPI0B_SCLK_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_PDRV_SHIFT)) & IOMUXD_QSPI0B_SCLK_PDRV_MASK)
66171 #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_MASK (0x1EU)
66172 #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_SHIFT (1U)
66173 /*! QSPI0B_SCLK_reserved_1_4 - reserved
66174  */
66175 #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_MASK)
66176 #define IOMUXD_QSPI0B_SCLK_PULL_MASK             (0x60U)
66177 #define IOMUXD_QSPI0B_SCLK_PULL_SHIFT            (5U)
66178 /*! PULL - Pull Down Pull Up
66179  *  0b10..pull down
66180  *  0b01..pull up
66181  *  0b00..Prohibited
66182  *  0b11..pull disabled
66183  */
66184 #define IOMUXD_QSPI0B_SCLK_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_PULL_SHIFT)) & IOMUXD_QSPI0B_SCLK_PULL_MASK)
66185 #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_MASK (0x7FF80U)
66186 #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_SHIFT (7U)
66187 /*! QSPI0B_SCLK_reserved_7_18 - reserved
66188  */
66189 #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_MASK)
66190 #define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_MASK      (0x380000U)
66191 #define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_SHIFT     (19U)
66192 /*! WAKEUP_CTRL - wakeup control
66193  *  0b000..OFF
66194  *  0b001..RESAMPLE
66195  *  0b100..LOW
66196  *  0b111..HIGH
66197  *  0b110..RISE
66198  *  0b101..FALL
66199  */
66200 #define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_MASK)
66201 #define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_MASK      (0x400000U)
66202 #define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_SHIFT     (22U)
66203 /*! WAKEUP_MASK - wakeup mask
66204  */
66205 #define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_MASK)
66206 #define IOMUXD_QSPI0B_SCLK_lp_config_MASK        (0x1800000U)
66207 #define IOMUXD_QSPI0B_SCLK_lp_config_SHIFT       (23U)
66208 /*! lp_config - lower power configuration
66209  *  0b01..EARLY_ISO
66210  *  0b10..LATE_ISO
66211  *  0b11..LATCH
66212  *  0b00..PASS
66213  */
66214 #define IOMUXD_QSPI0B_SCLK_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_lp_config_SHIFT)) & IOMUXD_QSPI0B_SCLK_lp_config_MASK)
66215 #define IOMUXD_QSPI0B_SCLK_sw_config_MASK        (0x6000000U)
66216 #define IOMUXD_QSPI0B_SCLK_sw_config_SHIFT       (25U)
66217 /*! sw_config - output and input configuration
66218  *  0b01..OPEN_DRAIN
66219  *  0b10..OPEN_DRAIN_INPUT
66220  *  0b11..INOUT
66221  *  0b00..DEFAULT
66222  */
66223 #define IOMUXD_QSPI0B_SCLK_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_sw_config_SHIFT)) & IOMUXD_QSPI0B_SCLK_sw_config_MASK)
66224 #define IOMUXD_QSPI0B_SCLK_mux_mode_MASK         (0x38000000U)
66225 #define IOMUXD_QSPI0B_SCLK_mux_mode_SHIFT        (27U)
66226 /*! mux_mode - mux_mode
66227  *  0b000..LSIO.QSPI0B.SCLK
66228  *  0b001..LSIO.QSPI1A.SCLK
66229  *  0b010..LSIO.KPP0.COL0
66230  *  0b100..LSIO.GPIO3.IO17
66231  */
66232 #define IOMUXD_QSPI0B_SCLK_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SCLK_mux_mode_MASK)
66233 #define IOMUXD_QSPI0B_SCLK_update_pad_ctl_MASK   (0x40000000U)
66234 #define IOMUXD_QSPI0B_SCLK_update_pad_ctl_SHIFT  (30U)
66235 /*! update_pad_ctl - update lock for pad control
66236  */
66237 #define IOMUXD_QSPI0B_SCLK_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SCLK_update_pad_ctl_MASK)
66238 #define IOMUXD_QSPI0B_SCLK_update_mux_mode_MASK  (0x80000000U)
66239 #define IOMUXD_QSPI0B_SCLK_update_mux_mode_SHIFT (31U)
66240 /*! update_mux_mode - update lock for mux control
66241  */
66242 #define IOMUXD_QSPI0B_SCLK_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SCLK_update_mux_mode_MASK)
66243 /*! @} */
66244 
66245 /*! @name QSPI0B_DATA0 - QSPI0B_DATA0 */
66246 /*! @{ */
66247 #define IOMUXD_QSPI0B_DATA0_PDRV_MASK            (0x1U)
66248 #define IOMUXD_QSPI0B_DATA0_PDRV_SHIFT           (0U)
66249 /*! PDRV - Drive
66250  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66251  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66252  */
66253 #define IOMUXD_QSPI0B_DATA0_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA0_PDRV_MASK)
66254 #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_MASK (0x1EU)
66255 #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_SHIFT (1U)
66256 /*! QSPI0B_DATA0_reserved_1_4 - reserved
66257  */
66258 #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_MASK)
66259 #define IOMUXD_QSPI0B_DATA0_PULL_MASK            (0x60U)
66260 #define IOMUXD_QSPI0B_DATA0_PULL_SHIFT           (5U)
66261 /*! PULL - Pull Down Pull Up
66262  *  0b10..pull down
66263  *  0b01..pull up
66264  *  0b00..Prohibited
66265  *  0b11..pull disabled
66266  */
66267 #define IOMUXD_QSPI0B_DATA0_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA0_PULL_MASK)
66268 #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_MASK (0x7FF80U)
66269 #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_SHIFT (7U)
66270 /*! QSPI0B_DATA0_reserved_7_18 - reserved
66271  */
66272 #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_MASK)
66273 #define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_MASK     (0x380000U)
66274 #define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_SHIFT    (19U)
66275 /*! WAKEUP_CTRL - wakeup control
66276  *  0b000..OFF
66277  *  0b001..RESAMPLE
66278  *  0b100..LOW
66279  *  0b111..HIGH
66280  *  0b110..RISE
66281  *  0b101..FALL
66282  */
66283 #define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_MASK)
66284 #define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_MASK     (0x400000U)
66285 #define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_SHIFT    (22U)
66286 /*! WAKEUP_MASK - wakeup mask
66287  */
66288 #define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_MASK)
66289 #define IOMUXD_QSPI0B_DATA0_lp_config_MASK       (0x1800000U)
66290 #define IOMUXD_QSPI0B_DATA0_lp_config_SHIFT      (23U)
66291 /*! lp_config - lower power configuration
66292  *  0b01..EARLY_ISO
66293  *  0b10..LATE_ISO
66294  *  0b11..LATCH
66295  *  0b00..PASS
66296  */
66297 #define IOMUXD_QSPI0B_DATA0_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA0_lp_config_MASK)
66298 #define IOMUXD_QSPI0B_DATA0_sw_config_MASK       (0x6000000U)
66299 #define IOMUXD_QSPI0B_DATA0_sw_config_SHIFT      (25U)
66300 /*! sw_config - output and input configuration
66301  *  0b01..OPEN_DRAIN
66302  *  0b10..OPEN_DRAIN_INPUT
66303  *  0b11..INOUT
66304  *  0b00..DEFAULT
66305  */
66306 #define IOMUXD_QSPI0B_DATA0_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA0_sw_config_MASK)
66307 #define IOMUXD_QSPI0B_DATA0_mux_mode_MASK        (0x38000000U)
66308 #define IOMUXD_QSPI0B_DATA0_mux_mode_SHIFT       (27U)
66309 /*! mux_mode - mux_mode
66310  *  0b000..LSIO.QSPI0B.DATA0
66311  *  0b001..LSIO.QSPI1A.DATA0
66312  *  0b010..LSIO.KPP0.COL1
66313  *  0b100..LSIO.GPIO3.IO18
66314  */
66315 #define IOMUXD_QSPI0B_DATA0_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA0_mux_mode_MASK)
66316 #define IOMUXD_QSPI0B_DATA0_update_pad_ctl_MASK  (0x40000000U)
66317 #define IOMUXD_QSPI0B_DATA0_update_pad_ctl_SHIFT (30U)
66318 /*! update_pad_ctl - update lock for pad control
66319  */
66320 #define IOMUXD_QSPI0B_DATA0_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA0_update_pad_ctl_MASK)
66321 #define IOMUXD_QSPI0B_DATA0_update_mux_mode_MASK (0x80000000U)
66322 #define IOMUXD_QSPI0B_DATA0_update_mux_mode_SHIFT (31U)
66323 /*! update_mux_mode - update lock for mux control
66324  */
66325 #define IOMUXD_QSPI0B_DATA0_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA0_update_mux_mode_MASK)
66326 /*! @} */
66327 
66328 /*! @name QSPI0B_DATA1 - QSPI0B_DATA1 */
66329 /*! @{ */
66330 #define IOMUXD_QSPI0B_DATA1_PDRV_MASK            (0x1U)
66331 #define IOMUXD_QSPI0B_DATA1_PDRV_SHIFT           (0U)
66332 /*! PDRV - Drive
66333  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66334  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66335  */
66336 #define IOMUXD_QSPI0B_DATA1_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA1_PDRV_MASK)
66337 #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_MASK (0x1EU)
66338 #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_SHIFT (1U)
66339 /*! QSPI0B_DATA1_reserved_1_4 - reserved
66340  */
66341 #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_MASK)
66342 #define IOMUXD_QSPI0B_DATA1_PULL_MASK            (0x60U)
66343 #define IOMUXD_QSPI0B_DATA1_PULL_SHIFT           (5U)
66344 /*! PULL - Pull Down Pull Up
66345  *  0b10..pull down
66346  *  0b01..pull up
66347  *  0b00..Prohibited
66348  *  0b11..pull disabled
66349  */
66350 #define IOMUXD_QSPI0B_DATA1_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA1_PULL_MASK)
66351 #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_MASK (0x7FF80U)
66352 #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_SHIFT (7U)
66353 /*! QSPI0B_DATA1_reserved_7_18 - reserved
66354  */
66355 #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_MASK)
66356 #define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_MASK     (0x380000U)
66357 #define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_SHIFT    (19U)
66358 /*! WAKEUP_CTRL - wakeup control
66359  *  0b000..OFF
66360  *  0b001..RESAMPLE
66361  *  0b100..LOW
66362  *  0b111..HIGH
66363  *  0b110..RISE
66364  *  0b101..FALL
66365  */
66366 #define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_MASK)
66367 #define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_MASK     (0x400000U)
66368 #define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_SHIFT    (22U)
66369 /*! WAKEUP_MASK - wakeup mask
66370  */
66371 #define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_MASK)
66372 #define IOMUXD_QSPI0B_DATA1_lp_config_MASK       (0x1800000U)
66373 #define IOMUXD_QSPI0B_DATA1_lp_config_SHIFT      (23U)
66374 /*! lp_config - lower power configuration
66375  *  0b01..EARLY_ISO
66376  *  0b10..LATE_ISO
66377  *  0b11..LATCH
66378  *  0b00..PASS
66379  */
66380 #define IOMUXD_QSPI0B_DATA1_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA1_lp_config_MASK)
66381 #define IOMUXD_QSPI0B_DATA1_sw_config_MASK       (0x6000000U)
66382 #define IOMUXD_QSPI0B_DATA1_sw_config_SHIFT      (25U)
66383 /*! sw_config - output and input configuration
66384  *  0b01..OPEN_DRAIN
66385  *  0b10..OPEN_DRAIN_INPUT
66386  *  0b11..INOUT
66387  *  0b00..DEFAULT
66388  */
66389 #define IOMUXD_QSPI0B_DATA1_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA1_sw_config_MASK)
66390 #define IOMUXD_QSPI0B_DATA1_mux_mode_MASK        (0x38000000U)
66391 #define IOMUXD_QSPI0B_DATA1_mux_mode_SHIFT       (27U)
66392 /*! mux_mode - mux_mode
66393  *  0b000..LSIO.QSPI0B.DATA1
66394  *  0b001..LSIO.QSPI1A.DATA1
66395  *  0b010..LSIO.KPP0.COL2
66396  *  0b100..LSIO.GPIO3.IO19
66397  */
66398 #define IOMUXD_QSPI0B_DATA1_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA1_mux_mode_MASK)
66399 #define IOMUXD_QSPI0B_DATA1_update_pad_ctl_MASK  (0x40000000U)
66400 #define IOMUXD_QSPI0B_DATA1_update_pad_ctl_SHIFT (30U)
66401 /*! update_pad_ctl - update lock for pad control
66402  */
66403 #define IOMUXD_QSPI0B_DATA1_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA1_update_pad_ctl_MASK)
66404 #define IOMUXD_QSPI0B_DATA1_update_mux_mode_MASK (0x80000000U)
66405 #define IOMUXD_QSPI0B_DATA1_update_mux_mode_SHIFT (31U)
66406 /*! update_mux_mode - update lock for mux control
66407  */
66408 #define IOMUXD_QSPI0B_DATA1_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA1_update_mux_mode_MASK)
66409 /*! @} */
66410 
66411 /*! @name QSPI0B_DATA2 - QSPI0B_DATA2 */
66412 /*! @{ */
66413 #define IOMUXD_QSPI0B_DATA2_PDRV_MASK            (0x1U)
66414 #define IOMUXD_QSPI0B_DATA2_PDRV_SHIFT           (0U)
66415 /*! PDRV - Drive
66416  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66417  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66418  */
66419 #define IOMUXD_QSPI0B_DATA2_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA2_PDRV_MASK)
66420 #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_MASK (0x1EU)
66421 #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_SHIFT (1U)
66422 /*! QSPI0B_DATA2_reserved_1_4 - reserved
66423  */
66424 #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_MASK)
66425 #define IOMUXD_QSPI0B_DATA2_PULL_MASK            (0x60U)
66426 #define IOMUXD_QSPI0B_DATA2_PULL_SHIFT           (5U)
66427 /*! PULL - Pull Down Pull Up
66428  *  0b10..pull down
66429  *  0b01..pull up
66430  *  0b00..Prohibited
66431  *  0b11..pull disabled
66432  */
66433 #define IOMUXD_QSPI0B_DATA2_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA2_PULL_MASK)
66434 #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_MASK (0x7FF80U)
66435 #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_SHIFT (7U)
66436 /*! QSPI0B_DATA2_reserved_7_18 - reserved
66437  */
66438 #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_MASK)
66439 #define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_MASK     (0x380000U)
66440 #define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_SHIFT    (19U)
66441 /*! WAKEUP_CTRL - wakeup control
66442  *  0b000..OFF
66443  *  0b001..RESAMPLE
66444  *  0b100..LOW
66445  *  0b111..HIGH
66446  *  0b110..RISE
66447  *  0b101..FALL
66448  */
66449 #define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_MASK)
66450 #define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_MASK     (0x400000U)
66451 #define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_SHIFT    (22U)
66452 /*! WAKEUP_MASK - wakeup mask
66453  */
66454 #define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_MASK)
66455 #define IOMUXD_QSPI0B_DATA2_lp_config_MASK       (0x1800000U)
66456 #define IOMUXD_QSPI0B_DATA2_lp_config_SHIFT      (23U)
66457 /*! lp_config - lower power configuration
66458  *  0b01..EARLY_ISO
66459  *  0b10..LATE_ISO
66460  *  0b11..LATCH
66461  *  0b00..PASS
66462  */
66463 #define IOMUXD_QSPI0B_DATA2_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA2_lp_config_MASK)
66464 #define IOMUXD_QSPI0B_DATA2_sw_config_MASK       (0x6000000U)
66465 #define IOMUXD_QSPI0B_DATA2_sw_config_SHIFT      (25U)
66466 /*! sw_config - output and input configuration
66467  *  0b01..OPEN_DRAIN
66468  *  0b10..OPEN_DRAIN_INPUT
66469  *  0b11..INOUT
66470  *  0b00..DEFAULT
66471  */
66472 #define IOMUXD_QSPI0B_DATA2_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA2_sw_config_MASK)
66473 #define IOMUXD_QSPI0B_DATA2_mux_mode_MASK        (0x38000000U)
66474 #define IOMUXD_QSPI0B_DATA2_mux_mode_SHIFT       (27U)
66475 /*! mux_mode - mux_mode
66476  *  0b000..LSIO.QSPI0B.DATA2
66477  *  0b001..LSIO.QSPI1A.DATA2
66478  *  0b010..LSIO.KPP0.COL3
66479  *  0b100..LSIO.GPIO3.IO20
66480  */
66481 #define IOMUXD_QSPI0B_DATA2_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA2_mux_mode_MASK)
66482 #define IOMUXD_QSPI0B_DATA2_update_pad_ctl_MASK  (0x40000000U)
66483 #define IOMUXD_QSPI0B_DATA2_update_pad_ctl_SHIFT (30U)
66484 /*! update_pad_ctl - update lock for pad control
66485  */
66486 #define IOMUXD_QSPI0B_DATA2_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA2_update_pad_ctl_MASK)
66487 #define IOMUXD_QSPI0B_DATA2_update_mux_mode_MASK (0x80000000U)
66488 #define IOMUXD_QSPI0B_DATA2_update_mux_mode_SHIFT (31U)
66489 /*! update_mux_mode - update lock for mux control
66490  */
66491 #define IOMUXD_QSPI0B_DATA2_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA2_update_mux_mode_MASK)
66492 /*! @} */
66493 
66494 /*! @name QSPI0B_DATA3 - QSPI0B_DATA3 */
66495 /*! @{ */
66496 #define IOMUXD_QSPI0B_DATA3_PDRV_MASK            (0x1U)
66497 #define IOMUXD_QSPI0B_DATA3_PDRV_SHIFT           (0U)
66498 /*! PDRV - Drive
66499  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66500  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66501  */
66502 #define IOMUXD_QSPI0B_DATA3_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA3_PDRV_MASK)
66503 #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_MASK (0x1EU)
66504 #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_SHIFT (1U)
66505 /*! QSPI0B_DATA3_reserved_1_4 - reserved
66506  */
66507 #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_MASK)
66508 #define IOMUXD_QSPI0B_DATA3_PULL_MASK            (0x60U)
66509 #define IOMUXD_QSPI0B_DATA3_PULL_SHIFT           (5U)
66510 /*! PULL - Pull Down Pull Up
66511  *  0b10..pull down
66512  *  0b01..pull up
66513  *  0b00..Prohibited
66514  *  0b11..pull disabled
66515  */
66516 #define IOMUXD_QSPI0B_DATA3_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA3_PULL_MASK)
66517 #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_MASK (0x7FF80U)
66518 #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_SHIFT (7U)
66519 /*! QSPI0B_DATA3_reserved_7_18 - reserved
66520  */
66521 #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_MASK)
66522 #define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_MASK     (0x380000U)
66523 #define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_SHIFT    (19U)
66524 /*! WAKEUP_CTRL - wakeup control
66525  *  0b000..OFF
66526  *  0b001..RESAMPLE
66527  *  0b100..LOW
66528  *  0b111..HIGH
66529  *  0b110..RISE
66530  *  0b101..FALL
66531  */
66532 #define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_MASK)
66533 #define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_MASK     (0x400000U)
66534 #define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_SHIFT    (22U)
66535 /*! WAKEUP_MASK - wakeup mask
66536  */
66537 #define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_MASK)
66538 #define IOMUXD_QSPI0B_DATA3_lp_config_MASK       (0x1800000U)
66539 #define IOMUXD_QSPI0B_DATA3_lp_config_SHIFT      (23U)
66540 /*! lp_config - lower power configuration
66541  *  0b01..EARLY_ISO
66542  *  0b10..LATE_ISO
66543  *  0b11..LATCH
66544  *  0b00..PASS
66545  */
66546 #define IOMUXD_QSPI0B_DATA3_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA3_lp_config_MASK)
66547 #define IOMUXD_QSPI0B_DATA3_sw_config_MASK       (0x6000000U)
66548 #define IOMUXD_QSPI0B_DATA3_sw_config_SHIFT      (25U)
66549 /*! sw_config - output and input configuration
66550  *  0b01..OPEN_DRAIN
66551  *  0b10..OPEN_DRAIN_INPUT
66552  *  0b11..INOUT
66553  *  0b00..DEFAULT
66554  */
66555 #define IOMUXD_QSPI0B_DATA3_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA3_sw_config_MASK)
66556 #define IOMUXD_QSPI0B_DATA3_mux_mode_MASK        (0x38000000U)
66557 #define IOMUXD_QSPI0B_DATA3_mux_mode_SHIFT       (27U)
66558 /*! mux_mode - mux_mode
66559  *  0b000..LSIO.QSPI0B.DATA3
66560  *  0b001..LSIO.QSPI1A.DATA3
66561  *  0b010..LSIO.KPP0.ROW0
66562  *  0b100..LSIO.GPIO3.IO21
66563  */
66564 #define IOMUXD_QSPI0B_DATA3_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA3_mux_mode_MASK)
66565 #define IOMUXD_QSPI0B_DATA3_update_pad_ctl_MASK  (0x40000000U)
66566 #define IOMUXD_QSPI0B_DATA3_update_pad_ctl_SHIFT (30U)
66567 /*! update_pad_ctl - update lock for pad control
66568  */
66569 #define IOMUXD_QSPI0B_DATA3_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA3_update_pad_ctl_MASK)
66570 #define IOMUXD_QSPI0B_DATA3_update_mux_mode_MASK (0x80000000U)
66571 #define IOMUXD_QSPI0B_DATA3_update_mux_mode_SHIFT (31U)
66572 /*! update_mux_mode - update lock for mux control
66573  */
66574 #define IOMUXD_QSPI0B_DATA3_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA3_update_mux_mode_MASK)
66575 /*! @} */
66576 
66577 /*! @name QSPI0B_DQS - QSPI0B_DQS */
66578 /*! @{ */
66579 #define IOMUXD_QSPI0B_DQS_PDRV_MASK              (0x1U)
66580 #define IOMUXD_QSPI0B_DQS_PDRV_SHIFT             (0U)
66581 /*! PDRV - Drive
66582  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66583  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66584  */
66585 #define IOMUXD_QSPI0B_DQS_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_PDRV_SHIFT)) & IOMUXD_QSPI0B_DQS_PDRV_MASK)
66586 #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_MASK (0x1EU)
66587 #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_SHIFT (1U)
66588 /*! QSPI0B_DQS_reserved_1_4 - reserved
66589  */
66590 #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_MASK)
66591 #define IOMUXD_QSPI0B_DQS_PULL_MASK              (0x60U)
66592 #define IOMUXD_QSPI0B_DQS_PULL_SHIFT             (5U)
66593 /*! PULL - Pull Down Pull Up
66594  *  0b10..pull down
66595  *  0b01..pull up
66596  *  0b00..Prohibited
66597  *  0b11..pull disabled
66598  */
66599 #define IOMUXD_QSPI0B_DQS_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_PULL_SHIFT)) & IOMUXD_QSPI0B_DQS_PULL_MASK)
66600 #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_MASK (0x7FF80U)
66601 #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_SHIFT (7U)
66602 /*! QSPI0B_DQS_reserved_7_18 - reserved
66603  */
66604 #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_MASK)
66605 #define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_MASK       (0x380000U)
66606 #define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_SHIFT      (19U)
66607 /*! WAKEUP_CTRL - wakeup control
66608  *  0b000..OFF
66609  *  0b001..RESAMPLE
66610  *  0b100..LOW
66611  *  0b111..HIGH
66612  *  0b110..RISE
66613  *  0b101..FALL
66614  */
66615 #define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_MASK)
66616 #define IOMUXD_QSPI0B_DQS_WAKEUP_MASK_MASK       (0x400000U)
66617 #define IOMUXD_QSPI0B_DQS_WAKEUP_MASK_SHIFT      (22U)
66618 /*! WAKEUP_MASK - wakeup mask
66619  */
66620 #define IOMUXD_QSPI0B_DQS_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DQS_WAKEUP_MASK_MASK)
66621 #define IOMUXD_QSPI0B_DQS_lp_config_MASK         (0x1800000U)
66622 #define IOMUXD_QSPI0B_DQS_lp_config_SHIFT        (23U)
66623 /*! lp_config - lower power configuration
66624  *  0b01..EARLY_ISO
66625  *  0b10..LATE_ISO
66626  *  0b11..LATCH
66627  *  0b00..PASS
66628  */
66629 #define IOMUXD_QSPI0B_DQS_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_lp_config_SHIFT)) & IOMUXD_QSPI0B_DQS_lp_config_MASK)
66630 #define IOMUXD_QSPI0B_DQS_sw_config_MASK         (0x6000000U)
66631 #define IOMUXD_QSPI0B_DQS_sw_config_SHIFT        (25U)
66632 /*! sw_config - output and input configuration
66633  *  0b01..OPEN_DRAIN
66634  *  0b10..OPEN_DRAIN_INPUT
66635  *  0b11..INOUT
66636  *  0b00..DEFAULT
66637  */
66638 #define IOMUXD_QSPI0B_DQS_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_sw_config_SHIFT)) & IOMUXD_QSPI0B_DQS_sw_config_MASK)
66639 #define IOMUXD_QSPI0B_DQS_mux_mode_MASK          (0x38000000U)
66640 #define IOMUXD_QSPI0B_DQS_mux_mode_SHIFT         (27U)
66641 /*! mux_mode - mux_mode
66642  *  0b000..LSIO.QSPI0B.DQS
66643  *  0b001..LSIO.QSPI1A.DQS
66644  *  0b010..LSIO.KPP0.ROW1
66645  *  0b100..LSIO.GPIO3.IO22
66646  */
66647 #define IOMUXD_QSPI0B_DQS_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DQS_mux_mode_MASK)
66648 #define IOMUXD_QSPI0B_DQS_update_pad_ctl_MASK    (0x40000000U)
66649 #define IOMUXD_QSPI0B_DQS_update_pad_ctl_SHIFT   (30U)
66650 /*! update_pad_ctl - update lock for pad control
66651  */
66652 #define IOMUXD_QSPI0B_DQS_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DQS_update_pad_ctl_MASK)
66653 #define IOMUXD_QSPI0B_DQS_update_mux_mode_MASK   (0x80000000U)
66654 #define IOMUXD_QSPI0B_DQS_update_mux_mode_SHIFT  (31U)
66655 /*! update_mux_mode - update lock for mux control
66656  */
66657 #define IOMUXD_QSPI0B_DQS_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DQS_update_mux_mode_MASK)
66658 /*! @} */
66659 
66660 /*! @name IOMUXD_GROUP_3_0 - na */
66661 /*! @{ */
66662 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_MASK (0x1U)
66663 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_SHIFT (0U)
66664 /*! QSPI0A_DATA0 - wakeup from QSPI0A_DATA0
66665  */
66666 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_MASK)
66667 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_MASK (0x2U)
66668 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_SHIFT (1U)
66669 /*! QSPI0A_DATA1 - wakeup from QSPI0A_DATA1
66670  */
66671 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_MASK)
66672 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_MASK (0x4U)
66673 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_SHIFT (2U)
66674 /*! QSPI0A_DATA2 - wakeup from QSPI0A_DATA2
66675  */
66676 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_MASK)
66677 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_MASK (0x8U)
66678 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_SHIFT (3U)
66679 /*! QSPI0A_DATA3 - wakeup from QSPI0A_DATA3
66680  */
66681 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_MASK)
66682 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_MASK  (0x10U)
66683 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_SHIFT (4U)
66684 /*! QSPI0A_DQS - wakeup from QSPI0A_DQS
66685  */
66686 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_MASK)
66687 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_MASK (0x20U)
66688 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_SHIFT (5U)
66689 /*! QSPI0A_SS0_B - wakeup from QSPI0A_SS0_B
66690  */
66691 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_MASK)
66692 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_MASK (0x40U)
66693 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_SHIFT (6U)
66694 /*! QSPI0A_SS1_B - wakeup from QSPI0A_SS1_B
66695  */
66696 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_MASK)
66697 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_MASK (0x80U)
66698 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_SHIFT (7U)
66699 /*! QSPI0A_SCLK - wakeup from QSPI0A_SCLK
66700  */
66701 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_MASK)
66702 #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_MASK (0x100U)
66703 #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_SHIFT (8U)
66704 /*! iomuxd_group_3_0_reserved_8_8 - reserved
66705  */
66706 #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_MASK)
66707 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_MASK (0x200U)
66708 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_SHIFT (9U)
66709 /*! QSPI0B_SCLK - wakeup from QSPI0B_SCLK
66710  */
66711 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_MASK)
66712 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_MASK (0x400U)
66713 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_SHIFT (10U)
66714 /*! QSPI0B_DATA0 - wakeup from QSPI0B_DATA0
66715  */
66716 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_MASK)
66717 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_MASK (0x800U)
66718 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_SHIFT (11U)
66719 /*! QSPI0B_DATA1 - wakeup from QSPI0B_DATA1
66720  */
66721 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_MASK)
66722 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_MASK (0x1000U)
66723 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_SHIFT (12U)
66724 /*! QSPI0B_DATA2 - wakeup from QSPI0B_DATA2
66725  */
66726 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_MASK)
66727 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_MASK (0x2000U)
66728 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_SHIFT (13U)
66729 /*! QSPI0B_DATA3 - wakeup from QSPI0B_DATA3
66730  */
66731 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_MASK)
66732 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_MASK  (0x4000U)
66733 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_SHIFT (14U)
66734 /*! QSPI0B_DQS - wakeup from QSPI0B_DQS
66735  */
66736 #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_MASK)
66737 #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_MASK (0xFFFF8000U)
66738 #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_SHIFT (15U)
66739 /*! iomuxd_group_3_0_reserved_15_31 - reserved
66740  */
66741 #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_MASK)
66742 /*! @} */
66743 
66744 /*! @name QSPI0B_SS0_B - QSPI0B_SS0_B */
66745 /*! @{ */
66746 #define IOMUXD_QSPI0B_SS0_B_PDRV_MASK            (0x1U)
66747 #define IOMUXD_QSPI0B_SS0_B_PDRV_SHIFT           (0U)
66748 /*! PDRV - Drive
66749  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66750  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66751  */
66752 #define IOMUXD_QSPI0B_SS0_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_PDRV_SHIFT)) & IOMUXD_QSPI0B_SS0_B_PDRV_MASK)
66753 #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_MASK (0x1EU)
66754 #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_SHIFT (1U)
66755 /*! QSPI0B_SS0_B_reserved_1_4 - reserved
66756  */
66757 #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_MASK)
66758 #define IOMUXD_QSPI0B_SS0_B_PULL_MASK            (0x60U)
66759 #define IOMUXD_QSPI0B_SS0_B_PULL_SHIFT           (5U)
66760 /*! PULL - Pull Down Pull Up
66761  *  0b10..pull down
66762  *  0b01..pull up
66763  *  0b00..Prohibited
66764  *  0b11..pull disabled
66765  */
66766 #define IOMUXD_QSPI0B_SS0_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_PULL_SHIFT)) & IOMUXD_QSPI0B_SS0_B_PULL_MASK)
66767 #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_MASK (0x7FF80U)
66768 #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_SHIFT (7U)
66769 /*! QSPI0B_SS0_B_reserved_7_18 - reserved
66770  */
66771 #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_MASK)
66772 #define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_MASK     (0x380000U)
66773 #define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_SHIFT    (19U)
66774 /*! WAKEUP_CTRL - wakeup control
66775  *  0b000..OFF
66776  *  0b001..RESAMPLE
66777  *  0b100..LOW
66778  *  0b111..HIGH
66779  *  0b110..RISE
66780  *  0b101..FALL
66781  */
66782 #define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_MASK)
66783 #define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_MASK     (0x400000U)
66784 #define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_SHIFT    (22U)
66785 /*! WAKEUP_MASK - wakeup mask
66786  */
66787 #define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_MASK)
66788 #define IOMUXD_QSPI0B_SS0_B_lp_config_MASK       (0x1800000U)
66789 #define IOMUXD_QSPI0B_SS0_B_lp_config_SHIFT      (23U)
66790 /*! lp_config - lower power configuration
66791  *  0b01..EARLY_ISO
66792  *  0b10..LATE_ISO
66793  *  0b11..LATCH
66794  *  0b00..PASS
66795  */
66796 #define IOMUXD_QSPI0B_SS0_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_lp_config_SHIFT)) & IOMUXD_QSPI0B_SS0_B_lp_config_MASK)
66797 #define IOMUXD_QSPI0B_SS0_B_sw_config_MASK       (0x6000000U)
66798 #define IOMUXD_QSPI0B_SS0_B_sw_config_SHIFT      (25U)
66799 /*! sw_config - output and input configuration
66800  *  0b01..OPEN_DRAIN
66801  *  0b10..OPEN_DRAIN_INPUT
66802  *  0b11..INOUT
66803  *  0b00..DEFAULT
66804  */
66805 #define IOMUXD_QSPI0B_SS0_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_sw_config_SHIFT)) & IOMUXD_QSPI0B_SS0_B_sw_config_MASK)
66806 #define IOMUXD_QSPI0B_SS0_B_mux_mode_MASK        (0x38000000U)
66807 #define IOMUXD_QSPI0B_SS0_B_mux_mode_SHIFT       (27U)
66808 /*! mux_mode - mux_mode
66809  *  0b000..LSIO.QSPI0B.SS0_B
66810  *  0b001..LSIO.QSPI1A.SS0_B
66811  *  0b010..LSIO.KPP0.ROW2
66812  *  0b100..LSIO.GPIO3.IO23
66813  */
66814 #define IOMUXD_QSPI0B_SS0_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS0_B_mux_mode_MASK)
66815 #define IOMUXD_QSPI0B_SS0_B_update_pad_ctl_MASK  (0x40000000U)
66816 #define IOMUXD_QSPI0B_SS0_B_update_pad_ctl_SHIFT (30U)
66817 /*! update_pad_ctl - update lock for pad control
66818  */
66819 #define IOMUXD_QSPI0B_SS0_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SS0_B_update_pad_ctl_MASK)
66820 #define IOMUXD_QSPI0B_SS0_B_update_mux_mode_MASK (0x80000000U)
66821 #define IOMUXD_QSPI0B_SS0_B_update_mux_mode_SHIFT (31U)
66822 /*! update_mux_mode - update lock for mux control
66823  */
66824 #define IOMUXD_QSPI0B_SS0_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS0_B_update_mux_mode_MASK)
66825 /*! @} */
66826 
66827 /*! @name QSPI0B_SS1_B - QSPI0B_SS1_B */
66828 /*! @{ */
66829 #define IOMUXD_QSPI0B_SS1_B_PDRV_MASK            (0x1U)
66830 #define IOMUXD_QSPI0B_SS1_B_PDRV_SHIFT           (0U)
66831 /*! PDRV - Drive
66832  *  0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66833  *  0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66834  */
66835 #define IOMUXD_QSPI0B_SS1_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI0B_SS1_B_PDRV_MASK)
66836 #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_MASK (0x1EU)
66837 #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_SHIFT (1U)
66838 /*! QSPI0B_SS1_B_reserved_1_4 - reserved
66839  */
66840 #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_MASK)
66841 #define IOMUXD_QSPI0B_SS1_B_PULL_MASK            (0x60U)
66842 #define IOMUXD_QSPI0B_SS1_B_PULL_SHIFT           (5U)
66843 /*! PULL - Pull Down Pull Up
66844  *  0b10..pull down
66845  *  0b01..pull up
66846  *  0b00..Prohibited
66847  *  0b11..pull disabled
66848  */
66849 #define IOMUXD_QSPI0B_SS1_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_PULL_SHIFT)) & IOMUXD_QSPI0B_SS1_B_PULL_MASK)
66850 #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_MASK (0x7FF80U)
66851 #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_SHIFT (7U)
66852 /*! QSPI0B_SS1_B_reserved_7_18 - reserved
66853  */
66854 #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_MASK)
66855 #define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_MASK     (0x380000U)
66856 #define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_SHIFT    (19U)
66857 /*! WAKEUP_CTRL - wakeup control
66858  *  0b000..OFF
66859  *  0b001..RESAMPLE
66860  *  0b100..LOW
66861  *  0b111..HIGH
66862  *  0b110..RISE
66863  *  0b101..FALL
66864  */
66865 #define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_MASK)
66866 #define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_MASK     (0x400000U)
66867 #define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_SHIFT    (22U)
66868 /*! WAKEUP_MASK - wakeup mask
66869  */
66870 #define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_MASK)
66871 #define IOMUXD_QSPI0B_SS1_B_lp_config_MASK       (0x1800000U)
66872 #define IOMUXD_QSPI0B_SS1_B_lp_config_SHIFT      (23U)
66873 /*! lp_config - lower power configuration
66874  *  0b01..EARLY_ISO
66875  *  0b10..LATE_ISO
66876  *  0b11..LATCH
66877  *  0b00..PASS
66878  */
66879 #define IOMUXD_QSPI0B_SS1_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_lp_config_SHIFT)) & IOMUXD_QSPI0B_SS1_B_lp_config_MASK)
66880 #define IOMUXD_QSPI0B_SS1_B_sw_config_MASK       (0x6000000U)
66881 #define IOMUXD_QSPI0B_SS1_B_sw_config_SHIFT      (25U)
66882 /*! sw_config - output and input configuration
66883  *  0b01..OPEN_DRAIN
66884  *  0b10..OPEN_DRAIN_INPUT
66885  *  0b11..INOUT
66886  *  0b00..DEFAULT
66887  */
66888 #define IOMUXD_QSPI0B_SS1_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_sw_config_SHIFT)) & IOMUXD_QSPI0B_SS1_B_sw_config_MASK)
66889 #define IOMUXD_QSPI0B_SS1_B_mux_mode_MASK        (0x38000000U)
66890 #define IOMUXD_QSPI0B_SS1_B_mux_mode_SHIFT       (27U)
66891 /*! mux_mode - mux_mode
66892  *  0b000..LSIO.QSPI0B.SS1_B
66893  *  0b001..LSIO.QSPI1A.SS1_B
66894  *  0b010..LSIO.KPP0.ROW3
66895  *  0b100..LSIO.GPIO3.IO24
66896  */
66897 #define IOMUXD_QSPI0B_SS1_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS1_B_mux_mode_MASK)
66898 #define IOMUXD_QSPI0B_SS1_B_update_pad_ctl_MASK  (0x40000000U)
66899 #define IOMUXD_QSPI0B_SS1_B_update_pad_ctl_SHIFT (30U)
66900 /*! update_pad_ctl - update lock for pad control
66901  */
66902 #define IOMUXD_QSPI0B_SS1_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SS1_B_update_pad_ctl_MASK)
66903 #define IOMUXD_QSPI0B_SS1_B_update_mux_mode_MASK (0x80000000U)
66904 #define IOMUXD_QSPI0B_SS1_B_update_mux_mode_SHIFT (31U)
66905 /*! update_mux_mode - update lock for mux control
66906  */
66907 #define IOMUXD_QSPI0B_SS1_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS1_B_update_mux_mode_MASK)
66908 /*! @} */
66909 
66910 /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B - IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B */
66911 /*! @{ */
66912 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_MASK (0x7U)
66913 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_SHIFT (0U)
66914 /*! COMP - COMP
66915  *  0b010..Fixed code mode
66916  *  0b100..High impedance mode
66917  *  0b110..Read mode
66918  *  0b000..Normal Mode
66919  *  0b001..Freeze Mode
66920  */
66921 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_MASK)
66922 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_MASK (0x8U)
66923 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_SHIFT (3U)
66924 /*! FASTFRZ_EN - FASTFRZ_EN
66925  *  0b1..FASTFRZ signal is driven by output of subsystem
66926  *  0b0..FASTFRZ signal is gated to 0
66927  */
66928 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_MASK)
66929 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_MASK (0x10U)
66930 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_SHIFT (4U)
66931 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4 - reserved
66932  */
66933 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_MASK)
66934 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_MASK (0x1E0U)
66935 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_SHIFT (5U)
66936 /*! RASRCP - RASRCP
66937  *  0b0101..Reset Value
66938  */
66939 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_MASK)
66940 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_MASK (0x1E00U)
66941 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_SHIFT (9U)
66942 /*! RASRCN - RASRCN
66943  *  0b1010..Reset Value
66944  */
66945 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_MASK)
66946 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_MASK (0x2000U)
66947 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_SHIFT (13U)
66948 /*! SELECT_NASRC - SELECT_NASRC
66949  *  0b1..NASRCN value
66950  *  0b0..NASRCP value
66951  */
66952 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_MASK)
66953 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_MASK (0x4000U)
66954 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_SHIFT (14U)
66955 /*! COMPOK - COMPOK
66956  *  0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
66957  *  0b1..compensation cell in Normal mode and tracking PVT
66958  */
66959 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_MASK)
66960 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_MASK (0x78000U)
66961 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_SHIFT (15U)
66962 /*! READ_NASRC - READ_NASRC
66963  *  0b0000..READ Only
66964  */
66965 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_MASK)
66966 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_MASK (0x780000U)
66967 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_SHIFT (19U)
66968 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22 - reserved
66969  */
66970 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_MASK)
66971 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_MASK (0x1800000U)
66972 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_SHIFT (23U)
66973 /*! SLEEP - SLEEP
66974  *  0b11..Force into sleep mode
66975  *  0b00..NO
66976  *  0b01..EARLY
66977  *  0b10..LATE
66978  */
66979 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_MASK)
66980 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_MASK (0x3E000000U)
66981 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_SHIFT (25U)
66982 /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29 - reserved
66983  */
66984 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_MASK)
66985 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_MASK (0x40000000U)
66986 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_SHIFT (30U)
66987 /*! update_pad_ctl - update lock for pad control
66988  */
66989 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_MASK)
66990 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_MASK (0x80000000U)
66991 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_SHIFT (31U)
66992 /*! update_mux_mode - update lock for mux control
66993  */
66994 #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_MASK)
66995 /*! @} */
66996 
66997 /*! @name IOMUXD_GROUP_3_1 - na */
66998 /*! @{ */
66999 #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_MASK (0x1U)
67000 #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_SHIFT (0U)
67001 /*! QSPI0B_SS0_B - wakeup from QSPI0B_SS0_B
67002  */
67003 #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_MASK)
67004 #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_MASK (0x2U)
67005 #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_SHIFT (1U)
67006 /*! QSPI0B_SS1_B - wakeup from QSPI0B_SS1_B
67007  */
67008 #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_MASK)
67009 #define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_MASK (0xFFFFFFFCU)
67010 #define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_SHIFT (2U)
67011 /*! iomuxd_group_3_1_reserved_2_31 - reserved
67012  */
67013 #define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_MASK)
67014 /*! @} */
67015 
67016 
67017 /*!
67018  * @}
67019  */ /* end of group IOMUXD_Register_Masks */
67020 
67021 
67022 /* IOMUXD - Peripheral instance base addresses */
67023 /** Peripheral IOMUXD base address */
67024 #define IOMUXD_BASE                              (0x33F80000u)
67025 /** Peripheral IOMUXD base pointer */
67026 #define IOMUXD                                   ((IOMUXD_Type *)IOMUXD_BASE)
67027 /** Array initializer of IOMUXD peripheral base addresses */
67028 #define IOMUXD_BASE_ADDRS                        { IOMUXD_BASE }
67029 /** Array initializer of IOMUXD peripheral base pointers */
67030 #define IOMUXD_BASE_PTRS                         { IOMUXD }
67031 
67032 /*!
67033  * @}
67034  */ /* end of group IOMUXD_Peripheral_Access_Layer */
67035 
67036 /*!
67037  * @brief DPU IRQn.
67038  */
67039 typedef enum DPU_IRQSTEER_IRQn
67040 {
67041     /* DISPLAY_INT_OUT0 */
67042     CmdSeqError_DPU_IRQn = 0,
67043     SoftwareInt0_DPU_IRQn = 1,
67044     SoftwareInt1_DPU_IRQn = 2,
67045     SoftwareInt2_DPU_IRQn = 3,
67046     SoftwareInt3_DPU_IRQn = 4,
67047 
67048     /* DISPLAY_INT_OUT2 */
67049     ExtDst0ShadowLoad_DPU_IRQn = 128,
67050     ExtDst0FrameComplete_DPU_IRQn = 129,
67051     ExtDst0SeqComplete_DPU_IRQn = 130,
67052     ExtDst4ShadowLoad_DPU_IRQn = 131,
67053     ExtDst4FrameComplete_DPU_IRQn = 132,
67054     ExtDst4SeqComplete_DPU_IRQn = 133,
67055     Display0ShadowLoad_DPU_IRQn = 136,
67056     Display0FrameComplete_DPU_IRQn = 137,
67057     Display0SeqComplete_DPU_IRQn = 138,
67058     FrameGen0Int0_DPU_IRQn = 139,
67059     FrameGen0Int1_DPU_IRQn = 140,
67060     FrameGen0Int2_DPU_IRQn = 141,
67061     FrameGen0Int3_DPU_IRQn = 142,
67062     Sig0ShadowLoad_DPU_IRQn = 143,
67063     Sig0Valid_DPU_IRQn = 144,
67064     Sig0Error_DPU_IRQn = 145,
67065     FrameGen0PrimSyncOn_DPU_IRQn = 146,
67066     FrameGen0PrimSyncOff_DPU_IRQn = 147,
67067     FrameGen0SecSyncOn_DPU_IRQn = 148,
67068     FrameGen0SecSyncOff_DPU_IRQn = 149,
67069 
67070     /* DISPLAY_INT_OUT4 */
67071     ExtDst1ShadowLoad_DPU_IRQn = 256,
67072     ExtDst1FrameComplete_DPU_IRQn = 257,
67073     ExtDst1SeqComplete_DPU_IRQn = 258,
67074     ExtDst5ShadowLoad_DPU_IRQn = 259,
67075     ExtDst5FrameComplete_DPU_IRQn = 260,
67076     ExtDst5SeqComplete_DPU_IRQn = 261,
67077     Display1ShadowLoad_DPU_IRQn = 263,
67078     Display1FrameComplete_DPU_IRQn = 264,
67079     Display1SeqComplete_DPU_IRQn = 265,
67080     FrameGen1Int0_DPU_IRQn = 266,
67081     FrameGen1Int1_DPU_IRQn = 267,
67082     FrameGen1Int2_DPU_IRQn = 268,
67083     FrameGen1Int3_DPU_IRQn = 269,
67084     Sig1ShadowLoad_DPU_IRQn = 270,
67085     Sig1Valid_DPU_IRQn = 271,
67086     Sig1Error_DPU_IRQn = 272,
67087     FrameGen1PrimSyncOn_DPU_IRQn = 273,
67088     FrameGen1PrimSyncOff_DPU_IRQn = 274,
67089     FrameGen1SecSyncOn_DPU_IRQn = 275,
67090     FrameGen1SecSyncOff_DPU_IRQn = 276,
67091 
67092     /* DISPLAY_INT_OUT7 */
67093     Store9ShadowLoad_DPU_IRQn = 448,
67094     Store9FrameComplete_DPU_IRQn = 449,
67095     Store9SeqComplete_DPU_IRQn = 450,
67096 } DPU_IRQSTEER_IRQn_Type;
67097 
67098 
67099 
67100 /* ----------------------------------------------------------------------------
67101    -- IRQSTEER Peripheral Access Layer
67102    ---------------------------------------------------------------------------- */
67103 
67104 /*!
67105  * @addtogroup IRQSTEER_Peripheral_Access_Layer IRQSTEER Peripheral Access Layer
67106  * @{
67107  */
67108 
67109 /** IRQSTEER - Register Layout Typedef */
67110 typedef struct {
67111   __IO uint32_t CHANnCTL;                          /**< Channel n Control Register, offset: 0x0 */
67112   __IO uint32_t CHn_MASK[16];                      /**< Channel n Interrupt Mask Register, array offset: 0x4, array step: 0x4 */
67113   __IO uint32_t CHn_SET[16];                       /**< Channel n Interrupt Set Register, array offset: 0x44, array step: 0x4 */
67114   __I  uint32_t CHn_STATUS[16];                    /**< Channel n Interrupt Status Register, array offset: 0x84, array step: 0x4 */
67115   __IO uint32_t CHn_MINTDIS;                       /**< Channel n Master Interrupt Disable Register, offset: 0xC4 */
67116   __I  uint32_t CHn_MSTRSTAT;                      /**< Channel n Master Status Register, offset: 0xC8 */
67117 } IRQSTEER_Type;
67118 
67119 /* ----------------------------------------------------------------------------
67120    -- IRQSTEER Register Masks
67121    ---------------------------------------------------------------------------- */
67122 
67123 /*!
67124  * @addtogroup IRQSTEER_Register_Masks IRQSTEER Register Masks
67125  * @{
67126  */
67127 
67128 /*! @name CHANnCTL - Channel n Control Register */
67129 /*! @{ */
67130 #define IRQSTEER_CHANnCTL_CH0_MASK               (0x1U)
67131 #define IRQSTEER_CHANnCTL_CH0_SHIFT              (0U)
67132 /*! CH0 - Channel 0 control
67133  *  0b0..Disable channel 0
67134  *  0b1..Enable channel 0
67135  */
67136 #define IRQSTEER_CHANnCTL_CH0(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH0_SHIFT)) & IRQSTEER_CHANnCTL_CH0_MASK)
67137 #define IRQSTEER_CHANnCTL_CH1_MASK               (0x2U)
67138 #define IRQSTEER_CHANnCTL_CH1_SHIFT              (1U)
67139 /*! CH1 - Channel 1 control
67140  *  0b0..Disable channel 1
67141  *  0b1..Enable channel 1
67142  */
67143 #define IRQSTEER_CHANnCTL_CH1(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH1_SHIFT)) & IRQSTEER_CHANnCTL_CH1_MASK)
67144 #define IRQSTEER_CHANnCTL_CH2_MASK               (0x4U)
67145 #define IRQSTEER_CHANnCTL_CH2_SHIFT              (2U)
67146 /*! CH2 - Channel 2 control
67147  *  0b0..Disable channel 2
67148  *  0b1..Enable channel 2
67149  */
67150 #define IRQSTEER_CHANnCTL_CH2(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH2_SHIFT)) & IRQSTEER_CHANnCTL_CH2_MASK)
67151 #define IRQSTEER_CHANnCTL_CH3_MASK               (0x8U)
67152 #define IRQSTEER_CHANnCTL_CH3_SHIFT              (3U)
67153 /*! CH3 - Channel 3 control
67154  *  0b0..Disable channel 3
67155  *  0b1..Enable channel 3
67156  */
67157 #define IRQSTEER_CHANnCTL_CH3(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH3_SHIFT)) & IRQSTEER_CHANnCTL_CH3_MASK)
67158 #define IRQSTEER_CHANnCTL_CH4_MASK               (0x10U)
67159 #define IRQSTEER_CHANnCTL_CH4_SHIFT              (4U)
67160 /*! CH4 - Channel 4 control
67161  *  0b0..Disable channel 4
67162  *  0b1..Enable channel 4
67163  */
67164 #define IRQSTEER_CHANnCTL_CH4(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH4_SHIFT)) & IRQSTEER_CHANnCTL_CH4_MASK)
67165 /*! @} */
67166 
67167 /*! @name CHn_MASK - Channel n Interrupt Mask Register */
67168 /*! @{ */
67169 #define IRQSTEER_CHn_MASK_MASKFLD_MASK           (0xFFFFFFFFU)
67170 #define IRQSTEER_CHn_MASK_MASKFLD_SHIFT          (0U)
67171 /*! MASKFLD - Mask bits
67172  *  0b00000000000000000000000000000000..Mask interrupt
67173  *  0b00000000000000000000000000000001..Do not mask interrupt
67174  */
67175 #define IRQSTEER_CHn_MASK_MASKFLD(x)             (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MASK_MASKFLD_SHIFT)) & IRQSTEER_CHn_MASK_MASKFLD_MASK)
67176 /*! @} */
67177 
67178 /* The count of IRQSTEER_CHn_MASK */
67179 #define IRQSTEER_CHn_MASK_COUNT                  (16U)
67180 
67181 /*! @name CHn_SET - Channel n Interrupt Set Register */
67182 /*! @{ */
67183 #define IRQSTEER_CHn_SET_FORCEFLD_MASK           (0xFFFFFFFFU)
67184 #define IRQSTEER_CHn_SET_FORCEFLD_SHIFT          (0U)
67185 /*! FORCEFLD - Brief bitfield description.
67186  *  0b00000000000000000000000000000000..Normal operation
67187  *  0b00000000000000000000000000000001..Force interrupt
67188  */
67189 #define IRQSTEER_CHn_SET_FORCEFLD(x)             (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_SET_FORCEFLD_SHIFT)) & IRQSTEER_CHn_SET_FORCEFLD_MASK)
67190 /*! @} */
67191 
67192 /* The count of IRQSTEER_CHn_SET */
67193 #define IRQSTEER_CHn_SET_COUNT                   (16U)
67194 
67195 /*! @name CHn_STATUS - Channel n Interrupt Status Register */
67196 /*! @{ */
67197 #define IRQSTEER_CHn_STATUS_STATUS_MASK          (0xFFFFFFFFU)
67198 #define IRQSTEER_CHn_STATUS_STATUS_SHIFT         (0U)
67199 /*! STATUS - Status of an interrupt
67200  *  0b00000000000000000000000000000000..Interrupt is not set.
67201  *  0b00000000000000000000000000000001..Interrupt is set.
67202  */
67203 #define IRQSTEER_CHn_STATUS_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_STATUS_STATUS_SHIFT)) & IRQSTEER_CHn_STATUS_STATUS_MASK)
67204 /*! @} */
67205 
67206 /* The count of IRQSTEER_CHn_STATUS */
67207 #define IRQSTEER_CHn_STATUS_COUNT                (16U)
67208 
67209 /*! @name CHn_MINTDIS - Channel n Master Interrupt Disable Register */
67210 /*! @{ */
67211 #define IRQSTEER_CHn_MINTDIS_DISABLE_MASK        (0xFFU)
67212 #define IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT       (0U)
67213 /*! DISABLE - Each bit of this field disables the corresponding interrupts in table above.
67214  *  0b00000000..Enable interrupts
67215  *  0b00000001..Disable interrupts
67216  */
67217 #define IRQSTEER_CHn_MINTDIS_DISABLE(x)          (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT)) & IRQSTEER_CHn_MINTDIS_DISABLE_MASK)
67218 /*! @} */
67219 
67220 /*! @name CHn_MSTRSTAT - Channel n Master Status Register */
67221 /*! @{ */
67222 #define IRQSTEER_CHn_MSTRSTAT_STATUS_MASK        (0x1U)
67223 #define IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT       (0U)
67224 /*! STATUS - Status of all interrupts
67225  *  0b0..No interrupts are asserted.
67226  *  0b1..At least one interrupt is asserted.
67227  */
67228 #define IRQSTEER_CHn_MSTRSTAT_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT)) & IRQSTEER_CHn_MSTRSTAT_STATUS_MASK)
67229 /*! @} */
67230 
67231 
67232 /*!
67233  * @}
67234  */ /* end of group IRQSTEER_Register_Masks */
67235 
67236 
67237 /* IRQSTEER - Peripheral instance base addresses */
67238 /** Peripheral IRQSTEER base address */
67239 #define IRQSTEER_BASE                            (0x51070000u)
67240 /** Peripheral IRQSTEER base pointer */
67241 #define IRQSTEER                                 ((IRQSTEER_Type *)IRQSTEER_BASE)
67242 /** Array initializer of IRQSTEER peripheral base addresses */
67243 #define IRQSTEER_BASE_ADDRS                      { IRQSTEER_BASE }
67244 /** Array initializer of IRQSTEER peripheral base pointers */
67245 #define IRQSTEER_BASE_PTRS                       { IRQSTEER }
67246 /* Backward compatibility */
67247 #define DPU0_IRQSTEER_BASE                       (0x56000000u)
67248 #define DPU0_IRQSTEER                            ((IRQSTEER_Type *)DPU0_IRQSTEER_BASE)
67249 #define IRQSTEER_IRQS                            { IRQSTEER_0_IRQn, IRQSTEER_1_IRQn, IRQSTEER_2_IRQn, IRQSTEER_3_IRQn, IRQSTEER_4_IRQn, IRQSTEER_5_IRQn, IRQSTEER_6_IRQn, IRQSTEER_7_IRQn }
67250 
67251 
67252 /*!
67253  * @}
67254  */ /* end of group IRQSTEER_Peripheral_Access_Layer */
67255 
67256 
67257 /* ----------------------------------------------------------------------------
67258    -- ISI Peripheral Access Layer
67259    ---------------------------------------------------------------------------- */
67260 
67261 /*!
67262  * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer
67263  * @{
67264  */
67265 
67266 /** ISI - Register Layout Typedef */
67267 typedef struct {
67268   __IO uint32_t CHNL_CTRL;                         /**< Channel Control Register, offset: 0x0 */
67269   __IO uint32_t CHNL_IMG_CTRL;                     /**< Channel Image Control Register, offset: 0x4 */
67270   __IO uint32_t CHNL_OUT_BUF_CTRL;                 /**< Channel Output Buffer Control Register, offset: 0x8 */
67271   __IO uint32_t CHNL_IMG_CFG;                      /**< Channel Image Configuration, offset: 0xC */
67272   __IO uint32_t CHNL_IER;                          /**< Channel Interrupt Enable Register, offset: 0x10 */
67273   __IO uint32_t CHNL_STS;                          /**< Channel Status Register, offset: 0x14 */
67274   __IO uint32_t CHNL_SCALE_FACTOR;                 /**< Channel Scale Factor Register, offset: 0x18 */
67275   __IO uint32_t CHNL_SCALE_OFFSET;                 /**< Channel Scale Offset Register, offset: 0x1C */
67276   __IO uint32_t CHNL_CROP_ULC;                     /**< Channel Crop Upper Left Corner Coordinate Register, offset: 0x20 */
67277   __IO uint32_t CHNL_CROP_LRC;                     /**< Channel Crop Lower Right Corner Coordinate Register, offset: 0x24 */
67278   __IO uint32_t CHNL_CSC_COEFF0;                   /**< Channel Color Space Conversion Coefficient Register 0, offset: 0x28 */
67279   __IO uint32_t CHNL_CSC_COEFF1;                   /**< Channel Color Space Conversion Coefficient Register 1, offset: 0x2C */
67280   __IO uint32_t CHNL_CSC_COEFF2;                   /**< Channel Color Space Conversion Coefficient Register 2, offset: 0x30 */
67281   __IO uint32_t CHNL_CSC_COEFF3;                   /**< Channel Color Space Conversion Coefficient Register 3, offset: 0x34 */
67282   __IO uint32_t CHNL_CSC_COEFF4;                   /**< Channel Color Space Conversion Coefficient Register 4, offset: 0x38 */
67283   __IO uint32_t CHNL_CSC_COEFF5;                   /**< Channel Color Space Conversion Coefficient Register 5, offset: 0x3C */
67284   struct {                                         /* offset: 0x40, array step: 0xC */
67285     __IO uint32_t CHNL_ROI_ALPHA;                    /**< Channel Alpha Value Register for Region of Interest 0..Channel Alpha Value Register for Region of Interest 3, array offset: 0x40, array step: 0xC */
67286     __IO uint32_t CHNL_ROI_ULC;                      /**< Channel Upper Left Coordinate Register for Region of Interest 0..Channel Upper Left Coordinate Register for Region of Interest 3, array offset: 0x44, array step: 0xC */
67287     __IO uint32_t CHNL_ROI_LRC;                      /**< Channel Lower Right Coordinate Register for Region of Interest 0..Channel Lower Right Coordinate Register for Region of Interest 3, array offset: 0x48, array step: 0xC */
67288   } ROI[4];
67289   __IO uint32_t CHNL_OUT_BUF1_ADDR_Y;              /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */
67290   __IO uint32_t CHNL_OUT_BUF1_ADDR_U;              /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */
67291   __IO uint32_t CHNL_OUT_BUF1_ADDR_V;              /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */
67292   __IO uint32_t CHNL_OUT_BUF_PITCH;                /**< Channel Output Buffer Pitch, offset: 0x7C */
67293   __IO uint32_t CHNL_IN_BUF_ADDR;                  /**< Channel Input Buffer Address, offset: 0x80 */
67294   __IO uint32_t CHNL_IN_BUF_PITCH;                 /**< Channel Input Buffer Pitch, offset: 0x84 */
67295   __IO uint32_t CHNL_MEM_RD_CTRL;                  /**< Channel Memory Read Control, offset: 0x88 */
67296   __IO uint32_t CHNL_OUT_BUF2_ADDR_Y;              /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */
67297   __IO uint32_t CHNL_OUT_BUF2_ADDR_U;              /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */
67298   __IO uint32_t CHNL_OUT_BUF2_ADDR_V;              /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */
67299   __IO uint32_t CHNL_SCL_IMG_CFG;                  /**< Channel Scaled Image Configuration, offset: 0x98 */
67300 } ISI_Type;
67301 
67302 /* ----------------------------------------------------------------------------
67303    -- ISI Register Masks
67304    ---------------------------------------------------------------------------- */
67305 
67306 /*!
67307  * @addtogroup ISI_Register_Masks ISI Register Masks
67308  * @{
67309  */
67310 
67311 /*! @name CHNL_CTRL - Channel Control Register */
67312 /*! @{ */
67313 #define ISI_CHNL_CTRL_SRC_MASK                   (0x7U)
67314 #define ISI_CHNL_CTRL_SRC_SHIFT                  (0U)
67315 /*! SRC - Input image source port selection
67316  *  0b000..Image will be sourced from input port 0 of the Pixel Link Crossbar
67317  *  0b001..Image will be sourced from input port 1 of the Pixel Link Crossbar
67318  *  0b010..Image will be sourced from input port 2 of the Pixel Link Crossbar
67319  *  0b011..Image will be sourced from input port 3 of the Pixel Link Crossbar
67320  *  0b100..Image will be sourced from input port 4 of the Pixel Link Crossbar
67321  *  0b101..Image will be sourced from input port 5 of the Pixel Link Crossbar (Input port 5 connected to AXI read)
67322  *  0b110..Reserved
67323  *  0b111..Reserved
67324  */
67325 #define ISI_CHNL_CTRL_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK)
67326 #define ISI_CHNL_CTRL_SRC_TYPE_MASK              (0x10U)
67327 #define ISI_CHNL_CTRL_SRC_TYPE_SHIFT             (4U)
67328 /*! SRC_TYPE - Type of selected input image source
67329  *  0b0..Image input source is MIPI CSI, Display Controller or HDMI Rx
67330  *  0b1..Image input source is Memory
67331  */
67332 #define ISI_CHNL_CTRL_SRC_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK)
67333 #define ISI_CHNL_CTRL_MIPI_VC_ID_MASK            (0xC0U)
67334 #define ISI_CHNL_CTRL_MIPI_VC_ID_SHIFT           (6U)
67335 /*! MIPI_VC_ID - Virtual channel ID
67336  *  0b00..Virtual Channel 0 selected or no virtual channel used
67337  *  0b01..Virtual Channel 1 selected
67338  *  0b10..Virtual Channel 2 selected
67339  *  0b11..Virtual Channel 3 selected
67340  */
67341 #define ISI_CHNL_CTRL_MIPI_VC_ID(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_MIPI_VC_ID_SHIFT)) & ISI_CHNL_CTRL_MIPI_VC_ID_MASK)
67342 #define ISI_CHNL_CTRL_SEC_LB_SRC_MASK            (0x700U)
67343 #define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT           (8U)
67344 /*! SEC_LB_SRC - Secondary line buffer source
67345  */
67346 #define ISI_CHNL_CTRL_SEC_LB_SRC(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK)
67347 #define ISI_CHNL_CTRL_BLANK_PXL_MASK             (0xFF0000U)
67348 #define ISI_CHNL_CTRL_BLANK_PXL_SHIFT            (16U)
67349 /*! BLANK_PXL - Blank pixel value
67350  *  0b11111111..Default value
67351  *  0b00000000..Black color
67352  */
67353 #define ISI_CHNL_CTRL_BLANK_PXL(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_BLANK_PXL_SHIFT)) & ISI_CHNL_CTRL_BLANK_PXL_MASK)
67354 #define ISI_CHNL_CTRL_SW_RST_MASK                (0x1000000U)
67355 #define ISI_CHNL_CTRL_SW_RST_SHIFT               (24U)
67356 /*! SW_RST - Software reset bit
67357  *  0b0..No Reset
67358  *  0b1..Channel pipeline is under software reset
67359  */
67360 #define ISI_CHNL_CTRL_SW_RST(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK)
67361 #define ISI_CHNL_CTRL_CHAIN_BUF_MASK             (0x6000000U)
67362 #define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT            (25U)
67363 /*! CHAIN_BUF - Chain line buffer control
67364  *  0b00..No line buffers chained (supports 2048 or less horizontal resolution)
67365  *  0b01..2 line buffers chained (supports 4096 horizontal resolution). Line buffers of channels 'n' and 'n+1' are chained.
67366  *  0b10..Reserved for future use
67367  *  0b11..Reserved for future use
67368  */
67369 #define ISI_CHNL_CTRL_CHAIN_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK)
67370 #define ISI_CHNL_CTRL_CHNL_BYPASS_MASK           (0x20000000U)
67371 #define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT          (29U)
67372 /*! CHNL_BYPASS - Channel bypass enable
67373  *  0b0..Channel is not bypassed
67374  *  0b1..Channel is bypassed
67375  */
67376 #define ISI_CHNL_CTRL_CHNL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK)
67377 #define ISI_CHNL_CTRL_CLK_EN_MASK                (0x40000000U)
67378 #define ISI_CHNL_CTRL_CLK_EN_SHIFT               (30U)
67379 /*! CLK_EN - Channel clock enable
67380  *  0b0..Channel processing clock is disabled
67381  *  0b1..Channel processing clock is enabled
67382  */
67383 #define ISI_CHNL_CTRL_CLK_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK)
67384 #define ISI_CHNL_CTRL_CHNL_EN_MASK               (0x80000000U)
67385 #define ISI_CHNL_CTRL_CHNL_EN_SHIFT              (31U)
67386 /*! CHNL_EN - Enable channel processing
67387  *  0b0..Processing channel is disabled
67388  *  0b1..Processing channel is enabled
67389  */
67390 #define ISI_CHNL_CTRL_CHNL_EN(x)                 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK)
67391 /*! @} */
67392 
67393 /*! @name CHNL_IMG_CTRL - Channel Image Control Register */
67394 /*! @{ */
67395 #define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK           (0x1U)
67396 #define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT          (0U)
67397 /*! CSC_BYP - Color Space Conversion bypass control
67398  *  0b0..CSC is operational
67399  *  0b1..CSC is bypassed
67400  */
67401 #define ISI_CHNL_IMG_CTRL_CSC_BYP(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK)
67402 #define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK          (0x6U)
67403 #define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT         (1U)
67404 /*! CSC_MODE - Color Space Conversion operating mode
67405  *  0b00..Convert from YUV to RGB
67406  *  0b01..Convert from YCbCr to RGB
67407  *  0b10..Convert from RGB to YUV
67408  *  0b11..Convert from RGB to YCbCr
67409  */
67410 #define ISI_CHNL_IMG_CTRL_CSC_MODE(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK)
67411 #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK        (0x8U)
67412 #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT       (3U)
67413 /*! YCBCR_MODE - YCbCr Mode
67414  *  0b0..YCbCr mode is disabled
67415  *  0b1..YCbCr mode is enabled
67416  */
67417 #define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK)
67418 #define ISI_CHNL_IMG_CTRL_RSVD2_MASK             (0x10U)
67419 #define ISI_CHNL_IMG_CTRL_RSVD2_SHIFT            (4U)
67420 /*! RSVD2 - Reserved field. Reads only zeros
67421  */
67422 #define ISI_CHNL_IMG_CTRL_RSVD2(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD2_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD2_MASK)
67423 #define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK          (0x20U)
67424 #define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT         (5U)
67425 /*! HFLIP_EN - Horizontal flip control
67426  *  0b0..Horizantal image flip disabled
67427  *  0b1..Horizontal image flip enabled
67428  */
67429 #define ISI_CHNL_IMG_CTRL_HFLIP_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK)
67430 #define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK          (0x40U)
67431 #define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT         (6U)
67432 /*! VFLIP_EN - Veritical flip control
67433  *  0b0..Vertical image flip disabled
67434  *  0b1..Vertical image flip enabled
67435  */
67436 #define ISI_CHNL_IMG_CTRL_VFLIP_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK)
67437 #define ISI_CHNL_IMG_CTRL_CROP_EN_MASK           (0x80U)
67438 #define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT          (7U)
67439 /*! CROP_EN - Output image cropping enable
67440  *  0b0..Image cropping is disabled
67441  *  0b1..Image cropping is enabled
67442  */
67443 #define ISI_CHNL_IMG_CTRL_CROP_EN(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK)
67444 #define ISI_CHNL_IMG_CTRL_DEC_Y_MASK             (0x300U)
67445 #define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT            (8U)
67446 /*! DEC_Y - Vertical pre-decimation control
67447  *  0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
67448  *  0b01..Decimate by 2
67449  *  0b10..Decimate by 4
67450  *  0b11..Decimate by 8
67451  */
67452 #define ISI_CHNL_IMG_CTRL_DEC_Y(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK)
67453 #define ISI_CHNL_IMG_CTRL_DEC_X_MASK             (0xC00U)
67454 #define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT            (10U)
67455 /*! DEC_X - Horizontal pre-decimation control
67456  *  0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
67457  *  0b01..Decimate by 2
67458  *  0b10..Decimate by 4
67459  *  0b11..Decimate by 8
67460  */
67461 #define ISI_CHNL_IMG_CTRL_DEC_X(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK)
67462 #define ISI_CHNL_IMG_CTRL_DEINT_MASK             (0x7000U)
67463 #define ISI_CHNL_IMG_CTRL_DEINT_SHIFT            (12U)
67464 /*! DEINT - De-interlace control
67465  *  0b000, 0b001..No de-interlacing done
67466  *  0b010..Weave de-interlacing (Odd, Even) method used
67467  *  0b011..Weave de-interlacing (Even, Odd) method used
67468  *  0b100..Blending or linear interpolation (Odd + Even) de-interlacing method used
67469  *  0b101..Blending or linear interpolation (Even + Odd) de-interlacing method used
67470  *  0b110, 0b111..Line doubling de-interlacing method used. Both Odd and Even fields are doubled.
67471  */
67472 #define ISI_CHNL_IMG_CTRL_DEINT(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK)
67473 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK      (0x8000U)
67474 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT     (15U)
67475 /*! GBL_ALPHA_EN - Global alpha value insertion enable
67476  *  0b0..Global Alpha value insertion is disabled
67477  *  0b1..Global Alpha value insertion is enabled
67478  */
67479 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK)
67480 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK     (0xFF0000U)
67481 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT    (16U)
67482 /*! GBL_ALPHA_VAL - Global alpha value
67483  *  0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels
67484  */
67485 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK)
67486 #define ISI_CHNL_IMG_CTRL_FORMAT_MASK            (0x3F000000U)
67487 #define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT           (24U)
67488 /*! FORMAT - Output image format
67489  *  0b000000..RGBA8888 - RGB format with alpha in LSB; 8-bits per component. 'A' indicates alpha value.
67490  *  0b000001..ABGR8888 - BGR format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
67491  *  0b000010..ARGB8888 - RGB format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
67492  *  0b000011..RGBX888 - RGB format with 8-bits per color component (unpacked and MSB-alinged in 32-bit DWORD). 'X' indicates the waste bits.
67493  *  0b000100..XBGR888 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
67494  *  0b000101..XRGB888 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
67495  *  0b000110..RGB888P - RGB format with 8-bits per color component (packed into 24-bits). No waste bits.
67496  *  0b000111..BGR888P - BGR format with 8-bits per color component (packed into 24-bits). No waste bits.
67497  *  0b001000..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
67498  *  0b001001..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
67499  *  0b001010..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 16-bits WORD). No waste bits.
67500  *  0b001011..RAW8 - 8-bit RAW data packed into 32-bit DWORD
67501  *  0b001100..RAW10 - 10-bit RAW data packed into 16-bit WORD with 6 LSBs waste bits
67502  *  0b001101..RAW10P - 10-bit RAW data packed into 32-bit DWORD
67503  *  0b001110..RAW12 - 12-bit RAW data packed into 16-bit DWORD with 4 LSBs waste bits
67504  *  0b001111..RAW16 - 16-bit RAW data packed into 32-bit DWORD
67505  *  0b010000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
67506  *  0b010001..YUV444_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
67507  *  0b010010..YUV444_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
67508  *  0b010011..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
67509  *  0b010100..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
67510  *  0b010101..YUV444_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
67511  *  0b010110..YUV444_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
67512  *  0b010111..Reserved for future use
67513  *  0b011000..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
67514  *  0b011001..YUV444_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
67515  *  0b011010..YUV444_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
67516  *  0b011011..Reserved for future use
67517  *  0b011100..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
67518  *  0b011101..YUV444_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
67519  *  0b011110..YUV444_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
67520  *  0b011111..Reserved for future use
67521  *  0b100000..YUV422_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
67522  *  0b100001..YUV422_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
67523  *  0b100010..YUV422_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
67524  *  0b100011..Reserved for future use
67525  *  0b100100..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
67526  *  0b100101..YUV422_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
67527  *  0b100110..YUV422_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
67528  *  0b100111..Reserved for future use
67529  *  0b101000..YUV422_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
67530  *  0b101001..YUV422_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
67531  *  0b101010..YUV422_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
67532  *  0b101011..Reserved for future use
67533  *  0b101100..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
67534  *  0b101101..YUV422_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
67535  *  0b101110..YUV422_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
67536  *  0b101111..Reserved for future use
67537  *  0b110000..Reserved for future use
67538  *  0b110001..YUV420_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
67539  *  0b110010..YUV420_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
67540  *  0b110011..Reserved for future use
67541  *  0b110100..Reserved for future use
67542  *  0b110101..YUV420_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
67543  *  0b110110..YUV420_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
67544  *  0b110111..Reserved for future use
67545  *  0b111000..Reserved for future use
67546  *  0b111001..YUV420_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
67547  *  0b111010..YUV420_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
67548  *  0b111011..Reserved for future use
67549  *  0b111100..Reserved for future use
67550  *  0b111101..YUV420_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
67551  *  0b111110..YUV420_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
67552  *  0b111111..Reserved for future use
67553  */
67554 #define ISI_CHNL_IMG_CTRL_FORMAT(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK)
67555 #define ISI_CHNL_IMG_CTRL_RSVD0_MASK             (0xC0000000U)
67556 #define ISI_CHNL_IMG_CTRL_RSVD0_SHIFT            (30U)
67557 /*! RSVD0 - Reserved field. Reads only zeros
67558  */
67559 #define ISI_CHNL_IMG_CTRL_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD0_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD0_MASK)
67560 /*! @} */
67561 
67562 /*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control Register */
67563 /*! @{ */
67564 #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK (0x3U)
67565 #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_SHIFT (0U)
67566 /*! OFLW_PANIC_SET_THD_Y - Overflow panic set threshold value for Y/RGB output buffer
67567  *  0b00..No panic alert will be asserted
67568  *  0b01..Panic will assert when the buffers are 25% full (i.e. have 128 bytes)
67569  *  0b10..Panic will assert when the buffers are 50% full (i.e. have 256 bytes)
67570  *  0b11..Panic will assert when the buffers are 75% full (i.e. have 384 bytes)
67571  */
67572 #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK)
67573 #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK (0x18U)
67574 #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_SHIFT (3U)
67575 /*! OFLW_PANIC_SET_THD_U - Overflow panic set threshold value for U output buffer
67576  *  0b00..No panic alert will be asserted
67577  *  0b01..Panic will assert when the buffers are 25% full (i.e. have 128 bytes)
67578  *  0b10..Panic will assert when the buffers are 50% full (i.e. have 256 bytes)
67579  *  0b11..Panic will assert when the buffers are 75% full (i.e. have 384 bytes)
67580  */
67581 #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK)
67582 #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK (0xC0U)
67583 #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_SHIFT (6U)
67584 /*! OFLW_PANIC_SET_THD_V - Overflow panic set threshold value for V output buffer
67585  *  0b00..No panic alert will be asserted
67586  *  0b01..Panic will assert when the buffers are 25% full (i.e. have 128 bytes)
67587  *  0b10..Panic will assert when the buffers are 50% full (i.e. have 256 bytes)
67588  *  0b11..Panic will assert when the buffers are 75% full (i.e. have 384 bytes)
67589  */
67590 #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK)
67591 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U)
67592 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U)
67593 /*! LOAD_BUF1_ADDR - Load Buffer 1 Address from CHNLOUT_BUF1_ADDR_* registers
67594  */
67595 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK)
67596 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U)
67597 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U)
67598 /*! LOAD_BUF2_ADDR - Load Buffer 2 Address from CHNLOUT_BUF2_ADDR_* registers
67599  */
67600 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK)
67601 /*! @} */
67602 
67603 /*! @name CHNL_IMG_CFG - Channel Image Configuration */
67604 /*! @{ */
67605 #define ISI_CHNL_IMG_CFG_WIDTH_MASK              (0x1FFFU)
67606 #define ISI_CHNL_IMG_CFG_WIDTH_SHIFT             (0U)
67607 /*! WIDTH - Input image width (pixels)
67608  */
67609 #define ISI_CHNL_IMG_CFG_WIDTH(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK)
67610 #define ISI_CHNL_IMG_CFG_RSVD0_MASK              (0xE000U)
67611 #define ISI_CHNL_IMG_CFG_RSVD0_SHIFT             (13U)
67612 /*! RSVD0 - Reserved field. Reads only zeros.
67613  */
67614 #define ISI_CHNL_IMG_CFG_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD0_MASK)
67615 #define ISI_CHNL_IMG_CFG_HEIGHT_MASK             (0x1FFF0000U)
67616 #define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT            (16U)
67617 /*! HEIGHT - Input image height (lines)
67618  */
67619 #define ISI_CHNL_IMG_CFG_HEIGHT(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK)
67620 #define ISI_CHNL_IMG_CFG_RSVD1_MASK              (0xE0000000U)
67621 #define ISI_CHNL_IMG_CFG_RSVD1_SHIFT             (29U)
67622 /*! RSVD1 - Reserved field. Reads only zeros.
67623  */
67624 #define ISI_CHNL_IMG_CFG_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD1_MASK)
67625 /*! @} */
67626 
67627 /*! @name CHNL_IER - Channel Interrupt Enable Register */
67628 /*! @{ */
67629 #define ISI_CHNL_IER_RSVD0_MASK                  (0x3FFFU)
67630 #define ISI_CHNL_IER_RSVD0_SHIFT                 (0U)
67631 /*! RSVD0 - Reserved field. Reads only zeros.
67632  */
67633 #define ISI_CHNL_IER_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_RSVD0_SHIFT)) & ISI_CHNL_IER_RSVD0_MASK)
67634 #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK      (0x4000U)
67635 #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT     (14U)
67636 /*! LATE_VSYNC_ERR_EN - VSYNC timing (Late) error interrupt enable bit
67637  *  0b0..Interrupt is disabled
67638  *  0b1..Interrupt is enabled
67639  */
67640 #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK)
67641 #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK     (0x8000U)
67642 #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT    (15U)
67643 /*! EARLY_VSYNC_ERR_EN - VSYNC timing (Early) error interrupt enable bit
67644  *  0b0..Interrupt is disabled
67645  *  0b1..Interrupt is enabled
67646  */
67647 #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK)
67648 #define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK          (0x10000U)
67649 #define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT         (16U)
67650 /*! OFLW_Y_BUF_EN - Y output buffer overflow interrupt enable bit
67651  *  0b0..Interrupt is disabled
67652  *  0b1..Interrupt is enabled
67653  */
67654 #define ISI_CHNL_IER_OFLW_Y_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK)
67655 #define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_MASK     (0x20000U)
67656 #define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_SHIFT    (17U)
67657 /*! EXCS_OFLW_Y_BUF_EN - Y output buffer excess overflow interrupt enable bit
67658  *  0b0..Interrupt is disabled
67659  *  0b1..Interrupt is enabled
67660  */
67661 #define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_MASK)
67662 #define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_MASK    (0x40000U)
67663 #define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_SHIFT   (18U)
67664 /*! OFLW_PANIC_Y_BUF_EN - Y output buffer potential overflow panic interrupt enable bit
67665  *  0b0..Interrupt is disabled
67666  *  0b1..Interrupt is enabled
67667  */
67668 #define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_MASK)
67669 #define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK          (0x80000U)
67670 #define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT         (19U)
67671 /*! OFLW_U_BUF_EN - U output buffer overflow interrupt enable bit
67672  *  0b0..Interrupt is disabled
67673  *  0b1..Interrupt is enabled
67674  */
67675 #define ISI_CHNL_IER_OFLW_U_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK)
67676 #define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_MASK     (0x100000U)
67677 #define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_SHIFT    (20U)
67678 /*! EXCS_OFLW_U_BUF_EN - U output buffer excess overflow interrupt enable bit
67679  *  0b0..Interrupt is disabled
67680  *  0b1..Interrupt is enabled
67681  */
67682 #define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_MASK)
67683 #define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_MASK    (0x200000U)
67684 #define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_SHIFT   (21U)
67685 /*! OFLW_PANIC_U_BUF_EN - U output buffer potential overflow panic interrupt enable bit
67686  *  0b0..Interrupt is disabled
67687  *  0b1..Interrupt is enabled
67688  */
67689 #define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_MASK)
67690 #define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK          (0x400000U)
67691 #define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT         (22U)
67692 /*! OFLW_V_BUF_EN - V output buffer overflow interrupt enable bit
67693  *  0b0..Interrupt is disabled
67694  *  0b1..Interrupt is enabled
67695  */
67696 #define ISI_CHNL_IER_OFLW_V_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK)
67697 #define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_MASK     (0x800000U)
67698 #define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_SHIFT    (23U)
67699 /*! EXCS_OFLW_V_BUF_EN - V output buffer excess overflow interrupt enable bit
67700  *  0b0..Interrupt is disabled
67701  *  0b1..Interrupt is enabled
67702  */
67703 #define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_MASK)
67704 #define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_MASK    (0x1000000U)
67705 #define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_SHIFT   (24U)
67706 /*! OFLW_PANIC_V_BUF_EN - V output buffer potential overflow panic interrupt enable bit
67707  *  0b0..Interrupt is disabled
67708  *  0b1..Interrupt is enabled
67709  */
67710 #define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_MASK)
67711 #define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK          (0x2000000U)
67712 #define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT         (25U)
67713 /*! AXI_RD_ERR_EN - AXI bus read error interrupt enable bit (Channel 0 only)
67714  *  0b0..Interrupt is disabled
67715  *  0b1..Interrupt is enabled
67716  */
67717 #define ISI_CHNL_IER_AXI_RD_ERR_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK)
67718 #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK        (0x4000000U)
67719 #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT       (26U)
67720 /*! AXI_WR_ERR_Y_EN - AXI bus read error interrupt enable bit for Y/RGB data buffer
67721  *  0b0..Interrupt is disabled
67722  *  0b1..Interrupt is enabled
67723  */
67724 #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK)
67725 #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK        (0x8000000U)
67726 #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT       (27U)
67727 /*! AXI_WR_ERR_U_EN - AXI bus read error interrupt enable bit for U data buffer
67728  *  0b0..Interrupt is disabled
67729  *  0b1..Interrupt is enabled
67730  */
67731 #define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK)
67732 #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK        (0x10000000U)
67733 #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT       (28U)
67734 /*! AXI_WR_ERR_V_EN - AXI bus read error interrupt enable bit for V data buffer
67735  *  0b0..Interrupt is disabled
67736  *  0b1..Interrupt is enabled
67737  */
67738 #define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK)
67739 #define ISI_CHNL_IER_FRM_RCVD_EN_MASK            (0x20000000U)
67740 #define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT           (29U)
67741 /*! FRM_RCVD_EN - Frame received interrupt enable bit
67742  *  0b0..Interrupt is disabled
67743  *  0b1..Interrupt is enabled
67744  */
67745 #define ISI_CHNL_IER_FRM_RCVD_EN(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK)
67746 #define ISI_CHNL_IER_LINE_RCVD_EN_MASK           (0x40000000U)
67747 #define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT          (30U)
67748 /*! LINE_RCVD_EN - Line received interrupt enable bit
67749  *  0b0..Interrupt is disabled
67750  *  0b1..Interrupt is enabled
67751  */
67752 #define ISI_CHNL_IER_LINE_RCVD_EN(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK)
67753 #define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK         (0x80000000U)
67754 #define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT        (31U)
67755 /*! MEM_RD_DONE_EN - Memory read complete interrupt enable bit
67756  *  0b0..Interrupt is disabled
67757  *  0b1..Interrupt is enabled
67758  */
67759 #define ISI_CHNL_IER_MEM_RD_DONE_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK)
67760 /*! @} */
67761 
67762 /*! @name CHNL_STS - Channel Status Register */
67763 /*! @{ */
67764 #define ISI_CHNL_STS_OFLW_BYTES_MASK             (0xFFU)
67765 #define ISI_CHNL_STS_OFLW_BYTES_SHIFT            (0U)
67766 /*! OFLW_BYTES - Number of bytes lost during an overflow event
67767  *  0b00000000..No overflow
67768  *  0b00000001-0b11111111..Total bytes lost during an overflow event
67769  */
67770 #define ISI_CHNL_STS_OFLW_BYTES(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_BYTES_SHIFT)) & ISI_CHNL_STS_OFLW_BYTES_MASK)
67771 #define ISI_CHNL_STS_BUF1_ACTIVE_MASK            (0x100U)
67772 #define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT           (8U)
67773 /*! BUF1_ACTIVE - Current frame being stored in Buffer 1 Address
67774  *  0b0..Buffer 1 Address inactive
67775  *  0b1..Buffer 1 Address in use
67776  */
67777 #define ISI_CHNL_STS_BUF1_ACTIVE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK)
67778 #define ISI_CHNL_STS_BUF2_ACTIVE_MASK            (0x200U)
67779 #define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT           (9U)
67780 /*! BUF2_ACTIVE - Current frame being stored in Buffer 2 Address
67781  *  0b0..Buffer 2 Address inactive
67782  *  0b1..Buffer 2 Address in use
67783  */
67784 #define ISI_CHNL_STS_BUF2_ACTIVE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK)
67785 #define ISI_CHNL_STS_MEM_RD_OFLOW_MASK           (0x400U)
67786 #define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT          (10U)
67787 /*! MEM_RD_OFLOW - Memory read FIFO overflow error status
67788  *  0b0..No overflow occurred during memory read
67789  *  0b1..FIFO overflow occurred during memory read
67790  */
67791 #define ISI_CHNL_STS_MEM_RD_OFLOW(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK)
67792 #define ISI_CHNL_STS_RSVD1_MASK                  (0x3800U)
67793 #define ISI_CHNL_STS_RSVD1_SHIFT                 (11U)
67794 /*! RSVD1 - Reserved field. Reads only zeros.
67795  */
67796 #define ISI_CHNL_STS_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_RSVD1_SHIFT)) & ISI_CHNL_STS_RSVD1_MASK)
67797 #define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK         (0x4000U)
67798 #define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT        (14U)
67799 /*! LATE_VSYNC_ERR - VSYNC timing (Late) error interrupt flag
67800  *  0b0..No error
67801  *  0b1..VSYNC detected later than expected
67802  */
67803 #define ISI_CHNL_STS_LATE_VSYNC_ERR(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK)
67804 #define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK        (0x8000U)
67805 #define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT       (15U)
67806 /*! EARLY_VSYNC_ERR - VSYNC timing (Early) error interrupt flag
67807  *  0b0..No error
67808  *  0b1..VSYNC detected earlier than expected
67809  */
67810 #define ISI_CHNL_STS_EARLY_VSYNC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK)
67811 #define ISI_CHNL_STS_OFLW_Y_BUF_MASK             (0x10000U)
67812 #define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT            (16U)
67813 /*! OFLW_Y_BUF - Overflow in Y/RGB output buffer interrupt flag
67814  *  0b0..No overflow
67815  *  0b1..Overflow has occured in the channel
67816  */
67817 #define ISI_CHNL_STS_OFLW_Y_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK)
67818 #define ISI_CHNL_STS_EXCS_OFLW_Y_BUF_MASK        (0x20000U)
67819 #define ISI_CHNL_STS_EXCS_OFLW_Y_BUF_SHIFT       (17U)
67820 /*! EXCS_OFLW_Y_BUF - Y/RGB output buffer excess overflow interrupt flag
67821  *  0b0..No overflow or overflow condition within recoverable limits
67822  *  0b1..Overflow confition beyond recoverable limits
67823  */
67824 #define ISI_CHNL_STS_EXCS_OFLW_Y_BUF(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_Y_BUF_MASK)
67825 #define ISI_CHNL_STS_OFLW_PANIC_Y_BUF_MASK       (0x40000U)
67826 #define ISI_CHNL_STS_OFLW_PANIC_Y_BUF_SHIFT      (18U)
67827 /*! OFLW_PANIC_Y_BUF - Y/RGB output buffer potential overflow panic alert interrupt flag
67828  *  0b0..Buffer has not crossed the panic threshold limit
67829  *  0b1..Panic threshold limit crossed. Software must take action.
67830  */
67831 #define ISI_CHNL_STS_OFLW_PANIC_Y_BUF(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_Y_BUF_MASK)
67832 #define ISI_CHNL_STS_OFLW_U_BUF_MASK             (0x80000U)
67833 #define ISI_CHNL_STS_OFLW_U_BUF_SHIFT            (19U)
67834 /*! OFLW_U_BUF - Overflow in U output buffer interrupt flag
67835  *  0b0..No overflow
67836  *  0b1..Overflow has occured in the channel
67837  */
67838 #define ISI_CHNL_STS_OFLW_U_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK)
67839 #define ISI_CHNL_STS_EXCS_OFLW_U_BUF_MASK        (0x100000U)
67840 #define ISI_CHNL_STS_EXCS_OFLW_U_BUF_SHIFT       (20U)
67841 /*! EXCS_OFLW_U_BUF - U output buffer excess overflow interrupt flag
67842  *  0b0..No overflow or overflow condition within recoverable limits
67843  *  0b1..Overflow confition beyond recoverable limits
67844  */
67845 #define ISI_CHNL_STS_EXCS_OFLW_U_BUF(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_U_BUF_MASK)
67846 #define ISI_CHNL_STS_OFLW_PANIC_U_BUF_MASK       (0x200000U)
67847 #define ISI_CHNL_STS_OFLW_PANIC_U_BUF_SHIFT      (21U)
67848 /*! OFLW_PANIC_U_BUF - U output buffer potential overflow panic alert interrupt flag
67849  *  0b0..Buffer has not crossed the panic threshold limit
67850  *  0b1..Panic threshold limit crossed. Software must take action.
67851  */
67852 #define ISI_CHNL_STS_OFLW_PANIC_U_BUF(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_U_BUF_MASK)
67853 #define ISI_CHNL_STS_OFLW_V_BUF_MASK             (0x400000U)
67854 #define ISI_CHNL_STS_OFLW_V_BUF_SHIFT            (22U)
67855 /*! OFLW_V_BUF - Overflow in U output buffer interrupt flag
67856  *  0b0..No overflow
67857  *  0b1..Overflow has occured in the channel
67858  */
67859 #define ISI_CHNL_STS_OFLW_V_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK)
67860 #define ISI_CHNL_STS_EXCS_OFLW_V_BUF_MASK        (0x800000U)
67861 #define ISI_CHNL_STS_EXCS_OFLW_V_BUF_SHIFT       (23U)
67862 /*! EXCS_OFLW_V_BUF - V output buffer excess overflow interrupt flag
67863  *  0b0..No overflow or overflow condition within recoverable limits
67864  *  0b1..Overflow confition beyond recoverable limits
67865  */
67866 #define ISI_CHNL_STS_EXCS_OFLW_V_BUF(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_V_BUF_MASK)
67867 #define ISI_CHNL_STS_OFLW_PANIC_V_BUF_MASK       (0x1000000U)
67868 #define ISI_CHNL_STS_OFLW_PANIC_V_BUF_SHIFT      (24U)
67869 /*! OFLW_PANIC_V_BUF - V output buffer potential overflow panic alert interrupt flag
67870  *  0b0..Buffer has not crossed the panic threshold limit
67871  *  0b1..Panic threshold limit crossed. Software must take action.
67872  */
67873 #define ISI_CHNL_STS_OFLW_PANIC_V_BUF(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_V_BUF_MASK)
67874 #define ISI_CHNL_STS_AXI_RD_ERR_MASK             (0x2000000U)
67875 #define ISI_CHNL_STS_AXI_RD_ERR_SHIFT            (25U)
67876 /*! AXI_RD_ERR - AXI Bus read error interrupt flag (Channel 0 only)
67877  *  0b0..No error
67878  *  0b1..Error occured during read
67879  */
67880 #define ISI_CHNL_STS_AXI_RD_ERR(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK)
67881 #define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK           (0x4000000U)
67882 #define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT          (26U)
67883 /*! AXI_WR_ERR_Y - AXI Bus write error interrupt flag for Y/RGB data buffer
67884  *  0b0..No error
67885  *  0b1..Error occured during write
67886  */
67887 #define ISI_CHNL_STS_AXI_WR_ERR_Y(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK)
67888 #define ISI_CHNL_STS_AXI_WR_ERR_U_MASK           (0x8000000U)
67889 #define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT          (27U)
67890 /*! AXI_WR_ERR_U - AXI Bus write error interrupt flag for U data buffer
67891  *  0b0..No error
67892  *  0b1..Error occured during write
67893  */
67894 #define ISI_CHNL_STS_AXI_WR_ERR_U(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK)
67895 #define ISI_CHNL_STS_AXI_WR_ERR_V_MASK           (0x10000000U)
67896 #define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT          (28U)
67897 /*! AXI_WR_ERR_V - AXI Bus write error interrupt flag for V data buffer
67898  *  0b0..No error
67899  *  0b1..Error occured during write
67900  */
67901 #define ISI_CHNL_STS_AXI_WR_ERR_V(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK)
67902 #define ISI_CHNL_STS_FRM_STRD_MASK               (0x20000000U)
67903 #define ISI_CHNL_STS_FRM_STRD_SHIFT              (29U)
67904 /*! FRM_STRD - Frame stored successfully interrupt flag
67905  *  0b0..No frame being received or in progress
67906  *  0b1..One full frame has been received and stored in memory
67907  */
67908 #define ISI_CHNL_STS_FRM_STRD(x)                 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK)
67909 #define ISI_CHNL_STS_LINE_STRD_MASK              (0x40000000U)
67910 #define ISI_CHNL_STS_LINE_STRD_SHIFT             (30U)
67911 /*! LINE_STRD - Line received and stored interrupt flag
67912  *  0b0..No new line received
67913  *  0b1..New line received and stored into memory
67914  */
67915 #define ISI_CHNL_STS_LINE_STRD(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK)
67916 #define ISI_CHNL_STS_MEM_RD_DONE_MASK            (0x80000000U)
67917 #define ISI_CHNL_STS_MEM_RD_DONE_SHIFT           (31U)
67918 /*! MEM_RD_DONE - Memory read complete interrupt flag
67919  *  0b0..Image read from memory not complete or not started
67920  *  0b1..Image read from memory completed
67921  */
67922 #define ISI_CHNL_STS_MEM_RD_DONE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK)
67923 /*! @} */
67924 
67925 /*! @name CHNL_SCALE_FACTOR - Channel Scale Factor Register */
67926 /*! @{ */
67927 #define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK       (0x3FFFU)
67928 #define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT      (0U)
67929 /*! X_SCALE - Horizontal scaling factor
67930  */
67931 #define ISI_CHNL_SCALE_FACTOR_X_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK)
67932 #define ISI_CHNL_SCALE_FACTOR_RSVD1_MASK         (0xC000U)
67933 #define ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT        (14U)
67934 /*! RSVD1 - Reserved field. Reads only zeros
67935  */
67936 #define ISI_CHNL_SCALE_FACTOR_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD1_MASK)
67937 #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK       (0x3FFF0000U)
67938 #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT      (16U)
67939 /*! Y_SCALE - Vertical scaling factor
67940  */
67941 #define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK)
67942 #define ISI_CHNL_SCALE_FACTOR_RSVD0_MASK         (0xC0000000U)
67943 #define ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT        (30U)
67944 /*! RSVD0 - Reserved field. Reads only zeros
67945  */
67946 #define ISI_CHNL_SCALE_FACTOR_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD0_MASK)
67947 /*! @} */
67948 
67949 /*! @name CHNL_SCALE_OFFSET - Channel Scale Offset Register */
67950 /*! @{ */
67951 #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK      (0xFFFU)
67952 #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT     (0U)
67953 /*! X_OFFSET - Horizontal scaling offset
67954  */
67955 #define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK)
67956 #define ISI_CHNL_SCALE_OFFSET_RSVD1_MASK         (0xF000U)
67957 #define ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT        (12U)
67958 /*! RSVD1 - Reserved field. Reads only zeros
67959  */
67960 #define ISI_CHNL_SCALE_OFFSET_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD1_MASK)
67961 #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK      (0xFFF0000U)
67962 #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT     (16U)
67963 /*! Y_OFFSET - Vertical scaling offset
67964  */
67965 #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK)
67966 #define ISI_CHNL_SCALE_OFFSET_RSVD0_MASK         (0xF0000000U)
67967 #define ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT        (28U)
67968 /*! RSVD0 - Reserved field. Reads only zeros
67969  */
67970 #define ISI_CHNL_SCALE_OFFSET_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD0_MASK)
67971 /*! @} */
67972 
67973 /*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate Register */
67974 /*! @{ */
67975 #define ISI_CHNL_CROP_ULC_Y_MASK                 (0xFFFU)
67976 #define ISI_CHNL_CROP_ULC_Y_SHIFT                (0U)
67977 /*! Y - Upper Left Y-coordinate
67978  */
67979 #define ISI_CHNL_CROP_ULC_Y(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK)
67980 #define ISI_CHNL_CROP_ULC_RSVD1_MASK             (0xF000U)
67981 #define ISI_CHNL_CROP_ULC_RSVD1_SHIFT            (12U)
67982 /*! RSVD1 - Reserved field. Reads only zeros
67983  */
67984 #define ISI_CHNL_CROP_ULC_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD1_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD1_MASK)
67985 #define ISI_CHNL_CROP_ULC_X_MASK                 (0xFFF0000U)
67986 #define ISI_CHNL_CROP_ULC_X_SHIFT                (16U)
67987 /*! X - Upper Left X-coordinate
67988  */
67989 #define ISI_CHNL_CROP_ULC_X(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK)
67990 #define ISI_CHNL_CROP_ULC_RSVD0_MASK             (0xF0000000U)
67991 #define ISI_CHNL_CROP_ULC_RSVD0_SHIFT            (28U)
67992 /*! RSVD0 - Reserved field. Reads only zeros
67993  */
67994 #define ISI_CHNL_CROP_ULC_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD0_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD0_MASK)
67995 /*! @} */
67996 
67997 /*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate Register */
67998 /*! @{ */
67999 #define ISI_CHNL_CROP_LRC_Y_MASK                 (0xFFFU)
68000 #define ISI_CHNL_CROP_LRC_Y_SHIFT                (0U)
68001 /*! Y - Lower Right Y-coordinate
68002  */
68003 #define ISI_CHNL_CROP_LRC_Y(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK)
68004 #define ISI_CHNL_CROP_LRC_RSVD1_MASK             (0xF000U)
68005 #define ISI_CHNL_CROP_LRC_RSVD1_SHIFT            (12U)
68006 /*! RSVD1 - Reserved field. Reads only zeros
68007  */
68008 #define ISI_CHNL_CROP_LRC_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD1_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD1_MASK)
68009 #define ISI_CHNL_CROP_LRC_X_MASK                 (0xFFF0000U)
68010 #define ISI_CHNL_CROP_LRC_X_SHIFT                (16U)
68011 /*! X - Lower Right X-coordinate
68012  */
68013 #define ISI_CHNL_CROP_LRC_X(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK)
68014 #define ISI_CHNL_CROP_LRC_RSVD0_MASK             (0xF0000000U)
68015 #define ISI_CHNL_CROP_LRC_RSVD0_SHIFT            (28U)
68016 /*! RSVD0 - Reserved field. Reads only zeros
68017  */
68018 #define ISI_CHNL_CROP_LRC_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD0_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD0_MASK)
68019 /*! @} */
68020 
68021 /*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient Register 0 */
68022 /*! @{ */
68023 #define ISI_CHNL_CSC_COEFF0_A1_MASK              (0x7FFU)
68024 #define ISI_CHNL_CSC_COEFF0_A1_SHIFT             (0U)
68025 /*! A1 - CSC Coefficient A1 value
68026  */
68027 #define ISI_CHNL_CSC_COEFF0_A1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK)
68028 #define ISI_CHNL_CSC_COEFF0_RSVD1_MASK           (0xF800U)
68029 #define ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT          (11U)
68030 /*! RSVD1 - Reserved Field. Reads only zeros
68031  */
68032 #define ISI_CHNL_CSC_COEFF0_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD1_MASK)
68033 #define ISI_CHNL_CSC_COEFF0_A2_MASK              (0x7FF0000U)
68034 #define ISI_CHNL_CSC_COEFF0_A2_SHIFT             (16U)
68035 /*! A2 - CSC Coefficient A2 value
68036  */
68037 #define ISI_CHNL_CSC_COEFF0_A2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK)
68038 #define ISI_CHNL_CSC_COEFF0_RSVD0_MASK           (0xF8000000U)
68039 #define ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT          (27U)
68040 /*! RSVD0 - Reserved Field. Reads only zeros
68041  */
68042 #define ISI_CHNL_CSC_COEFF0_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD0_MASK)
68043 /*! @} */
68044 
68045 /*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient Register 1 */
68046 /*! @{ */
68047 #define ISI_CHNL_CSC_COEFF1_A3_MASK              (0x7FFU)
68048 #define ISI_CHNL_CSC_COEFF1_A3_SHIFT             (0U)
68049 /*! A3 - CSC Coefficient A3 value
68050  */
68051 #define ISI_CHNL_CSC_COEFF1_A3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK)
68052 #define ISI_CHNL_CSC_COEFF1_RSVD1_MASK           (0xF800U)
68053 #define ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT          (11U)
68054 /*! RSVD1 - Reserved Field. Reads only zeros
68055  */
68056 #define ISI_CHNL_CSC_COEFF1_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD1_MASK)
68057 #define ISI_CHNL_CSC_COEFF1_B1_MASK              (0x7FF0000U)
68058 #define ISI_CHNL_CSC_COEFF1_B1_SHIFT             (16U)
68059 /*! B1 - CSC Coefficient B1 value
68060  */
68061 #define ISI_CHNL_CSC_COEFF1_B1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK)
68062 #define ISI_CHNL_CSC_COEFF1_RSVD0_MASK           (0xF8000000U)
68063 #define ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT          (27U)
68064 /*! RSVD0 - Reserved Field. Reads only zeros
68065  */
68066 #define ISI_CHNL_CSC_COEFF1_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD0_MASK)
68067 /*! @} */
68068 
68069 /*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient Register 2 */
68070 /*! @{ */
68071 #define ISI_CHNL_CSC_COEFF2_B2_MASK              (0x7FFU)
68072 #define ISI_CHNL_CSC_COEFF2_B2_SHIFT             (0U)
68073 /*! B2 - CSC Coefficient B2 value
68074  */
68075 #define ISI_CHNL_CSC_COEFF2_B2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK)
68076 #define ISI_CHNL_CSC_COEFF2_RSVD1_MASK           (0xF800U)
68077 #define ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT          (11U)
68078 /*! RSVD1 - Reserved Field. Reads only zeros
68079  */
68080 #define ISI_CHNL_CSC_COEFF2_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD1_MASK)
68081 #define ISI_CHNL_CSC_COEFF2_B3_MASK              (0x7FF0000U)
68082 #define ISI_CHNL_CSC_COEFF2_B3_SHIFT             (16U)
68083 /*! B3 - CSC Coefficient B3 value
68084  */
68085 #define ISI_CHNL_CSC_COEFF2_B3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK)
68086 #define ISI_CHNL_CSC_COEFF2_RSVD0_MASK           (0xF8000000U)
68087 #define ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT          (27U)
68088 /*! RSVD0 - Reserved Field. Reads only zeros
68089  */
68090 #define ISI_CHNL_CSC_COEFF2_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD0_MASK)
68091 /*! @} */
68092 
68093 /*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient Register 3 */
68094 /*! @{ */
68095 #define ISI_CHNL_CSC_COEFF3_C1_MASK              (0x7FFU)
68096 #define ISI_CHNL_CSC_COEFF3_C1_SHIFT             (0U)
68097 /*! C1 - CSC Coefficient C1 value
68098  */
68099 #define ISI_CHNL_CSC_COEFF3_C1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK)
68100 #define ISI_CHNL_CSC_COEFF3_RSVD1_MASK           (0xF800U)
68101 #define ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT          (11U)
68102 /*! RSVD1 - Reserved Field. Reads only zeros
68103  */
68104 #define ISI_CHNL_CSC_COEFF3_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD1_MASK)
68105 #define ISI_CHNL_CSC_COEFF3_C2_MASK              (0x7FF0000U)
68106 #define ISI_CHNL_CSC_COEFF3_C2_SHIFT             (16U)
68107 /*! C2 - CSC Coefficient C2 value
68108  */
68109 #define ISI_CHNL_CSC_COEFF3_C2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK)
68110 #define ISI_CHNL_CSC_COEFF3_RSVD0_MASK           (0xF8000000U)
68111 #define ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT          (27U)
68112 /*! RSVD0 - Reserved Field. Reads only zeros
68113  */
68114 #define ISI_CHNL_CSC_COEFF3_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD0_MASK)
68115 /*! @} */
68116 
68117 /*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient Register 4 */
68118 /*! @{ */
68119 #define ISI_CHNL_CSC_COEFF4_C3_MASK              (0x7FFU)
68120 #define ISI_CHNL_CSC_COEFF4_C3_SHIFT             (0U)
68121 /*! C3 - CSC Coefficient C3 value
68122  */
68123 #define ISI_CHNL_CSC_COEFF4_C3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK)
68124 #define ISI_CHNL_CSC_COEFF4_RSVD1_MASK           (0xF800U)
68125 #define ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT          (11U)
68126 /*! RSVD1 - Reserved Field. Reads only zeros
68127  */
68128 #define ISI_CHNL_CSC_COEFF4_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD1_MASK)
68129 #define ISI_CHNL_CSC_COEFF4_D1_MASK              (0x1FF0000U)
68130 #define ISI_CHNL_CSC_COEFF4_D1_SHIFT             (16U)
68131 /*! D1 - CSC Coefficient D1 value
68132  */
68133 #define ISI_CHNL_CSC_COEFF4_D1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK)
68134 #define ISI_CHNL_CSC_COEFF4_RSVD0_MASK           (0xFE000000U)
68135 #define ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT          (25U)
68136 /*! RSVD0 - Reserved Field. Reads only zeros
68137  */
68138 #define ISI_CHNL_CSC_COEFF4_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD0_MASK)
68139 /*! @} */
68140 
68141 /*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient Register 5 */
68142 /*! @{ */
68143 #define ISI_CHNL_CSC_COEFF5_D2_MASK              (0x1FFU)
68144 #define ISI_CHNL_CSC_COEFF5_D2_SHIFT             (0U)
68145 /*! D2 - CSC Coefficient D2 value
68146  */
68147 #define ISI_CHNL_CSC_COEFF5_D2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK)
68148 #define ISI_CHNL_CSC_COEFF5_RSVD1_MASK           (0xFE00U)
68149 #define ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT          (9U)
68150 /*! RSVD1 - Reserved Field. Reads only zeros
68151  */
68152 #define ISI_CHNL_CSC_COEFF5_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD1_MASK)
68153 #define ISI_CHNL_CSC_COEFF5_D3_MASK              (0x1FF0000U)
68154 #define ISI_CHNL_CSC_COEFF5_D3_SHIFT             (16U)
68155 /*! D3 - CSC Coefficient D3 value
68156  */
68157 #define ISI_CHNL_CSC_COEFF5_D3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK)
68158 #define ISI_CHNL_CSC_COEFF5_RSVD0_MASK           (0xFE000000U)
68159 #define ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT          (25U)
68160 /*! RSVD0 - Reserved Field. Reads only zeros
68161  */
68162 #define ISI_CHNL_CSC_COEFF5_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD0_MASK)
68163 /*! @} */
68164 
68165 /*! @name CHNL_ROI_ALPHA - Channel Alpha Value Register for Region of Interest 0..Channel Alpha Value Register for Region of Interest 3 */
68166 /*! @{ */
68167 #define ISI_CHNL_ROI_ALPHA_RSVD1_MASK            (0xFFFFU)
68168 #define ISI_CHNL_ROI_ALPHA_RSVD1_SHIFT           (0U)
68169 /*! RSVD1 - Reserved field. Reads only zeros
68170  */
68171 #define ISI_CHNL_ROI_ALPHA_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_ALPHA_RSVD1_MASK)
68172 #define ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK         (0x10000U)
68173 #define ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT        (16U)
68174 /*! ALPHA_EN - Alpha value insertion enable
68175  *  0b0..Alpha value insertion is disabled
68176  *  0b1..Alpha value insertion is enabled
68177  */
68178 #define ISI_CHNL_ROI_ALPHA_ALPHA_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK)
68179 #define ISI_CHNL_ROI_ALPHA_RSVD0_MASK            (0xFE0000U)
68180 #define ISI_CHNL_ROI_ALPHA_RSVD0_SHIFT           (17U)
68181 /*! RSVD0 - Reserved field. Reads only zeros
68182  */
68183 #define ISI_CHNL_ROI_ALPHA_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_ALPHA_RSVD0_MASK)
68184 #define ISI_CHNL_ROI_ALPHA_ALPHA_MASK            (0xFF000000U)
68185 #define ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT           (24U)
68186 /*! ALPHA - Alpha Value to be inserted with image
68187  */
68188 #define ISI_CHNL_ROI_ALPHA_ALPHA(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_MASK)
68189 /*! @} */
68190 
68191 /* The count of ISI_CHNL_ROI_ALPHA */
68192 #define ISI_CHNL_ROI_ALPHA_COUNT                 (4U)
68193 
68194 /*! @name CHNL_ROI_ULC - Channel Upper Left Coordinate Register for Region of Interest 0..Channel Upper Left Coordinate Register for Region of Interest 3 */
68195 /*! @{ */
68196 #define ISI_CHNL_ROI_ULC_Y_MASK                  (0xFFFU)
68197 #define ISI_CHNL_ROI_ULC_Y_SHIFT                 (0U)
68198 /*! Y - Upper Left Y-coordinate
68199  */
68200 #define ISI_CHNL_ROI_ULC_Y(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_Y_SHIFT)) & ISI_CHNL_ROI_ULC_Y_MASK)
68201 #define ISI_CHNL_ROI_ULC_RSVD1_MASK              (0xF000U)
68202 #define ISI_CHNL_ROI_ULC_RSVD1_SHIFT             (12U)
68203 /*! RSVD1 - Reserved field. Reads only zeros
68204  */
68205 #define ISI_CHNL_ROI_ULC_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_ULC_RSVD1_MASK)
68206 #define ISI_CHNL_ROI_ULC_X_MASK                  (0xFFF0000U)
68207 #define ISI_CHNL_ROI_ULC_X_SHIFT                 (16U)
68208 /*! X - Upper Left X-coordinate
68209  */
68210 #define ISI_CHNL_ROI_ULC_X(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_X_SHIFT)) & ISI_CHNL_ROI_ULC_X_MASK)
68211 #define ISI_CHNL_ROI_ULC_RSVD0_MASK              (0xF0000000U)
68212 #define ISI_CHNL_ROI_ULC_RSVD0_SHIFT             (28U)
68213 /*! RSVD0 - Reserved field. Reads only zeros
68214  */
68215 #define ISI_CHNL_ROI_ULC_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_ULC_RSVD0_MASK)
68216 /*! @} */
68217 
68218 /* The count of ISI_CHNL_ROI_ULC */
68219 #define ISI_CHNL_ROI_ULC_COUNT                   (4U)
68220 
68221 /*! @name CHNL_ROI_LRC - Channel Lower Right Coordinate Register for Region of Interest 0..Channel Lower Right Coordinate Register for Region of Interest 3 */
68222 /*! @{ */
68223 #define ISI_CHNL_ROI_LRC_Y_MASK                  (0xFFFU)
68224 #define ISI_CHNL_ROI_LRC_Y_SHIFT                 (0U)
68225 /*! Y - Lower Right Y-coordinate
68226  */
68227 #define ISI_CHNL_ROI_LRC_Y(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_Y_SHIFT)) & ISI_CHNL_ROI_LRC_Y_MASK)
68228 #define ISI_CHNL_ROI_LRC_RSVD1_MASK              (0xF000U)
68229 #define ISI_CHNL_ROI_LRC_RSVD1_SHIFT             (12U)
68230 /*! RSVD1 - Reserved field. Reads only zeros
68231  */
68232 #define ISI_CHNL_ROI_LRC_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_LRC_RSVD1_MASK)
68233 #define ISI_CHNL_ROI_LRC_X_MASK                  (0xFFF0000U)
68234 #define ISI_CHNL_ROI_LRC_X_SHIFT                 (16U)
68235 /*! X - Lower Right X-coordinate
68236  */
68237 #define ISI_CHNL_ROI_LRC_X(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_X_SHIFT)) & ISI_CHNL_ROI_LRC_X_MASK)
68238 #define ISI_CHNL_ROI_LRC_RSVD0_MASK              (0xF0000000U)
68239 #define ISI_CHNL_ROI_LRC_RSVD0_SHIFT             (28U)
68240 /*! RSVD0 - Reserved field. Reads only zeros
68241  */
68242 #define ISI_CHNL_ROI_LRC_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_LRC_RSVD0_MASK)
68243 /*! @} */
68244 
68245 /* The count of ISI_CHNL_ROI_LRC */
68246 #define ISI_CHNL_ROI_LRC_COUNT                   (4U)
68247 
68248 /*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */
68249 /*! @{ */
68250 #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK       (0xFFFFFFFFU)
68251 #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT      (0U)
68252 /*! ADDR - Starting address for the RGB or Y (luma) memory location
68253  */
68254 #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK)
68255 /*! @} */
68256 
68257 /*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
68258 /*! @{ */
68259 #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK       (0xFFFFFFFFU)
68260 #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT      (0U)
68261 /*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location
68262  */
68263 #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK)
68264 /*! @} */
68265 
68266 /*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */
68267 /*! @{ */
68268 #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK       (0xFFFFFFFFU)
68269 #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT      (0U)
68270 /*! ADDR - Starting address for the V/Cr memory location
68271  */
68272 #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK)
68273 /*! @} */
68274 
68275 /*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */
68276 /*! @{ */
68277 #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK   (0xFFFFU)
68278 #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT  (0U)
68279 /*! LINE_PITCH - Output Buffer Line Pitch
68280  */
68281 #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x)     (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK)
68282 /*! @} */
68283 
68284 /*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */
68285 /*! @{ */
68286 #define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK           (0xFFFFFFFFU)
68287 #define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT          (0U)
68288 #define ISI_CHNL_IN_BUF_ADDR_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK)
68289 /*! @} */
68290 
68291 /*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */
68292 /*! @{ */
68293 #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK    (0xFFFFU)
68294 #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT   (0U)
68295 /*! LINE_PITCH - Line Pitch
68296  */
68297 #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK)
68298 #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK     (0xFFFF0000U)
68299 #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT    (16U)
68300 /*! FRM_PITCH - Frame Pitch
68301  */
68302 #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK)
68303 /*! @} */
68304 
68305 /*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */
68306 /*! @{ */
68307 #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK       (0x1U)
68308 #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT      (0U)
68309 /*! READ_MEM - Initiate read from memory
68310  *  0b0..No reads from memory done
68311  *  0b1..Reads from memory initiated
68312  */
68313 #define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK)
68314 #define ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK          (0xFFFFFFEU)
68315 #define ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT         (1U)
68316 /*! RSVD0 - Reserved field. Reads only zeros
68317  */
68318 #define ISI_CHNL_MEM_RD_CTRL_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK)
68319 #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK       (0xF0000000U)
68320 #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT      (28U)
68321 /*! IMG_TYPE - Input image format
68322  *  0b0000..BGR8P - BGR format with 8-bits per color component (packed into 32-bit DWORD)
68323  *  0b0001..RGB8P - RGB format with 8-bits per color component (packed into 32-bit DWORD)
68324  *  0b0010..XRGB8 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
68325  *  0b0011..RGBX8 - RGB format with 8-bits per color component (unpacked and MSBalinged in 32-bit DWORD)
68326  *  0b0100..XBGR8 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
68327  *  0b0101..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 32-bit DWORD)
68328  *  0b0110..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component
68329  *  0b0111..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component
68330  *  0b1000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
68331  *  0b1001..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
68332  *  0b1010..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit WORD)
68333  *  0b1011..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
68334  *  0b1100..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
68335  *  0b1101..YUV422_1P8P with 8-bits per color component; 1-plane YUV interleaved packed bytes
68336  *  0b1110..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
68337  *  0b1111..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved packed bytes (4 MSBs waste bits in 16-bit WORD)
68338  */
68339 #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK)
68340 /*! @} */
68341 
68342 /*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */
68343 /*! @{ */
68344 #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK       (0xFFFFFFFFU)
68345 #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT      (0U)
68346 /*! ADDR - Starting address for the RGB or Y (luma) memory location
68347  */
68348 #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK)
68349 /*! @} */
68350 
68351 /*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */
68352 /*! @{ */
68353 #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK       (0xFFFFFFFFU)
68354 #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT      (0U)
68355 /*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location
68356  */
68357 #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK)
68358 /*! @} */
68359 
68360 /*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */
68361 /*! @{ */
68362 #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK       (0xFFFFFFFFU)
68363 #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT      (0U)
68364 /*! ADDR - Starting address for the V/Cr memory location
68365  */
68366 #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK)
68367 /*! @} */
68368 
68369 /*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */
68370 /*! @{ */
68371 #define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK          (0x1FFFU)
68372 #define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT         (0U)
68373 /*! WIDTH - Scaled image width (pixels)
68374  */
68375 #define ISI_CHNL_SCL_IMG_CFG_WIDTH(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK)
68376 #define ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK          (0xE000U)
68377 #define ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT         (13U)
68378 /*! RSVD0 - Reserved field. Reads only zeros.
68379  */
68380 #define ISI_CHNL_SCL_IMG_CFG_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK)
68381 #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK         (0x1FFF0000U)
68382 #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT        (16U)
68383 /*! HEIGHT - Scaled image height (lines)
68384  */
68385 #define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK)
68386 #define ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK          (0xE0000000U)
68387 #define ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT         (29U)
68388 /*! RSVD1 - Reserved field. Reads only zeros.
68389  */
68390 #define ISI_CHNL_SCL_IMG_CFG_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK)
68391 /*! @} */
68392 
68393 
68394 /*!
68395  * @}
68396  */ /* end of group ISI_Register_Masks */
68397 
68398 
68399 /* ISI - Peripheral instance base addresses */
68400 /** Peripheral IMAGING__ISI0 base address */
68401 #define IMAGING__ISI0_BASE                       (0x58100000u)
68402 /** Peripheral IMAGING__ISI0 base pointer */
68403 #define IMAGING__ISI0                            ((ISI_Type *)IMAGING__ISI0_BASE)
68404 /** Peripheral IMAGING__ISI1 base address */
68405 #define IMAGING__ISI1_BASE                       (0x58110000u)
68406 /** Peripheral IMAGING__ISI1 base pointer */
68407 #define IMAGING__ISI1                            ((ISI_Type *)IMAGING__ISI1_BASE)
68408 /** Peripheral IMAGING__ISI2 base address */
68409 #define IMAGING__ISI2_BASE                       (0x58120000u)
68410 /** Peripheral IMAGING__ISI2 base pointer */
68411 #define IMAGING__ISI2                            ((ISI_Type *)IMAGING__ISI2_BASE)
68412 /** Peripheral IMAGING__ISI3 base address */
68413 #define IMAGING__ISI3_BASE                       (0x58130000u)
68414 /** Peripheral IMAGING__ISI3 base pointer */
68415 #define IMAGING__ISI3                            ((ISI_Type *)IMAGING__ISI3_BASE)
68416 /** Peripheral IMAGING__ISI4 base address */
68417 #define IMAGING__ISI4_BASE                       (0x58140000u)
68418 /** Peripheral IMAGING__ISI4 base pointer */
68419 #define IMAGING__ISI4                            ((ISI_Type *)IMAGING__ISI4_BASE)
68420 /** Peripheral IMAGING__ISI5 base address */
68421 #define IMAGING__ISI5_BASE                       (0x58150000u)
68422 /** Peripheral IMAGING__ISI5 base pointer */
68423 #define IMAGING__ISI5                            ((ISI_Type *)IMAGING__ISI5_BASE)
68424 /** Array initializer of ISI peripheral base addresses */
68425 #define ISI_BASE_ADDRS                           { IMAGING__ISI0_BASE, IMAGING__ISI1_BASE, IMAGING__ISI2_BASE, IMAGING__ISI3_BASE, IMAGING__ISI4_BASE, IMAGING__ISI5_BASE }
68426 /** Array initializer of ISI peripheral base pointers */
68427 #define ISI_BASE_PTRS                            { IMAGING__ISI0, IMAGING__ISI1, IMAGING__ISI2, IMAGING__ISI3, IMAGING__ISI4, IMAGING__ISI5 }
68428 /** Interrupt vectors for the ISI peripheral type */
68429 #define ISI_IRQS                                 { IMAGING_PDMA_STREAM0_INT_IRQn, IMAGING_PDMA_STREAM1_INT_IRQn, IMAGING_PDMA_STREAM2_INT_IRQn, IMAGING_PDMA_STREAM3_INT_IRQn, IMAGING_PDMA_STREAM4_INT_IRQn, IMAGING_PDMA_STREAM5_INT_IRQn }
68430 
68431 /*!
68432  * @}
68433  */ /* end of group ISI_Peripheral_Access_Layer */
68434 
68435 
68436 /* ----------------------------------------------------------------------------
68437    -- JPEG_DEC Peripheral Access Layer
68438    ---------------------------------------------------------------------------- */
68439 
68440 /*!
68441  * @addtogroup JPEG_DEC_Peripheral_Access_Layer JPEG_DEC Peripheral Access Layer
68442  * @{
68443  */
68444 
68445 /** JPEG_DEC - Register Layout Typedef */
68446 typedef struct {
68447   union {                                          /* offset: 0x0 */
68448     struct {                                         /* offset: 0x0 */
68449            uint8_t RESERVED_0[52];
68450       __IO uint32_t CTRL;                              /**< Control Register, offset: 0x34 */
68451     } CONTROL;
68452     struct {                                         /* offset: 0x0 */
68453       __I  uint32_t STATUS_0;                          /**< Status 0 Register, offset: 0x0 */
68454       __I  uint32_t STATUS_1;                          /**< Status 1 Register, offset: 0x4 */
68455       __I  uint32_t STATUS_2;                          /**< Status 2 Register, offset: 0x8 */
68456       __I  uint32_t STATUS_3;                          /**< Status 3 Register, offset: 0xC */
68457       __I  uint32_t STATUS_4;                          /**< Status 4 Register, offset: 0x10 */
68458       __I  uint32_t STATUS_5;                          /**< Status 5 Register, offset: 0x14 */
68459       __I  uint32_t STATUS_6;                          /**< Status 6 Register, offset: 0x18 */
68460       __I  uint32_t STATUS_7;                          /**< Status 7 Register, offset: 0x1C */
68461       __I  uint32_t STATUS_8;                          /**< Status 8 Register, offset: 0x20 */
68462       __I  uint32_t STATUS_9;                          /**< Status 9 Register, offset: 0x24 */
68463       __I  uint32_t STATUS_10;                         /**< Status 10 Register, offset: 0x28 */
68464       __I  uint32_t STATUS_11;                         /**< Status 11 Register, offset: 0x2C */
68465       __I  uint32_t STATUS_12;                         /**< Status 12 Register, offset: 0x30 */
68466     } STATUS;
68467   };
68468 } JPEG_DEC_Type;
68469 
68470 /* ----------------------------------------------------------------------------
68471    -- JPEG_DEC Register Masks
68472    ---------------------------------------------------------------------------- */
68473 
68474 /*!
68475  * @addtogroup JPEG_DEC_Register_Masks JPEG_DEC Register Masks
68476  * @{
68477  */
68478 
68479 /*! @name CTRL - Control Register */
68480 /*! @{ */
68481 #define JPEG_DEC_CTRL_LP_MASK                    (0x1U)
68482 #define JPEG_DEC_CTRL_LP_SHIFT                   (0U)
68483 /*! LP - Low Power
68484  */
68485 #define JPEG_DEC_CTRL_LP(x)                      (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_CTRL_LP_SHIFT)) & JPEG_DEC_CTRL_LP_MASK)
68486 #define JPEG_DEC_CTRL_SWR_MASK                   (0x2U)
68487 #define JPEG_DEC_CTRL_SWR_SHIFT                  (1U)
68488 /*! SWR - Soft reset
68489  */
68490 #define JPEG_DEC_CTRL_SWR(x)                     (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_CTRL_SWR_SHIFT)) & JPEG_DEC_CTRL_SWR_MASK)
68491 #define JPEG_DEC_CTRL_GO_MASK                    (0x4U)
68492 #define JPEG_DEC_CTRL_GO_SHIFT                   (2U)
68493 /*! GO - Low Power
68494  */
68495 #define JPEG_DEC_CTRL_GO(x)                      (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_CTRL_GO_SHIFT)) & JPEG_DEC_CTRL_GO_MASK)
68496 /*! @} */
68497 
68498 /*! @name STATUS_0 - Status 0 Register */
68499 /*! @{ */
68500 #define JPEG_DEC_STATUS_0_X_MASK                 (0xFFFFU)
68501 #define JPEG_DEC_STATUS_0_X_SHIFT                (0U)
68502 /*! X - X
68503  */
68504 #define JPEG_DEC_STATUS_0_X(x)                   (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_0_X_SHIFT)) & JPEG_DEC_STATUS_0_X_MASK)
68505 /*! @} */
68506 
68507 /*! @name STATUS_1 - Status 1 Register */
68508 /*! @{ */
68509 #define JPEG_DEC_STATUS_1_Y_MASK                 (0xFFFFU)
68510 #define JPEG_DEC_STATUS_1_Y_SHIFT                (0U)
68511 /*! Y - Y
68512  */
68513 #define JPEG_DEC_STATUS_1_Y(x)                   (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_1_Y_SHIFT)) & JPEG_DEC_STATUS_1_Y_MASK)
68514 /*! @} */
68515 
68516 /*! @name STATUS_2 - Status 2 Register */
68517 /*! @{ */
68518 #define JPEG_DEC_STATUS_2_HMCU_MASK              (0xFFFFU)
68519 #define JPEG_DEC_STATUS_2_HMCU_SHIFT             (0U)
68520 /*! HMCU - HMCU
68521  */
68522 #define JPEG_DEC_STATUS_2_HMCU(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_2_HMCU_SHIFT)) & JPEG_DEC_STATUS_2_HMCU_MASK)
68523 /*! @} */
68524 
68525 /*! @name STATUS_3 - Status 3 Register */
68526 /*! @{ */
68527 #define JPEG_DEC_STATUS_3_VMCU_MASK              (0xFFFFU)
68528 #define JPEG_DEC_STATUS_3_VMCU_SHIFT             (0U)
68529 /*! VMCU - VMCU
68530  */
68531 #define JPEG_DEC_STATUS_3_VMCU(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_3_VMCU_SHIFT)) & JPEG_DEC_STATUS_3_VMCU_MASK)
68532 /*! @} */
68533 
68534 /*! @name STATUS_4 - Status 4 Register */
68535 /*! @{ */
68536 #define JPEG_DEC_STATUS_4_Tq0_MASK               (0x3U)
68537 #define JPEG_DEC_STATUS_4_Tq0_SHIFT              (0U)
68538 /*! Tq0 - Tq0
68539  */
68540 #define JPEG_DEC_STATUS_4_Tq0(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_4_Tq0_SHIFT)) & JPEG_DEC_STATUS_4_Tq0_MASK)
68541 #define JPEG_DEC_STATUS_4_V0_MASK                (0x1CU)
68542 #define JPEG_DEC_STATUS_4_V0_SHIFT               (2U)
68543 /*! V0 - V0
68544  */
68545 #define JPEG_DEC_STATUS_4_V0(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_4_V0_SHIFT)) & JPEG_DEC_STATUS_4_V0_MASK)
68546 #define JPEG_DEC_STATUS_4_H0_MASK                (0xE0U)
68547 #define JPEG_DEC_STATUS_4_H0_SHIFT               (5U)
68548 /*! H0 - H0
68549  */
68550 #define JPEG_DEC_STATUS_4_H0(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_4_H0_SHIFT)) & JPEG_DEC_STATUS_4_H0_MASK)
68551 #define JPEG_DEC_STATUS_4_C0_MASK                (0xFF00U)
68552 #define JPEG_DEC_STATUS_4_C0_SHIFT               (8U)
68553 /*! C0 - C0
68554  */
68555 #define JPEG_DEC_STATUS_4_C0(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_4_C0_SHIFT)) & JPEG_DEC_STATUS_4_C0_MASK)
68556 /*! @} */
68557 
68558 /*! @name STATUS_5 - Status 5 Register */
68559 /*! @{ */
68560 #define JPEG_DEC_STATUS_5_Tq1_MASK               (0x3U)
68561 #define JPEG_DEC_STATUS_5_Tq1_SHIFT              (0U)
68562 /*! Tq1 - Tq1
68563  */
68564 #define JPEG_DEC_STATUS_5_Tq1(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_5_Tq1_SHIFT)) & JPEG_DEC_STATUS_5_Tq1_MASK)
68565 #define JPEG_DEC_STATUS_5_V1_MASK                (0x1CU)
68566 #define JPEG_DEC_STATUS_5_V1_SHIFT               (2U)
68567 /*! V1 - V1
68568  */
68569 #define JPEG_DEC_STATUS_5_V1(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_5_V1_SHIFT)) & JPEG_DEC_STATUS_5_V1_MASK)
68570 #define JPEG_DEC_STATUS_5_H1_MASK                (0xE0U)
68571 #define JPEG_DEC_STATUS_5_H1_SHIFT               (5U)
68572 /*! H1 - H1
68573  */
68574 #define JPEG_DEC_STATUS_5_H1(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_5_H1_SHIFT)) & JPEG_DEC_STATUS_5_H1_MASK)
68575 #define JPEG_DEC_STATUS_5_C1_MASK                (0xFF00U)
68576 #define JPEG_DEC_STATUS_5_C1_SHIFT               (8U)
68577 /*! C1 - C1
68578  */
68579 #define JPEG_DEC_STATUS_5_C1(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_5_C1_SHIFT)) & JPEG_DEC_STATUS_5_C1_MASK)
68580 /*! @} */
68581 
68582 /*! @name STATUS_6 - Status 6 Register */
68583 /*! @{ */
68584 #define JPEG_DEC_STATUS_6_Tq2_MASK               (0x3U)
68585 #define JPEG_DEC_STATUS_6_Tq2_SHIFT              (0U)
68586 /*! Tq2 - Tq2
68587  */
68588 #define JPEG_DEC_STATUS_6_Tq2(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_6_Tq2_SHIFT)) & JPEG_DEC_STATUS_6_Tq2_MASK)
68589 #define JPEG_DEC_STATUS_6_V2_MASK                (0x1CU)
68590 #define JPEG_DEC_STATUS_6_V2_SHIFT               (2U)
68591 /*! V2 - V2
68592  */
68593 #define JPEG_DEC_STATUS_6_V2(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_6_V2_SHIFT)) & JPEG_DEC_STATUS_6_V2_MASK)
68594 #define JPEG_DEC_STATUS_6_H2_MASK                (0xE0U)
68595 #define JPEG_DEC_STATUS_6_H2_SHIFT               (5U)
68596 /*! H2 - H2
68597  */
68598 #define JPEG_DEC_STATUS_6_H2(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_6_H2_SHIFT)) & JPEG_DEC_STATUS_6_H2_MASK)
68599 #define JPEG_DEC_STATUS_6_C2_MASK                (0xFF00U)
68600 #define JPEG_DEC_STATUS_6_C2_SHIFT               (8U)
68601 /*! C2 - C2
68602  */
68603 #define JPEG_DEC_STATUS_6_C2(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_6_C2_SHIFT)) & JPEG_DEC_STATUS_6_C2_MASK)
68604 /*! @} */
68605 
68606 /*! @name STATUS_7 - Status 7 Register */
68607 /*! @{ */
68608 #define JPEG_DEC_STATUS_7_Tq3_MASK               (0x3U)
68609 #define JPEG_DEC_STATUS_7_Tq3_SHIFT              (0U)
68610 /*! Tq3 - Tq3
68611  */
68612 #define JPEG_DEC_STATUS_7_Tq3(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_7_Tq3_SHIFT)) & JPEG_DEC_STATUS_7_Tq3_MASK)
68613 #define JPEG_DEC_STATUS_7_V3_MASK                (0x1CU)
68614 #define JPEG_DEC_STATUS_7_V3_SHIFT               (2U)
68615 /*! V3 - V3
68616  */
68617 #define JPEG_DEC_STATUS_7_V3(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_7_V3_SHIFT)) & JPEG_DEC_STATUS_7_V3_MASK)
68618 #define JPEG_DEC_STATUS_7_H3_MASK                (0xE0U)
68619 #define JPEG_DEC_STATUS_7_H3_SHIFT               (5U)
68620 /*! H3 - H3
68621  */
68622 #define JPEG_DEC_STATUS_7_H3(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_7_H3_SHIFT)) & JPEG_DEC_STATUS_7_H3_MASK)
68623 #define JPEG_DEC_STATUS_7_C3_MASK                (0xFF00U)
68624 #define JPEG_DEC_STATUS_7_C3_SHIFT               (8U)
68625 /*! C3 - C3
68626  */
68627 #define JPEG_DEC_STATUS_7_C3(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_7_C3_SHIFT)) & JPEG_DEC_STATUS_7_C3_MASK)
68628 /*! @} */
68629 
68630 /*! @name STATUS_8 - Status 8 Register */
68631 /*! @{ */
68632 #define JPEG_DEC_STATUS_8_Nf_MASK                (0xFFU)
68633 #define JPEG_DEC_STATUS_8_Nf_SHIFT               (0U)
68634 /*! Nf - Nf
68635  */
68636 #define JPEG_DEC_STATUS_8_Nf(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_8_Nf_SHIFT)) & JPEG_DEC_STATUS_8_Nf_MASK)
68637 #define JPEG_DEC_STATUS_8_P_MASK                 (0xFF00U)
68638 #define JPEG_DEC_STATUS_8_P_SHIFT                (8U)
68639 /*! P - P
68640  */
68641 #define JPEG_DEC_STATUS_8_P(x)                   (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_8_P_SHIFT)) & JPEG_DEC_STATUS_8_P_MASK)
68642 /*! @} */
68643 
68644 /*! @name STATUS_9 - Status 9 Register */
68645 /*! @{ */
68646 #define JPEG_DEC_STATUS_9_DRI_MASK               (0xFFFFU)
68647 #define JPEG_DEC_STATUS_9_DRI_SHIFT              (0U)
68648 /*! DRI - DRI
68649  */
68650 #define JPEG_DEC_STATUS_9_DRI(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_9_DRI_SHIFT)) & JPEG_DEC_STATUS_9_DRI_MASK)
68651 /*! @} */
68652 
68653 /*! @name STATUS_10 - Status 10 Register */
68654 /*! @{ */
68655 #define JPEG_DEC_STATUS_10_Ns_MASK               (0xFU)
68656 #define JPEG_DEC_STATUS_10_Ns_SHIFT              (0U)
68657 /*! Ns - Ns
68658  */
68659 #define JPEG_DEC_STATUS_10_Ns(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_10_Ns_SHIFT)) & JPEG_DEC_STATUS_10_Ns_MASK)
68660 #define JPEG_DEC_STATUS_10_NBMCU_MASK            (0xF0U)
68661 #define JPEG_DEC_STATUS_10_NBMCU_SHIFT           (4U)
68662 /*! NBMCU - NBMCU
68663  */
68664 #define JPEG_DEC_STATUS_10_NBMCU(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_10_NBMCU_SHIFT)) & JPEG_DEC_STATUS_10_NBMCU_MASK)
68665 #define JPEG_DEC_STATUS_10_Vmax_MASK             (0xF00U)
68666 #define JPEG_DEC_STATUS_10_Vmax_SHIFT            (8U)
68667 /*! Vmax - Vmax
68668  */
68669 #define JPEG_DEC_STATUS_10_Vmax(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_10_Vmax_SHIFT)) & JPEG_DEC_STATUS_10_Vmax_MASK)
68670 #define JPEG_DEC_STATUS_10_Hmax_MASK             (0xF000U)
68671 #define JPEG_DEC_STATUS_10_Hmax_SHIFT            (12U)
68672 /*! Hmax - Hmax
68673  */
68674 #define JPEG_DEC_STATUS_10_Hmax(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_10_Hmax_SHIFT)) & JPEG_DEC_STATUS_10_Hmax_MASK)
68675 /*! @} */
68676 
68677 /*! @name STATUS_11 - Status 11 Register */
68678 /*! @{ */
68679 #define JPEG_DEC_STATUS_11_VHS0_MASK             (0xFU)
68680 #define JPEG_DEC_STATUS_11_VHS0_SHIFT            (0U)
68681 /*! VHS0 - VHS0
68682  */
68683 #define JPEG_DEC_STATUS_11_VHS0(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_11_VHS0_SHIFT)) & JPEG_DEC_STATUS_11_VHS0_MASK)
68684 #define JPEG_DEC_STATUS_11_VHS1_MASK             (0xF0U)
68685 #define JPEG_DEC_STATUS_11_VHS1_SHIFT            (4U)
68686 /*! VHS1 - VHS1
68687  */
68688 #define JPEG_DEC_STATUS_11_VHS1(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_11_VHS1_SHIFT)) & JPEG_DEC_STATUS_11_VHS1_MASK)
68689 #define JPEG_DEC_STATUS_11_VHS2_MASK             (0xF00U)
68690 #define JPEG_DEC_STATUS_11_VHS2_SHIFT            (8U)
68691 /*! VHS2 - VHS2
68692  */
68693 #define JPEG_DEC_STATUS_11_VHS2(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_11_VHS2_SHIFT)) & JPEG_DEC_STATUS_11_VHS2_MASK)
68694 #define JPEG_DEC_STATUS_11_VHS3_MASK             (0xF000U)
68695 #define JPEG_DEC_STATUS_11_VHS3_SHIFT            (12U)
68696 /*! VHS3 - VHS3
68697  */
68698 #define JPEG_DEC_STATUS_11_VHS3(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_11_VHS3_SHIFT)) & JPEG_DEC_STATUS_11_VHS3_MASK)
68699 /*! @} */
68700 
68701 /*! @name STATUS_12 - Status 12 Register */
68702 /*! @{ */
68703 #define JPEG_DEC_STATUS_12_COM_E_MASK            (0x1U)
68704 #define JPEG_DEC_STATUS_12_COM_E_SHIFT           (0U)
68705 /*! COM_E - COM_E
68706  */
68707 #define JPEG_DEC_STATUS_12_COM_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_COM_E_SHIFT)) & JPEG_DEC_STATUS_12_COM_E_MASK)
68708 #define JPEG_DEC_STATUS_12_APPn_E_MASK           (0x2U)
68709 #define JPEG_DEC_STATUS_12_APPn_E_SHIFT          (1U)
68710 /*! APPn_E - APPn_E
68711  */
68712 #define JPEG_DEC_STATUS_12_APPn_E(x)             (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_APPn_E_SHIFT)) & JPEG_DEC_STATUS_12_APPn_E_MASK)
68713 #define JPEG_DEC_STATUS_12_DRI_E_MASK            (0x4U)
68714 #define JPEG_DEC_STATUS_12_DRI_E_SHIFT           (2U)
68715 /*! DRI_E - DRI_E
68716  */
68717 #define JPEG_DEC_STATUS_12_DRI_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_DRI_E_SHIFT)) & JPEG_DEC_STATUS_12_DRI_E_MASK)
68718 #define JPEG_DEC_STATUS_12_DNL_E_MASK            (0x8U)
68719 #define JPEG_DEC_STATUS_12_DNL_E_SHIFT           (3U)
68720 /*! DNL_E - DNL_E
68721  */
68722 #define JPEG_DEC_STATUS_12_DNL_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_DNL_E_SHIFT)) & JPEG_DEC_STATUS_12_DNL_E_MASK)
68723 #define JPEG_DEC_STATUS_12_DHT_E_MASK            (0x10U)
68724 #define JPEG_DEC_STATUS_12_DHT_E_SHIFT           (4U)
68725 /*! DHT_E - DHT_E
68726  */
68727 #define JPEG_DEC_STATUS_12_DHT_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_DHT_E_SHIFT)) & JPEG_DEC_STATUS_12_DHT_E_MASK)
68728 #define JPEG_DEC_STATUS_12_DQT_E_MASK            (0x20U)
68729 #define JPEG_DEC_STATUS_12_DQT_E_SHIFT           (5U)
68730 /*! DQT_E - DQT_E
68731  */
68732 #define JPEG_DEC_STATUS_12_DQT_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_DQT_E_SHIFT)) & JPEG_DEC_STATUS_12_DQT_E_MASK)
68733 #define JPEG_DEC_STATUS_12_SOS_E_MASK            (0x40U)
68734 #define JPEG_DEC_STATUS_12_SOS_E_SHIFT           (6U)
68735 /*! SOS_E - SOS_E
68736  */
68737 #define JPEG_DEC_STATUS_12_SOS_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_SOS_E_SHIFT)) & JPEG_DEC_STATUS_12_SOS_E_MASK)
68738 #define JPEG_DEC_STATUS_12_SOF_E_MASK            (0x80U)
68739 #define JPEG_DEC_STATUS_12_SOF_E_SHIFT           (7U)
68740 /*! SOF_E - SOF_E
68741  */
68742 #define JPEG_DEC_STATUS_12_SOF_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_SOF_E_SHIFT)) & JPEG_DEC_STATUS_12_SOF_E_MASK)
68743 /*! @} */
68744 
68745 
68746 /*!
68747  * @}
68748  */ /* end of group JPEG_DEC_Register_Masks */
68749 
68750 
68751 /* JPEG_DEC - Peripheral instance base addresses */
68752 /** Peripheral IMAGING__DECODE_U_JPEG_D_X_NOMEM base address */
68753 #define IMAGING__DECODE_U_JPEG_D_X_NOMEM_BASE    (0x585D0000u)
68754 /** Peripheral IMAGING__DECODE_U_JPEG_D_X_NOMEM base pointer */
68755 #define IMAGING__DECODE_U_JPEG_D_X_NOMEM         ((JPEG_DEC_Type *)IMAGING__DECODE_U_JPEG_D_X_NOMEM_BASE)
68756 /** Array initializer of JPEG_DEC peripheral base addresses */
68757 #define JPEG_DEC_BASE_ADDRS                      { IMAGING__DECODE_U_JPEG_D_X_NOMEM_BASE }
68758 /** Array initializer of JPEG_DEC peripheral base pointers */
68759 #define JPEG_DEC_BASE_PTRS                       { IMAGING__DECODE_U_JPEG_D_X_NOMEM }
68760 
68761 /*!
68762  * @}
68763  */ /* end of group JPEG_DEC_Peripheral_Access_Layer */
68764 
68765 
68766 /* ----------------------------------------------------------------------------
68767    -- JPEG_DEC_WRAPPER Peripheral Access Layer
68768    ---------------------------------------------------------------------------- */
68769 
68770 /*!
68771  * @addtogroup JPEG_DEC_WRAPPER_Peripheral_Access_Layer JPEG_DEC_WRAPPER Peripheral Access Layer
68772  * @{
68773  */
68774 
68775 /** JPEG_DEC_WRAPPER - Register Layout Typedef */
68776 typedef struct {
68777   __IO uint32_t GLB_CTRL;                          /**< Global Control, offset: 0x0 */
68778   __I  uint32_t COM_STATUS;                        /**< Common Status, offset: 0x4 */
68779        uint32_t RSVD_COM_IRQ_EN;                   /**< RSVD, offset: 0x8 */
68780        uint32_t RSVD_CUR_DESCPT_PTR;               /**< RSVD, offset: 0xC */
68781        uint32_t RSVD_NXT_DESCPT_PTR;               /**< RSVD, offset: 0x10 */
68782   __IO uint32_t OUT_BUF_BASE0;                     /**< Output Image Frame Buffer0 Base Address, offset: 0x14 */
68783   __IO uint32_t OUT_BUF_BASE1;                     /**< Output Image Frame Buffer1 Base Address, offset: 0x18 */
68784   __IO uint32_t OUT_PITCH;                         /**< Image Output Buffer Pitch, offset: 0x1C */
68785   __IO uint32_t STM_BUFBASE;                       /**< Input JPEG Stream Buffer Base Address, offset: 0x20 */
68786   __IO uint32_t STM_BUFSIZE;                       /**< Input JPEG Stream Buffer Size, offset: 0x24 */
68787   __IO uint32_t IMGSIZE;                           /**< Image Resolution, offset: 0x28 */
68788   __IO uint32_t STM_CTRL;                          /**< Bit Stream and Switching Control, offset: 0x2C */
68789        uint8_t RESERVED_0[65488];
68790   struct {                                         /* offset: 0x10000, array step: 0x10000 */
68791     __IO uint32_t SLOT_STATUS;                       /**< Bitstream Status, array offset: 0x10000, array step: 0x10000 */
68792     __IO uint32_t SLOT_IRQ_EN;                       /**< Bitstream Interrupt Eanble, array offset: 0x10004, array step: 0x10000 */
68793     __I  uint32_t SLOT_BUF_PTR;                      /**< Bitstream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */
68794     __I  uint32_t SLOT_CUR_DESCPT_PTR;               /**< Current Descriptors, array offset: 0x1000C, array step: 0x10000 */
68795     __IO uint32_t SLOT_NXT_DESCPT_PTR;               /**< Next Descriptors, array offset: 0x10010, array step: 0x10000 */
68796          uint8_t RESERVED_0[65516];
68797   } BITSTRM_SLOT_REGS[4];
68798 } JPEG_DEC_WRAPPER_Type;
68799 
68800 /* ----------------------------------------------------------------------------
68801    -- JPEG_DEC_WRAPPER Register Masks
68802    ---------------------------------------------------------------------------- */
68803 
68804 /*!
68805  * @addtogroup JPEG_DEC_WRAPPER_Register_Masks JPEG_DEC_WRAPPER Register Masks
68806  * @{
68807  */
68808 
68809 /*! @name GLB_CTRL - Global Control */
68810 /*! @{ */
68811 #define JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN_MASK (0x1U)
68812 #define JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN_SHIFT (0U)
68813 /*! JPG_DEC_EN - JPEG decoder and the wrapper enable bit.
68814  */
68815 #define JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN_MASK)
68816 #define JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST_MASK    (0x2U)
68817 #define JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST_SHIFT   (1U)
68818 /*! SFTRST - Engine Soft reset
68819  */
68820 #define JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST(x)      (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST_MASK)
68821 #define JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO_MASK    (0x4U)
68822 #define JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO_SHIFT   (2U)
68823 /*! DEC_GO - Start Decoding
68824  */
68825 #define JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO(x)      (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO_MASK)
68826 #define JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN_MASK  (0x8U)
68827 #define JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN_SHIFT (3U)
68828 /*! L_ENDIAN - JPEG Fileformat LITTLE ENDIAN FORMAT
68829  */
68830 #define JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN(x)    (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN_MASK)
68831 #define JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN_MASK   (0xF0U)
68832 #define JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN_SHIFT  (4U)
68833 /*! SLOT_EN - Slots enable
68834  */
68835 #define JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN(x)     (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN_MASK)
68836 /*! @} */
68837 
68838 /*! @name COM_STATUS - Common Status */
68839 /*! @{ */
68840 #define JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT_MASK (0x60000000U)
68841 #define JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT_SHIFT (29U)
68842 /*! CUR_SLOT - Current executing bitstream slot
68843  */
68844 #define JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT_SHIFT)) & JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT_MASK)
68845 #define JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING_MASK (0x80000000U)
68846 #define JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING_SHIFT (31U)
68847 /*! DEC_ONGOING - Indicating the decoing is ongoing.
68848  */
68849 #define JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING_SHIFT)) & JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING_MASK)
68850 /*! @} */
68851 
68852 /*! @name OUT_BUF_BASE0 - Output Image Frame Buffer0 Base Address */
68853 /*! @{ */
68854 #define JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK (0xFFFFFFF0U)
68855 #define JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT (4U)
68856 /*! OUT_BUF_BASE0 - PIXEL FRAME BUF0 BASE
68857  */
68858 #define JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT)) & JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK)
68859 /*! @} */
68860 
68861 /*! @name OUT_BUF_BASE1 - Output Image Frame Buffer1 Base Address */
68862 /*! @{ */
68863 #define JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK (0xFFFFFFF0U)
68864 #define JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT (4U)
68865 /*! OUT_BUF_BASE1 - PIXEL FRAME BUF2 BASE
68866  */
68867 #define JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT)) & JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK)
68868 /*! @} */
68869 
68870 /*! @name OUT_PITCH - Image Output Buffer Pitch */
68871 /*! @{ */
68872 #define JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH_MASK (0xFFFFU)
68873 #define JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH_SHIFT (0U)
68874 /*! OUT_PITCH - image line stride setting in the memory
68875  */
68876 #define JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH_SHIFT)) & JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH_MASK)
68877 /*! @} */
68878 
68879 /*! @name STM_BUFBASE - Input JPEG Stream Buffer Base Address */
68880 /*! @{ */
68881 #define JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE_MASK (0xFFFFFFF0U)
68882 #define JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE_SHIFT (4U)
68883 /*! STM_BUFBASE - Bitstream BUF BASE
68884  */
68885 #define JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE_MASK)
68886 /*! @} */
68887 
68888 /*! @name STM_BUFSIZE - Input JPEG Stream Buffer Size */
68889 /*! @{ */
68890 #define JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_MASK (0xFFFFFC00U)
68891 #define JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_SHIFT (10U)
68892 /*! STM_BUFSIZE - Bitstream Buffer Size
68893  */
68894 #define JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_MASK)
68895 /*! @} */
68896 
68897 /*! @name IMGSIZE - Image Resolution */
68898 /*! @{ */
68899 #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT_MASK (0x3FFFU)
68900 #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT_SHIFT (0U)
68901 /*! IMG_HEIGHT - image height
68902  */
68903 #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT(x)   (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT_SHIFT)) & JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT_MASK)
68904 #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH_MASK  (0x3FFF0000U)
68905 #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH_SHIFT (16U)
68906 /*! IMG_WIDTH - image width
68907  */
68908 #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH(x)    (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH_SHIFT)) & JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH_MASK)
68909 /*! @} */
68910 
68911 /*! @name STM_CTRL - Bit Stream and Switching Control */
68912 /*! @{ */
68913 #define JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION_MASK (0x4U)
68914 #define JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION_SHIFT (2U)
68915 /*! PIXEL_PRECISION - Current decoding precision: 8bit or 12bit.
68916  */
68917 #define JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION_SHIFT)) & JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION_MASK)
68918 #define JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT_MASK (0x78U)
68919 #define JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT_SHIFT (3U)
68920 /*! IMAGE_FORMAT - IMAGE FORMAT
68921  *  0b0000..Image format is YUV420 (2 Plannar, Y at the 1st plannar and UV at the second plannar).
68922  *  0b0001..Image format is YUV422 (1 Plannar in YUYV sequence)
68923  *  0b0010..Image format is RGB (RGBRGB packed format)
68924  *  0b0011..Image format is YUV444 ( 1 Plannar in YUVYUV sequence)
68925  *  0b0100..Image format is Gray(Y8 or Y12) or Single Component.
68926  *  0b0101..Reserved for Future usage.
68927  *  0b0110..Image format is ARGB
68928  */
68929 #define JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT_SHIFT)) & JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT_MASK)
68930 #define JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR_MASK (0x80U)
68931 #define JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR_SHIFT (7U)
68932 /*! BITBUF_PTR_CLR - Switched bit stream buffer pointer clear bit.
68933  */
68934 #define JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR_SHIFT)) & JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR_MASK)
68935 #define JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START_MASK (0x100U)
68936 #define JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START_SHIFT (8U)
68937 /*! AUTO_START - Automatically write "GO" to Cast JPEG Decoder after context switch to start the new decoding.
68938  *  0b0..Will not write any CAST JPEG Decoder Control registers.
68939  *  0b1..Will write '1' to [Go] bit of Cast JPEG Decoder Control register
68940  */
68941 #define JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START_SHIFT)) & JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START_MASK)
68942 /*! @} */
68943 
68944 /*! @name SLOT_STATUS - Bitstream Status */
68945 /*! @{ */
68946 #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF_MASK (0x1U)
68947 #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF_SHIFT (0U)
68948 /*! STMBUF_HALF - Indicating the stream buf pointer has come over half size of the buf size.
68949  */
68950 #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF_MASK)
68951 #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND_MASK (0x2U)
68952 #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND_SHIFT (1U)
68953 /*! STMBUF_RTND - Indicating the stream buf pointer has come over the top size of the stream buffer.
68954  */
68955 #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND_MASK)
68956 #define JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN_MASK (0x4U)
68957 #define JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN_SHIFT (2U)
68958 /*! SWITCHED_IN - Current SLOT is switched in during context switch
68959  */
68960 #define JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN_MASK)
68961 #define JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE_MASK (0x8U)
68962 #define JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE_SHIFT (3U)
68963 /*! FRMDONE - One frame of image decoding finished for current bitstrem (ID).
68964  */
68965 #define JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE_MASK)
68966 #define JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR_MASK (0x100U)
68967 #define JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR_SHIFT (8U)
68968 /*! DECERR - Decoding error status bit
68969  */
68970 #define JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR(x)   (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR_MASK)
68971 #define JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR_MASK (0x200U)
68972 #define JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR_SHIFT (9U)
68973 /*! DES_RD_ERR - AXI Read error status for descriptor fetching
68974  */
68975 #define JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR_MASK)
68976 #define JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR_MASK (0x400U)
68977 #define JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR_SHIFT (10U)
68978 /*! BIT_RD_ERR - AXI Read error status for bitstream fetching
68979  */
68980 #define JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR_MASK)
68981 #define JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR_MASK (0x800U)
68982 #define JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR_SHIFT (11U)
68983 /*! PIXEL_WT_ERR - AXI Write error status for pixel storing
68984  */
68985 #define JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR_MASK)
68986 #define JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT_MASK (0x60000000U)
68987 #define JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT_SHIFT (29U)
68988 /*! CUR_SLOT - Current Executing bitstream slot
68989  */
68990 #define JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT_MASK)
68991 #define JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING_MASK (0x80000000U)
68992 #define JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING_SHIFT (31U)
68993 /*! DEC_ONGOING - Indicating the decoing is ongoing.
68994  */
68995 #define JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING_MASK)
68996 /*! @} */
68997 
68998 /* The count of JPEG_DEC_WRAPPER_SLOT_STATUS */
68999 #define JPEG_DEC_WRAPPER_SLOT_STATUS_COUNT       (4U)
69000 
69001 /*! @name SLOT_IRQ_EN - Bitstream Interrupt Eanble */
69002 /*! @{ */
69003 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK (0x1U)
69004 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT (0U)
69005 /*! STMBUF_HALF_IRQ_EN - Bitstream buffer pointer passing half size of buffer interrupt enable
69006  */
69007 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK)
69008 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK (0x2U)
69009 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT (1U)
69010 /*! STMBUF_RTND_IRQ_EN - Bitstream buffer pointer passing top of buffer interrupt enable
69011  */
69012 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK)
69013 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK (0x4U)
69014 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT (2U)
69015 /*! SWITCHED_IN_IRQ_EN - Context switched in for current bitstream ID interrupt enable
69016  */
69017 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK)
69018 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK (0x8U)
69019 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT (3U)
69020 /*! FRMDONE_IRQ_EN - Frame decoding done for current bitstream ID interrupt enable
69021  */
69022 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK)
69023 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en_MASK (0x100U)
69024 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en_SHIFT (8U)
69025 /*! DECERR_irq_en - Decoding error status interrupt enable
69026  */
69027 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en_MASK)
69028 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK (0x200U)
69029 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT (9U)
69030 /*! DES_RD_ERR_irq_en - AXI Read error status for descriptor fetching
69031  */
69032 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK)
69033 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_MASK (0x400U)
69034 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_SHIFT (10U)
69035 /*! BIT_RD_ERR_irq_en - AXI Read error status for bitstream fetching
69036  */
69037 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_MASK)
69038 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_MASK (0x800U)
69039 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_SHIFT (11U)
69040 /*! PIXEL_WT_ERR_irq_en - AXI Write error status for pixel storing
69041  */
69042 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_MASK)
69043 /*! @} */
69044 
69045 /* The count of JPEG_DEC_WRAPPER_SLOT_IRQ_EN */
69046 #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_COUNT       (4U)
69047 
69048 /*! @name SLOT_BUF_PTR - Bitstream Buffer Pointer */
69049 /*! @{ */
69050 #define JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_MASK (0xFFFFFFFFU)
69051 #define JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_SHIFT (0U)
69052 /*! stmbuf_ptr - stream buf pointer
69053  */
69054 #define JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_MASK)
69055 /*! @} */
69056 
69057 /* The count of JPEG_DEC_WRAPPER_SLOT_BUF_PTR */
69058 #define JPEG_DEC_WRAPPER_SLOT_BUF_PTR_COUNT      (4U)
69059 
69060 /*! @name SLOT_CUR_DESCPT_PTR - Current Descriptors */
69061 /*! @{ */
69062 #define JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU)
69063 #define JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U)
69064 /*! CUR_DESCPT_PRT - cur decoding descriptors pointer.
69065  */
69066 #define JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK)
69067 /*! @} */
69068 
69069 /* The count of JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR */
69070 #define JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_COUNT (4U)
69071 
69072 /*! @name SLOT_NXT_DESCPT_PTR - Next Descriptors */
69073 /*! @{ */
69074 #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK (0x1U)
69075 #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT (0U)
69076 /*! NXT_DESCPT_EN - if next stream descriptor pointor are valid
69077  *  0b0..There is no more descriptor to be fetched, decoding will pause when current frame is finished.
69078  *  0b1..Current descriptor pointer is valid, and wrapper will fetch the descriptor and start next frame decoding
69079  *       when current frame decoding is finished.
69080  */
69081 #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK)
69082 #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK (0xFFFFFFFCU)
69083 #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT (2U)
69084 /*! NXT_DESCPT_PRT - next decoding descriptors pointer.
69085  */
69086 #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK)
69087 /*! @} */
69088 
69089 /* The count of JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR */
69090 #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_COUNT (4U)
69091 
69092 
69093 /*!
69094  * @}
69095  */ /* end of group JPEG_DEC_WRAPPER_Register_Masks */
69096 
69097 
69098 /* JPEG_DEC_WRAPPER - Peripheral instance base addresses */
69099 /** Peripheral IMAGING__DECODE_U_JPEG_DEC_WRAPPER base address */
69100 #define IMAGING__DECODE_U_JPEG_DEC_WRAPPER_BASE  (0x58400000u)
69101 /** Peripheral IMAGING__DECODE_U_JPEG_DEC_WRAPPER base pointer */
69102 #define IMAGING__DECODE_U_JPEG_DEC_WRAPPER       ((JPEG_DEC_WRAPPER_Type *)IMAGING__DECODE_U_JPEG_DEC_WRAPPER_BASE)
69103 /** Array initializer of JPEG_DEC_WRAPPER peripheral base addresses */
69104 #define JPEG_DEC_WRAPPER_BASE_ADDRS              { IMAGING__DECODE_U_JPEG_DEC_WRAPPER_BASE }
69105 /** Array initializer of JPEG_DEC_WRAPPER peripheral base pointers */
69106 #define JPEG_DEC_WRAPPER_BASE_PTRS               { IMAGING__DECODE_U_JPEG_DEC_WRAPPER }
69107 
69108 /*!
69109  * @}
69110  */ /* end of group JPEG_DEC_WRAPPER_Peripheral_Access_Layer */
69111 
69112 
69113 /* ----------------------------------------------------------------------------
69114    -- JPEG_ENC Peripheral Access Layer
69115    ---------------------------------------------------------------------------- */
69116 
69117 /*!
69118  * @addtogroup JPEG_ENC_Peripheral_Access_Layer JPEG_ENC Peripheral Access Layer
69119  * @{
69120  */
69121 
69122 /** JPEG_ENC - Register Layout Typedef */
69123 typedef struct {
69124   union {                                          /* offset: 0x0 */
69125     struct {                                         /* offset: 0x0 */
69126       __IO uint32_t MODE;                              /**< MODE Control Register, offset: 0x0 */
69127       __IO uint32_t CFG_MODE;                          /**< CFG_MODE Control Register, offset: 0x4 */
69128       __IO uint32_t QUALITY;                           /**< , offset: 0x8 */
69129            uint32_t RSVD;                              /**< , offset: 0xC */
69130       __IO uint32_t REC_REGS_SEL;                      /**< Indirect Status Register Select, offset: 0x10 */
69131       __IO uint32_t LUMTH;                             /**< LUMTH Register, offset: 0x14 */
69132       __IO uint32_t CHRTH;                             /**< CHRTH Register, offset: 0x18 */
69133            uint8_t RESERVED_0[36];
69134       __IO uint32_t NOMFRSIZE_LO;                      /**< , offset: 0x40 */
69135       __IO uint32_t NOMFRSIZE_HI;                      /**< , offset: 0x44 */
69136       __IO uint32_t OFBSIZE_LO;                        /**< , offset: 0x48 */
69137       __IO uint32_t OFBSIZE_HI;                        /**< , offset: 0x4C */
69138     } CONTROL;
69139     struct {                                         /* offset: 0x0 */
69140       __IO uint32_t STATUS_0;                          /**< , offset: 0x0 */
69141       __IO uint32_t STATUS_1;                          /**< , offset: 0x4 */
69142       __IO uint32_t STATUS_2;                          /**< , offset: 0x8 */
69143       __IO uint32_t STATUS_3;                          /**< , offset: 0xC */
69144       __IO uint32_t STATUS_4;                          /**< , offset: 0x10 */
69145       __IO uint32_t STATUS_5;                          /**< , offset: 0x14 */
69146       __IO uint32_t STATUS_6;                          /**< , offset: 0x18 */
69147       __IO uint32_t STATUS_7;                          /**< , offset: 0x1C */
69148       __IO uint32_t STATUS_8;                          /**< , offset: 0x20 */
69149       __IO uint32_t STATUS_9;                          /**< , offset: 0x24 */
69150       __IO uint32_t STATUS_10;                         /**< , offset: 0x28 */
69151       __IO uint32_t STATUS_11;                         /**< , offset: 0x2C */
69152       __IO uint32_t STATUS_12;                         /**< , offset: 0x30 */
69153       __IO uint32_t STATUS_13;                         /**< , offset: 0x34 */
69154       __IO uint32_t STATUS_14;                         /**< , offset: 0x38 */
69155       __IO uint32_t STATUS_15;                         /**< , offset: 0x3C */
69156       __IO uint32_t STATUS_16;                         /**< , offset: 0x40 */
69157       __IO uint32_t STATUS_17;                         /**< , offset: 0x44 */
69158       __IO uint32_t STATUS_18;                         /**< , offset: 0x48 */
69159       __IO uint32_t STATUS_19;                         /**< , offset: 0x4C */
69160     } STATUS;
69161   };
69162 } JPEG_ENC_Type;
69163 
69164 /* ----------------------------------------------------------------------------
69165    -- JPEG_ENC Register Masks
69166    ---------------------------------------------------------------------------- */
69167 
69168 /*!
69169  * @addtogroup JPEG_ENC_Register_Masks JPEG_ENC Register Masks
69170  * @{
69171  */
69172 
69173 /*! @name MODE - MODE Control Register */
69174 /*! @{ */
69175 #define JPEG_ENC_MODE_LP_MASK                    (0x1U)
69176 #define JPEG_ENC_MODE_LP_SHIFT                   (0U)
69177 /*! LP - Low Power
69178  */
69179 #define JPEG_ENC_MODE_LP(x)                      (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_LP_SHIFT)) & JPEG_ENC_MODE_LP_MASK)
69180 #define JPEG_ENC_MODE_SWR_MASK                   (0x2U)
69181 #define JPEG_ENC_MODE_SWR_SHIFT                  (1U)
69182 /*! SWR - Soft reset
69183  */
69184 #define JPEG_ENC_MODE_SWR(x)                     (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_SWR_SHIFT)) & JPEG_ENC_MODE_SWR_MASK)
69185 #define JPEG_ENC_MODE_MS_MASK                    (0x8U)
69186 #define JPEG_ENC_MODE_MS_SHIFT                   (3U)
69187 /*! MS - Multi-scan JPEG
69188  */
69189 #define JPEG_ENC_MODE_MS(x)                      (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_MS_SHIFT)) & JPEG_ENC_MODE_MS_MASK)
69190 #define JPEG_ENC_MODE_EXTSEQ_MASK                (0x10U)
69191 #define JPEG_ENC_MODE_EXTSEQ_SHIFT               (4U)
69192 /*! EXTSEQ - EXTSEQ
69193  */
69194 #define JPEG_ENC_MODE_EXTSEQ(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_EXTSEQ_SHIFT)) & JPEG_ENC_MODE_EXTSEQ_MASK)
69195 #define JPEG_ENC_MODE_CONF_MASK                  (0x20U)
69196 #define JPEG_ENC_MODE_CONF_SHIFT                 (5U)
69197 /*! CONF - Configuration
69198  */
69199 #define JPEG_ENC_MODE_CONF(x)                    (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_CONF_SHIFT)) & JPEG_ENC_MODE_CONF_MASK)
69200 #define JPEG_ENC_MODE_GO_MASK                    (0x40U)
69201 #define JPEG_ENC_MODE_GO_SHIFT                   (6U)
69202 /*! GO - Low Power
69203  */
69204 #define JPEG_ENC_MODE_GO(x)                      (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_GO_SHIFT)) & JPEG_ENC_MODE_GO_MASK)
69205 #define JPEG_ENC_MODE_AUTOCLR_CONF_MASK          (0x80U)
69206 #define JPEG_ENC_MODE_AUTOCLR_CONF_SHIFT         (7U)
69207 /*! AUTOCLR_CONF - AUTOCLR_CONF
69208  */
69209 #define JPEG_ENC_MODE_AUTOCLR_CONF(x)            (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_AUTOCLR_CONF_SHIFT)) & JPEG_ENC_MODE_AUTOCLR_CONF_MASK)
69210 #define JPEG_ENC_MODE_AUTOCLR_GO_MASK            (0x100U)
69211 #define JPEG_ENC_MODE_AUTOCLR_GO_SHIFT           (8U)
69212 /*! AUTOCLR_GO - AUTOCLR_GO
69213  */
69214 #define JPEG_ENC_MODE_AUTOCLR_GO(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_AUTOCLR_GO_SHIFT)) & JPEG_ENC_MODE_AUTOCLR_GO_MASK)
69215 /*! @} */
69216 
69217 /*! @name CFG_MODE - CFG_MODE Control Register */
69218 /*! @{ */
69219 #define JPEG_ENC_CFG_MODE_MSOF0_MASK             (0x1U)
69220 #define JPEG_ENC_CFG_MODE_MSOF0_SHIFT            (0U)
69221 /*! MSOF0 - MSOF0
69222  */
69223 #define JPEG_ENC_CFG_MODE_MSOF0(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MSOF0_SHIFT)) & JPEG_ENC_CFG_MODE_MSOF0_MASK)
69224 #define JPEG_ENC_CFG_MODE_MDRI_MASK              (0x2U)
69225 #define JPEG_ENC_CFG_MODE_MDRI_SHIFT             (1U)
69226 /*! MDRI - Mask DRI
69227  */
69228 #define JPEG_ENC_CFG_MODE_MDRI(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MDRI_SHIFT)) & JPEG_ENC_CFG_MODE_MDRI_MASK)
69229 #define JPEG_ENC_CFG_MODE_MDQT_MASK              (0x4U)
69230 #define JPEG_ENC_CFG_MODE_MDQT_SHIFT             (2U)
69231 /*! MDQT - Mask DQT
69232  */
69233 #define JPEG_ENC_CFG_MODE_MDQT(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MDQT_SHIFT)) & JPEG_ENC_CFG_MODE_MDQT_MASK)
69234 #define JPEG_ENC_CFG_MODE_MDHT_MASK              (0x8U)
69235 #define JPEG_ENC_CFG_MODE_MDHT_SHIFT             (3U)
69236 /*! MDHT - Mask DHT
69237  */
69238 #define JPEG_ENC_CFG_MODE_MDHT(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MDHT_SHIFT)) & JPEG_ENC_CFG_MODE_MDHT_MASK)
69239 #define JPEG_ENC_CFG_MODE_MSOS_MASK              (0x10U)
69240 #define JPEG_ENC_CFG_MODE_MSOS_SHIFT             (4U)
69241 /*! MSOS - Mask SOS
69242  */
69243 #define JPEG_ENC_CFG_MODE_MSOS(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MSOS_SHIFT)) & JPEG_ENC_CFG_MODE_MSOS_MASK)
69244 #define JPEG_ENC_CFG_MODE_MDNL_MASK              (0x20U)
69245 #define JPEG_ENC_CFG_MODE_MDNL_SHIFT             (5U)
69246 /*! MDNL - Mask DNL
69247  */
69248 #define JPEG_ENC_CFG_MODE_MDNL(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MDNL_SHIFT)) & JPEG_ENC_CFG_MODE_MDNL_MASK)
69249 #define JPEG_ENC_CFG_MODE_MAPP_MASK              (0x40U)
69250 #define JPEG_ENC_CFG_MODE_MAPP_SHIFT             (6U)
69251 /*! MAPP - Mask APP
69252  */
69253 #define JPEG_ENC_CFG_MODE_MAPP(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MAPP_SHIFT)) & JPEG_ENC_CFG_MODE_MAPP_MASK)
69254 #define JPEG_ENC_CFG_MODE_MCOM_MASK              (0x80U)
69255 #define JPEG_ENC_CFG_MODE_MCOM_SHIFT             (7U)
69256 /*! MCOM - Mask COM
69257  */
69258 #define JPEG_ENC_CFG_MODE_MCOM(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MCOM_SHIFT)) & JPEG_ENC_CFG_MODE_MCOM_MASK)
69259 #define JPEG_ENC_CFG_MODE_COMB_DQT_MASK          (0x100U)
69260 #define JPEG_ENC_CFG_MODE_COMB_DQT_SHIFT         (8U)
69261 /*! COMB_DQT - COMB_DQT
69262  */
69263 #define JPEG_ENC_CFG_MODE_COMB_DQT(x)            (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_COMB_DQT_SHIFT)) & JPEG_ENC_CFG_MODE_COMB_DQT_MASK)
69264 #define JPEG_ENC_CFG_MODE_COMB_DHT_MASK          (0x200U)
69265 #define JPEG_ENC_CFG_MODE_COMB_DHT_SHIFT         (9U)
69266 /*! COMB_DHT - COMB_DHT
69267  */
69268 #define JPEG_ENC_CFG_MODE_COMB_DHT(x)            (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_COMB_DHT_SHIFT)) & JPEG_ENC_CFG_MODE_COMB_DHT_MASK)
69269 #define JPEG_ENC_CFG_MODE_DICOM_MASK             (0x400U)
69270 #define JPEG_ENC_CFG_MODE_DICOM_SHIFT            (10U)
69271 /*! DICOM - DICOM
69272  */
69273 #define JPEG_ENC_CFG_MODE_DICOM(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_DICOM_SHIFT)) & JPEG_ENC_CFG_MODE_DICOM_MASK)
69274 /*! @} */
69275 
69276 /*! @name QUALITY -  */
69277 /*! @{ */
69278 #define JPEG_ENC_QUALITY_QUALITY_MASK            (0x7FU)
69279 #define JPEG_ENC_QUALITY_QUALITY_SHIFT           (0U)
69280 /*! QUALITY - QUALITY
69281  */
69282 #define JPEG_ENC_QUALITY_QUALITY(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_QUALITY_QUALITY_SHIFT)) & JPEG_ENC_QUALITY_QUALITY_MASK)
69283 /*! @} */
69284 
69285 /*! @name REC_REGS_SEL - Indirect Status Register Select */
69286 /*! @{ */
69287 #define JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL_MASK   (0x3U)
69288 #define JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL_SHIFT  (0U)
69289 /*! RC_REGS_SEL - RC_REGS_SEL
69290  */
69291 #define JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL(x)     (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL_SHIFT)) & JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL_MASK)
69292 /*! @} */
69293 
69294 /*! @name LUMTH - LUMTH Register */
69295 /*! @{ */
69296 #define JPEG_ENC_LUMTH_LUMTH_MASK                (0xFFFFU)
69297 #define JPEG_ENC_LUMTH_LUMTH_SHIFT               (0U)
69298 /*! LUMTH - LUMTH
69299  */
69300 #define JPEG_ENC_LUMTH_LUMTH(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_LUMTH_LUMTH_SHIFT)) & JPEG_ENC_LUMTH_LUMTH_MASK)
69301 /*! @} */
69302 
69303 /*! @name CHRTH - CHRTH Register */
69304 /*! @{ */
69305 #define JPEG_ENC_CHRTH_CHRTH_MASK                (0xFFFFU)
69306 #define JPEG_ENC_CHRTH_CHRTH_SHIFT               (0U)
69307 /*! CHRTH - CHRTH
69308  */
69309 #define JPEG_ENC_CHRTH_CHRTH(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CHRTH_CHRTH_SHIFT)) & JPEG_ENC_CHRTH_CHRTH_MASK)
69310 /*! @} */
69311 
69312 /*! @name NOMFRSIZE_LO -  */
69313 /*! @{ */
69314 #define JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_MASK  (0xFFFFU)
69315 #define JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_SHIFT (0U)
69316 /*! NOMFRSIZE_LO - NOMFRSIZE_LO
69317  */
69318 #define JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO(x)    (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_SHIFT)) & JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_MASK)
69319 /*! @} */
69320 
69321 /*! @name NOMFRSIZE_HI -  */
69322 /*! @{ */
69323 #define JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_MASK  (0xFFFFU)
69324 #define JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_SHIFT (0U)
69325 /*! NOMFRSIZE_HI - NOMFRSIZE_HI
69326  */
69327 #define JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI(x)    (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_SHIFT)) & JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_MASK)
69328 /*! @} */
69329 
69330 /*! @name OFBSIZE_LO -  */
69331 /*! @{ */
69332 #define JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_MASK      (0xFFFFU)
69333 #define JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_SHIFT     (0U)
69334 /*! OFBSIZE_LO - OFBSIZE_LO
69335  */
69336 #define JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO(x)        (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_SHIFT)) & JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_MASK)
69337 /*! @} */
69338 
69339 /*! @name OFBSIZE_HI -  */
69340 /*! @{ */
69341 #define JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_MASK      (0xFFFFU)
69342 #define JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_SHIFT     (0U)
69343 /*! OFBSIZE_HI - OFBSIZE_HI
69344  */
69345 #define JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI(x)        (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_SHIFT)) & JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_MASK)
69346 /*! @} */
69347 
69348 /*! @name STATUS_0 -  */
69349 /*! @{ */
69350 #define JPEG_ENC_STATUS_0_X_MASK                 (0xFFFFU)
69351 #define JPEG_ENC_STATUS_0_X_SHIFT                (0U)
69352 /*! X - X
69353  */
69354 #define JPEG_ENC_STATUS_0_X(x)                   (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_0_X_SHIFT)) & JPEG_ENC_STATUS_0_X_MASK)
69355 /*! @} */
69356 
69357 /*! @name STATUS_1 -  */
69358 /*! @{ */
69359 #define JPEG_ENC_STATUS_1_Y_MASK                 (0xFFFFU)
69360 #define JPEG_ENC_STATUS_1_Y_SHIFT                (0U)
69361 /*! Y - Y
69362  */
69363 #define JPEG_ENC_STATUS_1_Y(x)                   (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_1_Y_SHIFT)) & JPEG_ENC_STATUS_1_Y_MASK)
69364 /*! @} */
69365 
69366 /*! @name STATUS_2 -  */
69367 /*! @{ */
69368 #define JPEG_ENC_STATUS_2_HMCU_MASK              (0xFFFFU)
69369 #define JPEG_ENC_STATUS_2_HMCU_SHIFT             (0U)
69370 /*! HMCU - HMCU
69371  */
69372 #define JPEG_ENC_STATUS_2_HMCU(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_2_HMCU_SHIFT)) & JPEG_ENC_STATUS_2_HMCU_MASK)
69373 /*! @} */
69374 
69375 /*! @name STATUS_3 -  */
69376 /*! @{ */
69377 #define JPEG_ENC_STATUS_3_VMCU_MASK              (0xFFFFU)
69378 #define JPEG_ENC_STATUS_3_VMCU_SHIFT             (0U)
69379 /*! VMCU - VMCU
69380  */
69381 #define JPEG_ENC_STATUS_3_VMCU(x)                (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_3_VMCU_SHIFT)) & JPEG_ENC_STATUS_3_VMCU_MASK)
69382 /*! @} */
69383 
69384 /*! @name STATUS_4 -  */
69385 /*! @{ */
69386 #define JPEG_ENC_STATUS_4_Tq0_MASK               (0x3U)
69387 #define JPEG_ENC_STATUS_4_Tq0_SHIFT              (0U)
69388 /*! Tq0 - Tq0
69389  */
69390 #define JPEG_ENC_STATUS_4_Tq0(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_4_Tq0_SHIFT)) & JPEG_ENC_STATUS_4_Tq0_MASK)
69391 #define JPEG_ENC_STATUS_4_V0_MASK                (0x1CU)
69392 #define JPEG_ENC_STATUS_4_V0_SHIFT               (2U)
69393 /*! V0 - V0
69394  */
69395 #define JPEG_ENC_STATUS_4_V0(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_4_V0_SHIFT)) & JPEG_ENC_STATUS_4_V0_MASK)
69396 #define JPEG_ENC_STATUS_4_H0_MASK                (0xE0U)
69397 #define JPEG_ENC_STATUS_4_H0_SHIFT               (5U)
69398 /*! H0 - H0
69399  */
69400 #define JPEG_ENC_STATUS_4_H0(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_4_H0_SHIFT)) & JPEG_ENC_STATUS_4_H0_MASK)
69401 #define JPEG_ENC_STATUS_4_C0_MASK                (0xFF00U)
69402 #define JPEG_ENC_STATUS_4_C0_SHIFT               (8U)
69403 /*! C0 - C0
69404  */
69405 #define JPEG_ENC_STATUS_4_C0(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_4_C0_SHIFT)) & JPEG_ENC_STATUS_4_C0_MASK)
69406 /*! @} */
69407 
69408 /*! @name STATUS_5 -  */
69409 /*! @{ */
69410 #define JPEG_ENC_STATUS_5_Tq1_MASK               (0x3U)
69411 #define JPEG_ENC_STATUS_5_Tq1_SHIFT              (0U)
69412 /*! Tq1 - Tq1
69413  */
69414 #define JPEG_ENC_STATUS_5_Tq1(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_5_Tq1_SHIFT)) & JPEG_ENC_STATUS_5_Tq1_MASK)
69415 #define JPEG_ENC_STATUS_5_V1_MASK                (0x1CU)
69416 #define JPEG_ENC_STATUS_5_V1_SHIFT               (2U)
69417 /*! V1 - V1
69418  */
69419 #define JPEG_ENC_STATUS_5_V1(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_5_V1_SHIFT)) & JPEG_ENC_STATUS_5_V1_MASK)
69420 #define JPEG_ENC_STATUS_5_H1_MASK                (0xE0U)
69421 #define JPEG_ENC_STATUS_5_H1_SHIFT               (5U)
69422 /*! H1 - H1
69423  */
69424 #define JPEG_ENC_STATUS_5_H1(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_5_H1_SHIFT)) & JPEG_ENC_STATUS_5_H1_MASK)
69425 #define JPEG_ENC_STATUS_5_C1_MASK                (0xFF00U)
69426 #define JPEG_ENC_STATUS_5_C1_SHIFT               (8U)
69427 /*! C1 - C1
69428  */
69429 #define JPEG_ENC_STATUS_5_C1(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_5_C1_SHIFT)) & JPEG_ENC_STATUS_5_C1_MASK)
69430 /*! @} */
69431 
69432 /*! @name STATUS_6 -  */
69433 /*! @{ */
69434 #define JPEG_ENC_STATUS_6_Tq2_MASK               (0x3U)
69435 #define JPEG_ENC_STATUS_6_Tq2_SHIFT              (0U)
69436 /*! Tq2 - Tq2
69437  */
69438 #define JPEG_ENC_STATUS_6_Tq2(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_6_Tq2_SHIFT)) & JPEG_ENC_STATUS_6_Tq2_MASK)
69439 #define JPEG_ENC_STATUS_6_V2_MASK                (0x1CU)
69440 #define JPEG_ENC_STATUS_6_V2_SHIFT               (2U)
69441 /*! V2 - V2
69442  */
69443 #define JPEG_ENC_STATUS_6_V2(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_6_V2_SHIFT)) & JPEG_ENC_STATUS_6_V2_MASK)
69444 #define JPEG_ENC_STATUS_6_H2_MASK                (0xE0U)
69445 #define JPEG_ENC_STATUS_6_H2_SHIFT               (5U)
69446 /*! H2 - H2
69447  */
69448 #define JPEG_ENC_STATUS_6_H2(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_6_H2_SHIFT)) & JPEG_ENC_STATUS_6_H2_MASK)
69449 #define JPEG_ENC_STATUS_6_C2_MASK                (0xFF00U)
69450 #define JPEG_ENC_STATUS_6_C2_SHIFT               (8U)
69451 /*! C2 - C2
69452  */
69453 #define JPEG_ENC_STATUS_6_C2(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_6_C2_SHIFT)) & JPEG_ENC_STATUS_6_C2_MASK)
69454 /*! @} */
69455 
69456 /*! @name STATUS_7 -  */
69457 /*! @{ */
69458 #define JPEG_ENC_STATUS_7_Tq3_MASK               (0x3U)
69459 #define JPEG_ENC_STATUS_7_Tq3_SHIFT              (0U)
69460 /*! Tq3 - Tq3
69461  */
69462 #define JPEG_ENC_STATUS_7_Tq3(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_7_Tq3_SHIFT)) & JPEG_ENC_STATUS_7_Tq3_MASK)
69463 #define JPEG_ENC_STATUS_7_V3_MASK                (0x1CU)
69464 #define JPEG_ENC_STATUS_7_V3_SHIFT               (2U)
69465 /*! V3 - V3
69466  */
69467 #define JPEG_ENC_STATUS_7_V3(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_7_V3_SHIFT)) & JPEG_ENC_STATUS_7_V3_MASK)
69468 #define JPEG_ENC_STATUS_7_H3_MASK                (0xE0U)
69469 #define JPEG_ENC_STATUS_7_H3_SHIFT               (5U)
69470 /*! H3 - H3
69471  */
69472 #define JPEG_ENC_STATUS_7_H3(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_7_H3_SHIFT)) & JPEG_ENC_STATUS_7_H3_MASK)
69473 #define JPEG_ENC_STATUS_7_C3_MASK                (0xFF00U)
69474 #define JPEG_ENC_STATUS_7_C3_SHIFT               (8U)
69475 /*! C3 - C3
69476  */
69477 #define JPEG_ENC_STATUS_7_C3(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_7_C3_SHIFT)) & JPEG_ENC_STATUS_7_C3_MASK)
69478 /*! @} */
69479 
69480 /*! @name STATUS_8 -  */
69481 /*! @{ */
69482 #define JPEG_ENC_STATUS_8_Nf_MASK                (0xFFU)
69483 #define JPEG_ENC_STATUS_8_Nf_SHIFT               (0U)
69484 /*! Nf - Nf
69485  */
69486 #define JPEG_ENC_STATUS_8_Nf(x)                  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_8_Nf_SHIFT)) & JPEG_ENC_STATUS_8_Nf_MASK)
69487 #define JPEG_ENC_STATUS_8_QUALITY_MASK           (0xFF00U)
69488 #define JPEG_ENC_STATUS_8_QUALITY_SHIFT          (8U)
69489 /*! QUALITY - QUALITY
69490  */
69491 #define JPEG_ENC_STATUS_8_QUALITY(x)             (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_8_QUALITY_SHIFT)) & JPEG_ENC_STATUS_8_QUALITY_MASK)
69492 /*! @} */
69493 
69494 /*! @name STATUS_9 -  */
69495 /*! @{ */
69496 #define JPEG_ENC_STATUS_9_DRI_MASK               (0xFFFFU)
69497 #define JPEG_ENC_STATUS_9_DRI_SHIFT              (0U)
69498 /*! DRI - DRI
69499  */
69500 #define JPEG_ENC_STATUS_9_DRI(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_9_DRI_SHIFT)) & JPEG_ENC_STATUS_9_DRI_MASK)
69501 /*! @} */
69502 
69503 /*! @name STATUS_10 -  */
69504 /*! @{ */
69505 #define JPEG_ENC_STATUS_10_Ns_MASK               (0xFU)
69506 #define JPEG_ENC_STATUS_10_Ns_SHIFT              (0U)
69507 /*! Ns - Ns
69508  */
69509 #define JPEG_ENC_STATUS_10_Ns(x)                 (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_10_Ns_SHIFT)) & JPEG_ENC_STATUS_10_Ns_MASK)
69510 #define JPEG_ENC_STATUS_10_NBMCU_MASK            (0xF0U)
69511 #define JPEG_ENC_STATUS_10_NBMCU_SHIFT           (4U)
69512 /*! NBMCU - NBMCU
69513  */
69514 #define JPEG_ENC_STATUS_10_NBMCU(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_10_NBMCU_SHIFT)) & JPEG_ENC_STATUS_10_NBMCU_MASK)
69515 #define JPEG_ENC_STATUS_10_Vmax_MASK             (0xF00U)
69516 #define JPEG_ENC_STATUS_10_Vmax_SHIFT            (8U)
69517 /*! Vmax - Vmax
69518  */
69519 #define JPEG_ENC_STATUS_10_Vmax(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_10_Vmax_SHIFT)) & JPEG_ENC_STATUS_10_Vmax_MASK)
69520 #define JPEG_ENC_STATUS_10_Hmax_MASK             (0xF000U)
69521 #define JPEG_ENC_STATUS_10_Hmax_SHIFT            (12U)
69522 /*! Hmax - Hmax
69523  */
69524 #define JPEG_ENC_STATUS_10_Hmax(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_10_Hmax_SHIFT)) & JPEG_ENC_STATUS_10_Hmax_MASK)
69525 /*! @} */
69526 
69527 /*! @name STATUS_11 -  */
69528 /*! @{ */
69529 #define JPEG_ENC_STATUS_11_VHS0_MASK             (0xFU)
69530 #define JPEG_ENC_STATUS_11_VHS0_SHIFT            (0U)
69531 /*! VHS0 - VHS0
69532  */
69533 #define JPEG_ENC_STATUS_11_VHS0(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_11_VHS0_SHIFT)) & JPEG_ENC_STATUS_11_VHS0_MASK)
69534 #define JPEG_ENC_STATUS_11_VHS1_MASK             (0xF0U)
69535 #define JPEG_ENC_STATUS_11_VHS1_SHIFT            (4U)
69536 /*! VHS1 - VHS1
69537  */
69538 #define JPEG_ENC_STATUS_11_VHS1(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_11_VHS1_SHIFT)) & JPEG_ENC_STATUS_11_VHS1_MASK)
69539 #define JPEG_ENC_STATUS_11_VHS2_MASK             (0xF00U)
69540 #define JPEG_ENC_STATUS_11_VHS2_SHIFT            (8U)
69541 /*! VHS2 - VHS2
69542  */
69543 #define JPEG_ENC_STATUS_11_VHS2(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_11_VHS2_SHIFT)) & JPEG_ENC_STATUS_11_VHS2_MASK)
69544 #define JPEG_ENC_STATUS_11_VHS3_MASK             (0xF000U)
69545 #define JPEG_ENC_STATUS_11_VHS3_SHIFT            (12U)
69546 /*! VHS3 - VHS3
69547  */
69548 #define JPEG_ENC_STATUS_11_VHS3(x)               (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_11_VHS3_SHIFT)) & JPEG_ENC_STATUS_11_VHS3_MASK)
69549 /*! @} */
69550 
69551 /*! @name STATUS_12 -  */
69552 /*! @{ */
69553 #define JPEG_ENC_STATUS_12_COM_E_MASK            (0x1U)
69554 #define JPEG_ENC_STATUS_12_COM_E_SHIFT           (0U)
69555 /*! COM_E - COM_E
69556  */
69557 #define JPEG_ENC_STATUS_12_COM_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_COM_E_SHIFT)) & JPEG_ENC_STATUS_12_COM_E_MASK)
69558 #define JPEG_ENC_STATUS_12_APPn_E_MASK           (0x2U)
69559 #define JPEG_ENC_STATUS_12_APPn_E_SHIFT          (1U)
69560 /*! APPn_E - APPn_E
69561  */
69562 #define JPEG_ENC_STATUS_12_APPn_E(x)             (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_APPn_E_SHIFT)) & JPEG_ENC_STATUS_12_APPn_E_MASK)
69563 #define JPEG_ENC_STATUS_12_DRI_E_MASK            (0x4U)
69564 #define JPEG_ENC_STATUS_12_DRI_E_SHIFT           (2U)
69565 /*! DRI_E - DRI_E
69566  */
69567 #define JPEG_ENC_STATUS_12_DRI_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_DRI_E_SHIFT)) & JPEG_ENC_STATUS_12_DRI_E_MASK)
69568 #define JPEG_ENC_STATUS_12_DNL_E_MASK            (0x8U)
69569 #define JPEG_ENC_STATUS_12_DNL_E_SHIFT           (3U)
69570 /*! DNL_E - DNL_E
69571  */
69572 #define JPEG_ENC_STATUS_12_DNL_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_DNL_E_SHIFT)) & JPEG_ENC_STATUS_12_DNL_E_MASK)
69573 #define JPEG_ENC_STATUS_12_DHT_E_MASK            (0x10U)
69574 #define JPEG_ENC_STATUS_12_DHT_E_SHIFT           (4U)
69575 /*! DHT_E - DHT_E
69576  */
69577 #define JPEG_ENC_STATUS_12_DHT_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_DHT_E_SHIFT)) & JPEG_ENC_STATUS_12_DHT_E_MASK)
69578 #define JPEG_ENC_STATUS_12_DQT_E_MASK            (0x20U)
69579 #define JPEG_ENC_STATUS_12_DQT_E_SHIFT           (5U)
69580 /*! DQT_E - DQT_E
69581  */
69582 #define JPEG_ENC_STATUS_12_DQT_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_DQT_E_SHIFT)) & JPEG_ENC_STATUS_12_DQT_E_MASK)
69583 #define JPEG_ENC_STATUS_12_SOS_E_MASK            (0x40U)
69584 #define JPEG_ENC_STATUS_12_SOS_E_SHIFT           (6U)
69585 /*! SOS_E - SOS_E
69586  */
69587 #define JPEG_ENC_STATUS_12_SOS_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_SOS_E_SHIFT)) & JPEG_ENC_STATUS_12_SOS_E_MASK)
69588 #define JPEG_ENC_STATUS_12_SOF_E_MASK            (0x80U)
69589 #define JPEG_ENC_STATUS_12_SOF_E_SHIFT           (7U)
69590 /*! SOF_E - SOF_E
69591  */
69592 #define JPEG_ENC_STATUS_12_SOF_E(x)              (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_SOF_E_SHIFT)) & JPEG_ENC_STATUS_12_SOF_E_MASK)
69593 #define JPEG_ENC_STATUS_12_CONFIGERROR_MASK      (0x100U)
69594 #define JPEG_ENC_STATUS_12_CONFIGERROR_SHIFT     (8U)
69595 /*! CONFIGERROR - CONFIGERROR
69596  */
69597 #define JPEG_ENC_STATUS_12_CONFIGERROR(x)        (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_CONFIGERROR_SHIFT)) & JPEG_ENC_STATUS_12_CONFIGERROR_MASK)
69598 #define JPEG_ENC_STATUS_12_JPEGIN_RDY_MASK       (0x200U)
69599 #define JPEG_ENC_STATUS_12_JPEGIN_RDY_SHIFT      (9U)
69600 /*! JPEGIN_RDY - JPEGIN_RDY
69601  */
69602 #define JPEG_ENC_STATUS_12_JPEGIN_RDY(x)         (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_JPEGIN_RDY_SHIFT)) & JPEG_ENC_STATUS_12_JPEGIN_RDY_MASK)
69603 #define JPEG_ENC_STATUS_12_PIXELIN_RDY_MASK      (0x400U)
69604 #define JPEG_ENC_STATUS_12_PIXELIN_RDY_SHIFT     (10U)
69605 /*! PIXELIN_RDY - PIXELIN_RDY
69606  */
69607 #define JPEG_ENC_STATUS_12_PIXELIN_RDY(x)        (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_PIXELIN_RDY_SHIFT)) & JPEG_ENC_STATUS_12_PIXELIN_RDY_MASK)
69608 #define JPEG_ENC_STATUS_12_SCANACTIVE_MASK       (0x800U)
69609 #define JPEG_ENC_STATUS_12_SCANACTIVE_SHIFT      (11U)
69610 /*! SCANACTIVE - SCANACTIVE
69611  */
69612 #define JPEG_ENC_STATUS_12_SCANACTIVE(x)         (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_SCANACTIVE_SHIFT)) & JPEG_ENC_STATUS_12_SCANACTIVE_MASK)
69613 /*! @} */
69614 
69615 /*! @name STATUS_13 -  */
69616 /*! @{ */
69617 #define JPEG_ENC_STATUS_13_CFG_MODE_MASK         (0xFFFFU)
69618 #define JPEG_ENC_STATUS_13_CFG_MODE_SHIFT        (0U)
69619 /*! CFG_MODE - CFG_MODE
69620  */
69621 #define JPEG_ENC_STATUS_13_CFG_MODE(x)           (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_13_CFG_MODE_SHIFT)) & JPEG_ENC_STATUS_13_CFG_MODE_MASK)
69622 /*! @} */
69623 
69624 /*! @name STATUS_14 -  */
69625 /*! @{ */
69626 #define JPEG_ENC_STATUS_14_RC_REGS0_MASK         (0xFFFFU)
69627 #define JPEG_ENC_STATUS_14_RC_REGS0_SHIFT        (0U)
69628 /*! RC_REGS0 - RC_REGS0
69629  */
69630 #define JPEG_ENC_STATUS_14_RC_REGS0(x)           (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_14_RC_REGS0_SHIFT)) & JPEG_ENC_STATUS_14_RC_REGS0_MASK)
69631 /*! @} */
69632 
69633 /*! @name STATUS_15 -  */
69634 /*! @{ */
69635 #define JPEG_ENC_STATUS_15_RC_REGS1_MASK         (0xFFFFU)
69636 #define JPEG_ENC_STATUS_15_RC_REGS1_SHIFT        (0U)
69637 /*! RC_REGS1 - RC_REGS1
69638  */
69639 #define JPEG_ENC_STATUS_15_RC_REGS1(x)           (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_15_RC_REGS1_SHIFT)) & JPEG_ENC_STATUS_15_RC_REGS1_MASK)
69640 /*! @} */
69641 
69642 /*! @name STATUS_16 -  */
69643 /*! @{ */
69644 #define JPEG_ENC_STATUS_16_NOMFRSIZE_LO_MASK     (0xFFFFU)
69645 #define JPEG_ENC_STATUS_16_NOMFRSIZE_LO_SHIFT    (0U)
69646 /*! NOMFRSIZE_LO - NOMFRSIZE_LO
69647  */
69648 #define JPEG_ENC_STATUS_16_NOMFRSIZE_LO(x)       (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_16_NOMFRSIZE_LO_SHIFT)) & JPEG_ENC_STATUS_16_NOMFRSIZE_LO_MASK)
69649 /*! @} */
69650 
69651 /*! @name STATUS_17 -  */
69652 /*! @{ */
69653 #define JPEG_ENC_STATUS_17_NOMFRSIZE_HI_MASK     (0xFFFFU)
69654 #define JPEG_ENC_STATUS_17_NOMFRSIZE_HI_SHIFT    (0U)
69655 /*! NOMFRSIZE_HI - NOMFRSIZE_HI
69656  */
69657 #define JPEG_ENC_STATUS_17_NOMFRSIZE_HI(x)       (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_17_NOMFRSIZE_HI_SHIFT)) & JPEG_ENC_STATUS_17_NOMFRSIZE_HI_MASK)
69658 /*! @} */
69659 
69660 /*! @name STATUS_18 -  */
69661 /*! @{ */
69662 #define JPEG_ENC_STATUS_18_OFBSIZE_LO_MASK       (0xFFFFU)
69663 #define JPEG_ENC_STATUS_18_OFBSIZE_LO_SHIFT      (0U)
69664 /*! OFBSIZE_LO - OFBSIZE_LO
69665  */
69666 #define JPEG_ENC_STATUS_18_OFBSIZE_LO(x)         (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_18_OFBSIZE_LO_SHIFT)) & JPEG_ENC_STATUS_18_OFBSIZE_LO_MASK)
69667 /*! @} */
69668 
69669 /*! @name STATUS_19 -  */
69670 /*! @{ */
69671 #define JPEG_ENC_STATUS_19_OFBSIZE_HI_MASK       (0xFFFFU)
69672 #define JPEG_ENC_STATUS_19_OFBSIZE_HI_SHIFT      (0U)
69673 /*! OFBSIZE_HI - OFBSIZE_HI
69674  */
69675 #define JPEG_ENC_STATUS_19_OFBSIZE_HI(x)         (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_19_OFBSIZE_HI_SHIFT)) & JPEG_ENC_STATUS_19_OFBSIZE_HI_MASK)
69676 /*! @} */
69677 
69678 
69679 /*!
69680  * @}
69681  */ /* end of group JPEG_ENC_Register_Masks */
69682 
69683 
69684 /* JPEG_ENC - Peripheral instance base addresses */
69685 /** Peripheral IMAGING__ENCODE_U_JPEG_E_X_NOMEM base address */
69686 #define IMAGING__ENCODE_U_JPEG_E_X_NOMEM_BASE    (0x585F0000u)
69687 /** Peripheral IMAGING__ENCODE_U_JPEG_E_X_NOMEM base pointer */
69688 #define IMAGING__ENCODE_U_JPEG_E_X_NOMEM         ((JPEG_ENC_Type *)IMAGING__ENCODE_U_JPEG_E_X_NOMEM_BASE)
69689 /** Array initializer of JPEG_ENC peripheral base addresses */
69690 #define JPEG_ENC_BASE_ADDRS                      { IMAGING__ENCODE_U_JPEG_E_X_NOMEM_BASE }
69691 /** Array initializer of JPEG_ENC peripheral base pointers */
69692 #define JPEG_ENC_BASE_PTRS                       { IMAGING__ENCODE_U_JPEG_E_X_NOMEM }
69693 
69694 /*!
69695  * @}
69696  */ /* end of group JPEG_ENC_Peripheral_Access_Layer */
69697 
69698 
69699 /* ----------------------------------------------------------------------------
69700    -- JPEG_ENC_WRAPPER Peripheral Access Layer
69701    ---------------------------------------------------------------------------- */
69702 
69703 /*!
69704  * @addtogroup JPEG_ENC_WRAPPER_Peripheral_Access_Layer JPEG_ENC_WRAPPER Peripheral Access Layer
69705  * @{
69706  */
69707 
69708 /** JPEG_ENC_WRAPPER - Register Layout Typedef */
69709 typedef struct {
69710   __IO uint32_t GLB_CTRL;                          /**< Global Control, offset: 0x0 */
69711   __I  uint32_t COM_STATUS;                        /**< Common Status, offset: 0x4 */
69712        uint32_t RSVD_COM_IRQ_EN;                   /**< RSVD, offset: 0x8 */
69713        uint32_t RSVD_CUR_DESCPT_PTR;               /**< RSVD, offset: 0xC */
69714        uint32_t RSVD_NXT_DESCPT_PTR;               /**< RSVD, offset: 0x10 */
69715   __IO uint32_t IN_BUF_BASE0;                      /**< Input Image Frame Buffer0 Base Address, offset: 0x14 */
69716   __IO uint32_t IN_BUF_BASE1;                      /**< Input Image Frame Buffer1 Base Address, offset: 0x18 */
69717   __IO uint32_t IN_LINE_PITCH;                     /**< Image Input Buffer Line Pitch, offset: 0x1C */
69718   __IO uint32_t STM_BUFBASE;                       /**< Output JPEG Stream Buffer Base Address, offset: 0x20 */
69719   __IO uint32_t STM_BUFSIZE;                       /**< Output JPEG Stream Buffer Size, offset: 0x24 */
69720   __IO uint32_t IMGSIZE;                           /**< Image Resolution, offset: 0x28 */
69721   __IO uint32_t STM_CTRL;                          /**< Bit Stream Switch and Control, offset: 0x2C */
69722        uint8_t RESERVED_0[65488];
69723   struct {                                         /* offset: 0x10000, array step: 0x10000 */
69724     __IO uint32_t SLOT_STATUS;                       /**< Bit Stream SLOT Status, array offset: 0x10000, array step: 0x10000 */
69725     __IO uint32_t SLOT_IRQ_EN;                       /**< Bit Stream Interrupt Enable Register, array offset: 0x10004, array step: 0x10000 */
69726     __I  uint32_t SLOT_BUF_PTR;                      /**< Bit Stream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */
69727     __I  uint32_t SLOT_CUR_DESCPT_PTR;               /**< Current Encoding Descriptor Pointer, array offset: 0x1000C, array step: 0x10000 */
69728     __IO uint32_t SLOT_NXT_DESCPT_PTR;               /**< Next Encoding Descriptor Pointer, array offset: 0x10010, array step: 0x10000 */
69729          uint8_t RESERVED_0[65516];
69730   } BIT_STREAM[4];
69731 } JPEG_ENC_WRAPPER_Type;
69732 
69733 /* ----------------------------------------------------------------------------
69734    -- JPEG_ENC_WRAPPER Register Masks
69735    ---------------------------------------------------------------------------- */
69736 
69737 /*!
69738  * @addtogroup JPEG_ENC_WRAPPER_Register_Masks JPEG_ENC_WRAPPER Register Masks
69739  * @{
69740  */
69741 
69742 /*! @name GLB_CTRL - Global Control */
69743 /*! @{ */
69744 #define JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN_MASK (0x1U)
69745 #define JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN_SHIFT (0U)
69746 /*! JPG_ENC_EN - JPEG Encoder and the wrapper enable bit
69747  */
69748 #define JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN_MASK)
69749 #define JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST_MASK    (0x2U)
69750 #define JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST_SHIFT   (1U)
69751 /*! SFTRST - Engine Soft reset
69752  */
69753 #define JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST(x)      (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST_MASK)
69754 #define JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO_MASK    (0x4U)
69755 #define JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO_SHIFT   (2U)
69756 /*! ENC_GO - Start Encoding
69757  */
69758 #define JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO(x)      (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO_MASK)
69759 #define JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN_MASK  (0x8U)
69760 #define JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN_SHIFT (3U)
69761 /*! L_ENDIAN - Little Endian
69762  */
69763 #define JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN(x)    (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN_MASK)
69764 #define JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN_MASK   (0xF0U)
69765 #define JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN_SHIFT  (4U)
69766 /*! SLOT_EN - Slot Enable
69767  */
69768 #define JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN(x)     (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN_MASK)
69769 /*! @} */
69770 
69771 /*! @name COM_STATUS - Common Status */
69772 /*! @{ */
69773 #define JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT_MASK (0x60000000U)
69774 #define JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT_SHIFT (29U)
69775 /*! CUR_SLOT - Current executing bitstream slot
69776  */
69777 #define JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT_SHIFT)) & JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT_MASK)
69778 #define JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING_MASK (0x80000000U)
69779 #define JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING_SHIFT (31U)
69780 /*! ENC_ONGOING - Indicating the encoding is ongoing.
69781  */
69782 #define JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING_SHIFT)) & JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING_MASK)
69783 /*! @} */
69784 
69785 /*! @name IN_BUF_BASE0 - Input Image Frame Buffer0 Base Address */
69786 /*! @{ */
69787 #define JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0_MASK (0xFFFFFFF0U)
69788 #define JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT (4U)
69789 /*! IN_BUF_BASE0 - Frame Buffer0 Base Address
69790  */
69791 #define JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT)) & JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0_MASK)
69792 /*! @} */
69793 
69794 /*! @name IN_BUF_BASE1 - Input Image Frame Buffer1 Base Address */
69795 /*! @{ */
69796 #define JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1_MASK (0xFFFFFFF0U)
69797 #define JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT (4U)
69798 /*! IN_BUF_BASE1 - JPEG Encoder and the wrapper enable bit.
69799  */
69800 #define JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT)) & JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1_MASK)
69801 /*! @} */
69802 
69803 /*! @name IN_LINE_PITCH - Image Input Buffer Line Pitch */
69804 /*! @{ */
69805 #define JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch_MASK (0xFFFFU)
69806 #define JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch_SHIFT (0U)
69807 /*! In_line_pitch - image line stride setting in the memory
69808  */
69809 #define JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch_SHIFT)) & JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch_MASK)
69810 /*! @} */
69811 
69812 /*! @name STM_BUFBASE - Output JPEG Stream Buffer Base Address */
69813 /*! @{ */
69814 #define JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE_MASK (0xFFFFFFF0U)
69815 #define JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE_SHIFT (4U)
69816 /*! STM_BUFBASE - Bitstream BUF BASE
69817  */
69818 #define JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE_MASK)
69819 /*! @} */
69820 
69821 /*! @name STM_BUFSIZE - Output JPEG Stream Buffer Size */
69822 /*! @{ */
69823 #define JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_MASK (0xFFFFFC00U)
69824 #define JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_SHIFT (10U)
69825 /*! STM_BUFSIZE - Bitstream Buffer Size
69826  */
69827 #define JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_MASK)
69828 /*! @} */
69829 
69830 /*! @name IMGSIZE - Image Resolution */
69831 /*! @{ */
69832 #define JPEG_ENC_WRAPPER_IMGSIZE_img_height_MASK (0x3FFFU)
69833 #define JPEG_ENC_WRAPPER_IMGSIZE_img_height_SHIFT (0U)
69834 /*! img_height - image height
69835  */
69836 #define JPEG_ENC_WRAPPER_IMGSIZE_img_height(x)   (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IMGSIZE_img_height_SHIFT)) & JPEG_ENC_WRAPPER_IMGSIZE_img_height_MASK)
69837 #define JPEG_ENC_WRAPPER_IMGSIZE_img_width_MASK  (0x3FFF0000U)
69838 #define JPEG_ENC_WRAPPER_IMGSIZE_img_width_SHIFT (16U)
69839 /*! img_width - image width
69840  */
69841 #define JPEG_ENC_WRAPPER_IMGSIZE_img_width(x)    (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IMGSIZE_img_width_SHIFT)) & JPEG_ENC_WRAPPER_IMGSIZE_img_width_MASK)
69842 /*! @} */
69843 
69844 /*! @name STM_CTRL - Bit Stream Switch and Control */
69845 /*! @{ */
69846 #define JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision_MASK (0x4U)
69847 #define JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision_SHIFT (2U)
69848 /*! pixel_precision - Current encoding precision: 8bit or 12bit.
69849  */
69850 #define JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision_MASK)
69851 #define JPEG_ENC_WRAPPER_STM_CTRL_image_format_MASK (0x78U)
69852 #define JPEG_ENC_WRAPPER_STM_CTRL_image_format_SHIFT (3U)
69853 /*! image_format - Image format for encoding
69854  *  0b0000..Image format is YUV420 (2 Plannar, Y at the 1st plannar and UV at the second plannar).
69855  *  0b0001..Image format is YUV422 (1 Plannar in YUYV sequence)
69856  *  0b0010..Image format is RGB (RGBRGB packed format)
69857  *  0b0011..Image format is YUV444 ( 1 Plannar in YUVYUV sequence)
69858  *  0b0100..Image format is Gray (Y8 or Y12) or Single Component
69859  *  0b0101..Reserved for Future Usage.
69860  *  0b0110..Image format is ARGB (ARGBARGB packed format)
69861  */
69862 #define JPEG_ENC_WRAPPER_STM_CTRL_image_format(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_image_format_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_image_format_MASK)
69863 #define JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr_MASK (0x80U)
69864 #define JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr_SHIFT (7U)
69865 /*! bitbuf_ptr_clr - Clear the bitstream buffer pointer for current ID
69866  *  0b0..After the context switching, the bitstream buffer point is restored to last time when the bitstream is switched out.
69867  *  0b1..Clear the bitstream buffer pointer after the context switching, and encoding output start from base of bit buffer.
69868  */
69869 #define JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr_MASK)
69870 #define JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START_MASK (0x100U)
69871 #define JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START_SHIFT (8U)
69872 /*! AUTO_START - Automatically write "GO" to Cast Encoder after context switching
69873  *  0b0..Will not write any CAST JPEG Encoder Control register.
69874  *  0b1..Will write "1" to Cast JPEG Encoder [Go] Control Register.
69875  */
69876 #define JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START_MASK)
69877 #define JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod_MASK (0x200U)
69878 #define JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod_SHIFT (9U)
69879 /*! Config_Mod - Current Encoding precision: 8bit or 12bit.
69880  */
69881 #define JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod_MASK)
69882 /*! @} */
69883 
69884 /*! @name SLOT_STATUS - Bit Stream SLOT Status */
69885 /*! @{ */
69886 #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF_MASK (0x1U)
69887 #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF_SHIFT (0U)
69888 /*! STMBUF_HALF - Indicating the stream buf pointer has come over half size of the buf size.
69889  */
69890 #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF_MASK)
69891 #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND_MASK (0x2U)
69892 #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND_SHIFT (1U)
69893 /*! STMBUF_RTND - Indicating the stream buf pointer has come over the top size of the stream buffer.
69894  */
69895 #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND_MASK)
69896 #define JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN_MASK (0x4U)
69897 #define JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN_SHIFT (2U)
69898 /*! SWITCHED_IN - Descriptor fetched completed during for this bitstream ID
69899  */
69900 #define JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN_MASK)
69901 #define JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE_MASK (0x8U)
69902 #define JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE_SHIFT (3U)
69903 /*! FRMDONE - One frame of image Encoding finished
69904  */
69905 #define JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE(x)  (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE_MASK)
69906 #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR_MASK (0x100U)
69907 #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR_SHIFT (8U)
69908 /*! ENC_CONFG_ERR - Cast JPEG Encoder Configure error flag
69909  */
69910 #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR_MASK)
69911 #define JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR_MASK (0x200U)
69912 #define JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR_SHIFT (9U)
69913 /*! DES_RD_ERR - AXI Read error status for descriptor fetching
69914  */
69915 #define JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR_MASK)
69916 #define JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR_MASK (0x400U)
69917 #define JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR_SHIFT (10U)
69918 /*! BIT_WT_ERR - AXI Write error status for bitstream storing
69919  */
69920 #define JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR_MASK)
69921 #define JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR_MASK (0x800U)
69922 #define JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR_SHIFT (11U)
69923 /*! IMG_RD_ERR - AXI Read error status for image or configuration bitstream fetching
69924  */
69925 #define JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR_MASK)
69926 #define JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT_MASK (0x60000000U)
69927 #define JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT_SHIFT (29U)
69928 /*! CUR_SLOT - Current Executing bitstream slot
69929  */
69930 #define JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT_MASK)
69931 #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING_MASK (0x80000000U)
69932 #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING_SHIFT (31U)
69933 /*! ENC_ONGOING - Indicating the encoding is ongoing.
69934  */
69935 #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING_MASK)
69936 /*! @} */
69937 
69938 /* The count of JPEG_ENC_WRAPPER_SLOT_STATUS */
69939 #define JPEG_ENC_WRAPPER_SLOT_STATUS_COUNT       (4U)
69940 
69941 /*! @name SLOT_IRQ_EN - Bit Stream Interrupt Enable Register */
69942 /*! @{ */
69943 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en_MASK (0x1U)
69944 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en_SHIFT (0U)
69945 /*! STMBUF_HALF_irq_en - Interrupt enable for current buf pointer over half size of the buf size.
69946  */
69947 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en_MASK)
69948 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en_MASK (0x2U)
69949 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en_SHIFT (1U)
69950 /*! STMBUF_RTND_irq_en - Interrupt enable for current buf pointer wrapper over the top size of the stream buffer.
69951  */
69952 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en_MASK)
69953 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en_MASK (0x4U)
69954 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en_SHIFT (2U)
69955 /*! SWITHCED_IN_irq_en - Indicating the stream buf pointer has come over half size of the buf size.
69956  */
69957 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en_MASK)
69958 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en_MASK (0x8U)
69959 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en_SHIFT (3U)
69960 /*! FRMDONE_irq_en - Frame encoding finished interrupt enable
69961  */
69962 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en_MASK)
69963 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en_MASK (0x100U)
69964 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en_SHIFT (8U)
69965 /*! ENC_CONFG_ERR_irq_en - Encoder Configure Error Interrupt Enable
69966  */
69967 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en_MASK)
69968 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK (0x200U)
69969 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT (9U)
69970 /*! DES_RD_ERR_irq_en - AXI read error interrupt enable
69971  */
69972 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK)
69973 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en_MASK (0x400U)
69974 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en_SHIFT (10U)
69975 /*! BIT_WT_ERR_irq_en - AXI write error interrupt enable
69976  */
69977 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en_MASK)
69978 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en_MASK (0x800U)
69979 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en_SHIFT (11U)
69980 /*! IMG_RD_ERR_irq_en - AXI write error interrupt enable
69981  */
69982 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en_MASK)
69983 /*! @} */
69984 
69985 /* The count of JPEG_ENC_WRAPPER_SLOT_IRQ_EN */
69986 #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_COUNT       (4U)
69987 
69988 /*! @name SLOT_BUF_PTR - Bit Stream Buffer Pointer */
69989 /*! @{ */
69990 #define JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_MASK (0xFFFFFFFFU)
69991 #define JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_SHIFT (0U)
69992 /*! stmbuf_ptr - stream0 buf pointer
69993  */
69994 #define JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_MASK)
69995 /*! @} */
69996 
69997 /* The count of JPEG_ENC_WRAPPER_SLOT_BUF_PTR */
69998 #define JPEG_ENC_WRAPPER_SLOT_BUF_PTR_COUNT      (4U)
69999 
70000 /*! @name SLOT_CUR_DESCPT_PTR - Current Encoding Descriptor Pointer */
70001 /*! @{ */
70002 #define JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU)
70003 #define JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U)
70004 /*! CUR_DESCPT_PRT - current slot the fetched descriptors pointer.
70005  */
70006 #define JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK)
70007 /*! @} */
70008 
70009 /* The count of JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR */
70010 #define JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_COUNT (4U)
70011 
70012 /*! @name SLOT_NXT_DESCPT_PTR - Next Encoding Descriptor Pointer */
70013 /*! @{ */
70014 #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK (0x1U)
70015 #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT (0U)
70016 /*! NXT_DESCPT_PTR_EN - slot next stream descriptor pointor enable
70017  */
70018 #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK)
70019 #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK (0xFFFFFFFCU)
70020 #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT (2U)
70021 /*! NXT_DESCPT_PRT - slot next encoding descriptors pointer
70022  */
70023 #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK)
70024 /*! @} */
70025 
70026 /* The count of JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR */
70027 #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_COUNT (4U)
70028 
70029 
70030 /*!
70031  * @}
70032  */ /* end of group JPEG_ENC_WRAPPER_Register_Masks */
70033 
70034 
70035 /* JPEG_ENC_WRAPPER - Peripheral instance base addresses */
70036 /** Peripheral IMAGING__ENCODE_U_JPEG_ENC_WRAPPER base address */
70037 #define IMAGING__ENCODE_U_JPEG_ENC_WRAPPER_BASE  (0x58450000u)
70038 /** Peripheral IMAGING__ENCODE_U_JPEG_ENC_WRAPPER base pointer */
70039 #define IMAGING__ENCODE_U_JPEG_ENC_WRAPPER       ((JPEG_ENC_WRAPPER_Type *)IMAGING__ENCODE_U_JPEG_ENC_WRAPPER_BASE)
70040 /** Array initializer of JPEG_ENC_WRAPPER peripheral base addresses */
70041 #define JPEG_ENC_WRAPPER_BASE_ADDRS              { IMAGING__ENCODE_U_JPEG_ENC_WRAPPER_BASE }
70042 /** Array initializer of JPEG_ENC_WRAPPER peripheral base pointers */
70043 #define JPEG_ENC_WRAPPER_BASE_PTRS               { IMAGING__ENCODE_U_JPEG_ENC_WRAPPER }
70044 
70045 /*!
70046  * @}
70047  */ /* end of group JPEG_ENC_WRAPPER_Peripheral_Access_Layer */
70048 
70049 
70050 /* ----------------------------------------------------------------------------
70051    -- KPP Peripheral Access Layer
70052    ---------------------------------------------------------------------------- */
70053 
70054 /*!
70055  * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
70056  * @{
70057  */
70058 
70059 /** KPP - Register Layout Typedef */
70060 typedef struct {
70061   __IO uint16_t KPCR;                              /**< Keypad Control Register, offset: 0x0 */
70062   __IO uint16_t KPSR;                              /**< Keypad Status Register, offset: 0x2 */
70063   __IO uint16_t KDDR;                              /**< Keypad Data Direction Register, offset: 0x4 */
70064   __IO uint16_t KPDR;                              /**< Keypad Data Register, offset: 0x6 */
70065 } KPP_Type;
70066 
70067 /* ----------------------------------------------------------------------------
70068    -- KPP Register Masks
70069    ---------------------------------------------------------------------------- */
70070 
70071 /*!
70072  * @addtogroup KPP_Register_Masks KPP Register Masks
70073  * @{
70074  */
70075 
70076 /*! @name KPCR - Keypad Control Register */
70077 /*! @{ */
70078 #define KPP_KPCR_KRE_MASK                        (0xFFU)
70079 #define KPP_KPCR_KRE_SHIFT                       (0U)
70080 /*! KRE - KRE
70081  *  0b00000000..Row is not included in the keypad key press detect.
70082  *  0b00000001..Row is included in the keypad key press detect.
70083  */
70084 #define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
70085 #define KPP_KPCR_KCO_MASK                        (0xFF00U)
70086 #define KPP_KPCR_KCO_SHIFT                       (8U)
70087 /*! KCO - KCO
70088  *  0b00000000..Column strobe output is totem pole drive.
70089  *  0b00000001..Column strobe output is open drain.
70090  */
70091 #define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
70092 /*! @} */
70093 
70094 /*! @name KPSR - Keypad Status Register */
70095 /*! @{ */
70096 #define KPP_KPSR_KPKD_MASK                       (0x1U)
70097 #define KPP_KPSR_KPKD_SHIFT                      (0U)
70098 /*! KPKD - KPKD
70099  *  0b0..No key presses detected
70100  *  0b1..A key has been depressed
70101  */
70102 #define KPP_KPSR_KPKD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
70103 #define KPP_KPSR_KPKR_MASK                       (0x2U)
70104 #define KPP_KPSR_KPKR_SHIFT                      (1U)
70105 /*! KPKR - KPKR
70106  *  0b0..No key release detected
70107  *  0b1..All keys have been released
70108  */
70109 #define KPP_KPSR_KPKR(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
70110 #define KPP_KPSR_KDSC_MASK                       (0x4U)
70111 #define KPP_KPSR_KDSC_SHIFT                      (2U)
70112 /*! KDSC - KDSC
70113  *  0b0..No effect
70114  *  0b1..Set bits that clear the keypad depress synchronizer chain
70115  */
70116 #define KPP_KPSR_KDSC(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
70117 #define KPP_KPSR_KRSS_MASK                       (0x8U)
70118 #define KPP_KPSR_KRSS_SHIFT                      (3U)
70119 /*! KRSS - KRSS
70120  *  0b0..No effect
70121  *  0b1..Set bits which sets keypad release synchronizer chain
70122  */
70123 #define KPP_KPSR_KRSS(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
70124 #define KPP_KPSR_KDIE_MASK                       (0x100U)
70125 #define KPP_KPSR_KDIE_SHIFT                      (8U)
70126 /*! KDIE - KDIE
70127  *  0b0..No interrupt request is generated when KPKD is set.
70128  *  0b1..An interrupt request is generated when KPKD is set.
70129  */
70130 #define KPP_KPSR_KDIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
70131 #define KPP_KPSR_KRIE_MASK                       (0x200U)
70132 #define KPP_KPSR_KRIE_SHIFT                      (9U)
70133 /*! KRIE - KRIE
70134  *  0b0..No interrupt request is generated when KPKR is set.
70135  *  0b1..An interrupt request is generated when KPKR is set.
70136  */
70137 #define KPP_KPSR_KRIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
70138 /*! @} */
70139 
70140 /*! @name KDDR - Keypad Data Direction Register */
70141 /*! @{ */
70142 #define KPP_KDDR_KRDD_MASK                       (0xFFU)
70143 #define KPP_KDDR_KRDD_SHIFT                      (0U)
70144 /*! KRDD - KRDD
70145  *  0b00000000..ROWn pin configured as an input.
70146  *  0b00000001..ROWn pin configured as an output.
70147  */
70148 #define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
70149 #define KPP_KDDR_KCDD_MASK                       (0xFF00U)
70150 #define KPP_KDDR_KCDD_SHIFT                      (8U)
70151 /*! KCDD - KCDD
70152  *  0b00000000..COLn pin is configured as an input.
70153  *  0b00000001..COLn pin is configured as an output.
70154  */
70155 #define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
70156 /*! @} */
70157 
70158 /*! @name KPDR - Keypad Data Register */
70159 /*! @{ */
70160 #define KPP_KPDR_KRD_MASK                        (0xFFU)
70161 #define KPP_KPDR_KRD_SHIFT                       (0U)
70162 /*! KRD - KRD
70163  */
70164 #define KPP_KPDR_KRD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
70165 #define KPP_KPDR_KCD_MASK                        (0xFF00U)
70166 #define KPP_KPDR_KCD_SHIFT                       (8U)
70167 /*! KCD - KCD
70168  */
70169 #define KPP_KPDR_KCD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
70170 /*! @} */
70171 
70172 
70173 /*!
70174  * @}
70175  */ /* end of group KPP_Register_Masks */
70176 
70177 
70178 /* KPP - Peripheral instance base addresses */
70179 /** Peripheral LSIO__KPP base address */
70180 #define LSIO__KPP_BASE                           (0x5D1A0000u)
70181 /** Peripheral LSIO__KPP base pointer */
70182 #define LSIO__KPP                                ((KPP_Type *)LSIO__KPP_BASE)
70183 /** Array initializer of KPP peripheral base addresses */
70184 #define KPP_BASE_ADDRS                           { LSIO__KPP_BASE }
70185 /** Array initializer of KPP peripheral base pointers */
70186 #define KPP_BASE_PTRS                            { LSIO__KPP }
70187 /** Interrupt vectors for the KPP peripheral type */
70188 #define KPP_IRQS                                 { LSIO_KPP_INT_IRQn }
70189 
70190 /*!
70191  * @}
70192  */ /* end of group KPP_Peripheral_Access_Layer */
70193 
70194 
70195 /* ----------------------------------------------------------------------------
70196    -- LCDIF Peripheral Access Layer
70197    ---------------------------------------------------------------------------- */
70198 
70199 /*!
70200  * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
70201  * @{
70202  */
70203 
70204 /** LCDIF - Register Layout Typedef */
70205 typedef struct {
70206   __IO uint32_t CTRL;                              /**< LCDIF General Control Register, offset: 0x0 */
70207   __IO uint32_t CTRL_SET;                          /**< LCDIF General Control Register, offset: 0x4 */
70208   __IO uint32_t CTRL_CLR;                          /**< LCDIF General Control Register, offset: 0x8 */
70209   __IO uint32_t CTRL_TOG;                          /**< LCDIF General Control Register, offset: 0xC */
70210   __IO uint32_t CTRL1;                             /**< LCDIF General Control1 Register, offset: 0x10 */
70211   __IO uint32_t CTRL1_SET;                         /**< LCDIF General Control1 Register, offset: 0x14 */
70212   __IO uint32_t CTRL1_CLR;                         /**< LCDIF General Control1 Register, offset: 0x18 */
70213   __IO uint32_t CTRL1_TOG;                         /**< LCDIF General Control1 Register, offset: 0x1C */
70214   __IO uint32_t CTRL2;                             /**< LCDIF General Control2 Register, offset: 0x20 */
70215   __IO uint32_t CTRL2_SET;                         /**< LCDIF General Control2 Register, offset: 0x24 */
70216   __IO uint32_t CTRL2_CLR;                         /**< LCDIF General Control2 Register, offset: 0x28 */
70217   __IO uint32_t CTRL2_TOG;                         /**< LCDIF General Control2 Register, offset: 0x2C */
70218   __IO uint32_t TRANSFER_COUNT;                    /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
70219        uint8_t RESERVED_0[12];
70220   __IO uint32_t CUR_BUF;                           /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
70221        uint8_t RESERVED_1[12];
70222   __IO uint32_t NEXT_BUF;                          /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
70223        uint8_t RESERVED_2[12];
70224   __IO uint32_t TIMING;                            /**< LCD Interface Timing Register, offset: 0x60 */
70225        uint8_t RESERVED_3[12];
70226   __IO uint32_t VDCTRL0;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
70227   __IO uint32_t VDCTRL0_SET;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
70228   __IO uint32_t VDCTRL0_CLR;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
70229   __IO uint32_t VDCTRL0_TOG;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
70230   __IO uint32_t VDCTRL1;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
70231        uint8_t RESERVED_4[12];
70232   __IO uint32_t VDCTRL2;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
70233        uint8_t RESERVED_5[12];
70234   __IO uint32_t VDCTRL3;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
70235        uint8_t RESERVED_6[12];
70236   __IO uint32_t VDCTRL4;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
70237        uint8_t RESERVED_7[12];
70238   __IO uint32_t DVICTRL0;                          /**< Digital Video Interface Control0 Register, offset: 0xC0 */
70239        uint8_t RESERVED_8[12];
70240   __IO uint32_t DVICTRL1;                          /**< Digital Video Interface Control1 Register, offset: 0xD0 */
70241        uint8_t RESERVED_9[12];
70242   __IO uint32_t DVICTRL2;                          /**< Digital Video Interface Control2 Register, offset: 0xE0 */
70243        uint8_t RESERVED_10[12];
70244   __IO uint32_t DVICTRL3;                          /**< Digital Video Interface Control3 Register, offset: 0xF0 */
70245        uint8_t RESERVED_11[12];
70246   __IO uint32_t DVICTRL4;                          /**< Digital Video Interface Control4 Register, offset: 0x100 */
70247        uint8_t RESERVED_12[12];
70248   __IO uint32_t CSC_COEFF0;                        /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */
70249        uint8_t RESERVED_13[12];
70250   __IO uint32_t CSC_COEFF1;                        /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */
70251        uint8_t RESERVED_14[12];
70252   __IO uint32_t CSC_COEFF2;                        /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */
70253        uint8_t RESERVED_15[12];
70254   __IO uint32_t CSC_COEFF3;                        /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */
70255        uint8_t RESERVED_16[12];
70256   __IO uint32_t CSC_COEFF4;                        /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */
70257        uint8_t RESERVED_17[12];
70258   __IO uint32_t CSC_OFFSET;                        /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */
70259        uint8_t RESERVED_18[12];
70260   __IO uint32_t CSC_LIMIT;                         /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */
70261        uint8_t RESERVED_19[12];
70262   __IO uint32_t DATA;                              /**< LCD Interface Data Register, offset: 0x180 */
70263        uint8_t RESERVED_20[12];
70264   __IO uint32_t BM_ERROR_STAT;                     /**< Bus Master Error Status Register, offset: 0x190 */
70265        uint8_t RESERVED_21[12];
70266   __IO uint32_t CRC_STAT;                          /**< CRC Status Register, offset: 0x1A0 */
70267        uint8_t RESERVED_22[12];
70268   __I  uint32_t STAT;                              /**< LCD Interface Status Register, offset: 0x1B0 */
70269        uint8_t RESERVED_23[76];
70270   __IO uint32_t THRES;                             /**< LCDIF Threshold Register, offset: 0x200 */
70271        uint8_t RESERVED_24[12];
70272   __IO uint32_t AS_CTRL;                           /**< LCDIF AS Buffer Control Register, offset: 0x210 */
70273        uint8_t RESERVED_25[12];
70274   __IO uint32_t AS_BUF;                            /**< Alpha Surface Buffer Pointer, offset: 0x220 */
70275        uint8_t RESERVED_26[12];
70276   __IO uint32_t AS_NEXT_BUF;                       /**< , offset: 0x230 */
70277        uint8_t RESERVED_27[12];
70278   __IO uint32_t AS_CLRKEYLOW;                      /**< LCDIF Overlay Color Key Low, offset: 0x240 */
70279        uint8_t RESERVED_28[12];
70280   __IO uint32_t AS_CLRKEYHIGH;                     /**< LCDIF Overlay Color Key High, offset: 0x250 */
70281        uint8_t RESERVED_29[12];
70282   __IO uint32_t SYNC_DELAY;                        /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */
70283 } LCDIF_Type;
70284 
70285 /* ----------------------------------------------------------------------------
70286    -- LCDIF Register Masks
70287    ---------------------------------------------------------------------------- */
70288 
70289 /*!
70290  * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
70291  * @{
70292  */
70293 
70294 /*! @name CTRL - LCDIF General Control Register */
70295 /*! @{ */
70296 #define LCDIF_CTRL_RUN_MASK                      (0x1U)
70297 #define LCDIF_CTRL_RUN_SHIFT                     (0U)
70298 #define LCDIF_CTRL_RUN(x)                        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
70299 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK       (0x2U)
70300 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT      (1U)
70301 /*! DATA_FORMAT_24_BIT
70302  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
70303  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
70304  *       each byte do not contain any useful data, and should be dropped.
70305  */
70306 #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
70307 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK       (0x4U)
70308 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT      (2U)
70309 /*! DATA_FORMAT_18_BIT
70310  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
70311  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
70312  */
70313 #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
70314 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK       (0x8U)
70315 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT      (3U)
70316 #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
70317 #define LCDIF_CTRL_RSRVD0_MASK                   (0x10U)
70318 #define LCDIF_CTRL_RSRVD0_SHIFT                  (4U)
70319 #define LCDIF_CTRL_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
70320 #define LCDIF_CTRL_MASTER_MASK                   (0x20U)
70321 #define LCDIF_CTRL_MASTER_SHIFT                  (5U)
70322 #define LCDIF_CTRL_MASTER(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
70323 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK      (0x80U)
70324 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT     (7U)
70325 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK)
70326 #define LCDIF_CTRL_WORD_LENGTH_MASK              (0x300U)
70327 #define LCDIF_CTRL_WORD_LENGTH_SHIFT             (8U)
70328 /*! WORD_LENGTH
70329  *  0b00..Input data is 16 bits per pixel.
70330  *  0b01..Input data is 8 bits wide.
70331  *  0b10..Input data is 18 bits per pixel.
70332  *  0b11..Input data is 24 bits per pixel.
70333  */
70334 #define LCDIF_CTRL_WORD_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
70335 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK        (0xC00U)
70336 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT       (10U)
70337 /*! LCD_DATABUS_WIDTH
70338  *  0b00..16-bit data bus mode.
70339  *  0b01..8-bit data bus mode.
70340  *  0b10..18-bit data bus mode.
70341  *  0b11..24-bit data bus mode.
70342  */
70343 #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
70344 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK         (0x3000U)
70345 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT        (12U)
70346 /*! CSC_DATA_SWIZZLE
70347  *  0b00..No byte swapping.(Little endian)
70348  *  0b00..Little Endian byte ordering (same as NO_SWAP).
70349  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
70350  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
70351  *  0b10..Swap half-words.
70352  *  0b11..Swap bytes within each half-word.
70353  */
70354 #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
70355 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK       (0xC000U)
70356 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT      (14U)
70357 /*! INPUT_DATA_SWIZZLE
70358  *  0b00..No byte swapping.(Little endian)
70359  *  0b00..Little Endian byte ordering (same as NO_SWAP).
70360  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
70361  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
70362  *  0b10..Swap half-words.
70363  *  0b11..Swap bytes within each half-word.
70364  */
70365 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
70366 #define LCDIF_CTRL_DATA_SELECT_MASK              (0x10000U)
70367 #define LCDIF_CTRL_DATA_SELECT_SHIFT             (16U)
70368 /*! DATA_SELECT
70369  *  0b0..Command Mode. LCD_RS signal is Low.
70370  *  0b1..Data Mode. LCD_RS signal is High.
70371  */
70372 #define LCDIF_CTRL_DATA_SELECT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK)
70373 #define LCDIF_CTRL_DOTCLK_MODE_MASK              (0x20000U)
70374 #define LCDIF_CTRL_DOTCLK_MODE_SHIFT             (17U)
70375 #define LCDIF_CTRL_DOTCLK_MODE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
70376 #define LCDIF_CTRL_VSYNC_MODE_MASK               (0x40000U)
70377 #define LCDIF_CTRL_VSYNC_MODE_SHIFT              (18U)
70378 #define LCDIF_CTRL_VSYNC_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK)
70379 #define LCDIF_CTRL_BYPASS_COUNT_MASK             (0x80000U)
70380 #define LCDIF_CTRL_BYPASS_COUNT_SHIFT            (19U)
70381 #define LCDIF_CTRL_BYPASS_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
70382 #define LCDIF_CTRL_DVI_MODE_MASK                 (0x100000U)
70383 #define LCDIF_CTRL_DVI_MODE_SHIFT                (20U)
70384 #define LCDIF_CTRL_DVI_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK)
70385 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK           (0x3E00000U)
70386 #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT          (21U)
70387 #define LCDIF_CTRL_SHIFT_NUM_BITS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
70388 #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK           (0x4000000U)
70389 #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT          (26U)
70390 /*! DATA_SHIFT_DIR
70391  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
70392  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
70393  */
70394 #define LCDIF_CTRL_DATA_SHIFT_DIR(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
70395 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK      (0x8000000U)
70396 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT     (27U)
70397 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK)
70398 #define LCDIF_CTRL_READ_WRITEB_MASK              (0x10000000U)
70399 #define LCDIF_CTRL_READ_WRITEB_SHIFT             (28U)
70400 #define LCDIF_CTRL_READ_WRITEB(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK)
70401 #define LCDIF_CTRL_YCBCR422_INPUT_MASK           (0x20000000U)
70402 #define LCDIF_CTRL_YCBCR422_INPUT_SHIFT          (29U)
70403 #define LCDIF_CTRL_YCBCR422_INPUT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK)
70404 #define LCDIF_CTRL_CLKGATE_MASK                  (0x40000000U)
70405 #define LCDIF_CTRL_CLKGATE_SHIFT                 (30U)
70406 #define LCDIF_CTRL_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
70407 #define LCDIF_CTRL_SFTRST_MASK                   (0x80000000U)
70408 #define LCDIF_CTRL_SFTRST_SHIFT                  (31U)
70409 #define LCDIF_CTRL_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
70410 /*! @} */
70411 
70412 /*! @name CTRL_SET - LCDIF General Control Register */
70413 /*! @{ */
70414 #define LCDIF_CTRL_SET_RUN_MASK                  (0x1U)
70415 #define LCDIF_CTRL_SET_RUN_SHIFT                 (0U)
70416 #define LCDIF_CTRL_SET_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
70417 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK   (0x2U)
70418 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT  (1U)
70419 /*! DATA_FORMAT_24_BIT
70420  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
70421  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
70422  *       each byte do not contain any useful data, and should be dropped.
70423  */
70424 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
70425 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK   (0x4U)
70426 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT  (2U)
70427 /*! DATA_FORMAT_18_BIT
70428  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
70429  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
70430  */
70431 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
70432 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK   (0x8U)
70433 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT  (3U)
70434 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
70435 #define LCDIF_CTRL_SET_RSRVD0_MASK               (0x10U)
70436 #define LCDIF_CTRL_SET_RSRVD0_SHIFT              (4U)
70437 #define LCDIF_CTRL_SET_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
70438 #define LCDIF_CTRL_SET_MASTER_MASK               (0x20U)
70439 #define LCDIF_CTRL_SET_MASTER_SHIFT              (5U)
70440 #define LCDIF_CTRL_SET_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
70441 #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK  (0x80U)
70442 #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U)
70443 #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK)
70444 #define LCDIF_CTRL_SET_WORD_LENGTH_MASK          (0x300U)
70445 #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT         (8U)
70446 /*! WORD_LENGTH
70447  *  0b00..Input data is 16 bits per pixel.
70448  *  0b01..Input data is 8 bits wide.
70449  *  0b10..Input data is 18 bits per pixel.
70450  *  0b11..Input data is 24 bits per pixel.
70451  */
70452 #define LCDIF_CTRL_SET_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
70453 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK    (0xC00U)
70454 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT   (10U)
70455 /*! LCD_DATABUS_WIDTH
70456  *  0b00..16-bit data bus mode.
70457  *  0b01..8-bit data bus mode.
70458  *  0b10..18-bit data bus mode.
70459  *  0b11..24-bit data bus mode.
70460  */
70461 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
70462 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK     (0x3000U)
70463 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT    (12U)
70464 /*! CSC_DATA_SWIZZLE
70465  *  0b00..No byte swapping.(Little endian)
70466  *  0b00..Little Endian byte ordering (same as NO_SWAP).
70467  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
70468  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
70469  *  0b10..Swap half-words.
70470  *  0b11..Swap bytes within each half-word.
70471  */
70472 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
70473 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
70474 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT  (14U)
70475 /*! INPUT_DATA_SWIZZLE
70476  *  0b00..No byte swapping.(Little endian)
70477  *  0b00..Little Endian byte ordering (same as NO_SWAP).
70478  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
70479  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
70480  *  0b10..Swap half-words.
70481  *  0b11..Swap bytes within each half-word.
70482  */
70483 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
70484 #define LCDIF_CTRL_SET_DATA_SELECT_MASK          (0x10000U)
70485 #define LCDIF_CTRL_SET_DATA_SELECT_SHIFT         (16U)
70486 /*! DATA_SELECT
70487  *  0b0..Command Mode. LCD_RS signal is Low.
70488  *  0b1..Data Mode. LCD_RS signal is High.
70489  */
70490 #define LCDIF_CTRL_SET_DATA_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK)
70491 #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK          (0x20000U)
70492 #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT         (17U)
70493 #define LCDIF_CTRL_SET_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
70494 #define LCDIF_CTRL_SET_VSYNC_MODE_MASK           (0x40000U)
70495 #define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT          (18U)
70496 #define LCDIF_CTRL_SET_VSYNC_MODE(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK)
70497 #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK         (0x80000U)
70498 #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT        (19U)
70499 #define LCDIF_CTRL_SET_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
70500 #define LCDIF_CTRL_SET_DVI_MODE_MASK             (0x100000U)
70501 #define LCDIF_CTRL_SET_DVI_MODE_SHIFT            (20U)
70502 #define LCDIF_CTRL_SET_DVI_MODE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK)
70503 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK       (0x3E00000U)
70504 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT      (21U)
70505 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
70506 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK       (0x4000000U)
70507 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT      (26U)
70508 /*! DATA_SHIFT_DIR
70509  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
70510  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
70511  */
70512 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
70513 #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK  (0x8000000U)
70514 #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
70515 #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK)
70516 #define LCDIF_CTRL_SET_READ_WRITEB_MASK          (0x10000000U)
70517 #define LCDIF_CTRL_SET_READ_WRITEB_SHIFT         (28U)
70518 #define LCDIF_CTRL_SET_READ_WRITEB(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK)
70519 #define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK       (0x20000000U)
70520 #define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT      (29U)
70521 #define LCDIF_CTRL_SET_YCBCR422_INPUT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK)
70522 #define LCDIF_CTRL_SET_CLKGATE_MASK              (0x40000000U)
70523 #define LCDIF_CTRL_SET_CLKGATE_SHIFT             (30U)
70524 #define LCDIF_CTRL_SET_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
70525 #define LCDIF_CTRL_SET_SFTRST_MASK               (0x80000000U)
70526 #define LCDIF_CTRL_SET_SFTRST_SHIFT              (31U)
70527 #define LCDIF_CTRL_SET_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
70528 /*! @} */
70529 
70530 /*! @name CTRL_CLR - LCDIF General Control Register */
70531 /*! @{ */
70532 #define LCDIF_CTRL_CLR_RUN_MASK                  (0x1U)
70533 #define LCDIF_CTRL_CLR_RUN_SHIFT                 (0U)
70534 #define LCDIF_CTRL_CLR_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
70535 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK   (0x2U)
70536 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT  (1U)
70537 /*! DATA_FORMAT_24_BIT
70538  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
70539  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
70540  *       each byte do not contain any useful data, and should be dropped.
70541  */
70542 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
70543 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK   (0x4U)
70544 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT  (2U)
70545 /*! DATA_FORMAT_18_BIT
70546  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
70547  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
70548  */
70549 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
70550 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK   (0x8U)
70551 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT  (3U)
70552 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
70553 #define LCDIF_CTRL_CLR_RSRVD0_MASK               (0x10U)
70554 #define LCDIF_CTRL_CLR_RSRVD0_SHIFT              (4U)
70555 #define LCDIF_CTRL_CLR_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
70556 #define LCDIF_CTRL_CLR_MASTER_MASK               (0x20U)
70557 #define LCDIF_CTRL_CLR_MASTER_SHIFT              (5U)
70558 #define LCDIF_CTRL_CLR_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
70559 #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK  (0x80U)
70560 #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U)
70561 #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK)
70562 #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK          (0x300U)
70563 #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT         (8U)
70564 /*! WORD_LENGTH
70565  *  0b00..Input data is 16 bits per pixel.
70566  *  0b01..Input data is 8 bits wide.
70567  *  0b10..Input data is 18 bits per pixel.
70568  *  0b11..Input data is 24 bits per pixel.
70569  */
70570 #define LCDIF_CTRL_CLR_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
70571 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK    (0xC00U)
70572 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT   (10U)
70573 /*! LCD_DATABUS_WIDTH
70574  *  0b00..16-bit data bus mode.
70575  *  0b01..8-bit data bus mode.
70576  *  0b10..18-bit data bus mode.
70577  *  0b11..24-bit data bus mode.
70578  */
70579 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
70580 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK     (0x3000U)
70581 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT    (12U)
70582 /*! CSC_DATA_SWIZZLE
70583  *  0b00..No byte swapping.(Little endian)
70584  *  0b00..Little Endian byte ordering (same as NO_SWAP).
70585  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
70586  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
70587  *  0b10..Swap half-words.
70588  *  0b11..Swap bytes within each half-word.
70589  */
70590 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
70591 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
70592 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT  (14U)
70593 /*! INPUT_DATA_SWIZZLE
70594  *  0b00..No byte swapping.(Little endian)
70595  *  0b00..Little Endian byte ordering (same as NO_SWAP).
70596  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
70597  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
70598  *  0b10..Swap half-words.
70599  *  0b11..Swap bytes within each half-word.
70600  */
70601 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
70602 #define LCDIF_CTRL_CLR_DATA_SELECT_MASK          (0x10000U)
70603 #define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT         (16U)
70604 /*! DATA_SELECT
70605  *  0b0..Command Mode. LCD_RS signal is Low.
70606  *  0b1..Data Mode. LCD_RS signal is High.
70607  */
70608 #define LCDIF_CTRL_CLR_DATA_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK)
70609 #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK          (0x20000U)
70610 #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT         (17U)
70611 #define LCDIF_CTRL_CLR_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
70612 #define LCDIF_CTRL_CLR_VSYNC_MODE_MASK           (0x40000U)
70613 #define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT          (18U)
70614 #define LCDIF_CTRL_CLR_VSYNC_MODE(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK)
70615 #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK         (0x80000U)
70616 #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT        (19U)
70617 #define LCDIF_CTRL_CLR_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
70618 #define LCDIF_CTRL_CLR_DVI_MODE_MASK             (0x100000U)
70619 #define LCDIF_CTRL_CLR_DVI_MODE_SHIFT            (20U)
70620 #define LCDIF_CTRL_CLR_DVI_MODE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK)
70621 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK       (0x3E00000U)
70622 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT      (21U)
70623 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
70624 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK       (0x4000000U)
70625 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT      (26U)
70626 /*! DATA_SHIFT_DIR
70627  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
70628  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
70629  */
70630 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
70631 #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK  (0x8000000U)
70632 #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
70633 #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK)
70634 #define LCDIF_CTRL_CLR_READ_WRITEB_MASK          (0x10000000U)
70635 #define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT         (28U)
70636 #define LCDIF_CTRL_CLR_READ_WRITEB(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK)
70637 #define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK       (0x20000000U)
70638 #define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT      (29U)
70639 #define LCDIF_CTRL_CLR_YCBCR422_INPUT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK)
70640 #define LCDIF_CTRL_CLR_CLKGATE_MASK              (0x40000000U)
70641 #define LCDIF_CTRL_CLR_CLKGATE_SHIFT             (30U)
70642 #define LCDIF_CTRL_CLR_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
70643 #define LCDIF_CTRL_CLR_SFTRST_MASK               (0x80000000U)
70644 #define LCDIF_CTRL_CLR_SFTRST_SHIFT              (31U)
70645 #define LCDIF_CTRL_CLR_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
70646 /*! @} */
70647 
70648 /*! @name CTRL_TOG - LCDIF General Control Register */
70649 /*! @{ */
70650 #define LCDIF_CTRL_TOG_RUN_MASK                  (0x1U)
70651 #define LCDIF_CTRL_TOG_RUN_SHIFT                 (0U)
70652 #define LCDIF_CTRL_TOG_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
70653 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK   (0x2U)
70654 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT  (1U)
70655 /*! DATA_FORMAT_24_BIT
70656  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
70657  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
70658  *       each byte do not contain any useful data, and should be dropped.
70659  */
70660 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
70661 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK   (0x4U)
70662 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT  (2U)
70663 /*! DATA_FORMAT_18_BIT
70664  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
70665  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
70666  */
70667 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
70668 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK   (0x8U)
70669 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT  (3U)
70670 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
70671 #define LCDIF_CTRL_TOG_RSRVD0_MASK               (0x10U)
70672 #define LCDIF_CTRL_TOG_RSRVD0_SHIFT              (4U)
70673 #define LCDIF_CTRL_TOG_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
70674 #define LCDIF_CTRL_TOG_MASTER_MASK               (0x20U)
70675 #define LCDIF_CTRL_TOG_MASTER_SHIFT              (5U)
70676 #define LCDIF_CTRL_TOG_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
70677 #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK  (0x80U)
70678 #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U)
70679 #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK)
70680 #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK          (0x300U)
70681 #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT         (8U)
70682 /*! WORD_LENGTH
70683  *  0b00..Input data is 16 bits per pixel.
70684  *  0b01..Input data is 8 bits wide.
70685  *  0b10..Input data is 18 bits per pixel.
70686  *  0b11..Input data is 24 bits per pixel.
70687  */
70688 #define LCDIF_CTRL_TOG_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
70689 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK    (0xC00U)
70690 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT   (10U)
70691 /*! LCD_DATABUS_WIDTH
70692  *  0b00..16-bit data bus mode.
70693  *  0b01..8-bit data bus mode.
70694  *  0b10..18-bit data bus mode.
70695  *  0b11..24-bit data bus mode.
70696  */
70697 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
70698 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK     (0x3000U)
70699 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT    (12U)
70700 /*! CSC_DATA_SWIZZLE
70701  *  0b00..No byte swapping.(Little endian)
70702  *  0b00..Little Endian byte ordering (same as NO_SWAP).
70703  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
70704  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
70705  *  0b10..Swap half-words.
70706  *  0b11..Swap bytes within each half-word.
70707  */
70708 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
70709 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
70710 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT  (14U)
70711 /*! INPUT_DATA_SWIZZLE
70712  *  0b00..No byte swapping.(Little endian)
70713  *  0b00..Little Endian byte ordering (same as NO_SWAP).
70714  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
70715  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
70716  *  0b10..Swap half-words.
70717  *  0b11..Swap bytes within each half-word.
70718  */
70719 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
70720 #define LCDIF_CTRL_TOG_DATA_SELECT_MASK          (0x10000U)
70721 #define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT         (16U)
70722 /*! DATA_SELECT
70723  *  0b0..Command Mode. LCD_RS signal is Low.
70724  *  0b1..Data Mode. LCD_RS signal is High.
70725  */
70726 #define LCDIF_CTRL_TOG_DATA_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK)
70727 #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK          (0x20000U)
70728 #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT         (17U)
70729 #define LCDIF_CTRL_TOG_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
70730 #define LCDIF_CTRL_TOG_VSYNC_MODE_MASK           (0x40000U)
70731 #define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT          (18U)
70732 #define LCDIF_CTRL_TOG_VSYNC_MODE(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK)
70733 #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK         (0x80000U)
70734 #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT        (19U)
70735 #define LCDIF_CTRL_TOG_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
70736 #define LCDIF_CTRL_TOG_DVI_MODE_MASK             (0x100000U)
70737 #define LCDIF_CTRL_TOG_DVI_MODE_SHIFT            (20U)
70738 #define LCDIF_CTRL_TOG_DVI_MODE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK)
70739 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK       (0x3E00000U)
70740 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT      (21U)
70741 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
70742 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK       (0x4000000U)
70743 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT      (26U)
70744 /*! DATA_SHIFT_DIR
70745  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
70746  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
70747  */
70748 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
70749 #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK  (0x8000000U)
70750 #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
70751 #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK)
70752 #define LCDIF_CTRL_TOG_READ_WRITEB_MASK          (0x10000000U)
70753 #define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT         (28U)
70754 #define LCDIF_CTRL_TOG_READ_WRITEB(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK)
70755 #define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK       (0x20000000U)
70756 #define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT      (29U)
70757 #define LCDIF_CTRL_TOG_YCBCR422_INPUT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK)
70758 #define LCDIF_CTRL_TOG_CLKGATE_MASK              (0x40000000U)
70759 #define LCDIF_CTRL_TOG_CLKGATE_SHIFT             (30U)
70760 #define LCDIF_CTRL_TOG_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
70761 #define LCDIF_CTRL_TOG_SFTRST_MASK               (0x80000000U)
70762 #define LCDIF_CTRL_TOG_SFTRST_SHIFT              (31U)
70763 #define LCDIF_CTRL_TOG_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
70764 /*! @} */
70765 
70766 /*! @name CTRL1 - LCDIF General Control1 Register */
70767 /*! @{ */
70768 #define LCDIF_CTRL1_RESET_MASK                   (0x1U)
70769 #define LCDIF_CTRL1_RESET_SHIFT                  (0U)
70770 /*! RESET
70771  *  0b0..LCD_RESET output signal is low.
70772  *  0b1..LCD_RESET output signal is high.
70773  */
70774 #define LCDIF_CTRL1_RESET(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK)
70775 #define LCDIF_CTRL1_MODE86_MASK                  (0x2U)
70776 #define LCDIF_CTRL1_MODE86_SHIFT                 (1U)
70777 /*! MODE86
70778  *  0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
70779  *  0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
70780  */
70781 #define LCDIF_CTRL1_MODE86(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK)
70782 #define LCDIF_CTRL1_BUSY_ENABLE_MASK             (0x4U)
70783 #define LCDIF_CTRL1_BUSY_ENABLE_SHIFT            (2U)
70784 /*! BUSY_ENABLE
70785  *  0b0..The busy signal from the LCD controller will be ignored.
70786  *  0b1..Enable the use of the busy signal from the LCD controller.
70787  */
70788 #define LCDIF_CTRL1_BUSY_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK)
70789 #define LCDIF_CTRL1_RSRVD0_MASK                  (0xF8U)
70790 #define LCDIF_CTRL1_RSRVD0_SHIFT                 (3U)
70791 #define LCDIF_CTRL1_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
70792 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK          (0x100U)
70793 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT         (8U)
70794 /*! VSYNC_EDGE_IRQ
70795  *  0b0..No Interrupt Request Pending.
70796  *  0b1..Interrupt Request Pending.
70797  */
70798 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
70799 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK      (0x200U)
70800 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT     (9U)
70801 /*! CUR_FRAME_DONE_IRQ
70802  *  0b0..No Interrupt Request Pending.
70803  *  0b1..Interrupt Request Pending.
70804  */
70805 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
70806 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK           (0x400U)
70807 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT          (10U)
70808 /*! UNDERFLOW_IRQ
70809  *  0b0..No Interrupt Request Pending.
70810  *  0b1..Interrupt Request Pending.
70811  */
70812 #define LCDIF_CTRL1_UNDERFLOW_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
70813 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK            (0x800U)
70814 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT           (11U)
70815 /*! OVERFLOW_IRQ
70816  *  0b0..No Interrupt Request Pending.
70817  *  0b1..Interrupt Request Pending.
70818  */
70819 #define LCDIF_CTRL1_OVERFLOW_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
70820 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK       (0x1000U)
70821 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT      (12U)
70822 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
70823 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK   (0x2000U)
70824 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT  (13U)
70825 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
70826 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK        (0x4000U)
70827 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT       (14U)
70828 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
70829 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK         (0x8000U)
70830 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT        (15U)
70831 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
70832 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK     (0xF0000U)
70833 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT    (16U)
70834 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
70835 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
70836 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
70837 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
70838 #define LCDIF_CTRL1_FIFO_CLEAR_MASK              (0x200000U)
70839 #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT             (21U)
70840 #define LCDIF_CTRL1_FIFO_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
70841 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
70842 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
70843 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
70844 #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK        (0x800000U)
70845 #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT       (23U)
70846 #define LCDIF_CTRL1_INTERLACE_FIELDS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
70847 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK    (0x1000000U)
70848 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT   (24U)
70849 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
70850 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK            (0x2000000U)
70851 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT           (25U)
70852 /*! BM_ERROR_IRQ
70853  *  0b0..No Interrupt Request Pending.
70854  *  0b1..Interrupt Request Pending.
70855  */
70856 #define LCDIF_CTRL1_BM_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
70857 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK         (0x4000000U)
70858 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT        (26U)
70859 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
70860 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK     (0x8000000U)
70861 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT    (27U)
70862 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK)
70863 /*! @} */
70864 
70865 /*! @name CTRL1_SET - LCDIF General Control1 Register */
70866 /*! @{ */
70867 #define LCDIF_CTRL1_SET_RESET_MASK               (0x1U)
70868 #define LCDIF_CTRL1_SET_RESET_SHIFT              (0U)
70869 /*! RESET
70870  *  0b0..LCD_RESET output signal is low.
70871  *  0b1..LCD_RESET output signal is high.
70872  */
70873 #define LCDIF_CTRL1_SET_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK)
70874 #define LCDIF_CTRL1_SET_MODE86_MASK              (0x2U)
70875 #define LCDIF_CTRL1_SET_MODE86_SHIFT             (1U)
70876 /*! MODE86
70877  *  0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
70878  *  0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
70879  */
70880 #define LCDIF_CTRL1_SET_MODE86(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK)
70881 #define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK         (0x4U)
70882 #define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT        (2U)
70883 /*! BUSY_ENABLE
70884  *  0b0..The busy signal from the LCD controller will be ignored.
70885  *  0b1..Enable the use of the busy signal from the LCD controller.
70886  */
70887 #define LCDIF_CTRL1_SET_BUSY_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK)
70888 #define LCDIF_CTRL1_SET_RSRVD0_MASK              (0xF8U)
70889 #define LCDIF_CTRL1_SET_RSRVD0_SHIFT             (3U)
70890 #define LCDIF_CTRL1_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
70891 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK      (0x100U)
70892 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT     (8U)
70893 /*! VSYNC_EDGE_IRQ
70894  *  0b0..No Interrupt Request Pending.
70895  *  0b1..Interrupt Request Pending.
70896  */
70897 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
70898 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
70899 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
70900 /*! CUR_FRAME_DONE_IRQ
70901  *  0b0..No Interrupt Request Pending.
70902  *  0b1..Interrupt Request Pending.
70903  */
70904 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
70905 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK       (0x400U)
70906 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT      (10U)
70907 /*! UNDERFLOW_IRQ
70908  *  0b0..No Interrupt Request Pending.
70909  *  0b1..Interrupt Request Pending.
70910  */
70911 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
70912 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK        (0x800U)
70913 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT       (11U)
70914 /*! OVERFLOW_IRQ
70915  *  0b0..No Interrupt Request Pending.
70916  *  0b1..Interrupt Request Pending.
70917  */
70918 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
70919 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
70920 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
70921 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
70922 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
70923 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
70924 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
70925 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
70926 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT   (14U)
70927 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
70928 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK     (0x8000U)
70929 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT    (15U)
70930 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
70931 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
70932 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
70933 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
70934 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
70935 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
70936 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
70937 #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK          (0x200000U)
70938 #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT         (21U)
70939 #define LCDIF_CTRL1_SET_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
70940 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
70941 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
70942 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
70943 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK    (0x800000U)
70944 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT   (23U)
70945 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
70946 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
70947 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
70948 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
70949 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK        (0x2000000U)
70950 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT       (25U)
70951 /*! BM_ERROR_IRQ
70952  *  0b0..No Interrupt Request Pending.
70953  *  0b1..Interrupt Request Pending.
70954  */
70955 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
70956 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
70957 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT    (26U)
70958 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
70959 #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
70960 #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U)
70961 #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK)
70962 /*! @} */
70963 
70964 /*! @name CTRL1_CLR - LCDIF General Control1 Register */
70965 /*! @{ */
70966 #define LCDIF_CTRL1_CLR_RESET_MASK               (0x1U)
70967 #define LCDIF_CTRL1_CLR_RESET_SHIFT              (0U)
70968 /*! RESET
70969  *  0b0..LCD_RESET output signal is low.
70970  *  0b1..LCD_RESET output signal is high.
70971  */
70972 #define LCDIF_CTRL1_CLR_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK)
70973 #define LCDIF_CTRL1_CLR_MODE86_MASK              (0x2U)
70974 #define LCDIF_CTRL1_CLR_MODE86_SHIFT             (1U)
70975 /*! MODE86
70976  *  0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
70977  *  0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
70978  */
70979 #define LCDIF_CTRL1_CLR_MODE86(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK)
70980 #define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK         (0x4U)
70981 #define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT        (2U)
70982 /*! BUSY_ENABLE
70983  *  0b0..The busy signal from the LCD controller will be ignored.
70984  *  0b1..Enable the use of the busy signal from the LCD controller.
70985  */
70986 #define LCDIF_CTRL1_CLR_BUSY_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK)
70987 #define LCDIF_CTRL1_CLR_RSRVD0_MASK              (0xF8U)
70988 #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT             (3U)
70989 #define LCDIF_CTRL1_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
70990 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK      (0x100U)
70991 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT     (8U)
70992 /*! VSYNC_EDGE_IRQ
70993  *  0b0..No Interrupt Request Pending.
70994  *  0b1..Interrupt Request Pending.
70995  */
70996 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
70997 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
70998 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
70999 /*! CUR_FRAME_DONE_IRQ
71000  *  0b0..No Interrupt Request Pending.
71001  *  0b1..Interrupt Request Pending.
71002  */
71003 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
71004 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK       (0x400U)
71005 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT      (10U)
71006 /*! UNDERFLOW_IRQ
71007  *  0b0..No Interrupt Request Pending.
71008  *  0b1..Interrupt Request Pending.
71009  */
71010 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
71011 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK        (0x800U)
71012 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT       (11U)
71013 /*! OVERFLOW_IRQ
71014  *  0b0..No Interrupt Request Pending.
71015  *  0b1..Interrupt Request Pending.
71016  */
71017 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
71018 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
71019 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
71020 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
71021 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
71022 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
71023 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
71024 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
71025 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT   (14U)
71026 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
71027 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK     (0x8000U)
71028 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT    (15U)
71029 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
71030 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
71031 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
71032 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
71033 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
71034 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
71035 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
71036 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK          (0x200000U)
71037 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT         (21U)
71038 #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
71039 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
71040 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
71041 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
71042 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK    (0x800000U)
71043 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT   (23U)
71044 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
71045 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
71046 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
71047 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
71048 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK        (0x2000000U)
71049 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT       (25U)
71050 /*! BM_ERROR_IRQ
71051  *  0b0..No Interrupt Request Pending.
71052  *  0b1..Interrupt Request Pending.
71053  */
71054 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
71055 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
71056 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT    (26U)
71057 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
71058 #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
71059 #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U)
71060 #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK)
71061 /*! @} */
71062 
71063 /*! @name CTRL1_TOG - LCDIF General Control1 Register */
71064 /*! @{ */
71065 #define LCDIF_CTRL1_TOG_RESET_MASK               (0x1U)
71066 #define LCDIF_CTRL1_TOG_RESET_SHIFT              (0U)
71067 /*! RESET
71068  *  0b0..LCD_RESET output signal is low.
71069  *  0b1..LCD_RESET output signal is high.
71070  */
71071 #define LCDIF_CTRL1_TOG_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK)
71072 #define LCDIF_CTRL1_TOG_MODE86_MASK              (0x2U)
71073 #define LCDIF_CTRL1_TOG_MODE86_SHIFT             (1U)
71074 /*! MODE86
71075  *  0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
71076  *  0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
71077  */
71078 #define LCDIF_CTRL1_TOG_MODE86(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK)
71079 #define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK         (0x4U)
71080 #define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT        (2U)
71081 /*! BUSY_ENABLE
71082  *  0b0..The busy signal from the LCD controller will be ignored.
71083  *  0b1..Enable the use of the busy signal from the LCD controller.
71084  */
71085 #define LCDIF_CTRL1_TOG_BUSY_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK)
71086 #define LCDIF_CTRL1_TOG_RSRVD0_MASK              (0xF8U)
71087 #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT             (3U)
71088 #define LCDIF_CTRL1_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
71089 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK      (0x100U)
71090 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT     (8U)
71091 /*! VSYNC_EDGE_IRQ
71092  *  0b0..No Interrupt Request Pending.
71093  *  0b1..Interrupt Request Pending.
71094  */
71095 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
71096 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
71097 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
71098 /*! CUR_FRAME_DONE_IRQ
71099  *  0b0..No Interrupt Request Pending.
71100  *  0b1..Interrupt Request Pending.
71101  */
71102 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
71103 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK       (0x400U)
71104 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT      (10U)
71105 /*! UNDERFLOW_IRQ
71106  *  0b0..No Interrupt Request Pending.
71107  *  0b1..Interrupt Request Pending.
71108  */
71109 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
71110 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK        (0x800U)
71111 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT       (11U)
71112 /*! OVERFLOW_IRQ
71113  *  0b0..No Interrupt Request Pending.
71114  *  0b1..Interrupt Request Pending.
71115  */
71116 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
71117 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
71118 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
71119 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
71120 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
71121 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
71122 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
71123 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
71124 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT   (14U)
71125 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
71126 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK     (0x8000U)
71127 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT    (15U)
71128 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
71129 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
71130 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
71131 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
71132 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
71133 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
71134 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
71135 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK          (0x200000U)
71136 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT         (21U)
71137 #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
71138 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
71139 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
71140 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
71141 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK    (0x800000U)
71142 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT   (23U)
71143 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
71144 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
71145 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
71146 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
71147 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK        (0x2000000U)
71148 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT       (25U)
71149 /*! BM_ERROR_IRQ
71150  *  0b0..No Interrupt Request Pending.
71151  *  0b1..Interrupt Request Pending.
71152  */
71153 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
71154 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
71155 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT    (26U)
71156 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
71157 #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
71158 #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U)
71159 #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK)
71160 /*! @} */
71161 
71162 /*! @name CTRL2 - LCDIF General Control2 Register */
71163 /*! @{ */
71164 #define LCDIF_CTRL2_RSRVD0_MASK                  (0x1U)
71165 #define LCDIF_CTRL2_RSRVD0_SHIFT                 (0U)
71166 #define LCDIF_CTRL2_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
71167 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK      (0xEU)
71168 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT     (1U)
71169 #define LCDIF_CTRL2_INITIAL_DUMMY_READ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK)
71170 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
71171 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
71172 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
71173 #define LCDIF_CTRL2_RSRVD1_MASK                  (0x80U)
71174 #define LCDIF_CTRL2_RSRVD1_SHIFT                 (7U)
71175 #define LCDIF_CTRL2_RSRVD1(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK)
71176 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK   (0x100U)
71177 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT  (8U)
71178 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK)
71179 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
71180 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
71181 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
71182 #define LCDIF_CTRL2_READ_PACK_DIR_MASK           (0x400U)
71183 #define LCDIF_CTRL2_READ_PACK_DIR_SHIFT          (10U)
71184 #define LCDIF_CTRL2_READ_PACK_DIR(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK)
71185 #define LCDIF_CTRL2_RSRVD2_MASK                  (0x800U)
71186 #define LCDIF_CTRL2_RSRVD2_SHIFT                 (11U)
71187 #define LCDIF_CTRL2_RSRVD2(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK)
71188 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK       (0x7000U)
71189 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT      (12U)
71190 /*! EVEN_LINE_PATTERN
71191  *  0b000..RGB
71192  *  0b001..RBG
71193  *  0b010..GBR
71194  *  0b011..GRB
71195  *  0b100..BRG
71196  *  0b101..BGR
71197  */
71198 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
71199 #define LCDIF_CTRL2_RSRVD3_MASK                  (0x8000U)
71200 #define LCDIF_CTRL2_RSRVD3_SHIFT                 (15U)
71201 #define LCDIF_CTRL2_RSRVD3(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
71202 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK        (0x70000U)
71203 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT       (16U)
71204 /*! ODD_LINE_PATTERN
71205  *  0b000..RGB
71206  *  0b001..RBG
71207  *  0b010..GBR
71208  *  0b011..GRB
71209  *  0b100..BRG
71210  *  0b101..BGR
71211  */
71212 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
71213 #define LCDIF_CTRL2_RSRVD4_MASK                  (0x80000U)
71214 #define LCDIF_CTRL2_RSRVD4_SHIFT                 (19U)
71215 #define LCDIF_CTRL2_RSRVD4(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
71216 #define LCDIF_CTRL2_BURST_LEN_8_MASK             (0x100000U)
71217 #define LCDIF_CTRL2_BURST_LEN_8_SHIFT            (20U)
71218 #define LCDIF_CTRL2_BURST_LEN_8(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
71219 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK        (0xE00000U)
71220 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT       (21U)
71221 /*! OUTSTANDING_REQS
71222  *  0b000..REQ_1
71223  *  0b001..REQ_2
71224  *  0b010..REQ_4
71225  *  0b011..REQ_8
71226  *  0b100..REQ_16
71227  */
71228 #define LCDIF_CTRL2_OUTSTANDING_REQS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
71229 #define LCDIF_CTRL2_RSRVD5_MASK                  (0xFF000000U)
71230 #define LCDIF_CTRL2_RSRVD5_SHIFT                 (24U)
71231 #define LCDIF_CTRL2_RSRVD5(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
71232 /*! @} */
71233 
71234 /*! @name CTRL2_SET - LCDIF General Control2 Register */
71235 /*! @{ */
71236 #define LCDIF_CTRL2_SET_RSRVD0_MASK              (0x1U)
71237 #define LCDIF_CTRL2_SET_RSRVD0_SHIFT             (0U)
71238 #define LCDIF_CTRL2_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
71239 #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK  (0xEU)
71240 #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U)
71241 #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK)
71242 #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
71243 #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
71244 #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
71245 #define LCDIF_CTRL2_SET_RSRVD1_MASK              (0x80U)
71246 #define LCDIF_CTRL2_SET_RSRVD1_SHIFT             (7U)
71247 #define LCDIF_CTRL2_SET_RSRVD1(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK)
71248 #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U)
71249 #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U)
71250 #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK)
71251 #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
71252 #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
71253 #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
71254 #define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK       (0x400U)
71255 #define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT      (10U)
71256 #define LCDIF_CTRL2_SET_READ_PACK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK)
71257 #define LCDIF_CTRL2_SET_RSRVD2_MASK              (0x800U)
71258 #define LCDIF_CTRL2_SET_RSRVD2_SHIFT             (11U)
71259 #define LCDIF_CTRL2_SET_RSRVD2(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK)
71260 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK   (0x7000U)
71261 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT  (12U)
71262 /*! EVEN_LINE_PATTERN
71263  *  0b000..RGB
71264  *  0b001..RBG
71265  *  0b010..GBR
71266  *  0b011..GRB
71267  *  0b100..BRG
71268  *  0b101..BGR
71269  */
71270 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
71271 #define LCDIF_CTRL2_SET_RSRVD3_MASK              (0x8000U)
71272 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT             (15U)
71273 #define LCDIF_CTRL2_SET_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
71274 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK    (0x70000U)
71275 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT   (16U)
71276 /*! ODD_LINE_PATTERN
71277  *  0b000..RGB
71278  *  0b001..RBG
71279  *  0b010..GBR
71280  *  0b011..GRB
71281  *  0b100..BRG
71282  *  0b101..BGR
71283  */
71284 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
71285 #define LCDIF_CTRL2_SET_RSRVD4_MASK              (0x80000U)
71286 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT             (19U)
71287 #define LCDIF_CTRL2_SET_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
71288 #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK         (0x100000U)
71289 #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT        (20U)
71290 #define LCDIF_CTRL2_SET_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
71291 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK    (0xE00000U)
71292 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT   (21U)
71293 /*! OUTSTANDING_REQS
71294  *  0b000..REQ_1
71295  *  0b001..REQ_2
71296  *  0b010..REQ_4
71297  *  0b011..REQ_8
71298  *  0b100..REQ_16
71299  */
71300 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
71301 #define LCDIF_CTRL2_SET_RSRVD5_MASK              (0xFF000000U)
71302 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT             (24U)
71303 #define LCDIF_CTRL2_SET_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
71304 /*! @} */
71305 
71306 /*! @name CTRL2_CLR - LCDIF General Control2 Register */
71307 /*! @{ */
71308 #define LCDIF_CTRL2_CLR_RSRVD0_MASK              (0x1U)
71309 #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT             (0U)
71310 #define LCDIF_CTRL2_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
71311 #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK  (0xEU)
71312 #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U)
71313 #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK)
71314 #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
71315 #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
71316 #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
71317 #define LCDIF_CTRL2_CLR_RSRVD1_MASK              (0x80U)
71318 #define LCDIF_CTRL2_CLR_RSRVD1_SHIFT             (7U)
71319 #define LCDIF_CTRL2_CLR_RSRVD1(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK)
71320 #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U)
71321 #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U)
71322 #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK)
71323 #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
71324 #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
71325 #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
71326 #define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK       (0x400U)
71327 #define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT      (10U)
71328 #define LCDIF_CTRL2_CLR_READ_PACK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK)
71329 #define LCDIF_CTRL2_CLR_RSRVD2_MASK              (0x800U)
71330 #define LCDIF_CTRL2_CLR_RSRVD2_SHIFT             (11U)
71331 #define LCDIF_CTRL2_CLR_RSRVD2(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK)
71332 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK   (0x7000U)
71333 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT  (12U)
71334 /*! EVEN_LINE_PATTERN
71335  *  0b000..RGB
71336  *  0b001..RBG
71337  *  0b010..GBR
71338  *  0b011..GRB
71339  *  0b100..BRG
71340  *  0b101..BGR
71341  */
71342 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
71343 #define LCDIF_CTRL2_CLR_RSRVD3_MASK              (0x8000U)
71344 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT             (15U)
71345 #define LCDIF_CTRL2_CLR_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
71346 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK    (0x70000U)
71347 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT   (16U)
71348 /*! ODD_LINE_PATTERN
71349  *  0b000..RGB
71350  *  0b001..RBG
71351  *  0b010..GBR
71352  *  0b011..GRB
71353  *  0b100..BRG
71354  *  0b101..BGR
71355  */
71356 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
71357 #define LCDIF_CTRL2_CLR_RSRVD4_MASK              (0x80000U)
71358 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT             (19U)
71359 #define LCDIF_CTRL2_CLR_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
71360 #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK         (0x100000U)
71361 #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT        (20U)
71362 #define LCDIF_CTRL2_CLR_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
71363 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK    (0xE00000U)
71364 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT   (21U)
71365 /*! OUTSTANDING_REQS
71366  *  0b000..REQ_1
71367  *  0b001..REQ_2
71368  *  0b010..REQ_4
71369  *  0b011..REQ_8
71370  *  0b100..REQ_16
71371  */
71372 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
71373 #define LCDIF_CTRL2_CLR_RSRVD5_MASK              (0xFF000000U)
71374 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT             (24U)
71375 #define LCDIF_CTRL2_CLR_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
71376 /*! @} */
71377 
71378 /*! @name CTRL2_TOG - LCDIF General Control2 Register */
71379 /*! @{ */
71380 #define LCDIF_CTRL2_TOG_RSRVD0_MASK              (0x1U)
71381 #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT             (0U)
71382 #define LCDIF_CTRL2_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
71383 #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK  (0xEU)
71384 #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U)
71385 #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK)
71386 #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
71387 #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
71388 #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
71389 #define LCDIF_CTRL2_TOG_RSRVD1_MASK              (0x80U)
71390 #define LCDIF_CTRL2_TOG_RSRVD1_SHIFT             (7U)
71391 #define LCDIF_CTRL2_TOG_RSRVD1(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK)
71392 #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U)
71393 #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U)
71394 #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK)
71395 #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
71396 #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
71397 #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
71398 #define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK       (0x400U)
71399 #define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT      (10U)
71400 #define LCDIF_CTRL2_TOG_READ_PACK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK)
71401 #define LCDIF_CTRL2_TOG_RSRVD2_MASK              (0x800U)
71402 #define LCDIF_CTRL2_TOG_RSRVD2_SHIFT             (11U)
71403 #define LCDIF_CTRL2_TOG_RSRVD2(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK)
71404 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK   (0x7000U)
71405 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT  (12U)
71406 /*! EVEN_LINE_PATTERN
71407  *  0b000..RGB
71408  *  0b001..RBG
71409  *  0b010..GBR
71410  *  0b011..GRB
71411  *  0b100..BRG
71412  *  0b101..BGR
71413  */
71414 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
71415 #define LCDIF_CTRL2_TOG_RSRVD3_MASK              (0x8000U)
71416 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT             (15U)
71417 #define LCDIF_CTRL2_TOG_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
71418 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK    (0x70000U)
71419 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT   (16U)
71420 /*! ODD_LINE_PATTERN
71421  *  0b000..RGB
71422  *  0b001..RBG
71423  *  0b010..GBR
71424  *  0b011..GRB
71425  *  0b100..BRG
71426  *  0b101..BGR
71427  */
71428 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
71429 #define LCDIF_CTRL2_TOG_RSRVD4_MASK              (0x80000U)
71430 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT             (19U)
71431 #define LCDIF_CTRL2_TOG_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
71432 #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK         (0x100000U)
71433 #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT        (20U)
71434 #define LCDIF_CTRL2_TOG_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
71435 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK    (0xE00000U)
71436 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT   (21U)
71437 /*! OUTSTANDING_REQS
71438  *  0b000..REQ_1
71439  *  0b001..REQ_2
71440  *  0b010..REQ_4
71441  *  0b011..REQ_8
71442  *  0b100..REQ_16
71443  */
71444 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
71445 #define LCDIF_CTRL2_TOG_RSRVD5_MASK              (0xFF000000U)
71446 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT             (24U)
71447 #define LCDIF_CTRL2_TOG_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
71448 /*! @} */
71449 
71450 /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
71451 /*! @{ */
71452 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK        (0xFFFFU)
71453 #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT       (0U)
71454 #define LCDIF_TRANSFER_COUNT_H_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
71455 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK        (0xFFFF0000U)
71456 #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT       (16U)
71457 #define LCDIF_TRANSFER_COUNT_V_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
71458 /*! @} */
71459 
71460 /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
71461 /*! @{ */
71462 #define LCDIF_CUR_BUF_ADDR_MASK                  (0xFFFFFFFFU)
71463 #define LCDIF_CUR_BUF_ADDR_SHIFT                 (0U)
71464 #define LCDIF_CUR_BUF_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
71465 /*! @} */
71466 
71467 /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
71468 /*! @{ */
71469 #define LCDIF_NEXT_BUF_ADDR_MASK                 (0xFFFFFFFFU)
71470 #define LCDIF_NEXT_BUF_ADDR_SHIFT                (0U)
71471 #define LCDIF_NEXT_BUF_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
71472 /*! @} */
71473 
71474 /*! @name TIMING - LCD Interface Timing Register */
71475 /*! @{ */
71476 #define LCDIF_TIMING_DATA_SETUP_MASK             (0xFFU)
71477 #define LCDIF_TIMING_DATA_SETUP_SHIFT            (0U)
71478 #define LCDIF_TIMING_DATA_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK)
71479 #define LCDIF_TIMING_DATA_HOLD_MASK              (0xFF00U)
71480 #define LCDIF_TIMING_DATA_HOLD_SHIFT             (8U)
71481 #define LCDIF_TIMING_DATA_HOLD(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK)
71482 #define LCDIF_TIMING_CMD_SETUP_MASK              (0xFF0000U)
71483 #define LCDIF_TIMING_CMD_SETUP_SHIFT             (16U)
71484 #define LCDIF_TIMING_CMD_SETUP(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK)
71485 #define LCDIF_TIMING_CMD_HOLD_MASK               (0xFF000000U)
71486 #define LCDIF_TIMING_CMD_HOLD_SHIFT              (24U)
71487 #define LCDIF_TIMING_CMD_HOLD(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK)
71488 /*! @} */
71489 
71490 /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
71491 /*! @{ */
71492 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK     (0x3FFFFU)
71493 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT    (0U)
71494 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
71495 #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK        (0x40000U)
71496 #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT       (18U)
71497 #define LCDIF_VDCTRL0_HALF_LINE_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
71498 #define LCDIF_VDCTRL0_HALF_LINE_MASK             (0x80000U)
71499 #define LCDIF_VDCTRL0_HALF_LINE_SHIFT            (19U)
71500 #define LCDIF_VDCTRL0_HALF_LINE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
71501 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
71502 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
71503 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
71504 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK     (0x200000U)
71505 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT    (21U)
71506 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
71507 #define LCDIF_VDCTRL0_RSRVD1_MASK                (0xC00000U)
71508 #define LCDIF_VDCTRL0_RSRVD1_SHIFT               (22U)
71509 #define LCDIF_VDCTRL0_RSRVD1(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
71510 #define LCDIF_VDCTRL0_ENABLE_POL_MASK            (0x1000000U)
71511 #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT           (24U)
71512 #define LCDIF_VDCTRL0_ENABLE_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
71513 #define LCDIF_VDCTRL0_DOTCLK_POL_MASK            (0x2000000U)
71514 #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT           (25U)
71515 #define LCDIF_VDCTRL0_DOTCLK_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
71516 #define LCDIF_VDCTRL0_HSYNC_POL_MASK             (0x4000000U)
71517 #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT            (26U)
71518 #define LCDIF_VDCTRL0_HSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
71519 #define LCDIF_VDCTRL0_VSYNC_POL_MASK             (0x8000000U)
71520 #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT            (27U)
71521 #define LCDIF_VDCTRL0_VSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
71522 #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK        (0x10000000U)
71523 #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT       (28U)
71524 #define LCDIF_VDCTRL0_ENABLE_PRESENT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
71525 #define LCDIF_VDCTRL0_VSYNC_OEB_MASK             (0x20000000U)
71526 #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT            (29U)
71527 /*! VSYNC_OEB
71528  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
71529  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
71530  */
71531 #define LCDIF_VDCTRL0_VSYNC_OEB(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)
71532 #define LCDIF_VDCTRL0_RSRVD2_MASK                (0xC0000000U)
71533 #define LCDIF_VDCTRL0_RSRVD2_SHIFT               (30U)
71534 #define LCDIF_VDCTRL0_RSRVD2(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
71535 /*! @} */
71536 
71537 /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
71538 /*! @{ */
71539 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
71540 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
71541 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
71542 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK    (0x40000U)
71543 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT   (18U)
71544 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
71545 #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK         (0x80000U)
71546 #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT        (19U)
71547 #define LCDIF_VDCTRL0_SET_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
71548 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
71549 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
71550 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
71551 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
71552 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
71553 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
71554 #define LCDIF_VDCTRL0_SET_RSRVD1_MASK            (0xC00000U)
71555 #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT           (22U)
71556 #define LCDIF_VDCTRL0_SET_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
71557 #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK        (0x1000000U)
71558 #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT       (24U)
71559 #define LCDIF_VDCTRL0_SET_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
71560 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK        (0x2000000U)
71561 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT       (25U)
71562 #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
71563 #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK         (0x4000000U)
71564 #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT        (26U)
71565 #define LCDIF_VDCTRL0_SET_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
71566 #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK         (0x8000000U)
71567 #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT        (27U)
71568 #define LCDIF_VDCTRL0_SET_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
71569 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK    (0x10000000U)
71570 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT   (28U)
71571 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
71572 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK         (0x20000000U)
71573 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT        (29U)
71574 /*! VSYNC_OEB
71575  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
71576  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
71577  */
71578 #define LCDIF_VDCTRL0_SET_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)
71579 #define LCDIF_VDCTRL0_SET_RSRVD2_MASK            (0xC0000000U)
71580 #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT           (30U)
71581 #define LCDIF_VDCTRL0_SET_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
71582 /*! @} */
71583 
71584 /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
71585 /*! @{ */
71586 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
71587 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
71588 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
71589 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK    (0x40000U)
71590 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT   (18U)
71591 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
71592 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK         (0x80000U)
71593 #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT        (19U)
71594 #define LCDIF_VDCTRL0_CLR_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
71595 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
71596 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
71597 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
71598 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
71599 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
71600 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
71601 #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK            (0xC00000U)
71602 #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT           (22U)
71603 #define LCDIF_VDCTRL0_CLR_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
71604 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK        (0x1000000U)
71605 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT       (24U)
71606 #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
71607 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK        (0x2000000U)
71608 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT       (25U)
71609 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
71610 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK         (0x4000000U)
71611 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT        (26U)
71612 #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
71613 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK         (0x8000000U)
71614 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT        (27U)
71615 #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
71616 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK    (0x10000000U)
71617 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT   (28U)
71618 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
71619 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK         (0x20000000U)
71620 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT        (29U)
71621 /*! VSYNC_OEB
71622  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
71623  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
71624  */
71625 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)
71626 #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK            (0xC0000000U)
71627 #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT           (30U)
71628 #define LCDIF_VDCTRL0_CLR_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
71629 /*! @} */
71630 
71631 /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
71632 /*! @{ */
71633 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
71634 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
71635 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
71636 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK    (0x40000U)
71637 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT   (18U)
71638 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
71639 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK         (0x80000U)
71640 #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT        (19U)
71641 #define LCDIF_VDCTRL0_TOG_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
71642 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
71643 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
71644 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
71645 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
71646 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
71647 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
71648 #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK            (0xC00000U)
71649 #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT           (22U)
71650 #define LCDIF_VDCTRL0_TOG_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
71651 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK        (0x1000000U)
71652 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT       (24U)
71653 #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
71654 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK        (0x2000000U)
71655 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT       (25U)
71656 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
71657 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK         (0x4000000U)
71658 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT        (26U)
71659 #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
71660 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK         (0x8000000U)
71661 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT        (27U)
71662 #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
71663 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK    (0x10000000U)
71664 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT   (28U)
71665 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
71666 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK         (0x20000000U)
71667 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT        (29U)
71668 /*! VSYNC_OEB
71669  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
71670  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
71671  */
71672 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)
71673 #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK            (0xC0000000U)
71674 #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT           (30U)
71675 #define LCDIF_VDCTRL0_TOG_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
71676 /*! @} */
71677 
71678 /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
71679 /*! @{ */
71680 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK          (0xFFFFFFFFU)
71681 #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT         (0U)
71682 #define LCDIF_VDCTRL1_VSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
71683 /*! @} */
71684 
71685 /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
71686 /*! @{ */
71687 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK          (0x3FFFFU)
71688 #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT         (0U)
71689 #define LCDIF_VDCTRL2_HSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
71690 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK     (0xFFFC0000U)
71691 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT    (18U)
71692 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
71693 /*! @} */
71694 
71695 /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
71696 /*! @{ */
71697 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK     (0xFFFFU)
71698 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT    (0U)
71699 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
71700 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK   (0xFFF0000U)
71701 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT  (16U)
71702 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
71703 #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK            (0x10000000U)
71704 #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT           (28U)
71705 #define LCDIF_VDCTRL3_VSYNC_ONLY(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
71706 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK      (0x20000000U)
71707 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT     (29U)
71708 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
71709 #define LCDIF_VDCTRL3_RSRVD0_MASK                (0xC0000000U)
71710 #define LCDIF_VDCTRL3_RSRVD0_SHIFT               (30U)
71711 #define LCDIF_VDCTRL3_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
71712 /*! @} */
71713 
71714 /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
71715 /*! @{ */
71716 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
71717 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
71718 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
71719 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK       (0x40000U)
71720 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT      (18U)
71721 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
71722 #define LCDIF_VDCTRL4_RSRVD0_MASK                (0x1FF80000U)
71723 #define LCDIF_VDCTRL4_RSRVD0_SHIFT               (19U)
71724 #define LCDIF_VDCTRL4_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
71725 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK        (0xE0000000U)
71726 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT       (29U)
71727 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
71728 /*! @} */
71729 
71730 /*! @name DVICTRL0 - Digital Video Interface Control0 Register */
71731 /*! @{ */
71732 #define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK       (0xFFFU)
71733 #define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT      (0U)
71734 #define LCDIF_DVICTRL0_H_BLANKING_CNT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK)
71735 #define LCDIF_DVICTRL0_RSRVD0_MASK               (0xF000U)
71736 #define LCDIF_DVICTRL0_RSRVD0_SHIFT              (12U)
71737 #define LCDIF_DVICTRL0_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK)
71738 #define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK         (0xFFF0000U)
71739 #define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT        (16U)
71740 #define LCDIF_DVICTRL0_H_ACTIVE_CNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK)
71741 #define LCDIF_DVICTRL0_RSRVD1_MASK               (0xF0000000U)
71742 #define LCDIF_DVICTRL0_RSRVD1_SHIFT              (28U)
71743 #define LCDIF_DVICTRL0_RSRVD1(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK)
71744 /*! @} */
71745 
71746 /*! @name DVICTRL1 - Digital Video Interface Control1 Register */
71747 /*! @{ */
71748 #define LCDIF_DVICTRL1_F2_START_LINE_MASK        (0x3FFU)
71749 #define LCDIF_DVICTRL1_F2_START_LINE_SHIFT       (0U)
71750 #define LCDIF_DVICTRL1_F2_START_LINE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK)
71751 #define LCDIF_DVICTRL1_F1_END_LINE_MASK          (0xFFC00U)
71752 #define LCDIF_DVICTRL1_F1_END_LINE_SHIFT         (10U)
71753 #define LCDIF_DVICTRL1_F1_END_LINE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK)
71754 #define LCDIF_DVICTRL1_F1_START_LINE_MASK        (0x3FF00000U)
71755 #define LCDIF_DVICTRL1_F1_START_LINE_SHIFT       (20U)
71756 #define LCDIF_DVICTRL1_F1_START_LINE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK)
71757 #define LCDIF_DVICTRL1_RSRVD0_MASK               (0xC0000000U)
71758 #define LCDIF_DVICTRL1_RSRVD0_SHIFT              (30U)
71759 #define LCDIF_DVICTRL1_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK)
71760 /*! @} */
71761 
71762 /*! @name DVICTRL2 - Digital Video Interface Control2 Register */
71763 /*! @{ */
71764 #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK    (0x3FFU)
71765 #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT   (0U)
71766 #define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK)
71767 #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK  (0xFFC00U)
71768 #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U)
71769 #define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK)
71770 #define LCDIF_DVICTRL2_F2_END_LINE_MASK          (0x3FF00000U)
71771 #define LCDIF_DVICTRL2_F2_END_LINE_SHIFT         (20U)
71772 #define LCDIF_DVICTRL2_F2_END_LINE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK)
71773 #define LCDIF_DVICTRL2_RSRVD0_MASK               (0xC0000000U)
71774 #define LCDIF_DVICTRL2_RSRVD0_SHIFT              (30U)
71775 #define LCDIF_DVICTRL2_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK)
71776 /*! @} */
71777 
71778 /*! @name DVICTRL3 - Digital Video Interface Control3 Register */
71779 /*! @{ */
71780 #define LCDIF_DVICTRL3_V_LINES_CNT_MASK          (0x3FFU)
71781 #define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT         (0U)
71782 #define LCDIF_DVICTRL3_V_LINES_CNT(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK)
71783 #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK    (0xFFC00U)
71784 #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT   (10U)
71785 #define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK)
71786 #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK  (0x3FF00000U)
71787 #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U)
71788 #define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK)
71789 #define LCDIF_DVICTRL3_RSRVD0_MASK               (0xC0000000U)
71790 #define LCDIF_DVICTRL3_RSRVD0_SHIFT              (30U)
71791 #define LCDIF_DVICTRL3_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK)
71792 /*! @} */
71793 
71794 /*! @name DVICTRL4 - Digital Video Interface Control4 Register */
71795 /*! @{ */
71796 #define LCDIF_DVICTRL4_H_FILL_CNT_MASK           (0xFFU)
71797 #define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT          (0U)
71798 #define LCDIF_DVICTRL4_H_FILL_CNT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK)
71799 #define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK        (0xFF00U)
71800 #define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT       (8U)
71801 #define LCDIF_DVICTRL4_CR_FILL_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK)
71802 #define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK        (0xFF0000U)
71803 #define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT       (16U)
71804 #define LCDIF_DVICTRL4_CB_FILL_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK)
71805 #define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK         (0xFF000000U)
71806 #define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT        (24U)
71807 #define LCDIF_DVICTRL4_Y_FILL_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK)
71808 /*! @} */
71809 
71810 /*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */
71811 /*! @{ */
71812 #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U)
71813 #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U)
71814 /*! CSC_SUBSAMPLE_FILTER
71815  *  0b00..No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1.
71816  *  0b01..Reserved
71817  *  0b10..Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the
71818  *        two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples.
71819  *  0b11..Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4) and that chroma value
71820  *        exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded.
71821  */
71822 #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK)
71823 #define LCDIF_CSC_COEFF0_RSRVD0_MASK             (0xFFFCU)
71824 #define LCDIF_CSC_COEFF0_RSRVD0_SHIFT            (2U)
71825 #define LCDIF_CSC_COEFF0_RSRVD0(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK)
71826 #define LCDIF_CSC_COEFF0_C0_MASK                 (0x3FF0000U)
71827 #define LCDIF_CSC_COEFF0_C0_SHIFT                (16U)
71828 #define LCDIF_CSC_COEFF0_C0(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK)
71829 #define LCDIF_CSC_COEFF0_RSRVD1_MASK             (0xFC000000U)
71830 #define LCDIF_CSC_COEFF0_RSRVD1_SHIFT            (26U)
71831 #define LCDIF_CSC_COEFF0_RSRVD1(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK)
71832 /*! @} */
71833 
71834 /*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */
71835 /*! @{ */
71836 #define LCDIF_CSC_COEFF1_C1_MASK                 (0x3FFU)
71837 #define LCDIF_CSC_COEFF1_C1_SHIFT                (0U)
71838 #define LCDIF_CSC_COEFF1_C1(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK)
71839 #define LCDIF_CSC_COEFF1_RSRVD0_MASK             (0xFC00U)
71840 #define LCDIF_CSC_COEFF1_RSRVD0_SHIFT            (10U)
71841 #define LCDIF_CSC_COEFF1_RSRVD0(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK)
71842 #define LCDIF_CSC_COEFF1_C2_MASK                 (0x3FF0000U)
71843 #define LCDIF_CSC_COEFF1_C2_SHIFT                (16U)
71844 #define LCDIF_CSC_COEFF1_C2(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK)
71845 #define LCDIF_CSC_COEFF1_RSRVD1_MASK             (0xFC000000U)
71846 #define LCDIF_CSC_COEFF1_RSRVD1_SHIFT            (26U)
71847 #define LCDIF_CSC_COEFF1_RSRVD1(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK)
71848 /*! @} */
71849 
71850 /*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */
71851 /*! @{ */
71852 #define LCDIF_CSC_COEFF2_C3_MASK                 (0x3FFU)
71853 #define LCDIF_CSC_COEFF2_C3_SHIFT                (0U)
71854 #define LCDIF_CSC_COEFF2_C3(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK)
71855 #define LCDIF_CSC_COEFF2_RSRVD0_MASK             (0xFC00U)
71856 #define LCDIF_CSC_COEFF2_RSRVD0_SHIFT            (10U)
71857 #define LCDIF_CSC_COEFF2_RSRVD0(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK)
71858 #define LCDIF_CSC_COEFF2_C4_MASK                 (0x3FF0000U)
71859 #define LCDIF_CSC_COEFF2_C4_SHIFT                (16U)
71860 #define LCDIF_CSC_COEFF2_C4(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK)
71861 #define LCDIF_CSC_COEFF2_RSRVD1_MASK             (0xFC000000U)
71862 #define LCDIF_CSC_COEFF2_RSRVD1_SHIFT            (26U)
71863 #define LCDIF_CSC_COEFF2_RSRVD1(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK)
71864 /*! @} */
71865 
71866 /*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */
71867 /*! @{ */
71868 #define LCDIF_CSC_COEFF3_C5_MASK                 (0x3FFU)
71869 #define LCDIF_CSC_COEFF3_C5_SHIFT                (0U)
71870 #define LCDIF_CSC_COEFF3_C5(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK)
71871 #define LCDIF_CSC_COEFF3_RSRVD0_MASK             (0xFC00U)
71872 #define LCDIF_CSC_COEFF3_RSRVD0_SHIFT            (10U)
71873 #define LCDIF_CSC_COEFF3_RSRVD0(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK)
71874 #define LCDIF_CSC_COEFF3_C6_MASK                 (0x3FF0000U)
71875 #define LCDIF_CSC_COEFF3_C6_SHIFT                (16U)
71876 #define LCDIF_CSC_COEFF3_C6(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK)
71877 #define LCDIF_CSC_COEFF3_RSRVD1_MASK             (0xFC000000U)
71878 #define LCDIF_CSC_COEFF3_RSRVD1_SHIFT            (26U)
71879 #define LCDIF_CSC_COEFF3_RSRVD1(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK)
71880 /*! @} */
71881 
71882 /*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */
71883 /*! @{ */
71884 #define LCDIF_CSC_COEFF4_C7_MASK                 (0x3FFU)
71885 #define LCDIF_CSC_COEFF4_C7_SHIFT                (0U)
71886 #define LCDIF_CSC_COEFF4_C7(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK)
71887 #define LCDIF_CSC_COEFF4_RSRVD0_MASK             (0xFC00U)
71888 #define LCDIF_CSC_COEFF4_RSRVD0_SHIFT            (10U)
71889 #define LCDIF_CSC_COEFF4_RSRVD0(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK)
71890 #define LCDIF_CSC_COEFF4_C8_MASK                 (0x3FF0000U)
71891 #define LCDIF_CSC_COEFF4_C8_SHIFT                (16U)
71892 #define LCDIF_CSC_COEFF4_C8(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK)
71893 #define LCDIF_CSC_COEFF4_RSRVD1_MASK             (0xFC000000U)
71894 #define LCDIF_CSC_COEFF4_RSRVD1_SHIFT            (26U)
71895 #define LCDIF_CSC_COEFF4_RSRVD1(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK)
71896 /*! @} */
71897 
71898 /*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */
71899 /*! @{ */
71900 #define LCDIF_CSC_OFFSET_Y_OFFSET_MASK           (0x1FFU)
71901 #define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT          (0U)
71902 #define LCDIF_CSC_OFFSET_Y_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK)
71903 #define LCDIF_CSC_OFFSET_RSRVD0_MASK             (0xFE00U)
71904 #define LCDIF_CSC_OFFSET_RSRVD0_SHIFT            (9U)
71905 #define LCDIF_CSC_OFFSET_RSRVD0(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK)
71906 #define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK        (0x1FF0000U)
71907 #define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT       (16U)
71908 #define LCDIF_CSC_OFFSET_CBCR_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK)
71909 #define LCDIF_CSC_OFFSET_RSRVD1_MASK             (0xFE000000U)
71910 #define LCDIF_CSC_OFFSET_RSRVD1_SHIFT            (25U)
71911 #define LCDIF_CSC_OFFSET_RSRVD1(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK)
71912 /*! @} */
71913 
71914 /*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */
71915 /*! @{ */
71916 #define LCDIF_CSC_LIMIT_Y_MAX_MASK               (0xFFU)
71917 #define LCDIF_CSC_LIMIT_Y_MAX_SHIFT              (0U)
71918 #define LCDIF_CSC_LIMIT_Y_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK)
71919 #define LCDIF_CSC_LIMIT_Y_MIN_MASK               (0xFF00U)
71920 #define LCDIF_CSC_LIMIT_Y_MIN_SHIFT              (8U)
71921 #define LCDIF_CSC_LIMIT_Y_MIN(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK)
71922 #define LCDIF_CSC_LIMIT_CBCR_MAX_MASK            (0xFF0000U)
71923 #define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT           (16U)
71924 #define LCDIF_CSC_LIMIT_CBCR_MAX(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK)
71925 #define LCDIF_CSC_LIMIT_CBCR_MIN_MASK            (0xFF000000U)
71926 #define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT           (24U)
71927 #define LCDIF_CSC_LIMIT_CBCR_MIN(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK)
71928 /*! @} */
71929 
71930 /*! @name DATA - LCD Interface Data Register */
71931 /*! @{ */
71932 #define LCDIF_DATA_DATA_ZERO_MASK                (0xFFU)
71933 #define LCDIF_DATA_DATA_ZERO_SHIFT               (0U)
71934 #define LCDIF_DATA_DATA_ZERO(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK)
71935 #define LCDIF_DATA_DATA_ONE_MASK                 (0xFF00U)
71936 #define LCDIF_DATA_DATA_ONE_SHIFT                (8U)
71937 #define LCDIF_DATA_DATA_ONE(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK)
71938 #define LCDIF_DATA_DATA_TWO_MASK                 (0xFF0000U)
71939 #define LCDIF_DATA_DATA_TWO_SHIFT                (16U)
71940 #define LCDIF_DATA_DATA_TWO(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK)
71941 #define LCDIF_DATA_DATA_THREE_MASK               (0xFF000000U)
71942 #define LCDIF_DATA_DATA_THREE_SHIFT              (24U)
71943 #define LCDIF_DATA_DATA_THREE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK)
71944 /*! @} */
71945 
71946 /*! @name BM_ERROR_STAT - Bus Master Error Status Register */
71947 /*! @{ */
71948 #define LCDIF_BM_ERROR_STAT_ADDR_MASK            (0xFFFFFFFFU)
71949 #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT           (0U)
71950 #define LCDIF_BM_ERROR_STAT_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
71951 /*! @} */
71952 
71953 /*! @name CRC_STAT - CRC Status Register */
71954 /*! @{ */
71955 #define LCDIF_CRC_STAT_CRC_VALUE_MASK            (0xFFFFFFFFU)
71956 #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT           (0U)
71957 #define LCDIF_CRC_STAT_CRC_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
71958 /*! @} */
71959 
71960 /*! @name STAT - LCD Interface Status Register */
71961 /*! @{ */
71962 #define LCDIF_STAT_LFIFO_COUNT_MASK              (0x1FFU)
71963 #define LCDIF_STAT_LFIFO_COUNT_SHIFT             (0U)
71964 #define LCDIF_STAT_LFIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
71965 #define LCDIF_STAT_RSRVD0_MASK                   (0xFFFE00U)
71966 #define LCDIF_STAT_RSRVD0_SHIFT                  (9U)
71967 #define LCDIF_STAT_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
71968 #define LCDIF_STAT_DVI_CURRENT_FIELD_MASK        (0x1000000U)
71969 #define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT       (24U)
71970 #define LCDIF_STAT_DVI_CURRENT_FIELD(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
71971 #define LCDIF_STAT_BUSY_MASK                     (0x2000000U)
71972 #define LCDIF_STAT_BUSY_SHIFT                    (25U)
71973 #define LCDIF_STAT_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK)
71974 #define LCDIF_STAT_TXFIFO_EMPTY_MASK             (0x4000000U)
71975 #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT            (26U)
71976 #define LCDIF_STAT_TXFIFO_EMPTY(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
71977 #define LCDIF_STAT_TXFIFO_FULL_MASK              (0x8000000U)
71978 #define LCDIF_STAT_TXFIFO_FULL_SHIFT             (27U)
71979 #define LCDIF_STAT_TXFIFO_FULL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
71980 #define LCDIF_STAT_LFIFO_EMPTY_MASK              (0x10000000U)
71981 #define LCDIF_STAT_LFIFO_EMPTY_SHIFT             (28U)
71982 #define LCDIF_STAT_LFIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
71983 #define LCDIF_STAT_LFIFO_FULL_MASK               (0x20000000U)
71984 #define LCDIF_STAT_LFIFO_FULL_SHIFT              (29U)
71985 #define LCDIF_STAT_LFIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
71986 #define LCDIF_STAT_PRESENT_MASK                  (0x80000000U)
71987 #define LCDIF_STAT_PRESENT_SHIFT                 (31U)
71988 #define LCDIF_STAT_PRESENT(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
71989 /*! @} */
71990 
71991 /*! @name THRES - LCDIF Threshold Register */
71992 /*! @{ */
71993 #define LCDIF_THRES_PANIC_MASK                   (0x1FFU)
71994 #define LCDIF_THRES_PANIC_SHIFT                  (0U)
71995 #define LCDIF_THRES_PANIC(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK)
71996 #define LCDIF_THRES_RSRVD1_MASK                  (0xFE00U)
71997 #define LCDIF_THRES_RSRVD1_SHIFT                 (9U)
71998 #define LCDIF_THRES_RSRVD1(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
71999 #define LCDIF_THRES_FASTCLOCK_MASK               (0x1FF0000U)
72000 #define LCDIF_THRES_FASTCLOCK_SHIFT              (16U)
72001 #define LCDIF_THRES_FASTCLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
72002 #define LCDIF_THRES_RSRVD2_MASK                  (0xFE000000U)
72003 #define LCDIF_THRES_RSRVD2_SHIFT                 (25U)
72004 #define LCDIF_THRES_RSRVD2(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
72005 /*! @} */
72006 
72007 /*! @name AS_CTRL - LCDIF AS Buffer Control Register */
72008 /*! @{ */
72009 #define LCDIF_AS_CTRL_AS_ENABLE_MASK             (0x1U)
72010 #define LCDIF_AS_CTRL_AS_ENABLE_SHIFT            (0U)
72011 #define LCDIF_AS_CTRL_AS_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK)
72012 #define LCDIF_AS_CTRL_ALPHA_CTRL_MASK            (0x6U)
72013 #define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT           (1U)
72014 #define LCDIF_AS_CTRL_ALPHA_CTRL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK)
72015 #define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK       (0x8U)
72016 #define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT      (3U)
72017 #define LCDIF_AS_CTRL_ENABLE_COLORKEY(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK)
72018 #define LCDIF_AS_CTRL_FORMAT_MASK                (0xF0U)
72019 #define LCDIF_AS_CTRL_FORMAT_SHIFT               (4U)
72020 #define LCDIF_AS_CTRL_FORMAT(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK)
72021 #define LCDIF_AS_CTRL_ALPHA_MASK                 (0xFF00U)
72022 #define LCDIF_AS_CTRL_ALPHA_SHIFT                (8U)
72023 #define LCDIF_AS_CTRL_ALPHA(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK)
72024 #define LCDIF_AS_CTRL_ROP_MASK                   (0xF0000U)
72025 #define LCDIF_AS_CTRL_ROP_SHIFT                  (16U)
72026 #define LCDIF_AS_CTRL_ROP(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK)
72027 #define LCDIF_AS_CTRL_ALPHA_INVERT_MASK          (0x100000U)
72028 #define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT         (20U)
72029 #define LCDIF_AS_CTRL_ALPHA_INVERT(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK)
72030 #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK    (0x600000U)
72031 #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT   (21U)
72032 #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK)
72033 #define LCDIF_AS_CTRL_PS_DISABLE_MASK            (0x800000U)
72034 #define LCDIF_AS_CTRL_PS_DISABLE_SHIFT           (23U)
72035 #define LCDIF_AS_CTRL_PS_DISABLE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK)
72036 #define LCDIF_AS_CTRL_RVDS1_MASK                 (0x7000000U)
72037 #define LCDIF_AS_CTRL_RVDS1_SHIFT                (24U)
72038 #define LCDIF_AS_CTRL_RVDS1(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK)
72039 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK       (0x8000000U)
72040 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT      (27U)
72041 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
72042 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK    (0x10000000U)
72043 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT   (28U)
72044 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
72045 #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK        (0x20000000U)
72046 #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT       (29U)
72047 #define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK)
72048 #define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK         (0x40000000U)
72049 #define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT        (30U)
72050 #define LCDIF_AS_CTRL_CSI_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK)
72051 #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK      (0x80000000U)
72052 #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT     (31U)
72053 #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK)
72054 /*! @} */
72055 
72056 /*! @name AS_BUF - Alpha Surface Buffer Pointer */
72057 /*! @{ */
72058 #define LCDIF_AS_BUF_ADDR_MASK                   (0xFFFFFFFFU)
72059 #define LCDIF_AS_BUF_ADDR_SHIFT                  (0U)
72060 #define LCDIF_AS_BUF_ADDR(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK)
72061 /*! @} */
72062 
72063 /*! @name AS_NEXT_BUF -  */
72064 /*! @{ */
72065 #define LCDIF_AS_NEXT_BUF_ADDR_MASK              (0xFFFFFFFFU)
72066 #define LCDIF_AS_NEXT_BUF_ADDR_SHIFT             (0U)
72067 #define LCDIF_AS_NEXT_BUF_ADDR(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK)
72068 /*! @} */
72069 
72070 /*! @name AS_CLRKEYLOW - LCDIF Overlay Color Key Low */
72071 /*! @{ */
72072 #define LCDIF_AS_CLRKEYLOW_PIXEL_MASK            (0xFFFFFFU)
72073 #define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT           (0U)
72074 #define LCDIF_AS_CLRKEYLOW_PIXEL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK)
72075 #define LCDIF_AS_CLRKEYLOW_RSVD1_MASK            (0xFF000000U)
72076 #define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT           (24U)
72077 #define LCDIF_AS_CLRKEYLOW_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK)
72078 /*! @} */
72079 
72080 /*! @name AS_CLRKEYHIGH - LCDIF Overlay Color Key High */
72081 /*! @{ */
72082 #define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK           (0xFFFFFFU)
72083 #define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT          (0U)
72084 #define LCDIF_AS_CLRKEYHIGH_PIXEL(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK)
72085 #define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK           (0xFF000000U)
72086 #define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT          (24U)
72087 #define LCDIF_AS_CLRKEYHIGH_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK)
72088 /*! @} */
72089 
72090 /*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */
72091 /*! @{ */
72092 #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK      (0xFFFFU)
72093 #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT     (0U)
72094 #define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK)
72095 #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK      (0xFFFF0000U)
72096 #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT     (16U)
72097 #define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK)
72098 /*! @} */
72099 
72100 
72101 /*!
72102  * @}
72103  */ /* end of group LCDIF_Register_Masks */
72104 
72105 
72106 /* LCDIF - Peripheral instance base addresses */
72107 /** Peripheral ADMA__LCDIF base address */
72108 #define ADMA__LCDIF_BASE                         (0x5A180000u)
72109 /** Peripheral ADMA__LCDIF base pointer */
72110 #define ADMA__LCDIF                              ((LCDIF_Type *)ADMA__LCDIF_BASE)
72111 /** Array initializer of LCDIF peripheral base addresses */
72112 #define LCDIF_BASE_ADDRS                         { ADMA__LCDIF_BASE }
72113 /** Array initializer of LCDIF peripheral base pointers */
72114 #define LCDIF_BASE_PTRS                          { ADMA__LCDIF }
72115 
72116 /*!
72117  * @}
72118  */ /* end of group LCDIF_Peripheral_Access_Layer */
72119 
72120 
72121 /* ----------------------------------------------------------------------------
72122    -- LMEM Peripheral Access Layer
72123    ---------------------------------------------------------------------------- */
72124 
72125 /*!
72126  * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
72127  * @{
72128  */
72129 
72130 /** LMEM - Register Layout Typedef */
72131 typedef struct {
72132   __IO uint32_t PCCCR;                             /**< Cache control register, offset: 0x0 */
72133   __IO uint32_t PCCLCR;                            /**< Cache line control register, offset: 0x4 */
72134   __IO uint32_t PCCSAR;                            /**< Cache search address register, offset: 0x8 */
72135   __IO uint32_t PCCCVR;                            /**< Cache read/write value register, offset: 0xC */
72136        uint8_t RESERVED_0[2032];
72137   __IO uint32_t PSCCR;                             /**< Cache control register, offset: 0x800 */
72138   __IO uint32_t PSCLCR;                            /**< Cache line control register, offset: 0x804 */
72139   __IO uint32_t PSCSAR;                            /**< Cache search address register, offset: 0x808 */
72140   __IO uint32_t PSCCVR;                            /**< Cache read/write value register, offset: 0x80C */
72141 } LMEM_Type;
72142 
72143 /* ----------------------------------------------------------------------------
72144    -- LMEM Register Masks
72145    ---------------------------------------------------------------------------- */
72146 
72147 /*!
72148  * @addtogroup LMEM_Register_Masks LMEM Register Masks
72149  * @{
72150  */
72151 
72152 /*! @name PCCCR - Cache control register */
72153 /*! @{ */
72154 #define LMEM_PCCCR_ENCACHE_MASK                  (0x1U)
72155 #define LMEM_PCCCR_ENCACHE_SHIFT                 (0U)
72156 /*! ENCACHE - Cache enable
72157  *  0b0..Cache disabled
72158  *  0b1..Cache enabled
72159  */
72160 #define LMEM_PCCCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
72161 #define LMEM_PCCCR_ENWRBUF_MASK                  (0x2U)
72162 #define LMEM_PCCCR_ENWRBUF_SHIFT                 (1U)
72163 /*! ENWRBUF - Enable Write Buffer
72164  *  0b0..Write buffer disabled
72165  *  0b1..Write buffer enabled
72166  */
72167 #define LMEM_PCCCR_ENWRBUF(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
72168 #define LMEM_PCCCR_PCCR2_MASK                    (0x4U)
72169 #define LMEM_PCCCR_PCCR2_SHIFT                   (2U)
72170 /*! PCCR2 - Forces all cacheable spaces to write through
72171  */
72172 #define LMEM_PCCCR_PCCR2(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
72173 #define LMEM_PCCCR_PCCR3_MASK                    (0x8U)
72174 #define LMEM_PCCCR_PCCR3_SHIFT                   (3U)
72175 /*! PCCR3 - Forces no allocation on cache misses (must also have PCCR2 asserted)
72176  */
72177 #define LMEM_PCCCR_PCCR3(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
72178 #define LMEM_PCCCR_INVW0_MASK                    (0x1000000U)
72179 #define LMEM_PCCCR_INVW0_SHIFT                   (24U)
72180 /*! INVW0 - Invalidate Way 0
72181  *  0b0..No operation
72182  *  0b1..When setting the GO bit, invalidate all lines in way 0.
72183  */
72184 #define LMEM_PCCCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
72185 #define LMEM_PCCCR_PUSHW0_MASK                   (0x2000000U)
72186 #define LMEM_PCCCR_PUSHW0_SHIFT                  (25U)
72187 /*! PUSHW0 - Push Way 0
72188  *  0b0..No operation
72189  *  0b1..When setting the GO bit, push all modified lines in way 0
72190  */
72191 #define LMEM_PCCCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
72192 #define LMEM_PCCCR_INVW1_MASK                    (0x4000000U)
72193 #define LMEM_PCCCR_INVW1_SHIFT                   (26U)
72194 /*! INVW1 - Invalidate Way 1
72195  *  0b0..No operation
72196  *  0b1..When setting the GO bit, invalidate all lines in way 1
72197  */
72198 #define LMEM_PCCCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
72199 #define LMEM_PCCCR_PUSHW1_MASK                   (0x8000000U)
72200 #define LMEM_PCCCR_PUSHW1_SHIFT                  (27U)
72201 /*! PUSHW1 - Push Way 1
72202  *  0b0..No operation
72203  *  0b1..When setting the GO bit, push all modified lines in way 1
72204  */
72205 #define LMEM_PCCCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
72206 #define LMEM_PCCCR_GO_MASK                       (0x80000000U)
72207 #define LMEM_PCCCR_GO_SHIFT                      (31U)
72208 /*! GO - Initiate Cache Command
72209  *  0b0..Write: no effect. Read: no cache command active.
72210  *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
72211  */
72212 #define LMEM_PCCCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
72213 /*! @} */
72214 
72215 /*! @name PCCLCR - Cache line control register */
72216 /*! @{ */
72217 #define LMEM_PCCLCR_LGO_MASK                     (0x1U)
72218 #define LMEM_PCCLCR_LGO_SHIFT                    (0U)
72219 /*! LGO - Initiate Cache Line Command
72220  *  0b0..Write: no effect. Read: no line command active.
72221  *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
72222  */
72223 #define LMEM_PCCLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
72224 #define LMEM_PCCLCR_CACHEADDR_MASK               (0x3FFCU)
72225 #define LMEM_PCCLCR_CACHEADDR_SHIFT              (2U)
72226 /*! CACHEADDR - Cache address
72227  */
72228 #define LMEM_PCCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
72229 #define LMEM_PCCLCR_WSEL_MASK                    (0x4000U)
72230 #define LMEM_PCCLCR_WSEL_SHIFT                   (14U)
72231 /*! WSEL - Way select
72232  *  0b0..Way 0
72233  *  0b1..Way 1
72234  */
72235 #define LMEM_PCCLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
72236 #define LMEM_PCCLCR_TDSEL_MASK                   (0x10000U)
72237 #define LMEM_PCCLCR_TDSEL_SHIFT                  (16U)
72238 /*! TDSEL - Tag/Data Select
72239  *  0b0..Data
72240  *  0b1..Tag
72241  */
72242 #define LMEM_PCCLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
72243 #define LMEM_PCCLCR_LCIVB_MASK                   (0x100000U)
72244 #define LMEM_PCCLCR_LCIVB_SHIFT                  (20U)
72245 /*! LCIVB - Line Command Initial Valid Bit
72246  */
72247 #define LMEM_PCCLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
72248 #define LMEM_PCCLCR_LCIMB_MASK                   (0x200000U)
72249 #define LMEM_PCCLCR_LCIMB_SHIFT                  (21U)
72250 /*! LCIMB - Line Command Initial Modified Bit
72251  */
72252 #define LMEM_PCCLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
72253 #define LMEM_PCCLCR_LCWAY_MASK                   (0x400000U)
72254 #define LMEM_PCCLCR_LCWAY_SHIFT                  (22U)
72255 /*! LCWAY - Line Command Way
72256  */
72257 #define LMEM_PCCLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
72258 #define LMEM_PCCLCR_LCMD_MASK                    (0x3000000U)
72259 #define LMEM_PCCLCR_LCMD_SHIFT                   (24U)
72260 /*! LCMD - Line Command
72261  *  0b00..Search and read or write
72262  *  0b01..Invalidate
72263  *  0b10..Push
72264  *  0b11..Clear
72265  */
72266 #define LMEM_PCCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
72267 #define LMEM_PCCLCR_LADSEL_MASK                  (0x4000000U)
72268 #define LMEM_PCCLCR_LADSEL_SHIFT                 (26U)
72269 /*! LADSEL - Line Address Select
72270  *  0b0..Cache address
72271  *  0b1..Physical address
72272  */
72273 #define LMEM_PCCLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
72274 #define LMEM_PCCLCR_LACC_MASK                    (0x8000000U)
72275 #define LMEM_PCCLCR_LACC_SHIFT                   (27U)
72276 /*! LACC - Line access type
72277  *  0b0..Read
72278  *  0b1..Write
72279  */
72280 #define LMEM_PCCLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
72281 /*! @} */
72282 
72283 /*! @name PCCSAR - Cache search address register */
72284 /*! @{ */
72285 #define LMEM_PCCSAR_LGO_MASK                     (0x1U)
72286 #define LMEM_PCCSAR_LGO_SHIFT                    (0U)
72287 /*! LGO - Initiate Cache Line Command
72288  *  0b0..Write: no effect. Read: no line command active.
72289  *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
72290  */
72291 #define LMEM_PCCSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
72292 #define LMEM_PCCSAR_PHYADDR_MASK                 (0xFFFFFFFEU)
72293 #define LMEM_PCCSAR_PHYADDR_SHIFT                (1U)
72294 /*! PHYADDR - Physical Address
72295  */
72296 #define LMEM_PCCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
72297 /*! @} */
72298 
72299 /*! @name PCCCVR - Cache read/write value register */
72300 /*! @{ */
72301 #define LMEM_PCCCVR_DATA_MASK                    (0xFFFFFFFFU)
72302 #define LMEM_PCCCVR_DATA_SHIFT                   (0U)
72303 /*! DATA - Cache read/write Data
72304  */
72305 #define LMEM_PCCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
72306 /*! @} */
72307 
72308 /*! @name PSCCR - Cache control register */
72309 /*! @{ */
72310 #define LMEM_PSCCR_ENCACHE_MASK                  (0x1U)
72311 #define LMEM_PSCCR_ENCACHE_SHIFT                 (0U)
72312 /*! ENCACHE - Cache enable
72313  *  0b0..Cache disabled
72314  *  0b1..Cache enabled
72315  */
72316 #define LMEM_PSCCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK)
72317 #define LMEM_PSCCR_ENWRBUF_MASK                  (0x2U)
72318 #define LMEM_PSCCR_ENWRBUF_SHIFT                 (1U)
72319 /*! ENWRBUF - Enable Write Buffer
72320  *  0b0..Write buffer disabled
72321  *  0b1..Write buffer enabled
72322  */
72323 #define LMEM_PSCCR_ENWRBUF(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK)
72324 #define LMEM_PSCCR_INVW0_MASK                    (0x1000000U)
72325 #define LMEM_PSCCR_INVW0_SHIFT                   (24U)
72326 /*! INVW0 - Invalidate Way 0
72327  *  0b0..No operation
72328  *  0b1..When setting the GO bit, invalidate all lines in way 0.
72329  */
72330 #define LMEM_PSCCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK)
72331 #define LMEM_PSCCR_PUSHW0_MASK                   (0x2000000U)
72332 #define LMEM_PSCCR_PUSHW0_SHIFT                  (25U)
72333 /*! PUSHW0 - Push Way 0
72334  *  0b0..No operation
72335  *  0b1..When setting the GO bit, push all modified lines in way 0
72336  */
72337 #define LMEM_PSCCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK)
72338 #define LMEM_PSCCR_INVW1_MASK                    (0x4000000U)
72339 #define LMEM_PSCCR_INVW1_SHIFT                   (26U)
72340 /*! INVW1 - Invalidate Way 1
72341  *  0b0..No operation
72342  *  0b1..When setting the GO bit, invalidate all lines in way 1
72343  */
72344 #define LMEM_PSCCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK)
72345 #define LMEM_PSCCR_PUSHW1_MASK                   (0x8000000U)
72346 #define LMEM_PSCCR_PUSHW1_SHIFT                  (27U)
72347 /*! PUSHW1 - Push Way 1
72348  *  0b0..No operation
72349  *  0b1..When setting the GO bit, push all modified lines in way 1
72350  */
72351 #define LMEM_PSCCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK)
72352 #define LMEM_PSCCR_GO_MASK                       (0x80000000U)
72353 #define LMEM_PSCCR_GO_SHIFT                      (31U)
72354 /*! GO - Initiate Cache Command
72355  *  0b0..Write: no effect. Read: no cache command active.
72356  *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
72357  */
72358 #define LMEM_PSCCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK)
72359 /*! @} */
72360 
72361 /*! @name PSCLCR - Cache line control register */
72362 /*! @{ */
72363 #define LMEM_PSCLCR_LGO_MASK                     (0x1U)
72364 #define LMEM_PSCLCR_LGO_SHIFT                    (0U)
72365 /*! LGO - Initiate Cache Line Command
72366  *  0b0..Write: no effect. Read: no line command active.
72367  *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
72368  */
72369 #define LMEM_PSCLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK)
72370 #define LMEM_PSCLCR_CACHEADDR_MASK               (0x3FFCU)
72371 #define LMEM_PSCLCR_CACHEADDR_SHIFT              (2U)
72372 /*! CACHEADDR - Cache address
72373  */
72374 #define LMEM_PSCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK)
72375 #define LMEM_PSCLCR_WSEL_MASK                    (0x4000U)
72376 #define LMEM_PSCLCR_WSEL_SHIFT                   (14U)
72377 /*! WSEL - Way select
72378  *  0b0..Way 0
72379  *  0b1..Way 1
72380  */
72381 #define LMEM_PSCLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK)
72382 #define LMEM_PSCLCR_TDSEL_MASK                   (0x10000U)
72383 #define LMEM_PSCLCR_TDSEL_SHIFT                  (16U)
72384 /*! TDSEL - Tag/Data Select
72385  *  0b0..Data
72386  *  0b1..Tag
72387  */
72388 #define LMEM_PSCLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK)
72389 #define LMEM_PSCLCR_LCIVB_MASK                   (0x100000U)
72390 #define LMEM_PSCLCR_LCIVB_SHIFT                  (20U)
72391 /*! LCIVB - Line Command Initial Valid Bit
72392  */
72393 #define LMEM_PSCLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK)
72394 #define LMEM_PSCLCR_LCIMB_MASK                   (0x200000U)
72395 #define LMEM_PSCLCR_LCIMB_SHIFT                  (21U)
72396 /*! LCIMB - Line Command Initial Modified Bit
72397  */
72398 #define LMEM_PSCLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK)
72399 #define LMEM_PSCLCR_LCWAY_MASK                   (0x400000U)
72400 #define LMEM_PSCLCR_LCWAY_SHIFT                  (22U)
72401 /*! LCWAY - Line Command Way
72402  */
72403 #define LMEM_PSCLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK)
72404 #define LMEM_PSCLCR_LCMD_MASK                    (0x3000000U)
72405 #define LMEM_PSCLCR_LCMD_SHIFT                   (24U)
72406 /*! LCMD - Line Command
72407  *  0b00..Search and read or write
72408  *  0b01..Invalidate
72409  *  0b10..Push
72410  *  0b11..Clear
72411  */
72412 #define LMEM_PSCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK)
72413 #define LMEM_PSCLCR_LADSEL_MASK                  (0x4000000U)
72414 #define LMEM_PSCLCR_LADSEL_SHIFT                 (26U)
72415 /*! LADSEL - Line Address Select
72416  *  0b0..Cache address
72417  *  0b1..Physical address
72418  */
72419 #define LMEM_PSCLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK)
72420 #define LMEM_PSCLCR_LACC_MASK                    (0x8000000U)
72421 #define LMEM_PSCLCR_LACC_SHIFT                   (27U)
72422 /*! LACC - Line access type
72423  *  0b0..Read
72424  *  0b1..Write
72425  */
72426 #define LMEM_PSCLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK)
72427 /*! @} */
72428 
72429 /*! @name PSCSAR - Cache search address register */
72430 /*! @{ */
72431 #define LMEM_PSCSAR_LGO_MASK                     (0x1U)
72432 #define LMEM_PSCSAR_LGO_SHIFT                    (0U)
72433 /*! LGO - Initiate Cache Line Command
72434  *  0b0..Write: no effect. Read: no line command active.
72435  *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
72436  */
72437 #define LMEM_PSCSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK)
72438 #define LMEM_PSCSAR_PHYADDR_MASK                 (0xFFFFFFFEU)
72439 #define LMEM_PSCSAR_PHYADDR_SHIFT                (1U)
72440 /*! PHYADDR - Physical Address
72441  */
72442 #define LMEM_PSCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK)
72443 /*! @} */
72444 
72445 /*! @name PSCCVR - Cache read/write value register */
72446 /*! @{ */
72447 #define LMEM_PSCCVR_DATA_MASK                    (0xFFFFFFFFU)
72448 #define LMEM_PSCCVR_DATA_SHIFT                   (0U)
72449 /*! DATA - Cache read/write Data
72450  */
72451 #define LMEM_PSCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK)
72452 /*! @} */
72453 
72454 
72455 /*!
72456  * @}
72457  */ /* end of group LMEM_Register_Masks */
72458 
72459 
72460 /* LMEM - Peripheral instance base addresses */
72461 /** Peripheral LMEM base address */
72462 #define LMEM_BASE                                (0xE0082000u)
72463 /** Peripheral LMEM base pointer */
72464 #define LMEM                                     ((LMEM_Type *)LMEM_BASE)
72465 /** Array initializer of LMEM peripheral base addresses */
72466 #define LMEM_BASE_ADDRS                          { LMEM_BASE }
72467 /** Array initializer of LMEM peripheral base pointers */
72468 #define LMEM_BASE_PTRS                           { LMEM }
72469 
72470 /*!
72471  * @}
72472  */ /* end of group LMEM_Peripheral_Access_Layer */
72473 
72474 
72475 /* ----------------------------------------------------------------------------
72476    -- LPC Peripheral Access Layer
72477    ---------------------------------------------------------------------------- */
72478 
72479 /*!
72480  * @addtogroup LPC_Peripheral_Access_Layer LPC Peripheral Access Layer
72481  * @{
72482  */
72483 
72484 /** LPC - Register Layout Typedef */
72485 typedef struct {
72486   __IO uint32_t LPC_PC[7];                         /**< LPC Power Control Register N, array offset: 0x0, array step: 0x4 */
72487   __IO uint32_t LPC_CR;                            /**< LPC Configuration Register, offset: 0x1C */
72488   __IO uint32_t LPC_ED[7];                         /**< LPC Entry Delay Stage N, array offset: 0x20, array step: 0x4 */
72489        uint8_t RESERVED_0[4];
72490   __IO uint32_t LPC_XD[6];                         /**< LPC Exit Delay Stage N, array offset: 0x40, array step: 0x4 */
72491   __IO uint32_t LPC_XD6;                           /**< LPC Exit Delay Stage 6, offset: 0x58 */
72492 } LPC_Type;
72493 
72494 /* ----------------------------------------------------------------------------
72495    -- LPC Register Masks
72496    ---------------------------------------------------------------------------- */
72497 
72498 /*!
72499  * @addtogroup LPC_Register_Masks LPC Register Masks
72500  * @{
72501  */
72502 
72503 /*! @name LPC_PC - LPC Power Control Register N */
72504 /*! @{ */
72505 #define LPC_LPC_PC_PC_MASK                       (0xFFFFFFU)
72506 #define LPC_LPC_PC_PC_SHIFT                      (0U)
72507 /*! PC - Power Control bus
72508  */
72509 #define LPC_LPC_PC_PC(x)                         (((uint32_t)(((uint32_t)(x)) << LPC_LPC_PC_PC_SHIFT)) & LPC_LPC_PC_PC_MASK)
72510 /*! @} */
72511 
72512 /* The count of LPC_LPC_PC */
72513 #define LPC_LPC_PC_COUNT                         (7U)
72514 
72515 /*! @name LPC_CR - LPC Configuration Register */
72516 /*! @{ */
72517 #define LPC_LPC_CR_ROSCDIS_MASK                  (0x1U)
72518 #define LPC_LPC_CR_ROSCDIS_SHIFT                 (0U)
72519 /*! ROSCDIS - ROSC Disable
72520  *  0b0..ROSC enabled during low power mode.
72521  *  0b1..ROSC disabled during low power mode.
72522  */
72523 #define LPC_LPC_CR_ROSCDIS(x)                    (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_ROSCDIS_SHIFT)) & LPC_LPC_CR_ROSCDIS_MASK)
72524 #define LPC_LPC_CR_PMICSTDBY_MASK                (0x2U)
72525 #define LPC_LPC_CR_PMICSTDBY_SHIFT               (1U)
72526 /*! PMICSTDBY - PMIC Standby
72527  *  0b0..PMIC standby request deasserted during low power mode.
72528  *  0b1..PMIC standby request asserted during low power mode.
72529  */
72530 #define LPC_LPC_CR_PMICSTDBY(x)                  (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_PMICSTDBY_SHIFT)) & LPC_LPC_CR_PMICSTDBY_MASK)
72531 #define LPC_LPC_CR_PCSEL_MASK                    (0x4U)
72532 #define LPC_LPC_CR_PCSEL_SHIFT                   (2U)
72533 /*! PCSEL - LPC/DSC Power Control Select
72534  *  0b0..Power controls driven by DSC.
72535  *  0b1..Power controls driven by LPC.
72536  */
72537 #define LPC_LPC_CR_PCSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_PCSEL_SHIFT)) & LPC_LPC_CR_PCSEL_MASK)
72538 #define LPC_LPC_CR_CLKSEL_MASK                   (0x30U)
72539 #define LPC_LPC_CR_CLKSEL_SHIFT                  (4U)
72540 /*! CLKSEL - LPC Clock Select
72541  *  0b00..25MHz clock selected
72542  *  0b01..1MHz clock selected
72543  *  0b10..32kHz clock selected
72544  *  0b11..Reserved
72545  */
72546 #define LPC_LPC_CR_CLKSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_CLKSEL_SHIFT)) & LPC_LPC_CR_CLKSEL_MASK)
72547 #define LPC_LPC_CR_CLKS_MASK                     (0x40U)
72548 #define LPC_LPC_CR_CLKS_SHIFT                    (6U)
72549 /*! CLKS - LPC Clock Status
72550  *  0b0..LPC Clock is not gated.
72551  *  0b1..LPC Clock is gated.
72552  */
72553 #define LPC_LPC_CR_CLKS(x)                       (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_CLKS_SHIFT)) & LPC_LPC_CR_CLKS_MASK)
72554 #define LPC_LPC_CR_CLKG_MASK                     (0x80U)
72555 #define LPC_LPC_CR_CLKG_SHIFT                    (7U)
72556 /*! CLKG - LPC Clock Gate
72557  *  0b0..LPC Clock gate not requested.
72558  *  0b1..LPC Clock gate requested.
72559  */
72560 #define LPC_LPC_CR_CLKG(x)                       (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_CLKG_SHIFT)) & LPC_LPC_CR_CLKG_MASK)
72561 /*! @} */
72562 
72563 /*! @name LPC_ED - LPC Entry Delay Stage N */
72564 /*! @{ */
72565 #define LPC_LPC_ED_ED_MASK                       (0x1FU)
72566 #define LPC_LPC_ED_ED_SHIFT                      (0U)
72567 /*! ED - Entry Delay
72568  */
72569 #define LPC_LPC_ED_ED(x)                         (((uint32_t)(((uint32_t)(x)) << LPC_LPC_ED_ED_SHIFT)) & LPC_LPC_ED_ED_MASK)
72570 /*! @} */
72571 
72572 /* The count of LPC_LPC_ED */
72573 #define LPC_LPC_ED_COUNT                         (7U)
72574 
72575 /*! @name LPC_XD - LPC Exit Delay Stage N */
72576 /*! @{ */
72577 #define LPC_LPC_XD_XD_MASK                       (0x1FU)
72578 #define LPC_LPC_XD_XD_SHIFT                      (0U)
72579 /*! XD - Exit Delay
72580  */
72581 #define LPC_LPC_XD_XD(x)                         (((uint32_t)(((uint32_t)(x)) << LPC_LPC_XD_XD_SHIFT)) & LPC_LPC_XD_XD_MASK)
72582 /*! @} */
72583 
72584 /* The count of LPC_LPC_XD */
72585 #define LPC_LPC_XD_COUNT                         (6U)
72586 
72587 /*! @name LPC_XD6 - LPC Exit Delay Stage 6 */
72588 /*! @{ */
72589 #define LPC_LPC_XD6_XD_MASK                      (0xFFFFU)
72590 #define LPC_LPC_XD6_XD_SHIFT                     (0U)
72591 /*! XD - Exit Delay
72592  */
72593 #define LPC_LPC_XD6_XD(x)                        (((uint32_t)(((uint32_t)(x)) << LPC_LPC_XD6_XD_SHIFT)) & LPC_LPC_XD6_XD_MASK)
72594 /*! @} */
72595 
72596 
72597 /*!
72598  * @}
72599  */ /* end of group LPC_Register_Masks */
72600 
72601 
72602 /* LPC - Peripheral instance base addresses */
72603 /** Peripheral SCU__LPC base address */
72604 #define SCU__LPC_BASE                            (0x32070000u)
72605 /** Peripheral SCU__LPC base pointer */
72606 #define SCU__LPC                                 ((LPC_Type *)SCU__LPC_BASE)
72607 /** Array initializer of LPC peripheral base addresses */
72608 #define LPC_BASE_ADDRS                           { SCU__LPC_BASE }
72609 /** Array initializer of LPC peripheral base pointers */
72610 #define LPC_BASE_PTRS                            { SCU__LPC }
72611 
72612 /*!
72613  * @}
72614  */ /* end of group LPC_Peripheral_Access_Layer */
72615 
72616 
72617 /* ----------------------------------------------------------------------------
72618    -- LPCG_AVSD Peripheral Access Layer
72619    ---------------------------------------------------------------------------- */
72620 
72621 /*!
72622  * @addtogroup LPCG_AVSD_Peripheral_Access_Layer LPCG_AVSD Peripheral Access Layer
72623  * @{
72624  */
72625 
72626 /** LPCG_AVSD - Register Layout Typedef */
72627 typedef struct {
72628   __IO uint32_t LPCG_AVSD_0;                       /**< na, offset: 0x0 */
72629 } LPCG_AVSD_Type;
72630 
72631 /* ----------------------------------------------------------------------------
72632    -- LPCG_AVSD Register Masks
72633    ---------------------------------------------------------------------------- */
72634 
72635 /*!
72636  * @addtogroup LPCG_AVSD_Register_Masks LPCG_AVSD Register Masks
72637  * @{
72638  */
72639 
72640 /*! @name LPCG_AVSD_0 - na */
72641 /*! @{ */
72642 #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0_MASK (0x1U)
72643 #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0_SHIFT (0U)
72644 /*! LPCG_AVSD_0_reserved_0_0 - reserved
72645  */
72646 #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0_MASK)
72647 #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_MASK (0x2U)
72648 #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_SHIFT (1U)
72649 /*! med_dec_mfd_avsd_clk_gated_SWEN - Software Enable
72650  *  0b0..Disable SW clock regardless of HWEN
72651  *  0b1..Enable SW clock gating
72652  */
72653 #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_MASK)
72654 #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2_MASK (0x4U)
72655 #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2_SHIFT (2U)
72656 /*! LPCG_AVSD_0_reserved_2_2 - reserved
72657  */
72658 #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2_MASK)
72659 #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_MASK (0x8U)
72660 #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_SHIFT (3U)
72661 /*! med_dec_mfd_avsd_clk_gated_STOP - show clock root status, 1 means clock stopped
72662  */
72663 #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_MASK)
72664 #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31_MASK (0xFFFFFFF0U)
72665 #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31_SHIFT (4U)
72666 /*! LPCG_AVSD_0_reserved_4_31 - reserved
72667  */
72668 #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31_MASK)
72669 /*! @} */
72670 
72671 
72672 /*!
72673  * @}
72674  */ /* end of group LPCG_AVSD_Register_Masks */
72675 
72676 
72677 /* LPCG_AVSD - Peripheral instance base addresses */
72678 /** Peripheral VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED base address */
72679 #define VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED_BASE (0x2D0B0000u)
72680 /** Peripheral VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED base pointer */
72681 #define VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED   ((LPCG_AVSD_Type *)VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED_BASE)
72682 /** Array initializer of LPCG_AVSD peripheral base addresses */
72683 #define LPCG_AVSD_BASE_ADDRS                     { VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED_BASE }
72684 /** Array initializer of LPCG_AVSD peripheral base pointers */
72685 #define LPCG_AVSD_BASE_PTRS                      { VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED }
72686 
72687 /*!
72688  * @}
72689  */ /* end of group LPCG_AVSD_Peripheral_Access_Layer */
72690 
72691 
72692 /* ----------------------------------------------------------------------------
72693    -- LPCG_CI_PI_LPCG Peripheral Access Layer
72694    ---------------------------------------------------------------------------- */
72695 
72696 /*!
72697  * @addtogroup LPCG_CI_PI_LPCG_Peripheral_Access_Layer LPCG_CI_PI_LPCG Peripheral Access Layer
72698  * @{
72699  */
72700 
72701 /** LPCG_CI_PI_LPCG - Register Layout Typedef */
72702 typedef struct {
72703   __IO uint32_t LPCG_CI_PI_LPCG_0;                 /**< na, offset: 0x0 */
72704   __IO uint32_t LPCG_CI_PI_LPCG_4;                 /**< na, offset: 0x4 */
72705   __IO uint32_t LPCG_CI_PI_LPCG_8;                 /**< na, offset: 0x8 */
72706   __IO uint32_t LPCG_CI_PI_LPCG_12;                /**< na, offset: 0xC */
72707   __IO uint32_t LPCG_CI_PI_LPCG_16;                /**< na, offset: 0x10 */
72708        uint8_t RESERVED_0[4];
72709   __IO uint32_t LPCG_CI_PI_LPCG_24;                /**< na, offset: 0x18 */
72710   __IO uint32_t LPCG_CI_PI_LPCG_28;                /**< na, offset: 0x1C */
72711 } LPCG_CI_PI_LPCG_Type;
72712 
72713 /* ----------------------------------------------------------------------------
72714    -- LPCG_CI_PI_LPCG Register Masks
72715    ---------------------------------------------------------------------------- */
72716 
72717 /*!
72718  * @addtogroup LPCG_CI_PI_LPCG_Register_Masks LPCG_CI_PI_LPCG Register Masks
72719  * @{
72720  */
72721 
72722 /*! @name LPCG_CI_PI_LPCG_0 - na */
72723 /*! @{ */
72724 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16_MASK (0x1FFFFU)
72725 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16_SHIFT (0U)
72726 /*! LPCG_ci_pi_lpcg_0_reserved_0_16 - reserved
72727  */
72728 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16_MASK)
72729 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN_MASK (0x20000U)
72730 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN_SHIFT (17U)
72731 /*! lis_ipg_clk_SWEN - Software Enable
72732  *  0b0..Disable SW clock regardless of HWEN
72733  *  0b1..Enable SW clock gating
72734  */
72735 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN_MASK)
72736 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18_MASK (0x40000U)
72737 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18_SHIFT (18U)
72738 /*! LPCG_ci_pi_lpcg_0_reserved_18_18 - reserved
72739  */
72740 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18_MASK)
72741 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP_MASK (0x80000U)
72742 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP_SHIFT (19U)
72743 /*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped
72744  */
72745 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP_MASK)
72746 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31_MASK (0xFFF00000U)
72747 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31_SHIFT (20U)
72748 /*! LPCG_ci_pi_lpcg_0_reserved_20_31 - reserved
72749  */
72750 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31_MASK)
72751 /*! @} */
72752 
72753 /*! @name LPCG_CI_PI_LPCG_4 - na */
72754 /*! @{ */
72755 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15_MASK (0xFFFFU)
72756 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15_SHIFT (0U)
72757 /*! LPCG_ci_pi_lpcg_4_reserved_0_15 - reserved
72758  */
72759 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15_MASK)
72760 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN_MASK (0x10000U)
72761 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN_SHIFT (16U)
72762 /*! ci_pi_regs_ipg_gatedclk_HWEN - Hardware Enable
72763  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
72764  *  0b1..Enable HW automatic gating
72765  */
72766 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN_MASK)
72767 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN_MASK (0x20000U)
72768 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN_SHIFT (17U)
72769 /*! ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN - Software Enable
72770  *  0b0..Disable SW clock regardless of HWEN
72771  *  0b1..Enable SW clock gating
72772  */
72773 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN_MASK)
72774 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18_MASK (0x40000U)
72775 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18_SHIFT (18U)
72776 /*! LPCG_ci_pi_lpcg_4_reserved_18_18 - reserved
72777  */
72778 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18_MASK)
72779 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP_MASK (0x80000U)
72780 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP_SHIFT (19U)
72781 /*! ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP - show clock root status, 1 means clock stopped
72782  */
72783 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP_MASK)
72784 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN_MASK (0x100000U)
72785 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN_SHIFT (20U)
72786 /*! ipsync_ci_pi_regs_ipg_master_clk_HWEN - Hardware Enable
72787  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
72788  *  0b1..Enable HW automatic gating
72789  */
72790 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN_MASK)
72791 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN_MASK (0x200000U)
72792 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN_SHIFT (21U)
72793 /*! ipsync_ci_pi_regs_ipg_master_clk_SWEN - Software Enable
72794  *  0b0..Disable SW clock regardless of HWEN
72795  *  0b1..Enable SW clock gating
72796  */
72797 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN_MASK)
72798 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22_MASK (0x400000U)
72799 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22_SHIFT (22U)
72800 /*! LPCG_ci_pi_lpcg_4_reserved_22_22 - reserved
72801  */
72802 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22_MASK)
72803 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP_MASK (0x800000U)
72804 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP_SHIFT (23U)
72805 /*! ipsync_ci_pi_regs_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
72806  */
72807 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP_MASK)
72808 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24_MASK (0x1000000U)
72809 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24_SHIFT (24U)
72810 /*! LPCG_ci_pi_lpcg_4_reserved_24_24 - reserved
72811  */
72812 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24_MASK)
72813 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN_MASK (0x2000000U)
72814 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN_SHIFT (25U)
72815 /*! ipsync_ci_pi_regs_ipg_slave_clk_SWEN - Software Enable
72816  *  0b0..Disable SW clock regardless of HWEN
72817  *  0b1..Enable SW clock gating
72818  */
72819 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN_MASK)
72820 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26_MASK (0x4000000U)
72821 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26_SHIFT (26U)
72822 /*! LPCG_ci_pi_lpcg_4_reserved_26_26 - reserved
72823  */
72824 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26_MASK)
72825 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP_MASK (0x8000000U)
72826 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP_SHIFT (27U)
72827 /*! ipsync_ci_pi_regs_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
72828  */
72829 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP_MASK)
72830 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31_MASK (0xF0000000U)
72831 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31_SHIFT (28U)
72832 /*! LPCG_ci_pi_lpcg_4_reserved_28_31 - reserved
72833  */
72834 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31_MASK)
72835 /*! @} */
72836 
72837 /*! @name LPCG_CI_PI_LPCG_8 - na */
72838 /*! @{ */
72839 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15_MASK (0xFFFFU)
72840 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15_SHIFT (0U)
72841 /*! LPCG_ci_pi_lpcg_8_reserved_0_15 - reserved
72842  */
72843 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15_MASK)
72844 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK (0x10000U)
72845 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT (16U)
72846 /*! gpio_ipg_clk_s_HWEN - Hardware Enable
72847  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
72848  *  0b1..Enable HW automatic gating
72849  */
72850 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK)
72851 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK (0x20000U)
72852 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT (17U)
72853 /*! gpio_ipg_clk_s_SWEN - Software Enable
72854  *  0b0..Disable SW clock regardless of HWEN
72855  *  0b1..Enable SW clock gating
72856  */
72857 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK)
72858 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18_MASK (0x40000U)
72859 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18_SHIFT (18U)
72860 /*! LPCG_ci_pi_lpcg_8_reserved_18_18 - reserved
72861  */
72862 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18_MASK)
72863 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP_MASK (0x80000U)
72864 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT (19U)
72865 /*! gpio_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
72866  */
72867 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP_MASK)
72868 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
72869 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31_SHIFT (20U)
72870 /*! LPCG_ci_pi_lpcg_8_reserved_20_31 - reserved
72871  */
72872 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31_MASK)
72873 /*! @} */
72874 
72875 /*! @name LPCG_CI_PI_LPCG_12 - na */
72876 /*! @{ */
72877 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0_MASK (0x1U)
72878 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0_SHIFT (0U)
72879 /*! LPCG_ci_pi_lpcg_12_reserved_0_0 - reserved
72880  */
72881 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0_MASK)
72882 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U)
72883 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U)
72884 /*! pwm_ipg_clk_highfreq_SWEN - Software Enable
72885  *  0b0..Disable SW clock regardless of HWEN
72886  *  0b1..Enable SW clock gating
72887  */
72888 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK)
72889 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2_MASK (0x4U)
72890 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2_SHIFT (2U)
72891 /*! LPCG_ci_pi_lpcg_12_reserved_2_2 - reserved
72892  */
72893 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2_MASK)
72894 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK (0x8U)
72895 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT (3U)
72896 /*! pwm_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
72897  */
72898 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK)
72899 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4_MASK (0x10U)
72900 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4_SHIFT (4U)
72901 /*! LPCG_ci_pi_lpcg_12_reserved_4_4 - reserved
72902  */
72903 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4_MASK)
72904 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK (0x20U)
72905 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT (5U)
72906 /*! ccm_ckil_sync_wrapper_clk_in_SWEN - Software Enable
72907  *  0b0..Disable SW clock regardless of HWEN
72908  *  0b1..Enable SW clock gating
72909  */
72910 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK)
72911 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6_MASK (0x40U)
72912 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6_SHIFT (6U)
72913 /*! LPCG_ci_pi_lpcg_12_reserved_6_6 - reserved
72914  */
72915 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6_MASK)
72916 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK (0x80U)
72917 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT (7U)
72918 /*! ccm_ckil_sync_wrapper_clk_in_STOP - show clock root status, 1 means clock stopped
72919  */
72920 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK)
72921 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15_MASK (0xFF00U)
72922 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15_SHIFT (8U)
72923 /*! LPCG_ci_pi_lpcg_12_reserved_8_15 - reserved
72924  */
72925 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15_MASK)
72926 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK (0x10000U)
72927 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT (16U)
72928 /*! pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN - Hardware Enable
72929  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
72930  *  0b1..Enable HW automatic gating
72931  */
72932 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK)
72933 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U)
72934 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U)
72935 /*! pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN - Software Enable
72936  *  0b0..Disable SW clock regardless of HWEN
72937  *  0b1..Enable SW clock gating
72938  */
72939 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK)
72940 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18_MASK (0x40000U)
72941 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18_SHIFT (18U)
72942 /*! LPCG_ci_pi_lpcg_12_reserved_18_18 - reserved
72943  */
72944 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18_MASK)
72945 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U)
72946 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U)
72947 /*! pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
72948  */
72949 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK)
72950 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK (0x100000U)
72951 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT (20U)
72952 /*! ipsync_pwm_ipg_master_clk_HWEN - Hardware Enable
72953  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
72954  *  0b1..Enable HW automatic gating
72955  */
72956 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK)
72957 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK (0x200000U)
72958 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT (21U)
72959 /*! ipsync_pwm_ipg_master_clk_SWEN - Software Enable
72960  *  0b0..Disable SW clock regardless of HWEN
72961  *  0b1..Enable SW clock gating
72962  */
72963 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK)
72964 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22_MASK (0x400000U)
72965 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22_SHIFT (22U)
72966 /*! LPCG_ci_pi_lpcg_12_reserved_22_22 - reserved
72967  */
72968 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22_MASK)
72969 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK (0x800000U)
72970 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT (23U)
72971 /*! ipsync_pwm_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
72972  */
72973 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK)
72974 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24_MASK (0x1000000U)
72975 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24_SHIFT (24U)
72976 /*! LPCG_ci_pi_lpcg_12_reserved_24_24 - reserved
72977  */
72978 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24_MASK)
72979 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK (0x2000000U)
72980 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT (25U)
72981 /*! ipsync_pwm_ipg_slave_clk_SWEN - Software Enable
72982  *  0b0..Disable SW clock regardless of HWEN
72983  *  0b1..Enable SW clock gating
72984  */
72985 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK)
72986 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26_MASK (0x4000000U)
72987 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26_SHIFT (26U)
72988 /*! LPCG_ci_pi_lpcg_12_reserved_26_26 - reserved
72989  */
72990 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26_MASK)
72991 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK (0x8000000U)
72992 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT (27U)
72993 /*! ipsync_pwm_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
72994  */
72995 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK)
72996 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31_MASK (0xF0000000U)
72997 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31_SHIFT (28U)
72998 /*! LPCG_ci_pi_lpcg_12_reserved_28_31 - reserved
72999  */
73000 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31_MASK)
73001 /*! @} */
73002 
73003 /*! @name LPCG_CI_PI_LPCG_16 - na */
73004 /*! @{ */
73005 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U)
73006 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U)
73007 /*! lpi2c0_lpi2c_div_clk_HWEN - Hardware Enable
73008  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73009  *  0b1..Enable HW automatic gating
73010  */
73011 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK)
73012 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U)
73013 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U)
73014 /*! lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN - Software Enable
73015  *  0b0..Disable SW clock regardless of HWEN
73016  *  0b1..Enable SW clock gating
73017  */
73018 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK)
73019 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2_MASK (0x4U)
73020 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2_SHIFT (2U)
73021 /*! LPCG_ci_pi_lpcg_16_reserved_2_2 - reserved
73022  */
73023 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2_MASK)
73024 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U)
73025 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U)
73026 /*! lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
73027  */
73028 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK)
73029 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15_MASK (0xFFF0U)
73030 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15_SHIFT (4U)
73031 /*! LPCG_ci_pi_lpcg_16_reserved_4_15 - reserved
73032  */
73033 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15_MASK)
73034 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK (0x10000U)
73035 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT (16U)
73036 /*! lpi2c0_ipg_clk_s_HWEN - Hardware Enable
73037  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73038  *  0b1..Enable HW automatic gating
73039  */
73040 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK)
73041 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK (0x20000U)
73042 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT (17U)
73043 /*! lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN - Software Enable
73044  *  0b0..Disable SW clock regardless of HWEN
73045  *  0b1..Enable SW clock gating
73046  */
73047 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK)
73048 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18_MASK (0x40000U)
73049 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18_SHIFT (18U)
73050 /*! LPCG_ci_pi_lpcg_16_reserved_18_18 - reserved
73051  */
73052 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18_MASK)
73053 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK (0x80000U)
73054 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT (19U)
73055 /*! lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
73056  */
73057 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK)
73058 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
73059 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31_SHIFT (20U)
73060 /*! LPCG_ci_pi_lpcg_16_reserved_20_31 - reserved
73061  */
73062 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31_MASK)
73063 /*! @} */
73064 
73065 /*! @name LPCG_CI_PI_LPCG_24 - na */
73066 /*! @{ */
73067 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0_MASK (0x1U)
73068 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0_SHIFT (0U)
73069 /*! LPCG_ci_pi_lpcg_24_reserved_0_0 - reserved
73070  */
73071 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0_MASK)
73072 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN_MASK (0x2U)
73073 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN_SHIFT (1U)
73074 /*! csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN - Software Enable
73075  *  0b0..Disable SW clock regardless of HWEN
73076  *  0b1..Enable SW clock gating
73077  */
73078 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN_MASK)
73079 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2_MASK (0x4U)
73080 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2_SHIFT (2U)
73081 /*! LPCG_ci_pi_lpcg_24_reserved_2_2 - reserved
73082  */
73083 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2_MASK)
73084 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP_MASK (0x8U)
73085 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP_SHIFT (3U)
73086 /*! csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP - show clock root status, 1 means clock stopped
73087  */
73088 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP_MASK)
73089 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U)
73090 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31_SHIFT (4U)
73091 /*! LPCG_ci_pi_lpcg_24_reserved_4_31 - reserved
73092  */
73093 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31_MASK)
73094 /*! @} */
73095 
73096 /*! @name LPCG_CI_PI_LPCG_28 - na */
73097 /*! @{ */
73098 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0_MASK (0x1U)
73099 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0_SHIFT (0U)
73100 /*! LPCG_ci_pi_lpcg_28_reserved_0_0 - reserved
73101  */
73102 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0_MASK)
73103 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN_MASK (0x2U)
73104 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN_SHIFT (1U)
73105 /*! MCLK_SWEN - Software Enable
73106  *  0b0..Disable SW clock regardless of HWEN
73107  *  0b1..Enable SW clock gating
73108  */
73109 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN_MASK)
73110 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2_MASK (0x4U)
73111 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2_SHIFT (2U)
73112 /*! LPCG_ci_pi_lpcg_28_reserved_2_2 - reserved
73113  */
73114 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2_MASK)
73115 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP_MASK (0x8U)
73116 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP_SHIFT (3U)
73117 /*! MCLK_STOP - show clock root status, 1 means clock stopped
73118  */
73119 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP_MASK)
73120 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U)
73121 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31_SHIFT (4U)
73122 /*! LPCG_ci_pi_lpcg_28_reserved_4_31 - reserved
73123  */
73124 #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31_MASK)
73125 /*! @} */
73126 
73127 
73128 /*!
73129  * @}
73130  */ /* end of group LPCG_CI_PI_LPCG_Register_Masks */
73131 
73132 
73133 /* LPCG_CI_PI_LPCG - Peripheral instance base addresses */
73134 /** Peripheral CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK base address */
73135 #define CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK_BASE   (0x58263000u)
73136 /** Peripheral CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK base pointer */
73137 #define CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK        ((LPCG_CI_PI_LPCG_Type *)CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK_BASE)
73138 /** Array initializer of LPCG_CI_PI_LPCG peripheral base addresses */
73139 #define LPCG_CI_PI_LPCG_BASE_ADDRS               { CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK_BASE }
73140 /** Array initializer of LPCG_CI_PI_LPCG peripheral base pointers */
73141 #define LPCG_CI_PI_LPCG_BASE_PTRS                { CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK }
73142 
73143 /*!
73144  * @}
73145  */ /* end of group LPCG_CI_PI_LPCG_Peripheral_Access_Layer */
73146 
73147 
73148 /* ----------------------------------------------------------------------------
73149    -- LPCG_DI_MIPI_DSI_LVDS Peripheral Access Layer
73150    ---------------------------------------------------------------------------- */
73151 
73152 /*!
73153  * @addtogroup LPCG_DI_MIPI_DSI_LVDS_Peripheral_Access_Layer LPCG_DI_MIPI_DSI_LVDS Peripheral Access Layer
73154  * @{
73155  */
73156 
73157 /** LPCG_DI_MIPI_DSI_LVDS - Register Layout Typedef */
73158 typedef struct {
73159   __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_0;      /**< na, offset: 0x0 */
73160   __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_4;      /**< na, offset: 0x4 */
73161   __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_8;      /**< na, offset: 0x8 */
73162   __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_12;     /**< na, offset: 0xC */
73163   __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_16;     /**< na, offset: 0x10 */
73164   __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_20;     /**< na, offset: 0x14 */
73165   __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_24;     /**< na, offset: 0x18 */
73166 } LPCG_DI_MIPI_DSI_LVDS_Type;
73167 
73168 /* ----------------------------------------------------------------------------
73169    -- LPCG_DI_MIPI_DSI_LVDS Register Masks
73170    ---------------------------------------------------------------------------- */
73171 
73172 /*!
73173  * @addtogroup LPCG_DI_MIPI_DSI_LVDS_Register_Masks LPCG_DI_MIPI_DSI_LVDS Register Masks
73174  * @{
73175  */
73176 
73177 /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_0 - na */
73178 /*! @{ */
73179 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16_MASK (0x1FFFFU)
73180 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16_SHIFT (0U)
73181 /*! LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16 - reserved
73182  */
73183 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16_MASK)
73184 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN_MASK (0x20000U)
73185 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN_SHIFT (17U)
73186 /*! lis_ipg_clk_SWEN - Software Enable
73187  *  0b0..Disable SW clock regardless of HWEN
73188  *  0b1..Enable SW clock gating
73189  */
73190 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN_MASK)
73191 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18_MASK (0x40000U)
73192 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18_SHIFT (18U)
73193 /*! LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18 - reserved
73194  */
73195 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18_MASK)
73196 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP_MASK (0x80000U)
73197 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP_SHIFT (19U)
73198 /*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped
73199  */
73200 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP_MASK)
73201 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31_MASK (0xFFF00000U)
73202 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31_SHIFT (20U)
73203 /*! LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31 - reserved
73204  */
73205 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31_MASK)
73206 /*! @} */
73207 
73208 /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_4 - na */
73209 /*! @{ */
73210 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16_MASK (0x1FFFFU)
73211 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16_SHIFT (0U)
73212 /*! LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16 - reserved
73213  */
73214 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16_MASK)
73215 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN_MASK (0x20000U)
73216 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN_SHIFT (17U)
73217 /*! di_mipi_dsi_lvds_regs_ipg_clk_SWEN - Software Enable
73218  *  0b0..Disable SW clock regardless of HWEN
73219  *  0b1..Enable SW clock gating
73220  */
73221 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN_MASK)
73222 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18_MASK (0x40000U)
73223 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18_SHIFT (18U)
73224 /*! LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18 - reserved
73225  */
73226 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18_MASK)
73227 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP_MASK (0x80000U)
73228 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP_SHIFT (19U)
73229 /*! di_mipi_dsi_lvds_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped
73230  */
73231 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP_MASK)
73232 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
73233 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31_SHIFT (20U)
73234 /*! LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31 - reserved
73235  */
73236 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31_MASK)
73237 /*! @} */
73238 
73239 /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_8 - na */
73240 /*! @{ */
73241 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15_MASK (0xFFFFU)
73242 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15_SHIFT (0U)
73243 /*! LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15 - reserved
73244  */
73245 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15_MASK)
73246 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_MASK (0x10000U)
73247 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT (16U)
73248 /*! gpio_ipg_clk_s_HWEN - Hardware Enable
73249  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73250  *  0b1..Enable HW automatic gating
73251  */
73252 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_MASK)
73253 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_MASK (0x20000U)
73254 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT (17U)
73255 /*! gpio_ipg_clk_s_SWEN - Software Enable
73256  *  0b0..Disable SW clock regardless of HWEN
73257  *  0b1..Enable SW clock gating
73258  */
73259 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_MASK)
73260 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18_MASK (0x40000U)
73261 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18_SHIFT (18U)
73262 /*! LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18 - reserved
73263  */
73264 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18_MASK)
73265 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_MASK (0x80000U)
73266 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT (19U)
73267 /*! gpio_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
73268  */
73269 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_MASK)
73270 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
73271 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31_SHIFT (20U)
73272 /*! LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31 - reserved
73273  */
73274 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31_MASK)
73275 /*! @} */
73276 
73277 /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_12 - na */
73278 /*! @{ */
73279 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0_MASK (0x1U)
73280 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0_SHIFT (0U)
73281 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0 - reserved
73282  */
73283 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0_MASK)
73284 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U)
73285 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U)
73286 /*! pwm_ipg_clk_highfreq_SWEN - Software Enable
73287  *  0b0..Disable SW clock regardless of HWEN
73288  *  0b1..Enable SW clock gating
73289  */
73290 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK)
73291 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2_MASK (0x4U)
73292 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2_SHIFT (2U)
73293 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2 - reserved
73294  */
73295 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2_MASK)
73296 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK (0x8U)
73297 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT (3U)
73298 /*! pwm_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
73299  */
73300 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK)
73301 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4_MASK (0x10U)
73302 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4_SHIFT (4U)
73303 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4 - reserved
73304  */
73305 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4_MASK)
73306 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK (0x20U)
73307 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT (5U)
73308 /*! ccm_ckil_sync_wrapper_clk_in_SWEN - Software Enable
73309  *  0b0..Disable SW clock regardless of HWEN
73310  *  0b1..Enable SW clock gating
73311  */
73312 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK)
73313 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6_MASK (0x40U)
73314 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6_SHIFT (6U)
73315 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6 - reserved
73316  */
73317 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6_MASK)
73318 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK (0x80U)
73319 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT (7U)
73320 /*! ccm_ckil_sync_wrapper_clk_in_STOP - show clock root status, 1 means clock stopped
73321  */
73322 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK)
73323 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15_MASK (0xFF00U)
73324 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15_SHIFT (8U)
73325 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15 - reserved
73326  */
73327 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15_MASK)
73328 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK (0x10000U)
73329 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT (16U)
73330 /*! pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN - Hardware Enable
73331  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73332  *  0b1..Enable HW automatic gating
73333  */
73334 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK)
73335 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U)
73336 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U)
73337 /*! pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN - Software Enable
73338  *  0b0..Disable SW clock regardless of HWEN
73339  *  0b1..Enable SW clock gating
73340  */
73341 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK)
73342 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18_MASK (0x40000U)
73343 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18_SHIFT (18U)
73344 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18 - reserved
73345  */
73346 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18_MASK)
73347 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U)
73348 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U)
73349 /*! pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
73350  */
73351 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK)
73352 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK (0x100000U)
73353 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT (20U)
73354 /*! ipsync_pwm_ipg_master_clk_HWEN - Hardware Enable
73355  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73356  *  0b1..Enable HW automatic gating
73357  */
73358 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK)
73359 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK (0x200000U)
73360 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT (21U)
73361 /*! ipsync_pwm_ipg_master_clk_SWEN - Software Enable
73362  *  0b0..Disable SW clock regardless of HWEN
73363  *  0b1..Enable SW clock gating
73364  */
73365 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK)
73366 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22_MASK (0x400000U)
73367 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22_SHIFT (22U)
73368 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22 - reserved
73369  */
73370 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22_MASK)
73371 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK (0x800000U)
73372 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT (23U)
73373 /*! ipsync_pwm_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
73374  */
73375 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK)
73376 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24_MASK (0x1000000U)
73377 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24_SHIFT (24U)
73378 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24 - reserved
73379  */
73380 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24_MASK)
73381 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK (0x2000000U)
73382 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT (25U)
73383 /*! ipsync_pwm_ipg_slave_clk_SWEN - Software Enable
73384  *  0b0..Disable SW clock regardless of HWEN
73385  *  0b1..Enable SW clock gating
73386  */
73387 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK)
73388 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26_MASK (0x4000000U)
73389 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26_SHIFT (26U)
73390 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26 - reserved
73391  */
73392 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26_MASK)
73393 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK (0x8000000U)
73394 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT (27U)
73395 /*! ipsync_pwm_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
73396  */
73397 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK)
73398 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31_MASK (0xF0000000U)
73399 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31_SHIFT (28U)
73400 /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31 - reserved
73401  */
73402 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31_MASK)
73403 /*! @} */
73404 
73405 /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_16 - na */
73406 /*! @{ */
73407 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U)
73408 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U)
73409 /*! lpi2c0_lpi2c_div_clk_HWEN - Hardware Enable
73410  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73411  *  0b1..Enable HW automatic gating
73412  */
73413 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK)
73414 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U)
73415 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U)
73416 /*! lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN - Software Enable
73417  *  0b0..Disable SW clock regardless of HWEN
73418  *  0b1..Enable SW clock gating
73419  */
73420 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK)
73421 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2_MASK (0x4U)
73422 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2_SHIFT (2U)
73423 /*! LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2 - reserved
73424  */
73425 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2_MASK)
73426 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U)
73427 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U)
73428 /*! lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
73429  */
73430 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK)
73431 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15_MASK (0xFFF0U)
73432 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15_SHIFT (4U)
73433 /*! LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15 - reserved
73434  */
73435 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15_MASK)
73436 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK (0x10000U)
73437 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT (16U)
73438 /*! lpi2c0_ipg_clk_s_HWEN - Hardware Enable
73439  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73440  *  0b1..Enable HW automatic gating
73441  */
73442 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK)
73443 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK (0x20000U)
73444 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT (17U)
73445 /*! lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN - Software Enable
73446  *  0b0..Disable SW clock regardless of HWEN
73447  *  0b1..Enable SW clock gating
73448  */
73449 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK)
73450 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18_MASK (0x40000U)
73451 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18_SHIFT (18U)
73452 /*! LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18 - reserved
73453  */
73454 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18_MASK)
73455 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK (0x80000U)
73456 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT (19U)
73457 /*! lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
73458  */
73459 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK)
73460 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
73461 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31_SHIFT (20U)
73462 /*! LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31 - reserved
73463  */
73464 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31_MASK)
73465 /*! @} */
73466 
73467 /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_20 - na */
73468 /*! @{ */
73469 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
73470 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
73471 /*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable
73472  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73473  *  0b1..Enable HW automatic gating
73474  */
73475 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_MASK)
73476 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
73477 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
73478 /*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable
73479  *  0b0..Disable SW clock regardless of HWEN
73480  *  0b1..Enable SW clock gating
73481  */
73482 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
73483 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2_MASK (0x4U)
73484 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2_SHIFT (2U)
73485 /*! LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2 - reserved
73486  */
73487 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2_MASK)
73488 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
73489 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
73490 /*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
73491  */
73492 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
73493 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15_MASK (0xFFF0U)
73494 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15_SHIFT (4U)
73495 /*! LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15 - reserved
73496  */
73497 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15_MASK)
73498 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_MASK (0x10000U)
73499 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_SHIFT (16U)
73500 /*! lpi2c1_ipg_clk_s_HWEN - Hardware Enable
73501  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73502  *  0b1..Enable HW automatic gating
73503  */
73504 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_MASK)
73505 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK (0x20000U)
73506 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT (17U)
73507 /*! lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN - Software Enable
73508  *  0b0..Disable SW clock regardless of HWEN
73509  *  0b1..Enable SW clock gating
73510  */
73511 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK)
73512 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18_MASK (0x40000U)
73513 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18_SHIFT (18U)
73514 /*! LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18 - reserved
73515  */
73516 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18_MASK)
73517 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK (0x80000U)
73518 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT (19U)
73519 /*! lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
73520  */
73521 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK)
73522 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31_MASK (0xFFF00000U)
73523 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31_SHIFT (20U)
73524 /*! LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31 - reserved
73525  */
73526 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31_MASK)
73527 /*! @} */
73528 
73529 /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_24 - na */
73530 /*! @{ */
73531 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0_MASK (0x1U)
73532 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0_SHIFT (0U)
73533 /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0 - reserved
73534  */
73535 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0_MASK)
73536 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN_MASK (0x2U)
73537 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN_SHIFT (1U)
73538 /*! mipi_dsi_ctrl_TxClkEsc_SWEN - Software Enable
73539  *  0b0..Disable SW clock regardless of HWEN
73540  *  0b1..Enable SW clock gating
73541  */
73542 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN_MASK)
73543 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2_MASK (0x4U)
73544 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2_SHIFT (2U)
73545 /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2 - reserved
73546  */
73547 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2_MASK)
73548 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP_MASK (0x8U)
73549 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP_SHIFT (3U)
73550 /*! mipi_dsi_ctrl_TxClkEsc_STOP - show clock root status, 1 means clock stopped
73551  */
73552 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP_MASK)
73553 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4_MASK (0x10U)
73554 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4_SHIFT (4U)
73555 /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4 - reserved
73556  */
73557 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4_MASK)
73558 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN_MASK (0x20U)
73559 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN_SHIFT (5U)
73560 /*! mipi_dsi_ctrl_RxClkEsc_SWEN - Software Enable
73561  *  0b0..Disable SW clock regardless of HWEN
73562  *  0b1..Enable SW clock gating
73563  */
73564 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN_MASK)
73565 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6_MASK (0x40U)
73566 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6_SHIFT (6U)
73567 /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6 - reserved
73568  */
73569 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6_MASK)
73570 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP_MASK (0x80U)
73571 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP_SHIFT (7U)
73572 /*! mipi_dsi_ctrl_RxClkEsc_STOP - show clock root status, 1 means clock stopped
73573  */
73574 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP_MASK)
73575 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8_MASK (0x100U)
73576 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8_SHIFT (8U)
73577 /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8 - reserved
73578  */
73579 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8_MASK)
73580 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN_MASK (0x200U)
73581 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN_SHIFT (9U)
73582 /*! mipi_clkref_SWEN - Software Enable
73583  *  0b0..Disable SW clock regardless of HWEN
73584  *  0b1..Enable SW clock gating
73585  */
73586 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN_MASK)
73587 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10_MASK (0x400U)
73588 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10_SHIFT (10U)
73589 /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10 - reserved
73590  */
73591 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10_MASK)
73592 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP_MASK (0x800U)
73593 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP_SHIFT (11U)
73594 /*! mipi_clkref_STOP - show clock root status, 1 means clock stopped
73595  */
73596 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP_MASK)
73597 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16_MASK (0x1F000U)
73598 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16_SHIFT (12U)
73599 /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16 - reserved
73600  */
73601 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16_MASK)
73602 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN_MASK (0x20000U)
73603 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN_SHIFT (17U)
73604 /*! mipi_dsi_ctrl_pclk_SWEN - Software Enable
73605  *  0b0..Disable SW clock regardless of HWEN
73606  *  0b1..Enable SW clock gating
73607  */
73608 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN_MASK)
73609 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18_MASK (0x40000U)
73610 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18_SHIFT (18U)
73611 /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18 - reserved
73612  */
73613 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18_MASK)
73614 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP_MASK (0x80000U)
73615 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP_SHIFT (19U)
73616 /*! mipi_dsi_ctrl_pclk_STOP - show clock root status, 1 means clock stopped
73617  */
73618 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP_MASK)
73619 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31_MASK (0xFFF00000U)
73620 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31_SHIFT (20U)
73621 /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31 - reserved
73622  */
73623 #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31_MASK)
73624 /*! @} */
73625 
73626 
73627 /*!
73628  * @}
73629  */ /* end of group LPCG_DI_MIPI_DSI_LVDS_Register_Masks */
73630 
73631 
73632 /* LPCG_DI_MIPI_DSI_LVDS - Peripheral instance base addresses */
73633 /** Peripheral DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK base address */
73634 #define DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK_BASE (0x56223000u)
73635 /** Peripheral DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK base pointer */
73636 #define DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK     ((LPCG_DI_MIPI_DSI_LVDS_Type *)DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK_BASE)
73637 /** Peripheral DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK base address */
73638 #define DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK_BASE (0x56243000u)
73639 /** Peripheral DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK base pointer */
73640 #define DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK     ((LPCG_DI_MIPI_DSI_LVDS_Type *)DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK_BASE)
73641 /** Array initializer of LPCG_DI_MIPI_DSI_LVDS peripheral base addresses */
73642 #define LPCG_DI_MIPI_DSI_LVDS_BASE_ADDRS         { DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK_BASE, DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK_BASE }
73643 /** Array initializer of LPCG_DI_MIPI_DSI_LVDS peripheral base pointers */
73644 #define LPCG_DI_MIPI_DSI_LVDS_BASE_PTRS          { DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK, DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK }
73645 
73646 /*!
73647  * @}
73648  */ /* end of group LPCG_DI_MIPI_DSI_LVDS_Peripheral_Access_Layer */
73649 
73650 
73651 /* ----------------------------------------------------------------------------
73652    -- LPCG_ENC Peripheral Access Layer
73653    ---------------------------------------------------------------------------- */
73654 
73655 /*!
73656  * @addtogroup LPCG_ENC_Peripheral_Access_Layer LPCG_ENC Peripheral Access Layer
73657  * @{
73658  */
73659 
73660 /** LPCG_ENC - Register Layout Typedef */
73661 typedef struct {
73662   __IO uint32_t LPCG_ENC_0;                        /**< na, offset: 0x0 */
73663 } LPCG_ENC_Type;
73664 
73665 /* ----------------------------------------------------------------------------
73666    -- LPCG_ENC Register Masks
73667    ---------------------------------------------------------------------------- */
73668 
73669 /*!
73670  * @addtogroup LPCG_ENC_Register_Masks LPCG_ENC Register Masks
73671  * @{
73672  */
73673 
73674 /*! @name LPCG_ENC_0 - na */
73675 /*! @{ */
73676 #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0_MASK (0x1U)
73677 #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0_SHIFT (0U)
73678 /*! LPCG_ENC_0_reserved_0_0 - reserved
73679  */
73680 #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0_SHIFT)) & LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0_MASK)
73681 #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN_MASK (0x2U)
73682 #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN_SHIFT (1U)
73683 /*! avehd_xbus_top_wrapper_sys_clk_SWEN - Software Enable
73684  *  0b0..Disable SW clock regardless of HWEN
73685  *  0b1..Enable SW clock gating
73686  */
73687 #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN_SHIFT)) & LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN_MASK)
73688 #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2_MASK (0x4U)
73689 #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2_SHIFT (2U)
73690 /*! LPCG_ENC_0_reserved_2_2 - reserved
73691  */
73692 #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2_SHIFT)) & LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2_MASK)
73693 #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP_MASK (0x8U)
73694 #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP_SHIFT (3U)
73695 /*! avehd_xbus_top_wrapper_sys_clk_STOP - show clock root status, 1 means clock stopped
73696  */
73697 #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP_SHIFT)) & LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP_MASK)
73698 #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31_MASK (0xFFFFFFF0U)
73699 #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31_SHIFT (4U)
73700 /*! LPCG_ENC_0_reserved_4_31 - reserved
73701  */
73702 #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31_SHIFT)) & LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31_MASK)
73703 /*! @} */
73704 
73705 
73706 /*!
73707  * @}
73708  */ /* end of group LPCG_ENC_Register_Masks */
73709 
73710 
73711 /* LPCG_ENC - Peripheral instance base addresses */
73712 /** Peripheral VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK base address */
73713 #define VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK_BASE (0x2D060000u)
73714 /** Peripheral VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK base pointer */
73715 #define VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK ((LPCG_ENC_Type *)VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK_BASE)
73716 /** Array initializer of LPCG_ENC peripheral base addresses */
73717 #define LPCG_ENC_BASE_ADDRS                      { VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK_BASE }
73718 /** Array initializer of LPCG_ENC peripheral base pointers */
73719 #define LPCG_ENC_BASE_PTRS                       { VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK }
73720 
73721 /*!
73722  * @}
73723  */ /* end of group LPCG_ENC_Peripheral_Access_Layer */
73724 
73725 
73726 /* ----------------------------------------------------------------------------
73727    -- LPCG_GPIO_CLK Peripheral Access Layer
73728    ---------------------------------------------------------------------------- */
73729 
73730 /*!
73731  * @addtogroup LPCG_GPIO_CLK_Peripheral_Access_Layer LPCG_GPIO_CLK Peripheral Access Layer
73732  * @{
73733  */
73734 
73735 /** LPCG_GPIO_CLK - Register Layout Typedef */
73736 typedef struct {
73737   __IO uint32_t LPCG_GPIO_CLK_0;                   /**< na, offset: 0x0 */
73738 } LPCG_GPIO_CLK_Type;
73739 
73740 /* ----------------------------------------------------------------------------
73741    -- LPCG_GPIO_CLK Register Masks
73742    ---------------------------------------------------------------------------- */
73743 
73744 /*!
73745  * @addtogroup LPCG_GPIO_CLK_Register_Masks LPCG_GPIO_CLK Register Masks
73746  * @{
73747  */
73748 
73749 /*! @name LPCG_GPIO_CLK_0 - na */
73750 /*! @{ */
73751 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_MASK (0xFFFFU)
73752 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_SHIFT (0U)
73753 /*! LPCG_GPIO_CLK_0_reserved_0_15 - reserved
73754  */
73755 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_MASK)
73756 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_MASK (0x10000U)
73757 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_SHIFT (16U)
73758 /*! gpio_ipg_clk_s_HWEN - Hardware Enable
73759  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
73760  *  0b1..Enable HW automatic gating
73761  */
73762 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_MASK)
73763 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_MASK (0x20000U)
73764 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_SHIFT (17U)
73765 /*! gpio_ipg_clk_s_SWEN - Software Enable
73766  *  0b0..Disable SW clock regardless of HWEN
73767  *  0b1..Enable SW clock gating
73768  */
73769 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_MASK)
73770 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_MASK (0x40000U)
73771 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_SHIFT (18U)
73772 /*! LPCG_GPIO_CLK_0_reserved_18_18 - reserved
73773  */
73774 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_MASK)
73775 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_MASK (0x80000U)
73776 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_SHIFT (19U)
73777 /*! gpio_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
73778  */
73779 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_MASK)
73780 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_MASK (0xFFF00000U)
73781 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_SHIFT (20U)
73782 /*! LPCG_GPIO_CLK_0_reserved_20_31 - reserved
73783  */
73784 #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_MASK)
73785 /*! @} */
73786 
73787 
73788 /*!
73789  * @}
73790  */ /* end of group LPCG_GPIO_CLK_Register_Masks */
73791 
73792 
73793 /* LPCG_GPIO_CLK - Peripheral instance base addresses */
73794 /** Peripheral HSIO__LPCG_GPIO_IPG_CLK_S base address */
73795 #define HSIO__LPCG_GPIO_IPG_CLK_S_BASE           (0x5F100000u)
73796 /** Peripheral HSIO__LPCG_GPIO_IPG_CLK_S base pointer */
73797 #define HSIO__LPCG_GPIO_IPG_CLK_S                ((LPCG_GPIO_CLK_Type *)HSIO__LPCG_GPIO_IPG_CLK_S_BASE)
73798 /** Array initializer of LPCG_GPIO_CLK peripheral base addresses */
73799 #define LPCG_GPIO_CLK_BASE_ADDRS                 { HSIO__LPCG_GPIO_IPG_CLK_S_BASE }
73800 /** Array initializer of LPCG_GPIO_CLK peripheral base pointers */
73801 #define LPCG_GPIO_CLK_BASE_PTRS                  { HSIO__LPCG_GPIO_IPG_CLK_S }
73802 
73803 /*!
73804  * @}
73805  */ /* end of group LPCG_GPIO_CLK_Peripheral_Access_Layer */
73806 
73807 
73808 /* ----------------------------------------------------------------------------
73809    -- LPCG_H264 Peripheral Access Layer
73810    ---------------------------------------------------------------------------- */
73811 
73812 /*!
73813  * @addtogroup LPCG_H264_Peripheral_Access_Layer LPCG_H264 Peripheral Access Layer
73814  * @{
73815  */
73816 
73817 /** LPCG_H264 - Register Layout Typedef */
73818 typedef struct {
73819   __IO uint32_t LPCG_H264_0;                       /**< na, offset: 0x0 */
73820 } LPCG_H264_Type;
73821 
73822 /* ----------------------------------------------------------------------------
73823    -- LPCG_H264 Register Masks
73824    ---------------------------------------------------------------------------- */
73825 
73826 /*!
73827  * @addtogroup LPCG_H264_Register_Masks LPCG_H264 Register Masks
73828  * @{
73829  */
73830 
73831 /*! @name LPCG_H264_0 - na */
73832 /*! @{ */
73833 #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0_MASK (0x1U)
73834 #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0_SHIFT (0U)
73835 /*! LPCG_H264_0_reserved_0_0 - reserved
73836  */
73837 #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0_SHIFT)) & LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0_MASK)
73838 #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_MASK (0x2U)
73839 #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_SHIFT (1U)
73840 /*! med_dec_mfd_h264_clk_gated_SWEN - Software Enable
73841  *  0b0..Disable SW clock regardless of HWEN
73842  *  0b1..Enable SW clock gating
73843  */
73844 #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_SHIFT)) & LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_MASK)
73845 #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2_MASK (0x4U)
73846 #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2_SHIFT (2U)
73847 /*! LPCG_H264_0_reserved_2_2 - reserved
73848  */
73849 #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2_SHIFT)) & LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2_MASK)
73850 #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_MASK (0x8U)
73851 #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_SHIFT (3U)
73852 /*! med_dec_mfd_h264_clk_gated_STOP - show clock root status, 1 means clock stopped
73853  */
73854 #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_SHIFT)) & LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_MASK)
73855 #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31_MASK (0xFFFFFFF0U)
73856 #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31_SHIFT (4U)
73857 /*! LPCG_H264_0_reserved_4_31 - reserved
73858  */
73859 #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31_SHIFT)) & LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31_MASK)
73860 /*! @} */
73861 
73862 
73863 /*!
73864  * @}
73865  */ /* end of group LPCG_H264_Register_Masks */
73866 
73867 
73868 /* LPCG_H264 - Peripheral instance base addresses */
73869 /** Peripheral VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED base address */
73870 #define VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED_BASE (0x2D080000u)
73871 /** Peripheral VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED base pointer */
73872 #define VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED     ((LPCG_H264_Type *)VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED_BASE)
73873 /** Array initializer of LPCG_H264 peripheral base addresses */
73874 #define LPCG_H264_BASE_ADDRS                     { VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED_BASE }
73875 /** Array initializer of LPCG_H264 peripheral base pointers */
73876 #define LPCG_H264_BASE_PTRS                      { VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED }
73877 
73878 /*!
73879  * @}
73880  */ /* end of group LPCG_H264_Peripheral_Access_Layer */
73881 
73882 
73883 /* ----------------------------------------------------------------------------
73884    -- LPCG_LPCG_0 Peripheral Access Layer
73885    ---------------------------------------------------------------------------- */
73886 
73887 /*!
73888  * @addtogroup LPCG_LPCG_0_Peripheral_Access_Layer LPCG_LPCG_0 Peripheral Access Layer
73889  * @{
73890  */
73891 
73892 /** LPCG_LPCG_0 - Register Layout Typedef */
73893 typedef struct {
73894   __IO uint32_t LPCG_LPCG_0_0;                     /**< na, offset: 0x0 */
73895 } LPCG_LPCG_0_Type;
73896 
73897 /* ----------------------------------------------------------------------------
73898    -- LPCG_LPCG_0 Register Masks
73899    ---------------------------------------------------------------------------- */
73900 
73901 /*!
73902  * @addtogroup LPCG_LPCG_0_Register_Masks LPCG_LPCG_0 Register Masks
73903  * @{
73904  */
73905 
73906 /*! @name LPCG_LPCG_0_0 - na */
73907 /*! @{ */
73908 #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_MASK (0x1U)
73909 #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_SHIFT (0U)
73910 /*! LPCG_lpcg_0_0_reserved_0_0 - reserved
73911  */
73912 #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_MASK)
73913 #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_MASK (0x2U)
73914 #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_SHIFT (1U)
73915 /*! ssi_port0_clk_SWEN - Software Enable
73916  *  0b0..Disable SW clock regardless of HWEN
73917  *  0b1..Enable SW clock gating
73918  */
73919 #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_MASK)
73920 #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_MASK (0x4U)
73921 #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_SHIFT (2U)
73922 /*! LPCG_lpcg_0_0_reserved_2_2 - reserved
73923  */
73924 #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_MASK)
73925 #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_MASK (0x8U)
73926 #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_SHIFT (3U)
73927 /*! ssi_port0_clk_STOP - show clock root status, 1 means clock stopped
73928  */
73929 #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_MASK)
73930 #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_MASK (0xFFFFFFF0U)
73931 #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_SHIFT (4U)
73932 /*! LPCG_lpcg_0_0_reserved_4_31 - reserved
73933  */
73934 #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_MASK)
73935 /*! @} */
73936 
73937 
73938 /*!
73939  * @}
73940  */ /* end of group LPCG_LPCG_0_Register_Masks */
73941 
73942 
73943 /* LPCG_LPCG_0 - Peripheral instance base addresses */
73944 /** Peripheral DRC__LPCG_SSI_PORT0_CLK base address */
73945 #define DRC__LPCG_SSI_PORT0_CLK_BASE             (0xB80C0000u)
73946 /** Peripheral DRC__LPCG_SSI_PORT0_CLK base pointer */
73947 #define DRC__LPCG_SSI_PORT0_CLK                  ((LPCG_LPCG_0_Type *)DRC__LPCG_SSI_PORT0_CLK_BASE)
73948 /** Array initializer of LPCG_LPCG_0 peripheral base addresses */
73949 #define LPCG_LPCG_0_BASE_ADDRS                   { DRC__LPCG_SSI_PORT0_CLK_BASE }
73950 /** Array initializer of LPCG_LPCG_0 peripheral base pointers */
73951 #define LPCG_LPCG_0_BASE_PTRS                    { DRC__LPCG_SSI_PORT0_CLK }
73952 
73953 /*!
73954  * @}
73955  */ /* end of group LPCG_LPCG_0_Peripheral_Access_Layer */
73956 
73957 
73958 /* ----------------------------------------------------------------------------
73959    -- LPCG_LPCG_1 Peripheral Access Layer
73960    ---------------------------------------------------------------------------- */
73961 
73962 /*!
73963  * @addtogroup LPCG_LPCG_1_Peripheral_Access_Layer LPCG_LPCG_1 Peripheral Access Layer
73964  * @{
73965  */
73966 
73967 /** LPCG_LPCG_1 - Register Layout Typedef */
73968 typedef struct {
73969   __IO uint32_t LPCG_LPCG_1_0;                     /**< na, offset: 0x0 */
73970 } LPCG_LPCG_1_Type;
73971 
73972 /* ----------------------------------------------------------------------------
73973    -- LPCG_LPCG_1 Register Masks
73974    ---------------------------------------------------------------------------- */
73975 
73976 /*!
73977  * @addtogroup LPCG_LPCG_1_Register_Masks LPCG_LPCG_1 Register Masks
73978  * @{
73979  */
73980 
73981 /*! @name LPCG_LPCG_1_0 - na */
73982 /*! @{ */
73983 #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_MASK (0x1U)
73984 #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_SHIFT (0U)
73985 /*! LPCG_lpcg_1_0_reserved_0_0 - reserved
73986  */
73987 #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_MASK)
73988 #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_MASK (0x2U)
73989 #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_SHIFT (1U)
73990 /*! ddr_ctl_core_ddrc_core_clk_SWEN - Software Enable
73991  *  0b0..Disable SW clock regardless of HWEN
73992  *  0b1..Enable SW clock gating
73993  */
73994 #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_MASK)
73995 #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_MASK (0x4U)
73996 #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_SHIFT (2U)
73997 /*! LPCG_lpcg_1_0_reserved_2_2 - reserved
73998  */
73999 #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_MASK)
74000 #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_MASK (0x8U)
74001 #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_SHIFT (3U)
74002 /*! ddr_ctl_core_ddrc_core_clk_STOP - show clock root status, 1 means clock stopped
74003  */
74004 #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_MASK)
74005 #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_MASK (0xFFFFFFF0U)
74006 #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_SHIFT (4U)
74007 /*! LPCG_lpcg_1_0_reserved_4_31 - reserved
74008  */
74009 #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_MASK)
74010 /*! @} */
74011 
74012 
74013 /*!
74014  * @}
74015  */ /* end of group LPCG_LPCG_1_Register_Masks */
74016 
74017 
74018 /* LPCG_LPCG_1 - Peripheral instance base addresses */
74019 /** Peripheral DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base address */
74020 #define DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE (0xB80D0000u)
74021 /** Peripheral DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base pointer */
74022 #define DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK     ((LPCG_LPCG_1_Type *)DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE)
74023 /** Array initializer of LPCG_LPCG_1 peripheral base addresses */
74024 #define LPCG_LPCG_1_BASE_ADDRS                   { DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE }
74025 /** Array initializer of LPCG_LPCG_1 peripheral base pointers */
74026 #define LPCG_LPCG_1_BASE_PTRS                    { DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK }
74027 
74028 /*!
74029  * @}
74030  */ /* end of group LPCG_LPCG_1_Peripheral_Access_Layer */
74031 
74032 
74033 /* ----------------------------------------------------------------------------
74034    -- LPCG_LPCG_3 Peripheral Access Layer
74035    ---------------------------------------------------------------------------- */
74036 
74037 /*!
74038  * @addtogroup LPCG_LPCG_3_Peripheral_Access_Layer LPCG_LPCG_3 Peripheral Access Layer
74039  * @{
74040  */
74041 
74042 /** LPCG_LPCG_3 - Register Layout Typedef */
74043 typedef struct {
74044   __IO uint32_t LPCG_LPCG_3_0;                     /**< na, offset: 0x0 */
74045   __IO uint32_t LPCG_LPCG_3_4;                     /**< na, offset: 0x4 */
74046 } LPCG_LPCG_3_Type;
74047 
74048 /* ----------------------------------------------------------------------------
74049    -- LPCG_LPCG_3 Register Masks
74050    ---------------------------------------------------------------------------- */
74051 
74052 /*!
74053  * @addtogroup LPCG_LPCG_3_Register_Masks LPCG_LPCG_3 Register Masks
74054  * @{
74055  */
74056 
74057 /*! @name LPCG_LPCG_3_0 - na */
74058 /*! @{ */
74059 #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_MASK (0x1U)
74060 #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_SHIFT (0U)
74061 /*! LPCG_lpcg_3_0_reserved_0_0 - reserved
74062  */
74063 #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_MASK)
74064 #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_MASK (0x2U)
74065 #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT (1U)
74066 /*! ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN - Software Enable
74067  *  0b0..Disable SW clock regardless of HWEN
74068  *  0b1..Enable SW clock gating
74069  */
74070 #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_MASK)
74071 #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_MASK (0x4U)
74072 #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_SHIFT (2U)
74073 /*! LPCG_lpcg_3_0_reserved_2_2 - reserved
74074  */
74075 #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_MASK)
74076 #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_MASK (0x8U)
74077 #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT (3U)
74078 /*! ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP - show clock root status, 1 means clock stopped
74079  */
74080 #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_MASK)
74081 #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_MASK (0xFFFFFFF0U)
74082 #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_SHIFT (4U)
74083 /*! LPCG_lpcg_3_0_reserved_4_31 - reserved
74084  */
74085 #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_MASK)
74086 /*! @} */
74087 
74088 /*! @name LPCG_LPCG_3_4 - na */
74089 /*! @{ */
74090 #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_MASK (0x1U)
74091 #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_SHIFT (0U)
74092 /*! LPCG_lpcg_3_4_reserved_0_0 - reserved
74093  */
74094 #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_MASK)
74095 #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_MASK (0x2U)
74096 #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT (1U)
74097 /*! ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN - Software Enable
74098  *  0b0..Disable SW clock regardless of HWEN
74099  *  0b1..Enable SW clock gating
74100  */
74101 #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_MASK)
74102 #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_MASK (0x4U)
74103 #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_SHIFT (2U)
74104 /*! LPCG_lpcg_3_4_reserved_2_2 - reserved
74105  */
74106 #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_MASK)
74107 #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_MASK (0x8U)
74108 #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT (3U)
74109 /*! ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP - show clock root status, 1 means clock stopped
74110  */
74111 #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_MASK)
74112 #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_MASK (0xFFFFFFF0U)
74113 #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_SHIFT (4U)
74114 /*! LPCG_lpcg_3_4_reserved_4_31 - reserved
74115  */
74116 #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_MASK)
74117 /*! @} */
74118 
74119 
74120 /*!
74121  * @}
74122  */ /* end of group LPCG_LPCG_3_Register_Masks */
74123 
74124 
74125 /* LPCG_LPCG_3 - Peripheral instance base addresses */
74126 /** Peripheral DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base address */
74127 #define DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE (0xB80F0000u)
74128 /** Peripheral DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base pointer */
74129 #define DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 ((LPCG_LPCG_3_Type *)DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE)
74130 /** Array initializer of LPCG_LPCG_3 peripheral base addresses */
74131 #define LPCG_LPCG_3_BASE_ADDRS                   { DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE }
74132 /** Array initializer of LPCG_LPCG_3 peripheral base pointers */
74133 #define LPCG_LPCG_3_BASE_PTRS                    { DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 }
74134 
74135 /*!
74136  * @}
74137  */ /* end of group LPCG_LPCG_3_Peripheral_Access_Layer */
74138 
74139 
74140 /* ----------------------------------------------------------------------------
74141    -- LPCG_LPCG_4 Peripheral Access Layer
74142    ---------------------------------------------------------------------------- */
74143 
74144 /*!
74145  * @addtogroup LPCG_LPCG_4_Peripheral_Access_Layer LPCG_LPCG_4 Peripheral Access Layer
74146  * @{
74147  */
74148 
74149 /** LPCG_LPCG_4 - Register Layout Typedef */
74150 typedef struct {
74151   __IO uint32_t LPCG_LPCG_4_0;                     /**< na, offset: 0x0 */
74152 } LPCG_LPCG_4_Type;
74153 
74154 /* ----------------------------------------------------------------------------
74155    -- LPCG_LPCG_4 Register Masks
74156    ---------------------------------------------------------------------------- */
74157 
74158 /*!
74159  * @addtogroup LPCG_LPCG_4_Register_Masks LPCG_LPCG_4 Register Masks
74160  * @{
74161  */
74162 
74163 /*! @name LPCG_LPCG_4_0 - na */
74164 /*! @{ */
74165 #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0_MASK (0x1U)
74166 #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0_SHIFT (0U)
74167 /*! LPCG_lpcg_4_0_reserved_0_0 - reserved
74168  */
74169 #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0_MASK)
74170 #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN_MASK (0x2U)
74171 #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN_SHIFT (1U)
74172 /*! ddr_ctl_sbr_clk_SWEN - Software Enable
74173  *  0b0..Disable SW clock regardless of HWEN
74174  *  0b1..Enable SW clock gating
74175  */
74176 #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN_MASK)
74177 #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2_MASK (0x4U)
74178 #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2_SHIFT (2U)
74179 /*! LPCG_lpcg_4_0_reserved_2_2 - reserved
74180  */
74181 #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2_MASK)
74182 #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP_MASK (0x8U)
74183 #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP_SHIFT (3U)
74184 /*! ddr_ctl_sbr_clk_STOP - show clock root status, 1 means clock stopped
74185  */
74186 #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP_MASK)
74187 #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31_MASK (0xFFFFFFF0U)
74188 #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31_SHIFT (4U)
74189 /*! LPCG_lpcg_4_0_reserved_4_31 - reserved
74190  */
74191 #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31_MASK)
74192 /*! @} */
74193 
74194 
74195 /*!
74196  * @}
74197  */ /* end of group LPCG_LPCG_4_Register_Masks */
74198 
74199 
74200 /* LPCG_LPCG_4 - Peripheral instance base addresses */
74201 /** Peripheral DRC__LPCG_DDR_CTL_SBR_CLK base address */
74202 #define DRC__LPCG_DDR_CTL_SBR_CLK_BASE           (0xB80B0000u)
74203 /** Peripheral DRC__LPCG_DDR_CTL_SBR_CLK base pointer */
74204 #define DRC__LPCG_DDR_CTL_SBR_CLK                ((LPCG_LPCG_4_Type *)DRC__LPCG_DDR_CTL_SBR_CLK_BASE)
74205 /** Array initializer of LPCG_LPCG_4 peripheral base addresses */
74206 #define LPCG_LPCG_4_BASE_ADDRS                   { DRC__LPCG_DDR_CTL_SBR_CLK_BASE }
74207 /** Array initializer of LPCG_LPCG_4 peripheral base pointers */
74208 #define LPCG_LPCG_4_BASE_PTRS                    { DRC__LPCG_DDR_CTL_SBR_CLK }
74209 
74210 /*!
74211  * @}
74212  */ /* end of group LPCG_LPCG_4_Peripheral_Access_Layer */
74213 
74214 
74215 /* ----------------------------------------------------------------------------
74216    -- LPCG_LPCG_5 Peripheral Access Layer
74217    ---------------------------------------------------------------------------- */
74218 
74219 /*!
74220  * @addtogroup LPCG_LPCG_5_Peripheral_Access_Layer LPCG_LPCG_5 Peripheral Access Layer
74221  * @{
74222  */
74223 
74224 /** LPCG_LPCG_5 - Register Layout Typedef */
74225 typedef struct {
74226   __IO uint32_t LPCG_LPCG_5_0;                     /**< na, offset: 0x0 */
74227 } LPCG_LPCG_5_Type;
74228 
74229 /* ----------------------------------------------------------------------------
74230    -- LPCG_LPCG_5 Register Masks
74231    ---------------------------------------------------------------------------- */
74232 
74233 /*!
74234  * @addtogroup LPCG_LPCG_5_Register_Masks LPCG_LPCG_5 Register Masks
74235  * @{
74236  */
74237 
74238 /*! @name LPCG_LPCG_5_0 - na */
74239 /*! @{ */
74240 #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0_MASK (0x1U)
74241 #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0_SHIFT (0U)
74242 /*! LPCG_lpcg_5_0_reserved_0_0 - reserved
74243  */
74244 #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0_MASK)
74245 #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN_MASK (0x2U)
74246 #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN_SHIFT (1U)
74247 /*! ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN - Software Enable
74248  *  0b0..Disable SW clock regardless of HWEN
74249  *  0b1..Enable SW clock gating
74250  */
74251 #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN_MASK)
74252 #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2_MASK (0x4U)
74253 #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2_SHIFT (2U)
74254 /*! LPCG_lpcg_5_0_reserved_2_2 - reserved
74255  */
74256 #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2_MASK)
74257 #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP_MASK (0x8U)
74258 #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP_SHIFT (3U)
74259 /*! ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP - show clock root status, 1 means clock stopped
74260  */
74261 #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP_MASK)
74262 #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31_MASK (0xFFFFFFF0U)
74263 #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31_SHIFT (4U)
74264 /*! LPCG_lpcg_5_0_reserved_4_31 - reserved
74265  */
74266 #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31_MASK)
74267 /*! @} */
74268 
74269 
74270 /*!
74271  * @}
74272  */ /* end of group LPCG_LPCG_5_Register_Masks */
74273 
74274 
74275 /* LPCG_LPCG_5 - Peripheral instance base addresses */
74276 /** Peripheral DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP base address */
74277 #define DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP_BASE (0xB80A0000u)
74278 /** Peripheral DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP base pointer */
74279 #define DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP ((LPCG_LPCG_5_Type *)DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP_BASE)
74280 /** Array initializer of LPCG_LPCG_5 peripheral base addresses */
74281 #define LPCG_LPCG_5_BASE_ADDRS                   { DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP_BASE }
74282 /** Array initializer of LPCG_LPCG_5 peripheral base pointers */
74283 #define LPCG_LPCG_5_BASE_PTRS                    { DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP }
74284 
74285 /*!
74286  * @}
74287  */ /* end of group LPCG_LPCG_5_Peripheral_Access_Layer */
74288 
74289 
74290 /* ----------------------------------------------------------------------------
74291    -- LPCG_LPCG_6 Peripheral Access Layer
74292    ---------------------------------------------------------------------------- */
74293 
74294 /*!
74295  * @addtogroup LPCG_LPCG_6_Peripheral_Access_Layer LPCG_LPCG_6 Peripheral Access Layer
74296  * @{
74297  */
74298 
74299 /** LPCG_LPCG_6 - Register Layout Typedef */
74300 typedef struct {
74301   __IO uint32_t LPCG_LPCG_6_0;                     /**< na, offset: 0x0 */
74302 } LPCG_LPCG_6_Type;
74303 
74304 /* ----------------------------------------------------------------------------
74305    -- LPCG_LPCG_6 Register Masks
74306    ---------------------------------------------------------------------------- */
74307 
74308 /*!
74309  * @addtogroup LPCG_LPCG_6_Register_Masks LPCG_LPCG_6 Register Masks
74310  * @{
74311  */
74312 
74313 /*! @name LPCG_LPCG_6_0 - na */
74314 /*! @{ */
74315 #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0_MASK (0x1U)
74316 #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0_SHIFT (0U)
74317 /*! LPCG_lpcg_6_0_reserved_0_0 - reserved
74318  */
74319 #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0_MASK)
74320 #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN_MASK (0x2U)
74321 #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN_SHIFT (1U)
74322 /*! atpg_phy_pub_clk_clk_mux_D0_SWEN - Software Enable
74323  *  0b0..Disable SW clock regardless of HWEN
74324  *  0b1..Enable SW clock gating
74325  */
74326 #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN_MASK)
74327 #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2_MASK (0x4U)
74328 #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2_SHIFT (2U)
74329 /*! LPCG_lpcg_6_0_reserved_2_2 - reserved
74330  */
74331 #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2_MASK)
74332 #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP_MASK (0x8U)
74333 #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP_SHIFT (3U)
74334 /*! atpg_phy_pub_clk_clk_mux_D0_STOP - show clock root status, 1 means clock stopped
74335  */
74336 #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP_MASK)
74337 #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31_MASK (0xFFFFFFF0U)
74338 #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31_SHIFT (4U)
74339 /*! LPCG_lpcg_6_0_reserved_4_31 - reserved
74340  */
74341 #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31_MASK)
74342 /*! @} */
74343 
74344 
74345 /*!
74346  * @}
74347  */ /* end of group LPCG_LPCG_6_Register_Masks */
74348 
74349 
74350 /* LPCG_LPCG_6 - Peripheral instance base addresses */
74351 /** Peripheral DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0 base address */
74352 #define DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0_BASE (0xB8090000u)
74353 /** Peripheral DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0 base pointer */
74354 #define DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0    ((LPCG_LPCG_6_Type *)DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0_BASE)
74355 /** Array initializer of LPCG_LPCG_6 peripheral base addresses */
74356 #define LPCG_LPCG_6_BASE_ADDRS                   { DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0_BASE }
74357 /** Array initializer of LPCG_LPCG_6 peripheral base pointers */
74358 #define LPCG_LPCG_6_BASE_PTRS                    { DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0 }
74359 
74360 /*!
74361  * @}
74362  */ /* end of group LPCG_LPCG_6_Peripheral_Access_Layer */
74363 
74364 
74365 /* ----------------------------------------------------------------------------
74366    -- LPCG_LPCG_ACM_REGS Peripheral Access Layer
74367    ---------------------------------------------------------------------------- */
74368 
74369 /*!
74370  * @addtogroup LPCG_LPCG_ACM_REGS_Peripheral_Access_Layer LPCG_LPCG_ACM_REGS Peripheral Access Layer
74371  * @{
74372  */
74373 
74374 /** LPCG_LPCG_ACM_REGS - Register Layout Typedef */
74375 typedef struct {
74376   __IO uint32_t LPCG_LPCG_ACM_REGS_0;              /**< na, offset: 0x0 */
74377 } LPCG_LPCG_ACM_REGS_Type;
74378 
74379 /* ----------------------------------------------------------------------------
74380    -- LPCG_LPCG_ACM_REGS Register Masks
74381    ---------------------------------------------------------------------------- */
74382 
74383 /*!
74384  * @addtogroup LPCG_LPCG_ACM_REGS_Register_Masks LPCG_LPCG_ACM_REGS Register Masks
74385  * @{
74386  */
74387 
74388 /*! @name LPCG_LPCG_ACM_REGS_0 - na */
74389 /*! @{ */
74390 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15_MASK (0xFFFFU)
74391 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15_SHIFT (0U)
74392 /*! LPCG_lpcg_acm_regs_0_reserved_0_15 - reserved
74393  */
74394 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15_MASK)
74395 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_MASK (0x10000U)
74396 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_SHIFT (16U)
74397 /*! acm_regs_ipg_clk_HWEN - Hardware Enable
74398  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
74399  *  0b1..Enable HW automatic gating
74400  */
74401 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_MASK)
74402 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_MASK (0x20000U)
74403 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_SHIFT (17U)
74404 /*! acm_regs_ipg_clk_SWEN - Software Enable
74405  *  0b0..Disable SW clock regardless of HWEN
74406  *  0b1..Enable SW clock gating
74407  */
74408 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_MASK)
74409 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18_MASK (0x40000U)
74410 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18_SHIFT (18U)
74411 /*! LPCG_lpcg_acm_regs_0_reserved_18_18 - reserved
74412  */
74413 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18_MASK)
74414 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_MASK (0x80000U)
74415 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_SHIFT (19U)
74416 /*! acm_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped
74417  */
74418 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_MASK)
74419 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31_MASK (0xFFF00000U)
74420 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31_SHIFT (20U)
74421 /*! LPCG_lpcg_acm_regs_0_reserved_20_31 - reserved
74422  */
74423 #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31_MASK)
74424 /*! @} */
74425 
74426 
74427 /*!
74428  * @}
74429  */ /* end of group LPCG_LPCG_ACM_REGS_Register_Masks */
74430 
74431 
74432 /* LPCG_LPCG_ACM_REGS - Peripheral instance base addresses */
74433 /** Peripheral ADMA__LPCG_ACM_REGS_IPG_CLK base address */
74434 #define ADMA__LPCG_ACM_REGS_IPG_CLK_BASE         (0x59C60000u)
74435 /** Peripheral ADMA__LPCG_ACM_REGS_IPG_CLK base pointer */
74436 #define ADMA__LPCG_ACM_REGS_IPG_CLK              ((LPCG_LPCG_ACM_REGS_Type *)ADMA__LPCG_ACM_REGS_IPG_CLK_BASE)
74437 /** Array initializer of LPCG_LPCG_ACM_REGS peripheral base addresses */
74438 #define LPCG_LPCG_ACM_REGS_BASE_ADDRS            { ADMA__LPCG_ACM_REGS_IPG_CLK_BASE }
74439 /** Array initializer of LPCG_LPCG_ACM_REGS peripheral base pointers */
74440 #define LPCG_LPCG_ACM_REGS_BASE_PTRS             { ADMA__LPCG_ACM_REGS_IPG_CLK }
74441 
74442 /*!
74443  * @}
74444  */ /* end of group LPCG_LPCG_ACM_REGS_Peripheral_Access_Layer */
74445 
74446 
74447 /* ----------------------------------------------------------------------------
74448    -- LPCG_LPCG_ADC0 Peripheral Access Layer
74449    ---------------------------------------------------------------------------- */
74450 
74451 /*!
74452  * @addtogroup LPCG_LPCG_ADC0_Peripheral_Access_Layer LPCG_LPCG_ADC0 Peripheral Access Layer
74453  * @{
74454  */
74455 
74456 /** LPCG_LPCG_ADC0 - Register Layout Typedef */
74457 typedef struct {
74458   __IO uint32_t LPCG_LPCG_ADC0_0;                  /**< na, offset: 0x0 */
74459 } LPCG_LPCG_ADC0_Type;
74460 
74461 /* ----------------------------------------------------------------------------
74462    -- LPCG_LPCG_ADC0 Register Masks
74463    ---------------------------------------------------------------------------- */
74464 
74465 /*!
74466  * @addtogroup LPCG_LPCG_ADC0_Register_Masks LPCG_LPCG_ADC0 Register Masks
74467  * @{
74468  */
74469 
74470 /*! @name LPCG_LPCG_ADC0_0 - na */
74471 /*! @{ */
74472 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0_MASK (0x1U)
74473 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0_SHIFT (0U)
74474 /*! LPCG_lpcg_adc0_0_reserved_0_0 - reserved
74475  */
74476 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0_MASK)
74477 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN_MASK (0x2U)
74478 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN_SHIFT (1U)
74479 /*! anamix_adc_clk_adc0_SWEN - Software Enable
74480  *  0b0..Disable SW clock regardless of HWEN
74481  *  0b1..Enable SW clock gating
74482  */
74483 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN_MASK)
74484 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2_MASK (0x4U)
74485 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2_SHIFT (2U)
74486 /*! LPCG_lpcg_adc0_0_reserved_2_2 - reserved
74487  */
74488 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2_MASK)
74489 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP_MASK (0x8U)
74490 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP_SHIFT (3U)
74491 /*! anamix_adc_clk_adc0_STOP - show clock root status, 1 means clock stopped
74492  */
74493 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP_MASK)
74494 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15_MASK (0xFFF0U)
74495 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15_SHIFT (4U)
74496 /*! LPCG_lpcg_adc0_0_reserved_4_15 - reserved
74497  */
74498 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15_MASK)
74499 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_MASK (0x10000U)
74500 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_SHIFT (16U)
74501 /*! anamix_ipg_clk_s_adc0_HWEN - Hardware Enable
74502  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
74503  *  0b1..Enable HW automatic gating
74504  */
74505 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_MASK)
74506 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_MASK (0x20000U)
74507 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_SHIFT (17U)
74508 /*! anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN - Software Enable
74509  *  0b0..Disable SW clock regardless of HWEN
74510  *  0b1..Enable SW clock gating
74511  */
74512 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_MASK)
74513 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18_MASK (0x40000U)
74514 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18_SHIFT (18U)
74515 /*! LPCG_lpcg_adc0_0_reserved_18_18 - reserved
74516  */
74517 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18_MASK)
74518 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_MASK (0x80000U)
74519 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_SHIFT (19U)
74520 /*! anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP - show clock root status, 1 means clock stopped
74521  */
74522 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_MASK)
74523 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31_MASK (0xFFF00000U)
74524 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31_SHIFT (20U)
74525 /*! LPCG_lpcg_adc0_0_reserved_20_31 - reserved
74526  */
74527 #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31_MASK)
74528 /*! @} */
74529 
74530 
74531 /*!
74532  * @}
74533  */ /* end of group LPCG_LPCG_ADC0_Register_Masks */
74534 
74535 
74536 /* LPCG_LPCG_ADC0 - Peripheral instance base addresses */
74537 /** Peripheral ADMA__LPCG_ANAMIX_IPG_CLK_ADC0 base address */
74538 #define ADMA__LPCG_ANAMIX_IPG_CLK_ADC0_BASE      (0x5AC80000u)
74539 /** Peripheral ADMA__LPCG_ANAMIX_IPG_CLK_ADC0 base pointer */
74540 #define ADMA__LPCG_ANAMIX_IPG_CLK_ADC0           ((LPCG_LPCG_ADC0_Type *)ADMA__LPCG_ANAMIX_IPG_CLK_ADC0_BASE)
74541 /** Array initializer of LPCG_LPCG_ADC0 peripheral base addresses */
74542 #define LPCG_LPCG_ADC0_BASE_ADDRS                { ADMA__LPCG_ANAMIX_IPG_CLK_ADC0_BASE }
74543 /** Array initializer of LPCG_LPCG_ADC0 peripheral base pointers */
74544 #define LPCG_LPCG_ADC0_BASE_PTRS                 { ADMA__LPCG_ANAMIX_IPG_CLK_ADC0 }
74545 
74546 /*!
74547  * @}
74548  */ /* end of group LPCG_LPCG_ADC0_Peripheral_Access_Layer */
74549 
74550 
74551 /* ----------------------------------------------------------------------------
74552    -- LPCG_LPCG_AMIX Peripheral Access Layer
74553    ---------------------------------------------------------------------------- */
74554 
74555 /*!
74556  * @addtogroup LPCG_LPCG_AMIX_Peripheral_Access_Layer LPCG_LPCG_AMIX Peripheral Access Layer
74557  * @{
74558  */
74559 
74560 /** LPCG_LPCG_AMIX - Register Layout Typedef */
74561 typedef struct {
74562   __IO uint32_t LPCG_LPCG_AMIX_0;                  /**< na, offset: 0x0 */
74563 } LPCG_LPCG_AMIX_Type;
74564 
74565 /* ----------------------------------------------------------------------------
74566    -- LPCG_LPCG_AMIX Register Masks
74567    ---------------------------------------------------------------------------- */
74568 
74569 /*!
74570  * @addtogroup LPCG_LPCG_AMIX_Register_Masks LPCG_LPCG_AMIX Register Masks
74571  * @{
74572  */
74573 
74574 /*! @name LPCG_LPCG_AMIX_0 - na */
74575 /*! @{ */
74576 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_MASK (0x1U)
74577 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_SHIFT (0U)
74578 /*! LPCG_lpcg_amix_0_reserved_0_0 - reserved
74579  */
74580 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_MASK)
74581 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_MASK (0x2U)
74582 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_SHIFT (1U)
74583 /*! amix_ipg_clk_SWEN - Software Enable
74584  *  0b0..Disable SW clock regardless of HWEN
74585  *  0b1..Enable SW clock gating
74586  */
74587 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_MASK)
74588 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_MASK (0x4U)
74589 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_SHIFT (2U)
74590 /*! LPCG_lpcg_amix_0_reserved_2_2 - reserved
74591  */
74592 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_MASK)
74593 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_MASK (0x8U)
74594 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_SHIFT (3U)
74595 /*! amix_ipg_clk_STOP - show clock root status, 1 means clock stopped
74596  */
74597 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_MASK)
74598 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_MASK (0xFFFFFFF0U)
74599 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_SHIFT (4U)
74600 /*! LPCG_lpcg_amix_0_reserved_4_31 - reserved
74601  */
74602 #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_MASK)
74603 /*! @} */
74604 
74605 
74606 /*!
74607  * @}
74608  */ /* end of group LPCG_LPCG_AMIX_Register_Masks */
74609 
74610 
74611 /* LPCG_LPCG_AMIX - Peripheral instance base addresses */
74612 /** Peripheral ADMA__LPCG_AMIX_IPG_CLK base address */
74613 #define ADMA__LPCG_AMIX_IPG_CLK_BASE             (0x59C40000u)
74614 /** Peripheral ADMA__LPCG_AMIX_IPG_CLK base pointer */
74615 #define ADMA__LPCG_AMIX_IPG_CLK                  ((LPCG_LPCG_AMIX_Type *)ADMA__LPCG_AMIX_IPG_CLK_BASE)
74616 /** Array initializer of LPCG_LPCG_AMIX peripheral base addresses */
74617 #define LPCG_LPCG_AMIX_BASE_ADDRS                { ADMA__LPCG_AMIX_IPG_CLK_BASE }
74618 /** Array initializer of LPCG_LPCG_AMIX peripheral base pointers */
74619 #define LPCG_LPCG_AMIX_BASE_PTRS                 { ADMA__LPCG_AMIX_IPG_CLK }
74620 
74621 /*!
74622  * @}
74623  */ /* end of group LPCG_LPCG_AMIX_Peripheral_Access_Layer */
74624 
74625 
74626 /* ----------------------------------------------------------------------------
74627    -- LPCG_LPCG_ASRC0 Peripheral Access Layer
74628    ---------------------------------------------------------------------------- */
74629 
74630 /*!
74631  * @addtogroup LPCG_LPCG_ASRC0_Peripheral_Access_Layer LPCG_LPCG_ASRC0 Peripheral Access Layer
74632  * @{
74633  */
74634 
74635 /** LPCG_LPCG_ASRC0 - Register Layout Typedef */
74636 typedef struct {
74637   __IO uint32_t LPCG_LPCG_ASRC0_0;                 /**< na, offset: 0x0 */
74638 } LPCG_LPCG_ASRC0_Type;
74639 
74640 /* ----------------------------------------------------------------------------
74641    -- LPCG_LPCG_ASRC0 Register Masks
74642    ---------------------------------------------------------------------------- */
74643 
74644 /*!
74645  * @addtogroup LPCG_LPCG_ASRC0_Register_Masks LPCG_LPCG_ASRC0 Register Masks
74646  * @{
74647  */
74648 
74649 /*! @name LPCG_LPCG_ASRC0_0 - na */
74650 /*! @{ */
74651 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16_MASK (0x1FFFFU)
74652 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16_SHIFT (0U)
74653 /*! LPCG_lpcg_asrc0_0_reserved_0_16 - reserved
74654  */
74655 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16_MASK)
74656 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_MASK (0x20000U)
74657 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_SHIFT (17U)
74658 /*! asrc0_ipg_clk_SWEN - Software Enable
74659  *  0b0..Disable SW clock regardless of HWEN
74660  *  0b1..Enable SW clock gating
74661  */
74662 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_MASK)
74663 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18_MASK (0x40000U)
74664 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18_SHIFT (18U)
74665 /*! LPCG_lpcg_asrc0_0_reserved_18_18 - reserved
74666  */
74667 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18_MASK)
74668 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_MASK (0x80000U)
74669 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_SHIFT (19U)
74670 /*! asrc0_ipg_clk_STOP - show clock root status, 1 means clock stopped
74671  */
74672 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_MASK)
74673 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31_MASK (0xFFF00000U)
74674 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31_SHIFT (20U)
74675 /*! LPCG_lpcg_asrc0_0_reserved_20_31 - reserved
74676  */
74677 #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31_MASK)
74678 /*! @} */
74679 
74680 
74681 /*!
74682  * @}
74683  */ /* end of group LPCG_LPCG_ASRC0_Register_Masks */
74684 
74685 
74686 /* LPCG_LPCG_ASRC0 - Peripheral instance base addresses */
74687 /** Peripheral ADMA__LPCG_ASRC0_IPG_CLK base address */
74688 #define ADMA__LPCG_ASRC0_IPG_CLK_BASE            (0x59400000u)
74689 /** Peripheral ADMA__LPCG_ASRC0_IPG_CLK base pointer */
74690 #define ADMA__LPCG_ASRC0_IPG_CLK                 ((LPCG_LPCG_ASRC0_Type *)ADMA__LPCG_ASRC0_IPG_CLK_BASE)
74691 /** Array initializer of LPCG_LPCG_ASRC0 peripheral base addresses */
74692 #define LPCG_LPCG_ASRC0_BASE_ADDRS               { ADMA__LPCG_ASRC0_IPG_CLK_BASE }
74693 /** Array initializer of LPCG_LPCG_ASRC0 peripheral base pointers */
74694 #define LPCG_LPCG_ASRC0_BASE_PTRS                { ADMA__LPCG_ASRC0_IPG_CLK }
74695 
74696 /*!
74697  * @}
74698  */ /* end of group LPCG_LPCG_ASRC0_Peripheral_Access_Layer */
74699 
74700 
74701 /* ----------------------------------------------------------------------------
74702    -- LPCG_LPCG_ASRC1 Peripheral Access Layer
74703    ---------------------------------------------------------------------------- */
74704 
74705 /*!
74706  * @addtogroup LPCG_LPCG_ASRC1_Peripheral_Access_Layer LPCG_LPCG_ASRC1 Peripheral Access Layer
74707  * @{
74708  */
74709 
74710 /** LPCG_LPCG_ASRC1 - Register Layout Typedef */
74711 typedef struct {
74712   __IO uint32_t LPCG_LPCG_ASRC1_0;                 /**< na, offset: 0x0 */
74713 } LPCG_LPCG_ASRC1_Type;
74714 
74715 /* ----------------------------------------------------------------------------
74716    -- LPCG_LPCG_ASRC1 Register Masks
74717    ---------------------------------------------------------------------------- */
74718 
74719 /*!
74720  * @addtogroup LPCG_LPCG_ASRC1_Register_Masks LPCG_LPCG_ASRC1 Register Masks
74721  * @{
74722  */
74723 
74724 /*! @name LPCG_LPCG_ASRC1_0 - na */
74725 /*! @{ */
74726 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16_MASK (0x1FFFFU)
74727 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16_SHIFT (0U)
74728 /*! LPCG_lpcg_asrc1_0_reserved_0_16 - reserved
74729  */
74730 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16_MASK)
74731 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_MASK (0x20000U)
74732 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_SHIFT (17U)
74733 /*! asrc1_ipg_clk_SWEN - Software Enable
74734  *  0b0..Disable SW clock regardless of HWEN
74735  *  0b1..Enable SW clock gating
74736  */
74737 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_MASK)
74738 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18_MASK (0x40000U)
74739 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18_SHIFT (18U)
74740 /*! LPCG_lpcg_asrc1_0_reserved_18_18 - reserved
74741  */
74742 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18_MASK)
74743 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_MASK (0x80000U)
74744 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_SHIFT (19U)
74745 /*! asrc1_ipg_clk_STOP - show clock root status, 1 means clock stopped
74746  */
74747 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_MASK)
74748 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31_MASK (0xFFF00000U)
74749 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31_SHIFT (20U)
74750 /*! LPCG_lpcg_asrc1_0_reserved_20_31 - reserved
74751  */
74752 #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31_MASK)
74753 /*! @} */
74754 
74755 
74756 /*!
74757  * @}
74758  */ /* end of group LPCG_LPCG_ASRC1_Register_Masks */
74759 
74760 
74761 /* LPCG_LPCG_ASRC1 - Peripheral instance base addresses */
74762 /** Peripheral ADMA__LPCG_ASRC1_IPG_CLK base address */
74763 #define ADMA__LPCG_ASRC1_IPG_CLK_BASE            (0x59C00000u)
74764 /** Peripheral ADMA__LPCG_ASRC1_IPG_CLK base pointer */
74765 #define ADMA__LPCG_ASRC1_IPG_CLK                 ((LPCG_LPCG_ASRC1_Type *)ADMA__LPCG_ASRC1_IPG_CLK_BASE)
74766 /** Array initializer of LPCG_LPCG_ASRC1 peripheral base addresses */
74767 #define LPCG_LPCG_ASRC1_BASE_ADDRS               { ADMA__LPCG_ASRC1_IPG_CLK_BASE }
74768 /** Array initializer of LPCG_LPCG_ASRC1 peripheral base pointers */
74769 #define LPCG_LPCG_ASRC1_BASE_PTRS                { ADMA__LPCG_ASRC1_IPG_CLK }
74770 
74771 /*!
74772  * @}
74773  */ /* end of group LPCG_LPCG_ASRC1_Peripheral_Access_Layer */
74774 
74775 
74776 /* ----------------------------------------------------------------------------
74777    -- LPCG_LPCG_AUD_PLL_DIV_CLK0 Peripheral Access Layer
74778    ---------------------------------------------------------------------------- */
74779 
74780 /*!
74781  * @addtogroup LPCG_LPCG_AUD_PLL_DIV_CLK0_Peripheral_Access_Layer LPCG_LPCG_AUD_PLL_DIV_CLK0 Peripheral Access Layer
74782  * @{
74783  */
74784 
74785 /** LPCG_LPCG_AUD_PLL_DIV_CLK0 - Register Layout Typedef */
74786 typedef struct {
74787   __IO uint32_t LPCG_LPCG_AUD_PLL_DIV_CLK0_0;      /**< na, offset: 0x0 */
74788 } LPCG_LPCG_AUD_PLL_DIV_CLK0_Type;
74789 
74790 /* ----------------------------------------------------------------------------
74791    -- LPCG_LPCG_AUD_PLL_DIV_CLK0 Register Masks
74792    ---------------------------------------------------------------------------- */
74793 
74794 /*!
74795  * @addtogroup LPCG_LPCG_AUD_PLL_DIV_CLK0_Register_Masks LPCG_LPCG_AUD_PLL_DIV_CLK0 Register Masks
74796  * @{
74797  */
74798 
74799 /*! @name LPCG_LPCG_AUD_PLL_DIV_CLK0_0 - na */
74800 /*! @{ */
74801 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_MASK (0x1U)
74802 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_SHIFT (0U)
74803 /*! LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0 - reserved
74804  */
74805 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_MASK)
74806 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_MASK (0x2U)
74807 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_SHIFT (1U)
74808 /*! acm_aud_pll_div_clk0_SWEN - Software Enable
74809  *  0b0..Disable SW clock regardless of HWEN
74810  *  0b1..Enable SW clock gating
74811  */
74812 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_MASK)
74813 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_MASK (0x4U)
74814 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_SHIFT (2U)
74815 /*! LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2 - reserved
74816  */
74817 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_MASK)
74818 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_MASK (0x8U)
74819 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_SHIFT (3U)
74820 /*! acm_aud_pll_div_clk0_STOP - show clock root status, 1 means clock stopped
74821  */
74822 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_MASK)
74823 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_MASK (0xFFFFFFF0U)
74824 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_SHIFT (4U)
74825 /*! LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31 - reserved
74826  */
74827 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_MASK)
74828 /*! @} */
74829 
74830 
74831 /*!
74832  * @}
74833  */ /* end of group LPCG_LPCG_AUD_PLL_DIV_CLK0_Register_Masks */
74834 
74835 
74836 /* LPCG_LPCG_AUD_PLL_DIV_CLK0 - Peripheral instance base addresses */
74837 /** Peripheral ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0 base address */
74838 #define ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE     (0x59D20000u)
74839 /** Peripheral ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0 base pointer */
74840 #define ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0          ((LPCG_LPCG_AUD_PLL_DIV_CLK0_Type *)ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE)
74841 /** Array initializer of LPCG_LPCG_AUD_PLL_DIV_CLK0 peripheral base addresses */
74842 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_BASE_ADDRS    { ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE }
74843 /** Array initializer of LPCG_LPCG_AUD_PLL_DIV_CLK0 peripheral base pointers */
74844 #define LPCG_LPCG_AUD_PLL_DIV_CLK0_BASE_PTRS     { ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0 }
74845 
74846 /*!
74847  * @}
74848  */ /* end of group LPCG_LPCG_AUD_PLL_DIV_CLK0_Peripheral_Access_Layer */
74849 
74850 
74851 /* ----------------------------------------------------------------------------
74852    -- LPCG_LPCG_AUD_PLL_DIV_CLK1 Peripheral Access Layer
74853    ---------------------------------------------------------------------------- */
74854 
74855 /*!
74856  * @addtogroup LPCG_LPCG_AUD_PLL_DIV_CLK1_Peripheral_Access_Layer LPCG_LPCG_AUD_PLL_DIV_CLK1 Peripheral Access Layer
74857  * @{
74858  */
74859 
74860 /** LPCG_LPCG_AUD_PLL_DIV_CLK1 - Register Layout Typedef */
74861 typedef struct {
74862   __IO uint32_t LPCG_LPCG_AUD_PLL_DIV_CLK1_0;      /**< na, offset: 0x0 */
74863 } LPCG_LPCG_AUD_PLL_DIV_CLK1_Type;
74864 
74865 /* ----------------------------------------------------------------------------
74866    -- LPCG_LPCG_AUD_PLL_DIV_CLK1 Register Masks
74867    ---------------------------------------------------------------------------- */
74868 
74869 /*!
74870  * @addtogroup LPCG_LPCG_AUD_PLL_DIV_CLK1_Register_Masks LPCG_LPCG_AUD_PLL_DIV_CLK1 Register Masks
74871  * @{
74872  */
74873 
74874 /*! @name LPCG_LPCG_AUD_PLL_DIV_CLK1_0 - na */
74875 /*! @{ */
74876 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_MASK (0x1U)
74877 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_SHIFT (0U)
74878 /*! LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0 - reserved
74879  */
74880 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_MASK)
74881 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_MASK (0x2U)
74882 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_SHIFT (1U)
74883 /*! acm_aud_pll_div_clk1_SWEN - Software Enable
74884  *  0b0..Disable SW clock regardless of HWEN
74885  *  0b1..Enable SW clock gating
74886  */
74887 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_MASK)
74888 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_MASK (0x4U)
74889 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_SHIFT (2U)
74890 /*! LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2 - reserved
74891  */
74892 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_MASK)
74893 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_MASK (0x8U)
74894 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_SHIFT (3U)
74895 /*! acm_aud_pll_div_clk1_STOP - show clock root status, 1 means clock stopped
74896  */
74897 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_MASK)
74898 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_MASK (0xFFFFFFF0U)
74899 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_SHIFT (4U)
74900 /*! LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31 - reserved
74901  */
74902 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_MASK)
74903 /*! @} */
74904 
74905 
74906 /*!
74907  * @}
74908  */ /* end of group LPCG_LPCG_AUD_PLL_DIV_CLK1_Register_Masks */
74909 
74910 
74911 /* LPCG_LPCG_AUD_PLL_DIV_CLK1 - Peripheral instance base addresses */
74912 /** Peripheral ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1 base address */
74913 #define ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE     (0x59D30000u)
74914 /** Peripheral ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1 base pointer */
74915 #define ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1          ((LPCG_LPCG_AUD_PLL_DIV_CLK1_Type *)ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE)
74916 /** Array initializer of LPCG_LPCG_AUD_PLL_DIV_CLK1 peripheral base addresses */
74917 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_BASE_ADDRS    { ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE }
74918 /** Array initializer of LPCG_LPCG_AUD_PLL_DIV_CLK1 peripheral base pointers */
74919 #define LPCG_LPCG_AUD_PLL_DIV_CLK1_BASE_PTRS     { ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1 }
74920 
74921 /*!
74922  * @}
74923  */ /* end of group LPCG_LPCG_AUD_PLL_DIV_CLK1_Peripheral_Access_Layer */
74924 
74925 
74926 /* ----------------------------------------------------------------------------
74927    -- LPCG_LPCG_AUD_REC_CLK0 Peripheral Access Layer
74928    ---------------------------------------------------------------------------- */
74929 
74930 /*!
74931  * @addtogroup LPCG_LPCG_AUD_REC_CLK0_Peripheral_Access_Layer LPCG_LPCG_AUD_REC_CLK0 Peripheral Access Layer
74932  * @{
74933  */
74934 
74935 /** LPCG_LPCG_AUD_REC_CLK0 - Register Layout Typedef */
74936 typedef struct {
74937   __IO uint32_t LPCG_LPCG_AUD_REC_CLK0_0;          /**< na, offset: 0x0 */
74938 } LPCG_LPCG_AUD_REC_CLK0_Type;
74939 
74940 /* ----------------------------------------------------------------------------
74941    -- LPCG_LPCG_AUD_REC_CLK0 Register Masks
74942    ---------------------------------------------------------------------------- */
74943 
74944 /*!
74945  * @addtogroup LPCG_LPCG_AUD_REC_CLK0_Register_Masks LPCG_LPCG_AUD_REC_CLK0 Register Masks
74946  * @{
74947  */
74948 
74949 /*! @name LPCG_LPCG_AUD_REC_CLK0_0 - na */
74950 /*! @{ */
74951 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_MASK (0x1U)
74952 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_SHIFT (0U)
74953 /*! LPCG_lpcg_aud_rec_clk0_0_reserved_0_0 - reserved
74954  */
74955 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_MASK)
74956 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_MASK (0x2U)
74957 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_SHIFT (1U)
74958 /*! acm_aud_rec_clk0_SWEN - Software Enable
74959  *  0b0..Disable SW clock regardless of HWEN
74960  *  0b1..Enable SW clock gating
74961  */
74962 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_MASK)
74963 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_MASK (0x4U)
74964 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_SHIFT (2U)
74965 /*! LPCG_lpcg_aud_rec_clk0_0_reserved_2_2 - reserved
74966  */
74967 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_MASK)
74968 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_MASK (0x8U)
74969 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_SHIFT (3U)
74970 /*! acm_aud_rec_clk0_STOP - show clock root status, 1 means clock stopped
74971  */
74972 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_MASK)
74973 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_MASK (0xFFFFFFF0U)
74974 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_SHIFT (4U)
74975 /*! LPCG_lpcg_aud_rec_clk0_0_reserved_4_31 - reserved
74976  */
74977 #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_MASK)
74978 /*! @} */
74979 
74980 
74981 /*!
74982  * @}
74983  */ /* end of group LPCG_LPCG_AUD_REC_CLK0_Register_Masks */
74984 
74985 
74986 /* LPCG_LPCG_AUD_REC_CLK0 - Peripheral instance base addresses */
74987 /** Peripheral ADMA__LPCG_ACM_AUD_REC_CLK0 base address */
74988 #define ADMA__LPCG_ACM_AUD_REC_CLK0_BASE         (0x59D00000u)
74989 /** Peripheral ADMA__LPCG_ACM_AUD_REC_CLK0 base pointer */
74990 #define ADMA__LPCG_ACM_AUD_REC_CLK0              ((LPCG_LPCG_AUD_REC_CLK0_Type *)ADMA__LPCG_ACM_AUD_REC_CLK0_BASE)
74991 /** Array initializer of LPCG_LPCG_AUD_REC_CLK0 peripheral base addresses */
74992 #define LPCG_LPCG_AUD_REC_CLK0_BASE_ADDRS        { ADMA__LPCG_ACM_AUD_REC_CLK0_BASE }
74993 /** Array initializer of LPCG_LPCG_AUD_REC_CLK0 peripheral base pointers */
74994 #define LPCG_LPCG_AUD_REC_CLK0_BASE_PTRS         { ADMA__LPCG_ACM_AUD_REC_CLK0 }
74995 
74996 /*!
74997  * @}
74998  */ /* end of group LPCG_LPCG_AUD_REC_CLK0_Peripheral_Access_Layer */
74999 
75000 
75001 /* ----------------------------------------------------------------------------
75002    -- LPCG_LPCG_AUD_REC_CLK1 Peripheral Access Layer
75003    ---------------------------------------------------------------------------- */
75004 
75005 /*!
75006  * @addtogroup LPCG_LPCG_AUD_REC_CLK1_Peripheral_Access_Layer LPCG_LPCG_AUD_REC_CLK1 Peripheral Access Layer
75007  * @{
75008  */
75009 
75010 /** LPCG_LPCG_AUD_REC_CLK1 - Register Layout Typedef */
75011 typedef struct {
75012   __IO uint32_t LPCG_LPCG_AUD_REC_CLK1_0;          /**< na, offset: 0x0 */
75013 } LPCG_LPCG_AUD_REC_CLK1_Type;
75014 
75015 /* ----------------------------------------------------------------------------
75016    -- LPCG_LPCG_AUD_REC_CLK1 Register Masks
75017    ---------------------------------------------------------------------------- */
75018 
75019 /*!
75020  * @addtogroup LPCG_LPCG_AUD_REC_CLK1_Register_Masks LPCG_LPCG_AUD_REC_CLK1 Register Masks
75021  * @{
75022  */
75023 
75024 /*! @name LPCG_LPCG_AUD_REC_CLK1_0 - na */
75025 /*! @{ */
75026 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_MASK (0x1U)
75027 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_SHIFT (0U)
75028 /*! LPCG_lpcg_aud_rec_clk1_0_reserved_0_0 - reserved
75029  */
75030 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_MASK)
75031 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_MASK (0x2U)
75032 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_SHIFT (1U)
75033 /*! acm_aud_rec_clk1_SWEN - Software Enable
75034  *  0b0..Disable SW clock regardless of HWEN
75035  *  0b1..Enable SW clock gating
75036  */
75037 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_MASK)
75038 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_MASK (0x4U)
75039 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_SHIFT (2U)
75040 /*! LPCG_lpcg_aud_rec_clk1_0_reserved_2_2 - reserved
75041  */
75042 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_MASK)
75043 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_MASK (0x8U)
75044 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_SHIFT (3U)
75045 /*! acm_aud_rec_clk1_STOP - show clock root status, 1 means clock stopped
75046  */
75047 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_MASK)
75048 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_MASK (0xFFFFFFF0U)
75049 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_SHIFT (4U)
75050 /*! LPCG_lpcg_aud_rec_clk1_0_reserved_4_31 - reserved
75051  */
75052 #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_MASK)
75053 /*! @} */
75054 
75055 
75056 /*!
75057  * @}
75058  */ /* end of group LPCG_LPCG_AUD_REC_CLK1_Register_Masks */
75059 
75060 
75061 /* LPCG_LPCG_AUD_REC_CLK1 - Peripheral instance base addresses */
75062 /** Peripheral ADMA__LPCG_ACM_AUD_REC_CLK1 base address */
75063 #define ADMA__LPCG_ACM_AUD_REC_CLK1_BASE         (0x59D10000u)
75064 /** Peripheral ADMA__LPCG_ACM_AUD_REC_CLK1 base pointer */
75065 #define ADMA__LPCG_ACM_AUD_REC_CLK1              ((LPCG_LPCG_AUD_REC_CLK1_Type *)ADMA__LPCG_ACM_AUD_REC_CLK1_BASE)
75066 /** Array initializer of LPCG_LPCG_AUD_REC_CLK1 peripheral base addresses */
75067 #define LPCG_LPCG_AUD_REC_CLK1_BASE_ADDRS        { ADMA__LPCG_ACM_AUD_REC_CLK1_BASE }
75068 /** Array initializer of LPCG_LPCG_AUD_REC_CLK1 peripheral base pointers */
75069 #define LPCG_LPCG_AUD_REC_CLK1_BASE_PTRS         { ADMA__LPCG_ACM_AUD_REC_CLK1 }
75070 
75071 /*!
75072  * @}
75073  */ /* end of group LPCG_LPCG_AUD_REC_CLK1_Peripheral_Access_Layer */
75074 
75075 
75076 /* ----------------------------------------------------------------------------
75077    -- LPCG_LPCG_CAN0 Peripheral Access Layer
75078    ---------------------------------------------------------------------------- */
75079 
75080 /*!
75081  * @addtogroup LPCG_LPCG_CAN0_Peripheral_Access_Layer LPCG_LPCG_CAN0 Peripheral Access Layer
75082  * @{
75083  */
75084 
75085 /** LPCG_LPCG_CAN0 - Register Layout Typedef */
75086 typedef struct {
75087   __IO uint32_t LPCG_LPCG_CAN0_0;                  /**< na, offset: 0x0 */
75088 } LPCG_LPCG_CAN0_Type;
75089 
75090 /* ----------------------------------------------------------------------------
75091    -- LPCG_LPCG_CAN0 Register Masks
75092    ---------------------------------------------------------------------------- */
75093 
75094 /*!
75095  * @addtogroup LPCG_LPCG_CAN0_Register_Masks LPCG_LPCG_CAN0 Register Masks
75096  * @{
75097  */
75098 
75099 /*! @name LPCG_LPCG_CAN0_0 - na */
75100 /*! @{ */
75101 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_MASK (0x1U)
75102 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_SHIFT (0U)
75103 /*! can0_ipg_clk_pe_HWEN - Hardware Enable
75104  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75105  *  0b1..Enable HW automatic gating
75106  */
75107 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_MASK)
75108 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN_MASK (0x2U)
75109 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN_SHIFT (1U)
75110 /*! can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN - Software Enable
75111  *  0b0..Disable SW clock regardless of HWEN
75112  *  0b1..Enable SW clock gating
75113  */
75114 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN_MASK)
75115 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2_MASK (0x4U)
75116 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2_SHIFT (2U)
75117 /*! LPCG_lpcg_can0_0_reserved_2_2 - reserved
75118  */
75119 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2_MASK)
75120 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP_MASK (0x8U)
75121 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP_SHIFT (3U)
75122 /*! can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP - show clock root status, 1 means clock stopped
75123  */
75124 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP_MASK)
75125 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15_MASK (0xFFF0U)
75126 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15_SHIFT (4U)
75127 /*! LPCG_lpcg_can0_0_reserved_4_15 - reserved
75128  */
75129 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15_MASK)
75130 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_MASK (0x10000U)
75131 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_SHIFT (16U)
75132 /*! can0_ipg_clk_s_HWEN - Hardware Enable
75133  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75134  *  0b1..Enable HW automatic gating
75135  */
75136 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_MASK)
75137 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_MASK (0x20000U)
75138 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_SHIFT (17U)
75139 /*! can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN - Software Enable
75140  *  0b0..Disable SW clock regardless of HWEN
75141  *  0b1..Enable SW clock gating
75142  */
75143 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_MASK)
75144 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18_MASK (0x40000U)
75145 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18_SHIFT (18U)
75146 /*! LPCG_lpcg_can0_0_reserved_18_18 - reserved
75147  */
75148 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18_MASK)
75149 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_MASK (0x80000U)
75150 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_SHIFT (19U)
75151 /*! can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
75152  */
75153 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_MASK)
75154 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_MASK (0x100000U)
75155 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_SHIFT (20U)
75156 /*! can0_ipg_clk_chi_HWEN - Hardware Enable
75157  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75158  *  0b1..Enable HW automatic gating
75159  */
75160 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_MASK)
75161 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_MASK (0x200000U)
75162 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_SHIFT (21U)
75163 /*! can0_ipg_clk_chi_SWEN - Software Enable
75164  *  0b0..Disable SW clock regardless of HWEN
75165  *  0b1..Enable SW clock gating
75166  */
75167 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_MASK)
75168 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22_MASK (0x400000U)
75169 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22_SHIFT (22U)
75170 /*! LPCG_lpcg_can0_0_reserved_22_22 - reserved
75171  */
75172 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22_MASK)
75173 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_MASK (0x800000U)
75174 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_SHIFT (23U)
75175 /*! can0_ipg_clk_chi_STOP - show clock root status, 1 means clock stopped
75176  */
75177 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_MASK)
75178 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31_MASK (0xFF000000U)
75179 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31_SHIFT (24U)
75180 /*! LPCG_lpcg_can0_0_reserved_24_31 - reserved
75181  */
75182 #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31_MASK)
75183 /*! @} */
75184 
75185 
75186 /*!
75187  * @}
75188  */ /* end of group LPCG_LPCG_CAN0_Register_Masks */
75189 
75190 
75191 /* LPCG_LPCG_CAN0 - Peripheral instance base addresses */
75192 /** Peripheral ADMA__LPCG_CAN0_IPG_CLK base address */
75193 #define ADMA__LPCG_CAN0_IPG_CLK_BASE             (0x5ACD0000u)
75194 /** Peripheral ADMA__LPCG_CAN0_IPG_CLK base pointer */
75195 #define ADMA__LPCG_CAN0_IPG_CLK                  ((LPCG_LPCG_CAN0_Type *)ADMA__LPCG_CAN0_IPG_CLK_BASE)
75196 /** Array initializer of LPCG_LPCG_CAN0 peripheral base addresses */
75197 #define LPCG_LPCG_CAN0_BASE_ADDRS                { ADMA__LPCG_CAN0_IPG_CLK_BASE }
75198 /** Array initializer of LPCG_LPCG_CAN0 peripheral base pointers */
75199 #define LPCG_LPCG_CAN0_BASE_PTRS                 { ADMA__LPCG_CAN0_IPG_CLK }
75200 
75201 /*!
75202  * @}
75203  */ /* end of group LPCG_LPCG_CAN0_Peripheral_Access_Layer */
75204 
75205 
75206 /* ----------------------------------------------------------------------------
75207    -- LPCG_LPCG_CAN1 Peripheral Access Layer
75208    ---------------------------------------------------------------------------- */
75209 
75210 /*!
75211  * @addtogroup LPCG_LPCG_CAN1_Peripheral_Access_Layer LPCG_LPCG_CAN1 Peripheral Access Layer
75212  * @{
75213  */
75214 
75215 /** LPCG_LPCG_CAN1 - Register Layout Typedef */
75216 typedef struct {
75217   __IO uint32_t LPCG_LPCG_CAN1_0;                  /**< na, offset: 0x0 */
75218 } LPCG_LPCG_CAN1_Type;
75219 
75220 /* ----------------------------------------------------------------------------
75221    -- LPCG_LPCG_CAN1 Register Masks
75222    ---------------------------------------------------------------------------- */
75223 
75224 /*!
75225  * @addtogroup LPCG_LPCG_CAN1_Register_Masks LPCG_LPCG_CAN1 Register Masks
75226  * @{
75227  */
75228 
75229 /*! @name LPCG_LPCG_CAN1_0 - na */
75230 /*! @{ */
75231 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_MASK (0x1U)
75232 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_SHIFT (0U)
75233 /*! can1_ipg_clk_pe_HWEN - Hardware Enable
75234  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75235  *  0b1..Enable HW automatic gating
75236  */
75237 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_MASK)
75238 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN_MASK (0x2U)
75239 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN_SHIFT (1U)
75240 /*! can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN - Software Enable
75241  *  0b0..Disable SW clock regardless of HWEN
75242  *  0b1..Enable SW clock gating
75243  */
75244 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN_MASK)
75245 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2_MASK (0x4U)
75246 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2_SHIFT (2U)
75247 /*! LPCG_lpcg_can1_0_reserved_2_2 - reserved
75248  */
75249 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2_MASK)
75250 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP_MASK (0x8U)
75251 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP_SHIFT (3U)
75252 /*! can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP - show clock root status, 1 means clock stopped
75253  */
75254 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP_MASK)
75255 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15_MASK (0xFFF0U)
75256 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15_SHIFT (4U)
75257 /*! LPCG_lpcg_can1_0_reserved_4_15 - reserved
75258  */
75259 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15_MASK)
75260 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_MASK (0x10000U)
75261 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_SHIFT (16U)
75262 /*! can1_ipg_clk_s_HWEN - Hardware Enable
75263  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75264  *  0b1..Enable HW automatic gating
75265  */
75266 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_MASK)
75267 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_MASK (0x20000U)
75268 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_SHIFT (17U)
75269 /*! can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN - Software Enable
75270  *  0b0..Disable SW clock regardless of HWEN
75271  *  0b1..Enable SW clock gating
75272  */
75273 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_MASK)
75274 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18_MASK (0x40000U)
75275 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18_SHIFT (18U)
75276 /*! LPCG_lpcg_can1_0_reserved_18_18 - reserved
75277  */
75278 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18_MASK)
75279 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_MASK (0x80000U)
75280 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_SHIFT (19U)
75281 /*! can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
75282  */
75283 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_MASK)
75284 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_MASK (0x100000U)
75285 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_SHIFT (20U)
75286 /*! can1_ipg_clk_chi_HWEN - Hardware Enable
75287  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75288  *  0b1..Enable HW automatic gating
75289  */
75290 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_MASK)
75291 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_MASK (0x200000U)
75292 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_SHIFT (21U)
75293 /*! can1_ipg_clk_chi_SWEN - Software Enable
75294  *  0b0..Disable SW clock regardless of HWEN
75295  *  0b1..Enable SW clock gating
75296  */
75297 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_MASK)
75298 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22_MASK (0x400000U)
75299 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22_SHIFT (22U)
75300 /*! LPCG_lpcg_can1_0_reserved_22_22 - reserved
75301  */
75302 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22_MASK)
75303 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_MASK (0x800000U)
75304 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_SHIFT (23U)
75305 /*! can1_ipg_clk_chi_STOP - show clock root status, 1 means clock stopped
75306  */
75307 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_MASK)
75308 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31_MASK (0xFF000000U)
75309 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31_SHIFT (24U)
75310 /*! LPCG_lpcg_can1_0_reserved_24_31 - reserved
75311  */
75312 #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31_MASK)
75313 /*! @} */
75314 
75315 
75316 /*!
75317  * @}
75318  */ /* end of group LPCG_LPCG_CAN1_Register_Masks */
75319 
75320 
75321 /* LPCG_LPCG_CAN1 - Peripheral instance base addresses */
75322 /** Peripheral ADMA__LPCG_CAN1_IPG_CLK base address */
75323 #define ADMA__LPCG_CAN1_IPG_CLK_BASE             (0x5ACE0000u)
75324 /** Peripheral ADMA__LPCG_CAN1_IPG_CLK base pointer */
75325 #define ADMA__LPCG_CAN1_IPG_CLK                  ((LPCG_LPCG_CAN1_Type *)ADMA__LPCG_CAN1_IPG_CLK_BASE)
75326 /** Array initializer of LPCG_LPCG_CAN1 peripheral base addresses */
75327 #define LPCG_LPCG_CAN1_BASE_ADDRS                { ADMA__LPCG_CAN1_IPG_CLK_BASE }
75328 /** Array initializer of LPCG_LPCG_CAN1 peripheral base pointers */
75329 #define LPCG_LPCG_CAN1_BASE_PTRS                 { ADMA__LPCG_CAN1_IPG_CLK }
75330 
75331 /*!
75332  * @}
75333  */ /* end of group LPCG_LPCG_CAN1_Peripheral_Access_Layer */
75334 
75335 
75336 /* ----------------------------------------------------------------------------
75337    -- LPCG_LPCG_CAN2 Peripheral Access Layer
75338    ---------------------------------------------------------------------------- */
75339 
75340 /*!
75341  * @addtogroup LPCG_LPCG_CAN2_Peripheral_Access_Layer LPCG_LPCG_CAN2 Peripheral Access Layer
75342  * @{
75343  */
75344 
75345 /** LPCG_LPCG_CAN2 - Register Layout Typedef */
75346 typedef struct {
75347   __IO uint32_t LPCG_LPCG_CAN2_0;                  /**< na, offset: 0x0 */
75348 } LPCG_LPCG_CAN2_Type;
75349 
75350 /* ----------------------------------------------------------------------------
75351    -- LPCG_LPCG_CAN2 Register Masks
75352    ---------------------------------------------------------------------------- */
75353 
75354 /*!
75355  * @addtogroup LPCG_LPCG_CAN2_Register_Masks LPCG_LPCG_CAN2 Register Masks
75356  * @{
75357  */
75358 
75359 /*! @name LPCG_LPCG_CAN2_0 - na */
75360 /*! @{ */
75361 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_MASK (0x1U)
75362 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_SHIFT (0U)
75363 /*! can2_ipg_clk_pe_HWEN - Hardware Enable
75364  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75365  *  0b1..Enable HW automatic gating
75366  */
75367 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_MASK)
75368 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN_MASK (0x2U)
75369 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN_SHIFT (1U)
75370 /*! can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN - Software Enable
75371  *  0b0..Disable SW clock regardless of HWEN
75372  *  0b1..Enable SW clock gating
75373  */
75374 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN_MASK)
75375 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2_MASK (0x4U)
75376 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2_SHIFT (2U)
75377 /*! LPCG_lpcg_can2_0_reserved_2_2 - reserved
75378  */
75379 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2_MASK)
75380 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP_MASK (0x8U)
75381 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP_SHIFT (3U)
75382 /*! can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP - show clock root status, 1 means clock stopped
75383  */
75384 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP_MASK)
75385 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15_MASK (0xFFF0U)
75386 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15_SHIFT (4U)
75387 /*! LPCG_lpcg_can2_0_reserved_4_15 - reserved
75388  */
75389 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15_MASK)
75390 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_MASK (0x10000U)
75391 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_SHIFT (16U)
75392 /*! can2_ipg_clk_s_HWEN - Hardware Enable
75393  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75394  *  0b1..Enable HW automatic gating
75395  */
75396 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_MASK)
75397 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_MASK (0x20000U)
75398 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_SHIFT (17U)
75399 /*! can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN - Software Enable
75400  *  0b0..Disable SW clock regardless of HWEN
75401  *  0b1..Enable SW clock gating
75402  */
75403 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_MASK)
75404 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18_MASK (0x40000U)
75405 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18_SHIFT (18U)
75406 /*! LPCG_lpcg_can2_0_reserved_18_18 - reserved
75407  */
75408 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18_MASK)
75409 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_MASK (0x80000U)
75410 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_SHIFT (19U)
75411 /*! can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
75412  */
75413 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_MASK)
75414 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_MASK (0x100000U)
75415 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_SHIFT (20U)
75416 /*! can2_ipg_clk_chi_HWEN - Hardware Enable
75417  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75418  *  0b1..Enable HW automatic gating
75419  */
75420 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_MASK)
75421 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_MASK (0x200000U)
75422 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_SHIFT (21U)
75423 /*! can2_ipg_clk_chi_SWEN - Software Enable
75424  *  0b0..Disable SW clock regardless of HWEN
75425  *  0b1..Enable SW clock gating
75426  */
75427 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_MASK)
75428 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22_MASK (0x400000U)
75429 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22_SHIFT (22U)
75430 /*! LPCG_lpcg_can2_0_reserved_22_22 - reserved
75431  */
75432 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22_MASK)
75433 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_MASK (0x800000U)
75434 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_SHIFT (23U)
75435 /*! can2_ipg_clk_chi_STOP - show clock root status, 1 means clock stopped
75436  */
75437 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_MASK)
75438 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31_MASK (0xFF000000U)
75439 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31_SHIFT (24U)
75440 /*! LPCG_lpcg_can2_0_reserved_24_31 - reserved
75441  */
75442 #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31_MASK)
75443 /*! @} */
75444 
75445 
75446 /*!
75447  * @}
75448  */ /* end of group LPCG_LPCG_CAN2_Register_Masks */
75449 
75450 
75451 /* LPCG_LPCG_CAN2 - Peripheral instance base addresses */
75452 /** Peripheral ADMA__LPCG_CAN2_IPG_CLK base address */
75453 #define ADMA__LPCG_CAN2_IPG_CLK_BASE             (0x5ACF0000u)
75454 /** Peripheral ADMA__LPCG_CAN2_IPG_CLK base pointer */
75455 #define ADMA__LPCG_CAN2_IPG_CLK                  ((LPCG_LPCG_CAN2_Type *)ADMA__LPCG_CAN2_IPG_CLK_BASE)
75456 /** Array initializer of LPCG_LPCG_CAN2 peripheral base addresses */
75457 #define LPCG_LPCG_CAN2_BASE_ADDRS                { ADMA__LPCG_CAN2_IPG_CLK_BASE }
75458 /** Array initializer of LPCG_LPCG_CAN2 peripheral base pointers */
75459 #define LPCG_LPCG_CAN2_BASE_PTRS                 { ADMA__LPCG_CAN2_IPG_CLK }
75460 
75461 /*!
75462  * @}
75463  */ /* end of group LPCG_LPCG_CAN2_Peripheral_Access_Layer */
75464 
75465 
75466 /* ----------------------------------------------------------------------------
75467    -- LPCG_LPCG_EDMA0 Peripheral Access Layer
75468    ---------------------------------------------------------------------------- */
75469 
75470 /*!
75471  * @addtogroup LPCG_LPCG_EDMA0_Peripheral_Access_Layer LPCG_LPCG_EDMA0 Peripheral Access Layer
75472  * @{
75473  */
75474 
75475 /** LPCG_LPCG_EDMA0 - Register Layout Typedef */
75476 typedef struct {
75477   __IO uint32_t LPCG_LPCG_EDMA0_0;                 /**< na, offset: 0x0 */
75478 } LPCG_LPCG_EDMA0_Type;
75479 
75480 /* ----------------------------------------------------------------------------
75481    -- LPCG_LPCG_EDMA0 Register Masks
75482    ---------------------------------------------------------------------------- */
75483 
75484 /*!
75485  * @addtogroup LPCG_LPCG_EDMA0_Register_Masks LPCG_LPCG_EDMA0 Register Masks
75486  * @{
75487  */
75488 
75489 /*! @name LPCG_LPCG_EDMA0_0 - na */
75490 /*! @{ */
75491 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_MASK (0x1U)
75492 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_SHIFT (0U)
75493 /*! LPCG_lpcg_edma0_0_reserved_0_0 - reserved
75494  */
75495 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_MASK)
75496 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN_MASK (0x2U)
75497 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN_SHIFT (1U)
75498 /*! edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN - Software Enable
75499  *  0b0..Disable SW clock regardless of HWEN
75500  *  0b1..Enable SW clock gating
75501  */
75502 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN_MASK)
75503 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_MASK (0x4U)
75504 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_SHIFT (2U)
75505 /*! LPCG_lpcg_edma0_0_reserved_2_2 - reserved
75506  */
75507 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_MASK)
75508 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP_MASK (0x8U)
75509 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP_SHIFT (3U)
75510 /*! edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP - show clock root status, 1 means clock stopped
75511  */
75512 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP_MASK)
75513 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_MASK (0x1FFF0U)
75514 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_SHIFT (4U)
75515 /*! LPCG_lpcg_edma0_0_reserved_4_16 - reserved
75516  */
75517 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_MASK)
75518 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_MASK (0x20000U)
75519 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_SHIFT (17U)
75520 /*! edma0_ipg_clk_SWEN - Software Enable
75521  *  0b0..Disable SW clock regardless of HWEN
75522  *  0b1..Enable SW clock gating
75523  */
75524 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_MASK)
75525 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_MASK (0x40000U)
75526 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_SHIFT (18U)
75527 /*! LPCG_lpcg_edma0_0_reserved_18_18 - reserved
75528  */
75529 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_MASK)
75530 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_MASK (0x80000U)
75531 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_SHIFT (19U)
75532 /*! edma0_ipg_clk_STOP - show clock root status, 1 means clock stopped
75533  */
75534 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_MASK)
75535 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31_MASK (0xFFF00000U)
75536 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31_SHIFT (20U)
75537 /*! LPCG_lpcg_edma0_0_reserved_20_31 - reserved
75538  */
75539 #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31_MASK)
75540 /*! @} */
75541 
75542 
75543 /*!
75544  * @}
75545  */ /* end of group LPCG_LPCG_EDMA0_Register_Masks */
75546 
75547 
75548 /* LPCG_LPCG_EDMA0 - Peripheral instance base addresses */
75549 /** Peripheral ADMA__LPCG_EDMA0_HCLK base address */
75550 #define ADMA__LPCG_EDMA0_HCLK_BASE               (0x595F0000u)
75551 /** Peripheral ADMA__LPCG_EDMA0_HCLK base pointer */
75552 #define ADMA__LPCG_EDMA0_HCLK                    ((LPCG_LPCG_EDMA0_Type *)ADMA__LPCG_EDMA0_HCLK_BASE)
75553 /** Array initializer of LPCG_LPCG_EDMA0 peripheral base addresses */
75554 #define LPCG_LPCG_EDMA0_BASE_ADDRS               { ADMA__LPCG_EDMA0_HCLK_BASE }
75555 /** Array initializer of LPCG_LPCG_EDMA0 peripheral base pointers */
75556 #define LPCG_LPCG_EDMA0_BASE_PTRS                { ADMA__LPCG_EDMA0_HCLK }
75557 
75558 /*!
75559  * @}
75560  */ /* end of group LPCG_LPCG_EDMA0_Peripheral_Access_Layer */
75561 
75562 
75563 /* ----------------------------------------------------------------------------
75564    -- LPCG_LPCG_EDMA1 Peripheral Access Layer
75565    ---------------------------------------------------------------------------- */
75566 
75567 /*!
75568  * @addtogroup LPCG_LPCG_EDMA1_Peripheral_Access_Layer LPCG_LPCG_EDMA1 Peripheral Access Layer
75569  * @{
75570  */
75571 
75572 /** LPCG_LPCG_EDMA1 - Register Layout Typedef */
75573 typedef struct {
75574   __IO uint32_t LPCG_LPCG_EDMA1_0;                 /**< na, offset: 0x0 */
75575 } LPCG_LPCG_EDMA1_Type;
75576 
75577 /* ----------------------------------------------------------------------------
75578    -- LPCG_LPCG_EDMA1 Register Masks
75579    ---------------------------------------------------------------------------- */
75580 
75581 /*!
75582  * @addtogroup LPCG_LPCG_EDMA1_Register_Masks LPCG_LPCG_EDMA1 Register Masks
75583  * @{
75584  */
75585 
75586 /*! @name LPCG_LPCG_EDMA1_0 - na */
75587 /*! @{ */
75588 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_MASK (0x1U)
75589 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_SHIFT (0U)
75590 /*! LPCG_lpcg_edma1_0_reserved_0_0 - reserved
75591  */
75592 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_MASK)
75593 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN_MASK (0x2U)
75594 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN_SHIFT (1U)
75595 /*! edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN - Software Enable
75596  *  0b0..Disable SW clock regardless of HWEN
75597  *  0b1..Enable SW clock gating
75598  */
75599 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN_MASK)
75600 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_MASK (0x4U)
75601 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_SHIFT (2U)
75602 /*! LPCG_lpcg_edma1_0_reserved_2_2 - reserved
75603  */
75604 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_MASK)
75605 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP_MASK (0x8U)
75606 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP_SHIFT (3U)
75607 /*! edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP - show clock root status, 1 means clock stopped
75608  */
75609 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP_MASK)
75610 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_MASK (0x1FFF0U)
75611 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_SHIFT (4U)
75612 /*! LPCG_lpcg_edma1_0_reserved_4_16 - reserved
75613  */
75614 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_MASK)
75615 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_MASK (0x20000U)
75616 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_SHIFT (17U)
75617 /*! edma1_ipg_clk_SWEN - Software Enable
75618  *  0b0..Disable SW clock regardless of HWEN
75619  *  0b1..Enable SW clock gating
75620  */
75621 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_MASK)
75622 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_MASK (0x40000U)
75623 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_SHIFT (18U)
75624 /*! LPCG_lpcg_edma1_0_reserved_18_18 - reserved
75625  */
75626 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_MASK)
75627 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_MASK (0x80000U)
75628 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_SHIFT (19U)
75629 /*! edma1_ipg_clk_STOP - show clock root status, 1 means clock stopped
75630  */
75631 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_MASK)
75632 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31_MASK (0xFFF00000U)
75633 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31_SHIFT (20U)
75634 /*! LPCG_lpcg_edma1_0_reserved_20_31 - reserved
75635  */
75636 #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31_MASK)
75637 /*! @} */
75638 
75639 
75640 /*!
75641  * @}
75642  */ /* end of group LPCG_LPCG_EDMA1_Register_Masks */
75643 
75644 
75645 /* LPCG_LPCG_EDMA1 - Peripheral instance base addresses */
75646 /** Peripheral ADMA__LPCG_EDMA1_HCLK base address */
75647 #define ADMA__LPCG_EDMA1_HCLK_BASE               (0x59DF0000u)
75648 /** Peripheral ADMA__LPCG_EDMA1_HCLK base pointer */
75649 #define ADMA__LPCG_EDMA1_HCLK                    ((LPCG_LPCG_EDMA1_Type *)ADMA__LPCG_EDMA1_HCLK_BASE)
75650 /** Array initializer of LPCG_LPCG_EDMA1 peripheral base addresses */
75651 #define LPCG_LPCG_EDMA1_BASE_ADDRS               { ADMA__LPCG_EDMA1_HCLK_BASE }
75652 /** Array initializer of LPCG_LPCG_EDMA1 peripheral base pointers */
75653 #define LPCG_LPCG_EDMA1_BASE_PTRS                { ADMA__LPCG_EDMA1_HCLK }
75654 
75655 /*!
75656  * @}
75657  */ /* end of group LPCG_LPCG_EDMA1_Peripheral_Access_Layer */
75658 
75659 
75660 /* ----------------------------------------------------------------------------
75661    -- LPCG_LPCG_EDMA2 Peripheral Access Layer
75662    ---------------------------------------------------------------------------- */
75663 
75664 /*!
75665  * @addtogroup LPCG_LPCG_EDMA2_Peripheral_Access_Layer LPCG_LPCG_EDMA2 Peripheral Access Layer
75666  * @{
75667  */
75668 
75669 /** LPCG_LPCG_EDMA2 - Register Layout Typedef */
75670 typedef struct {
75671   __IO uint32_t LPCG_LPCG_EDMA2_0;                 /**< na, offset: 0x0 */
75672 } LPCG_LPCG_EDMA2_Type;
75673 
75674 /* ----------------------------------------------------------------------------
75675    -- LPCG_LPCG_EDMA2 Register Masks
75676    ---------------------------------------------------------------------------- */
75677 
75678 /*!
75679  * @addtogroup LPCG_LPCG_EDMA2_Register_Masks LPCG_LPCG_EDMA2 Register Masks
75680  * @{
75681  */
75682 
75683 /*! @name LPCG_LPCG_EDMA2_0 - na */
75684 /*! @{ */
75685 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0_MASK (0x1U)
75686 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0_SHIFT (0U)
75687 /*! LPCG_lpcg_edma2_0_reserved_0_0 - reserved
75688  */
75689 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0_MASK)
75690 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN_MASK (0x2U)
75691 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN_SHIFT (1U)
75692 /*! edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN - Software Enable
75693  *  0b0..Disable SW clock regardless of HWEN
75694  *  0b1..Enable SW clock gating
75695  */
75696 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN_MASK)
75697 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2_MASK (0x4U)
75698 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2_SHIFT (2U)
75699 /*! LPCG_lpcg_edma2_0_reserved_2_2 - reserved
75700  */
75701 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2_MASK)
75702 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP_MASK (0x8U)
75703 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP_SHIFT (3U)
75704 /*! edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP - show clock root status, 1 means clock stopped
75705  */
75706 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP_MASK)
75707 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16_MASK (0x1FFF0U)
75708 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16_SHIFT (4U)
75709 /*! LPCG_lpcg_edma2_0_reserved_4_16 - reserved
75710  */
75711 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16_MASK)
75712 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN_MASK (0x20000U)
75713 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN_SHIFT (17U)
75714 /*! edma2_ipg_clk_SWEN - Software Enable
75715  *  0b0..Disable SW clock regardless of HWEN
75716  *  0b1..Enable SW clock gating
75717  */
75718 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN_MASK)
75719 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18_MASK (0x40000U)
75720 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18_SHIFT (18U)
75721 /*! LPCG_lpcg_edma2_0_reserved_18_18 - reserved
75722  */
75723 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18_MASK)
75724 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP_MASK (0x80000U)
75725 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP_SHIFT (19U)
75726 /*! edma2_ipg_clk_STOP - show clock root status, 1 means clock stopped
75727  */
75728 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP_MASK)
75729 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31_MASK (0xFFF00000U)
75730 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31_SHIFT (20U)
75731 /*! LPCG_lpcg_edma2_0_reserved_20_31 - reserved
75732  */
75733 #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31_MASK)
75734 /*! @} */
75735 
75736 
75737 /*!
75738  * @}
75739  */ /* end of group LPCG_LPCG_EDMA2_Register_Masks */
75740 
75741 
75742 /* LPCG_LPCG_EDMA2 - Peripheral instance base addresses */
75743 /** Peripheral ADMA__LPCG_EDMA2_HCLK base address */
75744 #define ADMA__LPCG_EDMA2_HCLK_BASE               (0x5A5F0000u)
75745 /** Peripheral ADMA__LPCG_EDMA2_HCLK base pointer */
75746 #define ADMA__LPCG_EDMA2_HCLK                    ((LPCG_LPCG_EDMA2_Type *)ADMA__LPCG_EDMA2_HCLK_BASE)
75747 /** Array initializer of LPCG_LPCG_EDMA2 peripheral base addresses */
75748 #define LPCG_LPCG_EDMA2_BASE_ADDRS               { ADMA__LPCG_EDMA2_HCLK_BASE }
75749 /** Array initializer of LPCG_LPCG_EDMA2 peripheral base pointers */
75750 #define LPCG_LPCG_EDMA2_BASE_PTRS                { ADMA__LPCG_EDMA2_HCLK }
75751 
75752 /*!
75753  * @}
75754  */ /* end of group LPCG_LPCG_EDMA2_Peripheral_Access_Layer */
75755 
75756 
75757 /* ----------------------------------------------------------------------------
75758    -- LPCG_LPCG_EDMA3 Peripheral Access Layer
75759    ---------------------------------------------------------------------------- */
75760 
75761 /*!
75762  * @addtogroup LPCG_LPCG_EDMA3_Peripheral_Access_Layer LPCG_LPCG_EDMA3 Peripheral Access Layer
75763  * @{
75764  */
75765 
75766 /** LPCG_LPCG_EDMA3 - Register Layout Typedef */
75767 typedef struct {
75768   __IO uint32_t LPCG_LPCG_EDMA3_0;                 /**< na, offset: 0x0 */
75769 } LPCG_LPCG_EDMA3_Type;
75770 
75771 /* ----------------------------------------------------------------------------
75772    -- LPCG_LPCG_EDMA3 Register Masks
75773    ---------------------------------------------------------------------------- */
75774 
75775 /*!
75776  * @addtogroup LPCG_LPCG_EDMA3_Register_Masks LPCG_LPCG_EDMA3 Register Masks
75777  * @{
75778  */
75779 
75780 /*! @name LPCG_LPCG_EDMA3_0 - na */
75781 /*! @{ */
75782 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0_MASK (0x1U)
75783 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0_SHIFT (0U)
75784 /*! LPCG_lpcg_edma3_0_reserved_0_0 - reserved
75785  */
75786 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0_MASK)
75787 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN_MASK (0x2U)
75788 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN_SHIFT (1U)
75789 /*! edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN - Software Enable
75790  *  0b0..Disable SW clock regardless of HWEN
75791  *  0b1..Enable SW clock gating
75792  */
75793 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN_MASK)
75794 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2_MASK (0x4U)
75795 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2_SHIFT (2U)
75796 /*! LPCG_lpcg_edma3_0_reserved_2_2 - reserved
75797  */
75798 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2_MASK)
75799 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP_MASK (0x8U)
75800 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP_SHIFT (3U)
75801 /*! edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP - show clock root status, 1 means clock stopped
75802  */
75803 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP_MASK)
75804 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16_MASK (0x1FFF0U)
75805 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16_SHIFT (4U)
75806 /*! LPCG_lpcg_edma3_0_reserved_4_16 - reserved
75807  */
75808 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16_MASK)
75809 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN_MASK (0x20000U)
75810 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN_SHIFT (17U)
75811 /*! edma3_ipg_clk_SWEN - Software Enable
75812  *  0b0..Disable SW clock regardless of HWEN
75813  *  0b1..Enable SW clock gating
75814  */
75815 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN_MASK)
75816 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18_MASK (0x40000U)
75817 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18_SHIFT (18U)
75818 /*! LPCG_lpcg_edma3_0_reserved_18_18 - reserved
75819  */
75820 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18_MASK)
75821 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP_MASK (0x80000U)
75822 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP_SHIFT (19U)
75823 /*! edma3_ipg_clk_STOP - show clock root status, 1 means clock stopped
75824  */
75825 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP_MASK)
75826 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31_MASK (0xFFF00000U)
75827 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31_SHIFT (20U)
75828 /*! LPCG_lpcg_edma3_0_reserved_20_31 - reserved
75829  */
75830 #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31_MASK)
75831 /*! @} */
75832 
75833 
75834 /*!
75835  * @}
75836  */ /* end of group LPCG_LPCG_EDMA3_Register_Masks */
75837 
75838 
75839 /* LPCG_LPCG_EDMA3 - Peripheral instance base addresses */
75840 /** Peripheral ADMA__LPCG_EDMA3_HCLK base address */
75841 #define ADMA__LPCG_EDMA3_HCLK_BASE               (0x5ADF0000u)
75842 /** Peripheral ADMA__LPCG_EDMA3_HCLK base pointer */
75843 #define ADMA__LPCG_EDMA3_HCLK                    ((LPCG_LPCG_EDMA3_Type *)ADMA__LPCG_EDMA3_HCLK_BASE)
75844 /** Array initializer of LPCG_LPCG_EDMA3 peripheral base addresses */
75845 #define LPCG_LPCG_EDMA3_BASE_ADDRS               { ADMA__LPCG_EDMA3_HCLK_BASE }
75846 /** Array initializer of LPCG_LPCG_EDMA3 peripheral base pointers */
75847 #define LPCG_LPCG_EDMA3_BASE_PTRS                { ADMA__LPCG_EDMA3_HCLK }
75848 
75849 /*!
75850  * @}
75851  */ /* end of group LPCG_LPCG_EDMA3_Peripheral_Access_Layer */
75852 
75853 
75854 /* ----------------------------------------------------------------------------
75855    -- LPCG_LPCG_ESAI0 Peripheral Access Layer
75856    ---------------------------------------------------------------------------- */
75857 
75858 /*!
75859  * @addtogroup LPCG_LPCG_ESAI0_Peripheral_Access_Layer LPCG_LPCG_ESAI0 Peripheral Access Layer
75860  * @{
75861  */
75862 
75863 /** LPCG_LPCG_ESAI0 - Register Layout Typedef */
75864 typedef struct {
75865   __IO uint32_t LPCG_LPCG_ESAI0_0;                 /**< na, offset: 0x0 */
75866 } LPCG_LPCG_ESAI0_Type;
75867 
75868 /* ----------------------------------------------------------------------------
75869    -- LPCG_LPCG_ESAI0 Register Masks
75870    ---------------------------------------------------------------------------- */
75871 
75872 /*!
75873  * @addtogroup LPCG_LPCG_ESAI0_Register_Masks LPCG_LPCG_ESAI0 Register Masks
75874  * @{
75875  */
75876 
75877 /*! @name LPCG_LPCG_ESAI0_0 - na */
75878 /*! @{ */
75879 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0_MASK (0x1U)
75880 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0_SHIFT (0U)
75881 /*! LPCG_lpcg_esai0_0_reserved_0_0 - reserved
75882  */
75883 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0_MASK)
75884 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_MASK (0x2U)
75885 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_SHIFT (1U)
75886 /*! esai0_extal_clk_SWEN - Software Enable
75887  *  0b0..Disable SW clock regardless of HWEN
75888  *  0b1..Enable SW clock gating
75889  */
75890 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_MASK)
75891 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_MASK (0x4U)
75892 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_SHIFT (2U)
75893 /*! LPCG_lpcg_esai0_0_reserved_2_2 - reserved
75894  */
75895 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_MASK)
75896 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_MASK (0x8U)
75897 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_SHIFT (3U)
75898 /*! esai0_extal_clk_STOP - show clock root status, 1 means clock stopped
75899  */
75900 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_MASK)
75901 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15_MASK (0xFFF0U)
75902 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15_SHIFT (4U)
75903 /*! LPCG_lpcg_esai0_0_reserved_4_15 - reserved
75904  */
75905 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15_MASK)
75906 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN_MASK (0x10000U)
75907 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN_SHIFT (16U)
75908 /*! esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN - Hardware Enable
75909  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75910  *  0b1..Enable HW automatic gating
75911  */
75912 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN_MASK)
75913 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN_MASK (0x20000U)
75914 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN_SHIFT (17U)
75915 /*! esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN - Software Enable
75916  *  0b0..Disable SW clock regardless of HWEN
75917  *  0b1..Enable SW clock gating
75918  */
75919 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN_MASK)
75920 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_MASK (0x40000U)
75921 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_SHIFT (18U)
75922 /*! LPCG_lpcg_esai0_0_reserved_18_18 - reserved
75923  */
75924 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_MASK)
75925 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP_MASK (0x80000U)
75926 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP_SHIFT (19U)
75927 /*! esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP - show clock root status, 1 means clock stopped
75928  */
75929 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP_MASK)
75930 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_MASK (0xFFF00000U)
75931 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_SHIFT (20U)
75932 /*! LPCG_lpcg_esai0_0_reserved_20_31 - reserved
75933  */
75934 #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_MASK)
75935 /*! @} */
75936 
75937 
75938 /*!
75939  * @}
75940  */ /* end of group LPCG_LPCG_ESAI0_Register_Masks */
75941 
75942 
75943 /* LPCG_LPCG_ESAI0 - Peripheral instance base addresses */
75944 /** Peripheral ADMA__LPCG_ESAI0_EXTAL_CLK base address */
75945 #define ADMA__LPCG_ESAI0_EXTAL_CLK_BASE          (0x59410000u)
75946 /** Peripheral ADMA__LPCG_ESAI0_EXTAL_CLK base pointer */
75947 #define ADMA__LPCG_ESAI0_EXTAL_CLK               ((LPCG_LPCG_ESAI0_Type *)ADMA__LPCG_ESAI0_EXTAL_CLK_BASE)
75948 /** Array initializer of LPCG_LPCG_ESAI0 peripheral base addresses */
75949 #define LPCG_LPCG_ESAI0_BASE_ADDRS               { ADMA__LPCG_ESAI0_EXTAL_CLK_BASE }
75950 /** Array initializer of LPCG_LPCG_ESAI0 peripheral base pointers */
75951 #define LPCG_LPCG_ESAI0_BASE_PTRS                { ADMA__LPCG_ESAI0_EXTAL_CLK }
75952 
75953 /*!
75954  * @}
75955  */ /* end of group LPCG_LPCG_ESAI0_Peripheral_Access_Layer */
75956 
75957 
75958 /* ----------------------------------------------------------------------------
75959    -- LPCG_LPCG_FTM0 Peripheral Access Layer
75960    ---------------------------------------------------------------------------- */
75961 
75962 /*!
75963  * @addtogroup LPCG_LPCG_FTM0_Peripheral_Access_Layer LPCG_LPCG_FTM0 Peripheral Access Layer
75964  * @{
75965  */
75966 
75967 /** LPCG_LPCG_FTM0 - Register Layout Typedef */
75968 typedef struct {
75969   __IO uint32_t LPCG_LPCG_FTM0_0;                  /**< na, offset: 0x0 */
75970 } LPCG_LPCG_FTM0_Type;
75971 
75972 /* ----------------------------------------------------------------------------
75973    -- LPCG_LPCG_FTM0 Register Masks
75974    ---------------------------------------------------------------------------- */
75975 
75976 /*!
75977  * @addtogroup LPCG_LPCG_FTM0_Register_Masks LPCG_LPCG_FTM0 Register Masks
75978  * @{
75979  */
75980 
75981 /*! @name LPCG_LPCG_FTM0_0 - na */
75982 /*! @{ */
75983 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_MASK (0x1U)
75984 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_SHIFT (0U)
75985 /*! ftm0_ipp_ind_extclk_HWEN - Hardware Enable
75986  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
75987  *  0b1..Enable HW automatic gating
75988  */
75989 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_MASK)
75990 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_MASK (0x2U)
75991 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_SHIFT (1U)
75992 /*! ftm0_ipp_ind_extclk_SWEN - Software Enable
75993  *  0b0..Disable SW clock regardless of HWEN
75994  *  0b1..Enable SW clock gating
75995  */
75996 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_MASK)
75997 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2_MASK (0x4U)
75998 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2_SHIFT (2U)
75999 /*! LPCG_lpcg_ftm0_0_reserved_2_2 - reserved
76000  */
76001 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2_MASK)
76002 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_MASK (0x8U)
76003 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_SHIFT (3U)
76004 /*! ftm0_ipp_ind_extclk_STOP - show clock root status, 1 means clock stopped
76005  */
76006 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_MASK)
76007 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15_MASK (0xFFF0U)
76008 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15_SHIFT (4U)
76009 /*! LPCG_lpcg_ftm0_0_reserved_4_15 - reserved
76010  */
76011 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15_MASK)
76012 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_MASK (0x10000U)
76013 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_SHIFT (16U)
76014 /*! ftm0_ipg_clk_s_HWEN - Hardware Enable
76015  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76016  *  0b1..Enable HW automatic gating
76017  */
76018 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_MASK)
76019 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_MASK (0x20000U)
76020 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_SHIFT (17U)
76021 /*! ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN - Software Enable
76022  *  0b0..Disable SW clock regardless of HWEN
76023  *  0b1..Enable SW clock gating
76024  */
76025 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_MASK)
76026 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18_MASK (0x40000U)
76027 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18_SHIFT (18U)
76028 /*! LPCG_lpcg_ftm0_0_reserved_18_18 - reserved
76029  */
76030 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18_MASK)
76031 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_MASK (0x80000U)
76032 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_SHIFT (19U)
76033 /*! ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
76034  */
76035 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_MASK)
76036 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31_MASK (0xFFF00000U)
76037 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31_SHIFT (20U)
76038 /*! LPCG_lpcg_ftm0_0_reserved_20_31 - reserved
76039  */
76040 #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31_MASK)
76041 /*! @} */
76042 
76043 
76044 /*!
76045  * @}
76046  */ /* end of group LPCG_LPCG_FTM0_Register_Masks */
76047 
76048 
76049 /* LPCG_LPCG_FTM0 - Peripheral instance base addresses */
76050 /** Peripheral ADMA__LPCG_FTM0_IPG_CLK base address */
76051 #define ADMA__LPCG_FTM0_IPG_CLK_BASE             (0x5ACA0000u)
76052 /** Peripheral ADMA__LPCG_FTM0_IPG_CLK base pointer */
76053 #define ADMA__LPCG_FTM0_IPG_CLK                  ((LPCG_LPCG_FTM0_Type *)ADMA__LPCG_FTM0_IPG_CLK_BASE)
76054 /** Array initializer of LPCG_LPCG_FTM0 peripheral base addresses */
76055 #define LPCG_LPCG_FTM0_BASE_ADDRS                { ADMA__LPCG_FTM0_IPG_CLK_BASE }
76056 /** Array initializer of LPCG_LPCG_FTM0 peripheral base pointers */
76057 #define LPCG_LPCG_FTM0_BASE_PTRS                 { ADMA__LPCG_FTM0_IPG_CLK }
76058 
76059 /*!
76060  * @}
76061  */ /* end of group LPCG_LPCG_FTM0_Peripheral_Access_Layer */
76062 
76063 
76064 /* ----------------------------------------------------------------------------
76065    -- LPCG_LPCG_FTM1 Peripheral Access Layer
76066    ---------------------------------------------------------------------------- */
76067 
76068 /*!
76069  * @addtogroup LPCG_LPCG_FTM1_Peripheral_Access_Layer LPCG_LPCG_FTM1 Peripheral Access Layer
76070  * @{
76071  */
76072 
76073 /** LPCG_LPCG_FTM1 - Register Layout Typedef */
76074 typedef struct {
76075   __IO uint32_t LPCG_LPCG_FTM1_0;                  /**< na, offset: 0x0 */
76076 } LPCG_LPCG_FTM1_Type;
76077 
76078 /* ----------------------------------------------------------------------------
76079    -- LPCG_LPCG_FTM1 Register Masks
76080    ---------------------------------------------------------------------------- */
76081 
76082 /*!
76083  * @addtogroup LPCG_LPCG_FTM1_Register_Masks LPCG_LPCG_FTM1 Register Masks
76084  * @{
76085  */
76086 
76087 /*! @name LPCG_LPCG_FTM1_0 - na */
76088 /*! @{ */
76089 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_MASK (0x1U)
76090 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_SHIFT (0U)
76091 /*! ftm1_ipp_ind_extclk_HWEN - Hardware Enable
76092  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76093  *  0b1..Enable HW automatic gating
76094  */
76095 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_MASK)
76096 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_MASK (0x2U)
76097 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_SHIFT (1U)
76098 /*! ftm1_ipp_ind_extclk_SWEN - Software Enable
76099  *  0b0..Disable SW clock regardless of HWEN
76100  *  0b1..Enable SW clock gating
76101  */
76102 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_MASK)
76103 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2_MASK (0x4U)
76104 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2_SHIFT (2U)
76105 /*! LPCG_lpcg_ftm1_0_reserved_2_2 - reserved
76106  */
76107 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2_MASK)
76108 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_MASK (0x8U)
76109 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_SHIFT (3U)
76110 /*! ftm1_ipp_ind_extclk_STOP - show clock root status, 1 means clock stopped
76111  */
76112 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_MASK)
76113 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15_MASK (0xFFF0U)
76114 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15_SHIFT (4U)
76115 /*! LPCG_lpcg_ftm1_0_reserved_4_15 - reserved
76116  */
76117 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15_MASK)
76118 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_MASK (0x10000U)
76119 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_SHIFT (16U)
76120 /*! ftm1_ipg_clk_s_HWEN - Hardware Enable
76121  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76122  *  0b1..Enable HW automatic gating
76123  */
76124 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_MASK)
76125 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_MASK (0x20000U)
76126 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_SHIFT (17U)
76127 /*! ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN - Software Enable
76128  *  0b0..Disable SW clock regardless of HWEN
76129  *  0b1..Enable SW clock gating
76130  */
76131 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_MASK)
76132 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18_MASK (0x40000U)
76133 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18_SHIFT (18U)
76134 /*! LPCG_lpcg_ftm1_0_reserved_18_18 - reserved
76135  */
76136 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18_MASK)
76137 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_MASK (0x80000U)
76138 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_SHIFT (19U)
76139 /*! ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
76140  */
76141 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_MASK)
76142 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31_MASK (0xFFF00000U)
76143 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31_SHIFT (20U)
76144 /*! LPCG_lpcg_ftm1_0_reserved_20_31 - reserved
76145  */
76146 #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31_MASK)
76147 /*! @} */
76148 
76149 
76150 /*!
76151  * @}
76152  */ /* end of group LPCG_LPCG_FTM1_Register_Masks */
76153 
76154 
76155 /* LPCG_LPCG_FTM1 - Peripheral instance base addresses */
76156 /** Peripheral ADMA__LPCG_FTM1_IPG_CLK base address */
76157 #define ADMA__LPCG_FTM1_IPG_CLK_BASE             (0x5ACB0000u)
76158 /** Peripheral ADMA__LPCG_FTM1_IPG_CLK base pointer */
76159 #define ADMA__LPCG_FTM1_IPG_CLK                  ((LPCG_LPCG_FTM1_Type *)ADMA__LPCG_FTM1_IPG_CLK_BASE)
76160 /** Array initializer of LPCG_LPCG_FTM1 peripheral base addresses */
76161 #define LPCG_LPCG_FTM1_BASE_ADDRS                { ADMA__LPCG_FTM1_IPG_CLK_BASE }
76162 /** Array initializer of LPCG_LPCG_FTM1 peripheral base pointers */
76163 #define LPCG_LPCG_FTM1_BASE_PTRS                 { ADMA__LPCG_FTM1_IPG_CLK }
76164 
76165 /*!
76166  * @}
76167  */ /* end of group LPCG_LPCG_FTM1_Peripheral_Access_Layer */
76168 
76169 
76170 /* ----------------------------------------------------------------------------
76171    -- LPCG_LPCG_GPT0 Peripheral Access Layer
76172    ---------------------------------------------------------------------------- */
76173 
76174 /*!
76175  * @addtogroup LPCG_LPCG_GPT0_Peripheral_Access_Layer LPCG_LPCG_GPT0 Peripheral Access Layer
76176  * @{
76177  */
76178 
76179 /** LPCG_LPCG_GPT0 - Register Layout Typedef */
76180 typedef struct {
76181   __IO uint32_t LPCG_LPCG_GPT0_0;                  /**< na, offset: 0x0 */
76182 } LPCG_LPCG_GPT0_Type;
76183 
76184 /* ----------------------------------------------------------------------------
76185    -- LPCG_LPCG_GPT0 Register Masks
76186    ---------------------------------------------------------------------------- */
76187 
76188 /*!
76189  * @addtogroup LPCG_LPCG_GPT0_Register_Masks LPCG_LPCG_GPT0 Register Masks
76190  * @{
76191  */
76192 
76193 /*! @name LPCG_LPCG_GPT0_0 - na */
76194 /*! @{ */
76195 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0_MASK (0x1U)
76196 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0_SHIFT (0U)
76197 /*! LPCG_lpcg_gpt0_0_reserved_0_0 - reserved
76198  */
76199 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0_MASK)
76200 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_MASK (0x2U)
76201 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_SHIFT (1U)
76202 /*! gpt0_ipp_ind_clkin_SWEN - Software Enable
76203  *  0b0..Disable SW clock regardless of HWEN
76204  *  0b1..Enable SW clock gating
76205  */
76206 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_MASK)
76207 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_MASK (0x4U)
76208 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_SHIFT (2U)
76209 /*! LPCG_lpcg_gpt0_0_reserved_2_2 - reserved
76210  */
76211 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_MASK)
76212 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_MASK (0x8U)
76213 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_SHIFT (3U)
76214 /*! gpt0_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped
76215  */
76216 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_MASK)
76217 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15_MASK (0xFFF0U)
76218 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15_SHIFT (4U)
76219 /*! LPCG_lpcg_gpt0_0_reserved_4_15 - reserved
76220  */
76221 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15_MASK)
76222 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN_MASK (0x10000U)
76223 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN_SHIFT (16U)
76224 /*! gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN - Hardware Enable
76225  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76226  *  0b1..Enable HW automatic gating
76227  */
76228 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN_MASK)
76229 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN_MASK (0x20000U)
76230 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN_SHIFT (17U)
76231 /*! gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN - Software Enable
76232  *  0b0..Disable SW clock regardless of HWEN
76233  *  0b1..Enable SW clock gating
76234  */
76235 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN_MASK)
76236 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_MASK (0x40000U)
76237 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_SHIFT (18U)
76238 /*! LPCG_lpcg_gpt0_0_reserved_18_18 - reserved
76239  */
76240 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_MASK)
76241 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP_MASK (0x80000U)
76242 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP_SHIFT (19U)
76243 /*! gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
76244  */
76245 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP_MASK)
76246 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31_MASK (0xFFF00000U)
76247 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31_SHIFT (20U)
76248 /*! LPCG_lpcg_gpt0_0_reserved_20_31 - reserved
76249  */
76250 #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31_MASK)
76251 /*! @} */
76252 
76253 
76254 /*!
76255  * @}
76256  */ /* end of group LPCG_LPCG_GPT0_Register_Masks */
76257 
76258 
76259 /* LPCG_LPCG_GPT0 - Peripheral instance base addresses */
76260 /** Peripheral ADMA__LPCG_GPT0_IPG_CLK_24M base address */
76261 #define ADMA__LPCG_GPT0_IPG_CLK_24M_BASE         (0x594B0000u)
76262 /** Peripheral ADMA__LPCG_GPT0_IPG_CLK_24M base pointer */
76263 #define ADMA__LPCG_GPT0_IPG_CLK_24M              ((LPCG_LPCG_GPT0_Type *)ADMA__LPCG_GPT0_IPG_CLK_24M_BASE)
76264 /** Array initializer of LPCG_LPCG_GPT0 peripheral base addresses */
76265 #define LPCG_LPCG_GPT0_BASE_ADDRS                { ADMA__LPCG_GPT0_IPG_CLK_24M_BASE }
76266 /** Array initializer of LPCG_LPCG_GPT0 peripheral base pointers */
76267 #define LPCG_LPCG_GPT0_BASE_PTRS                 { ADMA__LPCG_GPT0_IPG_CLK_24M }
76268 
76269 /*!
76270  * @}
76271  */ /* end of group LPCG_LPCG_GPT0_Peripheral_Access_Layer */
76272 
76273 
76274 /* ----------------------------------------------------------------------------
76275    -- LPCG_LPCG_GPT1 Peripheral Access Layer
76276    ---------------------------------------------------------------------------- */
76277 
76278 /*!
76279  * @addtogroup LPCG_LPCG_GPT1_Peripheral_Access_Layer LPCG_LPCG_GPT1 Peripheral Access Layer
76280  * @{
76281  */
76282 
76283 /** LPCG_LPCG_GPT1 - Register Layout Typedef */
76284 typedef struct {
76285   __IO uint32_t LPCG_LPCG_GPT1_0;                  /**< na, offset: 0x0 */
76286 } LPCG_LPCG_GPT1_Type;
76287 
76288 /* ----------------------------------------------------------------------------
76289    -- LPCG_LPCG_GPT1 Register Masks
76290    ---------------------------------------------------------------------------- */
76291 
76292 /*!
76293  * @addtogroup LPCG_LPCG_GPT1_Register_Masks LPCG_LPCG_GPT1 Register Masks
76294  * @{
76295  */
76296 
76297 /*! @name LPCG_LPCG_GPT1_0 - na */
76298 /*! @{ */
76299 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0_MASK (0x1U)
76300 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0_SHIFT (0U)
76301 /*! LPCG_lpcg_gpt1_0_reserved_0_0 - reserved
76302  */
76303 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0_MASK)
76304 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_MASK (0x2U)
76305 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_SHIFT (1U)
76306 /*! gpt1_ipp_ind_clkin_SWEN - Software Enable
76307  *  0b0..Disable SW clock regardless of HWEN
76308  *  0b1..Enable SW clock gating
76309  */
76310 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_MASK)
76311 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_MASK (0x4U)
76312 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_SHIFT (2U)
76313 /*! LPCG_lpcg_gpt1_0_reserved_2_2 - reserved
76314  */
76315 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_MASK)
76316 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_MASK (0x8U)
76317 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_SHIFT (3U)
76318 /*! gpt1_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped
76319  */
76320 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_MASK)
76321 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15_MASK (0xFFF0U)
76322 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15_SHIFT (4U)
76323 /*! LPCG_lpcg_gpt1_0_reserved_4_15 - reserved
76324  */
76325 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15_MASK)
76326 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN_MASK (0x10000U)
76327 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN_SHIFT (16U)
76328 /*! gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN - Hardware Enable
76329  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76330  *  0b1..Enable HW automatic gating
76331  */
76332 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN_MASK)
76333 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN_MASK (0x20000U)
76334 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN_SHIFT (17U)
76335 /*! gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN - Software Enable
76336  *  0b0..Disable SW clock regardless of HWEN
76337  *  0b1..Enable SW clock gating
76338  */
76339 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN_MASK)
76340 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_MASK (0x40000U)
76341 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_SHIFT (18U)
76342 /*! LPCG_lpcg_gpt1_0_reserved_18_18 - reserved
76343  */
76344 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_MASK)
76345 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP_MASK (0x80000U)
76346 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP_SHIFT (19U)
76347 /*! gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
76348  */
76349 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP_MASK)
76350 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31_MASK (0xFFF00000U)
76351 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31_SHIFT (20U)
76352 /*! LPCG_lpcg_gpt1_0_reserved_20_31 - reserved
76353  */
76354 #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31_MASK)
76355 /*! @} */
76356 
76357 
76358 /*!
76359  * @}
76360  */ /* end of group LPCG_LPCG_GPT1_Register_Masks */
76361 
76362 
76363 /* LPCG_LPCG_GPT1 - Peripheral instance base addresses */
76364 /** Peripheral ADMA__LPCG_GPT1_IPG_CLK_24M base address */
76365 #define ADMA__LPCG_GPT1_IPG_CLK_24M_BASE         (0x594C0000u)
76366 /** Peripheral ADMA__LPCG_GPT1_IPG_CLK_24M base pointer */
76367 #define ADMA__LPCG_GPT1_IPG_CLK_24M              ((LPCG_LPCG_GPT1_Type *)ADMA__LPCG_GPT1_IPG_CLK_24M_BASE)
76368 /** Array initializer of LPCG_LPCG_GPT1 peripheral base addresses */
76369 #define LPCG_LPCG_GPT1_BASE_ADDRS                { ADMA__LPCG_GPT1_IPG_CLK_24M_BASE }
76370 /** Array initializer of LPCG_LPCG_GPT1 peripheral base pointers */
76371 #define LPCG_LPCG_GPT1_BASE_PTRS                 { ADMA__LPCG_GPT1_IPG_CLK_24M }
76372 
76373 /*!
76374  * @}
76375  */ /* end of group LPCG_LPCG_GPT1_Peripheral_Access_Layer */
76376 
76377 
76378 /* ----------------------------------------------------------------------------
76379    -- LPCG_LPCG_GPT2 Peripheral Access Layer
76380    ---------------------------------------------------------------------------- */
76381 
76382 /*!
76383  * @addtogroup LPCG_LPCG_GPT2_Peripheral_Access_Layer LPCG_LPCG_GPT2 Peripheral Access Layer
76384  * @{
76385  */
76386 
76387 /** LPCG_LPCG_GPT2 - Register Layout Typedef */
76388 typedef struct {
76389   __IO uint32_t LPCG_LPCG_GPT2_0;                  /**< na, offset: 0x0 */
76390 } LPCG_LPCG_GPT2_Type;
76391 
76392 /* ----------------------------------------------------------------------------
76393    -- LPCG_LPCG_GPT2 Register Masks
76394    ---------------------------------------------------------------------------- */
76395 
76396 /*!
76397  * @addtogroup LPCG_LPCG_GPT2_Register_Masks LPCG_LPCG_GPT2 Register Masks
76398  * @{
76399  */
76400 
76401 /*! @name LPCG_LPCG_GPT2_0 - na */
76402 /*! @{ */
76403 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0_MASK (0x1U)
76404 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0_SHIFT (0U)
76405 /*! LPCG_lpcg_gpt2_0_reserved_0_0 - reserved
76406  */
76407 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0_MASK)
76408 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_MASK (0x2U)
76409 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_SHIFT (1U)
76410 /*! gpt2_ipp_ind_clkin_SWEN - Software Enable
76411  *  0b0..Disable SW clock regardless of HWEN
76412  *  0b1..Enable SW clock gating
76413  */
76414 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_MASK)
76415 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_MASK (0x4U)
76416 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_SHIFT (2U)
76417 /*! LPCG_lpcg_gpt2_0_reserved_2_2 - reserved
76418  */
76419 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_MASK)
76420 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_MASK (0x8U)
76421 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_SHIFT (3U)
76422 /*! gpt2_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped
76423  */
76424 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_MASK)
76425 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15_MASK (0xFFF0U)
76426 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15_SHIFT (4U)
76427 /*! LPCG_lpcg_gpt2_0_reserved_4_15 - reserved
76428  */
76429 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15_MASK)
76430 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN_MASK (0x10000U)
76431 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN_SHIFT (16U)
76432 /*! gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN - Hardware Enable
76433  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76434  *  0b1..Enable HW automatic gating
76435  */
76436 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN_MASK)
76437 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN_MASK (0x20000U)
76438 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN_SHIFT (17U)
76439 /*! gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN - Software Enable
76440  *  0b0..Disable SW clock regardless of HWEN
76441  *  0b1..Enable SW clock gating
76442  */
76443 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN_MASK)
76444 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_MASK (0x40000U)
76445 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_SHIFT (18U)
76446 /*! LPCG_lpcg_gpt2_0_reserved_18_18 - reserved
76447  */
76448 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_MASK)
76449 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP_MASK (0x80000U)
76450 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP_SHIFT (19U)
76451 /*! gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
76452  */
76453 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP_MASK)
76454 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31_MASK (0xFFF00000U)
76455 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31_SHIFT (20U)
76456 /*! LPCG_lpcg_gpt2_0_reserved_20_31 - reserved
76457  */
76458 #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31_MASK)
76459 /*! @} */
76460 
76461 
76462 /*!
76463  * @}
76464  */ /* end of group LPCG_LPCG_GPT2_Register_Masks */
76465 
76466 
76467 /* LPCG_LPCG_GPT2 - Peripheral instance base addresses */
76468 /** Peripheral ADMA__LPCG_GPT2_IPG_CLK_24M base address */
76469 #define ADMA__LPCG_GPT2_IPG_CLK_24M_BASE         (0x594D0000u)
76470 /** Peripheral ADMA__LPCG_GPT2_IPG_CLK_24M base pointer */
76471 #define ADMA__LPCG_GPT2_IPG_CLK_24M              ((LPCG_LPCG_GPT2_Type *)ADMA__LPCG_GPT2_IPG_CLK_24M_BASE)
76472 /** Array initializer of LPCG_LPCG_GPT2 peripheral base addresses */
76473 #define LPCG_LPCG_GPT2_BASE_ADDRS                { ADMA__LPCG_GPT2_IPG_CLK_24M_BASE }
76474 /** Array initializer of LPCG_LPCG_GPT2 peripheral base pointers */
76475 #define LPCG_LPCG_GPT2_BASE_PTRS                 { ADMA__LPCG_GPT2_IPG_CLK_24M }
76476 
76477 /*!
76478  * @}
76479  */ /* end of group LPCG_LPCG_GPT2_Peripheral_Access_Layer */
76480 
76481 
76482 /* ----------------------------------------------------------------------------
76483    -- LPCG_LPCG_GPT3 Peripheral Access Layer
76484    ---------------------------------------------------------------------------- */
76485 
76486 /*!
76487  * @addtogroup LPCG_LPCG_GPT3_Peripheral_Access_Layer LPCG_LPCG_GPT3 Peripheral Access Layer
76488  * @{
76489  */
76490 
76491 /** LPCG_LPCG_GPT3 - Register Layout Typedef */
76492 typedef struct {
76493   __IO uint32_t LPCG_LPCG_GPT3_0;                  /**< na, offset: 0x0 */
76494 } LPCG_LPCG_GPT3_Type;
76495 
76496 /* ----------------------------------------------------------------------------
76497    -- LPCG_LPCG_GPT3 Register Masks
76498    ---------------------------------------------------------------------------- */
76499 
76500 /*!
76501  * @addtogroup LPCG_LPCG_GPT3_Register_Masks LPCG_LPCG_GPT3 Register Masks
76502  * @{
76503  */
76504 
76505 /*! @name LPCG_LPCG_GPT3_0 - na */
76506 /*! @{ */
76507 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0_MASK (0x1U)
76508 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0_SHIFT (0U)
76509 /*! LPCG_lpcg_gpt3_0_reserved_0_0 - reserved
76510  */
76511 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0_MASK)
76512 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_MASK (0x2U)
76513 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_SHIFT (1U)
76514 /*! gpt3_ipp_ind_clkin_SWEN - Software Enable
76515  *  0b0..Disable SW clock regardless of HWEN
76516  *  0b1..Enable SW clock gating
76517  */
76518 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_MASK)
76519 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_MASK (0x4U)
76520 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_SHIFT (2U)
76521 /*! LPCG_lpcg_gpt3_0_reserved_2_2 - reserved
76522  */
76523 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_MASK)
76524 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_MASK (0x8U)
76525 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_SHIFT (3U)
76526 /*! gpt3_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped
76527  */
76528 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_MASK)
76529 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15_MASK (0xFFF0U)
76530 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15_SHIFT (4U)
76531 /*! LPCG_lpcg_gpt3_0_reserved_4_15 - reserved
76532  */
76533 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15_MASK)
76534 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN_MASK (0x10000U)
76535 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN_SHIFT (16U)
76536 /*! gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN - Hardware Enable
76537  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76538  *  0b1..Enable HW automatic gating
76539  */
76540 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN_MASK)
76541 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN_MASK (0x20000U)
76542 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN_SHIFT (17U)
76543 /*! gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN - Software Enable
76544  *  0b0..Disable SW clock regardless of HWEN
76545  *  0b1..Enable SW clock gating
76546  */
76547 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN_MASK)
76548 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_MASK (0x40000U)
76549 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_SHIFT (18U)
76550 /*! LPCG_lpcg_gpt3_0_reserved_18_18 - reserved
76551  */
76552 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_MASK)
76553 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP_MASK (0x80000U)
76554 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP_SHIFT (19U)
76555 /*! gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
76556  */
76557 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP_MASK)
76558 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31_MASK (0xFFF00000U)
76559 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31_SHIFT (20U)
76560 /*! LPCG_lpcg_gpt3_0_reserved_20_31 - reserved
76561  */
76562 #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31_MASK)
76563 /*! @} */
76564 
76565 
76566 /*!
76567  * @}
76568  */ /* end of group LPCG_LPCG_GPT3_Register_Masks */
76569 
76570 
76571 /* LPCG_LPCG_GPT3 - Peripheral instance base addresses */
76572 /** Peripheral ADMA__LPCG_GPT3_IPG_CLK_24M base address */
76573 #define ADMA__LPCG_GPT3_IPG_CLK_24M_BASE         (0x594E0000u)
76574 /** Peripheral ADMA__LPCG_GPT3_IPG_CLK_24M base pointer */
76575 #define ADMA__LPCG_GPT3_IPG_CLK_24M              ((LPCG_LPCG_GPT3_Type *)ADMA__LPCG_GPT3_IPG_CLK_24M_BASE)
76576 /** Array initializer of LPCG_LPCG_GPT3 peripheral base addresses */
76577 #define LPCG_LPCG_GPT3_BASE_ADDRS                { ADMA__LPCG_GPT3_IPG_CLK_24M_BASE }
76578 /** Array initializer of LPCG_LPCG_GPT3 peripheral base pointers */
76579 #define LPCG_LPCG_GPT3_BASE_PTRS                 { ADMA__LPCG_GPT3_IPG_CLK_24M }
76580 
76581 /*!
76582  * @}
76583  */ /* end of group LPCG_LPCG_GPT3_Peripheral_Access_Layer */
76584 
76585 
76586 /* ----------------------------------------------------------------------------
76587    -- LPCG_LPCG_GPT4 Peripheral Access Layer
76588    ---------------------------------------------------------------------------- */
76589 
76590 /*!
76591  * @addtogroup LPCG_LPCG_GPT4_Peripheral_Access_Layer LPCG_LPCG_GPT4 Peripheral Access Layer
76592  * @{
76593  */
76594 
76595 /** LPCG_LPCG_GPT4 - Register Layout Typedef */
76596 typedef struct {
76597   __IO uint32_t LPCG_LPCG_GPT4_0;                  /**< na, offset: 0x0 */
76598 } LPCG_LPCG_GPT4_Type;
76599 
76600 /* ----------------------------------------------------------------------------
76601    -- LPCG_LPCG_GPT4 Register Masks
76602    ---------------------------------------------------------------------------- */
76603 
76604 /*!
76605  * @addtogroup LPCG_LPCG_GPT4_Register_Masks LPCG_LPCG_GPT4 Register Masks
76606  * @{
76607  */
76608 
76609 /*! @name LPCG_LPCG_GPT4_0 - na */
76610 /*! @{ */
76611 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0_MASK (0x1U)
76612 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0_SHIFT (0U)
76613 /*! LPCG_lpcg_gpt4_0_reserved_0_0 - reserved
76614  */
76615 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0_MASK)
76616 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_MASK (0x2U)
76617 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_SHIFT (1U)
76618 /*! gpt4_ipp_ind_clkin_SWEN - Software Enable
76619  *  0b0..Disable SW clock regardless of HWEN
76620  *  0b1..Enable SW clock gating
76621  */
76622 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_MASK)
76623 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_MASK (0x4U)
76624 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_SHIFT (2U)
76625 /*! LPCG_lpcg_gpt4_0_reserved_2_2 - reserved
76626  */
76627 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_MASK)
76628 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_MASK (0x8U)
76629 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_SHIFT (3U)
76630 /*! gpt4_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped
76631  */
76632 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_MASK)
76633 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15_MASK (0xFFF0U)
76634 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15_SHIFT (4U)
76635 /*! LPCG_lpcg_gpt4_0_reserved_4_15 - reserved
76636  */
76637 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15_MASK)
76638 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN_MASK (0x10000U)
76639 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN_SHIFT (16U)
76640 /*! gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN - Hardware Enable
76641  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76642  *  0b1..Enable HW automatic gating
76643  */
76644 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN_MASK)
76645 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN_MASK (0x20000U)
76646 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN_SHIFT (17U)
76647 /*! gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN - Software Enable
76648  *  0b0..Disable SW clock regardless of HWEN
76649  *  0b1..Enable SW clock gating
76650  */
76651 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN_MASK)
76652 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_MASK (0x40000U)
76653 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_SHIFT (18U)
76654 /*! LPCG_lpcg_gpt4_0_reserved_18_18 - reserved
76655  */
76656 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_MASK)
76657 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP_MASK (0x80000U)
76658 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP_SHIFT (19U)
76659 /*! gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
76660  */
76661 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP_MASK)
76662 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31_MASK (0xFFF00000U)
76663 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31_SHIFT (20U)
76664 /*! LPCG_lpcg_gpt4_0_reserved_20_31 - reserved
76665  */
76666 #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31_MASK)
76667 /*! @} */
76668 
76669 
76670 /*!
76671  * @}
76672  */ /* end of group LPCG_LPCG_GPT4_Register_Masks */
76673 
76674 
76675 /* LPCG_LPCG_GPT4 - Peripheral instance base addresses */
76676 /** Peripheral ADMA__LPCG_GPT4_IPG_CLK_24M base address */
76677 #define ADMA__LPCG_GPT4_IPG_CLK_24M_BASE         (0x594F0000u)
76678 /** Peripheral ADMA__LPCG_GPT4_IPG_CLK_24M base pointer */
76679 #define ADMA__LPCG_GPT4_IPG_CLK_24M              ((LPCG_LPCG_GPT4_Type *)ADMA__LPCG_GPT4_IPG_CLK_24M_BASE)
76680 /** Array initializer of LPCG_LPCG_GPT4 peripheral base addresses */
76681 #define LPCG_LPCG_GPT4_BASE_ADDRS                { ADMA__LPCG_GPT4_IPG_CLK_24M_BASE }
76682 /** Array initializer of LPCG_LPCG_GPT4 peripheral base pointers */
76683 #define LPCG_LPCG_GPT4_BASE_PTRS                 { ADMA__LPCG_GPT4_IPG_CLK_24M }
76684 
76685 /*!
76686  * @}
76687  */ /* end of group LPCG_LPCG_GPT4_Peripheral_Access_Layer */
76688 
76689 
76690 /* ----------------------------------------------------------------------------
76691    -- LPCG_LPCG_GPT5 Peripheral Access Layer
76692    ---------------------------------------------------------------------------- */
76693 
76694 /*!
76695  * @addtogroup LPCG_LPCG_GPT5_Peripheral_Access_Layer LPCG_LPCG_GPT5 Peripheral Access Layer
76696  * @{
76697  */
76698 
76699 /** LPCG_LPCG_GPT5 - Register Layout Typedef */
76700 typedef struct {
76701   __IO uint32_t LPCG_LPCG_GPT5_0;                  /**< na, offset: 0x0 */
76702 } LPCG_LPCG_GPT5_Type;
76703 
76704 /* ----------------------------------------------------------------------------
76705    -- LPCG_LPCG_GPT5 Register Masks
76706    ---------------------------------------------------------------------------- */
76707 
76708 /*!
76709  * @addtogroup LPCG_LPCG_GPT5_Register_Masks LPCG_LPCG_GPT5 Register Masks
76710  * @{
76711  */
76712 
76713 /*! @name LPCG_LPCG_GPT5_0 - na */
76714 /*! @{ */
76715 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0_MASK (0x1U)
76716 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0_SHIFT (0U)
76717 /*! LPCG_lpcg_gpt5_0_reserved_0_0 - reserved
76718  */
76719 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0_MASK)
76720 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_MASK (0x2U)
76721 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_SHIFT (1U)
76722 /*! gpt5_ipp_ind_clkin_SWEN - Software Enable
76723  *  0b0..Disable SW clock regardless of HWEN
76724  *  0b1..Enable SW clock gating
76725  */
76726 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_MASK)
76727 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_MASK (0x4U)
76728 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_SHIFT (2U)
76729 /*! LPCG_lpcg_gpt5_0_reserved_2_2 - reserved
76730  */
76731 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_MASK)
76732 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_MASK (0x8U)
76733 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_SHIFT (3U)
76734 /*! gpt5_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped
76735  */
76736 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_MASK)
76737 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15_MASK (0xFFF0U)
76738 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15_SHIFT (4U)
76739 /*! LPCG_lpcg_gpt5_0_reserved_4_15 - reserved
76740  */
76741 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15_MASK)
76742 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN_MASK (0x10000U)
76743 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN_SHIFT (16U)
76744 /*! gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN - Hardware Enable
76745  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76746  *  0b1..Enable HW automatic gating
76747  */
76748 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN_MASK)
76749 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN_MASK (0x20000U)
76750 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN_SHIFT (17U)
76751 /*! gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN - Software Enable
76752  *  0b0..Disable SW clock regardless of HWEN
76753  *  0b1..Enable SW clock gating
76754  */
76755 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN_MASK)
76756 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_MASK (0x40000U)
76757 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_SHIFT (18U)
76758 /*! LPCG_lpcg_gpt5_0_reserved_18_18 - reserved
76759  */
76760 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_MASK)
76761 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP_MASK (0x80000U)
76762 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP_SHIFT (19U)
76763 /*! gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
76764  */
76765 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP_MASK)
76766 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31_MASK (0xFFF00000U)
76767 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31_SHIFT (20U)
76768 /*! LPCG_lpcg_gpt5_0_reserved_20_31 - reserved
76769  */
76770 #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31_MASK)
76771 /*! @} */
76772 
76773 
76774 /*!
76775  * @}
76776  */ /* end of group LPCG_LPCG_GPT5_Register_Masks */
76777 
76778 
76779 /* LPCG_LPCG_GPT5 - Peripheral instance base addresses */
76780 /** Peripheral ADMA__LPCG_GPT5_IPG_CLK_24M base address */
76781 #define ADMA__LPCG_GPT5_IPG_CLK_24M_BASE         (0x59500000u)
76782 /** Peripheral ADMA__LPCG_GPT5_IPG_CLK_24M base pointer */
76783 #define ADMA__LPCG_GPT5_IPG_CLK_24M              ((LPCG_LPCG_GPT5_Type *)ADMA__LPCG_GPT5_IPG_CLK_24M_BASE)
76784 /** Array initializer of LPCG_LPCG_GPT5 peripheral base addresses */
76785 #define LPCG_LPCG_GPT5_BASE_ADDRS                { ADMA__LPCG_GPT5_IPG_CLK_24M_BASE }
76786 /** Array initializer of LPCG_LPCG_GPT5 peripheral base pointers */
76787 #define LPCG_LPCG_GPT5_BASE_PTRS                 { ADMA__LPCG_GPT5_IPG_CLK_24M }
76788 
76789 /*!
76790  * @}
76791  */ /* end of group LPCG_LPCG_GPT5_Peripheral_Access_Layer */
76792 
76793 
76794 /* ----------------------------------------------------------------------------
76795    -- LPCG_LPCG_HIFI Peripheral Access Layer
76796    ---------------------------------------------------------------------------- */
76797 
76798 /*!
76799  * @addtogroup LPCG_LPCG_HIFI_Peripheral_Access_Layer LPCG_LPCG_HIFI Peripheral Access Layer
76800  * @{
76801  */
76802 
76803 /** LPCG_LPCG_HIFI - Register Layout Typedef */
76804 typedef struct {
76805   __IO uint32_t LPCG_LPCG_HIFI_0;                  /**< na, offset: 0x0 */
76806 } LPCG_LPCG_HIFI_Type;
76807 
76808 /* ----------------------------------------------------------------------------
76809    -- LPCG_LPCG_HIFI Register Masks
76810    ---------------------------------------------------------------------------- */
76811 
76812 /*!
76813  * @addtogroup LPCG_LPCG_HIFI_Register_Masks LPCG_LPCG_HIFI Register Masks
76814  * @{
76815  */
76816 
76817 /*! @name LPCG_LPCG_HIFI_0 - na */
76818 /*! @{ */
76819 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16_MASK (0x1FFFFU)
76820 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16_SHIFT (0U)
76821 /*! LPCG_lpcg_hifi_0_reserved_0_16 - reserved
76822  */
76823 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16_MASK)
76824 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_MASK (0x20000U)
76825 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_SHIFT (17U)
76826 /*! adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN - Software Enable
76827  *  0b0..Disable SW clock regardless of HWEN
76828  *  0b1..Enable SW clock gating
76829  */
76830 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_MASK)
76831 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18_MASK (0x40000U)
76832 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18_SHIFT (18U)
76833 /*! LPCG_lpcg_hifi_0_reserved_18_18 - reserved
76834  */
76835 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18_MASK)
76836 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_MASK (0x80000U)
76837 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_SHIFT (19U)
76838 /*! adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP - show clock root status, 1 means clock stopped
76839  */
76840 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_MASK)
76841 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20_MASK (0x100000U)
76842 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20_SHIFT (20U)
76843 /*! LPCG_lpcg_hifi_0_reserved_20_20 - reserved
76844  */
76845 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20_MASK)
76846 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN_MASK (0x200000U)
76847 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN_SHIFT (21U)
76848 /*! hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN - Software Enable
76849  *  0b0..Disable SW clock regardless of HWEN
76850  *  0b1..Enable SW clock gating
76851  */
76852 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN_MASK)
76853 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22_MASK (0x400000U)
76854 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22_SHIFT (22U)
76855 /*! LPCG_lpcg_hifi_0_reserved_22_22 - reserved
76856  */
76857 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22_MASK)
76858 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP_MASK (0x800000U)
76859 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP_SHIFT (23U)
76860 /*! hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP - show clock root status, 1 means clock stopped
76861  */
76862 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP_MASK)
76863 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28_MASK (0x1F000000U)
76864 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28_SHIFT (24U)
76865 /*! LPCG_lpcg_hifi_0_reserved_24_28 - reserved
76866  */
76867 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28_MASK)
76868 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN_MASK (0x20000000U)
76869 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN_SHIFT (29U)
76870 /*! hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN - Software Enable
76871  *  0b0..Disable SW clock regardless of HWEN
76872  *  0b1..Enable SW clock gating
76873  */
76874 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN_MASK)
76875 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30_MASK (0x40000000U)
76876 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30_SHIFT (30U)
76877 /*! LPCG_lpcg_hifi_0_reserved_30_30 - reserved
76878  */
76879 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30_MASK)
76880 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP_MASK (0x80000000U)
76881 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP_SHIFT (31U)
76882 /*! hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP - show clock root status, 1 means clock stopped
76883  */
76884 #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP_MASK)
76885 /*! @} */
76886 
76887 
76888 /*!
76889  * @}
76890  */ /* end of group LPCG_LPCG_HIFI_Register_Masks */
76891 
76892 
76893 /* LPCG_LPCG_HIFI - Peripheral instance base addresses */
76894 /** Peripheral ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK base address */
76895 #define ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK_BASE    (0x59580000u)
76896 /** Peripheral ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK base pointer */
76897 #define ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK         ((LPCG_LPCG_HIFI_Type *)ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK_BASE)
76898 /** Array initializer of LPCG_LPCG_HIFI peripheral base addresses */
76899 #define LPCG_LPCG_HIFI_BASE_ADDRS                { ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK_BASE }
76900 /** Array initializer of LPCG_LPCG_HIFI peripheral base pointers */
76901 #define LPCG_LPCG_HIFI_BASE_PTRS                 { ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK }
76902 
76903 /*!
76904  * @}
76905  */ /* end of group LPCG_LPCG_HIFI_Peripheral_Access_Layer */
76906 
76907 
76908 /* ----------------------------------------------------------------------------
76909    -- LPCG_LPCG_I2C0 Peripheral Access Layer
76910    ---------------------------------------------------------------------------- */
76911 
76912 /*!
76913  * @addtogroup LPCG_LPCG_I2C0_Peripheral_Access_Layer LPCG_LPCG_I2C0 Peripheral Access Layer
76914  * @{
76915  */
76916 
76917 /** LPCG_LPCG_I2C0 - Register Layout Typedef */
76918 typedef struct {
76919   __IO uint32_t LPCG_LPCG_I2C0_0;                  /**< na, offset: 0x0 */
76920 } LPCG_LPCG_I2C0_Type;
76921 
76922 /* ----------------------------------------------------------------------------
76923    -- LPCG_LPCG_I2C0 Register Masks
76924    ---------------------------------------------------------------------------- */
76925 
76926 /*!
76927  * @addtogroup LPCG_LPCG_I2C0_Register_Masks LPCG_LPCG_I2C0 Register Masks
76928  * @{
76929  */
76930 
76931 /*! @name LPCG_LPCG_I2C0_0 - na */
76932 /*! @{ */
76933 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN_MASK (0x1U)
76934 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN_SHIFT (0U)
76935 /*! i2c0_lpi2c_div_clk_HWEN - Hardware Enable
76936  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76937  *  0b1..Enable HW automatic gating
76938  */
76939 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN_MASK)
76940 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN_MASK (0x2U)
76941 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN_SHIFT (1U)
76942 /*! i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN - Software Enable
76943  *  0b0..Disable SW clock regardless of HWEN
76944  *  0b1..Enable SW clock gating
76945  */
76946 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN_MASK)
76947 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2_MASK (0x4U)
76948 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2_SHIFT (2U)
76949 /*! LPCG_lpcg_i2c0_0_reserved_2_2 - reserved
76950  */
76951 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2_MASK)
76952 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP_MASK (0x8U)
76953 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP_SHIFT (3U)
76954 /*! i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
76955  */
76956 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP_MASK)
76957 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15_MASK (0xFFF0U)
76958 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15_SHIFT (4U)
76959 /*! LPCG_lpcg_i2c0_0_reserved_4_15 - reserved
76960  */
76961 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15_MASK)
76962 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN_MASK (0x10000U)
76963 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN_SHIFT (16U)
76964 /*! i2c0_ipg_clk_s_HWEN - Hardware Enable
76965  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
76966  *  0b1..Enable HW automatic gating
76967  */
76968 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN_MASK)
76969 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN_MASK (0x20000U)
76970 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN_SHIFT (17U)
76971 /*! i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN - Software Enable
76972  *  0b0..Disable SW clock regardless of HWEN
76973  *  0b1..Enable SW clock gating
76974  */
76975 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN_MASK)
76976 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18_MASK (0x40000U)
76977 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18_SHIFT (18U)
76978 /*! LPCG_lpcg_i2c0_0_reserved_18_18 - reserved
76979  */
76980 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18_MASK)
76981 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP_MASK (0x80000U)
76982 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP_SHIFT (19U)
76983 /*! i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
76984  */
76985 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP_MASK)
76986 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31_MASK (0xFFF00000U)
76987 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31_SHIFT (20U)
76988 /*! LPCG_lpcg_i2c0_0_reserved_20_31 - reserved
76989  */
76990 #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31_MASK)
76991 /*! @} */
76992 
76993 
76994 /*!
76995  * @}
76996  */ /* end of group LPCG_LPCG_I2C0_Register_Masks */
76997 
76998 
76999 /* LPCG_LPCG_I2C0 - Peripheral instance base addresses */
77000 /** Peripheral ADMA__LPCG_I2C0_IPG_CLK base address */
77001 #define ADMA__LPCG_I2C0_IPG_CLK_BASE             (0x5AC00000u)
77002 /** Peripheral ADMA__LPCG_I2C0_IPG_CLK base pointer */
77003 #define ADMA__LPCG_I2C0_IPG_CLK                  ((LPCG_LPCG_I2C0_Type *)ADMA__LPCG_I2C0_IPG_CLK_BASE)
77004 /** Array initializer of LPCG_LPCG_I2C0 peripheral base addresses */
77005 #define LPCG_LPCG_I2C0_BASE_ADDRS                { ADMA__LPCG_I2C0_IPG_CLK_BASE }
77006 /** Array initializer of LPCG_LPCG_I2C0 peripheral base pointers */
77007 #define LPCG_LPCG_I2C0_BASE_PTRS                 { ADMA__LPCG_I2C0_IPG_CLK }
77008 
77009 /*!
77010  * @}
77011  */ /* end of group LPCG_LPCG_I2C0_Peripheral_Access_Layer */
77012 
77013 
77014 /* ----------------------------------------------------------------------------
77015    -- LPCG_LPCG_I2C1 Peripheral Access Layer
77016    ---------------------------------------------------------------------------- */
77017 
77018 /*!
77019  * @addtogroup LPCG_LPCG_I2C1_Peripheral_Access_Layer LPCG_LPCG_I2C1 Peripheral Access Layer
77020  * @{
77021  */
77022 
77023 /** LPCG_LPCG_I2C1 - Register Layout Typedef */
77024 typedef struct {
77025   __IO uint32_t LPCG_LPCG_I2C1_0;                  /**< na, offset: 0x0 */
77026 } LPCG_LPCG_I2C1_Type;
77027 
77028 /* ----------------------------------------------------------------------------
77029    -- LPCG_LPCG_I2C1 Register Masks
77030    ---------------------------------------------------------------------------- */
77031 
77032 /*!
77033  * @addtogroup LPCG_LPCG_I2C1_Register_Masks LPCG_LPCG_I2C1 Register Masks
77034  * @{
77035  */
77036 
77037 /*! @name LPCG_LPCG_I2C1_0 - na */
77038 /*! @{ */
77039 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
77040 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
77041 /*! i2c1_lpi2c_div_clk_HWEN - Hardware Enable
77042  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
77043  *  0b1..Enable HW automatic gating
77044  */
77045 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN_MASK)
77046 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
77047 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
77048 /*! i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN - Software Enable
77049  *  0b0..Disable SW clock regardless of HWEN
77050  *  0b1..Enable SW clock gating
77051  */
77052 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN_MASK)
77053 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2_MASK (0x4U)
77054 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2_SHIFT (2U)
77055 /*! LPCG_lpcg_i2c1_0_reserved_2_2 - reserved
77056  */
77057 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2_MASK)
77058 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP_MASK (0x8U)
77059 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP_SHIFT (3U)
77060 /*! i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
77061  */
77062 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP_MASK)
77063 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15_MASK (0xFFF0U)
77064 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15_SHIFT (4U)
77065 /*! LPCG_lpcg_i2c1_0_reserved_4_15 - reserved
77066  */
77067 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15_MASK)
77068 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN_MASK (0x10000U)
77069 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN_SHIFT (16U)
77070 /*! i2c1_ipg_clk_s_HWEN - Hardware Enable
77071  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
77072  *  0b1..Enable HW automatic gating
77073  */
77074 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN_MASK)
77075 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN_MASK (0x20000U)
77076 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN_SHIFT (17U)
77077 /*! i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN - Software Enable
77078  *  0b0..Disable SW clock regardless of HWEN
77079  *  0b1..Enable SW clock gating
77080  */
77081 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN_MASK)
77082 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18_MASK (0x40000U)
77083 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18_SHIFT (18U)
77084 /*! LPCG_lpcg_i2c1_0_reserved_18_18 - reserved
77085  */
77086 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18_MASK)
77087 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP_MASK (0x80000U)
77088 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP_SHIFT (19U)
77089 /*! i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
77090  */
77091 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP_MASK)
77092 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31_MASK (0xFFF00000U)
77093 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31_SHIFT (20U)
77094 /*! LPCG_lpcg_i2c1_0_reserved_20_31 - reserved
77095  */
77096 #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31_MASK)
77097 /*! @} */
77098 
77099 
77100 /*!
77101  * @}
77102  */ /* end of group LPCG_LPCG_I2C1_Register_Masks */
77103 
77104 
77105 /* LPCG_LPCG_I2C1 - Peripheral instance base addresses */
77106 /** Peripheral ADMA__LPCG_I2C1_IPG_CLK base address */
77107 #define ADMA__LPCG_I2C1_IPG_CLK_BASE             (0x5AC10000u)
77108 /** Peripheral ADMA__LPCG_I2C1_IPG_CLK base pointer */
77109 #define ADMA__LPCG_I2C1_IPG_CLK                  ((LPCG_LPCG_I2C1_Type *)ADMA__LPCG_I2C1_IPG_CLK_BASE)
77110 /** Array initializer of LPCG_LPCG_I2C1 peripheral base addresses */
77111 #define LPCG_LPCG_I2C1_BASE_ADDRS                { ADMA__LPCG_I2C1_IPG_CLK_BASE }
77112 /** Array initializer of LPCG_LPCG_I2C1 peripheral base pointers */
77113 #define LPCG_LPCG_I2C1_BASE_PTRS                 { ADMA__LPCG_I2C1_IPG_CLK }
77114 
77115 /*!
77116  * @}
77117  */ /* end of group LPCG_LPCG_I2C1_Peripheral_Access_Layer */
77118 
77119 
77120 /* ----------------------------------------------------------------------------
77121    -- LPCG_LPCG_I2C2 Peripheral Access Layer
77122    ---------------------------------------------------------------------------- */
77123 
77124 /*!
77125  * @addtogroup LPCG_LPCG_I2C2_Peripheral_Access_Layer LPCG_LPCG_I2C2 Peripheral Access Layer
77126  * @{
77127  */
77128 
77129 /** LPCG_LPCG_I2C2 - Register Layout Typedef */
77130 typedef struct {
77131   __IO uint32_t LPCG_LPCG_I2C2_0;                  /**< na, offset: 0x0 */
77132 } LPCG_LPCG_I2C2_Type;
77133 
77134 /* ----------------------------------------------------------------------------
77135    -- LPCG_LPCG_I2C2 Register Masks
77136    ---------------------------------------------------------------------------- */
77137 
77138 /*!
77139  * @addtogroup LPCG_LPCG_I2C2_Register_Masks LPCG_LPCG_I2C2 Register Masks
77140  * @{
77141  */
77142 
77143 /*! @name LPCG_LPCG_I2C2_0 - na */
77144 /*! @{ */
77145 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN_MASK (0x1U)
77146 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN_SHIFT (0U)
77147 /*! i2c2_lpi2c_div_clk_HWEN - Hardware Enable
77148  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
77149  *  0b1..Enable HW automatic gating
77150  */
77151 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN_MASK)
77152 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN_MASK (0x2U)
77153 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN_SHIFT (1U)
77154 /*! i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN - Software Enable
77155  *  0b0..Disable SW clock regardless of HWEN
77156  *  0b1..Enable SW clock gating
77157  */
77158 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN_MASK)
77159 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2_MASK (0x4U)
77160 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2_SHIFT (2U)
77161 /*! LPCG_lpcg_i2c2_0_reserved_2_2 - reserved
77162  */
77163 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2_MASK)
77164 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP_MASK (0x8U)
77165 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP_SHIFT (3U)
77166 /*! i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
77167  */
77168 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP_MASK)
77169 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15_MASK (0xFFF0U)
77170 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15_SHIFT (4U)
77171 /*! LPCG_lpcg_i2c2_0_reserved_4_15 - reserved
77172  */
77173 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15_MASK)
77174 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN_MASK (0x10000U)
77175 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN_SHIFT (16U)
77176 /*! i2c2_ipg_clk_s_HWEN - Hardware Enable
77177  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
77178  *  0b1..Enable HW automatic gating
77179  */
77180 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN_MASK)
77181 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN_MASK (0x20000U)
77182 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN_SHIFT (17U)
77183 /*! i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN - Software Enable
77184  *  0b0..Disable SW clock regardless of HWEN
77185  *  0b1..Enable SW clock gating
77186  */
77187 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN_MASK)
77188 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18_MASK (0x40000U)
77189 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18_SHIFT (18U)
77190 /*! LPCG_lpcg_i2c2_0_reserved_18_18 - reserved
77191  */
77192 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18_MASK)
77193 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP_MASK (0x80000U)
77194 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP_SHIFT (19U)
77195 /*! i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
77196  */
77197 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP_MASK)
77198 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31_MASK (0xFFF00000U)
77199 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31_SHIFT (20U)
77200 /*! LPCG_lpcg_i2c2_0_reserved_20_31 - reserved
77201  */
77202 #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31_MASK)
77203 /*! @} */
77204 
77205 
77206 /*!
77207  * @}
77208  */ /* end of group LPCG_LPCG_I2C2_Register_Masks */
77209 
77210 
77211 /* LPCG_LPCG_I2C2 - Peripheral instance base addresses */
77212 /** Peripheral ADMA__LPCG_I2C2_IPG_CLK base address */
77213 #define ADMA__LPCG_I2C2_IPG_CLK_BASE             (0x5AC20000u)
77214 /** Peripheral ADMA__LPCG_I2C2_IPG_CLK base pointer */
77215 #define ADMA__LPCG_I2C2_IPG_CLK                  ((LPCG_LPCG_I2C2_Type *)ADMA__LPCG_I2C2_IPG_CLK_BASE)
77216 /** Array initializer of LPCG_LPCG_I2C2 peripheral base addresses */
77217 #define LPCG_LPCG_I2C2_BASE_ADDRS                { ADMA__LPCG_I2C2_IPG_CLK_BASE }
77218 /** Array initializer of LPCG_LPCG_I2C2 peripheral base pointers */
77219 #define LPCG_LPCG_I2C2_BASE_PTRS                 { ADMA__LPCG_I2C2_IPG_CLK }
77220 
77221 /*!
77222  * @}
77223  */ /* end of group LPCG_LPCG_I2C2_Peripheral_Access_Layer */
77224 
77225 
77226 /* ----------------------------------------------------------------------------
77227    -- LPCG_LPCG_I2C3 Peripheral Access Layer
77228    ---------------------------------------------------------------------------- */
77229 
77230 /*!
77231  * @addtogroup LPCG_LPCG_I2C3_Peripheral_Access_Layer LPCG_LPCG_I2C3 Peripheral Access Layer
77232  * @{
77233  */
77234 
77235 /** LPCG_LPCG_I2C3 - Register Layout Typedef */
77236 typedef struct {
77237   __IO uint32_t LPCG_LPCG_I2C3_0;                  /**< na, offset: 0x0 */
77238 } LPCG_LPCG_I2C3_Type;
77239 
77240 /* ----------------------------------------------------------------------------
77241    -- LPCG_LPCG_I2C3 Register Masks
77242    ---------------------------------------------------------------------------- */
77243 
77244 /*!
77245  * @addtogroup LPCG_LPCG_I2C3_Register_Masks LPCG_LPCG_I2C3 Register Masks
77246  * @{
77247  */
77248 
77249 /*! @name LPCG_LPCG_I2C3_0 - na */
77250 /*! @{ */
77251 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN_MASK (0x1U)
77252 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN_SHIFT (0U)
77253 /*! i2c3_lpi2c_div_clk_HWEN - Hardware Enable
77254  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
77255  *  0b1..Enable HW automatic gating
77256  */
77257 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN_MASK)
77258 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN_MASK (0x2U)
77259 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN_SHIFT (1U)
77260 /*! i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN - Software Enable
77261  *  0b0..Disable SW clock regardless of HWEN
77262  *  0b1..Enable SW clock gating
77263  */
77264 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN_MASK)
77265 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2_MASK (0x4U)
77266 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2_SHIFT (2U)
77267 /*! LPCG_lpcg_i2c3_0_reserved_2_2 - reserved
77268  */
77269 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2_MASK)
77270 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP_MASK (0x8U)
77271 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP_SHIFT (3U)
77272 /*! i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
77273  */
77274 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP_MASK)
77275 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15_MASK (0xFFF0U)
77276 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15_SHIFT (4U)
77277 /*! LPCG_lpcg_i2c3_0_reserved_4_15 - reserved
77278  */
77279 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15_MASK)
77280 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN_MASK (0x10000U)
77281 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN_SHIFT (16U)
77282 /*! i2c3_ipg_clk_s_HWEN - Hardware Enable
77283  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
77284  *  0b1..Enable HW automatic gating
77285  */
77286 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN_MASK)
77287 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN_MASK (0x20000U)
77288 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN_SHIFT (17U)
77289 /*! i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN - Software Enable
77290  *  0b0..Disable SW clock regardless of HWEN
77291  *  0b1..Enable SW clock gating
77292  */
77293 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN_MASK)
77294 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18_MASK (0x40000U)
77295 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18_SHIFT (18U)
77296 /*! LPCG_lpcg_i2c3_0_reserved_18_18 - reserved
77297  */
77298 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18_MASK)
77299 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP_MASK (0x80000U)
77300 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP_SHIFT (19U)
77301 /*! i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
77302  */
77303 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP_MASK)
77304 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31_MASK (0xFFF00000U)
77305 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31_SHIFT (20U)
77306 /*! LPCG_lpcg_i2c3_0_reserved_20_31 - reserved
77307  */
77308 #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31_MASK)
77309 /*! @} */
77310 
77311 
77312 /*!
77313  * @}
77314  */ /* end of group LPCG_LPCG_I2C3_Register_Masks */
77315 
77316 
77317 /* LPCG_LPCG_I2C3 - Peripheral instance base addresses */
77318 /** Peripheral ADMA__LPCG_I2C3_IPG_CLK base address */
77319 #define ADMA__LPCG_I2C3_IPG_CLK_BASE             (0x5AC30000u)
77320 /** Peripheral ADMA__LPCG_I2C3_IPG_CLK base pointer */
77321 #define ADMA__LPCG_I2C3_IPG_CLK                  ((LPCG_LPCG_I2C3_Type *)ADMA__LPCG_I2C3_IPG_CLK_BASE)
77322 /** Array initializer of LPCG_LPCG_I2C3 peripheral base addresses */
77323 #define LPCG_LPCG_I2C3_BASE_ADDRS                { ADMA__LPCG_I2C3_IPG_CLK_BASE }
77324 /** Array initializer of LPCG_LPCG_I2C3 peripheral base pointers */
77325 #define LPCG_LPCG_I2C3_BASE_PTRS                 { ADMA__LPCG_I2C3_IPG_CLK }
77326 
77327 /*!
77328  * @}
77329  */ /* end of group LPCG_LPCG_I2C3_Peripheral_Access_Layer */
77330 
77331 
77332 /* ----------------------------------------------------------------------------
77333    -- LPCG_LPCG_IRQ Peripheral Access Layer
77334    ---------------------------------------------------------------------------- */
77335 
77336 /*!
77337  * @addtogroup LPCG_LPCG_IRQ_Peripheral_Access_Layer LPCG_LPCG_IRQ Peripheral Access Layer
77338  * @{
77339  */
77340 
77341 /** LPCG_LPCG_IRQ - Register Layout Typedef */
77342 typedef struct {
77343   __IO uint32_t LPCG_LPCG_IRQ_0;                   /**< na, offset: 0x0 */
77344 } LPCG_LPCG_IRQ_Type;
77345 
77346 /* ----------------------------------------------------------------------------
77347    -- LPCG_LPCG_IRQ Register Masks
77348    ---------------------------------------------------------------------------- */
77349 
77350 /*!
77351  * @addtogroup LPCG_LPCG_IRQ_Register_Masks LPCG_LPCG_IRQ Register Masks
77352  * @{
77353  */
77354 
77355 /*! @name LPCG_LPCG_IRQ_0 - na */
77356 /*! @{ */
77357 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0_MASK (0x1U)
77358 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0_SHIFT (0U)
77359 /*! LPCG_lpcg_irq_0_reserved_0_0 - reserved
77360  */
77361 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0_MASK)
77362 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN_MASK (0x2U)
77363 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN_SHIFT (1U)
77364 /*! adb_m0_aclk_SWEN - Software Enable
77365  *  0b0..Disable SW clock regardless of HWEN
77366  *  0b1..Enable SW clock gating
77367  */
77368 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN_MASK)
77369 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2_MASK (0x4U)
77370 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2_SHIFT (2U)
77371 /*! LPCG_lpcg_irq_0_reserved_2_2 - reserved
77372  */
77373 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2_MASK)
77374 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP_MASK (0x8U)
77375 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP_SHIFT (3U)
77376 /*! adb_m0_aclk_STOP - show clock root status, 1 means clock stopped
77377  */
77378 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP_MASK)
77379 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4_MASK (0x10U)
77380 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4_SHIFT (4U)
77381 /*! LPCG_lpcg_irq_0_reserved_4_4 - reserved
77382  */
77383 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4_MASK)
77384 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN_MASK (0x20U)
77385 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN_SHIFT (5U)
77386 /*! adb_s0_aclk_SWEN - Software Enable
77387  *  0b0..Disable SW clock regardless of HWEN
77388  *  0b1..Enable SW clock gating
77389  */
77390 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN_MASK)
77391 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6_MASK (0x40U)
77392 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6_SHIFT (6U)
77393 /*! LPCG_lpcg_irq_0_reserved_6_6 - reserved
77394  */
77395 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6_MASK)
77396 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP_MASK (0x80U)
77397 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP_SHIFT (7U)
77398 /*! adb_s0_aclk_STOP - show clock root status, 1 means clock stopped
77399  */
77400 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP_MASK)
77401 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15_MASK (0xFF00U)
77402 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15_SHIFT (8U)
77403 /*! LPCG_lpcg_irq_0_reserved_8_15 - reserved
77404  */
77405 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15_MASK)
77406 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN_MASK (0x10000U)
77407 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN_SHIFT (16U)
77408 /*! irqstr_ipg_clk_HWEN - Hardware Enable
77409  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
77410  *  0b1..Enable HW automatic gating
77411  */
77412 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN_MASK)
77413 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN_MASK (0x20000U)
77414 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN_SHIFT (17U)
77415 /*! irqstr_ipg_clk_SWEN - Software Enable
77416  *  0b0..Disable SW clock regardless of HWEN
77417  *  0b1..Enable SW clock gating
77418  */
77419 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN_MASK)
77420 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18_MASK (0x40000U)
77421 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18_SHIFT (18U)
77422 /*! LPCG_lpcg_irq_0_reserved_18_18 - reserved
77423  */
77424 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18_MASK)
77425 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP_MASK (0x80000U)
77426 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP_SHIFT (19U)
77427 /*! irqstr_ipg_clk_STOP - show clock root status, 1 means clock stopped
77428  */
77429 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP_MASK)
77430 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20_MASK (0x100000U)
77431 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20_SHIFT (20U)
77432 /*! LPCG_lpcg_irq_0_reserved_20_20 - reserved
77433  */
77434 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20_MASK)
77435 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN_MASK (0x200000U)
77436 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN_SHIFT (21U)
77437 /*! gic_clk_SWEN - Software Enable
77438  *  0b0..Disable SW clock regardless of HWEN
77439  *  0b1..Enable SW clock gating
77440  */
77441 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN_MASK)
77442 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22_MASK (0x400000U)
77443 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22_SHIFT (22U)
77444 /*! LPCG_lpcg_irq_0_reserved_22_22 - reserved
77445  */
77446 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22_MASK)
77447 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP_MASK (0x800000U)
77448 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP_SHIFT (23U)
77449 /*! gic_clk_STOP - show clock root status, 1 means clock stopped
77450  */
77451 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP_MASK)
77452 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31_MASK (0xFF000000U)
77453 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31_SHIFT (24U)
77454 /*! LPCG_lpcg_irq_0_reserved_24_31 - reserved
77455  */
77456 #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31_MASK)
77457 /*! @} */
77458 
77459 
77460 /*!
77461  * @}
77462  */ /* end of group LPCG_LPCG_IRQ_Register_Masks */
77463 
77464 
77465 /* LPCG_LPCG_IRQ - Peripheral instance base addresses */
77466 /** Peripheral ADMA__LPCG_GIC_CLK base address */
77467 #define ADMA__LPCG_GIC_CLK_BASE                  (0xD10F0000u)
77468 /** Peripheral ADMA__LPCG_GIC_CLK base pointer */
77469 #define ADMA__LPCG_GIC_CLK                       ((LPCG_LPCG_IRQ_Type *)ADMA__LPCG_GIC_CLK_BASE)
77470 /** Array initializer of LPCG_LPCG_IRQ peripheral base addresses */
77471 #define LPCG_LPCG_IRQ_BASE_ADDRS                 { ADMA__LPCG_GIC_CLK_BASE }
77472 /** Array initializer of LPCG_LPCG_IRQ peripheral base pointers */
77473 #define LPCG_LPCG_IRQ_BASE_PTRS                  { ADMA__LPCG_GIC_CLK }
77474 
77475 /*!
77476  * @}
77477  */ /* end of group LPCG_LPCG_IRQ_Peripheral_Access_Layer */
77478 
77479 
77480 /* ----------------------------------------------------------------------------
77481    -- LPCG_LPCG_LCDIF Peripheral Access Layer
77482    ---------------------------------------------------------------------------- */
77483 
77484 /*!
77485  * @addtogroup LPCG_LPCG_LCDIF_Peripheral_Access_Layer LPCG_LPCG_LCDIF Peripheral Access Layer
77486  * @{
77487  */
77488 
77489 /** LPCG_LPCG_LCDIF - Register Layout Typedef */
77490 typedef struct {
77491   __IO uint32_t LPCG_LPCG_LCDIF_0;                 /**< na, offset: 0x0 */
77492 } LPCG_LPCG_LCDIF_Type;
77493 
77494 /* ----------------------------------------------------------------------------
77495    -- LPCG_LPCG_LCDIF Register Masks
77496    ---------------------------------------------------------------------------- */
77497 
77498 /*!
77499  * @addtogroup LPCG_LPCG_LCDIF_Register_Masks LPCG_LPCG_LCDIF Register Masks
77500  * @{
77501  */
77502 
77503 /*! @name LPCG_LPCG_LCDIF_0 - na */
77504 /*! @{ */
77505 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0_MASK (0x1U)
77506 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0_SHIFT (0U)
77507 /*! LPCG_lpcg_lcdif_0_reserved_0_0 - reserved
77508  */
77509 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0_MASK)
77510 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN_MASK (0x2U)
77511 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN_SHIFT (1U)
77512 /*! lcdif_pix_clk_SWEN - Software Enable
77513  *  0b0..Disable SW clock regardless of HWEN
77514  *  0b1..Enable SW clock gating
77515  */
77516 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN_MASK)
77517 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2_MASK (0x4U)
77518 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2_SHIFT (2U)
77519 /*! LPCG_lpcg_lcdif_0_reserved_2_2 - reserved
77520  */
77521 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2_MASK)
77522 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP_MASK (0x8U)
77523 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP_SHIFT (3U)
77524 /*! lcdif_pix_clk_STOP - show clock root status, 1 means clock stopped
77525  */
77526 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP_MASK)
77527 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16_MASK (0x1FFF0U)
77528 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16_SHIFT (4U)
77529 /*! LPCG_lpcg_lcdif_0_reserved_4_16 - reserved
77530  */
77531 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16_MASK)
77532 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN_MASK (0x20000U)
77533 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN_SHIFT (17U)
77534 /*! lcdif_apb_clk_SWEN - Software Enable
77535  *  0b0..Disable SW clock regardless of HWEN
77536  *  0b1..Enable SW clock gating
77537  */
77538 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN_MASK)
77539 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18_MASK (0x40000U)
77540 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18_SHIFT (18U)
77541 /*! LPCG_lpcg_lcdif_0_reserved_18_18 - reserved
77542  */
77543 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18_MASK)
77544 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP_MASK (0x80000U)
77545 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP_SHIFT (19U)
77546 /*! lcdif_apb_clk_STOP - show clock root status, 1 means clock stopped
77547  */
77548 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP_MASK)
77549 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31_MASK (0xFFF00000U)
77550 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31_SHIFT (20U)
77551 /*! LPCG_lpcg_lcdif_0_reserved_20_31 - reserved
77552  */
77553 #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31_MASK)
77554 /*! @} */
77555 
77556 
77557 /*!
77558  * @}
77559  */ /* end of group LPCG_LPCG_LCDIF_Register_Masks */
77560 
77561 
77562 /* LPCG_LPCG_LCDIF - Peripheral instance base addresses */
77563 /** Peripheral ADMA__LPCG_LCDIF_APB_CLK base address */
77564 #define ADMA__LPCG_LCDIF_APB_CLK_BASE            (0x5A580000u)
77565 /** Peripheral ADMA__LPCG_LCDIF_APB_CLK base pointer */
77566 #define ADMA__LPCG_LCDIF_APB_CLK                 ((LPCG_LPCG_LCDIF_Type *)ADMA__LPCG_LCDIF_APB_CLK_BASE)
77567 /** Array initializer of LPCG_LPCG_LCDIF peripheral base addresses */
77568 #define LPCG_LPCG_LCDIF_BASE_ADDRS               { ADMA__LPCG_LCDIF_APB_CLK_BASE }
77569 /** Array initializer of LPCG_LPCG_LCDIF peripheral base pointers */
77570 #define LPCG_LPCG_LCDIF_BASE_PTRS                { ADMA__LPCG_LCDIF_APB_CLK }
77571 
77572 /*!
77573  * @}
77574  */ /* end of group LPCG_LPCG_LCDIF_Peripheral_Access_Layer */
77575 
77576 
77577 /* ----------------------------------------------------------------------------
77578    -- LPCG_LPCG_LCDIF_MUX Peripheral Access Layer
77579    ---------------------------------------------------------------------------- */
77580 
77581 /*!
77582  * @addtogroup LPCG_LPCG_LCDIF_MUX_Peripheral_Access_Layer LPCG_LPCG_LCDIF_MUX Peripheral Access Layer
77583  * @{
77584  */
77585 
77586 /** LPCG_LPCG_LCDIF_MUX - Register Layout Typedef */
77587 typedef struct {
77588   __IO uint32_t LPCG_LPCG_LCDIF_MUX_0;             /**< na, offset: 0x0 */
77589 } LPCG_LPCG_LCDIF_MUX_Type;
77590 
77591 /* ----------------------------------------------------------------------------
77592    -- LPCG_LPCG_LCDIF_MUX Register Masks
77593    ---------------------------------------------------------------------------- */
77594 
77595 /*!
77596  * @addtogroup LPCG_LPCG_LCDIF_MUX_Register_Masks LPCG_LPCG_LCDIF_MUX Register Masks
77597  * @{
77598  */
77599 
77600 /*! @name LPCG_LPCG_LCDIF_MUX_0 - na */
77601 /*! @{ */
77602 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0_MASK (0x1U)
77603 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0_SHIFT (0U)
77604 /*! LPCG_lpcg_lcdif_mux_0_reserved_0_0 - reserved
77605  */
77606 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0_MASK)
77607 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN_MASK (0x2U)
77608 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN_SHIFT (1U)
77609 /*! pixel_link_slv_ingress_clk_SWEN - Software Enable
77610  *  0b0..Disable SW clock regardless of HWEN
77611  *  0b1..Enable SW clock gating
77612  */
77613 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN_MASK)
77614 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2_MASK (0x4U)
77615 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2_SHIFT (2U)
77616 /*! LPCG_lpcg_lcdif_mux_0_reserved_2_2 - reserved
77617  */
77618 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2_MASK)
77619 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP_MASK (0x8U)
77620 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP_SHIFT (3U)
77621 /*! pixel_link_slv_ingress_clk_STOP - show clock root status, 1 means clock stopped
77622  */
77623 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP_MASK)
77624 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4_MASK (0x10U)
77625 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4_SHIFT (4U)
77626 /*! LPCG_lpcg_lcdif_mux_0_reserved_4_4 - reserved
77627  */
77628 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4_MASK)
77629 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN_MASK (0x20U)
77630 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN_SHIFT (5U)
77631 /*! lcdif_mux_pixel_link_slv_clk_SWEN - Software Enable
77632  *  0b0..Disable SW clock regardless of HWEN
77633  *  0b1..Enable SW clock gating
77634  */
77635 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN_MASK)
77636 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6_MASK (0x40U)
77637 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6_SHIFT (6U)
77638 /*! LPCG_lpcg_lcdif_mux_0_reserved_6_6 - reserved
77639  */
77640 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6_MASK)
77641 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP_MASK (0x80U)
77642 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP_SHIFT (7U)
77643 /*! lcdif_mux_pixel_link_slv_clk_STOP - show clock root status, 1 means clock stopped
77644  */
77645 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP_MASK)
77646 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16_MASK (0x1FF00U)
77647 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16_SHIFT (8U)
77648 /*! LPCG_lpcg_lcdif_mux_0_reserved_8_16 - reserved
77649  */
77650 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16_MASK)
77651 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN_MASK (0x20000U)
77652 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN_SHIFT (17U)
77653 /*! lcdif_mux_regs_ipg_clk_SWEN - Software Enable
77654  *  0b0..Disable SW clock regardless of HWEN
77655  *  0b1..Enable SW clock gating
77656  */
77657 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN_MASK)
77658 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18_MASK (0x40000U)
77659 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18_SHIFT (18U)
77660 /*! LPCG_lpcg_lcdif_mux_0_reserved_18_18 - reserved
77661  */
77662 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18_MASK)
77663 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP_MASK (0x80000U)
77664 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP_SHIFT (19U)
77665 /*! lcdif_mux_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped
77666  */
77667 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP_MASK)
77668 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31_MASK (0xFFF00000U)
77669 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31_SHIFT (20U)
77670 /*! LPCG_lpcg_lcdif_mux_0_reserved_20_31 - reserved
77671  */
77672 #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31_MASK)
77673 /*! @} */
77674 
77675 
77676 /*!
77677  * @}
77678  */ /* end of group LPCG_LPCG_LCDIF_MUX_Register_Masks */
77679 
77680 
77681 /* LPCG_LPCG_LCDIF_MUX - Peripheral instance base addresses */
77682 /** Peripheral ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK base address */
77683 #define ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK_BASE (0x5A570000u)
77684 /** Peripheral ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK base pointer */
77685 #define ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK    ((LPCG_LPCG_LCDIF_MUX_Type *)ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK_BASE)
77686 /** Array initializer of LPCG_LPCG_LCDIF_MUX peripheral base addresses */
77687 #define LPCG_LPCG_LCDIF_MUX_BASE_ADDRS           { ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK_BASE }
77688 /** Array initializer of LPCG_LPCG_LCDIF_MUX peripheral base pointers */
77689 #define LPCG_LPCG_LCDIF_MUX_BASE_PTRS            { ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK }
77690 
77691 /*!
77692  * @}
77693  */ /* end of group LPCG_LPCG_LCDIF_MUX_Peripheral_Access_Layer */
77694 
77695 
77696 /* ----------------------------------------------------------------------------
77697    -- LPCG_LPCG_MCLKOUT0 Peripheral Access Layer
77698    ---------------------------------------------------------------------------- */
77699 
77700 /*!
77701  * @addtogroup LPCG_LPCG_MCLKOUT0_Peripheral_Access_Layer LPCG_LPCG_MCLKOUT0 Peripheral Access Layer
77702  * @{
77703  */
77704 
77705 /** LPCG_LPCG_MCLKOUT0 - Register Layout Typedef */
77706 typedef struct {
77707   __IO uint32_t LPCG_LPCG_MCLKOUT0_0;              /**< na, offset: 0x0 */
77708 } LPCG_LPCG_MCLKOUT0_Type;
77709 
77710 /* ----------------------------------------------------------------------------
77711    -- LPCG_LPCG_MCLKOUT0 Register Masks
77712    ---------------------------------------------------------------------------- */
77713 
77714 /*!
77715  * @addtogroup LPCG_LPCG_MCLKOUT0_Register_Masks LPCG_LPCG_MCLKOUT0 Register Masks
77716  * @{
77717  */
77718 
77719 /*! @name LPCG_LPCG_MCLKOUT0_0 - na */
77720 /*! @{ */
77721 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_MASK (0x1U)
77722 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_SHIFT (0U)
77723 /*! LPCG_lpcg_mclkout0_0_reserved_0_0 - reserved
77724  */
77725 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_MASK)
77726 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_MASK (0x2U)
77727 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_SHIFT (1U)
77728 /*! mclkout0_SWEN - Software Enable
77729  *  0b0..Disable SW clock regardless of HWEN
77730  *  0b1..Enable SW clock gating
77731  */
77732 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_MASK)
77733 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_MASK (0x4U)
77734 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_SHIFT (2U)
77735 /*! LPCG_lpcg_mclkout0_0_reserved_2_2 - reserved
77736  */
77737 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_MASK)
77738 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_MASK (0x8U)
77739 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_SHIFT (3U)
77740 /*! mclkout0_STOP - show clock root status, 1 means clock stopped
77741  */
77742 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_MASK)
77743 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_MASK (0xFFFFFFF0U)
77744 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_SHIFT (4U)
77745 /*! LPCG_lpcg_mclkout0_0_reserved_4_31 - reserved
77746  */
77747 #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_MASK)
77748 /*! @} */
77749 
77750 
77751 /*!
77752  * @}
77753  */ /* end of group LPCG_LPCG_MCLKOUT0_Register_Masks */
77754 
77755 
77756 /* LPCG_LPCG_MCLKOUT0 - Peripheral instance base addresses */
77757 /** Peripheral ADMA__LPCG_MCLKOUT0 base address */
77758 #define ADMA__LPCG_MCLKOUT0_BASE                 (0x59D50000u)
77759 /** Peripheral ADMA__LPCG_MCLKOUT0 base pointer */
77760 #define ADMA__LPCG_MCLKOUT0                      ((LPCG_LPCG_MCLKOUT0_Type *)ADMA__LPCG_MCLKOUT0_BASE)
77761 /** Array initializer of LPCG_LPCG_MCLKOUT0 peripheral base addresses */
77762 #define LPCG_LPCG_MCLKOUT0_BASE_ADDRS            { ADMA__LPCG_MCLKOUT0_BASE }
77763 /** Array initializer of LPCG_LPCG_MCLKOUT0 peripheral base pointers */
77764 #define LPCG_LPCG_MCLKOUT0_BASE_PTRS             { ADMA__LPCG_MCLKOUT0 }
77765 
77766 /*!
77767  * @}
77768  */ /* end of group LPCG_LPCG_MCLKOUT0_Peripheral_Access_Layer */
77769 
77770 
77771 /* ----------------------------------------------------------------------------
77772    -- LPCG_LPCG_MCLKOUT1 Peripheral Access Layer
77773    ---------------------------------------------------------------------------- */
77774 
77775 /*!
77776  * @addtogroup LPCG_LPCG_MCLKOUT1_Peripheral_Access_Layer LPCG_LPCG_MCLKOUT1 Peripheral Access Layer
77777  * @{
77778  */
77779 
77780 /** LPCG_LPCG_MCLKOUT1 - Register Layout Typedef */
77781 typedef struct {
77782   __IO uint32_t LPCG_LPCG_MCLKOUT1_0;              /**< na, offset: 0x0 */
77783 } LPCG_LPCG_MCLKOUT1_Type;
77784 
77785 /* ----------------------------------------------------------------------------
77786    -- LPCG_LPCG_MCLKOUT1 Register Masks
77787    ---------------------------------------------------------------------------- */
77788 
77789 /*!
77790  * @addtogroup LPCG_LPCG_MCLKOUT1_Register_Masks LPCG_LPCG_MCLKOUT1 Register Masks
77791  * @{
77792  */
77793 
77794 /*! @name LPCG_LPCG_MCLKOUT1_0 - na */
77795 /*! @{ */
77796 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_MASK (0x1U)
77797 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_SHIFT (0U)
77798 /*! LPCG_lpcg_mclkout1_0_reserved_0_0 - reserved
77799  */
77800 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_MASK)
77801 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_MASK (0x2U)
77802 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_SHIFT (1U)
77803 /*! mclkout1_SWEN - Software Enable
77804  *  0b0..Disable SW clock regardless of HWEN
77805  *  0b1..Enable SW clock gating
77806  */
77807 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_MASK)
77808 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_MASK (0x4U)
77809 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_SHIFT (2U)
77810 /*! LPCG_lpcg_mclkout1_0_reserved_2_2 - reserved
77811  */
77812 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_MASK)
77813 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_MASK (0x8U)
77814 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_SHIFT (3U)
77815 /*! mclkout1_STOP - show clock root status, 1 means clock stopped
77816  */
77817 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_MASK)
77818 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_MASK (0xFFFFFFF0U)
77819 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_SHIFT (4U)
77820 /*! LPCG_lpcg_mclkout1_0_reserved_4_31 - reserved
77821  */
77822 #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_MASK)
77823 /*! @} */
77824 
77825 
77826 /*!
77827  * @}
77828  */ /* end of group LPCG_LPCG_MCLKOUT1_Register_Masks */
77829 
77830 
77831 /* LPCG_LPCG_MCLKOUT1 - Peripheral instance base addresses */
77832 /** Peripheral ADMA__LPCG_MCLKOUT1 base address */
77833 #define ADMA__LPCG_MCLKOUT1_BASE                 (0x59D60000u)
77834 /** Peripheral ADMA__LPCG_MCLKOUT1 base pointer */
77835 #define ADMA__LPCG_MCLKOUT1                      ((LPCG_LPCG_MCLKOUT1_Type *)ADMA__LPCG_MCLKOUT1_BASE)
77836 /** Array initializer of LPCG_LPCG_MCLKOUT1 peripheral base addresses */
77837 #define LPCG_LPCG_MCLKOUT1_BASE_ADDRS            { ADMA__LPCG_MCLKOUT1_BASE }
77838 /** Array initializer of LPCG_LPCG_MCLKOUT1 peripheral base pointers */
77839 #define LPCG_LPCG_MCLKOUT1_BASE_PTRS             { ADMA__LPCG_MCLKOUT1 }
77840 
77841 /*!
77842  * @}
77843  */ /* end of group LPCG_LPCG_MCLKOUT1_Peripheral_Access_Layer */
77844 
77845 
77846 /* ----------------------------------------------------------------------------
77847    -- LPCG_LPCG_MQS_REGS Peripheral Access Layer
77848    ---------------------------------------------------------------------------- */
77849 
77850 /*!
77851  * @addtogroup LPCG_LPCG_MQS_REGS_Peripheral_Access_Layer LPCG_LPCG_MQS_REGS Peripheral Access Layer
77852  * @{
77853  */
77854 
77855 /** LPCG_LPCG_MQS_REGS - Register Layout Typedef */
77856 typedef struct {
77857   __IO uint32_t LPCG_LPCG_MQS_REGS_0;              /**< na, offset: 0x0 */
77858 } LPCG_LPCG_MQS_REGS_Type;
77859 
77860 /* ----------------------------------------------------------------------------
77861    -- LPCG_LPCG_MQS_REGS Register Masks
77862    ---------------------------------------------------------------------------- */
77863 
77864 /*!
77865  * @addtogroup LPCG_LPCG_MQS_REGS_Register_Masks LPCG_LPCG_MQS_REGS Register Masks
77866  * @{
77867  */
77868 
77869 /*! @name LPCG_LPCG_MQS_REGS_0 - na */
77870 /*! @{ */
77871 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0_MASK (0x1U)
77872 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0_SHIFT (0U)
77873 /*! LPCG_lpcg_mqs_regs_0_reserved_0_0 - reserved
77874  */
77875 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0_MASK)
77876 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_MASK (0x2U)
77877 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_SHIFT (1U)
77878 /*! mqs_hmclk_SWEN - Software Enable
77879  *  0b0..Disable SW clock regardless of HWEN
77880  *  0b1..Enable SW clock gating
77881  */
77882 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_MASK)
77883 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_MASK (0x4U)
77884 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_SHIFT (2U)
77885 /*! LPCG_lpcg_mqs_regs_0_reserved_2_2 - reserved
77886  */
77887 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_MASK)
77888 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_MASK (0x8U)
77889 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_SHIFT (3U)
77890 /*! mqs_hmclk_STOP - show clock root status, 1 means clock stopped
77891  */
77892 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_MASK)
77893 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15_MASK (0xFFF0U)
77894 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15_SHIFT (4U)
77895 /*! LPCG_lpcg_mqs_regs_0_reserved_4_15 - reserved
77896  */
77897 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15_MASK)
77898 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_MASK (0x10000U)
77899 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_SHIFT (16U)
77900 /*! mqs_regs_ipg_clk_HWEN - Hardware Enable
77901  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
77902  *  0b1..Enable HW automatic gating
77903  */
77904 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_MASK)
77905 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_MASK (0x20000U)
77906 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_SHIFT (17U)
77907 /*! mqs_regs_ipg_clk_SWEN - Software Enable
77908  *  0b0..Disable SW clock regardless of HWEN
77909  *  0b1..Enable SW clock gating
77910  */
77911 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_MASK)
77912 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_MASK (0x40000U)
77913 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_SHIFT (18U)
77914 /*! LPCG_lpcg_mqs_regs_0_reserved_18_18 - reserved
77915  */
77916 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_MASK)
77917 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_MASK (0x80000U)
77918 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_SHIFT (19U)
77919 /*! mqs_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped
77920  */
77921 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_MASK)
77922 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_MASK (0xFFF00000U)
77923 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_SHIFT (20U)
77924 /*! LPCG_lpcg_mqs_regs_0_reserved_20_31 - reserved
77925  */
77926 #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_MASK)
77927 /*! @} */
77928 
77929 
77930 /*!
77931  * @}
77932  */ /* end of group LPCG_LPCG_MQS_REGS_Register_Masks */
77933 
77934 
77935 /* LPCG_LPCG_MQS_REGS - Peripheral instance base addresses */
77936 /** Peripheral ADMA__LPCG_MQS_HMCLK base address */
77937 #define ADMA__LPCG_MQS_HMCLK_BASE                (0x59C50000u)
77938 /** Peripheral ADMA__LPCG_MQS_HMCLK base pointer */
77939 #define ADMA__LPCG_MQS_HMCLK                     ((LPCG_LPCG_MQS_REGS_Type *)ADMA__LPCG_MQS_HMCLK_BASE)
77940 /** Array initializer of LPCG_LPCG_MQS_REGS peripheral base addresses */
77941 #define LPCG_LPCG_MQS_REGS_BASE_ADDRS            { ADMA__LPCG_MQS_HMCLK_BASE }
77942 /** Array initializer of LPCG_LPCG_MQS_REGS peripheral base pointers */
77943 #define LPCG_LPCG_MQS_REGS_BASE_PTRS             { ADMA__LPCG_MQS_HMCLK }
77944 
77945 /*!
77946  * @}
77947  */ /* end of group LPCG_LPCG_MQS_REGS_Peripheral_Access_Layer */
77948 
77949 
77950 /* ----------------------------------------------------------------------------
77951    -- LPCG_LPCG_OCRAM Peripheral Access Layer
77952    ---------------------------------------------------------------------------- */
77953 
77954 /*!
77955  * @addtogroup LPCG_LPCG_OCRAM_Peripheral_Access_Layer LPCG_LPCG_OCRAM Peripheral Access Layer
77956  * @{
77957  */
77958 
77959 /** LPCG_LPCG_OCRAM - Register Layout Typedef */
77960 typedef struct {
77961   __IO uint32_t LPCG_LPCG_OCRAM_0;                 /**< na, offset: 0x0 */
77962 } LPCG_LPCG_OCRAM_Type;
77963 
77964 /* ----------------------------------------------------------------------------
77965    -- LPCG_LPCG_OCRAM Register Masks
77966    ---------------------------------------------------------------------------- */
77967 
77968 /*!
77969  * @addtogroup LPCG_LPCG_OCRAM_Register_Masks LPCG_LPCG_OCRAM Register Masks
77970  * @{
77971  */
77972 
77973 /*! @name LPCG_LPCG_OCRAM_0 - na */
77974 /*! @{ */
77975 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16_MASK (0x1FFFFU)
77976 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16_SHIFT (0U)
77977 /*! LPCG_lpcg_ocram_0_reserved_0_16 - reserved
77978  */
77979 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16_MASK)
77980 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN_MASK (0x20000U)
77981 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN_SHIFT (17U)
77982 /*! ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN - Software Enable
77983  *  0b0..Disable SW clock regardless of HWEN
77984  *  0b1..Enable SW clock gating
77985  */
77986 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN_MASK)
77987 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18_MASK (0x40000U)
77988 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18_SHIFT (18U)
77989 /*! LPCG_lpcg_ocram_0_reserved_18_18 - reserved
77990  */
77991 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18_MASK)
77992 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP_MASK (0x80000U)
77993 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP_SHIFT (19U)
77994 /*! ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP - show clock root status, 1 means clock stopped
77995  */
77996 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP_MASK)
77997 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31_MASK (0xFFF00000U)
77998 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31_SHIFT (20U)
77999 /*! LPCG_lpcg_ocram_0_reserved_20_31 - reserved
78000  */
78001 #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31_MASK)
78002 /*! @} */
78003 
78004 
78005 /*!
78006  * @}
78007  */ /* end of group LPCG_LPCG_OCRAM_Register_Masks */
78008 
78009 
78010 /* LPCG_LPCG_OCRAM - Peripheral instance base addresses */
78011 /** Peripheral ADMA__LPCG_OCRAM_MEM_CLK base address */
78012 #define ADMA__LPCG_OCRAM_MEM_CLK_BASE            (0x59590000u)
78013 /** Peripheral ADMA__LPCG_OCRAM_MEM_CLK base pointer */
78014 #define ADMA__LPCG_OCRAM_MEM_CLK                 ((LPCG_LPCG_OCRAM_Type *)ADMA__LPCG_OCRAM_MEM_CLK_BASE)
78015 /** Array initializer of LPCG_LPCG_OCRAM peripheral base addresses */
78016 #define LPCG_LPCG_OCRAM_BASE_ADDRS               { ADMA__LPCG_OCRAM_MEM_CLK_BASE }
78017 /** Array initializer of LPCG_LPCG_OCRAM peripheral base pointers */
78018 #define LPCG_LPCG_OCRAM_BASE_PTRS                { ADMA__LPCG_OCRAM_MEM_CLK }
78019 
78020 /*!
78021  * @}
78022  */ /* end of group LPCG_LPCG_OCRAM_Peripheral_Access_Layer */
78023 
78024 
78025 /* ----------------------------------------------------------------------------
78026    -- LPCG_LPCG_PWM Peripheral Access Layer
78027    ---------------------------------------------------------------------------- */
78028 
78029 /*!
78030  * @addtogroup LPCG_LPCG_PWM_Peripheral_Access_Layer LPCG_LPCG_PWM Peripheral Access Layer
78031  * @{
78032  */
78033 
78034 /** LPCG_LPCG_PWM - Register Layout Typedef */
78035 typedef struct {
78036   __IO uint32_t LPCG_LPCG_PWM_0;                   /**< na, offset: 0x0 */
78037 } LPCG_LPCG_PWM_Type;
78038 
78039 /* ----------------------------------------------------------------------------
78040    -- LPCG_LPCG_PWM Register Masks
78041    ---------------------------------------------------------------------------- */
78042 
78043 /*!
78044  * @addtogroup LPCG_LPCG_PWM_Register_Masks LPCG_LPCG_PWM Register Masks
78045  * @{
78046  */
78047 
78048 /*! @name LPCG_LPCG_PWM_0 - na */
78049 /*! @{ */
78050 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0_MASK (0x1U)
78051 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0_SHIFT (0U)
78052 /*! LPCG_lpcg_pwm_0_reserved_0_0 - reserved
78053  */
78054 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0_MASK)
78055 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U)
78056 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U)
78057 /*! pwm_ipg_clk_highfreq_SWEN - Software Enable
78058  *  0b0..Disable SW clock regardless of HWEN
78059  *  0b1..Enable SW clock gating
78060  */
78061 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN_MASK)
78062 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2_MASK (0x4U)
78063 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2_SHIFT (2U)
78064 /*! LPCG_lpcg_pwm_0_reserved_2_2 - reserved
78065  */
78066 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2_MASK)
78067 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP_MASK (0x8U)
78068 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP_SHIFT (3U)
78069 /*! pwm_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
78070  */
78071 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP_MASK)
78072 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15_MASK (0xFFF0U)
78073 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15_SHIFT (4U)
78074 /*! LPCG_lpcg_pwm_0_reserved_4_15 - reserved
78075  */
78076 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15_MASK)
78077 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN_MASK (0x10000U)
78078 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN_SHIFT (16U)
78079 /*! pwm_ipg_clk_s_HWEN - Hardware Enable
78080  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78081  *  0b1..Enable HW automatic gating
78082  */
78083 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN_MASK)
78084 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U)
78085 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U)
78086 /*! pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN - Software Enable
78087  *  0b0..Disable SW clock regardless of HWEN
78088  *  0b1..Enable SW clock gating
78089  */
78090 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK)
78091 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18_MASK (0x40000U)
78092 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18_SHIFT (18U)
78093 /*! LPCG_lpcg_pwm_0_reserved_18_18 - reserved
78094  */
78095 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18_MASK)
78096 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U)
78097 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U)
78098 /*! pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
78099  */
78100 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK)
78101 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31_MASK (0xFFF00000U)
78102 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31_SHIFT (20U)
78103 /*! LPCG_lpcg_pwm_0_reserved_20_31 - reserved
78104  */
78105 #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31_MASK)
78106 /*! @} */
78107 
78108 
78109 /*!
78110  * @}
78111  */ /* end of group LPCG_LPCG_PWM_Register_Masks */
78112 
78113 
78114 /* LPCG_LPCG_PWM - Peripheral instance base addresses */
78115 /** Peripheral ADMA__LPCG_PWM_IPG_CLK base address */
78116 #define ADMA__LPCG_PWM_IPG_CLK_BASE              (0x5A590000u)
78117 /** Peripheral ADMA__LPCG_PWM_IPG_CLK base pointer */
78118 #define ADMA__LPCG_PWM_IPG_CLK                   ((LPCG_LPCG_PWM_Type *)ADMA__LPCG_PWM_IPG_CLK_BASE)
78119 /** Array initializer of LPCG_LPCG_PWM peripheral base addresses */
78120 #define LPCG_LPCG_PWM_BASE_ADDRS                 { ADMA__LPCG_PWM_IPG_CLK_BASE }
78121 /** Array initializer of LPCG_LPCG_PWM peripheral base pointers */
78122 #define LPCG_LPCG_PWM_BASE_PTRS                  { ADMA__LPCG_PWM_IPG_CLK }
78123 
78124 /*!
78125  * @}
78126  */ /* end of group LPCG_LPCG_PWM_Peripheral_Access_Layer */
78127 
78128 
78129 /* ----------------------------------------------------------------------------
78130    -- LPCG_LPCG_SAI0 Peripheral Access Layer
78131    ---------------------------------------------------------------------------- */
78132 
78133 /*!
78134  * @addtogroup LPCG_LPCG_SAI0_Peripheral_Access_Layer LPCG_LPCG_SAI0 Peripheral Access Layer
78135  * @{
78136  */
78137 
78138 /** LPCG_LPCG_SAI0 - Register Layout Typedef */
78139 typedef struct {
78140   __IO uint32_t LPCG_LPCG_SAI0_0;                  /**< na, offset: 0x0 */
78141 } LPCG_LPCG_SAI0_Type;
78142 
78143 /* ----------------------------------------------------------------------------
78144    -- LPCG_LPCG_SAI0 Register Masks
78145    ---------------------------------------------------------------------------- */
78146 
78147 /*!
78148  * @addtogroup LPCG_LPCG_SAI0_Register_Masks LPCG_LPCG_SAI0 Register Masks
78149  * @{
78150  */
78151 
78152 /*! @name LPCG_LPCG_SAI0_0 - na */
78153 /*! @{ */
78154 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_MASK (0x1U)
78155 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_SHIFT (0U)
78156 /*! LPCG_lpcg_sai0_0_reserved_0_0 - reserved
78157  */
78158 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_MASK)
78159 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U)
78160 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U)
78161 /*! sai0_ipg_clk_sai_mclk_1_SWEN - Software Enable
78162  *  0b0..Disable SW clock regardless of HWEN
78163  *  0b1..Enable SW clock gating
78164  */
78165 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_MASK)
78166 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_MASK (0x4U)
78167 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_SHIFT (2U)
78168 /*! LPCG_lpcg_sai0_0_reserved_2_2 - reserved
78169  */
78170 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_MASK)
78171 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_MASK (0x8U)
78172 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_SHIFT (3U)
78173 /*! sai0_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped
78174  */
78175 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_MASK)
78176 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15_MASK (0xFFF0U)
78177 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15_SHIFT (4U)
78178 /*! LPCG_lpcg_sai0_0_reserved_4_15 - reserved
78179  */
78180 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15_MASK)
78181 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_MASK (0x10000U)
78182 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_SHIFT (16U)
78183 /*! sai0_ipg_clk_s_HWEN - Hardware Enable
78184  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78185  *  0b1..Enable HW automatic gating
78186  */
78187 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_MASK)
78188 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN_MASK (0x20000U)
78189 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN_SHIFT (17U)
78190 /*! sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN - Software Enable
78191  *  0b0..Disable SW clock regardless of HWEN
78192  *  0b1..Enable SW clock gating
78193  */
78194 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN_MASK)
78195 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_MASK (0x40000U)
78196 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_SHIFT (18U)
78197 /*! LPCG_lpcg_sai0_0_reserved_18_18 - reserved
78198  */
78199 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_MASK)
78200 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP_MASK (0x80000U)
78201 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP_SHIFT (19U)
78202 /*! sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
78203  */
78204 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP_MASK)
78205 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_MASK (0xFFF00000U)
78206 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_SHIFT (20U)
78207 /*! LPCG_lpcg_sai0_0_reserved_20_31 - reserved
78208  */
78209 #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_MASK)
78210 /*! @} */
78211 
78212 
78213 /*!
78214  * @}
78215  */ /* end of group LPCG_LPCG_SAI0_Register_Masks */
78216 
78217 
78218 /* LPCG_LPCG_SAI0 - Peripheral instance base addresses */
78219 /** Peripheral ADMA__LPCG_SAI0_IPG_CLK base address */
78220 #define ADMA__LPCG_SAI0_IPG_CLK_BASE             (0x59440000u)
78221 /** Peripheral ADMA__LPCG_SAI0_IPG_CLK base pointer */
78222 #define ADMA__LPCG_SAI0_IPG_CLK                  ((LPCG_LPCG_SAI0_Type *)ADMA__LPCG_SAI0_IPG_CLK_BASE)
78223 /** Array initializer of LPCG_LPCG_SAI0 peripheral base addresses */
78224 #define LPCG_LPCG_SAI0_BASE_ADDRS                { ADMA__LPCG_SAI0_IPG_CLK_BASE }
78225 /** Array initializer of LPCG_LPCG_SAI0 peripheral base pointers */
78226 #define LPCG_LPCG_SAI0_BASE_PTRS                 { ADMA__LPCG_SAI0_IPG_CLK }
78227 
78228 /*!
78229  * @}
78230  */ /* end of group LPCG_LPCG_SAI0_Peripheral_Access_Layer */
78231 
78232 
78233 /* ----------------------------------------------------------------------------
78234    -- LPCG_LPCG_SAI1 Peripheral Access Layer
78235    ---------------------------------------------------------------------------- */
78236 
78237 /*!
78238  * @addtogroup LPCG_LPCG_SAI1_Peripheral_Access_Layer LPCG_LPCG_SAI1 Peripheral Access Layer
78239  * @{
78240  */
78241 
78242 /** LPCG_LPCG_SAI1 - Register Layout Typedef */
78243 typedef struct {
78244   __IO uint32_t LPCG_LPCG_SAI1_0;                  /**< na, offset: 0x0 */
78245 } LPCG_LPCG_SAI1_Type;
78246 
78247 /* ----------------------------------------------------------------------------
78248    -- LPCG_LPCG_SAI1 Register Masks
78249    ---------------------------------------------------------------------------- */
78250 
78251 /*!
78252  * @addtogroup LPCG_LPCG_SAI1_Register_Masks LPCG_LPCG_SAI1 Register Masks
78253  * @{
78254  */
78255 
78256 /*! @name LPCG_LPCG_SAI1_0 - na */
78257 /*! @{ */
78258 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_MASK (0x1U)
78259 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_SHIFT (0U)
78260 /*! LPCG_lpcg_sai1_0_reserved_0_0 - reserved
78261  */
78262 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_MASK)
78263 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U)
78264 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U)
78265 /*! sai1_ipg_clk_sai_mclk_1_SWEN - Software Enable
78266  *  0b0..Disable SW clock regardless of HWEN
78267  *  0b1..Enable SW clock gating
78268  */
78269 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_MASK)
78270 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_MASK (0x4U)
78271 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_SHIFT (2U)
78272 /*! LPCG_lpcg_sai1_0_reserved_2_2 - reserved
78273  */
78274 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_MASK)
78275 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_MASK (0x8U)
78276 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_SHIFT (3U)
78277 /*! sai1_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped
78278  */
78279 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_MASK)
78280 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15_MASK (0xFFF0U)
78281 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15_SHIFT (4U)
78282 /*! LPCG_lpcg_sai1_0_reserved_4_15 - reserved
78283  */
78284 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15_MASK)
78285 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_MASK (0x10000U)
78286 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_SHIFT (16U)
78287 /*! sai1_ipg_clk_s_HWEN - Hardware Enable
78288  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78289  *  0b1..Enable HW automatic gating
78290  */
78291 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_MASK)
78292 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN_MASK (0x20000U)
78293 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN_SHIFT (17U)
78294 /*! sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN - Software Enable
78295  *  0b0..Disable SW clock regardless of HWEN
78296  *  0b1..Enable SW clock gating
78297  */
78298 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN_MASK)
78299 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_MASK (0x40000U)
78300 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_SHIFT (18U)
78301 /*! LPCG_lpcg_sai1_0_reserved_18_18 - reserved
78302  */
78303 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_MASK)
78304 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP_MASK (0x80000U)
78305 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP_SHIFT (19U)
78306 /*! sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
78307  */
78308 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP_MASK)
78309 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_MASK (0xFFF00000U)
78310 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_SHIFT (20U)
78311 /*! LPCG_lpcg_sai1_0_reserved_20_31 - reserved
78312  */
78313 #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_MASK)
78314 /*! @} */
78315 
78316 
78317 /*!
78318  * @}
78319  */ /* end of group LPCG_LPCG_SAI1_Register_Masks */
78320 
78321 
78322 /* LPCG_LPCG_SAI1 - Peripheral instance base addresses */
78323 /** Peripheral ADMA__LPCG_SAI1_IPG_CLK base address */
78324 #define ADMA__LPCG_SAI1_IPG_CLK_BASE             (0x59450000u)
78325 /** Peripheral ADMA__LPCG_SAI1_IPG_CLK base pointer */
78326 #define ADMA__LPCG_SAI1_IPG_CLK                  ((LPCG_LPCG_SAI1_Type *)ADMA__LPCG_SAI1_IPG_CLK_BASE)
78327 /** Array initializer of LPCG_LPCG_SAI1 peripheral base addresses */
78328 #define LPCG_LPCG_SAI1_BASE_ADDRS                { ADMA__LPCG_SAI1_IPG_CLK_BASE }
78329 /** Array initializer of LPCG_LPCG_SAI1 peripheral base pointers */
78330 #define LPCG_LPCG_SAI1_BASE_PTRS                 { ADMA__LPCG_SAI1_IPG_CLK }
78331 
78332 /*!
78333  * @}
78334  */ /* end of group LPCG_LPCG_SAI1_Peripheral_Access_Layer */
78335 
78336 
78337 /* ----------------------------------------------------------------------------
78338    -- LPCG_LPCG_SAI2 Peripheral Access Layer
78339    ---------------------------------------------------------------------------- */
78340 
78341 /*!
78342  * @addtogroup LPCG_LPCG_SAI2_Peripheral_Access_Layer LPCG_LPCG_SAI2 Peripheral Access Layer
78343  * @{
78344  */
78345 
78346 /** LPCG_LPCG_SAI2 - Register Layout Typedef */
78347 typedef struct {
78348   __IO uint32_t LPCG_LPCG_SAI2_0;                  /**< na, offset: 0x0 */
78349 } LPCG_LPCG_SAI2_Type;
78350 
78351 /* ----------------------------------------------------------------------------
78352    -- LPCG_LPCG_SAI2 Register Masks
78353    ---------------------------------------------------------------------------- */
78354 
78355 /*!
78356  * @addtogroup LPCG_LPCG_SAI2_Register_Masks LPCG_LPCG_SAI2 Register Masks
78357  * @{
78358  */
78359 
78360 /*! @name LPCG_LPCG_SAI2_0 - na */
78361 /*! @{ */
78362 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_MASK (0x1U)
78363 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_SHIFT (0U)
78364 /*! LPCG_lpcg_sai2_0_reserved_0_0 - reserved
78365  */
78366 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_MASK)
78367 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U)
78368 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U)
78369 /*! sai2_ipg_clk_sai_mclk_1_SWEN - Software Enable
78370  *  0b0..Disable SW clock regardless of HWEN
78371  *  0b1..Enable SW clock gating
78372  */
78373 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_MASK)
78374 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_MASK (0x4U)
78375 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_SHIFT (2U)
78376 /*! LPCG_lpcg_sai2_0_reserved_2_2 - reserved
78377  */
78378 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_MASK)
78379 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_MASK (0x8U)
78380 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_SHIFT (3U)
78381 /*! sai2_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped
78382  */
78383 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_MASK)
78384 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15_MASK (0xFFF0U)
78385 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15_SHIFT (4U)
78386 /*! LPCG_lpcg_sai2_0_reserved_4_15 - reserved
78387  */
78388 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15_MASK)
78389 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_MASK (0x10000U)
78390 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_SHIFT (16U)
78391 /*! sai2_ipg_clk_s_HWEN - Hardware Enable
78392  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78393  *  0b1..Enable HW automatic gating
78394  */
78395 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_MASK)
78396 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN_MASK (0x20000U)
78397 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN_SHIFT (17U)
78398 /*! sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN - Software Enable
78399  *  0b0..Disable SW clock regardless of HWEN
78400  *  0b1..Enable SW clock gating
78401  */
78402 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN_MASK)
78403 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_MASK (0x40000U)
78404 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_SHIFT (18U)
78405 /*! LPCG_lpcg_sai2_0_reserved_18_18 - reserved
78406  */
78407 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_MASK)
78408 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP_MASK (0x80000U)
78409 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP_SHIFT (19U)
78410 /*! sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
78411  */
78412 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP_MASK)
78413 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_MASK (0xFFF00000U)
78414 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_SHIFT (20U)
78415 /*! LPCG_lpcg_sai2_0_reserved_20_31 - reserved
78416  */
78417 #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_MASK)
78418 /*! @} */
78419 
78420 
78421 /*!
78422  * @}
78423  */ /* end of group LPCG_LPCG_SAI2_Register_Masks */
78424 
78425 
78426 /* LPCG_LPCG_SAI2 - Peripheral instance base addresses */
78427 /** Peripheral ADMA__LPCG_SAI2_IPG_CLK base address */
78428 #define ADMA__LPCG_SAI2_IPG_CLK_BASE             (0x59460000u)
78429 /** Peripheral ADMA__LPCG_SAI2_IPG_CLK base pointer */
78430 #define ADMA__LPCG_SAI2_IPG_CLK                  ((LPCG_LPCG_SAI2_Type *)ADMA__LPCG_SAI2_IPG_CLK_BASE)
78431 /** Array initializer of LPCG_LPCG_SAI2 peripheral base addresses */
78432 #define LPCG_LPCG_SAI2_BASE_ADDRS                { ADMA__LPCG_SAI2_IPG_CLK_BASE }
78433 /** Array initializer of LPCG_LPCG_SAI2 peripheral base pointers */
78434 #define LPCG_LPCG_SAI2_BASE_PTRS                 { ADMA__LPCG_SAI2_IPG_CLK }
78435 
78436 /*!
78437  * @}
78438  */ /* end of group LPCG_LPCG_SAI2_Peripheral_Access_Layer */
78439 
78440 
78441 /* ----------------------------------------------------------------------------
78442    -- LPCG_LPCG_SAI3 Peripheral Access Layer
78443    ---------------------------------------------------------------------------- */
78444 
78445 /*!
78446  * @addtogroup LPCG_LPCG_SAI3_Peripheral_Access_Layer LPCG_LPCG_SAI3 Peripheral Access Layer
78447  * @{
78448  */
78449 
78450 /** LPCG_LPCG_SAI3 - Register Layout Typedef */
78451 typedef struct {
78452   __IO uint32_t LPCG_LPCG_SAI3_0;                  /**< na, offset: 0x0 */
78453 } LPCG_LPCG_SAI3_Type;
78454 
78455 /* ----------------------------------------------------------------------------
78456    -- LPCG_LPCG_SAI3 Register Masks
78457    ---------------------------------------------------------------------------- */
78458 
78459 /*!
78460  * @addtogroup LPCG_LPCG_SAI3_Register_Masks LPCG_LPCG_SAI3 Register Masks
78461  * @{
78462  */
78463 
78464 /*! @name LPCG_LPCG_SAI3_0 - na */
78465 /*! @{ */
78466 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_MASK (0x1U)
78467 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_SHIFT (0U)
78468 /*! LPCG_lpcg_sai3_0_reserved_0_0 - reserved
78469  */
78470 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_MASK)
78471 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U)
78472 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U)
78473 /*! sai3_ipg_clk_sai_mclk_1_SWEN - Software Enable
78474  *  0b0..Disable SW clock regardless of HWEN
78475  *  0b1..Enable SW clock gating
78476  */
78477 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_MASK)
78478 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_MASK (0x4U)
78479 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_SHIFT (2U)
78480 /*! LPCG_lpcg_sai3_0_reserved_2_2 - reserved
78481  */
78482 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_MASK)
78483 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_MASK (0x8U)
78484 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_SHIFT (3U)
78485 /*! sai3_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped
78486  */
78487 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_MASK)
78488 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15_MASK (0xFFF0U)
78489 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15_SHIFT (4U)
78490 /*! LPCG_lpcg_sai3_0_reserved_4_15 - reserved
78491  */
78492 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15_MASK)
78493 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_MASK (0x10000U)
78494 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_SHIFT (16U)
78495 /*! sai3_ipg_clk_s_HWEN - Hardware Enable
78496  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78497  *  0b1..Enable HW automatic gating
78498  */
78499 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_MASK)
78500 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN_MASK (0x20000U)
78501 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN_SHIFT (17U)
78502 /*! sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN - Software Enable
78503  *  0b0..Disable SW clock regardless of HWEN
78504  *  0b1..Enable SW clock gating
78505  */
78506 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN_MASK)
78507 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_MASK (0x40000U)
78508 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_SHIFT (18U)
78509 /*! LPCG_lpcg_sai3_0_reserved_18_18 - reserved
78510  */
78511 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_MASK)
78512 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP_MASK (0x80000U)
78513 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP_SHIFT (19U)
78514 /*! sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
78515  */
78516 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP_MASK)
78517 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_MASK (0xFFF00000U)
78518 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_SHIFT (20U)
78519 /*! LPCG_lpcg_sai3_0_reserved_20_31 - reserved
78520  */
78521 #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_MASK)
78522 /*! @} */
78523 
78524 
78525 /*!
78526  * @}
78527  */ /* end of group LPCG_LPCG_SAI3_Register_Masks */
78528 
78529 
78530 /* LPCG_LPCG_SAI3 - Peripheral instance base addresses */
78531 /** Peripheral ADMA__LPCG_SAI3_IPG_CLK base address */
78532 #define ADMA__LPCG_SAI3_IPG_CLK_BASE             (0x59470000u)
78533 /** Peripheral ADMA__LPCG_SAI3_IPG_CLK base pointer */
78534 #define ADMA__LPCG_SAI3_IPG_CLK                  ((LPCG_LPCG_SAI3_Type *)ADMA__LPCG_SAI3_IPG_CLK_BASE)
78535 /** Array initializer of LPCG_LPCG_SAI3 peripheral base addresses */
78536 #define LPCG_LPCG_SAI3_BASE_ADDRS                { ADMA__LPCG_SAI3_IPG_CLK_BASE }
78537 /** Array initializer of LPCG_LPCG_SAI3 peripheral base pointers */
78538 #define LPCG_LPCG_SAI3_BASE_PTRS                 { ADMA__LPCG_SAI3_IPG_CLK }
78539 
78540 /*!
78541  * @}
78542  */ /* end of group LPCG_LPCG_SAI3_Peripheral_Access_Layer */
78543 
78544 
78545 /* ----------------------------------------------------------------------------
78546    -- LPCG_LPCG_SAI4 Peripheral Access Layer
78547    ---------------------------------------------------------------------------- */
78548 
78549 /*!
78550  * @addtogroup LPCG_LPCG_SAI4_Peripheral_Access_Layer LPCG_LPCG_SAI4 Peripheral Access Layer
78551  * @{
78552  */
78553 
78554 /** LPCG_LPCG_SAI4 - Register Layout Typedef */
78555 typedef struct {
78556   __IO uint32_t LPCG_LPCG_SAI4_0;                  /**< na, offset: 0x0 */
78557 } LPCG_LPCG_SAI4_Type;
78558 
78559 /* ----------------------------------------------------------------------------
78560    -- LPCG_LPCG_SAI4 Register Masks
78561    ---------------------------------------------------------------------------- */
78562 
78563 /*!
78564  * @addtogroup LPCG_LPCG_SAI4_Register_Masks LPCG_LPCG_SAI4 Register Masks
78565  * @{
78566  */
78567 
78568 /*! @name LPCG_LPCG_SAI4_0 - na */
78569 /*! @{ */
78570 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0_MASK (0x1U)
78571 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0_SHIFT (0U)
78572 /*! LPCG_lpcg_sai4_0_reserved_0_0 - reserved
78573  */
78574 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0_MASK)
78575 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U)
78576 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U)
78577 /*! sai4_ipg_clk_sai_mclk_1_SWEN - Software Enable
78578  *  0b0..Disable SW clock regardless of HWEN
78579  *  0b1..Enable SW clock gating
78580  */
78581 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN_MASK)
78582 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2_MASK (0x4U)
78583 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2_SHIFT (2U)
78584 /*! LPCG_lpcg_sai4_0_reserved_2_2 - reserved
78585  */
78586 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2_MASK)
78587 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP_MASK (0x8U)
78588 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP_SHIFT (3U)
78589 /*! sai4_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped
78590  */
78591 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP_MASK)
78592 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15_MASK (0xFFF0U)
78593 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15_SHIFT (4U)
78594 /*! LPCG_lpcg_sai4_0_reserved_4_15 - reserved
78595  */
78596 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15_MASK)
78597 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN_MASK (0x10000U)
78598 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN_SHIFT (16U)
78599 /*! sai4_ipg_clk_s_HWEN - Hardware Enable
78600  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78601  *  0b1..Enable HW automatic gating
78602  */
78603 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN_MASK)
78604 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN_MASK (0x20000U)
78605 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN_SHIFT (17U)
78606 /*! sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN - Software Enable
78607  *  0b0..Disable SW clock regardless of HWEN
78608  *  0b1..Enable SW clock gating
78609  */
78610 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN_MASK)
78611 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18_MASK (0x40000U)
78612 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18_SHIFT (18U)
78613 /*! LPCG_lpcg_sai4_0_reserved_18_18 - reserved
78614  */
78615 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18_MASK)
78616 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP_MASK (0x80000U)
78617 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP_SHIFT (19U)
78618 /*! sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
78619  */
78620 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP_MASK)
78621 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31_MASK (0xFFF00000U)
78622 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31_SHIFT (20U)
78623 /*! LPCG_lpcg_sai4_0_reserved_20_31 - reserved
78624  */
78625 #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31_MASK)
78626 /*! @} */
78627 
78628 
78629 /*!
78630  * @}
78631  */ /* end of group LPCG_LPCG_SAI4_Register_Masks */
78632 
78633 
78634 /* LPCG_LPCG_SAI4 - Peripheral instance base addresses */
78635 /** Peripheral ADMA__LPCG_SAI4_IPG_CLK base address */
78636 #define ADMA__LPCG_SAI4_IPG_CLK_BASE             (0x59C20000u)
78637 /** Peripheral ADMA__LPCG_SAI4_IPG_CLK base pointer */
78638 #define ADMA__LPCG_SAI4_IPG_CLK                  ((LPCG_LPCG_SAI4_Type *)ADMA__LPCG_SAI4_IPG_CLK_BASE)
78639 /** Array initializer of LPCG_LPCG_SAI4 peripheral base addresses */
78640 #define LPCG_LPCG_SAI4_BASE_ADDRS                { ADMA__LPCG_SAI4_IPG_CLK_BASE }
78641 /** Array initializer of LPCG_LPCG_SAI4 peripheral base pointers */
78642 #define LPCG_LPCG_SAI4_BASE_PTRS                 { ADMA__LPCG_SAI4_IPG_CLK }
78643 
78644 /*!
78645  * @}
78646  */ /* end of group LPCG_LPCG_SAI4_Peripheral_Access_Layer */
78647 
78648 
78649 /* ----------------------------------------------------------------------------
78650    -- LPCG_LPCG_SAI5 Peripheral Access Layer
78651    ---------------------------------------------------------------------------- */
78652 
78653 /*!
78654  * @addtogroup LPCG_LPCG_SAI5_Peripheral_Access_Layer LPCG_LPCG_SAI5 Peripheral Access Layer
78655  * @{
78656  */
78657 
78658 /** LPCG_LPCG_SAI5 - Register Layout Typedef */
78659 typedef struct {
78660   __IO uint32_t LPCG_LPCG_SAI5_0;                  /**< na, offset: 0x0 */
78661 } LPCG_LPCG_SAI5_Type;
78662 
78663 /* ----------------------------------------------------------------------------
78664    -- LPCG_LPCG_SAI5 Register Masks
78665    ---------------------------------------------------------------------------- */
78666 
78667 /*!
78668  * @addtogroup LPCG_LPCG_SAI5_Register_Masks LPCG_LPCG_SAI5 Register Masks
78669  * @{
78670  */
78671 
78672 /*! @name LPCG_LPCG_SAI5_0 - na */
78673 /*! @{ */
78674 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0_MASK (0x1U)
78675 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0_SHIFT (0U)
78676 /*! LPCG_lpcg_sai5_0_reserved_0_0 - reserved
78677  */
78678 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0_MASK)
78679 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U)
78680 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U)
78681 /*! sai5_ipg_clk_sai_mclk_1_SWEN - Software Enable
78682  *  0b0..Disable SW clock regardless of HWEN
78683  *  0b1..Enable SW clock gating
78684  */
78685 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN_MASK)
78686 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2_MASK (0x4U)
78687 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2_SHIFT (2U)
78688 /*! LPCG_lpcg_sai5_0_reserved_2_2 - reserved
78689  */
78690 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2_MASK)
78691 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP_MASK (0x8U)
78692 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP_SHIFT (3U)
78693 /*! sai5_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped
78694  */
78695 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP_MASK)
78696 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15_MASK (0xFFF0U)
78697 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15_SHIFT (4U)
78698 /*! LPCG_lpcg_sai5_0_reserved_4_15 - reserved
78699  */
78700 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15_MASK)
78701 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN_MASK (0x10000U)
78702 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN_SHIFT (16U)
78703 /*! sai5_ipg_clk_s_HWEN - Hardware Enable
78704  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78705  *  0b1..Enable HW automatic gating
78706  */
78707 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN_MASK)
78708 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN_MASK (0x20000U)
78709 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN_SHIFT (17U)
78710 /*! sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN - Software Enable
78711  *  0b0..Disable SW clock regardless of HWEN
78712  *  0b1..Enable SW clock gating
78713  */
78714 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN_MASK)
78715 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18_MASK (0x40000U)
78716 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18_SHIFT (18U)
78717 /*! LPCG_lpcg_sai5_0_reserved_18_18 - reserved
78718  */
78719 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18_MASK)
78720 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP_MASK (0x80000U)
78721 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP_SHIFT (19U)
78722 /*! sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
78723  */
78724 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP_MASK)
78725 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31_MASK (0xFFF00000U)
78726 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31_SHIFT (20U)
78727 /*! LPCG_lpcg_sai5_0_reserved_20_31 - reserved
78728  */
78729 #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31_MASK)
78730 /*! @} */
78731 
78732 
78733 /*!
78734  * @}
78735  */ /* end of group LPCG_LPCG_SAI5_Register_Masks */
78736 
78737 
78738 /* LPCG_LPCG_SAI5 - Peripheral instance base addresses */
78739 /** Peripheral ADMA__LPCG_SAI5_IPG_CLK base address */
78740 #define ADMA__LPCG_SAI5_IPG_CLK_BASE             (0x59C30000u)
78741 /** Peripheral ADMA__LPCG_SAI5_IPG_CLK base pointer */
78742 #define ADMA__LPCG_SAI5_IPG_CLK                  ((LPCG_LPCG_SAI5_Type *)ADMA__LPCG_SAI5_IPG_CLK_BASE)
78743 /** Array initializer of LPCG_LPCG_SAI5 peripheral base addresses */
78744 #define LPCG_LPCG_SAI5_BASE_ADDRS                { ADMA__LPCG_SAI5_IPG_CLK_BASE }
78745 /** Array initializer of LPCG_LPCG_SAI5 peripheral base pointers */
78746 #define LPCG_LPCG_SAI5_BASE_PTRS                 { ADMA__LPCG_SAI5_IPG_CLK }
78747 
78748 /*!
78749  * @}
78750  */ /* end of group LPCG_LPCG_SAI5_Peripheral_Access_Layer */
78751 
78752 
78753 /* ----------------------------------------------------------------------------
78754    -- LPCG_LPCG_SPDIF0 Peripheral Access Layer
78755    ---------------------------------------------------------------------------- */
78756 
78757 /*!
78758  * @addtogroup LPCG_LPCG_SPDIF0_Peripheral_Access_Layer LPCG_LPCG_SPDIF0 Peripheral Access Layer
78759  * @{
78760  */
78761 
78762 /** LPCG_LPCG_SPDIF0 - Register Layout Typedef */
78763 typedef struct {
78764   __IO uint32_t LPCG_LPCG_SPDIF0_0;                /**< na, offset: 0x0 */
78765 } LPCG_LPCG_SPDIF0_Type;
78766 
78767 /* ----------------------------------------------------------------------------
78768    -- LPCG_LPCG_SPDIF0 Register Masks
78769    ---------------------------------------------------------------------------- */
78770 
78771 /*!
78772  * @addtogroup LPCG_LPCG_SPDIF0_Register_Masks LPCG_LPCG_SPDIF0 Register Masks
78773  * @{
78774  */
78775 
78776 /*! @name LPCG_LPCG_SPDIF0_0 - na */
78777 /*! @{ */
78778 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0_MASK (0x1U)
78779 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0_SHIFT (0U)
78780 /*! LPCG_lpcg_spdif0_0_reserved_0_0 - reserved
78781  */
78782 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0_MASK)
78783 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_MASK (0x2U)
78784 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_SHIFT (1U)
78785 /*! spdif0_tx_clk_SWEN - Software Enable
78786  *  0b0..Disable SW clock regardless of HWEN
78787  *  0b1..Enable SW clock gating
78788  */
78789 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_MASK)
78790 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_MASK (0x4U)
78791 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_SHIFT (2U)
78792 /*! LPCG_lpcg_spdif0_0_reserved_2_2 - reserved
78793  */
78794 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_MASK)
78795 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_MASK (0x8U)
78796 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_SHIFT (3U)
78797 /*! spdif0_tx_clk_STOP - show clock root status, 1 means clock stopped
78798  */
78799 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_MASK)
78800 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15_MASK (0xFFF0U)
78801 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15_SHIFT (4U)
78802 /*! LPCG_lpcg_spdif0_0_reserved_4_15 - reserved
78803  */
78804 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15_MASK)
78805 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_MASK (0x10000U)
78806 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_SHIFT (16U)
78807 /*! spdif0_ipg_clk_s_HWEN - Hardware Enable
78808  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78809  *  0b1..Enable HW automatic gating
78810  */
78811 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_MASK)
78812 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN_MASK (0x20000U)
78813 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN_SHIFT (17U)
78814 /*! spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN - Software Enable
78815  *  0b0..Disable SW clock regardless of HWEN
78816  *  0b1..Enable SW clock gating
78817  */
78818 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN_MASK)
78819 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_MASK (0x40000U)
78820 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_SHIFT (18U)
78821 /*! LPCG_lpcg_spdif0_0_reserved_18_18 - reserved
78822  */
78823 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_MASK)
78824 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP_MASK (0x80000U)
78825 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP_SHIFT (19U)
78826 /*! spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP - show clock root status, 1 means clock stopped
78827  */
78828 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP_MASK)
78829 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31_MASK (0xFFF00000U)
78830 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31_SHIFT (20U)
78831 /*! LPCG_lpcg_spdif0_0_reserved_20_31 - reserved
78832  */
78833 #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31_MASK)
78834 /*! @} */
78835 
78836 
78837 /*!
78838  * @}
78839  */ /* end of group LPCG_LPCG_SPDIF0_Register_Masks */
78840 
78841 
78842 /* LPCG_LPCG_SPDIF0 - Peripheral instance base addresses */
78843 /** Peripheral ADMA__LPCG_SPDIF0_GCLKW_T0 base address */
78844 #define ADMA__LPCG_SPDIF0_GCLKW_T0_BASE          (0x59420000u)
78845 /** Peripheral ADMA__LPCG_SPDIF0_GCLKW_T0 base pointer */
78846 #define ADMA__LPCG_SPDIF0_GCLKW_T0               ((LPCG_LPCG_SPDIF0_Type *)ADMA__LPCG_SPDIF0_GCLKW_T0_BASE)
78847 /** Array initializer of LPCG_LPCG_SPDIF0 peripheral base addresses */
78848 #define LPCG_LPCG_SPDIF0_BASE_ADDRS              { ADMA__LPCG_SPDIF0_GCLKW_T0_BASE }
78849 /** Array initializer of LPCG_LPCG_SPDIF0 peripheral base pointers */
78850 #define LPCG_LPCG_SPDIF0_BASE_PTRS               { ADMA__LPCG_SPDIF0_GCLKW_T0 }
78851 
78852 /*!
78853  * @}
78854  */ /* end of group LPCG_LPCG_SPDIF0_Peripheral_Access_Layer */
78855 
78856 
78857 /* ----------------------------------------------------------------------------
78858    -- LPCG_LPCG_SPI0 Peripheral Access Layer
78859    ---------------------------------------------------------------------------- */
78860 
78861 /*!
78862  * @addtogroup LPCG_LPCG_SPI0_Peripheral_Access_Layer LPCG_LPCG_SPI0 Peripheral Access Layer
78863  * @{
78864  */
78865 
78866 /** LPCG_LPCG_SPI0 - Register Layout Typedef */
78867 typedef struct {
78868   __IO uint32_t LPCG_LPCG_SPI0_0;                  /**< na, offset: 0x0 */
78869 } LPCG_LPCG_SPI0_Type;
78870 
78871 /* ----------------------------------------------------------------------------
78872    -- LPCG_LPCG_SPI0 Register Masks
78873    ---------------------------------------------------------------------------- */
78874 
78875 /*!
78876  * @addtogroup LPCG_LPCG_SPI0_Register_Masks LPCG_LPCG_SPI0 Register Masks
78877  * @{
78878  */
78879 
78880 /*! @name LPCG_LPCG_SPI0_0 - na */
78881 /*! @{ */
78882 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN_MASK (0x1U)
78883 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN_SHIFT (0U)
78884 /*! spi0_lpspi_div_clk_HWEN - Hardware Enable
78885  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78886  *  0b1..Enable HW automatic gating
78887  */
78888 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN_MASK)
78889 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN_MASK (0x2U)
78890 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN_SHIFT (1U)
78891 /*! spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN - Software Enable
78892  *  0b0..Disable SW clock regardless of HWEN
78893  *  0b1..Enable SW clock gating
78894  */
78895 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN_MASK)
78896 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2_MASK (0x4U)
78897 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2_SHIFT (2U)
78898 /*! LPCG_lpcg_spi0_0_reserved_2_2 - reserved
78899  */
78900 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2_MASK)
78901 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP_MASK (0x8U)
78902 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP_SHIFT (3U)
78903 /*! spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP - show clock root status, 1 means clock stopped
78904  */
78905 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP_MASK)
78906 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15_MASK (0xFFF0U)
78907 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15_SHIFT (4U)
78908 /*! LPCG_lpcg_spi0_0_reserved_4_15 - reserved
78909  */
78910 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15_MASK)
78911 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN_MASK (0x10000U)
78912 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN_SHIFT (16U)
78913 /*! spi0_ipg_clk_s_HWEN - Hardware Enable
78914  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78915  *  0b1..Enable HW automatic gating
78916  */
78917 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN_MASK)
78918 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN_MASK (0x20000U)
78919 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN_SHIFT (17U)
78920 /*! spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN - Software Enable
78921  *  0b0..Disable SW clock regardless of HWEN
78922  *  0b1..Enable SW clock gating
78923  */
78924 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN_MASK)
78925 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18_MASK (0x40000U)
78926 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18_SHIFT (18U)
78927 /*! LPCG_lpcg_spi0_0_reserved_18_18 - reserved
78928  */
78929 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18_MASK)
78930 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP_MASK (0x80000U)
78931 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP_SHIFT (19U)
78932 /*! spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
78933  */
78934 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP_MASK)
78935 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31_MASK (0xFFF00000U)
78936 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31_SHIFT (20U)
78937 /*! LPCG_lpcg_spi0_0_reserved_20_31 - reserved
78938  */
78939 #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31_MASK)
78940 /*! @} */
78941 
78942 
78943 /*!
78944  * @}
78945  */ /* end of group LPCG_LPCG_SPI0_Register_Masks */
78946 
78947 
78948 /* LPCG_LPCG_SPI0 - Peripheral instance base addresses */
78949 /** Peripheral ADMA__LPCG_SPI0_IPG_CLK base address */
78950 #define ADMA__LPCG_SPI0_IPG_CLK_BASE             (0x5A400000u)
78951 /** Peripheral ADMA__LPCG_SPI0_IPG_CLK base pointer */
78952 #define ADMA__LPCG_SPI0_IPG_CLK                  ((LPCG_LPCG_SPI0_Type *)ADMA__LPCG_SPI0_IPG_CLK_BASE)
78953 /** Array initializer of LPCG_LPCG_SPI0 peripheral base addresses */
78954 #define LPCG_LPCG_SPI0_BASE_ADDRS                { ADMA__LPCG_SPI0_IPG_CLK_BASE }
78955 /** Array initializer of LPCG_LPCG_SPI0 peripheral base pointers */
78956 #define LPCG_LPCG_SPI0_BASE_PTRS                 { ADMA__LPCG_SPI0_IPG_CLK }
78957 
78958 /*!
78959  * @}
78960  */ /* end of group LPCG_LPCG_SPI0_Peripheral_Access_Layer */
78961 
78962 
78963 /* ----------------------------------------------------------------------------
78964    -- LPCG_LPCG_SPI1 Peripheral Access Layer
78965    ---------------------------------------------------------------------------- */
78966 
78967 /*!
78968  * @addtogroup LPCG_LPCG_SPI1_Peripheral_Access_Layer LPCG_LPCG_SPI1 Peripheral Access Layer
78969  * @{
78970  */
78971 
78972 /** LPCG_LPCG_SPI1 - Register Layout Typedef */
78973 typedef struct {
78974   __IO uint32_t LPCG_LPCG_SPI1_0;                  /**< na, offset: 0x0 */
78975 } LPCG_LPCG_SPI1_Type;
78976 
78977 /* ----------------------------------------------------------------------------
78978    -- LPCG_LPCG_SPI1 Register Masks
78979    ---------------------------------------------------------------------------- */
78980 
78981 /*!
78982  * @addtogroup LPCG_LPCG_SPI1_Register_Masks LPCG_LPCG_SPI1 Register Masks
78983  * @{
78984  */
78985 
78986 /*! @name LPCG_LPCG_SPI1_0 - na */
78987 /*! @{ */
78988 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN_MASK (0x1U)
78989 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN_SHIFT (0U)
78990 /*! spi1_lpspi_div_clk_HWEN - Hardware Enable
78991  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
78992  *  0b1..Enable HW automatic gating
78993  */
78994 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN_MASK)
78995 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN_MASK (0x2U)
78996 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN_SHIFT (1U)
78997 /*! spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN - Software Enable
78998  *  0b0..Disable SW clock regardless of HWEN
78999  *  0b1..Enable SW clock gating
79000  */
79001 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN_MASK)
79002 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2_MASK (0x4U)
79003 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2_SHIFT (2U)
79004 /*! LPCG_lpcg_spi1_0_reserved_2_2 - reserved
79005  */
79006 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2_MASK)
79007 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP_MASK (0x8U)
79008 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP_SHIFT (3U)
79009 /*! spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP - show clock root status, 1 means clock stopped
79010  */
79011 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP_MASK)
79012 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15_MASK (0xFFF0U)
79013 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15_SHIFT (4U)
79014 /*! LPCG_lpcg_spi1_0_reserved_4_15 - reserved
79015  */
79016 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15_MASK)
79017 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN_MASK (0x10000U)
79018 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN_SHIFT (16U)
79019 /*! spi1_ipg_clk_s_HWEN - Hardware Enable
79020  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79021  *  0b1..Enable HW automatic gating
79022  */
79023 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN_MASK)
79024 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN_MASK (0x20000U)
79025 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN_SHIFT (17U)
79026 /*! spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN - Software Enable
79027  *  0b0..Disable SW clock regardless of HWEN
79028  *  0b1..Enable SW clock gating
79029  */
79030 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN_MASK)
79031 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18_MASK (0x40000U)
79032 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18_SHIFT (18U)
79033 /*! LPCG_lpcg_spi1_0_reserved_18_18 - reserved
79034  */
79035 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18_MASK)
79036 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP_MASK (0x80000U)
79037 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP_SHIFT (19U)
79038 /*! spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
79039  */
79040 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP_MASK)
79041 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31_MASK (0xFFF00000U)
79042 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31_SHIFT (20U)
79043 /*! LPCG_lpcg_spi1_0_reserved_20_31 - reserved
79044  */
79045 #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31_MASK)
79046 /*! @} */
79047 
79048 
79049 /*!
79050  * @}
79051  */ /* end of group LPCG_LPCG_SPI1_Register_Masks */
79052 
79053 
79054 /* LPCG_LPCG_SPI1 - Peripheral instance base addresses */
79055 /** Peripheral ADMA__LPCG_SPI1_IPG_CLK base address */
79056 #define ADMA__LPCG_SPI1_IPG_CLK_BASE             (0x5A410000u)
79057 /** Peripheral ADMA__LPCG_SPI1_IPG_CLK base pointer */
79058 #define ADMA__LPCG_SPI1_IPG_CLK                  ((LPCG_LPCG_SPI1_Type *)ADMA__LPCG_SPI1_IPG_CLK_BASE)
79059 /** Array initializer of LPCG_LPCG_SPI1 peripheral base addresses */
79060 #define LPCG_LPCG_SPI1_BASE_ADDRS                { ADMA__LPCG_SPI1_IPG_CLK_BASE }
79061 /** Array initializer of LPCG_LPCG_SPI1 peripheral base pointers */
79062 #define LPCG_LPCG_SPI1_BASE_PTRS                 { ADMA__LPCG_SPI1_IPG_CLK }
79063 
79064 /*!
79065  * @}
79066  */ /* end of group LPCG_LPCG_SPI1_Peripheral_Access_Layer */
79067 
79068 
79069 /* ----------------------------------------------------------------------------
79070    -- LPCG_LPCG_SPI2 Peripheral Access Layer
79071    ---------------------------------------------------------------------------- */
79072 
79073 /*!
79074  * @addtogroup LPCG_LPCG_SPI2_Peripheral_Access_Layer LPCG_LPCG_SPI2 Peripheral Access Layer
79075  * @{
79076  */
79077 
79078 /** LPCG_LPCG_SPI2 - Register Layout Typedef */
79079 typedef struct {
79080   __IO uint32_t LPCG_LPCG_SPI2_0;                  /**< na, offset: 0x0 */
79081 } LPCG_LPCG_SPI2_Type;
79082 
79083 /* ----------------------------------------------------------------------------
79084    -- LPCG_LPCG_SPI2 Register Masks
79085    ---------------------------------------------------------------------------- */
79086 
79087 /*!
79088  * @addtogroup LPCG_LPCG_SPI2_Register_Masks LPCG_LPCG_SPI2 Register Masks
79089  * @{
79090  */
79091 
79092 /*! @name LPCG_LPCG_SPI2_0 - na */
79093 /*! @{ */
79094 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN_MASK (0x1U)
79095 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN_SHIFT (0U)
79096 /*! spi2_lpspi_div_clk_HWEN - Hardware Enable
79097  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79098  *  0b1..Enable HW automatic gating
79099  */
79100 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN_MASK)
79101 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN_MASK (0x2U)
79102 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN_SHIFT (1U)
79103 /*! spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN - Software Enable
79104  *  0b0..Disable SW clock regardless of HWEN
79105  *  0b1..Enable SW clock gating
79106  */
79107 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN_MASK)
79108 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2_MASK (0x4U)
79109 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2_SHIFT (2U)
79110 /*! LPCG_lpcg_spi2_0_reserved_2_2 - reserved
79111  */
79112 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2_MASK)
79113 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP_MASK (0x8U)
79114 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP_SHIFT (3U)
79115 /*! spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP - show clock root status, 1 means clock stopped
79116  */
79117 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP_MASK)
79118 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15_MASK (0xFFF0U)
79119 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15_SHIFT (4U)
79120 /*! LPCG_lpcg_spi2_0_reserved_4_15 - reserved
79121  */
79122 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15_MASK)
79123 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN_MASK (0x10000U)
79124 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN_SHIFT (16U)
79125 /*! spi2_ipg_clk_s_HWEN - Hardware Enable
79126  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79127  *  0b1..Enable HW automatic gating
79128  */
79129 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN_MASK)
79130 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN_MASK (0x20000U)
79131 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN_SHIFT (17U)
79132 /*! spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN - Software Enable
79133  *  0b0..Disable SW clock regardless of HWEN
79134  *  0b1..Enable SW clock gating
79135  */
79136 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN_MASK)
79137 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18_MASK (0x40000U)
79138 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18_SHIFT (18U)
79139 /*! LPCG_lpcg_spi2_0_reserved_18_18 - reserved
79140  */
79141 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18_MASK)
79142 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP_MASK (0x80000U)
79143 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP_SHIFT (19U)
79144 /*! spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
79145  */
79146 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP_MASK)
79147 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31_MASK (0xFFF00000U)
79148 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31_SHIFT (20U)
79149 /*! LPCG_lpcg_spi2_0_reserved_20_31 - reserved
79150  */
79151 #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31_MASK)
79152 /*! @} */
79153 
79154 
79155 /*!
79156  * @}
79157  */ /* end of group LPCG_LPCG_SPI2_Register_Masks */
79158 
79159 
79160 /* LPCG_LPCG_SPI2 - Peripheral instance base addresses */
79161 /** Peripheral ADMA__LPCG_SPI2_IPG_CLK base address */
79162 #define ADMA__LPCG_SPI2_IPG_CLK_BASE             (0x5A420000u)
79163 /** Peripheral ADMA__LPCG_SPI2_IPG_CLK base pointer */
79164 #define ADMA__LPCG_SPI2_IPG_CLK                  ((LPCG_LPCG_SPI2_Type *)ADMA__LPCG_SPI2_IPG_CLK_BASE)
79165 /** Array initializer of LPCG_LPCG_SPI2 peripheral base addresses */
79166 #define LPCG_LPCG_SPI2_BASE_ADDRS                { ADMA__LPCG_SPI2_IPG_CLK_BASE }
79167 /** Array initializer of LPCG_LPCG_SPI2 peripheral base pointers */
79168 #define LPCG_LPCG_SPI2_BASE_PTRS                 { ADMA__LPCG_SPI2_IPG_CLK }
79169 
79170 /*!
79171  * @}
79172  */ /* end of group LPCG_LPCG_SPI2_Peripheral_Access_Layer */
79173 
79174 
79175 /* ----------------------------------------------------------------------------
79176    -- LPCG_LPCG_SPI3 Peripheral Access Layer
79177    ---------------------------------------------------------------------------- */
79178 
79179 /*!
79180  * @addtogroup LPCG_LPCG_SPI3_Peripheral_Access_Layer LPCG_LPCG_SPI3 Peripheral Access Layer
79181  * @{
79182  */
79183 
79184 /** LPCG_LPCG_SPI3 - Register Layout Typedef */
79185 typedef struct {
79186   __IO uint32_t LPCG_LPCG_SPI3_0;                  /**< na, offset: 0x0 */
79187 } LPCG_LPCG_SPI3_Type;
79188 
79189 /* ----------------------------------------------------------------------------
79190    -- LPCG_LPCG_SPI3 Register Masks
79191    ---------------------------------------------------------------------------- */
79192 
79193 /*!
79194  * @addtogroup LPCG_LPCG_SPI3_Register_Masks LPCG_LPCG_SPI3 Register Masks
79195  * @{
79196  */
79197 
79198 /*! @name LPCG_LPCG_SPI3_0 - na */
79199 /*! @{ */
79200 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN_MASK (0x1U)
79201 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN_SHIFT (0U)
79202 /*! spi3_lpspi_div_clk_HWEN - Hardware Enable
79203  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79204  *  0b1..Enable HW automatic gating
79205  */
79206 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN_MASK)
79207 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN_MASK (0x2U)
79208 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN_SHIFT (1U)
79209 /*! spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN - Software Enable
79210  *  0b0..Disable SW clock regardless of HWEN
79211  *  0b1..Enable SW clock gating
79212  */
79213 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN_MASK)
79214 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2_MASK (0x4U)
79215 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2_SHIFT (2U)
79216 /*! LPCG_lpcg_spi3_0_reserved_2_2 - reserved
79217  */
79218 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2_MASK)
79219 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP_MASK (0x8U)
79220 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP_SHIFT (3U)
79221 /*! spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP - show clock root status, 1 means clock stopped
79222  */
79223 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP_MASK)
79224 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15_MASK (0xFFF0U)
79225 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15_SHIFT (4U)
79226 /*! LPCG_lpcg_spi3_0_reserved_4_15 - reserved
79227  */
79228 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15_MASK)
79229 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN_MASK (0x10000U)
79230 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN_SHIFT (16U)
79231 /*! spi3_ipg_clk_s_HWEN - Hardware Enable
79232  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79233  *  0b1..Enable HW automatic gating
79234  */
79235 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN_MASK)
79236 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN_MASK (0x20000U)
79237 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN_SHIFT (17U)
79238 /*! spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN - Software Enable
79239  *  0b0..Disable SW clock regardless of HWEN
79240  *  0b1..Enable SW clock gating
79241  */
79242 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN_MASK)
79243 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18_MASK (0x40000U)
79244 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18_SHIFT (18U)
79245 /*! LPCG_lpcg_spi3_0_reserved_18_18 - reserved
79246  */
79247 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18_MASK)
79248 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP_MASK (0x80000U)
79249 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP_SHIFT (19U)
79250 /*! spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
79251  */
79252 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP_MASK)
79253 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31_MASK (0xFFF00000U)
79254 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31_SHIFT (20U)
79255 /*! LPCG_lpcg_spi3_0_reserved_20_31 - reserved
79256  */
79257 #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31_MASK)
79258 /*! @} */
79259 
79260 
79261 /*!
79262  * @}
79263  */ /* end of group LPCG_LPCG_SPI3_Register_Masks */
79264 
79265 
79266 /* LPCG_LPCG_SPI3 - Peripheral instance base addresses */
79267 /** Peripheral ADMA__LPCG_SPI3_IPG_CLK base address */
79268 #define ADMA__LPCG_SPI3_IPG_CLK_BASE             (0x5A430000u)
79269 /** Peripheral ADMA__LPCG_SPI3_IPG_CLK base pointer */
79270 #define ADMA__LPCG_SPI3_IPG_CLK                  ((LPCG_LPCG_SPI3_Type *)ADMA__LPCG_SPI3_IPG_CLK_BASE)
79271 /** Array initializer of LPCG_LPCG_SPI3 peripheral base addresses */
79272 #define LPCG_LPCG_SPI3_BASE_ADDRS                { ADMA__LPCG_SPI3_IPG_CLK_BASE }
79273 /** Array initializer of LPCG_LPCG_SPI3 peripheral base pointers */
79274 #define LPCG_LPCG_SPI3_BASE_PTRS                 { ADMA__LPCG_SPI3_IPG_CLK }
79275 
79276 /*!
79277  * @}
79278  */ /* end of group LPCG_LPCG_SPI3_Peripheral_Access_Layer */
79279 
79280 
79281 /* ----------------------------------------------------------------------------
79282    -- LPCG_LPCG_UART0 Peripheral Access Layer
79283    ---------------------------------------------------------------------------- */
79284 
79285 /*!
79286  * @addtogroup LPCG_LPCG_UART0_Peripheral_Access_Layer LPCG_LPCG_UART0 Peripheral Access Layer
79287  * @{
79288  */
79289 
79290 /** LPCG_LPCG_UART0 - Register Layout Typedef */
79291 typedef struct {
79292   __IO uint32_t LPCG_LPCG_UART0_0;                 /**< na, offset: 0x0 */
79293 } LPCG_LPCG_UART0_Type;
79294 
79295 /* ----------------------------------------------------------------------------
79296    -- LPCG_LPCG_UART0 Register Masks
79297    ---------------------------------------------------------------------------- */
79298 
79299 /*!
79300  * @addtogroup LPCG_LPCG_UART0_Register_Masks LPCG_LPCG_UART0 Register Masks
79301  * @{
79302  */
79303 
79304 /*! @name LPCG_LPCG_UART0_0 - na */
79305 /*! @{ */
79306 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
79307 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
79308 /*! uart0_lpuart_baud_gated_clk_HWEN - Hardware Enable
79309  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79310  *  0b1..Enable HW automatic gating
79311  */
79312 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN_MASK)
79313 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
79314 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
79315 /*! uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN - Software Enable
79316  *  0b0..Disable SW clock regardless of HWEN
79317  *  0b1..Enable SW clock gating
79318  */
79319 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN_MASK)
79320 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2_MASK (0x4U)
79321 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2_SHIFT (2U)
79322 /*! LPCG_lpcg_uart0_0_reserved_2_2 - reserved
79323  */
79324 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2_MASK)
79325 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP_MASK (0x8U)
79326 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP_SHIFT (3U)
79327 /*! uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
79328  */
79329 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP_MASK)
79330 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15_MASK (0xFFF0U)
79331 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15_SHIFT (4U)
79332 /*! LPCG_lpcg_uart0_0_reserved_4_15 - reserved
79333  */
79334 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15_MASK)
79335 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN_MASK (0x10000U)
79336 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN_SHIFT (16U)
79337 /*! uart0_ipg_clk_s_HWEN - Hardware Enable
79338  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79339  *  0b1..Enable HW automatic gating
79340  */
79341 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN_MASK)
79342 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN_MASK (0x20000U)
79343 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN_SHIFT (17U)
79344 /*! uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN - Software Enable
79345  *  0b0..Disable SW clock regardless of HWEN
79346  *  0b1..Enable SW clock gating
79347  */
79348 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN_MASK)
79349 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18_MASK (0x40000U)
79350 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18_SHIFT (18U)
79351 /*! LPCG_lpcg_uart0_0_reserved_18_18 - reserved
79352  */
79353 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18_MASK)
79354 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP_MASK (0x80000U)
79355 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP_SHIFT (19U)
79356 /*! uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
79357  */
79358 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP_MASK)
79359 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31_MASK (0xFFF00000U)
79360 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31_SHIFT (20U)
79361 /*! LPCG_lpcg_uart0_0_reserved_20_31 - reserved
79362  */
79363 #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31_MASK)
79364 /*! @} */
79365 
79366 
79367 /*!
79368  * @}
79369  */ /* end of group LPCG_LPCG_UART0_Register_Masks */
79370 
79371 
79372 /* LPCG_LPCG_UART0 - Peripheral instance base addresses */
79373 /** Peripheral ADMA__LPCG_UART0_IPG_CLK base address */
79374 #define ADMA__LPCG_UART0_IPG_CLK_BASE            (0x5A460000u)
79375 /** Peripheral ADMA__LPCG_UART0_IPG_CLK base pointer */
79376 #define ADMA__LPCG_UART0_IPG_CLK                 ((LPCG_LPCG_UART0_Type *)ADMA__LPCG_UART0_IPG_CLK_BASE)
79377 /** Array initializer of LPCG_LPCG_UART0 peripheral base addresses */
79378 #define LPCG_LPCG_UART0_BASE_ADDRS               { ADMA__LPCG_UART0_IPG_CLK_BASE }
79379 /** Array initializer of LPCG_LPCG_UART0 peripheral base pointers */
79380 #define LPCG_LPCG_UART0_BASE_PTRS                { ADMA__LPCG_UART0_IPG_CLK }
79381 
79382 /*!
79383  * @}
79384  */ /* end of group LPCG_LPCG_UART0_Peripheral_Access_Layer */
79385 
79386 
79387 /* ----------------------------------------------------------------------------
79388    -- LPCG_LPCG_UART1 Peripheral Access Layer
79389    ---------------------------------------------------------------------------- */
79390 
79391 /*!
79392  * @addtogroup LPCG_LPCG_UART1_Peripheral_Access_Layer LPCG_LPCG_UART1 Peripheral Access Layer
79393  * @{
79394  */
79395 
79396 /** LPCG_LPCG_UART1 - Register Layout Typedef */
79397 typedef struct {
79398   __IO uint32_t LPCG_LPCG_UART1_0;                 /**< na, offset: 0x0 */
79399 } LPCG_LPCG_UART1_Type;
79400 
79401 /* ----------------------------------------------------------------------------
79402    -- LPCG_LPCG_UART1 Register Masks
79403    ---------------------------------------------------------------------------- */
79404 
79405 /*!
79406  * @addtogroup LPCG_LPCG_UART1_Register_Masks LPCG_LPCG_UART1 Register Masks
79407  * @{
79408  */
79409 
79410 /*! @name LPCG_LPCG_UART1_0 - na */
79411 /*! @{ */
79412 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
79413 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
79414 /*! uart1_lpuart_baud_gated_clk_HWEN - Hardware Enable
79415  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79416  *  0b1..Enable HW automatic gating
79417  */
79418 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN_MASK)
79419 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
79420 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
79421 /*! uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN - Software Enable
79422  *  0b0..Disable SW clock regardless of HWEN
79423  *  0b1..Enable SW clock gating
79424  */
79425 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN_MASK)
79426 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2_MASK (0x4U)
79427 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2_SHIFT (2U)
79428 /*! LPCG_lpcg_uart1_0_reserved_2_2 - reserved
79429  */
79430 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2_MASK)
79431 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
79432 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
79433 /*! uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
79434  */
79435 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP_MASK)
79436 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15_MASK (0xFFF0U)
79437 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15_SHIFT (4U)
79438 /*! LPCG_lpcg_uart1_0_reserved_4_15 - reserved
79439  */
79440 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15_MASK)
79441 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN_MASK (0x10000U)
79442 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN_SHIFT (16U)
79443 /*! uart1_ipg_clk_s_HWEN - Hardware Enable
79444  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79445  *  0b1..Enable HW automatic gating
79446  */
79447 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN_MASK)
79448 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN_MASK (0x20000U)
79449 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN_SHIFT (17U)
79450 /*! uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN - Software Enable
79451  *  0b0..Disable SW clock regardless of HWEN
79452  *  0b1..Enable SW clock gating
79453  */
79454 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN_MASK)
79455 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18_MASK (0x40000U)
79456 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18_SHIFT (18U)
79457 /*! LPCG_lpcg_uart1_0_reserved_18_18 - reserved
79458  */
79459 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18_MASK)
79460 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP_MASK (0x80000U)
79461 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP_SHIFT (19U)
79462 /*! uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
79463  */
79464 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP_MASK)
79465 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31_MASK (0xFFF00000U)
79466 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31_SHIFT (20U)
79467 /*! LPCG_lpcg_uart1_0_reserved_20_31 - reserved
79468  */
79469 #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31_MASK)
79470 /*! @} */
79471 
79472 
79473 /*!
79474  * @}
79475  */ /* end of group LPCG_LPCG_UART1_Register_Masks */
79476 
79477 
79478 /* LPCG_LPCG_UART1 - Peripheral instance base addresses */
79479 /** Peripheral ADMA__LPCG_UART1_IPG_CLK base address */
79480 #define ADMA__LPCG_UART1_IPG_CLK_BASE            (0x5A470000u)
79481 /** Peripheral ADMA__LPCG_UART1_IPG_CLK base pointer */
79482 #define ADMA__LPCG_UART1_IPG_CLK                 ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
79483 /** Array initializer of LPCG_LPCG_UART1 peripheral base addresses */
79484 #define LPCG_LPCG_UART1_BASE_ADDRS               { ADMA__LPCG_UART1_IPG_CLK_BASE }
79485 /** Array initializer of LPCG_LPCG_UART1 peripheral base pointers */
79486 #define LPCG_LPCG_UART1_BASE_PTRS                { ADMA__LPCG_UART1_IPG_CLK }
79487 
79488 /*!
79489  * @}
79490  */ /* end of group LPCG_LPCG_UART1_Peripheral_Access_Layer */
79491 
79492 
79493 /* ----------------------------------------------------------------------------
79494    -- LPCG_LPCG_UART2 Peripheral Access Layer
79495    ---------------------------------------------------------------------------- */
79496 
79497 /*!
79498  * @addtogroup LPCG_LPCG_UART2_Peripheral_Access_Layer LPCG_LPCG_UART2 Peripheral Access Layer
79499  * @{
79500  */
79501 
79502 /** LPCG_LPCG_UART2 - Register Layout Typedef */
79503 typedef struct {
79504   __IO uint32_t LPCG_LPCG_UART2_0;                 /**< na, offset: 0x0 */
79505 } LPCG_LPCG_UART2_Type;
79506 
79507 /* ----------------------------------------------------------------------------
79508    -- LPCG_LPCG_UART2 Register Masks
79509    ---------------------------------------------------------------------------- */
79510 
79511 /*!
79512  * @addtogroup LPCG_LPCG_UART2_Register_Masks LPCG_LPCG_UART2 Register Masks
79513  * @{
79514  */
79515 
79516 /*! @name LPCG_LPCG_UART2_0 - na */
79517 /*! @{ */
79518 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
79519 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
79520 /*! uart2_lpuart_baud_gated_clk_HWEN - Hardware Enable
79521  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79522  *  0b1..Enable HW automatic gating
79523  */
79524 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN_MASK)
79525 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
79526 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
79527 /*! uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN - Software Enable
79528  *  0b0..Disable SW clock regardless of HWEN
79529  *  0b1..Enable SW clock gating
79530  */
79531 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN_MASK)
79532 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2_MASK (0x4U)
79533 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2_SHIFT (2U)
79534 /*! LPCG_lpcg_uart2_0_reserved_2_2 - reserved
79535  */
79536 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2_MASK)
79537 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP_MASK (0x8U)
79538 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP_SHIFT (3U)
79539 /*! uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
79540  */
79541 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP_MASK)
79542 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15_MASK (0xFFF0U)
79543 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15_SHIFT (4U)
79544 /*! LPCG_lpcg_uart2_0_reserved_4_15 - reserved
79545  */
79546 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15_MASK)
79547 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN_MASK (0x10000U)
79548 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN_SHIFT (16U)
79549 /*! uart2_ipg_clk_s_HWEN - Hardware Enable
79550  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79551  *  0b1..Enable HW automatic gating
79552  */
79553 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN_MASK)
79554 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN_MASK (0x20000U)
79555 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN_SHIFT (17U)
79556 /*! uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN - Software Enable
79557  *  0b0..Disable SW clock regardless of HWEN
79558  *  0b1..Enable SW clock gating
79559  */
79560 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN_MASK)
79561 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18_MASK (0x40000U)
79562 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18_SHIFT (18U)
79563 /*! LPCG_lpcg_uart2_0_reserved_18_18 - reserved
79564  */
79565 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18_MASK)
79566 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP_MASK (0x80000U)
79567 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP_SHIFT (19U)
79568 /*! uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
79569  */
79570 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP_MASK)
79571 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31_MASK (0xFFF00000U)
79572 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31_SHIFT (20U)
79573 /*! LPCG_lpcg_uart2_0_reserved_20_31 - reserved
79574  */
79575 #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31_MASK)
79576 /*! @} */
79577 
79578 
79579 /*!
79580  * @}
79581  */ /* end of group LPCG_LPCG_UART2_Register_Masks */
79582 
79583 
79584 /* LPCG_LPCG_UART2 - Peripheral instance base addresses */
79585 /** Peripheral ADMA__LPCG_UART2_IPG_CLK base address */
79586 #define ADMA__LPCG_UART2_IPG_CLK_BASE            (0x5A480000u)
79587 /** Peripheral ADMA__LPCG_UART2_IPG_CLK base pointer */
79588 #define ADMA__LPCG_UART2_IPG_CLK                 ((LPCG_LPCG_UART2_Type *)ADMA__LPCG_UART2_IPG_CLK_BASE)
79589 /** Array initializer of LPCG_LPCG_UART2 peripheral base addresses */
79590 #define LPCG_LPCG_UART2_BASE_ADDRS               { ADMA__LPCG_UART2_IPG_CLK_BASE }
79591 /** Array initializer of LPCG_LPCG_UART2 peripheral base pointers */
79592 #define LPCG_LPCG_UART2_BASE_PTRS                { ADMA__LPCG_UART2_IPG_CLK }
79593 
79594 /*!
79595  * @}
79596  */ /* end of group LPCG_LPCG_UART2_Peripheral_Access_Layer */
79597 
79598 
79599 /* ----------------------------------------------------------------------------
79600    -- LPCG_LPCG_UART3 Peripheral Access Layer
79601    ---------------------------------------------------------------------------- */
79602 
79603 /*!
79604  * @addtogroup LPCG_LPCG_UART3_Peripheral_Access_Layer LPCG_LPCG_UART3 Peripheral Access Layer
79605  * @{
79606  */
79607 
79608 /** LPCG_LPCG_UART3 - Register Layout Typedef */
79609 typedef struct {
79610   __IO uint32_t LPCG_LPCG_UART3_0;                 /**< na, offset: 0x0 */
79611 } LPCG_LPCG_UART3_Type;
79612 
79613 /* ----------------------------------------------------------------------------
79614    -- LPCG_LPCG_UART3 Register Masks
79615    ---------------------------------------------------------------------------- */
79616 
79617 /*!
79618  * @addtogroup LPCG_LPCG_UART3_Register_Masks LPCG_LPCG_UART3 Register Masks
79619  * @{
79620  */
79621 
79622 /*! @name LPCG_LPCG_UART3_0 - na */
79623 /*! @{ */
79624 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
79625 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
79626 /*! uart3_lpuart_baud_gated_clk_HWEN - Hardware Enable
79627  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79628  *  0b1..Enable HW automatic gating
79629  */
79630 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN_MASK)
79631 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
79632 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
79633 /*! uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN - Software Enable
79634  *  0b0..Disable SW clock regardless of HWEN
79635  *  0b1..Enable SW clock gating
79636  */
79637 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN_MASK)
79638 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2_MASK (0x4U)
79639 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2_SHIFT (2U)
79640 /*! LPCG_lpcg_uart3_0_reserved_2_2 - reserved
79641  */
79642 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2_MASK)
79643 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP_MASK (0x8U)
79644 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP_SHIFT (3U)
79645 /*! uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
79646  */
79647 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP_MASK)
79648 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15_MASK (0xFFF0U)
79649 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15_SHIFT (4U)
79650 /*! LPCG_lpcg_uart3_0_reserved_4_15 - reserved
79651  */
79652 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15_MASK)
79653 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN_MASK (0x10000U)
79654 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN_SHIFT (16U)
79655 /*! uart3_ipg_clk_s_HWEN - Hardware Enable
79656  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79657  *  0b1..Enable HW automatic gating
79658  */
79659 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN_MASK)
79660 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN_MASK (0x20000U)
79661 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN_SHIFT (17U)
79662 /*! uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN - Software Enable
79663  *  0b0..Disable SW clock regardless of HWEN
79664  *  0b1..Enable SW clock gating
79665  */
79666 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN_MASK)
79667 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18_MASK (0x40000U)
79668 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18_SHIFT (18U)
79669 /*! LPCG_lpcg_uart3_0_reserved_18_18 - reserved
79670  */
79671 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18_MASK)
79672 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP_MASK (0x80000U)
79673 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP_SHIFT (19U)
79674 /*! uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
79675  */
79676 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP_MASK)
79677 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31_MASK (0xFFF00000U)
79678 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31_SHIFT (20U)
79679 /*! LPCG_lpcg_uart3_0_reserved_20_31 - reserved
79680  */
79681 #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31_MASK)
79682 /*! @} */
79683 
79684 
79685 /*!
79686  * @}
79687  */ /* end of group LPCG_LPCG_UART3_Register_Masks */
79688 
79689 
79690 /* LPCG_LPCG_UART3 - Peripheral instance base addresses */
79691 /** Peripheral ADMA__LPCG_UART3_IPG_CLK base address */
79692 #define ADMA__LPCG_UART3_IPG_CLK_BASE            (0x5A490000u)
79693 /** Peripheral ADMA__LPCG_UART3_IPG_CLK base pointer */
79694 #define ADMA__LPCG_UART3_IPG_CLK                 ((LPCG_LPCG_UART3_Type *)ADMA__LPCG_UART3_IPG_CLK_BASE)
79695 /** Array initializer of LPCG_LPCG_UART3 peripheral base addresses */
79696 #define LPCG_LPCG_UART3_BASE_ADDRS               { ADMA__LPCG_UART3_IPG_CLK_BASE }
79697 /** Array initializer of LPCG_LPCG_UART3 peripheral base pointers */
79698 #define LPCG_LPCG_UART3_BASE_PTRS                { ADMA__LPCG_UART3_IPG_CLK }
79699 
79700 /*!
79701  * @}
79702  */ /* end of group LPCG_LPCG_UART3_Peripheral_Access_Layer */
79703 
79704 
79705 /* ----------------------------------------------------------------------------
79706    -- LPCG_LPI2C Peripheral Access Layer
79707    ---------------------------------------------------------------------------- */
79708 
79709 /*!
79710  * @addtogroup LPCG_LPI2C_Peripheral_Access_Layer LPCG_LPI2C Peripheral Access Layer
79711  * @{
79712  */
79713 
79714 /** LPCG_LPI2C - Register Layout Typedef */
79715 typedef struct {
79716   __IO uint32_t LPCG_LPI2C_0;                      /**< na, offset: 0x0 */
79717 } LPCG_LPI2C_Type;
79718 
79719 /* ----------------------------------------------------------------------------
79720    -- LPCG_LPI2C Register Masks
79721    ---------------------------------------------------------------------------- */
79722 
79723 /*!
79724  * @addtogroup LPCG_LPI2C_Register_Masks LPCG_LPI2C Register Masks
79725  * @{
79726  */
79727 
79728 /*! @name LPCG_LPI2C_0 - na */
79729 /*! @{ */
79730 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
79731 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
79732 /*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable
79733  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79734  *  0b1..Enable HW automatic gating
79735  */
79736 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK)
79737 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
79738 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
79739 /*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable
79740  *  0b0..Disable SW clock regardless of HWEN
79741  *  0b1..Enable SW clock gating
79742  */
79743 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
79744 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U)
79745 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U)
79746 /*! LPCG_LPI2C_0_reserved_2_2 - reserved
79747  */
79748 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK)
79749 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
79750 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
79751 /*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
79752  */
79753 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
79754 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U)
79755 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U)
79756 /*! LPCG_LPI2C_0_reserved_4_4 - reserved
79757  */
79758 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK)
79759 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U)
79760 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U)
79761 /*! lpi2c1_ipg_clk_SWEN - Software Enable
79762  *  0b0..Disable SW clock regardless of HWEN
79763  *  0b1..Enable SW clock gating
79764  */
79765 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK)
79766 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U)
79767 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U)
79768 /*! LPCG_LPI2C_0_reserved_6_6 - reserved
79769  */
79770 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK)
79771 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U)
79772 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U)
79773 /*! lpi2c1_ipg_clk_STOP - show clock root status, 1 means clock stopped
79774  */
79775 #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK)
79776 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U)
79777 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U)
79778 /*! LPCG_LPI2C_0_reserved_8_31 - reserved
79779  */
79780 #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK)
79781 /*! @} */
79782 
79783 
79784 /*!
79785  * @}
79786  */ /* end of group LPCG_LPI2C_Register_Masks */
79787 
79788 
79789 /* LPCG_LPI2C - Peripheral instance base addresses */
79790 /** Peripheral SCU__LPCG_LPI2C base address */
79791 #define SCU__LPCG_LPI2C_BASE                     (0x33630000u)
79792 /** Peripheral SCU__LPCG_LPI2C base pointer */
79793 #define SCU__LPCG_LPI2C                          ((LPCG_LPI2C_Type *)SCU__LPCG_LPI2C_BASE)
79794 /** Array initializer of LPCG_LPI2C peripheral base addresses */
79795 #define LPCG_LPI2C_BASE_ADDRS                    { SCU__LPCG_LPI2C_BASE }
79796 /** Array initializer of LPCG_LPI2C peripheral base pointers */
79797 #define LPCG_LPI2C_BASE_PTRS                     { SCU__LPCG_LPI2C }
79798 
79799 /*!
79800  * @}
79801  */ /* end of group LPCG_LPI2C_Peripheral_Access_Layer */
79802 
79803 
79804 /* ----------------------------------------------------------------------------
79805    -- LPCG_LPIT Peripheral Access Layer
79806    ---------------------------------------------------------------------------- */
79807 
79808 /*!
79809  * @addtogroup LPCG_LPIT_Peripheral_Access_Layer LPCG_LPIT Peripheral Access Layer
79810  * @{
79811  */
79812 
79813 /** LPCG_LPIT - Register Layout Typedef */
79814 typedef struct {
79815   __IO uint32_t LPCG_LPIT_0;                       /**< na, offset: 0x0 */
79816 } LPCG_LPIT_Type;
79817 
79818 /* ----------------------------------------------------------------------------
79819    -- LPCG_LPIT Register Masks
79820    ---------------------------------------------------------------------------- */
79821 
79822 /*!
79823  * @addtogroup LPCG_LPIT_Register_Masks LPCG_LPIT Register Masks
79824  * @{
79825  */
79826 
79827 /*! @name LPCG_LPIT_0 - na */
79828 /*! @{ */
79829 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U)
79830 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U)
79831 /*! lpit1_ipg_per_clk_HWEN - Hardware Enable
79832  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79833  *  0b1..Enable HW automatic gating
79834  */
79835 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK)
79836 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U)
79837 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U)
79838 /*! lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN - Software Enable
79839  *  0b0..Disable SW clock regardless of HWEN
79840  *  0b1..Enable SW clock gating
79841  */
79842 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK)
79843 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U)
79844 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U)
79845 /*! LPCG_LPIT_0_reserved_2_2 - reserved
79846  */
79847 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK)
79848 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U)
79849 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U)
79850 /*! lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP - show clock root status, 1 means clock stopped
79851  */
79852 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK)
79853 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U)
79854 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U)
79855 /*! LPCG_LPIT_0_reserved_4_4 - reserved
79856  */
79857 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK)
79858 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U)
79859 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U)
79860 /*! lpit1_ipg_clk_SWEN - Software Enable
79861  *  0b0..Disable SW clock regardless of HWEN
79862  *  0b1..Enable SW clock gating
79863  */
79864 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK)
79865 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U)
79866 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U)
79867 /*! LPCG_LPIT_0_reserved_6_6 - reserved
79868  */
79869 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK)
79870 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U)
79871 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U)
79872 /*! lpit1_ipg_clk_STOP - show clock root status, 1 means clock stopped
79873  */
79874 #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK)
79875 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U)
79876 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U)
79877 /*! LPCG_LPIT_0_reserved_8_31 - reserved
79878  */
79879 #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK)
79880 /*! @} */
79881 
79882 
79883 /*!
79884  * @}
79885  */ /* end of group LPCG_LPIT_Register_Masks */
79886 
79887 
79888 /* LPCG_LPIT - Peripheral instance base addresses */
79889 /** Peripheral SCU__LPCG_LPIT base address */
79890 #define SCU__LPCG_LPIT_BASE                      (0x33610000u)
79891 /** Peripheral SCU__LPCG_LPIT base pointer */
79892 #define SCU__LPCG_LPIT                           ((LPCG_LPIT_Type *)SCU__LPCG_LPIT_BASE)
79893 /** Array initializer of LPCG_LPIT peripheral base addresses */
79894 #define LPCG_LPIT_BASE_ADDRS                     { SCU__LPCG_LPIT_BASE }
79895 /** Array initializer of LPCG_LPIT peripheral base pointers */
79896 #define LPCG_LPIT_BASE_PTRS                      { SCU__LPCG_LPIT }
79897 
79898 /*!
79899  * @}
79900  */ /* end of group LPCG_LPIT_Peripheral_Access_Layer */
79901 
79902 
79903 /* ----------------------------------------------------------------------------
79904    -- LPCG_LPUART Peripheral Access Layer
79905    ---------------------------------------------------------------------------- */
79906 
79907 /*!
79908  * @addtogroup LPCG_LPUART_Peripheral_Access_Layer LPCG_LPUART Peripheral Access Layer
79909  * @{
79910  */
79911 
79912 /** LPCG_LPUART - Register Layout Typedef */
79913 typedef struct {
79914   __IO uint32_t LPCG_LPUART_0;                     /**< na, offset: 0x0 */
79915 } LPCG_LPUART_Type;
79916 
79917 /* ----------------------------------------------------------------------------
79918    -- LPCG_LPUART Register Masks
79919    ---------------------------------------------------------------------------- */
79920 
79921 /*!
79922  * @addtogroup LPCG_LPUART_Register_Masks LPCG_LPUART Register Masks
79923  * @{
79924  */
79925 
79926 /*! @name LPCG_LPUART_0 - na */
79927 /*! @{ */
79928 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
79929 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
79930 /*! lpuart1_lpuart_baud_gated_clk_HWEN - Hardware Enable
79931  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
79932  *  0b1..Enable HW automatic gating
79933  */
79934 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK)
79935 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
79936 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
79937 /*! lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN - Software Enable
79938  *  0b0..Disable SW clock regardless of HWEN
79939  *  0b1..Enable SW clock gating
79940  */
79941 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK)
79942 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U)
79943 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U)
79944 /*! LPCG_LPUART_0_reserved_2_2 - reserved
79945  */
79946 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK)
79947 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
79948 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
79949 /*! lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
79950  */
79951 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK)
79952 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U)
79953 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U)
79954 /*! LPCG_LPUART_0_reserved_4_4 - reserved
79955  */
79956 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK)
79957 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U)
79958 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U)
79959 /*! lpuart1_ipg_clk_SWEN - Software Enable
79960  *  0b0..Disable SW clock regardless of HWEN
79961  *  0b1..Enable SW clock gating
79962  */
79963 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK)
79964 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U)
79965 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U)
79966 /*! LPCG_LPUART_0_reserved_6_6 - reserved
79967  */
79968 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK)
79969 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U)
79970 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U)
79971 /*! lpuart1_ipg_clk_STOP - show clock root status, 1 means clock stopped
79972  */
79973 #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK)
79974 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U)
79975 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U)
79976 /*! LPCG_LPUART_0_reserved_8_31 - reserved
79977  */
79978 #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK)
79979 /*! @} */
79980 
79981 
79982 /*!
79983  * @}
79984  */ /* end of group LPCG_LPUART_Register_Masks */
79985 
79986 
79987 /* LPCG_LPUART - Peripheral instance base addresses */
79988 /** Peripheral SCU__LPCG_LPUART base address */
79989 #define SCU__LPCG_LPUART_BASE                    (0x33620000u)
79990 /** Peripheral SCU__LPCG_LPUART base pointer */
79991 #define SCU__LPCG_LPUART                         ((LPCG_LPUART_Type *)SCU__LPCG_LPUART_BASE)
79992 /** Array initializer of LPCG_LPUART peripheral base addresses */
79993 #define LPCG_LPUART_BASE_ADDRS                   { SCU__LPCG_LPUART_BASE }
79994 /** Array initializer of LPCG_LPUART peripheral base pointers */
79995 #define LPCG_LPUART_BASE_PTRS                    { SCU__LPCG_LPUART }
79996 
79997 /*!
79998  * @}
79999  */ /* end of group LPCG_LPUART_Peripheral_Access_Layer */
80000 
80001 
80002 /* ----------------------------------------------------------------------------
80003    -- LPCG_MFD Peripheral Access Layer
80004    ---------------------------------------------------------------------------- */
80005 
80006 /*!
80007  * @addtogroup LPCG_MFD_Peripheral_Access_Layer LPCG_MFD Peripheral Access Layer
80008  * @{
80009  */
80010 
80011 /** LPCG_MFD - Register Layout Typedef */
80012 typedef struct {
80013   __IO uint32_t LPCG_MFD_0;                        /**< na, offset: 0x0 */
80014 } LPCG_MFD_Type;
80015 
80016 /* ----------------------------------------------------------------------------
80017    -- LPCG_MFD Register Masks
80018    ---------------------------------------------------------------------------- */
80019 
80020 /*!
80021  * @addtogroup LPCG_MFD_Register_Masks LPCG_MFD Register Masks
80022  * @{
80023  */
80024 
80025 /*! @name LPCG_MFD_0 - na */
80026 /*! @{ */
80027 #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0_MASK (0x1U)
80028 #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0_SHIFT (0U)
80029 /*! LPCG_MFD_0_reserved_0_0 - reserved
80030  */
80031 #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0_SHIFT)) & LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0_MASK)
80032 #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN_MASK (0x2U)
80033 #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN_SHIFT (1U)
80034 /*! med_dec_mfd_sys_clk_gated_SWEN - Software Enable
80035  *  0b0..Disable SW clock regardless of HWEN
80036  *  0b1..Enable SW clock gating
80037  */
80038 #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN_SHIFT)) & LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN_MASK)
80039 #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2_MASK (0x4U)
80040 #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2_SHIFT (2U)
80041 /*! LPCG_MFD_0_reserved_2_2 - reserved
80042  */
80043 #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2_SHIFT)) & LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2_MASK)
80044 #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP_MASK (0x8U)
80045 #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP_SHIFT (3U)
80046 /*! med_dec_mfd_sys_clk_gated_STOP - show clock root status, 1 means clock stopped
80047  */
80048 #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP_SHIFT)) & LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP_MASK)
80049 #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31_MASK (0xFFFFFFF0U)
80050 #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31_SHIFT (4U)
80051 /*! LPCG_MFD_0_reserved_4_31 - reserved
80052  */
80053 #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31_SHIFT)) & LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31_MASK)
80054 /*! @} */
80055 
80056 
80057 /*!
80058  * @}
80059  */ /* end of group LPCG_MFD_Register_Masks */
80060 
80061 
80062 /* LPCG_MFD - Peripheral instance base addresses */
80063 /** Peripheral VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED base address */
80064 #define VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED_BASE (0x2D070000u)
80065 /** Peripheral VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED base pointer */
80066 #define VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED      ((LPCG_MFD_Type *)VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED_BASE)
80067 /** Array initializer of LPCG_MFD peripheral base addresses */
80068 #define LPCG_MFD_BASE_ADDRS                      { VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED_BASE }
80069 /** Array initializer of LPCG_MFD peripheral base pointers */
80070 #define LPCG_MFD_BASE_PTRS                       { VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED }
80071 
80072 /*!
80073  * @}
80074  */ /* end of group LPCG_MFD_Peripheral_Access_Layer */
80075 
80076 
80077 /* ----------------------------------------------------------------------------
80078    -- LPCG_MISC_CRR5 Peripheral Access Layer
80079    ---------------------------------------------------------------------------- */
80080 
80081 /*!
80082  * @addtogroup LPCG_MISC_CRR5_Peripheral_Access_Layer LPCG_MISC_CRR5 Peripheral Access Layer
80083  * @{
80084  */
80085 
80086 /** LPCG_MISC_CRR5 - Register Layout Typedef */
80087 typedef struct {
80088   __IO uint32_t LPCG_MISC_CRR5_0;                  /**< na, offset: 0x0 */
80089 } LPCG_MISC_CRR5_Type;
80090 
80091 /* ----------------------------------------------------------------------------
80092    -- LPCG_MISC_CRR5 Register Masks
80093    ---------------------------------------------------------------------------- */
80094 
80095 /*!
80096  * @addtogroup LPCG_MISC_CRR5_Register_Masks LPCG_MISC_CRR5 Register Masks
80097  * @{
80098  */
80099 
80100 /*! @name LPCG_MISC_CRR5_0 - na */
80101 /*! @{ */
80102 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_MASK (0xFFFFU)
80103 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_SHIFT (0U)
80104 /*! LPCG_MISC_CRR5_0_reserved_0_15 - reserved
80105  */
80106 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_MASK)
80107 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_MASK (0x10000U)
80108 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_SHIFT (16U)
80109 /*! hsio_misc_regs_ipg_clk_HWEN - Hardware Enable
80110  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
80111  *  0b1..Enable HW automatic gating
80112  */
80113 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_MASK)
80114 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_MASK (0x20000U)
80115 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_SHIFT (17U)
80116 /*! hsio_misc_regs_ipg_clk_SWEN - Software Enable
80117  *  0b0..Disable SW clock regardless of HWEN
80118  *  0b1..Enable SW clock gating
80119  */
80120 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_MASK)
80121 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_MASK (0x40000U)
80122 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_SHIFT (18U)
80123 /*! LPCG_MISC_CRR5_0_reserved_18_18 - reserved
80124  */
80125 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_MASK)
80126 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_MASK (0x80000U)
80127 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_SHIFT (19U)
80128 /*! hsio_misc_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped
80129  */
80130 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_MASK)
80131 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_MASK (0xFFF00000U)
80132 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_SHIFT (20U)
80133 /*! LPCG_MISC_CRR5_0_reserved_20_31 - reserved
80134  */
80135 #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_MASK)
80136 /*! @} */
80137 
80138 
80139 /*!
80140  * @}
80141  */ /* end of group LPCG_MISC_CRR5_Register_Masks */
80142 
80143 
80144 /* LPCG_MISC_CRR5 - Peripheral instance base addresses */
80145 /** Peripheral HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK base address */
80146 #define HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK_BASE   (0x5F0F0000u)
80147 /** Peripheral HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK base pointer */
80148 #define HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK        ((LPCG_MISC_CRR5_Type *)HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK_BASE)
80149 /** Array initializer of LPCG_MISC_CRR5 peripheral base addresses */
80150 #define LPCG_MISC_CRR5_BASE_ADDRS                { HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK_BASE }
80151 /** Array initializer of LPCG_MISC_CRR5 peripheral base pointers */
80152 #define LPCG_MISC_CRR5_BASE_PTRS                 { HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK }
80153 
80154 /*!
80155  * @}
80156  */ /* end of group LPCG_MISC_CRR5_Peripheral_Access_Layer */
80157 
80158 
80159 /* ----------------------------------------------------------------------------
80160    -- LPCG_MMCAU_HCLK Peripheral Access Layer
80161    ---------------------------------------------------------------------------- */
80162 
80163 /*!
80164  * @addtogroup LPCG_MMCAU_HCLK_Peripheral_Access_Layer LPCG_MMCAU_HCLK Peripheral Access Layer
80165  * @{
80166  */
80167 
80168 /** LPCG_MMCAU_HCLK - Register Layout Typedef */
80169 typedef struct {
80170   __IO uint32_t LPCG_MMCAU_HCLK_0;                 /**< na, offset: 0x0 */
80171 } LPCG_MMCAU_HCLK_Type;
80172 
80173 /* ----------------------------------------------------------------------------
80174    -- LPCG_MMCAU_HCLK Register Masks
80175    ---------------------------------------------------------------------------- */
80176 
80177 /*!
80178  * @addtogroup LPCG_MMCAU_HCLK_Register_Masks LPCG_MMCAU_HCLK Register Masks
80179  * @{
80180  */
80181 
80182 /*! @name LPCG_MMCAU_HCLK_0 - na */
80183 /*! @{ */
80184 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U)
80185 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U)
80186 /*! LPCG_MMCAU_HCLK_0_reserved_0_0 - reserved
80187  */
80188 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK)
80189 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U)
80190 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U)
80191 /*! cm4_mmcau_hclk_SWEN - Software Enable
80192  *  0b0..Disable SW clock regardless of HWEN
80193  *  0b1..Enable SW clock gating
80194  */
80195 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK)
80196 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U)
80197 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U)
80198 /*! LPCG_MMCAU_HCLK_0_reserved_2_2 - reserved
80199  */
80200 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK)
80201 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U)
80202 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U)
80203 /*! cm4_mmcau_hclk_STOP - show clock root status, 1 means clock stopped
80204  */
80205 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK)
80206 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
80207 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U)
80208 /*! LPCG_MMCAU_HCLK_0_reserved_4_31 - reserved
80209  */
80210 #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK)
80211 /*! @} */
80212 
80213 
80214 /*!
80215  * @}
80216  */ /* end of group LPCG_MMCAU_HCLK_Register_Masks */
80217 
80218 
80219 /* LPCG_MMCAU_HCLK - Peripheral instance base addresses */
80220 /** Peripheral SCU__LPCG_MMCAU_HCLK base address */
80221 #define SCU__LPCG_MMCAU_HCLK_BASE                (0x335F0000u)
80222 /** Peripheral SCU__LPCG_MMCAU_HCLK base pointer */
80223 #define SCU__LPCG_MMCAU_HCLK                     ((LPCG_MMCAU_HCLK_Type *)SCU__LPCG_MMCAU_HCLK_BASE)
80224 /** Array initializer of LPCG_MMCAU_HCLK peripheral base addresses */
80225 #define LPCG_MMCAU_HCLK_BASE_ADDRS               { SCU__LPCG_MMCAU_HCLK_BASE }
80226 /** Array initializer of LPCG_MMCAU_HCLK peripheral base pointers */
80227 #define LPCG_MMCAU_HCLK_BASE_PTRS                { SCU__LPCG_MMCAU_HCLK }
80228 
80229 /*!
80230  * @}
80231  */ /* end of group LPCG_MMCAU_HCLK_Peripheral_Access_Layer */
80232 
80233 
80234 /* ----------------------------------------------------------------------------
80235    -- LPCG_MPGD Peripheral Access Layer
80236    ---------------------------------------------------------------------------- */
80237 
80238 /*!
80239  * @addtogroup LPCG_MPGD_Peripheral_Access_Layer LPCG_MPGD Peripheral Access Layer
80240  * @{
80241  */
80242 
80243 /** LPCG_MPGD - Register Layout Typedef */
80244 typedef struct {
80245   __IO uint32_t LPCG_MPGD_0;                       /**< na, offset: 0x0 */
80246 } LPCG_MPGD_Type;
80247 
80248 /* ----------------------------------------------------------------------------
80249    -- LPCG_MPGD Register Masks
80250    ---------------------------------------------------------------------------- */
80251 
80252 /*!
80253  * @addtogroup LPCG_MPGD_Register_Masks LPCG_MPGD Register Masks
80254  * @{
80255  */
80256 
80257 /*! @name LPCG_MPGD_0 - na */
80258 /*! @{ */
80259 #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0_MASK (0x1U)
80260 #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0_SHIFT (0U)
80261 /*! LPCG_MPGD_0_reserved_0_0 - reserved
80262  */
80263 #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0_MASK)
80264 #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_MASK (0x2U)
80265 #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_SHIFT (1U)
80266 /*! med_dec_mfd_mpgd_clk_gated_SWEN - Software Enable
80267  *  0b0..Disable SW clock regardless of HWEN
80268  *  0b1..Enable SW clock gating
80269  */
80270 #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_MASK)
80271 #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2_MASK (0x4U)
80272 #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2_SHIFT (2U)
80273 /*! LPCG_MPGD_0_reserved_2_2 - reserved
80274  */
80275 #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2_MASK)
80276 #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_MASK (0x8U)
80277 #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_SHIFT (3U)
80278 /*! med_dec_mfd_mpgd_clk_gated_STOP - show clock root status, 1 means clock stopped
80279  */
80280 #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_MASK)
80281 #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31_MASK (0xFFFFFFF0U)
80282 #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31_SHIFT (4U)
80283 /*! LPCG_MPGD_0_reserved_4_31 - reserved
80284  */
80285 #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31_MASK)
80286 /*! @} */
80287 
80288 
80289 /*!
80290  * @}
80291  */ /* end of group LPCG_MPGD_Register_Masks */
80292 
80293 
80294 /* LPCG_MPGD - Peripheral instance base addresses */
80295 /** Peripheral VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED base address */
80296 #define VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED_BASE (0x2D0A0000u)
80297 /** Peripheral VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED base pointer */
80298 #define VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED     ((LPCG_MPGD_Type *)VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED_BASE)
80299 /** Array initializer of LPCG_MPGD peripheral base addresses */
80300 #define LPCG_MPGD_BASE_ADDRS                     { VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED_BASE }
80301 /** Array initializer of LPCG_MPGD peripheral base pointers */
80302 #define LPCG_MPGD_BASE_PTRS                      { VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED }
80303 
80304 /*!
80305  * @}
80306  */ /* end of group LPCG_MPGD_Peripheral_Access_Layer */
80307 
80308 
80309 /* ----------------------------------------------------------------------------
80310    -- LPCG_PCIEX1 Peripheral Access Layer
80311    ---------------------------------------------------------------------------- */
80312 
80313 /*!
80314  * @addtogroup LPCG_PCIEX1_Peripheral_Access_Layer LPCG_PCIEX1 Peripheral Access Layer
80315  * @{
80316  */
80317 
80318 /** LPCG_PCIEX1 - Register Layout Typedef */
80319 typedef struct {
80320   __IO uint32_t LPCG_PCIEX1_0;                     /**< na, offset: 0x0 */
80321 } LPCG_PCIEX1_Type;
80322 
80323 /* ----------------------------------------------------------------------------
80324    -- LPCG_PCIEX1 Register Masks
80325    ---------------------------------------------------------------------------- */
80326 
80327 /*!
80328  * @addtogroup LPCG_PCIEX1_Register_Masks LPCG_PCIEX1 Register Masks
80329  * @{
80330  */
80331 
80332 /*! @name LPCG_PCIEX1_0 - na */
80333 /*! @{ */
80334 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15_MASK (0xFFFFU)
80335 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15_SHIFT (0U)
80336 /*! LPCG_PCIEX1_0_reserved_0_15 - reserved
80337  */
80338 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15_MASK)
80339 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN_MASK (0x10000U)
80340 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN_SHIFT (16U)
80341 /*! pcie_clk_rst_mstr_axi_clk_HWEN - Hardware Enable
80342  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
80343  *  0b1..Enable HW automatic gating
80344  */
80345 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN_MASK)
80346 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN_MASK (0x20000U)
80347 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN_SHIFT (17U)
80348 /*! pcie_clk_rst_mstr_axi_clk_SWEN - Software Enable
80349  *  0b0..Disable SW clock regardless of HWEN
80350  *  0b1..Enable SW clock gating
80351  */
80352 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN_MASK)
80353 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_MASK (0x40000U)
80354 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_SHIFT (18U)
80355 /*! LPCG_PCIEX1_0_reserved_18_18 - reserved
80356  */
80357 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_MASK)
80358 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP_MASK (0x80000U)
80359 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP_SHIFT (19U)
80360 /*! pcie_clk_rst_mstr_axi_clk_STOP - show clock root status, 1 means clock stopped
80361  */
80362 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP_MASK)
80363 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN_MASK (0x100000U)
80364 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN_SHIFT (20U)
80365 /*! pcie_clk_rst_slv_axi_clk_HWEN - Hardware Enable
80366  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
80367  *  0b1..Enable HW automatic gating
80368  */
80369 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN_MASK)
80370 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN_MASK (0x200000U)
80371 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN_SHIFT (21U)
80372 /*! pcie_clk_rst_slv_axi_clk_SWEN - Software Enable
80373  *  0b0..Disable SW clock regardless of HWEN
80374  *  0b1..Enable SW clock gating
80375  */
80376 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN_MASK)
80377 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_MASK (0x400000U)
80378 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_SHIFT (22U)
80379 /*! LPCG_PCIEX1_0_reserved_22_22 - reserved
80380  */
80381 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_MASK)
80382 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP_MASK (0x800000U)
80383 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP_SHIFT (23U)
80384 /*! pcie_clk_rst_slv_axi_clk_STOP - show clock root status, 1 means clock stopped
80385  */
80386 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP_MASK)
80387 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN_MASK (0x1000000U)
80388 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN_SHIFT (24U)
80389 /*! pcie_clk_rst_dbi_axi_clk_HWEN - Hardware Enable
80390  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
80391  *  0b1..Enable HW automatic gating
80392  */
80393 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN_MASK)
80394 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN_MASK (0x2000000U)
80395 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN_SHIFT (25U)
80396 /*! pcie_clk_rst_dbi_axi_clk_SWEN - Software Enable
80397  *  0b0..Disable SW clock regardless of HWEN
80398  *  0b1..Enable SW clock gating
80399  */
80400 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN_MASK)
80401 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_MASK (0x4000000U)
80402 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_SHIFT (26U)
80403 /*! LPCG_PCIEX1_0_reserved_26_26 - reserved
80404  */
80405 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_MASK)
80406 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP_MASK (0x8000000U)
80407 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP_SHIFT (27U)
80408 /*! pcie_clk_rst_dbi_axi_clk_STOP - show clock root status, 1 means clock stopped
80409  */
80410 #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP_MASK)
80411 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_MASK (0xF0000000U)
80412 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_SHIFT (28U)
80413 /*! LPCG_PCIEX1_0_reserved_28_31 - reserved
80414  */
80415 #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_MASK)
80416 /*! @} */
80417 
80418 
80419 /*!
80420  * @}
80421  */ /* end of group LPCG_PCIEX1_Register_Masks */
80422 
80423 
80424 /* LPCG_PCIEX1 - Peripheral instance base addresses */
80425 /** Peripheral HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK base address */
80426 #define HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK_BASE (0x5F060000u)
80427 /** Peripheral HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK base pointer */
80428 #define HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK   ((LPCG_PCIEX1_Type *)HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK_BASE)
80429 /** Array initializer of LPCG_PCIEX1 peripheral base addresses */
80430 #define LPCG_PCIEX1_BASE_ADDRS                   { HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK_BASE }
80431 /** Array initializer of LPCG_PCIEX1 peripheral base pointers */
80432 #define LPCG_PCIEX1_BASE_PTRS                    { HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK }
80433 
80434 /*!
80435  * @}
80436  */ /* end of group LPCG_PCIEX1_Peripheral_Access_Layer */
80437 
80438 
80439 /* ----------------------------------------------------------------------------
80440    -- LPCG_PCIEX1_CRR3 Peripheral Access Layer
80441    ---------------------------------------------------------------------------- */
80442 
80443 /*!
80444  * @addtogroup LPCG_PCIEX1_CRR3_Peripheral_Access_Layer LPCG_PCIEX1_CRR3 Peripheral Access Layer
80445  * @{
80446  */
80447 
80448 /** LPCG_PCIEX1_CRR3 - Register Layout Typedef */
80449 typedef struct {
80450   __IO uint32_t LPCG_PCIEX1_CRR3_0;                /**< na, offset: 0x0 */
80451 } LPCG_PCIEX1_CRR3_Type;
80452 
80453 /* ----------------------------------------------------------------------------
80454    -- LPCG_PCIEX1_CRR3 Register Masks
80455    ---------------------------------------------------------------------------- */
80456 
80457 /*!
80458  * @addtogroup LPCG_PCIEX1_CRR3_Register_Masks LPCG_PCIEX1_CRR3 Register Masks
80459  * @{
80460  */
80461 
80462 /*! @name LPCG_PCIEX1_CRR3_0 - na */
80463 /*! @{ */
80464 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_MASK (0xFFFFU)
80465 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_SHIFT (0U)
80466 /*! LPCG_PCIEX1_CRR3_0_reserved_0_15 - reserved
80467  */
80468 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_MASK)
80469 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_MASK (0x10000U)
80470 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_SHIFT (16U)
80471 /*! hsio_pciex1_regs_ipg_clk_HWEN - Hardware Enable
80472  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
80473  *  0b1..Enable HW automatic gating
80474  */
80475 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_MASK)
80476 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_MASK (0x20000U)
80477 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_SHIFT (17U)
80478 /*! hsio_pciex1_regs_ipg_clk_SWEN - Software Enable
80479  *  0b0..Disable SW clock regardless of HWEN
80480  *  0b1..Enable SW clock gating
80481  */
80482 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_MASK)
80483 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_MASK (0x40000U)
80484 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_SHIFT (18U)
80485 /*! LPCG_PCIEX1_CRR3_0_reserved_18_18 - reserved
80486  */
80487 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_MASK)
80488 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_MASK (0x80000U)
80489 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_SHIFT (19U)
80490 /*! hsio_pciex1_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped
80491  */
80492 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_MASK)
80493 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_MASK (0xFFF00000U)
80494 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_SHIFT (20U)
80495 /*! LPCG_PCIEX1_CRR3_0_reserved_20_31 - reserved
80496  */
80497 #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_MASK)
80498 /*! @} */
80499 
80500 
80501 /*!
80502  * @}
80503  */ /* end of group LPCG_PCIEX1_CRR3_Register_Masks */
80504 
80505 
80506 /* LPCG_PCIEX1_CRR3 - Peripheral instance base addresses */
80507 /** Peripheral HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK base address */
80508 #define HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK_BASE (0x5F0D0000u)
80509 /** Peripheral HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK base pointer */
80510 #define HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK      ((LPCG_PCIEX1_CRR3_Type *)HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK_BASE)
80511 /** Array initializer of LPCG_PCIEX1_CRR3 peripheral base addresses */
80512 #define LPCG_PCIEX1_CRR3_BASE_ADDRS              { HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK_BASE }
80513 /** Array initializer of LPCG_PCIEX1_CRR3 peripheral base pointers */
80514 #define LPCG_PCIEX1_CRR3_BASE_PTRS               { HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK }
80515 
80516 /*!
80517  * @}
80518  */ /* end of group LPCG_PCIEX1_CRR3_Peripheral_Access_Layer */
80519 
80520 
80521 /* ----------------------------------------------------------------------------
80522    -- LPCG_PHYX1 Peripheral Access Layer
80523    ---------------------------------------------------------------------------- */
80524 
80525 /*!
80526  * @addtogroup LPCG_PHYX1_Peripheral_Access_Layer LPCG_PHYX1 Peripheral Access Layer
80527  * @{
80528  */
80529 
80530 /** LPCG_PHYX1 - Register Layout Typedef */
80531 typedef struct {
80532   __IO uint32_t LPCG_PHYX1_0;                      /**< na, offset: 0x0 */
80533 } LPCG_PHYX1_Type;
80534 
80535 /* ----------------------------------------------------------------------------
80536    -- LPCG_PHYX1 Register Masks
80537    ---------------------------------------------------------------------------- */
80538 
80539 /*!
80540  * @addtogroup LPCG_PHYX1_Register_Masks LPCG_PHYX1 Register Masks
80541  * @{
80542  */
80543 
80544 /*! @name LPCG_PHYX1_0 - na */
80545 /*! @{ */
80546 #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15_MASK (0xFFFFU)
80547 #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15_SHIFT (0U)
80548 /*! LPCG_PHYX1_0_reserved_0_15 - reserved
80549  */
80550 #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15_MASK)
80551 #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN_MASK (0x10000U)
80552 #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN_SHIFT (16U)
80553 /*! pcs_phy_x1_apb_pclk_0_HWEN - Hardware Enable
80554  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
80555  *  0b1..Enable HW automatic gating
80556  */
80557 #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN_MASK)
80558 #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_MASK (0x20000U)
80559 #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_SHIFT (17U)
80560 /*! pcs_phy_x1_apb_pclk_0_SWEN - Software Enable
80561  *  0b0..Disable SW clock regardless of HWEN
80562  *  0b1..Enable SW clock gating
80563  */
80564 #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_MASK)
80565 #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_MASK (0x40000U)
80566 #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_SHIFT (18U)
80567 /*! LPCG_PHYX1_0_reserved_18_18 - reserved
80568  */
80569 #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_MASK)
80570 #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_MASK (0x80000U)
80571 #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_SHIFT (19U)
80572 /*! pcs_phy_x1_apb_pclk_0_STOP - show clock root status, 1 means clock stopped
80573  */
80574 #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_MASK)
80575 #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_MASK (0xFFF00000U)
80576 #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_SHIFT (20U)
80577 /*! LPCG_PHYX1_0_reserved_20_31 - reserved
80578  */
80579 #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_MASK)
80580 /*! @} */
80581 
80582 
80583 /*!
80584  * @}
80585  */ /* end of group LPCG_PHYX1_Register_Masks */
80586 
80587 
80588 /* LPCG_PHYX1 - Peripheral instance base addresses */
80589 /** Peripheral HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0 base address */
80590 #define HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0_BASE    (0x5F090000u)
80591 /** Peripheral HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0 base pointer */
80592 #define HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0         ((LPCG_PHYX1_Type *)HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0_BASE)
80593 /** Array initializer of LPCG_PHYX1 peripheral base addresses */
80594 #define LPCG_PHYX1_BASE_ADDRS                    { HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0_BASE }
80595 /** Array initializer of LPCG_PHYX1 peripheral base pointers */
80596 #define LPCG_PHYX1_BASE_PTRS                     { HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0 }
80597 
80598 /*!
80599  * @}
80600  */ /* end of group LPCG_PHYX1_Peripheral_Access_Layer */
80601 
80602 
80603 /* ----------------------------------------------------------------------------
80604    -- LPCG_PHYX1_CRR1 Peripheral Access Layer
80605    ---------------------------------------------------------------------------- */
80606 
80607 /*!
80608  * @addtogroup LPCG_PHYX1_CRR1_Peripheral_Access_Layer LPCG_PHYX1_CRR1 Peripheral Access Layer
80609  * @{
80610  */
80611 
80612 /** LPCG_PHYX1_CRR1 - Register Layout Typedef */
80613 typedef struct {
80614   __IO uint32_t LPCG_PHYX1_CRR1_0;                 /**< na, offset: 0x0 */
80615 } LPCG_PHYX1_CRR1_Type;
80616 
80617 /* ----------------------------------------------------------------------------
80618    -- LPCG_PHYX1_CRR1 Register Masks
80619    ---------------------------------------------------------------------------- */
80620 
80621 /*!
80622  * @addtogroup LPCG_PHYX1_CRR1_Register_Masks LPCG_PHYX1_CRR1 Register Masks
80623  * @{
80624  */
80625 
80626 /*! @name LPCG_PHYX1_CRR1_0 - na */
80627 /*! @{ */
80628 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_MASK (0xFFFFU)
80629 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_SHIFT (0U)
80630 /*! LPCG_PHYX1_CRR1_0_reserved_0_15 - reserved
80631  */
80632 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_MASK)
80633 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_MASK (0x10000U)
80634 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_SHIFT (16U)
80635 /*! hsio_phyx1_regs_ipg_clk_HWEN - Hardware Enable
80636  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
80637  *  0b1..Enable HW automatic gating
80638  */
80639 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_MASK)
80640 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_MASK (0x20000U)
80641 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_SHIFT (17U)
80642 /*! hsio_phyx1_regs_ipg_clk_SWEN - Software Enable
80643  *  0b0..Disable SW clock regardless of HWEN
80644  *  0b1..Enable SW clock gating
80645  */
80646 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_MASK)
80647 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_MASK (0x40000U)
80648 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_SHIFT (18U)
80649 /*! LPCG_PHYX1_CRR1_0_reserved_18_18 - reserved
80650  */
80651 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_MASK)
80652 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_MASK (0x80000U)
80653 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_SHIFT (19U)
80654 /*! hsio_phyx1_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped
80655  */
80656 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_MASK)
80657 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_MASK (0xFFF00000U)
80658 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_SHIFT (20U)
80659 /*! LPCG_PHYX1_CRR1_0_reserved_20_31 - reserved
80660  */
80661 #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_MASK)
80662 /*! @} */
80663 
80664 
80665 /*!
80666  * @}
80667  */ /* end of group LPCG_PHYX1_CRR1_Register_Masks */
80668 
80669 
80670 /* LPCG_PHYX1_CRR1 - Peripheral instance base addresses */
80671 /** Peripheral HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK base address */
80672 #define HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK_BASE  (0x5F0B0000u)
80673 /** Peripheral HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK base pointer */
80674 #define HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK       ((LPCG_PHYX1_CRR1_Type *)HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK_BASE)
80675 /** Array initializer of LPCG_PHYX1_CRR1 peripheral base addresses */
80676 #define LPCG_PHYX1_CRR1_BASE_ADDRS               { HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK_BASE }
80677 /** Array initializer of LPCG_PHYX1_CRR1 peripheral base pointers */
80678 #define LPCG_PHYX1_CRR1_BASE_PTRS                { HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK }
80679 
80680 /*!
80681  * @}
80682  */ /* end of group LPCG_PHYX1_CRR1_Peripheral_Access_Layer */
80683 
80684 
80685 /* ----------------------------------------------------------------------------
80686    -- LPCG_SSI Peripheral Access Layer
80687    ---------------------------------------------------------------------------- */
80688 
80689 /*!
80690  * @addtogroup LPCG_SSI_Peripheral_Access_Layer LPCG_SSI Peripheral Access Layer
80691  * @{
80692  */
80693 
80694 /** LPCG_SSI - Register Layout Typedef */
80695 typedef struct {
80696   __IO uint32_t LPCG_SSI_0;                        /**< na, offset: 0x0 */
80697 } LPCG_SSI_Type;
80698 
80699 /* ----------------------------------------------------------------------------
80700    -- LPCG_SSI Register Masks
80701    ---------------------------------------------------------------------------- */
80702 
80703 /*!
80704  * @addtogroup LPCG_SSI_Register_Masks LPCG_SSI Register Masks
80705  * @{
80706  */
80707 
80708 /*! @name LPCG_SSI_0 - na */
80709 /*! @{ */
80710 #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN_MASK   (0x1U)
80711 #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN_SHIFT  (0U)
80712 /*! ssi_pclk_HWEN - Hardware Enable
80713  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
80714  *  0b1..Enable HW automatic gating
80715  */
80716 #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN(x)     (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN_SHIFT)) & LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN_MASK)
80717 #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN_MASK   (0x2U)
80718 #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN_SHIFT  (1U)
80719 /*! ssi_pclk_SWEN - Software Enable
80720  *  0b0..Disable SW clock regardless of HWEN
80721  *  0b1..Enable SW clock gating
80722  */
80723 #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN(x)     (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN_SHIFT)) & LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN_MASK)
80724 #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2_MASK (0x4U)
80725 #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2_SHIFT (2U)
80726 /*! LPCG_SSI_0_reserved_2_2 - reserved
80727  */
80728 #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2_SHIFT)) & LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2_MASK)
80729 #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP_MASK   (0x8U)
80730 #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP_SHIFT  (3U)
80731 /*! ssi_pclk_STOP - show clock root status, 1 means clock stopped
80732  */
80733 #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP(x)     (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP_SHIFT)) & LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP_MASK)
80734 #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31_MASK (0xFFFFFFF0U)
80735 #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31_SHIFT (4U)
80736 /*! LPCG_SSI_0_reserved_4_31 - reserved
80737  */
80738 #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31_SHIFT)) & LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31_MASK)
80739 /*! @} */
80740 
80741 
80742 /*!
80743  * @}
80744  */ /* end of group LPCG_SSI_Register_Masks */
80745 
80746 
80747 /* LPCG_SSI - Peripheral instance base addresses */
80748 /** Peripheral HSIO__LPCG_SSI_PCLK base address */
80749 #define HSIO__LPCG_SSI_PCLK_BASE                 (0x5F070000u)
80750 /** Peripheral HSIO__LPCG_SSI_PCLK base pointer */
80751 #define HSIO__LPCG_SSI_PCLK                      ((LPCG_SSI_Type *)HSIO__LPCG_SSI_PCLK_BASE)
80752 /** Array initializer of LPCG_SSI peripheral base addresses */
80753 #define LPCG_SSI_BASE_ADDRS                      { HSIO__LPCG_SSI_PCLK_BASE }
80754 /** Array initializer of LPCG_SSI peripheral base pointers */
80755 #define LPCG_SSI_BASE_PTRS                       { HSIO__LPCG_SSI_PCLK }
80756 
80757 /*!
80758  * @}
80759  */ /* end of group LPCG_SSI_Peripheral_Access_Layer */
80760 
80761 
80762 /* ----------------------------------------------------------------------------
80763    -- LPCG_TCMC_HCLK Peripheral Access Layer
80764    ---------------------------------------------------------------------------- */
80765 
80766 /*!
80767  * @addtogroup LPCG_TCMC_HCLK_Peripheral_Access_Layer LPCG_TCMC_HCLK Peripheral Access Layer
80768  * @{
80769  */
80770 
80771 /** LPCG_TCMC_HCLK - Register Layout Typedef */
80772 typedef struct {
80773   __IO uint32_t LPCG_TCMC_HCLK_0;                  /**< na, offset: 0x0 */
80774 } LPCG_TCMC_HCLK_Type;
80775 
80776 /* ----------------------------------------------------------------------------
80777    -- LPCG_TCMC_HCLK Register Masks
80778    ---------------------------------------------------------------------------- */
80779 
80780 /*!
80781  * @addtogroup LPCG_TCMC_HCLK_Register_Masks LPCG_TCMC_HCLK Register Masks
80782  * @{
80783  */
80784 
80785 /*! @name LPCG_TCMC_HCLK_0 - na */
80786 /*! @{ */
80787 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U)
80788 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U)
80789 /*! cm4_tcmc_hclk_HWEN - Hardware Enable
80790  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
80791  *  0b1..Enable HW automatic gating
80792  */
80793 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK)
80794 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U)
80795 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U)
80796 /*! cm4_tcmc_hclk_SWEN - Software Enable
80797  *  0b0..Disable SW clock regardless of HWEN
80798  *  0b1..Enable SW clock gating
80799  */
80800 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK)
80801 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U)
80802 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U)
80803 /*! LPCG_TCMC_HCLK_0_reserved_2_2 - reserved
80804  */
80805 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK)
80806 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U)
80807 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U)
80808 /*! cm4_tcmc_hclk_STOP - show clock root status, 1 means clock stopped
80809  */
80810 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK)
80811 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
80812 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U)
80813 /*! LPCG_TCMC_HCLK_0_reserved_4_31 - reserved
80814  */
80815 #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK)
80816 /*! @} */
80817 
80818 
80819 /*!
80820  * @}
80821  */ /* end of group LPCG_TCMC_HCLK_Register_Masks */
80822 
80823 
80824 /* LPCG_TCMC_HCLK - Peripheral instance base addresses */
80825 /** Peripheral SCU__LPCG_TCMC_HCLK base address */
80826 #define SCU__LPCG_TCMC_HCLK_BASE                 (0x335E0000u)
80827 /** Peripheral SCU__LPCG_TCMC_HCLK base pointer */
80828 #define SCU__LPCG_TCMC_HCLK                      ((LPCG_TCMC_HCLK_Type *)SCU__LPCG_TCMC_HCLK_BASE)
80829 /** Array initializer of LPCG_TCMC_HCLK peripheral base addresses */
80830 #define LPCG_TCMC_HCLK_BASE_ADDRS                { SCU__LPCG_TCMC_HCLK_BASE }
80831 /** Array initializer of LPCG_TCMC_HCLK peripheral base pointers */
80832 #define LPCG_TCMC_HCLK_BASE_PTRS                 { SCU__LPCG_TCMC_HCLK }
80833 
80834 /*!
80835  * @}
80836  */ /* end of group LPCG_TCMC_HCLK_Peripheral_Access_Layer */
80837 
80838 
80839 /* ----------------------------------------------------------------------------
80840    -- LPCG_TPM Peripheral Access Layer
80841    ---------------------------------------------------------------------------- */
80842 
80843 /*!
80844  * @addtogroup LPCG_TPM_Peripheral_Access_Layer LPCG_TPM Peripheral Access Layer
80845  * @{
80846  */
80847 
80848 /** LPCG_TPM - Register Layout Typedef */
80849 typedef struct {
80850   __IO uint32_t LPCG_TPM_0;                        /**< na, offset: 0x0 */
80851 } LPCG_TPM_Type;
80852 
80853 /* ----------------------------------------------------------------------------
80854    -- LPCG_TPM Register Masks
80855    ---------------------------------------------------------------------------- */
80856 
80857 /*!
80858  * @addtogroup LPCG_TPM_Register_Masks LPCG_TPM Register Masks
80859  * @{
80860  */
80861 
80862 /*! @name LPCG_TPM_0 - na */
80863 /*! @{ */
80864 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U)
80865 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U)
80866 /*! LPCG_TPM_0_reserved_0_0 - reserved
80867  */
80868 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK)
80869 #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U)
80870 #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U)
80871 /*! tpm1_lptpm_clk_SWEN - Software Enable
80872  *  0b0..Disable SW clock regardless of HWEN
80873  *  0b1..Enable SW clock gating
80874  */
80875 #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK)
80876 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U)
80877 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U)
80878 /*! LPCG_TPM_0_reserved_2_2 - reserved
80879  */
80880 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK)
80881 #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U)
80882 #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U)
80883 /*! tpm1_lptpm_clk_STOP - show clock root status, 1 means clock stopped
80884  */
80885 #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK)
80886 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U)
80887 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U)
80888 /*! LPCG_TPM_0_reserved_4_4 - reserved
80889  */
80890 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK)
80891 #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U)
80892 #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U)
80893 /*! tpm1_ipg_clk_SWEN - Software Enable
80894  *  0b0..Disable SW clock regardless of HWEN
80895  *  0b1..Enable SW clock gating
80896  */
80897 #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK)
80898 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U)
80899 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U)
80900 /*! LPCG_TPM_0_reserved_6_6 - reserved
80901  */
80902 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK)
80903 #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U)
80904 #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U)
80905 /*! tpm1_ipg_clk_STOP - show clock root status, 1 means clock stopped
80906  */
80907 #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK)
80908 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U)
80909 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U)
80910 /*! LPCG_TPM_0_reserved_8_31 - reserved
80911  */
80912 #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK)
80913 /*! @} */
80914 
80915 
80916 /*!
80917  * @}
80918  */ /* end of group LPCG_TPM_Register_Masks */
80919 
80920 
80921 /* LPCG_TPM - Peripheral instance base addresses */
80922 /** Peripheral SCU__LPCG_TPM base address */
80923 #define SCU__LPCG_TPM_BASE                       (0x33600000u)
80924 /** Peripheral SCU__LPCG_TPM base pointer */
80925 #define SCU__LPCG_TPM                            ((LPCG_TPM_Type *)SCU__LPCG_TPM_BASE)
80926 /** Array initializer of LPCG_TPM peripheral base addresses */
80927 #define LPCG_TPM_BASE_ADDRS                      { SCU__LPCG_TPM_BASE }
80928 /** Array initializer of LPCG_TPM peripheral base pointers */
80929 #define LPCG_TPM_BASE_PTRS                       { SCU__LPCG_TPM }
80930 
80931 /*!
80932  * @}
80933  */ /* end of group LPCG_TPM_Peripheral_Access_Layer */
80934 
80935 
80936 /* ----------------------------------------------------------------------------
80937    -- LPCG_VC1D Peripheral Access Layer
80938    ---------------------------------------------------------------------------- */
80939 
80940 /*!
80941  * @addtogroup LPCG_VC1D_Peripheral_Access_Layer LPCG_VC1D Peripheral Access Layer
80942  * @{
80943  */
80944 
80945 /** LPCG_VC1D - Register Layout Typedef */
80946 typedef struct {
80947   __IO uint32_t LPCG_VC1D_0;                       /**< na, offset: 0x0 */
80948 } LPCG_VC1D_Type;
80949 
80950 /* ----------------------------------------------------------------------------
80951    -- LPCG_VC1D Register Masks
80952    ---------------------------------------------------------------------------- */
80953 
80954 /*!
80955  * @addtogroup LPCG_VC1D_Register_Masks LPCG_VC1D Register Masks
80956  * @{
80957  */
80958 
80959 /*! @name LPCG_VC1D_0 - na */
80960 /*! @{ */
80961 #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0_MASK (0x1U)
80962 #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0_SHIFT (0U)
80963 /*! LPCG_VC1D_0_reserved_0_0 - reserved
80964  */
80965 #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0_MASK)
80966 #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_MASK (0x2U)
80967 #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_SHIFT (1U)
80968 /*! med_dec_mfd_vc1d_clk_gated_SWEN - Software Enable
80969  *  0b0..Disable SW clock regardless of HWEN
80970  *  0b1..Enable SW clock gating
80971  */
80972 #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_MASK)
80973 #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2_MASK (0x4U)
80974 #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2_SHIFT (2U)
80975 /*! LPCG_VC1D_0_reserved_2_2 - reserved
80976  */
80977 #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2_MASK)
80978 #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_MASK (0x8U)
80979 #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_SHIFT (3U)
80980 /*! med_dec_mfd_vc1d_clk_gated_STOP - show clock root status, 1 means clock stopped
80981  */
80982 #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_MASK)
80983 #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31_MASK (0xFFFFFFF0U)
80984 #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31_SHIFT (4U)
80985 /*! LPCG_VC1D_0_reserved_4_31 - reserved
80986  */
80987 #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31_MASK)
80988 /*! @} */
80989 
80990 
80991 /*!
80992  * @}
80993  */ /* end of group LPCG_VC1D_Register_Masks */
80994 
80995 
80996 /* LPCG_VC1D - Peripheral instance base addresses */
80997 /** Peripheral VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED base address */
80998 #define VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED_BASE (0x2D090000u)
80999 /** Peripheral VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED base pointer */
81000 #define VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED     ((LPCG_VC1D_Type *)VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED_BASE)
81001 /** Array initializer of LPCG_VC1D peripheral base addresses */
81002 #define LPCG_VC1D_BASE_ADDRS                     { VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED_BASE }
81003 /** Array initializer of LPCG_VC1D peripheral base pointers */
81004 #define LPCG_VC1D_BASE_PTRS                      { VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED }
81005 
81006 /*!
81007  * @}
81008  */ /* end of group LPCG_VC1D_Peripheral_Access_Layer */
81009 
81010 
81011 /* ----------------------------------------------------------------------------
81012    -- LPI2C Peripheral Access Layer
81013    ---------------------------------------------------------------------------- */
81014 
81015 /*!
81016  * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
81017  * @{
81018  */
81019 
81020 /** LPI2C - Register Layout Typedef */
81021 typedef struct {
81022   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
81023   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
81024        uint8_t RESERVED_0[8];
81025   __IO uint32_t MCR;                               /**< Master Control Register, offset: 0x10 */
81026   __IO uint32_t MSR;                               /**< Master Status Register, offset: 0x14 */
81027   __IO uint32_t MIER;                              /**< Master Interrupt Enable Register, offset: 0x18 */
81028   __IO uint32_t MDER;                              /**< Master DMA Enable Register, offset: 0x1C */
81029   __IO uint32_t MCFGR0;                            /**< Master Configuration Register 0, offset: 0x20 */
81030   __IO uint32_t MCFGR1;                            /**< Master Configuration Register 1, offset: 0x24 */
81031   __IO uint32_t MCFGR2;                            /**< Master Configuration Register 2, offset: 0x28 */
81032   __IO uint32_t MCFGR3;                            /**< Master Configuration Register 3, offset: 0x2C */
81033        uint8_t RESERVED_1[16];
81034   __IO uint32_t MDMR;                              /**< Master Data Match Register, offset: 0x40 */
81035        uint8_t RESERVED_2[4];
81036   __IO uint32_t MCCR0;                             /**< Master Clock Configuration Register 0, offset: 0x48 */
81037        uint8_t RESERVED_3[4];
81038   __IO uint32_t MCCR1;                             /**< Master Clock Configuration Register 1, offset: 0x50 */
81039        uint8_t RESERVED_4[4];
81040   __IO uint32_t MFCR;                              /**< Master FIFO Control Register, offset: 0x58 */
81041   __I  uint32_t MFSR;                              /**< Master FIFO Status Register, offset: 0x5C */
81042   __O  uint32_t MTDR;                              /**< Master Transmit Data Register, offset: 0x60 */
81043        uint8_t RESERVED_5[12];
81044   __I  uint32_t MRDR;                              /**< Master Receive Data Register, offset: 0x70 */
81045        uint8_t RESERVED_6[156];
81046   __IO uint32_t SCR;                               /**< Slave Control Register, offset: 0x110 */
81047   __IO uint32_t SSR;                               /**< Slave Status Register, offset: 0x114 */
81048   __IO uint32_t SIER;                              /**< Slave Interrupt Enable Register, offset: 0x118 */
81049   __IO uint32_t SDER;                              /**< Slave DMA Enable Register, offset: 0x11C */
81050        uint8_t RESERVED_7[4];
81051   __IO uint32_t SCFGR1;                            /**< Slave Configuration Register 1, offset: 0x124 */
81052   __IO uint32_t SCFGR2;                            /**< Slave Configuration Register 2, offset: 0x128 */
81053        uint8_t RESERVED_8[20];
81054   __IO uint32_t SAMR;                              /**< Slave Address Match Register, offset: 0x140 */
81055        uint8_t RESERVED_9[12];
81056   __I  uint32_t SASR;                              /**< Slave Address Status Register, offset: 0x150 */
81057   __IO uint32_t STAR;                              /**< Slave Transmit ACK Register, offset: 0x154 */
81058        uint8_t RESERVED_10[8];
81059   __O  uint32_t STDR;                              /**< Slave Transmit Data Register, offset: 0x160 */
81060        uint8_t RESERVED_11[12];
81061   __I  uint32_t SRDR;                              /**< Slave Receive Data Register, offset: 0x170 */
81062 } LPI2C_Type;
81063 
81064 /* ----------------------------------------------------------------------------
81065    -- LPI2C Register Masks
81066    ---------------------------------------------------------------------------- */
81067 
81068 /*!
81069  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
81070  * @{
81071  */
81072 
81073 /*! @name VERID - Version ID Register */
81074 /*! @{ */
81075 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
81076 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
81077 /*! FEATURE - Feature Specification Number
81078  *  0b0000000000000010..Master only, with standard feature set
81079  *  0b0000000000000011..Master and slave, with standard feature set
81080  */
81081 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
81082 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
81083 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
81084 /*! MINOR - Minor Version Number
81085  */
81086 #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
81087 #define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
81088 #define LPI2C_VERID_MAJOR_SHIFT                  (24U)
81089 /*! MAJOR - Major Version Number
81090  */
81091 #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
81092 /*! @} */
81093 
81094 /*! @name PARAM - Parameter Register */
81095 /*! @{ */
81096 #define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
81097 #define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
81098 /*! MTXFIFO - Master Transmit FIFO Size
81099  */
81100 #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
81101 #define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
81102 #define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
81103 /*! MRXFIFO - Master Receive FIFO Size
81104  */
81105 #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
81106 /*! @} */
81107 
81108 /*! @name MCR - Master Control Register */
81109 /*! @{ */
81110 #define LPI2C_MCR_MEN_MASK                       (0x1U)
81111 #define LPI2C_MCR_MEN_SHIFT                      (0U)
81112 /*! MEN - Master Enable
81113  *  0b0..Master logic is disabled
81114  *  0b1..Master logic is enabled
81115  */
81116 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
81117 #define LPI2C_MCR_RST_MASK                       (0x2U)
81118 #define LPI2C_MCR_RST_SHIFT                      (1U)
81119 /*! RST - Software Reset
81120  *  0b0..Master logic is not reset
81121  *  0b1..Master logic is reset
81122  */
81123 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
81124 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
81125 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
81126 /*! DOZEN - Doze mode enable
81127  *  0b0..Master is enabled in Doze mode
81128  *  0b1..Master is disabled in Doze mode
81129  */
81130 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
81131 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
81132 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
81133 /*! DBGEN - Debug Enable
81134  *  0b0..Master is disabled in debug mode
81135  *  0b1..Master is enabled in debug mode
81136  */
81137 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
81138 #define LPI2C_MCR_RTF_MASK                       (0x100U)
81139 #define LPI2C_MCR_RTF_SHIFT                      (8U)
81140 /*! RTF - Reset Transmit FIFO
81141  *  0b0..No effect
81142  *  0b1..Transmit FIFO is reset
81143  */
81144 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
81145 #define LPI2C_MCR_RRF_MASK                       (0x200U)
81146 #define LPI2C_MCR_RRF_SHIFT                      (9U)
81147 /*! RRF - Reset Receive FIFO
81148  *  0b0..No effect
81149  *  0b1..Receive FIFO is reset
81150  */
81151 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
81152 /*! @} */
81153 
81154 /*! @name MSR - Master Status Register */
81155 /*! @{ */
81156 #define LPI2C_MSR_TDF_MASK                       (0x1U)
81157 #define LPI2C_MSR_TDF_SHIFT                      (0U)
81158 /*! TDF - Transmit Data Flag
81159  *  0b0..Transmit data is not requested
81160  *  0b1..Transmit data is requested
81161  */
81162 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
81163 #define LPI2C_MSR_RDF_MASK                       (0x2U)
81164 #define LPI2C_MSR_RDF_SHIFT                      (1U)
81165 /*! RDF - Receive Data Flag
81166  *  0b0..Receive Data is not ready
81167  *  0b1..Receive data is ready
81168  */
81169 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
81170 #define LPI2C_MSR_EPF_MASK                       (0x100U)
81171 #define LPI2C_MSR_EPF_SHIFT                      (8U)
81172 /*! EPF - End Packet Flag
81173  *  0b0..Master has not generated a STOP or Repeated START condition
81174  *  0b1..Master has generated a STOP or Repeated START condition
81175  */
81176 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
81177 #define LPI2C_MSR_SDF_MASK                       (0x200U)
81178 #define LPI2C_MSR_SDF_SHIFT                      (9U)
81179 /*! SDF - STOP Detect Flag
81180  *  0b0..Master has not generated a STOP condition
81181  *  0b1..Master has generated a STOP condition
81182  */
81183 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
81184 #define LPI2C_MSR_NDF_MASK                       (0x400U)
81185 #define LPI2C_MSR_NDF_SHIFT                      (10U)
81186 /*! NDF - NACK Detect Flag
81187  *  0b0..Unexpected NACK was not detected
81188  *  0b1..Unexpected NACK was detected
81189  */
81190 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
81191 #define LPI2C_MSR_ALF_MASK                       (0x800U)
81192 #define LPI2C_MSR_ALF_SHIFT                      (11U)
81193 /*! ALF - Arbitration Lost Flag
81194  *  0b0..Master has not lost arbitration
81195  *  0b1..Master has lost arbitration
81196  */
81197 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
81198 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
81199 #define LPI2C_MSR_FEF_SHIFT                      (12U)
81200 /*! FEF - FIFO Error Flag
81201  *  0b0..No error
81202  *  0b1..Master sending or receiving data without a START condition
81203  */
81204 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
81205 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
81206 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
81207 /*! PLTF - Pin Low Timeout Flag
81208  *  0b0..Pin low timeout has not occurred or is disabled
81209  *  0b1..Pin low timeout has occurred
81210  */
81211 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
81212 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
81213 #define LPI2C_MSR_DMF_SHIFT                      (14U)
81214 /*! DMF - Data Match Flag
81215  *  0b0..Have not received matching data
81216  *  0b1..Have received matching data
81217  */
81218 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
81219 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
81220 #define LPI2C_MSR_MBF_SHIFT                      (24U)
81221 /*! MBF - Master Busy Flag
81222  *  0b0..I2C Master is idle
81223  *  0b1..I2C Master is busy
81224  */
81225 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
81226 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
81227 #define LPI2C_MSR_BBF_SHIFT                      (25U)
81228 /*! BBF - Bus Busy Flag
81229  *  0b0..I2C Bus is idle
81230  *  0b1..I2C Bus is busy
81231  */
81232 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
81233 /*! @} */
81234 
81235 /*! @name MIER - Master Interrupt Enable Register */
81236 /*! @{ */
81237 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
81238 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
81239 /*! TDIE - Transmit Data Interrupt Enable
81240  *  0b0..Disabled
81241  *  0b1..Enabled
81242  */
81243 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
81244 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
81245 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
81246 /*! RDIE - Receive Data Interrupt Enable
81247  *  0b0..Disabled
81248  *  0b1..Enabled
81249  */
81250 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
81251 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
81252 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
81253 /*! EPIE - End Packet Interrupt Enable
81254  *  0b0..Disabled
81255  *  0b1..Enabled
81256  */
81257 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
81258 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
81259 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
81260 /*! SDIE - STOP Detect Interrupt Enable
81261  *  0b0..Disabled
81262  *  0b1..Enabled
81263  */
81264 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
81265 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
81266 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
81267 /*! NDIE - NACK Detect Interrupt Enable
81268  *  0b0..Disabled
81269  *  0b1..Enabled
81270  */
81271 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
81272 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
81273 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
81274 /*! ALIE - Arbitration Lost Interrupt Enable
81275  *  0b0..Disabled
81276  *  0b1..Enabled
81277  */
81278 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
81279 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
81280 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
81281 /*! FEIE - FIFO Error Interrupt Enable
81282  *  0b0..Enabled
81283  *  0b1..Disabled
81284  */
81285 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
81286 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
81287 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
81288 /*! PLTIE - Pin Low Timeout Interrupt Enable
81289  *  0b0..Disabled
81290  *  0b1..Enabled
81291  */
81292 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
81293 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
81294 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
81295 /*! DMIE - Data Match Interrupt Enable
81296  *  0b0..Disabled
81297  *  0b1..Enabled
81298  */
81299 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
81300 /*! @} */
81301 
81302 /*! @name MDER - Master DMA Enable Register */
81303 /*! @{ */
81304 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
81305 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
81306 /*! TDDE - Transmit Data DMA Enable
81307  *  0b0..DMA request is disabled
81308  *  0b1..DMA request is enabled
81309  */
81310 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
81311 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
81312 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
81313 /*! RDDE - Receive Data DMA Enable
81314  *  0b0..DMA request is disabled
81315  *  0b1..DMA request is enabled
81316  */
81317 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
81318 /*! @} */
81319 
81320 /*! @name MCFGR0 - Master Configuration Register 0 */
81321 /*! @{ */
81322 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
81323 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
81324 /*! HREN - Host Request Enable
81325  *  0b0..Host request input is disabled
81326  *  0b1..Host request input is enabled
81327  */
81328 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
81329 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
81330 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
81331 /*! HRPOL - Host Request Polarity
81332  *  0b0..Active low
81333  *  0b1..Active high
81334  */
81335 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
81336 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
81337 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
81338 /*! HRSEL - Host Request Select
81339  *  0b0..Host request input is pin HREQ
81340  *  0b1..Host request input is input trigger
81341  */
81342 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
81343 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
81344 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
81345 /*! CIRFIFO - Circular FIFO Enable
81346  *  0b0..Circular FIFO is disabled
81347  *  0b1..Circular FIFO is enabled
81348  */
81349 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
81350 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
81351 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
81352 /*! RDMO - Receive Data Match Only
81353  *  0b0..Received data is stored in the receive FIFO
81354  *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
81355  */
81356 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
81357 /*! @} */
81358 
81359 /*! @name MCFGR1 - Master Configuration Register 1 */
81360 /*! @{ */
81361 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
81362 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
81363 /*! PRESCALE - Prescaler
81364  *  0b000..Divide by 1
81365  *  0b001..Divide by 2
81366  *  0b010..Divide by 4
81367  *  0b011..Divide by 8
81368  *  0b100..Divide by 16
81369  *  0b101..Divide by 32
81370  *  0b110..Divide by 64
81371  *  0b111..Divide by 128
81372  */
81373 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
81374 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
81375 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
81376 /*! AUTOSTOP - Automatic STOP Generation
81377  *  0b0..No effect
81378  *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
81379  */
81380 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
81381 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
81382 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
81383 /*! IGNACK - IGNACK
81384  *  0b0..LPI2C Master will receive ACK and NACK normally
81385  *  0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK
81386  */
81387 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
81388 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
81389 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
81390 /*! TIMECFG - Timeout Configuration
81391  *  0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout
81392  *  0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout
81393  */
81394 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
81395 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
81396 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
81397 /*! MATCFG - Match Configuration
81398  *  0b000..Match is disabled
81399  *  0b001..Reserved
81400  *  0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1)
81401  *  0b011..Match is enabled (any data word equals MATCH0 OR MATCH1)
81402  *  0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
81403  *  0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
81404  *  0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
81405  *  0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
81406  */
81407 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
81408 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
81409 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
81410 /*! PINCFG - Pin Configuration
81411  *  0b000..2-pin open drain mode
81412  *  0b001..2-pin output only mode (ultra-fast mode)
81413  *  0b010..2-pin push-pull mode
81414  *  0b011..4-pin push-pull mode
81415  *  0b100..2-pin open drain mode with separate LPI2C slave
81416  *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
81417  *  0b110..2-pin push-pull mode with separate LPI2C slave
81418  *  0b111..4-pin push-pull mode (inverted outputs)
81419  */
81420 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
81421 /*! @} */
81422 
81423 /*! @name MCFGR2 - Master Configuration Register 2 */
81424 /*! @{ */
81425 #define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
81426 #define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
81427 /*! BUSIDLE - Bus Idle Timeout
81428  */
81429 #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
81430 #define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
81431 #define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
81432 /*! FILTSCL - Glitch Filter SCL
81433  */
81434 #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
81435 #define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
81436 #define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
81437 /*! FILTSDA - Glitch Filter SDA
81438  */
81439 #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
81440 /*! @} */
81441 
81442 /*! @name MCFGR3 - Master Configuration Register 3 */
81443 /*! @{ */
81444 #define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
81445 #define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
81446 /*! PINLOW - Pin Low Timeout
81447  */
81448 #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
81449 /*! @} */
81450 
81451 /*! @name MDMR - Master Data Match Register */
81452 /*! @{ */
81453 #define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
81454 #define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
81455 /*! MATCH0 - Match 0 Value
81456  */
81457 #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
81458 #define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
81459 #define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
81460 /*! MATCH1 - Match 1 Value
81461  */
81462 #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
81463 /*! @} */
81464 
81465 /*! @name MCCR0 - Master Clock Configuration Register 0 */
81466 /*! @{ */
81467 #define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
81468 #define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
81469 /*! CLKLO - Clock Low Period
81470  */
81471 #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
81472 #define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
81473 #define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
81474 /*! CLKHI - Clock High Period
81475  */
81476 #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
81477 #define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
81478 #define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
81479 /*! SETHOLD - Setup Hold Delay
81480  */
81481 #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
81482 #define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
81483 #define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
81484 /*! DATAVD - Data Valid Delay
81485  */
81486 #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
81487 /*! @} */
81488 
81489 /*! @name MCCR1 - Master Clock Configuration Register 1 */
81490 /*! @{ */
81491 #define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
81492 #define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
81493 /*! CLKLO - Clock Low Period
81494  */
81495 #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
81496 #define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
81497 #define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
81498 /*! CLKHI - Clock High Period
81499  */
81500 #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
81501 #define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
81502 #define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
81503 /*! SETHOLD - Setup Hold Delay
81504  */
81505 #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
81506 #define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
81507 #define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
81508 /*! DATAVD - Data Valid Delay
81509  */
81510 #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
81511 /*! @} */
81512 
81513 /*! @name MFCR - Master FIFO Control Register */
81514 /*! @{ */
81515 #define LPI2C_MFCR_TXWATER_MASK                  (0xFU)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
81516 #define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
81517 /*! TXWATER - Transmit FIFO Watermark
81518  */
81519 #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
81520 #define LPI2C_MFCR_RXWATER_MASK                  (0xF0000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
81521 #define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
81522 /*! RXWATER - Receive FIFO Watermark
81523  */
81524 #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
81525 /*! @} */
81526 
81527 /*! @name MFSR - Master FIFO Status Register */
81528 /*! @{ */
81529 #define LPI2C_MFSR_TXCOUNT_MASK                  (0x1FU)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
81530 #define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
81531 /*! TXCOUNT - Transmit FIFO Count
81532  */
81533 #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
81534 #define LPI2C_MFSR_RXCOUNT_MASK                  (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
81535 #define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
81536 /*! RXCOUNT - Receive FIFO Count
81537  */
81538 #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
81539 /*! @} */
81540 
81541 /*! @name MTDR - Master Transmit Data Register */
81542 /*! @{ */
81543 #define LPI2C_MTDR_DATA_MASK                     (0xFFU)
81544 #define LPI2C_MTDR_DATA_SHIFT                    (0U)
81545 /*! DATA - Transmit Data
81546  */
81547 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
81548 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
81549 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
81550 /*! CMD - Command Data
81551  *  0b000..Transmit DATA[7:0]
81552  *  0b001..Receive (DATA[7:0] + 1) bytes
81553  *  0b010..Generate STOP condition
81554  *  0b011..Receive and discard (DATA[7:0] + 1) bytes
81555  *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
81556  *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
81557  *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
81558  *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
81559  */
81560 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
81561 /*! @} */
81562 
81563 /*! @name MRDR - Master Receive Data Register */
81564 /*! @{ */
81565 #define LPI2C_MRDR_DATA_MASK                     (0xFFU)
81566 #define LPI2C_MRDR_DATA_SHIFT                    (0U)
81567 /*! DATA - Receive Data
81568  */
81569 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
81570 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
81571 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
81572 /*! RXEMPTY - RX Empty
81573  *  0b0..Receive FIFO is not empty
81574  *  0b1..Receive FIFO is empty
81575  */
81576 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
81577 /*! @} */
81578 
81579 /*! @name SCR - Slave Control Register */
81580 /*! @{ */
81581 #define LPI2C_SCR_SEN_MASK                       (0x1U)
81582 #define LPI2C_SCR_SEN_SHIFT                      (0U)
81583 /*! SEN - Slave Enable
81584  *  0b0..I2C Slave mode is disabled
81585  *  0b1..I2C Slave mode is enabled
81586  */
81587 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
81588 #define LPI2C_SCR_RST_MASK                       (0x2U)
81589 #define LPI2C_SCR_RST_SHIFT                      (1U)
81590 /*! RST - Software Reset
81591  *  0b0..Slave mode logic is not reset
81592  *  0b1..Slave mode logic is reset
81593  */
81594 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
81595 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
81596 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
81597 /*! FILTEN - Filter Enable
81598  *  0b0..Disable digital filter and output delay counter for slave mode
81599  *  0b1..Enable digital filter and output delay counter for slave mode
81600  */
81601 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
81602 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
81603 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
81604 /*! FILTDZ - Filter Doze Enable
81605  *  0b0..Filter remains enabled in Doze mode
81606  *  0b1..Filter is disabled in Doze mode
81607  */
81608 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
81609 #define LPI2C_SCR_RTF_MASK                       (0x100U)
81610 #define LPI2C_SCR_RTF_SHIFT                      (8U)
81611 /*! RTF - Reset Transmit FIFO
81612  *  0b0..No effect
81613  *  0b1..Transmit Data Register is now empty
81614  */
81615 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
81616 #define LPI2C_SCR_RRF_MASK                       (0x200U)
81617 #define LPI2C_SCR_RRF_SHIFT                      (9U)
81618 /*! RRF - Reset Receive FIFO
81619  *  0b0..No effect
81620  *  0b1..Receive Data Register is now empty
81621  */
81622 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
81623 /*! @} */
81624 
81625 /*! @name SSR - Slave Status Register */
81626 /*! @{ */
81627 #define LPI2C_SSR_TDF_MASK                       (0x1U)
81628 #define LPI2C_SSR_TDF_SHIFT                      (0U)
81629 /*! TDF - Transmit Data Flag
81630  *  0b0..Transmit data not requested
81631  *  0b1..Transmit data is requested
81632  */
81633 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
81634 #define LPI2C_SSR_RDF_MASK                       (0x2U)
81635 #define LPI2C_SSR_RDF_SHIFT                      (1U)
81636 /*! RDF - Receive Data Flag
81637  *  0b0..Receive data is not ready
81638  *  0b1..Receive data is ready
81639  */
81640 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
81641 #define LPI2C_SSR_AVF_MASK                       (0x4U)
81642 #define LPI2C_SSR_AVF_SHIFT                      (2U)
81643 /*! AVF - Address Valid Flag
81644  *  0b0..Address Status Register is not valid
81645  *  0b1..Address Status Register is valid
81646  */
81647 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
81648 #define LPI2C_SSR_TAF_MASK                       (0x8U)
81649 #define LPI2C_SSR_TAF_SHIFT                      (3U)
81650 /*! TAF - Transmit ACK Flag
81651  *  0b0..Transmit ACK/NACK is not required
81652  *  0b1..Transmit ACK/NACK is required
81653  */
81654 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
81655 #define LPI2C_SSR_RSF_MASK                       (0x100U)
81656 #define LPI2C_SSR_RSF_SHIFT                      (8U)
81657 /*! RSF - Repeated Start Flag
81658  *  0b0..Slave has not detected a Repeated START condition
81659  *  0b1..Slave has detected a Repeated START condition
81660  */
81661 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
81662 #define LPI2C_SSR_SDF_MASK                       (0x200U)
81663 #define LPI2C_SSR_SDF_SHIFT                      (9U)
81664 /*! SDF - STOP Detect Flag
81665  *  0b0..Slave has not detected a STOP condition
81666  *  0b1..Slave has detected a STOP condition
81667  */
81668 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
81669 #define LPI2C_SSR_BEF_MASK                       (0x400U)
81670 #define LPI2C_SSR_BEF_SHIFT                      (10U)
81671 /*! BEF - Bit Error Flag
81672  *  0b0..Slave has not detected a bit error
81673  *  0b1..Slave has detected a bit error
81674  */
81675 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
81676 #define LPI2C_SSR_FEF_MASK                       (0x800U)
81677 #define LPI2C_SSR_FEF_SHIFT                      (11U)
81678 /*! FEF - FIFO Error Flag
81679  *  0b0..FIFO underflow or overflow was not detected
81680  *  0b1..FIFO underflow or overflow was detected
81681  */
81682 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
81683 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
81684 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
81685 /*! AM0F - Address Match 0 Flag
81686  *  0b0..Have not received an ADDR0 matching address
81687  *  0b1..Have received an ADDR0 matching address
81688  */
81689 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
81690 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
81691 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
81692 /*! AM1F - Address Match 1 Flag
81693  *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
81694  *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
81695  */
81696 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
81697 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
81698 #define LPI2C_SSR_GCF_SHIFT                      (14U)
81699 /*! GCF - General Call Flag
81700  *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
81701  *  0b1..Slave has detected the General Call Address
81702  */
81703 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
81704 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
81705 #define LPI2C_SSR_SARF_SHIFT                     (15U)
81706 /*! SARF - SMBus Alert Response Flag
81707  *  0b0..SMBus Alert Response is disabled or not detected
81708  *  0b1..SMBus Alert Response is enabled and detected
81709  */
81710 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
81711 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
81712 #define LPI2C_SSR_SBF_SHIFT                      (24U)
81713 /*! SBF - Slave Busy Flag
81714  *  0b0..I2C Slave is idle
81715  *  0b1..I2C Slave is busy
81716  */
81717 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
81718 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
81719 #define LPI2C_SSR_BBF_SHIFT                      (25U)
81720 /*! BBF - Bus Busy Flag
81721  *  0b0..I2C Bus is idle
81722  *  0b1..I2C Bus is busy
81723  */
81724 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
81725 /*! @} */
81726 
81727 /*! @name SIER - Slave Interrupt Enable Register */
81728 /*! @{ */
81729 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
81730 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
81731 /*! TDIE - Transmit Data Interrupt Enable
81732  *  0b0..Disabled
81733  *  0b1..Enabled
81734  */
81735 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
81736 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
81737 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
81738 /*! RDIE - Receive Data Interrupt Enable
81739  *  0b0..Disabled
81740  *  0b1..Enabled
81741  */
81742 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
81743 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
81744 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
81745 /*! AVIE - Address Valid Interrupt Enable
81746  *  0b0..Disabled
81747  *  0b1..Enabled
81748  */
81749 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
81750 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
81751 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
81752 /*! TAIE - Transmit ACK Interrupt Enable
81753  *  0b0..Disabled
81754  *  0b1..Enabled
81755  */
81756 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
81757 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
81758 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
81759 /*! RSIE - Repeated Start Interrupt Enable
81760  *  0b0..Disabled
81761  *  0b1..Enabled
81762  */
81763 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
81764 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
81765 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
81766 /*! SDIE - STOP Detect Interrupt Enable
81767  *  0b0..Disabled
81768  *  0b1..Enabled
81769  */
81770 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
81771 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
81772 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
81773 /*! BEIE - Bit Error Interrupt Enable
81774  *  0b0..Disabled
81775  *  0b1..Enabled
81776  */
81777 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
81778 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
81779 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
81780 /*! FEIE - FIFO Error Interrupt Enable
81781  *  0b0..Disabled
81782  *  0b1..Enabled
81783  */
81784 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
81785 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
81786 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
81787 /*! AM0IE - Address Match 0 Interrupt Enable
81788  *  0b0..Enabled
81789  *  0b1..Disabled
81790  */
81791 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
81792 #define LPI2C_SIER_AM1F_MASK                     (0x2000U)
81793 #define LPI2C_SIER_AM1F_SHIFT                    (13U)
81794 /*! AM1F - Address Match 1 Interrupt Enable
81795  *  0b0..Disabled
81796  *  0b1..Enabled
81797  */
81798 #define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
81799 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
81800 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
81801 /*! GCIE - General Call Interrupt Enable
81802  *  0b0..Disabled
81803  *  0b1..Enabled
81804  */
81805 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
81806 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
81807 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
81808 /*! SARIE - SMBus Alert Response Interrupt Enable
81809  *  0b0..Disabled
81810  *  0b1..Enabled
81811  */
81812 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
81813 /*! @} */
81814 
81815 /*! @name SDER - Slave DMA Enable Register */
81816 /*! @{ */
81817 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
81818 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
81819 /*! TDDE - Transmit Data DMA Enable
81820  *  0b0..DMA request is disabled
81821  *  0b1..DMA request is enabled
81822  */
81823 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
81824 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
81825 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
81826 /*! RDDE - Receive Data DMA Enable
81827  *  0b0..DMA request is disabled
81828  *  0b1..DMA request is enabled
81829  */
81830 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
81831 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
81832 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
81833 /*! AVDE - Address Valid DMA Enable
81834  *  0b0..DMA request is disabled
81835  *  0b1..DMA request is enabled
81836  */
81837 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
81838 #define LPI2C_SDER_RSDE_MASK                     (0x100U)
81839 #define LPI2C_SDER_RSDE_SHIFT                    (8U)
81840 /*! RSDE - Repeated Start DMA Enable
81841  *  0b0..DMA request is disabled
81842  *  0b1..DMA request is enabled
81843  */
81844 #define LPI2C_SDER_RSDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK)
81845 #define LPI2C_SDER_SDDE_MASK                     (0x200U)
81846 #define LPI2C_SDER_SDDE_SHIFT                    (9U)
81847 /*! SDDE - Stop Detect DMA Enable
81848  *  0b0..DMA request is disabled
81849  *  0b1..DMA request is enabled
81850  */
81851 #define LPI2C_SDER_SDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK)
81852 /*! @} */
81853 
81854 /*! @name SCFGR1 - Slave Configuration Register 1 */
81855 /*! @{ */
81856 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
81857 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
81858 /*! ADRSTALL - Address SCL Stall
81859  *  0b0..Clock stretching is disabled
81860  *  0b1..Clock stretching is enabled
81861  */
81862 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
81863 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
81864 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
81865 /*! RXSTALL - RX SCL Stall
81866  *  0b0..Clock stretching is disabled
81867  *  0b1..Clock stretching is enabled
81868  */
81869 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
81870 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
81871 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
81872 /*! TXDSTALL - TX Data SCL Stall
81873  *  0b0..Clock stretching is disabled
81874  *  0b1..Clock stretching is enabled
81875  */
81876 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
81877 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
81878 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
81879 /*! ACKSTALL - ACK SCL Stall
81880  *  0b0..Clock stretching is disabled
81881  *  0b1..Clock stretching is enabled
81882  */
81883 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
81884 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
81885 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
81886 /*! GCEN - General Call Enable
81887  *  0b0..General Call address is disabled
81888  *  0b1..General Call address is enabled
81889  */
81890 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
81891 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
81892 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
81893 /*! SAEN - SMBus Alert Enable
81894  *  0b0..Disables match on SMBus Alert
81895  *  0b1..Enables match on SMBus Alert
81896  */
81897 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
81898 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
81899 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
81900 /*! TXCFG - Transmit Flag Configuration
81901  *  0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty
81902  *  0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty
81903  */
81904 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
81905 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
81906 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
81907 /*! RXCFG - Receive Data Configuration
81908  *  0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).
81909  *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address
81910  *       Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid
81911  *       flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).
81912  */
81913 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
81914 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
81915 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
81916 /*! IGNACK - Ignore NACK
81917  *  0b0..Slave will end transfer when NACK is detected
81918  *  0b1..Slave will not end transfer when NACK detected
81919  */
81920 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
81921 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
81922 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
81923 /*! HSMEN - High Speed Mode Enable
81924  *  0b0..Disables detection of HS-mode master code
81925  *  0b1..Enables detection of HS-mode master code
81926  */
81927 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
81928 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
81929 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
81930 /*! ADDRCFG - Address Configuration
81931  *  0b000..Address match 0 (7-bit)
81932  *  0b001..Address match 0 (10-bit)
81933  *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
81934  *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
81935  *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
81936  *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
81937  *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
81938  *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
81939  */
81940 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
81941 /*! @} */
81942 
81943 /*! @name SCFGR2 - Slave Configuration Register 2 */
81944 /*! @{ */
81945 #define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
81946 #define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
81947 /*! CLKHOLD - Clock Hold Time
81948  */
81949 #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
81950 #define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
81951 #define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
81952 /*! DATAVD - Data Valid Delay
81953  */
81954 #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
81955 #define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
81956 #define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
81957 /*! FILTSCL - Glitch Filter SCL
81958  */
81959 #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
81960 #define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
81961 #define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
81962 /*! FILTSDA - Glitch Filter SDA
81963  */
81964 #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
81965 /*! @} */
81966 
81967 /*! @name SAMR - Slave Address Match Register */
81968 /*! @{ */
81969 #define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
81970 #define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
81971 /*! ADDR0 - Address 0 Value
81972  */
81973 #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
81974 #define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
81975 #define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
81976 /*! ADDR1 - Address 1 Value
81977  */
81978 #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
81979 /*! @} */
81980 
81981 /*! @name SASR - Slave Address Status Register */
81982 /*! @{ */
81983 #define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
81984 #define LPI2C_SASR_RADDR_SHIFT                   (0U)
81985 /*! RADDR - Received Address
81986  */
81987 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
81988 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
81989 #define LPI2C_SASR_ANV_SHIFT                     (14U)
81990 /*! ANV - Address Not Valid
81991  *  0b0..Received Address (RADDR) is valid
81992  *  0b1..Received Address (RADDR) is not valid
81993  */
81994 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
81995 /*! @} */
81996 
81997 /*! @name STAR - Slave Transmit ACK Register */
81998 /*! @{ */
81999 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
82000 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
82001 /*! TXNACK - Transmit NACK
82002  *  0b0..Write a Transmit ACK for each received word
82003  *  0b1..Write a Transmit NACK for each received word
82004  */
82005 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
82006 /*! @} */
82007 
82008 /*! @name STDR - Slave Transmit Data Register */
82009 /*! @{ */
82010 #define LPI2C_STDR_DATA_MASK                     (0xFFU)
82011 #define LPI2C_STDR_DATA_SHIFT                    (0U)
82012 /*! DATA - Transmit Data
82013  */
82014 #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
82015 /*! @} */
82016 
82017 /*! @name SRDR - Slave Receive Data Register */
82018 /*! @{ */
82019 #define LPI2C_SRDR_DATA_MASK                     (0xFFU)
82020 #define LPI2C_SRDR_DATA_SHIFT                    (0U)
82021 /*! DATA - Receive Data
82022  */
82023 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
82024 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
82025 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
82026 /*! RXEMPTY - RX Empty
82027  *  0b0..The Receive Data Register is not empty
82028  *  0b1..The Receive Data Register is empty
82029  */
82030 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
82031 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
82032 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
82033 /*! SOF - Start Of Frame
82034  *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
82035  *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
82036  */
82037 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
82038 /*! @} */
82039 
82040 
82041 /*!
82042  * @}
82043  */ /* end of group LPI2C_Register_Masks */
82044 
82045 
82046 /* LPI2C - Peripheral instance base addresses */
82047 /** Peripheral ADMA__LPI2C0 base address */
82048 #define ADMA__LPI2C0_BASE                        (0x5A800000u)
82049 /** Peripheral ADMA__LPI2C0 base pointer */
82050 #define ADMA__LPI2C0                             ((LPI2C_Type *)ADMA__LPI2C0_BASE)
82051 /** Peripheral ADMA__LPI2C1 base address */
82052 #define ADMA__LPI2C1_BASE                        (0x5A810000u)
82053 /** Peripheral ADMA__LPI2C1 base pointer */
82054 #define ADMA__LPI2C1                             ((LPI2C_Type *)ADMA__LPI2C1_BASE)
82055 /** Peripheral ADMA__LPI2C2 base address */
82056 #define ADMA__LPI2C2_BASE                        (0x5A820000u)
82057 /** Peripheral ADMA__LPI2C2 base pointer */
82058 #define ADMA__LPI2C2                             ((LPI2C_Type *)ADMA__LPI2C2_BASE)
82059 /** Peripheral ADMA__LPI2C3 base address */
82060 #define ADMA__LPI2C3_BASE                        (0x5A830000u)
82061 /** Peripheral ADMA__LPI2C3 base pointer */
82062 #define ADMA__LPI2C3                             ((LPI2C_Type *)ADMA__LPI2C3_BASE)
82063 /** Peripheral CI_PI__LPI2C0 base address */
82064 #define CI_PI__LPI2C0_BASE                       (0x58266000u)
82065 /** Peripheral CI_PI__LPI2C0 base pointer */
82066 #define CI_PI__LPI2C0                            ((LPI2C_Type *)CI_PI__LPI2C0_BASE)
82067 /** Peripheral CM4__LPI2C base address */
82068 #define CM4__LPI2C_BASE                          (0x41230000u)
82069 /** Peripheral CM4__LPI2C base pointer */
82070 #define CM4__LPI2C                               ((LPI2C_Type *)CM4__LPI2C_BASE)
82071 /** Peripheral DI_MIPI_DSI_LVDS_0__LPI2C0 base address */
82072 #define DI_MIPI_DSI_LVDS_0__LPI2C0_BASE          (0x56226000u)
82073 /** Peripheral DI_MIPI_DSI_LVDS_0__LPI2C0 base pointer */
82074 #define DI_MIPI_DSI_LVDS_0__LPI2C0               ((LPI2C_Type *)DI_MIPI_DSI_LVDS_0__LPI2C0_BASE)
82075 /** Peripheral DI_MIPI_DSI_LVDS_0__LPI2C1 base address */
82076 #define DI_MIPI_DSI_LVDS_0__LPI2C1_BASE          (0x56227000u)
82077 /** Peripheral DI_MIPI_DSI_LVDS_0__LPI2C1 base pointer */
82078 #define DI_MIPI_DSI_LVDS_0__LPI2C1               ((LPI2C_Type *)DI_MIPI_DSI_LVDS_0__LPI2C1_BASE)
82079 /** Peripheral DI_MIPI_DSI_LVDS_1__LPI2C0 base address */
82080 #define DI_MIPI_DSI_LVDS_1__LPI2C0_BASE          (0x56246000u)
82081 /** Peripheral DI_MIPI_DSI_LVDS_1__LPI2C0 base pointer */
82082 #define DI_MIPI_DSI_LVDS_1__LPI2C0               ((LPI2C_Type *)DI_MIPI_DSI_LVDS_1__LPI2C0_BASE)
82083 /** Peripheral DI_MIPI_DSI_LVDS_1__LPI2C1 base address */
82084 #define DI_MIPI_DSI_LVDS_1__LPI2C1_BASE          (0x56247000u)
82085 /** Peripheral DI_MIPI_DSI_LVDS_1__LPI2C1 base pointer */
82086 #define DI_MIPI_DSI_LVDS_1__LPI2C1               ((LPI2C_Type *)DI_MIPI_DSI_LVDS_1__LPI2C1_BASE)
82087 /** Peripheral MIPI_CSI__LPI2C base address */
82088 #define MIPI_CSI__LPI2C_BASE                     (0x58226000u)
82089 /** Peripheral MIPI_CSI__LPI2C base pointer */
82090 #define MIPI_CSI__LPI2C                          ((LPI2C_Type *)MIPI_CSI__LPI2C_BASE)
82091 /** Peripheral SCU__LPI2C base address */
82092 #define SCU__LPI2C_BASE                          (0x33230000u)
82093 /** Peripheral SCU__LPI2C base pointer */
82094 #define SCU__LPI2C                               ((LPI2C_Type *)SCU__LPI2C_BASE)
82095 /** Array initializer of LPI2C peripheral base addresses */
82096 #define LPI2C_BASE_ADDRS                         { ADMA__LPI2C0_BASE, ADMA__LPI2C1_BASE, ADMA__LPI2C2_BASE, ADMA__LPI2C3_BASE, CI_PI__LPI2C0_BASE, CM4__LPI2C_BASE, DI_MIPI_DSI_LVDS_0__LPI2C0_BASE, DI_MIPI_DSI_LVDS_0__LPI2C1_BASE, DI_MIPI_DSI_LVDS_1__LPI2C0_BASE, DI_MIPI_DSI_LVDS_1__LPI2C1_BASE, MIPI_CSI__LPI2C_BASE, SCU__LPI2C_BASE }
82097 /** Array initializer of LPI2C peripheral base pointers */
82098 #define LPI2C_BASE_PTRS                          { ADMA__LPI2C0, ADMA__LPI2C1, ADMA__LPI2C2, ADMA__LPI2C3, CI_PI__LPI2C0, CM4__LPI2C, DI_MIPI_DSI_LVDS_0__LPI2C0, DI_MIPI_DSI_LVDS_0__LPI2C1, DI_MIPI_DSI_LVDS_1__LPI2C0, DI_MIPI_DSI_LVDS_1__LPI2C1, MIPI_CSI__LPI2C, SCU__LPI2C }
82099 /** Interrupt vectors for the LPI2C peripheral type */
82100 #define LPI2C_IRQS                               { ADMA_I2C0_INT_IRQn, ADMA_I2C1_INT_IRQn, ADMA_I2C2_INT_IRQn, ADMA_I2C3_INT_IRQn, NotAvail_IRQn, M4_LPI2C_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
82101 
82102 /*!
82103  * @}
82104  */ /* end of group LPI2C_Peripheral_Access_Layer */
82105 
82106 
82107 /* ----------------------------------------------------------------------------
82108    -- LPIT Peripheral Access Layer
82109    ---------------------------------------------------------------------------- */
82110 
82111 /*!
82112  * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
82113  * @{
82114  */
82115 
82116 /** LPIT - Register Layout Typedef */
82117 typedef struct {
82118   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
82119   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
82120   __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x8 */
82121   __IO uint32_t MSR;                               /**< Module Status Register, offset: 0xC */
82122   __IO uint32_t MIER;                              /**< Module Interrupt Enable Register, offset: 0x10 */
82123   __IO uint32_t SETTEN;                            /**< Set Timer Enable Register, offset: 0x14 */
82124   __O  uint32_t CLRTEN;                            /**< Clear Timer Enable Register, offset: 0x18 */
82125        uint8_t RESERVED_0[4];
82126   struct {                                         /* offset: 0x20, array step: 0x10 */
82127     __IO uint32_t TVAL;                              /**< Timer Value Register, array offset: 0x20, array step: 0x10 */
82128     __I  uint32_t CVAL;                              /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
82129     __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x28, array step: 0x10 */
82130          uint8_t RESERVED_0[4];
82131   } CHANNEL[4];
82132 } LPIT_Type;
82133 
82134 /* ----------------------------------------------------------------------------
82135    -- LPIT Register Masks
82136    ---------------------------------------------------------------------------- */
82137 
82138 /*!
82139  * @addtogroup LPIT_Register_Masks LPIT Register Masks
82140  * @{
82141  */
82142 
82143 /*! @name VERID - Version ID Register */
82144 /*! @{ */
82145 #define LPIT_VERID_FEATURE_MASK                  (0xFFFFU)
82146 #define LPIT_VERID_FEATURE_SHIFT                 (0U)
82147 /*! FEATURE - Feature Number
82148  */
82149 #define LPIT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK)
82150 #define LPIT_VERID_MINOR_MASK                    (0xFF0000U)
82151 #define LPIT_VERID_MINOR_SHIFT                   (16U)
82152 /*! MINOR - Minor Version Number
82153  */
82154 #define LPIT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK)
82155 #define LPIT_VERID_MAJOR_MASK                    (0xFF000000U)
82156 #define LPIT_VERID_MAJOR_SHIFT                   (24U)
82157 /*! MAJOR - Major Version Number
82158  */
82159 #define LPIT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK)
82160 /*! @} */
82161 
82162 /*! @name PARAM - Parameter Register */
82163 /*! @{ */
82164 #define LPIT_PARAM_CHANNEL_MASK                  (0xFFU)
82165 #define LPIT_PARAM_CHANNEL_SHIFT                 (0U)
82166 /*! CHANNEL - Number of Timer Channels
82167  */
82168 #define LPIT_PARAM_CHANNEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK)
82169 #define LPIT_PARAM_EXT_TRIG_MASK                 (0xFF00U)
82170 #define LPIT_PARAM_EXT_TRIG_SHIFT                (8U)
82171 /*! EXT_TRIG - Number of External Trigger Inputs
82172  */
82173 #define LPIT_PARAM_EXT_TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK)
82174 /*! @} */
82175 
82176 /*! @name MCR - Module Control Register */
82177 /*! @{ */
82178 #define LPIT_MCR_M_CEN_MASK                      (0x1U)
82179 #define LPIT_MCR_M_CEN_SHIFT                     (0U)
82180 /*! M_CEN - Module Clock Enable
82181  *  0b0..Disable peripheral clock to timers
82182  *  0b1..Enable peripheral clock to timers
82183  */
82184 #define LPIT_MCR_M_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK)
82185 #define LPIT_MCR_SW_RST_MASK                     (0x2U)
82186 #define LPIT_MCR_SW_RST_SHIFT                    (1U)
82187 /*! SW_RST - Software Reset Bit
82188  *  0b0..Timer channels and registers are not reset
82189  *  0b1..Reset timer channels and registers
82190  */
82191 #define LPIT_MCR_SW_RST(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)
82192 #define LPIT_MCR_DOZE_EN_MASK                    (0x4U)
82193 #define LPIT_MCR_DOZE_EN_SHIFT                   (2U)
82194 /*! DOZE_EN - DOZE Mode Enable Bit
82195  *  0b0..Stop timer channels in DOZE mode
82196  *  0b1..Allow timer channels to continue to run in DOZE mode
82197  */
82198 #define LPIT_MCR_DOZE_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK)
82199 #define LPIT_MCR_DBG_EN_MASK                     (0x8U)
82200 #define LPIT_MCR_DBG_EN_SHIFT                    (3U)
82201 /*! DBG_EN - Debug Enable Bit
82202  *  0b0..Stop timer channels in Debug mode
82203  *  0b1..Allow timer channels to continue to run in Debug mode
82204  */
82205 #define LPIT_MCR_DBG_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK)
82206 /*! @} */
82207 
82208 /*! @name MSR - Module Status Register */
82209 /*! @{ */
82210 #define LPIT_MSR_TIF0_MASK                       (0x1U)
82211 #define LPIT_MSR_TIF0_SHIFT                      (0U)
82212 /*! TIF0 - Channel 0 Timer Interrupt Flag
82213  *  0b0..Timer has not timed out
82214  *  0b1..Timeout has occurred (timer has timed out)
82215  */
82216 #define LPIT_MSR_TIF0(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK)
82217 #define LPIT_MSR_TIF1_MASK                       (0x2U)
82218 #define LPIT_MSR_TIF1_SHIFT                      (1U)
82219 /*! TIF1 - Channel 1 Timer Interrupt Flag
82220  *  0b0..Timer has not timed out
82221  *  0b1..Timeout has occurred (timer has timed out)
82222  */
82223 #define LPIT_MSR_TIF1(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK)
82224 #define LPIT_MSR_TIF2_MASK                       (0x4U)
82225 #define LPIT_MSR_TIF2_SHIFT                      (2U)
82226 /*! TIF2 - Channel 2 Timer Interrupt Flag
82227  *  0b0..Timer has not timed out
82228  *  0b1..Timeout has occurred (timer has timed out)
82229  */
82230 #define LPIT_MSR_TIF2(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK)
82231 #define LPIT_MSR_TIF3_MASK                       (0x8U)
82232 #define LPIT_MSR_TIF3_SHIFT                      (3U)
82233 /*! TIF3 - Channel 3 Timer Interrupt Flag
82234  *  0b0..Timer has not timed out
82235  *  0b1..Timeout has occurred (timer has timed out)
82236  */
82237 #define LPIT_MSR_TIF3(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK)
82238 /*! @} */
82239 
82240 /*! @name MIER - Module Interrupt Enable Register */
82241 /*! @{ */
82242 #define LPIT_MIER_TIE0_MASK                      (0x1U)
82243 #define LPIT_MIER_TIE0_SHIFT                     (0U)
82244 /*! TIE0 - Channel 0 Timer Interrupt Enable
82245  *  0b0..Disabled
82246  *  0b1..Enabled
82247  */
82248 #define LPIT_MIER_TIE0(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK)
82249 #define LPIT_MIER_TIE1_MASK                      (0x2U)
82250 #define LPIT_MIER_TIE1_SHIFT                     (1U)
82251 /*! TIE1 - Channel 1 Timer Interrupt Enable
82252  *  0b0..Disabled
82253  *  0b1..Enabled
82254  */
82255 #define LPIT_MIER_TIE1(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK)
82256 #define LPIT_MIER_TIE2_MASK                      (0x4U)
82257 #define LPIT_MIER_TIE2_SHIFT                     (2U)
82258 /*! TIE2 - Channel 2 Timer Interrupt Enable
82259  *  0b0..Disabled
82260  *  0b1..Enabled
82261  */
82262 #define LPIT_MIER_TIE2(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK)
82263 #define LPIT_MIER_TIE3_MASK                      (0x8U)
82264 #define LPIT_MIER_TIE3_SHIFT                     (3U)
82265 /*! TIE3 - Channel 3 Timer Interrupt Enable
82266  *  0b0..Disabled
82267  *  0b1..Enabled
82268  */
82269 #define LPIT_MIER_TIE3(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK)
82270 /*! @} */
82271 
82272 /*! @name SETTEN - Set Timer Enable Register */
82273 /*! @{ */
82274 #define LPIT_SETTEN_SET_T_EN_0_MASK              (0x1U)
82275 #define LPIT_SETTEN_SET_T_EN_0_SHIFT             (0U)
82276 /*! SET_T_EN_0 - Set Timer 0 Enable
82277  *  0b0..No effect
82278  *  0b1..Enables Timer Channel 0
82279  */
82280 #define LPIT_SETTEN_SET_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK)
82281 #define LPIT_SETTEN_SET_T_EN_1_MASK              (0x2U)
82282 #define LPIT_SETTEN_SET_T_EN_1_SHIFT             (1U)
82283 /*! SET_T_EN_1 - Set Timer 1 Enable
82284  *  0b0..No Effect
82285  *  0b1..Enables Timer Channel 1
82286  */
82287 #define LPIT_SETTEN_SET_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK)
82288 #define LPIT_SETTEN_SET_T_EN_2_MASK              (0x4U)
82289 #define LPIT_SETTEN_SET_T_EN_2_SHIFT             (2U)
82290 /*! SET_T_EN_2 - Set Timer 2 Enable
82291  *  0b0..No Effect
82292  *  0b1..Enables Timer Channel 2
82293  */
82294 #define LPIT_SETTEN_SET_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK)
82295 #define LPIT_SETTEN_SET_T_EN_3_MASK              (0x8U)
82296 #define LPIT_SETTEN_SET_T_EN_3_SHIFT             (3U)
82297 /*! SET_T_EN_3 - Set Timer 3 Enable
82298  *  0b0..No effect
82299  *  0b1..Enables Timer Channel 3
82300  */
82301 #define LPIT_SETTEN_SET_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK)
82302 /*! @} */
82303 
82304 /*! @name CLRTEN - Clear Timer Enable Register */
82305 /*! @{ */
82306 #define LPIT_CLRTEN_CLR_T_EN_0_MASK              (0x1U)
82307 #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT             (0U)
82308 /*! CLR_T_EN_0 - Clear Timer 0 Enable
82309  *  0b0..No action
82310  *  0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0
82311  */
82312 #define LPIT_CLRTEN_CLR_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK)
82313 #define LPIT_CLRTEN_CLR_T_EN_1_MASK              (0x2U)
82314 #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT             (1U)
82315 /*! CLR_T_EN_1 - Clear Timer 1 Enable
82316  *  0b0..No Action
82317  *  0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1
82318  */
82319 #define LPIT_CLRTEN_CLR_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK)
82320 #define LPIT_CLRTEN_CLR_T_EN_2_MASK              (0x4U)
82321 #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT             (2U)
82322 /*! CLR_T_EN_2 - Clear Timer 2 Enable
82323  *  0b0..No Action
82324  *  0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2
82325  */
82326 #define LPIT_CLRTEN_CLR_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK)
82327 #define LPIT_CLRTEN_CLR_T_EN_3_MASK              (0x8U)
82328 #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT             (3U)
82329 /*! CLR_T_EN_3 - Clear Timer 3 Enable
82330  *  0b0..No Action
82331  *  0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3
82332  */
82333 #define LPIT_CLRTEN_CLR_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK)
82334 /*! @} */
82335 
82336 /*! @name TVAL - Timer Value Register */
82337 /*! @{ */
82338 #define LPIT_TVAL_TMR_VAL_MASK                   (0xFFFFFFFFU)
82339 #define LPIT_TVAL_TMR_VAL_SHIFT                  (0U)
82340 /*! TMR_VAL - Timer Value
82341  *  0b00000000000000000000000000000000..Invalid load value in compare mode
82342  *  0b00000000000000000000000000000001..Invalid load value in compare mode
82343  *  0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer
82344  */
82345 #define LPIT_TVAL_TMR_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK)
82346 /*! @} */
82347 
82348 /* The count of LPIT_TVAL */
82349 #define LPIT_TVAL_COUNT                          (4U)
82350 
82351 /*! @name CVAL - Current Timer Value */
82352 /*! @{ */
82353 #define LPIT_CVAL_TMR_CUR_VAL_MASK               (0xFFFFFFFFU)
82354 #define LPIT_CVAL_TMR_CUR_VAL_SHIFT              (0U)
82355 /*! TMR_CUR_VAL - Current Timer Value
82356  */
82357 #define LPIT_CVAL_TMR_CUR_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
82358 /*! @} */
82359 
82360 /* The count of LPIT_CVAL */
82361 #define LPIT_CVAL_COUNT                          (4U)
82362 
82363 /*! @name TCTRL - Timer Control Register */
82364 /*! @{ */
82365 #define LPIT_TCTRL_T_EN_MASK                     (0x1U)
82366 #define LPIT_TCTRL_T_EN_SHIFT                    (0U)
82367 /*! T_EN - Timer Enable
82368  *  0b0..Timer Channel is disabled
82369  *  0b1..Timer Channel is enabled
82370  */
82371 #define LPIT_TCTRL_T_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK)
82372 #define LPIT_TCTRL_CHAIN_MASK                    (0x2U)
82373 #define LPIT_TCTRL_CHAIN_SHIFT                   (1U)
82374 /*! CHAIN - Chain Channel
82375  *  0b0..Channel Chaining is disabled. The channel timer runs independently.
82376  *  0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
82377  */
82378 #define LPIT_TCTRL_CHAIN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK)
82379 #define LPIT_TCTRL_MODE_MASK                     (0xCU)
82380 #define LPIT_TCTRL_MODE_SHIFT                    (2U)
82381 /*! MODE - Timer Operation Mode
82382  *  0b00..32-bit Periodic Counter
82383  *  0b01..Dual 16-bit Periodic Counter
82384  *  0b10..32-bit Trigger Accumulator
82385  *  0b11..32-bit Trigger Input Capture
82386  */
82387 #define LPIT_TCTRL_MODE(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK)
82388 #define LPIT_TCTRL_TSOT_MASK                     (0x10000U)
82389 #define LPIT_TCTRL_TSOT_SHIFT                    (16U)
82390 /*! TSOT - Timer Start On Trigger
82391  *  0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
82392  *  0b1..Timer starts to decrement when a rising edge on a selected trigger is detected
82393  */
82394 #define LPIT_TCTRL_TSOT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK)
82395 #define LPIT_TCTRL_TSOI_MASK                     (0x20000U)
82396 #define LPIT_TCTRL_TSOI_SHIFT                    (17U)
82397 /*! TSOI - Timer Stop On Interrupt
82398  *  0b0..The channel timer does not stop after timeout
82399  *  0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On
82400  *       Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable
82401  *       bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1,
82402  *       the channel timer will restart after a rising edge on the selected trigger is detected.
82403  */
82404 #define LPIT_TCTRL_TSOI(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK)
82405 #define LPIT_TCTRL_TROT_MASK                     (0x40000U)
82406 #define LPIT_TCTRL_TROT_SHIFT                    (18U)
82407 /*! TROT - Timer Reload On Trigger
82408  *  0b0..Timer will not reload on the selected trigger
82409  *  0b1..Timer will reload on the selected trigger
82410  */
82411 #define LPIT_TCTRL_TROT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK)
82412 #define LPIT_TCTRL_TRG_SRC_MASK                  (0x800000U)
82413 #define LPIT_TCTRL_TRG_SRC_SHIFT                 (23U)
82414 /*! TRG_SRC - Trigger Source
82415  *  0b0..Selects external triggers
82416  *  0b1..Selects internal triggers
82417  */
82418 #define LPIT_TCTRL_TRG_SRC(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK)
82419 #define LPIT_TCTRL_TRG_SEL_MASK                  (0xF000000U)
82420 #define LPIT_TCTRL_TRG_SEL_SHIFT                 (24U)
82421 /*! TRG_SEL - Trigger Select
82422  *  0b0000-0b0011..Timer channel 0 - 3 trigger source is selected
82423  *  0b0100-0b1111..Reserved
82424  */
82425 #define LPIT_TCTRL_TRG_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK)
82426 /*! @} */
82427 
82428 /* The count of LPIT_TCTRL */
82429 #define LPIT_TCTRL_COUNT                         (4U)
82430 
82431 
82432 /*!
82433  * @}
82434  */ /* end of group LPIT_Register_Masks */
82435 
82436 
82437 /* LPIT - Peripheral instance base addresses */
82438 /** Peripheral CM4__LPIT base address */
82439 #define CM4__LPIT_BASE                           (0x41210000u)
82440 /** Peripheral CM4__LPIT base pointer */
82441 #define CM4__LPIT                                ((LPIT_Type *)CM4__LPIT_BASE)
82442 /** Peripheral SCU__LPIT base address */
82443 #define SCU__LPIT_BASE                           (0x33210000u)
82444 /** Peripheral SCU__LPIT base pointer */
82445 #define SCU__LPIT                                ((LPIT_Type *)SCU__LPIT_BASE)
82446 /** Array initializer of LPIT peripheral base addresses */
82447 #define LPIT_BASE_ADDRS                          { CM4__LPIT_BASE, SCU__LPIT_BASE }
82448 /** Array initializer of LPIT peripheral base pointers */
82449 #define LPIT_BASE_PTRS                           { CM4__LPIT, SCU__LPIT }
82450 /** Interrupt vectors for the LPIT peripheral type */
82451 #define LPIT_IRQS                                { { M4_LPIT_IRQn, M4_LPIT_IRQn, M4_LPIT_IRQn, M4_LPIT_IRQn }, { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } }
82452 
82453 /*!
82454  * @}
82455  */ /* end of group LPIT_Peripheral_Access_Layer */
82456 
82457 
82458 /* ----------------------------------------------------------------------------
82459    -- LPSPI Peripheral Access Layer
82460    ---------------------------------------------------------------------------- */
82461 
82462 /*!
82463  * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
82464  * @{
82465  */
82466 
82467 /** LPSPI - Register Layout Typedef */
82468 typedef struct {
82469   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
82470   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
82471        uint8_t RESERVED_0[8];
82472   __IO uint32_t CR;                                /**< Control Register, offset: 0x10 */
82473   __IO uint32_t SR;                                /**< Status Register, offset: 0x14 */
82474   __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x18 */
82475   __IO uint32_t DER;                               /**< DMA Enable Register, offset: 0x1C */
82476   __IO uint32_t CFGR0;                             /**< Configuration Register 0, offset: 0x20 */
82477   __IO uint32_t CFGR1;                             /**< Configuration Register 1, offset: 0x24 */
82478        uint8_t RESERVED_1[8];
82479   __IO uint32_t DMR0;                              /**< Data Match Register 0, offset: 0x30 */
82480   __IO uint32_t DMR1;                              /**< Data Match Register 1, offset: 0x34 */
82481        uint8_t RESERVED_2[8];
82482   __IO uint32_t CCR;                               /**< Clock Configuration Register, offset: 0x40 */
82483        uint8_t RESERVED_3[20];
82484   __IO uint32_t FCR;                               /**< FIFO Control Register, offset: 0x58 */
82485   __I  uint32_t FSR;                               /**< FIFO Status Register, offset: 0x5C */
82486   __IO uint32_t TCR;                               /**< Transmit Command Register, offset: 0x60 */
82487   __O  uint32_t TDR;                               /**< Transmit Data Register, offset: 0x64 */
82488        uint8_t RESERVED_4[8];
82489   __I  uint32_t RSR;                               /**< Receive Status Register, offset: 0x70 */
82490   __I  uint32_t RDR;                               /**< Receive Data Register, offset: 0x74 */
82491 } LPSPI_Type;
82492 
82493 /* ----------------------------------------------------------------------------
82494    -- LPSPI Register Masks
82495    ---------------------------------------------------------------------------- */
82496 
82497 /*!
82498  * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
82499  * @{
82500  */
82501 
82502 /*! @name VERID - Version ID Register */
82503 /*! @{ */
82504 #define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
82505 #define LPSPI_VERID_FEATURE_SHIFT                (0U)
82506 /*! FEATURE - Module Identification Number
82507  *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
82508  */
82509 #define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
82510 #define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
82511 #define LPSPI_VERID_MINOR_SHIFT                  (16U)
82512 /*! MINOR - Minor Version Number
82513  */
82514 #define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
82515 #define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
82516 #define LPSPI_VERID_MAJOR_SHIFT                  (24U)
82517 /*! MAJOR - Major Version Number
82518  */
82519 #define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
82520 /*! @} */
82521 
82522 /*! @name PARAM - Parameter Register */
82523 /*! @{ */
82524 #define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
82525 #define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
82526 /*! TXFIFO - Transmit FIFO Size
82527  */
82528 #define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
82529 #define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
82530 #define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
82531 /*! RXFIFO - Receive FIFO Size
82532  */
82533 #define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
82534 /*! @} */
82535 
82536 /*! @name CR - Control Register */
82537 /*! @{ */
82538 #define LPSPI_CR_MEN_MASK                        (0x1U)
82539 #define LPSPI_CR_MEN_SHIFT                       (0U)
82540 /*! MEN - Module Enable
82541  *  0b0..Module is disabled
82542  *  0b1..Module is enabled
82543  */
82544 #define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
82545 #define LPSPI_CR_RST_MASK                        (0x2U)
82546 #define LPSPI_CR_RST_SHIFT                       (1U)
82547 /*! RST - Software Reset
82548  *  0b0..Module is not reset
82549  *  0b1..Module is reset
82550  */
82551 #define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
82552 #define LPSPI_CR_DOZEN_MASK                      (0x4U)
82553 #define LPSPI_CR_DOZEN_SHIFT                     (2U)
82554 /*! DOZEN - Doze Mode Enable
82555  *  0b0..LPSPI module is enabled in Doze mode
82556  *  0b1..LPSPI module is disabled in Doze mode
82557  */
82558 #define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
82559 #define LPSPI_CR_DBGEN_MASK                      (0x8U)
82560 #define LPSPI_CR_DBGEN_SHIFT                     (3U)
82561 /*! DBGEN - Debug Enable
82562  *  0b0..LPSPI module is disabled in debug mode
82563  *  0b1..LPSPI module is enabled in debug mode
82564  */
82565 #define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
82566 #define LPSPI_CR_RTF_MASK                        (0x100U)
82567 #define LPSPI_CR_RTF_SHIFT                       (8U)
82568 /*! RTF - Reset Transmit FIFO
82569  *  0b0..No effect
82570  *  0b1..Transmit FIFO is reset
82571  */
82572 #define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
82573 #define LPSPI_CR_RRF_MASK                        (0x200U)
82574 #define LPSPI_CR_RRF_SHIFT                       (9U)
82575 /*! RRF - Reset Receive FIFO
82576  *  0b0..No effect
82577  *  0b1..Receive FIFO is reset
82578  */
82579 #define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
82580 /*! @} */
82581 
82582 /*! @name SR - Status Register */
82583 /*! @{ */
82584 #define LPSPI_SR_TDF_MASK                        (0x1U)
82585 #define LPSPI_SR_TDF_SHIFT                       (0U)
82586 /*! TDF - Transmit Data Flag
82587  *  0b0..Transmit data not requested
82588  *  0b1..Transmit data is requested
82589  */
82590 #define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
82591 #define LPSPI_SR_RDF_MASK                        (0x2U)
82592 #define LPSPI_SR_RDF_SHIFT                       (1U)
82593 /*! RDF - Receive Data Flag
82594  *  0b0..Receive Data is not ready
82595  *  0b1..Receive data is ready
82596  */
82597 #define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
82598 #define LPSPI_SR_WCF_MASK                        (0x100U)
82599 #define LPSPI_SR_WCF_SHIFT                       (8U)
82600 /*! WCF - Word Complete Flag
82601  *  0b0..Transfer of a received word has not yet completed
82602  *  0b1..Transfer of a received word has completed
82603  */
82604 #define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
82605 #define LPSPI_SR_FCF_MASK                        (0x200U)
82606 #define LPSPI_SR_FCF_SHIFT                       (9U)
82607 /*! FCF - Frame Complete Flag
82608  *  0b0..Frame transfer has not completed
82609  *  0b1..Frame transfer has completed
82610  */
82611 #define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
82612 #define LPSPI_SR_TCF_MASK                        (0x400U)
82613 #define LPSPI_SR_TCF_SHIFT                       (10U)
82614 /*! TCF - Transfer Complete Flag
82615  *  0b0..All transfers have not completed
82616  *  0b1..All transfers have completed
82617  */
82618 #define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
82619 #define LPSPI_SR_TEF_MASK                        (0x800U)
82620 #define LPSPI_SR_TEF_SHIFT                       (11U)
82621 /*! TEF - Transmit Error Flag
82622  *  0b0..Transmit FIFO underrun has not occurred
82623  *  0b1..Transmit FIFO underrun has occurred
82624  */
82625 #define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
82626 #define LPSPI_SR_REF_MASK                        (0x1000U)
82627 #define LPSPI_SR_REF_SHIFT                       (12U)
82628 /*! REF - Receive Error Flag
82629  *  0b0..Receive FIFO has not overflowed
82630  *  0b1..Receive FIFO has overflowed
82631  */
82632 #define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
82633 #define LPSPI_SR_DMF_MASK                        (0x2000U)
82634 #define LPSPI_SR_DMF_SHIFT                       (13U)
82635 /*! DMF - Data Match Flag
82636  *  0b0..Have not received matching data
82637  *  0b1..Have received matching data
82638  */
82639 #define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
82640 #define LPSPI_SR_MBF_MASK                        (0x1000000U)
82641 #define LPSPI_SR_MBF_SHIFT                       (24U)
82642 /*! MBF - Module Busy Flag
82643  *  0b0..LPSPI is idle
82644  *  0b1..LPSPI is busy
82645  */
82646 #define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
82647 /*! @} */
82648 
82649 /*! @name IER - Interrupt Enable Register */
82650 /*! @{ */
82651 #define LPSPI_IER_TDIE_MASK                      (0x1U)
82652 #define LPSPI_IER_TDIE_SHIFT                     (0U)
82653 /*! TDIE - Transmit Data Interrupt Enable
82654  *  0b0..Disabled
82655  *  0b1..Enabled
82656  */
82657 #define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
82658 #define LPSPI_IER_RDIE_MASK                      (0x2U)
82659 #define LPSPI_IER_RDIE_SHIFT                     (1U)
82660 /*! RDIE - Receive Data Interrupt Enable
82661  *  0b0..Disabled
82662  *  0b1..Enabled
82663  */
82664 #define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
82665 #define LPSPI_IER_WCIE_MASK                      (0x100U)
82666 #define LPSPI_IER_WCIE_SHIFT                     (8U)
82667 /*! WCIE - Word Complete Interrupt Enable
82668  *  0b0..Disabled
82669  *  0b1..Enabled
82670  */
82671 #define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
82672 #define LPSPI_IER_FCIE_MASK                      (0x200U)
82673 #define LPSPI_IER_FCIE_SHIFT                     (9U)
82674 /*! FCIE - Frame Complete Interrupt Enable
82675  *  0b0..Disabled
82676  *  0b1..Enabled
82677  */
82678 #define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
82679 #define LPSPI_IER_TCIE_MASK                      (0x400U)
82680 #define LPSPI_IER_TCIE_SHIFT                     (10U)
82681 /*! TCIE - Transfer Complete Interrupt Enable
82682  *  0b0..Disabled
82683  *  0b1..Enabled
82684  */
82685 #define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
82686 #define LPSPI_IER_TEIE_MASK                      (0x800U)
82687 #define LPSPI_IER_TEIE_SHIFT                     (11U)
82688 /*! TEIE - Transmit Error Interrupt Enable
82689  *  0b0..Disabled
82690  *  0b1..Enabled
82691  */
82692 #define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
82693 #define LPSPI_IER_REIE_MASK                      (0x1000U)
82694 #define LPSPI_IER_REIE_SHIFT                     (12U)
82695 /*! REIE - Receive Error Interrupt Enable
82696  *  0b0..Disabled
82697  *  0b1..Enabled
82698  */
82699 #define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
82700 #define LPSPI_IER_DMIE_MASK                      (0x2000U)
82701 #define LPSPI_IER_DMIE_SHIFT                     (13U)
82702 /*! DMIE - Data Match Interrupt Enable
82703  *  0b0..Disabled
82704  *  0b1..Enabled
82705  */
82706 #define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
82707 /*! @} */
82708 
82709 /*! @name DER - DMA Enable Register */
82710 /*! @{ */
82711 #define LPSPI_DER_TDDE_MASK                      (0x1U)
82712 #define LPSPI_DER_TDDE_SHIFT                     (0U)
82713 /*! TDDE - Transmit Data DMA Enable
82714  *  0b0..DMA request is disabled
82715  *  0b1..DMA request is enabled
82716  */
82717 #define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
82718 #define LPSPI_DER_RDDE_MASK                      (0x2U)
82719 #define LPSPI_DER_RDDE_SHIFT                     (1U)
82720 /*! RDDE - Receive Data DMA Enable
82721  *  0b0..DMA request is disabled
82722  *  0b1..DMA request is enabled
82723  */
82724 #define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
82725 #define LPSPI_DER_FCDE_MASK                      (0x200U)
82726 #define LPSPI_DER_FCDE_SHIFT                     (9U)
82727 /*! FCDE - Frame Complete DMA Enable
82728  *  0b0..DMA request is disabled
82729  *  0b1..DMA request is enabled
82730  */
82731 #define LPSPI_DER_FCDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK)
82732 /*! @} */
82733 
82734 /*! @name CFGR0 - Configuration Register 0 */
82735 /*! @{ */
82736 #define LPSPI_CFGR0_HREN_MASK                    (0x1U)
82737 #define LPSPI_CFGR0_HREN_SHIFT                   (0U)
82738 /*! HREN - Host Request Enable
82739  *  0b0..Host request is disabled
82740  *  0b1..Host request is enabled
82741  */
82742 #define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
82743 #define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
82744 #define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
82745 /*! HRPOL - Host Request Polarity
82746  *  0b0..Active low
82747  *  0b1..Active high
82748  */
82749 #define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
82750 #define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
82751 #define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
82752 /*! HRSEL - Host Request Select
82753  *  0b0..Host request input is the LPSPI_HREQ pin
82754  *  0b1..Host request input is the input trigger
82755  */
82756 #define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
82757 #define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
82758 #define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
82759 /*! CIRFIFO - Circular FIFO Enable
82760  *  0b0..Circular FIFO is disabled
82761  *  0b1..Circular FIFO is enabled
82762  */
82763 #define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
82764 #define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
82765 #define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
82766 /*! RDMO - Receive Data Match Only
82767  *  0b0..Received data is stored in the receive FIFO as in normal operations
82768  *  0b1..Received data is discarded unless the Data Match Flag (DMF) is set
82769  */
82770 #define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
82771 /*! @} */
82772 
82773 /*! @name CFGR1 - Configuration Register 1 */
82774 /*! @{ */
82775 #define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
82776 #define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
82777 /*! MASTER - Master Mode
82778  *  0b0..Slave mode
82779  *  0b1..Master mode
82780  */
82781 #define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
82782 #define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
82783 #define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
82784 /*! SAMPLE - Sample Point
82785  *  0b0..Input data is sampled on SCK edge
82786  *  0b1..Input data is sampled on delayed SCK edge
82787  */
82788 #define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
82789 #define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
82790 #define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
82791 /*! AUTOPCS - Automatic PCS
82792  *  0b0..Automatic PCS generation is disabled
82793  *  0b1..Automatic PCS generation is enabled
82794  */
82795 #define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
82796 #define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
82797 #define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
82798 /*! NOSTALL - No Stall
82799  *  0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
82800  *  0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
82801  */
82802 #define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
82803 #define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
82804 #define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
82805 /*! PCSPOL - Peripheral Chip Select Polarity
82806  */
82807 #define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
82808 #define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
82809 #define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
82810 /*! MATCFG - Match Configuration
82811  *  0b000..Match is disabled
82812  *  0b001..Reserved
82813  *  0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
82814  *  0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
82815  *  0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st
82816  *         data word = MATCH0) * (2nd data word = MATCH1)]
82817  *  0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e.,
82818  *         [(any data word = MATCH0) * (next data word = MATCH1)]
82819  *  0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
82820  *  0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
82821  */
82822 #define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
82823 #define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
82824 #define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
82825 /*! PINCFG - Pin Configuration
82826  *  0b00..SIN is used for input data and SOUT is used for output data
82827  *  0b01..SIN is used for both input and output data
82828  *  0b10..SOUT is used for both input and output data
82829  *  0b11..SOUT is used for input data and SIN is used for output data
82830  */
82831 #define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
82832 #define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
82833 #define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
82834 /*! OUTCFG - Output Configuration
82835  *  0b0..Output data retains last value when chip select is negated
82836  *  0b1..Output data is tristated when chip select is negated
82837  */
82838 #define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
82839 #define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
82840 #define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
82841 /*! PCSCFG - Peripheral Chip Select Configuration
82842  *  0b0..PCS[3:2] are enabled
82843  *  0b1..PCS[3:2] are disabled
82844  */
82845 #define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
82846 /*! @} */
82847 
82848 /*! @name DMR0 - Data Match Register 0 */
82849 /*! @{ */
82850 #define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
82851 #define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
82852 /*! MATCH0 - Match 0 Value
82853  */
82854 #define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
82855 /*! @} */
82856 
82857 /*! @name DMR1 - Data Match Register 1 */
82858 /*! @{ */
82859 #define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
82860 #define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
82861 /*! MATCH1 - Match 1 Value
82862  */
82863 #define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
82864 /*! @} */
82865 
82866 /*! @name CCR - Clock Configuration Register */
82867 /*! @{ */
82868 #define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
82869 #define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
82870 /*! SCKDIV - SCK Divider
82871  */
82872 #define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
82873 #define LPSPI_CCR_DBT_MASK                       (0xFF00U)
82874 #define LPSPI_CCR_DBT_SHIFT                      (8U)
82875 /*! DBT - Delay Between Transfers
82876  */
82877 #define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
82878 #define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
82879 #define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
82880 /*! PCSSCK - PCS-to-SCK Delay
82881  */
82882 #define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
82883 #define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
82884 #define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
82885 /*! SCKPCS - SCK-to-PCS Delay
82886  */
82887 #define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
82888 /*! @} */
82889 
82890 /*! @name FCR - FIFO Control Register */
82891 /*! @{ */
82892 #define LPSPI_FCR_TXWATER_MASK                   (0x3FU)
82893 #define LPSPI_FCR_TXWATER_SHIFT                  (0U)
82894 /*! TXWATER - Transmit FIFO Watermark
82895  */
82896 #define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
82897 #define LPSPI_FCR_RXWATER_MASK                   (0x3F0000U)
82898 #define LPSPI_FCR_RXWATER_SHIFT                  (16U)
82899 /*! RXWATER - Receive FIFO Watermark
82900  */
82901 #define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
82902 /*! @} */
82903 
82904 /*! @name FSR - FIFO Status Register */
82905 /*! @{ */
82906 #define LPSPI_FSR_TXCOUNT_MASK                   (0x7FU)
82907 #define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
82908 /*! TXCOUNT - Transmit FIFO Count
82909  */
82910 #define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
82911 #define LPSPI_FSR_RXCOUNT_MASK                   (0x7F0000U)
82912 #define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
82913 /*! RXCOUNT - Receive FIFO Count
82914  */
82915 #define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
82916 /*! @} */
82917 
82918 /*! @name TCR - Transmit Command Register */
82919 /*! @{ */
82920 #define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
82921 #define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
82922 /*! FRAMESZ - Frame Size
82923  */
82924 #define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
82925 #define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
82926 #define LPSPI_TCR_WIDTH_SHIFT                    (16U)
82927 /*! WIDTH - Transfer Width
82928  *  0b00..1 bit transfer
82929  *  0b01..2 bit transfer
82930  *  0b10..4 bit transfer
82931  *  0b11..Reserved
82932  */
82933 #define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
82934 #define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
82935 #define LPSPI_TCR_TXMSK_SHIFT                    (18U)
82936 /*! TXMSK - Transmit Data Mask
82937  *  0b0..Normal transfer
82938  *  0b1..Mask transmit data
82939  */
82940 #define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
82941 #define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
82942 #define LPSPI_TCR_RXMSK_SHIFT                    (19U)
82943 /*! RXMSK - Receive Data Mask
82944  *  0b0..Normal transfer
82945  *  0b1..Receive data is masked
82946  */
82947 #define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
82948 #define LPSPI_TCR_CONTC_MASK                     (0x100000U)
82949 #define LPSPI_TCR_CONTC_SHIFT                    (20U)
82950 /*! CONTC - Continuing Command
82951  *  0b0..Command word for start of new transfer
82952  *  0b1..Command word for continuing transfer
82953  */
82954 #define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
82955 #define LPSPI_TCR_CONT_MASK                      (0x200000U)
82956 #define LPSPI_TCR_CONT_SHIFT                     (21U)
82957 /*! CONT - Continuous Transfer
82958  *  0b0..Continuous transfer is disabled
82959  *  0b1..Continuous transfer is enabled
82960  */
82961 #define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
82962 #define LPSPI_TCR_BYSW_MASK                      (0x400000U)
82963 #define LPSPI_TCR_BYSW_SHIFT                     (22U)
82964 /*! BYSW - Byte Swap
82965  *  0b0..Byte swap is disabled
82966  *  0b1..Byte swap is enabled
82967  */
82968 #define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
82969 #define LPSPI_TCR_LSBF_MASK                      (0x800000U)
82970 #define LPSPI_TCR_LSBF_SHIFT                     (23U)
82971 /*! LSBF - LSB First
82972  *  0b0..Data is transferred MSB first
82973  *  0b1..Data is transferred LSB first
82974  */
82975 #define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
82976 #define LPSPI_TCR_PCS_MASK                       (0x3000000U)
82977 #define LPSPI_TCR_PCS_SHIFT                      (24U)
82978 /*! PCS - Peripheral Chip Select
82979  *  0b00..Transfer using LPSPI_PCS[0]
82980  *  0b01..Transfer using LPSPI_PCS[1]
82981  *  0b10..Transfer using LPSPI_PCS[2]
82982  *  0b11..Transfer using LPSPI_PCS[3]
82983  */
82984 #define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
82985 #define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
82986 #define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
82987 /*! PRESCALE - Prescaler Value
82988  *  0b000..Divide by 1
82989  *  0b001..Divide by 2
82990  *  0b010..Divide by 4
82991  *  0b011..Divide by 8
82992  *  0b100..Divide by 16
82993  *  0b101..Divide by 32
82994  *  0b110..Divide by 64
82995  *  0b111..Divide by 128
82996  */
82997 #define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
82998 #define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
82999 #define LPSPI_TCR_CPHA_SHIFT                     (30U)
83000 /*! CPHA - Clock Phase
83001  *  0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK
83002  *  0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK
83003  */
83004 #define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
83005 #define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
83006 #define LPSPI_TCR_CPOL_SHIFT                     (31U)
83007 /*! CPOL - Clock Polarity
83008  *  0b0..The inactive state value of SCK is low
83009  *  0b1..The inactive state value of SCK is high
83010  */
83011 #define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
83012 /*! @} */
83013 
83014 /*! @name TDR - Transmit Data Register */
83015 /*! @{ */
83016 #define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
83017 #define LPSPI_TDR_DATA_SHIFT                     (0U)
83018 /*! DATA - Transmit Data
83019  */
83020 #define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
83021 /*! @} */
83022 
83023 /*! @name RSR - Receive Status Register */
83024 /*! @{ */
83025 #define LPSPI_RSR_SOF_MASK                       (0x1U)
83026 #define LPSPI_RSR_SOF_SHIFT                      (0U)
83027 /*! SOF - Start Of Frame
83028  *  0b0..Subsequent data word received after LPSPI_PCS assertion
83029  *  0b1..First data word received after LPSPI_PCS assertion
83030  */
83031 #define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
83032 #define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
83033 #define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
83034 /*! RXEMPTY - RX FIFO Empty
83035  *  0b0..RX FIFO is not empty
83036  *  0b1..RX FIFO is empty
83037  */
83038 #define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
83039 /*! @} */
83040 
83041 /*! @name RDR - Receive Data Register */
83042 /*! @{ */
83043 #define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
83044 #define LPSPI_RDR_DATA_SHIFT                     (0U)
83045 /*! DATA - Receive Data
83046  */
83047 #define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
83048 /*! @} */
83049 
83050 
83051 /*!
83052  * @}
83053  */ /* end of group LPSPI_Register_Masks */
83054 
83055 
83056 /* LPSPI - Peripheral instance base addresses */
83057 /** Peripheral ADMA__LPSPI0 base address */
83058 #define ADMA__LPSPI0_BASE                        (0x5A000000u)
83059 /** Peripheral ADMA__LPSPI0 base pointer */
83060 #define ADMA__LPSPI0                             ((LPSPI_Type *)ADMA__LPSPI0_BASE)
83061 /** Peripheral ADMA__LPSPI1 base address */
83062 #define ADMA__LPSPI1_BASE                        (0x5A010000u)
83063 /** Peripheral ADMA__LPSPI1 base pointer */
83064 #define ADMA__LPSPI1                             ((LPSPI_Type *)ADMA__LPSPI1_BASE)
83065 /** Peripheral ADMA__LPSPI2 base address */
83066 #define ADMA__LPSPI2_BASE                        (0x5A020000u)
83067 /** Peripheral ADMA__LPSPI2 base pointer */
83068 #define ADMA__LPSPI2                             ((LPSPI_Type *)ADMA__LPSPI2_BASE)
83069 /** Peripheral ADMA__LPSPI3 base address */
83070 #define ADMA__LPSPI3_BASE                        (0x5A030000u)
83071 /** Peripheral ADMA__LPSPI3 base pointer */
83072 #define ADMA__LPSPI3                             ((LPSPI_Type *)ADMA__LPSPI3_BASE)
83073 /** Array initializer of LPSPI peripheral base addresses */
83074 #define LPSPI_BASE_ADDRS                         { ADMA__LPSPI0_BASE, ADMA__LPSPI1_BASE, ADMA__LPSPI2_BASE, ADMA__LPSPI3_BASE }
83075 /** Array initializer of LPSPI peripheral base pointers */
83076 #define LPSPI_BASE_PTRS                          { ADMA__LPSPI0, ADMA__LPSPI1, ADMA__LPSPI2, ADMA__LPSPI3 }
83077 /** Interrupt vectors for the LPSPI peripheral type */
83078 #define LPSPI_IRQS                               { ADMA_SPI0_INT_IRQn, ADMA_SPI1_INT_IRQn, ADMA_SPI2_INT_IRQn, ADMA_SPI3_INT_IRQn }
83079 
83080 /*!
83081  * @}
83082  */ /* end of group LPSPI_Peripheral_Access_Layer */
83083 
83084 
83085 /* ----------------------------------------------------------------------------
83086    -- LPUART Peripheral Access Layer
83087    ---------------------------------------------------------------------------- */
83088 
83089 /*!
83090  * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
83091  * @{
83092  */
83093 
83094 /** LPUART - Register Layout Typedef */
83095 typedef struct {
83096   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
83097   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
83098   __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
83099   __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
83100   __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
83101   __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
83102   __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
83103   __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
83104   __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
83105   __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
83106   __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
83107   __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
83108 } LPUART_Type;
83109 
83110 /* ----------------------------------------------------------------------------
83111    -- LPUART Register Masks
83112    ---------------------------------------------------------------------------- */
83113 
83114 /*!
83115  * @addtogroup LPUART_Register_Masks LPUART Register Masks
83116  * @{
83117  */
83118 
83119 /*! @name VERID - Version ID Register */
83120 /*! @{ */
83121 #define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
83122 #define LPUART_VERID_FEATURE_SHIFT               (0U)
83123 /*! FEATURE - Feature Identification Number
83124  *  0b0000000000000001..Standard feature set.
83125  *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
83126  */
83127 #define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
83128 #define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
83129 #define LPUART_VERID_MINOR_SHIFT                 (16U)
83130 /*! MINOR - Minor Version Number
83131  */
83132 #define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
83133 #define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
83134 #define LPUART_VERID_MAJOR_SHIFT                 (24U)
83135 /*! MAJOR - Major Version Number
83136  */
83137 #define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
83138 /*! @} */
83139 
83140 /*! @name PARAM - Parameter Register */
83141 /*! @{ */
83142 #define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
83143 #define LPUART_PARAM_TXFIFO_SHIFT                (0U)
83144 /*! TXFIFO - Transmit FIFO Size
83145  */
83146 #define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
83147 #define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
83148 #define LPUART_PARAM_RXFIFO_SHIFT                (8U)
83149 /*! RXFIFO - Receive FIFO Size
83150  */
83151 #define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
83152 /*! @} */
83153 
83154 /*! @name GLOBAL - LPUART Global Register */
83155 /*! @{ */
83156 #define LPUART_GLOBAL_RST_MASK                   (0x2U)
83157 #define LPUART_GLOBAL_RST_SHIFT                  (1U)
83158 /*! RST - Software Reset
83159  *  0b0..Module is not reset.
83160  *  0b1..Module is reset.
83161  */
83162 #define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
83163 /*! @} */
83164 
83165 /*! @name PINCFG - LPUART Pin Configuration Register */
83166 /*! @{ */
83167 #define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
83168 #define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
83169 /*! TRGSEL - Trigger Select
83170  *  0b00..Input trigger is disabled.
83171  *  0b01..Input trigger is used instead of RX pin input.
83172  *  0b10..Input trigger is used instead of CTS_B pin input.
83173  *  0b11..Input trigger is used to modulate the TX pin output. The TX pin output (after TXINV configuration) is ANDed with the input trigger.
83174  */
83175 #define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
83176 /*! @} */
83177 
83178 /*! @name BAUD - LPUART Baud Rate Register */
83179 /*! @{ */
83180 #define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
83181 #define LPUART_BAUD_SBR_SHIFT                    (0U)
83182 /*! SBR - Baud Rate Modulo Divisor.
83183  */
83184 #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
83185 #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
83186 #define LPUART_BAUD_SBNS_SHIFT                   (13U)
83187 /*! SBNS - Stop Bit Number Select
83188  *  0b0..One stop bit.
83189  *  0b1..Two stop bits.
83190  */
83191 #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
83192 #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
83193 #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
83194 /*! RXEDGIE - RX Input Active Edge Interrupt Enable
83195  *  0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
83196  *  0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
83197  */
83198 #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
83199 #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
83200 #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
83201 /*! LBKDIE - LIN Break Detect Interrupt Enable
83202  *  0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
83203  *  0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1.
83204  */
83205 #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
83206 #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
83207 #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
83208 /*! RESYNCDIS - Resynchronization Disable
83209  *  0b0..Resynchronization during received data word is supported
83210  *  0b1..Resynchronization during received data word is disabled
83211  */
83212 #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
83213 #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
83214 #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
83215 /*! BOTHEDGE - Both Edge Sampling
83216  *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
83217  *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
83218  */
83219 #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
83220 #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
83221 #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
83222 /*! MATCFG - Match Configuration
83223  *  0b00..Address Match Wakeup
83224  *  0b01..Idle Match Wakeup
83225  *  0b10..Match On and Match Off
83226  *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
83227  */
83228 #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
83229 #define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
83230 #define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
83231 /*! RIDMAE - Receiver Idle DMA Enable
83232  *  0b0..DMA request disabled.
83233  *  0b1..DMA request enabled.
83234  */
83235 #define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
83236 #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
83237 #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
83238 /*! RDMAE - Receiver Full DMA Enable
83239  *  0b0..DMA request disabled.
83240  *  0b1..DMA request enabled.
83241  */
83242 #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
83243 #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
83244 #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
83245 /*! TDMAE - Transmitter DMA Enable
83246  *  0b0..DMA request disabled.
83247  *  0b1..DMA request enabled.
83248  */
83249 #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
83250 #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
83251 #define LPUART_BAUD_OSR_SHIFT                    (24U)
83252 /*! OSR - Oversampling Ratio
83253  *  0b00000..Writing 0 to this field will result in an oversampling ratio of 16
83254  *  0b00001..Reserved
83255  *  0b00010..Reserved
83256  *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
83257  *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
83258  *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
83259  *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
83260  *  0b00111..Oversampling ratio of 8.
83261  *  0b01000..Oversampling ratio of 9.
83262  *  0b01001..Oversampling ratio of 10.
83263  *  0b01010..Oversampling ratio of 11.
83264  *  0b01011..Oversampling ratio of 12.
83265  *  0b01100..Oversampling ratio of 13.
83266  *  0b01101..Oversampling ratio of 14.
83267  *  0b01110..Oversampling ratio of 15.
83268  *  0b01111..Oversampling ratio of 16.
83269  *  0b10000..Oversampling ratio of 17.
83270  *  0b10001..Oversampling ratio of 18.
83271  *  0b10010..Oversampling ratio of 19.
83272  *  0b10011..Oversampling ratio of 20.
83273  *  0b10100..Oversampling ratio of 21.
83274  *  0b10101..Oversampling ratio of 22.
83275  *  0b10110..Oversampling ratio of 23.
83276  *  0b10111..Oversampling ratio of 24.
83277  *  0b11000..Oversampling ratio of 25.
83278  *  0b11001..Oversampling ratio of 26.
83279  *  0b11010..Oversampling ratio of 27.
83280  *  0b11011..Oversampling ratio of 28.
83281  *  0b11100..Oversampling ratio of 29.
83282  *  0b11101..Oversampling ratio of 30.
83283  *  0b11110..Oversampling ratio of 31.
83284  *  0b11111..Oversampling ratio of 32.
83285  */
83286 #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
83287 #define LPUART_BAUD_M10_MASK                     (0x20000000U)
83288 #define LPUART_BAUD_M10_SHIFT                    (29U)
83289 /*! M10 - 10-bit Mode select
83290  *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
83291  *  0b1..Receiver and transmitter use 10-bit data characters.
83292  */
83293 #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
83294 #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
83295 #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
83296 /*! MAEN2 - Match Address Mode Enable 2
83297  *  0b0..Normal operation.
83298  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
83299  */
83300 #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
83301 #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
83302 #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
83303 /*! MAEN1 - Match Address Mode Enable 1
83304  *  0b0..Normal operation.
83305  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
83306  */
83307 #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
83308 /*! @} */
83309 
83310 /*! @name STAT - LPUART Status Register */
83311 /*! @{ */
83312 #define LPUART_STAT_MA2F_MASK                    (0x4000U)
83313 #define LPUART_STAT_MA2F_SHIFT                   (14U)
83314 /*! MA2F - Match 2 Flag
83315  *  0b0..Received data is not equal to MA2
83316  *  0b1..Received data is equal to MA2
83317  */
83318 #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
83319 #define LPUART_STAT_MA1F_MASK                    (0x8000U)
83320 #define LPUART_STAT_MA1F_SHIFT                   (15U)
83321 /*! MA1F - Match 1 Flag
83322  *  0b0..Received data is not equal to MA1
83323  *  0b1..Received data is equal to MA1
83324  */
83325 #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
83326 #define LPUART_STAT_PF_MASK                      (0x10000U)
83327 #define LPUART_STAT_PF_SHIFT                     (16U)
83328 /*! PF - Parity Error Flag
83329  *  0b0..No parity error.
83330  *  0b1..Parity error.
83331  */
83332 #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
83333 #define LPUART_STAT_FE_MASK                      (0x20000U)
83334 #define LPUART_STAT_FE_SHIFT                     (17U)
83335 /*! FE - Framing Error Flag
83336  *  0b0..No framing error detected. This does not guarantee the framing is correct.
83337  *  0b1..Framing error.
83338  */
83339 #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
83340 #define LPUART_STAT_NF_MASK                      (0x40000U)
83341 #define LPUART_STAT_NF_SHIFT                     (18U)
83342 /*! NF - Noise Flag
83343  *  0b0..No noise detected.
83344  *  0b1..Noise detected in the received character in the DATA register.
83345  */
83346 #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
83347 #define LPUART_STAT_OR_MASK                      (0x80000U)
83348 #define LPUART_STAT_OR_SHIFT                     (19U)
83349 /*! OR - Receiver Overrun Flag
83350  *  0b0..No overrun.
83351  *  0b1..Receive overrun (new LPUART data lost).
83352  */
83353 #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
83354 #define LPUART_STAT_IDLE_MASK                    (0x100000U)
83355 #define LPUART_STAT_IDLE_SHIFT                   (20U)
83356 /*! IDLE - Idle Line Flag
83357  *  0b0..No idle line detected.
83358  *  0b1..Idle line was detected.
83359  */
83360 #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
83361 #define LPUART_STAT_RDRF_MASK                    (0x200000U)
83362 #define LPUART_STAT_RDRF_SHIFT                   (21U)
83363 /*! RDRF - Receive Data Register Full Flag
83364  *  0b0..Receive data buffer empty.
83365  *  0b1..Receive data buffer full.
83366  */
83367 #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
83368 #define LPUART_STAT_TC_MASK                      (0x400000U)
83369 #define LPUART_STAT_TC_SHIFT                     (22U)
83370 /*! TC - Transmission Complete Flag
83371  *  0b0..Transmitter active (sending data, a preamble, or a break).
83372  *  0b1..Transmitter idle (transmission activity complete).
83373  */
83374 #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
83375 #define LPUART_STAT_TDRE_MASK                    (0x800000U)
83376 #define LPUART_STAT_TDRE_SHIFT                   (23U)
83377 /*! TDRE - Transmit Data Register Empty Flag
83378  *  0b0..Transmit data buffer full.
83379  *  0b1..Transmit data buffer empty.
83380  */
83381 #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
83382 #define LPUART_STAT_RAF_MASK                     (0x1000000U)
83383 #define LPUART_STAT_RAF_SHIFT                    (24U)
83384 /*! RAF - Receiver Active Flag
83385  *  0b0..LPUART receiver idle waiting for a start bit.
83386  *  0b1..LPUART receiver active (RX input not idle).
83387  */
83388 #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
83389 #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
83390 #define LPUART_STAT_LBKDE_SHIFT                  (25U)
83391 /*! LBKDE - LIN Break Detection Enable
83392  *  0b0..LIN break detect is disabled, normal break character can be detected.
83393  *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
83394  */
83395 #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
83396 #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
83397 #define LPUART_STAT_BRK13_SHIFT                  (26U)
83398 /*! BRK13 - Break Character Generation Length
83399  *  0b0..Break character is transmitted with length of 9 to 13 bit times.
83400  *  0b1..Break character is transmitted with length of 12 to 15 bit times.
83401  */
83402 #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
83403 #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
83404 #define LPUART_STAT_RWUID_SHIFT                  (27U)
83405 /*! RWUID - Receive Wake Up Idle Detect
83406  *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
83407  *       character. During address match wakeup, the IDLE bit does not set when an address does not match.
83408  *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
83409  *       address match wakeup, the IDLE bit does set when an address does not match.
83410  */
83411 #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
83412 #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
83413 #define LPUART_STAT_RXINV_SHIFT                  (28U)
83414 /*! RXINV - Receive Data Inversion
83415  *  0b0..Receive data not inverted.
83416  *  0b1..Receive data inverted.
83417  */
83418 #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
83419 #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
83420 #define LPUART_STAT_MSBF_SHIFT                   (29U)
83421 /*! MSBF - MSB First
83422  *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
83423  *       after the start bit is identified as bit0.
83424  *  0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on
83425  *       the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is
83426  *       identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
83427  */
83428 #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
83429 #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
83430 #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
83431 /*! RXEDGIF - RX Pin Active Edge Interrupt Flag
83432  *  0b0..No active edge on the receive pin has occurred.
83433  *  0b1..An active edge on the receive pin has occurred.
83434  */
83435 #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
83436 #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
83437 #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
83438 /*! LBKDIF - LIN Break Detect Interrupt Flag
83439  *  0b0..No LIN break character has been detected.
83440  *  0b1..LIN break character has been detected.
83441  */
83442 #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
83443 /*! @} */
83444 
83445 /*! @name CTRL - LPUART Control Register */
83446 /*! @{ */
83447 #define LPUART_CTRL_PT_MASK                      (0x1U)
83448 #define LPUART_CTRL_PT_SHIFT                     (0U)
83449 /*! PT - Parity Type
83450  *  0b0..Even parity.
83451  *  0b1..Odd parity.
83452  */
83453 #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
83454 #define LPUART_CTRL_PE_MASK                      (0x2U)
83455 #define LPUART_CTRL_PE_SHIFT                     (1U)
83456 /*! PE - Parity Enable
83457  *  0b0..No hardware parity generation or checking.
83458  *  0b1..Parity enabled.
83459  */
83460 #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
83461 #define LPUART_CTRL_ILT_MASK                     (0x4U)
83462 #define LPUART_CTRL_ILT_SHIFT                    (2U)
83463 /*! ILT - Idle Line Type Select
83464  *  0b0..Idle character bit count starts after start bit.
83465  *  0b1..Idle character bit count starts after stop bit.
83466  */
83467 #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
83468 #define LPUART_CTRL_WAKE_MASK                    (0x8U)
83469 #define LPUART_CTRL_WAKE_SHIFT                   (3U)
83470 /*! WAKE - Receiver Wakeup Method Select
83471  *  0b0..Configures RWU for idle-line wakeup.
83472  *  0b1..Configures RWU with address-mark wakeup.
83473  */
83474 #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
83475 #define LPUART_CTRL_M_MASK                       (0x10U)
83476 #define LPUART_CTRL_M_SHIFT                      (4U)
83477 /*! M - 9-Bit or 8-Bit Mode Select
83478  *  0b0..Receiver and transmitter use 8-bit data characters.
83479  *  0b1..Receiver and transmitter use 9-bit data characters.
83480  */
83481 #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
83482 #define LPUART_CTRL_RSRC_MASK                    (0x20U)
83483 #define LPUART_CTRL_RSRC_SHIFT                   (5U)
83484 /*! RSRC - Receiver Source Select
83485  *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RX pin.
83486  *  0b1..Single-wire LPUART mode where the TX pin is connected to the transmitter output and receiver input.
83487  */
83488 #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
83489 #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
83490 #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
83491 /*! DOZEEN - Doze Enable
83492  *  0b0..LPUART is enabled in Doze mode.
83493  *  0b1..LPUART is disabled in Doze mode.
83494  */
83495 #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
83496 #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
83497 #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
83498 /*! LOOPS - Loop Mode Select
83499  *  0b0..Normal operation - RX and TX use separate pins.
83500  *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
83501  */
83502 #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
83503 #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
83504 #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
83505 /*! IDLECFG - Idle Configuration
83506  *  0b000..1 idle character
83507  *  0b001..2 idle characters
83508  *  0b010..4 idle characters
83509  *  0b011..8 idle characters
83510  *  0b100..16 idle characters
83511  *  0b101..32 idle characters
83512  *  0b110..64 idle characters
83513  *  0b111..128 idle characters
83514  */
83515 #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
83516 #define LPUART_CTRL_M7_MASK                      (0x800U)
83517 #define LPUART_CTRL_M7_SHIFT                     (11U)
83518 /*! M7 - 7-Bit Mode Select
83519  *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
83520  *  0b1..Receiver and transmitter use 7-bit data characters.
83521  */
83522 #define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
83523 #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
83524 #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
83525 /*! MA2IE - Match 2 Interrupt Enable
83526  *  0b0..MA2F interrupt disabled
83527  *  0b1..MA2F interrupt enabled
83528  */
83529 #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
83530 #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
83531 #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
83532 /*! MA1IE - Match 1 Interrupt Enable
83533  *  0b0..MA1F interrupt disabled
83534  *  0b1..MA1F interrupt enabled
83535  */
83536 #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
83537 #define LPUART_CTRL_SBK_MASK                     (0x10000U)
83538 #define LPUART_CTRL_SBK_SHIFT                    (16U)
83539 /*! SBK - Send Break
83540  *  0b0..Normal transmitter operation.
83541  *  0b1..Queue break character(s) to be sent.
83542  */
83543 #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
83544 #define LPUART_CTRL_RWU_MASK                     (0x20000U)
83545 #define LPUART_CTRL_RWU_SHIFT                    (17U)
83546 /*! RWU - Receiver Wakeup Control
83547  *  0b0..Normal receiver operation.
83548  *  0b1..LPUART receiver in standby waiting for wakeup condition.
83549  */
83550 #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
83551 #define LPUART_CTRL_RE_MASK                      (0x40000U)
83552 #define LPUART_CTRL_RE_SHIFT                     (18U)
83553 /*! RE - Receiver Enable
83554  *  0b0..Receiver disabled.
83555  *  0b1..Receiver enabled.
83556  */
83557 #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
83558 #define LPUART_CTRL_TE_MASK                      (0x80000U)
83559 #define LPUART_CTRL_TE_SHIFT                     (19U)
83560 /*! TE - Transmitter Enable
83561  *  0b0..Transmitter disabled.
83562  *  0b1..Transmitter enabled.
83563  */
83564 #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
83565 #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
83566 #define LPUART_CTRL_ILIE_SHIFT                   (20U)
83567 /*! ILIE - Idle Line Interrupt Enable
83568  *  0b0..Hardware interrupts from IDLE disabled; use polling.
83569  *  0b1..Hardware interrupt requested when IDLE flag is 1.
83570  */
83571 #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
83572 #define LPUART_CTRL_RIE_MASK                     (0x200000U)
83573 #define LPUART_CTRL_RIE_SHIFT                    (21U)
83574 /*! RIE - Receiver Interrupt Enable
83575  *  0b0..Hardware interrupts from RDRF disabled; use polling.
83576  *  0b1..Hardware interrupt requested when RDRF flag is 1.
83577  */
83578 #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
83579 #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
83580 #define LPUART_CTRL_TCIE_SHIFT                   (22U)
83581 /*! TCIE - Transmission Complete Interrupt Enable for
83582  *  0b0..Hardware interrupts from TC disabled; use polling.
83583  *  0b1..Hardware interrupt requested when TC flag is 1.
83584  */
83585 #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
83586 #define LPUART_CTRL_TIE_MASK                     (0x800000U)
83587 #define LPUART_CTRL_TIE_SHIFT                    (23U)
83588 /*! TIE - Transmit Interrupt Enable
83589  *  0b0..Hardware interrupts from TDRE disabled; use polling.
83590  *  0b1..Hardware interrupt requested when TDRE flag is 1.
83591  */
83592 #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
83593 #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
83594 #define LPUART_CTRL_PEIE_SHIFT                   (24U)
83595 /*! PEIE - Parity Error Interrupt Enable
83596  *  0b0..PF interrupts disabled; use polling).
83597  *  0b1..Hardware interrupt requested when PF is set.
83598  */
83599 #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
83600 #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
83601 #define LPUART_CTRL_FEIE_SHIFT                   (25U)
83602 /*! FEIE - Framing Error Interrupt Enable
83603  *  0b0..FE interrupts disabled; use polling.
83604  *  0b1..Hardware interrupt requested when FE is set.
83605  */
83606 #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
83607 #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
83608 #define LPUART_CTRL_NEIE_SHIFT                   (26U)
83609 /*! NEIE - Noise Error Interrupt Enable
83610  *  0b0..NF interrupts disabled; use polling.
83611  *  0b1..Hardware interrupt requested when NF is set.
83612  */
83613 #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
83614 #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
83615 #define LPUART_CTRL_ORIE_SHIFT                   (27U)
83616 /*! ORIE - Overrun Interrupt Enable
83617  *  0b0..OR interrupts disabled; use polling.
83618  *  0b1..Hardware interrupt requested when OR is set.
83619  */
83620 #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
83621 #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
83622 #define LPUART_CTRL_TXINV_SHIFT                  (28U)
83623 /*! TXINV - Transmit Data Inversion
83624  *  0b0..Transmit data not inverted.
83625  *  0b1..Transmit data inverted.
83626  */
83627 #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
83628 #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
83629 #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
83630 /*! TXDIR - TX Pin Direction in Single-Wire Mode
83631  *  0b0..TX pin is an input in single-wire mode.
83632  *  0b1..TX pin is an output in single-wire mode.
83633  */
83634 #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
83635 #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
83636 #define LPUART_CTRL_R9T8_SHIFT                   (30U)
83637 /*! R9T8 - Receive Bit 9 / Transmit Bit 8
83638  */
83639 #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
83640 #define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
83641 #define LPUART_CTRL_R8T9_SHIFT                   (31U)
83642 /*! R8T9 - Receive Bit 8 / Transmit Bit 9
83643  */
83644 #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
83645 /*! @} */
83646 
83647 /*! @name DATA - LPUART Data Register */
83648 /*! @{ */
83649 #define LPUART_DATA_R0T0_MASK                    (0x1U)
83650 #define LPUART_DATA_R0T0_SHIFT                   (0U)
83651 /*! R0T0 - R0T0
83652  */
83653 #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
83654 #define LPUART_DATA_R1T1_MASK                    (0x2U)
83655 #define LPUART_DATA_R1T1_SHIFT                   (1U)
83656 /*! R1T1 - R1T1
83657  */
83658 #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
83659 #define LPUART_DATA_R2T2_MASK                    (0x4U)
83660 #define LPUART_DATA_R2T2_SHIFT                   (2U)
83661 /*! R2T2 - R2T2
83662  */
83663 #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
83664 #define LPUART_DATA_R3T3_MASK                    (0x8U)
83665 #define LPUART_DATA_R3T3_SHIFT                   (3U)
83666 /*! R3T3 - R3T3
83667  */
83668 #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
83669 #define LPUART_DATA_R4T4_MASK                    (0x10U)
83670 #define LPUART_DATA_R4T4_SHIFT                   (4U)
83671 /*! R4T4 - R4T4
83672  */
83673 #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
83674 #define LPUART_DATA_R5T5_MASK                    (0x20U)
83675 #define LPUART_DATA_R5T5_SHIFT                   (5U)
83676 /*! R5T5 - R5T5
83677  */
83678 #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
83679 #define LPUART_DATA_R6T6_MASK                    (0x40U)
83680 #define LPUART_DATA_R6T6_SHIFT                   (6U)
83681 /*! R6T6 - R6T6
83682  */
83683 #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
83684 #define LPUART_DATA_R7T7_MASK                    (0x80U)
83685 #define LPUART_DATA_R7T7_SHIFT                   (7U)
83686 /*! R7T7 - R7T7
83687  */
83688 #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
83689 #define LPUART_DATA_R8T8_MASK                    (0x100U)
83690 #define LPUART_DATA_R8T8_SHIFT                   (8U)
83691 /*! R8T8 - R8T8
83692  */
83693 #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
83694 #define LPUART_DATA_R9T9_MASK                    (0x200U)
83695 #define LPUART_DATA_R9T9_SHIFT                   (9U)
83696 /*! R9T9 - R9T9
83697  */
83698 #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
83699 #define LPUART_DATA_IDLINE_MASK                  (0x800U)
83700 #define LPUART_DATA_IDLINE_SHIFT                 (11U)
83701 /*! IDLINE - Idle Line
83702  *  0b0..Receiver was not idle before receiving this character.
83703  *  0b1..Receiver was idle before receiving this character.
83704  */
83705 #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
83706 #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
83707 #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
83708 /*! RXEMPT - Receive Buffer Empty
83709  *  0b0..Receive buffer contains valid data.
83710  *  0b1..Receive buffer is empty, data returned on read is not valid.
83711  */
83712 #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
83713 #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
83714 #define LPUART_DATA_FRETSC_SHIFT                 (13U)
83715 /*! FRETSC - Frame Error / Transmit Special Character
83716  *  0b0..The dataword was received without a frame error on read, or transmit a normal character on write.
83717  *  0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit.
83718  */
83719 #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
83720 #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
83721 #define LPUART_DATA_PARITYE_SHIFT                (14U)
83722 /*! PARITYE - PARITYE
83723  *  0b0..The dataword was received without a parity error.
83724  *  0b1..The dataword was received with a parity error.
83725  */
83726 #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
83727 #define LPUART_DATA_NOISY_MASK                   (0x8000U)
83728 #define LPUART_DATA_NOISY_SHIFT                  (15U)
83729 /*! NOISY - NOISY
83730  *  0b0..The dataword was received without noise.
83731  *  0b1..The data was received with noise.
83732  */
83733 #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
83734 /*! @} */
83735 
83736 /*! @name MATCH - LPUART Match Address Register */
83737 /*! @{ */
83738 #define LPUART_MATCH_MA1_MASK                    (0x3FFU)
83739 #define LPUART_MATCH_MA1_SHIFT                   (0U)
83740 /*! MA1 - Match Address 1
83741  */
83742 #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
83743 #define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
83744 #define LPUART_MATCH_MA2_SHIFT                   (16U)
83745 /*! MA2 - Match Address 2
83746  */
83747 #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
83748 /*! @} */
83749 
83750 /*! @name MODIR - LPUART Modem IrDA Register */
83751 /*! @{ */
83752 #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
83753 #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
83754 /*! TXCTSE - Transmitter clear-to-send enable
83755  *  0b0..CTS has no effect on the transmitter.
83756  *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
83757  *       character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
83758  *       mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
83759  *       do not affect its transmission.
83760  */
83761 #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
83762 #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
83763 #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
83764 /*! TXRTSE - Transmitter request-to-send enable
83765  *  0b0..The transmitter has no effect on RTS.
83766  *  0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the
83767  *       start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and
83768  *       shift register are completely sent, including the last stop bit.
83769  */
83770 #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
83771 #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
83772 #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
83773 /*! TXRTSPOL - Transmitter request-to-send polarity
83774  *  0b0..Transmitter RTS is active low.
83775  *  0b1..Transmitter RTS is active high.
83776  */
83777 #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
83778 #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
83779 #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
83780 /*! RXRTSE - Receiver request-to-send enable
83781  *  0b0..The receiver has no effect on RTS.
83782  *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
83783  *       the receiver data register to become full. RTS is asserted if the receiver data register is not full and
83784  *       has not detected a start bit that would cause the receiver data register to become full.
83785  */
83786 #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
83787 #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
83788 #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
83789 /*! TXCTSC - Transmit CTS Configuration
83790  *  0b0..CTS input is sampled at the start of each character.
83791  *  0b1..CTS input is sampled when the transmitter is idle.
83792  */
83793 #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
83794 #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
83795 #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
83796 /*! TXCTSSRC - Transmit CTS Source
83797  *  0b0..CTS input is the CTS_B pin.
83798  *  0b1..CTS input is the inverted Receiver Match result.
83799  */
83800 #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
83801 #define LPUART_MODIR_RTSWATER_MASK               (0x3F00U)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
83802 #define LPUART_MODIR_RTSWATER_SHIFT              (8U)
83803 /*! RTSWATER - Receive RTS Configuration
83804  */
83805 #define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
83806 #define LPUART_MODIR_TNP_MASK                    (0x30000U)
83807 #define LPUART_MODIR_TNP_SHIFT                   (16U)
83808 /*! TNP - Transmitter narrow pulse
83809  *  0b00..1/OSR.
83810  *  0b01..2/OSR.
83811  *  0b10..3/OSR.
83812  *  0b11..4/OSR.
83813  */
83814 #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
83815 #define LPUART_MODIR_IREN_MASK                   (0x40000U)
83816 #define LPUART_MODIR_IREN_SHIFT                  (18U)
83817 /*! IREN - Infrared enable
83818  *  0b0..IR disabled.
83819  *  0b1..IR enabled.
83820  */
83821 #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
83822 /*! @} */
83823 
83824 /*! @name FIFO - LPUART FIFO Register */
83825 /*! @{ */
83826 #define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
83827 #define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
83828 /*! RXFIFOSIZE - Receive FIFO Buffer Depth
83829  *  0b000..Receive FIFO/Buffer depth = 1 dataword.
83830  *  0b001..Receive FIFO/Buffer depth = 4 datawords.
83831  *  0b010..Receive FIFO/Buffer depth = 8 datawords.
83832  *  0b011..Receive FIFO/Buffer depth = 16 datawords.
83833  *  0b100..Receive FIFO/Buffer depth = 32 datawords.
83834  *  0b101..Receive FIFO/Buffer depth = 64 datawords.
83835  *  0b110..Receive FIFO/Buffer depth = 128 datawords.
83836  *  0b111..Receive FIFO/Buffer depth = 256 datawords.
83837  */
83838 #define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
83839 #define LPUART_FIFO_RXFE_MASK                    (0x8U)
83840 #define LPUART_FIFO_RXFE_SHIFT                   (3U)
83841 /*! RXFE - Receive FIFO Enable
83842  *  0b0..Receive FIFO is not enabled. Buffer is depth 1.
83843  *  0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
83844  */
83845 #define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
83846 #define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
83847 #define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
83848 /*! TXFIFOSIZE - Transmit FIFO Buffer Depth
83849  *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
83850  *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
83851  *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
83852  *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
83853  *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
83854  *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
83855  *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
83856  *  0b111..Transmit FIFO/Buffer depth = 256 datawords
83857  */
83858 #define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
83859 #define LPUART_FIFO_TXFE_MASK                    (0x80U)
83860 #define LPUART_FIFO_TXFE_SHIFT                   (7U)
83861 /*! TXFE - Transmit FIFO Enable
83862  *  0b0..Transmit FIFO is not enabled. Buffer is depth 1.
83863  *  0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
83864  */
83865 #define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
83866 #define LPUART_FIFO_RXUFE_MASK                   (0x100U)
83867 #define LPUART_FIFO_RXUFE_SHIFT                  (8U)
83868 /*! RXUFE - Receive FIFO Underflow Interrupt Enable
83869  *  0b0..RXUF flag does not generate an interrupt to the host.
83870  *  0b1..RXUF flag generates an interrupt to the host.
83871  */
83872 #define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
83873 #define LPUART_FIFO_TXOFE_MASK                   (0x200U)
83874 #define LPUART_FIFO_TXOFE_SHIFT                  (9U)
83875 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
83876  *  0b0..TXOF flag does not generate an interrupt to the host.
83877  *  0b1..TXOF flag generates an interrupt to the host.
83878  */
83879 #define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
83880 #define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
83881 #define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
83882 /*! RXIDEN - Receiver Idle Empty Enable
83883  *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
83884  *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
83885  *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
83886  *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
83887  *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
83888  *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
83889  *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
83890  *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
83891  */
83892 #define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
83893 #define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
83894 #define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
83895 /*! RXFLUSH - Receive FIFO/Buffer Flush
83896  *  0b0..No flush operation occurs.
83897  *  0b1..All data in the receive FIFO/buffer is cleared out.
83898  */
83899 #define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
83900 #define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
83901 #define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
83902 /*! TXFLUSH - Transmit FIFO/Buffer Flush
83903  *  0b0..No flush operation occurs.
83904  *  0b1..All data in the transmit FIFO/Buffer is cleared out.
83905  */
83906 #define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
83907 #define LPUART_FIFO_RXUF_MASK                    (0x10000U)
83908 #define LPUART_FIFO_RXUF_SHIFT                   (16U)
83909 /*! RXUF - Receiver Buffer Underflow Flag
83910  *  0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
83911  *  0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
83912  */
83913 #define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
83914 #define LPUART_FIFO_TXOF_MASK                    (0x20000U)
83915 #define LPUART_FIFO_TXOF_SHIFT                   (17U)
83916 /*! TXOF - Transmitter Buffer Overflow Flag
83917  *  0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
83918  *  0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
83919  */
83920 #define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
83921 #define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
83922 #define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
83923 /*! RXEMPT - Receive Buffer/FIFO Empty
83924  *  0b0..Receive buffer is not empty.
83925  *  0b1..Receive buffer is empty.
83926  */
83927 #define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
83928 #define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
83929 #define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
83930 /*! TXEMPT - Transmit Buffer/FIFO Empty
83931  *  0b0..Transmit buffer is not empty.
83932  *  0b1..Transmit buffer is empty.
83933  */
83934 #define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
83935 /*! @} */
83936 
83937 /*! @name WATER - LPUART Watermark Register */
83938 /*! @{ */
83939 #define LPUART_WATER_TXWATER_MASK                (0x3FU)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
83940 #define LPUART_WATER_TXWATER_SHIFT               (0U)
83941 /*! TXWATER - Transmit Watermark
83942  */
83943 #define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
83944 #define LPUART_WATER_TXCOUNT_MASK                (0x7F00U)  /* Merged from fields with different position or width, of widths (6, 7), largest definition used */
83945 #define LPUART_WATER_TXCOUNT_SHIFT               (8U)
83946 /*! TXCOUNT - Transmit Counter
83947  */
83948 #define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (6, 7), largest definition used */
83949 #define LPUART_WATER_RXWATER_MASK                (0x3F0000U)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
83950 #define LPUART_WATER_RXWATER_SHIFT               (16U)
83951 /*! RXWATER - Receive Watermark
83952  */
83953 #define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
83954 #define LPUART_WATER_RXCOUNT_MASK                (0x7F000000U)  /* Merged from fields with different position or width, of widths (6, 7), largest definition used */
83955 #define LPUART_WATER_RXCOUNT_SHIFT               (24U)
83956 /*! RXCOUNT - Receive Counter
83957  */
83958 #define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (6, 7), largest definition used */
83959 /*! @} */
83960 
83961 
83962 /*!
83963  * @}
83964  */ /* end of group LPUART_Register_Masks */
83965 
83966 
83967 /* LPUART - Peripheral instance base addresses */
83968 /** Peripheral ADMA__LPUART0 base address */
83969 #define ADMA__LPUART0_BASE                       (0x5A060000u)
83970 /** Peripheral ADMA__LPUART0 base pointer */
83971 #define ADMA__LPUART0                            ((LPUART_Type *)ADMA__LPUART0_BASE)
83972 /** Peripheral ADMA__LPUART1 base address */
83973 #define ADMA__LPUART1_BASE                       (0x5A070000u)
83974 /** Peripheral ADMA__LPUART1 base pointer */
83975 #define ADMA__LPUART1                            ((LPUART_Type *)ADMA__LPUART1_BASE)
83976 /** Peripheral ADMA__LPUART2 base address */
83977 #define ADMA__LPUART2_BASE                       (0x5A080000u)
83978 /** Peripheral ADMA__LPUART2 base pointer */
83979 #define ADMA__LPUART2                            ((LPUART_Type *)ADMA__LPUART2_BASE)
83980 /** Peripheral ADMA__LPUART3 base address */
83981 #define ADMA__LPUART3_BASE                       (0x5A090000u)
83982 /** Peripheral ADMA__LPUART3 base pointer */
83983 #define ADMA__LPUART3                            ((LPUART_Type *)ADMA__LPUART3_BASE)
83984 /** Peripheral CM4__LPUART base address */
83985 #define CM4__LPUART_BASE                         (0x41220000u)
83986 /** Peripheral CM4__LPUART base pointer */
83987 #define CM4__LPUART                              ((LPUART_Type *)CM4__LPUART_BASE)
83988 /** Peripheral SCU__LPUART base address */
83989 #define SCU__LPUART_BASE                         (0x33220000u)
83990 /** Peripheral SCU__LPUART base pointer */
83991 #define SCU__LPUART                              ((LPUART_Type *)SCU__LPUART_BASE)
83992 /** Array initializer of LPUART peripheral base addresses */
83993 #define LPUART_BASE_ADDRS                        { ADMA__LPUART0_BASE, ADMA__LPUART1_BASE, ADMA__LPUART2_BASE, ADMA__LPUART3_BASE, CM4__LPUART_BASE, SCU__LPUART_BASE }
83994 /** Array initializer of LPUART peripheral base pointers */
83995 #define LPUART_BASE_PTRS                         { ADMA__LPUART0, ADMA__LPUART1, ADMA__LPUART2, ADMA__LPUART3, CM4__LPUART, SCU__LPUART }
83996 /** Interrupt vectors for the LPUART peripheral type */
83997 #define LPUART_RX_TX_IRQS                        { ADMA_UART0_INT_IRQn, ADMA_UART1_INT_IRQn, ADMA_UART2_INT_IRQn, ADMA_UART3_INT_IRQn, M4_LPUART_IRQn, NotAvail_IRQn }
83998 
83999 /*!
84000  * @}
84001  */ /* end of group LPUART_Peripheral_Access_Layer */
84002 
84003 
84004 /* ----------------------------------------------------------------------------
84005    -- LSIO_LPCG_GPIO0 Peripheral Access Layer
84006    ---------------------------------------------------------------------------- */
84007 
84008 /*!
84009  * @addtogroup LSIO_LPCG_GPIO0_Peripheral_Access_Layer LSIO_LPCG_GPIO0 Peripheral Access Layer
84010  * @{
84011  */
84012 
84013 /** LSIO_LPCG_GPIO0 - Register Layout Typedef */
84014 typedef struct {
84015   __IO uint32_t LPCG_GPIO0_0;                      /**< na, offset: 0x0 */
84016 } LSIO_LPCG_GPIO0_Type;
84017 
84018 /* ----------------------------------------------------------------------------
84019    -- LSIO_LPCG_GPIO0 Register Masks
84020    ---------------------------------------------------------------------------- */
84021 
84022 /*!
84023  * @addtogroup LSIO_LPCG_GPIO0_Register_Masks LSIO_LPCG_GPIO0 Register Masks
84024  * @{
84025  */
84026 
84027 /*! @name LPCG_GPIO0_0 - na */
84028 /*! @{ */
84029 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_MASK (0xFFFFU)
84030 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_SHIFT (0U)
84031 /*! LPCG_GPIO0_0_reserved_0_15 - reserved
84032  */
84033 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_MASK)
84034 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_MASK (0x10000U)
84035 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_SHIFT (16U)
84036 /*! gpio0_ipg_clk_s_HWEN - Hardware Enable
84037  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84038  *  0b1..Enable HW automatic gating
84039  */
84040 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_MASK)
84041 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_MASK (0x20000U)
84042 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_SHIFT (17U)
84043 /*! gpio0_ipg_clk_s_SWEN - Software Enable
84044  *  0b0..Disable SW clock regardless of HWEN
84045  *  0b1..Enable SW clock gating
84046  */
84047 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_MASK)
84048 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_MASK (0x40000U)
84049 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_SHIFT (18U)
84050 /*! LPCG_GPIO0_0_reserved_18_18 - reserved
84051  */
84052 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_MASK)
84053 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_MASK (0x80000U)
84054 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_SHIFT (19U)
84055 /*! gpio0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84056  */
84057 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_MASK)
84058 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_MASK (0xFFF00000U)
84059 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_SHIFT (20U)
84060 /*! LPCG_GPIO0_0_reserved_20_31 - reserved
84061  */
84062 #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_MASK)
84063 /*! @} */
84064 
84065 
84066 /*!
84067  * @}
84068  */ /* end of group LSIO_LPCG_GPIO0_Register_Masks */
84069 
84070 
84071 /* LSIO_LPCG_GPIO0 - Peripheral instance base addresses */
84072 /** Peripheral LSIO__LPCG_GPIO0 base address */
84073 #define LSIO__LPCG_GPIO0_BASE                    (0x5D480000u)
84074 /** Peripheral LSIO__LPCG_GPIO0 base pointer */
84075 #define LSIO__LPCG_GPIO0                         ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
84076 /** Array initializer of LSIO_LPCG_GPIO0 peripheral base addresses */
84077 #define LSIO_LPCG_GPIO0_BASE_ADDRS               { LSIO__LPCG_GPIO0_BASE }
84078 /** Array initializer of LSIO_LPCG_GPIO0 peripheral base pointers */
84079 #define LSIO_LPCG_GPIO0_BASE_PTRS                { LSIO__LPCG_GPIO0 }
84080 
84081 /*!
84082  * @}
84083  */ /* end of group LSIO_LPCG_GPIO0_Peripheral_Access_Layer */
84084 
84085 
84086 /* ----------------------------------------------------------------------------
84087    -- LSIO_LPCG_GPIO1 Peripheral Access Layer
84088    ---------------------------------------------------------------------------- */
84089 
84090 /*!
84091  * @addtogroup LSIO_LPCG_GPIO1_Peripheral_Access_Layer LSIO_LPCG_GPIO1 Peripheral Access Layer
84092  * @{
84093  */
84094 
84095 /** LSIO_LPCG_GPIO1 - Register Layout Typedef */
84096 typedef struct {
84097   __IO uint32_t LPCG_GPIO1_0;                      /**< na, offset: 0x0 */
84098 } LSIO_LPCG_GPIO1_Type;
84099 
84100 /* ----------------------------------------------------------------------------
84101    -- LSIO_LPCG_GPIO1 Register Masks
84102    ---------------------------------------------------------------------------- */
84103 
84104 /*!
84105  * @addtogroup LSIO_LPCG_GPIO1_Register_Masks LSIO_LPCG_GPIO1 Register Masks
84106  * @{
84107  */
84108 
84109 /*! @name LPCG_GPIO1_0 - na */
84110 /*! @{ */
84111 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_MASK (0xFFFFU)
84112 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_SHIFT (0U)
84113 /*! LPCG_GPIO1_0_reserved_0_15 - reserved
84114  */
84115 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_MASK)
84116 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_MASK (0x10000U)
84117 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_SHIFT (16U)
84118 /*! gpio1_ipg_clk_s_HWEN - Hardware Enable
84119  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84120  *  0b1..Enable HW automatic gating
84121  */
84122 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_MASK)
84123 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_MASK (0x20000U)
84124 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_SHIFT (17U)
84125 /*! gpio1_ipg_clk_s_SWEN - Software Enable
84126  *  0b0..Disable SW clock regardless of HWEN
84127  *  0b1..Enable SW clock gating
84128  */
84129 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_MASK)
84130 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_MASK (0x40000U)
84131 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_SHIFT (18U)
84132 /*! LPCG_GPIO1_0_reserved_18_18 - reserved
84133  */
84134 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_MASK)
84135 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_MASK (0x80000U)
84136 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_SHIFT (19U)
84137 /*! gpio1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84138  */
84139 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_MASK)
84140 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_MASK (0xFFF00000U)
84141 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_SHIFT (20U)
84142 /*! LPCG_GPIO1_0_reserved_20_31 - reserved
84143  */
84144 #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_MASK)
84145 /*! @} */
84146 
84147 
84148 /*!
84149  * @}
84150  */ /* end of group LSIO_LPCG_GPIO1_Register_Masks */
84151 
84152 
84153 /* LSIO_LPCG_GPIO1 - Peripheral instance base addresses */
84154 /** Peripheral LSIO__LPCG_GPIO1 base address */
84155 #define LSIO__LPCG_GPIO1_BASE                    (0x5D490000u)
84156 /** Peripheral LSIO__LPCG_GPIO1 base pointer */
84157 #define LSIO__LPCG_GPIO1                         ((LSIO_LPCG_GPIO1_Type *)LSIO__LPCG_GPIO1_BASE)
84158 /** Array initializer of LSIO_LPCG_GPIO1 peripheral base addresses */
84159 #define LSIO_LPCG_GPIO1_BASE_ADDRS               { LSIO__LPCG_GPIO1_BASE }
84160 /** Array initializer of LSIO_LPCG_GPIO1 peripheral base pointers */
84161 #define LSIO_LPCG_GPIO1_BASE_PTRS                { LSIO__LPCG_GPIO1 }
84162 
84163 /*!
84164  * @}
84165  */ /* end of group LSIO_LPCG_GPIO1_Peripheral_Access_Layer */
84166 
84167 
84168 /* ----------------------------------------------------------------------------
84169    -- LSIO_LPCG_GPIO2 Peripheral Access Layer
84170    ---------------------------------------------------------------------------- */
84171 
84172 /*!
84173  * @addtogroup LSIO_LPCG_GPIO2_Peripheral_Access_Layer LSIO_LPCG_GPIO2 Peripheral Access Layer
84174  * @{
84175  */
84176 
84177 /** LSIO_LPCG_GPIO2 - Register Layout Typedef */
84178 typedef struct {
84179   __IO uint32_t LPCG_GPIO2_0;                      /**< na, offset: 0x0 */
84180 } LSIO_LPCG_GPIO2_Type;
84181 
84182 /* ----------------------------------------------------------------------------
84183    -- LSIO_LPCG_GPIO2 Register Masks
84184    ---------------------------------------------------------------------------- */
84185 
84186 /*!
84187  * @addtogroup LSIO_LPCG_GPIO2_Register_Masks LSIO_LPCG_GPIO2 Register Masks
84188  * @{
84189  */
84190 
84191 /*! @name LPCG_GPIO2_0 - na */
84192 /*! @{ */
84193 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_MASK (0xFFFFU)
84194 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_SHIFT (0U)
84195 /*! LPCG_GPIO2_0_reserved_0_15 - reserved
84196  */
84197 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_MASK)
84198 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_MASK (0x10000U)
84199 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_SHIFT (16U)
84200 /*! gpio2_ipg_clk_s_HWEN - Hardware Enable
84201  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84202  *  0b1..Enable HW automatic gating
84203  */
84204 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_MASK)
84205 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_MASK (0x20000U)
84206 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_SHIFT (17U)
84207 /*! gpio2_ipg_clk_s_SWEN - Software Enable
84208  *  0b0..Disable SW clock regardless of HWEN
84209  *  0b1..Enable SW clock gating
84210  */
84211 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_MASK)
84212 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_MASK (0x40000U)
84213 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_SHIFT (18U)
84214 /*! LPCG_GPIO2_0_reserved_18_18 - reserved
84215  */
84216 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_MASK)
84217 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_MASK (0x80000U)
84218 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_SHIFT (19U)
84219 /*! gpio2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84220  */
84221 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_MASK)
84222 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_MASK (0xFFF00000U)
84223 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_SHIFT (20U)
84224 /*! LPCG_GPIO2_0_reserved_20_31 - reserved
84225  */
84226 #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_MASK)
84227 /*! @} */
84228 
84229 
84230 /*!
84231  * @}
84232  */ /* end of group LSIO_LPCG_GPIO2_Register_Masks */
84233 
84234 
84235 /* LSIO_LPCG_GPIO2 - Peripheral instance base addresses */
84236 /** Peripheral LSIO__LPCG_GPIO2 base address */
84237 #define LSIO__LPCG_GPIO2_BASE                    (0x5D4A0000u)
84238 /** Peripheral LSIO__LPCG_GPIO2 base pointer */
84239 #define LSIO__LPCG_GPIO2                         ((LSIO_LPCG_GPIO2_Type *)LSIO__LPCG_GPIO2_BASE)
84240 /** Array initializer of LSIO_LPCG_GPIO2 peripheral base addresses */
84241 #define LSIO_LPCG_GPIO2_BASE_ADDRS               { LSIO__LPCG_GPIO2_BASE }
84242 /** Array initializer of LSIO_LPCG_GPIO2 peripheral base pointers */
84243 #define LSIO_LPCG_GPIO2_BASE_PTRS                { LSIO__LPCG_GPIO2 }
84244 
84245 /*!
84246  * @}
84247  */ /* end of group LSIO_LPCG_GPIO2_Peripheral_Access_Layer */
84248 
84249 
84250 /* ----------------------------------------------------------------------------
84251    -- LSIO_LPCG_GPIO3 Peripheral Access Layer
84252    ---------------------------------------------------------------------------- */
84253 
84254 /*!
84255  * @addtogroup LSIO_LPCG_GPIO3_Peripheral_Access_Layer LSIO_LPCG_GPIO3 Peripheral Access Layer
84256  * @{
84257  */
84258 
84259 /** LSIO_LPCG_GPIO3 - Register Layout Typedef */
84260 typedef struct {
84261   __IO uint32_t LPCG_GPIO3_0;                      /**< na, offset: 0x0 */
84262 } LSIO_LPCG_GPIO3_Type;
84263 
84264 /* ----------------------------------------------------------------------------
84265    -- LSIO_LPCG_GPIO3 Register Masks
84266    ---------------------------------------------------------------------------- */
84267 
84268 /*!
84269  * @addtogroup LSIO_LPCG_GPIO3_Register_Masks LSIO_LPCG_GPIO3 Register Masks
84270  * @{
84271  */
84272 
84273 /*! @name LPCG_GPIO3_0 - na */
84274 /*! @{ */
84275 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_MASK (0xFFFFU)
84276 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_SHIFT (0U)
84277 /*! LPCG_GPIO3_0_reserved_0_15 - reserved
84278  */
84279 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_MASK)
84280 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_MASK (0x10000U)
84281 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_SHIFT (16U)
84282 /*! gpio3_ipg_clk_s_HWEN - Hardware Enable
84283  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84284  *  0b1..Enable HW automatic gating
84285  */
84286 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_MASK)
84287 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_MASK (0x20000U)
84288 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_SHIFT (17U)
84289 /*! gpio3_ipg_clk_s_SWEN - Software Enable
84290  *  0b0..Disable SW clock regardless of HWEN
84291  *  0b1..Enable SW clock gating
84292  */
84293 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_MASK)
84294 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_MASK (0x40000U)
84295 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_SHIFT (18U)
84296 /*! LPCG_GPIO3_0_reserved_18_18 - reserved
84297  */
84298 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_MASK)
84299 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_MASK (0x80000U)
84300 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_SHIFT (19U)
84301 /*! gpio3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84302  */
84303 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_MASK)
84304 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_MASK (0xFFF00000U)
84305 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_SHIFT (20U)
84306 /*! LPCG_GPIO3_0_reserved_20_31 - reserved
84307  */
84308 #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_MASK)
84309 /*! @} */
84310 
84311 
84312 /*!
84313  * @}
84314  */ /* end of group LSIO_LPCG_GPIO3_Register_Masks */
84315 
84316 
84317 /* LSIO_LPCG_GPIO3 - Peripheral instance base addresses */
84318 /** Peripheral LSIO__LPCG_GPIO3 base address */
84319 #define LSIO__LPCG_GPIO3_BASE                    (0x5D4B0000u)
84320 /** Peripheral LSIO__LPCG_GPIO3 base pointer */
84321 #define LSIO__LPCG_GPIO3                         ((LSIO_LPCG_GPIO3_Type *)LSIO__LPCG_GPIO3_BASE)
84322 /** Array initializer of LSIO_LPCG_GPIO3 peripheral base addresses */
84323 #define LSIO_LPCG_GPIO3_BASE_ADDRS               { LSIO__LPCG_GPIO3_BASE }
84324 /** Array initializer of LSIO_LPCG_GPIO3 peripheral base pointers */
84325 #define LSIO_LPCG_GPIO3_BASE_PTRS                { LSIO__LPCG_GPIO3 }
84326 
84327 /*!
84328  * @}
84329  */ /* end of group LSIO_LPCG_GPIO3_Peripheral_Access_Layer */
84330 
84331 
84332 /* ----------------------------------------------------------------------------
84333    -- LSIO_LPCG_GPIO4 Peripheral Access Layer
84334    ---------------------------------------------------------------------------- */
84335 
84336 /*!
84337  * @addtogroup LSIO_LPCG_GPIO4_Peripheral_Access_Layer LSIO_LPCG_GPIO4 Peripheral Access Layer
84338  * @{
84339  */
84340 
84341 /** LSIO_LPCG_GPIO4 - Register Layout Typedef */
84342 typedef struct {
84343   __IO uint32_t LPCG_GPIO4_0;                      /**< na, offset: 0x0 */
84344 } LSIO_LPCG_GPIO4_Type;
84345 
84346 /* ----------------------------------------------------------------------------
84347    -- LSIO_LPCG_GPIO4 Register Masks
84348    ---------------------------------------------------------------------------- */
84349 
84350 /*!
84351  * @addtogroup LSIO_LPCG_GPIO4_Register_Masks LSIO_LPCG_GPIO4 Register Masks
84352  * @{
84353  */
84354 
84355 /*! @name LPCG_GPIO4_0 - na */
84356 /*! @{ */
84357 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_MASK (0xFFFFU)
84358 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_SHIFT (0U)
84359 /*! LPCG_GPIO4_0_reserved_0_15 - reserved
84360  */
84361 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_MASK)
84362 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_MASK (0x10000U)
84363 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_SHIFT (16U)
84364 /*! gpio4_ipg_clk_s_HWEN - Hardware Enable
84365  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84366  *  0b1..Enable HW automatic gating
84367  */
84368 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_MASK)
84369 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_MASK (0x20000U)
84370 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_SHIFT (17U)
84371 /*! gpio4_ipg_clk_s_SWEN - Software Enable
84372  *  0b0..Disable SW clock regardless of HWEN
84373  *  0b1..Enable SW clock gating
84374  */
84375 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_MASK)
84376 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_MASK (0x40000U)
84377 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_SHIFT (18U)
84378 /*! LPCG_GPIO4_0_reserved_18_18 - reserved
84379  */
84380 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_MASK)
84381 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_MASK (0x80000U)
84382 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_SHIFT (19U)
84383 /*! gpio4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84384  */
84385 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_MASK)
84386 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_MASK (0xFFF00000U)
84387 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_SHIFT (20U)
84388 /*! LPCG_GPIO4_0_reserved_20_31 - reserved
84389  */
84390 #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_MASK)
84391 /*! @} */
84392 
84393 
84394 /*!
84395  * @}
84396  */ /* end of group LSIO_LPCG_GPIO4_Register_Masks */
84397 
84398 
84399 /* LSIO_LPCG_GPIO4 - Peripheral instance base addresses */
84400 /** Peripheral LSIO__LPCG_GPIO4 base address */
84401 #define LSIO__LPCG_GPIO4_BASE                    (0x5D4C0000u)
84402 /** Peripheral LSIO__LPCG_GPIO4 base pointer */
84403 #define LSIO__LPCG_GPIO4                         ((LSIO_LPCG_GPIO4_Type *)LSIO__LPCG_GPIO4_BASE)
84404 /** Array initializer of LSIO_LPCG_GPIO4 peripheral base addresses */
84405 #define LSIO_LPCG_GPIO4_BASE_ADDRS               { LSIO__LPCG_GPIO4_BASE }
84406 /** Array initializer of LSIO_LPCG_GPIO4 peripheral base pointers */
84407 #define LSIO_LPCG_GPIO4_BASE_PTRS                { LSIO__LPCG_GPIO4 }
84408 
84409 /*!
84410  * @}
84411  */ /* end of group LSIO_LPCG_GPIO4_Peripheral_Access_Layer */
84412 
84413 
84414 /* ----------------------------------------------------------------------------
84415    -- LSIO_LPCG_GPIO5 Peripheral Access Layer
84416    ---------------------------------------------------------------------------- */
84417 
84418 /*!
84419  * @addtogroup LSIO_LPCG_GPIO5_Peripheral_Access_Layer LSIO_LPCG_GPIO5 Peripheral Access Layer
84420  * @{
84421  */
84422 
84423 /** LSIO_LPCG_GPIO5 - Register Layout Typedef */
84424 typedef struct {
84425   __IO uint32_t LPCG_GPIO5_0;                      /**< na, offset: 0x0 */
84426 } LSIO_LPCG_GPIO5_Type;
84427 
84428 /* ----------------------------------------------------------------------------
84429    -- LSIO_LPCG_GPIO5 Register Masks
84430    ---------------------------------------------------------------------------- */
84431 
84432 /*!
84433  * @addtogroup LSIO_LPCG_GPIO5_Register_Masks LSIO_LPCG_GPIO5 Register Masks
84434  * @{
84435  */
84436 
84437 /*! @name LPCG_GPIO5_0 - na */
84438 /*! @{ */
84439 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_MASK (0xFFFFU)
84440 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_SHIFT (0U)
84441 /*! LPCG_GPIO5_0_reserved_0_15 - reserved
84442  */
84443 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_MASK)
84444 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_MASK (0x10000U)
84445 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_SHIFT (16U)
84446 /*! gpio5_ipg_clk_s_HWEN - Hardware Enable
84447  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84448  *  0b1..Enable HW automatic gating
84449  */
84450 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_MASK)
84451 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_MASK (0x20000U)
84452 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_SHIFT (17U)
84453 /*! gpio5_ipg_clk_s_SWEN - Software Enable
84454  *  0b0..Disable SW clock regardless of HWEN
84455  *  0b1..Enable SW clock gating
84456  */
84457 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_MASK)
84458 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_MASK (0x40000U)
84459 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_SHIFT (18U)
84460 /*! LPCG_GPIO5_0_reserved_18_18 - reserved
84461  */
84462 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_MASK)
84463 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_MASK (0x80000U)
84464 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_SHIFT (19U)
84465 /*! gpio5_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84466  */
84467 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_MASK)
84468 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_MASK (0xFFF00000U)
84469 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_SHIFT (20U)
84470 /*! LPCG_GPIO5_0_reserved_20_31 - reserved
84471  */
84472 #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_MASK)
84473 /*! @} */
84474 
84475 
84476 /*!
84477  * @}
84478  */ /* end of group LSIO_LPCG_GPIO5_Register_Masks */
84479 
84480 
84481 /* LSIO_LPCG_GPIO5 - Peripheral instance base addresses */
84482 /** Peripheral LSIO__LPCG_GPIO5 base address */
84483 #define LSIO__LPCG_GPIO5_BASE                    (0x5D4D0000u)
84484 /** Peripheral LSIO__LPCG_GPIO5 base pointer */
84485 #define LSIO__LPCG_GPIO5                         ((LSIO_LPCG_GPIO5_Type *)LSIO__LPCG_GPIO5_BASE)
84486 /** Array initializer of LSIO_LPCG_GPIO5 peripheral base addresses */
84487 #define LSIO_LPCG_GPIO5_BASE_ADDRS               { LSIO__LPCG_GPIO5_BASE }
84488 /** Array initializer of LSIO_LPCG_GPIO5 peripheral base pointers */
84489 #define LSIO_LPCG_GPIO5_BASE_PTRS                { LSIO__LPCG_GPIO5 }
84490 
84491 /*!
84492  * @}
84493  */ /* end of group LSIO_LPCG_GPIO5_Peripheral_Access_Layer */
84494 
84495 
84496 /* ----------------------------------------------------------------------------
84497    -- LSIO_LPCG_GPIO6 Peripheral Access Layer
84498    ---------------------------------------------------------------------------- */
84499 
84500 /*!
84501  * @addtogroup LSIO_LPCG_GPIO6_Peripheral_Access_Layer LSIO_LPCG_GPIO6 Peripheral Access Layer
84502  * @{
84503  */
84504 
84505 /** LSIO_LPCG_GPIO6 - Register Layout Typedef */
84506 typedef struct {
84507   __IO uint32_t LPCG_GPIO6_0;                      /**< na, offset: 0x0 */
84508 } LSIO_LPCG_GPIO6_Type;
84509 
84510 /* ----------------------------------------------------------------------------
84511    -- LSIO_LPCG_GPIO6 Register Masks
84512    ---------------------------------------------------------------------------- */
84513 
84514 /*!
84515  * @addtogroup LSIO_LPCG_GPIO6_Register_Masks LSIO_LPCG_GPIO6 Register Masks
84516  * @{
84517  */
84518 
84519 /*! @name LPCG_GPIO6_0 - na */
84520 /*! @{ */
84521 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_MASK (0xFFFFU)
84522 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_SHIFT (0U)
84523 /*! LPCG_GPIO6_0_reserved_0_15 - reserved
84524  */
84525 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_MASK)
84526 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_MASK (0x10000U)
84527 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_SHIFT (16U)
84528 /*! gpio6_ipg_clk_s_HWEN - Hardware Enable
84529  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84530  *  0b1..Enable HW automatic gating
84531  */
84532 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_MASK)
84533 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_MASK (0x20000U)
84534 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_SHIFT (17U)
84535 /*! gpio6_ipg_clk_s_SWEN - Software Enable
84536  *  0b0..Disable SW clock regardless of HWEN
84537  *  0b1..Enable SW clock gating
84538  */
84539 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_MASK)
84540 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_MASK (0x40000U)
84541 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_SHIFT (18U)
84542 /*! LPCG_GPIO6_0_reserved_18_18 - reserved
84543  */
84544 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_MASK)
84545 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_MASK (0x80000U)
84546 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_SHIFT (19U)
84547 /*! gpio6_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84548  */
84549 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_MASK)
84550 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_MASK (0xFFF00000U)
84551 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_SHIFT (20U)
84552 /*! LPCG_GPIO6_0_reserved_20_31 - reserved
84553  */
84554 #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_MASK)
84555 /*! @} */
84556 
84557 
84558 /*!
84559  * @}
84560  */ /* end of group LSIO_LPCG_GPIO6_Register_Masks */
84561 
84562 
84563 /* LSIO_LPCG_GPIO6 - Peripheral instance base addresses */
84564 /** Peripheral LSIO__LPCG_GPIO6 base address */
84565 #define LSIO__LPCG_GPIO6_BASE                    (0x5D4E0000u)
84566 /** Peripheral LSIO__LPCG_GPIO6 base pointer */
84567 #define LSIO__LPCG_GPIO6                         ((LSIO_LPCG_GPIO6_Type *)LSIO__LPCG_GPIO6_BASE)
84568 /** Array initializer of LSIO_LPCG_GPIO6 peripheral base addresses */
84569 #define LSIO_LPCG_GPIO6_BASE_ADDRS               { LSIO__LPCG_GPIO6_BASE }
84570 /** Array initializer of LSIO_LPCG_GPIO6 peripheral base pointers */
84571 #define LSIO_LPCG_GPIO6_BASE_PTRS                { LSIO__LPCG_GPIO6 }
84572 
84573 /*!
84574  * @}
84575  */ /* end of group LSIO_LPCG_GPIO6_Peripheral_Access_Layer */
84576 
84577 
84578 /* ----------------------------------------------------------------------------
84579    -- LSIO_LPCG_GPIO7 Peripheral Access Layer
84580    ---------------------------------------------------------------------------- */
84581 
84582 /*!
84583  * @addtogroup LSIO_LPCG_GPIO7_Peripheral_Access_Layer LSIO_LPCG_GPIO7 Peripheral Access Layer
84584  * @{
84585  */
84586 
84587 /** LSIO_LPCG_GPIO7 - Register Layout Typedef */
84588 typedef struct {
84589   __IO uint32_t LPCG_GPIO7_0;                      /**< na, offset: 0x0 */
84590 } LSIO_LPCG_GPIO7_Type;
84591 
84592 /* ----------------------------------------------------------------------------
84593    -- LSIO_LPCG_GPIO7 Register Masks
84594    ---------------------------------------------------------------------------- */
84595 
84596 /*!
84597  * @addtogroup LSIO_LPCG_GPIO7_Register_Masks LSIO_LPCG_GPIO7 Register Masks
84598  * @{
84599  */
84600 
84601 /*! @name LPCG_GPIO7_0 - na */
84602 /*! @{ */
84603 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_MASK (0xFFFFU)
84604 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_SHIFT (0U)
84605 /*! LPCG_GPIO7_0_reserved_0_15 - reserved
84606  */
84607 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_MASK)
84608 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_MASK (0x10000U)
84609 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_SHIFT (16U)
84610 /*! gpio7_ipg_clk_s_HWEN - Hardware Enable
84611  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84612  *  0b1..Enable HW automatic gating
84613  */
84614 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_MASK)
84615 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_MASK (0x20000U)
84616 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_SHIFT (17U)
84617 /*! gpio7_ipg_clk_s_SWEN - Software Enable
84618  *  0b0..Disable SW clock regardless of HWEN
84619  *  0b1..Enable SW clock gating
84620  */
84621 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_MASK)
84622 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_MASK (0x40000U)
84623 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_SHIFT (18U)
84624 /*! LPCG_GPIO7_0_reserved_18_18 - reserved
84625  */
84626 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_MASK)
84627 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_MASK (0x80000U)
84628 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_SHIFT (19U)
84629 /*! gpio7_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84630  */
84631 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_MASK)
84632 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_MASK (0xFFF00000U)
84633 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_SHIFT (20U)
84634 /*! LPCG_GPIO7_0_reserved_20_31 - reserved
84635  */
84636 #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_MASK)
84637 /*! @} */
84638 
84639 
84640 /*!
84641  * @}
84642  */ /* end of group LSIO_LPCG_GPIO7_Register_Masks */
84643 
84644 
84645 /* LSIO_LPCG_GPIO7 - Peripheral instance base addresses */
84646 /** Peripheral LSIO__LPCG_GPIO7 base address */
84647 #define LSIO__LPCG_GPIO7_BASE                    (0x5D4F0000u)
84648 /** Peripheral LSIO__LPCG_GPIO7 base pointer */
84649 #define LSIO__LPCG_GPIO7                         ((LSIO_LPCG_GPIO7_Type *)LSIO__LPCG_GPIO7_BASE)
84650 /** Array initializer of LSIO_LPCG_GPIO7 peripheral base addresses */
84651 #define LSIO_LPCG_GPIO7_BASE_ADDRS               { LSIO__LPCG_GPIO7_BASE }
84652 /** Array initializer of LSIO_LPCG_GPIO7 peripheral base pointers */
84653 #define LSIO_LPCG_GPIO7_BASE_PTRS                { LSIO__LPCG_GPIO7 }
84654 
84655 /*!
84656  * @}
84657  */ /* end of group LSIO_LPCG_GPIO7_Peripheral_Access_Layer */
84658 
84659 
84660 /* ----------------------------------------------------------------------------
84661    -- LSIO_LPCG_GPT0 Peripheral Access Layer
84662    ---------------------------------------------------------------------------- */
84663 
84664 /*!
84665  * @addtogroup LSIO_LPCG_GPT0_Peripheral_Access_Layer LSIO_LPCG_GPT0 Peripheral Access Layer
84666  * @{
84667  */
84668 
84669 /** LSIO_LPCG_GPT0 - Register Layout Typedef */
84670 typedef struct {
84671   __IO uint32_t LPCG_IPS_SYNC_GPT0_0;              /**< na, offset: 0x0 */
84672 } LSIO_LPCG_GPT0_Type;
84673 
84674 /* ----------------------------------------------------------------------------
84675    -- LSIO_LPCG_GPT0 Register Masks
84676    ---------------------------------------------------------------------------- */
84677 
84678 /*!
84679  * @addtogroup LSIO_LPCG_GPT0_Register_Masks LSIO_LPCG_GPT0 Register Masks
84680  * @{
84681  */
84682 
84683 /*! @name LPCG_IPS_SYNC_GPT0_0 - na */
84684 /*! @{ */
84685 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_MASK (0x1U)
84686 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_SHIFT (0U)
84687 /*! gpt0_ipg_clk_HWEN - Hardware Enable
84688  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84689  *  0b1..Enable HW automatic gating
84690  */
84691 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_MASK)
84692 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_MASK (0x2U)
84693 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_SHIFT (1U)
84694 /*! gpt0_ipg_clk_SWEN - Software Enable
84695  *  0b0..Disable SW clock regardless of HWEN
84696  *  0b1..Enable SW clock gating
84697  */
84698 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_MASK)
84699 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_MASK (0x4U)
84700 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_SHIFT (2U)
84701 /*! LPCG_IPS_SYNC_GPT0_0_reserved_2_2 - reserved
84702  */
84703 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_MASK)
84704 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_MASK (0x8U)
84705 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_SHIFT (3U)
84706 /*! gpt0_ipg_clk_STOP - show clock root status, 1 means clock stopped
84707  */
84708 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_MASK)
84709 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_MASK (0x10U)
84710 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_SHIFT (4U)
84711 /*! LPCG_IPS_SYNC_GPT0_0_reserved_4_4 - reserved
84712  */
84713 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_MASK)
84714 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_MASK (0x20U)
84715 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_SHIFT (5U)
84716 /*! gpt0_ipg_clk_highfreq_SWEN - Software Enable
84717  *  0b0..Disable SW clock regardless of HWEN
84718  *  0b1..Enable SW clock gating
84719  */
84720 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_MASK)
84721 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_MASK (0x40U)
84722 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_SHIFT (6U)
84723 /*! LPCG_IPS_SYNC_GPT0_0_reserved_6_6 - reserved
84724  */
84725 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_MASK)
84726 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_MASK (0x80U)
84727 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_SHIFT (7U)
84728 /*! gpt0_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
84729  */
84730 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_MASK)
84731 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_MASK (0x100U)
84732 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_SHIFT (8U)
84733 /*! LPCG_IPS_SYNC_GPT0_0_reserved_8_8 - reserved
84734  */
84735 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_MASK)
84736 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_MASK (0x200U)
84737 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_SHIFT (9U)
84738 /*! ccm_ckil_sync_wrapper0_clk_in_SWEN - Software Enable
84739  *  0b0..Disable SW clock regardless of HWEN
84740  *  0b1..Enable SW clock gating
84741  */
84742 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_MASK)
84743 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_MASK (0x400U)
84744 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_SHIFT (10U)
84745 /*! LPCG_IPS_SYNC_GPT0_0_reserved_10_10 - reserved
84746  */
84747 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_MASK)
84748 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_MASK (0x800U)
84749 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_SHIFT (11U)
84750 /*! ccm_ckil_sync_wrapper0_clk_in_STOP - show clock root status, 1 means clock stopped
84751  */
84752 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_MASK)
84753 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_MASK (0xF000U)
84754 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_SHIFT (12U)
84755 /*! LPCG_IPS_SYNC_GPT0_0_reserved_12_15 - reserved
84756  */
84757 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_MASK)
84758 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK (0x10000U)
84759 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT (16U)
84760 /*! gpt0_ipg_clk_s_HWEN - Hardware Enable
84761  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84762  *  0b1..Enable HW automatic gating
84763  */
84764 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK)
84765 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK (0x20000U)
84766 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT (17U)
84767 /*! gpt0_ipg_clk_s_SWEN - Software Enable
84768  *  0b0..Disable SW clock regardless of HWEN
84769  *  0b1..Enable SW clock gating
84770  */
84771 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK)
84772 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_MASK (0x40000U)
84773 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_SHIFT (18U)
84774 /*! LPCG_IPS_SYNC_GPT0_0_reserved_18_18 - reserved
84775  */
84776 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_MASK)
84777 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_MASK (0x80000U)
84778 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT (19U)
84779 /*! gpt0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84780  */
84781 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_MASK)
84782 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_MASK (0x100000U)
84783 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_SHIFT (20U)
84784 /*! LPCG_IPS_SYNC_GPT0_0_reserved_20_20 - reserved
84785  */
84786 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_MASK)
84787 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_MASK (0x200000U)
84788 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_SHIFT (21U)
84789 /*! ips_sync_gpt0_ipg_slave_clk_SWEN - Software Enable
84790  *  0b0..Disable SW clock regardless of HWEN
84791  *  0b1..Enable SW clock gating
84792  */
84793 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_MASK)
84794 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_MASK (0x400000U)
84795 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_SHIFT (22U)
84796 /*! LPCG_IPS_SYNC_GPT0_0_reserved_22_22 - reserved
84797  */
84798 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_MASK)
84799 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_MASK (0x800000U)
84800 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_SHIFT (23U)
84801 /*! ips_sync_gpt0_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
84802  */
84803 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_MASK)
84804 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_MASK (0x1000000U)
84805 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_SHIFT (24U)
84806 /*! ips_sync_gpt0_ipg_master_clk_HWEN - Hardware Enable
84807  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84808  *  0b1..Enable HW automatic gating
84809  */
84810 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_MASK)
84811 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_MASK (0x2000000U)
84812 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_SHIFT (25U)
84813 /*! ips_sync_gpt0_ipg_master_clk_SWEN - Software Enable
84814  *  0b0..Disable SW clock regardless of HWEN
84815  *  0b1..Enable SW clock gating
84816  */
84817 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_MASK)
84818 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_MASK (0x4000000U)
84819 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_SHIFT (26U)
84820 /*! LPCG_IPS_SYNC_GPT0_0_reserved_26_26 - reserved
84821  */
84822 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_MASK)
84823 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_MASK (0x8000000U)
84824 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_SHIFT (27U)
84825 /*! ips_sync_gpt0_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
84826  */
84827 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_MASK)
84828 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_MASK (0xF0000000U)
84829 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_SHIFT (28U)
84830 /*! LPCG_IPS_SYNC_GPT0_0_reserved_28_31 - reserved
84831  */
84832 #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_MASK)
84833 /*! @} */
84834 
84835 
84836 /*!
84837  * @}
84838  */ /* end of group LSIO_LPCG_GPT0_Register_Masks */
84839 
84840 
84841 /* LSIO_LPCG_GPT0 - Peripheral instance base addresses */
84842 /** Peripheral LSIO__LPCG_GPT0 base address */
84843 #define LSIO__LPCG_GPT0_BASE                     (0x5D540000u)
84844 /** Peripheral LSIO__LPCG_GPT0 base pointer */
84845 #define LSIO__LPCG_GPT0                          ((LSIO_LPCG_GPT0_Type *)LSIO__LPCG_GPT0_BASE)
84846 /** Array initializer of LSIO_LPCG_GPT0 peripheral base addresses */
84847 #define LSIO_LPCG_GPT0_BASE_ADDRS                { LSIO__LPCG_GPT0_BASE }
84848 /** Array initializer of LSIO_LPCG_GPT0 peripheral base pointers */
84849 #define LSIO_LPCG_GPT0_BASE_PTRS                 { LSIO__LPCG_GPT0 }
84850 
84851 /*!
84852  * @}
84853  */ /* end of group LSIO_LPCG_GPT0_Peripheral_Access_Layer */
84854 
84855 
84856 /* ----------------------------------------------------------------------------
84857    -- LSIO_LPCG_GPT1 Peripheral Access Layer
84858    ---------------------------------------------------------------------------- */
84859 
84860 /*!
84861  * @addtogroup LSIO_LPCG_GPT1_Peripheral_Access_Layer LSIO_LPCG_GPT1 Peripheral Access Layer
84862  * @{
84863  */
84864 
84865 /** LSIO_LPCG_GPT1 - Register Layout Typedef */
84866 typedef struct {
84867   __IO uint32_t LPCG_IPS_SYNC_GPT1_0;              /**< na, offset: 0x0 */
84868 } LSIO_LPCG_GPT1_Type;
84869 
84870 /* ----------------------------------------------------------------------------
84871    -- LSIO_LPCG_GPT1 Register Masks
84872    ---------------------------------------------------------------------------- */
84873 
84874 /*!
84875  * @addtogroup LSIO_LPCG_GPT1_Register_Masks LSIO_LPCG_GPT1 Register Masks
84876  * @{
84877  */
84878 
84879 /*! @name LPCG_IPS_SYNC_GPT1_0 - na */
84880 /*! @{ */
84881 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_MASK (0x1U)
84882 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_SHIFT (0U)
84883 /*! gpt1_ipg_clk_HWEN - Hardware Enable
84884  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84885  *  0b1..Enable HW automatic gating
84886  */
84887 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_MASK)
84888 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_MASK (0x2U)
84889 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_SHIFT (1U)
84890 /*! gpt1_ipg_clk_SWEN - Software Enable
84891  *  0b0..Disable SW clock regardless of HWEN
84892  *  0b1..Enable SW clock gating
84893  */
84894 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_MASK)
84895 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_MASK (0x4U)
84896 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_SHIFT (2U)
84897 /*! LPCG_IPS_SYNC_GPT1_0_reserved_2_2 - reserved
84898  */
84899 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_MASK)
84900 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_MASK (0x8U)
84901 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_SHIFT (3U)
84902 /*! gpt1_ipg_clk_STOP - show clock root status, 1 means clock stopped
84903  */
84904 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_MASK)
84905 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_MASK (0x10U)
84906 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_SHIFT (4U)
84907 /*! LPCG_IPS_SYNC_GPT1_0_reserved_4_4 - reserved
84908  */
84909 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_MASK)
84910 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_MASK (0x20U)
84911 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_SHIFT (5U)
84912 /*! gpt1_ipg_clk_highfreq_SWEN - Software Enable
84913  *  0b0..Disable SW clock regardless of HWEN
84914  *  0b1..Enable SW clock gating
84915  */
84916 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_MASK)
84917 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_MASK (0x40U)
84918 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_SHIFT (6U)
84919 /*! LPCG_IPS_SYNC_GPT1_0_reserved_6_6 - reserved
84920  */
84921 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_MASK)
84922 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_MASK (0x80U)
84923 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_SHIFT (7U)
84924 /*! gpt1_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
84925  */
84926 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_MASK)
84927 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_MASK (0x100U)
84928 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_SHIFT (8U)
84929 /*! LPCG_IPS_SYNC_GPT1_0_reserved_8_8 - reserved
84930  */
84931 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_MASK)
84932 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_MASK (0x200U)
84933 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_SHIFT (9U)
84934 /*! ccm_ckil_sync_wrapper1_clk_in_SWEN - Software Enable
84935  *  0b0..Disable SW clock regardless of HWEN
84936  *  0b1..Enable SW clock gating
84937  */
84938 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_MASK)
84939 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_MASK (0x400U)
84940 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_SHIFT (10U)
84941 /*! LPCG_IPS_SYNC_GPT1_0_reserved_10_10 - reserved
84942  */
84943 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_MASK)
84944 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_MASK (0x800U)
84945 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_SHIFT (11U)
84946 /*! ccm_ckil_sync_wrapper1_clk_in_STOP - show clock root status, 1 means clock stopped
84947  */
84948 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_MASK)
84949 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_MASK (0xF000U)
84950 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_SHIFT (12U)
84951 /*! LPCG_IPS_SYNC_GPT1_0_reserved_12_15 - reserved
84952  */
84953 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_MASK)
84954 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK (0x10000U)
84955 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT (16U)
84956 /*! gpt1_ipg_clk_s_HWEN - Hardware Enable
84957  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
84958  *  0b1..Enable HW automatic gating
84959  */
84960 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK)
84961 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK (0x20000U)
84962 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT (17U)
84963 /*! gpt1_ipg_clk_s_SWEN - Software Enable
84964  *  0b0..Disable SW clock regardless of HWEN
84965  *  0b1..Enable SW clock gating
84966  */
84967 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK)
84968 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_MASK (0x40000U)
84969 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_SHIFT (18U)
84970 /*! LPCG_IPS_SYNC_GPT1_0_reserved_18_18 - reserved
84971  */
84972 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_MASK)
84973 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_MASK (0x80000U)
84974 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT (19U)
84975 /*! gpt1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
84976  */
84977 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_MASK)
84978 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_MASK (0x100000U)
84979 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_SHIFT (20U)
84980 /*! LPCG_IPS_SYNC_GPT1_0_reserved_20_20 - reserved
84981  */
84982 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_MASK)
84983 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_MASK (0x200000U)
84984 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_SHIFT (21U)
84985 /*! ips_sync_gpt1_ipg_slave_clk_SWEN - Software Enable
84986  *  0b0..Disable SW clock regardless of HWEN
84987  *  0b1..Enable SW clock gating
84988  */
84989 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_MASK)
84990 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_MASK (0x400000U)
84991 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_SHIFT (22U)
84992 /*! LPCG_IPS_SYNC_GPT1_0_reserved_22_22 - reserved
84993  */
84994 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_MASK)
84995 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_MASK (0x800000U)
84996 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_SHIFT (23U)
84997 /*! ips_sync_gpt1_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
84998  */
84999 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_MASK)
85000 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_MASK (0x1000000U)
85001 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_SHIFT (24U)
85002 /*! ips_sync_gpt1_ipg_master_clk_HWEN - Hardware Enable
85003  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85004  *  0b1..Enable HW automatic gating
85005  */
85006 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_MASK)
85007 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_MASK (0x2000000U)
85008 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_SHIFT (25U)
85009 /*! ips_sync_gpt1_ipg_master_clk_SWEN - Software Enable
85010  *  0b0..Disable SW clock regardless of HWEN
85011  *  0b1..Enable SW clock gating
85012  */
85013 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_MASK)
85014 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_MASK (0x4000000U)
85015 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_SHIFT (26U)
85016 /*! LPCG_IPS_SYNC_GPT1_0_reserved_26_26 - reserved
85017  */
85018 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_MASK)
85019 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_MASK (0x8000000U)
85020 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_SHIFT (27U)
85021 /*! ips_sync_gpt1_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
85022  */
85023 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_MASK)
85024 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_MASK (0xF0000000U)
85025 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_SHIFT (28U)
85026 /*! LPCG_IPS_SYNC_GPT1_0_reserved_28_31 - reserved
85027  */
85028 #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_MASK)
85029 /*! @} */
85030 
85031 
85032 /*!
85033  * @}
85034  */ /* end of group LSIO_LPCG_GPT1_Register_Masks */
85035 
85036 
85037 /* LSIO_LPCG_GPT1 - Peripheral instance base addresses */
85038 /** Peripheral LSIO__LPCG_GPT1 base address */
85039 #define LSIO__LPCG_GPT1_BASE                     (0x5D550000u)
85040 /** Peripheral LSIO__LPCG_GPT1 base pointer */
85041 #define LSIO__LPCG_GPT1                          ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
85042 /** Array initializer of LSIO_LPCG_GPT1 peripheral base addresses */
85043 #define LSIO_LPCG_GPT1_BASE_ADDRS                { LSIO__LPCG_GPT1_BASE }
85044 /** Array initializer of LSIO_LPCG_GPT1 peripheral base pointers */
85045 #define LSIO_LPCG_GPT1_BASE_PTRS                 { LSIO__LPCG_GPT1 }
85046 
85047 /*!
85048  * @}
85049  */ /* end of group LSIO_LPCG_GPT1_Peripheral_Access_Layer */
85050 
85051 
85052 /* ----------------------------------------------------------------------------
85053    -- LSIO_LPCG_GPT2 Peripheral Access Layer
85054    ---------------------------------------------------------------------------- */
85055 
85056 /*!
85057  * @addtogroup LSIO_LPCG_GPT2_Peripheral_Access_Layer LSIO_LPCG_GPT2 Peripheral Access Layer
85058  * @{
85059  */
85060 
85061 /** LSIO_LPCG_GPT2 - Register Layout Typedef */
85062 typedef struct {
85063   __IO uint32_t LPCG_IPS_SYNC_GPT2_0;              /**< na, offset: 0x0 */
85064 } LSIO_LPCG_GPT2_Type;
85065 
85066 /* ----------------------------------------------------------------------------
85067    -- LSIO_LPCG_GPT2 Register Masks
85068    ---------------------------------------------------------------------------- */
85069 
85070 /*!
85071  * @addtogroup LSIO_LPCG_GPT2_Register_Masks LSIO_LPCG_GPT2 Register Masks
85072  * @{
85073  */
85074 
85075 /*! @name LPCG_IPS_SYNC_GPT2_0 - na */
85076 /*! @{ */
85077 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_MASK (0x1U)
85078 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_SHIFT (0U)
85079 /*! gpt2_ipg_clk_HWEN - Hardware Enable
85080  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85081  *  0b1..Enable HW automatic gating
85082  */
85083 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_MASK)
85084 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_MASK (0x2U)
85085 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_SHIFT (1U)
85086 /*! gpt2_ipg_clk_SWEN - Software Enable
85087  *  0b0..Disable SW clock regardless of HWEN
85088  *  0b1..Enable SW clock gating
85089  */
85090 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_MASK)
85091 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_MASK (0x4U)
85092 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_SHIFT (2U)
85093 /*! LPCG_IPS_SYNC_GPT2_0_reserved_2_2 - reserved
85094  */
85095 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_MASK)
85096 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_MASK (0x8U)
85097 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_SHIFT (3U)
85098 /*! gpt2_ipg_clk_STOP - show clock root status, 1 means clock stopped
85099  */
85100 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_MASK)
85101 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_MASK (0x10U)
85102 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_SHIFT (4U)
85103 /*! LPCG_IPS_SYNC_GPT2_0_reserved_4_4 - reserved
85104  */
85105 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_MASK)
85106 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_MASK (0x20U)
85107 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_SHIFT (5U)
85108 /*! gpt2_ipg_clk_highfreq_SWEN - Software Enable
85109  *  0b0..Disable SW clock regardless of HWEN
85110  *  0b1..Enable SW clock gating
85111  */
85112 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_MASK)
85113 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_MASK (0x40U)
85114 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_SHIFT (6U)
85115 /*! LPCG_IPS_SYNC_GPT2_0_reserved_6_6 - reserved
85116  */
85117 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_MASK)
85118 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_MASK (0x80U)
85119 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_SHIFT (7U)
85120 /*! gpt2_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
85121  */
85122 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_MASK)
85123 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_MASK (0x100U)
85124 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_SHIFT (8U)
85125 /*! LPCG_IPS_SYNC_GPT2_0_reserved_8_8 - reserved
85126  */
85127 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_MASK)
85128 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_MASK (0x200U)
85129 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_SHIFT (9U)
85130 /*! ccm_ckil_sync_wrapper2_clk_in_SWEN - Software Enable
85131  *  0b0..Disable SW clock regardless of HWEN
85132  *  0b1..Enable SW clock gating
85133  */
85134 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_MASK)
85135 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_MASK (0x400U)
85136 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_SHIFT (10U)
85137 /*! LPCG_IPS_SYNC_GPT2_0_reserved_10_10 - reserved
85138  */
85139 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_MASK)
85140 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_MASK (0x800U)
85141 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_SHIFT (11U)
85142 /*! ccm_ckil_sync_wrapper2_clk_in_STOP - show clock root status, 1 means clock stopped
85143  */
85144 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_MASK)
85145 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_MASK (0xF000U)
85146 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_SHIFT (12U)
85147 /*! LPCG_IPS_SYNC_GPT2_0_reserved_12_15 - reserved
85148  */
85149 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_MASK)
85150 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK (0x10000U)
85151 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT (16U)
85152 /*! gpt2_ipg_clk_s_HWEN - Hardware Enable
85153  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85154  *  0b1..Enable HW automatic gating
85155  */
85156 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK)
85157 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK (0x20000U)
85158 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT (17U)
85159 /*! gpt2_ipg_clk_s_SWEN - Software Enable
85160  *  0b0..Disable SW clock regardless of HWEN
85161  *  0b1..Enable SW clock gating
85162  */
85163 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK)
85164 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_MASK (0x40000U)
85165 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_SHIFT (18U)
85166 /*! LPCG_IPS_SYNC_GPT2_0_reserved_18_18 - reserved
85167  */
85168 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_MASK)
85169 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_MASK (0x80000U)
85170 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT (19U)
85171 /*! gpt2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
85172  */
85173 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_MASK)
85174 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_MASK (0x100000U)
85175 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_SHIFT (20U)
85176 /*! LPCG_IPS_SYNC_GPT2_0_reserved_20_20 - reserved
85177  */
85178 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_MASK)
85179 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_MASK (0x200000U)
85180 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_SHIFT (21U)
85181 /*! ips_sync_gpt2_ipg_slave_clk_SWEN - Software Enable
85182  *  0b0..Disable SW clock regardless of HWEN
85183  *  0b1..Enable SW clock gating
85184  */
85185 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_MASK)
85186 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_MASK (0x400000U)
85187 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_SHIFT (22U)
85188 /*! LPCG_IPS_SYNC_GPT2_0_reserved_22_22 - reserved
85189  */
85190 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_MASK)
85191 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_MASK (0x800000U)
85192 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_SHIFT (23U)
85193 /*! ips_sync_gpt2_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
85194  */
85195 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_MASK)
85196 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_MASK (0x1000000U)
85197 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_SHIFT (24U)
85198 /*! ips_sync_gpt2_ipg_master_clk_HWEN - Hardware Enable
85199  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85200  *  0b1..Enable HW automatic gating
85201  */
85202 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_MASK)
85203 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_MASK (0x2000000U)
85204 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_SHIFT (25U)
85205 /*! ips_sync_gpt2_ipg_master_clk_SWEN - Software Enable
85206  *  0b0..Disable SW clock regardless of HWEN
85207  *  0b1..Enable SW clock gating
85208  */
85209 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_MASK)
85210 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_MASK (0x4000000U)
85211 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_SHIFT (26U)
85212 /*! LPCG_IPS_SYNC_GPT2_0_reserved_26_26 - reserved
85213  */
85214 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_MASK)
85215 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_MASK (0x8000000U)
85216 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_SHIFT (27U)
85217 /*! ips_sync_gpt2_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
85218  */
85219 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_MASK)
85220 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_MASK (0xF0000000U)
85221 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_SHIFT (28U)
85222 /*! LPCG_IPS_SYNC_GPT2_0_reserved_28_31 - reserved
85223  */
85224 #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_MASK)
85225 /*! @} */
85226 
85227 
85228 /*!
85229  * @}
85230  */ /* end of group LSIO_LPCG_GPT2_Register_Masks */
85231 
85232 
85233 /* LSIO_LPCG_GPT2 - Peripheral instance base addresses */
85234 /** Peripheral LSIO__LPCG_GPT2 base address */
85235 #define LSIO__LPCG_GPT2_BASE                     (0x5D560000u)
85236 /** Peripheral LSIO__LPCG_GPT2 base pointer */
85237 #define LSIO__LPCG_GPT2                          ((LSIO_LPCG_GPT2_Type *)LSIO__LPCG_GPT2_BASE)
85238 /** Array initializer of LSIO_LPCG_GPT2 peripheral base addresses */
85239 #define LSIO_LPCG_GPT2_BASE_ADDRS                { LSIO__LPCG_GPT2_BASE }
85240 /** Array initializer of LSIO_LPCG_GPT2 peripheral base pointers */
85241 #define LSIO_LPCG_GPT2_BASE_PTRS                 { LSIO__LPCG_GPT2 }
85242 
85243 /*!
85244  * @}
85245  */ /* end of group LSIO_LPCG_GPT2_Peripheral_Access_Layer */
85246 
85247 
85248 /* ----------------------------------------------------------------------------
85249    -- LSIO_LPCG_GPT3 Peripheral Access Layer
85250    ---------------------------------------------------------------------------- */
85251 
85252 /*!
85253  * @addtogroup LSIO_LPCG_GPT3_Peripheral_Access_Layer LSIO_LPCG_GPT3 Peripheral Access Layer
85254  * @{
85255  */
85256 
85257 /** LSIO_LPCG_GPT3 - Register Layout Typedef */
85258 typedef struct {
85259   __IO uint32_t LPCG_IPS_SYNC_GPT3_0;              /**< na, offset: 0x0 */
85260 } LSIO_LPCG_GPT3_Type;
85261 
85262 /* ----------------------------------------------------------------------------
85263    -- LSIO_LPCG_GPT3 Register Masks
85264    ---------------------------------------------------------------------------- */
85265 
85266 /*!
85267  * @addtogroup LSIO_LPCG_GPT3_Register_Masks LSIO_LPCG_GPT3 Register Masks
85268  * @{
85269  */
85270 
85271 /*! @name LPCG_IPS_SYNC_GPT3_0 - na */
85272 /*! @{ */
85273 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_MASK (0x1U)
85274 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_SHIFT (0U)
85275 /*! gpt3_ipg_clk_HWEN - Hardware Enable
85276  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85277  *  0b1..Enable HW automatic gating
85278  */
85279 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_MASK)
85280 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_MASK (0x2U)
85281 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_SHIFT (1U)
85282 /*! gpt3_ipg_clk_SWEN - Software Enable
85283  *  0b0..Disable SW clock regardless of HWEN
85284  *  0b1..Enable SW clock gating
85285  */
85286 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_MASK)
85287 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_MASK (0x4U)
85288 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_SHIFT (2U)
85289 /*! LPCG_IPS_SYNC_GPT3_0_reserved_2_2 - reserved
85290  */
85291 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_MASK)
85292 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_MASK (0x8U)
85293 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_SHIFT (3U)
85294 /*! gpt3_ipg_clk_STOP - show clock root status, 1 means clock stopped
85295  */
85296 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_MASK)
85297 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_MASK (0x10U)
85298 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_SHIFT (4U)
85299 /*! LPCG_IPS_SYNC_GPT3_0_reserved_4_4 - reserved
85300  */
85301 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_MASK)
85302 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_MASK (0x20U)
85303 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_SHIFT (5U)
85304 /*! gpt3_ipg_clk_highfreq_SWEN - Software Enable
85305  *  0b0..Disable SW clock regardless of HWEN
85306  *  0b1..Enable SW clock gating
85307  */
85308 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_MASK)
85309 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_MASK (0x40U)
85310 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_SHIFT (6U)
85311 /*! LPCG_IPS_SYNC_GPT3_0_reserved_6_6 - reserved
85312  */
85313 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_MASK)
85314 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_MASK (0x80U)
85315 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_SHIFT (7U)
85316 /*! gpt3_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
85317  */
85318 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_MASK)
85319 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_MASK (0x100U)
85320 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_SHIFT (8U)
85321 /*! LPCG_IPS_SYNC_GPT3_0_reserved_8_8 - reserved
85322  */
85323 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_MASK)
85324 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_MASK (0x200U)
85325 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_SHIFT (9U)
85326 /*! ccm_ckil_sync_wrapper3_clk_in_SWEN - Software Enable
85327  *  0b0..Disable SW clock regardless of HWEN
85328  *  0b1..Enable SW clock gating
85329  */
85330 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_MASK)
85331 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_MASK (0x400U)
85332 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_SHIFT (10U)
85333 /*! LPCG_IPS_SYNC_GPT3_0_reserved_10_10 - reserved
85334  */
85335 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_MASK)
85336 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_MASK (0x800U)
85337 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_SHIFT (11U)
85338 /*! ccm_ckil_sync_wrapper3_clk_in_STOP - show clock root status, 1 means clock stopped
85339  */
85340 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_MASK)
85341 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_MASK (0xF000U)
85342 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_SHIFT (12U)
85343 /*! LPCG_IPS_SYNC_GPT3_0_reserved_12_15 - reserved
85344  */
85345 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_MASK)
85346 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK (0x10000U)
85347 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT (16U)
85348 /*! gpt3_ipg_clk_s_HWEN - Hardware Enable
85349  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85350  *  0b1..Enable HW automatic gating
85351  */
85352 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK)
85353 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK (0x20000U)
85354 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT (17U)
85355 /*! gpt3_ipg_clk_s_SWEN - Software Enable
85356  *  0b0..Disable SW clock regardless of HWEN
85357  *  0b1..Enable SW clock gating
85358  */
85359 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK)
85360 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_MASK (0x40000U)
85361 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_SHIFT (18U)
85362 /*! LPCG_IPS_SYNC_GPT3_0_reserved_18_18 - reserved
85363  */
85364 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_MASK)
85365 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_MASK (0x80000U)
85366 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT (19U)
85367 /*! gpt3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
85368  */
85369 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_MASK)
85370 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_MASK (0x100000U)
85371 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_SHIFT (20U)
85372 /*! LPCG_IPS_SYNC_GPT3_0_reserved_20_20 - reserved
85373  */
85374 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_MASK)
85375 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_MASK (0x200000U)
85376 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_SHIFT (21U)
85377 /*! ips_sync_gpt3_ipg_slave_clk_SWEN - Software Enable
85378  *  0b0..Disable SW clock regardless of HWEN
85379  *  0b1..Enable SW clock gating
85380  */
85381 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_MASK)
85382 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_MASK (0x400000U)
85383 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_SHIFT (22U)
85384 /*! LPCG_IPS_SYNC_GPT3_0_reserved_22_22 - reserved
85385  */
85386 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_MASK)
85387 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_MASK (0x800000U)
85388 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_SHIFT (23U)
85389 /*! ips_sync_gpt3_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
85390  */
85391 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_MASK)
85392 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_MASK (0x1000000U)
85393 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_SHIFT (24U)
85394 /*! ips_sync_gpt3_ipg_master_clk_HWEN - Hardware Enable
85395  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85396  *  0b1..Enable HW automatic gating
85397  */
85398 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_MASK)
85399 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_MASK (0x2000000U)
85400 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_SHIFT (25U)
85401 /*! ips_sync_gpt3_ipg_master_clk_SWEN - Software Enable
85402  *  0b0..Disable SW clock regardless of HWEN
85403  *  0b1..Enable SW clock gating
85404  */
85405 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_MASK)
85406 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_MASK (0x4000000U)
85407 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_SHIFT (26U)
85408 /*! LPCG_IPS_SYNC_GPT3_0_reserved_26_26 - reserved
85409  */
85410 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_MASK)
85411 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_MASK (0x8000000U)
85412 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_SHIFT (27U)
85413 /*! ips_sync_gpt3_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
85414  */
85415 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_MASK)
85416 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_MASK (0xF0000000U)
85417 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_SHIFT (28U)
85418 /*! LPCG_IPS_SYNC_GPT3_0_reserved_28_31 - reserved
85419  */
85420 #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_MASK)
85421 /*! @} */
85422 
85423 
85424 /*!
85425  * @}
85426  */ /* end of group LSIO_LPCG_GPT3_Register_Masks */
85427 
85428 
85429 /* LSIO_LPCG_GPT3 - Peripheral instance base addresses */
85430 /** Peripheral LSIO__LPCG_GPT3 base address */
85431 #define LSIO__LPCG_GPT3_BASE                     (0x5D570000u)
85432 /** Peripheral LSIO__LPCG_GPT3 base pointer */
85433 #define LSIO__LPCG_GPT3                          ((LSIO_LPCG_GPT3_Type *)LSIO__LPCG_GPT3_BASE)
85434 /** Array initializer of LSIO_LPCG_GPT3 peripheral base addresses */
85435 #define LSIO_LPCG_GPT3_BASE_ADDRS                { LSIO__LPCG_GPT3_BASE }
85436 /** Array initializer of LSIO_LPCG_GPT3 peripheral base pointers */
85437 #define LSIO_LPCG_GPT3_BASE_PTRS                 { LSIO__LPCG_GPT3 }
85438 
85439 /*!
85440  * @}
85441  */ /* end of group LSIO_LPCG_GPT3_Peripheral_Access_Layer */
85442 
85443 
85444 /* ----------------------------------------------------------------------------
85445    -- LSIO_LPCG_GPT4 Peripheral Access Layer
85446    ---------------------------------------------------------------------------- */
85447 
85448 /*!
85449  * @addtogroup LSIO_LPCG_GPT4_Peripheral_Access_Layer LSIO_LPCG_GPT4 Peripheral Access Layer
85450  * @{
85451  */
85452 
85453 /** LSIO_LPCG_GPT4 - Register Layout Typedef */
85454 typedef struct {
85455   __IO uint32_t LPCG_IPS_SYNC_GPT4_0;              /**< na, offset: 0x0 */
85456 } LSIO_LPCG_GPT4_Type;
85457 
85458 /* ----------------------------------------------------------------------------
85459    -- LSIO_LPCG_GPT4 Register Masks
85460    ---------------------------------------------------------------------------- */
85461 
85462 /*!
85463  * @addtogroup LSIO_LPCG_GPT4_Register_Masks LSIO_LPCG_GPT4 Register Masks
85464  * @{
85465  */
85466 
85467 /*! @name LPCG_IPS_SYNC_GPT4_0 - na */
85468 /*! @{ */
85469 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_MASK (0x1U)
85470 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_SHIFT (0U)
85471 /*! gpt4_ipg_clk_HWEN - Hardware Enable
85472  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85473  *  0b1..Enable HW automatic gating
85474  */
85475 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_MASK)
85476 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_MASK (0x2U)
85477 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_SHIFT (1U)
85478 /*! gpt4_ipg_clk_SWEN - Software Enable
85479  *  0b0..Disable SW clock regardless of HWEN
85480  *  0b1..Enable SW clock gating
85481  */
85482 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_MASK)
85483 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_MASK (0x4U)
85484 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_SHIFT (2U)
85485 /*! LPCG_IPS_SYNC_GPT4_0_reserved_2_2 - reserved
85486  */
85487 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_MASK)
85488 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_MASK (0x8U)
85489 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_SHIFT (3U)
85490 /*! gpt4_ipg_clk_STOP - show clock root status, 1 means clock stopped
85491  */
85492 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_MASK)
85493 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_MASK (0x10U)
85494 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_SHIFT (4U)
85495 /*! LPCG_IPS_SYNC_GPT4_0_reserved_4_4 - reserved
85496  */
85497 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_MASK)
85498 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_MASK (0x20U)
85499 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_SHIFT (5U)
85500 /*! gpt4_ipg_clk_highfreq_SWEN - Software Enable
85501  *  0b0..Disable SW clock regardless of HWEN
85502  *  0b1..Enable SW clock gating
85503  */
85504 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_MASK)
85505 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_MASK (0x40U)
85506 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_SHIFT (6U)
85507 /*! LPCG_IPS_SYNC_GPT4_0_reserved_6_6 - reserved
85508  */
85509 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_MASK)
85510 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_MASK (0x80U)
85511 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_SHIFT (7U)
85512 /*! gpt4_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
85513  */
85514 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_MASK)
85515 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_MASK (0x100U)
85516 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_SHIFT (8U)
85517 /*! LPCG_IPS_SYNC_GPT4_0_reserved_8_8 - reserved
85518  */
85519 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_MASK)
85520 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_MASK (0x200U)
85521 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_SHIFT (9U)
85522 /*! ccm_ckil_sync_wrapper4_clk_in_SWEN - Software Enable
85523  *  0b0..Disable SW clock regardless of HWEN
85524  *  0b1..Enable SW clock gating
85525  */
85526 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_MASK)
85527 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_MASK (0x400U)
85528 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_SHIFT (10U)
85529 /*! LPCG_IPS_SYNC_GPT4_0_reserved_10_10 - reserved
85530  */
85531 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_MASK)
85532 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_MASK (0x800U)
85533 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_SHIFT (11U)
85534 /*! ccm_ckil_sync_wrapper4_clk_in_STOP - show clock root status, 1 means clock stopped
85535  */
85536 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_MASK)
85537 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_MASK (0xF000U)
85538 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_SHIFT (12U)
85539 /*! LPCG_IPS_SYNC_GPT4_0_reserved_12_15 - reserved
85540  */
85541 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_MASK)
85542 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK (0x10000U)
85543 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT (16U)
85544 /*! gpt4_ipg_clk_s_HWEN - Hardware Enable
85545  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85546  *  0b1..Enable HW automatic gating
85547  */
85548 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK)
85549 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK (0x20000U)
85550 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT (17U)
85551 /*! gpt4_ipg_clk_s_SWEN - Software Enable
85552  *  0b0..Disable SW clock regardless of HWEN
85553  *  0b1..Enable SW clock gating
85554  */
85555 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK)
85556 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_MASK (0x40000U)
85557 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_SHIFT (18U)
85558 /*! LPCG_IPS_SYNC_GPT4_0_reserved_18_18 - reserved
85559  */
85560 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_MASK)
85561 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_MASK (0x80000U)
85562 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT (19U)
85563 /*! gpt4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
85564  */
85565 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_MASK)
85566 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_MASK (0x100000U)
85567 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_SHIFT (20U)
85568 /*! LPCG_IPS_SYNC_GPT4_0_reserved_20_20 - reserved
85569  */
85570 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_MASK)
85571 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_MASK (0x200000U)
85572 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_SHIFT (21U)
85573 /*! ips_sync_gpt4_ipg_slave_clk_SWEN - Software Enable
85574  *  0b0..Disable SW clock regardless of HWEN
85575  *  0b1..Enable SW clock gating
85576  */
85577 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_MASK)
85578 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_MASK (0x400000U)
85579 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_SHIFT (22U)
85580 /*! LPCG_IPS_SYNC_GPT4_0_reserved_22_22 - reserved
85581  */
85582 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_MASK)
85583 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_MASK (0x800000U)
85584 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_SHIFT (23U)
85585 /*! ips_sync_gpt4_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
85586  */
85587 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_MASK)
85588 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_MASK (0x1000000U)
85589 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_SHIFT (24U)
85590 /*! ips_sync_gpt4_ipg_master_clk_HWEN - Hardware Enable
85591  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85592  *  0b1..Enable HW automatic gating
85593  */
85594 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_MASK)
85595 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_MASK (0x2000000U)
85596 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_SHIFT (25U)
85597 /*! ips_sync_gpt4_ipg_master_clk_SWEN - Software Enable
85598  *  0b0..Disable SW clock regardless of HWEN
85599  *  0b1..Enable SW clock gating
85600  */
85601 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_MASK)
85602 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_MASK (0x4000000U)
85603 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_SHIFT (26U)
85604 /*! LPCG_IPS_SYNC_GPT4_0_reserved_26_26 - reserved
85605  */
85606 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_MASK)
85607 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_MASK (0x8000000U)
85608 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_SHIFT (27U)
85609 /*! ips_sync_gpt4_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
85610  */
85611 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_MASK)
85612 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_MASK (0xF0000000U)
85613 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_SHIFT (28U)
85614 /*! LPCG_IPS_SYNC_GPT4_0_reserved_28_31 - reserved
85615  */
85616 #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_MASK)
85617 /*! @} */
85618 
85619 
85620 /*!
85621  * @}
85622  */ /* end of group LSIO_LPCG_GPT4_Register_Masks */
85623 
85624 
85625 /* LSIO_LPCG_GPT4 - Peripheral instance base addresses */
85626 /** Peripheral LSIO__LPCG_GPT4 base address */
85627 #define LSIO__LPCG_GPT4_BASE                     (0x5D580000u)
85628 /** Peripheral LSIO__LPCG_GPT4 base pointer */
85629 #define LSIO__LPCG_GPT4                          ((LSIO_LPCG_GPT4_Type *)LSIO__LPCG_GPT4_BASE)
85630 /** Array initializer of LSIO_LPCG_GPT4 peripheral base addresses */
85631 #define LSIO_LPCG_GPT4_BASE_ADDRS                { LSIO__LPCG_GPT4_BASE }
85632 /** Array initializer of LSIO_LPCG_GPT4 peripheral base pointers */
85633 #define LSIO_LPCG_GPT4_BASE_PTRS                 { LSIO__LPCG_GPT4 }
85634 
85635 /*!
85636  * @}
85637  */ /* end of group LSIO_LPCG_GPT4_Peripheral_Access_Layer */
85638 
85639 
85640 /* ----------------------------------------------------------------------------
85641    -- LSIO_LPCG_KPP Peripheral Access Layer
85642    ---------------------------------------------------------------------------- */
85643 
85644 /*!
85645  * @addtogroup LSIO_LPCG_KPP_Peripheral_Access_Layer LSIO_LPCG_KPP Peripheral Access Layer
85646  * @{
85647  */
85648 
85649 /** LSIO_LPCG_KPP - Register Layout Typedef */
85650 typedef struct {
85651   __IO uint32_t LPCG_KPP_0;                        /**< na, offset: 0x0 */
85652 } LSIO_LPCG_KPP_Type;
85653 
85654 /* ----------------------------------------------------------------------------
85655    -- LSIO_LPCG_KPP Register Masks
85656    ---------------------------------------------------------------------------- */
85657 
85658 /*!
85659  * @addtogroup LSIO_LPCG_KPP_Register_Masks LSIO_LPCG_KPP Register Masks
85660  * @{
85661  */
85662 
85663 /*! @name LPCG_KPP_0 - na */
85664 /*! @{ */
85665 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_MASK (0x1U)
85666 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_SHIFT (0U)
85667 /*! LPCG_KPP_0_reserved_0_0 - reserved
85668  */
85669 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_MASK)
85670 #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_MASK (0x2U)
85671 #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_SHIFT (1U)
85672 /*! ccm_ckil_sync_wrapper13_clk_in_SWEN - Software Enable
85673  *  0b0..Disable SW clock regardless of HWEN
85674  *  0b1..Enable SW clock gating
85675  */
85676 #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_MASK)
85677 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_MASK (0x4U)
85678 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_SHIFT (2U)
85679 /*! LPCG_KPP_0_reserved_2_2 - reserved
85680  */
85681 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_MASK)
85682 #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_MASK (0x8U)
85683 #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_SHIFT (3U)
85684 /*! ccm_ckil_sync_wrapper13_clk_in_STOP - show clock root status, 1 means clock stopped
85685  */
85686 #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_MASK)
85687 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_MASK (0xFFF0U)
85688 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_SHIFT (4U)
85689 /*! LPCG_KPP_0_reserved_4_15 - reserved
85690  */
85691 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_MASK)
85692 #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_MASK (0x10000U)
85693 #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_SHIFT (16U)
85694 /*! kpp_ipg_clk_s_HWEN - Hardware Enable
85695  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85696  *  0b1..Enable HW automatic gating
85697  */
85698 #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_MASK)
85699 #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_MASK (0x20000U)
85700 #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_SHIFT (17U)
85701 /*! kpp_ipg_clk_s_SWEN - Software Enable
85702  *  0b0..Disable SW clock regardless of HWEN
85703  *  0b1..Enable SW clock gating
85704  */
85705 #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_MASK)
85706 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_MASK (0x40000U)
85707 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_SHIFT (18U)
85708 /*! LPCG_KPP_0_reserved_18_18 - reserved
85709  */
85710 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_MASK)
85711 #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_MASK (0x80000U)
85712 #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_SHIFT (19U)
85713 /*! kpp_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
85714  */
85715 #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_MASK)
85716 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_MASK (0xFFF00000U)
85717 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_SHIFT (20U)
85718 /*! LPCG_KPP_0_reserved_20_31 - reserved
85719  */
85720 #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_MASK)
85721 /*! @} */
85722 
85723 
85724 /*!
85725  * @}
85726  */ /* end of group LSIO_LPCG_KPP_Register_Masks */
85727 
85728 
85729 /* LSIO_LPCG_KPP - Peripheral instance base addresses */
85730 /** Peripheral LSIO__LPCG_KPP base address */
85731 #define LSIO__LPCG_KPP_BASE                      (0x5D5A0000u)
85732 /** Peripheral LSIO__LPCG_KPP base pointer */
85733 #define LSIO__LPCG_KPP                           ((LSIO_LPCG_KPP_Type *)LSIO__LPCG_KPP_BASE)
85734 /** Array initializer of LSIO_LPCG_KPP peripheral base addresses */
85735 #define LSIO_LPCG_KPP_BASE_ADDRS                 { LSIO__LPCG_KPP_BASE }
85736 /** Array initializer of LSIO_LPCG_KPP peripheral base pointers */
85737 #define LSIO_LPCG_KPP_BASE_PTRS                  { LSIO__LPCG_KPP }
85738 
85739 /*!
85740  * @}
85741  */ /* end of group LSIO_LPCG_KPP_Peripheral_Access_Layer */
85742 
85743 
85744 /* ----------------------------------------------------------------------------
85745    -- LSIO_LPCG_MU10_DSP Peripheral Access Layer
85746    ---------------------------------------------------------------------------- */
85747 
85748 /*!
85749  * @addtogroup LSIO_LPCG_MU10_DSP_Peripheral_Access_Layer LSIO_LPCG_MU10_DSP Peripheral Access Layer
85750  * @{
85751  */
85752 
85753 /** LSIO_LPCG_MU10_DSP - Register Layout Typedef */
85754 typedef struct {
85755   __IO uint32_t LPCG_MU10_DSP_0;                   /**< na, offset: 0x0 */
85756 } LSIO_LPCG_MU10_DSP_Type;
85757 
85758 /* ----------------------------------------------------------------------------
85759    -- LSIO_LPCG_MU10_DSP Register Masks
85760    ---------------------------------------------------------------------------- */
85761 
85762 /*!
85763  * @addtogroup LSIO_LPCG_MU10_DSP_Register_Masks LSIO_LPCG_MU10_DSP Register Masks
85764  * @{
85765  */
85766 
85767 /*! @name LPCG_MU10_DSP_0 - na */
85768 /*! @{ */
85769 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_MASK (0x1U)
85770 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_SHIFT (0U)
85771 /*! LPCG_MU10_DSP_0_reserved_0_0 - reserved
85772  */
85773 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_MASK)
85774 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_MASK (0x2U)
85775 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_SHIFT (1U)
85776 /*! mu10_ipg_clk_dsp_SWEN - Software Enable
85777  *  0b0..Disable SW clock regardless of HWEN
85778  *  0b1..Enable SW clock gating
85779  */
85780 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_MASK)
85781 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_MASK (0x4U)
85782 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_SHIFT (2U)
85783 /*! LPCG_MU10_DSP_0_reserved_2_2 - reserved
85784  */
85785 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_MASK)
85786 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_MASK (0x8U)
85787 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_SHIFT (3U)
85788 /*! mu10_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped
85789  */
85790 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_MASK)
85791 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_MASK (0xFFF0U)
85792 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_SHIFT (4U)
85793 /*! LPCG_MU10_DSP_0_reserved_4_15 - reserved
85794  */
85795 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_MASK)
85796 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
85797 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_SHIFT (16U)
85798 /*! mu10_ipg_clk_s_dsp_HWEN - Hardware Enable
85799  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85800  *  0b1..Enable HW automatic gating
85801  */
85802 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_MASK)
85803 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
85804 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_SHIFT (17U)
85805 /*! mu10_ipg_clk_s_dsp_SWEN - Software Enable
85806  *  0b0..Disable SW clock regardless of HWEN
85807  *  0b1..Enable SW clock gating
85808  */
85809 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_MASK)
85810 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_MASK (0x40000U)
85811 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_SHIFT (18U)
85812 /*! LPCG_MU10_DSP_0_reserved_18_18 - reserved
85813  */
85814 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_MASK)
85815 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_MASK (0x80000U)
85816 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_SHIFT (19U)
85817 /*! mu10_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped
85818  */
85819 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_MASK)
85820 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_MASK (0xFFF00000U)
85821 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_SHIFT (20U)
85822 /*! LPCG_MU10_DSP_0_reserved_20_31 - reserved
85823  */
85824 #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_MASK)
85825 /*! @} */
85826 
85827 
85828 /*!
85829  * @}
85830  */ /* end of group LSIO_LPCG_MU10_DSP_Register_Masks */
85831 
85832 
85833 /* LSIO_LPCG_MU10_DSP - Peripheral instance base addresses */
85834 /** Peripheral LSIO__LPCG_MU10_DSP base address */
85835 #define LSIO__LPCG_MU10_DSP_BASE                 (0x5D6E0000u)
85836 /** Peripheral LSIO__LPCG_MU10_DSP base pointer */
85837 #define LSIO__LPCG_MU10_DSP                      ((LSIO_LPCG_MU10_DSP_Type *)LSIO__LPCG_MU10_DSP_BASE)
85838 /** Array initializer of LSIO_LPCG_MU10_DSP peripheral base addresses */
85839 #define LSIO_LPCG_MU10_DSP_BASE_ADDRS            { LSIO__LPCG_MU10_DSP_BASE }
85840 /** Array initializer of LSIO_LPCG_MU10_DSP peripheral base pointers */
85841 #define LSIO_LPCG_MU10_DSP_BASE_PTRS             { LSIO__LPCG_MU10_DSP }
85842 
85843 /*!
85844  * @}
85845  */ /* end of group LSIO_LPCG_MU10_DSP_Peripheral_Access_Layer */
85846 
85847 
85848 /* ----------------------------------------------------------------------------
85849    -- LSIO_LPCG_MU10_MCU Peripheral Access Layer
85850    ---------------------------------------------------------------------------- */
85851 
85852 /*!
85853  * @addtogroup LSIO_LPCG_MU10_MCU_Peripheral_Access_Layer LSIO_LPCG_MU10_MCU Peripheral Access Layer
85854  * @{
85855  */
85856 
85857 /** LSIO_LPCG_MU10_MCU - Register Layout Typedef */
85858 typedef struct {
85859   __IO uint32_t LPCG_MU10_MCU_0;                   /**< na, offset: 0x0 */
85860 } LSIO_LPCG_MU10_MCU_Type;
85861 
85862 /* ----------------------------------------------------------------------------
85863    -- LSIO_LPCG_MU10_MCU Register Masks
85864    ---------------------------------------------------------------------------- */
85865 
85866 /*!
85867  * @addtogroup LSIO_LPCG_MU10_MCU_Register_Masks LSIO_LPCG_MU10_MCU Register Masks
85868  * @{
85869  */
85870 
85871 /*! @name LPCG_MU10_MCU_0 - na */
85872 /*! @{ */
85873 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_MASK (0x1U)
85874 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_SHIFT (0U)
85875 /*! LPCG_MU10_MCU_0_reserved_0_0 - reserved
85876  */
85877 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_MASK)
85878 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_MASK (0x2U)
85879 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_SHIFT (1U)
85880 /*! mu10_ipg_clk_mcu_SWEN - Software Enable
85881  *  0b0..Disable SW clock regardless of HWEN
85882  *  0b1..Enable SW clock gating
85883  */
85884 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_MASK)
85885 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_MASK (0x4U)
85886 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_SHIFT (2U)
85887 /*! LPCG_MU10_MCU_0_reserved_2_2 - reserved
85888  */
85889 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_MASK)
85890 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_MASK (0x8U)
85891 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_SHIFT (3U)
85892 /*! mu10_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped
85893  */
85894 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_MASK)
85895 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_MASK (0xFFF0U)
85896 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_SHIFT (4U)
85897 /*! LPCG_MU10_MCU_0_reserved_4_15 - reserved
85898  */
85899 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_MASK)
85900 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
85901 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_SHIFT (16U)
85902 /*! mu10_ipg_clk_s_mcu_HWEN - Hardware Enable
85903  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
85904  *  0b1..Enable HW automatic gating
85905  */
85906 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_MASK)
85907 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
85908 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_SHIFT (17U)
85909 /*! mu10_ipg_clk_s_mcu_SWEN - Software Enable
85910  *  0b0..Disable SW clock regardless of HWEN
85911  *  0b1..Enable SW clock gating
85912  */
85913 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_MASK)
85914 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_MASK (0x40000U)
85915 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_SHIFT (18U)
85916 /*! LPCG_MU10_MCU_0_reserved_18_18 - reserved
85917  */
85918 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_MASK)
85919 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_MASK (0x80000U)
85920 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_SHIFT (19U)
85921 /*! mu10_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped
85922  */
85923 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_MASK)
85924 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_MASK (0xFFF00000U)
85925 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_SHIFT (20U)
85926 /*! LPCG_MU10_MCU_0_reserved_20_31 - reserved
85927  */
85928 #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_MASK)
85929 /*! @} */
85930 
85931 
85932 /*!
85933  * @}
85934  */ /* end of group LSIO_LPCG_MU10_MCU_Register_Masks */
85935 
85936 
85937 /* LSIO_LPCG_MU10_MCU - Peripheral instance base addresses */
85938 /** Peripheral LSIO__LPCG_MU10_MCU base address */
85939 #define LSIO__LPCG_MU10_MCU_BASE                 (0x5D650000u)
85940 /** Peripheral LSIO__LPCG_MU10_MCU base pointer */
85941 #define LSIO__LPCG_MU10_MCU                      ((LSIO_LPCG_MU10_MCU_Type *)LSIO__LPCG_MU10_MCU_BASE)
85942 /** Array initializer of LSIO_LPCG_MU10_MCU peripheral base addresses */
85943 #define LSIO_LPCG_MU10_MCU_BASE_ADDRS            { LSIO__LPCG_MU10_MCU_BASE }
85944 /** Array initializer of LSIO_LPCG_MU10_MCU peripheral base pointers */
85945 #define LSIO_LPCG_MU10_MCU_BASE_PTRS             { LSIO__LPCG_MU10_MCU }
85946 
85947 /*!
85948  * @}
85949  */ /* end of group LSIO_LPCG_MU10_MCU_Peripheral_Access_Layer */
85950 
85951 
85952 /* ----------------------------------------------------------------------------
85953    -- LSIO_LPCG_MU11_DSP Peripheral Access Layer
85954    ---------------------------------------------------------------------------- */
85955 
85956 /*!
85957  * @addtogroup LSIO_LPCG_MU11_DSP_Peripheral_Access_Layer LSIO_LPCG_MU11_DSP Peripheral Access Layer
85958  * @{
85959  */
85960 
85961 /** LSIO_LPCG_MU11_DSP - Register Layout Typedef */
85962 typedef struct {
85963   __IO uint32_t LPCG_MU11_DSP_0;                   /**< na, offset: 0x0 */
85964 } LSIO_LPCG_MU11_DSP_Type;
85965 
85966 /* ----------------------------------------------------------------------------
85967    -- LSIO_LPCG_MU11_DSP Register Masks
85968    ---------------------------------------------------------------------------- */
85969 
85970 /*!
85971  * @addtogroup LSIO_LPCG_MU11_DSP_Register_Masks LSIO_LPCG_MU11_DSP Register Masks
85972  * @{
85973  */
85974 
85975 /*! @name LPCG_MU11_DSP_0 - na */
85976 /*! @{ */
85977 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_MASK (0x1U)
85978 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_SHIFT (0U)
85979 /*! LPCG_MU11_DSP_0_reserved_0_0 - reserved
85980  */
85981 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_MASK)
85982 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_MASK (0x2U)
85983 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_SHIFT (1U)
85984 /*! mu11_ipg_clk_dsp_SWEN - Software Enable
85985  *  0b0..Disable SW clock regardless of HWEN
85986  *  0b1..Enable SW clock gating
85987  */
85988 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_MASK)
85989 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_MASK (0x4U)
85990 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_SHIFT (2U)
85991 /*! LPCG_MU11_DSP_0_reserved_2_2 - reserved
85992  */
85993 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_MASK)
85994 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_MASK (0x8U)
85995 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_SHIFT (3U)
85996 /*! mu11_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped
85997  */
85998 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_MASK)
85999 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_MASK (0xFFF0U)
86000 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_SHIFT (4U)
86001 /*! LPCG_MU11_DSP_0_reserved_4_15 - reserved
86002  */
86003 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_MASK)
86004 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
86005 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_SHIFT (16U)
86006 /*! mu11_ipg_clk_s_dsp_HWEN - Hardware Enable
86007  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86008  *  0b1..Enable HW automatic gating
86009  */
86010 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_MASK)
86011 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
86012 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_SHIFT (17U)
86013 /*! mu11_ipg_clk_s_dsp_SWEN - Software Enable
86014  *  0b0..Disable SW clock regardless of HWEN
86015  *  0b1..Enable SW clock gating
86016  */
86017 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_MASK)
86018 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_MASK (0x40000U)
86019 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_SHIFT (18U)
86020 /*! LPCG_MU11_DSP_0_reserved_18_18 - reserved
86021  */
86022 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_MASK)
86023 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_MASK (0x80000U)
86024 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_SHIFT (19U)
86025 /*! mu11_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped
86026  */
86027 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_MASK)
86028 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_MASK (0xFFF00000U)
86029 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_SHIFT (20U)
86030 /*! LPCG_MU11_DSP_0_reserved_20_31 - reserved
86031  */
86032 #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_MASK)
86033 /*! @} */
86034 
86035 
86036 /*!
86037  * @}
86038  */ /* end of group LSIO_LPCG_MU11_DSP_Register_Masks */
86039 
86040 
86041 /* LSIO_LPCG_MU11_DSP - Peripheral instance base addresses */
86042 /** Peripheral LSIO__LPCG_MU11_DSP base address */
86043 #define LSIO__LPCG_MU11_DSP_BASE                 (0x5D6F0000u)
86044 /** Peripheral LSIO__LPCG_MU11_DSP base pointer */
86045 #define LSIO__LPCG_MU11_DSP                      ((LSIO_LPCG_MU11_DSP_Type *)LSIO__LPCG_MU11_DSP_BASE)
86046 /** Array initializer of LSIO_LPCG_MU11_DSP peripheral base addresses */
86047 #define LSIO_LPCG_MU11_DSP_BASE_ADDRS            { LSIO__LPCG_MU11_DSP_BASE }
86048 /** Array initializer of LSIO_LPCG_MU11_DSP peripheral base pointers */
86049 #define LSIO_LPCG_MU11_DSP_BASE_PTRS             { LSIO__LPCG_MU11_DSP }
86050 
86051 /*!
86052  * @}
86053  */ /* end of group LSIO_LPCG_MU11_DSP_Peripheral_Access_Layer */
86054 
86055 
86056 /* ----------------------------------------------------------------------------
86057    -- LSIO_LPCG_MU11_MCU Peripheral Access Layer
86058    ---------------------------------------------------------------------------- */
86059 
86060 /*!
86061  * @addtogroup LSIO_LPCG_MU11_MCU_Peripheral_Access_Layer LSIO_LPCG_MU11_MCU Peripheral Access Layer
86062  * @{
86063  */
86064 
86065 /** LSIO_LPCG_MU11_MCU - Register Layout Typedef */
86066 typedef struct {
86067   __IO uint32_t LPCG_MU11_MCU_0;                   /**< na, offset: 0x0 */
86068 } LSIO_LPCG_MU11_MCU_Type;
86069 
86070 /* ----------------------------------------------------------------------------
86071    -- LSIO_LPCG_MU11_MCU Register Masks
86072    ---------------------------------------------------------------------------- */
86073 
86074 /*!
86075  * @addtogroup LSIO_LPCG_MU11_MCU_Register_Masks LSIO_LPCG_MU11_MCU Register Masks
86076  * @{
86077  */
86078 
86079 /*! @name LPCG_MU11_MCU_0 - na */
86080 /*! @{ */
86081 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_MASK (0x1U)
86082 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_SHIFT (0U)
86083 /*! LPCG_MU11_MCU_0_reserved_0_0 - reserved
86084  */
86085 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_MASK)
86086 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_MASK (0x2U)
86087 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_SHIFT (1U)
86088 /*! mu11_ipg_clk_mcu_SWEN - Software Enable
86089  *  0b0..Disable SW clock regardless of HWEN
86090  *  0b1..Enable SW clock gating
86091  */
86092 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_MASK)
86093 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_MASK (0x4U)
86094 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_SHIFT (2U)
86095 /*! LPCG_MU11_MCU_0_reserved_2_2 - reserved
86096  */
86097 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_MASK)
86098 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_MASK (0x8U)
86099 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_SHIFT (3U)
86100 /*! mu11_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped
86101  */
86102 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_MASK)
86103 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_MASK (0xFFF0U)
86104 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_SHIFT (4U)
86105 /*! LPCG_MU11_MCU_0_reserved_4_15 - reserved
86106  */
86107 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_MASK)
86108 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
86109 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_SHIFT (16U)
86110 /*! mu11_ipg_clk_s_mcu_HWEN - Hardware Enable
86111  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86112  *  0b1..Enable HW automatic gating
86113  */
86114 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_MASK)
86115 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
86116 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_SHIFT (17U)
86117 /*! mu11_ipg_clk_s_mcu_SWEN - Software Enable
86118  *  0b0..Disable SW clock regardless of HWEN
86119  *  0b1..Enable SW clock gating
86120  */
86121 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_MASK)
86122 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_MASK (0x40000U)
86123 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_SHIFT (18U)
86124 /*! LPCG_MU11_MCU_0_reserved_18_18 - reserved
86125  */
86126 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_MASK)
86127 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_MASK (0x80000U)
86128 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_SHIFT (19U)
86129 /*! mu11_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped
86130  */
86131 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_MASK)
86132 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_MASK (0xFFF00000U)
86133 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_SHIFT (20U)
86134 /*! LPCG_MU11_MCU_0_reserved_20_31 - reserved
86135  */
86136 #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_MASK)
86137 /*! @} */
86138 
86139 
86140 /*!
86141  * @}
86142  */ /* end of group LSIO_LPCG_MU11_MCU_Register_Masks */
86143 
86144 
86145 /* LSIO_LPCG_MU11_MCU - Peripheral instance base addresses */
86146 /** Peripheral LSIO__LPCG_MU11_MCU base address */
86147 #define LSIO__LPCG_MU11_MCU_BASE                 (0x5D660000u)
86148 /** Peripheral LSIO__LPCG_MU11_MCU base pointer */
86149 #define LSIO__LPCG_MU11_MCU                      ((LSIO_LPCG_MU11_MCU_Type *)LSIO__LPCG_MU11_MCU_BASE)
86150 /** Array initializer of LSIO_LPCG_MU11_MCU peripheral base addresses */
86151 #define LSIO_LPCG_MU11_MCU_BASE_ADDRS            { LSIO__LPCG_MU11_MCU_BASE }
86152 /** Array initializer of LSIO_LPCG_MU11_MCU peripheral base pointers */
86153 #define LSIO_LPCG_MU11_MCU_BASE_PTRS             { LSIO__LPCG_MU11_MCU }
86154 
86155 /*!
86156  * @}
86157  */ /* end of group LSIO_LPCG_MU11_MCU_Peripheral_Access_Layer */
86158 
86159 
86160 /* ----------------------------------------------------------------------------
86161    -- LSIO_LPCG_MU12_DSP Peripheral Access Layer
86162    ---------------------------------------------------------------------------- */
86163 
86164 /*!
86165  * @addtogroup LSIO_LPCG_MU12_DSP_Peripheral_Access_Layer LSIO_LPCG_MU12_DSP Peripheral Access Layer
86166  * @{
86167  */
86168 
86169 /** LSIO_LPCG_MU12_DSP - Register Layout Typedef */
86170 typedef struct {
86171   __IO uint32_t LPCG_MU12_DSP_0;                   /**< na, offset: 0x0 */
86172 } LSIO_LPCG_MU12_DSP_Type;
86173 
86174 /* ----------------------------------------------------------------------------
86175    -- LSIO_LPCG_MU12_DSP Register Masks
86176    ---------------------------------------------------------------------------- */
86177 
86178 /*!
86179  * @addtogroup LSIO_LPCG_MU12_DSP_Register_Masks LSIO_LPCG_MU12_DSP Register Masks
86180  * @{
86181  */
86182 
86183 /*! @name LPCG_MU12_DSP_0 - na */
86184 /*! @{ */
86185 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_MASK (0x1U)
86186 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_SHIFT (0U)
86187 /*! LPCG_MU12_DSP_0_reserved_0_0 - reserved
86188  */
86189 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_MASK)
86190 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_MASK (0x2U)
86191 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_SHIFT (1U)
86192 /*! mu12_ipg_clk_dsp_SWEN - Software Enable
86193  *  0b0..Disable SW clock regardless of HWEN
86194  *  0b1..Enable SW clock gating
86195  */
86196 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_MASK)
86197 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_MASK (0x4U)
86198 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_SHIFT (2U)
86199 /*! LPCG_MU12_DSP_0_reserved_2_2 - reserved
86200  */
86201 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_MASK)
86202 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_MASK (0x8U)
86203 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_SHIFT (3U)
86204 /*! mu12_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped
86205  */
86206 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_MASK)
86207 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_MASK (0xFFF0U)
86208 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_SHIFT (4U)
86209 /*! LPCG_MU12_DSP_0_reserved_4_15 - reserved
86210  */
86211 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_MASK)
86212 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
86213 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_SHIFT (16U)
86214 /*! mu12_ipg_clk_s_dsp_HWEN - Hardware Enable
86215  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86216  *  0b1..Enable HW automatic gating
86217  */
86218 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_MASK)
86219 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
86220 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_SHIFT (17U)
86221 /*! mu12_ipg_clk_s_dsp_SWEN - Software Enable
86222  *  0b0..Disable SW clock regardless of HWEN
86223  *  0b1..Enable SW clock gating
86224  */
86225 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_MASK)
86226 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_MASK (0x40000U)
86227 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_SHIFT (18U)
86228 /*! LPCG_MU12_DSP_0_reserved_18_18 - reserved
86229  */
86230 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_MASK)
86231 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_MASK (0x80000U)
86232 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_SHIFT (19U)
86233 /*! mu12_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped
86234  */
86235 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_MASK)
86236 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_MASK (0xFFF00000U)
86237 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_SHIFT (20U)
86238 /*! LPCG_MU12_DSP_0_reserved_20_31 - reserved
86239  */
86240 #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_MASK)
86241 /*! @} */
86242 
86243 
86244 /*!
86245  * @}
86246  */ /* end of group LSIO_LPCG_MU12_DSP_Register_Masks */
86247 
86248 
86249 /* LSIO_LPCG_MU12_DSP - Peripheral instance base addresses */
86250 /** Peripheral LSIO__LPCG_MU12_DSP base address */
86251 #define LSIO__LPCG_MU12_DSP_BASE                 (0x5D700000u)
86252 /** Peripheral LSIO__LPCG_MU12_DSP base pointer */
86253 #define LSIO__LPCG_MU12_DSP                      ((LSIO_LPCG_MU12_DSP_Type *)LSIO__LPCG_MU12_DSP_BASE)
86254 /** Array initializer of LSIO_LPCG_MU12_DSP peripheral base addresses */
86255 #define LSIO_LPCG_MU12_DSP_BASE_ADDRS            { LSIO__LPCG_MU12_DSP_BASE }
86256 /** Array initializer of LSIO_LPCG_MU12_DSP peripheral base pointers */
86257 #define LSIO_LPCG_MU12_DSP_BASE_PTRS             { LSIO__LPCG_MU12_DSP }
86258 
86259 /*!
86260  * @}
86261  */ /* end of group LSIO_LPCG_MU12_DSP_Peripheral_Access_Layer */
86262 
86263 
86264 /* ----------------------------------------------------------------------------
86265    -- LSIO_LPCG_MU12_MCU Peripheral Access Layer
86266    ---------------------------------------------------------------------------- */
86267 
86268 /*!
86269  * @addtogroup LSIO_LPCG_MU12_MCU_Peripheral_Access_Layer LSIO_LPCG_MU12_MCU Peripheral Access Layer
86270  * @{
86271  */
86272 
86273 /** LSIO_LPCG_MU12_MCU - Register Layout Typedef */
86274 typedef struct {
86275   __IO uint32_t LPCG_MU12_MCU_0;                   /**< na, offset: 0x0 */
86276 } LSIO_LPCG_MU12_MCU_Type;
86277 
86278 /* ----------------------------------------------------------------------------
86279    -- LSIO_LPCG_MU12_MCU Register Masks
86280    ---------------------------------------------------------------------------- */
86281 
86282 /*!
86283  * @addtogroup LSIO_LPCG_MU12_MCU_Register_Masks LSIO_LPCG_MU12_MCU Register Masks
86284  * @{
86285  */
86286 
86287 /*! @name LPCG_MU12_MCU_0 - na */
86288 /*! @{ */
86289 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_MASK (0x1U)
86290 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_SHIFT (0U)
86291 /*! LPCG_MU12_MCU_0_reserved_0_0 - reserved
86292  */
86293 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_MASK)
86294 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_MASK (0x2U)
86295 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_SHIFT (1U)
86296 /*! mu12_ipg_clk_mcu_SWEN - Software Enable
86297  *  0b0..Disable SW clock regardless of HWEN
86298  *  0b1..Enable SW clock gating
86299  */
86300 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_MASK)
86301 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_MASK (0x4U)
86302 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_SHIFT (2U)
86303 /*! LPCG_MU12_MCU_0_reserved_2_2 - reserved
86304  */
86305 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_MASK)
86306 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_MASK (0x8U)
86307 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_SHIFT (3U)
86308 /*! mu12_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped
86309  */
86310 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_MASK)
86311 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_MASK (0xFFF0U)
86312 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_SHIFT (4U)
86313 /*! LPCG_MU12_MCU_0_reserved_4_15 - reserved
86314  */
86315 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_MASK)
86316 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
86317 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_SHIFT (16U)
86318 /*! mu12_ipg_clk_s_mcu_HWEN - Hardware Enable
86319  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86320  *  0b1..Enable HW automatic gating
86321  */
86322 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_MASK)
86323 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
86324 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_SHIFT (17U)
86325 /*! mu12_ipg_clk_s_mcu_SWEN - Software Enable
86326  *  0b0..Disable SW clock regardless of HWEN
86327  *  0b1..Enable SW clock gating
86328  */
86329 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_MASK)
86330 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_MASK (0x40000U)
86331 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_SHIFT (18U)
86332 /*! LPCG_MU12_MCU_0_reserved_18_18 - reserved
86333  */
86334 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_MASK)
86335 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_MASK (0x80000U)
86336 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_SHIFT (19U)
86337 /*! mu12_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped
86338  */
86339 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_MASK)
86340 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_MASK (0xFFF00000U)
86341 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_SHIFT (20U)
86342 /*! LPCG_MU12_MCU_0_reserved_20_31 - reserved
86343  */
86344 #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_MASK)
86345 /*! @} */
86346 
86347 
86348 /*!
86349  * @}
86350  */ /* end of group LSIO_LPCG_MU12_MCU_Register_Masks */
86351 
86352 
86353 /* LSIO_LPCG_MU12_MCU - Peripheral instance base addresses */
86354 /** Peripheral LSIO__LPCG_MU12_MCU base address */
86355 #define LSIO__LPCG_MU12_MCU_BASE                 (0x5D670000u)
86356 /** Peripheral LSIO__LPCG_MU12_MCU base pointer */
86357 #define LSIO__LPCG_MU12_MCU                      ((LSIO_LPCG_MU12_MCU_Type *)LSIO__LPCG_MU12_MCU_BASE)
86358 /** Array initializer of LSIO_LPCG_MU12_MCU peripheral base addresses */
86359 #define LSIO_LPCG_MU12_MCU_BASE_ADDRS            { LSIO__LPCG_MU12_MCU_BASE }
86360 /** Array initializer of LSIO_LPCG_MU12_MCU peripheral base pointers */
86361 #define LSIO_LPCG_MU12_MCU_BASE_PTRS             { LSIO__LPCG_MU12_MCU }
86362 
86363 /*!
86364  * @}
86365  */ /* end of group LSIO_LPCG_MU12_MCU_Peripheral_Access_Layer */
86366 
86367 
86368 /* ----------------------------------------------------------------------------
86369    -- LSIO_LPCG_MU13_DSP Peripheral Access Layer
86370    ---------------------------------------------------------------------------- */
86371 
86372 /*!
86373  * @addtogroup LSIO_LPCG_MU13_DSP_Peripheral_Access_Layer LSIO_LPCG_MU13_DSP Peripheral Access Layer
86374  * @{
86375  */
86376 
86377 /** LSIO_LPCG_MU13_DSP - Register Layout Typedef */
86378 typedef struct {
86379   __IO uint32_t LPCG_MU13_DSP_0;                   /**< na, offset: 0x0 */
86380 } LSIO_LPCG_MU13_DSP_Type;
86381 
86382 /* ----------------------------------------------------------------------------
86383    -- LSIO_LPCG_MU13_DSP Register Masks
86384    ---------------------------------------------------------------------------- */
86385 
86386 /*!
86387  * @addtogroup LSIO_LPCG_MU13_DSP_Register_Masks LSIO_LPCG_MU13_DSP Register Masks
86388  * @{
86389  */
86390 
86391 /*! @name LPCG_MU13_DSP_0 - na */
86392 /*! @{ */
86393 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_MASK (0x1U)
86394 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_SHIFT (0U)
86395 /*! LPCG_MU13_DSP_0_reserved_0_0 - reserved
86396  */
86397 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_MASK)
86398 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_MASK (0x2U)
86399 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_SHIFT (1U)
86400 /*! mu13_ipg_clk_dsp_SWEN - Software Enable
86401  *  0b0..Disable SW clock regardless of HWEN
86402  *  0b1..Enable SW clock gating
86403  */
86404 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_MASK)
86405 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_MASK (0x4U)
86406 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_SHIFT (2U)
86407 /*! LPCG_MU13_DSP_0_reserved_2_2 - reserved
86408  */
86409 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_MASK)
86410 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_MASK (0x8U)
86411 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_SHIFT (3U)
86412 /*! mu13_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped
86413  */
86414 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_MASK)
86415 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_MASK (0xFFF0U)
86416 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_SHIFT (4U)
86417 /*! LPCG_MU13_DSP_0_reserved_4_15 - reserved
86418  */
86419 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_MASK)
86420 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
86421 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_SHIFT (16U)
86422 /*! mu13_ipg_clk_s_dsp_HWEN - Hardware Enable
86423  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86424  *  0b1..Enable HW automatic gating
86425  */
86426 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_MASK)
86427 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
86428 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_SHIFT (17U)
86429 /*! mu13_ipg_clk_s_dsp_SWEN - Software Enable
86430  *  0b0..Disable SW clock regardless of HWEN
86431  *  0b1..Enable SW clock gating
86432  */
86433 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_MASK)
86434 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_MASK (0x40000U)
86435 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_SHIFT (18U)
86436 /*! LPCG_MU13_DSP_0_reserved_18_18 - reserved
86437  */
86438 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_MASK)
86439 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_MASK (0x80000U)
86440 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_SHIFT (19U)
86441 /*! mu13_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped
86442  */
86443 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_MASK)
86444 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_MASK (0xFFF00000U)
86445 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_SHIFT (20U)
86446 /*! LPCG_MU13_DSP_0_reserved_20_31 - reserved
86447  */
86448 #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_MASK)
86449 /*! @} */
86450 
86451 
86452 /*!
86453  * @}
86454  */ /* end of group LSIO_LPCG_MU13_DSP_Register_Masks */
86455 
86456 
86457 /* LSIO_LPCG_MU13_DSP - Peripheral instance base addresses */
86458 /** Peripheral LSIO__LPCG_MU13_DSP base address */
86459 #define LSIO__LPCG_MU13_DSP_BASE                 (0x5D710000u)
86460 /** Peripheral LSIO__LPCG_MU13_DSP base pointer */
86461 #define LSIO__LPCG_MU13_DSP                      ((LSIO_LPCG_MU13_DSP_Type *)LSIO__LPCG_MU13_DSP_BASE)
86462 /** Array initializer of LSIO_LPCG_MU13_DSP peripheral base addresses */
86463 #define LSIO_LPCG_MU13_DSP_BASE_ADDRS            { LSIO__LPCG_MU13_DSP_BASE }
86464 /** Array initializer of LSIO_LPCG_MU13_DSP peripheral base pointers */
86465 #define LSIO_LPCG_MU13_DSP_BASE_PTRS             { LSIO__LPCG_MU13_DSP }
86466 
86467 /*!
86468  * @}
86469  */ /* end of group LSIO_LPCG_MU13_DSP_Peripheral_Access_Layer */
86470 
86471 
86472 /* ----------------------------------------------------------------------------
86473    -- LSIO_LPCG_MU13_MCU Peripheral Access Layer
86474    ---------------------------------------------------------------------------- */
86475 
86476 /*!
86477  * @addtogroup LSIO_LPCG_MU13_MCU_Peripheral_Access_Layer LSIO_LPCG_MU13_MCU Peripheral Access Layer
86478  * @{
86479  */
86480 
86481 /** LSIO_LPCG_MU13_MCU - Register Layout Typedef */
86482 typedef struct {
86483   __IO uint32_t LPCG_MU13_MCU_0;                   /**< na, offset: 0x0 */
86484 } LSIO_LPCG_MU13_MCU_Type;
86485 
86486 /* ----------------------------------------------------------------------------
86487    -- LSIO_LPCG_MU13_MCU Register Masks
86488    ---------------------------------------------------------------------------- */
86489 
86490 /*!
86491  * @addtogroup LSIO_LPCG_MU13_MCU_Register_Masks LSIO_LPCG_MU13_MCU Register Masks
86492  * @{
86493  */
86494 
86495 /*! @name LPCG_MU13_MCU_0 - na */
86496 /*! @{ */
86497 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_MASK (0x1U)
86498 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_SHIFT (0U)
86499 /*! LPCG_MU13_MCU_0_reserved_0_0 - reserved
86500  */
86501 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_MASK)
86502 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_MASK (0x2U)
86503 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_SHIFT (1U)
86504 /*! mu13_ipg_clk_mcu_SWEN - Software Enable
86505  *  0b0..Disable SW clock regardless of HWEN
86506  *  0b1..Enable SW clock gating
86507  */
86508 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_MASK)
86509 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_MASK (0x4U)
86510 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_SHIFT (2U)
86511 /*! LPCG_MU13_MCU_0_reserved_2_2 - reserved
86512  */
86513 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_MASK)
86514 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_MASK (0x8U)
86515 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_SHIFT (3U)
86516 /*! mu13_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped
86517  */
86518 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_MASK)
86519 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_MASK (0xFFF0U)
86520 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_SHIFT (4U)
86521 /*! LPCG_MU13_MCU_0_reserved_4_15 - reserved
86522  */
86523 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_MASK)
86524 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
86525 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_SHIFT (16U)
86526 /*! mu13_ipg_clk_s_mcu_HWEN - Hardware Enable
86527  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86528  *  0b1..Enable HW automatic gating
86529  */
86530 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_MASK)
86531 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
86532 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_SHIFT (17U)
86533 /*! mu13_ipg_clk_s_mcu_SWEN - Software Enable
86534  *  0b0..Disable SW clock regardless of HWEN
86535  *  0b1..Enable SW clock gating
86536  */
86537 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_MASK)
86538 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_MASK (0x40000U)
86539 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_SHIFT (18U)
86540 /*! LPCG_MU13_MCU_0_reserved_18_18 - reserved
86541  */
86542 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_MASK)
86543 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_MASK (0x80000U)
86544 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_SHIFT (19U)
86545 /*! mu13_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped
86546  */
86547 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_MASK)
86548 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_MASK (0xFFF00000U)
86549 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_SHIFT (20U)
86550 /*! LPCG_MU13_MCU_0_reserved_20_31 - reserved
86551  */
86552 #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_MASK)
86553 /*! @} */
86554 
86555 
86556 /*!
86557  * @}
86558  */ /* end of group LSIO_LPCG_MU13_MCU_Register_Masks */
86559 
86560 
86561 /* LSIO_LPCG_MU13_MCU - Peripheral instance base addresses */
86562 /** Peripheral LSIO__LPCG_MU13_MCU base address */
86563 #define LSIO__LPCG_MU13_MCU_BASE                 (0x5D680000u)
86564 /** Peripheral LSIO__LPCG_MU13_MCU base pointer */
86565 #define LSIO__LPCG_MU13_MCU                      ((LSIO_LPCG_MU13_MCU_Type *)LSIO__LPCG_MU13_MCU_BASE)
86566 /** Array initializer of LSIO_LPCG_MU13_MCU peripheral base addresses */
86567 #define LSIO_LPCG_MU13_MCU_BASE_ADDRS            { LSIO__LPCG_MU13_MCU_BASE }
86568 /** Array initializer of LSIO_LPCG_MU13_MCU peripheral base pointers */
86569 #define LSIO_LPCG_MU13_MCU_BASE_PTRS             { LSIO__LPCG_MU13_MCU }
86570 
86571 /*!
86572  * @}
86573  */ /* end of group LSIO_LPCG_MU13_MCU_Peripheral_Access_Layer */
86574 
86575 
86576 /* ----------------------------------------------------------------------------
86577    -- LSIO_LPCG_MU5_DSP Peripheral Access Layer
86578    ---------------------------------------------------------------------------- */
86579 
86580 /*!
86581  * @addtogroup LSIO_LPCG_MU5_DSP_Peripheral_Access_Layer LSIO_LPCG_MU5_DSP Peripheral Access Layer
86582  * @{
86583  */
86584 
86585 /** LSIO_LPCG_MU5_DSP - Register Layout Typedef */
86586 typedef struct {
86587   __IO uint32_t LPCG_MU5_DSP_0;                    /**< na, offset: 0x0 */
86588 } LSIO_LPCG_MU5_DSP_Type;
86589 
86590 /* ----------------------------------------------------------------------------
86591    -- LSIO_LPCG_MU5_DSP Register Masks
86592    ---------------------------------------------------------------------------- */
86593 
86594 /*!
86595  * @addtogroup LSIO_LPCG_MU5_DSP_Register_Masks LSIO_LPCG_MU5_DSP Register Masks
86596  * @{
86597  */
86598 
86599 /*! @name LPCG_MU5_DSP_0 - na */
86600 /*! @{ */
86601 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_MASK (0x1U)
86602 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_SHIFT (0U)
86603 /*! LPCG_MU5_DSP_0_reserved_0_0 - reserved
86604  */
86605 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_MASK)
86606 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_MASK (0x2U)
86607 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_SHIFT (1U)
86608 /*! mu5_ipg_clk_dsp_SWEN - Software Enable
86609  *  0b0..Disable SW clock regardless of HWEN
86610  *  0b1..Enable SW clock gating
86611  */
86612 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_MASK)
86613 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_MASK (0x4U)
86614 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_SHIFT (2U)
86615 /*! LPCG_MU5_DSP_0_reserved_2_2 - reserved
86616  */
86617 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_MASK)
86618 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_MASK (0x8U)
86619 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_SHIFT (3U)
86620 /*! mu5_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped
86621  */
86622 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_MASK)
86623 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_MASK (0xFFF0U)
86624 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_SHIFT (4U)
86625 /*! LPCG_MU5_DSP_0_reserved_4_15 - reserved
86626  */
86627 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_MASK)
86628 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
86629 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_SHIFT (16U)
86630 /*! mu5_ipg_clk_s_dsp_HWEN - Hardware Enable
86631  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86632  *  0b1..Enable HW automatic gating
86633  */
86634 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_MASK)
86635 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
86636 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_SHIFT (17U)
86637 /*! mu5_ipg_clk_s_dsp_SWEN - Software Enable
86638  *  0b0..Disable SW clock regardless of HWEN
86639  *  0b1..Enable SW clock gating
86640  */
86641 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_MASK)
86642 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_MASK (0x40000U)
86643 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_SHIFT (18U)
86644 /*! LPCG_MU5_DSP_0_reserved_18_18 - reserved
86645  */
86646 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_MASK)
86647 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_MASK (0x80000U)
86648 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_SHIFT (19U)
86649 /*! mu5_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped
86650  */
86651 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_MASK)
86652 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_MASK (0xFFF00000U)
86653 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_SHIFT (20U)
86654 /*! LPCG_MU5_DSP_0_reserved_20_31 - reserved
86655  */
86656 #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_MASK)
86657 /*! @} */
86658 
86659 
86660 /*!
86661  * @}
86662  */ /* end of group LSIO_LPCG_MU5_DSP_Register_Masks */
86663 
86664 
86665 /* LSIO_LPCG_MU5_DSP - Peripheral instance base addresses */
86666 /** Peripheral LSIO__LPCG_MU5_DSP base address */
86667 #define LSIO__LPCG_MU5_DSP_BASE                  (0x5D690000u)
86668 /** Peripheral LSIO__LPCG_MU5_DSP base pointer */
86669 #define LSIO__LPCG_MU5_DSP                       ((LSIO_LPCG_MU5_DSP_Type *)LSIO__LPCG_MU5_DSP_BASE)
86670 /** Array initializer of LSIO_LPCG_MU5_DSP peripheral base addresses */
86671 #define LSIO_LPCG_MU5_DSP_BASE_ADDRS             { LSIO__LPCG_MU5_DSP_BASE }
86672 /** Array initializer of LSIO_LPCG_MU5_DSP peripheral base pointers */
86673 #define LSIO_LPCG_MU5_DSP_BASE_PTRS              { LSIO__LPCG_MU5_DSP }
86674 
86675 /*!
86676  * @}
86677  */ /* end of group LSIO_LPCG_MU5_DSP_Peripheral_Access_Layer */
86678 
86679 
86680 /* ----------------------------------------------------------------------------
86681    -- LSIO_LPCG_MU5_MCU Peripheral Access Layer
86682    ---------------------------------------------------------------------------- */
86683 
86684 /*!
86685  * @addtogroup LSIO_LPCG_MU5_MCU_Peripheral_Access_Layer LSIO_LPCG_MU5_MCU Peripheral Access Layer
86686  * @{
86687  */
86688 
86689 /** LSIO_LPCG_MU5_MCU - Register Layout Typedef */
86690 typedef struct {
86691   __IO uint32_t LPCG_MU5_MCU_0;                    /**< na, offset: 0x0 */
86692 } LSIO_LPCG_MU5_MCU_Type;
86693 
86694 /* ----------------------------------------------------------------------------
86695    -- LSIO_LPCG_MU5_MCU Register Masks
86696    ---------------------------------------------------------------------------- */
86697 
86698 /*!
86699  * @addtogroup LSIO_LPCG_MU5_MCU_Register_Masks LSIO_LPCG_MU5_MCU Register Masks
86700  * @{
86701  */
86702 
86703 /*! @name LPCG_MU5_MCU_0 - na */
86704 /*! @{ */
86705 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_MASK (0x1U)
86706 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_SHIFT (0U)
86707 /*! LPCG_MU5_MCU_0_reserved_0_0 - reserved
86708  */
86709 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_MASK)
86710 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_MASK (0x2U)
86711 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_SHIFT (1U)
86712 /*! mu5_ipg_clk_mcu_SWEN - Software Enable
86713  *  0b0..Disable SW clock regardless of HWEN
86714  *  0b1..Enable SW clock gating
86715  */
86716 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_MASK)
86717 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_MASK (0x4U)
86718 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_SHIFT (2U)
86719 /*! LPCG_MU5_MCU_0_reserved_2_2 - reserved
86720  */
86721 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_MASK)
86722 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_MASK (0x8U)
86723 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_SHIFT (3U)
86724 /*! mu5_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped
86725  */
86726 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_MASK)
86727 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_MASK (0xFFF0U)
86728 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_SHIFT (4U)
86729 /*! LPCG_MU5_MCU_0_reserved_4_15 - reserved
86730  */
86731 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_MASK)
86732 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
86733 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_SHIFT (16U)
86734 /*! mu5_ipg_clk_s_mcu_HWEN - Hardware Enable
86735  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86736  *  0b1..Enable HW automatic gating
86737  */
86738 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_MASK)
86739 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
86740 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_SHIFT (17U)
86741 /*! mu5_ipg_clk_s_mcu_SWEN - Software Enable
86742  *  0b0..Disable SW clock regardless of HWEN
86743  *  0b1..Enable SW clock gating
86744  */
86745 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_MASK)
86746 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_MASK (0x40000U)
86747 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_SHIFT (18U)
86748 /*! LPCG_MU5_MCU_0_reserved_18_18 - reserved
86749  */
86750 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_MASK)
86751 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_MASK (0x80000U)
86752 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_SHIFT (19U)
86753 /*! mu5_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped
86754  */
86755 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_MASK)
86756 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_MASK (0xFFF00000U)
86757 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_SHIFT (20U)
86758 /*! LPCG_MU5_MCU_0_reserved_20_31 - reserved
86759  */
86760 #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_MASK)
86761 /*! @} */
86762 
86763 
86764 /*!
86765  * @}
86766  */ /* end of group LSIO_LPCG_MU5_MCU_Register_Masks */
86767 
86768 
86769 /* LSIO_LPCG_MU5_MCU - Peripheral instance base addresses */
86770 /** Peripheral LSIO__LPCG_MU5_MCU base address */
86771 #define LSIO__LPCG_MU5_MCU_BASE                  (0x5D600000u)
86772 /** Peripheral LSIO__LPCG_MU5_MCU base pointer */
86773 #define LSIO__LPCG_MU5_MCU                       ((LSIO_LPCG_MU5_MCU_Type *)LSIO__LPCG_MU5_MCU_BASE)
86774 /** Array initializer of LSIO_LPCG_MU5_MCU peripheral base addresses */
86775 #define LSIO_LPCG_MU5_MCU_BASE_ADDRS             { LSIO__LPCG_MU5_MCU_BASE }
86776 /** Array initializer of LSIO_LPCG_MU5_MCU peripheral base pointers */
86777 #define LSIO_LPCG_MU5_MCU_BASE_PTRS              { LSIO__LPCG_MU5_MCU }
86778 
86779 /*!
86780  * @}
86781  */ /* end of group LSIO_LPCG_MU5_MCU_Peripheral_Access_Layer */
86782 
86783 
86784 /* ----------------------------------------------------------------------------
86785    -- LSIO_LPCG_MU6_DSP Peripheral Access Layer
86786    ---------------------------------------------------------------------------- */
86787 
86788 /*!
86789  * @addtogroup LSIO_LPCG_MU6_DSP_Peripheral_Access_Layer LSIO_LPCG_MU6_DSP Peripheral Access Layer
86790  * @{
86791  */
86792 
86793 /** LSIO_LPCG_MU6_DSP - Register Layout Typedef */
86794 typedef struct {
86795   __IO uint32_t LPCG_MU6_DSP_0;                    /**< na, offset: 0x0 */
86796 } LSIO_LPCG_MU6_DSP_Type;
86797 
86798 /* ----------------------------------------------------------------------------
86799    -- LSIO_LPCG_MU6_DSP Register Masks
86800    ---------------------------------------------------------------------------- */
86801 
86802 /*!
86803  * @addtogroup LSIO_LPCG_MU6_DSP_Register_Masks LSIO_LPCG_MU6_DSP Register Masks
86804  * @{
86805  */
86806 
86807 /*! @name LPCG_MU6_DSP_0 - na */
86808 /*! @{ */
86809 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_MASK (0x1U)
86810 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_SHIFT (0U)
86811 /*! LPCG_MU6_DSP_0_reserved_0_0 - reserved
86812  */
86813 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_MASK)
86814 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_MASK (0x2U)
86815 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_SHIFT (1U)
86816 /*! mu6_ipg_clk_dsp_SWEN - Software Enable
86817  *  0b0..Disable SW clock regardless of HWEN
86818  *  0b1..Enable SW clock gating
86819  */
86820 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_MASK)
86821 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_MASK (0x4U)
86822 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_SHIFT (2U)
86823 /*! LPCG_MU6_DSP_0_reserved_2_2 - reserved
86824  */
86825 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_MASK)
86826 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_MASK (0x8U)
86827 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_SHIFT (3U)
86828 /*! mu6_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped
86829  */
86830 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_MASK)
86831 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_MASK (0xFFF0U)
86832 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_SHIFT (4U)
86833 /*! LPCG_MU6_DSP_0_reserved_4_15 - reserved
86834  */
86835 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_MASK)
86836 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
86837 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_SHIFT (16U)
86838 /*! mu6_ipg_clk_s_dsp_HWEN - Hardware Enable
86839  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86840  *  0b1..Enable HW automatic gating
86841  */
86842 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_MASK)
86843 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
86844 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_SHIFT (17U)
86845 /*! mu6_ipg_clk_s_dsp_SWEN - Software Enable
86846  *  0b0..Disable SW clock regardless of HWEN
86847  *  0b1..Enable SW clock gating
86848  */
86849 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_MASK)
86850 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_MASK (0x40000U)
86851 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_SHIFT (18U)
86852 /*! LPCG_MU6_DSP_0_reserved_18_18 - reserved
86853  */
86854 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_MASK)
86855 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_MASK (0x80000U)
86856 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_SHIFT (19U)
86857 /*! mu6_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped
86858  */
86859 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_MASK)
86860 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_MASK (0xFFF00000U)
86861 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_SHIFT (20U)
86862 /*! LPCG_MU6_DSP_0_reserved_20_31 - reserved
86863  */
86864 #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_MASK)
86865 /*! @} */
86866 
86867 
86868 /*!
86869  * @}
86870  */ /* end of group LSIO_LPCG_MU6_DSP_Register_Masks */
86871 
86872 
86873 /* LSIO_LPCG_MU6_DSP - Peripheral instance base addresses */
86874 /** Peripheral LSIO__LPCG_MU6_DSP base address */
86875 #define LSIO__LPCG_MU6_DSP_BASE                  (0x5D6A0000u)
86876 /** Peripheral LSIO__LPCG_MU6_DSP base pointer */
86877 #define LSIO__LPCG_MU6_DSP                       ((LSIO_LPCG_MU6_DSP_Type *)LSIO__LPCG_MU6_DSP_BASE)
86878 /** Array initializer of LSIO_LPCG_MU6_DSP peripheral base addresses */
86879 #define LSIO_LPCG_MU6_DSP_BASE_ADDRS             { LSIO__LPCG_MU6_DSP_BASE }
86880 /** Array initializer of LSIO_LPCG_MU6_DSP peripheral base pointers */
86881 #define LSIO_LPCG_MU6_DSP_BASE_PTRS              { LSIO__LPCG_MU6_DSP }
86882 
86883 /*!
86884  * @}
86885  */ /* end of group LSIO_LPCG_MU6_DSP_Peripheral_Access_Layer */
86886 
86887 
86888 /* ----------------------------------------------------------------------------
86889    -- LSIO_LPCG_MU6_MCU Peripheral Access Layer
86890    ---------------------------------------------------------------------------- */
86891 
86892 /*!
86893  * @addtogroup LSIO_LPCG_MU6_MCU_Peripheral_Access_Layer LSIO_LPCG_MU6_MCU Peripheral Access Layer
86894  * @{
86895  */
86896 
86897 /** LSIO_LPCG_MU6_MCU - Register Layout Typedef */
86898 typedef struct {
86899   __IO uint32_t LPCG_MU6_MCU_0;                    /**< na, offset: 0x0 */
86900 } LSIO_LPCG_MU6_MCU_Type;
86901 
86902 /* ----------------------------------------------------------------------------
86903    -- LSIO_LPCG_MU6_MCU Register Masks
86904    ---------------------------------------------------------------------------- */
86905 
86906 /*!
86907  * @addtogroup LSIO_LPCG_MU6_MCU_Register_Masks LSIO_LPCG_MU6_MCU Register Masks
86908  * @{
86909  */
86910 
86911 /*! @name LPCG_MU6_MCU_0 - na */
86912 /*! @{ */
86913 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_MASK (0x1U)
86914 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_SHIFT (0U)
86915 /*! LPCG_MU6_MCU_0_reserved_0_0 - reserved
86916  */
86917 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_MASK)
86918 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_MASK (0x2U)
86919 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_SHIFT (1U)
86920 /*! mu6_ipg_clk_mcu_SWEN - Software Enable
86921  *  0b0..Disable SW clock regardless of HWEN
86922  *  0b1..Enable SW clock gating
86923  */
86924 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_MASK)
86925 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_MASK (0x4U)
86926 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_SHIFT (2U)
86927 /*! LPCG_MU6_MCU_0_reserved_2_2 - reserved
86928  */
86929 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_MASK)
86930 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_MASK (0x8U)
86931 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_SHIFT (3U)
86932 /*! mu6_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped
86933  */
86934 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_MASK)
86935 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_MASK (0xFFF0U)
86936 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_SHIFT (4U)
86937 /*! LPCG_MU6_MCU_0_reserved_4_15 - reserved
86938  */
86939 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_MASK)
86940 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
86941 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_SHIFT (16U)
86942 /*! mu6_ipg_clk_s_mcu_HWEN - Hardware Enable
86943  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
86944  *  0b1..Enable HW automatic gating
86945  */
86946 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_MASK)
86947 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
86948 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_SHIFT (17U)
86949 /*! mu6_ipg_clk_s_mcu_SWEN - Software Enable
86950  *  0b0..Disable SW clock regardless of HWEN
86951  *  0b1..Enable SW clock gating
86952  */
86953 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_MASK)
86954 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_MASK (0x40000U)
86955 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_SHIFT (18U)
86956 /*! LPCG_MU6_MCU_0_reserved_18_18 - reserved
86957  */
86958 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_MASK)
86959 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_MASK (0x80000U)
86960 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_SHIFT (19U)
86961 /*! mu6_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped
86962  */
86963 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_MASK)
86964 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_MASK (0xFFF00000U)
86965 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_SHIFT (20U)
86966 /*! LPCG_MU6_MCU_0_reserved_20_31 - reserved
86967  */
86968 #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_MASK)
86969 /*! @} */
86970 
86971 
86972 /*!
86973  * @}
86974  */ /* end of group LSIO_LPCG_MU6_MCU_Register_Masks */
86975 
86976 
86977 /* LSIO_LPCG_MU6_MCU - Peripheral instance base addresses */
86978 /** Peripheral LSIO__LPCG_MU6_MCU base address */
86979 #define LSIO__LPCG_MU6_MCU_BASE                  (0x5D610000u)
86980 /** Peripheral LSIO__LPCG_MU6_MCU base pointer */
86981 #define LSIO__LPCG_MU6_MCU                       ((LSIO_LPCG_MU6_MCU_Type *)LSIO__LPCG_MU6_MCU_BASE)
86982 /** Array initializer of LSIO_LPCG_MU6_MCU peripheral base addresses */
86983 #define LSIO_LPCG_MU6_MCU_BASE_ADDRS             { LSIO__LPCG_MU6_MCU_BASE }
86984 /** Array initializer of LSIO_LPCG_MU6_MCU peripheral base pointers */
86985 #define LSIO_LPCG_MU6_MCU_BASE_PTRS              { LSIO__LPCG_MU6_MCU }
86986 
86987 /*!
86988  * @}
86989  */ /* end of group LSIO_LPCG_MU6_MCU_Peripheral_Access_Layer */
86990 
86991 
86992 /* ----------------------------------------------------------------------------
86993    -- LSIO_LPCG_MU7_DSP Peripheral Access Layer
86994    ---------------------------------------------------------------------------- */
86995 
86996 /*!
86997  * @addtogroup LSIO_LPCG_MU7_DSP_Peripheral_Access_Layer LSIO_LPCG_MU7_DSP Peripheral Access Layer
86998  * @{
86999  */
87000 
87001 /** LSIO_LPCG_MU7_DSP - Register Layout Typedef */
87002 typedef struct {
87003   __IO uint32_t LPCG_MU7_DSP_0;                    /**< na, offset: 0x0 */
87004 } LSIO_LPCG_MU7_DSP_Type;
87005 
87006 /* ----------------------------------------------------------------------------
87007    -- LSIO_LPCG_MU7_DSP Register Masks
87008    ---------------------------------------------------------------------------- */
87009 
87010 /*!
87011  * @addtogroup LSIO_LPCG_MU7_DSP_Register_Masks LSIO_LPCG_MU7_DSP Register Masks
87012  * @{
87013  */
87014 
87015 /*! @name LPCG_MU7_DSP_0 - na */
87016 /*! @{ */
87017 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_MASK (0x1U)
87018 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_SHIFT (0U)
87019 /*! LPCG_MU7_DSP_0_reserved_0_0 - reserved
87020  */
87021 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_MASK)
87022 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_MASK (0x2U)
87023 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_SHIFT (1U)
87024 /*! mu7_ipg_clk_dsp_SWEN - Software Enable
87025  *  0b0..Disable SW clock regardless of HWEN
87026  *  0b1..Enable SW clock gating
87027  */
87028 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_MASK)
87029 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_MASK (0x4U)
87030 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_SHIFT (2U)
87031 /*! LPCG_MU7_DSP_0_reserved_2_2 - reserved
87032  */
87033 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_MASK)
87034 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_MASK (0x8U)
87035 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_SHIFT (3U)
87036 /*! mu7_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped
87037  */
87038 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_MASK)
87039 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_MASK (0xFFF0U)
87040 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_SHIFT (4U)
87041 /*! LPCG_MU7_DSP_0_reserved_4_15 - reserved
87042  */
87043 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_MASK)
87044 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
87045 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_SHIFT (16U)
87046 /*! mu7_ipg_clk_s_dsp_HWEN - Hardware Enable
87047  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87048  *  0b1..Enable HW automatic gating
87049  */
87050 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_MASK)
87051 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
87052 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_SHIFT (17U)
87053 /*! mu7_ipg_clk_s_dsp_SWEN - Software Enable
87054  *  0b0..Disable SW clock regardless of HWEN
87055  *  0b1..Enable SW clock gating
87056  */
87057 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_MASK)
87058 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_MASK (0x40000U)
87059 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_SHIFT (18U)
87060 /*! LPCG_MU7_DSP_0_reserved_18_18 - reserved
87061  */
87062 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_MASK)
87063 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_MASK (0x80000U)
87064 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_SHIFT (19U)
87065 /*! mu7_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped
87066  */
87067 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_MASK)
87068 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_MASK (0xFFF00000U)
87069 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_SHIFT (20U)
87070 /*! LPCG_MU7_DSP_0_reserved_20_31 - reserved
87071  */
87072 #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_MASK)
87073 /*! @} */
87074 
87075 
87076 /*!
87077  * @}
87078  */ /* end of group LSIO_LPCG_MU7_DSP_Register_Masks */
87079 
87080 
87081 /* LSIO_LPCG_MU7_DSP - Peripheral instance base addresses */
87082 /** Peripheral LSIO__LPCG_MU7_DSP base address */
87083 #define LSIO__LPCG_MU7_DSP_BASE                  (0x5D6B0000u)
87084 /** Peripheral LSIO__LPCG_MU7_DSP base pointer */
87085 #define LSIO__LPCG_MU7_DSP                       ((LSIO_LPCG_MU7_DSP_Type *)LSIO__LPCG_MU7_DSP_BASE)
87086 /** Array initializer of LSIO_LPCG_MU7_DSP peripheral base addresses */
87087 #define LSIO_LPCG_MU7_DSP_BASE_ADDRS             { LSIO__LPCG_MU7_DSP_BASE }
87088 /** Array initializer of LSIO_LPCG_MU7_DSP peripheral base pointers */
87089 #define LSIO_LPCG_MU7_DSP_BASE_PTRS              { LSIO__LPCG_MU7_DSP }
87090 
87091 /*!
87092  * @}
87093  */ /* end of group LSIO_LPCG_MU7_DSP_Peripheral_Access_Layer */
87094 
87095 
87096 /* ----------------------------------------------------------------------------
87097    -- LSIO_LPCG_MU7_MCU Peripheral Access Layer
87098    ---------------------------------------------------------------------------- */
87099 
87100 /*!
87101  * @addtogroup LSIO_LPCG_MU7_MCU_Peripheral_Access_Layer LSIO_LPCG_MU7_MCU Peripheral Access Layer
87102  * @{
87103  */
87104 
87105 /** LSIO_LPCG_MU7_MCU - Register Layout Typedef */
87106 typedef struct {
87107   __IO uint32_t LPCG_MU7_MCU_0;                    /**< na, offset: 0x0 */
87108 } LSIO_LPCG_MU7_MCU_Type;
87109 
87110 /* ----------------------------------------------------------------------------
87111    -- LSIO_LPCG_MU7_MCU Register Masks
87112    ---------------------------------------------------------------------------- */
87113 
87114 /*!
87115  * @addtogroup LSIO_LPCG_MU7_MCU_Register_Masks LSIO_LPCG_MU7_MCU Register Masks
87116  * @{
87117  */
87118 
87119 /*! @name LPCG_MU7_MCU_0 - na */
87120 /*! @{ */
87121 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_MASK (0x1U)
87122 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_SHIFT (0U)
87123 /*! LPCG_MU7_MCU_0_reserved_0_0 - reserved
87124  */
87125 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_MASK)
87126 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_MASK (0x2U)
87127 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_SHIFT (1U)
87128 /*! mu7_ipg_clk_mcu_SWEN - Software Enable
87129  *  0b0..Disable SW clock regardless of HWEN
87130  *  0b1..Enable SW clock gating
87131  */
87132 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_MASK)
87133 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_MASK (0x4U)
87134 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_SHIFT (2U)
87135 /*! LPCG_MU7_MCU_0_reserved_2_2 - reserved
87136  */
87137 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_MASK)
87138 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_MASK (0x8U)
87139 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_SHIFT (3U)
87140 /*! mu7_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped
87141  */
87142 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_MASK)
87143 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_MASK (0xFFF0U)
87144 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_SHIFT (4U)
87145 /*! LPCG_MU7_MCU_0_reserved_4_15 - reserved
87146  */
87147 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_MASK)
87148 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
87149 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_SHIFT (16U)
87150 /*! mu7_ipg_clk_s_mcu_HWEN - Hardware Enable
87151  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87152  *  0b1..Enable HW automatic gating
87153  */
87154 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_MASK)
87155 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
87156 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_SHIFT (17U)
87157 /*! mu7_ipg_clk_s_mcu_SWEN - Software Enable
87158  *  0b0..Disable SW clock regardless of HWEN
87159  *  0b1..Enable SW clock gating
87160  */
87161 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_MASK)
87162 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_MASK (0x40000U)
87163 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_SHIFT (18U)
87164 /*! LPCG_MU7_MCU_0_reserved_18_18 - reserved
87165  */
87166 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_MASK)
87167 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_MASK (0x80000U)
87168 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_SHIFT (19U)
87169 /*! mu7_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped
87170  */
87171 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_MASK)
87172 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_MASK (0xFFF00000U)
87173 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_SHIFT (20U)
87174 /*! LPCG_MU7_MCU_0_reserved_20_31 - reserved
87175  */
87176 #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_MASK)
87177 /*! @} */
87178 
87179 
87180 /*!
87181  * @}
87182  */ /* end of group LSIO_LPCG_MU7_MCU_Register_Masks */
87183 
87184 
87185 /* LSIO_LPCG_MU7_MCU - Peripheral instance base addresses */
87186 /** Peripheral LSIO__LPCG_MU7_MCU base address */
87187 #define LSIO__LPCG_MU7_MCU_BASE                  (0x5D620000u)
87188 /** Peripheral LSIO__LPCG_MU7_MCU base pointer */
87189 #define LSIO__LPCG_MU7_MCU                       ((LSIO_LPCG_MU7_MCU_Type *)LSIO__LPCG_MU7_MCU_BASE)
87190 /** Array initializer of LSIO_LPCG_MU7_MCU peripheral base addresses */
87191 #define LSIO_LPCG_MU7_MCU_BASE_ADDRS             { LSIO__LPCG_MU7_MCU_BASE }
87192 /** Array initializer of LSIO_LPCG_MU7_MCU peripheral base pointers */
87193 #define LSIO_LPCG_MU7_MCU_BASE_PTRS              { LSIO__LPCG_MU7_MCU }
87194 
87195 /*!
87196  * @}
87197  */ /* end of group LSIO_LPCG_MU7_MCU_Peripheral_Access_Layer */
87198 
87199 
87200 /* ----------------------------------------------------------------------------
87201    -- LSIO_LPCG_MU8_DSP Peripheral Access Layer
87202    ---------------------------------------------------------------------------- */
87203 
87204 /*!
87205  * @addtogroup LSIO_LPCG_MU8_DSP_Peripheral_Access_Layer LSIO_LPCG_MU8_DSP Peripheral Access Layer
87206  * @{
87207  */
87208 
87209 /** LSIO_LPCG_MU8_DSP - Register Layout Typedef */
87210 typedef struct {
87211   __IO uint32_t LPCG_MU8_DSP_0;                    /**< na, offset: 0x0 */
87212 } LSIO_LPCG_MU8_DSP_Type;
87213 
87214 /* ----------------------------------------------------------------------------
87215    -- LSIO_LPCG_MU8_DSP Register Masks
87216    ---------------------------------------------------------------------------- */
87217 
87218 /*!
87219  * @addtogroup LSIO_LPCG_MU8_DSP_Register_Masks LSIO_LPCG_MU8_DSP Register Masks
87220  * @{
87221  */
87222 
87223 /*! @name LPCG_MU8_DSP_0 - na */
87224 /*! @{ */
87225 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_MASK (0x1U)
87226 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_SHIFT (0U)
87227 /*! LPCG_MU8_DSP_0_reserved_0_0 - reserved
87228  */
87229 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_MASK)
87230 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_MASK (0x2U)
87231 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_SHIFT (1U)
87232 /*! mu8_ipg_clk_dsp_SWEN - Software Enable
87233  *  0b0..Disable SW clock regardless of HWEN
87234  *  0b1..Enable SW clock gating
87235  */
87236 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_MASK)
87237 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_MASK (0x4U)
87238 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_SHIFT (2U)
87239 /*! LPCG_MU8_DSP_0_reserved_2_2 - reserved
87240  */
87241 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_MASK)
87242 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_MASK (0x8U)
87243 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_SHIFT (3U)
87244 /*! mu8_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped
87245  */
87246 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_MASK)
87247 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_MASK (0xFFF0U)
87248 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_SHIFT (4U)
87249 /*! LPCG_MU8_DSP_0_reserved_4_15 - reserved
87250  */
87251 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_MASK)
87252 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
87253 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_SHIFT (16U)
87254 /*! mu8_ipg_clk_s_dsp_HWEN - Hardware Enable
87255  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87256  *  0b1..Enable HW automatic gating
87257  */
87258 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_MASK)
87259 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
87260 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_SHIFT (17U)
87261 /*! mu8_ipg_clk_s_dsp_SWEN - Software Enable
87262  *  0b0..Disable SW clock regardless of HWEN
87263  *  0b1..Enable SW clock gating
87264  */
87265 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_MASK)
87266 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_MASK (0x40000U)
87267 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_SHIFT (18U)
87268 /*! LPCG_MU8_DSP_0_reserved_18_18 - reserved
87269  */
87270 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_MASK)
87271 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_MASK (0x80000U)
87272 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_SHIFT (19U)
87273 /*! mu8_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped
87274  */
87275 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_MASK)
87276 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_MASK (0xFFF00000U)
87277 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_SHIFT (20U)
87278 /*! LPCG_MU8_DSP_0_reserved_20_31 - reserved
87279  */
87280 #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_MASK)
87281 /*! @} */
87282 
87283 
87284 /*!
87285  * @}
87286  */ /* end of group LSIO_LPCG_MU8_DSP_Register_Masks */
87287 
87288 
87289 /* LSIO_LPCG_MU8_DSP - Peripheral instance base addresses */
87290 /** Peripheral LSIO__LPCG_MU8_DSP base address */
87291 #define LSIO__LPCG_MU8_DSP_BASE                  (0x5D6C0000u)
87292 /** Peripheral LSIO__LPCG_MU8_DSP base pointer */
87293 #define LSIO__LPCG_MU8_DSP                       ((LSIO_LPCG_MU8_DSP_Type *)LSIO__LPCG_MU8_DSP_BASE)
87294 /** Array initializer of LSIO_LPCG_MU8_DSP peripheral base addresses */
87295 #define LSIO_LPCG_MU8_DSP_BASE_ADDRS             { LSIO__LPCG_MU8_DSP_BASE }
87296 /** Array initializer of LSIO_LPCG_MU8_DSP peripheral base pointers */
87297 #define LSIO_LPCG_MU8_DSP_BASE_PTRS              { LSIO__LPCG_MU8_DSP }
87298 
87299 /*!
87300  * @}
87301  */ /* end of group LSIO_LPCG_MU8_DSP_Peripheral_Access_Layer */
87302 
87303 
87304 /* ----------------------------------------------------------------------------
87305    -- LSIO_LPCG_MU8_MCU Peripheral Access Layer
87306    ---------------------------------------------------------------------------- */
87307 
87308 /*!
87309  * @addtogroup LSIO_LPCG_MU8_MCU_Peripheral_Access_Layer LSIO_LPCG_MU8_MCU Peripheral Access Layer
87310  * @{
87311  */
87312 
87313 /** LSIO_LPCG_MU8_MCU - Register Layout Typedef */
87314 typedef struct {
87315   __IO uint32_t LPCG_MU8_MCU_0;                    /**< na, offset: 0x0 */
87316 } LSIO_LPCG_MU8_MCU_Type;
87317 
87318 /* ----------------------------------------------------------------------------
87319    -- LSIO_LPCG_MU8_MCU Register Masks
87320    ---------------------------------------------------------------------------- */
87321 
87322 /*!
87323  * @addtogroup LSIO_LPCG_MU8_MCU_Register_Masks LSIO_LPCG_MU8_MCU Register Masks
87324  * @{
87325  */
87326 
87327 /*! @name LPCG_MU8_MCU_0 - na */
87328 /*! @{ */
87329 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_MASK (0x1U)
87330 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_SHIFT (0U)
87331 /*! LPCG_MU8_MCU_0_reserved_0_0 - reserved
87332  */
87333 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_MASK)
87334 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_MASK (0x2U)
87335 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_SHIFT (1U)
87336 /*! mu8_ipg_clk_mcu_SWEN - Software Enable
87337  *  0b0..Disable SW clock regardless of HWEN
87338  *  0b1..Enable SW clock gating
87339  */
87340 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_MASK)
87341 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_MASK (0x4U)
87342 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_SHIFT (2U)
87343 /*! LPCG_MU8_MCU_0_reserved_2_2 - reserved
87344  */
87345 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_MASK)
87346 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_MASK (0x8U)
87347 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_SHIFT (3U)
87348 /*! mu8_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped
87349  */
87350 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_MASK)
87351 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_MASK (0xFFF0U)
87352 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_SHIFT (4U)
87353 /*! LPCG_MU8_MCU_0_reserved_4_15 - reserved
87354  */
87355 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_MASK)
87356 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
87357 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_SHIFT (16U)
87358 /*! mu8_ipg_clk_s_mcu_HWEN - Hardware Enable
87359  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87360  *  0b1..Enable HW automatic gating
87361  */
87362 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_MASK)
87363 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
87364 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_SHIFT (17U)
87365 /*! mu8_ipg_clk_s_mcu_SWEN - Software Enable
87366  *  0b0..Disable SW clock regardless of HWEN
87367  *  0b1..Enable SW clock gating
87368  */
87369 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_MASK)
87370 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_MASK (0x40000U)
87371 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_SHIFT (18U)
87372 /*! LPCG_MU8_MCU_0_reserved_18_18 - reserved
87373  */
87374 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_MASK)
87375 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_MASK (0x80000U)
87376 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_SHIFT (19U)
87377 /*! mu8_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped
87378  */
87379 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_MASK)
87380 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_MASK (0xFFF00000U)
87381 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_SHIFT (20U)
87382 /*! LPCG_MU8_MCU_0_reserved_20_31 - reserved
87383  */
87384 #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_MASK)
87385 /*! @} */
87386 
87387 
87388 /*!
87389  * @}
87390  */ /* end of group LSIO_LPCG_MU8_MCU_Register_Masks */
87391 
87392 
87393 /* LSIO_LPCG_MU8_MCU - Peripheral instance base addresses */
87394 /** Peripheral LSIO__LPCG_MU8_MCU base address */
87395 #define LSIO__LPCG_MU8_MCU_BASE                  (0x5D630000u)
87396 /** Peripheral LSIO__LPCG_MU8_MCU base pointer */
87397 #define LSIO__LPCG_MU8_MCU                       ((LSIO_LPCG_MU8_MCU_Type *)LSIO__LPCG_MU8_MCU_BASE)
87398 /** Array initializer of LSIO_LPCG_MU8_MCU peripheral base addresses */
87399 #define LSIO_LPCG_MU8_MCU_BASE_ADDRS             { LSIO__LPCG_MU8_MCU_BASE }
87400 /** Array initializer of LSIO_LPCG_MU8_MCU peripheral base pointers */
87401 #define LSIO_LPCG_MU8_MCU_BASE_PTRS              { LSIO__LPCG_MU8_MCU }
87402 
87403 /*!
87404  * @}
87405  */ /* end of group LSIO_LPCG_MU8_MCU_Peripheral_Access_Layer */
87406 
87407 
87408 /* ----------------------------------------------------------------------------
87409    -- LSIO_LPCG_MU9_DSP Peripheral Access Layer
87410    ---------------------------------------------------------------------------- */
87411 
87412 /*!
87413  * @addtogroup LSIO_LPCG_MU9_DSP_Peripheral_Access_Layer LSIO_LPCG_MU9_DSP Peripheral Access Layer
87414  * @{
87415  */
87416 
87417 /** LSIO_LPCG_MU9_DSP - Register Layout Typedef */
87418 typedef struct {
87419   __IO uint32_t LPCG_MU9_DSP_0;                    /**< na, offset: 0x0 */
87420 } LSIO_LPCG_MU9_DSP_Type;
87421 
87422 /* ----------------------------------------------------------------------------
87423    -- LSIO_LPCG_MU9_DSP Register Masks
87424    ---------------------------------------------------------------------------- */
87425 
87426 /*!
87427  * @addtogroup LSIO_LPCG_MU9_DSP_Register_Masks LSIO_LPCG_MU9_DSP Register Masks
87428  * @{
87429  */
87430 
87431 /*! @name LPCG_MU9_DSP_0 - na */
87432 /*! @{ */
87433 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_MASK (0x1U)
87434 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_SHIFT (0U)
87435 /*! LPCG_MU9_DSP_0_reserved_0_0 - reserved
87436  */
87437 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_MASK)
87438 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_MASK (0x2U)
87439 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_SHIFT (1U)
87440 /*! mu9_ipg_clk_dsp_SWEN - Software Enable
87441  *  0b0..Disable SW clock regardless of HWEN
87442  *  0b1..Enable SW clock gating
87443  */
87444 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_MASK)
87445 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_MASK (0x4U)
87446 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_SHIFT (2U)
87447 /*! LPCG_MU9_DSP_0_reserved_2_2 - reserved
87448  */
87449 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_MASK)
87450 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_MASK (0x8U)
87451 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_SHIFT (3U)
87452 /*! mu9_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped
87453  */
87454 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_MASK)
87455 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_MASK (0xFFF0U)
87456 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_SHIFT (4U)
87457 /*! LPCG_MU9_DSP_0_reserved_4_15 - reserved
87458  */
87459 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_MASK)
87460 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
87461 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_SHIFT (16U)
87462 /*! mu9_ipg_clk_s_dsp_HWEN - Hardware Enable
87463  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87464  *  0b1..Enable HW automatic gating
87465  */
87466 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_MASK)
87467 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
87468 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_SHIFT (17U)
87469 /*! mu9_ipg_clk_s_dsp_SWEN - Software Enable
87470  *  0b0..Disable SW clock regardless of HWEN
87471  *  0b1..Enable SW clock gating
87472  */
87473 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_MASK)
87474 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_MASK (0x40000U)
87475 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_SHIFT (18U)
87476 /*! LPCG_MU9_DSP_0_reserved_18_18 - reserved
87477  */
87478 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_MASK)
87479 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_MASK (0x80000U)
87480 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_SHIFT (19U)
87481 /*! mu9_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped
87482  */
87483 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_MASK)
87484 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_MASK (0xFFF00000U)
87485 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_SHIFT (20U)
87486 /*! LPCG_MU9_DSP_0_reserved_20_31 - reserved
87487  */
87488 #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_MASK)
87489 /*! @} */
87490 
87491 
87492 /*!
87493  * @}
87494  */ /* end of group LSIO_LPCG_MU9_DSP_Register_Masks */
87495 
87496 
87497 /* LSIO_LPCG_MU9_DSP - Peripheral instance base addresses */
87498 /** Peripheral LSIO__LPCG_MU9_DSP base address */
87499 #define LSIO__LPCG_MU9_DSP_BASE                  (0x5D6D0000u)
87500 /** Peripheral LSIO__LPCG_MU9_DSP base pointer */
87501 #define LSIO__LPCG_MU9_DSP                       ((LSIO_LPCG_MU9_DSP_Type *)LSIO__LPCG_MU9_DSP_BASE)
87502 /** Array initializer of LSIO_LPCG_MU9_DSP peripheral base addresses */
87503 #define LSIO_LPCG_MU9_DSP_BASE_ADDRS             { LSIO__LPCG_MU9_DSP_BASE }
87504 /** Array initializer of LSIO_LPCG_MU9_DSP peripheral base pointers */
87505 #define LSIO_LPCG_MU9_DSP_BASE_PTRS              { LSIO__LPCG_MU9_DSP }
87506 
87507 /*!
87508  * @}
87509  */ /* end of group LSIO_LPCG_MU9_DSP_Peripheral_Access_Layer */
87510 
87511 
87512 /* ----------------------------------------------------------------------------
87513    -- LSIO_LPCG_MU9_MCU Peripheral Access Layer
87514    ---------------------------------------------------------------------------- */
87515 
87516 /*!
87517  * @addtogroup LSIO_LPCG_MU9_MCU_Peripheral_Access_Layer LSIO_LPCG_MU9_MCU Peripheral Access Layer
87518  * @{
87519  */
87520 
87521 /** LSIO_LPCG_MU9_MCU - Register Layout Typedef */
87522 typedef struct {
87523   __IO uint32_t LPCG_MU9_MCU_0;                    /**< na, offset: 0x0 */
87524 } LSIO_LPCG_MU9_MCU_Type;
87525 
87526 /* ----------------------------------------------------------------------------
87527    -- LSIO_LPCG_MU9_MCU Register Masks
87528    ---------------------------------------------------------------------------- */
87529 
87530 /*!
87531  * @addtogroup LSIO_LPCG_MU9_MCU_Register_Masks LSIO_LPCG_MU9_MCU Register Masks
87532  * @{
87533  */
87534 
87535 /*! @name LPCG_MU9_MCU_0 - na */
87536 /*! @{ */
87537 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_MASK (0x1U)
87538 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_SHIFT (0U)
87539 /*! LPCG_MU9_MCU_0_reserved_0_0 - reserved
87540  */
87541 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_MASK)
87542 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_MASK (0x2U)
87543 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_SHIFT (1U)
87544 /*! mu9_ipg_clk_mcu_SWEN - Software Enable
87545  *  0b0..Disable SW clock regardless of HWEN
87546  *  0b1..Enable SW clock gating
87547  */
87548 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_MASK)
87549 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_MASK (0x4U)
87550 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_SHIFT (2U)
87551 /*! LPCG_MU9_MCU_0_reserved_2_2 - reserved
87552  */
87553 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_MASK)
87554 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_MASK (0x8U)
87555 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_SHIFT (3U)
87556 /*! mu9_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped
87557  */
87558 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_MASK)
87559 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_MASK (0xFFF0U)
87560 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_SHIFT (4U)
87561 /*! LPCG_MU9_MCU_0_reserved_4_15 - reserved
87562  */
87563 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_MASK)
87564 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
87565 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_SHIFT (16U)
87566 /*! mu9_ipg_clk_s_mcu_HWEN - Hardware Enable
87567  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87568  *  0b1..Enable HW automatic gating
87569  */
87570 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_MASK)
87571 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
87572 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_SHIFT (17U)
87573 /*! mu9_ipg_clk_s_mcu_SWEN - Software Enable
87574  *  0b0..Disable SW clock regardless of HWEN
87575  *  0b1..Enable SW clock gating
87576  */
87577 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_MASK)
87578 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_MASK (0x40000U)
87579 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_SHIFT (18U)
87580 /*! LPCG_MU9_MCU_0_reserved_18_18 - reserved
87581  */
87582 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_MASK)
87583 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_MASK (0x80000U)
87584 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_SHIFT (19U)
87585 /*! mu9_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped
87586  */
87587 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_MASK)
87588 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_MASK (0xFFF00000U)
87589 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_SHIFT (20U)
87590 /*! LPCG_MU9_MCU_0_reserved_20_31 - reserved
87591  */
87592 #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_MASK)
87593 /*! @} */
87594 
87595 
87596 /*!
87597  * @}
87598  */ /* end of group LSIO_LPCG_MU9_MCU_Register_Masks */
87599 
87600 
87601 /* LSIO_LPCG_MU9_MCU - Peripheral instance base addresses */
87602 /** Peripheral LSIO__LPCG_MU9_MCU base address */
87603 #define LSIO__LPCG_MU9_MCU_BASE                  (0x5D640000u)
87604 /** Peripheral LSIO__LPCG_MU9_MCU base pointer */
87605 #define LSIO__LPCG_MU9_MCU                       ((LSIO_LPCG_MU9_MCU_Type *)LSIO__LPCG_MU9_MCU_BASE)
87606 /** Array initializer of LSIO_LPCG_MU9_MCU peripheral base addresses */
87607 #define LSIO_LPCG_MU9_MCU_BASE_ADDRS             { LSIO__LPCG_MU9_MCU_BASE }
87608 /** Array initializer of LSIO_LPCG_MU9_MCU peripheral base pointers */
87609 #define LSIO_LPCG_MU9_MCU_BASE_PTRS              { LSIO__LPCG_MU9_MCU }
87610 
87611 /*!
87612  * @}
87613  */ /* end of group LSIO_LPCG_MU9_MCU_Peripheral_Access_Layer */
87614 
87615 
87616 /* ----------------------------------------------------------------------------
87617    -- LSIO_LPCG_OCRAM Peripheral Access Layer
87618    ---------------------------------------------------------------------------- */
87619 
87620 /*!
87621  * @addtogroup LSIO_LPCG_OCRAM_Peripheral_Access_Layer LSIO_LPCG_OCRAM Peripheral Access Layer
87622  * @{
87623  */
87624 
87625 /** LSIO_LPCG_OCRAM - Register Layout Typedef */
87626 typedef struct {
87627   __IO uint32_t LPCG_OCRAM_0;                      /**< na, offset: 0x0 */
87628 } LSIO_LPCG_OCRAM_Type;
87629 
87630 /* ----------------------------------------------------------------------------
87631    -- LSIO_LPCG_OCRAM Register Masks
87632    ---------------------------------------------------------------------------- */
87633 
87634 /*!
87635  * @addtogroup LSIO_LPCG_OCRAM_Register_Masks LSIO_LPCG_OCRAM Register Masks
87636  * @{
87637  */
87638 
87639 /*! @name LPCG_OCRAM_0 - na */
87640 /*! @{ */
87641 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_MASK (0x1U)
87642 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_SHIFT (0U)
87643 /*! LPCG_OCRAM_0_reserved_0_0 - reserved
87644  */
87645 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_MASK)
87646 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_MASK (0x2U)
87647 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_SHIFT (1U)
87648 /*! ocram_ctrl_clk_SWEN - Software Enable
87649  *  0b0..Disable SW clock regardless of HWEN
87650  *  0b1..Enable SW clock gating
87651  */
87652 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_MASK)
87653 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_MASK (0x4U)
87654 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_SHIFT (2U)
87655 /*! LPCG_OCRAM_0_reserved_2_2 - reserved
87656  */
87657 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_MASK)
87658 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_MASK (0x8U)
87659 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_SHIFT (3U)
87660 /*! ocram_ctrl_clk_STOP - show clock root status, 1 means clock stopped
87661  */
87662 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_MASK)
87663 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_MASK (0x10U)
87664 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_SHIFT (4U)
87665 /*! LPCG_OCRAM_0_reserved_4_4 - reserved
87666  */
87667 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_MASK)
87668 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_MASK (0x20U)
87669 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_SHIFT (5U)
87670 /*! ocram_mem_wrapper_clk_SWEN - Software Enable
87671  *  0b0..Disable SW clock regardless of HWEN
87672  *  0b1..Enable SW clock gating
87673  */
87674 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_MASK)
87675 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_MASK (0x40U)
87676 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_SHIFT (6U)
87677 /*! LPCG_OCRAM_0_reserved_6_6 - reserved
87678  */
87679 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_MASK)
87680 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_MASK (0x80U)
87681 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_SHIFT (7U)
87682 /*! ocram_mem_wrapper_clk_STOP - show clock root status, 1 means clock stopped
87683  */
87684 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_MASK)
87685 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_MASK (0xFFFFFF00U)
87686 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_SHIFT (8U)
87687 /*! LPCG_OCRAM_0_reserved_8_31 - reserved
87688  */
87689 #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_MASK)
87690 /*! @} */
87691 
87692 
87693 /*!
87694  * @}
87695  */ /* end of group LSIO_LPCG_OCRAM_Register_Masks */
87696 
87697 
87698 /* LSIO_LPCG_OCRAM - Peripheral instance base addresses */
87699 /** Peripheral LSIO__LPCG_OCRAM base address */
87700 #define LSIO__LPCG_OCRAM_BASE                    (0x5D590000u)
87701 /** Peripheral LSIO__LPCG_OCRAM base pointer */
87702 #define LSIO__LPCG_OCRAM                         ((LSIO_LPCG_OCRAM_Type *)LSIO__LPCG_OCRAM_BASE)
87703 /** Array initializer of LSIO_LPCG_OCRAM peripheral base addresses */
87704 #define LSIO_LPCG_OCRAM_BASE_ADDRS               { LSIO__LPCG_OCRAM_BASE }
87705 /** Array initializer of LSIO_LPCG_OCRAM peripheral base pointers */
87706 #define LSIO_LPCG_OCRAM_BASE_PTRS                { LSIO__LPCG_OCRAM }
87707 
87708 /*!
87709  * @}
87710  */ /* end of group LSIO_LPCG_OCRAM_Peripheral_Access_Layer */
87711 
87712 
87713 /* ----------------------------------------------------------------------------
87714    -- LSIO_LPCG_PWM0 Peripheral Access Layer
87715    ---------------------------------------------------------------------------- */
87716 
87717 /*!
87718  * @addtogroup LSIO_LPCG_PWM0_Peripheral_Access_Layer LSIO_LPCG_PWM0 Peripheral Access Layer
87719  * @{
87720  */
87721 
87722 /** LSIO_LPCG_PWM0 - Register Layout Typedef */
87723 typedef struct {
87724   __IO uint32_t LPCG_IPS_SYNC_PWM0_0;              /**< na, offset: 0x0 */
87725 } LSIO_LPCG_PWM0_Type;
87726 
87727 /* ----------------------------------------------------------------------------
87728    -- LSIO_LPCG_PWM0 Register Masks
87729    ---------------------------------------------------------------------------- */
87730 
87731 /*!
87732  * @addtogroup LSIO_LPCG_PWM0_Register_Masks LSIO_LPCG_PWM0 Register Masks
87733  * @{
87734  */
87735 
87736 /*! @name LPCG_IPS_SYNC_PWM0_0 - na */
87737 /*! @{ */
87738 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_MASK (0x1U)
87739 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_SHIFT (0U)
87740 /*! pwm0_ipg_clk_HWEN - Hardware Enable
87741  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87742  *  0b1..Enable HW automatic gating
87743  */
87744 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_MASK)
87745 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_MASK (0x2U)
87746 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_SHIFT (1U)
87747 /*! pwm0_ipg_clk_SWEN - Software Enable
87748  *  0b0..Disable SW clock regardless of HWEN
87749  *  0b1..Enable SW clock gating
87750  */
87751 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_MASK)
87752 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_MASK (0x4U)
87753 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_SHIFT (2U)
87754 /*! LPCG_IPS_SYNC_PWM0_0_reserved_2_2 - reserved
87755  */
87756 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_MASK)
87757 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_MASK (0x8U)
87758 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_SHIFT (3U)
87759 /*! pwm0_ipg_clk_STOP - show clock root status, 1 means clock stopped
87760  */
87761 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_MASK)
87762 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_MASK (0x10U)
87763 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_SHIFT (4U)
87764 /*! LPCG_IPS_SYNC_PWM0_0_reserved_4_4 - reserved
87765  */
87766 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_MASK)
87767 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_MASK (0x20U)
87768 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_SHIFT (5U)
87769 /*! pwm0_ipg_clk_highfreq_SWEN - Software Enable
87770  *  0b0..Disable SW clock regardless of HWEN
87771  *  0b1..Enable SW clock gating
87772  */
87773 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_MASK)
87774 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_MASK (0x40U)
87775 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_SHIFT (6U)
87776 /*! LPCG_IPS_SYNC_PWM0_0_reserved_6_6 - reserved
87777  */
87778 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_MASK)
87779 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_MASK (0x80U)
87780 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_SHIFT (7U)
87781 /*! pwm0_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
87782  */
87783 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_MASK)
87784 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_MASK (0x100U)
87785 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_SHIFT (8U)
87786 /*! LPCG_IPS_SYNC_PWM0_0_reserved_8_8 - reserved
87787  */
87788 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_MASK)
87789 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_MASK (0x200U)
87790 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_SHIFT (9U)
87791 /*! ccm_ckil_sync_wrapper5_clk_in_SWEN - Software Enable
87792  *  0b0..Disable SW clock regardless of HWEN
87793  *  0b1..Enable SW clock gating
87794  */
87795 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_MASK)
87796 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_MASK (0x400U)
87797 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_SHIFT (10U)
87798 /*! LPCG_IPS_SYNC_PWM0_0_reserved_10_10 - reserved
87799  */
87800 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_MASK)
87801 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_MASK (0x800U)
87802 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_SHIFT (11U)
87803 /*! ccm_ckil_sync_wrapper5_clk_in_STOP - show clock root status, 1 means clock stopped
87804  */
87805 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_MASK)
87806 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_MASK (0xF000U)
87807 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_SHIFT (12U)
87808 /*! LPCG_IPS_SYNC_PWM0_0_reserved_12_15 - reserved
87809  */
87810 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_MASK)
87811 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_MASK (0x10000U)
87812 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_SHIFT (16U)
87813 /*! pwm0_ipg_clk_s_HWEN - Hardware Enable
87814  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87815  *  0b1..Enable HW automatic gating
87816  */
87817 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_MASK)
87818 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_MASK (0x20000U)
87819 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_SHIFT (17U)
87820 /*! pwm0_ipg_clk_s_SWEN - Software Enable
87821  *  0b0..Disable SW clock regardless of HWEN
87822  *  0b1..Enable SW clock gating
87823  */
87824 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_MASK)
87825 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_MASK (0x40000U)
87826 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_SHIFT (18U)
87827 /*! LPCG_IPS_SYNC_PWM0_0_reserved_18_18 - reserved
87828  */
87829 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_MASK)
87830 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_MASK (0x80000U)
87831 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_SHIFT (19U)
87832 /*! pwm0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
87833  */
87834 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_MASK)
87835 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_MASK (0x100000U)
87836 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_SHIFT (20U)
87837 /*! LPCG_IPS_SYNC_PWM0_0_reserved_20_20 - reserved
87838  */
87839 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_MASK)
87840 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_MASK (0x200000U)
87841 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_SHIFT (21U)
87842 /*! ips_sync_pwm0_ipg_slave_clk_SWEN - Software Enable
87843  *  0b0..Disable SW clock regardless of HWEN
87844  *  0b1..Enable SW clock gating
87845  */
87846 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_MASK)
87847 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_MASK (0x400000U)
87848 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_SHIFT (22U)
87849 /*! LPCG_IPS_SYNC_PWM0_0_reserved_22_22 - reserved
87850  */
87851 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_MASK)
87852 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_MASK (0x800000U)
87853 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_SHIFT (23U)
87854 /*! ips_sync_pwm0_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
87855  */
87856 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_MASK)
87857 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_MASK (0x1000000U)
87858 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_SHIFT (24U)
87859 /*! ips_sync_pwm0_ipg_master_clk_HWEN - Hardware Enable
87860  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87861  *  0b1..Enable HW automatic gating
87862  */
87863 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_MASK)
87864 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_MASK (0x2000000U)
87865 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_SHIFT (25U)
87866 /*! ips_sync_pwm0_ipg_master_clk_SWEN - Software Enable
87867  *  0b0..Disable SW clock regardless of HWEN
87868  *  0b1..Enable SW clock gating
87869  */
87870 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_MASK)
87871 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_MASK (0x4000000U)
87872 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_SHIFT (26U)
87873 /*! LPCG_IPS_SYNC_PWM0_0_reserved_26_26 - reserved
87874  */
87875 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_MASK)
87876 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_MASK (0x8000000U)
87877 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_SHIFT (27U)
87878 /*! ips_sync_pwm0_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
87879  */
87880 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_MASK)
87881 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_MASK (0xF0000000U)
87882 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_SHIFT (28U)
87883 /*! LPCG_IPS_SYNC_PWM0_0_reserved_28_31 - reserved
87884  */
87885 #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_MASK)
87886 /*! @} */
87887 
87888 
87889 /*!
87890  * @}
87891  */ /* end of group LSIO_LPCG_PWM0_Register_Masks */
87892 
87893 
87894 /* LSIO_LPCG_PWM0 - Peripheral instance base addresses */
87895 /** Peripheral LSIO__LPCG_PWM0 base address */
87896 #define LSIO__LPCG_PWM0_BASE                     (0x5D400000u)
87897 /** Peripheral LSIO__LPCG_PWM0 base pointer */
87898 #define LSIO__LPCG_PWM0                          ((LSIO_LPCG_PWM0_Type *)LSIO__LPCG_PWM0_BASE)
87899 /** Array initializer of LSIO_LPCG_PWM0 peripheral base addresses */
87900 #define LSIO_LPCG_PWM0_BASE_ADDRS                { LSIO__LPCG_PWM0_BASE }
87901 /** Array initializer of LSIO_LPCG_PWM0 peripheral base pointers */
87902 #define LSIO_LPCG_PWM0_BASE_PTRS                 { LSIO__LPCG_PWM0 }
87903 
87904 /*!
87905  * @}
87906  */ /* end of group LSIO_LPCG_PWM0_Peripheral_Access_Layer */
87907 
87908 
87909 /* ----------------------------------------------------------------------------
87910    -- LSIO_LPCG_PWM1 Peripheral Access Layer
87911    ---------------------------------------------------------------------------- */
87912 
87913 /*!
87914  * @addtogroup LSIO_LPCG_PWM1_Peripheral_Access_Layer LSIO_LPCG_PWM1 Peripheral Access Layer
87915  * @{
87916  */
87917 
87918 /** LSIO_LPCG_PWM1 - Register Layout Typedef */
87919 typedef struct {
87920   __IO uint32_t LPCG_IPS_SYNC_PWM1_0;              /**< na, offset: 0x0 */
87921 } LSIO_LPCG_PWM1_Type;
87922 
87923 /* ----------------------------------------------------------------------------
87924    -- LSIO_LPCG_PWM1 Register Masks
87925    ---------------------------------------------------------------------------- */
87926 
87927 /*!
87928  * @addtogroup LSIO_LPCG_PWM1_Register_Masks LSIO_LPCG_PWM1 Register Masks
87929  * @{
87930  */
87931 
87932 /*! @name LPCG_IPS_SYNC_PWM1_0 - na */
87933 /*! @{ */
87934 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_MASK (0x1U)
87935 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_SHIFT (0U)
87936 /*! pwm1_ipg_clk_HWEN - Hardware Enable
87937  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
87938  *  0b1..Enable HW automatic gating
87939  */
87940 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_MASK)
87941 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_MASK (0x2U)
87942 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_SHIFT (1U)
87943 /*! pwm1_ipg_clk_SWEN - Software Enable
87944  *  0b0..Disable SW clock regardless of HWEN
87945  *  0b1..Enable SW clock gating
87946  */
87947 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_MASK)
87948 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_MASK (0x4U)
87949 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_SHIFT (2U)
87950 /*! LPCG_IPS_SYNC_PWM1_0_reserved_2_2 - reserved
87951  */
87952 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_MASK)
87953 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_MASK (0x8U)
87954 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_SHIFT (3U)
87955 /*! pwm1_ipg_clk_STOP - show clock root status, 1 means clock stopped
87956  */
87957 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_MASK)
87958 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_MASK (0x10U)
87959 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_SHIFT (4U)
87960 /*! LPCG_IPS_SYNC_PWM1_0_reserved_4_4 - reserved
87961  */
87962 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_MASK)
87963 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_MASK (0x20U)
87964 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_SHIFT (5U)
87965 /*! pwm1_ipg_clk_highfreq_SWEN - Software Enable
87966  *  0b0..Disable SW clock regardless of HWEN
87967  *  0b1..Enable SW clock gating
87968  */
87969 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_MASK)
87970 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_MASK (0x40U)
87971 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_SHIFT (6U)
87972 /*! LPCG_IPS_SYNC_PWM1_0_reserved_6_6 - reserved
87973  */
87974 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_MASK)
87975 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_MASK (0x80U)
87976 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_SHIFT (7U)
87977 /*! pwm1_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
87978  */
87979 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_MASK)
87980 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_MASK (0x100U)
87981 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_SHIFT (8U)
87982 /*! LPCG_IPS_SYNC_PWM1_0_reserved_8_8 - reserved
87983  */
87984 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_MASK)
87985 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_MASK (0x200U)
87986 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_SHIFT (9U)
87987 /*! ccm_ckil_sync_wrapper6_clk_in_SWEN - Software Enable
87988  *  0b0..Disable SW clock regardless of HWEN
87989  *  0b1..Enable SW clock gating
87990  */
87991 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_MASK)
87992 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_MASK (0x400U)
87993 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_SHIFT (10U)
87994 /*! LPCG_IPS_SYNC_PWM1_0_reserved_10_10 - reserved
87995  */
87996 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_MASK)
87997 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_MASK (0x800U)
87998 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_SHIFT (11U)
87999 /*! ccm_ckil_sync_wrapper6_clk_in_STOP - show clock root status, 1 means clock stopped
88000  */
88001 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_MASK)
88002 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_MASK (0xF000U)
88003 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_SHIFT (12U)
88004 /*! LPCG_IPS_SYNC_PWM1_0_reserved_12_15 - reserved
88005  */
88006 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_MASK)
88007 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_MASK (0x10000U)
88008 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_SHIFT (16U)
88009 /*! pwm1_ipg_clk_s_HWEN - Hardware Enable
88010  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88011  *  0b1..Enable HW automatic gating
88012  */
88013 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_MASK)
88014 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_MASK (0x20000U)
88015 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_SHIFT (17U)
88016 /*! pwm1_ipg_clk_s_SWEN - Software Enable
88017  *  0b0..Disable SW clock regardless of HWEN
88018  *  0b1..Enable SW clock gating
88019  */
88020 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_MASK)
88021 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_MASK (0x40000U)
88022 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_SHIFT (18U)
88023 /*! LPCG_IPS_SYNC_PWM1_0_reserved_18_18 - reserved
88024  */
88025 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_MASK)
88026 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_MASK (0x80000U)
88027 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_SHIFT (19U)
88028 /*! pwm1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
88029  */
88030 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_MASK)
88031 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_MASK (0x100000U)
88032 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_SHIFT (20U)
88033 /*! LPCG_IPS_SYNC_PWM1_0_reserved_20_20 - reserved
88034  */
88035 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_MASK)
88036 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_MASK (0x200000U)
88037 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_SHIFT (21U)
88038 /*! ips_sync_pwm1_ipg_slave_clk_SWEN - Software Enable
88039  *  0b0..Disable SW clock regardless of HWEN
88040  *  0b1..Enable SW clock gating
88041  */
88042 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_MASK)
88043 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_MASK (0x400000U)
88044 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_SHIFT (22U)
88045 /*! LPCG_IPS_SYNC_PWM1_0_reserved_22_22 - reserved
88046  */
88047 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_MASK)
88048 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_MASK (0x800000U)
88049 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_SHIFT (23U)
88050 /*! ips_sync_pwm1_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
88051  */
88052 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_MASK)
88053 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_MASK (0x1000000U)
88054 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_SHIFT (24U)
88055 /*! ips_sync_pwm1_ipg_master_clk_HWEN - Hardware Enable
88056  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88057  *  0b1..Enable HW automatic gating
88058  */
88059 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_MASK)
88060 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_MASK (0x2000000U)
88061 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_SHIFT (25U)
88062 /*! ips_sync_pwm1_ipg_master_clk_SWEN - Software Enable
88063  *  0b0..Disable SW clock regardless of HWEN
88064  *  0b1..Enable SW clock gating
88065  */
88066 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_MASK)
88067 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_MASK (0x4000000U)
88068 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_SHIFT (26U)
88069 /*! LPCG_IPS_SYNC_PWM1_0_reserved_26_26 - reserved
88070  */
88071 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_MASK)
88072 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_MASK (0x8000000U)
88073 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_SHIFT (27U)
88074 /*! ips_sync_pwm1_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
88075  */
88076 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_MASK)
88077 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_MASK (0xF0000000U)
88078 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_SHIFT (28U)
88079 /*! LPCG_IPS_SYNC_PWM1_0_reserved_28_31 - reserved
88080  */
88081 #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_MASK)
88082 /*! @} */
88083 
88084 
88085 /*!
88086  * @}
88087  */ /* end of group LSIO_LPCG_PWM1_Register_Masks */
88088 
88089 
88090 /* LSIO_LPCG_PWM1 - Peripheral instance base addresses */
88091 /** Peripheral LSIO__LPCG_PWM1 base address */
88092 #define LSIO__LPCG_PWM1_BASE                     (0x5D410000u)
88093 /** Peripheral LSIO__LPCG_PWM1 base pointer */
88094 #define LSIO__LPCG_PWM1                          ((LSIO_LPCG_PWM1_Type *)LSIO__LPCG_PWM1_BASE)
88095 /** Array initializer of LSIO_LPCG_PWM1 peripheral base addresses */
88096 #define LSIO_LPCG_PWM1_BASE_ADDRS                { LSIO__LPCG_PWM1_BASE }
88097 /** Array initializer of LSIO_LPCG_PWM1 peripheral base pointers */
88098 #define LSIO_LPCG_PWM1_BASE_PTRS                 { LSIO__LPCG_PWM1 }
88099 
88100 /*!
88101  * @}
88102  */ /* end of group LSIO_LPCG_PWM1_Peripheral_Access_Layer */
88103 
88104 
88105 /* ----------------------------------------------------------------------------
88106    -- LSIO_LPCG_PWM2 Peripheral Access Layer
88107    ---------------------------------------------------------------------------- */
88108 
88109 /*!
88110  * @addtogroup LSIO_LPCG_PWM2_Peripheral_Access_Layer LSIO_LPCG_PWM2 Peripheral Access Layer
88111  * @{
88112  */
88113 
88114 /** LSIO_LPCG_PWM2 - Register Layout Typedef */
88115 typedef struct {
88116   __IO uint32_t LPCG_IPS_SYNC_PWM2_0;              /**< na, offset: 0x0 */
88117 } LSIO_LPCG_PWM2_Type;
88118 
88119 /* ----------------------------------------------------------------------------
88120    -- LSIO_LPCG_PWM2 Register Masks
88121    ---------------------------------------------------------------------------- */
88122 
88123 /*!
88124  * @addtogroup LSIO_LPCG_PWM2_Register_Masks LSIO_LPCG_PWM2 Register Masks
88125  * @{
88126  */
88127 
88128 /*! @name LPCG_IPS_SYNC_PWM2_0 - na */
88129 /*! @{ */
88130 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_MASK (0x1U)
88131 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_SHIFT (0U)
88132 /*! pwm2_ipg_clk_HWEN - Hardware Enable
88133  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88134  *  0b1..Enable HW automatic gating
88135  */
88136 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_MASK)
88137 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_MASK (0x2U)
88138 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_SHIFT (1U)
88139 /*! pwm2_ipg_clk_SWEN - Software Enable
88140  *  0b0..Disable SW clock regardless of HWEN
88141  *  0b1..Enable SW clock gating
88142  */
88143 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_MASK)
88144 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_MASK (0x4U)
88145 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_SHIFT (2U)
88146 /*! LPCG_IPS_SYNC_PWM2_0_reserved_2_2 - reserved
88147  */
88148 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_MASK)
88149 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_MASK (0x8U)
88150 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_SHIFT (3U)
88151 /*! pwm2_ipg_clk_STOP - show clock root status, 1 means clock stopped
88152  */
88153 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_MASK)
88154 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_MASK (0x10U)
88155 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_SHIFT (4U)
88156 /*! LPCG_IPS_SYNC_PWM2_0_reserved_4_4 - reserved
88157  */
88158 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_MASK)
88159 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_MASK (0x20U)
88160 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_SHIFT (5U)
88161 /*! pwm2_ipg_clk_highfreq_SWEN - Software Enable
88162  *  0b0..Disable SW clock regardless of HWEN
88163  *  0b1..Enable SW clock gating
88164  */
88165 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_MASK)
88166 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_MASK (0x40U)
88167 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_SHIFT (6U)
88168 /*! LPCG_IPS_SYNC_PWM2_0_reserved_6_6 - reserved
88169  */
88170 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_MASK)
88171 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_MASK (0x80U)
88172 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_SHIFT (7U)
88173 /*! pwm2_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
88174  */
88175 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_MASK)
88176 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_MASK (0x100U)
88177 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_SHIFT (8U)
88178 /*! LPCG_IPS_SYNC_PWM2_0_reserved_8_8 - reserved
88179  */
88180 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_MASK)
88181 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_MASK (0x200U)
88182 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_SHIFT (9U)
88183 /*! ccm_ckil_sync_wrapper7_clk_in_SWEN - Software Enable
88184  *  0b0..Disable SW clock regardless of HWEN
88185  *  0b1..Enable SW clock gating
88186  */
88187 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_MASK)
88188 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_MASK (0x400U)
88189 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_SHIFT (10U)
88190 /*! LPCG_IPS_SYNC_PWM2_0_reserved_10_10 - reserved
88191  */
88192 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_MASK)
88193 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_MASK (0x800U)
88194 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_SHIFT (11U)
88195 /*! ccm_ckil_sync_wrapper7_clk_in_STOP - show clock root status, 1 means clock stopped
88196  */
88197 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_MASK)
88198 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_MASK (0xF000U)
88199 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_SHIFT (12U)
88200 /*! LPCG_IPS_SYNC_PWM2_0_reserved_12_15 - reserved
88201  */
88202 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_MASK)
88203 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_MASK (0x10000U)
88204 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_SHIFT (16U)
88205 /*! pwm2_ipg_clk_s_HWEN - Hardware Enable
88206  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88207  *  0b1..Enable HW automatic gating
88208  */
88209 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_MASK)
88210 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_MASK (0x20000U)
88211 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_SHIFT (17U)
88212 /*! pwm2_ipg_clk_s_SWEN - Software Enable
88213  *  0b0..Disable SW clock regardless of HWEN
88214  *  0b1..Enable SW clock gating
88215  */
88216 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_MASK)
88217 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_MASK (0x40000U)
88218 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_SHIFT (18U)
88219 /*! LPCG_IPS_SYNC_PWM2_0_reserved_18_18 - reserved
88220  */
88221 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_MASK)
88222 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_MASK (0x80000U)
88223 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_SHIFT (19U)
88224 /*! pwm2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
88225  */
88226 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_MASK)
88227 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_MASK (0x100000U)
88228 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_SHIFT (20U)
88229 /*! LPCG_IPS_SYNC_PWM2_0_reserved_20_20 - reserved
88230  */
88231 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_MASK)
88232 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_MASK (0x200000U)
88233 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_SHIFT (21U)
88234 /*! ips_sync_pwm2_ipg_slave_clk_SWEN - Software Enable
88235  *  0b0..Disable SW clock regardless of HWEN
88236  *  0b1..Enable SW clock gating
88237  */
88238 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_MASK)
88239 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_MASK (0x400000U)
88240 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_SHIFT (22U)
88241 /*! LPCG_IPS_SYNC_PWM2_0_reserved_22_22 - reserved
88242  */
88243 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_MASK)
88244 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_MASK (0x800000U)
88245 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_SHIFT (23U)
88246 /*! ips_sync_pwm2_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
88247  */
88248 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_MASK)
88249 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_MASK (0x1000000U)
88250 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_SHIFT (24U)
88251 /*! ips_sync_pwm2_ipg_master_clk_HWEN - Hardware Enable
88252  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88253  *  0b1..Enable HW automatic gating
88254  */
88255 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_MASK)
88256 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_MASK (0x2000000U)
88257 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_SHIFT (25U)
88258 /*! ips_sync_pwm2_ipg_master_clk_SWEN - Software Enable
88259  *  0b0..Disable SW clock regardless of HWEN
88260  *  0b1..Enable SW clock gating
88261  */
88262 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_MASK)
88263 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_MASK (0x4000000U)
88264 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_SHIFT (26U)
88265 /*! LPCG_IPS_SYNC_PWM2_0_reserved_26_26 - reserved
88266  */
88267 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_MASK)
88268 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_MASK (0x8000000U)
88269 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_SHIFT (27U)
88270 /*! ips_sync_pwm2_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
88271  */
88272 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_MASK)
88273 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_MASK (0xF0000000U)
88274 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_SHIFT (28U)
88275 /*! LPCG_IPS_SYNC_PWM2_0_reserved_28_31 - reserved
88276  */
88277 #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_MASK)
88278 /*! @} */
88279 
88280 
88281 /*!
88282  * @}
88283  */ /* end of group LSIO_LPCG_PWM2_Register_Masks */
88284 
88285 
88286 /* LSIO_LPCG_PWM2 - Peripheral instance base addresses */
88287 /** Peripheral LSIO__LPCG_PWM2 base address */
88288 #define LSIO__LPCG_PWM2_BASE                     (0x5D420000u)
88289 /** Peripheral LSIO__LPCG_PWM2 base pointer */
88290 #define LSIO__LPCG_PWM2                          ((LSIO_LPCG_PWM2_Type *)LSIO__LPCG_PWM2_BASE)
88291 /** Array initializer of LSIO_LPCG_PWM2 peripheral base addresses */
88292 #define LSIO_LPCG_PWM2_BASE_ADDRS                { LSIO__LPCG_PWM2_BASE }
88293 /** Array initializer of LSIO_LPCG_PWM2 peripheral base pointers */
88294 #define LSIO_LPCG_PWM2_BASE_PTRS                 { LSIO__LPCG_PWM2 }
88295 
88296 /*!
88297  * @}
88298  */ /* end of group LSIO_LPCG_PWM2_Peripheral_Access_Layer */
88299 
88300 
88301 /* ----------------------------------------------------------------------------
88302    -- LSIO_LPCG_PWM3 Peripheral Access Layer
88303    ---------------------------------------------------------------------------- */
88304 
88305 /*!
88306  * @addtogroup LSIO_LPCG_PWM3_Peripheral_Access_Layer LSIO_LPCG_PWM3 Peripheral Access Layer
88307  * @{
88308  */
88309 
88310 /** LSIO_LPCG_PWM3 - Register Layout Typedef */
88311 typedef struct {
88312   __IO uint32_t LPCG_IPS_SYNC_PWM3_0;              /**< na, offset: 0x0 */
88313 } LSIO_LPCG_PWM3_Type;
88314 
88315 /* ----------------------------------------------------------------------------
88316    -- LSIO_LPCG_PWM3 Register Masks
88317    ---------------------------------------------------------------------------- */
88318 
88319 /*!
88320  * @addtogroup LSIO_LPCG_PWM3_Register_Masks LSIO_LPCG_PWM3 Register Masks
88321  * @{
88322  */
88323 
88324 /*! @name LPCG_IPS_SYNC_PWM3_0 - na */
88325 /*! @{ */
88326 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_MASK (0x1U)
88327 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_SHIFT (0U)
88328 /*! pwm3_ipg_clk_HWEN - Hardware Enable
88329  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88330  *  0b1..Enable HW automatic gating
88331  */
88332 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_MASK)
88333 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_MASK (0x2U)
88334 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_SHIFT (1U)
88335 /*! pwm3_ipg_clk_SWEN - Software Enable
88336  *  0b0..Disable SW clock regardless of HWEN
88337  *  0b1..Enable SW clock gating
88338  */
88339 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_MASK)
88340 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_MASK (0x4U)
88341 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_SHIFT (2U)
88342 /*! LPCG_IPS_SYNC_PWM3_0_reserved_2_2 - reserved
88343  */
88344 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_MASK)
88345 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_MASK (0x8U)
88346 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_SHIFT (3U)
88347 /*! pwm3_ipg_clk_STOP - show clock root status, 1 means clock stopped
88348  */
88349 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_MASK)
88350 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_MASK (0x10U)
88351 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_SHIFT (4U)
88352 /*! LPCG_IPS_SYNC_PWM3_0_reserved_4_4 - reserved
88353  */
88354 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_MASK)
88355 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_MASK (0x20U)
88356 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_SHIFT (5U)
88357 /*! pwm3_ipg_clk_highfreq_SWEN - Software Enable
88358  *  0b0..Disable SW clock regardless of HWEN
88359  *  0b1..Enable SW clock gating
88360  */
88361 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_MASK)
88362 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_MASK (0x40U)
88363 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_SHIFT (6U)
88364 /*! LPCG_IPS_SYNC_PWM3_0_reserved_6_6 - reserved
88365  */
88366 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_MASK)
88367 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_MASK (0x80U)
88368 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_SHIFT (7U)
88369 /*! pwm3_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
88370  */
88371 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_MASK)
88372 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_MASK (0x100U)
88373 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_SHIFT (8U)
88374 /*! LPCG_IPS_SYNC_PWM3_0_reserved_8_8 - reserved
88375  */
88376 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_MASK)
88377 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_MASK (0x200U)
88378 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_SHIFT (9U)
88379 /*! ccm_ckil_sync_wrapper8_clk_in_SWEN - Software Enable
88380  *  0b0..Disable SW clock regardless of HWEN
88381  *  0b1..Enable SW clock gating
88382  */
88383 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_MASK)
88384 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_MASK (0x400U)
88385 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_SHIFT (10U)
88386 /*! LPCG_IPS_SYNC_PWM3_0_reserved_10_10 - reserved
88387  */
88388 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_MASK)
88389 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_MASK (0x800U)
88390 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_SHIFT (11U)
88391 /*! ccm_ckil_sync_wrapper8_clk_in_STOP - show clock root status, 1 means clock stopped
88392  */
88393 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_MASK)
88394 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_MASK (0xF000U)
88395 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_SHIFT (12U)
88396 /*! LPCG_IPS_SYNC_PWM3_0_reserved_12_15 - reserved
88397  */
88398 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_MASK)
88399 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_MASK (0x10000U)
88400 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_SHIFT (16U)
88401 /*! pwm3_ipg_clk_s_HWEN - Hardware Enable
88402  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88403  *  0b1..Enable HW automatic gating
88404  */
88405 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_MASK)
88406 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_MASK (0x20000U)
88407 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_SHIFT (17U)
88408 /*! pwm3_ipg_clk_s_SWEN - Software Enable
88409  *  0b0..Disable SW clock regardless of HWEN
88410  *  0b1..Enable SW clock gating
88411  */
88412 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_MASK)
88413 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_MASK (0x40000U)
88414 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_SHIFT (18U)
88415 /*! LPCG_IPS_SYNC_PWM3_0_reserved_18_18 - reserved
88416  */
88417 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_MASK)
88418 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_MASK (0x80000U)
88419 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_SHIFT (19U)
88420 /*! pwm3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
88421  */
88422 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_MASK)
88423 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_MASK (0x100000U)
88424 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_SHIFT (20U)
88425 /*! LPCG_IPS_SYNC_PWM3_0_reserved_20_20 - reserved
88426  */
88427 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_MASK)
88428 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_MASK (0x200000U)
88429 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_SHIFT (21U)
88430 /*! ips_sync_pwm3_ipg_slave_clk_SWEN - Software Enable
88431  *  0b0..Disable SW clock regardless of HWEN
88432  *  0b1..Enable SW clock gating
88433  */
88434 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_MASK)
88435 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_MASK (0x400000U)
88436 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_SHIFT (22U)
88437 /*! LPCG_IPS_SYNC_PWM3_0_reserved_22_22 - reserved
88438  */
88439 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_MASK)
88440 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_MASK (0x800000U)
88441 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_SHIFT (23U)
88442 /*! ips_sync_pwm3_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
88443  */
88444 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_MASK)
88445 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_MASK (0x1000000U)
88446 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_SHIFT (24U)
88447 /*! ips_sync_pwm3_ipg_master_clk_HWEN - Hardware Enable
88448  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88449  *  0b1..Enable HW automatic gating
88450  */
88451 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_MASK)
88452 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_MASK (0x2000000U)
88453 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_SHIFT (25U)
88454 /*! ips_sync_pwm3_ipg_master_clk_SWEN - Software Enable
88455  *  0b0..Disable SW clock regardless of HWEN
88456  *  0b1..Enable SW clock gating
88457  */
88458 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_MASK)
88459 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_MASK (0x4000000U)
88460 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_SHIFT (26U)
88461 /*! LPCG_IPS_SYNC_PWM3_0_reserved_26_26 - reserved
88462  */
88463 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_MASK)
88464 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_MASK (0x8000000U)
88465 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_SHIFT (27U)
88466 /*! ips_sync_pwm3_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
88467  */
88468 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_MASK)
88469 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_MASK (0xF0000000U)
88470 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_SHIFT (28U)
88471 /*! LPCG_IPS_SYNC_PWM3_0_reserved_28_31 - reserved
88472  */
88473 #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_MASK)
88474 /*! @} */
88475 
88476 
88477 /*!
88478  * @}
88479  */ /* end of group LSIO_LPCG_PWM3_Register_Masks */
88480 
88481 
88482 /* LSIO_LPCG_PWM3 - Peripheral instance base addresses */
88483 /** Peripheral LSIO__LPCG_PWM3 base address */
88484 #define LSIO__LPCG_PWM3_BASE                     (0x5D430000u)
88485 /** Peripheral LSIO__LPCG_PWM3 base pointer */
88486 #define LSIO__LPCG_PWM3                          ((LSIO_LPCG_PWM3_Type *)LSIO__LPCG_PWM3_BASE)
88487 /** Array initializer of LSIO_LPCG_PWM3 peripheral base addresses */
88488 #define LSIO_LPCG_PWM3_BASE_ADDRS                { LSIO__LPCG_PWM3_BASE }
88489 /** Array initializer of LSIO_LPCG_PWM3 peripheral base pointers */
88490 #define LSIO_LPCG_PWM3_BASE_PTRS                 { LSIO__LPCG_PWM3 }
88491 
88492 /*!
88493  * @}
88494  */ /* end of group LSIO_LPCG_PWM3_Peripheral_Access_Layer */
88495 
88496 
88497 /* ----------------------------------------------------------------------------
88498    -- LSIO_LPCG_PWM4 Peripheral Access Layer
88499    ---------------------------------------------------------------------------- */
88500 
88501 /*!
88502  * @addtogroup LSIO_LPCG_PWM4_Peripheral_Access_Layer LSIO_LPCG_PWM4 Peripheral Access Layer
88503  * @{
88504  */
88505 
88506 /** LSIO_LPCG_PWM4 - Register Layout Typedef */
88507 typedef struct {
88508   __IO uint32_t LPCG_IPS_SYNC_PWM4_0;              /**< na, offset: 0x0 */
88509 } LSIO_LPCG_PWM4_Type;
88510 
88511 /* ----------------------------------------------------------------------------
88512    -- LSIO_LPCG_PWM4 Register Masks
88513    ---------------------------------------------------------------------------- */
88514 
88515 /*!
88516  * @addtogroup LSIO_LPCG_PWM4_Register_Masks LSIO_LPCG_PWM4 Register Masks
88517  * @{
88518  */
88519 
88520 /*! @name LPCG_IPS_SYNC_PWM4_0 - na */
88521 /*! @{ */
88522 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_MASK (0x1U)
88523 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_SHIFT (0U)
88524 /*! pwm4_ipg_clk_HWEN - Hardware Enable
88525  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88526  *  0b1..Enable HW automatic gating
88527  */
88528 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_MASK)
88529 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_MASK (0x2U)
88530 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_SHIFT (1U)
88531 /*! pwm4_ipg_clk_SWEN - Software Enable
88532  *  0b0..Disable SW clock regardless of HWEN
88533  *  0b1..Enable SW clock gating
88534  */
88535 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_MASK)
88536 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_MASK (0x4U)
88537 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_SHIFT (2U)
88538 /*! LPCG_IPS_SYNC_PWM4_0_reserved_2_2 - reserved
88539  */
88540 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_MASK)
88541 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_MASK (0x8U)
88542 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_SHIFT (3U)
88543 /*! pwm4_ipg_clk_STOP - show clock root status, 1 means clock stopped
88544  */
88545 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_MASK)
88546 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_MASK (0x10U)
88547 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_SHIFT (4U)
88548 /*! LPCG_IPS_SYNC_PWM4_0_reserved_4_4 - reserved
88549  */
88550 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_MASK)
88551 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_MASK (0x20U)
88552 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_SHIFT (5U)
88553 /*! pwm4_ipg_clk_highfreq_SWEN - Software Enable
88554  *  0b0..Disable SW clock regardless of HWEN
88555  *  0b1..Enable SW clock gating
88556  */
88557 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_MASK)
88558 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_MASK (0x40U)
88559 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_SHIFT (6U)
88560 /*! LPCG_IPS_SYNC_PWM4_0_reserved_6_6 - reserved
88561  */
88562 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_MASK)
88563 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_MASK (0x80U)
88564 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_SHIFT (7U)
88565 /*! pwm4_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
88566  */
88567 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_MASK)
88568 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_MASK (0x100U)
88569 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_SHIFT (8U)
88570 /*! LPCG_IPS_SYNC_PWM4_0_reserved_8_8 - reserved
88571  */
88572 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_MASK)
88573 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_MASK (0x200U)
88574 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_SHIFT (9U)
88575 /*! ccm_ckil_sync_wrapper9_clk_in_SWEN - Software Enable
88576  *  0b0..Disable SW clock regardless of HWEN
88577  *  0b1..Enable SW clock gating
88578  */
88579 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_MASK)
88580 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_MASK (0x400U)
88581 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_SHIFT (10U)
88582 /*! LPCG_IPS_SYNC_PWM4_0_reserved_10_10 - reserved
88583  */
88584 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_MASK)
88585 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_MASK (0x800U)
88586 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_SHIFT (11U)
88587 /*! ccm_ckil_sync_wrapper9_clk_in_STOP - show clock root status, 1 means clock stopped
88588  */
88589 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_MASK)
88590 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_MASK (0xF000U)
88591 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_SHIFT (12U)
88592 /*! LPCG_IPS_SYNC_PWM4_0_reserved_12_15 - reserved
88593  */
88594 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_MASK)
88595 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_MASK (0x10000U)
88596 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_SHIFT (16U)
88597 /*! pwm4_ipg_clk_s_HWEN - Hardware Enable
88598  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88599  *  0b1..Enable HW automatic gating
88600  */
88601 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_MASK)
88602 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_MASK (0x20000U)
88603 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_SHIFT (17U)
88604 /*! pwm4_ipg_clk_s_SWEN - Software Enable
88605  *  0b0..Disable SW clock regardless of HWEN
88606  *  0b1..Enable SW clock gating
88607  */
88608 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_MASK)
88609 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_MASK (0x40000U)
88610 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_SHIFT (18U)
88611 /*! LPCG_IPS_SYNC_PWM4_0_reserved_18_18 - reserved
88612  */
88613 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_MASK)
88614 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_MASK (0x80000U)
88615 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_SHIFT (19U)
88616 /*! pwm4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
88617  */
88618 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_MASK)
88619 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_MASK (0x100000U)
88620 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_SHIFT (20U)
88621 /*! LPCG_IPS_SYNC_PWM4_0_reserved_20_20 - reserved
88622  */
88623 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_MASK)
88624 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_MASK (0x200000U)
88625 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_SHIFT (21U)
88626 /*! ips_sync_pwm4_ipg_slave_clk_SWEN - Software Enable
88627  *  0b0..Disable SW clock regardless of HWEN
88628  *  0b1..Enable SW clock gating
88629  */
88630 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_MASK)
88631 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_MASK (0x400000U)
88632 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_SHIFT (22U)
88633 /*! LPCG_IPS_SYNC_PWM4_0_reserved_22_22 - reserved
88634  */
88635 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_MASK)
88636 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_MASK (0x800000U)
88637 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_SHIFT (23U)
88638 /*! ips_sync_pwm4_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
88639  */
88640 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_MASK)
88641 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_MASK (0x1000000U)
88642 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_SHIFT (24U)
88643 /*! ips_sync_pwm4_ipg_master_clk_HWEN - Hardware Enable
88644  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88645  *  0b1..Enable HW automatic gating
88646  */
88647 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_MASK)
88648 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_MASK (0x2000000U)
88649 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_SHIFT (25U)
88650 /*! ips_sync_pwm4_ipg_master_clk_SWEN - Software Enable
88651  *  0b0..Disable SW clock regardless of HWEN
88652  *  0b1..Enable SW clock gating
88653  */
88654 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_MASK)
88655 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_MASK (0x4000000U)
88656 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_SHIFT (26U)
88657 /*! LPCG_IPS_SYNC_PWM4_0_reserved_26_26 - reserved
88658  */
88659 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_MASK)
88660 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_MASK (0x8000000U)
88661 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_SHIFT (27U)
88662 /*! ips_sync_pwm4_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
88663  */
88664 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_MASK)
88665 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_MASK (0xF0000000U)
88666 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_SHIFT (28U)
88667 /*! LPCG_IPS_SYNC_PWM4_0_reserved_28_31 - reserved
88668  */
88669 #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_MASK)
88670 /*! @} */
88671 
88672 
88673 /*!
88674  * @}
88675  */ /* end of group LSIO_LPCG_PWM4_Register_Masks */
88676 
88677 
88678 /* LSIO_LPCG_PWM4 - Peripheral instance base addresses */
88679 /** Peripheral LSIO__LPCG_PWM4 base address */
88680 #define LSIO__LPCG_PWM4_BASE                     (0x5D440000u)
88681 /** Peripheral LSIO__LPCG_PWM4 base pointer */
88682 #define LSIO__LPCG_PWM4                          ((LSIO_LPCG_PWM4_Type *)LSIO__LPCG_PWM4_BASE)
88683 /** Array initializer of LSIO_LPCG_PWM4 peripheral base addresses */
88684 #define LSIO_LPCG_PWM4_BASE_ADDRS                { LSIO__LPCG_PWM4_BASE }
88685 /** Array initializer of LSIO_LPCG_PWM4 peripheral base pointers */
88686 #define LSIO_LPCG_PWM4_BASE_PTRS                 { LSIO__LPCG_PWM4 }
88687 
88688 /*!
88689  * @}
88690  */ /* end of group LSIO_LPCG_PWM4_Peripheral_Access_Layer */
88691 
88692 
88693 /* ----------------------------------------------------------------------------
88694    -- LSIO_LPCG_PWM5 Peripheral Access Layer
88695    ---------------------------------------------------------------------------- */
88696 
88697 /*!
88698  * @addtogroup LSIO_LPCG_PWM5_Peripheral_Access_Layer LSIO_LPCG_PWM5 Peripheral Access Layer
88699  * @{
88700  */
88701 
88702 /** LSIO_LPCG_PWM5 - Register Layout Typedef */
88703 typedef struct {
88704   __IO uint32_t LPCG_IPS_SYNC_PWM5_0;              /**< na, offset: 0x0 */
88705 } LSIO_LPCG_PWM5_Type;
88706 
88707 /* ----------------------------------------------------------------------------
88708    -- LSIO_LPCG_PWM5 Register Masks
88709    ---------------------------------------------------------------------------- */
88710 
88711 /*!
88712  * @addtogroup LSIO_LPCG_PWM5_Register_Masks LSIO_LPCG_PWM5 Register Masks
88713  * @{
88714  */
88715 
88716 /*! @name LPCG_IPS_SYNC_PWM5_0 - na */
88717 /*! @{ */
88718 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_MASK (0x1U)
88719 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_SHIFT (0U)
88720 /*! pwm5_ipg_clk_HWEN - Hardware Enable
88721  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88722  *  0b1..Enable HW automatic gating
88723  */
88724 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_MASK)
88725 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_MASK (0x2U)
88726 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_SHIFT (1U)
88727 /*! pwm5_ipg_clk_SWEN - Software Enable
88728  *  0b0..Disable SW clock regardless of HWEN
88729  *  0b1..Enable SW clock gating
88730  */
88731 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_MASK)
88732 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_MASK (0x4U)
88733 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_SHIFT (2U)
88734 /*! LPCG_IPS_SYNC_PWM5_0_reserved_2_2 - reserved
88735  */
88736 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_MASK)
88737 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_MASK (0x8U)
88738 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_SHIFT (3U)
88739 /*! pwm5_ipg_clk_STOP - show clock root status, 1 means clock stopped
88740  */
88741 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_MASK)
88742 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_MASK (0x10U)
88743 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_SHIFT (4U)
88744 /*! LPCG_IPS_SYNC_PWM5_0_reserved_4_4 - reserved
88745  */
88746 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_MASK)
88747 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_MASK (0x20U)
88748 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_SHIFT (5U)
88749 /*! pwm5_ipg_clk_highfreq_SWEN - Software Enable
88750  *  0b0..Disable SW clock regardless of HWEN
88751  *  0b1..Enable SW clock gating
88752  */
88753 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_MASK)
88754 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_MASK (0x40U)
88755 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_SHIFT (6U)
88756 /*! LPCG_IPS_SYNC_PWM5_0_reserved_6_6 - reserved
88757  */
88758 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_MASK)
88759 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_MASK (0x80U)
88760 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_SHIFT (7U)
88761 /*! pwm5_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
88762  */
88763 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_MASK)
88764 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_MASK (0x100U)
88765 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_SHIFT (8U)
88766 /*! LPCG_IPS_SYNC_PWM5_0_reserved_8_8 - reserved
88767  */
88768 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_MASK)
88769 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_MASK (0x200U)
88770 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_SHIFT (9U)
88771 /*! ccm_ckil_sync_wrapper10_clk_in_SWEN - Software Enable
88772  *  0b0..Disable SW clock regardless of HWEN
88773  *  0b1..Enable SW clock gating
88774  */
88775 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_MASK)
88776 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_MASK (0x400U)
88777 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_SHIFT (10U)
88778 /*! LPCG_IPS_SYNC_PWM5_0_reserved_10_10 - reserved
88779  */
88780 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_MASK)
88781 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_MASK (0x800U)
88782 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_SHIFT (11U)
88783 /*! ccm_ckil_sync_wrapper10_clk_in_STOP - show clock root status, 1 means clock stopped
88784  */
88785 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_MASK)
88786 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_MASK (0xF000U)
88787 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_SHIFT (12U)
88788 /*! LPCG_IPS_SYNC_PWM5_0_reserved_12_15 - reserved
88789  */
88790 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_MASK)
88791 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_MASK (0x10000U)
88792 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_SHIFT (16U)
88793 /*! pwm5_ipg_clk_s_HWEN - Hardware Enable
88794  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88795  *  0b1..Enable HW automatic gating
88796  */
88797 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_MASK)
88798 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_MASK (0x20000U)
88799 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_SHIFT (17U)
88800 /*! pwm5_ipg_clk_s_SWEN - Software Enable
88801  *  0b0..Disable SW clock regardless of HWEN
88802  *  0b1..Enable SW clock gating
88803  */
88804 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_MASK)
88805 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_MASK (0x40000U)
88806 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_SHIFT (18U)
88807 /*! LPCG_IPS_SYNC_PWM5_0_reserved_18_18 - reserved
88808  */
88809 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_MASK)
88810 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_MASK (0x80000U)
88811 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_SHIFT (19U)
88812 /*! pwm5_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
88813  */
88814 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_MASK)
88815 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_MASK (0x100000U)
88816 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_SHIFT (20U)
88817 /*! LPCG_IPS_SYNC_PWM5_0_reserved_20_20 - reserved
88818  */
88819 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_MASK)
88820 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_MASK (0x200000U)
88821 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_SHIFT (21U)
88822 /*! ips_sync_pwm5_ipg_slave_clk_SWEN - Software Enable
88823  *  0b0..Disable SW clock regardless of HWEN
88824  *  0b1..Enable SW clock gating
88825  */
88826 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_MASK)
88827 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_MASK (0x400000U)
88828 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_SHIFT (22U)
88829 /*! LPCG_IPS_SYNC_PWM5_0_reserved_22_22 - reserved
88830  */
88831 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_MASK)
88832 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_MASK (0x800000U)
88833 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_SHIFT (23U)
88834 /*! ips_sync_pwm5_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
88835  */
88836 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_MASK)
88837 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_MASK (0x1000000U)
88838 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_SHIFT (24U)
88839 /*! ips_sync_pwm5_ipg_master_clk_HWEN - Hardware Enable
88840  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88841  *  0b1..Enable HW automatic gating
88842  */
88843 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_MASK)
88844 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_MASK (0x2000000U)
88845 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_SHIFT (25U)
88846 /*! ips_sync_pwm5_ipg_master_clk_SWEN - Software Enable
88847  *  0b0..Disable SW clock regardless of HWEN
88848  *  0b1..Enable SW clock gating
88849  */
88850 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_MASK)
88851 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_MASK (0x4000000U)
88852 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_SHIFT (26U)
88853 /*! LPCG_IPS_SYNC_PWM5_0_reserved_26_26 - reserved
88854  */
88855 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_MASK)
88856 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_MASK (0x8000000U)
88857 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_SHIFT (27U)
88858 /*! ips_sync_pwm5_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
88859  */
88860 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_MASK)
88861 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_MASK (0xF0000000U)
88862 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_SHIFT (28U)
88863 /*! LPCG_IPS_SYNC_PWM5_0_reserved_28_31 - reserved
88864  */
88865 #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_MASK)
88866 /*! @} */
88867 
88868 
88869 /*!
88870  * @}
88871  */ /* end of group LSIO_LPCG_PWM5_Register_Masks */
88872 
88873 
88874 /* LSIO_LPCG_PWM5 - Peripheral instance base addresses */
88875 /** Peripheral LSIO__LPCG_PWM5 base address */
88876 #define LSIO__LPCG_PWM5_BASE                     (0x5D450000u)
88877 /** Peripheral LSIO__LPCG_PWM5 base pointer */
88878 #define LSIO__LPCG_PWM5                          ((LSIO_LPCG_PWM5_Type *)LSIO__LPCG_PWM5_BASE)
88879 /** Array initializer of LSIO_LPCG_PWM5 peripheral base addresses */
88880 #define LSIO_LPCG_PWM5_BASE_ADDRS                { LSIO__LPCG_PWM5_BASE }
88881 /** Array initializer of LSIO_LPCG_PWM5 peripheral base pointers */
88882 #define LSIO_LPCG_PWM5_BASE_PTRS                 { LSIO__LPCG_PWM5 }
88883 
88884 /*!
88885  * @}
88886  */ /* end of group LSIO_LPCG_PWM5_Peripheral_Access_Layer */
88887 
88888 
88889 /* ----------------------------------------------------------------------------
88890    -- LSIO_LPCG_PWM6 Peripheral Access Layer
88891    ---------------------------------------------------------------------------- */
88892 
88893 /*!
88894  * @addtogroup LSIO_LPCG_PWM6_Peripheral_Access_Layer LSIO_LPCG_PWM6 Peripheral Access Layer
88895  * @{
88896  */
88897 
88898 /** LSIO_LPCG_PWM6 - Register Layout Typedef */
88899 typedef struct {
88900   __IO uint32_t LPCG_IPS_SYNC_PWM6_0;              /**< na, offset: 0x0 */
88901 } LSIO_LPCG_PWM6_Type;
88902 
88903 /* ----------------------------------------------------------------------------
88904    -- LSIO_LPCG_PWM6 Register Masks
88905    ---------------------------------------------------------------------------- */
88906 
88907 /*!
88908  * @addtogroup LSIO_LPCG_PWM6_Register_Masks LSIO_LPCG_PWM6 Register Masks
88909  * @{
88910  */
88911 
88912 /*! @name LPCG_IPS_SYNC_PWM6_0 - na */
88913 /*! @{ */
88914 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_MASK (0x1U)
88915 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_SHIFT (0U)
88916 /*! pwm6_ipg_clk_HWEN - Hardware Enable
88917  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88918  *  0b1..Enable HW automatic gating
88919  */
88920 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_MASK)
88921 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_MASK (0x2U)
88922 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_SHIFT (1U)
88923 /*! pwm6_ipg_clk_SWEN - Software Enable
88924  *  0b0..Disable SW clock regardless of HWEN
88925  *  0b1..Enable SW clock gating
88926  */
88927 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_MASK)
88928 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_MASK (0x4U)
88929 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_SHIFT (2U)
88930 /*! LPCG_IPS_SYNC_PWM6_0_reserved_2_2 - reserved
88931  */
88932 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_MASK)
88933 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_MASK (0x8U)
88934 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_SHIFT (3U)
88935 /*! pwm6_ipg_clk_STOP - show clock root status, 1 means clock stopped
88936  */
88937 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_MASK)
88938 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_MASK (0x10U)
88939 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_SHIFT (4U)
88940 /*! LPCG_IPS_SYNC_PWM6_0_reserved_4_4 - reserved
88941  */
88942 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_MASK)
88943 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_MASK (0x20U)
88944 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_SHIFT (5U)
88945 /*! pwm6_ipg_clk_highfreq_SWEN - Software Enable
88946  *  0b0..Disable SW clock regardless of HWEN
88947  *  0b1..Enable SW clock gating
88948  */
88949 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_MASK)
88950 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_MASK (0x40U)
88951 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_SHIFT (6U)
88952 /*! LPCG_IPS_SYNC_PWM6_0_reserved_6_6 - reserved
88953  */
88954 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_MASK)
88955 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_MASK (0x80U)
88956 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_SHIFT (7U)
88957 /*! pwm6_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
88958  */
88959 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_MASK)
88960 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_MASK (0x100U)
88961 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_SHIFT (8U)
88962 /*! LPCG_IPS_SYNC_PWM6_0_reserved_8_8 - reserved
88963  */
88964 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_MASK)
88965 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_MASK (0x200U)
88966 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_SHIFT (9U)
88967 /*! ccm_ckil_sync_wrapper11_clk_in_SWEN - Software Enable
88968  *  0b0..Disable SW clock regardless of HWEN
88969  *  0b1..Enable SW clock gating
88970  */
88971 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_MASK)
88972 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_MASK (0x400U)
88973 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_SHIFT (10U)
88974 /*! LPCG_IPS_SYNC_PWM6_0_reserved_10_10 - reserved
88975  */
88976 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_MASK)
88977 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_MASK (0x800U)
88978 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_SHIFT (11U)
88979 /*! ccm_ckil_sync_wrapper11_clk_in_STOP - show clock root status, 1 means clock stopped
88980  */
88981 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_MASK)
88982 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_MASK (0xF000U)
88983 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_SHIFT (12U)
88984 /*! LPCG_IPS_SYNC_PWM6_0_reserved_12_15 - reserved
88985  */
88986 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_MASK)
88987 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_MASK (0x10000U)
88988 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_SHIFT (16U)
88989 /*! pwm6_ipg_clk_s_HWEN - Hardware Enable
88990  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
88991  *  0b1..Enable HW automatic gating
88992  */
88993 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_MASK)
88994 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_MASK (0x20000U)
88995 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_SHIFT (17U)
88996 /*! pwm6_ipg_clk_s_SWEN - Software Enable
88997  *  0b0..Disable SW clock regardless of HWEN
88998  *  0b1..Enable SW clock gating
88999  */
89000 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_MASK)
89001 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_MASK (0x40000U)
89002 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_SHIFT (18U)
89003 /*! LPCG_IPS_SYNC_PWM6_0_reserved_18_18 - reserved
89004  */
89005 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_MASK)
89006 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_MASK (0x80000U)
89007 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_SHIFT (19U)
89008 /*! pwm6_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
89009  */
89010 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_MASK)
89011 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_MASK (0x100000U)
89012 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_SHIFT (20U)
89013 /*! LPCG_IPS_SYNC_PWM6_0_reserved_20_20 - reserved
89014  */
89015 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_MASK)
89016 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_MASK (0x200000U)
89017 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_SHIFT (21U)
89018 /*! ips_sync_pwm6_ipg_slave_clk_SWEN - Software Enable
89019  *  0b0..Disable SW clock regardless of HWEN
89020  *  0b1..Enable SW clock gating
89021  */
89022 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_MASK)
89023 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_MASK (0x400000U)
89024 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_SHIFT (22U)
89025 /*! LPCG_IPS_SYNC_PWM6_0_reserved_22_22 - reserved
89026  */
89027 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_MASK)
89028 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_MASK (0x800000U)
89029 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_SHIFT (23U)
89030 /*! ips_sync_pwm6_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
89031  */
89032 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_MASK)
89033 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_MASK (0x1000000U)
89034 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_SHIFT (24U)
89035 /*! ips_sync_pwm6_ipg_master_clk_HWEN - Hardware Enable
89036  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
89037  *  0b1..Enable HW automatic gating
89038  */
89039 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_MASK)
89040 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_MASK (0x2000000U)
89041 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_SHIFT (25U)
89042 /*! ips_sync_pwm6_ipg_master_clk_SWEN - Software Enable
89043  *  0b0..Disable SW clock regardless of HWEN
89044  *  0b1..Enable SW clock gating
89045  */
89046 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_MASK)
89047 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_MASK (0x4000000U)
89048 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_SHIFT (26U)
89049 /*! LPCG_IPS_SYNC_PWM6_0_reserved_26_26 - reserved
89050  */
89051 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_MASK)
89052 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_MASK (0x8000000U)
89053 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_SHIFT (27U)
89054 /*! ips_sync_pwm6_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
89055  */
89056 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_MASK)
89057 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_MASK (0xF0000000U)
89058 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_SHIFT (28U)
89059 /*! LPCG_IPS_SYNC_PWM6_0_reserved_28_31 - reserved
89060  */
89061 #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_MASK)
89062 /*! @} */
89063 
89064 
89065 /*!
89066  * @}
89067  */ /* end of group LSIO_LPCG_PWM6_Register_Masks */
89068 
89069 
89070 /* LSIO_LPCG_PWM6 - Peripheral instance base addresses */
89071 /** Peripheral LSIO__LPCG_PWM6 base address */
89072 #define LSIO__LPCG_PWM6_BASE                     (0x5D460000u)
89073 /** Peripheral LSIO__LPCG_PWM6 base pointer */
89074 #define LSIO__LPCG_PWM6                          ((LSIO_LPCG_PWM6_Type *)LSIO__LPCG_PWM6_BASE)
89075 /** Array initializer of LSIO_LPCG_PWM6 peripheral base addresses */
89076 #define LSIO_LPCG_PWM6_BASE_ADDRS                { LSIO__LPCG_PWM6_BASE }
89077 /** Array initializer of LSIO_LPCG_PWM6 peripheral base pointers */
89078 #define LSIO_LPCG_PWM6_BASE_PTRS                 { LSIO__LPCG_PWM6 }
89079 
89080 /*!
89081  * @}
89082  */ /* end of group LSIO_LPCG_PWM6_Peripheral_Access_Layer */
89083 
89084 
89085 /* ----------------------------------------------------------------------------
89086    -- LSIO_LPCG_PWM7 Peripheral Access Layer
89087    ---------------------------------------------------------------------------- */
89088 
89089 /*!
89090  * @addtogroup LSIO_LPCG_PWM7_Peripheral_Access_Layer LSIO_LPCG_PWM7 Peripheral Access Layer
89091  * @{
89092  */
89093 
89094 /** LSIO_LPCG_PWM7 - Register Layout Typedef */
89095 typedef struct {
89096   __IO uint32_t LPCG_IPS_SYNC_PWM7_0;              /**< na, offset: 0x0 */
89097 } LSIO_LPCG_PWM7_Type;
89098 
89099 /* ----------------------------------------------------------------------------
89100    -- LSIO_LPCG_PWM7 Register Masks
89101    ---------------------------------------------------------------------------- */
89102 
89103 /*!
89104  * @addtogroup LSIO_LPCG_PWM7_Register_Masks LSIO_LPCG_PWM7 Register Masks
89105  * @{
89106  */
89107 
89108 /*! @name LPCG_IPS_SYNC_PWM7_0 - na */
89109 /*! @{ */
89110 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_MASK (0x1U)
89111 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_SHIFT (0U)
89112 /*! pwm7_ipg_clk_HWEN - Hardware Enable
89113  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
89114  *  0b1..Enable HW automatic gating
89115  */
89116 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_MASK)
89117 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_MASK (0x2U)
89118 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_SHIFT (1U)
89119 /*! pwm7_ipg_clk_SWEN - Software Enable
89120  *  0b0..Disable SW clock regardless of HWEN
89121  *  0b1..Enable SW clock gating
89122  */
89123 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_MASK)
89124 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_MASK (0x4U)
89125 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_SHIFT (2U)
89126 /*! LPCG_IPS_SYNC_PWM7_0_reserved_2_2 - reserved
89127  */
89128 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_MASK)
89129 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_MASK (0x8U)
89130 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_SHIFT (3U)
89131 /*! pwm7_ipg_clk_STOP - show clock root status, 1 means clock stopped
89132  */
89133 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_MASK)
89134 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_MASK (0x10U)
89135 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_SHIFT (4U)
89136 /*! LPCG_IPS_SYNC_PWM7_0_reserved_4_4 - reserved
89137  */
89138 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_MASK)
89139 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_MASK (0x20U)
89140 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_SHIFT (5U)
89141 /*! pwm7_ipg_clk_highfreq_SWEN - Software Enable
89142  *  0b0..Disable SW clock regardless of HWEN
89143  *  0b1..Enable SW clock gating
89144  */
89145 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_MASK)
89146 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_MASK (0x40U)
89147 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_SHIFT (6U)
89148 /*! LPCG_IPS_SYNC_PWM7_0_reserved_6_6 - reserved
89149  */
89150 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_MASK)
89151 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_MASK (0x80U)
89152 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_SHIFT (7U)
89153 /*! pwm7_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
89154  */
89155 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_MASK)
89156 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_MASK (0x100U)
89157 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_SHIFT (8U)
89158 /*! LPCG_IPS_SYNC_PWM7_0_reserved_8_8 - reserved
89159  */
89160 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_MASK)
89161 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_MASK (0x200U)
89162 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_SHIFT (9U)
89163 /*! ccm_ckil_sync_wrapper12_clk_in_SWEN - Software Enable
89164  *  0b0..Disable SW clock regardless of HWEN
89165  *  0b1..Enable SW clock gating
89166  */
89167 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_MASK)
89168 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_MASK (0x400U)
89169 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_SHIFT (10U)
89170 /*! LPCG_IPS_SYNC_PWM7_0_reserved_10_10 - reserved
89171  */
89172 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_MASK)
89173 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_MASK (0x800U)
89174 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_SHIFT (11U)
89175 /*! ccm_ckil_sync_wrapper12_clk_in_STOP - show clock root status, 1 means clock stopped
89176  */
89177 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_MASK)
89178 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_MASK (0xF000U)
89179 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_SHIFT (12U)
89180 /*! LPCG_IPS_SYNC_PWM7_0_reserved_12_15 - reserved
89181  */
89182 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_MASK)
89183 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_MASK (0x10000U)
89184 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_SHIFT (16U)
89185 /*! pwm7_ipg_clk_s_HWEN - Hardware Enable
89186  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
89187  *  0b1..Enable HW automatic gating
89188  */
89189 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_MASK)
89190 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_MASK (0x20000U)
89191 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_SHIFT (17U)
89192 /*! pwm7_ipg_clk_s_SWEN - Software Enable
89193  *  0b0..Disable SW clock regardless of HWEN
89194  *  0b1..Enable SW clock gating
89195  */
89196 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_MASK)
89197 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_MASK (0x40000U)
89198 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_SHIFT (18U)
89199 /*! LPCG_IPS_SYNC_PWM7_0_reserved_18_18 - reserved
89200  */
89201 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_MASK)
89202 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_MASK (0x80000U)
89203 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_SHIFT (19U)
89204 /*! pwm7_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
89205  */
89206 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_MASK)
89207 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_MASK (0x100000U)
89208 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_SHIFT (20U)
89209 /*! LPCG_IPS_SYNC_PWM7_0_reserved_20_20 - reserved
89210  */
89211 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_MASK)
89212 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_MASK (0x200000U)
89213 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_SHIFT (21U)
89214 /*! ips_sync_pwm7_ipg_slave_clk_SWEN - Software Enable
89215  *  0b0..Disable SW clock regardless of HWEN
89216  *  0b1..Enable SW clock gating
89217  */
89218 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_MASK)
89219 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_MASK (0x400000U)
89220 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_SHIFT (22U)
89221 /*! LPCG_IPS_SYNC_PWM7_0_reserved_22_22 - reserved
89222  */
89223 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_MASK)
89224 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_MASK (0x800000U)
89225 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_SHIFT (23U)
89226 /*! ips_sync_pwm7_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped
89227  */
89228 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_MASK)
89229 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_MASK (0x1000000U)
89230 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_SHIFT (24U)
89231 /*! ips_sync_pwm7_ipg_master_clk_HWEN - Hardware Enable
89232  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
89233  *  0b1..Enable HW automatic gating
89234  */
89235 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_MASK)
89236 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_MASK (0x2000000U)
89237 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_SHIFT (25U)
89238 /*! ips_sync_pwm7_ipg_master_clk_SWEN - Software Enable
89239  *  0b0..Disable SW clock regardless of HWEN
89240  *  0b1..Enable SW clock gating
89241  */
89242 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_MASK)
89243 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_MASK (0x4000000U)
89244 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_SHIFT (26U)
89245 /*! LPCG_IPS_SYNC_PWM7_0_reserved_26_26 - reserved
89246  */
89247 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_MASK)
89248 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_MASK (0x8000000U)
89249 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_SHIFT (27U)
89250 /*! ips_sync_pwm7_ipg_master_clk_STOP - show clock root status, 1 means clock stopped
89251  */
89252 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_MASK)
89253 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_MASK (0xF0000000U)
89254 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_SHIFT (28U)
89255 /*! LPCG_IPS_SYNC_PWM7_0_reserved_28_31 - reserved
89256  */
89257 #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_MASK)
89258 /*! @} */
89259 
89260 
89261 /*!
89262  * @}
89263  */ /* end of group LSIO_LPCG_PWM7_Register_Masks */
89264 
89265 
89266 /* LSIO_LPCG_PWM7 - Peripheral instance base addresses */
89267 /** Peripheral LSIO__LPCG_PWM7 base address */
89268 #define LSIO__LPCG_PWM7_BASE                     (0x5D470000u)
89269 /** Peripheral LSIO__LPCG_PWM7 base pointer */
89270 #define LSIO__LPCG_PWM7                          ((LSIO_LPCG_PWM7_Type *)LSIO__LPCG_PWM7_BASE)
89271 /** Array initializer of LSIO_LPCG_PWM7 peripheral base addresses */
89272 #define LSIO_LPCG_PWM7_BASE_ADDRS                { LSIO__LPCG_PWM7_BASE }
89273 /** Array initializer of LSIO_LPCG_PWM7 peripheral base pointers */
89274 #define LSIO_LPCG_PWM7_BASE_PTRS                 { LSIO__LPCG_PWM7 }
89275 
89276 /*!
89277  * @}
89278  */ /* end of group LSIO_LPCG_PWM7_Peripheral_Access_Layer */
89279 
89280 
89281 /* ----------------------------------------------------------------------------
89282    -- LSIO_LPCG_QSPI0 Peripheral Access Layer
89283    ---------------------------------------------------------------------------- */
89284 
89285 /*!
89286  * @addtogroup LSIO_LPCG_QSPI0_Peripheral_Access_Layer LSIO_LPCG_QSPI0 Peripheral Access Layer
89287  * @{
89288  */
89289 
89290 /** LSIO_LPCG_QSPI0 - Register Layout Typedef */
89291 typedef struct {
89292   __IO uint32_t LPCG_QSPI0_0;                      /**< na, offset: 0x0 */
89293 } LSIO_LPCG_QSPI0_Type;
89294 
89295 /* ----------------------------------------------------------------------------
89296    -- LSIO_LPCG_QSPI0 Register Masks
89297    ---------------------------------------------------------------------------- */
89298 
89299 /*!
89300  * @addtogroup LSIO_LPCG_QSPI0_Register_Masks LSIO_LPCG_QSPI0 Register Masks
89301  * @{
89302  */
89303 
89304 /*! @name LPCG_QSPI0_0 - na */
89305 /*! @{ */
89306 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_MASK (0x1U)
89307 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_SHIFT (0U)
89308 /*! LPCG_QSPI0_0_reserved_0_0 - reserved
89309  */
89310 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_MASK)
89311 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_MASK (0x2U)
89312 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_SHIFT (1U)
89313 /*! qspi0_ipg_clk_sfck_SWEN - Software Enable
89314  *  0b0..Disable SW clock regardless of HWEN
89315  *  0b1..Enable SW clock gating
89316  */
89317 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_MASK)
89318 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_MASK (0x4U)
89319 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_SHIFT (2U)
89320 /*! LPCG_QSPI0_0_reserved_2_2 - reserved
89321  */
89322 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_MASK)
89323 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_MASK (0x8U)
89324 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_SHIFT (3U)
89325 /*! qspi0_ipg_clk_sfck_STOP - show clock root status, 1 means clock stopped
89326  */
89327 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_MASK)
89328 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_MASK (0x1FFF0U)
89329 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_SHIFT (4U)
89330 /*! LPCG_QSPI0_0_reserved_4_16 - reserved
89331  */
89332 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_MASK)
89333 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_MASK (0x20000U)
89334 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_SHIFT (17U)
89335 /*! qspi0_hclk_SWEN - Software Enable
89336  *  0b0..Disable SW clock regardless of HWEN
89337  *  0b1..Enable SW clock gating
89338  */
89339 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_MASK)
89340 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_MASK (0x40000U)
89341 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_SHIFT (18U)
89342 /*! LPCG_QSPI0_0_reserved_18_18 - reserved
89343  */
89344 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_MASK)
89345 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_MASK (0x80000U)
89346 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_SHIFT (19U)
89347 /*! qspi0_hclk_STOP - show clock root status, 1 means clock stopped
89348  */
89349 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_MASK)
89350 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_MASK (0x100000U)
89351 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_SHIFT (20U)
89352 /*! LPCG_QSPI0_0_reserved_20_20 - reserved
89353  */
89354 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_MASK)
89355 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_MASK (0x200000U)
89356 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_SHIFT (21U)
89357 /*! qspi0_ipg_clk_SWEN - Software Enable
89358  *  0b0..Disable SW clock regardless of HWEN
89359  *  0b1..Enable SW clock gating
89360  */
89361 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_MASK)
89362 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_MASK (0x400000U)
89363 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_SHIFT (22U)
89364 /*! LPCG_QSPI0_0_reserved_22_22 - reserved
89365  */
89366 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_MASK)
89367 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_MASK (0x800000U)
89368 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_SHIFT (23U)
89369 /*! qspi0_ipg_clk_STOP - show clock root status, 1 means clock stopped
89370  */
89371 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_MASK)
89372 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_MASK (0x1000000U)
89373 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_SHIFT (24U)
89374 /*! qspi0_ipg_clk_s_HWEN - Hardware Enable
89375  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
89376  *  0b1..Enable HW automatic gating
89377  */
89378 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_MASK)
89379 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_MASK (0x2000000U)
89380 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_SHIFT (25U)
89381 /*! qspi0_ipg_clk_s_SWEN - Software Enable
89382  *  0b0..Disable SW clock regardless of HWEN
89383  *  0b1..Enable SW clock gating
89384  */
89385 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_MASK)
89386 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_MASK (0x4000000U)
89387 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_SHIFT (26U)
89388 /*! LPCG_QSPI0_0_reserved_26_26 - reserved
89389  */
89390 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_MASK)
89391 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_MASK (0x8000000U)
89392 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_SHIFT (27U)
89393 /*! qspi0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
89394  */
89395 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_MASK)
89396 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_MASK (0xF0000000U)
89397 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_SHIFT (28U)
89398 /*! LPCG_QSPI0_0_reserved_28_31 - reserved
89399  */
89400 #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_MASK)
89401 /*! @} */
89402 
89403 
89404 /*!
89405  * @}
89406  */ /* end of group LSIO_LPCG_QSPI0_Register_Masks */
89407 
89408 
89409 /* LSIO_LPCG_QSPI0 - Peripheral instance base addresses */
89410 /** Peripheral LSIO__LPCG_QSPI0 base address */
89411 #define LSIO__LPCG_QSPI0_BASE                    (0x5D520000u)
89412 /** Peripheral LSIO__LPCG_QSPI0 base pointer */
89413 #define LSIO__LPCG_QSPI0                         ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
89414 /** Array initializer of LSIO_LPCG_QSPI0 peripheral base addresses */
89415 #define LSIO_LPCG_QSPI0_BASE_ADDRS               { LSIO__LPCG_QSPI0_BASE }
89416 /** Array initializer of LSIO_LPCG_QSPI0 peripheral base pointers */
89417 #define LSIO_LPCG_QSPI0_BASE_PTRS                { LSIO__LPCG_QSPI0 }
89418 
89419 /*!
89420  * @}
89421  */ /* end of group LSIO_LPCG_QSPI0_Peripheral_Access_Layer */
89422 
89423 
89424 /* ----------------------------------------------------------------------------
89425    -- LSIO_LPCG_QSPI1 Peripheral Access Layer
89426    ---------------------------------------------------------------------------- */
89427 
89428 /*!
89429  * @addtogroup LSIO_LPCG_QSPI1_Peripheral_Access_Layer LSIO_LPCG_QSPI1 Peripheral Access Layer
89430  * @{
89431  */
89432 
89433 /** LSIO_LPCG_QSPI1 - Register Layout Typedef */
89434 typedef struct {
89435   __IO uint32_t LPCG_QSPI1_0;                      /**< na, offset: 0x0 */
89436 } LSIO_LPCG_QSPI1_Type;
89437 
89438 /* ----------------------------------------------------------------------------
89439    -- LSIO_LPCG_QSPI1 Register Masks
89440    ---------------------------------------------------------------------------- */
89441 
89442 /*!
89443  * @addtogroup LSIO_LPCG_QSPI1_Register_Masks LSIO_LPCG_QSPI1 Register Masks
89444  * @{
89445  */
89446 
89447 /*! @name LPCG_QSPI1_0 - na */
89448 /*! @{ */
89449 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_MASK (0x1U)
89450 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_SHIFT (0U)
89451 /*! LPCG_QSPI1_0_reserved_0_0 - reserved
89452  */
89453 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_MASK)
89454 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_MASK (0x2U)
89455 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_SHIFT (1U)
89456 /*! qspi1_ipg_clk_sfck_SWEN - Software Enable
89457  *  0b0..Disable SW clock regardless of HWEN
89458  *  0b1..Enable SW clock gating
89459  */
89460 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_MASK)
89461 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_MASK (0x4U)
89462 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_SHIFT (2U)
89463 /*! LPCG_QSPI1_0_reserved_2_2 - reserved
89464  */
89465 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_MASK)
89466 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_MASK (0x8U)
89467 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_SHIFT (3U)
89468 /*! qspi1_ipg_clk_sfck_STOP - show clock root status, 1 means clock stopped
89469  */
89470 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_MASK)
89471 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_MASK (0x1FFF0U)
89472 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_SHIFT (4U)
89473 /*! LPCG_QSPI1_0_reserved_4_16 - reserved
89474  */
89475 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_MASK)
89476 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_MASK (0x20000U)
89477 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_SHIFT (17U)
89478 /*! qspi1_hclk_SWEN - Software Enable
89479  *  0b0..Disable SW clock regardless of HWEN
89480  *  0b1..Enable SW clock gating
89481  */
89482 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_MASK)
89483 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_MASK (0x40000U)
89484 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_SHIFT (18U)
89485 /*! LPCG_QSPI1_0_reserved_18_18 - reserved
89486  */
89487 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_MASK)
89488 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_MASK (0x80000U)
89489 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_SHIFT (19U)
89490 /*! qspi1_hclk_STOP - show clock root status, 1 means clock stopped
89491  */
89492 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_MASK)
89493 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_MASK (0x100000U)
89494 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_SHIFT (20U)
89495 /*! LPCG_QSPI1_0_reserved_20_20 - reserved
89496  */
89497 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_MASK)
89498 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_MASK (0x200000U)
89499 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_SHIFT (21U)
89500 /*! qspi1_ipg_clk_SWEN - Software Enable
89501  *  0b0..Disable SW clock regardless of HWEN
89502  *  0b1..Enable SW clock gating
89503  */
89504 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_MASK)
89505 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_MASK (0x400000U)
89506 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_SHIFT (22U)
89507 /*! LPCG_QSPI1_0_reserved_22_22 - reserved
89508  */
89509 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_MASK)
89510 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_MASK (0x800000U)
89511 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_SHIFT (23U)
89512 /*! qspi1_ipg_clk_STOP - show clock root status, 1 means clock stopped
89513  */
89514 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_MASK)
89515 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_MASK (0x1000000U)
89516 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_SHIFT (24U)
89517 /*! qspi1_ipg_clk_s_HWEN - Hardware Enable
89518  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
89519  *  0b1..Enable HW automatic gating
89520  */
89521 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_MASK)
89522 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_MASK (0x2000000U)
89523 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_SHIFT (25U)
89524 /*! qspi1_ipg_clk_s_SWEN - Software Enable
89525  *  0b0..Disable SW clock regardless of HWEN
89526  *  0b1..Enable SW clock gating
89527  */
89528 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_MASK)
89529 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_MASK (0x4000000U)
89530 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_SHIFT (26U)
89531 /*! LPCG_QSPI1_0_reserved_26_26 - reserved
89532  */
89533 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_MASK)
89534 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_MASK (0x8000000U)
89535 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_SHIFT (27U)
89536 /*! qspi1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
89537  */
89538 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_MASK)
89539 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_MASK (0xF0000000U)
89540 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_SHIFT (28U)
89541 /*! LPCG_QSPI1_0_reserved_28_31 - reserved
89542  */
89543 #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_MASK)
89544 /*! @} */
89545 
89546 
89547 /*!
89548  * @}
89549  */ /* end of group LSIO_LPCG_QSPI1_Register_Masks */
89550 
89551 
89552 /* LSIO_LPCG_QSPI1 - Peripheral instance base addresses */
89553 /** Peripheral LSIO__LPCG_QSPI1 base address */
89554 #define LSIO__LPCG_QSPI1_BASE                    (0x5D530000u)
89555 /** Peripheral LSIO__LPCG_QSPI1 base pointer */
89556 #define LSIO__LPCG_QSPI1                         ((LSIO_LPCG_QSPI1_Type *)LSIO__LPCG_QSPI1_BASE)
89557 /** Array initializer of LSIO_LPCG_QSPI1 peripheral base addresses */
89558 #define LSIO_LPCG_QSPI1_BASE_ADDRS               { LSIO__LPCG_QSPI1_BASE }
89559 /** Array initializer of LSIO_LPCG_QSPI1 peripheral base pointers */
89560 #define LSIO_LPCG_QSPI1_BASE_PTRS                { LSIO__LPCG_QSPI1 }
89561 
89562 /*!
89563  * @}
89564  */ /* end of group LSIO_LPCG_QSPI1_Peripheral_Access_Layer */
89565 
89566 
89567 /* ----------------------------------------------------------------------------
89568    -- MCM Peripheral Access Layer
89569    ---------------------------------------------------------------------------- */
89570 
89571 /*!
89572  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
89573  * @{
89574  */
89575 
89576 /** MCM - Register Layout Typedef */
89577 typedef struct {
89578        uint8_t RESERVED_0[8];
89579   __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
89580   __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
89581        uint32_t PLACR;                             /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
89582        uint8_t RESERVED_1[16];
89583   __I  uint32_t FADR;                              /**< Fault address register, offset: 0x20 */
89584   __I  uint32_t FATR;                              /**< Fault attributes register, offset: 0x24 */
89585   __I  uint32_t FDR;                               /**< Fault data register, offset: 0x28 */
89586 } MCM_Type;
89587 
89588 /* ----------------------------------------------------------------------------
89589    -- MCM Register Masks
89590    ---------------------------------------------------------------------------- */
89591 
89592 /*!
89593  * @addtogroup MCM_Register_Masks MCM Register Masks
89594  * @{
89595  */
89596 
89597 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
89598 /*! @{ */
89599 #define MCM_PLASC_ASC_MASK                       (0xFFU)
89600 #define MCM_PLASC_ASC_SHIFT                      (0U)
89601 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the
89602  *    crossbar switch's slave input port.
89603  *  0b00000000..A bus slave connection to AXBS input port n is absent
89604  *  0b00000001..A bus slave connection to AXBS input port n is present
89605  */
89606 #define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
89607 /*! @} */
89608 
89609 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
89610 /*! @{ */
89611 #define MCM_PLAMC_AMC_MASK                       (0xFFU)
89612 #define MCM_PLAMC_AMC_SHIFT                      (0U)
89613 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
89614  *  0b00000000..A bus master connection to AXBS input port n is absent
89615  *  0b00000001..A bus master connection to AXBS input port n is present
89616  */
89617 #define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
89618 /*! @} */
89619 
89620 /*! @name FADR - Fault address register */
89621 /*! @{ */
89622 #define MCM_FADR_ADDRESS_MASK                    (0xFFFFFFFFU)
89623 #define MCM_FADR_ADDRESS_SHIFT                   (0U)
89624 /*! ADDRESS - Fault address
89625  */
89626 #define MCM_FADR_ADDRESS(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
89627 /*! @} */
89628 
89629 /*! @name FATR - Fault attributes register */
89630 /*! @{ */
89631 #define MCM_FATR_BEDA_MASK                       (0x1U)
89632 #define MCM_FATR_BEDA_SHIFT                      (0U)
89633 /*! BEDA - Bus error access type
89634  *  0b0..Instruction
89635  *  0b1..Data
89636  */
89637 #define MCM_FATR_BEDA(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
89638 #define MCM_FATR_BEMD_MASK                       (0x2U)
89639 #define MCM_FATR_BEMD_SHIFT                      (1U)
89640 /*! BEMD - Bus error privilege level
89641  *  0b0..User mode
89642  *  0b1..Supervisor/privileged mode
89643  */
89644 #define MCM_FATR_BEMD(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
89645 #define MCM_FATR_BESZ_MASK                       (0x30U)
89646 #define MCM_FATR_BESZ_SHIFT                      (4U)
89647 /*! BESZ - Bus error size
89648  *  0b00..8-bit access
89649  *  0b01..16-bit access
89650  *  0b10..32-bit access
89651  *  0b11..Reserved
89652  */
89653 #define MCM_FATR_BESZ(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
89654 #define MCM_FATR_BEWT_MASK                       (0x80U)
89655 #define MCM_FATR_BEWT_SHIFT                      (7U)
89656 /*! BEWT - Bus error write
89657  *  0b0..Read access
89658  *  0b1..Write access
89659  */
89660 #define MCM_FATR_BEWT(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
89661 #define MCM_FATR_BEMN_MASK                       (0xF00U)
89662 #define MCM_FATR_BEMN_SHIFT                      (8U)
89663 /*! BEMN - Bus error master number
89664  */
89665 #define MCM_FATR_BEMN(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
89666 #define MCM_FATR_BEOVR_MASK                      (0x80000000U)
89667 #define MCM_FATR_BEOVR_SHIFT                     (31U)
89668 /*! BEOVR - Bus error overrun
89669  *  0b0..No bus error overrun
89670  *  0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.
89671  */
89672 #define MCM_FATR_BEOVR(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
89673 /*! @} */
89674 
89675 /*! @name FDR - Fault data register */
89676 /*! @{ */
89677 #define MCM_FDR_DATA_MASK                        (0xFFFFFFFFU)
89678 #define MCM_FDR_DATA_SHIFT                       (0U)
89679 /*! DATA - Fault data
89680  */
89681 #define MCM_FDR_DATA(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
89682 /*! @} */
89683 
89684 
89685 /*!
89686  * @}
89687  */ /* end of group MCM_Register_Masks */
89688 
89689 
89690 /* MCM - Peripheral instance base addresses */
89691 /** Peripheral MCM base address */
89692 #define MCM_BASE                                 (0xE0080000u)
89693 /** Peripheral MCM base pointer */
89694 #define MCM                                      ((MCM_Type *)MCM_BASE)
89695 /** Array initializer of MCM peripheral base addresses */
89696 #define MCM_BASE_ADDRS                           { MCM_BASE }
89697 /** Array initializer of MCM peripheral base pointers */
89698 #define MCM_BASE_PTRS                            { MCM }
89699 
89700 /*!
89701  * @}
89702  */ /* end of group MCM_Peripheral_Access_Layer */
89703 
89704 
89705 /* ----------------------------------------------------------------------------
89706    -- MIPI_CSI2RX Peripheral Access Layer
89707    ---------------------------------------------------------------------------- */
89708 
89709 /*!
89710  * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer
89711  * @{
89712  */
89713 
89714 /** MIPI_CSI2RX - Register Layout Typedef */
89715 typedef struct {
89716        uint8_t RESERVED_0[256];
89717   __IO uint32_t CSI2RX_CFG_NUM_LANES;              /**< Lane Configuration Register, offset: 0x100 */
89718   __IO uint32_t CSI2RX_CFG_DISABLE_DATA_LANES;     /**< Disable Data Lane Register, offset: 0x104 */
89719   __I  uint32_t CSI2RX_BIT_ERR;                    /**< ECC and CRC Error Status Register, offset: 0x108 */
89720   __I  uint32_t CSI2RX_IRQ_STATUS;                 /**< IRQ Status Register, offset: 0x10C */
89721   __IO uint32_t CSI2RX_IRQ_MASK;                   /**< IRQ Mask Setting Regsiter, offset: 0x110 */
89722   __I  uint32_t CSI2RX_ULPS_STATUS;                /**< ULPS Status Register, offset: 0x114 */
89723   __I  uint32_t CSI2RX_PPI_ERRSOT_HS;              /**< ERRSot HS Status Register, offset: 0x118 */
89724   __I  uint32_t CSI2RX_PPI_ERRSOTSYNC_HS;          /**< ErrSotSync HS Status Register, offset: 0x11C */
89725   __I  uint32_t CSI2RX_PPI_ERRESC;                 /**< ErrEsc Status Register, offset: 0x120 */
89726   __I  uint32_t CSI2RX_PPI_ERRSYNCESC;             /**< ErrSyncEsc Status Register, offset: 0x124 */
89727   __I  uint32_t CSI2RX_PPI_ERRCONTROL;             /**< ErrControl Status Register, offset: 0x128 */
89728   __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_0;      /**< Disable Payload 0 Register, offset: 0x12C */
89729   __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_1;      /**< Disable Payload 1 Register, offset: 0x130 */
89730        uint8_t RESERVED_1[76];
89731   __IO uint32_t CSI2RX_CFG_IGNORE_VC;              /**< Ignore Virtual Channel Register, offset: 0x180 */
89732   __IO uint32_t CSI2RX_CFG_VID_VC;                 /**< Virtual Channel value Register, offset: 0x184 */
89733   __IO uint32_t CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL;  /**< FIFO Send Level Configuration Register, offset: 0x188 */
89734   __IO uint32_t CSI2RX_CFG_VID_VSYNC;              /**< VSYNC Configuration Register, offset: 0x18C */
89735   __IO uint32_t CSI2RX_CFG_VID_HSYNC_FP;           /**< Start of HSYNC Delay control Register, offset: 0x190 */
89736   __IO uint32_t CSI2RX_CFG_VID_HSYNC;              /**< HSYNC Configuration Register, offset: 0x194 */
89737   __IO uint32_t CSI2RX_CFG_VID_HSYNC_BP;           /**< End of HSYNC Delay Control Register, offset: 0x198 */
89738 } MIPI_CSI2RX_Type;
89739 
89740 /* ----------------------------------------------------------------------------
89741    -- MIPI_CSI2RX Register Masks
89742    ---------------------------------------------------------------------------- */
89743 
89744 /*!
89745  * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks
89746  * @{
89747  */
89748 
89749 /*! @name CSI2RX_CFG_NUM_LANES - Lane Configuration Register */
89750 /*! @{ */
89751 #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U)
89752 #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U)
89753 /*! CFG_NUM_LANES - Sets the number of active lanes that are to be used for receiving data.
89754  *  0b00..1 Lane
89755  *  0b01..2 Lane
89756  *  0b10..3 Lane
89757  *  0b11..4 Lane
89758  */
89759 #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK)
89760 /*! @} */
89761 
89762 /*! @name CSI2RX_CFG_DISABLE_DATA_LANES - Disable Data Lane Register */
89763 /*! @{ */
89764 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU)
89765 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U)
89766 /*! CFG_DISABLE_DATA_LANES - Setting bits to a '1' value causes the DPHY Enable signal to deassert.
89767  *  0b0001..Data Lane 0
89768  *  0b0010..Data Lane 1
89769  *  0b0100..Data Lane 2
89770  *  0b1000..Data Lane 3
89771  */
89772 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK)
89773 /*! @} */
89774 
89775 /*! @name CSI2RX_BIT_ERR - ECC and CRC Error Status Register */
89776 /*! @{ */
89777 #define MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_MASK  (0x3FFU)
89778 #define MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_SHIFT (0U)
89779 /*! BIT_ERR - BIT_ERR: CSI-2 RX Controller ECC and CRC error status.
89780  */
89781 #define MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_MASK)
89782 /*! @} */
89783 
89784 /*! @name CSI2RX_IRQ_STATUS - IRQ Status Register */
89785 /*! @{ */
89786 #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK (0x1FFU)
89787 #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT (0U)
89788 /*! IRQ_STATUS - CSI2 RX IRQ status
89789  */
89790 #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK)
89791 /*! @} */
89792 
89793 /*! @name CSI2RX_IRQ_MASK - IRQ Mask Setting Regsiter */
89794 /*! @{ */
89795 #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_MASK (0x1FFU)
89796 #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT (0U)
89797 /*! IRQ_MASK - CSI2 RX IRQ Mask setting
89798  */
89799 #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_MASK)
89800 /*! @} */
89801 
89802 /*! @name CSI2RX_ULPS_STATUS - ULPS Status Register */
89803 /*! @{ */
89804 #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_MASK (0x3FFU)
89805 #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_SHIFT (0U)
89806 /*! STATUS - Status of RX DPHY ULPS state
89807  */
89808 #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_MASK)
89809 /*! @} */
89810 
89811 /*! @name CSI2RX_PPI_ERRSOT_HS - ERRSot HS Status Register */
89812 /*! @{ */
89813 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK (0xFU)
89814 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT (0U)
89815 /*! STATUS - CSI2 RX DPHY PPI ErrSotHS captured status from the DPHY.
89816  */
89817 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK)
89818 /*! @} */
89819 
89820 /*! @name CSI2RX_PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register */
89821 /*! @{ */
89822 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK (0xFU)
89823 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT (0U)
89824 /*! STATUS - CSI2 RX DPHY PPI ErrSotSync_HS captured status from the DPHY.
89825  */
89826 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK)
89827 /*! @} */
89828 
89829 /*! @name CSI2RX_PPI_ERRESC - ErrEsc Status Register */
89830 /*! @{ */
89831 #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_MASK (0xFU)
89832 #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_SHIFT (0U)
89833 /*! STATUS - CSI2 RX DPHY PPI ErrEsc captured status from the DPHY.
89834  */
89835 #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_MASK)
89836 /*! @} */
89837 
89838 /*! @name CSI2RX_PPI_ERRSYNCESC - ErrSyncEsc Status Register */
89839 /*! @{ */
89840 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK (0xFU)
89841 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT (0U)
89842 /*! STATUS - CSI2 RX DPHY PPI ErrSyncEsc captured status from the DPHY.
89843  */
89844 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK)
89845 /*! @} */
89846 
89847 /*! @name CSI2RX_PPI_ERRCONTROL - ErrControl Status Register */
89848 /*! @{ */
89849 #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_MASK (0xFU)
89850 #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT (0U)
89851 /*! STATUS - CSI2 RX DPHY PPI ErrControl captured status from the DPHY.
89852  */
89853 #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_MASK)
89854 /*! @} */
89855 
89856 /*! @name CSI2RX_CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register */
89857 /*! @{ */
89858 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U)
89859 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U)
89860 /*! DIS_PAYLOAD_NULL - Null
89861  */
89862 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK)
89863 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U)
89864 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U)
89865 /*! DIS_PAYLOAD_BLANK - Blank
89866  */
89867 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK)
89868 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U)
89869 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U)
89870 /*! DIS_PAYLOAD_EMBEDDED - Embedded
89871  */
89872 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK)
89873 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U)
89874 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U)
89875 /*! DIS_PAYLOAD_YUV420 - Legacy YUV 420 8 bit
89876  */
89877 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK)
89878 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U)
89879 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U)
89880 /*! DIS_PAYLOAD_YUV422_8BIT - YUV422 8 bit
89881  */
89882 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK)
89883 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_MASK (0x8000U)
89884 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_SHIFT (15U)
89885 /*! DIS_PAYLOAD_YUV422_10BIT - YUV422 10 bit
89886  */
89887 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_MASK)
89888 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U)
89889 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U)
89890 /*! DIS_PAYLOAD_RGB444 - RGB444
89891  */
89892 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK)
89893 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U)
89894 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U)
89895 /*! DIS_PAYLOAD_RGB555 - RGB555
89896  */
89897 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK)
89898 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U)
89899 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U)
89900 /*! DIS_PAYLOAD_RGB565 - RGB565
89901  */
89902 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK)
89903 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U)
89904 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U)
89905 /*! DIS_PAYLOAD_RGB666 - RGB666
89906  */
89907 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK)
89908 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U)
89909 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U)
89910 /*! DIS_PAYLOAD_RGB888 - RGB888
89911  */
89912 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK)
89913 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_MASK (0x1000000U)
89914 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_SHIFT (24U)
89915 /*! DIS_PAYLOAD_RAW6 - RAW6
89916  */
89917 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_MASK)
89918 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7_MASK (0x2000000U)
89919 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7_SHIFT (25U)
89920 /*! DIS_PAYLOAD_RAW7 - RAW7
89921  */
89922 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7_MASK)
89923 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_MASK (0x4000000U)
89924 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_SHIFT (26U)
89925 /*! DIS_PAYLOAD_RAW8 - RAW8
89926  */
89927 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_MASK)
89928 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_MASK (0x8000000U)
89929 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_SHIFT (27U)
89930 /*! DIS_PAYLOAD_RAW10 - RAW10
89931  */
89932 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_MASK)
89933 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_MASK (0x10000000U)
89934 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_SHIFT (28U)
89935 /*! DIS_PAYLOAD_RAW12 - RAW12
89936  */
89937 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_MASK)
89938 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14_MASK (0x20000000U)
89939 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14_SHIFT (29U)
89940 /*! DIS_PAYLOAD_RAW14 - RAW14
89941  */
89942 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14_MASK)
89943 /*! @} */
89944 
89945 /*! @name CSI2RX_CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register */
89946 /*! @{ */
89947 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U)
89948 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U)
89949 /*! DIS_PAYLOAD_UDEF_30 - User defined type 0x31
89950  */
89951 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK)
89952 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U)
89953 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U)
89954 /*! DIS_PAYLOAD_UDEF_31 - User defined type 0x32
89955  */
89956 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK)
89957 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U)
89958 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U)
89959 /*! DIS_PAYLOAD_UDEF_32 - User defined type 0x33
89960  */
89961 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK)
89962 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U)
89963 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U)
89964 /*! DIS_PAYLOAD_UDEF_33 - User defined type 0x34
89965  */
89966 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK)
89967 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U)
89968 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U)
89969 /*! DIS_PAYLOAD_UDEF_34 - User defined type 0x35
89970  */
89971 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK)
89972 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U)
89973 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U)
89974 /*! DIS_PAYLOAD_UDEF_35 - User defined type 0x35
89975  */
89976 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK)
89977 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U)
89978 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U)
89979 /*! DIS_PAYLOAD_UDEF_36 - User defined type 0x36
89980  */
89981 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK)
89982 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U)
89983 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U)
89984 /*! DIS_PAYLOAD_UDEF_37 - User defined type 0x37
89985  */
89986 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK)
89987 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U)
89988 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U)
89989 /*! DIS_PAYLOAD_UNSUPPORTED - Unsupported Data Types
89990  */
89991 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK)
89992 /*! @} */
89993 
89994 /*! @name CSI2RX_CFG_IGNORE_VC - Ignore Virtual Channel Register */
89995 /*! @{ */
89996 #define MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK (0x1U)
89997 #define MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT (0U)
89998 #define MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK)
89999 /*! @} */
90000 
90001 /*! @name CSI2RX_CFG_VID_VC - Virtual Channel value Register */
90002 /*! @{ */
90003 #define MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC_MASK (0x3U)
90004 #define MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC_SHIFT (0U)
90005 #define MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC_MASK)
90006 /*! @} */
90007 
90008 /*! @name CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL - FIFO Send Level Configuration Register */
90009 /*! @{ */
90010 #define MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK (0xFFFFU)
90011 #define MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT (0U)
90012 /*! SEND_LEVEL - FIFO Send Level field
90013  */
90014 #define MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK)
90015 /*! @} */
90016 
90017 /*! @name CSI2RX_CFG_VID_VSYNC - VSYNC Configuration Register */
90018 /*! @{ */
90019 #define MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK (0xFFU)
90020 #define MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT (0U)
90021 /*! WIDTH - Width of VSYNC
90022  */
90023 #define MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK)
90024 /*! @} */
90025 
90026 /*! @name CSI2RX_CFG_VID_HSYNC_FP - Start of HSYNC Delay control Register */
90027 /*! @{ */
90028 #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK (0xFFU)
90029 #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT (0U)
90030 /*! DELAY_CTL - Delay control for beginning of HSYNC pulse
90031  */
90032 #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK)
90033 /*! @} */
90034 
90035 /*! @name CSI2RX_CFG_VID_HSYNC - HSYNC Configuration Register */
90036 /*! @{ */
90037 #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK (0xFFU)
90038 #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT (0U)
90039 /*! WIDTH - Width of HSYNC
90040  */
90041 #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK)
90042 /*! @} */
90043 
90044 /*! @name CSI2RX_CFG_VID_HSYNC_BP - End of HSYNC Delay Control Register */
90045 /*! @{ */
90046 #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK (0xFFU)
90047 #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT (0U)
90048 /*! DELAY_CTL - Delay Control for end of HSYNC pulse
90049  */
90050 #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK)
90051 /*! @} */
90052 
90053 
90054 /*!
90055  * @}
90056  */ /* end of group MIPI_CSI2RX_Register_Masks */
90057 
90058 
90059 /* MIPI_CSI2RX - Peripheral instance base addresses */
90060 /** Peripheral MIPI_CSI__MIPI_CSI2RX base address */
90061 #define MIPI_CSI__MIPI_CSI2RX_BASE               (0x58227000u)
90062 /** Peripheral MIPI_CSI__MIPI_CSI2RX base pointer */
90063 #define MIPI_CSI__MIPI_CSI2RX                    ((MIPI_CSI2RX_Type *)MIPI_CSI__MIPI_CSI2RX_BASE)
90064 /** Array initializer of MIPI_CSI2RX peripheral base addresses */
90065 #define MIPI_CSI2RX_BASE_ADDRS                   { MIPI_CSI__MIPI_CSI2RX_BASE }
90066 /** Array initializer of MIPI_CSI2RX peripheral base pointers */
90067 #define MIPI_CSI2RX_BASE_PTRS                    { MIPI_CSI__MIPI_CSI2RX }
90068 /* Backward compatibility */
90069 #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK        MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK
90070 #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT        MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT
90071 #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes(x)        MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x)
90072 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK        MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK
90073 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT        MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT
90074 #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes(x)        MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x)
90075 #define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK        MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_MASK
90076 #define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT        MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_SHIFT
90077 #define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err(x)        MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR(x)
90078 #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK        MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK
90079 #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT        MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT
90080 #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status(x)        MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS(x)
90081 #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK        MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_MASK
90082 #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT        MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT
90083 #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask(x)        MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK(x)
90084 #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK        MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_MASK
90085 #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT        MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_SHIFT
90086 #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status(x)        MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS(x)
90087 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK        MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK
90088 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT        MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT
90089 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs(x)        MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS(x)
90090 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK        MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK
90091 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT        MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT
90092 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs(x)        MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x)
90093 #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK        MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_MASK
90094 #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT        MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_SHIFT
90095 #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc(x)        MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS(x)
90096 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK        MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK
90097 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT        MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT
90098 #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc(x)        MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS(x)
90099 #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK        MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_MASK
90100 #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT        MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT
90101 #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol(x)        MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS(x)
90102 
90103 
90104 /*!
90105  * @}
90106  */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */
90107 
90108 
90109 /* ----------------------------------------------------------------------------
90110    -- MIPI_CSI_CSR Peripheral Access Layer
90111    ---------------------------------------------------------------------------- */
90112 
90113 /*!
90114  * @addtogroup MIPI_CSI_CSR_Peripheral_Access_Layer MIPI_CSI_CSR Peripheral Access Layer
90115  * @{
90116  */
90117 
90118 /** MIPI_CSI_CSR - Register Layout Typedef */
90119 typedef struct {
90120   __IO uint32_t PLM_CTRL;                          /**< Pixel Link Master (PLM) Control, offset: 0x0 */
90121   __IO uint32_t PHY_CTRL;                          /**< PHY_CTRL are outputs from CSR to the PHY or Controller., offset: 0x4 */
90122   __I  uint32_t PHY_STATUS;                        /**< , offset: 0x8 */
90123        uint8_t RESERVED_0[4];
90124   __I  uint32_t PHY_TEST_STATUS;                   /**< , offset: 0x10 */
90125   __I  uint32_t PHY_TEST_STATUS_D0;                /**< , offset: 0x14 */
90126   __I  uint32_t PHY_TEST_STATUS_D1;                /**< , offset: 0x18 */
90127   __I  uint32_t PHY_TEST_STATUS_D2;                /**< , offset: 0x1C */
90128   __I  uint32_t PHY_TEST_STATUS_D3;                /**< , offset: 0x20 */
90129        uint8_t RESERVED_1[12];
90130   __IO uint32_t VC_INTERLACED;                     /**< , offset: 0x30 */
90131        uint8_t RESERVED_2[4];
90132   __IO uint32_t DATA_TYPE_DISABLE_BF;              /**< , offset: 0x38 */
90133        uint8_t RESERVED_3[4];
90134   __IO uint32_t YUV420_FIRST_LINE_DATA_TYPE;       /**< , offset: 0x40 */
90135   __IO uint32_t CONTROLLER_CLOCK_RESET_CONTROL;    /**< , offset: 0x44 */
90136   __IO uint32_t STREAM_FENCING_CONTROL;            /**< Stream Fencing Control (RW - to Pixel Reformatter), offset: 0x48 */
90137   __I  uint32_t STREAM_FENCING_STATUS;             /**< Stream Fencing Status (RO - from Pixel Reformatter), offset: 0x4C */
90138 } MIPI_CSI_CSR_Type;
90139 
90140 /* ----------------------------------------------------------------------------
90141    -- MIPI_CSI_CSR Register Masks
90142    ---------------------------------------------------------------------------- */
90143 
90144 /*!
90145  * @addtogroup MIPI_CSI_CSR_Register_Masks MIPI_CSI_CSR Register Masks
90146  * @{
90147  */
90148 
90149 /*! @name PLM_CTRL - Pixel Link Master (PLM) Control */
90150 /*! @{ */
90151 #define MIPI_CSI_CSR_PLM_CTRL_ENABLE_MASK        (0x1U)
90152 #define MIPI_CSI_CSR_PLM_CTRL_ENABLE_SHIFT       (0U)
90153 /*! ENABLE - Enable - for pixel link
90154  */
90155 #define MIPI_CSI_CSR_PLM_CTRL_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_ENABLE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_ENABLE_MASK)
90156 #define MIPI_CSI_CSR_PLM_CTRL_ADDR_MASK          (0x6U)
90157 #define MIPI_CSI_CSR_PLM_CTRL_ADDR_SHIFT         (1U)
90158 /*! ADDR - For selecting the destination module that receives the data. Can be defaulted to 0.
90159  */
90160 #define MIPI_CSI_CSR_PLM_CTRL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_ADDR_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_ADDR_MASK)
90161 #define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_MASK (0x200U)
90162 #define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_SHIFT (9U)
90163 /*! VSYNC_OVERIDE - Used to force the Pixel Link Master VSYNC input to be active (MUXed with the
90164  *    functional VSync before entering the PL, e.g. in HVSync Generation module)
90165  */
90166 #define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_MASK)
90167 #define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_MASK (0x400U)
90168 #define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_SHIFT (10U)
90169 /*! HSYNC_OVERIDE - Used to force the Pixel Link Master HSYNC input to be active (MUXed with the
90170  *    functional HSync before entering the PL, e.g. in HVSync Generation module)
90171  */
90172 #define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_MASK)
90173 #define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_MASK (0x800U)
90174 #define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_SHIFT (11U)
90175 /*! VALID_OVERRIDE - Used to drive valid on the Pixel Link (MUXed with the functional valid before
90176  *    entering the PL, e.g. in HVSync Generation module)
90177  */
90178 #define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_MASK)
90179 #define MIPI_CSI_CSR_PLM_CTRL_POLARITY_MASK      (0x1000U)
90180 #define MIPI_CSI_CSR_PLM_CTRL_POLARITY_SHIFT     (12U)
90181 /*! POLARITY - POLARITY
90182  *  0b1..HSYNC and VSYNC signals should be active high
90183  *  0b0..HSYNC and VSYNC signals should be active low. Also a reset value (active low).
90184  */
90185 #define MIPI_CSI_CSR_PLM_CTRL_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_POLARITY_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_POLARITY_MASK)
90186 /*! @} */
90187 
90188 /*! @name PHY_CTRL - PHY_CTRL are outputs from CSR to the PHY or Controller. */
90189 /*! @{ */
90190 #define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_MASK     (0x1U)
90191 #define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_SHIFT    (0U)
90192 /*! RX_ENABLE - RX_ENABLE
90193  */
90194 #define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_MASK)
90195 #define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_MASK    (0x2U)
90196 #define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_SHIFT   (1U)
90197 /*! AUTO_PD_EN - AUTO_PD_EN
90198  */
90199 #define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_MASK)
90200 #define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_MASK     (0x4U)
90201 #define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_SHIFT    (2U)
90202 /*! DDRCLK_EN - DDRCLK_EN
90203  */
90204 #define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_MASK)
90205 #define MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_MASK (0x8U)
90206 #define MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_SHIFT (3U)
90207 /*! CONT_CLK_MODE - CONT_CLK_MODE
90208  */
90209 #define MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_MASK)
90210 #define MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_MASK (0x3F0U)
90211 #define MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_SHIFT (4U)
90212 /*! S_PRG_RXHS_SETTLE - S_PRG_RXHS_SETTLE[5:0]
90213  */
90214 #define MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_MASK)
90215 #define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_MASK     (0x200000U)
90216 #define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_SHIFT    (21U)
90217 /*! RTERM_SEL - RTERM_SEL
90218  */
90219 #define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_MASK)
90220 #define MIPI_CSI_CSR_PHY_CTRL_PD_MASK            (0x400000U)
90221 #define MIPI_CSI_CSR_PHY_CTRL_PD_SHIFT           (22U)
90222 /*! PD - PD
90223  */
90224 #define MIPI_CSI_CSR_PHY_CTRL_PD(x)              (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_PD_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_PD_MASK)
90225 /*! @} */
90226 
90227 /*! @name PHY_STATUS -  */
90228 /*! @{ */
90229 #define MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_MASK (0x1U)
90230 #define MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_SHIFT (0U)
90231 /*! LANES_STOPPED - LANES_STOPPED (csi_controller.ulps_active[4:0] = 5'b0)
90232  */
90233 #define MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_SHIFT)) & MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_MASK)
90234 /*! @} */
90235 
90236 /*! @name PHY_TEST_STATUS -  */
90237 /*! @{ */
90238 #define MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT_MASK (0x3FFU)
90239 #define MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT_SHIFT (0U)
90240 /*! DC_TEST_OUT - DC_TEST_OUT
90241  */
90242 #define MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT_MASK)
90243 /*! @} */
90244 
90245 /*! @name PHY_TEST_STATUS_D0 -  */
90246 /*! @{ */
90247 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT_MASK (0x3FFU)
90248 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT_SHIFT (0U)
90249 /*! LB_D0_ERR_CNT - LB_D0_ERR_CNT[9:0]
90250  */
90251 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT_MASK)
90252 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT_MASK (0xFFC00U)
90253 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT_SHIFT (10U)
90254 /*! LB_D0_BYTE_CNT - LB_D0_BYTE_CNT[9:0]
90255  */
90256 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT_MASK)
90257 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS_MASK (0x300000U)
90258 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS_SHIFT (20U)
90259 /*! D0_LB_PASS - D0_LB_PASS[1:0]
90260  */
90261 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS_MASK)
90262 /*! @} */
90263 
90264 /*! @name PHY_TEST_STATUS_D1 -  */
90265 /*! @{ */
90266 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT_MASK (0x3FFU)
90267 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT_SHIFT (0U)
90268 /*! LB_D1_ERR_CNT - LB_D1_ERR_CNT[9:0]
90269  */
90270 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT_MASK)
90271 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT_MASK (0xFFC00U)
90272 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT_SHIFT (10U)
90273 /*! LB_D1_BYTE_CNT - LB_D1_BYTE_CNT[9:0]
90274  */
90275 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT_MASK)
90276 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS_MASK (0x300000U)
90277 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS_SHIFT (20U)
90278 /*! D1_LB_PASS - D1_LB_PASS[1:0]
90279  */
90280 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS_MASK)
90281 /*! @} */
90282 
90283 /*! @name PHY_TEST_STATUS_D2 -  */
90284 /*! @{ */
90285 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT_MASK (0x3FFU)
90286 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT_SHIFT (0U)
90287 /*! LB_D2_ERR_CNT - LB_D2_ERR_CNT[9:0]
90288  */
90289 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT_MASK)
90290 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT_MASK (0xFFC00U)
90291 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT_SHIFT (10U)
90292 /*! LB_D2_BYTE_CNT - LB_D2_BYTE_CNT[9:0]
90293  */
90294 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT_MASK)
90295 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS_MASK (0x300000U)
90296 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS_SHIFT (20U)
90297 /*! D2_LB_PASS - D2_LB_PASS[1:0]
90298  */
90299 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS_MASK)
90300 /*! @} */
90301 
90302 /*! @name PHY_TEST_STATUS_D3 -  */
90303 /*! @{ */
90304 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT_MASK (0x3FFU)
90305 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT_SHIFT (0U)
90306 /*! LB_D3_ERR_CNT - LB_D3_ERR_CNT[9:0]
90307  */
90308 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT_MASK)
90309 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT_MASK (0xFFC00U)
90310 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT_SHIFT (10U)
90311 /*! LB_D3_BYTE_CNT - LB_D3_BYTE_CNT[9:0]
90312  */
90313 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT_MASK)
90314 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS_MASK (0x300000U)
90315 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS_SHIFT (20U)
90316 /*! D3_LB_PASS - D3_LB_PASS[1:0]
90317  */
90318 #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS_MASK)
90319 /*! @} */
90320 
90321 /*! @name VC_INTERLACED -  */
90322 /*! @{ */
90323 #define MIPI_CSI_CSR_VC_INTERLACED_VC0_MASK      (0x1U)
90324 #define MIPI_CSI_CSR_VC_INTERLACED_VC0_SHIFT     (0U)
90325 /*! VC0
90326  *  0b1..VC0 is interlaced
90327  *  0b0..Default
90328  */
90329 #define MIPI_CSI_CSR_VC_INTERLACED_VC0(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC0_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC0_MASK)
90330 #define MIPI_CSI_CSR_VC_INTERLACED_VC1_MASK      (0x2U)
90331 #define MIPI_CSI_CSR_VC_INTERLACED_VC1_SHIFT     (1U)
90332 /*! VC1
90333  *  0b1..VC1 is interlaced
90334  *  0b0..Default
90335  */
90336 #define MIPI_CSI_CSR_VC_INTERLACED_VC1(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC1_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC1_MASK)
90337 #define MIPI_CSI_CSR_VC_INTERLACED_VC2_MASK      (0x4U)
90338 #define MIPI_CSI_CSR_VC_INTERLACED_VC2_SHIFT     (2U)
90339 /*! VC2
90340  *  0b1..VC2 is interlaced
90341  *  0b0..Default
90342  */
90343 #define MIPI_CSI_CSR_VC_INTERLACED_VC2(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC2_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC2_MASK)
90344 #define MIPI_CSI_CSR_VC_INTERLACED_VC3_MASK      (0x8U)
90345 #define MIPI_CSI_CSR_VC_INTERLACED_VC3_SHIFT     (3U)
90346 /*! VC3
90347  *  0b1..VC3 is interlaced
90348  *  0b0..Default
90349  */
90350 #define MIPI_CSI_CSR_VC_INTERLACED_VC3(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC3_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC3_MASK)
90351 /*! @} */
90352 
90353 /*! @name DATA_TYPE_DISABLE_BF -  */
90354 /*! @{ */
90355 #define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_MASK (0xFFFFFFU)
90356 #define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_SHIFT (0U)
90357 /*! DATA_TYPE_DISABLE - Data Type Disable
90358  */
90359 #define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_SHIFT)) & MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_MASK)
90360 /*! @} */
90361 
90362 /*! @name YUV420_FIRST_LINE_DATA_TYPE -  */
90363 /*! @{ */
90364 #define MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_MASK (0x1U)
90365 #define MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_SHIFT (0U)
90366 /*! YUV420_FIRST_LINE_DATA_TYPE - YUV420_FIRST_LINE_DATA_TYPE
90367  *  0b0..Odd (reset value)
90368  *  0b1..Even
90369  */
90370 #define MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_SHIFT)) & MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_MASK)
90371 /*! @} */
90372 
90373 /*! @name CONTROLLER_CLOCK_RESET_CONTROL -  */
90374 /*! @{ */
90375 #define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_MASK (0x3U)
90376 #define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_SHIFT (0U)
90377 /*! CONTROLLER_CLOCK_RESET_CONTROL - CONTROLLER_CLOCK_RESET_CONTROL
90378  *  0b00..SW_RESETN (reset value is 0)
90379  *  0b01..CTL_CLK_OFF (connect to LPCG) (reset value is 1)
90380  */
90381 #define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_SHIFT)) & MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_MASK)
90382 /*! @} */
90383 
90384 /*! @name STREAM_FENCING_CONTROL - Stream Fencing Control (RW - to Pixel Reformatter) */
90385 /*! @{ */
90386 #define MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_MASK (0xFU)
90387 #define MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_SHIFT (0U)
90388 /*! STREAM_FENCING_CONTROL
90389  *  0b0000..Fence VC0
90390  *  0b0001..Fence VC1
90391  *  0b0010..Fence VC2
90392  *  0b0011..Fence VC3
90393  */
90394 #define MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_SHIFT)) & MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_MASK)
90395 /*! @} */
90396 
90397 /*! @name STREAM_FENCING_STATUS - Stream Fencing Status (RO - from Pixel Reformatter) */
90398 /*! @{ */
90399 #define MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_MASK (0xFU)
90400 #define MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_SHIFT (0U)
90401 /*! STREAM_FENCING_STATUS
90402  *  0b0000..VC0 is fenced
90403  *  0b0001..VC1 is fenced
90404  *  0b0010..VC2 is fenced
90405  *  0b0011..VC3 is fenced
90406  */
90407 #define MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_SHIFT)) & MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_MASK)
90408 /*! @} */
90409 
90410 
90411 /*!
90412  * @}
90413  */ /* end of group MIPI_CSI_CSR_Register_Masks */
90414 
90415 
90416 /* MIPI_CSI_CSR - Peripheral instance base addresses */
90417 /** Peripheral MIPI_CSI_CSR base address */
90418 #define MIPI_CSI_CSR_BASE                        (0x58221000u)
90419 /** Peripheral MIPI_CSI_CSR base pointer */
90420 #define MIPI_CSI_CSR                             ((MIPI_CSI_CSR_Type *)MIPI_CSI_CSR_BASE)
90421 /** Array initializer of MIPI_CSI_CSR peripheral base addresses */
90422 #define MIPI_CSI_CSR_BASE_ADDRS                  { MIPI_CSI_CSR_BASE }
90423 /** Array initializer of MIPI_CSI_CSR peripheral base pointers */
90424 #define MIPI_CSI_CSR_BASE_PTRS                   { MIPI_CSI_CSR }
90425 
90426 /*!
90427  * @}
90428  */ /* end of group MIPI_CSI_CSR_Peripheral_Access_Layer */
90429 
90430 
90431 /* ----------------------------------------------------------------------------
90432    -- MIPI_CSI_LPCG Peripheral Access Layer
90433    ---------------------------------------------------------------------------- */
90434 
90435 /*!
90436  * @addtogroup MIPI_CSI_LPCG_Peripheral_Access_Layer MIPI_CSI_LPCG Peripheral Access Layer
90437  * @{
90438  */
90439 
90440 /** MIPI_CSI_LPCG - Register Layout Typedef */
90441 typedef struct {
90442   __IO uint32_t LPCG_MIPI_CSI_LPCG_0;              /**< na, offset: 0x0 */
90443   __IO uint32_t LPCG_MIPI_CSI_LPCG_4;              /**< na, offset: 0x4 */
90444   __IO uint32_t LPCG_MIPI_CSI_LPCG_8;              /**< na, offset: 0x8 */
90445        uint8_t RESERVED_0[4];
90446   __IO uint32_t LPCG_MIPI_CSI_LPCG_16;             /**< na, offset: 0x10 */
90447   __IO uint32_t LPCG_MIPI_CSI_LPCG_20;             /**< na, offset: 0x14 */
90448   __IO uint32_t LPCG_MIPI_CSI_LPCG_24;             /**< na, offset: 0x18 */
90449   __IO uint32_t LPCG_MIPI_CSI_LPCG_28;             /**< na, offset: 0x1C */
90450 } MIPI_CSI_LPCG_Type;
90451 
90452 /* ----------------------------------------------------------------------------
90453    -- MIPI_CSI_LPCG Register Masks
90454    ---------------------------------------------------------------------------- */
90455 
90456 /*!
90457  * @addtogroup MIPI_CSI_LPCG_Register_Masks MIPI_CSI_LPCG Register Masks
90458  * @{
90459  */
90460 
90461 /*! @name LPCG_MIPI_CSI_LPCG_0 - na */
90462 /*! @{ */
90463 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_MASK (0x1FFFFU)
90464 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_SHIFT (0U)
90465 /*! LPCG_mipi_csi_lpcg_0_reserved_0_16 - reserved
90466  */
90467 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_MASK)
90468 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_MASK (0x20000U)
90469 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_SHIFT (17U)
90470 /*! lis_ipg_clk_SWEN - Software Enable
90471  *  0b0..Disable SW clock regardless of HWEN
90472  *  0b1..Enable SW clock gating
90473  */
90474 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_MASK)
90475 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_MASK (0x40000U)
90476 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_SHIFT (18U)
90477 /*! LPCG_mipi_csi_lpcg_0_reserved_18_18 - reserved
90478  */
90479 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_MASK)
90480 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_MASK (0x80000U)
90481 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_SHIFT (19U)
90482 /*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped
90483  */
90484 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_MASK)
90485 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_MASK (0xFFF00000U)
90486 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_SHIFT (20U)
90487 /*! LPCG_mipi_csi_lpcg_0_reserved_20_31 - reserved
90488  */
90489 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_MASK)
90490 /*! @} */
90491 
90492 /*! @name LPCG_MIPI_CSI_LPCG_4 - na */
90493 /*! @{ */
90494 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_MASK (0x1FFFFU)
90495 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_SHIFT (0U)
90496 /*! LPCG_mipi_csi_lpcg_4_reserved_0_16 - reserved
90497  */
90498 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_MASK)
90499 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_MASK (0x20000U)
90500 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_SHIFT (17U)
90501 /*! mipi_csi_regs_apb_clk_SWEN - Software Enable
90502  *  0b0..Disable SW clock regardless of HWEN
90503  *  0b1..Enable SW clock gating
90504  */
90505 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_MASK)
90506 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_MASK (0x40000U)
90507 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_SHIFT (18U)
90508 /*! LPCG_mipi_csi_lpcg_4_reserved_18_18 - reserved
90509  */
90510 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_MASK)
90511 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_MASK (0x80000U)
90512 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_SHIFT (19U)
90513 /*! mipi_csi_regs_apb_clk_STOP - show clock root status, 1 means clock stopped
90514  */
90515 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_MASK)
90516 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
90517 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_SHIFT (20U)
90518 /*! LPCG_mipi_csi_lpcg_4_reserved_20_31 - reserved
90519  */
90520 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_MASK)
90521 /*! @} */
90522 
90523 /*! @name LPCG_MIPI_CSI_LPCG_8 - na */
90524 /*! @{ */
90525 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_MASK (0xFFFFU)
90526 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_SHIFT (0U)
90527 /*! LPCG_mipi_csi_lpcg_8_reserved_0_15 - reserved
90528  */
90529 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_MASK)
90530 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK (0x10000U)
90531 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT (16U)
90532 /*! gpio_ipg_clk_s_HWEN - Hardware Enable
90533  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
90534  *  0b1..Enable HW automatic gating
90535  */
90536 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK)
90537 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK (0x20000U)
90538 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT (17U)
90539 /*! gpio_ipg_clk_s_SWEN - Software Enable
90540  *  0b0..Disable SW clock regardless of HWEN
90541  *  0b1..Enable SW clock gating
90542  */
90543 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK)
90544 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_MASK (0x40000U)
90545 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_SHIFT (18U)
90546 /*! LPCG_mipi_csi_lpcg_8_reserved_18_18 - reserved
90547  */
90548 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_MASK)
90549 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_MASK (0x80000U)
90550 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT (19U)
90551 /*! gpio_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
90552  */
90553 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_MASK)
90554 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
90555 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_SHIFT (20U)
90556 /*! LPCG_mipi_csi_lpcg_8_reserved_20_31 - reserved
90557  */
90558 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_MASK)
90559 /*! @} */
90560 
90561 /*! @name LPCG_MIPI_CSI_LPCG_16 - na */
90562 /*! @{ */
90563 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_MASK (0x1U)
90564 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_SHIFT (0U)
90565 /*! LPCG_mipi_csi_lpcg_16_reserved_0_0 - reserved
90566  */
90567 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_MASK)
90568 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U)
90569 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U)
90570 /*! pwm_ipg_clk_highfreq_SWEN - Software Enable
90571  *  0b0..Disable SW clock regardless of HWEN
90572  *  0b1..Enable SW clock gating
90573  */
90574 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK)
90575 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_MASK (0x4U)
90576 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_SHIFT (2U)
90577 /*! LPCG_mipi_csi_lpcg_16_reserved_2_2 - reserved
90578  */
90579 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_MASK)
90580 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK (0x8U)
90581 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT (3U)
90582 /*! pwm_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped
90583  */
90584 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK)
90585 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_MASK (0xFFF0U)
90586 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_SHIFT (4U)
90587 /*! LPCG_mipi_csi_lpcg_16_reserved_4_15 - reserved
90588  */
90589 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_MASK)
90590 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK (0x10000U)
90591 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT (16U)
90592 /*! pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN - Hardware Enable
90593  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
90594  *  0b1..Enable HW automatic gating
90595  */
90596 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK)
90597 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U)
90598 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U)
90599 /*! pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN - Software Enable
90600  *  0b0..Disable SW clock regardless of HWEN
90601  *  0b1..Enable SW clock gating
90602  */
90603 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK)
90604 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_MASK (0x40000U)
90605 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_SHIFT (18U)
90606 /*! LPCG_mipi_csi_lpcg_16_reserved_18_18 - reserved
90607  */
90608 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_MASK)
90609 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U)
90610 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U)
90611 /*! pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
90612  */
90613 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK)
90614 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
90615 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_SHIFT (20U)
90616 /*! LPCG_mipi_csi_lpcg_16_reserved_20_31 - reserved
90617  */
90618 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_MASK)
90619 /*! @} */
90620 
90621 /*! @name LPCG_MIPI_CSI_LPCG_20 - na */
90622 /*! @{ */
90623 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_MASK (0x1U)
90624 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_SHIFT (0U)
90625 /*! lpi2c_lpi2c_div_clk_HWEN - Hardware Enable
90626  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
90627  *  0b1..Enable HW automatic gating
90628  */
90629 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_MASK)
90630 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_MASK (0x2U)
90631 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_SHIFT (1U)
90632 /*! lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN - Software Enable
90633  *  0b0..Disable SW clock regardless of HWEN
90634  *  0b1..Enable SW clock gating
90635  */
90636 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_MASK)
90637 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_MASK (0x4U)
90638 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_SHIFT (2U)
90639 /*! LPCG_mipi_csi_lpcg_20_reserved_2_2 - reserved
90640  */
90641 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_MASK)
90642 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_MASK (0x8U)
90643 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_SHIFT (3U)
90644 /*! lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
90645  */
90646 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_MASK)
90647 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_MASK (0xFFF0U)
90648 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_SHIFT (4U)
90649 /*! LPCG_mipi_csi_lpcg_20_reserved_4_15 - reserved
90650  */
90651 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_MASK)
90652 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_MASK (0x10000U)
90653 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_SHIFT (16U)
90654 /*! lpi2c_ipg_clk_s_HWEN - Hardware Enable
90655  *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
90656  *  0b1..Enable HW automatic gating
90657  */
90658 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_MASK)
90659 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_MASK (0x20000U)
90660 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_SHIFT (17U)
90661 /*! lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN - Software Enable
90662  *  0b0..Disable SW clock regardless of HWEN
90663  *  0b1..Enable SW clock gating
90664  */
90665 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_MASK)
90666 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_MASK (0x40000U)
90667 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_SHIFT (18U)
90668 /*! LPCG_mipi_csi_lpcg_20_reserved_18_18 - reserved
90669  */
90670 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_MASK)
90671 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_MASK (0x80000U)
90672 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_SHIFT (19U)
90673 /*! lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
90674  */
90675 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_MASK)
90676 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_MASK (0xFFF00000U)
90677 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_SHIFT (20U)
90678 /*! LPCG_mipi_csi_lpcg_20_reserved_20_31 - reserved
90679  */
90680 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_MASK)
90681 /*! @} */
90682 
90683 /*! @name LPCG_MIPI_CSI_LPCG_24 - na */
90684 /*! @{ */
90685 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_MASK (0x1U)
90686 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_SHIFT (0U)
90687 /*! LPCG_mipi_csi_lpcg_24_reserved_0_0 - reserved
90688  */
90689 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_MASK)
90690 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_MASK (0x2U)
90691 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_SHIFT (1U)
90692 /*! csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN - Software Enable
90693  *  0b0..Disable SW clock regardless of HWEN
90694  *  0b1..Enable SW clock gating
90695  */
90696 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_MASK)
90697 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_MASK (0x4U)
90698 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_SHIFT (2U)
90699 /*! LPCG_mipi_csi_lpcg_24_reserved_2_2 - reserved
90700  */
90701 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_MASK)
90702 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_MASK (0x8U)
90703 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_SHIFT (3U)
90704 /*! csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP - show clock root status, 1 means clock stopped
90705  */
90706 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_MASK)
90707 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U)
90708 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_SHIFT (4U)
90709 /*! LPCG_mipi_csi_lpcg_24_reserved_4_31 - reserved
90710  */
90711 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_MASK)
90712 /*! @} */
90713 
90714 /*! @name LPCG_MIPI_CSI_LPCG_28 - na */
90715 /*! @{ */
90716 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_MASK (0x1U)
90717 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_SHIFT (0U)
90718 /*! LPCG_mipi_csi_lpcg_28_reserved_0_0 - reserved
90719  */
90720 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_MASK)
90721 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_MASK (0x2U)
90722 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_SHIFT (1U)
90723 /*! csi2_rx_top_clk_esc_SWEN - Software Enable
90724  *  0b0..Disable SW clock regardless of HWEN
90725  *  0b1..Enable SW clock gating
90726  */
90727 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_MASK)
90728 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_MASK (0x4U)
90729 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_SHIFT (2U)
90730 /*! LPCG_mipi_csi_lpcg_28_reserved_2_2 - reserved
90731  */
90732 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_MASK)
90733 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_MASK (0x8U)
90734 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_SHIFT (3U)
90735 /*! csi2_rx_top_clk_esc_STOP - show clock root status, 1 means clock stopped
90736  */
90737 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_MASK)
90738 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U)
90739 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_SHIFT (4U)
90740 /*! LPCG_mipi_csi_lpcg_28_reserved_4_31 - reserved
90741  */
90742 #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_MASK)
90743 /*! @} */
90744 
90745 
90746 /*!
90747  * @}
90748  */ /* end of group MIPI_CSI_LPCG_Register_Masks */
90749 
90750 
90751 /* MIPI_CSI_LPCG - Peripheral instance base addresses */
90752 /** Peripheral MIPI_CSI__LPCG_CLK base address */
90753 #define MIPI_CSI__LPCG_CLK_BASE                  (0x58223000u)
90754 /** Peripheral MIPI_CSI__LPCG_CLK base pointer */
90755 #define MIPI_CSI__LPCG_CLK                       ((MIPI_CSI_LPCG_Type *)MIPI_CSI__LPCG_CLK_BASE)
90756 /** Array initializer of MIPI_CSI_LPCG peripheral base addresses */
90757 #define MIPI_CSI_LPCG_BASE_ADDRS                 { MIPI_CSI__LPCG_CLK_BASE }
90758 /** Array initializer of MIPI_CSI_LPCG peripheral base pointers */
90759 #define MIPI_CSI_LPCG_BASE_PTRS                  { MIPI_CSI__LPCG_CLK }
90760 
90761 /*!
90762  * @}
90763  */ /* end of group MIPI_CSI_LPCG_Peripheral_Access_Layer */
90764 
90765 
90766 /* ----------------------------------------------------------------------------
90767    -- MIPI_DSI_HOST Peripheral Access Layer
90768    ---------------------------------------------------------------------------- */
90769 
90770 /*!
90771  * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer
90772  * @{
90773  */
90774 
90775 /** MIPI_DSI_HOST - Register Layout Typedef */
90776 typedef struct {
90777   __IO uint32_t DSI_HOST_CFG_NUM_LANES;            /**< , offset: 0x0 */
90778   __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK;    /**< , offset: 0x4 */
90779   __IO uint32_t DSI_HOST_CFG_T_PRE;                /**< , offset: 0x8 */
90780   __IO uint32_t DSI_HOST_CFG_T_POST;               /**< , offset: 0xC */
90781   __IO uint32_t DSI_HOST_CFG_TX_GAP;               /**< , offset: 0x10 */
90782   __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP;      /**< , offset: 0x14 */
90783   __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< , offset: 0x18 */
90784   __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT;         /**< , offset: 0x1C */
90785   __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT;       /**< , offset: 0x20 */
90786   __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT;       /**< , offset: 0x24 */
90787   __IO uint32_t DSI_HOST_CFG_TWAKEUP;              /**< , offset: 0x28 */
90788   __I  uint32_t DSI_HOST_CFG_STATUS_OUT;           /**< , offset: 0x2C */
90789   __I  uint32_t DSI_HOST_RX_ERROR_STATUS;          /**< , offset: 0x30 */
90790        uint8_t RESERVED_0[460];
90791   __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x200 */
90792   __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x204 */
90793   __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< , offset: 0x208 */
90794   __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT;     /**< , offset: 0x20C */
90795   __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY;   /**< , offset: 0x210 */
90796   __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY;   /**< , offset: 0x214 */
90797   __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE;       /**< , offset: 0x218 */
90798   __IO uint32_t DSI_HOST_CFG_DPI_HFP;              /**< , offset: 0x21C */
90799   __IO uint32_t DSI_HOST_CFG_DPI_HBP;              /**< , offset: 0x220 */
90800   __IO uint32_t DSI_HOST_CFG_DPI_HSA;              /**< , offset: 0x224 */
90801   __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< , offset: 0x228 */
90802   __IO uint32_t DSI_HOST_CFG_DPI_VBP;              /**< , offset: 0x22C */
90803   __IO uint32_t DSI_HOST_CFG_DPI_VFP;              /**< , offset: 0x230 */
90804   __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE;        /**< , offset: 0x234 */
90805   __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< , offset: 0x238 */
90806   __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE;          /**< , offset: 0x23C */
90807   __IO uint32_t DSI_HOST_CFG_DPI_VC;               /**< , offset: 0x240 */
90808        uint8_t RESERVED_1[60];
90809   __IO uint32_t DSI_HOST_TX_PAYLOAD;               /**< , offset: 0x280 */
90810   __IO uint32_t DSI_HOST_PKT_CONTROL;              /**< , offset: 0x284 */
90811   __IO uint32_t DSI_HOST_SEND_PACKET;              /**< , offset: 0x288 */
90812   __I  uint32_t DSI_HOST_PKT_STATUS;               /**< , offset: 0x28C */
90813   __I  uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL;        /**< , offset: 0x290 */
90814   __I  uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL;        /**< , offset: 0x294 */
90815   __I  uint32_t DSI_HOST_PKT_RX_PAYLOAD;           /**< , offset: 0x298 */
90816   __I  uint32_t DSI_HOST_PKT_RX_PKT_HEADER;        /**< , offset: 0x29C */
90817   __I  uint32_t DSI_HOST_IRQ_STATUS;               /**< , offset: 0x2A0 */
90818   __I  uint32_t DSI_HOST_IRQ_STATUS2;              /**< , offset: 0x2A4 */
90819   __IO uint32_t DSI_HOST_IRQ_MASK;                 /**< , offset: 0x2A8 */
90820   __IO uint32_t DSI_HOST_IRQ_MASK2;                /**< , offset: 0x2AC */
90821        uint8_t RESERVED_2[80];
90822   __IO uint32_t DPHY_PD_TX;                        /**< , offset: 0x300 */
90823   __IO uint32_t DPHY_M_PRG_HS_PREPARE;             /**< , offset: 0x304 */
90824   __IO uint32_t DPHY_MC_PRG_HS_PREPARE;            /**< , offset: 0x308 */
90825   __IO uint32_t DPHY_M_PRG_HS_ZERO;                /**< , offset: 0x30C */
90826   __IO uint32_t DPHY_MC_PRG_HS_ZERO;               /**< , offset: 0x310 */
90827   __IO uint32_t DPHY_M_PRG_HS_TRAIL;               /**< , offset: 0x314 */
90828   __IO uint32_t DPHY_MC_PRG_HS_TRAIL;              /**< , offset: 0x318 */
90829   __IO uint32_t DPHY_PD_PLL;                       /**< , offset: 0x31C */
90830   __IO uint32_t DPHY_TST;                          /**< , offset: 0x320 */
90831   __IO uint32_t DPHY_CN;                           /**< , offset: 0x324 */
90832   __IO uint32_t DPHY_CM;                           /**< , offset: 0x328 */
90833   __IO uint32_t DPHY_CO;                           /**< , offset: 0x32C */
90834   __I  uint32_t DPHY_LOCK;                         /**< , offset: 0x330 */
90835   __IO uint32_t DPHY_LOCK_BYP;                     /**< , offset: 0x334 */
90836   __IO uint32_t DPHY_TX_RCAL;                      /**< , offset: 0x338 */
90837   __IO uint32_t DPHY_AUTO_PD_EN;                   /**< , offset: 0x33C */
90838   __IO uint32_t DPHY_RXLPRP;                       /**< , offset: 0x340 */
90839   __IO uint32_t DPHY_RXCDRP;                       /**< , offset: 0x344 */
90840 } MIPI_DSI_HOST_Type;
90841 
90842 /* ----------------------------------------------------------------------------
90843    -- MIPI_DSI_HOST Register Masks
90844    ---------------------------------------------------------------------------- */
90845 
90846 /*!
90847  * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks
90848  * @{
90849  */
90850 
90851 /*! @name DSI_HOST_CFG_NUM_LANES -  */
90852 /*! @{ */
90853 #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U)
90854 #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U)
90855 /*! dsi_host_cfg_num_lanes - Sets the number of active lanes that are to be used for transmitting data.
90856  *  0b00..1 lane
90857  *  0b01..2 lanes
90858  *  0b10..3 lanes
90859  *  0b11..4 lanes
90860  */
90861 #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK)
90862 #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_MASK (0xFFFFFFFCU)
90863 #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_SHIFT (2U)
90864 /*! reserved - reserved
90865  */
90866 #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_MASK)
90867 /*! @} */
90868 
90869 /*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK -  */
90870 /*! @{ */
90871 #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U)
90872 #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U)
90873 /*! dsi_host_cfg_noncontinuous_clk - Sets the Host Controller into non-continuous MIPI clock mode.
90874  *    When in non-continuous clock mode, the high speed clock will transistion into low power mode
90875  *    between transmissions.
90876  *  0b0..Continuous high speed clock
90877  *  0b1..Non-Continuous high speed clock
90878  */
90879 #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK)
90880 #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_MASK (0xFFFFFFFEU)
90881 #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_SHIFT (1U)
90882 /*! reserved - reserved
90883  */
90884 #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_MASK)
90885 /*! @} */
90886 
90887 /*! @name DSI_HOST_CFG_T_PRE -  */
90888 /*! @{ */
90889 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0xFFU)
90890 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U)
90891 /*! dsi_host_cfg_t_pre - Sets the number of byte clock periods ('clk_byte' input) that the
90892  *    controller will wait after enabling the clock lane for HS operation before enabling the data lanes for
90893  *    HS operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value
90894  *    for this port is 1.
90895  */
90896 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK)
90897 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_MASK (0xFFFFFF00U)
90898 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_SHIFT (8U)
90899 /*! reserved - reserved
90900  */
90901 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_MASK)
90902 /*! @} */
90903 
90904 /*! @name DSI_HOST_CFG_T_POST -  */
90905 /*! @{ */
90906 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0xFFU)
90907 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U)
90908 /*! dsi_host_cfg_t_post - Sets the number of byte clock periods ('clk_byte' input) to wait before
90909  *    putting the clock lane into LP mode after the data lanes have been detected to be in Stop State.
90910  *    This setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE
90911  *    requirement for the clock lane before the data lane is allowed to change from LP11 to start a
90912  *    high speed transmission. The minimum value for this port is 1.
90913  */
90914 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK)
90915 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_MASK (0xFFFFFF00U)
90916 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_SHIFT (8U)
90917 /*! reserved - reserved
90918  */
90919 #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_MASK)
90920 /*! @} */
90921 
90922 /*! @name DSI_HOST_CFG_TX_GAP -  */
90923 /*! @{ */
90924 #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK (0xFFU)
90925 #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT (0U)
90926 /*! dsi_host_cfg_tx_gap - Sets the number of byte clock periods ('clk_byte' input) that the
90927  *    controller will wait after the clock lane has been put into LP mode before enabling the clock lane for
90928  *    HS mode again. This setting represents the THS-EXIT DPHY timing parameter. The minimum value
90929  *    for this port is 1.
90930  */
90931 #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK)
90932 #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_MASK (0xFFFFFF00U)
90933 #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_SHIFT (8U)
90934 /*! reserved - reserved
90935  */
90936 #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_MASK)
90937 /*! @} */
90938 
90939 /*! @name DSI_HOST_CFG_AUTOINSERT_EOTP -  */
90940 /*! @{ */
90941 #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U)
90942 #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U)
90943 /*! dsi_host_cfg_autoinsert_eotp - Enables the Host Controller to automatically insert an EoTp short
90944  *    packet when switching from HS to LP mode. 1'b0 - EoTp is not automatically inserted 1'b1 -
90945  *    EoTp is automatically inserted
90946  */
90947 #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK)
90948 #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_MASK (0xFFFFFFFEU)
90949 #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_SHIFT (1U)
90950 /*! reserved - reserved
90951  */
90952 #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_MASK)
90953 /*! @} */
90954 
90955 /*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP -  */
90956 /*! @{ */
90957 #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU)
90958 #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U)
90959 /*! dsi_host_cfg_extra_cmds_after_eotp - Configures the DSI Host Controller to send extra End Of
90960  *    Transmission Packets after the end of a packet. The value is the number of extra EOTP packets
90961  *    sent.
90962  */
90963 #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK)
90964 #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_MASK (0xFFFFFF00U)
90965 #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_SHIFT (8U)
90966 /*! reserved - reserved
90967  */
90968 #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_MASK)
90969 /*! @} */
90970 
90971 /*! @name DSI_HOST_CFG_HTX_TO_COUNT -  */
90972 /*! @{ */
90973 #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU)
90974 #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U)
90975 /*! dsi_host_cfg_htx_to_count - Sets the value of the DSI Host High Speed TX timeout count in
90976  *    clk_byte clock periods that once reached will initiate a timeout error and follow the recovery
90977  *    procedure documented in the DSI specification.
90978  */
90979 #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK)
90980 #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_MASK (0xFF000000U)
90981 #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_SHIFT (24U)
90982 /*! reserved - reserved
90983  */
90984 #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_MASK)
90985 /*! @} */
90986 
90987 /*! @name DSI_HOST_CFG_LRX_H_TO_COUNT -  */
90988 /*! @{ */
90989 #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU)
90990 #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U)
90991 /*! dsi_host_cfg_lrx_h_to_count - Sets the value of the DSI Host low power RX timeout count in
90992  *    clk_byte clock periods that once reached will initiate a timeout error and follow the recovery
90993  *    procedure documented in the DSI specification.
90994  */
90995 #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK)
90996 #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_MASK (0xFF000000U)
90997 #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_SHIFT (24U)
90998 /*! reserved - reserved
90999  */
91000 #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_MASK)
91001 /*! @} */
91002 
91003 /*! @name DSI_HOST_CFG_BTA_H_TO_COUNT -  */
91004 /*! @{ */
91005 #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU)
91006 #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U)
91007 /*! dsi_host_cfg_bta_h_to_count - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in
91008  *    clk_byte clock periods that once reached will initiate a timeout error.
91009  */
91010 #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK)
91011 #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_MASK (0xFF000000U)
91012 #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_SHIFT (24U)
91013 /*! reserved - reserved
91014  */
91015 #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_MASK)
91016 /*! @} */
91017 
91018 /*! @name DSI_HOST_CFG_TWAKEUP -  */
91019 /*! @{ */
91020 #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK (0x7FFFFU)
91021 #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT (0U)
91022 /*! dsi_host_cfg_twakeup - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods
91023  *    to keep a clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a
91024  *    minimum of 1ms in Mark-1 state after leaving ULPS.
91025  */
91026 #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK)
91027 #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_MASK (0xFFF80000U)
91028 #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_SHIFT (19U)
91029 /*! reserved - reserved
91030  */
91031 #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_MASK)
91032 /*! @} */
91033 
91034 /*! @name DSI_HOST_CFG_STATUS_OUT -  */
91035 /*! @{ */
91036 #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK (0xFFFFFFFFU)
91037 #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT (0U)
91038 /*! dsi_host_cfg_status_out - Status Register
91039  */
91040 #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK)
91041 /*! @} */
91042 
91043 /*! @name DSI_HOST_RX_ERROR_STATUS -  */
91044 /*! @{ */
91045 #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU)
91046 #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U)
91047 /*! dsi_host_rx_error_status - Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators.
91048  *  0b00000000000..ECC single bit error detected
91049  *  0b00000000001..ECC multi bit error detected
91050  *  0b00000000010-0b00000000110..Errored bit position for single bit ECC error
91051  *  0b00000000111..CRC error detected
91052  *  0b00000001000..High Speed forward TX timeout detected
91053  *  0b00000001001..Reverse Low power data receive timeout detected
91054  *  0b00000001010..BTA timeout detected
91055  */
91056 #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK)
91057 #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_MASK (0xFFFFF800U)
91058 #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_SHIFT (11U)
91059 /*! reserved - reserved
91060  */
91061 #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_MASK)
91062 /*! @} */
91063 
91064 /*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE -  */
91065 /*! @{ */
91066 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU)
91067 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U)
91068 /*! dsi_host_cfg_dpi_pixel_payload_size - Maximum number of pixels that should be sent as one DSI
91069  *    packet. Recommended to be evenly divisible by the line size (in pixels).
91070  */
91071 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK)
91072 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_MASK (0xFFFF0000U)
91073 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT (16U)
91074 /*! reserved - reserved
91075  */
91076 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_MASK)
91077 /*! @} */
91078 
91079 /*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL -  */
91080 /*! @{ */
91081 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU)
91082 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U)
91083 /*! dsi_host_cfg_dpi_pixel_fifo_send_level - In order to optimize DSI utility, the DPI bridge
91084  *    buffers a cerntain number of DPI pixels before initiating a DSI packet. This configuration port
91085  *    controls the level at which the DPI Host bridge begins sending pixels.
91086  */
91087 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK)
91088 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK (0xFFFF0000U)
91089 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT (16U)
91090 /*! reserved - reserved
91091  */
91092 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK)
91093 /*! @} */
91094 
91095 /*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING -  */
91096 /*! @{ */
91097 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U)
91098 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U)
91099 /*! dsi_host_cfg_dpi_interface_color_coding - Sets the distribution of RGB bits within the 24-bit d
91100  *    bus, as specified by the DPI specification. 0= 16-bit Configuration 1 1= 16-bit Configuration
91101  *    2 2= 16-bit Configuration 3 3= 18-bit Configuration 1 4= 18-bit Configuration 2 5= 24-bit
91102  *  0b000..16-bit Configuration 1
91103  *  0b001..16-bit Configuration 2
91104  *  0b010..16-bit Configuration 3
91105  *  0b011..18-bit Configuration 1
91106  *  0b100..18-bit Configuration 2
91107  *  0b101..24-bit
91108  */
91109 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK)
91110 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_MASK (0xFFFFFFF8U)
91111 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_SHIFT (3U)
91112 /*! reserved - reserved
91113  */
91114 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_MASK)
91115 /*! @} */
91116 
91117 /*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT -  */
91118 /*! @{ */
91119 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U)
91120 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U)
91121 /*! dsi_host_cfg_dpi_pixel_format - Sets the DSI packet type of the pixels.
91122  *  0b00..16 bit
91123  *  0b01..18 bit
91124  *  0b10..18 bit loosely packed
91125  *  0b11..24 bit
91126  */
91127 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK)
91128 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_MASK (0xFFFFFFFCU)
91129 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_SHIFT (2U)
91130 /*! reserved - reserved
91131  */
91132 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_MASK)
91133 /*! @} */
91134 
91135 /*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY -  */
91136 /*! @{ */
91137 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U)
91138 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U)
91139 /*! dsi_host_cfg_dpi_vsync_polarity - Sets polarity of dpi_vsync_input 0 - active low 1 - active high
91140  */
91141 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK)
91142 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_MASK (0xFFFFFFFEU)
91143 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_SHIFT (1U)
91144 /*! reserved - reserved
91145  */
91146 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_MASK)
91147 /*! @} */
91148 
91149 /*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY -  */
91150 /*! @{ */
91151 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U)
91152 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U)
91153 /*! dsi_host_cfg_dpi_hsync_polarity - Sets polarity of dpi_hsync_input.
91154  *  0b0..active low
91155  *  0b1..active high
91156  */
91157 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK)
91158 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_MASK (0xFFFFFFFEU)
91159 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_SHIFT (1U)
91160 /*! reserved - reserved
91161  */
91162 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_MASK)
91163 /*! @} */
91164 
91165 /*! @name DSI_HOST_CFG_DPI_VIDEO_MODE -  */
91166 /*! @{ */
91167 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U)
91168 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U)
91169 /*! dsi_host_cfg_dpi_video_mode - Select DSI video mode that the host DPI module should generate packets for.
91170  *  0b00..Non-Burst mode with Sync Pulses
91171  *  0b01..Non-Burst mode with Sync Events
91172  *  0b10..Burst mode
91173  *  0b11..Reserved, not valid
91174  */
91175 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK)
91176 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_MASK (0xFFFFFFFCU)
91177 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_SHIFT (2U)
91178 /*! reserved - reserved
91179  */
91180 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_MASK)
91181 /*! @} */
91182 
91183 /*! @name DSI_HOST_CFG_DPI_HFP -  */
91184 /*! @{ */
91185 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU)
91186 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U)
91187 /*! dsi_host_cfg_dpi_hfp - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet.
91188  */
91189 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK)
91190 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_MASK (0xFFFF0000U)
91191 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_SHIFT (16U)
91192 /*! reserved - reserved
91193  */
91194 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_MASK)
91195 /*! @} */
91196 
91197 /*! @name DSI_HOST_CFG_DPI_HBP -  */
91198 /*! @{ */
91199 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU)
91200 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U)
91201 /*! dsi_host_cfg_dpi_hbp - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet.
91202  */
91203 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK)
91204 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_MASK (0xFFFF0000U)
91205 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_SHIFT (16U)
91206 /*! reserved - reserved
91207  */
91208 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_MASK)
91209 /*! @} */
91210 
91211 /*! @name DSI_HOST_CFG_DPI_HSA -  */
91212 /*! @{ */
91213 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU)
91214 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U)
91215 /*! dsi_host_cfg_dpi_hsa - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet.
91216  */
91217 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK)
91218 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_MASK (0xFFFF0000U)
91219 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_SHIFT (16U)
91220 /*! reserved - reserved
91221  */
91222 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_MASK)
91223 /*! @} */
91224 
91225 /*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS -  */
91226 /*! @{ */
91227 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U)
91228 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U)
91229 /*! dsi_host_cfg_dpi_enable_mult_pkts - Enable Multiple packets per video line. When enabled,
91230  *    cfg_dpi_pixel_payload_size must be set to exactly half the size of the video line.
91231  *  0b0..Video Line is sent in a single packet
91232  *  0b1..Video Line is sent in two packets
91233  */
91234 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK)
91235 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_MASK (0xFFFFFFFEU)
91236 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_SHIFT (1U)
91237 /*! reserved - reserved
91238  */
91239 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_MASK)
91240 /*! @} */
91241 
91242 /*! @name DSI_HOST_CFG_DPI_VBP -  */
91243 /*! @{ */
91244 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU)
91245 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U)
91246 /*! dsi_host_cfg_dpi_vbp - Sets the number of lines in the vertical back porch.
91247  */
91248 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK)
91249 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_MASK (0xFFFFFF00U)
91250 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_SHIFT (8U)
91251 /*! reserved - reserved
91252  */
91253 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_MASK)
91254 /*! @} */
91255 
91256 /*! @name DSI_HOST_CFG_DPI_VFP -  */
91257 /*! @{ */
91258 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU)
91259 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U)
91260 /*! dsi_host_cfg_dpi_vfp - Sets the number of lines in the vertical front porch.
91261  */
91262 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK)
91263 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_MASK (0xFFFFFF00U)
91264 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_SHIFT (8U)
91265 /*! reserved - reserved
91266  */
91267 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_MASK)
91268 /*! @} */
91269 
91270 /*! @name DSI_HOST_CFG_DPI_BLLP_MODE -  */
91271 /*! @{ */
91272 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U)
91273 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U)
91274 /*! dsi_host_cfg_dpi_bllp_mode - Optimize bllp periods to Low Power mode when possible.
91275  *  0b0..Blanking packets are sent during BLLP periods
91276  *  0b1..LP mode is used for BLLP periods
91277  */
91278 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK)
91279 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_MASK (0xFFFFFFFEU)
91280 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_SHIFT (1U)
91281 /*! reserved - reserved
91282  */
91283 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_MASK)
91284 /*! @} */
91285 
91286 /*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP -  */
91287 /*! @{ */
91288 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U)
91289 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U)
91290 /*! dsi_host_cfg_dpi_use_null_pkt_bllp - Selects type of blanking packet to be sent during bllp region.
91291  *  0b0..Blanking packet used in bllp region 1
91292  *  0b1..Null packet used in bllp region
91293  */
91294 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK)
91295 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_MASK (0xFFFFFFFEU)
91296 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_SHIFT (1U)
91297 /*! reserved - reserved
91298  */
91299 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_MASK)
91300 /*! @} */
91301 
91302 /*! @name DSI_HOST_CFG_DPI_VACTIVE -  */
91303 /*! @{ */
91304 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU)
91305 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U)
91306 /*! dsi_host_cfg_dpi_vactive - Sets the number of lines in the vertical active aread.
91307  */
91308 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK)
91309 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_MASK (0xFFFFC000U)
91310 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_SHIFT (14U)
91311 /*! reserved - reserved
91312  */
91313 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_MASK)
91314 /*! @} */
91315 
91316 /*! @name DSI_HOST_CFG_DPI_VC -  */
91317 /*! @{ */
91318 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U)
91319 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U)
91320 /*! dsi_host_cfg_dpi_vc - Sets the Virtual Channel (VC) of packets that will be sent to the receive
91321  *    packet interface. Packets with VC not equal to this value are discarded and the "DSI VC ID
91322  *    Invalid" bit (bit 12) in the DSI error report is set.
91323  */
91324 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK)
91325 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_MASK (0xFFFFFFFCU)
91326 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_SHIFT (2U)
91327 /*! reserved - reserved
91328  */
91329 #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_MASK)
91330 /*! @} */
91331 
91332 /*! @name DSI_HOST_TX_PAYLOAD -  */
91333 /*! @{ */
91334 #define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU)
91335 #define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U)
91336 /*! dsi_host_tx_payload - Tx Payload data write register. Writes to this registers load the payload fifo with 32 bit values.
91337  */
91338 #define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK)
91339 /*! @} */
91340 
91341 /*! @name DSI_HOST_PKT_CONTROL -  */
91342 /*! @{ */
91343 #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU)
91344 #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U)
91345 /*! dsi_host_pkt_control - Tx packet control register.
91346  *  0b000000000000000000000000000-0b000000000000000000000001111..Packet word count
91347  *  0b000000000000000000000010000-0b000000000000000000000010001..Packet Virtual Channel
91348  *  0b000000000000000000000010010-0b000000000000000000000010111..Packet Header DSI Data Type
91349  *  0b000000000000000000000011000..Lp or HS select
91350  *  0b000000000000000000000011001..perform BTA after packet is sent
91351  *  0b000000000000000000000011010..perform BTA only, no packet tx
91352  */
91353 #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK)
91354 #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_MASK (0xF8000000U)
91355 #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_SHIFT (27U)
91356 /*! reserved - reserved
91357  */
91358 #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_MASK)
91359 /*! @} */
91360 
91361 /*! @name DSI_HOST_SEND_PACKET -  */
91362 /*! @{ */
91363 #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U)
91364 #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U)
91365 /*! dsi_host_send_packet - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent.
91366  */
91367 #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK)
91368 #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_MASK (0xFFFFFFFEU)
91369 #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_SHIFT (1U)
91370 /*! reserved - reserved
91371  */
91372 #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_MASK)
91373 /*! @} */
91374 
91375 /*! @name DSI_HOST_PKT_STATUS -  */
91376 /*! @{ */
91377 #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU)
91378 #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U)
91379 /*! dsi_host_pkt_status - Status of APB to packet interface.
91380  *  0b000000000..state machine not idle
91381  *  0b000000001..Tx packet done
91382  *  0b000000010..dphy direction
91383  *  0b000000011..tx fifo overflow
91384  *  0b000000100..tx fifo underflow
91385  *  0b000000101..rx fifo overflow
91386  *  0b000000110..rx fifo underflow
91387  *  0b000000111..rx packet header has been received
91388  *  0b000001000..all rx packet payload data has been received
91389  */
91390 #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK)
91391 #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_MASK (0xFFFFFE00U)
91392 #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_SHIFT (9U)
91393 /*! reserved - reserved
91394  */
91395 #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_MASK)
91396 /*! @} */
91397 
91398 /*! @name DSI_HOST_PKT_FIFO_WR_LEVEL -  */
91399 /*! @{ */
91400 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU)
91401 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U)
91402 /*! dsi_host_pkt_fifo_wr_level - Write level of APB to pkt interface fifo
91403  */
91404 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK)
91405 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_MASK (0xFFFF0000U)
91406 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_SHIFT (16U)
91407 /*! reserved - reserved
91408  */
91409 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_MASK)
91410 /*! @} */
91411 
91412 /*! @name DSI_HOST_PKT_FIFO_RD_LEVEL -  */
91413 /*! @{ */
91414 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU)
91415 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U)
91416 /*! dsi_host_pkt_fifo_rd_level - Read level of APB to pkt interface fifo
91417  */
91418 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK)
91419 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_MASK (0xFFFF0000U)
91420 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_SHIFT (16U)
91421 /*! reserved - reserved
91422  */
91423 #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_MASK)
91424 /*! @} */
91425 
91426 /*! @name DSI_HOST_PKT_RX_PAYLOAD -  */
91427 /*! @{ */
91428 #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU)
91429 #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U)
91430 /*! dsi_host_pkt_rx_payload - APB to pkt interface rx payload read
91431  */
91432 #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK)
91433 /*! @} */
91434 
91435 /*! @name DSI_HOST_PKT_RX_PKT_HEADER -  */
91436 /*! @{ */
91437 #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU)
91438 #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U)
91439 /*! dsi_host_pkt_rx_pkt_header - APB to pkt interface rx packet header.
91440  *  0b000000000000000000000000-0b000000000000000000001111..word count
91441  *  0b000000000000000000010000-0b000000000000000000010101..data type
91442  *  0b000000000000000000010110-0b000000000000000000010111..Virtual Channel
91443  */
91444 #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK)
91445 #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_MASK (0xFF000000U)
91446 #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_SHIFT (24U)
91447 /*! reserved - reserved
91448  */
91449 #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_MASK)
91450 /*! @} */
91451 
91452 /*! @name DSI_HOST_IRQ_STATUS -  */
91453 /*! @{ */
91454 #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU)
91455 #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U)
91456 /*! dsi_host_irq_status - Status of APB to packet interface.
91457  *  0b00000000000000000000000000000000..state machine not idle
91458  *  0b00000000000000000000000000000001..Tx packet done
91459  *  0b00000000000000000000000000000010..dphy direction
91460  *  0b00000000000000000000000000000011..tx fifo overflow
91461  *  0b00000000000000000000000000000100..tx fifo underflow
91462  *  0b00000000000000000000000000000101..rx fifo overflow
91463  *  0b00000000000000000000000000000110..rx fifo underflow
91464  *  0b00000000000000000000000000000111..rx packet header has been received
91465  *  0b00000000000000000000000000001000..all rx packet payload data has been received status_out port bit descriptions
91466  *  0b00000000000000000000000000001000-0b00000000000000000000000000011100..map directory to dsi host controller
91467  *  0b00000000000000000000000000011101..host bta timeout, host controller host_bta_timeout port
91468  *  0b00000000000000000000000000011110..low power rx timeout, host controller lp_rx_timeout port
91469  *  0b00000000000000000000000000011111..high speed tx timeout, host controller hs_tx_timeout port
91470  */
91471 #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK)
91472 /*! @} */
91473 
91474 /*! @name DSI_HOST_IRQ_STATUS2 -  */
91475 /*! @{ */
91476 #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U)
91477 #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U)
91478 /*! dsi_host_irq_status2 - Status of APB to packet interface part 2, read part 2 first then
91479  *    dsi_host_irq_status. reading dsi_host_irq_status will clear both status and status2.
91480  *  0b000..single bit ecc error
91481  *  0b001..multi bit ecc error
91482  *  0b010..crc error
91483  */
91484 #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK)
91485 #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_MASK (0xFFFFFFF8U)
91486 #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_SHIFT (3U)
91487 /*! reserved - reserved
91488  */
91489 #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_MASK)
91490 /*! @} */
91491 
91492 /*! @name DSI_HOST_IRQ_MASK -  */
91493 /*! @{ */
91494 #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU)
91495 #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U)
91496 /*! dsi_host_irq_mask - irq mask
91497  *  0b00000000000000000000000000000000..state machine not idle
91498  *  0b00000000000000000000000000000001..Tx packet done
91499  *  0b00000000000000000000000000000010..dphy direction
91500  *  0b00000000000000000000000000000011..tx fifo overflow
91501  *  0b00000000000000000000000000000100..tx fifo underflow
91502  *  0b00000000000000000000000000000101..rx fifo overflow
91503  *  0b00000000000000000000000000000110..rx fifo underflow
91504  *  0b00000000000000000000000000000111..rx packet header has been received
91505  *  0b00000000000000000000000000001000..all rx packet payload data has been received
91506  *  0b00000000000000000000000000001000-0b00000000000000000000000000011100..map directory to dsi host controller status_out port bit descriptions
91507  *  0b00000000000000000000000000011101..high speed tx timeout, host controller hs_tx_timeout port
91508  *  0b00000000000000000000000000011110..low power rx timeout, host controller lp_rx_timeout port
91509  *  0b00000000000000000000000000011111..host bta timeout, host controller host_bta_timeout port
91510  */
91511 #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK)
91512 /*! @} */
91513 
91514 /*! @name DSI_HOST_IRQ_MASK2 -  */
91515 /*! @{ */
91516 #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U)
91517 #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U)
91518 /*! dsi_host_irq_mask2 - irq mask 2
91519  *  0b000..single bit ecc error
91520  *  0b001..multi bit ecc error
91521  *  0b010..crc error
91522  */
91523 #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK)
91524 #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_MASK (0xFFFFFFF8U)
91525 #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_SHIFT (3U)
91526 /*! reserved - reserved
91527  */
91528 #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_MASK)
91529 /*! @} */
91530 
91531 /*! @name DPHY_PD_TX -  */
91532 /*! @{ */
91533 #define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_MASK (0x1U)
91534 #define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_SHIFT (0U)
91535 /*! dphy_pd_tx - DPHY PD_TX input control
91536  */
91537 #define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_MASK)
91538 #define MIPI_DSI_HOST_DPHY_PD_TX_reserved_MASK   (0xFFFFFFFEU)
91539 #define MIPI_DSI_HOST_DPHY_PD_TX_reserved_SHIFT  (1U)
91540 /*! reserved - reserved
91541  */
91542 #define MIPI_DSI_HOST_DPHY_PD_TX_reserved(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_TX_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_TX_reserved_MASK)
91543 /*! @} */
91544 
91545 /*! @name DPHY_M_PRG_HS_PREPARE -  */
91546 /*! @{ */
91547 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U)
91548 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U)
91549 /*! dphy_m_prg_hs_prepare - DPHY m_PRG_HS_PREPARE input
91550  */
91551 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK)
91552 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_MASK (0xFFFFFFFCU)
91553 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_SHIFT (2U)
91554 /*! reserved - reserved
91555  */
91556 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_MASK)
91557 /*! @} */
91558 
91559 /*! @name DPHY_MC_PRG_HS_PREPARE -  */
91560 /*! @{ */
91561 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U)
91562 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U)
91563 /*! dphy_mc_prg_hs_prepare - DPHY mc_PRG_HS_PREPARE input
91564  */
91565 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK)
91566 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_MASK (0xFFFFFFFEU)
91567 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_SHIFT (1U)
91568 /*! reserved - reserved
91569  */
91570 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_MASK)
91571 /*! @} */
91572 
91573 /*! @name DPHY_M_PRG_HS_ZERO -  */
91574 /*! @{ */
91575 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU)
91576 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U)
91577 /*! dphy_m_prg_hs_zero - DPHY m_PRG_HS_ZERO input
91578  */
91579 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK)
91580 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_MASK (0xFFFFFFE0U)
91581 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_SHIFT (5U)
91582 /*! reserved - reserved
91583  */
91584 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_MASK)
91585 /*! @} */
91586 
91587 /*! @name DPHY_MC_PRG_HS_ZERO -  */
91588 /*! @{ */
91589 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU)
91590 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U)
91591 /*! dphy_mc_prg_hs_zero - DPHY mc_PRG_HS_ZERO input
91592  */
91593 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK)
91594 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_MASK (0xFFFFFFC0U)
91595 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_SHIFT (6U)
91596 /*! reserved - reserved
91597  */
91598 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_MASK)
91599 /*! @} */
91600 
91601 /*! @name DPHY_M_PRG_HS_TRAIL -  */
91602 /*! @{ */
91603 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU)
91604 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U)
91605 /*! dphy_m_prg_hs_trail - DPHY m_PRG_HS_TRAIL input
91606  */
91607 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK)
91608 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_MASK (0xFFFFFFF0U)
91609 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_SHIFT (4U)
91610 /*! reserved - reserved
91611  */
91612 #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_MASK)
91613 /*! @} */
91614 
91615 /*! @name DPHY_MC_PRG_HS_TRAIL -  */
91616 /*! @{ */
91617 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU)
91618 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U)
91619 /*! dphy_mc_prg_hs_trail - DPHY mc_PRG_HS_TRAIL input
91620  */
91621 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK)
91622 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_MASK (0xFFFFFFF0U)
91623 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_SHIFT (4U)
91624 /*! reserved - reserved
91625  */
91626 #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_MASK)
91627 /*! @} */
91628 
91629 /*! @name DPHY_PD_PLL -  */
91630 /*! @{ */
91631 #define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_MASK (0x1U)
91632 #define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_SHIFT (0U)
91633 /*! dphy_pd_pll - DPHY PD_PLL input
91634  */
91635 #define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_MASK)
91636 #define MIPI_DSI_HOST_DPHY_PD_PLL_reserved_MASK  (0xFFFFFFFEU)
91637 #define MIPI_DSI_HOST_DPHY_PD_PLL_reserved_SHIFT (1U)
91638 /*! reserved - reserved
91639  */
91640 #define MIPI_DSI_HOST_DPHY_PD_PLL_reserved(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_PLL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_PLL_reserved_MASK)
91641 /*! @} */
91642 
91643 /*! @name DPHY_TST -  */
91644 /*! @{ */
91645 #define MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK     (0x3FU)
91646 #define MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT    (0U)
91647 /*! dphy_tst - DPHY TST input
91648  */
91649 #define MIPI_DSI_HOST_DPHY_TST_dphy_tst(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK)
91650 #define MIPI_DSI_HOST_DPHY_TST_reserved_MASK     (0xFFFFFFC0U)
91651 #define MIPI_DSI_HOST_DPHY_TST_reserved_SHIFT    (6U)
91652 /*! reserved - reserved
91653  */
91654 #define MIPI_DSI_HOST_DPHY_TST_reserved(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_reserved_MASK)
91655 /*! @} */
91656 
91657 /*! @name DPHY_CN -  */
91658 /*! @{ */
91659 #define MIPI_DSI_HOST_DPHY_CN_dphy_cn_MASK       (0x1FU)
91660 #define MIPI_DSI_HOST_DPHY_CN_dphy_cn_SHIFT      (0U)
91661 /*! dphy_cn - DPHY CN input
91662  */
91663 #define MIPI_DSI_HOST_DPHY_CN_dphy_cn(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CN_dphy_cn_SHIFT)) & MIPI_DSI_HOST_DPHY_CN_dphy_cn_MASK)
91664 #define MIPI_DSI_HOST_DPHY_CN_reserved_MASK      (0xFFFFFFE0U)
91665 #define MIPI_DSI_HOST_DPHY_CN_reserved_SHIFT     (5U)
91666 /*! reserved - reserved
91667  */
91668 #define MIPI_DSI_HOST_DPHY_CN_reserved(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CN_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_CN_reserved_MASK)
91669 /*! @} */
91670 
91671 /*! @name DPHY_CM -  */
91672 /*! @{ */
91673 #define MIPI_DSI_HOST_DPHY_CM_dphy_cm_MASK       (0xFFU)
91674 #define MIPI_DSI_HOST_DPHY_CM_dphy_cm_SHIFT      (0U)
91675 /*! dphy_cm - DPHY CM input
91676  */
91677 #define MIPI_DSI_HOST_DPHY_CM_dphy_cm(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CM_dphy_cm_SHIFT)) & MIPI_DSI_HOST_DPHY_CM_dphy_cm_MASK)
91678 #define MIPI_DSI_HOST_DPHY_CM_reserved_MASK      (0xFFFFFF00U)
91679 #define MIPI_DSI_HOST_DPHY_CM_reserved_SHIFT     (8U)
91680 /*! reserved - reserved
91681  */
91682 #define MIPI_DSI_HOST_DPHY_CM_reserved(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CM_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_CM_reserved_MASK)
91683 /*! @} */
91684 
91685 /*! @name DPHY_CO -  */
91686 /*! @{ */
91687 #define MIPI_DSI_HOST_DPHY_CO_dphy_co_MASK       (0x3U)
91688 #define MIPI_DSI_HOST_DPHY_CO_dphy_co_SHIFT      (0U)
91689 /*! dphy_co - DPHY CO input
91690  */
91691 #define MIPI_DSI_HOST_DPHY_CO_dphy_co(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CO_dphy_co_SHIFT)) & MIPI_DSI_HOST_DPHY_CO_dphy_co_MASK)
91692 #define MIPI_DSI_HOST_DPHY_CO_reserved_MASK      (0xFFFFFFFCU)
91693 #define MIPI_DSI_HOST_DPHY_CO_reserved_SHIFT     (2U)
91694 /*! reserved - reserved
91695  */
91696 #define MIPI_DSI_HOST_DPHY_CO_reserved(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_CO_reserved_MASK)
91697 /*! @} */
91698 
91699 /*! @name DPHY_LOCK -  */
91700 /*! @{ */
91701 #define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_MASK   (0x1U)
91702 #define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_SHIFT  (0U)
91703 /*! dphy_lock - DPHY PLL LOCK output
91704  */
91705 #define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_MASK)
91706 #define MIPI_DSI_HOST_DPHY_LOCK_reserved_MASK    (0xFFFFFFFEU)
91707 #define MIPI_DSI_HOST_DPHY_LOCK_reserved_SHIFT   (1U)
91708 /*! reserved - reserved
91709  */
91710 #define MIPI_DSI_HOST_DPHY_LOCK_reserved(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_reserved_MASK)
91711 /*! @} */
91712 
91713 /*! @name DPHY_LOCK_BYP -  */
91714 /*! @{ */
91715 #define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_MASK (0x1U)
91716 #define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT (0U)
91717 /*! dphy_lock_byp - DPHY LOCK_BYP input
91718  */
91719 #define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_MASK)
91720 #define MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved_MASK (0xFFFFFFFEU)
91721 #define MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved_SHIFT (1U)
91722 /*! reserved - reserved
91723  */
91724 #define MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved_MASK)
91725 /*! @} */
91726 
91727 /*! @name DPHY_TX_RCAL -  */
91728 /*! @{ */
91729 #define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_MASK (0x3U)
91730 #define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_SHIFT (0U)
91731 /*! dphy_tx_rcal - DPHY RTERM_SEL input
91732  */
91733 #define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_SHIFT)) & MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_MASK)
91734 #define MIPI_DSI_HOST_DPHY_TX_RCAL_reserved_MASK (0xFFFFFFFCU)
91735 #define MIPI_DSI_HOST_DPHY_TX_RCAL_reserved_SHIFT (2U)
91736 /*! reserved - reserved
91737  */
91738 #define MIPI_DSI_HOST_DPHY_TX_RCAL_reserved(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TX_RCAL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_TX_RCAL_reserved_MASK)
91739 /*! @} */
91740 
91741 /*! @name DPHY_AUTO_PD_EN -  */
91742 /*! @{ */
91743 #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U)
91744 #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U)
91745 /*! dphy_auto_pd_en - DPHY AUTO_PD_EN input
91746  */
91747 #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK)
91748 #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_MASK (0xFFFFFFFEU)
91749 #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_SHIFT (1U)
91750 /*! reserved - reserved
91751  */
91752 #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_MASK)
91753 /*! @} */
91754 
91755 /*! @name DPHY_RXLPRP -  */
91756 /*! @{ */
91757 #define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U)
91758 #define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U)
91759 /*! dphy_rxlprp - DPHY RXLPRP input
91760  */
91761 #define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK)
91762 #define MIPI_DSI_HOST_DPHY_RXLPRP_reserved_MASK  (0xFFFFFFFCU)
91763 #define MIPI_DSI_HOST_DPHY_RXLPRP_reserved_SHIFT (2U)
91764 /*! reserved - reserved
91765  */
91766 #define MIPI_DSI_HOST_DPHY_RXLPRP_reserved(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_reserved_MASK)
91767 /*! @} */
91768 
91769 /*! @name DPHY_RXCDRP -  */
91770 /*! @{ */
91771 #define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U)
91772 #define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U)
91773 /*! dphy_rxcdrp - DPHY RXCDRP input
91774  */
91775 #define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK)
91776 #define MIPI_DSI_HOST_DPHY_RXCDRP_reserved_MASK  (0xFFFFFFFCU)
91777 #define MIPI_DSI_HOST_DPHY_RXCDRP_reserved_SHIFT (2U)
91778 /*! reserved - reserved
91779  */
91780 #define MIPI_DSI_HOST_DPHY_RXCDRP_reserved(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_reserved_MASK)
91781 /*! @} */
91782 
91783 
91784 /*!
91785  * @}
91786  */ /* end of group MIPI_DSI_HOST_Register_Masks */
91787 
91788 
91789 /* MIPI_DSI_HOST - Peripheral instance base addresses */
91790 /** Peripheral DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST base address */
91791 #define DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST_BASE   (0x56228000u)
91792 /** Peripheral DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST base pointer */
91793 #define DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST        ((MIPI_DSI_HOST_Type *)DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST_BASE)
91794 /** Peripheral DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST base address */
91795 #define DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST_BASE   (0x56248000u)
91796 /** Peripheral DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST base pointer */
91797 #define DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST        ((MIPI_DSI_HOST_Type *)DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST_BASE)
91798 /** Array initializer of MIPI_DSI_HOST peripheral base addresses */
91799 #define MIPI_DSI_HOST_BASE_ADDRS                 { DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST_BASE, DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST_BASE }
91800 /** Array initializer of MIPI_DSI_HOST peripheral base pointers */
91801 #define MIPI_DSI_HOST_BASE_PTRS                  { DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST, DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST }
91802 
91803 /*!
91804  * @}
91805  */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */
91806 
91807 
91808 /* ----------------------------------------------------------------------------
91809    -- MIPI_DSI_LVDS_COMBO_CSR Peripheral Access Layer
91810    ---------------------------------------------------------------------------- */
91811 
91812 /*!
91813  * @addtogroup MIPI_DSI_LVDS_COMBO_CSR_Peripheral_Access_Layer MIPI_DSI_LVDS_COMBO_CSR Peripheral Access Layer
91814  * @{
91815  */
91816 
91817 /** MIPI_DSI_LVDS_COMBO_CSR - Register Layout Typedef */
91818 typedef struct {
91819   __IO uint32_t LVDS_PHY_CTRL;                     /**< PHY in LVDS mode control register, offset: 0x0 */
91820        uint8_t RESERVED_0[28];
91821   __IO uint32_t SS_CRTL;                           /**< SS control register, offset: 0x20 */
91822        uint8_t RESERVED_1[12];
91823   __IO uint32_t ULPS_CTRL;                         /**< ULPS Control Register, offset: 0x30 */
91824        uint8_t RESERVED_2[12];
91825   __IO uint32_t PXL2DPI_CTRL;                      /**< PXL2DPI Control Register, offset: 0x40 */
91826        uint8_t RESERVED_3[156];
91827   __IO uint32_t PM_CTRL;                           /**< Pixel Mapper Control Register, offset: 0xE0 */
91828 } MIPI_DSI_LVDS_COMBO_CSR_Type;
91829 
91830 /* ----------------------------------------------------------------------------
91831    -- MIPI_DSI_LVDS_COMBO_CSR Register Masks
91832    ---------------------------------------------------------------------------- */
91833 
91834 /*!
91835  * @addtogroup MIPI_DSI_LVDS_COMBO_CSR_Register_Masks MIPI_DSI_LVDS_COMBO_CSR Register Masks
91836  * @{
91837  */
91838 
91839 /*! @name LVDS_PHY_CTRL - PHY in LVDS mode control register */
91840 /*! @{ */
91841 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN_MASK (0x1U)
91842 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN_SHIFT (0U)
91843 /*! LVDS_EN - LVDS TX enable
91844  *  0b0..LVDS TX disable
91845  *  0b1..LVDS TX enable
91846  */
91847 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN_MASK)
91848 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB_MASK (0x2U)
91849 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB_SHIFT (1U)
91850 /*! RFB - Rising / falling edge clock selection
91851  *  0b0..Falling edge
91852  *  0b1..Rising edge
91853  */
91854 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB_MASK)
91855 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA_MASK (0x1CU)
91856 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA_SHIFT (2U)
91857 /*! CA - Driver output current
91858  *  0b100..Default setting
91859  */
91860 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA_MASK)
91861 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM_MASK (0xE0U)
91862 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM_SHIFT (5U)
91863 /*! CCM - Common mode voltage
91864  *  0b100..Default setting
91865  */
91866 #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM_MASK)
91867 /*! @} */
91868 
91869 /*! @name SS_CRTL - SS control register */
91870 /*! @{ */
91871 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL_MASK (0x1U)
91872 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL_SHIFT (0U)
91873 /*! CH0_HSYNC_POL - HSYNC polarity control
91874  *  0b0..HSYNC is Low active
91875  *  0b1..HSYNC is High active
91876  */
91877 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL_MASK)
91878 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL_MASK (0x2U)
91879 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL_SHIFT (1U)
91880 /*! CH0_VSYNC_POL - VSYNC polarity control
91881  *  0b0..VSYNC is Low active
91882  *  0b1..VSYNC is High active
91883  */
91884 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL_MASK)
91885 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL_MASK (0x4U)
91886 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL_SHIFT (2U)
91887 /*! CH1_HSYNC_POL - HSYNC polarity control
91888  *  0b0..HSYNC is Low active
91889  *  0b1..HSYNC is High active
91890  */
91891 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL_MASK)
91892 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL_MASK (0x8U)
91893 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL_SHIFT (3U)
91894 /*! CH1_VSYNC_POL - VSYNC polarity control
91895  *  0b0..VSYNC is Low active
91896  *  0b1..VSYNC is High active
91897  */
91898 #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL_MASK)
91899 /*! @} */
91900 
91901 /*! @name ULPS_CTRL - ULPS Control Register */
91902 /*! @{ */
91903 #define MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS_MASK (0x1FU)
91904 #define MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS_SHIFT (0U)
91905 /*! TX_ULPS - Low power control of DSI lanes
91906  */
91907 #define MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS_MASK)
91908 /*! @} */
91909 
91910 /*! @name PXL2DPI_CTRL - PXL2DPI Control Register */
91911 /*! @{ */
91912 #define MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI_MASK (0x7U)
91913 #define MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI_SHIFT (0U)
91914 /*! PXL2DPI - pxl2dpi_config encoding
91915  */
91916 #define MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI_MASK)
91917 /*! @} */
91918 
91919 /*! @name PM_CTRL - Pixel Mapper Control Register */
91920 /*! @{ */
91921 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE_MASK (0x3U)
91922 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE_SHIFT (0U)
91923 /*! CH0_MODE - LVDS Channel 0 operation mode
91924  *  0b00..Channel disabled
91925  *  0b01..Channel enabled, routed to DI0
91926  *  0b10..Channel disabled
91927  *  0b11..Channel enabled, routed to DI1
91928  */
91929 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE_MASK)
91930 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE_MASK (0xCU)
91931 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE_SHIFT (2U)
91932 /*! CH1_MODE - LVDS Channel 1 operation mode
91933  *  0b00..Channel disabled
91934  *  0b01..Channel enabled, routed to DI0
91935  *  0b10..Channel disabled
91936  *  0b11..Channel enabled, routed to DI1
91937  */
91938 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE_MASK)
91939 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN_MASK (0x10U)
91940 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN_SHIFT (4U)
91941 /*! SPLIT_MODE_EN - Enable split mode
91942  *  0b0..Split mode enabled
91943  */
91944 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN_MASK)
91945 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH_MASK (0x20U)
91946 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH_SHIFT (5U)
91947 /*! CH0_DATA_WIDTH - Data width for LVDS channel 0
91948  *  0b0..Data width is 18-bits wide
91949  *  0b1..Data width is 24-bits wide
91950  */
91951 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH_MASK)
91952 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING_MASK (0x40U)
91953 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING_SHIFT (6U)
91954 /*! CH0_BIT_MAPPING - Data mapping to LVDS channel 0
91955  *  0b0..Use VESA standard
91956  *  0b1..Use JEIDA standard
91957  */
91958 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING_MASK)
91959 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH_MASK (0x80U)
91960 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH_SHIFT (7U)
91961 /*! CH1_DATA_WIDTH - Data width for LVDS channel 1
91962  *  0b0..Data width is 18-bits wide
91963  *  0b1..Data width is 24-bits wide
91964  */
91965 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH_MASK)
91966 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING_MASK (0x100U)
91967 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING_SHIFT (8U)
91968 /*! CH1_BIT_MAPPING - Data mapping to LVDS channel 1
91969  *  0b0..Use SPWG standard
91970  *  0b1..Use JEIDA standard
91971  */
91972 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING_MASK)
91973 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY_MASK (0x200U)
91974 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY_SHIFT (9U)
91975 /*! DI0_VS_POLARITY - Vsync polarity for DI0 interface
91976  *  0b0..Vsync is active low
91977  *  0b1..Vsync is active high
91978  */
91979 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY_MASK)
91980 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY_MASK (0x400U)
91981 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY_SHIFT (10U)
91982 /*! DI1_VS_POLARITY - Vsync polarity for DI1 interface
91983  *  0b0..Vsync is active low
91984  *  0b1..Vsync is active high
91985  */
91986 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY_MASK)
91987 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL_MASK (0x10000000U)
91988 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL_SHIFT (28U)
91989 /*! CH_SEL
91990  *  0b0..Channel 0 (Even pixel) data output to LVDS PHY
91991  *  0b1..Channel 1 (Odd Pixel) data output to LVDS PHY
91992  */
91993 #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL_MASK)
91994 /*! @} */
91995 
91996 
91997 /*!
91998  * @}
91999  */ /* end of group MIPI_DSI_LVDS_COMBO_CSR_Register_Masks */
92000 
92001 
92002 /* MIPI_DSI_LVDS_COMBO_CSR - Peripheral instance base addresses */
92003 /** Peripheral MIPI_DSI_LVDS_COMBO0_CSR base address */
92004 #define MIPI_DSI_LVDS_COMBO0_CSR_BASE            (0x56221000u)
92005 /** Peripheral MIPI_DSI_LVDS_COMBO0_CSR base pointer */
92006 #define MIPI_DSI_LVDS_COMBO0_CSR                 ((MIPI_DSI_LVDS_COMBO_CSR_Type *)MIPI_DSI_LVDS_COMBO0_CSR_BASE)
92007 /** Peripheral MIPI_DSI_LVDS_COMBO1_CSR base address */
92008 #define MIPI_DSI_LVDS_COMBO1_CSR_BASE            (0x56241000u)
92009 /** Peripheral MIPI_DSI_LVDS_COMBO1_CSR base pointer */
92010 #define MIPI_DSI_LVDS_COMBO1_CSR                 ((MIPI_DSI_LVDS_COMBO_CSR_Type *)MIPI_DSI_LVDS_COMBO1_CSR_BASE)
92011 /** Array initializer of MIPI_DSI_LVDS_COMBO_CSR peripheral base addresses */
92012 #define MIPI_DSI_LVDS_COMBO_CSR_BASE_ADDRS       { MIPI_DSI_LVDS_COMBO0_CSR_BASE, MIPI_DSI_LVDS_COMBO1_CSR_BASE }
92013 /** Array initializer of MIPI_DSI_LVDS_COMBO_CSR peripheral base pointers */
92014 #define MIPI_DSI_LVDS_COMBO_CSR_BASE_PTRS        { MIPI_DSI_LVDS_COMBO0_CSR, MIPI_DSI_LVDS_COMBO1_CSR }
92015 
92016 /*!
92017  * @}
92018  */ /* end of group MIPI_DSI_LVDS_COMBO_CSR_Peripheral_Access_Layer */
92019 
92020 
92021 /* ----------------------------------------------------------------------------
92022    -- MIXER Peripheral Access Layer
92023    ---------------------------------------------------------------------------- */
92024 
92025 /*!
92026  * @addtogroup MIXER_Peripheral_Access_Layer MIXER Peripheral Access Layer
92027  * @{
92028  */
92029 
92030 /** MIXER - Register Layout Typedef */
92031 typedef struct {
92032        uint8_t RESERVED_0[512];
92033   __IO uint32_t CTR;                               /**< Mixer Control Register, offset: 0x200 */
92034   __I  uint32_t STR;                               /**< Mixer Status Register, offset: 0x204 */
92035   struct {                                         /* offset: 0x208, array step: 0x20 */
92036     __IO uint32_t ATCR;                              /**< Attenuation Control Register, array offset: 0x208, array step: 0x20 */
92037     __IO uint32_t ATIVAL;                            /**< Attenuation Initial value register, array offset: 0x20C, array step: 0x20 */
92038     __IO uint32_t ATSTPUP;                           /**< Attenuation step up factor, array offset: 0x210, array step: 0x20 */
92039     __IO uint32_t ATSTPDN;                           /**< Attenuation step down factor, array offset: 0x214, array step: 0x20 */
92040     __IO uint32_t ATSTPTGT;                          /**< Attenuation step target, array offset: 0x218, array step: 0x20 */
92041     __I  uint32_t ATTNVAL;                           /**< Attenuation Value register, array offset: 0x21C, array step: 0x20 */
92042     __I  uint32_t ATSTP;                             /**< Attenuation step number register, array offset: 0x220, array step: 0x20 */
92043          uint8_t RESERVED_0[4];
92044   } AT[2];
92045 } MIXER_Type;
92046 
92047 /* ----------------------------------------------------------------------------
92048    -- MIXER Register Masks
92049    ---------------------------------------------------------------------------- */
92050 
92051 /*!
92052  * @addtogroup MIXER_Register_Masks MIXER Register Masks
92053  * @{
92054  */
92055 
92056 /*! @name CTR - Mixer Control Register */
92057 /*! @{ */
92058 #define MIXER_CTR_MIXCLK_MASK                    (0x1U)
92059 #define MIXER_CTR_MIXCLK_SHIFT                   (0U)
92060 /*! MIXCLK - Mixing Clock source selection
92061  *  0b0..TDM 1 interface clock
92062  *  0b1..TDM 2 interface clock
92063  */
92064 #define MIXER_CTR_MIXCLK(x)                      (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_MIXCLK_SHIFT)) & MIXER_CTR_MIXCLK_MASK)
92065 #define MIXER_CTR_OUTSRC_MASK                    (0x6U)
92066 #define MIXER_CTR_OUTSRC_SHIFT                   (1U)
92067 /*! OUTSRC - Output Source selection
92068  *  0b00..Disabled
92069  *  0b01..TDM 1 audio
92070  *  0b10..TDM 2 audio
92071  *  0b11..Mixed audio
92072  */
92073 #define MIXER_CTR_OUTSRC(x)                      (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_OUTSRC_SHIFT)) & MIXER_CTR_OUTSRC_MASK)
92074 #define MIXER_CTR_OUTWIDTH_MASK                  (0x38U)
92075 #define MIXER_CTR_OUTWIDTH_SHIFT                 (3U)
92076 /*! OUTWIDTH - Audio sample width in TDM outgoing frame
92077  *  0b000..16 bit
92078  *  0b001..18 bit
92079  *  0b010..20 bit
92080  *  0b011..24 bit
92081  */
92082 #define MIXER_CTR_OUTWIDTH(x)                    (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_OUTWIDTH_SHIFT)) & MIXER_CTR_OUTWIDTH_MASK)
92083 #define MIXER_CTR_OUTCKPOL_MASK                  (0x40U)
92084 #define MIXER_CTR_OUTCKPOL_SHIFT                 (6U)
92085 /*! OUTCKPOL - Polarity of bit clock of TDM out interface
92086  *  0b0..positive edge
92087  *  0b1..Negative edge
92088  */
92089 #define MIXER_CTR_OUTCKPOL(x)                    (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_OUTCKPOL_SHIFT)) & MIXER_CTR_OUTCKPOL_MASK)
92090 #define MIXER_CTR_MASKRTDF_MASK                  (0x80U)
92091 #define MIXER_CTR_MASKRTDF_SHIFT                 (7U)
92092 /*! MASKRTDF - Mask Frame rate difference error
92093  *  0b0..Unmask error, Frame rate mismatch error checked for mixing operation (Default)
92094  *  0b1..Mask error, Frame rate mismatch error not checked when entering into Mixing process
92095  */
92096 #define MIXER_CTR_MASKRTDF(x)                    (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_MASKRTDF_SHIFT)) & MIXER_CTR_MASKRTDF_MASK)
92097 #define MIXER_CTR_MASKCKDF_MASK                  (0x100U)
92098 #define MIXER_CTR_MASKCKDF_SHIFT                 (8U)
92099 /*! MASKCKDF - Mask Clock frequency difference error
92100  *  0b0..Unmask error, Clock frequency mismatch error checked for mixing operation (Default)
92101  *  0b1..Mask error, Clock frequency mismatch error not checked when entering into Mixing process
92102  */
92103 #define MIXER_CTR_MASKCKDF(x)                    (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_MASKCKDF_SHIFT)) & MIXER_CTR_MASKCKDF_MASK)
92104 #define MIXER_CTR_SYNCMODE_MASK                  (0x200U)
92105 #define MIXER_CTR_SYNCMODE_SHIFT                 (9U)
92106 /*! SYNCMODE - Sync mode configuration Enable
92107  *  0b0..Disable ; Attenuators work on their Own interface bit clock
92108  *  0b1..Enable; Any one Attenuator works on Ohters interface bit clock
92109  */
92110 #define MIXER_CTR_SYNCMODE(x)                    (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_SYNCMODE_SHIFT)) & MIXER_CTR_SYNCMODE_MASK)
92111 #define MIXER_CTR_SYNCSRC_MASK                   (0x400U)
92112 #define MIXER_CTR_SYNCSRC_SHIFT                  (10U)
92113 /*! SYNCSRC - Sync mode clock source
92114  *  0b0..TDM 1 interface
92115  *  0b1..TDM 2 interface
92116  */
92117 #define MIXER_CTR_SYNCSRC(x)                     (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_SYNCSRC_SHIFT)) & MIXER_CTR_SYNCSRC_MASK)
92118 /*! @} */
92119 
92120 /*! @name STR - Mixer Status Register */
92121 /*! @{ */
92122 #define MIXER_STR_RATEDIFF_MASK                  (0x1U)
92123 #define MIXER_STR_RATEDIFF_SHIFT                 (0U)
92124 /*! RATEDIFF - Rate difference
92125  *  0b0..Frame rate matches between TDM1 and TDM2
92126  *  0b1..Frame Rate mismatch between TDM1 and TDM2
92127  */
92128 #define MIXER_STR_RATEDIFF(x)                    (((uint32_t)(((uint32_t)(x)) << MIXER_STR_RATEDIFF_SHIFT)) & MIXER_STR_RATEDIFF_MASK)
92129 #define MIXER_STR_CLKDIFF_MASK                   (0x2U)
92130 #define MIXER_STR_CLKDIFF_SHIFT                  (1U)
92131 /*! CLKDIFF - Bit clock difference
92132  *  0b0..Bit clock frequency matches between TDM1 and TDM2
92133  *  0b1..Bit clock frequency mismatch between TDM1 and TDM2
92134  */
92135 #define MIXER_STR_CLKDIFF(x)                     (((uint32_t)(((uint32_t)(x)) << MIXER_STR_CLKDIFF_SHIFT)) & MIXER_STR_CLKDIFF_MASK)
92136 #define MIXER_STR_MIXSTAT_MASK                   (0xCU)
92137 #define MIXER_STR_MIXSTAT_SHIFT                  (2U)
92138 /*! MIXSTAT - Mixer Status
92139  *  0b00..Mixer in DISABLED state (No output)
92140  *  0b01..Mixer in TDM_1 state (Output is TDM 1 stream)
92141  *  0b10..Mixer in TDM_2 state (Output is TDM 2 stream)
92142  *  0b11..Mixer in MIXED state (Output is MIXED stream of TDM 1 and TDM 2)
92143  */
92144 #define MIXER_STR_MIXSTAT(x)                     (((uint32_t)(((uint32_t)(x)) << MIXER_STR_MIXSTAT_SHIFT)) & MIXER_STR_MIXSTAT_MASK)
92145 /*! @} */
92146 
92147 /*! @name ATCR - Attenuation Control Register */
92148 /*! @{ */
92149 #define MIXER_ATCR_AT_EN_MASK                    (0x1U)
92150 #define MIXER_ATCR_AT_EN_SHIFT                   (0U)
92151 /*! AT_EN - Attenuation Enable
92152  *  0b0..Attenuation disabled
92153  *  0b1..Attenuation enabled
92154  */
92155 #define MIXER_ATCR_AT_EN(x)                      (((uint32_t)(((uint32_t)(x)) << MIXER_ATCR_AT_EN_SHIFT)) & MIXER_ATCR_AT_EN_MASK)
92156 #define MIXER_ATCR_AT_UPDN_MASK                  (0x2U)
92157 #define MIXER_ATCR_AT_UPDN_SHIFT                 (1U)
92158 /*! AT_UPDN - Attenuation direction
92159  *  0b0..Downward attenuation
92160  *  0b1..Upward attenuation
92161  */
92162 #define MIXER_ATCR_AT_UPDN(x)                    (((uint32_t)(((uint32_t)(x)) << MIXER_ATCR_AT_UPDN_SHIFT)) & MIXER_ATCR_AT_UPDN_MASK)
92163 #define MIXER_ATCR_ATSTPDIV_MASK                 (0x3FFCU)
92164 #define MIXER_ATCR_ATSTPDIV_SHIFT                (2U)
92165 /*! ATSTPDIV - Step divider
92166  */
92167 #define MIXER_ATCR_ATSTPDIV(x)                   (((uint32_t)(((uint32_t)(x)) << MIXER_ATCR_ATSTPDIV_SHIFT)) & MIXER_ATCR_ATSTPDIV_MASK)
92168 /*! @} */
92169 
92170 /* The count of MIXER_ATCR */
92171 #define MIXER_ATCR_COUNT                         (2U)
92172 
92173 /*! @name ATIVAL - Attenuation Initial value register */
92174 /*! @{ */
92175 #define MIXER_ATIVAL_ATINTVAL_MASK               (0x3FFFFU)
92176 #define MIXER_ATIVAL_ATINTVAL_SHIFT              (0U)
92177 /*! ATINTVAL - Attnuation Initial value
92178  *  0b100000000000000000..= 0.5
92179  *  0b110000000000000000..= 0.75
92180  *  0b111111111111111111..= 0.999996185 (default)
92181  */
92182 #define MIXER_ATIVAL_ATINTVAL(x)                 (((uint32_t)(((uint32_t)(x)) << MIXER_ATIVAL_ATINTVAL_SHIFT)) & MIXER_ATIVAL_ATINTVAL_MASK)
92183 /*! @} */
92184 
92185 /* The count of MIXER_ATIVAL */
92186 #define MIXER_ATIVAL_COUNT                       (2U)
92187 
92188 /*! @name ATSTPUP - Attenuation step up factor */
92189 /*! @{ */
92190 #define MIXER_ATSTPUP_ATSTEPUP_MASK              (0x3FFFFU)
92191 #define MIXER_ATSTPUP_ATSTEPUP_SHIFT             (0U)
92192 /*! ATSTEPUP - Attnuation step up factor
92193  *  0b100000000000000000..= 0.5
92194  *  0b110000000000000000..= 0.75
92195  *  0b101010101010101010..= 0.666664124 (default)
92196  *  0b111111111111111111..= 0.999996185
92197  */
92198 #define MIXER_ATSTPUP_ATSTEPUP(x)                (((uint32_t)(((uint32_t)(x)) << MIXER_ATSTPUP_ATSTEPUP_SHIFT)) & MIXER_ATSTPUP_ATSTEPUP_MASK)
92199 /*! @} */
92200 
92201 /* The count of MIXER_ATSTPUP */
92202 #define MIXER_ATSTPUP_COUNT                      (2U)
92203 
92204 /*! @name ATSTPDN - Attenuation step down factor */
92205 /*! @{ */
92206 #define MIXER_ATSTPDN_ATSTEPDN_MASK              (0x3FFFFU)
92207 #define MIXER_ATSTPDN_ATSTEPDN_SHIFT             (0U)
92208 /*! ATSTEPDN - Attnuation step down factor
92209  *  0b100000000000000000..= 0.5
92210  *  0b110000000000000000..= 0.75 (default)
92211  *  0b111111111111111111..= 0.999996185
92212  */
92213 #define MIXER_ATSTPDN_ATSTEPDN(x)                (((uint32_t)(((uint32_t)(x)) << MIXER_ATSTPDN_ATSTEPDN_SHIFT)) & MIXER_ATSTPDN_ATSTEPDN_MASK)
92214 /*! @} */
92215 
92216 /* The count of MIXER_ATSTPDN */
92217 #define MIXER_ATSTPDN_COUNT                      (2U)
92218 
92219 /*! @name ATSTPTGT - Attenuation step target */
92220 /*! @{ */
92221 #define MIXER_ATSTPTGT_ATSTPTG_MASK              (0x3FFFFU)
92222 #define MIXER_ATSTPTGT_ATSTPTG_SHIFT             (0U)
92223 /*! ATSTPTG - Attenuation step target value
92224  */
92225 #define MIXER_ATSTPTGT_ATSTPTG(x)                (((uint32_t)(((uint32_t)(x)) << MIXER_ATSTPTGT_ATSTPTG_SHIFT)) & MIXER_ATSTPTGT_ATSTPTG_MASK)
92226 /*! @} */
92227 
92228 /* The count of MIXER_ATSTPTGT */
92229 #define MIXER_ATSTPTGT_COUNT                     (2U)
92230 
92231 /*! @name ATTNVAL - Attenuation Value register */
92232 /*! @{ */
92233 #define MIXER_ATTNVAL_ATCURVAL_MASK              (0x3FFFFU)
92234 #define MIXER_ATTNVAL_ATCURVAL_SHIFT             (0U)
92235 /*! ATCURVAL - Current value of attenuation
92236  */
92237 #define MIXER_ATTNVAL_ATCURVAL(x)                (((uint32_t)(((uint32_t)(x)) << MIXER_ATTNVAL_ATCURVAL_SHIFT)) & MIXER_ATTNVAL_ATCURVAL_MASK)
92238 /*! @} */
92239 
92240 /* The count of MIXER_ATTNVAL */
92241 #define MIXER_ATTNVAL_COUNT                      (2U)
92242 
92243 /*! @name ATSTP - Attenuation step number register */
92244 /*! @{ */
92245 #define MIXER_ATSTP_STPCTR_MASK                  (0x3FFFFU)
92246 #define MIXER_ATSTP_STPCTR_SHIFT                 (0U)
92247 /*! STPCTR - Step counter value
92248  */
92249 #define MIXER_ATSTP_STPCTR(x)                    (((uint32_t)(((uint32_t)(x)) << MIXER_ATSTP_STPCTR_SHIFT)) & MIXER_ATSTP_STPCTR_MASK)
92250 /*! @} */
92251 
92252 /* The count of MIXER_ATSTP */
92253 #define MIXER_ATSTP_COUNT                        (2U)
92254 
92255 
92256 /*!
92257  * @}
92258  */ /* end of group MIXER_Register_Masks */
92259 
92260 
92261 /* MIXER - Peripheral instance base addresses */
92262 /** Peripheral ADMA__MIXER base address */
92263 #define ADMA__MIXER_BASE                         (0x59840000u)
92264 /** Peripheral ADMA__MIXER base pointer */
92265 #define ADMA__MIXER                              ((MIXER_Type *)ADMA__MIXER_BASE)
92266 /** Array initializer of MIXER peripheral base addresses */
92267 #define MIXER_BASE_ADDRS                         { ADMA__MIXER_BASE }
92268 /** Array initializer of MIXER peripheral base pointers */
92269 #define MIXER_BASE_PTRS                          { ADMA__MIXER }
92270 
92271 /*!
92272  * @}
92273  */ /* end of group MIXER_Peripheral_Access_Layer */
92274 
92275 
92276 /* ----------------------------------------------------------------------------
92277    -- MMCAU Peripheral Access Layer
92278    ---------------------------------------------------------------------------- */
92279 
92280 /*!
92281  * @addtogroup MMCAU_Peripheral_Access_Layer MMCAU Peripheral Access Layer
92282  * @{
92283  */
92284 
92285 /** MMCAU - Register Layout Typedef */
92286 typedef struct {
92287   __IO uint32_t CASR;                              /**< Status Register, offset: 0x0 */
92288   __IO uint32_t CAA;                               /**< Accumulator, offset: 0x4 */
92289   __IO uint32_t CA[9];                             /**< General Purpose Register, array offset: 0x8, array step: 0x4 */
92290 } MMCAU_Type;
92291 
92292 /* ----------------------------------------------------------------------------
92293    -- MMCAU Register Masks
92294    ---------------------------------------------------------------------------- */
92295 
92296 /*!
92297  * @addtogroup MMCAU_Register_Masks MMCAU Register Masks
92298  * @{
92299  */
92300 
92301 /*! @name CASR - Status Register */
92302 /*! @{ */
92303 #define MMCAU_CASR_IC_MASK                       (0x1U)
92304 #define MMCAU_CASR_IC_SHIFT                      (0U)
92305 /*! IC - Illegal Command
92306  *  0b0..No illegal commands issued.
92307  *  0b1..Illegal command issued.
92308  */
92309 #define MMCAU_CASR_IC(x)                         (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_IC_SHIFT)) & MMCAU_CASR_IC_MASK)
92310 #define MMCAU_CASR_DPE_MASK                      (0x2U)
92311 #define MMCAU_CASR_DPE_SHIFT                     (1U)
92312 /*! DPE - DES Parity Error
92313  *  0b0..No error detected.
92314  *  0b1..DES key parity error detected.
92315  */
92316 #define MMCAU_CASR_DPE(x)                        (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_DPE_SHIFT)) & MMCAU_CASR_DPE_MASK)
92317 #define MMCAU_CASR_VER_MASK                      (0xF0000000U)
92318 #define MMCAU_CASR_VER_SHIFT                     (28U)
92319 /*! VER - CAU Version
92320  *  0b0001..Initial CAU version.
92321  *  0b0010..Second version, added support for SHA-256 algorithm (This is the value on this device).
92322  */
92323 #define MMCAU_CASR_VER(x)                        (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_VER_SHIFT)) & MMCAU_CASR_VER_MASK)
92324 /*! @} */
92325 
92326 /*! @name CAA - Accumulator */
92327 /*! @{ */
92328 #define MMCAU_CAA_ACC_MASK                       (0xFFFFFFFFU)
92329 #define MMCAU_CAA_ACC_SHIFT                      (0U)
92330 /*! ACC - Accumulator
92331  */
92332 #define MMCAU_CAA_ACC(x)                         (((uint32_t)(((uint32_t)(x)) << MMCAU_CAA_ACC_SHIFT)) & MMCAU_CAA_ACC_MASK)
92333 /*! @} */
92334 
92335 /*! @name CA - General Purpose Register */
92336 /*! @{ */
92337 #define MMCAU_CA_CAn_MASK                        (0xFFFFFFFFU)
92338 #define MMCAU_CA_CAn_SHIFT                       (0U)
92339 /*! CAn - General Purpose Registers
92340  */
92341 #define MMCAU_CA_CAn(x)                          (((uint32_t)(((uint32_t)(x)) << MMCAU_CA_CAn_SHIFT)) & MMCAU_CA_CAn_MASK)
92342 /*! @} */
92343 
92344 /* The count of MMCAU_CA */
92345 #define MMCAU_CA_COUNT                           (9U)
92346 
92347 
92348 /*!
92349  * @}
92350  */ /* end of group MMCAU_Register_Masks */
92351 
92352 
92353 /* MMCAU - Peripheral instance base addresses */
92354 /** Peripheral MMCAU base address */
92355 #define MMCAU_BASE                               (0xE0081000u)
92356 /** Peripheral MMCAU base pointer */
92357 #define MMCAU                                    ((MMCAU_Type *)MMCAU_BASE)
92358 /** Array initializer of MMCAU peripheral base addresses */
92359 #define MMCAU_BASE_ADDRS                         { MMCAU_BASE }
92360 /** Array initializer of MMCAU peripheral base pointers */
92361 #define MMCAU_BASE_PTRS                          { MMCAU }
92362 
92363 /*!
92364  * @}
92365  */ /* end of group MMCAU_Peripheral_Access_Layer */
92366 
92367 
92368 /* ----------------------------------------------------------------------------
92369    -- MQS Peripheral Access Layer
92370    ---------------------------------------------------------------------------- */
92371 
92372 /*!
92373  * @addtogroup MQS_Peripheral_Access_Layer MQS Peripheral Access Layer
92374  * @{
92375  */
92376 
92377 /** MQS - Register Layout Typedef */
92378 typedef struct {
92379   __IO uint32_t MCR;                               /**< MQS Configuration Register, offset: 0x0 */
92380 } MQS_Type;
92381 
92382 /* ----------------------------------------------------------------------------
92383    -- MQS Register Masks
92384    ---------------------------------------------------------------------------- */
92385 
92386 /*!
92387  * @addtogroup MQS_Register_Masks MQS Register Masks
92388  * @{
92389  */
92390 
92391 /*! @name MCR - MQS Configuration Register */
92392 /*! @{ */
92393 #define MQS_MCR_DIV_MASK                         (0xFFU)
92394 #define MQS_MCR_DIV_SHIFT                        (0U)
92395 /*! DIV - Clock Divider Ratio
92396  *  0bxxxxxxxx..MQS clock = SAI output clock/(DIV+1)
92397  */
92398 #define MQS_MCR_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << MQS_MCR_DIV_SHIFT)) & MQS_MCR_DIV_MASK)
92399 #define MQS_MCR_OVR_MASK                         (0x100000U)
92400 #define MQS_MCR_OVR_SHIFT                        (20U)
92401 /*! OVR - PWM Oversampling Ratio
92402  *  0b0..32
92403  *  0b1..64
92404  */
92405 #define MQS_MCR_OVR(x)                           (((uint32_t)(((uint32_t)(x)) << MQS_MCR_OVR_SHIFT)) & MQS_MCR_OVR_MASK)
92406 #define MQS_MCR_RST_MASK                         (0x1000000U)
92407 #define MQS_MCR_RST_SHIFT                        (24U)
92408 /*! RST - Software Reset
92409  *  0b0..Negate Reset
92410  *  0b1..Assert Reset
92411  */
92412 #define MQS_MCR_RST(x)                           (((uint32_t)(((uint32_t)(x)) << MQS_MCR_RST_SHIFT)) & MQS_MCR_RST_MASK)
92413 #define MQS_MCR_ENB_MASK                         (0x10000000U)
92414 #define MQS_MCR_ENB_SHIFT                        (28U)
92415 /*! ENB - MQS Module Enable
92416  *  0b0..Disable MQS
92417  *  0b1..Enable MQS
92418  */
92419 #define MQS_MCR_ENB(x)                           (((uint32_t)(((uint32_t)(x)) << MQS_MCR_ENB_SHIFT)) & MQS_MCR_ENB_MASK)
92420 /*! @} */
92421 
92422 
92423 /*!
92424  * @}
92425  */ /* end of group MQS_Register_Masks */
92426 
92427 
92428 /* MQS - Peripheral instance base addresses */
92429 /** Peripheral ADMA__MQS base address */
92430 #define ADMA__MQS_BASE                           (0x59850000u)
92431 /** Peripheral ADMA__MQS base pointer */
92432 #define ADMA__MQS                                ((MQS_Type *)ADMA__MQS_BASE)
92433 /** Array initializer of MQS peripheral base addresses */
92434 #define MQS_BASE_ADDRS                           { ADMA__MQS_BASE }
92435 /** Array initializer of MQS peripheral base pointers */
92436 #define MQS_BASE_PTRS                            { ADMA__MQS }
92437 
92438 /*!
92439  * @}
92440  */ /* end of group MQS_Peripheral_Access_Layer */
92441 
92442 /*!
92443  * @brief Core B boot mode.
92444  */
92445 typedef enum _mu_core_boot_mode
92446 {
92447     kMU_CoreBootFromAddr0 = 0x00U, /*!< Boot from 0x00.      */
92448     kMU_CoreBootFromDmem = 0x01U, /*!< Boot from DMEM base. */
92449     kMU_CoreBootFromImem = 0x02U, /*!< Boot from IMEM base. */
92450 } mu_core_boot_mode_t;
92451 
92452 /*!
92453  * @brief Power mode definition.
92454  */
92455 typedef enum _mu_power_mode
92456 {
92457     kMU_PowerModeRun   = 0x00U, /*!< Run mode.      */
92458     kMU_PowerModeWait  = 0x01U, /*!< WAIT mode. */
92459     kMU_PowerModeStop  = 0x02U, /*!< STOP/VLPS mode. */
92460     kMU_PowerModeDsm   = 0x03U, /*!< DSM: LLS/VLLS mode. */
92461 } mu_power_mode_t;
92462 
92463 
92464 /* ----------------------------------------------------------------------------
92465    -- MU Peripheral Access Layer
92466    ---------------------------------------------------------------------------- */
92467 
92468 /*!
92469  * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
92470  * @{
92471  */
92472 
92473 /** MU - Register Layout Typedef */
92474 typedef struct {
92475   __IO uint32_t TR[4];                             /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4 */
92476   __I  uint32_t RR[4];                             /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4 */
92477   __IO uint32_t SR;                                /**< Processor B Status Register, offset: 0x20 */
92478   __IO uint32_t CR;                                /**< Processor B Control Register, offset: 0x24 */
92479 } MU_Type;
92480 
92481 /* ----------------------------------------------------------------------------
92482    -- MU Register Masks
92483    ---------------------------------------------------------------------------- */
92484 
92485 /*!
92486  * @addtogroup MU_Register_Masks MU Register Masks
92487  * @{
92488  */
92489 
92490 /*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */
92491 /*! @{ */
92492 #define MU_TR_ATR0_MASK                          (0xFFFFFFFFU)
92493 #define MU_TR_ATR0_SHIFT                         (0U)
92494 /*! ATR0 - ATR0
92495  */
92496 #define MU_TR_ATR0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_ATR0_SHIFT)) & MU_TR_ATR0_MASK)
92497 #define MU_TR_ATR1_MASK                          (0xFFFFFFFFU)
92498 #define MU_TR_ATR1_SHIFT                         (0U)
92499 /*! ATR1 - ATR1
92500  */
92501 #define MU_TR_ATR1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_ATR1_SHIFT)) & MU_TR_ATR1_MASK)
92502 #define MU_TR_ATR2_MASK                          (0xFFFFFFFFU)
92503 #define MU_TR_ATR2_SHIFT                         (0U)
92504 /*! ATR2 - ATR2
92505  */
92506 #define MU_TR_ATR2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_ATR2_SHIFT)) & MU_TR_ATR2_MASK)
92507 #define MU_TR_ATR3_MASK                          (0xFFFFFFFFU)
92508 #define MU_TR_ATR3_SHIFT                         (0U)
92509 /*! ATR3 - ATR3
92510  */
92511 #define MU_TR_ATR3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_ATR3_SHIFT)) & MU_TR_ATR3_MASK)
92512 #define MU_TR_BTR0_MASK                          (0xFFFFFFFFU)
92513 #define MU_TR_BTR0_SHIFT                         (0U)
92514 /*! BTR0 - BTR0
92515  */
92516 #define MU_TR_BTR0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR0_SHIFT)) & MU_TR_BTR0_MASK)
92517 #define MU_TR_BTR1_MASK                          (0xFFFFFFFFU)
92518 #define MU_TR_BTR1_SHIFT                         (0U)
92519 /*! BTR1 - BTR1
92520  */
92521 #define MU_TR_BTR1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR1_SHIFT)) & MU_TR_BTR1_MASK)
92522 #define MU_TR_BTR2_MASK                          (0xFFFFFFFFU)
92523 #define MU_TR_BTR2_SHIFT                         (0U)
92524 /*! BTR2 - BTR2
92525  */
92526 #define MU_TR_BTR2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
92527 #define MU_TR_BTR3_MASK                          (0xFFFFFFFFU)
92528 #define MU_TR_BTR3_SHIFT                         (0U)
92529 /*! BTR3 - BTR3
92530  */
92531 #define MU_TR_BTR3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR3_SHIFT)) & MU_TR_BTR3_MASK)
92532 /*! @} */
92533 
92534 /* The count of MU_TR */
92535 #define MU_TR_COUNT                              (4U)
92536 
92537 /*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */
92538 /*! @{ */
92539 #define MU_RR_ARR0_MASK                          (0xFFFFFFFFU)
92540 #define MU_RR_ARR0_SHIFT                         (0U)
92541 /*! ARR0 - ARR0
92542  */
92543 #define MU_RR_ARR0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_ARR0_SHIFT)) & MU_RR_ARR0_MASK)
92544 #define MU_RR_ARR1_MASK                          (0xFFFFFFFFU)
92545 #define MU_RR_ARR1_SHIFT                         (0U)
92546 /*! ARR1 - ARR1
92547  */
92548 #define MU_RR_ARR1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_ARR1_SHIFT)) & MU_RR_ARR1_MASK)
92549 #define MU_RR_ARR2_MASK                          (0xFFFFFFFFU)
92550 #define MU_RR_ARR2_SHIFT                         (0U)
92551 /*! ARR2 - ARR2
92552  */
92553 #define MU_RR_ARR2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_ARR2_SHIFT)) & MU_RR_ARR2_MASK)
92554 #define MU_RR_ARR3_MASK                          (0xFFFFFFFFU)
92555 #define MU_RR_ARR3_SHIFT                         (0U)
92556 /*! ARR3 - ARR3
92557  */
92558 #define MU_RR_ARR3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_ARR3_SHIFT)) & MU_RR_ARR3_MASK)
92559 #define MU_RR_BRR0_MASK                          (0xFFFFFFFFU)
92560 #define MU_RR_BRR0_SHIFT                         (0U)
92561 /*! BRR0 - BRR0
92562  */
92563 #define MU_RR_BRR0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR0_SHIFT)) & MU_RR_BRR0_MASK)
92564 #define MU_RR_BRR1_MASK                          (0xFFFFFFFFU)
92565 #define MU_RR_BRR1_SHIFT                         (0U)
92566 /*! BRR1 - BRR1
92567  */
92568 #define MU_RR_BRR1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR1_SHIFT)) & MU_RR_BRR1_MASK)
92569 #define MU_RR_BRR2_MASK                          (0xFFFFFFFFU)
92570 #define MU_RR_BRR2_SHIFT                         (0U)
92571 /*! BRR2 - BRR2
92572  */
92573 #define MU_RR_BRR2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR2_SHIFT)) & MU_RR_BRR2_MASK)
92574 #define MU_RR_BRR3_MASK                          (0xFFFFFFFFU)
92575 #define MU_RR_BRR3_SHIFT                         (0U)
92576 /*! BRR3 - BRR3
92577  */
92578 #define MU_RR_BRR3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR3_SHIFT)) & MU_RR_BRR3_MASK)
92579 /*! @} */
92580 
92581 /* The count of MU_RR */
92582 #define MU_RR_COUNT                              (4U)
92583 
92584 /*! @name SR - Processor B Status Register */
92585 /*! @{ */
92586 #define MU_SR_Fn_MASK                            (0x7U)
92587 #define MU_SR_Fn_SHIFT                           (0U)
92588 /*! Fn - Fn
92589  *  0b000..BAFn bit in BCR register is written 0 (default).
92590  *  0b001..BAFn bit in BCR register is written 1.
92591  */
92592 #define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
92593 #define MU_SR_EP_MASK                            (0x10U)
92594 #define MU_SR_EP_SHIFT                           (4U)
92595 /*! EP - EP
92596  *  0b0..The Processor A-side event is not pending (default).
92597  *  0b1..The Processor A-side event is pending.
92598  */
92599 #define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
92600 #define MU_SR_APM_MASK                           (0x60U)
92601 #define MU_SR_APM_SHIFT                          (5U)
92602 /*! APM - APM
92603  *  0b00..The System is in Run Mode.
92604  *  0b01..The System is in WAIT Mode.
92605  *  0b10..Reserved.
92606  *  0b11..The System is in STOP Mode.
92607  */
92608 #define MU_SR_APM(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_APM_SHIFT)) & MU_SR_APM_MASK)
92609 #define MU_SR_ARS_MASK                           (0x80U)
92610 #define MU_SR_ARS_SHIFT                          (7U)
92611 /*! ARS - ARS
92612  *  0b0..The Processor A or the Processor A-side of the MU is not in reset.
92613  *  0b1..The Processor A or the Processor A-side of the MU is in reset.
92614  */
92615 #define MU_SR_ARS(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_ARS_SHIFT)) & MU_SR_ARS_MASK)
92616 #define MU_SR_BRS_MASK                           (0x80U)
92617 #define MU_SR_BRS_SHIFT                          (7U)
92618 /*! BRS - BRS
92619  *  0b0..The Processor B-side of the MU is not in reset.
92620  *  0b1..The Processor B-side of the MU is in reset.
92621  */
92622 #define MU_SR_BRS(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_BRS_SHIFT)) & MU_SR_BRS_MASK)
92623 #define MU_SR_FUP_MASK                           (0x100U)
92624 #define MU_SR_FUP_SHIFT                          (8U)
92625 /*! FUP - FUP
92626  *  0b0..No flags updated, initiated by the Processor A, in progress (default)
92627  *  0b1..Processor A initiated flags update, processing
92628  */
92629 #define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
92630 #define MU_SR_BRDIP_MASK                         (0x200U)
92631 #define MU_SR_BRDIP_SHIFT                        (9U)
92632 /*! BRDIP - BRDIP
92633  *  0b0..The Processor A general purpose interrupt 3, because of a Processor B-side reset de-assertion, is cleared (default).
92634  *  0b1..The Processor B-side is out of reset.
92635  */
92636 #define MU_SR_BRDIP(x)                           (((uint32_t)(((uint32_t)(x)) << MU_SR_BRDIP_SHIFT)) & MU_SR_BRDIP_MASK)
92637 #define MU_SR_TEn_MASK                           (0xF00000U)
92638 #define MU_SR_TEn_SHIFT                          (20U)
92639 /*! TEn - TEn
92640  *  0b0000..ATRn register is not empty.
92641  *  0b0001..ATRn register is empty (default).
92642  */
92643 #define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
92644 #define MU_SR_RFn_MASK                           (0xF000000U)
92645 #define MU_SR_RFn_SHIFT                          (24U)
92646 /*! RFn - RFn
92647  *  0b0000..ARRn register is not full (default).
92648  *  0b0001..ARRn register has received data from BTRn register and is ready to be read by the Processor A.
92649  */
92650 #define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
92651 #define MU_SR_GIPn_MASK                          (0xF0000000U)
92652 #define MU_SR_GIPn_SHIFT                         (28U)
92653 /*! GIPn - GIPn
92654  *  0b0000..Processor A general purpose interrupt n is not pending. (default)
92655  *  0b0001..Processor A general purpose interrupt n is pending.
92656  */
92657 #define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
92658 /*! @} */
92659 
92660 /*! @name CR - Processor B Control Register */
92661 /*! @{ */
92662 #define MU_CR_ABFn_MASK                          (0x7U)
92663 #define MU_CR_ABFn_SHIFT                         (0U)
92664 /*! ABFn - ABFn
92665  *  0b000..N/A. Self clearing bit (default).
92666  *  0b001..Asserts the Processor A MU reset.
92667  */
92668 #define MU_CR_ABFn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_ABFn_SHIFT)) & MU_CR_ABFn_MASK)
92669 #define MU_CR_BAFn_MASK                          (0x7U)
92670 #define MU_CR_BAFn_SHIFT                         (0U)
92671 /*! BAFn - BAFn
92672  *  0b000..Clears the Fn bit in the ASR register.
92673  *  0b001..Sets the Fn bit in the ASR register.
92674  */
92675 #define MU_CR_BAFn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_BAFn_SHIFT)) & MU_CR_BAFn_MASK)
92676 #define MU_CR_BHR_MASK                           (0x10U)
92677 #define MU_CR_BHR_SHIFT                          (4U)
92678 /*! BHR - BHR
92679  *  0b0..De-assert Hardware reset to the Processor B. (default)
92680  *  0b1..Assert Hardware reset to the Processor B.
92681  */
92682 #define MU_CR_BHR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_BHR_SHIFT)) & MU_CR_BHR_MASK)
92683 #define MU_CR_HRM_MASK                           (0x10U)
92684 #define MU_CR_HRM_SHIFT                          (4U)
92685 /*! HRM - HRM
92686  *  0b0..BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset).
92687  *  0b1..BHR bit in ACR is masked, disables the hardware reset request to the Processor B.
92688  */
92689 #define MU_CR_HRM(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_HRM_SHIFT)) & MU_CR_HRM_MASK)
92690 #define MU_CR_MUR_MASK                           (0x20U)
92691 #define MU_CR_MUR_SHIFT                          (5U)
92692 /*! MUR - MUR
92693  *  0b0..N/A. Self clearing bit (default).
92694  *  0b1..Asserts the Processor A MU reset.
92695  */
92696 #define MU_CR_MUR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
92697 #define MU_CR_BRDIE_MASK                         (0x40U)
92698 #define MU_CR_BRDIE_SHIFT                        (6U)
92699 /*! BRDIE - BRDIE
92700  *  0b0..Disables the Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion to
92701  *       the Processor A. Processor B reset deassertion causes Processor B and MU-Processor B side to come out of
92702  *       reset thus setting BRDIP bit to "1".
92703  *  0b1..Enables Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion to the Processor A.
92704  */
92705 #define MU_CR_BRDIE(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CR_BRDIE_SHIFT)) & MU_CR_BRDIE_MASK)
92706 #define MU_CR_GIRn_MASK                          (0xF0000U)
92707 #define MU_CR_GIRn_SHIFT                         (16U)
92708 /*! GIRn - GIRn
92709  *  0b0000..Processor A General Interrupt n is not requested to the Processor B (default).
92710  *  0b0001..Processor A General Interrupt n is requested to the Processor B.
92711  */
92712 #define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
92713 #define MU_CR_TIEn_MASK                          (0xF00000U)
92714 #define MU_CR_TIEn_SHIFT                         (20U)
92715 /*! TIEn - TIEn
92716  *  0b0000..Disables Processor A Transmit Interrupt n. (default)
92717  *  0b0001..Enables Processor A Transmit Interrupt n.
92718  */
92719 #define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
92720 #define MU_CR_RIEn_MASK                          (0xF000000U)
92721 #define MU_CR_RIEn_SHIFT                         (24U)
92722 /*! RIEn - RIEn
92723  *  0b0000..Disables Processor A Receive Interrupt n. (default)
92724  *  0b0001..Enables Processor A Receive Interrupt n.
92725  */
92726 #define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
92727 #define MU_CR_GIEn_MASK                          (0xF0000000U)
92728 #define MU_CR_GIEn_SHIFT                         (28U)
92729 /*! GIEn - GIEn
92730  *  0b0000..Disables Processor A General Interrupt n. (default)
92731  *  0b0001..Enables Processor A General Interrupt n.
92732  */
92733 #define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
92734 /*! @} */
92735 
92736 
92737 /*!
92738  * @}
92739  */ /* end of group MU_Register_Masks */
92740 
92741 
92742 /* MU - Peripheral instance base addresses */
92743 /** Peripheral CM4__MU0_A0 base address */
92744 #define CM4__MU0_A0_BASE                         (0x41440000u)
92745 /** Peripheral CM4__MU0_A0 base pointer */
92746 #define CM4__MU0_A0                              ((MU_Type *)CM4__MU0_A0_BASE)
92747 /** Peripheral CM4__MU0_A1 base address */
92748 #define CM4__MU0_A1_BASE                         (0x41450000u)
92749 /** Peripheral CM4__MU0_A1 base pointer */
92750 #define CM4__MU0_A1                              ((MU_Type *)CM4__MU0_A1_BASE)
92751 /** Peripheral CM4__MU0_A2 base address */
92752 #define CM4__MU0_A2_BASE                         (0x41460000u)
92753 /** Peripheral CM4__MU0_A2 base pointer */
92754 #define CM4__MU0_A2                              ((MU_Type *)CM4__MU0_A2_BASE)
92755 /** Peripheral CM4__MU0_A3 base address */
92756 #define CM4__MU0_A3_BASE                         (0x41470000u)
92757 /** Peripheral CM4__MU0_A3 base pointer */
92758 #define CM4__MU0_A3                              ((MU_Type *)CM4__MU0_A3_BASE)
92759 /** Peripheral CM4__MU0_B0 base address */
92760 #define CM4__MU0_B0_BASE                         (0x41430000u)
92761 /** Peripheral CM4__MU0_B0 base pointer */
92762 #define CM4__MU0_B0                              ((MU_Type *)CM4__MU0_B0_BASE)
92763 /** Peripheral CM4__MU0_B1 base address */
92764 #define CM4__MU0_B1_BASE                         (0x41430080u)
92765 /** Peripheral CM4__MU0_B1 base pointer */
92766 #define CM4__MU0_B1                              ((MU_Type *)CM4__MU0_B1_BASE)
92767 /** Peripheral CM4__MU0_B2 base address */
92768 #define CM4__MU0_B2_BASE                         (0x41430100u)
92769 /** Peripheral CM4__MU0_B2 base pointer */
92770 #define CM4__MU0_B2                              ((MU_Type *)CM4__MU0_B2_BASE)
92771 /** Peripheral CM4__MU0_B3 base address */
92772 #define CM4__MU0_B3_BASE                         (0x41430180u)
92773 /** Peripheral CM4__MU0_B3 base pointer */
92774 #define CM4__MU0_B3                              ((MU_Type *)CM4__MU0_B3_BASE)
92775 /** Peripheral CM4__MU1_A base address */
92776 #define CM4__MU1_A_BASE                          (0x41480000u)
92777 /** Peripheral CM4__MU1_A base pointer */
92778 #define CM4__MU1_A                               ((MU_Type *)CM4__MU1_A_BASE)
92779 /** Peripheral LSIO__MU0_A base address */
92780 #define LSIO__MU0_A_BASE                         (0x5D1B0000u)
92781 /** Peripheral LSIO__MU0_A base pointer */
92782 #define LSIO__MU0_A                              ((MU_Type *)LSIO__MU0_A_BASE)
92783 /** Peripheral LSIO__MU1_A base address */
92784 #define LSIO__MU1_A_BASE                         (0x5D1C0000u)
92785 /** Peripheral LSIO__MU1_A base pointer */
92786 #define LSIO__MU1_A                              ((MU_Type *)LSIO__MU1_A_BASE)
92787 /** Peripheral LSIO__MU2_A base address */
92788 #define LSIO__MU2_A_BASE                         (0x5D1D0000u)
92789 /** Peripheral LSIO__MU2_A base pointer */
92790 #define LSIO__MU2_A                              ((MU_Type *)LSIO__MU2_A_BASE)
92791 /** Peripheral LSIO__MU3_A base address */
92792 #define LSIO__MU3_A_BASE                         (0x5D1E0000u)
92793 /** Peripheral LSIO__MU3_A base pointer */
92794 #define LSIO__MU3_A                              ((MU_Type *)LSIO__MU3_A_BASE)
92795 /** Peripheral LSIO__MU4_A base address */
92796 #define LSIO__MU4_A_BASE                         (0x5D1F0000u)
92797 /** Peripheral LSIO__MU4_A base pointer */
92798 #define LSIO__MU4_A                              ((MU_Type *)LSIO__MU4_A_BASE)
92799 /** Peripheral LSIO__MU5_A base address */
92800 #define LSIO__MU5_A_BASE                         (0x5D200000u)
92801 /** Peripheral LSIO__MU5_A base pointer */
92802 #define LSIO__MU5_A                              ((MU_Type *)LSIO__MU5_A_BASE)
92803 /** Peripheral LSIO__MU5_B base address */
92804 #define LSIO__MU5_B_BASE                         (0x5D290000u)
92805 /** Peripheral LSIO__MU5_B base pointer */
92806 #define LSIO__MU5_B                              ((MU_Type *)LSIO__MU5_B_BASE)
92807 /** Peripheral LSIO__MU6_A base address */
92808 #define LSIO__MU6_A_BASE                         (0x5D210000u)
92809 /** Peripheral LSIO__MU6_A base pointer */
92810 #define LSIO__MU6_A                              ((MU_Type *)LSIO__MU6_A_BASE)
92811 /** Peripheral LSIO__MU6_B base address */
92812 #define LSIO__MU6_B_BASE                         (0x5D2A0000u)
92813 /** Peripheral LSIO__MU6_B base pointer */
92814 #define LSIO__MU6_B                              ((MU_Type *)LSIO__MU6_B_BASE)
92815 /** Peripheral LSIO__MU7_A base address */
92816 #define LSIO__MU7_A_BASE                         (0x5D220000u)
92817 /** Peripheral LSIO__MU7_A base pointer */
92818 #define LSIO__MU7_A                              ((MU_Type *)LSIO__MU7_A_BASE)
92819 /** Peripheral LSIO__MU7_B base address */
92820 #define LSIO__MU7_B_BASE                         (0x5D2B0000u)
92821 /** Peripheral LSIO__MU7_B base pointer */
92822 #define LSIO__MU7_B                              ((MU_Type *)LSIO__MU7_B_BASE)
92823 /** Peripheral LSIO__MU8_A base address */
92824 #define LSIO__MU8_A_BASE                         (0x5D230000u)
92825 /** Peripheral LSIO__MU8_A base pointer */
92826 #define LSIO__MU8_A                              ((MU_Type *)LSIO__MU8_A_BASE)
92827 /** Peripheral LSIO__MU8_B base address */
92828 #define LSIO__MU8_B_BASE                         (0x5D2C0000u)
92829 /** Peripheral LSIO__MU8_B base pointer */
92830 #define LSIO__MU8_B                              ((MU_Type *)LSIO__MU8_B_BASE)
92831 /** Peripheral LSIO__MU9_A base address */
92832 #define LSIO__MU9_A_BASE                         (0x5D240000u)
92833 /** Peripheral LSIO__MU9_A base pointer */
92834 #define LSIO__MU9_A                              ((MU_Type *)LSIO__MU9_A_BASE)
92835 /** Peripheral LSIO__MU9_B base address */
92836 #define LSIO__MU9_B_BASE                         (0x5D2D0000u)
92837 /** Peripheral LSIO__MU9_B base pointer */
92838 #define LSIO__MU9_B                              ((MU_Type *)LSIO__MU9_B_BASE)
92839 /** Peripheral LSIO__MU10_A base address */
92840 #define LSIO__MU10_A_BASE                        (0x5D250000u)
92841 /** Peripheral LSIO__MU10_A base pointer */
92842 #define LSIO__MU10_A                             ((MU_Type *)LSIO__MU10_A_BASE)
92843 /** Peripheral LSIO__MU10_B base address */
92844 #define LSIO__MU10_B_BASE                        (0x5D2E0000u)
92845 /** Peripheral LSIO__MU10_B base pointer */
92846 #define LSIO__MU10_B                             ((MU_Type *)LSIO__MU10_B_BASE)
92847 /** Peripheral LSIO__MU11_A base address */
92848 #define LSIO__MU11_A_BASE                        (0x5D260000u)
92849 /** Peripheral LSIO__MU11_A base pointer */
92850 #define LSIO__MU11_A                             ((MU_Type *)LSIO__MU11_A_BASE)
92851 /** Peripheral LSIO__MU11_B base address */
92852 #define LSIO__MU11_B_BASE                        (0x5D2F0000u)
92853 /** Peripheral LSIO__MU11_B base pointer */
92854 #define LSIO__MU11_B                             ((MU_Type *)LSIO__MU11_B_BASE)
92855 /** Peripheral LSIO__MU12_A base address */
92856 #define LSIO__MU12_A_BASE                        (0x5D270000u)
92857 /** Peripheral LSIO__MU12_A base pointer */
92858 #define LSIO__MU12_A                             ((MU_Type *)LSIO__MU12_A_BASE)
92859 /** Peripheral LSIO__MU12_B base address */
92860 #define LSIO__MU12_B_BASE                        (0x5D300000u)
92861 /** Peripheral LSIO__MU12_B base pointer */
92862 #define LSIO__MU12_B                             ((MU_Type *)LSIO__MU12_B_BASE)
92863 /** Peripheral LSIO__MU13_A base address */
92864 #define LSIO__MU13_A_BASE                        (0x5D280000u)
92865 /** Peripheral LSIO__MU13_A base pointer */
92866 #define LSIO__MU13_A                             ((MU_Type *)LSIO__MU13_A_BASE)
92867 /** Peripheral LSIO__MU13_B base address */
92868 #define LSIO__MU13_B_BASE                        (0x5D310000u)
92869 /** Peripheral LSIO__MU13_B base pointer */
92870 #define LSIO__MU13_B                             ((MU_Type *)LSIO__MU13_B_BASE)
92871 /** Peripheral SCU__MU0_A0 base address */
92872 #define SCU__MU0_A0_BASE                         (0x33440000u)
92873 /** Peripheral SCU__MU0_A0 base pointer */
92874 #define SCU__MU0_A0                              ((MU_Type *)SCU__MU0_A0_BASE)
92875 /** Peripheral SCU__MU0_A1 base address */
92876 #define SCU__MU0_A1_BASE                         (0x33450000u)
92877 /** Peripheral SCU__MU0_A1 base pointer */
92878 #define SCU__MU0_A1                              ((MU_Type *)SCU__MU0_A1_BASE)
92879 /** Peripheral SCU__MU0_A2 base address */
92880 #define SCU__MU0_A2_BASE                         (0x33460000u)
92881 /** Peripheral SCU__MU0_A2 base pointer */
92882 #define SCU__MU0_A2                              ((MU_Type *)SCU__MU0_A2_BASE)
92883 /** Peripheral SCU__MU0_A3 base address */
92884 #define SCU__MU0_A3_BASE                         (0x33470000u)
92885 /** Peripheral SCU__MU0_A3 base pointer */
92886 #define SCU__MU0_A3                              ((MU_Type *)SCU__MU0_A3_BASE)
92887 /** Peripheral SCU__MU0_B0 base address */
92888 #define SCU__MU0_B0_BASE                         (0x33430000u)
92889 /** Peripheral SCU__MU0_B0 base pointer */
92890 #define SCU__MU0_B0                              ((MU_Type *)SCU__MU0_B0_BASE)
92891 /** Peripheral SCU__MU0_B1 base address */
92892 #define SCU__MU0_B1_BASE                         (0x33430080u)
92893 /** Peripheral SCU__MU0_B1 base pointer */
92894 #define SCU__MU0_B1                              ((MU_Type *)SCU__MU0_B1_BASE)
92895 /** Peripheral SCU__MU0_B2 base address */
92896 #define SCU__MU0_B2_BASE                         (0x33430100u)
92897 /** Peripheral SCU__MU0_B2 base pointer */
92898 #define SCU__MU0_B2                              ((MU_Type *)SCU__MU0_B2_BASE)
92899 /** Peripheral SCU__MU0_B3 base address */
92900 #define SCU__MU0_B3_BASE                         (0x33430180u)
92901 /** Peripheral SCU__MU0_B3 base pointer */
92902 #define SCU__MU0_B3                              ((MU_Type *)SCU__MU0_B3_BASE)
92903 /** Peripheral SCU__MU1_A base address */
92904 #define SCU__MU1_A_BASE                          (0x33480000u)
92905 /** Peripheral SCU__MU1_A base pointer */
92906 #define SCU__MU1_A                               ((MU_Type *)SCU__MU1_A_BASE)
92907 /** Array initializer of MU peripheral base addresses */
92908 #define MU_BASE_ADDRS                            { CM4__MU0_A0_BASE, CM4__MU0_A1_BASE, CM4__MU0_A2_BASE, CM4__MU0_A3_BASE, CM4__MU0_B0_BASE, CM4__MU0_B1_BASE, CM4__MU0_B2_BASE, CM4__MU0_B3_BASE, CM4__MU1_A_BASE, LSIO__MU0_A_BASE, LSIO__MU1_A_BASE, LSIO__MU2_A_BASE, LSIO__MU3_A_BASE, LSIO__MU4_A_BASE, LSIO__MU5_A_BASE, LSIO__MU5_B_BASE, LSIO__MU6_A_BASE, LSIO__MU6_B_BASE, LSIO__MU7_A_BASE, LSIO__MU7_B_BASE, LSIO__MU8_A_BASE, LSIO__MU8_B_BASE, LSIO__MU9_A_BASE, LSIO__MU9_B_BASE, LSIO__MU10_A_BASE, LSIO__MU10_B_BASE, LSIO__MU11_A_BASE, LSIO__MU11_B_BASE, LSIO__MU12_A_BASE, LSIO__MU12_B_BASE, LSIO__MU13_A_BASE, LSIO__MU13_B_BASE, SCU__MU0_A0_BASE, SCU__MU0_A1_BASE, SCU__MU0_A2_BASE, SCU__MU0_A3_BASE, SCU__MU0_B0_BASE, SCU__MU0_B1_BASE, SCU__MU0_B2_BASE, SCU__MU0_B3_BASE, SCU__MU1_A_BASE }
92909 /** Array initializer of MU peripheral base pointers */
92910 #define MU_BASE_PTRS                             { CM4__MU0_A0, CM4__MU0_A1, CM4__MU0_A2, CM4__MU0_A3, CM4__MU0_B0, CM4__MU0_B1, CM4__MU0_B2, CM4__MU0_B3, CM4__MU1_A, LSIO__MU0_A, LSIO__MU1_A, LSIO__MU2_A, LSIO__MU3_A, LSIO__MU4_A, LSIO__MU5_A, LSIO__MU5_B, LSIO__MU6_A, LSIO__MU6_B, LSIO__MU7_A, LSIO__MU7_B, LSIO__MU8_A, LSIO__MU8_B, LSIO__MU9_A, LSIO__MU9_B, LSIO__MU10_A, LSIO__MU10_B, LSIO__MU11_A, LSIO__MU11_B, LSIO__MU12_A, LSIO__MU12_B, LSIO__MU13_A, LSIO__MU13_B, SCU__MU0_A0, SCU__MU0_A1, SCU__MU0_A2, SCU__MU0_A3, SCU__MU0_B0, SCU__MU0_B1, SCU__MU0_B2, SCU__MU0_B3, SCU__MU1_A }
92911 /* Backward compatibility */
92912 #define MU_SR_PM_MASK                             MU_SR_APM_MASK
92913 #define MU_SR_PM_SHIFT                            MU_SR_APM_SHIFT
92914 #define MU_SR_PM(x)                               MU_SR_APM(x)
92915 #define MU_SR_RS_MASK                             MU_SR_ARS_MASK
92916 #define MU_SR_RS_SHIFT                            MU_SR_ARS_SHIFT
92917 #define MU_SR_RS(x)                               MU_SR_ARS(x)
92918 #define MU_CR_Fn_MASK                             MU_CR_BAFn_MASK
92919 #define MU_CR_Fn_SHIFT                            MU_CR_BAFn_SHIFT
92920 #define MU_CR_Fn(x)                               MU_CR_BAFn(x)
92921 
92922 
92923 /*!
92924  * @}
92925  */ /* end of group MU_Peripheral_Access_Layer */
92926 
92927 
92928 /* ----------------------------------------------------------------------------
92929    -- PWM Peripheral Access Layer
92930    ---------------------------------------------------------------------------- */
92931 
92932 /*!
92933  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
92934  * @{
92935  */
92936 
92937 /** PWM - Register Layout Typedef */
92938 typedef struct {
92939   __IO uint32_t PWMCR;                             /**< PWM Control Register, offset: 0x0 */
92940   __IO uint32_t PWMSR;                             /**< PWM Status Register, offset: 0x4 */
92941   __IO uint32_t PWMIR;                             /**< PWM Interrupt Register, offset: 0x8 */
92942   __IO uint32_t PWMSAR;                            /**< PWM Sample Register, offset: 0xC */
92943   __IO uint32_t PWMPR;                             /**< PWM Period Register, offset: 0x10 */
92944   __I  uint32_t PWMCNR;                            /**< PWM Counter Register, offset: 0x14 */
92945 } PWM_Type;
92946 
92947 /* ----------------------------------------------------------------------------
92948    -- PWM Register Masks
92949    ---------------------------------------------------------------------------- */
92950 
92951 /*!
92952  * @addtogroup PWM_Register_Masks PWM Register Masks
92953  * @{
92954  */
92955 
92956 /*! @name PWMCR - PWM Control Register */
92957 /*! @{ */
92958 #define PWM_PWMCR_EN_MASK                        (0x1U)
92959 #define PWM_PWMCR_EN_SHIFT                       (0U)
92960 /*! EN - EN
92961  *  0b0..PWM disabled
92962  *  0b1..PWM enabled
92963  */
92964 #define PWM_PWMCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK)
92965 #define PWM_PWMCR_REPEAT_MASK                    (0x6U)
92966 #define PWM_PWMCR_REPEAT_SHIFT                   (1U)
92967 /*! REPEAT - REPEAT
92968  *  0b00..Use each sample once
92969  *  0b01..Use each sample twice
92970  *  0b10..Use each sample four times
92971  *  0b11..Use each sample eight times
92972  */
92973 #define PWM_PWMCR_REPEAT(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK)
92974 #define PWM_PWMCR_SWR_MASK                       (0x8U)
92975 #define PWM_PWMCR_SWR_SHIFT                      (3U)
92976 /*! SWR - SWR
92977  *  0b0..PWM is out of reset
92978  *  0b1..PWM is undergoing reset
92979  */
92980 #define PWM_PWMCR_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK)
92981 #define PWM_PWMCR_PRESCALER_MASK                 (0xFFF0U)
92982 #define PWM_PWMCR_PRESCALER_SHIFT                (4U)
92983 /*! PRESCALER - PRESCALER
92984  *  0b000000000000..Divide by 1
92985  *  0b000000000001..Divide by 2
92986  *  0b111111111111..Divide by 4096
92987  */
92988 #define PWM_PWMCR_PRESCALER(x)                   (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK)
92989 #define PWM_PWMCR_CLKSRC_MASK                    (0x30000U)
92990 #define PWM_PWMCR_CLKSRC_SHIFT                   (16U)
92991 /*! CLKSRC - CLKSRC
92992  *  0b00..Clock is off
92993  *  0b01..ipg_clk
92994  *  0b10..ipg_clk_highfreq
92995  *  0b11..ipg_clk_32k
92996  */
92997 #define PWM_PWMCR_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK)
92998 #define PWM_PWMCR_POUTC_MASK                     (0xC0000U)
92999 #define PWM_PWMCR_POUTC_SHIFT                    (18U)
93000 /*! POUTC - POUTC
93001  *  0b00..Output pin is set at rollover and cleared at comparison
93002  *  0b01..Output pin is cleared at rollover and set at comparison
93003  *  0b10..PWM output is disconnected
93004  *  0b11..PWM output is disconnected
93005  */
93006 #define PWM_PWMCR_POUTC(x)                       (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK)
93007 #define PWM_PWMCR_HCTR_MASK                      (0x100000U)
93008 #define PWM_PWMCR_HCTR_SHIFT                     (20U)
93009 /*! HCTR - HCTR
93010  *  0b0..Half word swapping does not take place
93011  *  0b1..Half words from write data bus are swapped
93012  */
93013 #define PWM_PWMCR_HCTR(x)                        (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK)
93014 #define PWM_PWMCR_BCTR_MASK                      (0x200000U)
93015 #define PWM_PWMCR_BCTR_SHIFT                     (21U)
93016 /*! BCTR - BCTR
93017  *  0b0..byte ordering remains the same
93018  *  0b1..byte ordering is reversed
93019  */
93020 #define PWM_PWMCR_BCTR(x)                        (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK)
93021 #define PWM_PWMCR_DBGEN_MASK                     (0x400000U)
93022 #define PWM_PWMCR_DBGEN_SHIFT                    (22U)
93023 /*! DBGEN - DBGEN
93024  *  0b0..Inactive in debug mode
93025  *  0b1..Active in debug mode
93026  */
93027 #define PWM_PWMCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK)
93028 #define PWM_PWMCR_WAITEN_MASK                    (0x800000U)
93029 #define PWM_PWMCR_WAITEN_SHIFT                   (23U)
93030 /*! WAITEN - WAITEN
93031  *  0b0..Inactive in wait mode
93032  *  0b1..Active in wait mode
93033  */
93034 #define PWM_PWMCR_WAITEN(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK)
93035 #define PWM_PWMCR_DOZEN_MASK                     (0x1000000U)
93036 #define PWM_PWMCR_DOZEN_SHIFT                    (24U)
93037 /*! DOZEN - DOZEN
93038  *  0b0..Inactive in doze mode
93039  *  0b1..Active in doze mode
93040  */
93041 #define PWM_PWMCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK)
93042 #define PWM_PWMCR_STOPEN_MASK                    (0x2000000U)
93043 #define PWM_PWMCR_STOPEN_SHIFT                   (25U)
93044 /*! STOPEN - STOPEN
93045  *  0b0..Inactive in stop mode
93046  *  0b1..Active in stop mode
93047  */
93048 #define PWM_PWMCR_STOPEN(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK)
93049 #define PWM_PWMCR_FWM_MASK                       (0xC000000U)
93050 #define PWM_PWMCR_FWM_SHIFT                      (26U)
93051 /*! FWM - FWM
93052  *  0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO
93053  *  0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO
93054  *  0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO
93055  *  0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO
93056  */
93057 #define PWM_PWMCR_FWM(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK)
93058 /*! @} */
93059 
93060 /*! @name PWMSR - PWM Status Register */
93061 /*! @{ */
93062 #define PWM_PWMSR_FIFOAV_MASK                    (0x7U)
93063 #define PWM_PWMSR_FIFOAV_SHIFT                   (0U)
93064 /*! FIFOAV - FIFOAV
93065  *  0b000..No data available
93066  *  0b001..1 word of data in FIFO
93067  *  0b010..2 words of data in FIFO
93068  *  0b011..3 words of data in FIFO
93069  *  0b100..4 words of data in FIFO
93070  *  0b101..unused
93071  *  0b110..unused
93072  *  0b111..unused
93073  */
93074 #define PWM_PWMSR_FIFOAV(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK)
93075 #define PWM_PWMSR_FE_MASK                        (0x8U)
93076 #define PWM_PWMSR_FE_SHIFT                       (3U)
93077 /*! FE - FE
93078  *  0b0..Data level is above water mark
93079  *  0b1..When the data level falls below the mark set by FWM field
93080  */
93081 #define PWM_PWMSR_FE(x)                          (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK)
93082 #define PWM_PWMSR_ROV_MASK                       (0x10U)
93083 #define PWM_PWMSR_ROV_SHIFT                      (4U)
93084 /*! ROV - ROV
93085  *  0b0..Roll-over event not occurred
93086  *  0b1..Roll-over event occurred
93087  */
93088 #define PWM_PWMSR_ROV(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK)
93089 #define PWM_PWMSR_CMP_MASK                       (0x20U)
93090 #define PWM_PWMSR_CMP_SHIFT                      (5U)
93091 /*! CMP - CMP
93092  *  0b0..Compare event not occurred
93093  *  0b1..Compare event occurred
93094  */
93095 #define PWM_PWMSR_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK)
93096 #define PWM_PWMSR_FWE_MASK                       (0x40U)
93097 #define PWM_PWMSR_FWE_SHIFT                      (6U)
93098 /*! FWE - FWE
93099  *  0b0..FIFO write error not occurred
93100  *  0b1..FIFO write error occurred
93101  */
93102 #define PWM_PWMSR_FWE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK)
93103 /*! @} */
93104 
93105 /*! @name PWMIR - PWM Interrupt Register */
93106 /*! @{ */
93107 #define PWM_PWMIR_FIE_MASK                       (0x1U)
93108 #define PWM_PWMIR_FIE_SHIFT                      (0U)
93109 /*! FIE - FIE
93110  *  0b0..FIFO Empty interrupt disabled
93111  *  0b1..FIFO Empty interrupt enabled
93112  */
93113 #define PWM_PWMIR_FIE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK)
93114 #define PWM_PWMIR_RIE_MASK                       (0x2U)
93115 #define PWM_PWMIR_RIE_SHIFT                      (1U)
93116 /*! RIE - RIE
93117  *  0b0..Roll-over interrupt not enabled
93118  *  0b1..Roll-over Interrupt enabled
93119  */
93120 #define PWM_PWMIR_RIE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK)
93121 #define PWM_PWMIR_CIE_MASK                       (0x4U)
93122 #define PWM_PWMIR_CIE_SHIFT                      (2U)
93123 /*! CIE - CIE
93124  *  0b0..Compare Interrupt not enabled
93125  *  0b1..Compare Interrupt enabled
93126  */
93127 #define PWM_PWMIR_CIE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK)
93128 /*! @} */
93129 
93130 /*! @name PWMSAR - PWM Sample Register */
93131 /*! @{ */
93132 #define PWM_PWMSAR_SAMPLE_MASK                   (0xFFFFU)
93133 #define PWM_PWMSAR_SAMPLE_SHIFT                  (0U)
93134 /*! SAMPLE - SAMPLE
93135  */
93136 #define PWM_PWMSAR_SAMPLE(x)                     (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK)
93137 /*! @} */
93138 
93139 /*! @name PWMPR - PWM Period Register */
93140 /*! @{ */
93141 #define PWM_PWMPR_PERIOD_MASK                    (0xFFFFU)
93142 #define PWM_PWMPR_PERIOD_SHIFT                   (0U)
93143 /*! PERIOD - PERIOD
93144  */
93145 #define PWM_PWMPR_PERIOD(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK)
93146 /*! @} */
93147 
93148 /*! @name PWMCNR - PWM Counter Register */
93149 /*! @{ */
93150 #define PWM_PWMCNR_COUNT_MASK                    (0xFFFFU)
93151 #define PWM_PWMCNR_COUNT_SHIFT                   (0U)
93152 /*! COUNT - COUNT
93153  */
93154 #define PWM_PWMCNR_COUNT(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK)
93155 /*! @} */
93156 
93157 
93158 /*!
93159  * @}
93160  */ /* end of group PWM_Register_Masks */
93161 
93162 
93163 /* PWM - Peripheral instance base addresses */
93164 /** Peripheral ADMA__PWM base address */
93165 #define ADMA__PWM_BASE                           (0x5A190000u)
93166 /** Peripheral ADMA__PWM base pointer */
93167 #define ADMA__PWM                                ((PWM_Type *)ADMA__PWM_BASE)
93168 /** Peripheral CI_PI__PWM base address */
93169 #define CI_PI__PWM_BASE                          (0x58264000u)
93170 /** Peripheral CI_PI__PWM base pointer */
93171 #define CI_PI__PWM                               ((PWM_Type *)CI_PI__PWM_BASE)
93172 /** Peripheral DI_MIPI_DSI_LVDS_0__PWM base address */
93173 #define DI_MIPI_DSI_LVDS_0__PWM_BASE             (0x56224000u)
93174 /** Peripheral DI_MIPI_DSI_LVDS_0__PWM base pointer */
93175 #define DI_MIPI_DSI_LVDS_0__PWM                  ((PWM_Type *)DI_MIPI_DSI_LVDS_0__PWM_BASE)
93176 /** Peripheral DI_MIPI_DSI_LVDS_1__PWM base address */
93177 #define DI_MIPI_DSI_LVDS_1__PWM_BASE             (0x56244000u)
93178 /** Peripheral DI_MIPI_DSI_LVDS_1__PWM base pointer */
93179 #define DI_MIPI_DSI_LVDS_1__PWM                  ((PWM_Type *)DI_MIPI_DSI_LVDS_1__PWM_BASE)
93180 /** Peripheral LSIO__PWM0 base address */
93181 #define LSIO__PWM0_BASE                          (0x5D000000u)
93182 /** Peripheral LSIO__PWM0 base pointer */
93183 #define LSIO__PWM0                               ((PWM_Type *)LSIO__PWM0_BASE)
93184 /** Peripheral LSIO__PWM1 base address */
93185 #define LSIO__PWM1_BASE                          (0x5D010000u)
93186 /** Peripheral LSIO__PWM1 base pointer */
93187 #define LSIO__PWM1                               ((PWM_Type *)LSIO__PWM1_BASE)
93188 /** Peripheral LSIO__PWM2 base address */
93189 #define LSIO__PWM2_BASE                          (0x5D020000u)
93190 /** Peripheral LSIO__PWM2 base pointer */
93191 #define LSIO__PWM2                               ((PWM_Type *)LSIO__PWM2_BASE)
93192 /** Peripheral LSIO__PWM3 base address */
93193 #define LSIO__PWM3_BASE                          (0x5D030000u)
93194 /** Peripheral LSIO__PWM3 base pointer */
93195 #define LSIO__PWM3                               ((PWM_Type *)LSIO__PWM3_BASE)
93196 /** Peripheral LSIO__PWM4 base address */
93197 #define LSIO__PWM4_BASE                          (0x5D040000u)
93198 /** Peripheral LSIO__PWM4 base pointer */
93199 #define LSIO__PWM4                               ((PWM_Type *)LSIO__PWM4_BASE)
93200 /** Peripheral LSIO__PWM5 base address */
93201 #define LSIO__PWM5_BASE                          (0x5D050000u)
93202 /** Peripheral LSIO__PWM5 base pointer */
93203 #define LSIO__PWM5                               ((PWM_Type *)LSIO__PWM5_BASE)
93204 /** Peripheral LSIO__PWM6 base address */
93205 #define LSIO__PWM6_BASE                          (0x5D060000u)
93206 /** Peripheral LSIO__PWM6 base pointer */
93207 #define LSIO__PWM6                               ((PWM_Type *)LSIO__PWM6_BASE)
93208 /** Peripheral LSIO__PWM7 base address */
93209 #define LSIO__PWM7_BASE                          (0x5D070000u)
93210 /** Peripheral LSIO__PWM7 base pointer */
93211 #define LSIO__PWM7                               ((PWM_Type *)LSIO__PWM7_BASE)
93212 /** Peripheral MIPI_CSI__PWM base address */
93213 #define MIPI_CSI__PWM_BASE                       (0x58224000u)
93214 /** Peripheral MIPI_CSI__PWM base pointer */
93215 #define MIPI_CSI__PWM                            ((PWM_Type *)MIPI_CSI__PWM_BASE)
93216 /** Array initializer of PWM peripheral base addresses */
93217 #define PWM_BASE_ADDRS                           { ADMA__PWM_BASE, CI_PI__PWM_BASE, DI_MIPI_DSI_LVDS_0__PWM_BASE, DI_MIPI_DSI_LVDS_1__PWM_BASE, LSIO__PWM0_BASE, LSIO__PWM1_BASE, LSIO__PWM2_BASE, LSIO__PWM3_BASE, LSIO__PWM4_BASE, LSIO__PWM5_BASE, LSIO__PWM6_BASE, LSIO__PWM7_BASE, MIPI_CSI__PWM_BASE }
93218 /** Array initializer of PWM peripheral base pointers */
93219 #define PWM_BASE_PTRS                            { ADMA__PWM, CI_PI__PWM, DI_MIPI_DSI_LVDS_0__PWM, DI_MIPI_DSI_LVDS_1__PWM, LSIO__PWM0, LSIO__PWM1, LSIO__PWM2, LSIO__PWM3, LSIO__PWM4, LSIO__PWM5, LSIO__PWM6, LSIO__PWM7, MIPI_CSI__PWM }
93220 /** Interrupt vectors for the PWM peripheral type */
93221 #define PWM_IRQS                                 { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LSIO_PWM0_INT_IRQn, LSIO_PWM1_INT_IRQn, LSIO_PWM2_INT_IRQn, LSIO_PWM3_INT_IRQn, LSIO_PWM4_INT_IRQn, LSIO_PWM5_INT_IRQn, LSIO_PWM6_INT_IRQn, LSIO_PWM7_INT_IRQn, NotAvail_IRQn }
93222 
93223 /*!
93224  * @}
93225  */ /* end of group PWM_Peripheral_Access_Layer */
93226 
93227 
93228 /* ----------------------------------------------------------------------------
93229    -- RGPIO Peripheral Access Layer
93230    ---------------------------------------------------------------------------- */
93231 
93232 /*!
93233  * @addtogroup RGPIO_Peripheral_Access_Layer RGPIO Peripheral Access Layer
93234  * @{
93235  */
93236 
93237 /** RGPIO - Register Layout Typedef */
93238 typedef struct {
93239   __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
93240   __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
93241   __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
93242   __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
93243   __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
93244   __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
93245 } RGPIO_Type;
93246 
93247 /* ----------------------------------------------------------------------------
93248    -- RGPIO Register Masks
93249    ---------------------------------------------------------------------------- */
93250 
93251 /*!
93252  * @addtogroup RGPIO_Register_Masks RGPIO Register Masks
93253  * @{
93254  */
93255 
93256 /*! @name PDOR - Port Data Output Register */
93257 /*! @{ */
93258 #define RGPIO_PDOR_PDO_MASK                      (0xFFFFFFFFU)
93259 #define RGPIO_PDOR_PDO_SHIFT                     (0U)
93260 /*! PDO - Port Data Output
93261  */
93262 #define RGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO_SHIFT)) & RGPIO_PDOR_PDO_MASK)
93263 /*! @} */
93264 
93265 /*! @name PSOR - Port Set Output Register */
93266 /*! @{ */
93267 #define RGPIO_PSOR_PTSO_MASK                     (0xFFFFFFFFU)
93268 #define RGPIO_PSOR_PTSO_SHIFT                    (0U)
93269 /*! PTSO - Port Set Output
93270  */
93271 #define RGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO_SHIFT)) & RGPIO_PSOR_PTSO_MASK)
93272 /*! @} */
93273 
93274 /*! @name PCOR - Port Clear Output Register */
93275 /*! @{ */
93276 #define RGPIO_PCOR_PTCO_MASK                     (0xFFFFFFFFU)
93277 #define RGPIO_PCOR_PTCO_SHIFT                    (0U)
93278 /*! PTCO - Port Clear Output
93279  */
93280 #define RGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO_SHIFT)) & RGPIO_PCOR_PTCO_MASK)
93281 /*! @} */
93282 
93283 /*! @name PTOR - Port Toggle Output Register */
93284 /*! @{ */
93285 #define RGPIO_PTOR_PTTO_MASK                     (0xFFFFFFFFU)
93286 #define RGPIO_PTOR_PTTO_SHIFT                    (0U)
93287 /*! PTTO - Port Toggle Output
93288  */
93289 #define RGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO_SHIFT)) & RGPIO_PTOR_PTTO_MASK)
93290 /*! @} */
93291 
93292 /*! @name PDIR - Port Data Input Register */
93293 /*! @{ */
93294 #define RGPIO_PDIR_PDI_MASK                      (0xFFFFFFFFU)
93295 #define RGPIO_PDIR_PDI_SHIFT                     (0U)
93296 /*! PDI - Port Data Input
93297  */
93298 #define RGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI_SHIFT)) & RGPIO_PDIR_PDI_MASK)
93299 /*! @} */
93300 
93301 /*! @name PDDR - Port Data Direction Register */
93302 /*! @{ */
93303 #define RGPIO_PDDR_PDD_MASK                      (0xFFFFFFFFU)
93304 #define RGPIO_PDDR_PDD_SHIFT                     (0U)
93305 /*! PDD - Port Data Direction
93306  */
93307 #define RGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD_SHIFT)) & RGPIO_PDDR_PDD_MASK)
93308 /*! @} */
93309 
93310 
93311 /*!
93312  * @}
93313  */ /* end of group RGPIO_Register_Masks */
93314 
93315 
93316 /* RGPIO - Peripheral instance base addresses */
93317 /** Peripheral CM4__RGPIO base address */
93318 #define CM4__RGPIO_BASE                          (0x410F0000u)
93319 /** Peripheral CM4__RGPIO base pointer */
93320 #define CM4__RGPIO                               ((RGPIO_Type *)CM4__RGPIO_BASE)
93321 /** Peripheral SCU__RGPIO base address */
93322 #define SCU__RGPIO_BASE                          (0x330F0000u)
93323 /** Peripheral SCU__RGPIO base pointer */
93324 #define SCU__RGPIO                               ((RGPIO_Type *)SCU__RGPIO_BASE)
93325 /** Array initializer of RGPIO peripheral base addresses */
93326 #define RGPIO_BASE_ADDRS                         { CM4__RGPIO_BASE, SCU__RGPIO_BASE }
93327 /** Array initializer of RGPIO peripheral base pointers */
93328 #define RGPIO_BASE_PTRS                          { CM4__RGPIO, SCU__RGPIO }
93329 
93330 /*!
93331  * @}
93332  */ /* end of group RGPIO_Peripheral_Access_Layer */
93333 
93334 
93335 /* ----------------------------------------------------------------------------
93336    -- ROMCP Peripheral Access Layer
93337    ---------------------------------------------------------------------------- */
93338 
93339 /*!
93340  * @addtogroup ROMCP_Peripheral_Access_Layer ROMCP Peripheral Access Layer
93341  * @{
93342  */
93343 
93344 /** ROMCP - Register Layout Typedef */
93345 typedef struct {
93346        uint8_t RESERVED_0[212];
93347   __IO uint32_t ROMPATCHD[8];                      /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
93348   __IO uint32_t ROMPATCHCNTL;                      /**< ROMC Control Register, offset: 0xF4 */
93349        uint32_t ROMPATCHENH;                       /**< ROMC Enable Register High, offset: 0xF8 */
93350   __IO uint32_t ROMPATCHENL;                       /**< ROMC Enable Register Low, offset: 0xFC */
93351   __IO uint32_t ROMPATCHA[16];                     /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
93352        uint8_t RESERVED_1[200];
93353   __IO uint32_t ROMPATCHSR;                        /**< ROMC Status Register, offset: 0x208 */
93354 } ROMCP_Type;
93355 
93356 /* ----------------------------------------------------------------------------
93357    -- ROMCP Register Masks
93358    ---------------------------------------------------------------------------- */
93359 
93360 /*!
93361  * @addtogroup ROMCP_Register_Masks ROMCP Register Masks
93362  * @{
93363  */
93364 
93365 /*! @name ROMPATCHD - ROMC Data Registers */
93366 /*! @{ */
93367 #define ROMCP_ROMPATCHD_DATAX_MASK               (0xFFFFFFFFU)
93368 #define ROMCP_ROMPATCHD_DATAX_SHIFT              (0U)
93369 /*! DATAX - DATAX
93370  */
93371 #define ROMCP_ROMPATCHD_DATAX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHD_DATAX_SHIFT)) & ROMCP_ROMPATCHD_DATAX_MASK)
93372 /*! @} */
93373 
93374 /* The count of ROMCP_ROMPATCHD */
93375 #define ROMCP_ROMPATCHD_COUNT                    (8U)
93376 
93377 /*! @name ROMPATCHCNTL - ROMC Control Register */
93378 /*! @{ */
93379 #define ROMCP_ROMPATCHCNTL_DATAFIX_MASK          (0xFFU)
93380 #define ROMCP_ROMPATCHCNTL_DATAFIX_SHIFT         (0U)
93381 /*! DATAFIX - DATAFIX
93382  *  0b00000000..Address comparator triggers a opcode patch
93383  *  0b00000001..Address comparator triggers a data fix
93384  */
93385 #define ROMCP_ROMPATCHCNTL_DATAFIX(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX_MASK)
93386 #define ROMCP_ROMPATCHCNTL_DIS_MASK              (0x20000000U)
93387 #define ROMCP_ROMPATCHCNTL_DIS_SHIFT             (29U)
93388 /*! DIS - DIS
93389  *  0b0..Does not affect any ROMC functions (default)
93390  *  0b1..Disable all ROMC functions: data fixing, and opcode patching
93391  */
93392 #define ROMCP_ROMPATCHCNTL_DIS(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DIS_SHIFT)) & ROMCP_ROMPATCHCNTL_DIS_MASK)
93393 /*! @} */
93394 
93395 /*! @name ROMPATCHENL - ROMC Enable Register Low */
93396 /*! @{ */
93397 #define ROMCP_ROMPATCHENL_ENABLE_MASK            (0xFFFFU)
93398 #define ROMCP_ROMPATCHENL_ENABLE_SHIFT           (0U)
93399 /*! ENABLE - ENABLE
93400  *  0b0000000000000000..Address comparator disabled
93401  *  0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address
93402  */
93403 #define ROMCP_ROMPATCHENL_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE_MASK)
93404 /*! @} */
93405 
93406 /*! @name ROMPATCHA - ROMC Address Registers */
93407 /*! @{ */
93408 #define ROMCP_ROMPATCHA_THUMBX_MASK              (0x1U)
93409 #define ROMCP_ROMPATCHA_THUMBX_SHIFT             (0U)
93410 /*! THUMBX - THUMBX
93411  *  0b0..ARM patch
93412  *  0b1..THUMB patch (ignore if data fix)
93413  */
93414 #define ROMCP_ROMPATCHA_THUMBX(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_THUMBX_SHIFT)) & ROMCP_ROMPATCHA_THUMBX_MASK)
93415 #define ROMCP_ROMPATCHA_ADDRX_MASK               (0x7FFFFEU)
93416 #define ROMCP_ROMPATCHA_ADDRX_SHIFT              (1U)
93417 /*! ADDRX - ADDRX
93418  */
93419 #define ROMCP_ROMPATCHA_ADDRX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_ADDRX_SHIFT)) & ROMCP_ROMPATCHA_ADDRX_MASK)
93420 /*! @} */
93421 
93422 /* The count of ROMCP_ROMPATCHA */
93423 #define ROMCP_ROMPATCHA_COUNT                    (16U)
93424 
93425 /*! @name ROMPATCHSR - ROMC Status Register */
93426 /*! @{ */
93427 #define ROMCP_ROMPATCHSR_SOURCE_MASK             (0x3FU)
93428 #define ROMCP_ROMPATCHSR_SOURCE_SHIFT            (0U)
93429 /*! SOURCE - SOURCE
93430  *  0b000000..Address Comparator 0 matched
93431  *  0b000001..Address Comparator 1 matched
93432  *  0b001111..Address Comparator 15 matched
93433  */
93434 #define ROMCP_ROMPATCHSR_SOURCE(x)               (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SOURCE_SHIFT)) & ROMCP_ROMPATCHSR_SOURCE_MASK)
93435 #define ROMCP_ROMPATCHSR_SW_MASK                 (0x20000U)
93436 #define ROMCP_ROMPATCHSR_SW_SHIFT                (17U)
93437 /*! SW - SW
93438  *  0b0..no event or comparator collisions
93439  *  0b1..a collision has occurred
93440  */
93441 #define ROMCP_ROMPATCHSR_SW(x)                   (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SW_SHIFT)) & ROMCP_ROMPATCHSR_SW_MASK)
93442 /*! @} */
93443 
93444 
93445 /*!
93446  * @}
93447  */ /* end of group ROMCP_Register_Masks */
93448 
93449 
93450 /* ROMCP - Peripheral instance base addresses */
93451 /** Peripheral SCU__ROMCP base address */
93452 #define SCU__ROMCP_BASE                          (0x32060000u)
93453 /** Peripheral SCU__ROMCP base pointer */
93454 #define SCU__ROMCP                               ((ROMCP_Type *)SCU__ROMCP_BASE)
93455 /** Array initializer of ROMCP peripheral base addresses */
93456 #define ROMCP_BASE_ADDRS                         { SCU__ROMCP_BASE }
93457 /** Array initializer of ROMCP peripheral base pointers */
93458 #define ROMCP_BASE_PTRS                          { SCU__ROMCP }
93459 
93460 /*!
93461  * @}
93462  */ /* end of group ROMCP_Peripheral_Access_Layer */
93463 
93464 
93465 /* ----------------------------------------------------------------------------
93466    -- SEMA42 Peripheral Access Layer
93467    ---------------------------------------------------------------------------- */
93468 
93469 /*!
93470  * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
93471  * @{
93472  */
93473 
93474 /** SEMA42 - Register Layout Typedef */
93475 typedef struct {
93476   __IO uint8_t GATE3;                              /**< Gate Register, offset: 0x0 */
93477   __IO uint8_t GATE2;                              /**< Gate Register, offset: 0x1 */
93478   __IO uint8_t GATE1;                              /**< Gate Register, offset: 0x2 */
93479   __IO uint8_t GATE0;                              /**< Gate Register, offset: 0x3 */
93480   __IO uint8_t GATE7;                              /**< Gate Register, offset: 0x4 */
93481   __IO uint8_t GATE6;                              /**< Gate Register, offset: 0x5 */
93482   __IO uint8_t GATE5;                              /**< Gate Register, offset: 0x6 */
93483   __IO uint8_t GATE4;                              /**< Gate Register, offset: 0x7 */
93484   __IO uint8_t GATE11;                             /**< Gate Register, offset: 0x8 */
93485   __IO uint8_t GATE10;                             /**< Gate Register, offset: 0x9 */
93486   __IO uint8_t GATE9;                              /**< Gate Register, offset: 0xA */
93487   __IO uint8_t GATE8;                              /**< Gate Register, offset: 0xB */
93488   __IO uint8_t GATE15;                             /**< Gate Register, offset: 0xC */
93489   __IO uint8_t GATE14;                             /**< Gate Register, offset: 0xD */
93490   __IO uint8_t GATE13;                             /**< Gate Register, offset: 0xE */
93491   __IO uint8_t GATE12;                             /**< Gate Register, offset: 0xF */
93492        uint8_t RESERVED_0[50];
93493   union {                                          /* offset: 0x42 */
93494     __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
93495     __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
93496   };
93497 } SEMA42_Type;
93498 
93499 /* ----------------------------------------------------------------------------
93500    -- SEMA42 Register Masks
93501    ---------------------------------------------------------------------------- */
93502 
93503 /*!
93504  * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
93505  * @{
93506  */
93507 
93508 /*! @name GATE3 - Gate Register */
93509 /*! @{ */
93510 #define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
93511 #define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
93512 /*! GTFSM - Gate finite state machine
93513  *  0b0000..The gate is unlocked (free).
93514  *  0b0001..Domain 0 locked the gate.
93515  *  0b0010..Domain 1 locked the gate.
93516  *  0b0011..Domain 2 locked the gate.
93517  *  0b0100..Domain 3 locked the gate.
93518  *  0b0101..Domain 4 locked the gate.
93519  *  0b0110..Domain 5 locked the gate.
93520  *  0b0111..Domain 6 locked the gate.
93521  *  0b1000..Domain 7 locked the gate.
93522  *  0b1001..Domain 8 locked the gate.
93523  *  0b1010..Domain 9 locked the gate.
93524  *  0b1011..Domain 10 locked the gate.
93525  *  0b1100..Domain 11 locked the gate.
93526  *  0b1101..Domain 12 locked the gate.
93527  *  0b1110..Domain 13 locked the gate.
93528  *  0b1111..Domain 14 locked the gate.
93529  */
93530 #define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
93531 /*! @} */
93532 
93533 /*! @name GATE2 - Gate Register */
93534 /*! @{ */
93535 #define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
93536 #define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
93537 /*! GTFSM - Gate finite state machine
93538  *  0b0000..The gate is unlocked (free).
93539  *  0b0001..Domain 0 locked the gate.
93540  *  0b0010..Domain 1 locked the gate.
93541  *  0b0011..Domain 2 locked the gate.
93542  *  0b0100..Domain 3 locked the gate.
93543  *  0b0101..Domain 4 locked the gate.
93544  *  0b0110..Domain 5 locked the gate.
93545  *  0b0111..Domain 6 locked the gate.
93546  *  0b1000..Domain 7 locked the gate.
93547  *  0b1001..Domain 8 locked the gate.
93548  *  0b1010..Domain 9 locked the gate.
93549  *  0b1011..Domain 10 locked the gate.
93550  *  0b1100..Domain 11 locked the gate.
93551  *  0b1101..Domain 12 locked the gate.
93552  *  0b1110..Domain 13 locked the gate.
93553  *  0b1111..Domain 14 locked the gate.
93554  */
93555 #define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
93556 /*! @} */
93557 
93558 /*! @name GATE1 - Gate Register */
93559 /*! @{ */
93560 #define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
93561 #define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
93562 /*! GTFSM - Gate finite state machine
93563  *  0b0000..The gate is unlocked (free).
93564  *  0b0001..Domain 0 locked the gate.
93565  *  0b0010..Domain 1 locked the gate.
93566  *  0b0011..Domain 2 locked the gate.
93567  *  0b0100..Domain 3 locked the gate.
93568  *  0b0101..Domain 4 locked the gate.
93569  *  0b0110..Domain 5 locked the gate.
93570  *  0b0111..Domain 6 locked the gate.
93571  *  0b1000..Domain 7 locked the gate.
93572  *  0b1001..Domain 8 locked the gate.
93573  *  0b1010..Domain 9 locked the gate.
93574  *  0b1011..Domain 10 locked the gate.
93575  *  0b1100..Domain 11 locked the gate.
93576  *  0b1101..Domain 12 locked the gate.
93577  *  0b1110..Domain 13 locked the gate.
93578  *  0b1111..Domain 14 locked the gate.
93579  */
93580 #define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
93581 /*! @} */
93582 
93583 /*! @name GATE0 - Gate Register */
93584 /*! @{ */
93585 #define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
93586 #define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
93587 /*! GTFSM - Gate finite state machine
93588  *  0b0000..The gate is unlocked (free).
93589  *  0b0001..Domain 0 locked the gate.
93590  *  0b0010..Domain 1 locked the gate.
93591  *  0b0011..Domain 2 locked the gate.
93592  *  0b0100..Domain 3 locked the gate.
93593  *  0b0101..Domain 4 locked the gate.
93594  *  0b0110..Domain 5 locked the gate.
93595  *  0b0111..Domain 6 locked the gate.
93596  *  0b1000..Domain 7 locked the gate.
93597  *  0b1001..Domain 8 locked the gate.
93598  *  0b1010..Domain 9 locked the gate.
93599  *  0b1011..Domain 10 locked the gate.
93600  *  0b1100..Domain 11 locked the gate.
93601  *  0b1101..Domain 12 locked the gate.
93602  *  0b1110..Domain 13 locked the gate.
93603  *  0b1111..Domain 14 locked the gate.
93604  */
93605 #define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
93606 /*! @} */
93607 
93608 /*! @name GATE7 - Gate Register */
93609 /*! @{ */
93610 #define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
93611 #define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
93612 /*! GTFSM - Gate finite state machine
93613  *  0b0000..The gate is unlocked (free).
93614  *  0b0001..Domain 0 locked the gate.
93615  *  0b0010..Domain 1 locked the gate.
93616  *  0b0011..Domain 2 locked the gate.
93617  *  0b0100..Domain 3 locked the gate.
93618  *  0b0101..Domain 4 locked the gate.
93619  *  0b0110..Domain 5 locked the gate.
93620  *  0b0111..Domain 6 locked the gate.
93621  *  0b1000..Domain 7 locked the gate.
93622  *  0b1001..Domain 8 locked the gate.
93623  *  0b1010..Domain 9 locked the gate.
93624  *  0b1011..Domain 10 locked the gate.
93625  *  0b1100..Domain 11 locked the gate.
93626  *  0b1101..Domain 12 locked the gate.
93627  *  0b1110..Domain 13 locked the gate.
93628  *  0b1111..Domain 14 locked the gate.
93629  */
93630 #define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
93631 /*! @} */
93632 
93633 /*! @name GATE6 - Gate Register */
93634 /*! @{ */
93635 #define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
93636 #define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
93637 /*! GTFSM - Gate finite state machine
93638  *  0b0000..The gate is unlocked (free).
93639  *  0b0001..Domain 0 locked the gate.
93640  *  0b0010..Domain 1 locked the gate.
93641  *  0b0011..Domain 2 locked the gate.
93642  *  0b0100..Domain 3 locked the gate.
93643  *  0b0101..Domain 4 locked the gate.
93644  *  0b0110..Domain 5 locked the gate.
93645  *  0b0111..Domain 6 locked the gate.
93646  *  0b1000..Domain 7 locked the gate.
93647  *  0b1001..Domain 8 locked the gate.
93648  *  0b1010..Domain 9 locked the gate.
93649  *  0b1011..Domain 10 locked the gate.
93650  *  0b1100..Domain 11 locked the gate.
93651  *  0b1101..Domain 12 locked the gate.
93652  *  0b1110..Domain 13 locked the gate.
93653  *  0b1111..Domain 14 locked the gate.
93654  */
93655 #define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
93656 /*! @} */
93657 
93658 /*! @name GATE5 - Gate Register */
93659 /*! @{ */
93660 #define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
93661 #define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
93662 /*! GTFSM - Gate finite state machine
93663  *  0b0000..The gate is unlocked (free).
93664  *  0b0001..Domain 0 locked the gate.
93665  *  0b0010..Domain 1 locked the gate.
93666  *  0b0011..Domain 2 locked the gate.
93667  *  0b0100..Domain 3 locked the gate.
93668  *  0b0101..Domain 4 locked the gate.
93669  *  0b0110..Domain 5 locked the gate.
93670  *  0b0111..Domain 6 locked the gate.
93671  *  0b1000..Domain 7 locked the gate.
93672  *  0b1001..Domain 8 locked the gate.
93673  *  0b1010..Domain 9 locked the gate.
93674  *  0b1011..Domain 10 locked the gate.
93675  *  0b1100..Domain 11 locked the gate.
93676  *  0b1101..Domain 12 locked the gate.
93677  *  0b1110..Domain 13 locked the gate.
93678  *  0b1111..Domain 14 locked the gate.
93679  */
93680 #define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
93681 /*! @} */
93682 
93683 /*! @name GATE4 - Gate Register */
93684 /*! @{ */
93685 #define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
93686 #define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
93687 /*! GTFSM - Gate finite state machine
93688  *  0b0000..The gate is unlocked (free).
93689  *  0b0001..Domain 0 locked the gate.
93690  *  0b0010..Domain 1 locked the gate.
93691  *  0b0011..Domain 2 locked the gate.
93692  *  0b0100..Domain 3 locked the gate.
93693  *  0b0101..Domain 4 locked the gate.
93694  *  0b0110..Domain 5 locked the gate.
93695  *  0b0111..Domain 6 locked the gate.
93696  *  0b1000..Domain 7 locked the gate.
93697  *  0b1001..Domain 8 locked the gate.
93698  *  0b1010..Domain 9 locked the gate.
93699  *  0b1011..Domain 10 locked the gate.
93700  *  0b1100..Domain 11 locked the gate.
93701  *  0b1101..Domain 12 locked the gate.
93702  *  0b1110..Domain 13 locked the gate.
93703  *  0b1111..Domain 14 locked the gate.
93704  */
93705 #define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
93706 /*! @} */
93707 
93708 /*! @name GATE11 - Gate Register */
93709 /*! @{ */
93710 #define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
93711 #define SEMA42_GATE11_GTFSM_SHIFT                (0U)
93712 /*! GTFSM - Gate finite state machine
93713  *  0b0000..The gate is unlocked (free).
93714  *  0b0001..Domain 0 locked the gate.
93715  *  0b0010..Domain 1 locked the gate.
93716  *  0b0011..Domain 2 locked the gate.
93717  *  0b0100..Domain 3 locked the gate.
93718  *  0b0101..Domain 4 locked the gate.
93719  *  0b0110..Domain 5 locked the gate.
93720  *  0b0111..Domain 6 locked the gate.
93721  *  0b1000..Domain 7 locked the gate.
93722  *  0b1001..Domain 8 locked the gate.
93723  *  0b1010..Domain 9 locked the gate.
93724  *  0b1011..Domain 10 locked the gate.
93725  *  0b1100..Domain 11 locked the gate.
93726  *  0b1101..Domain 12 locked the gate.
93727  *  0b1110..Domain 13 locked the gate.
93728  *  0b1111..Domain 14 locked the gate.
93729  */
93730 #define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
93731 /*! @} */
93732 
93733 /*! @name GATE10 - Gate Register */
93734 /*! @{ */
93735 #define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
93736 #define SEMA42_GATE10_GTFSM_SHIFT                (0U)
93737 /*! GTFSM - Gate finite state machine
93738  *  0b0000..The gate is unlocked (free).
93739  *  0b0001..Domain 0 locked the gate.
93740  *  0b0010..Domain 1 locked the gate.
93741  *  0b0011..Domain 2 locked the gate.
93742  *  0b0100..Domain 3 locked the gate.
93743  *  0b0101..Domain 4 locked the gate.
93744  *  0b0110..Domain 5 locked the gate.
93745  *  0b0111..Domain 6 locked the gate.
93746  *  0b1000..Domain 7 locked the gate.
93747  *  0b1001..Domain 8 locked the gate.
93748  *  0b1010..Domain 9 locked the gate.
93749  *  0b1011..Domain 10 locked the gate.
93750  *  0b1100..Domain 11 locked the gate.
93751  *  0b1101..Domain 12 locked the gate.
93752  *  0b1110..Domain 13 locked the gate.
93753  *  0b1111..Domain 14 locked the gate.
93754  */
93755 #define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
93756 /*! @} */
93757 
93758 /*! @name GATE9 - Gate Register */
93759 /*! @{ */
93760 #define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
93761 #define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
93762 /*! GTFSM - Gate finite state machine
93763  *  0b0000..The gate is unlocked (free).
93764  *  0b0001..Domain 0 locked the gate.
93765  *  0b0010..Domain 1 locked the gate.
93766  *  0b0011..Domain 2 locked the gate.
93767  *  0b0100..Domain 3 locked the gate.
93768  *  0b0101..Domain 4 locked the gate.
93769  *  0b0110..Domain 5 locked the gate.
93770  *  0b0111..Domain 6 locked the gate.
93771  *  0b1000..Domain 7 locked the gate.
93772  *  0b1001..Domain 8 locked the gate.
93773  *  0b1010..Domain 9 locked the gate.
93774  *  0b1011..Domain 10 locked the gate.
93775  *  0b1100..Domain 11 locked the gate.
93776  *  0b1101..Domain 12 locked the gate.
93777  *  0b1110..Domain 13 locked the gate.
93778  *  0b1111..Domain 14 locked the gate.
93779  */
93780 #define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
93781 /*! @} */
93782 
93783 /*! @name GATE8 - Gate Register */
93784 /*! @{ */
93785 #define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
93786 #define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
93787 /*! GTFSM - Gate finite state machine
93788  *  0b0000..The gate is unlocked (free).
93789  *  0b0001..Domain 0 locked the gate.
93790  *  0b0010..Domain 1 locked the gate.
93791  *  0b0011..Domain 2 locked the gate.
93792  *  0b0100..Domain 3 locked the gate.
93793  *  0b0101..Domain 4 locked the gate.
93794  *  0b0110..Domain 5 locked the gate.
93795  *  0b0111..Domain 6 locked the gate.
93796  *  0b1000..Domain 7 locked the gate.
93797  *  0b1001..Domain 8 locked the gate.
93798  *  0b1010..Domain 9 locked the gate.
93799  *  0b1011..Domain 10 locked the gate.
93800  *  0b1100..Domain 11 locked the gate.
93801  *  0b1101..Domain 12 locked the gate.
93802  *  0b1110..Domain 13 locked the gate.
93803  *  0b1111..Domain 14 locked the gate.
93804  */
93805 #define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
93806 /*! @} */
93807 
93808 /*! @name GATE15 - Gate Register */
93809 /*! @{ */
93810 #define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
93811 #define SEMA42_GATE15_GTFSM_SHIFT                (0U)
93812 /*! GTFSM - Gate finite state machine
93813  *  0b0000..The gate is unlocked (free).
93814  *  0b0001..Domain 0 locked the gate.
93815  *  0b0010..Domain 1 locked the gate.
93816  *  0b0011..Domain 2 locked the gate.
93817  *  0b0100..Domain 3 locked the gate.
93818  *  0b0101..Domain 4 locked the gate.
93819  *  0b0110..Domain 5 locked the gate.
93820  *  0b0111..Domain 6 locked the gate.
93821  *  0b1000..Domain 7 locked the gate.
93822  *  0b1001..Domain 8 locked the gate.
93823  *  0b1010..Domain 9 locked the gate.
93824  *  0b1011..Domain 10 locked the gate.
93825  *  0b1100..Domain 11 locked the gate.
93826  *  0b1101..Domain 12 locked the gate.
93827  *  0b1110..Domain 13 locked the gate.
93828  *  0b1111..Domain 14 locked the gate.
93829  */
93830 #define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
93831 /*! @} */
93832 
93833 /*! @name GATE14 - Gate Register */
93834 /*! @{ */
93835 #define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
93836 #define SEMA42_GATE14_GTFSM_SHIFT                (0U)
93837 /*! GTFSM - Gate finite state machine
93838  *  0b0000..The gate is unlocked (free).
93839  *  0b0001..Domain 0 locked the gate.
93840  *  0b0010..Domain 1 locked the gate.
93841  *  0b0011..Domain 2 locked the gate.
93842  *  0b0100..Domain 3 locked the gate.
93843  *  0b0101..Domain 4 locked the gate.
93844  *  0b0110..Domain 5 locked the gate.
93845  *  0b0111..Domain 6 locked the gate.
93846  *  0b1000..Domain 7 locked the gate.
93847  *  0b1001..Domain 8 locked the gate.
93848  *  0b1010..Domain 9 locked the gate.
93849  *  0b1011..Domain 10 locked the gate.
93850  *  0b1100..Domain 11 locked the gate.
93851  *  0b1101..Domain 12 locked the gate.
93852  *  0b1110..Domain 13 locked the gate.
93853  *  0b1111..Domain 14 locked the gate.
93854  */
93855 #define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
93856 /*! @} */
93857 
93858 /*! @name GATE13 - Gate Register */
93859 /*! @{ */
93860 #define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
93861 #define SEMA42_GATE13_GTFSM_SHIFT                (0U)
93862 /*! GTFSM - Gate finite state machine
93863  *  0b0000..The gate is unlocked (free).
93864  *  0b0001..Domain 0 locked the gate.
93865  *  0b0010..Domain 1 locked the gate.
93866  *  0b0011..Domain 2 locked the gate.
93867  *  0b0100..Domain 3 locked the gate.
93868  *  0b0101..Domain 4 locked the gate.
93869  *  0b0110..Domain 5 locked the gate.
93870  *  0b0111..Domain 6 locked the gate.
93871  *  0b1000..Domain 7 locked the gate.
93872  *  0b1001..Domain 8 locked the gate.
93873  *  0b1010..Domain 9 locked the gate.
93874  *  0b1011..Domain 10 locked the gate.
93875  *  0b1100..Domain 11 locked the gate.
93876  *  0b1101..Domain 12 locked the gate.
93877  *  0b1110..Domain 13 locked the gate.
93878  *  0b1111..Domain 14 locked the gate.
93879  */
93880 #define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
93881 /*! @} */
93882 
93883 /*! @name GATE12 - Gate Register */
93884 /*! @{ */
93885 #define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
93886 #define SEMA42_GATE12_GTFSM_SHIFT                (0U)
93887 /*! GTFSM - Gate finite state machine
93888  *  0b0000..The gate is unlocked (free).
93889  *  0b0001..Domain 0 locked the gate.
93890  *  0b0010..Domain 1 locked the gate.
93891  *  0b0011..Domain 2 locked the gate.
93892  *  0b0100..Domain 3 locked the gate.
93893  *  0b0101..Domain 4 locked the gate.
93894  *  0b0110..Domain 5 locked the gate.
93895  *  0b0111..Domain 6 locked the gate.
93896  *  0b1000..Domain 7 locked the gate.
93897  *  0b1001..Domain 8 locked the gate.
93898  *  0b1010..Domain 9 locked the gate.
93899  *  0b1011..Domain 10 locked the gate.
93900  *  0b1100..Domain 11 locked the gate.
93901  *  0b1101..Domain 12 locked the gate.
93902  *  0b1110..Domain 13 locked the gate.
93903  *  0b1111..Domain 14 locked the gate.
93904  */
93905 #define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
93906 /*! @} */
93907 
93908 /*! @name RSTGT_R - Reset Gate Read */
93909 /*! @{ */
93910 #define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
93911 #define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
93912 /*! RSTGTN - Reset gate number
93913  */
93914 #define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)
93915 #define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
93916 #define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
93917 /*! RSTGMS - Reset gate domain
93918  */
93919 #define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
93920 #define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
93921 #define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
93922 /*! RSTGSM - Reset gate finite state machine
93923  *  0b00..Idle, waiting for the first data pattern write.
93924  *  0b01..Waiting for the second data pattern write
93925  *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
93926  *        this machine returns to the idle (waiting for first data pattern write) state.
93927  *  0b11..This state encoding is never used and therefore reserved.
93928  */
93929 #define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
93930 #define SEMA42_RSTGT_R_ROZ_MASK                  (0xC000U)
93931 #define SEMA42_RSTGT_R_ROZ_SHIFT                 (14U)
93932 /*! ROZ - ROZ
93933  */
93934 #define SEMA42_RSTGT_R_ROZ(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK)
93935 /*! @} */
93936 
93937 /*! @name RSTGT_W - Reset Gate Write */
93938 /*! @{ */
93939 #define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
93940 #define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
93941 /*! RSTGTN - Reset gate number
93942  */
93943 #define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)
93944 #define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
93945 #define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
93946 /*! RSTGDP - Reset gate data pattern
93947  */
93948 #define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
93949 /*! @} */
93950 
93951 
93952 /*!
93953  * @}
93954  */ /* end of group SEMA42_Register_Masks */
93955 
93956 
93957 /* SEMA42 - Peripheral instance base addresses */
93958 /** Peripheral CM4__SEMA42 base address */
93959 #define CM4__SEMA42_BASE                         (0x411B0000u)
93960 /** Peripheral CM4__SEMA42 base pointer */
93961 #define CM4__SEMA42                              ((SEMA42_Type *)CM4__SEMA42_BASE)
93962 /** Peripheral SCU__SEMA42 base address */
93963 #define SCU__SEMA42_BASE                         (0x331B0000u)
93964 /** Peripheral SCU__SEMA42 base pointer */
93965 #define SCU__SEMA42                              ((SEMA42_Type *)SCU__SEMA42_BASE)
93966 /** Array initializer of SEMA42 peripheral base addresses */
93967 #define SEMA42_BASE_ADDRS                        { CM4__SEMA42_BASE, SCU__SEMA42_BASE }
93968 /** Array initializer of SEMA42 peripheral base pointers */
93969 #define SEMA42_BASE_PTRS                         { CM4__SEMA42, SCU__SEMA42 }
93970 
93971 /*!
93972  * @}
93973  */ /* end of group SEMA42_Peripheral_Access_Layer */
93974 
93975 
93976 /* ----------------------------------------------------------------------------
93977    -- SPDIF Peripheral Access Layer
93978    ---------------------------------------------------------------------------- */
93979 
93980 /*!
93981  * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
93982  * @{
93983  */
93984 
93985 /** SPDIF - Register Layout Typedef */
93986 typedef struct {
93987   __IO uint32_t SCR;                               /**< SPDIF Configuration Register, offset: 0x0 */
93988   __IO uint32_t SRCD;                              /**< CDText Control Register, offset: 0x4 */
93989   __IO uint32_t SRPC;                              /**< PhaseConfig Register, offset: 0x8 */
93990   __IO uint32_t SIE;                               /**< InterruptEn Register, offset: 0xC */
93991   union {                                          /* offset: 0x10 */
93992     __O  uint32_t SIC;                               /**< InterruptClear Register, offset: 0x10 */
93993     __I  uint32_t SIS;                               /**< InterruptStat Register, offset: 0x10 */
93994   };
93995   __I  uint32_t SRL;                               /**< SPDIFRxLeft Register, offset: 0x14 */
93996   __I  uint32_t SRR;                               /**< SPDIFRxRight Register, offset: 0x18 */
93997   __I  uint32_t SRCSH;                             /**< SPDIFRxCChannel_h Register, offset: 0x1C */
93998   __I  uint32_t SRCSL;                             /**< SPDIFRxCChannel_l Register, offset: 0x20 */
93999   __I  uint32_t SRU;                               /**< UchannelRx Register, offset: 0x24 */
94000   __I  uint32_t SRQ;                               /**< QchannelRx Register, offset: 0x28 */
94001   __O  uint32_t STL;                               /**< SPDIFTxLeft Register, offset: 0x2C */
94002   __O  uint32_t STR;                               /**< SPDIFTxRight Register, offset: 0x30 */
94003   __IO uint32_t STCSCH;                            /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
94004   __IO uint32_t STCSCL;                            /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
94005        uint8_t RESERVED_0[8];
94006   __I  uint32_t SRFM;                              /**< FreqMeas Register, offset: 0x44 */
94007        uint8_t RESERVED_1[8];
94008   __IO uint32_t STC;                               /**< SPDIFTxClk Register, offset: 0x50 */
94009 } SPDIF_Type;
94010 
94011 /* ----------------------------------------------------------------------------
94012    -- SPDIF Register Masks
94013    ---------------------------------------------------------------------------- */
94014 
94015 /*!
94016  * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
94017  * @{
94018  */
94019 
94020 /*! @name SCR - SPDIF Configuration Register */
94021 /*! @{ */
94022 #define SPDIF_SCR_USRC_SEL_MASK                  (0x3U)
94023 #define SPDIF_SCR_USRC_SEL_SHIFT                 (0U)
94024 /*! USrc_Sel - USrc_Sel
94025  *  0b00..No embedded U channel
94026  *  0b01..U channel from SPDIF receive block (CD mode)
94027  *  0b10..Reserved
94028  *  0b11..U channel from on chip transmitter
94029  */
94030 #define SPDIF_SCR_USRC_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
94031 #define SPDIF_SCR_TXSEL_MASK                     (0x1CU)
94032 #define SPDIF_SCR_TXSEL_SHIFT                    (2U)
94033 /*! TxSel - TxSel
94034  *  0b000..Off and output 0
94035  *  0b001..Feed-through SPDIFIN
94036  *  0b101..Tx Normal operation
94037  */
94038 #define SPDIF_SCR_TXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
94039 #define SPDIF_SCR_VALCTRL_MASK                   (0x20U)
94040 #define SPDIF_SCR_VALCTRL_SHIFT                  (5U)
94041 /*! ValCtrl - ValCtrl
94042  *  0b0..Outgoing Validity always set
94043  *  0b1..Outgoing Validity always clear
94044  */
94045 #define SPDIF_SCR_VALCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
94046 #define SPDIF_SCR_DMA_TX_EN_MASK                 (0x100U)
94047 #define SPDIF_SCR_DMA_TX_EN_SHIFT                (8U)
94048 /*! DMA_TX_En - DMA_TX_En
94049  */
94050 #define SPDIF_SCR_DMA_TX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
94051 #define SPDIF_SCR_DMA_RX_EN_MASK                 (0x200U)
94052 #define SPDIF_SCR_DMA_RX_EN_SHIFT                (9U)
94053 /*! DMA_Rx_En - DMA_Rx_En
94054  */
94055 #define SPDIF_SCR_DMA_RX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
94056 #define SPDIF_SCR_TXFIFO_CTRL_MASK               (0xC00U)
94057 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT              (10U)
94058 /*! TxFIFO_Ctrl - TxFIFO_Ctrl
94059  *  0b00..Send out digital zero on SPDIF Tx
94060  *  0b01..Tx Normal operation
94061  *  0b10..Reset to 1 sample remaining
94062  *  0b11..Reserved
94063  */
94064 #define SPDIF_SCR_TXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
94065 #define SPDIF_SCR_SOFT_RESET_MASK                (0x1000U)
94066 #define SPDIF_SCR_SOFT_RESET_SHIFT               (12U)
94067 /*! soft_reset - soft_reset
94068  */
94069 #define SPDIF_SCR_SOFT_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
94070 #define SPDIF_SCR_LOW_POWER_MASK                 (0x2000U)
94071 #define SPDIF_SCR_LOW_POWER_SHIFT                (13U)
94072 /*! LOW_POWER - LOW_POWER
94073  */
94074 #define SPDIF_SCR_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
94075 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK           (0x18000U)
94076 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT          (15U)
94077 /*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel
94078  *  0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
94079  *  0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
94080  *  0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
94081  *  0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
94082  */
94083 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
94084 #define SPDIF_SCR_TXAUTOSYNC_MASK                (0x20000U)
94085 #define SPDIF_SCR_TXAUTOSYNC_SHIFT               (17U)
94086 /*! TxAutoSync - TxAutoSync
94087  *  0b0..Tx FIFO auto sync off
94088  *  0b1..Tx FIFO auto sync on
94089  */
94090 #define SPDIF_SCR_TXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
94091 #define SPDIF_SCR_RXAUTOSYNC_MASK                (0x40000U)
94092 #define SPDIF_SCR_RXAUTOSYNC_SHIFT               (18U)
94093 /*! RxAutoSync - RxAutoSync
94094  *  0b0..Rx FIFO auto sync off
94095  *  0b1..RxFIFO auto sync on
94096  */
94097 #define SPDIF_SCR_RXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
94098 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK            (0x180000U)
94099 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT           (19U)
94100 /*! RxFIFOFull_Sel - RxFIFOFull_Sel
94101  *  0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
94102  *  0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
94103  *  0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
94104  *  0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
94105  */
94106 #define SPDIF_SCR_RXFIFOFULL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
94107 #define SPDIF_SCR_RXFIFO_RST_MASK                (0x200000U)
94108 #define SPDIF_SCR_RXFIFO_RST_SHIFT               (21U)
94109 /*! RxFIFO_Rst - RxFIFO_Rst
94110  *  0b0..Normal operation
94111  *  0b1..Reset register to 1 sample remaining
94112  */
94113 #define SPDIF_SCR_RXFIFO_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
94114 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK             (0x400000U)
94115 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT            (22U)
94116 /*! RxFIFO_Off_On - RxFIFO_Off_On
94117  *  0b0..SPDIF Rx FIFO is on
94118  *  0b1..SPDIF Rx FIFO is off. Does not accept data from interface
94119  */
94120 #define SPDIF_SCR_RXFIFO_OFF_ON(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
94121 #define SPDIF_SCR_RXFIFO_CTRL_MASK               (0x800000U)
94122 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT              (23U)
94123 /*! RxFIFO_Ctrl - RxFIFO_Ctrl
94124  *  0b0..Normal operation
94125  *  0b1..Always read zero from Rx data register
94126  */
94127 #define SPDIF_SCR_RXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
94128 /*! @} */
94129 
94130 /*! @name SRCD - CDText Control Register */
94131 /*! @{ */
94132 #define SPDIF_SRCD_USYNCMODE_MASK                (0x2U)
94133 #define SPDIF_SRCD_USYNCMODE_SHIFT               (1U)
94134 /*! USyncMode - USyncMode
94135  *  0b0..Non-CD data
94136  *  0b1..CD user channel subcode
94137  */
94138 #define SPDIF_SRCD_USYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
94139 /*! @} */
94140 
94141 /*! @name SRPC - PhaseConfig Register */
94142 /*! @{ */
94143 #define SPDIF_SRPC_GAINSEL_MASK                  (0x38U)
94144 #define SPDIF_SRPC_GAINSEL_SHIFT                 (3U)
94145 /*! GainSel - GainSel
94146  *  0b000..24*(2**10)
94147  *  0b001..16*(2**10)
94148  *  0b010..12*(2**10)
94149  *  0b011..8*(2**10)
94150  *  0b100..6*(2**10)
94151  *  0b101..4*(2**10)
94152  *  0b110..3*(2**10)
94153  */
94154 #define SPDIF_SRPC_GAINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
94155 #define SPDIF_SRPC_LOCK_MASK                     (0x40U)
94156 #define SPDIF_SRPC_LOCK_SHIFT                    (6U)
94157 /*! LOCK - LOCK
94158  */
94159 #define SPDIF_SRPC_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
94160 #define SPDIF_SRPC_CLKSRC_SEL_MASK               (0x780U)
94161 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT              (7U)
94162 /*! ClkSrc_Sel - ClkSrc_Sel
94163  *  0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
94164  *  0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
94165  *  0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
94166  *  0b0101..REF_CLK_32K (XTALOSC)
94167  *  0b0110..tx_clk (SPDIF0_CLK_ROOT)
94168  *  0b1000..SPDIF_EXT_CLK
94169  */
94170 #define SPDIF_SRPC_CLKSRC_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
94171 /*! @} */
94172 
94173 /*! @name SIE - InterruptEn Register */
94174 /*! @{ */
94175 #define SPDIF_SIE_RXFIFOFUL_MASK                 (0x1U)
94176 #define SPDIF_SIE_RXFIFOFUL_SHIFT                (0U)
94177 /*! RxFIFOFul - RxFIFOFul
94178  */
94179 #define SPDIF_SIE_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
94180 #define SPDIF_SIE_TXEM_MASK                      (0x2U)
94181 #define SPDIF_SIE_TXEM_SHIFT                     (1U)
94182 /*! TxEm - TxEm
94183  */
94184 #define SPDIF_SIE_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
94185 #define SPDIF_SIE_LOCKLOSS_MASK                  (0x4U)
94186 #define SPDIF_SIE_LOCKLOSS_SHIFT                 (2U)
94187 /*! LockLoss - LockLoss
94188  */
94189 #define SPDIF_SIE_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
94190 #define SPDIF_SIE_RXFIFORESYN_MASK               (0x8U)
94191 #define SPDIF_SIE_RXFIFORESYN_SHIFT              (3U)
94192 /*! RxFIFOResyn - RxFIFOResyn
94193  */
94194 #define SPDIF_SIE_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
94195 #define SPDIF_SIE_RXFIFOUNOV_MASK                (0x10U)
94196 #define SPDIF_SIE_RXFIFOUNOV_SHIFT               (4U)
94197 /*! RxFIFOUnOv - RxFIFOUnOv
94198  */
94199 #define SPDIF_SIE_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
94200 #define SPDIF_SIE_UQERR_MASK                     (0x20U)
94201 #define SPDIF_SIE_UQERR_SHIFT                    (5U)
94202 /*! UQErr - UQErr
94203  */
94204 #define SPDIF_SIE_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
94205 #define SPDIF_SIE_UQSYNC_MASK                    (0x40U)
94206 #define SPDIF_SIE_UQSYNC_SHIFT                   (6U)
94207 /*! UQSync - UQSync
94208  */
94209 #define SPDIF_SIE_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
94210 #define SPDIF_SIE_QRXOV_MASK                     (0x80U)
94211 #define SPDIF_SIE_QRXOV_SHIFT                    (7U)
94212 /*! QRxOv - QRxOv
94213  */
94214 #define SPDIF_SIE_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
94215 #define SPDIF_SIE_QRXFUL_MASK                    (0x100U)
94216 #define SPDIF_SIE_QRXFUL_SHIFT                   (8U)
94217 /*! QRxFul - QRxFul
94218  */
94219 #define SPDIF_SIE_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
94220 #define SPDIF_SIE_URXOV_MASK                     (0x200U)
94221 #define SPDIF_SIE_URXOV_SHIFT                    (9U)
94222 /*! URxOv - URxOv
94223  */
94224 #define SPDIF_SIE_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
94225 #define SPDIF_SIE_URXFUL_MASK                    (0x400U)
94226 #define SPDIF_SIE_URXFUL_SHIFT                   (10U)
94227 /*! URxFul - URxFul
94228  */
94229 #define SPDIF_SIE_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
94230 #define SPDIF_SIE_BITERR_MASK                    (0x4000U)
94231 #define SPDIF_SIE_BITERR_SHIFT                   (14U)
94232 /*! BitErr - BitErr
94233  */
94234 #define SPDIF_SIE_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
94235 #define SPDIF_SIE_SYMERR_MASK                    (0x8000U)
94236 #define SPDIF_SIE_SYMERR_SHIFT                   (15U)
94237 /*! SymErr - SymErr
94238  */
94239 #define SPDIF_SIE_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
94240 #define SPDIF_SIE_VALNOGOOD_MASK                 (0x10000U)
94241 #define SPDIF_SIE_VALNOGOOD_SHIFT                (16U)
94242 /*! ValNoGood - ValNoGood
94243  */
94244 #define SPDIF_SIE_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
94245 #define SPDIF_SIE_CNEW_MASK                      (0x20000U)
94246 #define SPDIF_SIE_CNEW_SHIFT                     (17U)
94247 /*! CNew - CNew
94248  */
94249 #define SPDIF_SIE_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
94250 #define SPDIF_SIE_TXRESYN_MASK                   (0x40000U)
94251 #define SPDIF_SIE_TXRESYN_SHIFT                  (18U)
94252 /*! TxResyn - TxResyn
94253  */
94254 #define SPDIF_SIE_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
94255 #define SPDIF_SIE_TXUNOV_MASK                    (0x80000U)
94256 #define SPDIF_SIE_TXUNOV_SHIFT                   (19U)
94257 /*! TxUnOv - TxUnOv
94258  */
94259 #define SPDIF_SIE_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
94260 #define SPDIF_SIE_LOCK_MASK                      (0x100000U)
94261 #define SPDIF_SIE_LOCK_SHIFT                     (20U)
94262 /*! Lock - Lock
94263  */
94264 #define SPDIF_SIE_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
94265 /*! @} */
94266 
94267 /*! @name SIC - InterruptClear Register */
94268 /*! @{ */
94269 #define SPDIF_SIC_LOCKLOSS_MASK                  (0x4U)
94270 #define SPDIF_SIC_LOCKLOSS_SHIFT                 (2U)
94271 /*! LockLoss - LockLoss
94272  */
94273 #define SPDIF_SIC_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
94274 #define SPDIF_SIC_RXFIFORESYN_MASK               (0x8U)
94275 #define SPDIF_SIC_RXFIFORESYN_SHIFT              (3U)
94276 /*! RxFIFOResyn - RxFIFOResyn
94277  */
94278 #define SPDIF_SIC_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
94279 #define SPDIF_SIC_RXFIFOUNOV_MASK                (0x10U)
94280 #define SPDIF_SIC_RXFIFOUNOV_SHIFT               (4U)
94281 /*! RxFIFOUnOv - RxFIFOUnOv
94282  */
94283 #define SPDIF_SIC_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
94284 #define SPDIF_SIC_UQERR_MASK                     (0x20U)
94285 #define SPDIF_SIC_UQERR_SHIFT                    (5U)
94286 /*! UQErr - UQErr
94287  */
94288 #define SPDIF_SIC_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
94289 #define SPDIF_SIC_UQSYNC_MASK                    (0x40U)
94290 #define SPDIF_SIC_UQSYNC_SHIFT                   (6U)
94291 /*! UQSync - UQSync
94292  */
94293 #define SPDIF_SIC_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
94294 #define SPDIF_SIC_QRXOV_MASK                     (0x80U)
94295 #define SPDIF_SIC_QRXOV_SHIFT                    (7U)
94296 /*! QRxOv - QRxOv
94297  */
94298 #define SPDIF_SIC_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
94299 #define SPDIF_SIC_URXOV_MASK                     (0x200U)
94300 #define SPDIF_SIC_URXOV_SHIFT                    (9U)
94301 /*! URxOv - URxOv
94302  */
94303 #define SPDIF_SIC_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
94304 #define SPDIF_SIC_BITERR_MASK                    (0x4000U)
94305 #define SPDIF_SIC_BITERR_SHIFT                   (14U)
94306 /*! BitErr - BitErr
94307  */
94308 #define SPDIF_SIC_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
94309 #define SPDIF_SIC_SYMERR_MASK                    (0x8000U)
94310 #define SPDIF_SIC_SYMERR_SHIFT                   (15U)
94311 /*! SymErr - SymErr
94312  */
94313 #define SPDIF_SIC_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
94314 #define SPDIF_SIC_VALNOGOOD_MASK                 (0x10000U)
94315 #define SPDIF_SIC_VALNOGOOD_SHIFT                (16U)
94316 /*! ValNoGood - ValNoGood
94317  */
94318 #define SPDIF_SIC_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
94319 #define SPDIF_SIC_CNEW_MASK                      (0x20000U)
94320 #define SPDIF_SIC_CNEW_SHIFT                     (17U)
94321 /*! CNew - CNew
94322  */
94323 #define SPDIF_SIC_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
94324 #define SPDIF_SIC_TXRESYN_MASK                   (0x40000U)
94325 #define SPDIF_SIC_TXRESYN_SHIFT                  (18U)
94326 /*! TxResyn - TxResyn
94327  */
94328 #define SPDIF_SIC_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
94329 #define SPDIF_SIC_TXUNOV_MASK                    (0x80000U)
94330 #define SPDIF_SIC_TXUNOV_SHIFT                   (19U)
94331 /*! TxUnOv - TxUnOv
94332  */
94333 #define SPDIF_SIC_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
94334 #define SPDIF_SIC_LOCK_MASK                      (0x100000U)
94335 #define SPDIF_SIC_LOCK_SHIFT                     (20U)
94336 /*! Lock - Lock
94337  */
94338 #define SPDIF_SIC_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
94339 /*! @} */
94340 
94341 /*! @name SIS - InterruptStat Register */
94342 /*! @{ */
94343 #define SPDIF_SIS_RXFIFOFUL_MASK                 (0x1U)
94344 #define SPDIF_SIS_RXFIFOFUL_SHIFT                (0U)
94345 /*! RxFIFOFul - RxFIFOFul
94346  */
94347 #define SPDIF_SIS_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
94348 #define SPDIF_SIS_TXEM_MASK                      (0x2U)
94349 #define SPDIF_SIS_TXEM_SHIFT                     (1U)
94350 /*! TxEm - TxEm
94351  */
94352 #define SPDIF_SIS_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
94353 #define SPDIF_SIS_LOCKLOSS_MASK                  (0x4U)
94354 #define SPDIF_SIS_LOCKLOSS_SHIFT                 (2U)
94355 /*! LockLoss - LockLoss
94356  */
94357 #define SPDIF_SIS_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
94358 #define SPDIF_SIS_RXFIFORESYN_MASK               (0x8U)
94359 #define SPDIF_SIS_RXFIFORESYN_SHIFT              (3U)
94360 /*! RxFIFOResyn - RxFIFOResyn
94361  */
94362 #define SPDIF_SIS_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
94363 #define SPDIF_SIS_RXFIFOUNOV_MASK                (0x10U)
94364 #define SPDIF_SIS_RXFIFOUNOV_SHIFT               (4U)
94365 /*! RxFIFOUnOv - RxFIFOUnOv
94366  */
94367 #define SPDIF_SIS_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
94368 #define SPDIF_SIS_UQERR_MASK                     (0x20U)
94369 #define SPDIF_SIS_UQERR_SHIFT                    (5U)
94370 /*! UQErr - UQErr
94371  */
94372 #define SPDIF_SIS_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
94373 #define SPDIF_SIS_UQSYNC_MASK                    (0x40U)
94374 #define SPDIF_SIS_UQSYNC_SHIFT                   (6U)
94375 /*! UQSync - UQSync
94376  */
94377 #define SPDIF_SIS_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
94378 #define SPDIF_SIS_QRXOV_MASK                     (0x80U)
94379 #define SPDIF_SIS_QRXOV_SHIFT                    (7U)
94380 /*! QRxOv - QRxOv
94381  */
94382 #define SPDIF_SIS_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
94383 #define SPDIF_SIS_QRXFUL_MASK                    (0x100U)
94384 #define SPDIF_SIS_QRXFUL_SHIFT                   (8U)
94385 /*! QRxFul - QRxFul
94386  */
94387 #define SPDIF_SIS_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
94388 #define SPDIF_SIS_URXOV_MASK                     (0x200U)
94389 #define SPDIF_SIS_URXOV_SHIFT                    (9U)
94390 /*! URxOv - URxOv
94391  */
94392 #define SPDIF_SIS_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
94393 #define SPDIF_SIS_URXFUL_MASK                    (0x400U)
94394 #define SPDIF_SIS_URXFUL_SHIFT                   (10U)
94395 /*! URxFul - URxFul
94396  */
94397 #define SPDIF_SIS_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
94398 #define SPDIF_SIS_BITERR_MASK                    (0x4000U)
94399 #define SPDIF_SIS_BITERR_SHIFT                   (14U)
94400 /*! BitErr - BitErr
94401  */
94402 #define SPDIF_SIS_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
94403 #define SPDIF_SIS_SYMERR_MASK                    (0x8000U)
94404 #define SPDIF_SIS_SYMERR_SHIFT                   (15U)
94405 /*! SymErr - SymErr
94406  */
94407 #define SPDIF_SIS_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
94408 #define SPDIF_SIS_VALNOGOOD_MASK                 (0x10000U)
94409 #define SPDIF_SIS_VALNOGOOD_SHIFT                (16U)
94410 /*! ValNoGood - ValNoGood
94411  */
94412 #define SPDIF_SIS_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
94413 #define SPDIF_SIS_CNEW_MASK                      (0x20000U)
94414 #define SPDIF_SIS_CNEW_SHIFT                     (17U)
94415 /*! CNew - CNew
94416  */
94417 #define SPDIF_SIS_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
94418 #define SPDIF_SIS_TXRESYN_MASK                   (0x40000U)
94419 #define SPDIF_SIS_TXRESYN_SHIFT                  (18U)
94420 /*! TxResyn - TxResyn
94421  */
94422 #define SPDIF_SIS_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
94423 #define SPDIF_SIS_TXUNOV_MASK                    (0x80000U)
94424 #define SPDIF_SIS_TXUNOV_SHIFT                   (19U)
94425 /*! TxUnOv - TxUnOv
94426  */
94427 #define SPDIF_SIS_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
94428 #define SPDIF_SIS_LOCK_MASK                      (0x100000U)
94429 #define SPDIF_SIS_LOCK_SHIFT                     (20U)
94430 /*! Lock - Lock
94431  */
94432 #define SPDIF_SIS_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
94433 /*! @} */
94434 
94435 /*! @name SRL - SPDIFRxLeft Register */
94436 /*! @{ */
94437 #define SPDIF_SRL_RXDATALEFT_MASK                (0xFFFFFFU)
94438 #define SPDIF_SRL_RXDATALEFT_SHIFT               (0U)
94439 /*! RxDataLeft - RxDataLeft
94440  */
94441 #define SPDIF_SRL_RXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
94442 /*! @} */
94443 
94444 /*! @name SRR - SPDIFRxRight Register */
94445 /*! @{ */
94446 #define SPDIF_SRR_RXDATARIGHT_MASK               (0xFFFFFFU)
94447 #define SPDIF_SRR_RXDATARIGHT_SHIFT              (0U)
94448 /*! RxDataRight - RxDataRight
94449  */
94450 #define SPDIF_SRR_RXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
94451 /*! @} */
94452 
94453 /*! @name SRCSH - SPDIFRxCChannel_h Register */
94454 /*! @{ */
94455 #define SPDIF_SRCSH_RXCCHANNEL_H_MASK            (0xFFFFFFU)
94456 #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT           (0U)
94457 /*! RxCChannel_h - RxCChannel_h
94458  */
94459 #define SPDIF_SRCSH_RXCCHANNEL_H(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
94460 /*! @} */
94461 
94462 /*! @name SRCSL - SPDIFRxCChannel_l Register */
94463 /*! @{ */
94464 #define SPDIF_SRCSL_RXCCHANNEL_L_MASK            (0xFFFFFFU)
94465 #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT           (0U)
94466 /*! RxCChannel_l - RxCChannel_l
94467  */
94468 #define SPDIF_SRCSL_RXCCHANNEL_L(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
94469 /*! @} */
94470 
94471 /*! @name SRU - UchannelRx Register */
94472 /*! @{ */
94473 #define SPDIF_SRU_RXUCHANNEL_MASK                (0xFFFFFFU)
94474 #define SPDIF_SRU_RXUCHANNEL_SHIFT               (0U)
94475 /*! RxUChannel - RxUChannel
94476  */
94477 #define SPDIF_SRU_RXUCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
94478 /*! @} */
94479 
94480 /*! @name SRQ - QchannelRx Register */
94481 /*! @{ */
94482 #define SPDIF_SRQ_RXQCHANNEL_MASK                (0xFFFFFFU)
94483 #define SPDIF_SRQ_RXQCHANNEL_SHIFT               (0U)
94484 /*! RxQChannel - RxQChannel
94485  */
94486 #define SPDIF_SRQ_RXQCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
94487 /*! @} */
94488 
94489 /*! @name STL - SPDIFTxLeft Register */
94490 /*! @{ */
94491 #define SPDIF_STL_TXDATALEFT_MASK                (0xFFFFFFU)
94492 #define SPDIF_STL_TXDATALEFT_SHIFT               (0U)
94493 /*! TxDataLeft - TxDataLeft
94494  */
94495 #define SPDIF_STL_TXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
94496 /*! @} */
94497 
94498 /*! @name STR - SPDIFTxRight Register */
94499 /*! @{ */
94500 #define SPDIF_STR_TXDATARIGHT_MASK               (0xFFFFFFU)
94501 #define SPDIF_STR_TXDATARIGHT_SHIFT              (0U)
94502 /*! TxDataRight - TxDataRight
94503  */
94504 #define SPDIF_STR_TXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
94505 /*! @} */
94506 
94507 /*! @name STCSCH - SPDIFTxCChannelCons_h Register */
94508 /*! @{ */
94509 #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK       (0xFFFFFFU)
94510 #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT      (0U)
94511 /*! TxCChannelCons_h - TxCChannelCons_h
94512  */
94513 #define SPDIF_STCSCH_TXCCHANNELCONS_H(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
94514 /*! @} */
94515 
94516 /*! @name STCSCL - SPDIFTxCChannelCons_l Register */
94517 /*! @{ */
94518 #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK       (0xFFFFFFU)
94519 #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT      (0U)
94520 /*! TxCChannelCons_l - TxCChannelCons_l
94521  */
94522 #define SPDIF_STCSCL_TXCCHANNELCONS_L(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
94523 /*! @} */
94524 
94525 /*! @name SRFM - FreqMeas Register */
94526 /*! @{ */
94527 #define SPDIF_SRFM_FREQMEAS_MASK                 (0xFFFFFFU)
94528 #define SPDIF_SRFM_FREQMEAS_SHIFT                (0U)
94529 /*! FreqMeas - FreqMeas
94530  */
94531 #define SPDIF_SRFM_FREQMEAS(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
94532 /*! @} */
94533 
94534 /*! @name STC - SPDIFTxClk Register */
94535 /*! @{ */
94536 #define SPDIF_STC_TXCLK_DF_MASK                  (0x7FU)
94537 #define SPDIF_STC_TXCLK_DF_SHIFT                 (0U)
94538 /*! TxClk_DF - TxClk_DF
94539  *  0b0000000..divider factor is 1
94540  *  0b0000001..divider factor is 2
94541  *  0b1111111..divider factor is 128
94542  */
94543 #define SPDIF_STC_TXCLK_DF(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
94544 #define SPDIF_STC_TX_ALL_CLK_EN_MASK             (0x80U)
94545 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT            (7U)
94546 /*! tx_all_clk_en - tx_all_clk_en
94547  *  0b0..disable transfer clock.
94548  *  0b1..enable transfer clock.
94549  */
94550 #define SPDIF_STC_TX_ALL_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
94551 #define SPDIF_STC_TXCLK_SOURCE_MASK              (0x700U)
94552 #define SPDIF_STC_TXCLK_SOURCE_SHIFT             (8U)
94553 /*! TxClk_Source - TxClk_Source
94554  *  0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
94555  *  0b001..tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.)
94556  *  0b011..SPDIF_EXT_CLK, from pads
94557  *  0b101..ipg_clk input (frequency divided)
94558  */
94559 #define SPDIF_STC_TXCLK_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
94560 #define SPDIF_STC_SYSCLK_DF_MASK                 (0xFF800U)
94561 #define SPDIF_STC_SYSCLK_DF_SHIFT                (11U)
94562 /*! SYSCLK_DF - SYSCLK_DF
94563  *  0b000000000..no clock signal
94564  *  0b000000001..divider factor is 2
94565  *  0b111111111..divider factor is 512
94566  */
94567 #define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
94568 /*! @} */
94569 
94570 
94571 /*!
94572  * @}
94573  */ /* end of group SPDIF_Register_Masks */
94574 
94575 
94576 /* SPDIF - Peripheral instance base addresses */
94577 /** Peripheral ADMA__SPDIF0 base address */
94578 #define ADMA__SPDIF0_BASE                        (0x59020000u)
94579 /** Peripheral ADMA__SPDIF0 base pointer */
94580 #define ADMA__SPDIF0                             ((SPDIF_Type *)ADMA__SPDIF0_BASE)
94581 /** Array initializer of SPDIF peripheral base addresses */
94582 #define SPDIF_BASE_ADDRS                         { ADMA__SPDIF0_BASE }
94583 /** Array initializer of SPDIF peripheral base pointers */
94584 #define SPDIF_BASE_PTRS                          { ADMA__SPDIF0 }
94585 
94586 /*!
94587  * @}
94588  */ /* end of group SPDIF_Peripheral_Access_Layer */
94589 
94590 
94591 /* ----------------------------------------------------------------------------
94592    -- TPM Peripheral Access Layer
94593    ---------------------------------------------------------------------------- */
94594 
94595 /*!
94596  * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
94597  * @{
94598  */
94599 
94600 /** TPM - Register Layout Typedef */
94601 typedef struct {
94602   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
94603   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
94604   __IO uint32_t GLOBAL;                            /**< TPM Global Register, offset: 0x8 */
94605        uint8_t RESERVED_0[4];
94606   __IO uint32_t SC;                                /**< Status and Control, offset: 0x10 */
94607   __IO uint32_t CNT;                               /**< Counter, offset: 0x14 */
94608   __IO uint32_t MOD;                               /**< Modulo, offset: 0x18 */
94609   __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x1C */
94610   struct {                                         /* offset: 0x20, array step: 0x8 */
94611     __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
94612     __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
94613   } CONTROLS[6];
94614        uint8_t RESERVED_1[20];
94615   __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
94616        uint8_t RESERVED_2[4];
94617   __IO uint32_t TRIG;                              /**< Channel Trigger, offset: 0x6C */
94618   __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
94619        uint8_t RESERVED_3[4];
94620   __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
94621        uint8_t RESERVED_4[4];
94622   __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
94623   __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
94624 } TPM_Type;
94625 
94626 /* ----------------------------------------------------------------------------
94627    -- TPM Register Masks
94628    ---------------------------------------------------------------------------- */
94629 
94630 /*!
94631  * @addtogroup TPM_Register_Masks TPM Register Masks
94632  * @{
94633  */
94634 
94635 /*! @name VERID - Version ID Register */
94636 /*! @{ */
94637 #define TPM_VERID_FEATURE_MASK                   (0xFFFFU)
94638 #define TPM_VERID_FEATURE_SHIFT                  (0U)
94639 /*! FEATURE - Feature Identification Number
94640  *  0b0000000000000001..Standard feature set.
94641  *  0b0000000000000011..Standard feature set with Filter and Combine registers implemented.
94642  *  0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented.
94643  */
94644 #define TPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK)
94645 #define TPM_VERID_MINOR_MASK                     (0xFF0000U)
94646 #define TPM_VERID_MINOR_SHIFT                    (16U)
94647 /*! MINOR - Minor Version Number
94648  */
94649 #define TPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK)
94650 #define TPM_VERID_MAJOR_MASK                     (0xFF000000U)
94651 #define TPM_VERID_MAJOR_SHIFT                    (24U)
94652 /*! MAJOR - Major Version Number
94653  */
94654 #define TPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK)
94655 /*! @} */
94656 
94657 /*! @name PARAM - Parameter Register */
94658 /*! @{ */
94659 #define TPM_PARAM_CHAN_MASK                      (0xFFU)
94660 #define TPM_PARAM_CHAN_SHIFT                     (0U)
94661 /*! CHAN - Channel Count
94662  */
94663 #define TPM_PARAM_CHAN(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK)
94664 #define TPM_PARAM_TRIG_MASK                      (0xFF00U)
94665 #define TPM_PARAM_TRIG_SHIFT                     (8U)
94666 /*! TRIG - Trigger Count
94667  */
94668 #define TPM_PARAM_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK)
94669 #define TPM_PARAM_WIDTH_MASK                     (0xFF0000U)
94670 #define TPM_PARAM_WIDTH_SHIFT                    (16U)
94671 /*! WIDTH - Counter Width
94672  */
94673 #define TPM_PARAM_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK)
94674 /*! @} */
94675 
94676 /*! @name GLOBAL - TPM Global Register */
94677 /*! @{ */
94678 #define TPM_GLOBAL_RST_MASK                      (0x2U)
94679 #define TPM_GLOBAL_RST_SHIFT                     (1U)
94680 /*! RST - Software Reset
94681  *  0b0..Module is not reset.
94682  *  0b1..Module is reset.
94683  */
94684 #define TPM_GLOBAL_RST(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK)
94685 /*! @} */
94686 
94687 /*! @name SC - Status and Control */
94688 /*! @{ */
94689 #define TPM_SC_PS_MASK                           (0x7U)
94690 #define TPM_SC_PS_SHIFT                          (0U)
94691 /*! PS - Prescale Factor Selection
94692  *  0b000..Divide by 1
94693  *  0b001..Divide by 2
94694  *  0b010..Divide by 4
94695  *  0b011..Divide by 8
94696  *  0b100..Divide by 16
94697  *  0b101..Divide by 32
94698  *  0b110..Divide by 64
94699  *  0b111..Divide by 128
94700  */
94701 #define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
94702 #define TPM_SC_CMOD_MASK                         (0x18U)
94703 #define TPM_SC_CMOD_SHIFT                        (3U)
94704 /*! CMOD - Clock Mode Selection
94705  *  0b00..TPM counter is disabled
94706  *  0b01..TPM counter increments on every TPM counter clock
94707  *  0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
94708  *  0b11..TPM counter increments on rising edge of the selected external input trigger.
94709  */
94710 #define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
94711 #define TPM_SC_CPWMS_MASK                        (0x20U)
94712 #define TPM_SC_CPWMS_SHIFT                       (5U)
94713 /*! CPWMS - Center-Aligned PWM Select
94714  *  0b0..TPM counter operates in up counting mode.
94715  *  0b1..TPM counter operates in up-down counting mode.
94716  */
94717 #define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
94718 #define TPM_SC_TOIE_MASK                         (0x40U)
94719 #define TPM_SC_TOIE_SHIFT                        (6U)
94720 /*! TOIE - Timer Overflow Interrupt Enable
94721  *  0b0..Disable TOF interrupts. Use software polling or DMA request.
94722  *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
94723  */
94724 #define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
94725 #define TPM_SC_TOF_MASK                          (0x80U)
94726 #define TPM_SC_TOF_SHIFT                         (7U)
94727 /*! TOF - Timer Overflow Flag
94728  *  0b0..TPM counter has not overflowed.
94729  *  0b1..TPM counter has overflowed.
94730  */
94731 #define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
94732 #define TPM_SC_DMA_MASK                          (0x100U)
94733 #define TPM_SC_DMA_SHIFT                         (8U)
94734 /*! DMA - DMA Enable
94735  *  0b0..Disables DMA transfers.
94736  *  0b1..Enables DMA transfers.
94737  */
94738 #define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
94739 /*! @} */
94740 
94741 /*! @name CNT - Counter */
94742 /*! @{ */
94743 #define TPM_CNT_COUNT_MASK                       (0xFFFFFFFFU)
94744 #define TPM_CNT_COUNT_SHIFT                      (0U)
94745 /*! COUNT - Counter value
94746  */
94747 #define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
94748 /*! @} */
94749 
94750 /*! @name MOD - Modulo */
94751 /*! @{ */
94752 #define TPM_MOD_MOD_MASK                         (0xFFFFFFFFU)
94753 #define TPM_MOD_MOD_SHIFT                        (0U)
94754 /*! MOD - Modulo value
94755  */
94756 #define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
94757 /*! @} */
94758 
94759 /*! @name STATUS - Capture and Compare Status */
94760 /*! @{ */
94761 #define TPM_STATUS_CH0F_MASK                     (0x1U)
94762 #define TPM_STATUS_CH0F_SHIFT                    (0U)
94763 /*! CH0F - Channel 0 Flag
94764  *  0b0..No channel event has occurred.
94765  *  0b1..A channel event has occurred.
94766  */
94767 #define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
94768 #define TPM_STATUS_CH1F_MASK                     (0x2U)
94769 #define TPM_STATUS_CH1F_SHIFT                    (1U)
94770 /*! CH1F - Channel 1 Flag
94771  *  0b0..No channel event has occurred.
94772  *  0b1..A channel event has occurred.
94773  */
94774 #define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
94775 #define TPM_STATUS_CH2F_MASK                     (0x4U)
94776 #define TPM_STATUS_CH2F_SHIFT                    (2U)
94777 /*! CH2F - Channel 2 Flag
94778  *  0b0..No channel event has occurred.
94779  *  0b1..A channel event has occurred.
94780  */
94781 #define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
94782 #define TPM_STATUS_CH3F_MASK                     (0x8U)
94783 #define TPM_STATUS_CH3F_SHIFT                    (3U)
94784 /*! CH3F - Channel 3 Flag
94785  *  0b0..No channel event has occurred.
94786  *  0b1..A channel event has occurred.
94787  */
94788 #define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
94789 #define TPM_STATUS_CH4F_MASK                     (0x10U)
94790 #define TPM_STATUS_CH4F_SHIFT                    (4U)
94791 /*! CH4F - Channel 4 Flag
94792  *  0b0..No channel event has occurred.
94793  *  0b1..A channel event has occurred.
94794  */
94795 #define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
94796 #define TPM_STATUS_CH5F_MASK                     (0x20U)
94797 #define TPM_STATUS_CH5F_SHIFT                    (5U)
94798 /*! CH5F - Channel 5 Flag
94799  *  0b0..No channel event has occurred.
94800  *  0b1..A channel event has occurred.
94801  */
94802 #define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
94803 #define TPM_STATUS_TOF_MASK                      (0x100U)
94804 #define TPM_STATUS_TOF_SHIFT                     (8U)
94805 /*! TOF - Timer Overflow Flag
94806  *  0b0..TPM counter has not overflowed.
94807  *  0b1..TPM counter has overflowed.
94808  */
94809 #define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
94810 /*! @} */
94811 
94812 /*! @name CnSC - Channel (n) Status and Control */
94813 /*! @{ */
94814 #define TPM_CnSC_DMA_MASK                        (0x1U)
94815 #define TPM_CnSC_DMA_SHIFT                       (0U)
94816 /*! DMA - DMA Enable
94817  *  0b0..Disable DMA transfers.
94818  *  0b1..Enable DMA transfers.
94819  */
94820 #define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
94821 #define TPM_CnSC_ELSA_MASK                       (0x4U)
94822 #define TPM_CnSC_ELSA_SHIFT                      (2U)
94823 /*! ELSA - Edge or Level Select
94824  */
94825 #define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
94826 #define TPM_CnSC_ELSB_MASK                       (0x8U)
94827 #define TPM_CnSC_ELSB_SHIFT                      (3U)
94828 /*! ELSB - Edge or Level Select
94829  */
94830 #define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
94831 #define TPM_CnSC_MSA_MASK                        (0x10U)
94832 #define TPM_CnSC_MSA_SHIFT                       (4U)
94833 /*! MSA - Channel Mode Select
94834  */
94835 #define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
94836 #define TPM_CnSC_MSB_MASK                        (0x20U)
94837 #define TPM_CnSC_MSB_SHIFT                       (5U)
94838 /*! MSB - Channel Mode Select
94839  */
94840 #define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
94841 #define TPM_CnSC_CHIE_MASK                       (0x40U)
94842 #define TPM_CnSC_CHIE_SHIFT                      (6U)
94843 /*! CHIE - Channel Interrupt Enable
94844  *  0b0..Disable channel interrupts.
94845  *  0b1..Enable channel interrupts.
94846  */
94847 #define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
94848 #define TPM_CnSC_CHF_MASK                        (0x80U)
94849 #define TPM_CnSC_CHF_SHIFT                       (7U)
94850 /*! CHF - Channel Flag
94851  *  0b0..No channel event has occurred.
94852  *  0b1..A channel event has occurred.
94853  */
94854 #define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
94855 /*! @} */
94856 
94857 /* The count of TPM_CnSC */
94858 #define TPM_CnSC_COUNT                           (6U)
94859 
94860 /*! @name CnV - Channel (n) Value */
94861 /*! @{ */
94862 #define TPM_CnV_VAL_MASK                         (0xFFFFFFFFU)
94863 #define TPM_CnV_VAL_SHIFT                        (0U)
94864 /*! VAL - Channel Value
94865  */
94866 #define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
94867 /*! @} */
94868 
94869 /* The count of TPM_CnV */
94870 #define TPM_CnV_COUNT                            (6U)
94871 
94872 /*! @name COMBINE - Combine Channel Register */
94873 /*! @{ */
94874 #define TPM_COMBINE_COMBINE0_MASK                (0x1U)
94875 #define TPM_COMBINE_COMBINE0_SHIFT               (0U)
94876 /*! COMBINE0 - Combine Channels 0 and 1
94877  *  0b0..Channels 0 and 1 are independent.
94878  *  0b1..Channels 0 and 1 are combined.
94879  */
94880 #define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
94881 #define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
94882 #define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
94883 /*! COMSWAP0 - Combine Channel 0 and 1 Swap
94884  *  0b0..Even channel is used for input capture and 1st compare.
94885  *  0b1..Odd channel is used for input capture and 1st compare.
94886  */
94887 #define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
94888 #define TPM_COMBINE_COMBINE1_MASK                (0x100U)
94889 #define TPM_COMBINE_COMBINE1_SHIFT               (8U)
94890 /*! COMBINE1 - Combine Channels 2 and 3
94891  *  0b0..Channels 2 and 3 are independent.
94892  *  0b1..Channels 2 and 3 are combined.
94893  */
94894 #define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
94895 #define TPM_COMBINE_COMSWAP1_MASK                (0x200U)
94896 #define TPM_COMBINE_COMSWAP1_SHIFT               (9U)
94897 /*! COMSWAP1 - Combine Channels 2 and 3 Swap
94898  *  0b0..Even channel is used for input capture and 1st compare.
94899  *  0b1..Odd channel is used for input capture and 1st compare.
94900  */
94901 #define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
94902 #define TPM_COMBINE_COMBINE2_MASK                (0x10000U)
94903 #define TPM_COMBINE_COMBINE2_SHIFT               (16U)
94904 /*! COMBINE2 - Combine Channels 4 and 5
94905  *  0b0..Channels 4 and 5 are independent.
94906  *  0b1..Channels 4 and 5 are combined.
94907  */
94908 #define TPM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK)
94909 #define TPM_COMBINE_COMSWAP2_MASK                (0x20000U)
94910 #define TPM_COMBINE_COMSWAP2_SHIFT               (17U)
94911 /*! COMSWAP2 - Combine Channels 4 and 5 Swap
94912  *  0b0..Even channel is used for input capture and 1st compare.
94913  *  0b1..Odd channel is used for input capture and 1st compare.
94914  */
94915 #define TPM_COMBINE_COMSWAP2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK)
94916 /*! @} */
94917 
94918 /*! @name TRIG - Channel Trigger */
94919 /*! @{ */
94920 #define TPM_TRIG_TRIG0_MASK                      (0x1U)
94921 #define TPM_TRIG_TRIG0_SHIFT                     (0U)
94922 /*! TRIG0 - Channel 0 Trigger
94923  *  0b0..No effect.
94924  *  0b1..Configures trigger input 0 to be used by channel 0.
94925  */
94926 #define TPM_TRIG_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK)
94927 #define TPM_TRIG_TRIG1_MASK                      (0x2U)
94928 #define TPM_TRIG_TRIG1_SHIFT                     (1U)
94929 /*! TRIG1 - Channel 1 Trigger
94930  *  0b0..No effect.
94931  *  0b1..Configures trigger input 1 to be used by channel 1.
94932  */
94933 #define TPM_TRIG_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK)
94934 #define TPM_TRIG_TRIG2_MASK                      (0x4U)
94935 #define TPM_TRIG_TRIG2_SHIFT                     (2U)
94936 /*! TRIG2 - Channel 2 Trigger
94937  *  0b0..No effect.
94938  *  0b1..Configures trigger input 0 to be used by channel 2.
94939  */
94940 #define TPM_TRIG_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK)
94941 #define TPM_TRIG_TRIG3_MASK                      (0x8U)
94942 #define TPM_TRIG_TRIG3_SHIFT                     (3U)
94943 /*! TRIG3 - Channel 3 Trigger
94944  *  0b0..No effect.
94945  *  0b1..Configures trigger input 1 to be used by channel 3.
94946  */
94947 #define TPM_TRIG_TRIG3(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK)
94948 #define TPM_TRIG_TRIG4_MASK                      (0x10U)
94949 #define TPM_TRIG_TRIG4_SHIFT                     (4U)
94950 /*! TRIG4 - Channel 4 Trigger
94951  *  0b0..No effect.
94952  *  0b1..Configures trigger input 0 to be used by channel 4.
94953  */
94954 #define TPM_TRIG_TRIG4(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK)
94955 #define TPM_TRIG_TRIG5_MASK                      (0x20U)
94956 #define TPM_TRIG_TRIG5_SHIFT                     (5U)
94957 /*! TRIG5 - Channel 5 Trigger
94958  *  0b0..No effect.
94959  *  0b1..Configures trigger input 1 to be used by channel 5.
94960  */
94961 #define TPM_TRIG_TRIG5(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK)
94962 /*! @} */
94963 
94964 /*! @name POL - Channel Polarity */
94965 /*! @{ */
94966 #define TPM_POL_POL0_MASK                        (0x1U)
94967 #define TPM_POL_POL0_SHIFT                       (0U)
94968 /*! POL0 - Channel 0 Polarity
94969  *  0b0..The channel polarity is active high.
94970  *  0b1..The channel polarity is active low.
94971  */
94972 #define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
94973 #define TPM_POL_POL1_MASK                        (0x2U)
94974 #define TPM_POL_POL1_SHIFT                       (1U)
94975 /*! POL1 - Channel 1 Polarity
94976  *  0b0..The channel polarity is active high.
94977  *  0b1..The channel polarity is active low.
94978  */
94979 #define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
94980 #define TPM_POL_POL2_MASK                        (0x4U)
94981 #define TPM_POL_POL2_SHIFT                       (2U)
94982 /*! POL2 - Channel 2 Polarity
94983  *  0b0..The channel polarity is active high.
94984  *  0b1..The channel polarity is active low.
94985  */
94986 #define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
94987 #define TPM_POL_POL3_MASK                        (0x8U)
94988 #define TPM_POL_POL3_SHIFT                       (3U)
94989 /*! POL3 - Channel 3 Polarity
94990  *  0b0..The channel polarity is active high.
94991  *  0b1..The channel polarity is active low.
94992  */
94993 #define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
94994 #define TPM_POL_POL4_MASK                        (0x10U)
94995 #define TPM_POL_POL4_SHIFT                       (4U)
94996 /*! POL4 - Channel 4 Polarity
94997  *  0b0..The channel polarity is active high
94998  *  0b1..The channel polarity is active low.
94999  */
95000 #define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
95001 #define TPM_POL_POL5_MASK                        (0x20U)
95002 #define TPM_POL_POL5_SHIFT                       (5U)
95003 /*! POL5 - Channel 5 Polarity
95004  *  0b0..The channel polarity is active high.
95005  *  0b1..The channel polarity is active low.
95006  */
95007 #define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
95008 /*! @} */
95009 
95010 /*! @name FILTER - Filter Control */
95011 /*! @{ */
95012 #define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
95013 #define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
95014 /*! CH0FVAL - Channel 0 Filter Value
95015  */
95016 #define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
95017 #define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
95018 #define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
95019 /*! CH1FVAL - Channel 1 Filter Value
95020  */
95021 #define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
95022 #define TPM_FILTER_CH2FVAL_MASK                  (0xF00U)
95023 #define TPM_FILTER_CH2FVAL_SHIFT                 (8U)
95024 /*! CH2FVAL - Channel 2 Filter Value
95025  */
95026 #define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
95027 #define TPM_FILTER_CH3FVAL_MASK                  (0xF000U)
95028 #define TPM_FILTER_CH3FVAL_SHIFT                 (12U)
95029 /*! CH3FVAL - Channel 3 Filter Value
95030  */
95031 #define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
95032 #define TPM_FILTER_CH4FVAL_MASK                  (0xF0000U)
95033 #define TPM_FILTER_CH4FVAL_SHIFT                 (16U)
95034 /*! CH4FVAL - Channel 4 Filter Value
95035  */
95036 #define TPM_FILTER_CH4FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK)
95037 #define TPM_FILTER_CH5FVAL_MASK                  (0xF00000U)
95038 #define TPM_FILTER_CH5FVAL_SHIFT                 (20U)
95039 /*! CH5FVAL - Channel 5 Filter Value
95040  */
95041 #define TPM_FILTER_CH5FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK)
95042 /*! @} */
95043 
95044 /*! @name QDCTRL - Quadrature Decoder Control and Status */
95045 /*! @{ */
95046 #define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
95047 #define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
95048 /*! QUADEN - QUADEN
95049  *  0b0..Quadrature decoder mode is disabled.
95050  *  0b1..Quadrature decoder mode is enabled.
95051  */
95052 #define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
95053 #define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
95054 #define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
95055 /*! TOFDIR - TOFDIR
95056  *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes
95057  *       from its minimum value (zero) to its maximum value (MOD register).
95058  *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from
95059  *       its maximum value (MOD register) to its minimum value (zero).
95060  */
95061 #define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
95062 #define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
95063 #define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
95064 /*! QUADIR - Counter Direction in Quadrature Decode Mode
95065  *  0b0..Counter direction is decreasing (counter decrement).
95066  *  0b1..Counter direction is increasing (counter increment).
95067  */
95068 #define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
95069 #define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
95070 #define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
95071 /*! QUADMODE - Quadrature Decoder Mode
95072  *  0b0..Phase encoding mode.
95073  *  0b1..Count and direction encoding mode.
95074  */
95075 #define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
95076 /*! @} */
95077 
95078 /*! @name CONF - Configuration */
95079 /*! @{ */
95080 #define TPM_CONF_DOZEEN_MASK                     (0x20U)
95081 #define TPM_CONF_DOZEEN_SHIFT                    (5U)
95082 /*! DOZEEN - Doze Enable
95083  *  0b0..Internal TPM counter continues in Doze mode.
95084  *  0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture
95085  *       events are ignored, and PWM outputs are forced to their default state.
95086  */
95087 #define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
95088 #define TPM_CONF_DBGMODE_MASK                    (0xC0U)
95089 #define TPM_CONF_DBGMODE_SHIFT                   (6U)
95090 /*! DBGMODE - Debug Mode
95091  *  0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events
95092  *        are ignored, and PWM outputs are forced to their default state.
95093  *  0b11..TPM counter continues in debug mode.
95094  */
95095 #define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
95096 #define TPM_CONF_GTBSYNC_MASK                    (0x100U)
95097 #define TPM_CONF_GTBSYNC_SHIFT                   (8U)
95098 /*! GTBSYNC - Global Time Base Synchronization
95099  *  0b0..Global timebase synchronization disabled.
95100  *  0b1..Global timebase synchronization enabled.
95101  */
95102 #define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
95103 #define TPM_CONF_GTBEEN_MASK                     (0x200U)
95104 #define TPM_CONF_GTBEEN_SHIFT                    (9U)
95105 /*! GTBEEN - Global time base enable
95106  *  0b0..All channels use the internally generated TPM counter as their timebase
95107  *  0b1..All channels use an externally generated global timebase as their timebase
95108  */
95109 #define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
95110 #define TPM_CONF_CSOT_MASK                       (0x10000U)
95111 #define TPM_CONF_CSOT_SHIFT                      (16U)
95112 /*! CSOT - Counter Start on Trigger
95113  *  0b0..TPM counter starts to increment immediately, once it is enabled.
95114  *  0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected,
95115  *       after it has been enabled or after it has stopped due to overflow.
95116  */
95117 #define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
95118 #define TPM_CONF_CSOO_MASK                       (0x20000U)
95119 #define TPM_CONF_CSOO_SHIFT                      (17U)
95120 /*! CSOO - Counter Stop On Overflow
95121  *  0b0..TPM counter continues incrementing or decrementing after overflow
95122  *  0b1..TPM counter stops incrementing or decrementing after overflow.
95123  */
95124 #define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
95125 #define TPM_CONF_CROT_MASK                       (0x40000U)
95126 #define TPM_CONF_CROT_SHIFT                      (18U)
95127 /*! CROT - Counter Reload On Trigger
95128  *  0b0..Counter is not reloaded due to a rising edge on the selected input trigger
95129  *  0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
95130  */
95131 #define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
95132 #define TPM_CONF_CPOT_MASK                       (0x80000U)
95133 #define TPM_CONF_CPOT_SHIFT                      (19U)
95134 /*! CPOT - Counter Pause On Trigger
95135  */
95136 #define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
95137 #define TPM_CONF_TRGPOL_MASK                     (0x400000U)
95138 #define TPM_CONF_TRGPOL_SHIFT                    (22U)
95139 /*! TRGPOL - Trigger Polarity
95140  *  0b0..Trigger is active high.
95141  *  0b1..Trigger is active low.
95142  */
95143 #define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
95144 #define TPM_CONF_TRGSRC_MASK                     (0x800000U)
95145 #define TPM_CONF_TRGSRC_SHIFT                    (23U)
95146 /*! TRGSRC - Trigger Source
95147  *  0b0..Trigger source selected by TRGSEL is external.
95148  *  0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
95149  */
95150 #define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
95151 #define TPM_CONF_TRGSEL_MASK                     (0xF000000U)
95152 #define TPM_CONF_TRGSEL_SHIFT                    (24U)
95153 /*! TRGSEL - Trigger Select
95154  *  0b0001..Channel 0 pin input capture
95155  *  0b0010..Channel 1 pin input capture
95156  *  0b0011..Channel 0 or Channel 1 pin input capture
95157  *  0b0100..Channel 2 pin input capture
95158  *  0b0101..Channel 0 or Channel 2 pin input capture
95159  *  0b0110..Channel 1 or Channel 2 pin input capture
95160  *  0b0111..Channel 0 or Channel 1 or Channel 2 pin input capture
95161  *  0b1000..Channel 3 pin input capture
95162  *  0b1001..Channel 0 or Channel 3 pin input capture
95163  *  0b1010..Channel 1 or Channel 3 pin input capture
95164  *  0b1011..Channel 0 or Channel 1 or Channel 3 pin input capture
95165  *  0b1100..Channel 2 or Channel 3 pin input capture
95166  *  0b1101..Channel 0 or Channel 2 or Channel 3 pin input capture
95167  *  0b1110..Channel 1 or Channel 2 or Channel 3 pin input capture
95168  *  0b1111..Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture
95169  */
95170 #define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
95171 /*! @} */
95172 
95173 
95174 /*!
95175  * @}
95176  */ /* end of group TPM_Register_Masks */
95177 
95178 
95179 /* TPM - Peripheral instance base addresses */
95180 /** Peripheral CM4__TPM base address */
95181 #define CM4__TPM_BASE                            (0x41200000u)
95182 /** Peripheral CM4__TPM base pointer */
95183 #define CM4__TPM                                 ((TPM_Type *)CM4__TPM_BASE)
95184 /** Peripheral SCU__TPM base address */
95185 #define SCU__TPM_BASE                            (0x33200000u)
95186 /** Peripheral SCU__TPM base pointer */
95187 #define SCU__TPM                                 ((TPM_Type *)SCU__TPM_BASE)
95188 /** Array initializer of TPM peripheral base addresses */
95189 #define TPM_BASE_ADDRS                           { CM4__TPM_BASE, SCU__TPM_BASE }
95190 /** Array initializer of TPM peripheral base pointers */
95191 #define TPM_BASE_PTRS                            { CM4__TPM, SCU__TPM }
95192 /** Interrupt vectors for the TPM peripheral type */
95193 #define TPM_IRQS                                 { M4_TPM_IRQn, NotAvail_IRQn }
95194 
95195 /*!
95196  * @}
95197  */ /* end of group TPM_Peripheral_Access_Layer */
95198 
95199 
95200 /* ----------------------------------------------------------------------------
95201    -- TSTMR Peripheral Access Layer
95202    ---------------------------------------------------------------------------- */
95203 
95204 /*!
95205  * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
95206  * @{
95207  */
95208 
95209 /** TSTMR - Register Layout Typedef */
95210 typedef struct {
95211   __I  uint32_t L;                                 /**< Time Stamp Timer Register Low, offset: 0x0 */
95212   __I  uint32_t H;                                 /**< Time Stamp Timer Register High, offset: 0x4 */
95213 } TSTMR_Type;
95214 
95215 /* ----------------------------------------------------------------------------
95216    -- TSTMR Register Masks
95217    ---------------------------------------------------------------------------- */
95218 
95219 /*!
95220  * @addtogroup TSTMR_Register_Masks TSTMR Register Masks
95221  * @{
95222  */
95223 
95224 /*! @name L - Time Stamp Timer Register Low */
95225 /*! @{ */
95226 #define TSTMR_L_VALUE_MASK                       (0xFFFFFFFFU)
95227 #define TSTMR_L_VALUE_SHIFT                      (0U)
95228 /*! VALUE - Time Stamp Timer Low
95229  */
95230 #define TSTMR_L_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK)
95231 /*! @} */
95232 
95233 /*! @name H - Time Stamp Timer Register High */
95234 /*! @{ */
95235 #define TSTMR_H_VALUE_MASK                       (0xFFFFFFFFU)
95236 #define TSTMR_H_VALUE_SHIFT                      (0U)
95237 /*! VALUE - Time Stamp Timer High
95238  */
95239 #define TSTMR_H_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK)
95240 /*! @} */
95241 
95242 
95243 /*!
95244  * @}
95245  */ /* end of group TSTMR_Register_Masks */
95246 
95247 
95248 /* TSTMR - Peripheral instance base addresses */
95249 /** Peripheral CM4__TSTMR base address */
95250 #define CM4__TSTMR_BASE                          (0x414100F0u)
95251 /** Peripheral CM4__TSTMR base pointer */
95252 #define CM4__TSTMR                               ((TSTMR_Type *)CM4__TSTMR_BASE)
95253 /** Peripheral SCU__TSTMR base address */
95254 #define SCU__TSTMR_BASE                          (0x334100F0u)
95255 /** Peripheral SCU__TSTMR base pointer */
95256 #define SCU__TSTMR                               ((TSTMR_Type *)SCU__TSTMR_BASE)
95257 /** Array initializer of TSTMR peripheral base addresses */
95258 #define TSTMR_BASE_ADDRS                         { CM4__TSTMR_BASE, SCU__TSTMR_BASE }
95259 /** Array initializer of TSTMR peripheral base pointers */
95260 #define TSTMR_BASE_PTRS                          { CM4__TSTMR, SCU__TSTMR }
95261 
95262 /*!
95263  * @}
95264  */ /* end of group TSTMR_Peripheral_Access_Layer */
95265 
95266 
95267 /* ----------------------------------------------------------------------------
95268    -- USB Peripheral Access Layer
95269    ---------------------------------------------------------------------------- */
95270 
95271 /*!
95272  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
95273  * @{
95274  */
95275 
95276 /** USB - Register Layout Typedef */
95277 typedef struct {
95278   __I  uint32_t ID;                                /**< Identification register, offset: 0x0 */
95279   __I  uint32_t HWGENERAL;                         /**< Hardware General, offset: 0x4 */
95280   __I  uint32_t HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
95281   __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
95282   __I  uint32_t HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
95283   __I  uint32_t HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
95284        uint8_t RESERVED_0[104];
95285   __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x80 */
95286   __IO uint32_t GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x84 */
95287   __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x88 */
95288   __IO uint32_t GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x8C */
95289   __IO uint32_t SBUSCFG;                           /**< System Bus Config, offset: 0x90 */
95290        uint8_t RESERVED_1[108];
95291   __I  uint8_t CAPLENGTH;                          /**< Capability Registers Length, offset: 0x100 */
95292        uint8_t RESERVED_2[1];
95293   __I  uint16_t HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
95294   __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
95295   __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
95296        uint8_t RESERVED_3[20];
95297   __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
95298        uint8_t RESERVED_4[2];
95299   __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
95300        uint8_t RESERVED_5[24];
95301   __IO uint32_t USBCMD;                            /**< USB Command Register, offset: 0x140 */
95302   __IO uint32_t USBSTS;                            /**< USB Status Register, offset: 0x144 */
95303   __IO uint32_t USBINTR;                           /**< Interrupt Enable Register, offset: 0x148 */
95304   __IO uint32_t FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
95305        uint8_t RESERVED_6[4];
95306   union {                                          /* offset: 0x154 */
95307     __IO uint32_t DEVICEADDR;                        /**< Device Address, offset: 0x154 */
95308     __IO uint32_t PERIODICLISTBASE;                  /**< Frame List Base Address, offset: 0x154 */
95309   };
95310   union {                                          /* offset: 0x158 */
95311     __IO uint32_t ASYNCLISTADDR;                     /**< Next Asynch. Address, offset: 0x158 */
95312     __IO uint32_t ENDPTLISTADDR;                     /**< Endpoint List Address, offset: 0x158 */
95313   };
95314        uint8_t RESERVED_7[4];
95315   __IO uint32_t BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
95316   __IO uint32_t TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
95317        uint8_t RESERVED_8[16];
95318   __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
95319   __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
95320   __I  uint32_t CONFIGFLAG;                        /**< Configure Flag Register, offset: 0x180 */
95321   __IO uint32_t PORTSC1;                           /**< Port Status & Control, offset: 0x184 */
95322        uint8_t RESERVED_9[28];
95323   __IO uint32_t OTGSC;                             /**< On-The-Go Status & control, offset: 0x1A4 */
95324   __IO uint32_t USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
95325   __IO uint32_t ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
95326   __IO uint32_t ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x1B0 */
95327   __IO uint32_t ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x1B4 */
95328   __I  uint32_t ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
95329   __IO uint32_t ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
95330   __IO uint32_t ENDPTCTRL0;                        /**< Endpoint Control0, offset: 0x1C0 */
95331   __IO uint32_t ENDPTCTRL[7];                      /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
95332 } USB_Type;
95333 
95334 /* ----------------------------------------------------------------------------
95335    -- USB Register Masks
95336    ---------------------------------------------------------------------------- */
95337 
95338 /*!
95339  * @addtogroup USB_Register_Masks USB Register Masks
95340  * @{
95341  */
95342 
95343 /*! @name ID - Identification register */
95344 /*! @{ */
95345 #define USB_ID_ID_MASK                           (0x3FU)
95346 #define USB_ID_ID_SHIFT                          (0U)
95347 #define USB_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
95348 #define USB_ID_NID_MASK                          (0x3F00U)
95349 #define USB_ID_NID_SHIFT                         (8U)
95350 #define USB_ID_NID(x)                            (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
95351 #define USB_ID_REVISION_MASK                     (0xFF0000U)
95352 #define USB_ID_REVISION_SHIFT                    (16U)
95353 #define USB_ID_REVISION(x)                       (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
95354 /*! @} */
95355 
95356 /*! @name HWGENERAL - Hardware General */
95357 /*! @{ */
95358 #define USB_HWGENERAL_PHYW_MASK                  (0x30U)
95359 #define USB_HWGENERAL_PHYW_SHIFT                 (4U)
95360 /*! PHYW
95361  *  0b00..8 bit wide data bus Software non-programmable
95362  *  0b01..16 bit wide data bus Software non-programmable
95363  *  0b10..Reset to 8 bit wide data bus Software programmable
95364  *  0b11..Reset to 16 bit wide data bus Software programmable
95365  */
95366 #define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
95367 #define USB_HWGENERAL_PHYM_MASK                  (0x1C0U)
95368 #define USB_HWGENERAL_PHYM_SHIFT                 (6U)
95369 /*! PHYM
95370  *  0b000..UTMI/UMTI+
95371  *  0b001..ULPI DDR
95372  *  0b010..ULPI
95373  *  0b011..Serial Only
95374  *  0b100..Software programmable - reset to UTMI/UTMI+
95375  *  0b101..Software programmable - reset to ULPI DDR
95376  *  0b110..Software programmable - reset to ULPI
95377  *  0b111..Software programmable - reset to Serial
95378  */
95379 #define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
95380 #define USB_HWGENERAL_SM_MASK                    (0x600U)
95381 #define USB_HWGENERAL_SM_SHIFT                   (9U)
95382 /*! SM
95383  *  0b00..No Serial Engine, always use parallel signalling.
95384  *  0b01..Serial Engine present, always use serial signalling for FS/LS.
95385  *  0b10..Software programmable - Reset to use parallel signalling for FS/LS
95386  *  0b11..Software programmable - Reset to use serial signalling for FS/LS
95387  */
95388 #define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
95389 /*! @} */
95390 
95391 /*! @name HWHOST - Host Hardware Parameters */
95392 /*! @{ */
95393 #define USB_HWHOST_HC_MASK                       (0x1U)
95394 #define USB_HWHOST_HC_SHIFT                      (0U)
95395 /*! HC
95396  *  0b1..Supported
95397  *  0b0..Not supported
95398  */
95399 #define USB_HWHOST_HC(x)                         (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
95400 #define USB_HWHOST_NPORT_MASK                    (0xEU)
95401 #define USB_HWHOST_NPORT_SHIFT                   (1U)
95402 #define USB_HWHOST_NPORT(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
95403 /*! @} */
95404 
95405 /*! @name HWDEVICE - Device Hardware Parameters */
95406 /*! @{ */
95407 #define USB_HWDEVICE_DC_MASK                     (0x1U)
95408 #define USB_HWDEVICE_DC_SHIFT                    (0U)
95409 /*! DC
95410  *  0b1..Supported
95411  *  0b0..Not supported
95412  */
95413 #define USB_HWDEVICE_DC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
95414 #define USB_HWDEVICE_DEVEP_MASK                  (0x3EU)
95415 #define USB_HWDEVICE_DEVEP_SHIFT                 (1U)
95416 #define USB_HWDEVICE_DEVEP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
95417 /*! @} */
95418 
95419 /*! @name HWTXBUF - TX Buffer Hardware Parameters */
95420 /*! @{ */
95421 #define USB_HWTXBUF_TXBURST_MASK                 (0xFFU)
95422 #define USB_HWTXBUF_TXBURST_SHIFT                (0U)
95423 #define USB_HWTXBUF_TXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
95424 #define USB_HWTXBUF_TXCHANADD_MASK               (0xFF0000U)
95425 #define USB_HWTXBUF_TXCHANADD_SHIFT              (16U)
95426 #define USB_HWTXBUF_TXCHANADD(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
95427 /*! @} */
95428 
95429 /*! @name HWRXBUF - RX Buffer Hardware Parameters */
95430 /*! @{ */
95431 #define USB_HWRXBUF_RXBURST_MASK                 (0xFFU)
95432 #define USB_HWRXBUF_RXBURST_SHIFT                (0U)
95433 #define USB_HWRXBUF_RXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
95434 #define USB_HWRXBUF_RXADD_MASK                   (0xFF00U)
95435 #define USB_HWRXBUF_RXADD_SHIFT                  (8U)
95436 #define USB_HWRXBUF_RXADD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
95437 /*! @} */
95438 
95439 /*! @name GPTIMER0LD - General Purpose Timer #0 Load */
95440 /*! @{ */
95441 #define USB_GPTIMER0LD_GPTLD_MASK                (0xFFFFFFU)
95442 #define USB_GPTIMER0LD_GPTLD_SHIFT               (0U)
95443 #define USB_GPTIMER0LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
95444 /*! @} */
95445 
95446 /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
95447 /*! @{ */
95448 #define USB_GPTIMER0CTRL_GPTCNT_MASK             (0xFFFFFFU)
95449 #define USB_GPTIMER0CTRL_GPTCNT_SHIFT            (0U)
95450 #define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
95451 #define USB_GPTIMER0CTRL_GPTMODE_MASK            (0x1000000U)
95452 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT           (24U)
95453 /*! GPTMODE
95454  *  0b0..One Shot Mode
95455  *  0b1..Repeat Mode
95456  */
95457 #define USB_GPTIMER0CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
95458 #define USB_GPTIMER0CTRL_GPTRST_MASK             (0x40000000U)
95459 #define USB_GPTIMER0CTRL_GPTRST_SHIFT            (30U)
95460 /*! GPTRST
95461  *  0b0..No action
95462  *  0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
95463  */
95464 #define USB_GPTIMER0CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
95465 #define USB_GPTIMER0CTRL_GPTRUN_MASK             (0x80000000U)
95466 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT            (31U)
95467 /*! GPTRUN
95468  *  0b0..Stop counting
95469  *  0b1..Run
95470  */
95471 #define USB_GPTIMER0CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
95472 /*! @} */
95473 
95474 /*! @name GPTIMER1LD - General Purpose Timer #1 Load */
95475 /*! @{ */
95476 #define USB_GPTIMER1LD_GPTLD_MASK                (0xFFFFFFU)
95477 #define USB_GPTIMER1LD_GPTLD_SHIFT               (0U)
95478 #define USB_GPTIMER1LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
95479 /*! @} */
95480 
95481 /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
95482 /*! @{ */
95483 #define USB_GPTIMER1CTRL_GPTCNT_MASK             (0xFFFFFFU)
95484 #define USB_GPTIMER1CTRL_GPTCNT_SHIFT            (0U)
95485 #define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
95486 #define USB_GPTIMER1CTRL_GPTMODE_MASK            (0x1000000U)
95487 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT           (24U)
95488 /*! GPTMODE
95489  *  0b0..One Shot Mode
95490  *  0b1..Repeat Mode
95491  */
95492 #define USB_GPTIMER1CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
95493 #define USB_GPTIMER1CTRL_GPTRST_MASK             (0x40000000U)
95494 #define USB_GPTIMER1CTRL_GPTRST_SHIFT            (30U)
95495 /*! GPTRST
95496  *  0b0..No action
95497  *  0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
95498  */
95499 #define USB_GPTIMER1CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
95500 #define USB_GPTIMER1CTRL_GPTRUN_MASK             (0x80000000U)
95501 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT            (31U)
95502 /*! GPTRUN
95503  *  0b0..Stop counting
95504  *  0b1..Run
95505  */
95506 #define USB_GPTIMER1CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
95507 /*! @} */
95508 
95509 /*! @name SBUSCFG - System Bus Config */
95510 /*! @{ */
95511 #define USB_SBUSCFG_AHBBRST_MASK                 (0x7U)
95512 #define USB_SBUSCFG_AHBBRST_SHIFT                (0U)
95513 /*! AHBBRST
95514  *  0b000..Incremental burst of unspecified length only
95515  *  0b001..INCR4 burst, then single transfer
95516  *  0b010..INCR8 burst, INCR4 burst, then single transfer
95517  *  0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
95518  *  0b100..Reserved, don't use
95519  *  0b101..INCR4 burst, then incremental burst of unspecified length
95520  *  0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
95521  *  0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
95522  */
95523 #define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
95524 /*! @} */
95525 
95526 /*! @name CAPLENGTH - Capability Registers Length */
95527 /*! @{ */
95528 #define USB_CAPLENGTH_CAPLENGTH_MASK             (0xFFU)
95529 #define USB_CAPLENGTH_CAPLENGTH_SHIFT            (0U)
95530 #define USB_CAPLENGTH_CAPLENGTH(x)               (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
95531 /*! @} */
95532 
95533 /*! @name HCIVERSION - Host Controller Interface Version */
95534 /*! @{ */
95535 #define USB_HCIVERSION_HCIVERSION_MASK           (0xFFFFU)
95536 #define USB_HCIVERSION_HCIVERSION_SHIFT          (0U)
95537 #define USB_HCIVERSION_HCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
95538 /*! @} */
95539 
95540 /*! @name HCSPARAMS - Host Controller Structural Parameters */
95541 /*! @{ */
95542 #define USB_HCSPARAMS_N_PORTS_MASK               (0xFU)
95543 #define USB_HCSPARAMS_N_PORTS_SHIFT              (0U)
95544 #define USB_HCSPARAMS_N_PORTS(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
95545 #define USB_HCSPARAMS_PPC_MASK                   (0x10U)
95546 #define USB_HCSPARAMS_PPC_SHIFT                  (4U)
95547 #define USB_HCSPARAMS_PPC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
95548 #define USB_HCSPARAMS_N_PCC_MASK                 (0xF00U)
95549 #define USB_HCSPARAMS_N_PCC_SHIFT                (8U)
95550 #define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
95551 #define USB_HCSPARAMS_N_CC_MASK                  (0xF000U)
95552 #define USB_HCSPARAMS_N_CC_SHIFT                 (12U)
95553 /*! N_CC
95554  *  0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
95555  *  0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
95556  */
95557 #define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
95558 #define USB_HCSPARAMS_PI_MASK                    (0x10000U)
95559 #define USB_HCSPARAMS_PI_SHIFT                   (16U)
95560 #define USB_HCSPARAMS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
95561 #define USB_HCSPARAMS_N_PTT_MASK                 (0xF00000U)
95562 #define USB_HCSPARAMS_N_PTT_SHIFT                (20U)
95563 #define USB_HCSPARAMS_N_PTT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
95564 #define USB_HCSPARAMS_N_TT_MASK                  (0xF000000U)
95565 #define USB_HCSPARAMS_N_TT_SHIFT                 (24U)
95566 #define USB_HCSPARAMS_N_TT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
95567 /*! @} */
95568 
95569 /*! @name HCCPARAMS - Host Controller Capability Parameters */
95570 /*! @{ */
95571 #define USB_HCCPARAMS_ADC_MASK                   (0x1U)
95572 #define USB_HCCPARAMS_ADC_SHIFT                  (0U)
95573 #define USB_HCCPARAMS_ADC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
95574 #define USB_HCCPARAMS_PFL_MASK                   (0x2U)
95575 #define USB_HCCPARAMS_PFL_SHIFT                  (1U)
95576 #define USB_HCCPARAMS_PFL(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
95577 #define USB_HCCPARAMS_ASP_MASK                   (0x4U)
95578 #define USB_HCCPARAMS_ASP_SHIFT                  (2U)
95579 #define USB_HCCPARAMS_ASP(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
95580 #define USB_HCCPARAMS_IST_MASK                   (0xF0U)
95581 #define USB_HCCPARAMS_IST_SHIFT                  (4U)
95582 #define USB_HCCPARAMS_IST(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
95583 #define USB_HCCPARAMS_EECP_MASK                  (0xFF00U)
95584 #define USB_HCCPARAMS_EECP_SHIFT                 (8U)
95585 #define USB_HCCPARAMS_EECP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
95586 /*! @} */
95587 
95588 /*! @name DCIVERSION - Device Controller Interface Version */
95589 /*! @{ */
95590 #define USB_DCIVERSION_DCIVERSION_MASK           (0xFFFFU)
95591 #define USB_DCIVERSION_DCIVERSION_SHIFT          (0U)
95592 #define USB_DCIVERSION_DCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
95593 /*! @} */
95594 
95595 /*! @name DCCPARAMS - Device Controller Capability Parameters */
95596 /*! @{ */
95597 #define USB_DCCPARAMS_DEN_MASK                   (0x1FU)
95598 #define USB_DCCPARAMS_DEN_SHIFT                  (0U)
95599 #define USB_DCCPARAMS_DEN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
95600 #define USB_DCCPARAMS_DC_MASK                    (0x80U)
95601 #define USB_DCCPARAMS_DC_SHIFT                   (7U)
95602 #define USB_DCCPARAMS_DC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
95603 #define USB_DCCPARAMS_HC_MASK                    (0x100U)
95604 #define USB_DCCPARAMS_HC_SHIFT                   (8U)
95605 #define USB_DCCPARAMS_HC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
95606 /*! @} */
95607 
95608 /*! @name USBCMD - USB Command Register */
95609 /*! @{ */
95610 #define USB_USBCMD_RS_MASK                       (0x1U)
95611 #define USB_USBCMD_RS_SHIFT                      (0U)
95612 #define USB_USBCMD_RS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
95613 #define USB_USBCMD_RST_MASK                      (0x2U)
95614 #define USB_USBCMD_RST_SHIFT                     (1U)
95615 #define USB_USBCMD_RST(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
95616 #define USB_USBCMD_FS_1_MASK                     (0xCU)
95617 #define USB_USBCMD_FS_1_SHIFT                    (2U)
95618 #define USB_USBCMD_FS_1(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
95619 #define USB_USBCMD_PSE_MASK                      (0x10U)
95620 #define USB_USBCMD_PSE_SHIFT                     (4U)
95621 /*! PSE
95622  *  0b0..Do not process the Periodic Schedule
95623  *  0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
95624  */
95625 #define USB_USBCMD_PSE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
95626 #define USB_USBCMD_ASE_MASK                      (0x20U)
95627 #define USB_USBCMD_ASE_SHIFT                     (5U)
95628 /*! ASE
95629  *  0b0..Do not process the Asynchronous Schedule.
95630  *  0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
95631  */
95632 #define USB_USBCMD_ASE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
95633 #define USB_USBCMD_IAA_MASK                      (0x40U)
95634 #define USB_USBCMD_IAA_SHIFT                     (6U)
95635 #define USB_USBCMD_IAA(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
95636 #define USB_USBCMD_ASP_MASK                      (0x300U)
95637 #define USB_USBCMD_ASP_SHIFT                     (8U)
95638 #define USB_USBCMD_ASP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
95639 #define USB_USBCMD_ASPE_MASK                     (0x800U)
95640 #define USB_USBCMD_ASPE_SHIFT                    (11U)
95641 #define USB_USBCMD_ASPE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
95642 #define USB_USBCMD_SUTW_MASK                     (0x2000U)
95643 #define USB_USBCMD_SUTW_SHIFT                    (13U)
95644 #define USB_USBCMD_SUTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
95645 #define USB_USBCMD_ATDTW_MASK                    (0x4000U)
95646 #define USB_USBCMD_ATDTW_SHIFT                   (14U)
95647 #define USB_USBCMD_ATDTW(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
95648 #define USB_USBCMD_FS_2_MASK                     (0x8000U)
95649 #define USB_USBCMD_FS_2_SHIFT                    (15U)
95650 /*! FS_2
95651  *  0b0..1024 elements (4096 bytes) Default value
95652  *  0b1..512 elements (2048 bytes)
95653  */
95654 #define USB_USBCMD_FS_2(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
95655 #define USB_USBCMD_ITC_MASK                      (0xFF0000U)
95656 #define USB_USBCMD_ITC_SHIFT                     (16U)
95657 /*! ITC
95658  *  0b00000000..Immediate (no threshold)
95659  *  0b00000001..1 micro-frame
95660  *  0b00000010..2 micro-frames
95661  *  0b00000100..4 micro-frames
95662  *  0b00001000..8 micro-frames
95663  *  0b00010000..16 micro-frames
95664  *  0b00100000..32 micro-frames
95665  *  0b01000000..64 micro-frames
95666  */
95667 #define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
95668 /*! @} */
95669 
95670 /*! @name USBSTS - USB Status Register */
95671 /*! @{ */
95672 #define USB_USBSTS_UI_MASK                       (0x1U)
95673 #define USB_USBSTS_UI_SHIFT                      (0U)
95674 #define USB_USBSTS_UI(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
95675 #define USB_USBSTS_UEI_MASK                      (0x2U)
95676 #define USB_USBSTS_UEI_SHIFT                     (1U)
95677 #define USB_USBSTS_UEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
95678 #define USB_USBSTS_PCI_MASK                      (0x4U)
95679 #define USB_USBSTS_PCI_SHIFT                     (2U)
95680 #define USB_USBSTS_PCI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
95681 #define USB_USBSTS_FRI_MASK                      (0x8U)
95682 #define USB_USBSTS_FRI_SHIFT                     (3U)
95683 #define USB_USBSTS_FRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
95684 #define USB_USBSTS_SEI_MASK                      (0x10U)
95685 #define USB_USBSTS_SEI_SHIFT                     (4U)
95686 #define USB_USBSTS_SEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
95687 #define USB_USBSTS_AAI_MASK                      (0x20U)
95688 #define USB_USBSTS_AAI_SHIFT                     (5U)
95689 #define USB_USBSTS_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
95690 #define USB_USBSTS_URI_MASK                      (0x40U)
95691 #define USB_USBSTS_URI_SHIFT                     (6U)
95692 #define USB_USBSTS_URI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
95693 #define USB_USBSTS_SRI_MASK                      (0x80U)
95694 #define USB_USBSTS_SRI_SHIFT                     (7U)
95695 #define USB_USBSTS_SRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
95696 #define USB_USBSTS_SLI_MASK                      (0x100U)
95697 #define USB_USBSTS_SLI_SHIFT                     (8U)
95698 #define USB_USBSTS_SLI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
95699 #define USB_USBSTS_ULPII_MASK                    (0x400U)
95700 #define USB_USBSTS_ULPII_SHIFT                   (10U)
95701 #define USB_USBSTS_ULPII(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
95702 #define USB_USBSTS_HCH_MASK                      (0x1000U)
95703 #define USB_USBSTS_HCH_SHIFT                     (12U)
95704 #define USB_USBSTS_HCH(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
95705 #define USB_USBSTS_RCL_MASK                      (0x2000U)
95706 #define USB_USBSTS_RCL_SHIFT                     (13U)
95707 #define USB_USBSTS_RCL(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
95708 #define USB_USBSTS_PS_MASK                       (0x4000U)
95709 #define USB_USBSTS_PS_SHIFT                      (14U)
95710 #define USB_USBSTS_PS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
95711 #define USB_USBSTS_AS_MASK                       (0x8000U)
95712 #define USB_USBSTS_AS_SHIFT                      (15U)
95713 #define USB_USBSTS_AS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
95714 #define USB_USBSTS_NAKI_MASK                     (0x10000U)
95715 #define USB_USBSTS_NAKI_SHIFT                    (16U)
95716 #define USB_USBSTS_NAKI(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
95717 #define USB_USBSTS_TI0_MASK                      (0x1000000U)
95718 #define USB_USBSTS_TI0_SHIFT                     (24U)
95719 #define USB_USBSTS_TI0(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
95720 #define USB_USBSTS_TI1_MASK                      (0x2000000U)
95721 #define USB_USBSTS_TI1_SHIFT                     (25U)
95722 #define USB_USBSTS_TI1(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
95723 /*! @} */
95724 
95725 /*! @name USBINTR - Interrupt Enable Register */
95726 /*! @{ */
95727 #define USB_USBINTR_UE_MASK                      (0x1U)
95728 #define USB_USBINTR_UE_SHIFT                     (0U)
95729 #define USB_USBINTR_UE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
95730 #define USB_USBINTR_UEE_MASK                     (0x2U)
95731 #define USB_USBINTR_UEE_SHIFT                    (1U)
95732 #define USB_USBINTR_UEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
95733 #define USB_USBINTR_PCE_MASK                     (0x4U)
95734 #define USB_USBINTR_PCE_SHIFT                    (2U)
95735 #define USB_USBINTR_PCE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
95736 #define USB_USBINTR_FRE_MASK                     (0x8U)
95737 #define USB_USBINTR_FRE_SHIFT                    (3U)
95738 #define USB_USBINTR_FRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
95739 #define USB_USBINTR_SEE_MASK                     (0x10U)
95740 #define USB_USBINTR_SEE_SHIFT                    (4U)
95741 #define USB_USBINTR_SEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
95742 #define USB_USBINTR_AAE_MASK                     (0x20U)
95743 #define USB_USBINTR_AAE_SHIFT                    (5U)
95744 #define USB_USBINTR_AAE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
95745 #define USB_USBINTR_URE_MASK                     (0x40U)
95746 #define USB_USBINTR_URE_SHIFT                    (6U)
95747 #define USB_USBINTR_URE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
95748 #define USB_USBINTR_SRE_MASK                     (0x80U)
95749 #define USB_USBINTR_SRE_SHIFT                    (7U)
95750 #define USB_USBINTR_SRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
95751 #define USB_USBINTR_SLE_MASK                     (0x100U)
95752 #define USB_USBINTR_SLE_SHIFT                    (8U)
95753 #define USB_USBINTR_SLE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
95754 #define USB_USBINTR_ULPIE_MASK                   (0x400U)
95755 #define USB_USBINTR_ULPIE_SHIFT                  (10U)
95756 #define USB_USBINTR_ULPIE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
95757 #define USB_USBINTR_NAKE_MASK                    (0x10000U)
95758 #define USB_USBINTR_NAKE_SHIFT                   (16U)
95759 #define USB_USBINTR_NAKE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
95760 #define USB_USBINTR_UAIE_MASK                    (0x40000U)
95761 #define USB_USBINTR_UAIE_SHIFT                   (18U)
95762 #define USB_USBINTR_UAIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
95763 #define USB_USBINTR_UPIE_MASK                    (0x80000U)
95764 #define USB_USBINTR_UPIE_SHIFT                   (19U)
95765 #define USB_USBINTR_UPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
95766 #define USB_USBINTR_TIE0_MASK                    (0x1000000U)
95767 #define USB_USBINTR_TIE0_SHIFT                   (24U)
95768 #define USB_USBINTR_TIE0(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
95769 #define USB_USBINTR_TIE1_MASK                    (0x2000000U)
95770 #define USB_USBINTR_TIE1_SHIFT                   (25U)
95771 #define USB_USBINTR_TIE1(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
95772 /*! @} */
95773 
95774 /*! @name FRINDEX - USB Frame Index */
95775 /*! @{ */
95776 #define USB_FRINDEX_FRINDEX_MASK                 (0x3FFFU)
95777 #define USB_FRINDEX_FRINDEX_SHIFT                (0U)
95778 /*! FRINDEX
95779  *  0b00000000000000..(1024) 12
95780  *  0b00000000000001..(512) 11
95781  *  0b00000000000010..(256) 10
95782  *  0b00000000000011..(128) 9
95783  *  0b00000000000100..(64) 8
95784  *  0b00000000000101..(32) 7
95785  *  0b00000000000110..(16) 6
95786  *  0b00000000000111..(8) 5
95787  */
95788 #define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
95789 /*! @} */
95790 
95791 /*! @name DEVICEADDR - Device Address */
95792 /*! @{ */
95793 #define USB_DEVICEADDR_USBADRA_MASK              (0x1000000U)
95794 #define USB_DEVICEADDR_USBADRA_SHIFT             (24U)
95795 #define USB_DEVICEADDR_USBADRA(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
95796 #define USB_DEVICEADDR_USBADR_MASK               (0xFE000000U)
95797 #define USB_DEVICEADDR_USBADR_SHIFT              (25U)
95798 #define USB_DEVICEADDR_USBADR(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
95799 /*! @} */
95800 
95801 /*! @name PERIODICLISTBASE - Frame List Base Address */
95802 /*! @{ */
95803 #define USB_PERIODICLISTBASE_BASEADR_MASK        (0xFFFFF000U)
95804 #define USB_PERIODICLISTBASE_BASEADR_SHIFT       (12U)
95805 #define USB_PERIODICLISTBASE_BASEADR(x)          (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
95806 /*! @} */
95807 
95808 /*! @name ASYNCLISTADDR - Next Asynch. Address */
95809 /*! @{ */
95810 #define USB_ASYNCLISTADDR_ASYBASE_MASK           (0xFFFFFFE0U)
95811 #define USB_ASYNCLISTADDR_ASYBASE_SHIFT          (5U)
95812 #define USB_ASYNCLISTADDR_ASYBASE(x)             (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
95813 /*! @} */
95814 
95815 /*! @name ENDPTLISTADDR - Endpoint List Address */
95816 /*! @{ */
95817 #define USB_ENDPTLISTADDR_EPBASE_MASK            (0xFFFFF800U)
95818 #define USB_ENDPTLISTADDR_EPBASE_SHIFT           (11U)
95819 #define USB_ENDPTLISTADDR_EPBASE(x)              (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
95820 /*! @} */
95821 
95822 /*! @name BURSTSIZE - Programmable Burst Size */
95823 /*! @{ */
95824 #define USB_BURSTSIZE_RXPBURST_MASK              (0xFFU)
95825 #define USB_BURSTSIZE_RXPBURST_SHIFT             (0U)
95826 #define USB_BURSTSIZE_RXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
95827 #define USB_BURSTSIZE_TXPBURST_MASK              (0x1FF00U)
95828 #define USB_BURSTSIZE_TXPBURST_SHIFT             (8U)
95829 #define USB_BURSTSIZE_TXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
95830 /*! @} */
95831 
95832 /*! @name TXFILLTUNING - TX FIFO Fill Tuning */
95833 /*! @{ */
95834 #define USB_TXFILLTUNING_TXSCHOH_MASK            (0xFFU)
95835 #define USB_TXFILLTUNING_TXSCHOH_SHIFT           (0U)
95836 #define USB_TXFILLTUNING_TXSCHOH(x)              (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
95837 #define USB_TXFILLTUNING_TXSCHHEALTH_MASK        (0x1F00U)
95838 #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT       (8U)
95839 #define USB_TXFILLTUNING_TXSCHHEALTH(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
95840 #define USB_TXFILLTUNING_TXFIFOTHRES_MASK        (0x3F0000U)
95841 #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT       (16U)
95842 #define USB_TXFILLTUNING_TXFIFOTHRES(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
95843 /*! @} */
95844 
95845 /*! @name ENDPTNAK - Endpoint NAK */
95846 /*! @{ */
95847 #define USB_ENDPTNAK_EPRN_MASK                   (0xFFU)
95848 #define USB_ENDPTNAK_EPRN_SHIFT                  (0U)
95849 #define USB_ENDPTNAK_EPRN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
95850 #define USB_ENDPTNAK_EPTN_MASK                   (0xFF0000U)
95851 #define USB_ENDPTNAK_EPTN_SHIFT                  (16U)
95852 #define USB_ENDPTNAK_EPTN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
95853 /*! @} */
95854 
95855 /*! @name ENDPTNAKEN - Endpoint NAK Enable */
95856 /*! @{ */
95857 #define USB_ENDPTNAKEN_EPRNE_MASK                (0xFFU)
95858 #define USB_ENDPTNAKEN_EPRNE_SHIFT               (0U)
95859 #define USB_ENDPTNAKEN_EPRNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
95860 #define USB_ENDPTNAKEN_EPTNE_MASK                (0xFF0000U)
95861 #define USB_ENDPTNAKEN_EPTNE_SHIFT               (16U)
95862 #define USB_ENDPTNAKEN_EPTNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
95863 /*! @} */
95864 
95865 /*! @name CONFIGFLAG - Configure Flag Register */
95866 /*! @{ */
95867 #define USB_CONFIGFLAG_CF_MASK                   (0x1U)
95868 #define USB_CONFIGFLAG_CF_SHIFT                  (0U)
95869 /*! CF
95870  *  0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
95871  *  0b1..Port routing control logic default-routes all ports to this host controller.
95872  */
95873 #define USB_CONFIGFLAG_CF(x)                     (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
95874 /*! @} */
95875 
95876 /*! @name PORTSC1 - Port Status & Control */
95877 /*! @{ */
95878 #define USB_PORTSC1_CCS_MASK                     (0x1U)
95879 #define USB_PORTSC1_CCS_SHIFT                    (0U)
95880 #define USB_PORTSC1_CCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
95881 #define USB_PORTSC1_CSC_MASK                     (0x2U)
95882 #define USB_PORTSC1_CSC_SHIFT                    (1U)
95883 #define USB_PORTSC1_CSC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
95884 #define USB_PORTSC1_PE_MASK                      (0x4U)
95885 #define USB_PORTSC1_PE_SHIFT                     (2U)
95886 #define USB_PORTSC1_PE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
95887 #define USB_PORTSC1_PEC_MASK                     (0x8U)
95888 #define USB_PORTSC1_PEC_SHIFT                    (3U)
95889 #define USB_PORTSC1_PEC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
95890 #define USB_PORTSC1_OCA_MASK                     (0x10U)
95891 #define USB_PORTSC1_OCA_SHIFT                    (4U)
95892 /*! OCA
95893  *  0b1..This port currently has an over-current condition
95894  *  0b0..This port does not have an over-current condition.
95895  */
95896 #define USB_PORTSC1_OCA(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
95897 #define USB_PORTSC1_OCC_MASK                     (0x20U)
95898 #define USB_PORTSC1_OCC_SHIFT                    (5U)
95899 #define USB_PORTSC1_OCC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
95900 #define USB_PORTSC1_FPR_MASK                     (0x40U)
95901 #define USB_PORTSC1_FPR_SHIFT                    (6U)
95902 #define USB_PORTSC1_FPR(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
95903 #define USB_PORTSC1_SUSP_MASK                    (0x80U)
95904 #define USB_PORTSC1_SUSP_SHIFT                   (7U)
95905 #define USB_PORTSC1_SUSP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
95906 #define USB_PORTSC1_PR_MASK                      (0x100U)
95907 #define USB_PORTSC1_PR_SHIFT                     (8U)
95908 #define USB_PORTSC1_PR(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
95909 #define USB_PORTSC1_HSP_MASK                     (0x200U)
95910 #define USB_PORTSC1_HSP_SHIFT                    (9U)
95911 #define USB_PORTSC1_HSP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
95912 #define USB_PORTSC1_LS_MASK                      (0xC00U)
95913 #define USB_PORTSC1_LS_SHIFT                     (10U)
95914 /*! LS
95915  *  0b00..SE0
95916  *  0b10..J-state
95917  *  0b01..K-state
95918  *  0b11..Undefined
95919  */
95920 #define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
95921 #define USB_PORTSC1_PP_MASK                      (0x1000U)
95922 #define USB_PORTSC1_PP_SHIFT                     (12U)
95923 #define USB_PORTSC1_PP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
95924 #define USB_PORTSC1_PO_MASK                      (0x2000U)
95925 #define USB_PORTSC1_PO_SHIFT                     (13U)
95926 #define USB_PORTSC1_PO(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
95927 #define USB_PORTSC1_PIC_MASK                     (0xC000U)
95928 #define USB_PORTSC1_PIC_SHIFT                    (14U)
95929 /*! PIC
95930  *  0b00..Port indicators are off
95931  *  0b01..Amber
95932  *  0b10..Green
95933  *  0b11..Undefined
95934  */
95935 #define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
95936 #define USB_PORTSC1_PTC_MASK                     (0xF0000U)
95937 #define USB_PORTSC1_PTC_SHIFT                    (16U)
95938 /*! PTC
95939  *  0b0000..TEST_MODE_DISABLE
95940  *  0b0001..J_STATE
95941  *  0b0010..K_STATE
95942  *  0b0011..SE0 (host) / NAK (device)
95943  *  0b0100..Packet
95944  *  0b0101..FORCE_ENABLE_HS
95945  *  0b0110..FORCE_ENABLE_FS
95946  *  0b0111..FORCE_ENABLE_LS
95947  */
95948 #define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
95949 #define USB_PORTSC1_WKCN_MASK                    (0x100000U)
95950 #define USB_PORTSC1_WKCN_SHIFT                   (20U)
95951 #define USB_PORTSC1_WKCN(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
95952 #define USB_PORTSC1_WKDC_MASK                    (0x200000U)
95953 #define USB_PORTSC1_WKDC_SHIFT                   (21U)
95954 #define USB_PORTSC1_WKDC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
95955 #define USB_PORTSC1_WKOC_MASK                    (0x400000U)
95956 #define USB_PORTSC1_WKOC_SHIFT                   (22U)
95957 #define USB_PORTSC1_WKOC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
95958 #define USB_PORTSC1_PHCD_MASK                    (0x800000U)
95959 #define USB_PORTSC1_PHCD_SHIFT                   (23U)
95960 /*! PHCD
95961  *  0b1..Disable PHY clock
95962  *  0b0..Enable PHY clock
95963  */
95964 #define USB_PORTSC1_PHCD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
95965 #define USB_PORTSC1_PFSC_MASK                    (0x1000000U)
95966 #define USB_PORTSC1_PFSC_SHIFT                   (24U)
95967 /*! PFSC
95968  *  0b1..Forced to full speed
95969  *  0b0..Normal operation
95970  */
95971 #define USB_PORTSC1_PFSC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
95972 #define USB_PORTSC1_PTS_2_MASK                   (0x2000000U)
95973 #define USB_PORTSC1_PTS_2_SHIFT                  (25U)
95974 #define USB_PORTSC1_PTS_2(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
95975 #define USB_PORTSC1_PSPD_MASK                    (0xC000000U)
95976 #define USB_PORTSC1_PSPD_SHIFT                   (26U)
95977 /*! PSPD
95978  *  0b00..Full Speed
95979  *  0b01..Low Speed
95980  *  0b10..High Speed
95981  *  0b11..Undefined
95982  */
95983 #define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
95984 #define USB_PORTSC1_PTW_MASK                     (0x10000000U)
95985 #define USB_PORTSC1_PTW_SHIFT                    (28U)
95986 /*! PTW
95987  *  0b0..Select the 8-bit UTMI interface [60MHz]
95988  *  0b1..Select the 16-bit UTMI interface [30MHz]
95989  */
95990 #define USB_PORTSC1_PTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
95991 #define USB_PORTSC1_STS_MASK                     (0x20000000U)
95992 #define USB_PORTSC1_STS_SHIFT                    (29U)
95993 #define USB_PORTSC1_STS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
95994 #define USB_PORTSC1_PTS_1_MASK                   (0xC0000000U)
95995 #define USB_PORTSC1_PTS_1_SHIFT                  (30U)
95996 #define USB_PORTSC1_PTS_1(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
95997 /*! @} */
95998 
95999 /*! @name OTGSC - On-The-Go Status & control */
96000 /*! @{ */
96001 #define USB_OTGSC_VD_MASK                        (0x1U)
96002 #define USB_OTGSC_VD_SHIFT                       (0U)
96003 #define USB_OTGSC_VD(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
96004 #define USB_OTGSC_VC_MASK                        (0x2U)
96005 #define USB_OTGSC_VC_SHIFT                       (1U)
96006 #define USB_OTGSC_VC(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
96007 #define USB_OTGSC_OT_MASK                        (0x8U)
96008 #define USB_OTGSC_OT_SHIFT                       (3U)
96009 #define USB_OTGSC_OT(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
96010 #define USB_OTGSC_DP_MASK                        (0x10U)
96011 #define USB_OTGSC_DP_SHIFT                       (4U)
96012 #define USB_OTGSC_DP(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
96013 #define USB_OTGSC_IDPU_MASK                      (0x20U)
96014 #define USB_OTGSC_IDPU_SHIFT                     (5U)
96015 #define USB_OTGSC_IDPU(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
96016 #define USB_OTGSC_ID_MASK                        (0x100U)
96017 #define USB_OTGSC_ID_SHIFT                       (8U)
96018 #define USB_OTGSC_ID(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
96019 #define USB_OTGSC_AVV_MASK                       (0x200U)
96020 #define USB_OTGSC_AVV_SHIFT                      (9U)
96021 #define USB_OTGSC_AVV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
96022 #define USB_OTGSC_ASV_MASK                       (0x400U)
96023 #define USB_OTGSC_ASV_SHIFT                      (10U)
96024 #define USB_OTGSC_ASV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
96025 #define USB_OTGSC_BSV_MASK                       (0x800U)
96026 #define USB_OTGSC_BSV_SHIFT                      (11U)
96027 #define USB_OTGSC_BSV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
96028 #define USB_OTGSC_BSE_MASK                       (0x1000U)
96029 #define USB_OTGSC_BSE_SHIFT                      (12U)
96030 #define USB_OTGSC_BSE(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
96031 #define USB_OTGSC_TOG_1MS_MASK                   (0x2000U)
96032 #define USB_OTGSC_TOG_1MS_SHIFT                  (13U)
96033 #define USB_OTGSC_TOG_1MS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
96034 #define USB_OTGSC_DPS_MASK                       (0x4000U)
96035 #define USB_OTGSC_DPS_SHIFT                      (14U)
96036 #define USB_OTGSC_DPS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
96037 #define USB_OTGSC_IDIS_MASK                      (0x10000U)
96038 #define USB_OTGSC_IDIS_SHIFT                     (16U)
96039 #define USB_OTGSC_IDIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
96040 #define USB_OTGSC_AVVIS_MASK                     (0x20000U)
96041 #define USB_OTGSC_AVVIS_SHIFT                    (17U)
96042 #define USB_OTGSC_AVVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
96043 #define USB_OTGSC_ASVIS_MASK                     (0x40000U)
96044 #define USB_OTGSC_ASVIS_SHIFT                    (18U)
96045 #define USB_OTGSC_ASVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
96046 #define USB_OTGSC_BSVIS_MASK                     (0x80000U)
96047 #define USB_OTGSC_BSVIS_SHIFT                    (19U)
96048 #define USB_OTGSC_BSVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
96049 #define USB_OTGSC_BSEIS_MASK                     (0x100000U)
96050 #define USB_OTGSC_BSEIS_SHIFT                    (20U)
96051 #define USB_OTGSC_BSEIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
96052 #define USB_OTGSC_STATUS_1MS_MASK                (0x200000U)
96053 #define USB_OTGSC_STATUS_1MS_SHIFT               (21U)
96054 #define USB_OTGSC_STATUS_1MS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
96055 #define USB_OTGSC_DPIS_MASK                      (0x400000U)
96056 #define USB_OTGSC_DPIS_SHIFT                     (22U)
96057 #define USB_OTGSC_DPIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
96058 #define USB_OTGSC_IDIE_MASK                      (0x1000000U)
96059 #define USB_OTGSC_IDIE_SHIFT                     (24U)
96060 #define USB_OTGSC_IDIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
96061 #define USB_OTGSC_AVVIE_MASK                     (0x2000000U)
96062 #define USB_OTGSC_AVVIE_SHIFT                    (25U)
96063 #define USB_OTGSC_AVVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
96064 #define USB_OTGSC_ASVIE_MASK                     (0x4000000U)
96065 #define USB_OTGSC_ASVIE_SHIFT                    (26U)
96066 #define USB_OTGSC_ASVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
96067 #define USB_OTGSC_BSVIE_MASK                     (0x8000000U)
96068 #define USB_OTGSC_BSVIE_SHIFT                    (27U)
96069 #define USB_OTGSC_BSVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
96070 #define USB_OTGSC_BSEIE_MASK                     (0x10000000U)
96071 #define USB_OTGSC_BSEIE_SHIFT                    (28U)
96072 #define USB_OTGSC_BSEIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
96073 #define USB_OTGSC_EN_1MS_MASK                    (0x20000000U)
96074 #define USB_OTGSC_EN_1MS_SHIFT                   (29U)
96075 #define USB_OTGSC_EN_1MS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
96076 #define USB_OTGSC_DPIE_MASK                      (0x40000000U)
96077 #define USB_OTGSC_DPIE_SHIFT                     (30U)
96078 #define USB_OTGSC_DPIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
96079 /*! @} */
96080 
96081 /*! @name USBMODE - USB Device Mode */
96082 /*! @{ */
96083 #define USB_USBMODE_CM_MASK                      (0x3U)
96084 #define USB_USBMODE_CM_SHIFT                     (0U)
96085 /*! CM
96086  *  0b00..Idle [Default for combination host/device]
96087  *  0b01..Reserved
96088  *  0b10..Device Controller [Default for device only controller]
96089  *  0b11..Host Controller [Default for host only controller]
96090  */
96091 #define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
96092 #define USB_USBMODE_ES_MASK                      (0x4U)
96093 #define USB_USBMODE_ES_SHIFT                     (2U)
96094 /*! ES
96095  *  0b0..Little Endian [Default]
96096  *  0b1..Big Endian
96097  */
96098 #define USB_USBMODE_ES(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
96099 #define USB_USBMODE_SLOM_MASK                    (0x8U)
96100 #define USB_USBMODE_SLOM_SHIFT                   (3U)
96101 /*! SLOM
96102  *  0b0..Setup Lockouts On (default);
96103  *  0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register .
96104  */
96105 #define USB_USBMODE_SLOM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
96106 #define USB_USBMODE_SDIS_MASK                    (0x10U)
96107 #define USB_USBMODE_SDIS_SHIFT                   (4U)
96108 #define USB_USBMODE_SDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
96109 /*! @} */
96110 
96111 /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
96112 /*! @{ */
96113 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   (0xFFFFU)
96114 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT  (0U)
96115 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
96116 /*! @} */
96117 
96118 /*! @name ENDPTPRIME - Endpoint Prime */
96119 /*! @{ */
96120 #define USB_ENDPTPRIME_PERB_MASK                 (0xFFU)
96121 #define USB_ENDPTPRIME_PERB_SHIFT                (0U)
96122 #define USB_ENDPTPRIME_PERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
96123 #define USB_ENDPTPRIME_PETB_MASK                 (0xFF0000U)
96124 #define USB_ENDPTPRIME_PETB_SHIFT                (16U)
96125 #define USB_ENDPTPRIME_PETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
96126 /*! @} */
96127 
96128 /*! @name ENDPTFLUSH - Endpoint Flush */
96129 /*! @{ */
96130 #define USB_ENDPTFLUSH_FERB_MASK                 (0xFFU)
96131 #define USB_ENDPTFLUSH_FERB_SHIFT                (0U)
96132 #define USB_ENDPTFLUSH_FERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
96133 #define USB_ENDPTFLUSH_FETB_MASK                 (0xFF0000U)
96134 #define USB_ENDPTFLUSH_FETB_SHIFT                (16U)
96135 #define USB_ENDPTFLUSH_FETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
96136 /*! @} */
96137 
96138 /*! @name ENDPTSTAT - Endpoint Status */
96139 /*! @{ */
96140 #define USB_ENDPTSTAT_ERBR_MASK                  (0xFFU)
96141 #define USB_ENDPTSTAT_ERBR_SHIFT                 (0U)
96142 #define USB_ENDPTSTAT_ERBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
96143 #define USB_ENDPTSTAT_ETBR_MASK                  (0xFF0000U)
96144 #define USB_ENDPTSTAT_ETBR_SHIFT                 (16U)
96145 #define USB_ENDPTSTAT_ETBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
96146 /*! @} */
96147 
96148 /*! @name ENDPTCOMPLETE - Endpoint Complete */
96149 /*! @{ */
96150 #define USB_ENDPTCOMPLETE_ERCE_MASK              (0xFFU)
96151 #define USB_ENDPTCOMPLETE_ERCE_SHIFT             (0U)
96152 #define USB_ENDPTCOMPLETE_ERCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
96153 #define USB_ENDPTCOMPLETE_ETCE_MASK              (0xFF0000U)
96154 #define USB_ENDPTCOMPLETE_ETCE_SHIFT             (16U)
96155 #define USB_ENDPTCOMPLETE_ETCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
96156 /*! @} */
96157 
96158 /*! @name ENDPTCTRL0 - Endpoint Control0 */
96159 /*! @{ */
96160 #define USB_ENDPTCTRL0_RXS_MASK                  (0x1U)
96161 #define USB_ENDPTCTRL0_RXS_SHIFT                 (0U)
96162 #define USB_ENDPTCTRL0_RXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
96163 #define USB_ENDPTCTRL0_RXT_MASK                  (0xCU)
96164 #define USB_ENDPTCTRL0_RXT_SHIFT                 (2U)
96165 #define USB_ENDPTCTRL0_RXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
96166 #define USB_ENDPTCTRL0_RXE_MASK                  (0x80U)
96167 #define USB_ENDPTCTRL0_RXE_SHIFT                 (7U)
96168 #define USB_ENDPTCTRL0_RXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
96169 #define USB_ENDPTCTRL0_TXS_MASK                  (0x10000U)
96170 #define USB_ENDPTCTRL0_TXS_SHIFT                 (16U)
96171 #define USB_ENDPTCTRL0_TXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
96172 #define USB_ENDPTCTRL0_TXT_MASK                  (0xC0000U)
96173 #define USB_ENDPTCTRL0_TXT_SHIFT                 (18U)
96174 #define USB_ENDPTCTRL0_TXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
96175 #define USB_ENDPTCTRL0_TXE_MASK                  (0x800000U)
96176 #define USB_ENDPTCTRL0_TXE_SHIFT                 (23U)
96177 #define USB_ENDPTCTRL0_TXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
96178 /*! @} */
96179 
96180 /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
96181 /*! @{ */
96182 #define USB_ENDPTCTRL_RXS_MASK                   (0x1U)
96183 #define USB_ENDPTCTRL_RXS_SHIFT                  (0U)
96184 #define USB_ENDPTCTRL_RXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
96185 #define USB_ENDPTCTRL_RXD_MASK                   (0x2U)
96186 #define USB_ENDPTCTRL_RXD_SHIFT                  (1U)
96187 #define USB_ENDPTCTRL_RXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
96188 #define USB_ENDPTCTRL_RXT_MASK                   (0xCU)
96189 #define USB_ENDPTCTRL_RXT_SHIFT                  (2U)
96190 #define USB_ENDPTCTRL_RXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
96191 #define USB_ENDPTCTRL_RXI_MASK                   (0x20U)
96192 #define USB_ENDPTCTRL_RXI_SHIFT                  (5U)
96193 #define USB_ENDPTCTRL_RXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
96194 #define USB_ENDPTCTRL_RXR_MASK                   (0x40U)
96195 #define USB_ENDPTCTRL_RXR_SHIFT                  (6U)
96196 #define USB_ENDPTCTRL_RXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
96197 #define USB_ENDPTCTRL_RXE_MASK                   (0x80U)
96198 #define USB_ENDPTCTRL_RXE_SHIFT                  (7U)
96199 #define USB_ENDPTCTRL_RXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
96200 #define USB_ENDPTCTRL_TXS_MASK                   (0x10000U)
96201 #define USB_ENDPTCTRL_TXS_SHIFT                  (16U)
96202 #define USB_ENDPTCTRL_TXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
96203 #define USB_ENDPTCTRL_TXD_MASK                   (0x20000U)
96204 #define USB_ENDPTCTRL_TXD_SHIFT                  (17U)
96205 #define USB_ENDPTCTRL_TXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
96206 #define USB_ENDPTCTRL_TXT_MASK                   (0xC0000U)
96207 #define USB_ENDPTCTRL_TXT_SHIFT                  (18U)
96208 #define USB_ENDPTCTRL_TXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
96209 #define USB_ENDPTCTRL_TXI_MASK                   (0x200000U)
96210 #define USB_ENDPTCTRL_TXI_SHIFT                  (21U)
96211 #define USB_ENDPTCTRL_TXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
96212 #define USB_ENDPTCTRL_TXR_MASK                   (0x400000U)
96213 #define USB_ENDPTCTRL_TXR_SHIFT                  (22U)
96214 #define USB_ENDPTCTRL_TXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
96215 #define USB_ENDPTCTRL_TXE_MASK                   (0x800000U)
96216 #define USB_ENDPTCTRL_TXE_SHIFT                  (23U)
96217 #define USB_ENDPTCTRL_TXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
96218 /*! @} */
96219 
96220 /* The count of USB_ENDPTCTRL */
96221 #define USB_ENDPTCTRL_COUNT                      (7U)
96222 
96223 
96224 /*!
96225  * @}
96226  */ /* end of group USB_Register_Masks */
96227 
96228 
96229 /* USB - Peripheral instance base addresses */
96230 /** Peripheral CONNECTIVITY__USB2 base address */
96231 #define CONNECTIVITY__USB2_BASE                  (0x5B0D0000u)
96232 /** Peripheral CONNECTIVITY__USB2 base pointer */
96233 #define CONNECTIVITY__USB2                       ((USB_Type *)CONNECTIVITY__USB2_BASE)
96234 /** Array initializer of USB peripheral base addresses */
96235 #define USB_BASE_ADDRS                           { CONNECTIVITY__USB2_BASE }
96236 /** Array initializer of USB peripheral base pointers */
96237 #define USB_BASE_PTRS                            { CONNECTIVITY__USB2 }
96238 
96239 /*!
96240  * @}
96241  */ /* end of group USB_Peripheral_Access_Layer */
96242 
96243 
96244 /* ----------------------------------------------------------------------------
96245    -- USB3 Peripheral Access Layer
96246    ---------------------------------------------------------------------------- */
96247 
96248 /*!
96249  * @addtogroup USB3_Peripheral_Access_Layer USB3 Peripheral Access Layer
96250  * @{
96251  */
96252 
96253 /** USB3 - Register Layout Typedef */
96254 typedef struct {
96255   __IO uint32_t CORE_CTRL11;                       /**< Core Control, offset: 0x0 */
96256        uint32_t CORE_CTRL12;                       /**< Core Control, offset: 0x4 */
96257   __IO uint32_t INT;                               /**< Interrupt, offset: 0x8 */
96258   __I  uint32_t CORE_STATUS;                       /**< Core Status, offset: 0xC */
96259        uint32_t RESERVED;                          /**< RESERVED, offset: 0x10 */
96260        uint8_t RESERVED_0[65516];
96261   __O  uint32_t OTGCMD;                            /**< OTG Command, offset: 0x10000 */
96262   __I  uint32_t OTGSTS;                            /**< OTG Status, offset: 0x10004 */
96263   __I  uint32_t OTGSTATE;                          /**< OTG State, offset: 0x10008 */
96264   __IO uint32_t OTGREFCLK;                         /**< OTG Reference Clock, offset: 0x1000C */
96265   __IO uint32_t OTGIEN;                            /**< OTG Interrupt Enable, offset: 0x10010 */
96266   __IO uint32_t OTGIVECT;                          /**< OTG Interrupt Vector, offset: 0x10014 */
96267        uint8_t RESERVED_1[8];
96268   __IO uint32_t CLK_FREQ;                          /**< Clock Frequency, offset: 0x10020 */
96269   __O  uint32_t OTGTMR;                            /**< OTG Timer, offset: 0x10024 */
96270        uint8_t RESERVED_2[8];
96271   __I  uint32_t OTGVERSION;                        /**< OTG Version, offset: 0x10030 */
96272   __I  uint32_t OTGCAPABILITY;                     /**< OTG Capability, offset: 0x10034 */
96273        uint8_t RESERVED_3[8];
96274   __IO uint32_t OTGSIMULATE;                       /**< OTG Simulate, offset: 0x10040 */
96275        uint8_t RESERVED_4[12];
96276   __I  uint32_t OTGANASTS;                         /**< OTG Attach Detection Protocol BC Status, offset: 0x10050 */
96277   __I  uint32_t ADP_RAMP_TIME;                     /**< Attach Detection Protocol Ramp Time, offset: 0x10054 */
96278   __IO uint32_t OTGCTRL1;                          /**< OTG Control, offset: 0x10058 */
96279   __IO uint32_t OTGCTRL2;                          /**< OTG Control, offset: 0x1005C */
96280        uint8_t RESERVED_5[65440];
96281   __I  uint32_t HCIVERSION_CAPLENGTH;              /**< HCI Version and CAPLENGTH, offset: 0x20000 */
96282   __I  uint32_t HCSPARAMS1;                        /**< Structural Parameters 1, offset: 0x20004 */
96283   __I  uint32_t HCSPARAMS2;                        /**< Structural Parameters 2, offset: 0x20008 */
96284   __I  uint32_t HCSPARAMS3;                        /**< Structural Parameters 3, offset: 0x2000C */
96285   __I  uint32_t HCCPARAMS;                         /**< Capability Parameters, offset: 0x20010 */
96286   __I  uint32_t DBOFF;                             /**< DoorBell Array Offset, offset: 0x20014 */
96287   __I  uint32_t RTSOFF;                            /**< xHCI Runtime Registers Offset, offset: 0x20018 */
96288        uint8_t RESERVED_6[100];
96289   __IO uint32_t USBCMD;                            /**< USB Command, offset: 0x20080 */
96290   __IO uint32_t USBSTS;                            /**< USB Status, offset: 0x20084 */
96291   __I  uint32_t PAGESIZE;                          /**< Page Size, offset: 0x20088 */
96292        uint8_t RESERVED_7[8];
96293   __IO uint32_t DNCTRL;                            /**< Device Notification Control, offset: 0x20094 */
96294   __IO uint32_t CRCR_LO;                           /**< Command Ring Control Register Low, offset: 0x20098 */
96295   __IO uint32_t CRCR_HI;                           /**< Command Ring Control Register High, offset: 0x2009C */
96296        uint8_t RESERVED_8[16];
96297   __IO uint32_t DCBAAP_LO;                         /**< Device Context Base Address Array Pointer(LOW), offset: 0x200B0 */
96298   __IO uint32_t DCBAAP_HI;                         /**< Device Context Base Address Array Pointer (HIGH), offset: 0x200B4 */
96299   __IO uint32_t CONFIG;                            /**< Configure, offset: 0x200B8 */
96300        uint8_t RESERVED_9[964];
96301   __IO uint32_t PORTSC1USB2;                       /**< USB2 Port Status and Control, offset: 0x20480 */
96302   __IO uint32_t PORTPMSC1USB2;                     /**< USB2 Port Power Management Status and Control, offset: 0x20484 */
96303        uint8_t RESERVED_10[4];
96304   __IO uint32_t PORT1HLPMC;                        /**< USB2 Port Hardware LPM Control register, offset: 0x2048C */
96305   __IO uint32_t PORTSC1USB3;                       /**< USB3 Port Status and Control, offset: 0x20490 */
96306   __IO uint32_t PORTPMSC1USB3;                     /**< USB3 Port Power Management Status and Control, offset: 0x20494 */
96307   __I  uint32_t PORTLI1;                           /**< USB3 Port Link Info, offset: 0x20498 */
96308        uint8_t RESERVED_11[7012];
96309   __I  uint32_t MFINDEX;                           /**< MicroFrame Index, offset: 0x22000 */
96310        uint8_t RESERVED_12[28];
96311   __IO uint32_t IMAN0;                             /**< Interrupter Management, offset: 0x22020 */
96312   __IO uint32_t IMOD0;                             /**< Interrupter Moderation, offset: 0x22024 */
96313   __IO uint32_t ERSTSZ0;                           /**< Event Ring Segment Table Size, offset: 0x22028 */
96314        uint32_t RSVD0;                             /**< Reserved, offset: 0x2202C */
96315   __IO uint32_t ERSTBA0_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x22030 */
96316   __IO uint32_t ERSTBA00_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22034 */
96317   __IO uint32_t ERDP0_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x22038 */
96318   __IO uint32_t ERDP0_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2203C */
96319   __IO uint32_t IMAN1;                             /**< Interrupter Management, offset: 0x22040 */
96320   __IO uint32_t IMOD1;                             /**< Interrupter Moderation, offset: 0x22044 */
96321   __IO uint32_t ERSTSZ1;                           /**< Event Ring Segment Table Size, offset: 0x22048 */
96322        uint32_t RSVD1;                             /**< Reserved, offset: 0x2204C */
96323   __IO uint32_t ERSTBA1_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x22050 */
96324   __IO uint32_t ERSTBA01_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22054 */
96325   __IO uint32_t ERDP1_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x22058 */
96326   __IO uint32_t ERDP1_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2205C */
96327   __IO uint32_t IMAN2;                             /**< Interrupter Management, offset: 0x22060 */
96328   __IO uint32_t IMOD2;                             /**< Interrupter Moderation, offset: 0x22064 */
96329   __IO uint32_t ERSTSZ2;                           /**< Event Ring Segment Table Size, offset: 0x22068 */
96330        uint32_t RSVD2;                             /**< Reserved, offset: 0x2206C */
96331   __IO uint32_t ERSTBA2_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x22070 */
96332   __IO uint32_t ERSTBA02_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22074 */
96333   __IO uint32_t ERDP2_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x22078 */
96334   __IO uint32_t ERDP2_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2207C */
96335   __IO uint32_t IMAN3;                             /**< Interrupter Management, offset: 0x22080 */
96336   __IO uint32_t IMOD3;                             /**< Interrupter Moderation, offset: 0x22084 */
96337   __IO uint32_t ERSTSZ3;                           /**< Event Ring Segment Table Size, offset: 0x22088 */
96338        uint32_t RSVD3;                             /**< Reserved, offset: 0x2208C */
96339   __IO uint32_t ERSTBA3_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x22090 */
96340   __IO uint32_t ERSTBA03_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22094 */
96341   __IO uint32_t ERDP3_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x22098 */
96342   __IO uint32_t ERDP3_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2209C */
96343   __IO uint32_t IMAN4;                             /**< Interrupter Management, offset: 0x220A0 */
96344   __IO uint32_t IMOD4;                             /**< Interrupter Moderation, offset: 0x220A4 */
96345   __IO uint32_t ERSTSZ4;                           /**< Event Ring Segment Table Size, offset: 0x220A8 */
96346        uint32_t RSVD4;                             /**< Reserved, offset: 0x220AC */
96347   __IO uint32_t ERSTBA4_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x220B0 */
96348   __IO uint32_t ERSTBA04_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x220B4 */
96349   __IO uint32_t ERDP4_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x220B8 */
96350   __IO uint32_t ERDP4_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x220BC */
96351   __IO uint32_t IMAN5;                             /**< Interrupter Management, offset: 0x220C0 */
96352   __IO uint32_t IMOD5;                             /**< Interrupter Moderation, offset: 0x220C4 */
96353   __IO uint32_t ERSTSZ5;                           /**< Event Ring Segment Table Size, offset: 0x220C8 */
96354        uint32_t RSVD5;                             /**< Reserved, offset: 0x220CC */
96355   __IO uint32_t ERSTBA5_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x220D0 */
96356   __IO uint32_t ERSTBA05_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x220D4 */
96357   __IO uint32_t ERDP5_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x220D8 */
96358   __IO uint32_t ERDP5_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x220DC */
96359   __IO uint32_t IMAN6;                             /**< Interrupter Management, offset: 0x220E0 */
96360   __IO uint32_t IMOD6;                             /**< Interrupter Moderation, offset: 0x220E4 */
96361   __IO uint32_t ERSTSZ6;                           /**< Event Ring Segment Table Size, offset: 0x220E8 */
96362        uint32_t RSVD6;                             /**< Reserved, offset: 0x220EC */
96363   __IO uint32_t ERSTBA6_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x220F0 */
96364   __IO uint32_t ERSTBA06_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x220F4 */
96365   __IO uint32_t ERDP6_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x220F8 */
96366   __IO uint32_t ERDP6_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x220FC */
96367   __IO uint32_t IMAN7;                             /**< Interrupter Management, offset: 0x22100 */
96368   __IO uint32_t IMOD7;                             /**< Interrupter Moderation, offset: 0x22104 */
96369   __IO uint32_t ERSTSZ7;                           /**< Event Ring Segment Table Size, offset: 0x22108 */
96370        uint32_t RSVD7;                             /**< Reserved, offset: 0x2210C */
96371   __IO uint32_t ERSTBA7_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x22110 */
96372   __IO uint32_t ERSTBA07_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22114 */
96373   __IO uint32_t ERDP7_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x22118 */
96374   __IO uint32_t ERDP7_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2211C */
96375        uint8_t RESERVED_13[3808];
96376   __IO uint32_t DB0;                               /**< Host Controller Doorbell, offset: 0x23000 */
96377   __IO uint32_t DB1;                               /**< Doorbell Array, offset: 0x23004 */
96378   __IO uint32_t DB2;                               /**< Doorbell Array, offset: 0x23008 */
96379   __IO uint32_t DB3;                               /**< Doorbell Array, offset: 0x2300C */
96380   __IO uint32_t DB4;                               /**< Doorbell Array, offset: 0x23010 */
96381   __IO uint32_t DB5;                               /**< Doorbell Array, offset: 0x23014 */
96382   __IO uint32_t DB6;                               /**< Doorbell Array, offset: 0x23018 */
96383   __IO uint32_t DB7;                               /**< Doorbell Array, offset: 0x2301C */
96384   __IO uint32_t DB8;                               /**< Doorbell Array, offset: 0x23020 */
96385   __IO uint32_t DB9;                               /**< Doorbell Array, offset: 0x23024 */
96386   __IO uint32_t DB10;                              /**< Doorbell Array, offset: 0x23028 */
96387   __IO uint32_t DB11;                              /**< Doorbell Array, offset: 0x2302C */
96388   __IO uint32_t DB12;                              /**< Doorbell Array, offset: 0x23030 */
96389   __IO uint32_t DB13;                              /**< Doorbell Array, offset: 0x23034 */
96390   __IO uint32_t DB14;                              /**< Doorbell Array, offset: 0x23038 */
96391   __IO uint32_t DB15;                              /**< Doorbell Array, offset: 0x2303C */
96392   __IO uint32_t DB16;                              /**< Doorbell Array, offset: 0x23040 */
96393   __IO uint32_t DB17;                              /**< Doorbell Array, offset: 0x23044 */
96394   __IO uint32_t DB18;                              /**< Doorbell Array, offset: 0x23048 */
96395   __IO uint32_t DB19;                              /**< Doorbell Array, offset: 0x2304C */
96396   __IO uint32_t DB20;                              /**< Doorbell Array, offset: 0x23050 */
96397   __IO uint32_t DB21;                              /**< Doorbell Array, offset: 0x23054 */
96398   __IO uint32_t DB22;                              /**< Doorbell Array, offset: 0x23058 */
96399   __IO uint32_t DB23;                              /**< Doorbell Array, offset: 0x2305C */
96400   __IO uint32_t DB24;                              /**< Doorbell Array, offset: 0x23060 */
96401   __IO uint32_t DB25;                              /**< Doorbell Array, offset: 0x23064 */
96402   __IO uint32_t DB26;                              /**< Doorbell Array, offset: 0x23068 */
96403   __IO uint32_t DB27;                              /**< Doorbell Array, offset: 0x2306C */
96404   __IO uint32_t DB28;                              /**< Doorbell Array, offset: 0x23070 */
96405   __IO uint32_t DB29;                              /**< Doorbell Array, offset: 0x23074 */
96406   __IO uint32_t DB30;                              /**< Doorbell Array, offset: 0x23078 */
96407   __IO uint32_t DB31;                              /**< Doorbell Array, offset: 0x2307C */
96408   __IO uint32_t DB32;                              /**< Doorbell Array, offset: 0x23080 */
96409        uint8_t RESERVED_14[20348];
96410   __IO uint32_t XECP_PORT_CAP_REG;                 /**< USB3 Extended capability, offset: 0x28000 */
96411   __IO uint32_t XECP_PORT_1_REG;                   /**< USB3 Extended capability, offset: 0x28004 */
96412   __IO uint32_t XECP_CDNS_DEBUG_BUS_CAP;           /**< xHCI Debug Bus Capability, offset: 0x28008 */
96413   __IO uint32_t XECP_CDNS_DEBUG_BUS_CTRL;          /**< xHCI Debug Bus Control, offset: 0x2800C */
96414   __I  uint32_t XECP_CDNS_DEBUG_BUS_STATUS;        /**< xHCI Debug Bus Status, offset: 0x28010 */
96415   __IO uint32_t XECP_PM_CAP;                       /**< Extended Power Management capability, offset: 0x28014 */
96416   __IO uint32_t XECP_PM_PMCSR;                     /**< Extended Power Management Control/Status, offset: 0x28018 */
96417   __IO uint32_t XECP_MSI_CAP;                      /**< MSI configuration, offset: 0x2801C */
96418   __IO uint32_t XECP_MSI_ADDR_L;                   /**< Message Lower Address, offset: 0x28020 */
96419   __IO uint32_t XECP_MSI_ADDR_H;                   /**< Message Upper Address, offset: 0x28024 */
96420   __IO uint32_t XECP_MSI_DATA;                     /**< Message data, offset: 0x28028 */
96421   __IO uint32_t XECP_AXI_CAP;                      /**< AXI Master Wrapper Extended Capability, offset: 0x2802C */
96422   __I  uint32_t XECP_AXI_CFG0;                     /**< AXI Master Wrapper Extended Capability Configuration, offset: 0x28030 */
96423   __IO uint32_t XECP_AXI_CTRL0;                    /**< AXI Master Wrapper Extended Capability Control, offset: 0x28034 */
96424   __IO uint32_t XECP_AXI_CTRL1;                    /**< AXI Master Wrapper Extended Capability Control, offset: 0x28038 */
96425   __IO uint32_t XECP_AXI_CTRL2;                    /**< AXI Master Wrapper Extended Capability Control, offset: 0x2803C */
96426   __I  uint32_t XECP_SUPP_USB2_CAP0;               /**< xHCI Supported Protocol Capability, offset: 0x28040 */
96427   __I  uint32_t XECP_SUPP_USB2_CAP1;               /**< xHCI Supported Protocol Capability, offset: 0x28044 */
96428   __I  uint32_t XECP_SUPP_USB2_CAP2;               /**< xHCI Supported Protocol Capability, offset: 0x28048 */
96429   __I  uint32_t XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE; /**< Protocol Slot Type, offset: 0x2804C */
96430   __I  uint32_t XECP_PSI_FULL_SPEED;               /**< Protocol Speed ID, offset: 0x28050 */
96431   __I  uint32_t XECP_PSI_LOW_SPEED;                /**< Protocol Speed ID, offset: 0x28054 */
96432   __I  uint32_t XECP_PSI_HIGH_SPEED;               /**< Protocol Speed ID, offset: 0x28058 */
96433        uint8_t RESERVED_15[4];
96434   __I  uint32_t XECP_SUPP_USB3_CAP0;               /**< xHCI Supported Protocol Capability, offset: 0x28060 */
96435   __I  uint32_t XECP_SUPP_USB3_CAP1;               /**< xHCI Supported Protocol Capability, offset: 0x28064 */
96436   __I  uint32_t XECP_SUPP_USB3_CAP2;               /**< xHCI Supported Protocol Capability; USB 3, offset: 0x28068 */
96437   __I  uint32_t XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE; /**< Protocol Slot Type, offset: 0x2806C */
96438   __I  uint32_t PSI_SUPER_SPEED;                   /**< Protocol Speed ID, offset: 0x28070 */
96439        uint8_t RESERVED_16[12];
96440   __I  uint32_t XECP_CMDM_STS0;                    /**< Command Ring related status, offset: 0x28080 */
96441        uint32_t RSVD01;                            /**< Reserved, offset: 0x28084 */
96442        uint32_t RSVD02;                            /**< Reserved, offset: 0x28088 */
96443        uint32_t RSVD03;                            /**< Reserved, offset: 0x2808C */
96444        uint32_t RSVD04;                            /**< Reserved, offset: 0x28090 */
96445        uint32_t RSVD05;                            /**< Reserved, offset: 0x28094 */
96446   __IO uint32_t XECP_CMDM_CTRL_REG1;               /**< Command Manager Control, offset: 0x28098 */
96447   __IO uint32_t XECP_CMDM_CTRL_REG2;               /**< Command Manager Control, offset: 0x2809C */
96448   __IO uint32_t XECP_CMDM_CTRL_REG3;               /**< Command Manager Control, offset: 0x280A0 */
96449        uint8_t RESERVED_17[12];
96450   __I  uint32_t XECP_HOST_CTRL_CAP;                /**< Host Control Capability, offset: 0x280B0 */
96451        uint32_t XECP_HOST_CTRL_RSVD;               /**< Reserved, offset: 0x280B4 */
96452   __O  uint32_t XECP_HOST_CLR_MASK_REG;            /**< Override Endpoint Flow Control, offset: 0x280B8 */
96453   __O  uint32_t XECP_HOST_CLR_IN_EP_VALID_REG;     /**< Clear Active IN EP ID Control, offset: 0x280BC */
96454   __O  uint32_t XECP_HOST_CLR_PMASK_REG;           /**< Clear Poll Mask Control, offset: 0x280C0 */
96455   __IO uint32_t XECP_HOST_CTRL_OCRD_REG;           /**< Port Credit Control, offset: 0x280C4 */
96456   __I  uint32_t XECP_HOST_CTRL_TEST_BUS_LO;        /**< Test Bus Low, offset: 0x280C8 */
96457   __I  uint32_t XECP_HOST_CTRL_TEST_BUS_HI;        /**< Test Bus High, offset: 0x280CC */
96458   __IO uint32_t XECP_HOST_CTRL_TRM_REG1;           /**< Host Control Transfer Manager, offset: 0x280D0 */
96459   __IO uint32_t XECP_HOST_CTRL_SCH_REG1;           /**< Host Control Scheduler, offset: 0x280D4 */
96460   __IO uint32_t XECP_HOST_CTRL_ODMA_REG;           /**< Host Control ODMA, offset: 0x280D8 */
96461   __IO uint32_t XECP_HOST_CTRL_IDMA_REG;           /**< Host Control IDMA, offset: 0x280DC */
96462   __IO uint32_t XECP_HOST_CTRL_PORT_CTRL;          /**< Global Port Control, offset: 0x280E0 */
96463        uint8_t RESERVED_18[28];
96464   __IO uint32_t XECP_AUX_CTRL_REG;                 /**< AUX Reset Control, offset: 0x28100 */
96465   __IO uint32_t XECP_HOST_BW_OV_SS_REG;            /**< Super Speed Bandwidth Overload, offset: 0x28104 */
96466   __IO uint32_t XECP_HOST_BW_OV_HS_REG;            /**< High Speed TT Bandwidth Overload, offset: 0x28108 */
96467   __IO uint32_t XECP_HOST_BW_OV_FS_LS_REG;         /**< Bandwidth Overload Full and Low Speed, offset: 0x2810C */
96468   __IO uint32_t XECP_HOST_BW_OV_SYS_REG;           /**< System Bandwidth Overload, offset: 0x28110 */
96469   __IO uint32_t XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG; /**< Scheduler Async Delay, offset: 0x28114 */
96470   __O  uint32_t XECP_UPORTS_PON_RST_REG;           /**< AUX Power PHY Reset, offset: 0x28118 */
96471   __IO uint32_t XECP_HOST_CTRL_TRM_REG3;           /**< Host Control Transfer Manager (TRM), offset: 0x2811C */
96472   __IO uint32_t XECP_AUX_CTRL_REG1;                /**< AUX Power Management Control 1, offset: 0x28120 */
96473        uint8_t RESERVED_19[4];
96474   __IO uint32_t XECP_HOST_CTRL_WATERMARK_REG;      /**< Port Watermark, offset: 0x28128 */
96475   __IO uint32_t XECP_HOST_CTRL_PORT_LINK_REG;      /**< SuperSpeed Port Link Control, offset: 0x2812C */
96476   __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG1;      /**< USB2 Port Link Control, offset: 0x28130 */
96477   __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG2;      /**< USB2 Port Link Control, offset: 0x28134 */
96478   __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG3;      /**< USB2 Port Link Control, offset: 0x28138 */
96479   __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG4;      /**< USB2 Port Link Control, offset: 0x2813C */
96480   __IO uint32_t XECP_HOST_CTRL_BW_MAX_REG;         /**< USB2 Max Bandwidth Control, offset: 0x28140 */
96481   __I  uint32_t XECP_FPGA_REVISION_REG;            /**< FPGA_REVISION_REG, offset: 0x28144 */
96482   __IO uint32_t XECP_HOST_INTF_CTRL_REG;           /**< Host interface control, offset: 0x28148 */
96483        uint8_t RESERVED_20[548];
96484   __IO uint32_t XECP_USBLEGSUP;                    /**< USB Legacy Support Capability, offset: 0x28370 */
96485   __IO uint32_t XECP_USBLEGCTLSTS;                 /**< USB Legacy Support Control Status, offset: 0x28374 */
96486        uint8_t RESERVED_21[8];
96487   __I  uint32_t XECP_DCID;                         /**< Debug Capability ID, offset: 0x28380 */
96488   __IO uint32_t XECP_DCDB;                         /**< Debug Capability Doorbell, offset: 0x28384 */
96489   __IO uint32_t XECP_DCERSTSZ;                     /**< Debug Capability Event Ring Segment Table Size, offset: 0x28388 */
96490        uint32_t XECP_RSVD_0C;                      /**< Reserved, offset: 0x2838C */
96491   __IO uint32_t XECP_DCERSTBA_LOW;                 /**< Debug Capability Event Ring Segment Table Base Address, offset: 0x28390 */
96492   __IO uint32_t XECP_DCERSTBA_HIGH;                /**< Debug Capability Event Ring Segment Table Base Address, offset: 0x28394 */
96493   __IO uint32_t XECP_DCERDP_LOW;                   /**< Debug Capability Event Ring Dequeue Pointer, offset: 0x28398 */
96494   __IO uint32_t XECP_DCERDP_HIGH;                  /**< Debug Capability Event Ring Dequeue Pointer, offset: 0x2839C */
96495   __IO uint32_t XECP_DCCTRL;                       /**< Debug Capability Control, offset: 0x283A0 */
96496   __I  uint32_t XECP_DCST;                         /**< Debug Capability Status, offset: 0x283A4 */
96497   __IO uint32_t XECP_DCPORTSC;                     /**< Debug Capability Port Status and Control, offset: 0x283A8 */
96498        uint32_t XECP_RSVD_2C;                      /**< Reserved, offset: 0x283AC */
96499   __IO uint32_t XECP_DCCP_LOW;                     /**< Debug Capability Context Pointer, offset: 0x283B0 */
96500   __IO uint32_t XECP_DCCP_HIGH;                    /**< Debug Capability Context Pointer, offset: 0x283B4 */
96501   __IO uint32_t XECP_DCDDI1;                       /**< Debug Capability Device Descriptor Info, offset: 0x283B8 */
96502   __IO uint32_t XECP_DCDDI2;                       /**< The Debug Capability Device Descriptor, offset: 0x283BC */
96503        uint8_t RESERVED_22[31808];
96504   __IO uint32_t USB_CONF;                          /**< Global Configuration, offset: 0x30000 */
96505   __I  uint32_t USB_STS;                           /**< Global Status, offset: 0x30004 */
96506   __IO uint32_t USB_CMD;                           /**< Global Command, offset: 0x30008 */
96507   __I  uint32_t USB_IPTN;                          /**< ITP Number, offset: 0x3000C */
96508   __I  uint32_t USB_LPM;                           /**< Link Power Management, offset: 0x30010 */
96509   __IO uint32_t USB_IEN;                           /**< Interrupt Enable, offset: 0x30014 */
96510   __IO uint32_t USB_ISTS;                          /**< Interrupt Status, offset: 0x30018 */
96511   __IO uint32_t EP_SEL;                            /**< Endpoint Select, offset: 0x3001C */
96512   __IO uint32_t EP_TRADDR;                         /**< Endpoint Transfer Ring Address, offset: 0x30020 */
96513   __IO uint32_t EP_CFG;                            /**< Endpoint Configuration, offset: 0x30024 */
96514   __IO uint32_t EP_CMD;                            /**< Endpoint Command, offset: 0x30028 */
96515   __IO uint32_t EP_STS;                            /**< Endpoint Status, offset: 0x3002C */
96516   __I  uint32_t EP_STS_SID;                        /**< Endpoint Status, offset: 0x30030 */
96517   __IO uint32_t EP_STS_EN;                         /**< Endpoint Status Register Enable, offset: 0x30034 */
96518   __IO uint32_t DRBL;                              /**< Doorbell Register, offset: 0x30038 */
96519   __IO uint32_t EP_IEN;                            /**< Endpoints Interrupt Enable), offset: 0x3003C */
96520   __I  uint32_t EP_ISTS;                           /**< Endpoints Interrupt Status, offset: 0x30040 */
96521   __IO uint32_t USB_PWR;                           /**< Global power configuration, offset: 0x30044 */
96522   __IO uint32_t USB_CONF2;                         /**< USB configuration, offset: 0x30048 */
96523   __I  uint32_t USB_CAP1;                          /**< USB Capability, offset: 0x3004C */
96524   __I  uint32_t USB_CAP2;                          /**< USB Capability, offset: 0x30050 */
96525   __I  uint32_t USB_CAP3;                          /**< USB Capability, offset: 0x30054 */
96526   __I  uint32_t USB_CAP4;                          /**< ISO HW support, offset: 0x30058 */
96527   __I  uint32_t USB_CAP5;                          /**< Bulk Stream HW, offset: 0x3005C */
96528   __I  uint32_t USB_CAP6;                          /**< Device controller version, offset: 0x30060 */
96529   __IO uint32_t USB_CPKT1;                         /**< Custom Packet value, offset: 0x30064 */
96530   __IO uint32_t USB_CPKT2;                         /**< Custom Packet value, offset: 0x30068 */
96531   __IO uint32_t USB_CPKT3;                         /**< Custom Packet value, offset: 0x3006C */
96532        uint8_t RESERVED_23[144];
96533   __IO uint32_t CFG_REG1;                          /**< VBUS debouncer Configuration, offset: 0x30100 */
96534   __IO uint32_t DBG_LINK1;                         /**< Link, offset: 0x30104 */
96535   __IO uint32_t DBG_LINK2;                         /**< Link, offset: 0x30108 */
96536   __IO uint32_t CFG_REG4;                          /**< USB3 Configuration, offset: 0x3010C */
96537   __IO uint32_t CFG_REG5;                          /**< USB3 Configuration, offset: 0x30110 */
96538   __IO uint32_t CFG_REG6;                          /**< Configuration Register 6, offset: 0x30114 */
96539   __IO uint32_t CFG_REG7;                          /**< USB3 Configuration, offset: 0x30118 */
96540   __IO uint32_t CFG_REG8;                          /**< USB3 Configuration, offset: 0x3011C */
96541   __IO uint32_t CFG_REG9;                          /**< USB3 Configuration, offset: 0x30120 */
96542   __IO uint32_t CFG_REG10;                         /**< USB3 Configuration, offset: 0x30124 */
96543   __IO uint32_t CFG_REG11;                         /**< USB3 Configuration, offset: 0x30128 */
96544   __IO uint32_t CFG_REG12;                         /**< USB3 Configuration, offset: 0x3012C */
96545   __IO uint32_t CFG_REG13;                         /**< USB3 Configuration, offset: 0x30130 */
96546   __IO uint32_t CFG_REG14;                         /**< USB3 Configuration, offset: 0x30134 */
96547   __IO uint32_t CFG_REG15;                         /**< USB3 Configuration, offset: 0x30138 */
96548   __IO uint32_t CFG_REG16;                         /**< USB3 Configuration, offset: 0x3013C */
96549   __IO uint32_t CFG_REG17;                         /**< USB3 Configuration, offset: 0x30140 */
96550   __IO uint32_t CFG_REG18;                         /**< USB3 Configuration, offset: 0x30144 */
96551   __IO uint32_t CFG_REG19;                         /**< USB3 Configuration, offset: 0x30148 */
96552   __IO uint32_t CFG_REG20;                         /**< USB3 Configuration, offset: 0x3014C */
96553   __IO uint32_t CFG_REG21;                         /**< USB3 Configuration, offset: 0x30150 */
96554   __IO uint32_t CFG_REG22;                         /**< USB3 Configuration, offset: 0x30154 */
96555   __IO uint32_t CFG_REG23;                         /**< USB3 Configuration, offset: 0x30158 */
96556   __IO uint32_t CFG_REG24;                         /**< USB3 Configuration, offset: 0x3015C */
96557   __IO uint32_t CFG_REG25;                         /**< USB3 Configuration, offset: 0x30160 */
96558   __IO uint32_t CFG_REG26;                         /**< USB3 Configuration, offset: 0x30164 */
96559   __IO uint32_t CFG_REG27;                         /**< USB3 Configuration, offset: 0x30168 */
96560   __IO uint32_t CFG_REG28;                         /**< USB3 Configuration, offset: 0x3016C */
96561   __IO uint32_t CFG_REG29;                         /**< USB3 Configuration, offset: 0x30170 */
96562   __IO uint32_t CFG_REG30;                         /**< USB3 Configuration, offset: 0x30174 */
96563   __IO uint32_t CFG_REG31;                         /**< USB3 Configuration, offset: 0x30178 */
96564   __IO uint32_t CFG_REG32;                         /**< USB3 Configuration, offset: 0x3017C */
96565   __IO uint32_t CFG_REG33;                         /**< USB3 Configuration, offset: 0x30180 */
96566   __IO uint32_t CFG_REG34;                         /**< USB3 Configuration, offset: 0x30184 */
96567   __IO uint32_t CFG_REG35;                         /**< USB3 Configuration, offset: 0x30188 */
96568        uint8_t RESERVED_24[32];
96569   __IO uint32_t CFG_REG36;                         /**< USB3 Configuration, offset: 0x301AC */
96570   __IO uint32_t CFG_REG37;                         /**< USB3 Configuration, offset: 0x301B0 */
96571   __IO uint32_t CFG_REG38;                         /**< USB3 Configuration, offset: 0x301B4 */
96572   __IO uint32_t CFG_REG39;                         /**< USB3 Configuration, offset: 0x301B8 */
96573   __IO uint32_t CFG_REG40;                         /**< USB3 Configuration, offset: 0x301BC */
96574   __IO uint32_t CFG_REG41;                         /**< USB3 Configuration, offset: 0x301C0 */
96575   __IO uint32_t CFG_REG42;                         /**< USB3 Configuration, offset: 0x301C4 */
96576   __IO uint32_t CFG_REG43;                         /**< USB3 Configuration, offset: 0x301C8 */
96577   __IO uint32_t CFG_REG44;                         /**< USB3 Configuration, offset: 0x301CC */
96578   __IO uint32_t CFG_REG45;                         /**< USB3 Configuration, offset: 0x301D0 */
96579   __IO uint32_t CFG_REG46;                         /**< USB3 Configuration, offset: 0x301D4 */
96580   __IO uint32_t CFG_REG47;                         /**< USB3 Configuration, offset: 0x301D8 */
96581   __IO uint32_t CFG_REG48;                         /**< USB2 Configuration, offset: 0x301DC */
96582   __IO uint32_t CFG_REG49;                         /**< USB2 Configuration, offset: 0x301E0 */
96583   __IO uint32_t CFG_REG50;                         /**< USB2 Configuration, offset: 0x301E4 */
96584   __IO uint32_t CFG_REG51;                         /**< USB2 Configuration, offset: 0x301E8 */
96585   __IO uint32_t CFG_REG52;                         /**< USB2 Configuration, offset: 0x301EC */
96586   __IO uint32_t CFG_REG53;                         /**< USB2 Configuration, offset: 0x301F0 */
96587   __IO uint32_t CFG_REG54;                         /**< USB2 Configuration, offset: 0x301F4 */
96588   __IO uint32_t CFG_REG55;                         /**< USB2 Configuration, offset: 0x301F8 */
96589   __IO uint32_t CFG_REG56;                         /**< USB2 Configuration, offset: 0x301FC */
96590   __IO uint32_t CFG_REG57;                         /**< USB3 Configuration, offset: 0x30200 */
96591   __IO uint32_t CFG_REG58;                         /**< USB3 Configuration, offset: 0x30204 */
96592   __IO uint32_t CFG_REG59;                         /**< USB3 Configuration, offset: 0x30208 */
96593   __IO uint32_t CFG_REG60;                         /**< USB3 Configuration, offset: 0x3020C */
96594   __IO uint32_t CFG_REG61;                         /**< USB3 Configuration, offset: 0x30210 */
96595   __IO uint32_t CFG_REG62;                         /**< USB3 Configuration, offset: 0x30214 */
96596   __IO uint32_t CFG_REG63;                         /**< USB3 Configuration, offset: 0x30218 */
96597        uint8_t RESERVED_25[4];
96598   __IO uint32_t CFG_REG64;                         /**< USB2 Configuration, offset: 0x30220 */
96599   __IO uint32_t CFG_REG65;                         /**< USB2 Configuration, offset: 0x30224 */
96600   __IO uint32_t CFG_REG66;                         /**< USB2 Configuration, offset: 0x30228 */
96601        uint8_t RESERVED_26[212];
96602   __IO uint32_t DMA_AXI_CTRL;                      /**< DMA AXI Master Control, offset: 0x30300 */
96603   __IO uint32_t DMA_AXI_ID;                        /**< DMA AXI Master ID, offset: 0x30304 */
96604   __IO uint32_t DMA_AXI_CAP;                       /**< DMA AXI Master Extended Capability, offset: 0x30308 */
96605   __IO uint32_t DMA_AXI_CTRL0;                     /**< DMA AXI Master Control, offset: 0x3030C */
96606   __IO uint32_t DMA_AXI_CTRL1;                     /**< DMA AXI Master Control, offset: 0x30310 */
96607 } USB3_Type;
96608 
96609 /* ----------------------------------------------------------------------------
96610    -- USB3 Register Masks
96611    ---------------------------------------------------------------------------- */
96612 
96613 /*!
96614  * @addtogroup USB3_Register_Masks USB3 Register Masks
96615  * @{
96616  */
96617 
96618 /*! @name CORE_CTRL11 - Core Control */
96619 /*! @{ */
96620 #define USB3_CORE_CTRL11_MODE_STRAP_MASK         (0x7U)
96621 #define USB3_CORE_CTRL11_MODE_STRAP_SHIFT        (0U)
96622 /*! MODE_STRAP - Can only be changed when the pwr_sw_reset is 1.
96623  *  0b001..OTG mode (Default)
96624  *  0b010..xHCI mode
96625  *  0b100..DEV mode
96626  */
96627 #define USB3_CORE_CTRL11_MODE_STRAP(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_MODE_STRAP_SHIFT)) & USB3_CORE_CTRL11_MODE_STRAP_MASK)
96628 #define USB3_CORE_CTRL11_WAKEUP_INT_CLR_MASK     (0x8U)
96629 #define USB3_CORE_CTRL11_WAKEUP_INT_CLR_SHIFT    (3U)
96630 /*! WAKEUP_INT_CLR - Wakeup Interrupt Clear
96631  *  0b1..Wakeup interrupt is cleared.
96632  */
96633 #define USB3_CORE_CTRL11_WAKEUP_INT_CLR(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_WAKEUP_INT_CLR_SHIFT)) & USB3_CORE_CTRL11_WAKEUP_INT_CLR_MASK)
96634 #define USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON_MASK (0x10U)
96635 #define USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON_SHIFT (4U)
96636 /*! APP_CLK_125_ALWAYSON - Set to always enable the 125MHz Clock
96637  */
96638 #define USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON_SHIFT)) & USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON_MASK)
96639 #define USB3_CORE_CTRL11_LPM_CLK_ALWAYSON_MASK   (0x20U)
96640 #define USB3_CORE_CTRL11_LPM_CLK_ALWAYSON_SHIFT  (5U)
96641 /*! LPM_CLK_ALWAYSON - set to always enable lpm_clk
96642  */
96643 #define USB3_CORE_CTRL11_LPM_CLK_ALWAYSON(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_LPM_CLK_ALWAYSON_SHIFT)) & USB3_CORE_CTRL11_LPM_CLK_ALWAYSON_MASK)
96644 #define USB3_CORE_CTRL11_XHC_D0_REQ_MASK         (0x40U)
96645 #define USB3_CORE_CTRL11_XHC_D0_REQ_SHIFT        (6U)
96646 /*! XHC_D0_REQ - Request Host mode transition to D0 state. Once asserted, shall be held high until xhc_d0_ack is asserted.
96647  */
96648 #define USB3_CORE_CTRL11_XHC_D0_REQ(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_XHC_D0_REQ_SHIFT)) & USB3_CORE_CTRL11_XHC_D0_REQ_MASK)
96649 #define USB3_CORE_CTRL11_MDCTRL_CLK_SEL_MASK     (0x80U)
96650 #define USB3_CORE_CTRL11_MDCTRL_CLK_SEL_SHIFT    (7U)
96651 /*! MDCTRL_CLK_SEL - OTG logic clock select signal
96652  *  0b0..OTG logic shall operate on the otg_fast_clk. It is a default, after power-on reset value.
96653  *  0b1..OTG logic shall operate on the stb_clk_predft (32kHz) clock
96654  */
96655 #define USB3_CORE_CTRL11_MDCTRL_CLK_SEL(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_MDCTRL_CLK_SEL_SHIFT)) & USB3_CORE_CTRL11_MDCTRL_CLK_SEL_MASK)
96656 #define USB3_CORE_CTRL11_OVERCURRENT_POLARITY_MASK (0x100U)
96657 #define USB3_CORE_CTRL11_OVERCURRENT_POLARITY_SHIFT (8U)
96658 /*! OVERCURRENT_POLARITY - Over Current Polarity
96659  *  0b0..Active Low
96660  *  0b1..Active High
96661  */
96662 #define USB3_CORE_CTRL11_OVERCURRENT_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OVERCURRENT_POLARITY_SHIFT)) & USB3_CORE_CTRL11_OVERCURRENT_POLARITY_MASK)
96663 #define USB3_CORE_CTRL11_OVERCURRENT_DISABLE_MASK (0x200U)
96664 #define USB3_CORE_CTRL11_OVERCURRENT_DISABLE_SHIFT (9U)
96665 /*! OVERCURRENT_DISABLE - 1 to disable overcurrent, since core is active low, so set to 1 will always set overcurrent_n to core.
96666  */
96667 #define USB3_CORE_CTRL11_OVERCURRENT_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OVERCURRENT_DISABLE_SHIFT)) & USB3_CORE_CTRL11_OVERCURRENT_DISABLE_MASK)
96668 #define USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN_MASK   (0x2000U)
96669 #define USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN_SHIFT  (13U)
96670 /*! OTG_ID_WAKEUP_EN - id wakeup interrupt enable, used only when usb3 controller is power down and usb2phy is power on.
96671  */
96672 #define USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN_SHIFT)) & USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN_MASK)
96673 #define USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN_MASK (0x4000U)
96674 #define USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN_SHIFT (14U)
96675 /*! OTG_VBUS_WAKEUP_EN - vbus/sessvalid wakeup interrupt enable, used only when usb3 controller is power down and usb2phy is power on
96676  */
96677 #define USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN_SHIFT)) & USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN_MASK)
96678 #define USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN_MASK   (0x8000U)
96679 #define USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN_SHIFT  (15U)
96680 /*! OTG_WKDPDMCHG_EN - dpdm wakeup interrupt enable, used only when usb3 controller is power down and usb2phy is power on
96681  */
96682 #define USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN_SHIFT)) & USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN_MASK)
96683 #define USB3_CORE_CTRL11_WAKEUP_INT_STATUS_MASK  (0x10000U)
96684 #define USB3_CORE_CTRL11_WAKEUP_INT_STATUS_SHIFT (16U)
96685 /*! WAKEUP_INT_STATUS - Wakeup_int_status is read.
96686  */
96687 #define USB3_CORE_CTRL11_WAKEUP_INT_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_WAKEUP_INT_STATUS_SHIFT)) & USB3_CORE_CTRL11_WAKEUP_INT_STATUS_MASK)
96688 #define USB3_CORE_CTRL11_PHYAPB_SW_RESET_MASK    (0x4000000U)
96689 #define USB3_CORE_CTRL11_PHYAPB_SW_RESET_SHIFT   (26U)
96690 /*! PHYAPB_SW_RESET - software reset for usb3phy apb bus
96691  *  0b1..Reset (Default)
96692  */
96693 #define USB3_CORE_CTRL11_PHYAPB_SW_RESET(x)      (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_PHYAPB_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_PHYAPB_SW_RESET_MASK)
96694 #define USB3_CORE_CTRL11_PHY_SW_RESET_MASK       (0x8000000U)
96695 #define USB3_CORE_CTRL11_PHY_SW_RESET_SHIFT      (27U)
96696 /*! PHY_SW_RESET - Softwrae reset for usb3 PHY
96697  *  0b1..Reset (Default)
96698  */
96699 #define USB3_CORE_CTRL11_PHY_SW_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_PHY_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_PHY_SW_RESET_MASK)
96700 #define USB3_CORE_CTRL11_AXI_SW_RESET_MASK       (0x20000000U)
96701 #define USB3_CORE_CTRL11_AXI_SW_RESET_SHIFT      (29U)
96702 /*! AXI_SW_RESET - software reset for usb3 axi bus
96703  *  0b1..Reset (Default)
96704  */
96705 #define USB3_CORE_CTRL11_AXI_SW_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_AXI_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_AXI_SW_RESET_MASK)
96706 #define USB3_CORE_CTRL11_APB_SW_RESET_MASK       (0x40000000U)
96707 #define USB3_CORE_CTRL11_APB_SW_RESET_SHIFT      (30U)
96708 /*! APB_SW_RESET - software reset for usb3 core apb bus
96709  *  0b1..Reset (Default)
96710  */
96711 #define USB3_CORE_CTRL11_APB_SW_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_APB_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_APB_SW_RESET_MASK)
96712 #define USB3_CORE_CTRL11_PWR_SW_RESET_MASK       (0x80000000U)
96713 #define USB3_CORE_CTRL11_PWR_SW_RESET_SHIFT      (31U)
96714 /*! PWR_SW_RESET - software reset for usb3 core
96715  *  0b1..Reset (Default)
96716  */
96717 #define USB3_CORE_CTRL11_PWR_SW_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_PWR_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_PWR_SW_RESET_MASK)
96718 /*! @} */
96719 
96720 /*! @name INT - Interrupt */
96721 /*! @{ */
96722 #define USB3_INT_XHCI_INT_EN_MASK                (0xFFU)
96723 #define USB3_INT_XHCI_INT_EN_SHIFT               (0U)
96724 /*! XHCI_INT_EN - xHCI Interrupt Enable
96725  */
96726 #define USB3_INT_XHCI_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_INT_XHCI_INT_EN_SHIFT)) & USB3_INT_XHCI_INT_EN_MASK)
96727 #define USB3_INT_DEV_INT_EN_MASK                 (0x300U)
96728 #define USB3_INT_DEV_INT_EN_SHIFT                (8U)
96729 /*! DEV_INT_EN - Device Interrupts Enable
96730  */
96731 #define USB3_INT_DEV_INT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_INT_DEV_INT_EN_SHIFT)) & USB3_INT_DEV_INT_EN_MASK)
96732 #define USB3_INT_OTG_INT_EN_MASK                 (0x400U)
96733 #define USB3_INT_OTG_INT_EN_SHIFT                (10U)
96734 /*! OTG_INT_EN - OTG Interrupt Enable
96735  */
96736 #define USB3_INT_OTG_INT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_INT_OTG_INT_EN_SHIFT)) & USB3_INT_OTG_INT_EN_MASK)
96737 #define USB3_INT_LTM_HOST_EN_MASK                (0x800U)
96738 #define USB3_INT_LTM_HOST_EN_SHIFT               (11U)
96739 /*! LTM_HOST_EN - LTM(Latency Tolerance messaging) request Interrupt Enable
96740  */
96741 #define USB3_INT_LTM_HOST_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_INT_LTM_HOST_EN_SHIFT)) & USB3_INT_LTM_HOST_EN_MASK)
96742 #define USB3_INT_OTG_WAKEUP_EN_MASK              (0x1000U)
96743 #define USB3_INT_OTG_WAKEUP_EN_SHIFT             (12U)
96744 /*! OTG_WAKEUP_EN - OTG Wakeup Enable
96745  */
96746 #define USB3_INT_OTG_WAKEUP_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_INT_OTG_WAKEUP_EN_SHIFT)) & USB3_INT_OTG_WAKEUP_EN_MASK)
96747 #define USB3_INT_DEVU3_WAKEUP_EN_MASK            (0x4000U)
96748 #define USB3_INT_DEVU3_WAKEUP_EN_SHIFT           (14U)
96749 /*! DEVU3_WAKEUP_EN - Device U3 Wakeup Enable
96750  */
96751 #define USB3_INT_DEVU3_WAKEUP_EN(x)              (((uint32_t)(((uint32_t)(x)) << USB3_INT_DEVU3_WAKEUP_EN_SHIFT)) & USB3_INT_DEVU3_WAKEUP_EN_MASK)
96752 #define USB3_INT_DEV_WAKEUP_MASK                 (0x8000U)
96753 #define USB3_INT_DEV_WAKEUP_SHIFT                (15U)
96754 /*! DEV_WAKEUP - connect to wakeup of device core
96755  */
96756 #define USB3_INT_DEV_WAKEUP(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_INT_DEV_WAKEUP_SHIFT)) & USB3_INT_DEV_WAKEUP_MASK)
96757 #define USB3_INT_INTERRUPT_REQ_MASK              (0xFF0000U)
96758 #define USB3_INT_INTERRUPT_REQ_SHIFT             (16U)
96759 /*! INTERRUPT_REQ - xHCI Interrupts
96760  */
96761 #define USB3_INT_INTERRUPT_REQ(x)                (((uint32_t)(((uint32_t)(x)) << USB3_INT_INTERRUPT_REQ_SHIFT)) & USB3_INT_INTERRUPT_REQ_MASK)
96762 #define USB3_INT_DEV_IRQS_MASK                   (0x3000000U)
96763 #define USB3_INT_DEV_IRQS_SHIFT                  (24U)
96764 /*! DEV_IRQS - Device interrupts
96765  */
96766 #define USB3_INT_DEV_IRQS(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_INT_DEV_IRQS_SHIFT)) & USB3_INT_DEV_IRQS_MASK)
96767 #define USB3_INT_OTGIRQ_MASK                     (0x4000000U)
96768 #define USB3_INT_OTGIRQ_SHIFT                    (26U)
96769 /*! OTGIRQ - OTG interrupts
96770  */
96771 #define USB3_INT_OTGIRQ(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_INT_OTGIRQ_SHIFT)) & USB3_INT_OTGIRQ_MASK)
96772 #define USB3_INT_LTM_HOST_REQ_MASK               (0x8000000U)
96773 #define USB3_INT_LTM_HOST_REQ_SHIFT              (27U)
96774 /*! LTM_HOST_REQ - LTM Request Interrupt
96775  */
96776 #define USB3_INT_LTM_HOST_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_INT_LTM_HOST_REQ_SHIFT)) & USB3_INT_LTM_HOST_REQ_MASK)
96777 #define USB3_INT_LPM_HOST_REQ_MASK               (0x10000000U)
96778 #define USB3_INT_LPM_HOST_REQ_SHIFT              (28U)
96779 /*! LPM_HOST_REQ - indicate usb3core request lpm_clkc
96780  */
96781 #define USB3_INT_LPM_HOST_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_INT_LPM_HOST_REQ_SHIFT)) & USB3_INT_LPM_HOST_REQ_MASK)
96782 #define USB3_INT_CLK_125_REQ_MASK                (0x20000000U)
96783 #define USB3_INT_CLK_125_REQ_SHIFT               (29U)
96784 /*! CLK_125_REQ - indicate usb3core request 125MHz clock
96785  */
96786 #define USB3_INT_CLK_125_REQ(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_INT_CLK_125_REQ_SHIFT)) & USB3_INT_CLK_125_REQ_MASK)
96787 #define USB3_INT_PHY_REFCLK_REQ_MASK             (0x40000000U)
96788 #define USB3_INT_PHY_REFCLK_REQ_SHIFT            (30U)
96789 /*! PHY_REFCLK_REQ - indicate PHY request reference clock
96790  */
96791 #define USB3_INT_PHY_REFCLK_REQ(x)               (((uint32_t)(((uint32_t)(x)) << USB3_INT_PHY_REFCLK_REQ_SHIFT)) & USB3_INT_PHY_REFCLK_REQ_MASK)
96792 /*! @} */
96793 
96794 /*! @name CORE_STATUS - Core Status */
96795 /*! @{ */
96796 #define USB3_CORE_STATUS_LOWEST_BELT_MASK        (0xFFFU)
96797 #define USB3_CORE_STATUS_LOWEST_BELT_SHIFT       (0U)
96798 /*! LOWEST_BELT - lowexst BELT value from xhci core
96799  */
96800 #define USB3_CORE_STATUS_LOWEST_BELT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_LOWEST_BELT_SHIFT)) & USB3_CORE_STATUS_LOWEST_BELT_MASK)
96801 #define USB3_CORE_STATUS_XHCI_POWER_ON_READY_MASK (0x1000U)
96802 #define USB3_CORE_STATUS_XHCI_POWER_ON_READY_SHIFT (12U)
96803 /*! XHCI_POWER_ON_READY - xhci ready, SW should wait it to be 1 before access any xhci registers
96804  */
96805 #define USB3_CORE_STATUS_XHCI_POWER_ON_READY(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_XHCI_POWER_ON_READY_SHIFT)) & USB3_CORE_STATUS_XHCI_POWER_ON_READY_MASK)
96806 #define USB3_CORE_STATUS_USBDEV_POWER_ON_READY_MASK (0x2000U)
96807 #define USB3_CORE_STATUS_USBDEV_POWER_ON_READY_SHIFT (13U)
96808 /*! USBDEV_POWER_ON_READY - device ready, SW should wait it to be 1 before access any device registers
96809  */
96810 #define USB3_CORE_STATUS_USBDEV_POWER_ON_READY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_USBDEV_POWER_ON_READY_SHIFT)) & USB3_CORE_STATUS_USBDEV_POWER_ON_READY_MASK)
96811 #define USB3_CORE_STATUS_XHC_D0_ACK_MASK         (0x4000U)
96812 #define USB3_CORE_STATUS_XHC_D0_ACK_SHIFT        (14U)
96813 /*! XHC_D0_ACK - Acknowledge for D0 state entry request indicating that Host entered D0 state. Once
96814  *    asserted, will be held high until xhc_d0_req is de-asserted
96815  */
96816 #define USB3_CORE_STATUS_XHC_D0_ACK(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_XHC_D0_ACK_SHIFT)) & USB3_CORE_STATUS_XHC_D0_ACK_MASK)
96817 #define USB3_CORE_STATUS_MDCTRL_CLK_STATUS_MASK  (0x8000U)
96818 #define USB3_CORE_STATUS_MDCTRL_CLK_STATUS_SHIFT (15U)
96819 /*! MDCTRL_CLK_STATUS - Status from USBSS-DRD to indicate on which clock OTG logic is currently
96820  *    running. Change on this signal can be considered as an acknowledge for the mdctrl_clk_sel.
96821  *  0b1..OTG logic is currently running on the stb_clk_predft (32Khz) clock
96822  *  0b0..OTG logic is currently running on the otg_fast_clk.
96823  */
96824 #define USB3_CORE_STATUS_MDCTRL_CLK_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_MDCTRL_CLK_STATUS_SHIFT)) & USB3_CORE_STATUS_MDCTRL_CLK_STATUS_MASK)
96825 /*! @} */
96826 
96827 /*! @name OTGCMD - OTG Command */
96828 /*! @{ */
96829 #define USB3_OTGCMD_DEV_BUS_REQ_MASK             (0x1U)
96830 #define USB3_OTGCMD_DEV_BUS_REQ_SHIFT            (0U)
96831 /*! DEV_BUS_REQ - Request the bus for Device mode. It will set DEV_ACTIVE bit is OTGSTS
96832  */
96833 #define USB3_OTGCMD_DEV_BUS_REQ(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_BUS_REQ_SHIFT)) & USB3_OTGCMD_DEV_BUS_REQ_MASK)
96834 #define USB3_OTGCMD_HOST_BUS_REQ_MASK            (0x2U)
96835 #define USB3_OTGCMD_HOST_BUS_REQ_SHIFT           (1U)
96836 /*! HOST_BUS_REQ - Request the bus for Host mode. It will set HOST_ACTIVE bit is OTGSTS
96837  */
96838 #define USB3_OTGCMD_HOST_BUS_REQ(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_HOST_BUS_REQ_SHIFT)) & USB3_OTGCMD_HOST_BUS_REQ_MASK)
96839 #define USB3_OTGCMD_OTG_EN_MASK                  (0x4U)
96840 #define USB3_OTGCMD_OTG_EN_SHIFT                 (2U)
96841 /*! OTG_EN - Enable OTG mode. It will set OTG_IS_ENABLED bit is OTGSTS
96842  */
96843 #define USB3_OTGCMD_OTG_EN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_OTG_EN_SHIFT)) & USB3_OTGCMD_OTG_EN_MASK)
96844 #define USB3_OTGCMD_OTG_DIS_MASK                 (0x8U)
96845 #define USB3_OTGCMD_OTG_DIS_SHIFT                (3U)
96846 /*! OTG_DIS - Disable OTG mode. It will clear OTG_IS_ENABLED bit is OTGSTS
96847  */
96848 #define USB3_OTGCMD_OTG_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_OTG_DIS_SHIFT)) & USB3_OTGCMD_OTG_DIS_MASK)
96849 #define USB3_OTGCMD_A_DEV_EN_MASK                (0x10U)
96850 #define USB3_OTGCMD_A_DEV_EN_SHIFT               (4U)
96851 /*! A_DEV_EN - Configure OTG as A-Device. It is only valid if OTG mode is enabled. This bit should be set in the same time when OTG_EN
96852  */
96853 #define USB3_OTGCMD_A_DEV_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_DEV_EN_SHIFT)) & USB3_OTGCMD_A_DEV_EN_MASK)
96854 #define USB3_OTGCMD_A_DEV_DIS_MASK               (0x20U)
96855 #define USB3_OTGCMD_A_DEV_DIS_SHIFT              (5U)
96856 /*! A_DEV_DIS - Configure OTG as B-Device. It is only valid if OTG mode is enabled. This bit should be set in the same time when OTG_EN
96857  */
96858 #define USB3_OTGCMD_A_DEV_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_DEV_DIS_SHIFT)) & USB3_OTGCMD_A_DEV_DIS_MASK)
96859 #define USB3_OTGCMD_DEV_SESS_VLD_USE_SET_MASK    (0x40U)
96860 #define USB3_OTGCMD_DEV_SESS_VLD_USE_SET_SHIFT   (6U)
96861 /*! DEV_SESS_VLD_USE_SET - Device should use b_sess_vld as vbus valid indication. This bit should be set in the same time when DEV_BUS_REQ
96862  */
96863 #define USB3_OTGCMD_DEV_SESS_VLD_USE_SET(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_SESS_VLD_USE_SET_SHIFT)) & USB3_OTGCMD_DEV_SESS_VLD_USE_SET_MASK)
96864 #define USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_MASK    (0x80U)
96865 #define USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_SHIFT   (7U)
96866 /*! DEV_SESS_VLD_USE_CLR - Device should use a_vbus_vld as vbus valid indication. This bit should be set in the same time when DEV_BUS_REQ
96867  */
96868 #define USB3_OTGCMD_DEV_SESS_VLD_USE_CLR(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_SHIFT)) & USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_MASK)
96869 #define USB3_OTGCMD_DEV_BUS_DROP_MASK            (0x100U)
96870 #define USB3_OTGCMD_DEV_BUS_DROP_SHIFT           (8U)
96871 /*! DEV_BUS_DROP - Drop the bus for Device mode. This bit should be set when Device mode is no
96872  *    longer needed. It will clear DEV_ACTIVE bit is OTGSTS
96873  */
96874 #define USB3_OTGCMD_DEV_BUS_DROP(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_BUS_DROP_SHIFT)) & USB3_OTGCMD_DEV_BUS_DROP_MASK)
96875 #define USB3_OTGCMD_HOST_BUS_DROP_MASK           (0x200U)
96876 #define USB3_OTGCMD_HOST_BUS_DROP_SHIFT          (9U)
96877 /*! HOST_BUS_DROP - Drop the bus for Host mode. This bit should be set when Host mode is no longer
96878  *    needed. It will clear HOST_ACTIVE bit is OTGSTS
96879  */
96880 #define USB3_OTGCMD_HOST_BUS_DROP(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_HOST_BUS_DROP_SHIFT)) & USB3_OTGCMD_HOST_BUS_DROP_MASK)
96881 #define USB3_OTGCMD_DIS_VBUS_DROP_MASK           (0x400U)
96882 #define USB3_OTGCMD_DIS_VBUS_DROP_SHIFT          (10U)
96883 /*! DIS_VBUS_DROP - Do not disable vbus while bus is dropped. This bit is valid only if DEV_BUS_DROP or HOST_BUS_DROP are set
96884  */
96885 #define USB3_OTGCMD_DIS_VBUS_DROP(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DIS_VBUS_DROP_SHIFT)) & USB3_OTGCMD_DIS_VBUS_DROP_MASK)
96886 #define USB3_OTGCMD_DEV_POWER_OFF_MASK           (0x800U)
96887 #define USB3_OTGCMD_DEV_POWER_OFF_SHIFT          (11U)
96888 /*! DEV_POWER_OFF - Power Down USBSS-DEV
96889  */
96890 #define USB3_OTGCMD_DEV_POWER_OFF(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_POWER_OFF_SHIFT)) & USB3_OTGCMD_DEV_POWER_OFF_MASK)
96891 #define USB3_OTGCMD_HOST_POWER_OFF_MASK          (0x1000U)
96892 #define USB3_OTGCMD_HOST_POWER_OFF_SHIFT         (12U)
96893 /*! HOST_POWER_OFF - Power Down CDNSXHCI
96894  */
96895 #define USB3_OTGCMD_HOST_POWER_OFF(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_HOST_POWER_OFF_SHIFT)) & USB3_OTGCMD_HOST_POWER_OFF_MASK)
96896 #define USB3_OTGCMD_DEV_DEVEN_FORCE_SET_MASK     (0x2000U)
96897 #define USB3_OTGCMD_DEV_DEVEN_FORCE_SET_SHIFT    (13U)
96898 /*! DEV_DEVEN_FORCE_SET - Set forcing Device DEVEN bit to 1. This bit may be set while switching
96899  *    from Host to Device mode takes place. Setting this bit should be done in the same time when
96900  *    Device mode is activated (DEV_BUS_REQ). Setting this bit causes DEV_DEVEN_FORCE bit in OTGSTS set
96901  */
96902 #define USB3_OTGCMD_DEV_DEVEN_FORCE_SET(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_DEVEN_FORCE_SET_SHIFT)) & USB3_OTGCMD_DEV_DEVEN_FORCE_SET_MASK)
96903 #define USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_MASK     (0x4000U)
96904 #define USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_SHIFT    (14U)
96905 /*! DEV_DEVEN_FORCE_CLR - Clear forcing Device DEVEN bit to 1. Setting this bit causes DEV_DEVEN_FORCE bit in OTGSTS clear
96906  */
96907 #define USB3_OTGCMD_DEV_DEVEN_FORCE_CLR(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_SHIFT)) & USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_MASK)
96908 #define USB3_OTGCMD_H_WRST_FOR_SWAP_SET_MASK     (0x8000U)
96909 #define USB3_OTGCMD_H_WRST_FOR_SWAP_SET_SHIFT    (15U)
96910 /*! H_WRST_FOR_SWAP_SET - Upcoming Warm Reset will be generated for Role Swapping. This bit should
96911  *    be set before Warm Reset for Role Swap is generated on the Port
96912  */
96913 #define USB3_OTGCMD_H_WRST_FOR_SWAP_SET(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_H_WRST_FOR_SWAP_SET_SHIFT)) & USB3_OTGCMD_H_WRST_FOR_SWAP_SET_MASK)
96914 #define USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_MASK     (0x10000U)
96915 #define USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_SHIFT    (16U)
96916 /*! H_WRST_FOR_SWAP_CLR - Upcoming Warm Reset will not be generated for Role Swapping. This bit
96917  *    should be set after Warm Reset for Role Swap is generated on the Port
96918  */
96919 #define USB3_OTGCMD_H_WRST_FOR_SWAP_CLR(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_SHIFT)) & USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_MASK)
96920 #define USB3_OTGCMD_D_WRST_FOR_SWAP_SET_MASK     (0x20000U)
96921 #define USB3_OTGCMD_D_WRST_FOR_SWAP_SET_SHIFT    (17U)
96922 /*! D_WRST_FOR_SWAP_SET - Upcoming Warm Reset will be received for Role Swapping. This bit should be
96923  *    set before Warm Reset for Role Swap is received on the Port
96924  */
96925 #define USB3_OTGCMD_D_WRST_FOR_SWAP_SET(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_D_WRST_FOR_SWAP_SET_SHIFT)) & USB3_OTGCMD_D_WRST_FOR_SWAP_SET_MASK)
96926 #define USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_MASK     (0x40000U)
96927 #define USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_SHIFT    (18U)
96928 /*! D_WRST_FOR_SWAP_CLR - Upcoming received Warm Reset should not be treated as Role Swapping
96929  *    indication. This bit should be set after Warm Reset for Role Swap is received on the Port
96930  */
96931 #define USB3_OTGCMD_D_WRST_FOR_SWAP_CLR(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_SHIFT)) & USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_MASK)
96932 #define USB3_OTGCMD_SS_HOST_DISABLED_SET_MASK    (0x80000U)
96933 #define USB3_OTGCMD_SS_HOST_DISABLED_SET_SHIFT   (19U)
96934 /*! SS_HOST_DISABLED_SET - Disable SuperSpeed host functionality. Can be used only if Host mode is not active
96935  */
96936 #define USB3_OTGCMD_SS_HOST_DISABLED_SET(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_HOST_DISABLED_SET_SHIFT)) & USB3_OTGCMD_SS_HOST_DISABLED_SET_MASK)
96937 #define USB3_OTGCMD_SS_HOST_DISABLED_CLR_MASK    (0x100000U)
96938 #define USB3_OTGCMD_SS_HOST_DISABLED_CLR_SHIFT   (20U)
96939 /*! SS_HOST_DISABLED_CLR - Enable SuperSpeed host functionality
96940  */
96941 #define USB3_OTGCMD_SS_HOST_DISABLED_CLR(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_HOST_DISABLED_CLR_SHIFT)) & USB3_OTGCMD_SS_HOST_DISABLED_CLR_MASK)
96942 #define USB3_OTGCMD_SS_PERIPH_DISABLED_SET_MASK  (0x200000U)
96943 #define USB3_OTGCMD_SS_PERIPH_DISABLED_SET_SHIFT (21U)
96944 /*! SS_PERIPH_DISABLED_SET - Disable SuperSpeed peripheral device functionality. Can be used only if Peripheral mode is not active
96945  */
96946 #define USB3_OTGCMD_SS_PERIPH_DISABLED_SET(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_PERIPH_DISABLED_SET_SHIFT)) & USB3_OTGCMD_SS_PERIPH_DISABLED_SET_MASK)
96947 #define USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_MASK  (0x400000U)
96948 #define USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_SHIFT (22U)
96949 /*! SS_PERIPH_DISABLED_CLR - Enable SuperSpeed peripheral device functionality
96950  */
96951 #define USB3_OTGCMD_SS_PERIPH_DISABLED_CLR(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_SHIFT)) & USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_MASK)
96952 #define USB3_OTGCMD_A_SET_B_HNP_EN_SET_MASK      (0x800000U)
96953 #define USB3_OTGCMD_A_SET_B_HNP_EN_SET_SHIFT     (23U)
96954 /*! A_SET_B_HNP_EN_SET - This bit should be written if SetFeature(b_hnp_enable) has been sent
96955  */
96956 #define USB3_OTGCMD_A_SET_B_HNP_EN_SET(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_SET_B_HNP_EN_SET_SHIFT)) & USB3_OTGCMD_A_SET_B_HNP_EN_SET_MASK)
96957 #define USB3_OTGCMD_A_SET_B_HNP_EN_CLR_MASK      (0x1000000U)
96958 #define USB3_OTGCMD_A_SET_B_HNP_EN_CLR_SHIFT     (24U)
96959 /*! A_SET_B_HNP_EN_CLR - This bit should be written if upcoming USB 2.0 bus suspend should not cause Role Swap
96960  */
96961 #define USB3_OTGCMD_A_SET_B_HNP_EN_CLR(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_SET_B_HNP_EN_CLR_SHIFT)) & USB3_OTGCMD_A_SET_B_HNP_EN_CLR_MASK)
96962 #define USB3_OTGCMD_B_HNP_EN_SET_MASK            (0x2000000U)
96963 #define USB3_OTGCMD_B_HNP_EN_SET_SHIFT           (25U)
96964 /*! B_HNP_EN_SET - This bit should be written if SetFeature(b_hnp_enable) has been accepted
96965  */
96966 #define USB3_OTGCMD_B_HNP_EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_B_HNP_EN_SET_SHIFT)) & USB3_OTGCMD_B_HNP_EN_SET_MASK)
96967 #define USB3_OTGCMD_B_HNP_EN_CLR_MASK            (0x4000000U)
96968 #define USB3_OTGCMD_B_HNP_EN_CLR_SHIFT           (26U)
96969 /*! B_HNP_EN_CLR - This bit should be written if software wants to clear b_hnp_enable
96970  */
96971 #define USB3_OTGCMD_B_HNP_EN_CLR(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_B_HNP_EN_CLR_SHIFT)) & USB3_OTGCMD_B_HNP_EN_CLR_MASK)
96972 #define USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_MASK   (0x8000000U)
96973 #define USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_SHIFT  (27U)
96974 /*! OTG2_SWITCH_TO_PERIPH - Switch to Peripheral mode when operating at USB 2.0
96975  */
96976 #define USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_SHIFT)) & USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_MASK)
96977 #define USB3_OTGCMD_INIT_SRP_MASK                (0x10000000U)
96978 #define USB3_OTGCMD_INIT_SRP_SHIFT               (28U)
96979 /*! INIT_SRP - Initiate SRP
96980  */
96981 #define USB3_OTGCMD_INIT_SRP(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_INIT_SRP_SHIFT)) & USB3_OTGCMD_INIT_SRP_MASK)
96982 #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_MASK  (0x20000000U)
96983 #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_SHIFT (29U)
96984 /*! DEV_VBUS_DEB_SHORT_SET - Enable forcing Device short VBUS debounce time. This bit should be set
96985  *    while switching from Host to Device mode takes place. Setting this bit should be done in the
96986  *    same time when Device mode is activated (DEV_BUS_REQ). Setting this bit causes
96987  *    DEV_VBUS_DEB_SHORT bit in OTGSTS set
96988  */
96989 #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_SHIFT)) & USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_MASK)
96990 #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_MASK  (0x40000000U)
96991 #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_SHIFT (30U)
96992 /*! DEV_VBUS_DEB_SHORT_CLR - Disable forcing Device short VBUS debounce time. Setting this bit causes DEV_VBUS_DEB_SHORT bit in OTGSTS clear
96993  */
96994 #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_SHIFT)) & USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_MASK)
96995 /*! @} */
96996 
96997 /*! @name OTGSTS - OTG Status */
96998 /*! @{ */
96999 #define USB3_OTGSTS_ID_VALUE_MASK                (0x1U)
97000 #define USB3_OTGSTS_ID_VALUE_SHIFT               (0U)
97001 /*! ID_VALUE - Current value of the ID pin. It is only valid when idpullup in OTGCTRL1_TYPE register
97002  *    is set to '1'. ID_VALUE must be valid within 50ms after idpullup is set to '1'
97003  */
97004 #define USB3_OTGSTS_ID_VALUE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_ID_VALUE_SHIFT)) & USB3_OTGSTS_ID_VALUE_MASK)
97005 #define USB3_OTGSTS_VBUS_VALID_MASK              (0x2U)
97006 #define USB3_OTGSTS_VBUS_VALID_SHIFT             (1U)
97007 /*! VBUS_VALID - Current value of the vbus_valid
97008  */
97009 #define USB3_OTGSTS_VBUS_VALID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_VBUS_VALID_SHIFT)) & USB3_OTGSTS_VBUS_VALID_MASK)
97010 #define USB3_OTGSTS_SESSION_VALID_MASK           (0x4U)
97011 #define USB3_OTGSTS_SESSION_VALID_SHIFT          (2U)
97012 /*! SESSION_VALID - Current value of the b_sess_vld
97013  */
97014 #define USB3_OTGSTS_SESSION_VALID(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SESSION_VALID_SHIFT)) & USB3_OTGSTS_SESSION_VALID_MASK)
97015 #define USB3_OTGSTS_DEV_ACTIVE_MASK              (0x8U)
97016 #define USB3_OTGSTS_DEV_ACTIVE_SHIFT             (3U)
97017 /*! DEV_ACTIVE - Device mode is active. NOTE: It is possible that Device is in inactive state (even turned off) while DEV_ACTIVE is 1
97018  */
97019 #define USB3_OTGSTS_DEV_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_ACTIVE_SHIFT)) & USB3_OTGSTS_DEV_ACTIVE_MASK)
97020 #define USB3_OTGSTS_HOST_ACTIVE_MASK             (0x10U)
97021 #define USB3_OTGSTS_HOST_ACTIVE_SHIFT            (4U)
97022 /*! HOST_ACTIVE - Device mode is active. NOTE: It is possible that Host is in inactive state (even turned off) while HOST_ACTIVE is 1
97023  */
97024 #define USB3_OTGSTS_HOST_ACTIVE(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_HOST_ACTIVE_SHIFT)) & USB3_OTGSTS_HOST_ACTIVE_MASK)
97025 #define USB3_OTGSTS_OTG_IS_ENABLED_MASK          (0x20U)
97026 #define USB3_OTGSTS_OTG_IS_ENABLED_SHIFT         (5U)
97027 /*! OTG_IS_ENABLED - OTG functionality is enabled
97028  */
97029 #define USB3_OTGSTS_OTG_IS_ENABLED(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_OTG_IS_ENABLED_SHIFT)) & USB3_OTGSTS_OTG_IS_ENABLED_MASK)
97030 #define USB3_OTGSTS_OTG_MODE_MASK                (0x40U)
97031 #define USB3_OTGSTS_OTG_MODE_SHIFT               (6U)
97032 /*! OTG_MODE - OTG mode: 0 - A-Device 1 - B-Device Valid only if OTG_IS_ENABLED is 1
97033  */
97034 #define USB3_OTGSTS_OTG_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_OTG_MODE_SHIFT)) & USB3_OTGSTS_OTG_MODE_MASK)
97035 #define USB3_OTGSTS_SS_HOST_DISABLED_MASK        (0x80U)
97036 #define USB3_OTGSTS_SS_HOST_DISABLED_SHIFT       (7U)
97037 /*! SS_HOST_DISABLED - SuperSpeed host functionality is disabled. Port will be operating at USB 2.0 speed
97038  */
97039 #define USB3_OTGSTS_SS_HOST_DISABLED(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SS_HOST_DISABLED_SHIFT)) & USB3_OTGSTS_SS_HOST_DISABLED_MASK)
97040 #define USB3_OTGSTS_SS_PERIPH_DISABLED_MASK      (0x100U)
97041 #define USB3_OTGSTS_SS_PERIPH_DISABLED_SHIFT     (8U)
97042 /*! SS_PERIPH_DISABLED - SuperSpeed device functionality is disabled. Port will be operating at USB 2.0 speed
97043  */
97044 #define USB3_OTGSTS_SS_PERIPH_DISABLED(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SS_PERIPH_DISABLED_SHIFT)) & USB3_OTGSTS_SS_PERIPH_DISABLED_MASK)
97045 #define USB3_OTGSTS_DEV_VBUS_DEB_SHORT_MASK      (0x200U)
97046 #define USB3_OTGSTS_DEV_VBUS_DEB_SHORT_SHIFT     (9U)
97047 /*! DEV_VBUS_DEB_SHORT - Device forcing short VBUS decounce is enabled
97048  */
97049 #define USB3_OTGSTS_DEV_VBUS_DEB_SHORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_VBUS_DEB_SHORT_SHIFT)) & USB3_OTGSTS_DEV_VBUS_DEB_SHORT_MASK)
97050 #define USB3_OTGSTS_DEV_SESS_VLD_USE_MASK        (0x400U)
97051 #define USB3_OTGSTS_DEV_SESS_VLD_USE_SHIFT       (10U)
97052 /*! DEV_SESS_VLD_USE - Device mode vbus valid indication: 0: a_vbus_vld is used as vbus valid 1: b_sess_vld is used as vbus valid
97053  */
97054 #define USB3_OTGSTS_DEV_SESS_VLD_USE(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_SESS_VLD_USE_SHIFT)) & USB3_OTGSTS_DEV_SESS_VLD_USE_MASK)
97055 #define USB3_OTGSTS_OTG_NRDY_MASK                (0x800U)
97056 #define USB3_OTGSTS_OTG_NRDY_SHIFT               (11U)
97057 /*! OTG_NRDY - OTG Controller not ready. Software shall not read nor write any register except OTGISTS if this bit is set
97058  */
97059 #define USB3_OTGSTS_OTG_NRDY(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_OTG_NRDY_SHIFT)) & USB3_OTGSTS_OTG_NRDY_MASK)
97060 #define USB3_OTGSTS_STRAP_MASK                   (0x7000U)
97061 #define USB3_OTGSTS_STRAP_SHIFT                  (12U)
97062 /*! STRAP - Value of the strap pins. 000 - no default configuration 010 - Controller initiall
97063  *    configured as Host 100 - Controller initially configured as Device other - Reserved (might be used
97064  *    for Type-C)
97065  */
97066 #define USB3_OTGSTS_STRAP(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_STRAP_SHIFT)) & USB3_OTGSTS_STRAP_MASK)
97067 #define USB3_OTGSTS_H_WRST_FOR_SWAP_MASK         (0x8000U)
97068 #define USB3_OTGSTS_H_WRST_FOR_SWAP_SHIFT        (15U)
97069 /*! H_WRST_FOR_SWAP - Upcoming Warm Reset will be generated for Role Swapping from Host to Peripheral
97070  */
97071 #define USB3_OTGSTS_H_WRST_FOR_SWAP(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_H_WRST_FOR_SWAP_SHIFT)) & USB3_OTGSTS_H_WRST_FOR_SWAP_MASK)
97072 #define USB3_OTGSTS_DEV_DEVEN_FORCE_MASK         (0x10000U)
97073 #define USB3_OTGSTS_DEV_DEVEN_FORCE_SHIFT        (16U)
97074 /*! DEV_DEVEN_FORCE - Device forcing DEVEN bit is enabled
97075  */
97076 #define USB3_OTGSTS_DEV_DEVEN_FORCE(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_DEVEN_FORCE_SHIFT)) & USB3_OTGSTS_DEV_DEVEN_FORCE_MASK)
97077 #define USB3_OTGSTS_D_WRST_FOR_SWAP_MASK         (0x20000U)
97078 #define USB3_OTGSTS_D_WRST_FOR_SWAP_SHIFT        (17U)
97079 /*! D_WRST_FOR_SWAP - Upcoming Warm Reset will be received for Role Swapping from Peripheral to Host
97080  */
97081 #define USB3_OTGSTS_D_WRST_FOR_SWAP(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_D_WRST_FOR_SWAP_SHIFT)) & USB3_OTGSTS_D_WRST_FOR_SWAP_MASK)
97082 #define USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_MASK (0x40000U)
97083 #define USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_SHIFT (18U)
97084 /*! SRP_INITIAL_CONDITION_MET - SRP initial condition are met. OTG B-device software should issue SRP puluse onli if this bit is set
97085  */
97086 #define USB3_OTGSTS_SRP_INITIAL_CONDITION_MET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_SHIFT)) & USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_MASK)
97087 #define USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_MASK (0x80000U)
97088 #define USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_SHIFT (19U)
97089 /*! SRP_DET_NOT_COMPLIANT_DEV - OTG A-device detected not compilant device. If this bit is set then
97090  *    OTG A-device should disable SRP detection until not compilant device is disconnected
97091  *    (SRP_NOT_COMP_DEV_REMOVED_INT)
97092  */
97093 #define USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_SHIFT)) & USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_MASK)
97094 #define USB3_OTGSTS_A_SET_B_HNP_EN_MASK          (0x800000U)
97095 #define USB3_OTGSTS_A_SET_B_HNP_EN_SHIFT         (23U)
97096 /*! A_SET_B_HNP_EN - SetFeature(b_hnp_enable) has been sent and is valid
97097  */
97098 #define USB3_OTGSTS_A_SET_B_HNP_EN(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_A_SET_B_HNP_EN_SHIFT)) & USB3_OTGSTS_A_SET_B_HNP_EN_MASK)
97099 #define USB3_OTGSTS_B_HNP_EN_MASK                (0x2000000U)
97100 #define USB3_OTGSTS_B_HNP_EN_SHIFT               (25U)
97101 /*! B_HNP_EN - SetFeature(b_hnp_enable) has been accepted
97102  */
97103 #define USB3_OTGSTS_B_HNP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_B_HNP_EN_SHIFT)) & USB3_OTGSTS_B_HNP_EN_MASK)
97104 #define USB3_OTGSTS_XHC_READY_MASK               (0x4000000U)
97105 #define USB3_OTGSTS_XHC_READY_SHIFT              (26U)
97106 /*! XHC_READY - Host mode is turned on; registers in CDNSXHCI AUX domain are accessible through APB
97107  */
97108 #define USB3_OTGSTS_XHC_READY(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_XHC_READY_SHIFT)) & USB3_OTGSTS_XHC_READY_MASK)
97109 #define USB3_OTGSTS_DEV_READY_MASK               (0x8000000U)
97110 #define USB3_OTGSTS_DEV_READY_SHIFT              (27U)
97111 /*! DEV_READY - Device mode is turned on; registers in USBSS-DEV domain are accessible through APB
97112  */
97113 #define USB3_OTGSTS_DEV_READY(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_READY_SHIFT)) & USB3_OTGSTS_DEV_READY_MASK)
97114 /*! @} */
97115 
97116 /*! @name OTGSTATE - OTG State */
97117 /*! @{ */
97118 #define USB3_OTGSTATE_DEV_OTG_STATE_MASK         (0x7U)
97119 #define USB3_OTGSTATE_DEV_OTG_STATE_SHIFT        (0U)
97120 /*! DEV_OTG_STATE - Current state of the OTG Device FSM
97121  *  0b000..DEV_IDLE
97122  *  0b001..DEV_MODE
97123  *  0b010..DEV_SRP
97124  *  0b011..DEV_WAIT_VBUS_FALL
97125  *  0b100..DEV_SWITCH_TO_HOST
97126  *  0b101..DEV_WAIT_FOR_CONN
97127  */
97128 #define USB3_OTGSTATE_DEV_OTG_STATE(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_DEV_OTG_STATE_SHIFT)) & USB3_OTGSTATE_DEV_OTG_STATE_MASK)
97129 #define USB3_OTGSTATE_HOST_OTG_STATE_MASK        (0x38U)
97130 #define USB3_OTGSTATE_HOST_OTG_STATE_SHIFT       (3U)
97131 /*! HOST_OTG_STATE - Current state of the OTG Host FSM
97132  *  0b000..H_IDLE
97133  *  0b001..H_VBUS_ON
97134  *  0b010..H_VBUS_FAILED
97135  *  0b011..H_OTG_HOST_MODE
97136  *  0b100..H_HOST_MODE
97137  *  0b101..H_SWITCH_TO_DEVICE
97138  *  0b110..H_A_SUSPEND
97139  *  0b111..H_WAIT_VBUS_FALL
97140  */
97141 #define USB3_OTGSTATE_HOST_OTG_STATE(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_HOST_OTG_STATE_SHIFT)) & USB3_OTGSTATE_HOST_OTG_STATE_MASK)
97142 #define USB3_OTGSTATE_APB_AXI_CTRL_MASK          (0x300U)
97143 #define USB3_OTGSTATE_APB_AXI_CTRL_SHIFT         (8U)
97144 /*! APB_AXI_CTRL - Current state of the ABP/AXI mux selector
97145  *  0b00..Both modes off
97146  *  0b01..Host Active
97147  *  0b10..Device Active
97148  *  0b11..Illegal(Both modes off)
97149  */
97150 #define USB3_OTGSTATE_APB_AXI_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_APB_AXI_CTRL_SHIFT)) & USB3_OTGSTATE_APB_AXI_CTRL_MASK)
97151 #define USB3_OTGSTATE_PIPE_CTRL_MASK             (0xC00U)
97152 #define USB3_OTGSTATE_PIPE_CTRL_SHIFT            (10U)
97153 /*! PIPE_CTRL - Current state of the USB3 PIPE mux selector
97154  *  0b00..Both modes off
97155  *  0b01..Host Active
97156  *  0b10..Device Active
97157  *  0b11..Illegal(both modes off)
97158  */
97159 #define USB3_OTGSTATE_PIPE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PIPE_CTRL_SHIFT)) & USB3_OTGSTATE_PIPE_CTRL_MASK)
97160 #define USB3_OTGSTATE_UTMI_CTRL_MASK             (0x3000U)
97161 #define USB3_OTGSTATE_UTMI_CTRL_SHIFT            (12U)
97162 /*! UTMI_CTRL - Current state of the USB2 UTMI mux selector
97163  *  0b00..Both modes off, and OTG takes control over UTMI (SRP,BC)
97164  *  0b01..Host Active
97165  *  0b10..Device Active
97166  *  0b11..Illegal(both modes off)
97167  */
97168 #define USB3_OTGSTATE_UTMI_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_UTMI_CTRL_SHIFT)) & USB3_OTGSTATE_UTMI_CTRL_MASK)
97169 #define USB3_OTGSTATE_DEV_POWER_STATE_MASK       (0x70000U)
97170 #define USB3_OTGSTATE_DEV_POWER_STATE_SHIFT      (16U)
97171 /*! DEV_POWER_STATE - Current state of the Device power controlling FSM
97172  *  0b000..POWER_IDLE
97173  *  0b001..POWER_OFF_ACK
97174  *  0b010..POWER_OFF_MAIN_ACK
97175  *  0b011..POWER_OFF
97176  *  0b100..POWER_ON_REQ
97177  *  0b101..POWER_ISO_DIS
97178  *  0b110..POWER_ON
97179  *  0b111..POWER_ON_READY
97180  */
97181 #define USB3_OTGSTATE_DEV_POWER_STATE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_DEV_POWER_STATE_SHIFT)) & USB3_OTGSTATE_DEV_POWER_STATE_MASK)
97182 #define USB3_OTGSTATE_HOST_POWER_STATE_MASK      (0x380000U)
97183 #define USB3_OTGSTATE_HOST_POWER_STATE_SHIFT     (19U)
97184 /*! HOST_POWER_STATE - Current state of the Host power controlling FSM
97185  *  0b000..POWER_IDLE
97186  *  0b001..POWER_OFF_ACK
97187  *  0b010..POWER_OFF_MAIN_ACK
97188  *  0b011..POWER_OFF
97189  *  0b100..POWER_ON_REQ
97190  *  0b101..POWER_ISO_DIS
97191  *  0b110..POWER_ON
97192  *  0b111..POWER_ON_READY
97193  */
97194 #define USB3_OTGSTATE_HOST_POWER_STATE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_HOST_POWER_STATE_SHIFT)) & USB3_OTGSTATE_HOST_POWER_STATE_MASK)
97195 #define USB3_OTGSTATE_PHY_REFCLK_REQ_MASK        (0x1000000U)
97196 #define USB3_OTGSTATE_PHY_REFCLK_REQ_SHIFT       (24U)
97197 /*! PHY_REFCLK_REQ - Value of the phy_refclk_req signal from the PHY Reference Clock Control interface
97198  */
97199 #define USB3_OTGSTATE_PHY_REFCLK_REQ(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PHY_REFCLK_REQ_SHIFT)) & USB3_OTGSTATE_PHY_REFCLK_REQ_MASK)
97200 #define USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_MASK (0x2000000U)
97201 #define USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_SHIFT (25U)
97202 /*! PHY_REFCLK_1PCT_VALID - Value of the phy_refclk_1pct_valid signal from the PHY Reference Clock Control interface
97203  */
97204 #define USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_SHIFT)) & USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_MASK)
97205 #define USB3_OTGSTATE_PHY_REFCLK_VALID_MASK      (0x4000000U)
97206 #define USB3_OTGSTATE_PHY_REFCLK_VALID_SHIFT     (26U)
97207 /*! PHY_REFCLK_VALID - Value of the phy_refclk_valid signal from the PHY Reference Clock Control interface
97208  */
97209 #define USB3_OTGSTATE_PHY_REFCLK_VALID(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PHY_REFCLK_VALID_SHIFT)) & USB3_OTGSTATE_PHY_REFCLK_VALID_MASK)
97210 #define USB3_OTGSTATE_REFCLK_FSM_MASK            (0x38000000U)
97211 #define USB3_OTGSTATE_REFCLK_FSM_SHIFT           (27U)
97212 /*! REFCLK_FSM - Reference Clock control FSM state
97213  *  0b000..IDLE
97214  *  0b001..SWITCH32_GATE_ON
97215  *  0b010..REFCLK_OFF
97216  *  0b011..REFCLK_REQ
97217  *  0b100..GATE_OFF
97218  *  0b101..REFCLK_ON_SWITCH32
97219  *  0b110..REFCLK_ON_PHY3_AT_SLOW
97220  *  0b111..REFCLK_ON_SWITCH24
97221  */
97222 #define USB3_OTGSTATE_REFCLK_FSM(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_REFCLK_FSM_SHIFT)) & USB3_OTGSTATE_REFCLK_FSM_MASK)
97223 /*! @} */
97224 
97225 /*! @name OTGREFCLK - OTG Reference Clock */
97226 /*! @{ */
97227 #define USB3_OTGREFCLK_P3_TO_REFCLK_REQ_MASK     (0x3FFFU)
97228 #define USB3_OTGREFCLK_P3_TO_REFCLK_REQ_SHIFT    (0U)
97229 /*! P3_TO_REFCLK_REQ - Time in stb_clk_predft clock period units within which the module won't be
97230  *    requesting for Reference Clock to be off after USB 3.0 PHY powerdown changes to P3
97231  */
97232 #define USB3_OTGREFCLK_P3_TO_REFCLK_REQ(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGREFCLK_P3_TO_REFCLK_REQ_SHIFT)) & USB3_OTGREFCLK_P3_TO_REFCLK_REQ_MASK)
97233 #define USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_MASK (0x3FFF0000U)
97234 #define USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_SHIFT (16U)
97235 /*! SUSPEND_TO_REFCLK_REQ - Time in stb_clk_predft clock period units within which the module won't
97236  *    be requesting for Reference Clock to be off after USB 2.0 PHY is requested to enter suspend
97237  *    (L2) state
97238  */
97239 #define USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_SHIFT)) & USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_MASK)
97240 #define USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_MASK (0x80000000U)
97241 #define USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_SHIFT (31U)
97242 /*! OTG_STB_CLK_SWITCH_EN - Allow PHY Reference Clock sour to be either low frequency of turned-off when both modes (Host/Device) are disabled
97243  */
97244 #define USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_SHIFT)) & USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_MASK)
97245 /*! @} */
97246 
97247 /*! @name OTGIEN - OTG Interrupt Enable */
97248 /*! @{ */
97249 #define USB3_OTGIEN_ID_CHANGE_INT_EN_MASK        (0x1U)
97250 #define USB3_OTGIEN_ID_CHANGE_INT_EN_SHIFT       (0U)
97251 /*! ID_CHANGE_INT_EN - ID change interrupt enable
97252  */
97253 #define USB3_OTGIEN_ID_CHANGE_INT_EN(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_ID_CHANGE_INT_EN_SHIFT)) & USB3_OTGIEN_ID_CHANGE_INT_EN_MASK)
97254 #define USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_MASK   (0x2U)
97255 #define USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_SHIFT  (1U)
97256 /*! VBUS_ON_FAILED_INT_EN - Enabling Vbus by A-Device has failed interrupt enable
97257  */
97258 #define USB3_OTGIEN_VBUS_ON_FAILED_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_SHIFT)) & USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_MASK)
97259 #define USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_MASK (0x4U)
97260 #define USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_SHIFT (2U)
97261 /*! OTGSESSVALID_RISE_INT_EN - Otgsessvalid rise detected interrupt enable
97262  */
97263 #define USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_MASK)
97264 #define USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_MASK (0x8U)
97265 #define USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_SHIFT (3U)
97266 /*! OTGSESSVALID_FALL_INT_EN - Otgsessvalid fall detected interrupt enable
97267  */
97268 #define USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_MASK)
97269 #define USB3_OTGIEN_VBUSVALID_RISE_INT_EN_MASK   (0x10U)
97270 #define USB3_OTGIEN_VBUSVALID_RISE_INT_EN_SHIFT  (4U)
97271 /*! VBUSVALID_RISE_INT_EN - Vbusvalid fall detected interrupt enable
97272  */
97273 #define USB3_OTGIEN_VBUSVALID_RISE_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_VBUSVALID_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_VBUSVALID_RISE_INT_EN_MASK)
97274 #define USB3_OTGIEN_VBUSVALID_FALL_INT_EN_MASK   (0x20U)
97275 #define USB3_OTGIEN_VBUSVALID_FALL_INT_EN_SHIFT  (5U)
97276 /*! VBUSVALID_FALL_INT_EN - Vbusvalid fall detected interrupt enable
97277  */
97278 #define USB3_OTGIEN_VBUSVALID_FALL_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_VBUSVALID_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_VBUSVALID_FALL_INT_EN_MASK)
97279 #define USB3_OTGIEN_SENSE_RISE_INT_EN_MASK       (0x40U)
97280 #define USB3_OTGIEN_SENSE_RISE_INT_EN_SHIFT      (6U)
97281 /*! SENSE_RISE_INT_EN - ADP sense comparator rise detected interrupt enable
97282  */
97283 #define USB3_OTGIEN_SENSE_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SENSE_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_SENSE_RISE_INT_EN_MASK)
97284 #define USB3_OTGIEN_PROBE_RISE_INT_EN_MASK       (0x80U)
97285 #define USB3_OTGIEN_PROBE_RISE_INT_EN_SHIFT      (7U)
97286 /*! PROBE_RISE_INT_EN - ADP probe comparator rise detected interrupt enable
97287  */
97288 #define USB3_OTGIEN_PROBE_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_PROBE_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_PROBE_RISE_INT_EN_MASK)
97289 #define USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_MASK (0x100U)
97290 #define USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_SHIFT (8U)
97291 /*! ADP_PROBE_COMPLETED_INT_EN - ADP probe completed interrupt enable
97292  */
97293 #define USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_SHIFT)) & USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_MASK)
97294 #define USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_MASK (0x200U)
97295 #define USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_SHIFT (9U)
97296 /*! TA_AIDL_BDIS_TMOUT_INT_EN - No response from B-Device for HNP interrupt enable
97297  */
97298 #define USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_MASK)
97299 #define USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_MASK (0x400U)
97300 #define USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_SHIFT (10U)
97301 /*! TA_BIDL_ADIS_TMOUT_INT_EN - No activity from B-Device timeout interrupt enable
97302  */
97303 #define USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_MASK)
97304 #define USB3_OTGIEN_SRP_DET_INT_EN_MASK          (0x800U)
97305 #define USB3_OTGIEN_SRP_DET_INT_EN_SHIFT         (11U)
97306 /*! SRP_DET_INT_EN - SRP pulse detected interrupt enable. NOTE: SRP detection can be enabled only if
97307  *    core is enabled to work as a A-device (OTGSTS.OTG_MODE=0)
97308  */
97309 #define USB3_OTGIEN_SRP_DET_INT_EN(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_DET_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_DET_INT_EN_MASK)
97310 #define USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_MASK (0x1000U)
97311 #define USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_SHIFT (12U)
97312 /*! SRP_NOT_COMP_DEV_REMOVED_INT_EN - Non cmpliant device disconnect interrupt enable
97313  */
97314 #define USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_MASK)
97315 #define USB3_OTGIEN_OVERCURRENT_INT_EN_MASK      (0x2000U)
97316 #define USB3_OTGIEN_OVERCURRENT_INT_EN_SHIFT     (13U)
97317 /*! OVERCURRENT_INT_EN - Overcurrent condition detected interrupt enable
97318  */
97319 #define USB3_OTGIEN_OVERCURRENT_INT_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_OVERCURRENT_INT_EN_SHIFT)) & USB3_OTGIEN_OVERCURRENT_INT_EN_MASK)
97320 #define USB3_OTGIEN_SRP_FAIL_INT_EN_MASK         (0x4000U)
97321 #define USB3_OTGIEN_SRP_FAIL_INT_EN_SHIFT        (14U)
97322 /*! SRP_FAIL_INT_EN - No response from SRP from A-Device interrupt enable
97323  */
97324 #define USB3_OTGIEN_SRP_FAIL_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_FAIL_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_FAIL_INT_EN_MASK)
97325 #define USB3_OTGIEN_SRP_CMPL_INT_EN_MASK         (0x8000U)
97326 #define USB3_OTGIEN_SRP_CMPL_INT_EN_SHIFT        (15U)
97327 /*! SRP_CMPL_INT_EN - SRP completed interrupt enable
97328  */
97329 #define USB3_OTGIEN_SRP_CMPL_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_CMPL_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_CMPL_INT_EN_MASK)
97330 #define USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_MASK (0x10000U)
97331 #define USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_SHIFT (16U)
97332 /*! TB_ASE0_BRST_TMOUT_INT_EN - No response from A-Device to HNP interrupt enable
97333  */
97334 #define USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_MASK)
97335 #define USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_MASK (0x20000U)
97336 #define USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_SHIFT (17U)
97337 /*! TB_AIDL_BDIS_MIN_TMOUT_INT_EN - The bus has been in Idle state for the required time during HNP interrupt enable
97338  */
97339 #define USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_MASK)
97340 #define USB3_OTGIEN_TIMER_TMOUT_INT_EN_MASK      (0x40000U)
97341 #define USB3_OTGIEN_TIMER_TMOUT_INT_EN_SHIFT     (18U)
97342 /*! TIMER_TMOUT_INT_EN - Timer timeout interrupt enable
97343  */
97344 #define USB3_OTGIEN_TIMER_TMOUT_INT_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TIMER_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TIMER_TMOUT_INT_EN_MASK)
97345 #define USB3_OTGIEN_H_POLL_ENTRY_INT_EN_MASK     (0x80000U)
97346 #define USB3_OTGIEN_H_POLL_ENTRY_INT_EN_SHIFT    (19U)
97347 /*! H_POLL_ENTRY_INT_EN - Host Polling state entry interrupt enable
97348  */
97349 #define USB3_OTGIEN_H_POLL_ENTRY_INT_EN(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_H_POLL_ENTRY_INT_EN_SHIFT)) & USB3_OTGIEN_H_POLL_ENTRY_INT_EN_MASK)
97350 #define USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_MASK  (0x100000U)
97351 #define USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_SHIFT (20U)
97352 /*! H_WRST_GEN_CMPL_INT_EN - Host Warm Reset generation completed interrupt enable
97353  */
97354 #define USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_SHIFT)) & USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_MASK)
97355 #define USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_MASK   (0x200000U)
97356 #define USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_SHIFT  (21U)
97357 /*! RID_FLOAT_FALL_INT_EN - RID floating comparator detect interrupt enable
97358  */
97359 #define USB3_OTGIEN_RID_FLOAT_FALL_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_MASK)
97360 #define USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_MASK   (0x400000U)
97361 #define USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_SHIFT  (22U)
97362 /*! RID_FLOAT_RISE_INT_EN - RID floating comparator rise detect interrupt enable
97363  */
97364 #define USB3_OTGIEN_RID_FLOAT_RISE_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_MASK)
97365 #define USB3_OTGIEN_RID_GND_RISE_INT_EN_MASK     (0x800000U)
97366 #define USB3_OTGIEN_RID_GND_RISE_INT_EN_SHIFT    (23U)
97367 /*! RID_GND_RISE_INT_EN - RID GND comparator rise detect interrupt enable
97368  */
97369 #define USB3_OTGIEN_RID_GND_RISE_INT_EN(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_GND_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_GND_RISE_INT_EN_MASK)
97370 #define USB3_OTGIEN_RID_C_RISE_INT_EN_MASK       (0x1000000U)
97371 #define USB3_OTGIEN_RID_C_RISE_INT_EN_SHIFT      (24U)
97372 /*! RID_C_RISE_INT_EN - RID C comparator rise detect interrupt enable
97373  */
97374 #define USB3_OTGIEN_RID_C_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_C_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_C_RISE_INT_EN_MASK)
97375 #define USB3_OTGIEN_RID_B_RISE_INT_EN_MASK       (0x2000000U)
97376 #define USB3_OTGIEN_RID_B_RISE_INT_EN_SHIFT      (25U)
97377 /*! RID_B_RISE_INT_EN - RID B comparator rise detect interrupt enable
97378  */
97379 #define USB3_OTGIEN_RID_B_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_B_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_B_RISE_INT_EN_MASK)
97380 #define USB3_OTGIEN_RID_A_RISE_INT_EN_MASK       (0x4000000U)
97381 #define USB3_OTGIEN_RID_A_RISE_INT_EN_SHIFT      (26U)
97382 /*! RID_A_RISE_INT_EN - RID A comparator rise detect interrupt enable
97383  */
97384 #define USB3_OTGIEN_RID_A_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_A_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_A_RISE_INT_EN_MASK)
97385 #define USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_MASK (0x8000000U)
97386 #define USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_SHIFT (27U)
97387 /*! DM_VDAT_REF_RISE_INT_EN - DM VDAT comparator rise detect interrupt enable
97388  */
97389 #define USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_MASK)
97390 #define USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_MASK (0x10000000U)
97391 #define USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_SHIFT (28U)
97392 /*! DP_VDAT_REF_RISE_INT_EN - DP VDAT comparator rise detect interrupt enable
97393  */
97394 #define USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_MASK)
97395 #define USB3_OTGIEN_DCD_COMP_RISE_INT_EN_MASK    (0x20000000U)
97396 #define USB3_OTGIEN_DCD_COMP_RISE_INT_EN_SHIFT   (29U)
97397 /*! DCD_COMP_RISE_INT_EN - DCD comparator rise detect interrupt enable
97398  */
97399 #define USB3_OTGIEN_DCD_COMP_RISE_INT_EN(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DCD_COMP_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DCD_COMP_RISE_INT_EN_MASK)
97400 #define USB3_OTGIEN_DCD_COMP_FALL_INT_EN_MASK    (0x40000000U)
97401 #define USB3_OTGIEN_DCD_COMP_FALL_INT_EN_SHIFT   (30U)
97402 /*! DCD_COMP_FALL_INT_EN - DCD comparator fall detect interrupt enable
97403  */
97404 #define USB3_OTGIEN_DCD_COMP_FALL_INT_EN(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DCD_COMP_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_DCD_COMP_FALL_INT_EN_MASK)
97405 #define USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_MASK (0x80000000U)
97406 #define USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_SHIFT (31U)
97407 /*! DM_VLGC_COMP_RISE_INT_EN - DM VLGC comparator rise detect interrupt enable
97408  */
97409 #define USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_MASK)
97410 /*! @} */
97411 
97412 /*! @name OTGIVECT - OTG Interrupt Vector */
97413 /*! @{ */
97414 #define USB3_OTGIVECT_ID_CHANGE_INT_MASK         (0x1U)
97415 #define USB3_OTGIVECT_ID_CHANGE_INT_SHIFT        (0U)
97416 /*! ID_CHANGE_INT - ID change interrupt
97417  */
97418 #define USB3_OTGIVECT_ID_CHANGE_INT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_ID_CHANGE_INT_SHIFT)) & USB3_OTGIVECT_ID_CHANGE_INT_MASK)
97419 #define USB3_OTGIVECT_VBUS_ON_FAILED_INT_MASK    (0x2U)
97420 #define USB3_OTGIVECT_VBUS_ON_FAILED_INT_SHIFT   (1U)
97421 /*! VBUS_ON_FAILED_INT - Enabling Vbus by A-Device has failed. This bit should be cleared before enabling subsequent connection as host
97422  */
97423 #define USB3_OTGIVECT_VBUS_ON_FAILED_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_VBUS_ON_FAILED_INT_SHIFT)) & USB3_OTGIVECT_VBUS_ON_FAILED_INT_MASK)
97424 #define USB3_OTGIVECT_OTGSESSVALID_RISE_INT_MASK (0x4U)
97425 #define USB3_OTGIVECT_OTGSESSVALID_RISE_INT_SHIFT (2U)
97426 /*! OTGSESSVALID_RISE_INT - Otgsessvalid rise detected interrupt
97427  */
97428 #define USB3_OTGIVECT_OTGSESSVALID_RISE_INT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_OTGSESSVALID_RISE_INT_SHIFT)) & USB3_OTGIVECT_OTGSESSVALID_RISE_INT_MASK)
97429 #define USB3_OTGIVECT_OTGSESSVALID_FALL_INT_MASK (0x8U)
97430 #define USB3_OTGIVECT_OTGSESSVALID_FALL_INT_SHIFT (3U)
97431 /*! OTGSESSVALID_FALL_INT - Otgsessvalid fall detected interrupt
97432  */
97433 #define USB3_OTGIVECT_OTGSESSVALID_FALL_INT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_OTGSESSVALID_FALL_INT_SHIFT)) & USB3_OTGIVECT_OTGSESSVALID_FALL_INT_MASK)
97434 #define USB3_OTGIVECT_VBUSVALID_RISE_INT_MASK    (0x10U)
97435 #define USB3_OTGIVECT_VBUSVALID_RISE_INT_SHIFT   (4U)
97436 /*! VBUSVALID_RISE_INT - Vbusvalid fall detected interrupt
97437  */
97438 #define USB3_OTGIVECT_VBUSVALID_RISE_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_VBUSVALID_RISE_INT_SHIFT)) & USB3_OTGIVECT_VBUSVALID_RISE_INT_MASK)
97439 #define USB3_OTGIVECT_VBUSVALID_FALL_INT_MASK    (0x20U)
97440 #define USB3_OTGIVECT_VBUSVALID_FALL_INT_SHIFT   (5U)
97441 /*! VBUSVALID_FALL_INT - Vbusvalid fall detected interrupt
97442  */
97443 #define USB3_OTGIVECT_VBUSVALID_FALL_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_VBUSVALID_FALL_INT_SHIFT)) & USB3_OTGIVECT_VBUSVALID_FALL_INT_MASK)
97444 #define USB3_OTGIVECT_SENSE_RISE_INT_MASK        (0x40U)
97445 #define USB3_OTGIVECT_SENSE_RISE_INT_SHIFT       (6U)
97446 /*! SENSE_RISE_INT - ADP sense comparator rise detected interrupt
97447  */
97448 #define USB3_OTGIVECT_SENSE_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SENSE_RISE_INT_SHIFT)) & USB3_OTGIVECT_SENSE_RISE_INT_MASK)
97449 #define USB3_OTGIVECT_PROBE_RISE_INT_MASK        (0x80U)
97450 #define USB3_OTGIVECT_PROBE_RISE_INT_SHIFT       (7U)
97451 /*! PROBE_RISE_INT - ADP probe comparator rise detected interrupt
97452  */
97453 #define USB3_OTGIVECT_PROBE_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_PROBE_RISE_INT_SHIFT)) & USB3_OTGIVECT_PROBE_RISE_INT_MASK)
97454 #define USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_MASK (0x100U)
97455 #define USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_SHIFT (8U)
97456 /*! ADP_PROBE_COMPLETED_INT - ADP completed. Status is reported in OTGADPSTS
97457  */
97458 #define USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_SHIFT)) & USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_MASK)
97459 #define USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_MASK (0x200U)
97460 #define USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_SHIFT (9U)
97461 /*! TA_AIDL_BDIS_TMOUT_INT - No response from B-Device for HNP interrupt
97462  */
97463 #define USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_MASK)
97464 #define USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_MASK (0x400U)
97465 #define USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_SHIFT (10U)
97466 /*! TA_BIDL_ADIS_TMOUT_INT - No activity from B-Device timeout interrupt
97467  */
97468 #define USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_MASK)
97469 #define USB3_OTGIVECT_SRP_DET_INT_MASK           (0x800U)
97470 #define USB3_OTGIVECT_SRP_DET_INT_SHIFT          (11U)
97471 /*! SRP_DET_INT - SRP pulse detected interrupt
97472  */
97473 #define USB3_OTGIVECT_SRP_DET_INT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_DET_INT_SHIFT)) & USB3_OTGIVECT_SRP_DET_INT_MASK)
97474 #define USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_MASK (0x1000U)
97475 #define USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_SHIFT (12U)
97476 /*! SRP_NOT_COMP_DEV_REMOVED_INT - Not cmpliant device disconnect detect interrupt
97477  */
97478 #define USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_SHIFT)) & USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_MASK)
97479 #define USB3_OTGIVECT_OVERCURRENT_INT_MASK       (0x2000U)
97480 #define USB3_OTGIVECT_OVERCURRENT_INT_SHIFT      (13U)
97481 /*! OVERCURRENT_INT - Overcurrent condition detected interrupt
97482  */
97483 #define USB3_OTGIVECT_OVERCURRENT_INT(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_OVERCURRENT_INT_SHIFT)) & USB3_OTGIVECT_OVERCURRENT_INT_MASK)
97484 #define USB3_OTGIVECT_SRP_FAIL_INT_MASK          (0x4000U)
97485 #define USB3_OTGIVECT_SRP_FAIL_INT_SHIFT         (14U)
97486 /*! SRP_FAIL_INT - No response from SRP from A-Device interrupt
97487  */
97488 #define USB3_OTGIVECT_SRP_FAIL_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_FAIL_INT_SHIFT)) & USB3_OTGIVECT_SRP_FAIL_INT_MASK)
97489 #define USB3_OTGIVECT_SRP_CMPL_INT_MASK          (0x8000U)
97490 #define USB3_OTGIVECT_SRP_CMPL_INT_SHIFT         (15U)
97491 /*! SRP_CMPL_INT - SRP completed interrupt
97492  */
97493 #define USB3_OTGIVECT_SRP_CMPL_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_CMPL_INT_SHIFT)) & USB3_OTGIVECT_SRP_CMPL_INT_MASK)
97494 #define USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_MASK (0x10000U)
97495 #define USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_SHIFT (16U)
97496 /*! TB_ASE0_BRST_TMOUT_INT - No response from A-Device to HNP interrupt
97497  */
97498 #define USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_MASK)
97499 #define USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_MASK (0x20000U)
97500 #define USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_SHIFT (17U)
97501 /*! TB_AIDL_BDIS_MIN_TMOUT_INT - The bus has been in Idle state for the required time during HNP interrupt
97502  */
97503 #define USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_MASK)
97504 #define USB3_OTGIVECT_TIMER_TMOUT_INT_MASK       (0x40000U)
97505 #define USB3_OTGIVECT_TIMER_TMOUT_INT_SHIFT      (18U)
97506 /*! TIMER_TMOUT_INT - Timer timeout interrupt
97507  */
97508 #define USB3_OTGIVECT_TIMER_TMOUT_INT(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TIMER_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TIMER_TMOUT_INT_MASK)
97509 #define USB3_OTGIVECT_H_POLLTRY_INT_MASK         (0x80000U)
97510 #define USB3_OTGIVECT_H_POLLTRY_INT_SHIFT        (19U)
97511 /*! H_POLLTRY_INT - Host Polling state entry interrupt
97512  */
97513 #define USB3_OTGIVECT_H_POLLTRY_INT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_H_POLLTRY_INT_SHIFT)) & USB3_OTGIVECT_H_POLLTRY_INT_MASK)
97514 #define USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_MASK   (0x100000U)
97515 #define USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_SHIFT  (20U)
97516 /*! H_WRST_GEN_CMPL_INT - Host Warm Reset generation completed interrupt
97517  */
97518 #define USB3_OTGIVECT_H_WRST_GEN_CMPL_INT(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_SHIFT)) & USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_MASK)
97519 #define USB3_OTGIVECT_RID_FLOAT_FALL_INT_MASK    (0x200000U)
97520 #define USB3_OTGIVECT_RID_FLOAT_FALL_INT_SHIFT   (21U)
97521 /*! RID_FLOAT_FALL_INT - RID floating comparator detect interrupt
97522  */
97523 #define USB3_OTGIVECT_RID_FLOAT_FALL_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_FLOAT_FALL_INT_SHIFT)) & USB3_OTGIVECT_RID_FLOAT_FALL_INT_MASK)
97524 #define USB3_OTGIVECT_RID_FLOAT_RISE_INT_MASK    (0x400000U)
97525 #define USB3_OTGIVECT_RID_FLOAT_RISE_INT_SHIFT   (22U)
97526 /*! RID_FLOAT_RISE_INT - RID floating comparator rise detect interrupt
97527  */
97528 #define USB3_OTGIVECT_RID_FLOAT_RISE_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_FLOAT_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_FLOAT_RISE_INT_MASK)
97529 #define USB3_OTGIVECT_RID_GND_RISE_INT_MASK      (0x800000U)
97530 #define USB3_OTGIVECT_RID_GND_RISE_INT_SHIFT     (23U)
97531 /*! RID_GND_RISE_INT - RID GND comparator rise detect interrupt
97532  */
97533 #define USB3_OTGIVECT_RID_GND_RISE_INT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_GND_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_GND_RISE_INT_MASK)
97534 #define USB3_OTGIVECT_RID_C_RISE_INT_MASK        (0x1000000U)
97535 #define USB3_OTGIVECT_RID_C_RISE_INT_SHIFT       (24U)
97536 /*! RID_C_RISE_INT - RID C comparator rise detect interrupt
97537  */
97538 #define USB3_OTGIVECT_RID_C_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_C_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_C_RISE_INT_MASK)
97539 #define USB3_OTGIVECT_RID_B_RISE_INT_MASK        (0x2000000U)
97540 #define USB3_OTGIVECT_RID_B_RISE_INT_SHIFT       (25U)
97541 /*! RID_B_RISE_INT - RID B comparator rise detect interrupt
97542  */
97543 #define USB3_OTGIVECT_RID_B_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_B_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_B_RISE_INT_MASK)
97544 #define USB3_OTGIVECT_RID_A_RISE_INT_MASK        (0x4000000U)
97545 #define USB3_OTGIVECT_RID_A_RISE_INT_SHIFT       (26U)
97546 /*! RID_A_RISE_INT - RID A comparator rise detect interrupt
97547  */
97548 #define USB3_OTGIVECT_RID_A_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_A_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_A_RISE_INT_MASK)
97549 #define USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_MASK  (0x8000000U)
97550 #define USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_SHIFT (27U)
97551 /*! DM_VDAT_REF_RISE_INT - DM VDAT comparator rise detect interrupt
97552  */
97553 #define USB3_OTGIVECT_DM_VDAT_REF_RISE_INT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_SHIFT)) & USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_MASK)
97554 #define USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_MASK  (0x10000000U)
97555 #define USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_SHIFT (28U)
97556 /*! DP_VDAT_REF_RISE_INT - DP VDAT comparator rise detect interrupt
97557  */
97558 #define USB3_OTGIVECT_DP_VDAT_REF_RISE_INT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_SHIFT)) & USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_MASK)
97559 #define USB3_OTGIVECT_DCD_COMP_RISE_INT_MASK     (0x20000000U)
97560 #define USB3_OTGIVECT_DCD_COMP_RISE_INT_SHIFT    (29U)
97561 /*! DCD_COMP_RISE_INT - DCD comparator rise detect interrupt
97562  */
97563 #define USB3_OTGIVECT_DCD_COMP_RISE_INT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DCD_COMP_RISE_INT_SHIFT)) & USB3_OTGIVECT_DCD_COMP_RISE_INT_MASK)
97564 #define USB3_OTGIVECT_DCD_COMP_FALL_INT_MASK     (0x40000000U)
97565 #define USB3_OTGIVECT_DCD_COMP_FALL_INT_SHIFT    (30U)
97566 /*! DCD_COMP_FALL_INT - DCD comparator fall detect interrupt
97567  */
97568 #define USB3_OTGIVECT_DCD_COMP_FALL_INT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DCD_COMP_FALL_INT_SHIFT)) & USB3_OTGIVECT_DCD_COMP_FALL_INT_MASK)
97569 #define USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_MASK (0x80000000U)
97570 #define USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_SHIFT (31U)
97571 /*! DM_VLGC_COMP_RISE_INT - DM VLGC comparator rise detect interrupt
97572  */
97573 #define USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_SHIFT)) & USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_MASK)
97574 /*! @} */
97575 
97576 /*! @name CLK_FREQ - Clock Frequency */
97577 /*! @{ */
97578 #define USB3_CLK_FREQ_CLK_FREQ_MHZ_MASK          (0xFFFFU)
97579 #define USB3_CLK_FREQ_CLK_FREQ_MHZ_SHIFT         (0U)
97580 /*! CLK_FREQ_MHZ - CLK_FREQ_MHZ defines how many cycles are needed to determine 1 us clock base for
97581  *    fast clock Example: Let's say that fast clock frequency is 12MHz. With CLK_FREQ_MHZ set to 12
97582  *    time base would be 12 cycles of 12Mhz clock which gives 1 us
97583  */
97584 #define USB3_CLK_FREQ_CLK_FREQ_MHZ(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CLK_FREQ_CLK_FREQ_MHZ_SHIFT)) & USB3_CLK_FREQ_CLK_FREQ_MHZ_MASK)
97585 #define USB3_CLK_FREQ_CLK_FREQ_KHZ_MASK          (0xFFFF0000U)
97586 #define USB3_CLK_FREQ_CLK_FREQ_KHZ_SHIFT         (16U)
97587 /*! CLK_FREQ_KHZ - CLK_FREQ_KHZ defines how many cycles are needed to determine 1 ms clock base for
97588  *    stb_clk_predft. Example: Let's say that stb_clk_predft frequency is 32kHz. With CLK_FREQ_KHZ
97589  *    set to 32 time base would be 32 cycles of 32khz clock which gives 1 ms
97590  */
97591 #define USB3_CLK_FREQ_CLK_FREQ_KHZ(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CLK_FREQ_CLK_FREQ_KHZ_SHIFT)) & USB3_CLK_FREQ_CLK_FREQ_KHZ_MASK)
97592 /*! @} */
97593 
97594 /*! @name OTGTMR - OTG Timer */
97595 /*! @{ */
97596 #define USB3_OTGTMR_TIMEOUT_VALUE_MASK           (0xFFFFU)
97597 #define USB3_OTGTMR_TIMEOUT_VALUE_SHIFT          (0U)
97598 /*! TIMEOUT_VALUE - Timeout value for timer. Valid only if TIMER_WRITE is 1
97599  */
97600 #define USB3_OTGTMR_TIMEOUT_VALUE(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMEOUT_VALUE_SHIFT)) & USB3_OTGTMR_TIMEOUT_VALUE_MASK)
97601 #define USB3_OTGTMR_TIMEOUT_UNITS_MASK           (0x30000U)
97602 #define USB3_OTGTMR_TIMEOUT_UNITS_SHIFT          (16U)
97603 /*! TIMEOUT_UNITS - Time units
97604  *  0b00..hundreds of microseconds (valid only if otg controller clock is in MHz range)
97605  *  0b01..milliseconds
97606  *  0b10..tens of milliseconds
97607  *  0b11..hundreds of milliseconds, Valid only if TIMER_WRITE is 1
97608  */
97609 #define USB3_OTGTMR_TIMEOUT_UNITS(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMEOUT_UNITS_SHIFT)) & USB3_OTGTMR_TIMEOUT_UNITS_MASK)
97610 #define USB3_OTGTMR_TIMER_WRITE_MASK             (0x40000U)
97611 #define USB3_OTGTMR_TIMER_WRITE_SHIFT            (18U)
97612 /*! TIMER_WRITE - Timer value and units write strobe
97613  */
97614 #define USB3_OTGTMR_TIMER_WRITE(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMER_WRITE_SHIFT)) & USB3_OTGTMR_TIMER_WRITE_MASK)
97615 #define USB3_OTGTMR_TIMER_START_MASK             (0x80000U)
97616 #define USB3_OTGTMR_TIMER_START_SHIFT            (19U)
97617 /*! TIMER_START - Start timer
97618  */
97619 #define USB3_OTGTMR_TIMER_START(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMER_START_SHIFT)) & USB3_OTGTMR_TIMER_START_MASK)
97620 #define USB3_OTGTMR_TIMER_STOP_MASK              (0x100000U)
97621 #define USB3_OTGTMR_TIMER_STOP_SHIFT             (20U)
97622 /*! TIMER_STOP - Stop timer
97623  */
97624 #define USB3_OTGTMR_TIMER_STOP(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMER_STOP_SHIFT)) & USB3_OTGTMR_TIMER_STOP_MASK)
97625 /*! @} */
97626 
97627 /*! @name OTGVERSION - OTG Version */
97628 /*! @{ */
97629 #define USB3_OTGVERSION_OTGVERSION_MASK          (0xFFFFU)
97630 #define USB3_OTGVERSION_OTGVERSION_SHIFT         (0U)
97631 /*! OTGVERSION - OTG core revision
97632  */
97633 #define USB3_OTGVERSION_OTGVERSION(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGVERSION_OTGVERSION_SHIFT)) & USB3_OTGVERSION_OTGVERSION_MASK)
97634 /*! @} */
97635 
97636 /*! @name OTGCAPABILITY - OTG Capability */
97637 /*! @{ */
97638 #define USB3_OTGCAPABILITY_SRP_SUPPORT_MASK      (0x1U)
97639 #define USB3_OTGCAPABILITY_SRP_SUPPORT_SHIFT     (0U)
97640 /*! SRP_SUPPORT - SRP support. 0 - SRP not supported 1 - SRP supported
97641  */
97642 #define USB3_OTGCAPABILITY_SRP_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_SRP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_SRP_SUPPORT_MASK)
97643 #define USB3_OTGCAPABILITY_HNP_SUPPORT_MASK      (0x2U)
97644 #define USB3_OTGCAPABILITY_HNP_SUPPORT_SHIFT     (1U)
97645 /*! HNP_SUPPORT - HNP support. 0 - HNP not supported 1 - HNP supported
97646  */
97647 #define USB3_OTGCAPABILITY_HNP_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_HNP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_HNP_SUPPORT_MASK)
97648 #define USB3_OTGCAPABILITY_ADP_SUPPORT_MASK      (0x4U)
97649 #define USB3_OTGCAPABILITY_ADP_SUPPORT_SHIFT     (2U)
97650 /*! ADP_SUPPORT - ADP support. 0 - ADP not supported 1 - ADP supported
97651  */
97652 #define USB3_OTGCAPABILITY_ADP_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_ADP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_ADP_SUPPORT_MASK)
97653 #define USB3_OTGCAPABILITY_BC_SUPPORT_MASK       (0x8U)
97654 #define USB3_OTGCAPABILITY_BC_SUPPORT_SHIFT      (3U)
97655 /*! BC_SUPPORT - BC Support (Battery Charging specification rev 1.2). 0 - BC not supported 1 - BC supported
97656  */
97657 #define USB3_OTGCAPABILITY_BC_SUPPORT(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_BC_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_BC_SUPPORT_MASK)
97658 #define USB3_OTGCAPABILITY_RSP_SUPPORT_MASK      (0x10U)
97659 #define USB3_OTGCAPABILITY_RSP_SUPPORT_SHIFT     (4U)
97660 /*! RSP_SUPPORT - RSP support. 0 - RSP not supported 1 - RSP supported
97661  */
97662 #define USB3_OTGCAPABILITY_RSP_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_RSP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_RSP_SUPPORT_MASK)
97663 #define USB3_OTGCAPABILITY_OTG2REVISION_MASK     (0xFFF00U)
97664 #define USB3_OTGCAPABILITY_OTG2REVISION_SHIFT    (8U)
97665 /*! OTG2REVISION - Specifies implemeted OTG2.0 specification revision
97666  */
97667 #define USB3_OTGCAPABILITY_OTG2REVISION(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_OTG2REVISION_SHIFT)) & USB3_OTGCAPABILITY_OTG2REVISION_MASK)
97668 #define USB3_OTGCAPABILITY_OTG3REVISION_MASK     (0xFFF00000U)
97669 #define USB3_OTGCAPABILITY_OTG3REVISION_SHIFT    (20U)
97670 /*! OTG3REVISION - Specifies implemeted OTG3.0 specification revision
97671  */
97672 #define USB3_OTGCAPABILITY_OTG3REVISION(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_OTG3REVISION_SHIFT)) & USB3_OTGCAPABILITY_OTG3REVISION_MASK)
97673 /*! @} */
97674 
97675 /*! @name OTGSIMULATE - OTG Simulate */
97676 /*! @{ */
97677 #define USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_MASK  (0x1U)
97678 #define USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_SHIFT (0U)
97679 /*! OTG_CFG_FAST_SIMS - Debug Feature. This bit is for simulation modes only. It enables reductions
97680  *    to OTG timings. '0': Normal timings '1': Enable fast simulation timing modes This bit should
97681  *    be written '0' in normal operation
97682  */
97683 #define USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_SHIFT)) & USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_MASK)
97684 /*! @} */
97685 
97686 /*! @name OTGANASTS - OTG Attach Detection Protocol BC Status */
97687 /*! @{ */
97688 #define USB3_OTGANASTS_dp_vdat_ref_comp_sts_MASK (0x1U)
97689 #define USB3_OTGANASTS_dp_vdat_ref_comp_sts_SHIFT (0U)
97690 /*! dp_vdat_ref_comp_sts - 1: DP > VDAT_REF Detected 0: DP < VDAT_REF Detected Note: This status
97691  *    shall be re-used from the single ended receiver output of D+ whenever dp_vdat_ref_comp_en is '1'
97692  */
97693 #define USB3_OTGANASTS_dp_vdat_ref_comp_sts(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dp_vdat_ref_comp_sts_SHIFT)) & USB3_OTGANASTS_dp_vdat_ref_comp_sts_MASK)
97694 #define USB3_OTGANASTS_dm_vdat_ref_comp_sts_MASK (0x2U)
97695 #define USB3_OTGANASTS_dm_vdat_ref_comp_sts_SHIFT (1U)
97696 /*! dm_vdat_ref_comp_sts - 1: DM > VDAT_REF Detected 0: DM < VDAT_REF Detected Note: This status
97697  *    shall be re-used from the single ended receiver output of D- whenever dm_vdat_ref_comp_en is '1'
97698  */
97699 #define USB3_OTGANASTS_dm_vdat_ref_comp_sts(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dm_vdat_ref_comp_sts_SHIFT)) & USB3_OTGANASTS_dm_vdat_ref_comp_sts_MASK)
97700 #define USB3_OTGANASTS_dm_vlgc_comp_sts_MASK     (0x4U)
97701 #define USB3_OTGANASTS_dm_vlgc_comp_sts_SHIFT    (2U)
97702 /*! dm_vlgc_comp_sts - 1: DM > VLGC Detected 0: DM < VLGC Detected Note: This status shall be
97703  *    re-used from the single ended receiver output of D- whenever dm_vlgc_comp_en is '1'
97704  */
97705 #define USB3_OTGANASTS_dm_vlgc_comp_sts(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dm_vlgc_comp_sts_SHIFT)) & USB3_OTGANASTS_dm_vlgc_comp_sts_MASK)
97706 #define USB3_OTGANASTS_dcd_comp_sts_MASK         (0x8U)
97707 #define USB3_OTGANASTS_dcd_comp_sts_SHIFT        (3U)
97708 /*! dcd_comp_sts - Data Contact Detect (DCD) Comparator Status 1: DP line is asserted 0: DP line is not asserted
97709  */
97710 #define USB3_OTGANASTS_dcd_comp_sts(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dcd_comp_sts_SHIFT)) & USB3_OTGANASTS_dcd_comp_sts_MASK)
97711 #define USB3_OTGANASTS_otgsessvalid_MASK         (0x10U)
97712 #define USB3_OTGANASTS_otgsessvalid_SHIFT        (4U)
97713 /*! otgsessvalid - B-Peripheral is Valid: Indicates if the session for a B-Peripheral is valid (0.8V
97714  *    < VTH < 4.0V). The signal bvalid from OTG 1.3 is now renamed as otgsessvalid. 0: VBUS < 0.8V
97715  *    1: VBUS > 4.0V
97716  */
97717 #define USB3_OTGANASTS_otgsessvalid(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_otgsessvalid_SHIFT)) & USB3_OTGANASTS_otgsessvalid_MASK)
97718 #define USB3_OTGANASTS_adp_probe_ana_MASK        (0x20U)
97719 #define USB3_OTGANASTS_adp_probe_ana_SHIFT       (5U)
97720 /*! adp_probe_ana - Output of ADP Probe Comparator. 0: VBUS < 0.6V 1: VBUS > 0.75V
97721  */
97722 #define USB3_OTGANASTS_adp_probe_ana(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_adp_probe_ana_SHIFT)) & USB3_OTGANASTS_adp_probe_ana_MASK)
97723 #define USB3_OTGANASTS_adp_sense_ana_MASK        (0x40U)
97724 #define USB3_OTGANASTS_adp_sense_ana_SHIFT       (6U)
97725 /*! adp_sense_ana - Output of ADP Sense Comparator. 0: VBUS < 0.2V 1: VBUS > 0.55V
97726  */
97727 #define USB3_OTGANASTS_adp_sense_ana(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_adp_sense_ana_SHIFT)) & USB3_OTGANASTS_adp_sense_ana_MASK)
97728 #define USB3_OTGANASTS_sessend_MASK              (0x80U)
97729 #define USB3_OTGANASTS_sessend_SHIFT             (7U)
97730 /*! sessend - VBUS Valid: Indicates if the voltage on VBUS is at a valid level for operation (4.4V <
97731  *    VTH < 4.75V). 0: VBUS < 4.4V 1: VBUS > 4.75V
97732  */
97733 #define USB3_OTGANASTS_sessend(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_sessend_SHIFT)) & USB3_OTGANASTS_sessend_MASK)
97734 #define USB3_OTGANASTS_rid_float_comp_sts_MASK   (0x100U)
97735 #define USB3_OTGANASTS_rid_float_comp_sts_SHIFT  (8U)
97736 /*! rid_float_comp_sts - RID float comparator status 1: RID_FLOAT Detected on ID Pin 0: RID_FLOAT not Detected on ID Pin
97737  */
97738 #define USB3_OTGANASTS_rid_float_comp_sts(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_float_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_float_comp_sts_MASK)
97739 #define USB3_OTGANASTS_rid_gnd_comp_sts_MASK     (0x200U)
97740 #define USB3_OTGANASTS_rid_gnd_comp_sts_SHIFT    (9U)
97741 /*! rid_gnd_comp_sts - RID GND comparator status 1: RID_GND Detected on ID Pin 0: RID_GND not Detected on ID Pin
97742  */
97743 #define USB3_OTGANASTS_rid_gnd_comp_sts(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_gnd_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_gnd_comp_sts_MASK)
97744 #define USB3_OTGANASTS_rid_c_comp_sts_MASK       (0x400U)
97745 #define USB3_OTGANASTS_rid_c_comp_sts_SHIFT      (10U)
97746 /*! rid_c_comp_sts - RID C comparator status 1: RID_C Detected on ID Pin 0: RID_C not Detected on ID Pin
97747  */
97748 #define USB3_OTGANASTS_rid_c_comp_sts(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_c_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_c_comp_sts_MASK)
97749 #define USB3_OTGANASTS_rid_b_comp_sts_MASK       (0x800U)
97750 #define USB3_OTGANASTS_rid_b_comp_sts_SHIFT      (11U)
97751 /*! rid_b_comp_sts - RID B comparator status 1: RID_B Detected on ID Pin 0: RID_B not Detected on ID Pin
97752  */
97753 #define USB3_OTGANASTS_rid_b_comp_sts(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_b_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_b_comp_sts_MASK)
97754 #define USB3_OTGANASTS_rid_a_comp_sts_MASK       (0x1000U)
97755 #define USB3_OTGANASTS_rid_a_comp_sts_SHIFT      (12U)
97756 /*! rid_a_comp_sts - RID A comparator status 1: RID_A Detected on ID Pin 0: RID_A not Detected on ID Pin
97757  */
97758 #define USB3_OTGANASTS_rid_a_comp_sts(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_a_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_a_comp_sts_MASK)
97759 #define USB3_OTGANASTS_iddig_MASK                (0x2000U)
97760 #define USB3_OTGANASTS_iddig_SHIFT               (13U)
97761 /*! iddig - ID Pin Status: Indicates whether the connected USB plug is Micro-A or Micro-B. This is
97762  *    only valid when idpullup is set to '1'. It must be valid within 50ms after idpullup is set to
97763  *    '1'. 0: Connected plug is a Micro-A 1: Connected plug is a Micro-B
97764  */
97765 #define USB3_OTGANASTS_iddig(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_iddig_SHIFT)) & USB3_OTGANASTS_iddig_MASK)
97766 #define USB3_OTGANASTS_linestate_MASK            (0xC000U)
97767 #define USB3_OTGANASTS_linestate_SHIFT           (14U)
97768 /*! linestate - Line State: These signals reflect the current state of the single ended receivers.
97769  *    They are combinatorial until a 'usable' sieclock is available, then they are synchronized to
97770  *    sieclock. They reflect the current state of the DP (linestate [0]) and DM (linestate [1])
97771  *    signals. 00: SE0 (Single Ended Zero) 01: 'J' State 10: 'K' State 11: SE1 (Single Ended One)
97772  */
97773 #define USB3_OTGANASTS_linestate(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_linestate_SHIFT)) & USB3_OTGANASTS_linestate_MASK)
97774 #define USB3_OTGANASTS_rid_float_MASK            (0x10000U)
97775 #define USB3_OTGANASTS_rid_float_SHIFT           (16U)
97776 /*! rid_float - RID float status reg
97777  */
97778 #define USB3_OTGANASTS_rid_float(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_float_SHIFT)) & USB3_OTGANASTS_rid_float_MASK)
97779 #define USB3_OTGANASTS_rid_gnd_MASK              (0x20000U)
97780 #define USB3_OTGANASTS_rid_gnd_SHIFT             (17U)
97781 /*! rid_gnd - RID GND status reg
97782  */
97783 #define USB3_OTGANASTS_rid_gnd(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_gnd_SHIFT)) & USB3_OTGANASTS_rid_gnd_MASK)
97784 #define USB3_OTGANASTS_rid_c_MASK                (0x40000U)
97785 #define USB3_OTGANASTS_rid_c_SHIFT               (18U)
97786 /*! rid_c - RID C status reg
97787  */
97788 #define USB3_OTGANASTS_rid_c(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_c_SHIFT)) & USB3_OTGANASTS_rid_c_MASK)
97789 #define USB3_OTGANASTS_rid_b_MASK                (0x80000U)
97790 #define USB3_OTGANASTS_rid_b_SHIFT               (19U)
97791 /*! rid_b - RID B status reg
97792  */
97793 #define USB3_OTGANASTS_rid_b(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_b_SHIFT)) & USB3_OTGANASTS_rid_b_MASK)
97794 #define USB3_OTGANASTS_rid_a_MASK                (0x100000U)
97795 #define USB3_OTGANASTS_rid_a_SHIFT               (20U)
97796 /*! rid_a - RID A status reg
97797  */
97798 #define USB3_OTGANASTS_rid_a(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_a_SHIFT)) & USB3_OTGANASTS_rid_a_MASK)
97799 #define USB3_OTGANASTS_adp_chrg_tmout_det_MASK   (0x1000000U)
97800 #define USB3_OTGANASTS_adp_chrg_tmout_det_SHIFT  (24U)
97801 /*! adp_chrg_tmout_det - ADP charge timeout detected
97802  */
97803 #define USB3_OTGANASTS_adp_chrg_tmout_det(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_adp_chrg_tmout_det_SHIFT)) & USB3_OTGANASTS_adp_chrg_tmout_det_MASK)
97804 /*! @} */
97805 
97806 /*! @name ADP_RAMP_TIME - Attach Detection Protocol Ramp Time */
97807 /*! @{ */
97808 #define USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_MASK    (0xFFFFFFFFU)
97809 #define USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_SHIFT   (0U)
97810 /*! ADP_RAMP_TIME - ADP ramp time measurement value. Software should read this register upon ADP_PROBE_COMPLETED_INT_EN interrupt detection
97811  */
97812 #define USB3_ADP_RAMP_TIME_ADP_RAMP_TIME(x)      (((uint32_t)(((uint32_t)(x)) << USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_SHIFT)) & USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_MASK)
97813 /*! @} */
97814 
97815 /*! @name OTGCTRL1 - OTG Control */
97816 /*! @{ */
97817 #define USB3_OTGCTRL1_adp_en_MASK                (0x1U)
97818 #define USB3_OTGCTRL1_adp_en_SHIFT               (0U)
97819 /*! adp_en - ADP Feature Enable. This signal is the master enable for all the ADP PHY logics. 0: ADP
97820  *    Logics are powered OFF 1: ADP Logics are powered ON
97821  */
97822 #define USB3_OTGCTRL1_adp_en(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_en_SHIFT)) & USB3_OTGCTRL1_adp_en_MASK)
97823 #define USB3_OTGCTRL1_adp_probe_en_MASK          (0x2U)
97824 #define USB3_OTGCTRL1_adp_probe_en_SHIFT         (1U)
97825 /*! adp_probe_en - This signal enables the probe mode of the ADP. During this mode, probe
97826  *    comparators and the current sources will be ON based on the source and sink current enables. 0: ADP
97827  *    Probe Mode OFF 1: ADP Probe Mode ON
97828  */
97829 #define USB3_OTGCTRL1_adp_probe_en(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_probe_en_SHIFT)) & USB3_OTGCTRL1_adp_probe_en_MASK)
97830 #define USB3_OTGCTRL1_adp_sense_en_MASK          (0x4U)
97831 #define USB3_OTGCTRL1_adp_sense_en_SHIFT         (2U)
97832 /*! adp_sense_en - This signal enables the probe mode of the ADP. During this mode, sense
97833  *    comparators and the current sources will be ON based on the source and sink current enables. 0: ADP
97834  *    Probe Sense OFF 1: ADP Probe Sense ON
97835  */
97836 #define USB3_OTGCTRL1_adp_sense_en(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_sense_en_SHIFT)) & USB3_OTGCTRL1_adp_sense_en_MASK)
97837 #define USB3_OTGCTRL1_adp_sink_current_en_MASK   (0x8U)
97838 #define USB3_OTGCTRL1_adp_sink_current_en_SHIFT  (3U)
97839 /*! adp_sink_current_en - When this signal is high, VBUS is discharged to ground. This signal should
97840  *    be asserted 5us after the assertion of adp_en. 0: ADP Sink Current Enable OFF 1: ADP Sink
97841  *    Current Enable ON
97842  */
97843 #define USB3_OTGCTRL1_adp_sink_current_en(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_sink_current_en_SHIFT)) & USB3_OTGCTRL1_adp_sink_current_en_MASK)
97844 #define USB3_OTGCTRL1_adp_source_current_en_MASK (0x10U)
97845 #define USB3_OTGCTRL1_adp_source_current_en_SHIFT (4U)
97846 /*! adp_source_current_en - When this signal is high, VBUS is charged to the probe threshold
97847  *    (0.75V). This signal should be asserted 5us after the assertion of adp_en. 0: ADP Source Current
97848  *    Enable OFF 1: ADP Source Current Enable ON
97849  */
97850 #define USB3_OTGCTRL1_adp_source_current_en(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_source_current_en_SHIFT)) & USB3_OTGCTRL1_adp_source_current_en_MASK)
97851 #define USB3_OTGCTRL1_do_adp_prb_MASK            (0x20U)
97852 #define USB3_OTGCTRL1_do_adp_prb_SHIFT           (5U)
97853 /*! do_adp_prb - ADP probing enable in automated mode
97854  */
97855 #define USB3_OTGCTRL1_do_adp_prb(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_do_adp_prb_SHIFT)) & USB3_OTGCTRL1_do_adp_prb_MASK)
97856 #define USB3_OTGCTRL1_do_adp_sns_MASK            (0x40U)
97857 #define USB3_OTGCTRL1_do_adp_sns_SHIFT           (6U)
97858 /*! do_adp_sns - ADP sensing enable in automated mode
97859  */
97860 #define USB3_OTGCTRL1_do_adp_sns(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_do_adp_sns_SHIFT)) & USB3_OTGCTRL1_do_adp_sns_MASK)
97861 #define USB3_OTGCTRL1_adp_auto_MASK              (0x80U)
97862 #define USB3_OTGCTRL1_adp_auto_SHIFT             (7U)
97863 /*! adp_auto - ADP mode. If set to 1 ADP probing is controlled by internal FSM. If set to 0 then software should control ADP sequence
97864  */
97865 #define USB3_OTGCTRL1_adp_auto(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_auto_SHIFT)) & USB3_OTGCTRL1_adp_auto_MASK)
97866 #define USB3_OTGCTRL1_bc_en_MASK                 (0x100U)
97867 #define USB3_OTGCTRL1_bc_en_SHIFT                (8U)
97868 /*! bc_en - Battery Charging Circuits Master Enable. 1: BC Enabled 0: BC Disabled
97869  */
97870 #define USB3_OTGCTRL1_bc_en(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_en_SHIFT)) & USB3_OTGCTRL1_bc_en_MASK)
97871 #define USB3_OTGCTRL1_idm_sink_en_MASK           (0x200U)
97872 #define USB3_OTGCTRL1_idm_sink_en_SHIFT          (9U)
97873 /*! idm_sink_en - 1: Current Sink on DM Enabled 0: Current Sink on DM Disabled
97874  */
97875 #define USB3_OTGCTRL1_idm_sink_en(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idm_sink_en_SHIFT)) & USB3_OTGCTRL1_idm_sink_en_MASK)
97876 #define USB3_OTGCTRL1_idp_sink_en_MASK           (0x400U)
97877 #define USB3_OTGCTRL1_idp_sink_en_SHIFT          (10U)
97878 /*! idp_sink_en - 1: Current Sink on DP Enabled 0: Current Sink on DP Disabled
97879  */
97880 #define USB3_OTGCTRL1_idp_sink_en(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idp_sink_en_SHIFT)) & USB3_OTGCTRL1_idp_sink_en_MASK)
97881 #define USB3_OTGCTRL1_idp_src_en_MASK            (0x800U)
97882 #define USB3_OTGCTRL1_idp_src_en_SHIFT           (11U)
97883 /*! idp_src_en - 1: Current Source on DP Enabled 0: Current Source on DP Disabled
97884  */
97885 #define USB3_OTGCTRL1_idp_src_en(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idp_src_en_SHIFT)) & USB3_OTGCTRL1_idp_src_en_MASK)
97886 #define USB3_OTGCTRL1_vdm_src_en_MASK            (0x1000U)
97887 #define USB3_OTGCTRL1_vdm_src_en_SHIFT           (12U)
97888 /*! vdm_src_en - 1: Voltage Source on DM Enabled 0: Voltage Source on DM Disabled
97889  */
97890 #define USB3_OTGCTRL1_vdm_src_en(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_vdm_src_en_SHIFT)) & USB3_OTGCTRL1_vdm_src_en_MASK)
97891 #define USB3_OTGCTRL1_vdp_src_en_MASK            (0x2000U)
97892 #define USB3_OTGCTRL1_vdp_src_en_SHIFT           (13U)
97893 /*! vdp_src_en - 1: Voltage Source on DP Enabled 0: Voltage Source on DP Disabled
97894  */
97895 #define USB3_OTGCTRL1_vdp_src_en(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_vdp_src_en_SHIFT)) & USB3_OTGCTRL1_vdp_src_en_MASK)
97896 #define USB3_OTGCTRL1_dm_vdat_ref_comp_en_MASK   (0x10000U)
97897 #define USB3_OTGCTRL1_dm_vdat_ref_comp_en_SHIFT  (16U)
97898 /*! dm_vdat_ref_comp_en - 1: DM to VDAT_REF Comparator Enabled 0: DM to VDAT_REF Comparator Disabled
97899  */
97900 #define USB3_OTGCTRL1_dm_vdat_ref_comp_en(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_dm_vdat_ref_comp_en_SHIFT)) & USB3_OTGCTRL1_dm_vdat_ref_comp_en_MASK)
97901 #define USB3_OTGCTRL1_dm_vlgc_comp_en_MASK       (0x20000U)
97902 #define USB3_OTGCTRL1_dm_vlgc_comp_en_SHIFT      (17U)
97903 /*! dm_vlgc_comp_en - 1: DM to VLGC Comparator Enabled 0: DM to VLGC Comparator Disabled
97904  */
97905 #define USB3_OTGCTRL1_dm_vlgc_comp_en(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_dm_vlgc_comp_en_SHIFT)) & USB3_OTGCTRL1_dm_vlgc_comp_en_MASK)
97906 #define USB3_OTGCTRL1_dp_vdat_ref_comp_en_MASK   (0x40000U)
97907 #define USB3_OTGCTRL1_dp_vdat_ref_comp_en_SHIFT  (18U)
97908 /*! dp_vdat_ref_comp_en - 1: DP to VDAT_REF Comparator Enabled 0: DP to VDAT_REF Comparator Disabled
97909  */
97910 #define USB3_OTGCTRL1_dp_vdat_ref_comp_en(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_dp_vdat_ref_comp_en_SHIFT)) & USB3_OTGCTRL1_dp_vdat_ref_comp_en_MASK)
97911 #define USB3_OTGCTRL1_rid_float_comp_en_MASK     (0x80000U)
97912 #define USB3_OTGCTRL1_rid_float_comp_en_SHIFT    (19U)
97913 /*! rid_float_comp_en - 1: RID Float Comparator Enabled 0: RID Float Comparator Disabled Note: This
97914  *    ID Comparator enable is used to detect whether the ID line is floating or non-floating. If it
97915  *    is identified to be non-floating, then rid_nonfloat_comp_en is enabled to check for RID_A or
97916  *    RID_B or RID_C or RID_GND
97917  */
97918 #define USB3_OTGCTRL1_rid_float_comp_en(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_rid_float_comp_en_SHIFT)) & USB3_OTGCTRL1_rid_float_comp_en_MASK)
97919 #define USB3_OTGCTRL1_rid_nonfloat_comp_en_MASK  (0x100000U)
97920 #define USB3_OTGCTRL1_rid_nonfloat_comp_en_SHIFT (20U)
97921 /*! rid_nonfloat_comp_en - 1: RID Non-Float Comparator Enabled 0: RID Non-Float Comparator Disabled
97922  *    Note: This ID Comparator enable is used to detect the presence of RID_A or RID_B or RID_C or
97923  *    RID_GND when the ID pin is non-floating
97924  */
97925 #define USB3_OTGCTRL1_rid_nonfloat_comp_en(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_rid_nonfloat_comp_en_SHIFT)) & USB3_OTGCTRL1_rid_nonfloat_comp_en_MASK)
97926 #define USB3_OTGCTRL1_bc_dmpulldown_MASK         (0x200000U)
97927 #define USB3_OTGCTRL1_bc_dmpulldown_SHIFT        (21U)
97928 /*! bc_dmpulldown - BC dmpulldown enable
97929  */
97930 #define USB3_OTGCTRL1_bc_dmpulldown(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_dmpulldown_SHIFT)) & USB3_OTGCTRL1_bc_dmpulldown_MASK)
97931 #define USB3_OTGCTRL1_bc_dppulldown_MASK         (0x400000U)
97932 #define USB3_OTGCTRL1_bc_dppulldown_SHIFT        (22U)
97933 /*! bc_dppulldown - BC dppulldown enable
97934  */
97935 #define USB3_OTGCTRL1_bc_dppulldown(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_dppulldown_SHIFT)) & USB3_OTGCTRL1_bc_dppulldown_MASK)
97936 #define USB3_OTGCTRL1_bc_pulldownctrl_MASK       (0x800000U)
97937 #define USB3_OTGCTRL1_bc_pulldownctrl_SHIFT      (23U)
97938 /*! bc_pulldownctrl - BC pulldowncotrol 1: puldowns are controlled by bc_dppulldown and bc_dmpulldown 0: puldowns are controlled by OTG
97939  */
97940 #define USB3_OTGCTRL1_bc_pulldownctrl(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_pulldownctrl_SHIFT)) & USB3_OTGCTRL1_bc_pulldownctrl_MASK)
97941 #define USB3_OTGCTRL1_idpullup_MASK              (0x1000000U)
97942 #define USB3_OTGCTRL1_idpullup_SHIFT             (24U)
97943 /*! idpullup - ID Pin Sample Enable: Active High. Signal that enables the sampling of the analog ID
97944  *    line. 0: Sampling of ID pin is disabled, iddig is not valid 1: Sampling of ID pin is enabled
97945  */
97946 #define USB3_OTGCTRL1_idpullup(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idpullup_SHIFT)) & USB3_OTGCTRL1_idpullup_MASK)
97947 #define USB3_OTGCTRL1_drive_vbus_sel_MASK        (0x2000000U)
97948 #define USB3_OTGCTRL1_drive_vbus_sel_SHIFT       (25U)
97949 /*! drive_vbus_sel - VBUS drive control select. This register allows SW driver take control over
97950  *    drive_vbus as follows: 0: drive_vbus controlled from OTG controller 1: drive_vbus controlled from
97951  *    SFR
97952  */
97953 #define USB3_OTGCTRL1_drive_vbus_sel(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_drive_vbus_sel_SHIFT)) & USB3_OTGCTRL1_drive_vbus_sel_MASK)
97954 #define USB3_OTGCTRL1_drive_vbus_sfr_MASK        (0x4000000U)
97955 #define USB3_OTGCTRL1_drive_vbus_sfr_SHIFT       (26U)
97956 /*! drive_vbus_sfr - SFR drive_vbus control. 0: drive_vbus = 0 1: drive_vbus = 1 This bit is valid
97957  *    only with OTGCTRL1.drive_vbus_sel set to '1'. This bit is auto-cleared upon over-current
97958  *    condition
97959  */
97960 #define USB3_OTGCTRL1_drive_vbus_sfr(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_drive_vbus_sfr_SHIFT)) & USB3_OTGCTRL1_drive_vbus_sfr_MASK)
97961 #define USB3_OTGCTRL1_force_opmode01_MASK        (0x8000000U)
97962 #define USB3_OTGCTRL1_force_opmode01_SHIFT       (27U)
97963 /*! force_opmode01 - with both cores disabled seting this bit to '1' will result with forcing UTMI opmode set to 2'b01 (non-driving)
97964  */
97965 #define USB3_OTGCTRL1_force_opmode01(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_force_opmode01_SHIFT)) & USB3_OTGCTRL1_force_opmode01_MASK)
97966 /*! @} */
97967 
97968 /*! @name OTGCTRL2 - OTG Control */
97969 /*! @{ */
97970 #define USB3_OTGCTRL2_TA_ADP_PRB_MASK            (0xFFU)
97971 #define USB3_OTGCTRL2_TA_ADP_PRB_SHIFT           (0U)
97972 /*! TA_ADP_PRB - A-device ADP probing period. TA_ADP_PRB = {reg_value} * 10 ms
97973  */
97974 #define USB3_OTGCTRL2_TA_ADP_PRB(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_TA_ADP_PRB_SHIFT)) & USB3_OTGCTRL2_TA_ADP_PRB_MASK)
97975 #define USB3_OTGCTRL2_TB_ADP_PRB_MASK            (0xFF00U)
97976 #define USB3_OTGCTRL2_TB_ADP_PRB_SHIFT           (8U)
97977 /*! TB_ADP_PRB - B-device ADP probing period. TB_ADP_PRB = {reg_value} * 10 ms
97978  */
97979 #define USB3_OTGCTRL2_TB_ADP_PRB(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_TB_ADP_PRB_SHIFT)) & USB3_OTGCTRL2_TB_ADP_PRB_MASK)
97980 #define USB3_OTGCTRL2_ADP_CHRG_TMOUT_MASK        (0xFF0000U)
97981 #define USB3_OTGCTRL2_ADP_CHRG_TMOUT_SHIFT       (16U)
97982 /*! ADP_CHRG_TMOUT - ADP probing timeout value. Defines maximum time for ADP charging. If this time
97983  *    is reached during charging then adp_chrg_tmout_det bit in OTGADPBCSTS is set ADP_CHRG_TMOUT =
97984  *    {reg_value} * 1 ms
97985  */
97986 #define USB3_OTGCTRL2_ADP_CHRG_TMOUT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_ADP_CHRG_TMOUT_SHIFT)) & USB3_OTGCTRL2_ADP_CHRG_TMOUT_MASK)
97987 #define USB3_OTGCTRL2_T_ADP_DSCHG_MASK           (0xFF000000U)
97988 #define USB3_OTGCTRL2_T_ADP_DSCHG_SHIFT          (24U)
97989 /*! T_ADP_DSCHG - ADP probing discharge time. T_ADP_DSCHG = {reg_value} * 1 ms
97990  */
97991 #define USB3_OTGCTRL2_T_ADP_DSCHG(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_T_ADP_DSCHG_SHIFT)) & USB3_OTGCTRL2_T_ADP_DSCHG_MASK)
97992 /*! @} */
97993 
97994 /*! @name HCIVERSION_CAPLENGTH - HCI Version and CAPLENGTH */
97995 /*! @{ */
97996 #define USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
97997 #define USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_SHIFT (0U)
97998 /*! CAPLENGTH - Capability Registers Length (CAPLENGTH). This register is used as an offset to add
97999  *    to register base to find the beginning of the Operational Register Space
98000  */
98001 #define USB3_HCIVERSION_CAPLENGTH_CAPLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_SHIFT)) & USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_MASK)
98002 #define USB3_HCIVERSION_CAPLENGTH_HCIVERSION_MASK (0xFFFF0000U)
98003 #define USB3_HCIVERSION_CAPLENGTH_HCIVERSION_SHIFT (16U)
98004 /*! HCIVERSION - Host Controller Interface Version Number (HCIVERSION). This is a two-byte register
98005  *    containing a BCD encoding of the xHCI specification revision number supported by this host
98006  *    controller. The most significant byte of this register represents a major revision and the least
98007  *    significant byte is the minor revision. e.g. 0100h corresponds to xHCI version 1.0
98008  */
98009 #define USB3_HCIVERSION_CAPLENGTH_HCIVERSION(x)  (((uint32_t)(((uint32_t)(x)) << USB3_HCIVERSION_CAPLENGTH_HCIVERSION_SHIFT)) & USB3_HCIVERSION_CAPLENGTH_HCIVERSION_MASK)
98010 /*! @} */
98011 
98012 /*! @name HCSPARAMS1 - Structural Parameters 1 */
98013 /*! @{ */
98014 #define USB3_HCSPARAMS1_MaxSlots_MASK            (0xFFU)
98015 #define USB3_HCSPARAMS1_MaxSlots_SHIFT           (0U)
98016 /*! MaxSlots - Number of Device Slots (MaxSlots). This field specifies the maximum number of Device
98017  *    Context Structures and Doorbell Array entries this host controller can support. Valid values
98018  *    are in the range of 1 to 255. The value of 0 is reserved
98019  */
98020 #define USB3_HCSPARAMS1_MaxSlots(x)              (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS1_MaxSlots_SHIFT)) & USB3_HCSPARAMS1_MaxSlots_MASK)
98021 #define USB3_HCSPARAMS1_MaxIntrs_MASK            (0x7FF00U)
98022 #define USB3_HCSPARAMS1_MaxIntrs_SHIFT           (8U)
98023 /*! MaxIntrs - Number of Interrupters (MaxIntrs). This field specifies the number of Interrupters
98024  *    implemented on this host controller. Each Interrupter may be allocated to a MSI or MSI-X vector
98025  *    and controls its generation and moderation. The value of this field determines how many
98026  *    Interrupter Register Sets are addressable in the Runtime Register Space (refer to section 5.5 of
98027  *    xHCI specification). Valid values are in the range of 1h to 400h. A '0' in this field is undefined
98028  */
98029 #define USB3_HCSPARAMS1_MaxIntrs(x)              (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS1_MaxIntrs_SHIFT)) & USB3_HCSPARAMS1_MaxIntrs_MASK)
98030 #define USB3_HCSPARAMS1_MaxPorts_MASK            (0xFF000000U)
98031 #define USB3_HCSPARAMS1_MaxPorts_SHIFT           (24U)
98032 /*! MaxPorts - Number of Ports (MaxPorts). This field specifies the maximum Port Number value, i.e.
98033  *    the highest numbered Port Register Set that are addressable in the Operational Register Space.
98034  *    Valid values are in the range of 1h to FFh. The value in this field shall reflect the maximum
98035  *    Port Number value assigned by an xHCI Supported Protocol Capability, described in section 7.2
98036  *    of xHCI specification. Software shall refer to these capabilities to identify whether a
98037  *    specific Port Number is valid, and the protocol supported by the associated Port Register Set
98038  */
98039 #define USB3_HCSPARAMS1_MaxPorts(x)              (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS1_MaxPorts_SHIFT)) & USB3_HCSPARAMS1_MaxPorts_MASK)
98040 /*! @} */
98041 
98042 /*! @name HCSPARAMS2 - Structural Parameters 2 */
98043 /*! @{ */
98044 #define USB3_HCSPARAMS2_IST_MASK                 (0xFU)
98045 #define USB3_HCSPARAMS2_IST_SHIFT                (0U)
98046 /*! IST - Isochronous Scheduling Threshold (IST). Default = implementation dependent. The value in
98047  *    this field indicates to system software the minimum distance (in time) that it is required to
98048  *    stay ahead of the host controller while adding TRBs, in order to have the host controller
98049  *    process them at the correct time. The value shall be specified in terms of number of
98050  *    frames/microframes. If bit [3] of IST is cleared to '0', software can add a TRB no later than IST[2:0]
98051  *    Microframes before that TRB is scheduled to be executed. If bit [3] of IST is set to '1', software
98052  *    can add a TRB no later than IST[2:0] Frames before that TRB is scheduled to be executed. Refer
98053  *    to Section 4.14.2 of xHCI specification for details on how software uses this information for
98054  *    scheduling isochronous transfers
98055  */
98056 #define USB3_HCSPARAMS2_IST(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_IST_SHIFT)) & USB3_HCSPARAMS2_IST_MASK)
98057 #define USB3_HCSPARAMS2_ERSTMax_MASK             (0xF0U)
98058 #define USB3_HCSPARAMS2_ERSTMax_SHIFT            (4U)
98059 /*! ERSTMax - Event Ring Segment Table Max (ERST Max). Default = implementation dependent. Valid
98060  *    values are 0-15. This field determines the maximum value supported the Event Ring Segment Table
98061  *    Base Size registers (5.5.2.3.1), where: The maximum number of Event Ring Segment Table entries
98062  *    = 2 ^(ERSTMax), e.g. if the ERST Max = 7, then the xHC Event Ring Segment Table(s) supports up
98063  *    to 128 entries, 15 then 32K entries, etc
98064  */
98065 #define USB3_HCSPARAMS2_ERSTMax(x)               (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_ERSTMax_SHIFT)) & USB3_HCSPARAMS2_ERSTMax_MASK)
98066 #define USB3_HCSPARAMS2_MaxSPBufHi_MASK          (0x3E00000U)
98067 #define USB3_HCSPARAMS2_MaxSPBufHi_SHIFT         (21U)
98068 /*! MaxSPBufHi - Max Scratchpad Buffers (Max Scratchpad Bufs Hi). Default = implementation
98069  *    dependent. This field indicates the high order 5 bits of the number of Scratchpad Buffers system
98070  *    software shall reserve for the xHC. Refer to section 4.20 of xHCI specification for more information
98071  */
98072 #define USB3_HCSPARAMS2_MaxSPBufHi(x)            (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_MaxSPBufHi_SHIFT)) & USB3_HCSPARAMS2_MaxSPBufHi_MASK)
98073 #define USB3_HCSPARAMS2_SPR_MASK                 (0x4000000U)
98074 #define USB3_HCSPARAMS2_SPR_SHIFT                (26U)
98075 /*! SPR - Scratchpad Restore (SPR). Default = implementation dependent. If Max Scratchpad Buffers is
98076  *    > 0 then this flag indicates whether the xHC uses the Scratchpad Buffers for saving state
98077  *    when executing Save and Restore State operations. If Max Scratchpad Buffers is = 0 then this flag
98078  *    shall be 0. Refer to section 4.23.2 of xHCI specification for more information. A value of
98079  *    '1' indicates that the xHC requires the integrity of the Scratchpad Buffer space to be
98080  *    maintained across power events. A value of '0' indicates that the Scratchpad Buffer space may be freed
98081  *    and reallocated between power events
98082  */
98083 #define USB3_HCSPARAMS2_SPR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_SPR_SHIFT)) & USB3_HCSPARAMS2_SPR_MASK)
98084 #define USB3_HCSPARAMS2_MaxSPBufLo_MASK          (0xF8000000U)
98085 #define USB3_HCSPARAMS2_MaxSPBufLo_SHIFT         (27U)
98086 /*! MaxSPBufLo - Max Scratchpad Buffers (Max Scratchpad Bufs Lo). Default = implementation
98087  *    dependent. Valid values for Max Scratchpad Buffers (Hi and Lo) are 0-1023. This field indicates the low
98088  *    order 5 bits of the number of Scratchpad Buffers system software shall reserve for the xHC.
98089  *    Refer to section 4.20 of xHCI specification for more information
98090  */
98091 #define USB3_HCSPARAMS2_MaxSPBufLo(x)            (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_MaxSPBufLo_SHIFT)) & USB3_HCSPARAMS2_MaxSPBufLo_MASK)
98092 /*! @} */
98093 
98094 /*! @name HCSPARAMS3 - Structural Parameters 3 */
98095 /*! @{ */
98096 #define USB3_HCSPARAMS3_U1DevExitLat_MASK        (0xFFU)
98097 #define USB3_HCSPARAMS3_U1DevExitLat_SHIFT       (0U)
98098 /*! U1DevExitLat - U1 Device Exit Latency. Worst case latency to transition a root hub Port Link
98099  *    State (PLS) from U1 to U0. Applies to all root hub ports. The following are permissible values:
98100  *    00h Zero, 01h Less than 1 s., 02h Less than 2 s., ... 0Ah Less than 10 s., 0B-FFh Reserved
98101  */
98102 #define USB3_HCSPARAMS3_U1DevExitLat(x)          (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS3_U1DevExitLat_SHIFT)) & USB3_HCSPARAMS3_U1DevExitLat_MASK)
98103 #define USB3_HCSPARAMS3_U2DevExitLat_MASK        (0xFFFF0000U)
98104 #define USB3_HCSPARAMS3_U2DevExitLat_SHIFT       (16U)
98105 /*! U2DevExitLat - U2 Device Exit Latency. Worst case latency to transition from U2 to U0. Applies
98106  *    to all root hub ports. The following are permissible values: 0000h Zero, 0001h Less than 1 s.,
98107  *    0002h Less than 2 s., ... 07FFh Less than 2047 s., 0800-FFFFh Reserved
98108  */
98109 #define USB3_HCSPARAMS3_U2DevExitLat(x)          (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS3_U2DevExitLat_SHIFT)) & USB3_HCSPARAMS3_U2DevExitLat_MASK)
98110 /*! @} */
98111 
98112 /*! @name HCCPARAMS - Capability Parameters */
98113 /*! @{ */
98114 #define USB3_HCCPARAMS_AC64_MASK                 (0x1U)
98115 #define USB3_HCCPARAMS_AC64_SHIFT                (0U)
98116 /*! AC64 - 64-bit Addressing Capability (AC64). This flag documents the addressing range capability
98117  *    of this implementation. The value of this flag determines whether the xHC has implemented the
98118  *    high order 32 bits of 64 bit register and data structure pointer fields. Values for this flag
98119  *    have the following interpretation: '0': 32-bit address memory pointers implemented, '1':
98120  *    64-bit address memory pointers implemented. If 32-bit address memory pointers are implemented, the
98121  *    xHC shall ignore the high order 32 bits of 64 bit data structure pointer fields, and system
98122  *    software shall ignore the high order 32 bits of 64 bit xHC registers
98123  */
98124 #define USB3_HCCPARAMS_AC64(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_AC64_SHIFT)) & USB3_HCCPARAMS_AC64_MASK)
98125 #define USB3_HCCPARAMS_BNC_MASK                  (0x2U)
98126 #define USB3_HCCPARAMS_BNC_SHIFT                 (1U)
98127 /*! BNC - BW Negotiation Capability (BNC). This flag identifies whether the xHC has implemented the
98128  *    Bandwidth Negotiation. Values for this flag have the following interpretation: '0': BW
98129  *    Negotiation not implemented '1': BW Negotiation implemented Refer to section 4.16 of xHCI
98130  *    specification for more information on Bandwidth Negotiation
98131  */
98132 #define USB3_HCCPARAMS_BNC(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_BNC_SHIFT)) & USB3_HCCPARAMS_BNC_MASK)
98133 #define USB3_HCCPARAMS_CSZ_MASK                  (0x4U)
98134 #define USB3_HCCPARAMS_CSZ_SHIFT                 (2U)
98135 /*! CSZ - Context Size (CSZ). If this bit is set to '1', then the xHC uses 64 byte Context data
98136  *    structures. If this bit is cleared to 0, then the xHC uses 32 byte Context data structures. Note:
98137  *    This flag does not apply to Stream Contexts
98138  */
98139 #define USB3_HCCPARAMS_CSZ(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_CSZ_SHIFT)) & USB3_HCCPARAMS_CSZ_MASK)
98140 #define USB3_HCCPARAMS_PPC_MASK                  (0x8U)
98141 #define USB3_HCCPARAMS_PPC_SHIFT                 (3U)
98142 /*! PPC - Port Power Control (PPC). This flag indicates whether the host controller implementation
98143  *    includes port power control. A '1' in this bit indicates the ports have port power switches. A
98144  *    '0' in this bit indicates the port do not have port power switches. The value of this flag
98145  *    affects the functionality of the PP flag in each port status and control register (refer to
98146  *    Section 5.4.8 of xHCI specification). When DEBUG_CTRL_REG capability is used
98147  *    (CDNS_RM_CBIT_DEBUG_CTRL_REG is not defined) then this bit is treated as RW. Its value can be changed only by writes
98148  *    to bit 8 of DEBUG_CTRL_REG (port_pwr_ctrl_toggle). Direct writes to this bit are not possible
98149  */
98150 #define USB3_HCCPARAMS_PPC(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_PPC_SHIFT)) & USB3_HCCPARAMS_PPC_MASK)
98151 #define USB3_HCCPARAMS_PIND_MASK                 (0x10U)
98152 #define USB3_HCCPARAMS_PIND_SHIFT                (4U)
98153 /*! PIND - Port Indicators (PIND). This bit indicates whether the xHC root hub ports support port
98154  *    indicator control. When this bit is a '1', the port status and control registers include a
98155  *    read/writeable field for controlling the state of the port indicator. Refer to Section 5.4.8 of
98156  *    xHCI specification for definition of the Port Indicator Control field (PIC field of PORTSC
98157  *    register)
98158  */
98159 #define USB3_HCCPARAMS_PIND(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_PIND_SHIFT)) & USB3_HCCPARAMS_PIND_MASK)
98160 #define USB3_HCCPARAMS_LHRC_MASK                 (0x20U)
98161 #define USB3_HCCPARAMS_LHRC_SHIFT                (5U)
98162 /*! LHRC - Light HC Reset Capability (LHRC). This flag indicates whether the host controller
98163  *    implementation supports a Light Host Controller Reset. A '1' in this bit indicates that Light Host
98164  *    Controller Reset is supported. A '0' in this bit indicates that Light Host Controller Reset is
98165  *    not supported. The value of this flag affects the functionality of the Light Host Controller
98166  *    Reset (LHCRST) flag in the USBCMD register (refer to Section 5.4.1 of xHCI specification)
98167  */
98168 #define USB3_HCCPARAMS_LHRC(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_LHRC_SHIFT)) & USB3_HCCPARAMS_LHRC_MASK)
98169 #define USB3_HCCPARAMS_LTC_MASK                  (0x40U)
98170 #define USB3_HCCPARAMS_LTC_SHIFT                 (6U)
98171 /*! LTC - Latency Tolerance Messaging Capability (LTC). This flag indicates whether the host
98172  *    controller implementation supports Latency Tolerance Messaging (LTM). A '1' in this bit indicates
98173  *    that LTM is supported. A 0 in this bit indicates that LTM is not supported. Refer to section
98174  *    4.13.1 of xHCI specification for more information on LTM
98175  */
98176 #define USB3_HCCPARAMS_LTC(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_LTC_SHIFT)) & USB3_HCCPARAMS_LTC_MASK)
98177 #define USB3_HCCPARAMS_NSS_MASK                  (0x80U)
98178 #define USB3_HCCPARAMS_NSS_SHIFT                 (7U)
98179 /*! NSS - No Secondary SID Support (NSS). This flag indicates whether the host controller
98180  *    implementation supports Secondary Stream IDs. A '1'in this bit indicates that Secondary Stream ID
98181  *    decoding is not supported. A '0' in this bit indicates that Secondary Stream ID decoding is
98182  *    supported. (refer to Sections 4.12.2 and 6.2.3 of xHCI specification)
98183  */
98184 #define USB3_HCCPARAMS_NSS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_NSS_SHIFT)) & USB3_HCCPARAMS_NSS_MASK)
98185 #define USB3_HCCPARAMS_PAE_MASK                  (0x100U)
98186 #define USB3_HCCPARAMS_PAE_SHIFT                 (8U)
98187 /*! PAE - Parse All Event Data (PAE). This flag indicates whether the host controller implementation
98188  *    Parses all Event Data TRBs while advancing to the next TD after a Short Packet, or it skips
98189  *    all but the first Event Data TRB. A '1' in this bit indicates that all Event Data TRBs are
98190  *    parsed. A '0' in this bit indicates that only the first Event Data TRB is parsed (refer to section
98191  *    4.10.1.1 of xHCI specification)
98192  */
98193 #define USB3_HCCPARAMS_PAE(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_PAE_SHIFT)) & USB3_HCCPARAMS_PAE_MASK)
98194 #define USB3_HCCPARAMS_SPC_MASK                  (0x200U)
98195 #define USB3_HCCPARAMS_SPC_SHIFT                 (9U)
98196 /*! SPC - Stopped - Short Packet Capability (SPC). This flag indicates that the host controller
98197  *    implementation is capable of generating a Stopped - Short Packet Completion Code. Refer to section
98198  *    4.6.9 of xHCI specification for more information
98199  */
98200 #define USB3_HCCPARAMS_SPC(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_SPC_SHIFT)) & USB3_HCCPARAMS_SPC_MASK)
98201 #define USB3_HCCPARAMS_MaxPSASize_MASK           (0xF000U)
98202 #define USB3_HCCPARAMS_MaxPSASize_SHIFT          (12U)
98203 /*! MaxPSASize - Maximum Primary Stream Array Size (MaxPSASize). This fields identifies the maximum
98204  *    size Primary Stream Array that the xHC supports. The Primary Stream Array size =
98205  *    2MaxPSASize+1. Valid MaxPSASize values are 0 to 15, where 0 indicates that Streams are not supported
98206  */
98207 #define USB3_HCCPARAMS_MaxPSASize(x)             (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_MaxPSASize_SHIFT)) & USB3_HCCPARAMS_MaxPSASize_MASK)
98208 #define USB3_HCCPARAMS_xECP_MASK                 (0xFFFF0000U)
98209 #define USB3_HCCPARAMS_xECP_SHIFT                (16U)
98210 /*! xECP - xHCI Extended Capabilities Pointer (xECP). This field indicates the existence of a
98211  *    capabilities list. The value of this field indicates a relative offset, in 32-bit words, from Base
98212  *    to the beginning of the first extended capability. For example, using the offset of Base is
98213  *    1000h and the xECP value of 0068h, we can calculate the following effective address of the first
98214  *    extended capability: 1000h + (0068h << 2) -> 1000h + 01A0h -> 11A0h
98215  */
98216 #define USB3_HCCPARAMS_xECP(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_xECP_SHIFT)) & USB3_HCCPARAMS_xECP_MASK)
98217 /*! @} */
98218 
98219 /*! @name DBOFF - DoorBell Array Offset */
98220 /*! @{ */
98221 #define USB3_DBOFF_DAO_MASK                      (0xFFFFFFFCU)
98222 #define USB3_DBOFF_DAO_SHIFT                     (2U)
98223 /*! DAO - Doorbell Array Offset, RO. Default = implementation dependent. This field defines the
98224  *    offset in Dwords of the Doorbell Array base address from the Base (i.e. the base address of the
98225  *    xHCI Capability register address space)
98226  */
98227 #define USB3_DBOFF_DAO(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DBOFF_DAO_SHIFT)) & USB3_DBOFF_DAO_MASK)
98228 /*! @} */
98229 
98230 /*! @name RTSOFF - xHCI Runtime Registers Offset */
98231 /*! @{ */
98232 #define USB3_RTSOFF_RRSO_MASK                    (0xFFFFFFE0U)
98233 #define USB3_RTSOFF_RRSO_SHIFT                   (5U)
98234 /*! RRSO - Runtime Register Space Offset, RO. Default = implementation dependent. This field defines
98235  *    the 32-byte offset of the xHCI Runtime Registers from the Base. i.e. Runtime Register Base
98236  *    Address = Base + Runtime Register Set Offset
98237  */
98238 #define USB3_RTSOFF_RRSO(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_RTSOFF_RRSO_SHIFT)) & USB3_RTSOFF_RRSO_MASK)
98239 /*! @} */
98240 
98241 /*! @name USBCMD - USB Command */
98242 /*! @{ */
98243 #define USB3_USBCMD_R_S_MASK                     (0x1U)
98244 #define USB3_USBCMD_R_S_SHIFT                    (0U)
98245 /*! R_S - Run/Stop (R/S), RW. Default = '0'. '1' = Run. '0' = Stop. When set to a '1', the xHC
98246  *    proceeds with execution of the schedule. The xHC continues execution as long as this bit is set to
98247  *    a '1'. When this bit is cleared to '0', the xHC completes any current or queued commands or
98248  *    TDs, and any USB transactions associated with them, then halts. Refer to section 5.4.1.1 of xHCI
98249  *    specification for more information on how R/S shall be managed. The xHC shall halt within 16
98250  *    ms after software clears the Run/Stop bit if the above conditions have been met. The HCHalted
98251  *    (HCH) bit in the USBSTS register indicates when the xHC has finished its pending pipelined
98252  *    transactions and has entered the stopped state. Software shall not write a '1' to this flag
98253  *    unless the xHC is in the Halted state (i.e. HCH in the USBSTS register is '1'). Doing so may yield
98254  *    undefined results. Writing a '0' to this flag when the xHC is in the Running state (i.e. HCH =
98255  *    '0') and any Event Rings are in the Event Ring Full state (refer to section 4.9.4 of xHCI
98256  *    specification) may result in lost events. When this register is exposed by a Virtual Function
98257  *    (VF), this bit only controls the run state of the xHC instance presented by the selected VF.
98258  *    Refer to section 8 of xHCI specification for more information
98259  */
98260 #define USB3_USBCMD_R_S(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_R_S_SHIFT)) & USB3_USBCMD_R_S_MASK)
98261 #define USB3_USBCMD_HCRST_MASK                   (0x2U)
98262 #define USB3_USBCMD_HCRST_SHIFT                  (1U)
98263 /*! HCRST - Host Controller Reset (HCRST), RW. Default = '0'. This control bit is used by software
98264  *    to reset the host controller. The effects of this bit on the xHC and the Root Hub registers are
98265  *    similar to a Chip Hardware Reset. When software writes a '1' to this bit, the Host Controller
98266  *    resets its internal pipelines, timers, counters, state machines, etc. to their initial value.
98267  *    Any transaction currently in progress on the USB is immediately terminated. A USB reset shall
98268  *    not be driven on USB2 downstream ports, however a Hot or Warm Reset shall be initiated on
98269  *    USB3 Root Hub downstream ports. PCI Configuration registers are not affected by this reset. All
98270  *    operational registers, including port registers and port state machines are set to their
98271  *    initial values. Software shall reinitialize the host controller as described in Section 4.1 of xHCI
98272  *    specification in order to return the host controller to an operational state. This bit is
98273  *    cleared to '0' by the Host Controller when the reset process is complete. Software cannot
98274  *    terminate the reset process early by writing a '0' to this bit and shall not write any xHC Operational
98275  *    or Runtime registers until while HCRST is '1'. Note, the completion of the xHC reset process
98276  *    is not gated by the Root Hub port reset process. Software shall not set this bit to '1' when
98277  *    the HCHalted (HCH) bit in the USBSTS register is a '0'. Attempting to reset an actively running
98278  *    host controller may result in undefined behavior. When this register is exposed by a Virtual
98279  *    Function (VF), this bit only resets the xHC instance presented by the selected VF. Refer to
98280  *    section 8 of xHCI specification for more information
98281  */
98282 #define USB3_USBCMD_HCRST(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_HCRST_SHIFT)) & USB3_USBCMD_HCRST_MASK)
98283 #define USB3_USBCMD_INTE_MASK                    (0x4U)
98284 #define USB3_USBCMD_INTE_SHIFT                   (2U)
98285 /*! INTE - Interrupter Enable (INTE), RW. Default = '0'. This bit provides system software with a
98286  *    means of enabling or disabling the host system interrupts generated by Interrupters. When this
98287  *    bit is a '1', then Interrupter host system interrupt generation is allowed, e.g. the xHC shall
98288  *    issue an interrupt at the next interrupt threshold if the host system interrupt mechanism
98289  *    (e.g. MSI, MSIX, etc.) is enabled. The interrupt is acknowledged by a host system interrupt
98290  *    specific mechanism. When this register is exposed by a Virtual Function (VF), this bit only enables
98291  *    the set of Interrupters assigned to the selected VF. Refer to section 7.7.2 of xHCI
98292  *    specification for more information
98293  */
98294 #define USB3_USBCMD_INTE(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_INTE_SHIFT)) & USB3_USBCMD_INTE_MASK)
98295 #define USB3_USBCMD_HSEE_MASK                    (0x8U)
98296 #define USB3_USBCMD_HSEE_SHIFT                   (3U)
98297 /*! HSEE - Host System Error Enable (HSEE), RW. Default = '0'. When this bit is a '1', and the HSE
98298  *    bit in the USBSTS register is a '1', the xHC shall assert out-of-band error signaling to the
98299  *    host. The signaling is acknowledged by software clearing the HSE bit. Refer to section 4.10.2.6
98300  *    of xHCI specification for more information. When this register is exposed by a Virtual
98301  *    Function (VF), the effect of the assertion of this bit on the Physical Function (PF0) is determined
98302  *    by the VMM. Refer to section 8 of xHCI specification for more information
98303  */
98304 #define USB3_USBCMD_HSEE(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_HSEE_SHIFT)) & USB3_USBCMD_HSEE_MASK)
98305 #define USB3_USBCMD_LHCRST_MASK                  (0x80U)
98306 #define USB3_USBCMD_LHCRST_SHIFT                 (7U)
98307 /*! LHCRST - Light Host Controller Reset (LHCRST), RO or RW. Optional normative. Default = '0'. If
98308  *    the Light HC Reset Capability (LHRC) bit in the HCCPARAMS register is '1', then this flag
98309  *    allows the driver to reset the xHC without affecting the state of the ports. A system software read
98310  *    of this bit as '0' indicates the Light Host Controller Reset has completed and it is safe for
98311  *    software to re-initialize the xHC. A software read of this bit as a '1' indicates that the
98312  *    Light Host Controller Reset has not yet completed. If not implemented, a read of this flag shall
98313  *    always return a '0'. All registers in the Aux Power well shall maintain the values that had
98314  *    been asserted prior to the Light Host Controller Reset. Refer to section 4.23.1 of xHCI
98315  *    specification for more information. When this register is exposed by a Virtual Function (VF), this
98316  *    bit only generates a Light Reset to the xHC instance presented by the selected VF, e.g. Disable
98317  *    the VFs device slots and set the associated VF Run bit to Stopped. Refer to section 8 of xHCI
98318  *    specification for more information
98319  */
98320 #define USB3_USBCMD_LHCRST(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_LHCRST_SHIFT)) & USB3_USBCMD_LHCRST_MASK)
98321 #define USB3_USBCMD_CSS_MASK                     (0x100U)
98322 #define USB3_USBCMD_CSS_SHIFT                    (8U)
98323 /*! CSS - Controller Save State (CSS), RW. Default = '0'. When written by software with '1' and
98324  *    HCHalted (HCH) = '1', then the xHC shall save any internal state that may be restored by a
98325  *    subsequent Restore State operation. When written by software with '1' and HCHalted (HCH) = '0', or
98326  *    written with '0', no Save State operation shall be performed. This flag always returns '0' when
98327  *    read. Refer to the Save State Status (SSS) flag in the USBSTS register for information on Save
98328  *    State completion. Refer to section 4.23.2 of xHCI specification for more information on xHC
98329  *    Save/Restore operation. Note that undefined behavior may occur if a Save State operation is
98330  *    initiated while Restore State Status (RSS) ='1'. When this register is exposed by a Virtual
98331  *    Function (VF), this bit only controls saving the state of the xHC instance presented by the
98332  *    selected VF. Refer to section 8 of xHCI specifications for more information
98333  */
98334 #define USB3_USBCMD_CSS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_CSS_SHIFT)) & USB3_USBCMD_CSS_MASK)
98335 #define USB3_USBCMD_CRS_MASK                     (0x200U)
98336 #define USB3_USBCMD_CRS_SHIFT                    (9U)
98337 /*! CRS - Controller Restore State (CRS), RW. Default = '0'. When set to '1', and HCHalted (HCH) =
98338  *    '1', then the xHC shall perform a Restore State operation and restore its internal state. When
98339  *    set to '1' and Run/Stop (R/S) = '1' or HCHalted (HCH) = '0', or when cleared to '0', no
98340  *    Restore State operation shall be performed. This flag always returns '0' when read. Refer to the
98341  *    Restore State Status (RSS) flag in the USBSTS register for information on Restore State
98342  *    completion. Refer to section 4.23.2 of xHCI specification for more information. Note that undefined
98343  *    behavior may occur if a Restore State operation is initiated while Save State Status (SSS) = '1'.
98344  *    When this register is exposed by a Virtual Function (VF), this bit only controls restoring
98345  *    the state of the xHC instance presented by the selected VF. Refer to section 8 of xHCI
98346  *    specification for more information
98347  */
98348 #define USB3_USBCMD_CRS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_CRS_SHIFT)) & USB3_USBCMD_CRS_MASK)
98349 #define USB3_USBCMD_EWE_MASK                     (0x400U)
98350 #define USB3_USBCMD_EWE_SHIFT                    (10U)
98351 /*! EWE - Enable Wrap Event (EWE), RW. Default = '0'. When set to '1', the xHC shall generate a
98352  *    MFINDEX Wrap Event every time the MFINDEX register transitions from 03FFFh to 0. When cleared to
98353  *    '0' no MFINDEX Wrap Events are generated. Refer to section 4.14.2 of xHCI specification for
98354  *    more information. When this register is exposed by a Virtual Function (VF), the generation of
98355  *    MFINDEX Wrap Events to VFs shall be emulated by the VMM
98356  */
98357 #define USB3_USBCMD_EWE(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_EWE_SHIFT)) & USB3_USBCMD_EWE_MASK)
98358 #define USB3_USBCMD_EU3S_MASK                    (0x800U)
98359 #define USB3_USBCMD_EU3S_SHIFT                   (11U)
98360 /*! EU3S - Enable U3 MFINDEX Stop (EU3S), RW. Default = '0'. When set to '1', the xHC may stop the
98361  *    MFINDEX counting action if all Root Hub ports are in the U3, Disconnected, Disabled, or
98362  *    Powered-off state. When cleared to '0' the xHC may stop the MFINDEX counting action if all Root Hub
98363  *    ports are in the Disconnected, Disabled, Training, or Powered-off state. Refer to section
98364  *    4.14.2 of xHCI specification for more information
98365  */
98366 #define USB3_USBCMD_EU3S(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_EU3S_SHIFT)) & USB3_USBCMD_EU3S_MASK)
98367 /*! @} */
98368 
98369 /*! @name USBSTS - USB Status */
98370 /*! @{ */
98371 #define USB3_USBSTS_HCH_MASK                     (0x1U)
98372 #define USB3_USBSTS_HCH_SHIFT                    (0U)
98373 /*! HCH - HCHalted (HCH), RO. Default = '1'. This bit is a '0' whenever the Run/Stop (R/S) bit is a
98374  *    '1'. The xHC sets this bit to '1' after it has stopped executing as a result of the Run/Stop
98375  *    (R/S) bit being cleared to '0', either by software or by the xHC hardware (e.g. internal
98376  *    error). If this bit is '1', then SOFs, microSOFs, or Isochronous Timestamp Packets (ITP) shall not
98377  *    be generated by the xHC, and any received Transaction Packet shall be dropped. When this
98378  *    register is exposed by a Virtual Function (VF), this bit only reflects the Halted state of the xHC
98379  *    instance presented by the selected VF. Refer to section 8 of xHCI specification for more
98380  *    information
98381  */
98382 #define USB3_USBSTS_HCH(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_HCH_SHIFT)) & USB3_USBSTS_HCH_MASK)
98383 #define USB3_USBSTS_HSE_MASK                     (0x4U)
98384 #define USB3_USBSTS_HSE_SHIFT                    (2U)
98385 /*! HSE - Host System Error (HSE), RW1C. Default = '0'. The xHC sets this bit to '1' when a serious
98386  *    error is detected, either internal to the xHC or during a host system access involving the xHC
98387  *    module. (In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI
98388  *    Master Abort, and PCI Target Abort.) When this error occurs, the xHC clears the Run/Stop (R/S)
98389  *    bit in the USBCMD register to prevent further execution of the scheduled TDs. If the HSEE bit in
98390  *    the USBCMD register is a '1', the xHC shall also assert out-of-band error signaling to the
98391  *    host. Refer to section 4.10.2.6 of xHCI specification for more information. When this register
98392  *    is exposed by a Virtual Function (VF), the assertion of this bit affects all VFs and reflects
98393  *    the Host System Error state of the Physical Function (PF0). Refer to section 8 of xHCI
98394  *    specification for more information
98395  */
98396 #define USB3_USBSTS_HSE(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_HSE_SHIFT)) & USB3_USBSTS_HSE_MASK)
98397 #define USB3_USBSTS_EINT_MASK                    (0x8U)
98398 #define USB3_USBSTS_EINT_SHIFT                   (3U)
98399 /*! EINT - Event Interrupt (EINT), RW1C. Default = '0'. The xHC sets this bit to '1' when the
98400  *    Interrupt Pending (IP) bit of any Interrupter transitions from '0' to '1'. Refer to section 7.1.2 of
98401  *    xHCI specification for use. Software that uses EINT shall clear it prior to clearing any IP
98402  *    flags. A race condition may occur if software clears the IP flags then clears the EINT flag,
98403  *    and between the operations another IP '0' to '1' transition occurs. In this case the new IP
98404  *    transition shall be lost. When this register is exposed by a Virtual Function (VF), this bit is
98405  *    the logical 'OR' of the IP bits for the Interrupters assigned to the selected VF. And it shall
98406  *    be cleared to '0' when all associated interrupter IP bits are cleared, i.e. all the VFs
98407  *    Interrupter Event Ring(s) are empty. Refer to section 8 of xHCI specification for more information
98408  */
98409 #define USB3_USBSTS_EINT(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_EINT_SHIFT)) & USB3_USBSTS_EINT_MASK)
98410 #define USB3_USBSTS_PCD_MASK                     (0x10U)
98411 #define USB3_USBSTS_PCD_SHIFT                    (4U)
98412 /*! PCD - Port Change Detect (PCD), RW1C. Default = '0'. The xHC sets this bit to a '1' when any
98413  *    port has a change bit transition from a '0' to a '1'. This bit is allowed to be maintained in the
98414  *    Aux Power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the
98415  *    xHC, this bit is loaded with the OR of all of the PORTSC change bits. Refer to section 4.19.3 of
98416  *    xHCI specification. This bit provides system software an efficient means of determining if
98417  *    there has been Root Hub port activity. Refer to section 4.15.2.3 of xHCI specification for more
98418  *    information. When this register is exposed by a Virtual Function (VF), the VMM determines the
98419  *    state of this bit as a function of the Root Hub Ports associated with the Device Slots assigned
98420  *    to the selected VF. Refer to section 8 of xHCI specification for more information
98421  */
98422 #define USB3_USBSTS_PCD(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_PCD_SHIFT)) & USB3_USBSTS_PCD_MASK)
98423 #define USB3_USBSTS_SSS_MASK                     (0x100U)
98424 #define USB3_USBSTS_SSS_SHIFT                    (8U)
98425 /*! SSS - Save State Status (SSS), RO. Default = '0'. When the Controller Save State (CSS) flag in
98426  *    the USBCMD register is written with '1' this bit shall be set to '1' and remain '1' while the
98427  *    xHC saves its internal state. When the Save State operation is complete, this bit shall be
98428  *    cleared to '0'. Refer to section 4.23.2 of xHCI specification for more information. When this
98429  *    register is exposed by a Virtual Function (VF), the VMM determines the state of this bit as a
98430  *    function of the saving the state for the selected VF. Refer to section 8 of xHCI specification for
98431  *    more information
98432  */
98433 #define USB3_USBSTS_SSS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_SSS_SHIFT)) & USB3_USBSTS_SSS_MASK)
98434 #define USB3_USBSTS_RSS_MASK                     (0x200U)
98435 #define USB3_USBSTS_RSS_SHIFT                    (9U)
98436 /*! RSS - Restore State Status (RSS), RO. Default = '0'. When the Controller Restore State (CRS)
98437  *    flag in the USBCMD register is written with '1' this bit shall be set to '1' and remain '1' while
98438  *    the xHC restores its internal state. When the Restore State operation is complete, this bit
98439  *    shall be cleared to '0'. Refer to section 4.23.2 of xHCI specification for more information.
98440  *    When this register is exposed by a Virtual Function (VF), the VMM determines the state of this
98441  *    bit as a function of the restoring the state for the selected VF. Refer to section 8 of xHCI
98442  *    specification for more information
98443  */
98444 #define USB3_USBSTS_RSS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_RSS_SHIFT)) & USB3_USBSTS_RSS_MASK)
98445 #define USB3_USBSTS_SRE_MASK                     (0x400U)
98446 #define USB3_USBSTS_SRE_SHIFT                    (10U)
98447 /*! SRE - Save/Restore Error (SRE), RW1C. Default = '0'. If an error occurs during a Save or Restore
98448  *    operation this bit shall be set to '1'. This bit shall be cleared to '0' when a Save or
98449  *    Restore operation is initiated or when written with '1'. Refer to section 4.23.2 of xHCI
98450  *    specification for more information. When this register is exposed by a Virtual Function (VF), the VMM
98451  *    determines the state of this bit as a function of the Save/Restore completion status for the
98452  *    selected VF. Refer to section 8 of xHCI specification for more information
98453  */
98454 #define USB3_USBSTS_SRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_SRE_SHIFT)) & USB3_USBSTS_SRE_MASK)
98455 #define USB3_USBSTS_CNR_MASK                     (0x800U)
98456 #define USB3_USBSTS_CNR_SHIFT                    (11U)
98457 /*! CNR - Controller Not Ready (CNR), RO. Default = '1'. '0' = Ready and '1' = Not Ready. When this
98458  *    bit is '1', software shall not read or write any register of the xHC, other than those
98459  *    explicitly listed in the Design Specification section titled Register Accessibility. This flag is set
98460  *    by the xHC after a Chip Hardware Reset and cleared when the xHC is ready to begin accepting
98461  *    register reads or writes to all registers. This flag shall remain cleared ('0') until the next
98462  *    Chip Hardware Reset
98463  */
98464 #define USB3_USBSTS_CNR(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_CNR_SHIFT)) & USB3_USBSTS_CNR_MASK)
98465 #define USB3_USBSTS_HCE_MASK                     (0x1000U)
98466 #define USB3_USBSTS_HCE_SHIFT                    (12U)
98467 /*! HCE - Host Controller Error (HCE), RO. Default = '0'. '0' = No internal xHC error conditions
98468  *    exist and '1' = Internal xHC error condition. This flag shall be set to indicate that an internal
98469  *    error condition has been detected which requires software to reset and reinitialize the xHC.
98470  *    Refer to section 4.24.1 of xHCI specification for more information
98471  */
98472 #define USB3_USBSTS_HCE(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_HCE_SHIFT)) & USB3_USBSTS_HCE_MASK)
98473 /*! @} */
98474 
98475 /*! @name PAGESIZE - Page Size */
98476 /*! @{ */
98477 #define USB3_PAGESIZE_PAGESIZE_MASK              (0xFFFFU)
98478 #define USB3_PAGESIZE_PAGESIZE_SHIFT             (0U)
98479 /*! PAGESIZE - Page Size, RO. Default = Implementation defined. This field defines the page size
98480  *    supported by the xHC implementation. This xHC supports a page size of 2^(n+12) if bit n is Set.
98481  *    For example, if bit 0 is Set, the xHC supports 4k byte page sizes. For a Virtual Function, this
98482  *    register reflects the page size selected in the System Page Size field of the SR-IOV Extended
98483  *    Capability structure. For the Physical Function 0, this register reflects the implementation
98484  *    dependent default xHC page size. Various xHC resources reference PAGESIZE to describe their
98485  *    minimum alignment requirements. The maximum possible page size is 128M
98486  */
98487 #define USB3_PAGESIZE_PAGESIZE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PAGESIZE_PAGESIZE_SHIFT)) & USB3_PAGESIZE_PAGESIZE_MASK)
98488 /*! @} */
98489 
98490 /*! @name DNCTRL - Device Notification Control */
98491 /*! @{ */
98492 #define USB3_DNCTRL_N0_MASK                      (0x1U)
98493 #define USB3_DNCTRL_N0_SHIFT                     (0U)
98494 /*! N0 - Notification Enable flag 0
98495  */
98496 #define USB3_DNCTRL_N0(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N0_SHIFT)) & USB3_DNCTRL_N0_MASK)
98497 #define USB3_DNCTRL_N1_MASK                      (0x2U)
98498 #define USB3_DNCTRL_N1_SHIFT                     (1U)
98499 /*! N1 - Notification Enable flag 1
98500  */
98501 #define USB3_DNCTRL_N1(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N1_SHIFT)) & USB3_DNCTRL_N1_MASK)
98502 #define USB3_DNCTRL_N2_MASK                      (0x4U)
98503 #define USB3_DNCTRL_N2_SHIFT                     (2U)
98504 /*! N2 - Notification Enable flag 2. LATENCY_TOLERANCE_MESSAGE
98505  */
98506 #define USB3_DNCTRL_N2(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N2_SHIFT)) & USB3_DNCTRL_N2_MASK)
98507 #define USB3_DNCTRL_N3_MASK                      (0x8U)
98508 #define USB3_DNCTRL_N3_SHIFT                     (3U)
98509 /*! N3 - Notification Enable flag 3. BUS_INTERVAL_ADJUSTMENT_MESSAGE
98510  */
98511 #define USB3_DNCTRL_N3(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N3_SHIFT)) & USB3_DNCTRL_N3_MASK)
98512 #define USB3_DNCTRL_N4_MASK                      (0x10U)
98513 #define USB3_DNCTRL_N4_SHIFT                     (4U)
98514 /*! N4 - Notification Enable flag 4
98515  */
98516 #define USB3_DNCTRL_N4(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N4_SHIFT)) & USB3_DNCTRL_N4_MASK)
98517 #define USB3_DNCTRL_N5_MASK                      (0x20U)
98518 #define USB3_DNCTRL_N5_SHIFT                     (5U)
98519 /*! N5 - Notification Enable flag 5
98520  */
98521 #define USB3_DNCTRL_N5(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N5_SHIFT)) & USB3_DNCTRL_N5_MASK)
98522 #define USB3_DNCTRL_N6_MASK                      (0x40U)
98523 #define USB3_DNCTRL_N6_SHIFT                     (6U)
98524 /*! N6 - Notification Enable flag 6
98525  */
98526 #define USB3_DNCTRL_N6(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N6_SHIFT)) & USB3_DNCTRL_N6_MASK)
98527 #define USB3_DNCTRL_N7_MASK                      (0x80U)
98528 #define USB3_DNCTRL_N7_SHIFT                     (7U)
98529 /*! N7 - Notification Enable flag 7
98530  */
98531 #define USB3_DNCTRL_N7(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N7_SHIFT)) & USB3_DNCTRL_N7_MASK)
98532 #define USB3_DNCTRL_N8_MASK                      (0x100U)
98533 #define USB3_DNCTRL_N8_SHIFT                     (8U)
98534 /*! N8 - Notification Enable flag 8
98535  */
98536 #define USB3_DNCTRL_N8(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N8_SHIFT)) & USB3_DNCTRL_N8_MASK)
98537 #define USB3_DNCTRL_N9_MASK                      (0x200U)
98538 #define USB3_DNCTRL_N9_SHIFT                     (9U)
98539 /*! N9 - Notification Enable flag 9
98540  */
98541 #define USB3_DNCTRL_N9(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N9_SHIFT)) & USB3_DNCTRL_N9_MASK)
98542 #define USB3_DNCTRL_N10_MASK                     (0x400U)
98543 #define USB3_DNCTRL_N10_SHIFT                    (10U)
98544 /*! N10 - Notification Enable flag 10
98545  */
98546 #define USB3_DNCTRL_N10(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N10_SHIFT)) & USB3_DNCTRL_N10_MASK)
98547 #define USB3_DNCTRL_N11_MASK                     (0x800U)
98548 #define USB3_DNCTRL_N11_SHIFT                    (11U)
98549 /*! N11 - Notification Enable flag 11
98550  */
98551 #define USB3_DNCTRL_N11(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N11_SHIFT)) & USB3_DNCTRL_N11_MASK)
98552 #define USB3_DNCTRL_N12_MASK                     (0x1000U)
98553 #define USB3_DNCTRL_N12_SHIFT                    (12U)
98554 /*! N12 - Notification Enable flag 12
98555  */
98556 #define USB3_DNCTRL_N12(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N12_SHIFT)) & USB3_DNCTRL_N12_MASK)
98557 #define USB3_DNCTRL_N13_MASK                     (0x2000U)
98558 #define USB3_DNCTRL_N13_SHIFT                    (13U)
98559 /*! N13 - Notification Enable flag 13
98560  */
98561 #define USB3_DNCTRL_N13(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N13_SHIFT)) & USB3_DNCTRL_N13_MASK)
98562 #define USB3_DNCTRL_N14_MASK                     (0x4000U)
98563 #define USB3_DNCTRL_N14_SHIFT                    (14U)
98564 /*! N14 - Notification Enable flag 14
98565  */
98566 #define USB3_DNCTRL_N14(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N14_SHIFT)) & USB3_DNCTRL_N14_MASK)
98567 #define USB3_DNCTRL_N15_MASK                     (0x8000U)
98568 #define USB3_DNCTRL_N15_SHIFT                    (15U)
98569 /*! N15 - Notification Enable flag 15
98570  */
98571 #define USB3_DNCTRL_N15(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N15_SHIFT)) & USB3_DNCTRL_N15_MASK)
98572 /*! @} */
98573 
98574 /*! @name CRCR_LO - Command Ring Control Register Low */
98575 /*! @{ */
98576 #define USB3_CRCR_LO_RCS_MASK                    (0x1U)
98577 #define USB3_CRCR_LO_RCS_SHIFT                   (0U)
98578 /*! RCS - Ring Cycle State (RCS), RW. This bit identifies the value of the xHC Consumer Cycle State
98579  *    (CCS) flag for the TRB referenced by the Command Ring Pointer. Refer to section 4.9.3 of xHCI
98580  *    specification for more information. Writes to this flag are ignored if Command Ring Running
98581  *    (CRR) is '1'. If the CRCR is written while the Command Ring is stopped (CRR = '0'), then the
98582  *    value of this flag shall be used to fetch the first Command TRB the next time the Host Controller
98583  *    Doorbell register is written with the DB Reason field set to Host Controller Command. If the
98584  *    CRCR is not written while the Command Ring is stopped (CRR = '0'), then the Command Ring shall
98585  *    begin fetching Command TRBs using the current value of the internal Command Ring CCS flag.
98586  *    Reading this flag always returns '0'
98587  */
98588 #define USB3_CRCR_LO_RCS(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_RCS_SHIFT)) & USB3_CRCR_LO_RCS_MASK)
98589 #define USB3_CRCR_LO_CS_MASK                     (0x2U)
98590 #define USB3_CRCR_LO_CS_SHIFT                    (1U)
98591 /*! CS - Command Stop (CS), RW1S. Default = '0'. Writing a '1' to this bit shall stop the operation
98592  *    of the Command Ring after the completion of the currently executing command, and generate a
98593  *    Command Completion Event with the Completion Code set to Command Ring Stopped and the Command
98594  *    TRB Pointer set to the current value of the Command Ring Dequeue Pointer. Refer to section
98595  *    4.6.1.1 of xHCI specification for more information on stopping a command. The next write to the
98596  *    Host Controller Doorbell with DB Reason field set to Host Controller Command shall restart the
98597  *    Command Ring operation. Writes to this flag are ignored by the xHC if Command Ring Running (CRR)
98598  *    = '0'. Reading this bit shall always return '0'
98599  */
98600 #define USB3_CRCR_LO_CS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CS_SHIFT)) & USB3_CRCR_LO_CS_MASK)
98601 #define USB3_CRCR_LO_CA_MASK                     (0x4U)
98602 #define USB3_CRCR_LO_CA_SHIFT                    (2U)
98603 /*! CA - Command Abort (CA), RW1S. Default = '0'. Writing a '1' to this bit shall immediately
98604  *    terminate the currently executing command, stop the Command Ring, and generate a Command Completion
98605  *    Event with the Completion Code set to Command Ring Stopped. Refer to section 4.6.1.2 of xHCI
98606  *    specification for more information on aborting a command. The next write to the Host Controller
98607  *    Doorbell with DB Reason field set to Host Controller Command shall restart the Command Ring
98608  *    operation. Writes to this flag are ignored by the xHC if Command Ring Running (CRR) = '0'.
98609  *    Reading this bit always returns '0'
98610  */
98611 #define USB3_CRCR_LO_CA(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CA_SHIFT)) & USB3_CRCR_LO_CA_MASK)
98612 #define USB3_CRCR_LO_CRR_MASK                    (0x8U)
98613 #define USB3_CRCR_LO_CRR_SHIFT                   (3U)
98614 /*! CRR - Command Ring Running (CRR), RO. Default = '0'. This flag is set to '1' if the Run/Stop
98615  *    (R/S) bit is '1' and the Host Controller Doorbell register is written with the DB Reason field
98616  *    set to Host Controller Command. It is cleared to '0' when the Command Ring is stopped after
98617  *    writing a '1' to the Command Stop (CS) or Command Abort (CA) flags, or if the R/S bit is cleared
98618  *    to '0'
98619  */
98620 #define USB3_CRCR_LO_CRR(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CRR_SHIFT)) & USB3_CRCR_LO_CRR_MASK)
98621 #define USB3_CRCR_LO_CRPtr_L_MASK                (0xFFFFFFC0U)
98622 #define USB3_CRCR_LO_CRPtr_L_SHIFT               (6U)
98623 /*! CRPtr_L - Command Ring Pointer Low, RW. Default = 0. This field defines low order bits of the
98624  *    initial value of the 64-bit Command Ring Dequeue Pointer. Writes to this field are ignored when
98625  *    Command Ring Running (CRR) = '1'. If the CRCR is written while the Command Ring is stopped
98626  *    (CCR = '0'), the value of this field shall be used to fetch the first Command TRB the next time
98627  *    the Host Controller Doorbell register is written with the DB Reason field set to Host
98628  *    Controller Command. If the CRCR is not written while the Command Ring is stopped (CCR = '0') then the
98629  *    Command Ring shall begin fetching Command TRBs at the current value of the internal xHC Command
98630  *    Ring Dequeue Pointer. Reading this field always returns zero
98631  */
98632 #define USB3_CRCR_LO_CRPtr_L(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CRPtr_L_SHIFT)) & USB3_CRCR_LO_CRPtr_L_MASK)
98633 /*! @} */
98634 
98635 /*! @name CRCR_HI - Command Ring Control Register High */
98636 /*! @{ */
98637 #define USB3_CRCR_HI_CRPtr_H_MASK                (0xFFFFFFFFU)
98638 #define USB3_CRCR_HI_CRPtr_H_SHIFT               (0U)
98639 /*! CRPtr_H - Command Ring Pointer High, RW. Default = 0. This field defines high order bits of the
98640  *    initial value of the 64-bit Command Ring Dequeue Pointer. Writes to this field are ignored
98641  *    when Command Ring Running (CRR) = '1'. If the CRCR is written while the Command Ring is stopped
98642  *    (CCR = '0'), the value of this field shall be used to fetch the first Command TRB the next time
98643  *    the Host Controller Doorbell register is written with the DB Reason field set to Host
98644  *    Controller Command. If the CRCR is not written while the Command Ring is stopped (CCR = '0') then the
98645  *    Command Ring shall begin fetching Command TRBs at the current value of the internal xHC
98646  *    Command Ring Dequeue Pointer. Reading this field always returns zero
98647  */
98648 #define USB3_CRCR_HI_CRPtr_H(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_HI_CRPtr_H_SHIFT)) & USB3_CRCR_HI_CRPtr_H_MASK)
98649 /*! @} */
98650 
98651 /*! @name DCBAAP_LO - Device Context Base Address Array Pointer(LOW) */
98652 /*! @{ */
98653 #define USB3_DCBAAP_LO_DCBAAPtr_L_MASK           (0xFFFFFFC0U)
98654 #define USB3_DCBAAP_LO_DCBAAPtr_L_SHIFT          (6U)
98655 /*! DCBAAPtr_L - Device Context Base Address Array Pointer, RW. Default = 0. This field defines low
98656  *    order bits of the 64-bit base address of the Device Context Pointer Array. A table of address
98657  *    pointers that reference Device Context structures for the devices attached to the host
98658  */
98659 #define USB3_DCBAAP_LO_DCBAAPtr_L(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DCBAAP_LO_DCBAAPtr_L_SHIFT)) & USB3_DCBAAP_LO_DCBAAPtr_L_MASK)
98660 /*! @} */
98661 
98662 /*! @name DCBAAP_HI - Device Context Base Address Array Pointer (HIGH) */
98663 /*! @{ */
98664 #define USB3_DCBAAP_HI_DCBAAPtr_H_MASK           (0xFFFFFFFFU)
98665 #define USB3_DCBAAP_HI_DCBAAPtr_H_SHIFT          (0U)
98666 /*! DCBAAPtr_H - Device Context Base Address Array Pointer, RW. Default = 0. This field defines high
98667  *    order bits of the 64-bit base address of the Device Context Pointer Array. A table of address
98668  *    pointers that reference Device Context structures for the devices attached to the host
98669  */
98670 #define USB3_DCBAAP_HI_DCBAAPtr_H(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DCBAAP_HI_DCBAAPtr_H_SHIFT)) & USB3_DCBAAP_HI_DCBAAPtr_H_MASK)
98671 /*! @} */
98672 
98673 /*! @name CONFIG - Configure */
98674 /*! @{ */
98675 #define USB3_CONFIG_MaxSlotsEn_MASK              (0xFFU)
98676 #define USB3_CONFIG_MaxSlotsEn_SHIFT             (0U)
98677 /*! MaxSlotsEn - Max Device Slots Enabled (MaxSlotsEn), RW. Default = 0. This field specifies the
98678  *    maximum number of enabled Device Slots. Valid values are in the range of 0 to MaxSlots. Enabled
98679  *    Devices Slots are allocated contiguously. e.g. A value of 16 specifies that Device Slots 1 to
98680  *    16 are active. A value of 0 disables all Device Slots. A disabled Device Slot shall not
98681  *    respond to Doorbell Register references. This field shall not be modified by software if the xHC is
98682  *    running (Run/Stop (R/S) = 1)
98683  */
98684 #define USB3_CONFIG_MaxSlotsEn(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CONFIG_MaxSlotsEn_SHIFT)) & USB3_CONFIG_MaxSlotsEn_MASK)
98685 /*! @} */
98686 
98687 /*! @name PORTSC1USB2 - USB2 Port Status and Control */
98688 /*! @{ */
98689 #define USB3_PORTSC1USB2_CCS_MASK                (0x1U)
98690 #define USB3_PORTSC1USB2_CCS_SHIFT               (0U)
98691 /*! CCS - Current Connect Status (CCS), ROS. Default = '0'. '1' = A device is connected to the port.
98692  *    '0' = A device is not connected. This value reflects the current state of the port, and may
98693  *    not correspond directly to the event that caused the Connect Status Change (CSC) bit to be set
98694  *    to '1'. Refer to sections 4.19.3 and 4.19.4 of xHCI specification for more details on the
98695  *    Connect Status Change (CSC) assertion conditions. This flag is '0' if PP is '0'
98696  */
98697 #define USB3_PORTSC1USB2_CCS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_CCS_SHIFT)) & USB3_PORTSC1USB2_CCS_MASK)
98698 #define USB3_PORTSC1USB2_PED_MASK                (0x2U)
98699 #define USB3_PORTSC1USB2_PED_SHIFT               (1U)
98700 /*! PED - Port Enabled/Disabled (PED), RW1CS. Default = '0'. '1' = Enabled. '0' = Disabled. Ports
98701  *    may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag. A
98702  *    port may be disabled by software writing a '1' to this flag. This flag shall automatically be
98703  *    cleared to '0' by a disconnect event or other fault condition. Note that the bit status does
98704  *    not change until the port state actually changes. There may be a delay in disabling or enabling
98705  *    a port due to other host controller or bus events. When the port is disabled (PED = '0')
98706  *    downstream propagation of data is blocked on this port, except for reset. When the port is in the
98707  *    Disabled state, software shall reset the port (PR = '1') to transition PED to '1' and the port
98708  *    to the Enabled state. Note that when software writes this bit to a '1', it shall also write a
98709  *    '0' to the PR bit. This flag is '0' if PP is '0'
98710  */
98711 #define USB3_PORTSC1USB2_PED(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PED_SHIFT)) & USB3_PORTSC1USB2_PED_MASK)
98712 #define USB3_PORTSC1USB2_OCA_MASK                (0x8U)
98713 #define USB3_PORTSC1USB2_OCA_SHIFT               (3U)
98714 /*! OCA - Over-current Active (OCA), RO. Default = '0'. '1' = This port currently has an
98715  *    over-current condition. '0' = This port does not have an over-current condition. This bit shall
98716  *    automatically transition from a '1' to a '0' when the over-current condition is removed
98717  */
98718 #define USB3_PORTSC1USB2_OCA(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_OCA_SHIFT)) & USB3_PORTSC1USB2_OCA_MASK)
98719 #define USB3_PORTSC1USB2_PR_MASK                 (0x10U)
98720 #define USB3_PORTSC1USB2_PR_SHIFT                (4U)
98721 /*! PR - Port Reset (PR), RW1S. Default = '0'. '1' = Port Reset signaling is asserted. '0' = Port is
98722  *    not in Reset. When software writes a '1' to this bit generating a '0' to '1' transition, the
98723  *    bus reset sequence is initiated; USB2 protocol ports shall execute the bus reset sequence as
98724  *    defined in the USB2 Spec. PR remains set until reset signaling is completed by the root hub.
98725  *    Note that software shall write a '1' to this flag to transition a USB2 port from the Polling
98726  *    state to the Enabled state. Refer to sections 4.15.2.3 and 4.19.1.1 of xHCI specification. This
98727  *    flag is '0' if PP is '0'
98728  */
98729 #define USB3_PORTSC1USB2_PR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PR_SHIFT)) & USB3_PORTSC1USB2_PR_MASK)
98730 #define USB3_PORTSC1USB2_PLS_MASK                (0x1E0U)
98731 #define USB3_PORTSC1USB2_PLS_SHIFT               (5U)
98732 /*! PLS - Port Link State (PLS), RWS. Default = RxDetect ('5'). This field is used to power manage
98733  *    the port and reflects its current link state. When the port is in the Enabled state, system
98734  *    software may set the link U state by writing this field. System software may also write this
98735  *    field to force a Disabled to Disconnected state transition of the port. Write Values: 0: The link
98736  *    shall transition to a U0 state from any of the U states. 2: The link should transition to the
98737  *    U2 State. 3: The link shall transition to a U3 state from the U0 state. This action
98738  *    selectively suspends the device connected to this port. While the Port Link State = U3, the hub does not
98739  *    propagate downstream-directed traffic to this port, but the hub shall respond to resume
98740  *    signaling from the port. 1,4-14: Ignored. 15: If the port is in the U3 state (PLS = U3), then the
98741  *    link shall remain in the U3 state and the port shall transition to the Resume substate, else
98742  *    ignored. Refer to section 4.15.2 of xHCI specification for more information. State Encoding: 0:
98743  *    Link is in the U0 State, 1: Link is in the U1 State, 2: Link is in the U2 State, 3: Link is in
98744  *    the U3 State (Device Suspended), 4: Link is in the Disabled State, 5: Link is in the RxDetect
98745  *    State, 6: Link is in the Inactive State, 7: Link is in the Polling State, 8: Link is in the
98746  *    Recovery State, 9: Link is in the Hot Reset State, 10 Link is in the Compliance Mode State, 11:
98747  *    Link is in the Test Mode State, 12-14: Reserved, 15: Link is in the Resume State. Note: The
98748  *    Port Link State Write Strobe (LWS) shall also be set to '1' to write this field. This field is
98749  *    undefined if PP = '0'. Writing a value of '2' to this field shall request LPM, asserting L1
98750  *    signaling on the USB2 bus. Software may read this field to determine if the transition to the U2
98751  *    state was successful. Writing a value of '0' shall deassert L1 signaling on the USB. Writing
98752  *    a value of '1' shall have no effect. The U1 state shall never be reported by a USB2 protocol
98753  *    port. Note: Transitions between different states are not reflected until the transition is
98754  *    complete. Refer to section 4.19 of xHCI specification for PLS transition conditions. Refer to
98755  *    sections 4.15.2 and 4.23.5 for more information on the use of this field. Refer to the USB2 LPM
98756  *    ECR for more information on USB link power management operation
98757  */
98758 #define USB3_PORTSC1USB2_PLS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PLS_SHIFT)) & USB3_PORTSC1USB2_PLS_MASK)
98759 #define USB3_PORTSC1USB2_PP_MASK                 (0x200U)
98760 #define USB3_PORTSC1USB2_PP_SHIFT                (9U)
98761 /*! PP - Port Power (PP), RWS. Default = '1'. This flag reflects a port's logical, power control
98762  *    state. Because host controllers can implement different methods of port power switching, this
98763  *    flag may or may not represent whether (VBus) power is actually applied to the port. When PP
98764  *    equals a '0' the port is nonfunctional and shall not report attaches, detaches, or Port Link State
98765  *    (PLS) changes. However, the port shall report over-current conditions when PP = '0' if PPC =
98766  *    '0'. After modifying PP, software shall read PP and confirm that it has reached its target
98767  *    state before modifying it again, undefined behavior may occur if this procedure is not followed.
98768  *    '0' = This port is in the Powered-off state. '1' = This port is not in the Powered-off state.
98769  *    If the Port Power Control (PPC) flag in the HCCPARAMS register is '1', then xHC has port power
98770  *    control switches and this bit represents the current setting of the switch ('0' = off,
98771  *    '1'=on). If the Port Power Control (PPC) flag in the HCCPARAMS register is '0', then xHC does not
98772  *    have port power control switches and each port is hard wired to power, and not affected by this
98773  *    bit. When an over-current condition is detected on a powered port, the xHC shall transition the
98774  *    PP bit in each affected port from a '1' to '0' (removing power from the port). Refer to
98775  *    section 4.19.4 for more information
98776  */
98777 #define USB3_PORTSC1USB2_PP(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PP_SHIFT)) & USB3_PORTSC1USB2_PP_MASK)
98778 #define USB3_PORTSC1USB2_PortSpeed_MASK          (0x3C00U)
98779 #define USB3_PORTSC1USB2_PortSpeed_SHIFT         (10U)
98780 /*! PortSpeed - Port Speed (Port Speed), ROS. Default = '0'. This field identifies the speed of the
98781  *    connected USB Device. This field is only relevant if a device is connected (CCS = '1') in all
98782  *    other cases this field shall indicate Undefined Speed. Possible values: 0: Undefined Speed
98783  *    1-15: Protocol Speed ID (PSI), refer to section 7.2.1 of xHCI specification for the definition of
98784  *    PSIV field in the PSI Dword. Note: This field is invalid on a USB2 protocol port until after
98785  *    the port is reset
98786  */
98787 #define USB3_PORTSC1USB2_PortSpeed(x)            (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PortSpeed_SHIFT)) & USB3_PORTSC1USB2_PortSpeed_MASK)
98788 #define USB3_PORTSC1USB2_PIC_MASK                (0xC000U)
98789 #define USB3_PORTSC1USB2_PIC_SHIFT               (14U)
98790 /*! PIC - Port Indicator Control (PIC), RWS. Default = '0'. Writing to these bits has no effect if
98791  *    the Port Indicators (PIND) bit in the HCCPARAMS register is a '0'. If PIND bit is a '1', then
98792  *    the bit encodings are: 0: Port indicators are off, 1: Amber, 2: Green, 3: Undefined. Refer to
98793  *    the USB2 Specification section 11.5.3 for a description on how these bits shall be used. This
98794  *    field is '0' if PP is '0'
98795  */
98796 #define USB3_PORTSC1USB2_PIC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PIC_SHIFT)) & USB3_PORTSC1USB2_PIC_MASK)
98797 #define USB3_PORTSC1USB2_LWS_MASK                (0x10000U)
98798 #define USB3_PORTSC1USB2_LWS_SHIFT               (16U)
98799 /*! LWS - Port Link State Write Strobe (LWS), RW. Default = '0'. When this bit is set to '1' on a
98800  *    write reference to this register, this flag enables writes to the PLS field. When '0', write
98801  *    data in PLS field is ignored. Reads to this bit return '0'
98802  */
98803 #define USB3_PORTSC1USB2_LWS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_LWS_SHIFT)) & USB3_PORTSC1USB2_LWS_MASK)
98804 #define USB3_PORTSC1USB2_CSC_MASK                (0x20000U)
98805 #define USB3_PORTSC1USB2_CSC_SHIFT               (17U)
98806 /*! CSC - Connect Status Change (CSC), RW1CS. Default = '0'. '1' = Change in CCS. '0' = No change.
98807  *    This flag indicates a change has occurred in the ports Current Connect Status (CCS) or Cold
98808  *    Attach Status (CAS) bits. Note that this flag shall not be set if the CCS transition was due to
98809  *    software setting PP to '0', or the CAS transition was due to software setting WPR to '1'. The
98810  *    xHC sets this bit to '1' for all changes to the port device connect status, even if system
98811  *    software has not cleared an existing Connect Status Change. For example, the insertion status
98812  *    changes twice before system software has cleared the changed condition, root hub hardware will be
98813  *    setting an already-set bit (i.e., the bit will remain 1). Software shall clear this bit by
98814  *    writing a '1' to it. Refer to section 4.19.2 of xHCI specification for more information on change
98815  *    bit usage
98816  */
98817 #define USB3_PORTSC1USB2_CSC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_CSC_SHIFT)) & USB3_PORTSC1USB2_CSC_MASK)
98818 #define USB3_PORTSC1USB2_PEC_MASK                (0x40000U)
98819 #define USB3_PORTSC1USB2_PEC_SHIFT               (18U)
98820 /*! PEC - Port Enabled/Disabled Change (PEC), RW1CS. Default = '0'. '1' = change in PED. '0' = No
98821  *    change. Note that this flag shall not be set if the PED transition was due to software setting
98822  *    PP to '0'. Software shall clear this bit by writing a '1' to it. Refer to section 4.19.2 of
98823  *    xHCI specification for more information on change bit usage. This bit shall be set to '1' only
98824  *    when the port is disabled due to the appropriate conditions existing at the EOF2 point (refer to
98825  *    section 11.8.1 of the USB2 Specification for the definition of a Port Error)
98826  */
98827 #define USB3_PORTSC1USB2_PEC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PEC_SHIFT)) & USB3_PORTSC1USB2_PEC_MASK)
98828 #define USB3_PORTSC1USB2_WRC_MASK                (0x80000U)
98829 #define USB3_PORTSC1USB2_WRC_SHIFT               (19U)
98830 /*! WRC - Warm Port Reset Change (WRC), RW1CS/RsvdZ. Default = '0'. This bit is set when Warm Reset
98831  *    processing on this port completes. '0' = No change. '1' = Warm Reset complete. Note that this
98832  *    flag shall not be set to '1' if the Warm Reset processing was forced to terminate due to
98833  *    software clearing PP or PED to '0'. Software shall clear this bit by writing a '1' to it. Refer to
98834  *    section 4.19.5.1 of xHCI specification. Refer to section 4.19.2 of xHCI specification for more
98835  *    information on change bit usage. This bit only applies to USB3 protocol ports. For USB2
98836  *    protocol ports it shall be RsvdZ
98837  */
98838 #define USB3_PORTSC1USB2_WRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WRC_SHIFT)) & USB3_PORTSC1USB2_WRC_MASK)
98839 #define USB3_PORTSC1USB2_OCC_MASK                (0x100000U)
98840 #define USB3_PORTSC1USB2_OCC_SHIFT               (20U)
98841 /*! OCC - Over-current Change (OCC), RW1CS. Default = '0'. This bit shall be set to a '1' when there
98842  *    is a '0' to '1' or '1' to '0' transition of Over-current Active (OCA). Software shall clear
98843  *    this bit by writing a '1' to it. Refer to section 4.19.2 of xHCI specification for more
98844  *    information on change bit usage
98845  */
98846 #define USB3_PORTSC1USB2_OCC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_OCC_SHIFT)) & USB3_PORTSC1USB2_OCC_MASK)
98847 #define USB3_PORTSC1USB2_PRC_MASK                (0x200000U)
98848 #define USB3_PORTSC1USB2_PRC_SHIFT               (21U)
98849 /*! PRC - Port Reset Change (PRC), RW1CS. Default = '0'. This flag is set to '1' due to a '1' to '0'
98850  *    transition of Port Reset (PR), e.g. when any reset processing (Warm or Hot) on this port is
98851  *    complete. Note that this flag shall not be set to '1' if the reset processing was forced to
98852  *    terminate due to software clearing PP or PED to '0'. '0' = No change. '1' = Reset complete.
98853  *    Software shall clear this bit by writing a '1' to it. Refer to section 4.19.5 of xHCI
98854  *    specification. Refer to section 4.19.2 of xHCI specification for more information on change bit usage
98855  */
98856 #define USB3_PORTSC1USB2_PRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PRC_SHIFT)) & USB3_PORTSC1USB2_PRC_MASK)
98857 #define USB3_PORTSC1USB2_PLC_MASK                (0x400000U)
98858 #define USB3_PORTSC1USB2_PLC_SHIFT               (22U)
98859 /*! PLC - Port Link State Change (PLC), RW1CS. Default = '0'. This flag is set to '1' due to the
98860  *    following PLS transitions: U3 -> Resume (Wakeup signaling from a device), Resume -> Recovery ->
98861  *    U0 (Device Resume complete (USB3 protocol ports only)), Resume -> U0 (Device Resume complete
98862  *    (USB2 protocol ports only)), U3 -> Recovery -> U0 (Software Resume complete (USB3 protocol ports
98863  *    only)), U3 -> U0 (Software Resume complete (USB2 protocol ports only)), U2 -> U0 (L1 Resume
98864  *    complete (USB2 protocol ports only)), U0 -> U0 (L1 Entry Reject (USB2 protocol ports only)),
98865  *    Any state -> Inactive (Error (USB3 protocol ports only)). Note that this flag shall not be set
98866  *    if the PLS transition was due to software setting PP to 0. Refer to section 4.23.5 of xHCI
98867  *    specification for more information. '0' = No change. '1' = Link Status Changed. Software shall
98868  *    clear this bit by writing a '1' to it. Refer to PLC Condition: references in section 4.19.1 for
98869  *    the specific port state transitions that set this flag. Refer to section 4.19.2 of xHCI
98870  *    specification for more information on change bit usage
98871  */
98872 #define USB3_PORTSC1USB2_PLC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PLC_SHIFT)) & USB3_PORTSC1USB2_PLC_MASK)
98873 #define USB3_PORTSC1USB2_CAS_MASK                (0x1000000U)
98874 #define USB3_PORTSC1USB2_CAS_SHIFT               (24U)
98875 /*! CAS - Cold Attach Status (CAS), RO. Default = '0'. '1' = Far-end Receiver Terminations were
98876  *    detected in the Disconnected state and the Root Hub Port State Machine was unable to advance to
98877  *    the Enabled state. Refer to sections 4.19.8 of xHCI specification for more details on the Cold
98878  *    Attach Status (CAS) assertion conditions. Software shall clear this bit by writing a '1' to WPR
98879  *    or the xHC shall clear this bit if CCS transitions to '1'. This flag is '0' for USB2 protocol
98880  *    ports
98881  */
98882 #define USB3_PORTSC1USB2_CAS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_CAS_SHIFT)) & USB3_PORTSC1USB2_CAS_MASK)
98883 #define USB3_PORTSC1USB2_WCE_MASK                (0x2000000U)
98884 #define USB3_PORTSC1USB2_WCE_SHIFT               (25U)
98885 /*! WCE - Wake on Connect Enable (WCE), RWS. Default = '0'. Writing this bit to a '1' enables the
98886  *    port to be sensitive to device connects as system wake-up events. Refer to section 4.15 of xHCI
98887  *    specification for operational model
98888  */
98889 #define USB3_PORTSC1USB2_WCE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WCE_SHIFT)) & USB3_PORTSC1USB2_WCE_MASK)
98890 #define USB3_PORTSC1USB2_WDE_MASK                (0x4000000U)
98891 #define USB3_PORTSC1USB2_WDE_SHIFT               (26U)
98892 /*! WDE - Wake on Disconnect Enable (WDE), RWS. Default = '0'. Writing this bit to a '1' enables the
98893  *    port to be sensitive to device disconnects as system wake-up events. Refer to section 4.15 of
98894  *    xHCI specification for operational model
98895  */
98896 #define USB3_PORTSC1USB2_WDE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WDE_SHIFT)) & USB3_PORTSC1USB2_WDE_MASK)
98897 #define USB3_PORTSC1USB2_WOE_MASK                (0x8000000U)
98898 #define USB3_PORTSC1USB2_WOE_SHIFT               (27U)
98899 /*! WOE - Wake on Over-current Enable (WOE), RWS. Default = '0'. Writing this bit to a '1' enables
98900  *    the port to be sensitive to over-current conditions as system wake-up events. Refer to section
98901  *    4.15 of xHCI specification for operational model
98902  */
98903 #define USB3_PORTSC1USB2_WOE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WOE_SHIFT)) & USB3_PORTSC1USB2_WOE_MASK)
98904 #define USB3_PORTSC1USB2_DR_MASK                 (0x40000000U)
98905 #define USB3_PORTSC1USB2_DR_SHIFT                (30U)
98906 /*! DR - Device Removable (DR), RO. This flag indicates if this port has a removable device
98907  *    attached. '0' = Device is removable; '1' = Device is non-removable
98908  */
98909 #define USB3_PORTSC1USB2_DR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_DR_SHIFT)) & USB3_PORTSC1USB2_DR_MASK)
98910 /*! @} */
98911 
98912 /*! @name PORTPMSC1USB2 - USB2 Port Power Management Status and Control */
98913 /*! @{ */
98914 #define USB3_PORTPMSC1USB2_L1S_MASK              (0x7U)
98915 #define USB3_PORTPMSC1USB2_L1S_SHIFT             (0U)
98916 /*! L1S - L1 Status (L1S), RO. Default = 0. This field is used by software to determine whether an
98917  *    L1-based suspend request (LPM transaction) was successful, specifically: 0: Invalid - This
98918  *    field shall be ignored by software. 1: Success - Port successfully transitioned to L1 (ACK) 2: Not
98919  *    Yet - Device is unable to enter L1 at this time (NYET) 3: Not Supported - Device does not
98920  *    support L1 transitions (STALL) 4: Timeout/Error - Device failed to respond to the LPM Transaction
98921  *    or an error occurred 5-7: Reserved The value of this field is only valid when the port
98922  *    resides in the L0 or L1 state (PLS = 0 or 2). Refer to section 4.23.5.1.1 of xHCI specification for
98923  *    more information
98924  */
98925 #define USB3_PORTPMSC1USB2_L1S(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_L1S_SHIFT)) & USB3_PORTPMSC1USB2_L1S_MASK)
98926 #define USB3_PORTPMSC1USB2_RWE_MASK              (0x8U)
98927 #define USB3_PORTPMSC1USB2_RWE_SHIFT             (3U)
98928 /*! RWE - Remote Wake Enable (RWE), RW. Default = '0'. System software sets this flag to enable or
98929  *    disable the device for remote wake from L1. The value of this flag shall temporarily (while in
98930  *    L1) override the current setting of the Remote Wake feature set by the standard
98931  *    Set/ClearFeature() commands defined in Universal Serial Bus Specification, revision 2.0, Chapter 9
98932  */
98933 #define USB3_PORTPMSC1USB2_RWE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_RWE_SHIFT)) & USB3_PORTPMSC1USB2_RWE_MASK)
98934 #define USB3_PORTPMSC1USB2_BESL_MASK             (0xF0U)
98935 #define USB3_PORTPMSC1USB2_BESL_SHIFT            (4U)
98936 /*! BESL - Best Effort Service Latency (BESL), RW. Default = 0. System software sets this field to
98937  *    indicate to the recipient device how long the xHC will drive resume if it (the xHC) initiates
98938  *    an exit from L1. The BESL value encoding is defined in Table 13. Note that the BESL field is
98939  *    used by both software and hardware controlled LPM. Refer to section 4.23.5.1.1 of xHCI
98940  *    specification for more information on BESL use. Refer to section 5.2.5 of xHCI specification for
98941  *    information on how DBESL may be used to establish an initial value for BESL
98942  */
98943 #define USB3_PORTPMSC1USB2_BESL(x)               (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_BESL_SHIFT)) & USB3_PORTPMSC1USB2_BESL_MASK)
98944 #define USB3_PORTPMSC1USB2_L1DS_MASK             (0xFF00U)
98945 #define USB3_PORTPMSC1USB2_L1DS_SHIFT            (8U)
98946 /*! L1DS - L1 Device Slot, RW. Default = 0. System software sets this field to indicate the ID of
98947  *    the Device Slot associated with the device directly attached to the Root Hub port. A value of
98948  *    '0' indicates no device is present. The xHC uses this field to lookup information necessary to
98949  *    generate the LPM Token packet
98950  */
98951 #define USB3_PORTPMSC1USB2_L1DS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_L1DS_SHIFT)) & USB3_PORTPMSC1USB2_L1DS_MASK)
98952 #define USB3_PORTPMSC1USB2_HLE_MASK              (0x10000U)
98953 #define USB3_PORTPMSC1USB2_HLE_SHIFT             (16U)
98954 /*! HLE - Hardware LPM Enable (HLE), RW. Default = '0'. If this bit is set to '1', then hardware
98955  *    controlled LPM shall be enabled for this port. Refer to section 4.23.5.1.1.1 of xHCI
98956  *    specification. If the USB2 Hardware LPM Capability is not supported (HLC = '0') this field shall be RsvdZ
98957  */
98958 #define USB3_PORTPMSC1USB2_HLE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_HLE_SHIFT)) & USB3_PORTPMSC1USB2_HLE_MASK)
98959 #define USB3_PORTPMSC1USB2_PTC_MASK              (0xF0000000U)
98960 #define USB3_PORTPMSC1USB2_PTC_SHIFT             (28U)
98961 /*! PTC - Port Test Control, RW. Default = '0'. When this field is '0', the port is NOT operating in
98962  *    a test mode. A non-zero value indicates that it is operating in test mode and the specific
98963  *    test mode is indicated by the specific value. A non-zero Port Test Control value is only valid
98964  *    to a port that is in the Powered-Off state (PLS = Disabled). If the port is not in this state,
98965  *    the xHC shall respond with the Port Test Control field set to Port Test Control Error. Refer
98966  *    to section 4.19.6 for the operational model for using these test modes. The encoding of the
98967  *    Test Mode bits for a USB2 protocol port are: 0: Test mode not enabled 1: Test J_STATE 2: Test
98968  *    K_STATE 3: Test SE0_NAK 4: Test Packet 5: Test FORCE_ENABLE 6-14: Reserved. 15: Port Test Control
98969  *    Error. Refer to the sections 7.1.20 and 11.24.2.13 of the USB2 spec for more information on
98970  *    Test Modes
98971  */
98972 #define USB3_PORTPMSC1USB2_PTC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_PTC_SHIFT)) & USB3_PORTPMSC1USB2_PTC_MASK)
98973 /*! @} */
98974 
98975 /*! @name PORT1HLPMC - USB2 Port Hardware LPM Control register */
98976 /*! @{ */
98977 #define USB3_PORT1HLPMC_HIRDM_MASK               (0x3U)
98978 #define USB3_PORT1HLPMC_HIRDM_SHIFT              (0U)
98979 /*! HIRDM - Host Initiated Resume Duration Mode (HIRDM), RWS. Default = 0h. Indicates which HIRD
98980  *    value should be used. The following are permissible values: 0: Initiate L1 using BESL only on
98981  *    timeout. (default) 1: Initiate L1 using BESLD on timeout. If rejected by device, initiate L1
98982  *    using BESL. 3-2: Reserved
98983  */
98984 #define USB3_PORT1HLPMC_HIRDM(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_PORT1HLPMC_HIRDM_SHIFT)) & USB3_PORT1HLPMC_HIRDM_MASK)
98985 #define USB3_PORT1HLPMC_L1_timeout_MASK          (0x3FCU)
98986 #define USB3_PORT1HLPMC_L1_timeout_SHIFT         (2U)
98987 /*! L1_timeout - L1 Timeout, RWS. Default = 00h. Timeout value for the L1 inactivity timer (LPM
98988  *    Timer). This field shall be set to 00h by the assertion of PR to '1'. Refer to section
98989  *    4.23.5.1.1.1 of xHci specification for more information on L1 Timeout operation. The following are
98990  *    permissible values: 00h 128 us. (default) 01h 256 us. 02h 512 us. 03h 768 us. ... FFh 65,280 us
98991  */
98992 #define USB3_PORT1HLPMC_L1_timeout(x)            (((uint32_t)(((uint32_t)(x)) << USB3_PORT1HLPMC_L1_timeout_SHIFT)) & USB3_PORT1HLPMC_L1_timeout_MASK)
98993 #define USB3_PORT1HLPMC_BESLD_MASK               (0x3C00U)
98994 #define USB3_PORT1HLPMC_BESLD_SHIFT              (10U)
98995 /*! BESLD - Best Effort Service Latency Deep (BESLD), RWS. Default = '0'. System software sets this
98996  *    field to indicate to the recipient device how long the xHC will drive resume on an exit from
98997  *    U2. Refer to section 4.23.5.1.1.1 of xHCI specification for more information on BESLD use. The
98998  *    BESLD value encoding is defined in Table 13. Refer to section 5.2.6 of xHCI specification for
98999  *    information on how DBESLD may be used to establish an initial value for BESLD
99000  */
99001 #define USB3_PORT1HLPMC_BESLD(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_PORT1HLPMC_BESLD_SHIFT)) & USB3_PORT1HLPMC_BESLD_MASK)
99002 /*! @} */
99003 
99004 /*! @name PORTSC1USB3 - USB3 Port Status and Control */
99005 /*! @{ */
99006 #define USB3_PORTSC1USB3_CCS_MASK                (0x1U)
99007 #define USB3_PORTSC1USB3_CCS_SHIFT               (0U)
99008 /*! CCS - Current Connect Status (CCS), ROS. Default = '0'. '1' = A device is connected to the port.
99009  *    '0' = A device is not connected. This value reflects the current state of the port, and may
99010  *    not correspond directly to the event that caused the Connect Status Change (CSC) bit to be set
99011  *    to '1'. Refer to sections 4.19.3 and 4.19.4 of xHCI specification for more details on the
99012  *    Connect Status Change (CSC) assertion conditions. This flag is '0' if PP is '0'
99013  */
99014 #define USB3_PORTSC1USB3_CCS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CCS_SHIFT)) & USB3_PORTSC1USB3_CCS_MASK)
99015 #define USB3_PORTSC1USB3_PED_MASK                (0x2U)
99016 #define USB3_PORTSC1USB3_PED_SHIFT               (1U)
99017 /*! PED - Port Enabled/Disabled (PED), RW1CS. Default = '0'. '1' = Enabled. '0' = Disabled. Ports
99018  *    may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag. A
99019  *    port may be disabled by software writing a '1' to this flag. This flag shall automatically be
99020  *    cleared to '0' by a disconnect event or other fault condition. Note that the bit status does
99021  *    not change until the port state actually changes. There may be a delay in disabling or enabling
99022  *    a port due to other host controller or bus events. When the port is disabled (PED = '0')
99023  *    downstream propagation of data is blocked on this port, except for reset. When the port is in the
99024  *    Polling state (after detecting an attach), the port shall automatically transition to the
99025  *    Enabled state and set PED to '1' upon the completion of successful link training. When the port is
99026  *    in the Disabled state, software shall write a 5 (RxDetect) to the PLS field to transition the
99027  *    port to the Disconnected state. Refer to section 4.19.1.2 of xHCI specification. PED shall
99028  *    automatically be cleared to '0' when PR is set to '1', and set to '1' when PR transitions from
99029  *    '1' to '0' after a successful reset. Refer to Port Reset (PR) bit for more information on how
99030  *    the PED bit is managed. Note that when software writes this bit to a '1', it shall also write a
99031  *    '0' to the PR bit. This flag is '0' if PP is '0'
99032  */
99033 #define USB3_PORTSC1USB3_PED(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PED_SHIFT)) & USB3_PORTSC1USB3_PED_MASK)
99034 #define USB3_PORTSC1USB3_OCA_MASK                (0x8U)
99035 #define USB3_PORTSC1USB3_OCA_SHIFT               (3U)
99036 /*! OCA - Over-current Active (OCA), RO. Default = '0'. '1' = This port currently has an
99037  *    over-current condition. '0' = This port does not have an over-current condition. This bit shall
99038  *    automatically transition from a '1' to a '0' when the over-current condition is removed
99039  */
99040 #define USB3_PORTSC1USB3_OCA(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_OCA_SHIFT)) & USB3_PORTSC1USB3_OCA_MASK)
99041 #define USB3_PORTSC1USB3_PR_MASK                 (0x10U)
99042 #define USB3_PORTSC1USB3_PR_SHIFT                (4U)
99043 /*! PR - Port Reset (PR), RW1S. Default = '0'. '1' = Port Reset signaling is asserted. '0' = Port is
99044  *    not in Reset. When software writes a '1' to this bit generating a '0' to '1' transition, the
99045  *    bus reset sequence is initiated; USB3 protocol ports shall execute the Hot Reset sequence as
99046  *    defined in the USB3 Spec. PR remains set until reset signaling is completed by the root hub.
99047  *    This flag is '0' if PP is '0'
99048  */
99049 #define USB3_PORTSC1USB3_PR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PR_SHIFT)) & USB3_PORTSC1USB3_PR_MASK)
99050 #define USB3_PORTSC1USB3_PLS_MASK                (0x1E0U)
99051 #define USB3_PORTSC1USB3_PLS_SHIFT               (5U)
99052 /*! PLS - Port Link State (PLS), RWS. Default = RxDetect ('5'). This field is used to power manage
99053  *    the port and reflects its current link state. When the port is in the Enabled state, system
99054  *    software may set the link U state by writing this field. System software may also write this
99055  *    field to force a Disabled to Disconnected state transition of the port. Write Values: 0: The link
99056  *    shall transition to a U0 state from any of the U states. 3: The link shall transition to a U3
99057  *    state from the U0 state. This action selectively suspends the device connected to this port.
99058  *    While the Port Link State = U3, the hub does not propagate downstream-directed traffic to this
99059  *    port, but the hub shall respond to resume signaling from the port. 5: If the port is in the
99060  *    Disabled state (PLS = Disabled, PP = '1'), then the link shall transition to a RxDetect state
99061  *    and the port shall transition to the Disconnected state, else ignored. 1-2,4,6-15: Ignored.
99062  *    State Encoding: 0: Link is in the U0 State, 1: Link is in the U1 State, 2: Link is in the U2
99063  *    State, 3: Link is in the U3 State (Device Suspended), 4: Link is in the Disabled State, 5: Link is
99064  *    in the RxDetect State, 6: Link is in the Inactive State, 7: Link is in the Polling State, 8:
99065  *    Link is in the Recovery State, 9: Link is in the Hot Reset State, 10 Link is in the Compliance
99066  *    Mode State, 11: Link is in the Test Mode State, 12-14: Reserved, 15: Link is in the Resume
99067  *    State. Note: The Port Link State Write Strobe (LWS) shall also be set to '1' to write this field.
99068  *    This field is undefined if PP = '0'. Note: Transitions between different states are not
99069  *    reflected until the transition is complete. Refer to section 4.19 of xHCI specification for PLS
99070  *    transition conditions. Refer to sections 4.15.2 and 4.23.5 for more information on the use of
99071  *    this field
99072  */
99073 #define USB3_PORTSC1USB3_PLS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PLS_SHIFT)) & USB3_PORTSC1USB3_PLS_MASK)
99074 #define USB3_PORTSC1USB3_PP_MASK                 (0x200U)
99075 #define USB3_PORTSC1USB3_PP_SHIFT                (9U)
99076 /*! PP - Port Power (PP), RWS. Default = '1'. This flag reflects a port's logical, power control
99077  *    state. Because host controllers can implement different methods of port power switching, this
99078  *    flag may or may not represent whether (VBus) power is actually applied to the port. When PP
99079  *    equals a '0' the port is nonfunctional and shall not report attaches, detaches, or Port Link State
99080  *    (PLS) changes. However, the port shall report over-current conditions when PP = '0' if PPC =
99081  *    '0'. After modifying PP, software shall read PP and confirm that it has reached its target
99082  *    state before modifying it again, undefined behavior may occur if this procedure is not followed.
99083  *    '0' = This port is in the Powered-off state. '1' = This port is not in the Powered-off state.
99084  *    If the Port Power Control (PPC) flag in the HCCPARAMS register is '1', then xHC has port power
99085  *    control switches and this bit represents the current setting of the switch ('0' = off,
99086  *    '1'=on). If the Port Power Control (PPC) flag in the HCCPARAMS register is '0', then xHC does not
99087  *    have port power control switches and each port is hard wired to power, and not affected by this
99088  *    bit. When an over-current condition is detected on a powered port, the xHC shall transition the
99089  *    PP bit in each affected port from a '1' to '0' (removing power from the port). Refer to
99090  *    section 4.19.4 for more information
99091  */
99092 #define USB3_PORTSC1USB3_PP(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PP_SHIFT)) & USB3_PORTSC1USB3_PP_MASK)
99093 #define USB3_PORTSC1USB3_PortSpeed_MASK          (0x3C00U)
99094 #define USB3_PORTSC1USB3_PortSpeed_SHIFT         (10U)
99095 /*! PortSpeed - Port Speed (Port Speed), ROS. Default = '0'. This field identifies the speed of the
99096  *    connected USB Device. This field is only relevant if a device is connected (CCS = '1') in all
99097  *    other cases this field shall indicate Undefined Speed. Possible values: 0: Undefined Speed
99098  *    1-15: Protocol Speed ID (PSI), refer to section 7.2.1 of xHCI specification for the definition of
99099  *    PSIV field in the PSI Dword
99100  */
99101 #define USB3_PORTSC1USB3_PortSpeed(x)            (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PortSpeed_SHIFT)) & USB3_PORTSC1USB3_PortSpeed_MASK)
99102 #define USB3_PORTSC1USB3_PIC_MASK                (0xC000U)
99103 #define USB3_PORTSC1USB3_PIC_SHIFT               (14U)
99104 /*! PIC - Port Indicator Control (PIC), RWS. Default = '0'. Writing to these bits has no effect if
99105  *    the Port Indicators (PIND) bit in the HCCPARAMS register is a '0'. If PIND bit is a '1', then
99106  *    the bit encodings are: 0: Port indicators are off, 1: Amber, 2: Green, 3: Undefined. This field
99107  *    is '0' if PP is '0'
99108  */
99109 #define USB3_PORTSC1USB3_PIC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PIC_SHIFT)) & USB3_PORTSC1USB3_PIC_MASK)
99110 #define USB3_PORTSC1USB3_LWS_MASK                (0x10000U)
99111 #define USB3_PORTSC1USB3_LWS_SHIFT               (16U)
99112 /*! LWS - Port Link State Write Strobe (LWS), RW. Default = '0'. When this bit is set to '1' on a
99113  *    write reference to this register, this flag enables writes to the PLS field. When '0', write
99114  *    data in PLS field is ignored. Reads to this bit return '0'
99115  */
99116 #define USB3_PORTSC1USB3_LWS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_LWS_SHIFT)) & USB3_PORTSC1USB3_LWS_MASK)
99117 #define USB3_PORTSC1USB3_CSC_MASK                (0x20000U)
99118 #define USB3_PORTSC1USB3_CSC_SHIFT               (17U)
99119 /*! CSC - Connect Status Change (CSC), RW1CS. Default = '0'. '1' = Change in CCS. '0' = No change.
99120  *    This flag indicates a change has occurred in the ports Current Connect Status (CCS) or Cold
99121  *    Attach Status (CAS) bits. Note that this flag shall not be set if the CCS transition was due to
99122  *    software setting PP to '0', or the CAS transition was due to software setting WPR to '1'. The
99123  *    xHC sets this bit to '1' for all changes to the port device connect status, even if system
99124  *    software has not cleared an existing Connect Status Change. For example, the insertion status
99125  *    changes twice before system software has cleared the changed condition, root hub hardware will be
99126  *    setting an already-set bit (i.e., the bit will remain 1). Software shall clear this bit by
99127  *    writing a '1' to it. Refer to section 4.19.2 of xHCI specification for more information on change
99128  *    bit usage
99129  */
99130 #define USB3_PORTSC1USB3_CSC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CSC_SHIFT)) & USB3_PORTSC1USB3_CSC_MASK)
99131 #define USB3_PORTSC1USB3_PEC_MASK                (0x40000U)
99132 #define USB3_PORTSC1USB3_PEC_SHIFT               (18U)
99133 /*! PEC - Port Enabled/Disabled Change (PEC), RW1CS. Default = '0'. '1' = change in PED. '0' = No
99134  *    change. Note that this flag shall not be set if the PED transition was due to software setting
99135  *    PP to '0'. Software shall clear this bit by writing a '1' to it. Refer to section 4.19.2 of
99136  *    xHCI specification for more information on change bit usage. This bit shall never be set to '1'
99137  */
99138 #define USB3_PORTSC1USB3_PEC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PEC_SHIFT)) & USB3_PORTSC1USB3_PEC_MASK)
99139 #define USB3_PORTSC1USB3_WRC_MASK                (0x80000U)
99140 #define USB3_PORTSC1USB3_WRC_SHIFT               (19U)
99141 /*! WRC - Warm Port Reset Change (WRC), RW1CS. Default = '0'. This bit is set when Warm Reset
99142  *    processing on this port completes. '0' = No change. '1' = Warm Reset complete. Note that this flag
99143  *    shall not be set to '1' if the Warm Reset processing was forced to terminate due to software
99144  *    clearing PP or PED to '0'. Software shall clear this bit by writing a '1' to it. Refer to
99145  *    section 4.19.5.1 of xHCI specification. Refer to section 4.19.2 of xHCI specification for more
99146  *    information on change bit usage
99147  */
99148 #define USB3_PORTSC1USB3_WRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WRC_SHIFT)) & USB3_PORTSC1USB3_WRC_MASK)
99149 #define USB3_PORTSC1USB3_OCC_MASK                (0x100000U)
99150 #define USB3_PORTSC1USB3_OCC_SHIFT               (20U)
99151 /*! OCC - Over-current Change (OCC), RW1CS. Default = '0'. This bit shall be set to a '1' when there
99152  *    is a '0' to '1' or '1' to '0' transition of Over-current Active (OCA). Software shall clear
99153  *    this bit by writing a '1' to it. Refer to section 4.19.2 of xHCI specification for more
99154  *    information on change bit usage
99155  */
99156 #define USB3_PORTSC1USB3_OCC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_OCC_SHIFT)) & USB3_PORTSC1USB3_OCC_MASK)
99157 #define USB3_PORTSC1USB3_PRC_MASK                (0x200000U)
99158 #define USB3_PORTSC1USB3_PRC_SHIFT               (21U)
99159 /*! PRC - Port Reset Change (PRC), RW1CS. Default = '0'. This flag is set to '1' due to a '1' to '0'
99160  *    transition of Port Reset (PR), e.g. when any reset processing (Warm or Hot) on this port is
99161  *    complete. Note that this flag shall not be set to '1' if the reset processing was forced to
99162  *    terminate due to software clearing PP or PED to '0'. '0' = No change. '1' = Reset complete.
99163  *    Software shall clear this bit by writing a '1' to it. Refer to section 4.19.5 of xHCI
99164  *    specification. Refer to section 4.19.2 of xHCI specification for more information on change bit usage
99165  */
99166 #define USB3_PORTSC1USB3_PRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PRC_SHIFT)) & USB3_PORTSC1USB3_PRC_MASK)
99167 #define USB3_PORTSC1USB3_PLC_MASK                (0x400000U)
99168 #define USB3_PORTSC1USB3_PLC_SHIFT               (22U)
99169 /*! PLC - Port Link State Change (PLC), RW1CS. Default = '0'. This flag is set to '1' due to the
99170  *    following PLS transitions: U3 -> Resume (Wakeup signaling from a device), Resume -> Recovery ->
99171  *    U0 (Device Resume complete (USB3 protocol ports only)), Resume -> U0 (Device Resume complete
99172  *    (USB2 protocol ports only)), U3 -> Recovery -> U0 (Software Resume complete (USB3 protocol ports
99173  *    only)), U3 -> U0 (Software Resume complete (USB2 protocol ports only)), U2 -> U0 (L1 Resume
99174  *    complete (USB2 protocol ports only)), U0 -> U0 (L1 Entry Reject (USB2 protocol ports only)),
99175  *    Any state -> Inactive (Error (USB3 protocol ports only)). Note that this flag shall not be set
99176  *    if the PLS transition was due to software setting PP to 0. Refer to section 4.23.5 of xHCI
99177  *    specification for more information. '0' = No change. '1' = Link Status Changed. Software shall
99178  *    clear this bit by writing a '1' to it. Refer to PLC Condition: references in section 4.19.1 for
99179  *    the specific port state transitions that set this flag. Refer to section 4.19.2 of xHCI
99180  *    specification for more information on change bit usage
99181  */
99182 #define USB3_PORTSC1USB3_PLC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PLC_SHIFT)) & USB3_PORTSC1USB3_PLC_MASK)
99183 #define USB3_PORTSC1USB3_CEC_MASK                (0x800000U)
99184 #define USB3_PORTSC1USB3_CEC_SHIFT               (23U)
99185 /*! CEC - Port Config Error Change (CEC), RW1CS. Default = '0'. This flag indicates that the port
99186  *    failed to configure its link partner. '0' = No change. '1' = Port Config Error detected.
99187  *    Software shall clear this bit by writing a '1' to it. Refer to section 4.19.2 of xHCI specification
99188  *    for more information on change bit usage
99189  */
99190 #define USB3_PORTSC1USB3_CEC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CEC_SHIFT)) & USB3_PORTSC1USB3_CEC_MASK)
99191 #define USB3_PORTSC1USB3_CAS_MASK                (0x1000000U)
99192 #define USB3_PORTSC1USB3_CAS_SHIFT               (24U)
99193 /*! CAS - Cold Attach Status (CAS), RO. Default = '0'. '1' = Far-end Receiver Terminations were
99194  *    detected in the Disconnected state and the Root Hub Port State Machine was unable to advance to
99195  *    the Enabled state. Refer to sections 4.19.8 of xHCI specification for more details on the Cold
99196  *    Attach Status (CAS) assertion conditions. Software shall clear this bit by writing a '1' to WPR
99197  *    or the xHC shall clear this bit if CCS transitions to '1'. This flag is 0 if PP is 0 or for
99198  *    USB2 protocol ports. Note: Additionally to the xHCI spec the CAS may be set in D1/D2 state. If
99199  *    customer's PLL lock time ensures finishing LFPS in tPollingLFPSTimeout (360ms) the SW driver
99200  *    may ignore the CAS and wait for PORTSC.CCS. It prevents additional reset on USB port. However,
99201  *    handling CAS in normal way should not have any negative impact on the device
99202  */
99203 #define USB3_PORTSC1USB3_CAS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CAS_SHIFT)) & USB3_PORTSC1USB3_CAS_MASK)
99204 #define USB3_PORTSC1USB3_WCE_MASK                (0x2000000U)
99205 #define USB3_PORTSC1USB3_WCE_SHIFT               (25U)
99206 /*! WCE - Wake on Connect Enable (WCE), RWS. Default = '0'. Writing this bit to a '1' enables the
99207  *    port to be sensitive to device connects as system wake-up events. Refer to section 4.15 of xHCI
99208  *    specification for operational model
99209  */
99210 #define USB3_PORTSC1USB3_WCE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WCE_SHIFT)) & USB3_PORTSC1USB3_WCE_MASK)
99211 #define USB3_PORTSC1USB3_WDE_MASK                (0x4000000U)
99212 #define USB3_PORTSC1USB3_WDE_SHIFT               (26U)
99213 /*! WDE - Wake on Disconnect Enable (WDE), RWS. Default = '0'. Writing this bit to a '1' enables the
99214  *    port to be sensitive to device disconnects as system wake-up events. Refer to section 4.15 of
99215  *    xHCI specification for operational model
99216  */
99217 #define USB3_PORTSC1USB3_WDE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WDE_SHIFT)) & USB3_PORTSC1USB3_WDE_MASK)
99218 #define USB3_PORTSC1USB3_WOE_MASK                (0x8000000U)
99219 #define USB3_PORTSC1USB3_WOE_SHIFT               (27U)
99220 /*! WOE - Wake on Over-current Enable (WOE), RWS. Default = '0'. Writing this bit to a '1' enables
99221  *    the port to be sensitive to over-current conditions as system wake-up events. Refer to section
99222  *    4.15 of xHCI specification for operational model
99223  */
99224 #define USB3_PORTSC1USB3_WOE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WOE_SHIFT)) & USB3_PORTSC1USB3_WOE_MASK)
99225 #define USB3_PORTSC1USB3_DR_MASK                 (0x40000000U)
99226 #define USB3_PORTSC1USB3_DR_SHIFT                (30U)
99227 /*! DR - Device Removable (DR), RO. This flag indicates if this port has a removable device
99228  *    attached. '0' = Device is removable; '1' = Device is non-removable
99229  */
99230 #define USB3_PORTSC1USB3_DR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_DR_SHIFT)) & USB3_PORTSC1USB3_DR_MASK)
99231 #define USB3_PORTSC1USB3_WPR_MASK                (0x80000000U)
99232 #define USB3_PORTSC1USB3_WPR_SHIFT               (31U)
99233 /*! WPR - Warm Port Reset (WPR), RW1S. Default = '0'. When software writes a '1' to this bit, the
99234  *    Warm Reset sequence as defined in the USB3 Specification is initiated and the PR flag is set to
99235  *    '1'. Once initiated, the PR, PRC, and WRC flags shall reflect the progress of the Warm Reset
99236  *    sequence. This flag shall always return 0 when read. Refer to section 4.19.5.1 of xHCI
99237  *    specification
99238  */
99239 #define USB3_PORTSC1USB3_WPR(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WPR_SHIFT)) & USB3_PORTSC1USB3_WPR_MASK)
99240 /*! @} */
99241 
99242 /*! @name PORTPMSC1USB3 - USB3 Port Power Management Status and Control */
99243 /*! @{ */
99244 #define USB3_PORTPMSC1USB3_U1_timeout_MASK       (0xFFU)
99245 #define USB3_PORTPMSC1USB3_U1_timeout_SHIFT      (0U)
99246 /*! U1_timeout - U1 Timeout, RWS. Default = 0. Timeout value for U1 inactivity timer. If equal to
99247  *    FFh, the port is disabled from initiating U1 entry. This field shall be set to '0' by the
99248  *    assertion of PR to '1'. Refer to section 4.19.4.1 of xHCI specification for more information on U1
99249  *    Timeout operation. The following are permissible values: 00h Zero (default) 01h 1 us. 02h 2 us.
99250  *    ... 7Fh 127 us. 80h - FEh Reserved FFh Infinite
99251  */
99252 #define USB3_PORTPMSC1USB3_U1_timeout(x)         (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB3_U1_timeout_SHIFT)) & USB3_PORTPMSC1USB3_U1_timeout_MASK)
99253 #define USB3_PORTPMSC1USB3_U2_timeout_MASK       (0xFF00U)
99254 #define USB3_PORTPMSC1USB3_U2_timeout_SHIFT      (8U)
99255 /*! U2_timeout - U2 Timeout, RWS. Default = 0. Timeout value for U2 inactivity timer. If equal to
99256  *    FFh, the port is disabled from initiating U2 entry. This field shall be set to '0' by the
99257  *    assertion of PR to '1'. Refer to section 4.19.4.1 of xHCI specification for more information on U2
99258  *    Timeout operation. The following are permissible values: 00h Zero (default) 01h 256 us 02h 512
99259  *    us ... FEh 65,.024 ms FFh Infinite A U2 Inactivity Timeout LMP shall be sent by the xHC to the
99260  *    device connected on this port when this field is written. Refer to Sections 8.4.3 and
99261  *    10.4.2.10 of the USB3 specification for more details
99262  */
99263 #define USB3_PORTPMSC1USB3_U2_timeout(x)         (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB3_U2_timeout_SHIFT)) & USB3_PORTPMSC1USB3_U2_timeout_MASK)
99264 #define USB3_PORTPMSC1USB3_FLA_MASK              (0x10000U)
99265 #define USB3_PORTPMSC1USB3_FLA_SHIFT             (16U)
99266 /*! FLA - Force Link PM Accept (FLA), RW. Default = '0'. When this bit is set to '1', the port shall
99267  *    generate a Set Link Function LMP with the Force_LinkPM_Accept bit asserted ('1'). When this
99268  *    bit is cleared to '0', the port shall generate a Set Link Function LMP with the
99269  *    Force_LinkPM_Accept bit de-asserted ('0'). This flag shall be set to '0' by the assertion of PR to '1' or
99270  *    when CCS = transitions from '0' to '1'. Writes to this flag have no effect if PP = '0'. The Set
99271  *    Link Function LMP is sent by the xHC to the device connected on this port when this bit
99272  *    transitions from '0' to '1' or '1' to '0'. Refer to Sections 8.4.2 and 10.14.2.2 of the USB3
99273  *    specification for more details. Improper use of the SS Force_LinkPM_Accept functionality can impact
99274  *    the performance of the link significantly. This bit shall only be used for compliance and
99275  *    testing purposes. Software shall ensure that there are no pending packets at the link level before
99276  *    setting this bit. This flag is '0' if PP is '0'
99277  */
99278 #define USB3_PORTPMSC1USB3_FLA(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB3_FLA_SHIFT)) & USB3_PORTPMSC1USB3_FLA_MASK)
99279 /*! @} */
99280 
99281 /*! @name PORTLI1 - USB3 Port Link Info */
99282 /*! @{ */
99283 #define USB3_PORTLI1_LEC_MASK                    (0xFFFFU)
99284 #define USB3_PORTLI1_LEC_SHIFT                   (0U)
99285 /*! LEC - Link Error Count, RO. Default = '0'. This field returns the number of link errors detected
99286  *    by the port. This value shall be reset to '0' by the assertion of a Chip Hardware Reset,
99287  *    HCRST, when PR transitions from 1 to 0, or when CCS = transitions from '0' to '1'
99288  */
99289 #define USB3_PORTLI1_LEC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_PORTLI1_LEC_SHIFT)) & USB3_PORTLI1_LEC_MASK)
99290 /*! @} */
99291 
99292 /*! @name MFINDEX - MicroFrame Index */
99293 /*! @{ */
99294 #define USB3_MFINDEX_MFIndex_MASK                (0x3FFFU)
99295 #define USB3_MFINDEX_MFIndex_SHIFT               (0U)
99296 /*! MFIndex - Microframe Index, RO. The value in this register increments at the end of each
99297  *    microframe (e.g. 125us.). Bits [13:3] may be used to determine the current 1ms Frame Index. Note:
99298  *    Setting frindex_wr_en to '1' (bit 31 of XECP_CMDM_CTRL_REG3) enables software writes to this field
99299  */
99300 #define USB3_MFINDEX_MFIndex(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_MFINDEX_MFIndex_SHIFT)) & USB3_MFINDEX_MFIndex_MASK)
99301 /*! @} */
99302 
99303 /*! @name IMAN0 - Interrupter Management */
99304 /*! @{ */
99305 #define USB3_IMAN0_IP_MASK                       (0x1U)
99306 #define USB3_IMAN0_IP_SHIFT                      (0U)
99307 /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the
99308  *    Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates
99309  *    that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI
99310  *    specification for the conditions that modify the state of this flag
99311  */
99312 #define USB3_IMAN0_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN0_IP_SHIFT)) & USB3_IMAN0_IP_MASK)
99313 #define USB3_IMAN0_IE_MASK                       (0x2U)
99314 #define USB3_IMAN0_IE_SHIFT                      (1U)
99315 /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is
99316  *    capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter
99317  *    shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is
99318  *    '0', then the Interrupter is prohibited from generating interrupts
99319  */
99320 #define USB3_IMAN0_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN0_IE_SHIFT)) & USB3_IMAN0_IE_MASK)
99321 /*! @} */
99322 
99323 /*! @name IMOD0 - Interrupter Moderation */
99324 /*! @{ */
99325 #define USB3_IMOD0_IMODI_MASK                    (0xFFFFU)
99326 #define USB3_IMOD0_IMODI_SHIFT                   (0U)
99327 /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum
99328  *    inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables
99329  *    interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and
99330  *    the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization
99331  *    and reset. It may be loaded with an alternative value by software when the Interrupter is
99332  *    initialized
99333  */
99334 #define USB3_IMOD0_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD0_IMODI_SHIFT)) & USB3_IMOD0_IMODI_MASK)
99335 #define USB3_IMOD0_IMODC_MASK                    (0xFFFF0000U)
99336 #define USB3_IMOD0_IMODC_SHIFT                   (16U)
99337 /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with
99338  *    the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated
99339  *    interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE
99340  *    and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time
99341  *    to alter the interrupt rate
99342  */
99343 #define USB3_IMOD0_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD0_IMODC_SHIFT)) & USB3_IMOD0_IMODC_MASK)
99344 /*! @} */
99345 
99346 /*! @name ERSTSZ0 - Event Ring Segment Table Size */
99347 /*! @{ */
99348 #define USB3_ERSTSZ0_ERSTS_MASK                  (0xFFFFU)
99349 #define USB3_ERSTSZ0_ERSTS_SHIFT                 (0U)
99350 /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of
99351  *    valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event
99352  *    Ring Segment Table Base Address register. The maximum value supported by an xHC implementation
99353  *    for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary
99354  *    Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at
99355  *    this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For
99356  *    the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior
99357  *    of the Event Ring. The Primary Event Ring cannot be disabled
99358  */
99359 #define USB3_ERSTSZ0_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ0_ERSTS_SHIFT)) & USB3_ERSTSZ0_ERSTS_MASK)
99360 /*! @} */
99361 
99362 /*! @name ERSTBA0_LO - Event Ring Segment Table Base Address (LOW) */
99363 /*! @{ */
99364 #define USB3_ERSTBA0_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
99365 #define USB3_ERSTBA0_LO_ERSTBAddr_LO_SHIFT       (6U)
99366 /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99367  *    defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address
99368  *    is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement
99369  *    to the Start state. This field shall not be modified if HCHalted (HCH) = '0'
99370  */
99371 #define USB3_ERSTBA0_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA0_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA0_LO_ERSTBAddr_LO_MASK)
99372 /*! @} */
99373 
99374 /*! @name ERSTBA00_HI - Event Ring Segment Table Base Address (HIGH) */
99375 /*! @{ */
99376 #define USB3_ERSTBA00_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
99377 #define USB3_ERSTBA00_HI_ERSTBAddr_HI_SHIFT      (0U)
99378 /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99379  *    defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the
99380  *    address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement
99381  *    to the Start state. Refer to Figure 20 in xHCI specification for more information. This field
99382  *    shall not be modified if HCHalted (HCH) = '0'
99383  */
99384 #define USB3_ERSTBA00_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA00_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA00_HI_ERSTBAddr_HI_MASK)
99385 /*! @} */
99386 
99387 /*! @name ERDP0_LO - Event Ring Dequeue Pointer (LOW) */
99388 /*! @{ */
99389 #define USB3_ERDP0_LO_DESI_MASK                  (0x7U)
99390 #define USB3_ERDP0_LO_DESI_SHIFT                 (0U)
99391 /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to
99392  *    accelerate checking the Event Ring full condition. This field is written with the low order 3 bits
99393  *    of the offset of the ERST entry which defines the Event Ring segment that the Event Ring
99394  *    Dequeue Pointer resides in
99395  */
99396 #define USB3_ERDP0_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_LO_DESI_SHIFT)) & USB3_ERDP0_LO_DESI_MASK)
99397 #define USB3_ERDP0_LO_EHB_MASK                   (0x8U)
99398 #define USB3_ERDP0_LO_EHB_SHIFT                  (3U)
99399 /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP
99400  *    bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written.
99401  *    Refer to section 4.17.2 of xHCI specification for more information
99402  */
99403 #define USB3_ERDP0_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_LO_EHB_SHIFT)) & USB3_ERDP0_LO_EHB_MASK)
99404 #define USB3_ERDP0_LO_ERDPtr_MASK                (0xFFFFFFF0U)
99405 #define USB3_ERDP0_LO_ERDPtr_SHIFT               (4U)
99406 /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits
99407  *    of the 64-bit address of the current Event Ring Dequeue Pointer
99408  */
99409 #define USB3_ERDP0_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_LO_ERDPtr_SHIFT)) & USB3_ERDP0_LO_ERDPtr_MASK)
99410 /*! @} */
99411 
99412 /*! @name ERDP0_HI - Event Ring Dequeue Pointer (HIGH) */
99413 /*! @{ */
99414 #define USB3_ERDP0_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
99415 #define USB3_ERDP0_HI_ERDPtr_HI_SHIFT            (0U)
99416 /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order
99417  *    bits of the 64-bit address of the current Event Ring Dequeue Pointer
99418  */
99419 #define USB3_ERDP0_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP0_HI_ERDPtr_HI_MASK)
99420 /*! @} */
99421 
99422 /*! @name IMAN1 - Interrupter Management */
99423 /*! @{ */
99424 #define USB3_IMAN1_IP_MASK                       (0x1U)
99425 #define USB3_IMAN1_IP_SHIFT                      (0U)
99426 /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the
99427  *    Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates
99428  *    that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI
99429  *    specification for the conditions that modify the state of this flag
99430  */
99431 #define USB3_IMAN1_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN1_IP_SHIFT)) & USB3_IMAN1_IP_MASK)
99432 #define USB3_IMAN1_IE_MASK                       (0x2U)
99433 #define USB3_IMAN1_IE_SHIFT                      (1U)
99434 /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is
99435  *    capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter
99436  *    shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is
99437  *    '0', then the Interrupter is prohibited from generating interrupts
99438  */
99439 #define USB3_IMAN1_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN1_IE_SHIFT)) & USB3_IMAN1_IE_MASK)
99440 /*! @} */
99441 
99442 /*! @name IMOD1 - Interrupter Moderation */
99443 /*! @{ */
99444 #define USB3_IMOD1_IMODI_MASK                    (0xFFFFU)
99445 #define USB3_IMOD1_IMODI_SHIFT                   (0U)
99446 /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum
99447  *    inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables
99448  *    interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and
99449  *    the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization
99450  *    and reset. It may be loaded with an alternative value by software when the Interrupter is
99451  *    initialized
99452  */
99453 #define USB3_IMOD1_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD1_IMODI_SHIFT)) & USB3_IMOD1_IMODI_MASK)
99454 #define USB3_IMOD1_IMODC_MASK                    (0xFFFF0000U)
99455 #define USB3_IMOD1_IMODC_SHIFT                   (16U)
99456 /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with
99457  *    the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated
99458  *    interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE
99459  *    and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time
99460  *    to alter the interrupt rate
99461  */
99462 #define USB3_IMOD1_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD1_IMODC_SHIFT)) & USB3_IMOD1_IMODC_MASK)
99463 /*! @} */
99464 
99465 /*! @name ERSTSZ1 - Event Ring Segment Table Size */
99466 /*! @{ */
99467 #define USB3_ERSTSZ1_ERSTS_MASK                  (0xFFFFU)
99468 #define USB3_ERSTSZ1_ERSTS_SHIFT                 (0U)
99469 /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of
99470  *    valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event
99471  *    Ring Segment Table Base Address register. The maximum value supported by an xHC implementation
99472  *    for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary
99473  *    Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at
99474  *    this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For
99475  *    the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior
99476  *    of the Event Ring. The Primary Event Ring cannot be disabled
99477  */
99478 #define USB3_ERSTSZ1_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ1_ERSTS_SHIFT)) & USB3_ERSTSZ1_ERSTS_MASK)
99479 /*! @} */
99480 
99481 /*! @name ERSTBA1_LO - Event Ring Segment Table Base Address (LOW) */
99482 /*! @{ */
99483 #define USB3_ERSTBA1_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
99484 #define USB3_ERSTBA1_LO_ERSTBAddr_LO_SHIFT       (6U)
99485 /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99486  *    defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address
99487  *    is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement
99488  *    to the Start state. This field shall not be modified if HCHalted (HCH) = '0'
99489  */
99490 #define USB3_ERSTBA1_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA1_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA1_LO_ERSTBAddr_LO_MASK)
99491 /*! @} */
99492 
99493 /*! @name ERSTBA01_HI - Event Ring Segment Table Base Address (HIGH) */
99494 /*! @{ */
99495 #define USB3_ERSTBA01_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
99496 #define USB3_ERSTBA01_HI_ERSTBAddr_HI_SHIFT      (0U)
99497 /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99498  *    defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the
99499  *    address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement
99500  *    to the Start state. Refer to Figure 20 in xHCI specification for more information. This field
99501  *    shall not be modified if HCHalted (HCH) = '0'
99502  */
99503 #define USB3_ERSTBA01_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA01_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA01_HI_ERSTBAddr_HI_MASK)
99504 /*! @} */
99505 
99506 /*! @name ERDP1_LO - Event Ring Dequeue Pointer (LOW) */
99507 /*! @{ */
99508 #define USB3_ERDP1_LO_DESI_MASK                  (0x7U)
99509 #define USB3_ERDP1_LO_DESI_SHIFT                 (0U)
99510 /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to
99511  *    accelerate checking the Event Ring full condition. This field is written with the low order 3 bits
99512  *    of the offset of the ERST entry which defines the Event Ring segment that the Event Ring
99513  *    Dequeue Pointer resides in
99514  */
99515 #define USB3_ERDP1_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_LO_DESI_SHIFT)) & USB3_ERDP1_LO_DESI_MASK)
99516 #define USB3_ERDP1_LO_EHB_MASK                   (0x8U)
99517 #define USB3_ERDP1_LO_EHB_SHIFT                  (3U)
99518 /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP
99519  *    bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written.
99520  *    Refer to section 4.17.2 of xHCI specification for more information
99521  */
99522 #define USB3_ERDP1_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_LO_EHB_SHIFT)) & USB3_ERDP1_LO_EHB_MASK)
99523 #define USB3_ERDP1_LO_ERDPtr_MASK                (0xFFFFFFF0U)
99524 #define USB3_ERDP1_LO_ERDPtr_SHIFT               (4U)
99525 /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits
99526  *    of the 64-bit address of the current Event Ring Dequeue Pointer
99527  */
99528 #define USB3_ERDP1_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_LO_ERDPtr_SHIFT)) & USB3_ERDP1_LO_ERDPtr_MASK)
99529 /*! @} */
99530 
99531 /*! @name ERDP1_HI - Event Ring Dequeue Pointer (HIGH) */
99532 /*! @{ */
99533 #define USB3_ERDP1_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
99534 #define USB3_ERDP1_HI_ERDPtr_HI_SHIFT            (0U)
99535 /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order
99536  *    bits of the 64-bit address of the current Event Ring Dequeue Pointer
99537  */
99538 #define USB3_ERDP1_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP1_HI_ERDPtr_HI_MASK)
99539 /*! @} */
99540 
99541 /*! @name IMAN2 - Interrupter Management */
99542 /*! @{ */
99543 #define USB3_IMAN2_IP_MASK                       (0x1U)
99544 #define USB3_IMAN2_IP_SHIFT                      (0U)
99545 /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the
99546  *    Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates
99547  *    that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI
99548  *    specification for the conditions that modify the state of this flag
99549  */
99550 #define USB3_IMAN2_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN2_IP_SHIFT)) & USB3_IMAN2_IP_MASK)
99551 #define USB3_IMAN2_IE_MASK                       (0x2U)
99552 #define USB3_IMAN2_IE_SHIFT                      (1U)
99553 /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is
99554  *    capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter
99555  *    shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is
99556  *    '0', then the Interrupter is prohibited from generating interrupts
99557  */
99558 #define USB3_IMAN2_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN2_IE_SHIFT)) & USB3_IMAN2_IE_MASK)
99559 /*! @} */
99560 
99561 /*! @name IMOD2 - Interrupter Moderation */
99562 /*! @{ */
99563 #define USB3_IMOD2_IMODI_MASK                    (0xFFFFU)
99564 #define USB3_IMOD2_IMODI_SHIFT                   (0U)
99565 /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum
99566  *    inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables
99567  *    interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and
99568  *    the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization
99569  *    and reset. It may be loaded with an alternative value by software when the Interrupter is
99570  *    initialized
99571  */
99572 #define USB3_IMOD2_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD2_IMODI_SHIFT)) & USB3_IMOD2_IMODI_MASK)
99573 #define USB3_IMOD2_IMODC_MASK                    (0xFFFF0000U)
99574 #define USB3_IMOD2_IMODC_SHIFT                   (16U)
99575 /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with
99576  *    the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated
99577  *    interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE
99578  *    and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time
99579  *    to alter the interrupt rate
99580  */
99581 #define USB3_IMOD2_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD2_IMODC_SHIFT)) & USB3_IMOD2_IMODC_MASK)
99582 /*! @} */
99583 
99584 /*! @name ERSTSZ2 - Event Ring Segment Table Size */
99585 /*! @{ */
99586 #define USB3_ERSTSZ2_ERSTS_MASK                  (0xFFFFU)
99587 #define USB3_ERSTSZ2_ERSTS_SHIFT                 (0U)
99588 /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of
99589  *    valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event
99590  *    Ring Segment Table Base Address register. The maximum value supported by an xHC implementation
99591  *    for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary
99592  *    Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at
99593  *    this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For
99594  *    the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior
99595  *    of the Event Ring. The Primary Event Ring cannot be disabled
99596  */
99597 #define USB3_ERSTSZ2_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ2_ERSTS_SHIFT)) & USB3_ERSTSZ2_ERSTS_MASK)
99598 /*! @} */
99599 
99600 /*! @name ERSTBA2_LO - Event Ring Segment Table Base Address (LOW) */
99601 /*! @{ */
99602 #define USB3_ERSTBA2_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
99603 #define USB3_ERSTBA2_LO_ERSTBAddr_LO_SHIFT       (6U)
99604 /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99605  *    defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address
99606  *    is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement
99607  *    to the Start state. This field shall not be modified if HCHalted (HCH) = '0'
99608  */
99609 #define USB3_ERSTBA2_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA2_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA2_LO_ERSTBAddr_LO_MASK)
99610 /*! @} */
99611 
99612 /*! @name ERSTBA02_HI - Event Ring Segment Table Base Address (HIGH) */
99613 /*! @{ */
99614 #define USB3_ERSTBA02_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
99615 #define USB3_ERSTBA02_HI_ERSTBAddr_HI_SHIFT      (0U)
99616 /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99617  *    defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the
99618  *    address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement
99619  *    to the Start state. Refer to Figure 20 in xHCI specification for more information. This field
99620  *    shall not be modified if HCHalted (HCH) = '0'
99621  */
99622 #define USB3_ERSTBA02_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA02_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA02_HI_ERSTBAddr_HI_MASK)
99623 /*! @} */
99624 
99625 /*! @name ERDP2_LO - Event Ring Dequeue Pointer (LOW) */
99626 /*! @{ */
99627 #define USB3_ERDP2_LO_DESI_MASK                  (0x7U)
99628 #define USB3_ERDP2_LO_DESI_SHIFT                 (0U)
99629 /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to
99630  *    accelerate checking the Event Ring full condition. This field is written with the low order 3 bits
99631  *    of the offset of the ERST entry which defines the Event Ring segment that the Event Ring
99632  *    Dequeue Pointer resides in
99633  */
99634 #define USB3_ERDP2_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_LO_DESI_SHIFT)) & USB3_ERDP2_LO_DESI_MASK)
99635 #define USB3_ERDP2_LO_EHB_MASK                   (0x8U)
99636 #define USB3_ERDP2_LO_EHB_SHIFT                  (3U)
99637 /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP
99638  *    bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written.
99639  *    Refer to section 4.17.2 of xHCI specification for more information
99640  */
99641 #define USB3_ERDP2_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_LO_EHB_SHIFT)) & USB3_ERDP2_LO_EHB_MASK)
99642 #define USB3_ERDP2_LO_ERDPtr_MASK                (0xFFFFFFF0U)
99643 #define USB3_ERDP2_LO_ERDPtr_SHIFT               (4U)
99644 /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits
99645  *    of the 64-bit address of the current Event Ring Dequeue Pointer
99646  */
99647 #define USB3_ERDP2_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_LO_ERDPtr_SHIFT)) & USB3_ERDP2_LO_ERDPtr_MASK)
99648 /*! @} */
99649 
99650 /*! @name ERDP2_HI - Event Ring Dequeue Pointer (HIGH) */
99651 /*! @{ */
99652 #define USB3_ERDP2_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
99653 #define USB3_ERDP2_HI_ERDPtr_HI_SHIFT            (0U)
99654 /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order
99655  *    bits of the 64-bit address of the current Event Ring Dequeue Pointer
99656  */
99657 #define USB3_ERDP2_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP2_HI_ERDPtr_HI_MASK)
99658 /*! @} */
99659 
99660 /*! @name IMAN3 - Interrupter Management */
99661 /*! @{ */
99662 #define USB3_IMAN3_IP_MASK                       (0x1U)
99663 #define USB3_IMAN3_IP_SHIFT                      (0U)
99664 /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the
99665  *    Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates
99666  *    that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI
99667  *    specification for the conditions that modify the state of this flag
99668  */
99669 #define USB3_IMAN3_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN3_IP_SHIFT)) & USB3_IMAN3_IP_MASK)
99670 #define USB3_IMAN3_IE_MASK                       (0x2U)
99671 #define USB3_IMAN3_IE_SHIFT                      (1U)
99672 /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is
99673  *    capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter
99674  *    shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is
99675  *    '0', then the Interrupter is prohibited from generating interrupts
99676  */
99677 #define USB3_IMAN3_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN3_IE_SHIFT)) & USB3_IMAN3_IE_MASK)
99678 /*! @} */
99679 
99680 /*! @name IMOD3 - Interrupter Moderation */
99681 /*! @{ */
99682 #define USB3_IMOD3_IMODI_MASK                    (0xFFFFU)
99683 #define USB3_IMOD3_IMODI_SHIFT                   (0U)
99684 /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum
99685  *    inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables
99686  *    interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and
99687  *    the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization
99688  *    and reset. It may be loaded with an alternative value by software when the Interrupter is
99689  *    initialized
99690  */
99691 #define USB3_IMOD3_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD3_IMODI_SHIFT)) & USB3_IMOD3_IMODI_MASK)
99692 #define USB3_IMOD3_IMODC_MASK                    (0xFFFF0000U)
99693 #define USB3_IMOD3_IMODC_SHIFT                   (16U)
99694 /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with
99695  *    the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated
99696  *    interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE
99697  *    and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time
99698  *    to alter the interrupt rate
99699  */
99700 #define USB3_IMOD3_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD3_IMODC_SHIFT)) & USB3_IMOD3_IMODC_MASK)
99701 /*! @} */
99702 
99703 /*! @name ERSTSZ3 - Event Ring Segment Table Size */
99704 /*! @{ */
99705 #define USB3_ERSTSZ3_ERSTS_MASK                  (0xFFFFU)
99706 #define USB3_ERSTSZ3_ERSTS_SHIFT                 (0U)
99707 /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of
99708  *    valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event
99709  *    Ring Segment Table Base Address register. The maximum value supported by an xHC implementation
99710  *    for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary
99711  *    Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at
99712  *    this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For
99713  *    the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior
99714  *    of the Event Ring. The Primary Event Ring cannot be disabled
99715  */
99716 #define USB3_ERSTSZ3_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ3_ERSTS_SHIFT)) & USB3_ERSTSZ3_ERSTS_MASK)
99717 /*! @} */
99718 
99719 /*! @name ERSTBA3_LO - Event Ring Segment Table Base Address (LOW) */
99720 /*! @{ */
99721 #define USB3_ERSTBA3_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
99722 #define USB3_ERSTBA3_LO_ERSTBAddr_LO_SHIFT       (6U)
99723 /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99724  *    defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address
99725  *    is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement
99726  *    to the Start state. This field shall not be modified if HCHalted (HCH) = '0'
99727  */
99728 #define USB3_ERSTBA3_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA3_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA3_LO_ERSTBAddr_LO_MASK)
99729 /*! @} */
99730 
99731 /*! @name ERSTBA03_HI - Event Ring Segment Table Base Address (HIGH) */
99732 /*! @{ */
99733 #define USB3_ERSTBA03_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
99734 #define USB3_ERSTBA03_HI_ERSTBAddr_HI_SHIFT      (0U)
99735 /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99736  *    defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the
99737  *    address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement
99738  *    to the Start state. Refer to Figure 20 in xHCI specification for more information. This field
99739  *    shall not be modified if HCHalted (HCH) = '0'
99740  */
99741 #define USB3_ERSTBA03_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA03_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA03_HI_ERSTBAddr_HI_MASK)
99742 /*! @} */
99743 
99744 /*! @name ERDP3_LO - Event Ring Dequeue Pointer (LOW) */
99745 /*! @{ */
99746 #define USB3_ERDP3_LO_DESI_MASK                  (0x7U)
99747 #define USB3_ERDP3_LO_DESI_SHIFT                 (0U)
99748 /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to
99749  *    accelerate checking the Event Ring full condition. This field is written with the low order 3 bits
99750  *    of the offset of the ERST entry which defines the Event Ring segment that the Event Ring
99751  *    Dequeue Pointer resides in
99752  */
99753 #define USB3_ERDP3_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_LO_DESI_SHIFT)) & USB3_ERDP3_LO_DESI_MASK)
99754 #define USB3_ERDP3_LO_EHB_MASK                   (0x8U)
99755 #define USB3_ERDP3_LO_EHB_SHIFT                  (3U)
99756 /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP
99757  *    bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written.
99758  *    Refer to section 4.17.2 of xHCI specification for more information
99759  */
99760 #define USB3_ERDP3_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_LO_EHB_SHIFT)) & USB3_ERDP3_LO_EHB_MASK)
99761 #define USB3_ERDP3_LO_ERDPtr_MASK                (0xFFFFFFF0U)
99762 #define USB3_ERDP3_LO_ERDPtr_SHIFT               (4U)
99763 /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits
99764  *    of the 64-bit address of the current Event Ring Dequeue Pointer
99765  */
99766 #define USB3_ERDP3_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_LO_ERDPtr_SHIFT)) & USB3_ERDP3_LO_ERDPtr_MASK)
99767 /*! @} */
99768 
99769 /*! @name ERDP3_HI - Event Ring Dequeue Pointer (HIGH) */
99770 /*! @{ */
99771 #define USB3_ERDP3_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
99772 #define USB3_ERDP3_HI_ERDPtr_HI_SHIFT            (0U)
99773 /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order
99774  *    bits of the 64-bit address of the current Event Ring Dequeue Pointer
99775  */
99776 #define USB3_ERDP3_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP3_HI_ERDPtr_HI_MASK)
99777 /*! @} */
99778 
99779 /*! @name IMAN4 - Interrupter Management */
99780 /*! @{ */
99781 #define USB3_IMAN4_IP_MASK                       (0x1U)
99782 #define USB3_IMAN4_IP_SHIFT                      (0U)
99783 /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the
99784  *    Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates
99785  *    that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI
99786  *    specification for the conditions that modify the state of this flag
99787  */
99788 #define USB3_IMAN4_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN4_IP_SHIFT)) & USB3_IMAN4_IP_MASK)
99789 #define USB3_IMAN4_IE_MASK                       (0x2U)
99790 #define USB3_IMAN4_IE_SHIFT                      (1U)
99791 /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is
99792  *    capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter
99793  *    shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is
99794  *    '0', then the Interrupter is prohibited from generating interrupts
99795  */
99796 #define USB3_IMAN4_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN4_IE_SHIFT)) & USB3_IMAN4_IE_MASK)
99797 /*! @} */
99798 
99799 /*! @name IMOD4 - Interrupter Moderation */
99800 /*! @{ */
99801 #define USB3_IMOD4_IMODI_MASK                    (0xFFFFU)
99802 #define USB3_IMOD4_IMODI_SHIFT                   (0U)
99803 /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum
99804  *    inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables
99805  *    interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and
99806  *    the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization
99807  *    and reset. It may be loaded with an alternative value by software when the Interrupter is
99808  *    initialized
99809  */
99810 #define USB3_IMOD4_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD4_IMODI_SHIFT)) & USB3_IMOD4_IMODI_MASK)
99811 #define USB3_IMOD4_IMODC_MASK                    (0xFFFF0000U)
99812 #define USB3_IMOD4_IMODC_SHIFT                   (16U)
99813 /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with
99814  *    the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated
99815  *    interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE
99816  *    and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time
99817  *    to alter the interrupt rate
99818  */
99819 #define USB3_IMOD4_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD4_IMODC_SHIFT)) & USB3_IMOD4_IMODC_MASK)
99820 /*! @} */
99821 
99822 /*! @name ERSTSZ4 - Event Ring Segment Table Size */
99823 /*! @{ */
99824 #define USB3_ERSTSZ4_ERSTS_MASK                  (0xFFFFU)
99825 #define USB3_ERSTSZ4_ERSTS_SHIFT                 (0U)
99826 /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of
99827  *    valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event
99828  *    Ring Segment Table Base Address register. The maximum value supported by an xHC implementation
99829  *    for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary
99830  *    Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at
99831  *    this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For
99832  *    the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior
99833  *    of the Event Ring. The Primary Event Ring cannot be disabled
99834  */
99835 #define USB3_ERSTSZ4_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ4_ERSTS_SHIFT)) & USB3_ERSTSZ4_ERSTS_MASK)
99836 /*! @} */
99837 
99838 /*! @name ERSTBA4_LO - Event Ring Segment Table Base Address (LOW) */
99839 /*! @{ */
99840 #define USB3_ERSTBA4_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
99841 #define USB3_ERSTBA4_LO_ERSTBAddr_LO_SHIFT       (6U)
99842 /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99843  *    defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address
99844  *    is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement
99845  *    to the Start state. This field shall not be modified if HCHalted (HCH) = '0'
99846  */
99847 #define USB3_ERSTBA4_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA4_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA4_LO_ERSTBAddr_LO_MASK)
99848 /*! @} */
99849 
99850 /*! @name ERSTBA04_HI - Event Ring Segment Table Base Address (HIGH) */
99851 /*! @{ */
99852 #define USB3_ERSTBA04_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
99853 #define USB3_ERSTBA04_HI_ERSTBAddr_HI_SHIFT      (0U)
99854 /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99855  *    defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the
99856  *    address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement
99857  *    to the Start state. Refer to Figure 20 in xHCI specification for more information. This field
99858  *    shall not be modified if HCHalted (HCH) = '0'
99859  */
99860 #define USB3_ERSTBA04_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA04_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA04_HI_ERSTBAddr_HI_MASK)
99861 /*! @} */
99862 
99863 /*! @name ERDP4_LO - Event Ring Dequeue Pointer (LOW) */
99864 /*! @{ */
99865 #define USB3_ERDP4_LO_DESI_MASK                  (0x7U)
99866 #define USB3_ERDP4_LO_DESI_SHIFT                 (0U)
99867 /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to
99868  *    accelerate checking the Event Ring full condition. This field is written with the low order 3 bits
99869  *    of the offset of the ERST entry which defines the Event Ring segment that the Event Ring
99870  *    Dequeue Pointer resides in
99871  */
99872 #define USB3_ERDP4_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_LO_DESI_SHIFT)) & USB3_ERDP4_LO_DESI_MASK)
99873 #define USB3_ERDP4_LO_EHB_MASK                   (0x8U)
99874 #define USB3_ERDP4_LO_EHB_SHIFT                  (3U)
99875 /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP
99876  *    bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written.
99877  *    Refer to section 4.17.2 of xHCI specification for more information
99878  */
99879 #define USB3_ERDP4_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_LO_EHB_SHIFT)) & USB3_ERDP4_LO_EHB_MASK)
99880 #define USB3_ERDP4_LO_ERDPtr_MASK                (0xFFFFFFF0U)
99881 #define USB3_ERDP4_LO_ERDPtr_SHIFT               (4U)
99882 /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits
99883  *    of the 64-bit address of the current Event Ring Dequeue Pointer
99884  */
99885 #define USB3_ERDP4_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_LO_ERDPtr_SHIFT)) & USB3_ERDP4_LO_ERDPtr_MASK)
99886 /*! @} */
99887 
99888 /*! @name ERDP4_HI - Event Ring Dequeue Pointer (HIGH) */
99889 /*! @{ */
99890 #define USB3_ERDP4_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
99891 #define USB3_ERDP4_HI_ERDPtr_HI_SHIFT            (0U)
99892 /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order
99893  *    bits of the 64-bit address of the current Event Ring Dequeue Pointer
99894  */
99895 #define USB3_ERDP4_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP4_HI_ERDPtr_HI_MASK)
99896 /*! @} */
99897 
99898 /*! @name IMAN5 - Interrupter Management */
99899 /*! @{ */
99900 #define USB3_IMAN5_IP_MASK                       (0x1U)
99901 #define USB3_IMAN5_IP_SHIFT                      (0U)
99902 /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the
99903  *    Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates
99904  *    that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI
99905  *    specification for the conditions that modify the state of this flag
99906  */
99907 #define USB3_IMAN5_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN5_IP_SHIFT)) & USB3_IMAN5_IP_MASK)
99908 #define USB3_IMAN5_IE_MASK                       (0x2U)
99909 #define USB3_IMAN5_IE_SHIFT                      (1U)
99910 /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is
99911  *    capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter
99912  *    shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is
99913  *    '0', then the Interrupter is prohibited from generating interrupts
99914  */
99915 #define USB3_IMAN5_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN5_IE_SHIFT)) & USB3_IMAN5_IE_MASK)
99916 /*! @} */
99917 
99918 /*! @name IMOD5 - Interrupter Moderation */
99919 /*! @{ */
99920 #define USB3_IMOD5_IMODI_MASK                    (0xFFFFU)
99921 #define USB3_IMOD5_IMODI_SHIFT                   (0U)
99922 /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum
99923  *    inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables
99924  *    interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and
99925  *    the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization
99926  *    and reset. It may be loaded with an alternative value by software when the Interrupter is
99927  *    initialized
99928  */
99929 #define USB3_IMOD5_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD5_IMODI_SHIFT)) & USB3_IMOD5_IMODI_MASK)
99930 #define USB3_IMOD5_IMODC_MASK                    (0xFFFF0000U)
99931 #define USB3_IMOD5_IMODC_SHIFT                   (16U)
99932 /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with
99933  *    the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated
99934  *    interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE
99935  *    and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time
99936  *    to alter the interrupt rate
99937  */
99938 #define USB3_IMOD5_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD5_IMODC_SHIFT)) & USB3_IMOD5_IMODC_MASK)
99939 /*! @} */
99940 
99941 /*! @name ERSTSZ5 - Event Ring Segment Table Size */
99942 /*! @{ */
99943 #define USB3_ERSTSZ5_ERSTS_MASK                  (0xFFFFU)
99944 #define USB3_ERSTSZ5_ERSTS_SHIFT                 (0U)
99945 /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of
99946  *    valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event
99947  *    Ring Segment Table Base Address register. The maximum value supported by an xHC implementation
99948  *    for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary
99949  *    Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at
99950  *    this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For
99951  *    the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior
99952  *    of the Event Ring. The Primary Event Ring cannot be disabled
99953  */
99954 #define USB3_ERSTSZ5_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ5_ERSTS_SHIFT)) & USB3_ERSTSZ5_ERSTS_MASK)
99955 /*! @} */
99956 
99957 /*! @name ERSTBA5_LO - Event Ring Segment Table Base Address (LOW) */
99958 /*! @{ */
99959 #define USB3_ERSTBA5_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
99960 #define USB3_ERSTBA5_LO_ERSTBAddr_LO_SHIFT       (6U)
99961 /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99962  *    defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address
99963  *    is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement
99964  *    to the Start state. This field shall not be modified if HCHalted (HCH) = '0'
99965  */
99966 #define USB3_ERSTBA5_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA5_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA5_LO_ERSTBAddr_LO_MASK)
99967 /*! @} */
99968 
99969 /*! @name ERSTBA05_HI - Event Ring Segment Table Base Address (HIGH) */
99970 /*! @{ */
99971 #define USB3_ERSTBA05_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
99972 #define USB3_ERSTBA05_HI_ERSTBAddr_HI_SHIFT      (0U)
99973 /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
99974  *    defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the
99975  *    address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement
99976  *    to the Start state. Refer to Figure 20 in xHCI specification for more information. This field
99977  *    shall not be modified if HCHalted (HCH) = '0'
99978  */
99979 #define USB3_ERSTBA05_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA05_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA05_HI_ERSTBAddr_HI_MASK)
99980 /*! @} */
99981 
99982 /*! @name ERDP5_LO - Event Ring Dequeue Pointer (LOW) */
99983 /*! @{ */
99984 #define USB3_ERDP5_LO_DESI_MASK                  (0x7U)
99985 #define USB3_ERDP5_LO_DESI_SHIFT                 (0U)
99986 /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to
99987  *    accelerate checking the Event Ring full condition. This field is written with the low order 3 bits
99988  *    of the offset of the ERST entry which defines the Event Ring segment that the Event Ring
99989  *    Dequeue Pointer resides in
99990  */
99991 #define USB3_ERDP5_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_LO_DESI_SHIFT)) & USB3_ERDP5_LO_DESI_MASK)
99992 #define USB3_ERDP5_LO_EHB_MASK                   (0x8U)
99993 #define USB3_ERDP5_LO_EHB_SHIFT                  (3U)
99994 /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP
99995  *    bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written.
99996  *    Refer to section 4.17.2 of xHCI specification for more information
99997  */
99998 #define USB3_ERDP5_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_LO_EHB_SHIFT)) & USB3_ERDP5_LO_EHB_MASK)
99999 #define USB3_ERDP5_LO_ERDPtr_MASK                (0xFFFFFFF0U)
100000 #define USB3_ERDP5_LO_ERDPtr_SHIFT               (4U)
100001 /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits
100002  *    of the 64-bit address of the current Event Ring Dequeue Pointer
100003  */
100004 #define USB3_ERDP5_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_LO_ERDPtr_SHIFT)) & USB3_ERDP5_LO_ERDPtr_MASK)
100005 /*! @} */
100006 
100007 /*! @name ERDP5_HI - Event Ring Dequeue Pointer (HIGH) */
100008 /*! @{ */
100009 #define USB3_ERDP5_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
100010 #define USB3_ERDP5_HI_ERDPtr_HI_SHIFT            (0U)
100011 /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order
100012  *    bits of the 64-bit address of the current Event Ring Dequeue Pointer
100013  */
100014 #define USB3_ERDP5_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP5_HI_ERDPtr_HI_MASK)
100015 /*! @} */
100016 
100017 /*! @name IMAN6 - Interrupter Management */
100018 /*! @{ */
100019 #define USB3_IMAN6_IP_MASK                       (0x1U)
100020 #define USB3_IMAN6_IP_SHIFT                      (0U)
100021 /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the
100022  *    Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates
100023  *    that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI
100024  *    specification for the conditions that modify the state of this flag
100025  */
100026 #define USB3_IMAN6_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN6_IP_SHIFT)) & USB3_IMAN6_IP_MASK)
100027 #define USB3_IMAN6_IE_MASK                       (0x2U)
100028 #define USB3_IMAN6_IE_SHIFT                      (1U)
100029 /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is
100030  *    capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter
100031  *    shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is
100032  *    '0', then the Interrupter is prohibited from generating interrupts
100033  */
100034 #define USB3_IMAN6_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN6_IE_SHIFT)) & USB3_IMAN6_IE_MASK)
100035 /*! @} */
100036 
100037 /*! @name IMOD6 - Interrupter Moderation */
100038 /*! @{ */
100039 #define USB3_IMOD6_IMODI_MASK                    (0xFFFFU)
100040 #define USB3_IMOD6_IMODI_SHIFT                   (0U)
100041 /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum
100042  *    inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables
100043  *    interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and
100044  *    the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization
100045  *    and reset. It may be loaded with an alternative value by software when the Interrupter is
100046  *    initialized
100047  */
100048 #define USB3_IMOD6_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD6_IMODI_SHIFT)) & USB3_IMOD6_IMODI_MASK)
100049 #define USB3_IMOD6_IMODC_MASK                    (0xFFFF0000U)
100050 #define USB3_IMOD6_IMODC_SHIFT                   (16U)
100051 /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with
100052  *    the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated
100053  *    interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE
100054  *    and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time
100055  *    to alter the interrupt rate
100056  */
100057 #define USB3_IMOD6_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD6_IMODC_SHIFT)) & USB3_IMOD6_IMODC_MASK)
100058 /*! @} */
100059 
100060 /*! @name ERSTSZ6 - Event Ring Segment Table Size */
100061 /*! @{ */
100062 #define USB3_ERSTSZ6_ERSTS_MASK                  (0xFFFFU)
100063 #define USB3_ERSTSZ6_ERSTS_SHIFT                 (0U)
100064 /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of
100065  *    valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event
100066  *    Ring Segment Table Base Address register. The maximum value supported by an xHC implementation
100067  *    for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary
100068  *    Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at
100069  *    this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For
100070  *    the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior
100071  *    of the Event Ring. The Primary Event Ring cannot be disabled
100072  */
100073 #define USB3_ERSTSZ6_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ6_ERSTS_SHIFT)) & USB3_ERSTSZ6_ERSTS_MASK)
100074 /*! @} */
100075 
100076 /*! @name ERSTBA6_LO - Event Ring Segment Table Base Address (LOW) */
100077 /*! @{ */
100078 #define USB3_ERSTBA6_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
100079 #define USB3_ERSTBA6_LO_ERSTBAddr_LO_SHIFT       (6U)
100080 /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
100081  *    defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address
100082  *    is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement
100083  *    to the Start state. This field shall not be modified if HCHalted (HCH) = '0'
100084  */
100085 #define USB3_ERSTBA6_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA6_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA6_LO_ERSTBAddr_LO_MASK)
100086 /*! @} */
100087 
100088 /*! @name ERSTBA06_HI - Event Ring Segment Table Base Address (HIGH) */
100089 /*! @{ */
100090 #define USB3_ERSTBA06_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
100091 #define USB3_ERSTBA06_HI_ERSTBAddr_HI_SHIFT      (0U)
100092 /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
100093  *    defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the
100094  *    address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement
100095  *    to the Start state. Refer to Figure 20 in xHCI specification for more information. This field
100096  *    shall not be modified if HCHalted (HCH) = '0'
100097  */
100098 #define USB3_ERSTBA06_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA06_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA06_HI_ERSTBAddr_HI_MASK)
100099 /*! @} */
100100 
100101 /*! @name ERDP6_LO - Event Ring Dequeue Pointer (LOW) */
100102 /*! @{ */
100103 #define USB3_ERDP6_LO_DESI_MASK                  (0x7U)
100104 #define USB3_ERDP6_LO_DESI_SHIFT                 (0U)
100105 /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to
100106  *    accelerate checking the Event Ring full condition. This field is written with the low order 3 bits
100107  *    of the offset of the ERST entry which defines the Event Ring segment that the Event Ring
100108  *    Dequeue Pointer resides in
100109  */
100110 #define USB3_ERDP6_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_LO_DESI_SHIFT)) & USB3_ERDP6_LO_DESI_MASK)
100111 #define USB3_ERDP6_LO_EHB_MASK                   (0x8U)
100112 #define USB3_ERDP6_LO_EHB_SHIFT                  (3U)
100113 /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP
100114  *    bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written.
100115  *    Refer to section 4.17.2 of xHCI specification for more information
100116  */
100117 #define USB3_ERDP6_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_LO_EHB_SHIFT)) & USB3_ERDP6_LO_EHB_MASK)
100118 #define USB3_ERDP6_LO_ERDPtr_MASK                (0xFFFFFFF0U)
100119 #define USB3_ERDP6_LO_ERDPtr_SHIFT               (4U)
100120 /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits
100121  *    of the 64-bit address of the current Event Ring Dequeue Pointer
100122  */
100123 #define USB3_ERDP6_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_LO_ERDPtr_SHIFT)) & USB3_ERDP6_LO_ERDPtr_MASK)
100124 /*! @} */
100125 
100126 /*! @name ERDP6_HI - Event Ring Dequeue Pointer (HIGH) */
100127 /*! @{ */
100128 #define USB3_ERDP6_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
100129 #define USB3_ERDP6_HI_ERDPtr_HI_SHIFT            (0U)
100130 /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order
100131  *    bits of the 64-bit address of the current Event Ring Dequeue Pointer
100132  */
100133 #define USB3_ERDP6_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP6_HI_ERDPtr_HI_MASK)
100134 /*! @} */
100135 
100136 /*! @name IMAN7 - Interrupter Management */
100137 /*! @{ */
100138 #define USB3_IMAN7_IP_MASK                       (0x1U)
100139 #define USB3_IMAN7_IP_SHIFT                      (0U)
100140 /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the
100141  *    Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates
100142  *    that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI
100143  *    specification for the conditions that modify the state of this flag
100144  */
100145 #define USB3_IMAN7_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN7_IP_SHIFT)) & USB3_IMAN7_IP_MASK)
100146 #define USB3_IMAN7_IE_MASK                       (0x2U)
100147 #define USB3_IMAN7_IE_SHIFT                      (1U)
100148 /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is
100149  *    capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter
100150  *    shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is
100151  *    '0', then the Interrupter is prohibited from generating interrupts
100152  */
100153 #define USB3_IMAN7_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN7_IE_SHIFT)) & USB3_IMAN7_IE_MASK)
100154 /*! @} */
100155 
100156 /*! @name IMOD7 - Interrupter Moderation */
100157 /*! @{ */
100158 #define USB3_IMOD7_IMODI_MASK                    (0xFFFFU)
100159 #define USB3_IMOD7_IMODI_SHIFT                   (0U)
100160 /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum
100161  *    inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables
100162  *    interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and
100163  *    the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization
100164  *    and reset. It may be loaded with an alternative value by software when the Interrupter is
100165  *    initialized
100166  */
100167 #define USB3_IMOD7_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD7_IMODI_SHIFT)) & USB3_IMOD7_IMODI_MASK)
100168 #define USB3_IMOD7_IMODC_MASK                    (0xFFFF0000U)
100169 #define USB3_IMOD7_IMODC_SHIFT                   (16U)
100170 /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with
100171  *    the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated
100172  *    interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE
100173  *    and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time
100174  *    to alter the interrupt rate
100175  */
100176 #define USB3_IMOD7_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD7_IMODC_SHIFT)) & USB3_IMOD7_IMODC_MASK)
100177 /*! @} */
100178 
100179 /*! @name ERSTSZ7 - Event Ring Segment Table Size */
100180 /*! @{ */
100181 #define USB3_ERSTSZ7_ERSTS_MASK                  (0xFFFFU)
100182 #define USB3_ERSTSZ7_ERSTS_SHIFT                 (0U)
100183 /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of
100184  *    valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event
100185  *    Ring Segment Table Base Address register. The maximum value supported by an xHC implementation
100186  *    for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary
100187  *    Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at
100188  *    this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For
100189  *    the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior
100190  *    of the Event Ring. The Primary Event Ring cannot be disabled
100191  */
100192 #define USB3_ERSTSZ7_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ7_ERSTS_SHIFT)) & USB3_ERSTSZ7_ERSTS_MASK)
100193 /*! @} */
100194 
100195 /*! @name ERSTBA7_LO - Event Ring Segment Table Base Address (LOW) */
100196 /*! @{ */
100197 #define USB3_ERSTBA7_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
100198 #define USB3_ERSTBA7_LO_ERSTBAddr_LO_SHIFT       (6U)
100199 /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
100200  *    defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address
100201  *    is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement
100202  *    to the Start state. This field shall not be modified if HCHalted (HCH) = '0'
100203  */
100204 #define USB3_ERSTBA7_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA7_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA7_LO_ERSTBAddr_LO_MASK)
100205 /*! @} */
100206 
100207 /*! @name ERSTBA07_HI - Event Ring Segment Table Base Address (HIGH) */
100208 /*! @{ */
100209 #define USB3_ERSTBA07_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
100210 #define USB3_ERSTBA07_HI_ERSTBAddr_HI_SHIFT      (0U)
100211 /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field
100212  *    defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the
100213  *    address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement
100214  *    to the Start state. Refer to Figure 20 in xHCI specification for more information. This field
100215  *    shall not be modified if HCHalted (HCH) = '0'
100216  */
100217 #define USB3_ERSTBA07_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA07_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA07_HI_ERSTBAddr_HI_MASK)
100218 /*! @} */
100219 
100220 /*! @name ERDP7_LO - Event Ring Dequeue Pointer (LOW) */
100221 /*! @{ */
100222 #define USB3_ERDP7_LO_DESI_MASK                  (0x7U)
100223 #define USB3_ERDP7_LO_DESI_SHIFT                 (0U)
100224 /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to
100225  *    accelerate checking the Event Ring full condition. This field is written with the low order 3 bits
100226  *    of the offset of the ERST entry which defines the Event Ring segment that the Event Ring
100227  *    Dequeue Pointer resides in
100228  */
100229 #define USB3_ERDP7_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_LO_DESI_SHIFT)) & USB3_ERDP7_LO_DESI_MASK)
100230 #define USB3_ERDP7_LO_EHB_MASK                   (0x8U)
100231 #define USB3_ERDP7_LO_EHB_SHIFT                  (3U)
100232 /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP
100233  *    bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written.
100234  *    Refer to section 4.17.2 of xHCI specification for more information
100235  */
100236 #define USB3_ERDP7_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_LO_EHB_SHIFT)) & USB3_ERDP7_LO_EHB_MASK)
100237 #define USB3_ERDP7_LO_ERDPtr_MASK                (0xFFFFFFF0U)
100238 #define USB3_ERDP7_LO_ERDPtr_SHIFT               (4U)
100239 /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits
100240  *    of the 64-bit address of the current Event Ring Dequeue Pointer
100241  */
100242 #define USB3_ERDP7_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_LO_ERDPtr_SHIFT)) & USB3_ERDP7_LO_ERDPtr_MASK)
100243 /*! @} */
100244 
100245 /*! @name ERDP7_HI - Event Ring Dequeue Pointer (HIGH) */
100246 /*! @{ */
100247 #define USB3_ERDP7_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
100248 #define USB3_ERDP7_HI_ERDPtr_HI_SHIFT            (0U)
100249 /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order
100250  *    bits of the 64-bit address of the current Event Ring Dequeue Pointer
100251  */
100252 #define USB3_ERDP7_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP7_HI_ERDPtr_HI_MASK)
100253 /*! @} */
100254 
100255 /*! @name DB0 - Host Controller Doorbell */
100256 /*! @{ */
100257 #define USB3_DB0_DB_target_MASK                  (0xFFU)
100258 #define USB3_DB0_DB_target_SHIFT                 (0U)
100259 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100260  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100261  *    Note that Doorbell Register 0 is dedicated to Command Ring and decodes this field differently
100262  *    than the other Doorbell Registers. Possible values ( For this register, there is only one valid
100263  *    value for the DB Target field, 0 (Host Controller Command). The remaining values (1-255) are
100264  *    reserved.): 0: Command Doorbell 1:247 Reserved 248:255 Vendor Defined This field returns zero
100265  *    when read and should be treated as undefined by software. When the Command Doorbell is
100266  *    written, the DB Stream ID field shall be cleared to zero
100267  */
100268 #define USB3_DB0_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB0_DB_target_SHIFT)) & USB3_DB0_DB_target_MASK)
100269 #define USB3_DB0_DB_stream_ID_MASK               (0xFFFF0000U)
100270 #define USB3_DB0_DB_stream_ID_SHIFT              (16U)
100271 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100272  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100273  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100274  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100275  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100276  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100277  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100278  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100279  *    returns zero when read
100280  */
100281 #define USB3_DB0_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB0_DB_stream_ID_SHIFT)) & USB3_DB0_DB_stream_ID_MASK)
100282 /*! @} */
100283 
100284 /*! @name DB1 - Doorbell Array */
100285 /*! @{ */
100286 #define USB3_DB1_DB_target_MASK                  (0xFFU)
100287 #define USB3_DB1_DB_target_SHIFT                 (0U)
100288 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100289  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100290  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100291  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100292  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100293  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100294  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100295  *    shall be cleared to zero
100296  */
100297 #define USB3_DB1_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB1_DB_target_SHIFT)) & USB3_DB1_DB_target_MASK)
100298 #define USB3_DB1_DB_stream_ID_MASK               (0xFFFF0000U)
100299 #define USB3_DB1_DB_stream_ID_SHIFT              (16U)
100300 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100301  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100302  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100303  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100304  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100305  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100306  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100307  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100308  *    returns zero when read
100309  */
100310 #define USB3_DB1_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB1_DB_stream_ID_SHIFT)) & USB3_DB1_DB_stream_ID_MASK)
100311 /*! @} */
100312 
100313 /*! @name DB2 - Doorbell Array */
100314 /*! @{ */
100315 #define USB3_DB2_DB_target_MASK                  (0xFFU)
100316 #define USB3_DB2_DB_target_SHIFT                 (0U)
100317 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100318  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100319  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100320  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100321  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100322  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100323  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100324  *    shall be cleared to zero
100325  */
100326 #define USB3_DB2_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB2_DB_target_SHIFT)) & USB3_DB2_DB_target_MASK)
100327 #define USB3_DB2_DB_stream_ID_MASK               (0xFFFF0000U)
100328 #define USB3_DB2_DB_stream_ID_SHIFT              (16U)
100329 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100330  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100331  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100332  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100333  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100334  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100335  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100336  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100337  *    returns zero when read
100338  */
100339 #define USB3_DB2_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB2_DB_stream_ID_SHIFT)) & USB3_DB2_DB_stream_ID_MASK)
100340 /*! @} */
100341 
100342 /*! @name DB3 - Doorbell Array */
100343 /*! @{ */
100344 #define USB3_DB3_DB_target_MASK                  (0xFFU)
100345 #define USB3_DB3_DB_target_SHIFT                 (0U)
100346 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100347  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100348  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100349  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100350  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100351  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100352  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100353  *    shall be cleared to zero
100354  */
100355 #define USB3_DB3_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB3_DB_target_SHIFT)) & USB3_DB3_DB_target_MASK)
100356 #define USB3_DB3_DB_stream_ID_MASK               (0xFFFF0000U)
100357 #define USB3_DB3_DB_stream_ID_SHIFT              (16U)
100358 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100359  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100360  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100361  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100362  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100363  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100364  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100365  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100366  *    returns zero when read
100367  */
100368 #define USB3_DB3_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB3_DB_stream_ID_SHIFT)) & USB3_DB3_DB_stream_ID_MASK)
100369 /*! @} */
100370 
100371 /*! @name DB4 - Doorbell Array */
100372 /*! @{ */
100373 #define USB3_DB4_DB_target_MASK                  (0xFFU)
100374 #define USB3_DB4_DB_target_SHIFT                 (0U)
100375 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100376  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100377  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100378  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100379  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100380  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100381  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100382  *    shall be cleared to zero
100383  */
100384 #define USB3_DB4_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB4_DB_target_SHIFT)) & USB3_DB4_DB_target_MASK)
100385 #define USB3_DB4_DB_stream_ID_MASK               (0xFFFF0000U)
100386 #define USB3_DB4_DB_stream_ID_SHIFT              (16U)
100387 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100388  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100389  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100390  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100391  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100392  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100393  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100394  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100395  *    returns zero when read
100396  */
100397 #define USB3_DB4_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB4_DB_stream_ID_SHIFT)) & USB3_DB4_DB_stream_ID_MASK)
100398 /*! @} */
100399 
100400 /*! @name DB5 - Doorbell Array */
100401 /*! @{ */
100402 #define USB3_DB5_DB_target_MASK                  (0xFFU)
100403 #define USB3_DB5_DB_target_SHIFT                 (0U)
100404 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100405  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100406  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100407  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100408  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100409  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100410  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100411  *    shall be cleared to zero
100412  */
100413 #define USB3_DB5_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB5_DB_target_SHIFT)) & USB3_DB5_DB_target_MASK)
100414 #define USB3_DB5_DB_stream_ID_MASK               (0xFFFF0000U)
100415 #define USB3_DB5_DB_stream_ID_SHIFT              (16U)
100416 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100417  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100418  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100419  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100420  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100421  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100422  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100423  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100424  *    returns zero when read
100425  */
100426 #define USB3_DB5_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB5_DB_stream_ID_SHIFT)) & USB3_DB5_DB_stream_ID_MASK)
100427 /*! @} */
100428 
100429 /*! @name DB6 - Doorbell Array */
100430 /*! @{ */
100431 #define USB3_DB6_DB_target_MASK                  (0xFFU)
100432 #define USB3_DB6_DB_target_SHIFT                 (0U)
100433 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100434  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100435  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100436  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100437  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100438  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100439  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100440  *    shall be cleared to zero
100441  */
100442 #define USB3_DB6_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB6_DB_target_SHIFT)) & USB3_DB6_DB_target_MASK)
100443 #define USB3_DB6_DB_stream_ID_MASK               (0xFFFF0000U)
100444 #define USB3_DB6_DB_stream_ID_SHIFT              (16U)
100445 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100446  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100447  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100448  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100449  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100450  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100451  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100452  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100453  *    returns zero when read
100454  */
100455 #define USB3_DB6_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB6_DB_stream_ID_SHIFT)) & USB3_DB6_DB_stream_ID_MASK)
100456 /*! @} */
100457 
100458 /*! @name DB7 - Doorbell Array */
100459 /*! @{ */
100460 #define USB3_DB7_DB_target_MASK                  (0xFFU)
100461 #define USB3_DB7_DB_target_SHIFT                 (0U)
100462 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100463  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100464  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100465  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100466  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100467  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100468  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100469  *    shall be cleared to zero
100470  */
100471 #define USB3_DB7_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB7_DB_target_SHIFT)) & USB3_DB7_DB_target_MASK)
100472 #define USB3_DB7_DB_stream_ID_MASK               (0xFFFF0000U)
100473 #define USB3_DB7_DB_stream_ID_SHIFT              (16U)
100474 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100475  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100476  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100477  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100478  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100479  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100480  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100481  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100482  *    returns zero when read
100483  */
100484 #define USB3_DB7_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB7_DB_stream_ID_SHIFT)) & USB3_DB7_DB_stream_ID_MASK)
100485 /*! @} */
100486 
100487 /*! @name DB8 - Doorbell Array */
100488 /*! @{ */
100489 #define USB3_DB8_DB_target_MASK                  (0xFFU)
100490 #define USB3_DB8_DB_target_SHIFT                 (0U)
100491 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100492  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100493  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100494  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100495  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100496  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100497  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100498  *    shall be cleared to zero
100499  */
100500 #define USB3_DB8_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB8_DB_target_SHIFT)) & USB3_DB8_DB_target_MASK)
100501 #define USB3_DB8_DB_stream_ID_MASK               (0xFFFF0000U)
100502 #define USB3_DB8_DB_stream_ID_SHIFT              (16U)
100503 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100504  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100505  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100506  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100507  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100508  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100509  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100510  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100511  *    returns zero when read
100512  */
100513 #define USB3_DB8_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB8_DB_stream_ID_SHIFT)) & USB3_DB8_DB_stream_ID_MASK)
100514 /*! @} */
100515 
100516 /*! @name DB9 - Doorbell Array */
100517 /*! @{ */
100518 #define USB3_DB9_DB_target_MASK                  (0xFFU)
100519 #define USB3_DB9_DB_target_SHIFT                 (0U)
100520 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100521  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100522  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100523  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100524  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100525  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100526  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100527  *    shall be cleared to zero
100528  */
100529 #define USB3_DB9_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB9_DB_target_SHIFT)) & USB3_DB9_DB_target_MASK)
100530 #define USB3_DB9_DB_stream_ID_MASK               (0xFFFF0000U)
100531 #define USB3_DB9_DB_stream_ID_SHIFT              (16U)
100532 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100533  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100534  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100535  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100536  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100537  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100538  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100539  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100540  *    returns zero when read
100541  */
100542 #define USB3_DB9_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB9_DB_stream_ID_SHIFT)) & USB3_DB9_DB_stream_ID_MASK)
100543 /*! @} */
100544 
100545 /*! @name DB10 - Doorbell Array */
100546 /*! @{ */
100547 #define USB3_DB10_DB_target_MASK                 (0xFFU)
100548 #define USB3_DB10_DB_target_SHIFT                (0U)
100549 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100550  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100551  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100552  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100553  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100554  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100555  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100556  *    shall be cleared to zero
100557  */
100558 #define USB3_DB10_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB10_DB_target_SHIFT)) & USB3_DB10_DB_target_MASK)
100559 #define USB3_DB10_DB_stream_ID_MASK              (0xFFFF0000U)
100560 #define USB3_DB10_DB_stream_ID_SHIFT             (16U)
100561 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100562  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100563  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100564  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100565  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100566  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100567  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100568  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100569  *    returns zero when read
100570  */
100571 #define USB3_DB10_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB10_DB_stream_ID_SHIFT)) & USB3_DB10_DB_stream_ID_MASK)
100572 /*! @} */
100573 
100574 /*! @name DB11 - Doorbell Array */
100575 /*! @{ */
100576 #define USB3_DB11_DB_target_MASK                 (0xFFU)
100577 #define USB3_DB11_DB_target_SHIFT                (0U)
100578 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100579  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100580  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100581  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100582  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100583  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100584  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100585  *    shall be cleared to zero
100586  */
100587 #define USB3_DB11_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB11_DB_target_SHIFT)) & USB3_DB11_DB_target_MASK)
100588 #define USB3_DB11_DB_stream_ID_MASK              (0xFFFF0000U)
100589 #define USB3_DB11_DB_stream_ID_SHIFT             (16U)
100590 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100591  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100592  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100593  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100594  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100595  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100596  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100597  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100598  *    returns zero when read
100599  */
100600 #define USB3_DB11_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB11_DB_stream_ID_SHIFT)) & USB3_DB11_DB_stream_ID_MASK)
100601 /*! @} */
100602 
100603 /*! @name DB12 - Doorbell Array */
100604 /*! @{ */
100605 #define USB3_DB12_DB_target_MASK                 (0xFFU)
100606 #define USB3_DB12_DB_target_SHIFT                (0U)
100607 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100608  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100609  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100610  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100611  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100612  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100613  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100614  *    shall be cleared to zero
100615  */
100616 #define USB3_DB12_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB12_DB_target_SHIFT)) & USB3_DB12_DB_target_MASK)
100617 #define USB3_DB12_DB_stream_ID_MASK              (0xFFFF0000U)
100618 #define USB3_DB12_DB_stream_ID_SHIFT             (16U)
100619 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100620  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100621  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100622  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100623  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100624  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100625  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100626  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100627  *    returns zero when read
100628  */
100629 #define USB3_DB12_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB12_DB_stream_ID_SHIFT)) & USB3_DB12_DB_stream_ID_MASK)
100630 /*! @} */
100631 
100632 /*! @name DB13 - Doorbell Array */
100633 /*! @{ */
100634 #define USB3_DB13_DB_target_MASK                 (0xFFU)
100635 #define USB3_DB13_DB_target_SHIFT                (0U)
100636 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100637  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100638  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100639  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100640  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100641  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100642  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100643  *    shall be cleared to zero
100644  */
100645 #define USB3_DB13_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB13_DB_target_SHIFT)) & USB3_DB13_DB_target_MASK)
100646 #define USB3_DB13_DB_stream_ID_MASK              (0xFFFF0000U)
100647 #define USB3_DB13_DB_stream_ID_SHIFT             (16U)
100648 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100649  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100650  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100651  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100652  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100653  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100654  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100655  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100656  *    returns zero when read
100657  */
100658 #define USB3_DB13_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB13_DB_stream_ID_SHIFT)) & USB3_DB13_DB_stream_ID_MASK)
100659 /*! @} */
100660 
100661 /*! @name DB14 - Doorbell Array */
100662 /*! @{ */
100663 #define USB3_DB14_DB_target_MASK                 (0xFFU)
100664 #define USB3_DB14_DB_target_SHIFT                (0U)
100665 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100666  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100667  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100668  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100669  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100670  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100671  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100672  *    shall be cleared to zero
100673  */
100674 #define USB3_DB14_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB14_DB_target_SHIFT)) & USB3_DB14_DB_target_MASK)
100675 #define USB3_DB14_DB_stream_ID_MASK              (0xFFFF0000U)
100676 #define USB3_DB14_DB_stream_ID_SHIFT             (16U)
100677 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100678  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100679  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100680  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100681  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100682  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100683  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100684  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100685  *    returns zero when read
100686  */
100687 #define USB3_DB14_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB14_DB_stream_ID_SHIFT)) & USB3_DB14_DB_stream_ID_MASK)
100688 /*! @} */
100689 
100690 /*! @name DB15 - Doorbell Array */
100691 /*! @{ */
100692 #define USB3_DB15_DB_target_MASK                 (0xFFU)
100693 #define USB3_DB15_DB_target_SHIFT                (0U)
100694 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100695  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100696  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100697  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100698  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100699  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100700  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100701  *    shall be cleared to zero
100702  */
100703 #define USB3_DB15_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB15_DB_target_SHIFT)) & USB3_DB15_DB_target_MASK)
100704 #define USB3_DB15_DB_stream_ID_MASK              (0xFFFF0000U)
100705 #define USB3_DB15_DB_stream_ID_SHIFT             (16U)
100706 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100707  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100708  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100709  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100710  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100711  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100712  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100713  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100714  *    returns zero when read
100715  */
100716 #define USB3_DB15_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB15_DB_stream_ID_SHIFT)) & USB3_DB15_DB_stream_ID_MASK)
100717 /*! @} */
100718 
100719 /*! @name DB16 - Doorbell Array */
100720 /*! @{ */
100721 #define USB3_DB16_DB_target_MASK                 (0xFFU)
100722 #define USB3_DB16_DB_target_SHIFT                (0U)
100723 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100724  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100725  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100726  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100727  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100728  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100729  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100730  *    shall be cleared to zero
100731  */
100732 #define USB3_DB16_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB16_DB_target_SHIFT)) & USB3_DB16_DB_target_MASK)
100733 #define USB3_DB16_DB_stream_ID_MASK              (0xFFFF0000U)
100734 #define USB3_DB16_DB_stream_ID_SHIFT             (16U)
100735 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100736  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100737  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100738  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100739  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100740  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100741  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100742  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100743  *    returns zero when read
100744  */
100745 #define USB3_DB16_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB16_DB_stream_ID_SHIFT)) & USB3_DB16_DB_stream_ID_MASK)
100746 /*! @} */
100747 
100748 /*! @name DB17 - Doorbell Array */
100749 /*! @{ */
100750 #define USB3_DB17_DB_target_MASK                 (0xFFU)
100751 #define USB3_DB17_DB_target_SHIFT                (0U)
100752 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100753  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100754  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100755  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100756  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100757  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100758  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100759  *    shall be cleared to zero
100760  */
100761 #define USB3_DB17_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB17_DB_target_SHIFT)) & USB3_DB17_DB_target_MASK)
100762 #define USB3_DB17_DB_stream_ID_MASK              (0xFFFF0000U)
100763 #define USB3_DB17_DB_stream_ID_SHIFT             (16U)
100764 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100765  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100766  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100767  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100768  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100769  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100770  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100771  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100772  *    returns zero when read
100773  */
100774 #define USB3_DB17_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB17_DB_stream_ID_SHIFT)) & USB3_DB17_DB_stream_ID_MASK)
100775 /*! @} */
100776 
100777 /*! @name DB18 - Doorbell Array */
100778 /*! @{ */
100779 #define USB3_DB18_DB_target_MASK                 (0xFFU)
100780 #define USB3_DB18_DB_target_SHIFT                (0U)
100781 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100782  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100783  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100784  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100785  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100786  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100787  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100788  *    shall be cleared to zero
100789  */
100790 #define USB3_DB18_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB18_DB_target_SHIFT)) & USB3_DB18_DB_target_MASK)
100791 #define USB3_DB18_DB_stream_ID_MASK              (0xFFFF0000U)
100792 #define USB3_DB18_DB_stream_ID_SHIFT             (16U)
100793 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100794  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100795  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100796  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100797  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100798  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100799  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100800  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100801  *    returns zero when read
100802  */
100803 #define USB3_DB18_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB18_DB_stream_ID_SHIFT)) & USB3_DB18_DB_stream_ID_MASK)
100804 /*! @} */
100805 
100806 /*! @name DB19 - Doorbell Array */
100807 /*! @{ */
100808 #define USB3_DB19_DB_target_MASK                 (0xFFU)
100809 #define USB3_DB19_DB_target_SHIFT                (0U)
100810 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100811  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100812  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100813  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100814  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100815  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100816  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100817  *    shall be cleared to zero
100818  */
100819 #define USB3_DB19_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB19_DB_target_SHIFT)) & USB3_DB19_DB_target_MASK)
100820 #define USB3_DB19_DB_stream_ID_MASK              (0xFFFF0000U)
100821 #define USB3_DB19_DB_stream_ID_SHIFT             (16U)
100822 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100823  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100824  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100825  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100826  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100827  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100828  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100829  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100830  *    returns zero when read
100831  */
100832 #define USB3_DB19_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB19_DB_stream_ID_SHIFT)) & USB3_DB19_DB_stream_ID_MASK)
100833 /*! @} */
100834 
100835 /*! @name DB20 - Doorbell Array */
100836 /*! @{ */
100837 #define USB3_DB20_DB_target_MASK                 (0xFFU)
100838 #define USB3_DB20_DB_target_SHIFT                (0U)
100839 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100840  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100841  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100842  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100843  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100844  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100845  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100846  *    shall be cleared to zero
100847  */
100848 #define USB3_DB20_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB20_DB_target_SHIFT)) & USB3_DB20_DB_target_MASK)
100849 #define USB3_DB20_DB_stream_ID_MASK              (0xFFFF0000U)
100850 #define USB3_DB20_DB_stream_ID_SHIFT             (16U)
100851 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100852  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100853  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100854  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100855  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100856  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100857  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100858  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100859  *    returns zero when read
100860  */
100861 #define USB3_DB20_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB20_DB_stream_ID_SHIFT)) & USB3_DB20_DB_stream_ID_MASK)
100862 /*! @} */
100863 
100864 /*! @name DB21 - Doorbell Array */
100865 /*! @{ */
100866 #define USB3_DB21_DB_target_MASK                 (0xFFU)
100867 #define USB3_DB21_DB_target_SHIFT                (0U)
100868 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100869  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100870  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100871  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100872  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100873  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100874  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100875  *    shall be cleared to zero
100876  */
100877 #define USB3_DB21_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB21_DB_target_SHIFT)) & USB3_DB21_DB_target_MASK)
100878 #define USB3_DB21_DB_stream_ID_MASK              (0xFFFF0000U)
100879 #define USB3_DB21_DB_stream_ID_SHIFT             (16U)
100880 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100881  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100882  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100883  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100884  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100885  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100886  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100887  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100888  *    returns zero when read
100889  */
100890 #define USB3_DB21_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB21_DB_stream_ID_SHIFT)) & USB3_DB21_DB_stream_ID_MASK)
100891 /*! @} */
100892 
100893 /*! @name DB22 - Doorbell Array */
100894 /*! @{ */
100895 #define USB3_DB22_DB_target_MASK                 (0xFFU)
100896 #define USB3_DB22_DB_target_SHIFT                (0U)
100897 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100898  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100899  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100900  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100901  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100902  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100903  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100904  *    shall be cleared to zero
100905  */
100906 #define USB3_DB22_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB22_DB_target_SHIFT)) & USB3_DB22_DB_target_MASK)
100907 #define USB3_DB22_DB_stream_ID_MASK              (0xFFFF0000U)
100908 #define USB3_DB22_DB_stream_ID_SHIFT             (16U)
100909 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100910  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100911  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100912  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100913  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100914  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100915  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100916  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100917  *    returns zero when read
100918  */
100919 #define USB3_DB22_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB22_DB_stream_ID_SHIFT)) & USB3_DB22_DB_stream_ID_MASK)
100920 /*! @} */
100921 
100922 /*! @name DB23 - Doorbell Array */
100923 /*! @{ */
100924 #define USB3_DB23_DB_target_MASK                 (0xFFU)
100925 #define USB3_DB23_DB_target_SHIFT                (0U)
100926 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100927  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100928  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100929  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100930  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100931  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100932  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100933  *    shall be cleared to zero
100934  */
100935 #define USB3_DB23_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB23_DB_target_SHIFT)) & USB3_DB23_DB_target_MASK)
100936 #define USB3_DB23_DB_stream_ID_MASK              (0xFFFF0000U)
100937 #define USB3_DB23_DB_stream_ID_SHIFT             (16U)
100938 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100939  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100940  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100941  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100942  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100943  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100944  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100945  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100946  *    returns zero when read
100947  */
100948 #define USB3_DB23_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB23_DB_stream_ID_SHIFT)) & USB3_DB23_DB_stream_ID_MASK)
100949 /*! @} */
100950 
100951 /*! @name DB24 - Doorbell Array */
100952 /*! @{ */
100953 #define USB3_DB24_DB_target_MASK                 (0xFFU)
100954 #define USB3_DB24_DB_target_SHIFT                (0U)
100955 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100956  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100957  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100958  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100959  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100960  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100961  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100962  *    shall be cleared to zero
100963  */
100964 #define USB3_DB24_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB24_DB_target_SHIFT)) & USB3_DB24_DB_target_MASK)
100965 #define USB3_DB24_DB_stream_ID_MASK              (0xFFFF0000U)
100966 #define USB3_DB24_DB_stream_ID_SHIFT             (16U)
100967 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100968  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100969  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100970  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
100971  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
100972  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
100973  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
100974  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
100975  *    returns zero when read
100976  */
100977 #define USB3_DB24_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB24_DB_stream_ID_SHIFT)) & USB3_DB24_DB_stream_ID_MASK)
100978 /*! @} */
100979 
100980 /*! @name DB25 - Doorbell Array */
100981 /*! @{ */
100982 #define USB3_DB25_DB_target_MASK                 (0xFFU)
100983 #define USB3_DB25_DB_target_SHIFT                (0U)
100984 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
100985  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
100986  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
100987  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
100988  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
100989  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
100990  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
100991  *    shall be cleared to zero
100992  */
100993 #define USB3_DB25_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB25_DB_target_SHIFT)) & USB3_DB25_DB_target_MASK)
100994 #define USB3_DB25_DB_stream_ID_MASK              (0xFFFF0000U)
100995 #define USB3_DB25_DB_stream_ID_SHIFT             (16U)
100996 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
100997  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
100998  *    doorbell reference is targeting. System software is responsible for ensuring that the value
100999  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
101000  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
101001  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
101002  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
101003  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
101004  *    returns zero when read
101005  */
101006 #define USB3_DB25_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB25_DB_stream_ID_SHIFT)) & USB3_DB25_DB_stream_ID_MASK)
101007 /*! @} */
101008 
101009 /*! @name DB26 - Doorbell Array */
101010 /*! @{ */
101011 #define USB3_DB26_DB_target_MASK                 (0xFFU)
101012 #define USB3_DB26_DB_target_SHIFT                (0U)
101013 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
101014  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
101015  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
101016  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
101017  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
101018  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
101019  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
101020  *    shall be cleared to zero
101021  */
101022 #define USB3_DB26_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB26_DB_target_SHIFT)) & USB3_DB26_DB_target_MASK)
101023 #define USB3_DB26_DB_stream_ID_MASK              (0xFFFF0000U)
101024 #define USB3_DB26_DB_stream_ID_SHIFT             (16U)
101025 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
101026  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
101027  *    doorbell reference is targeting. System software is responsible for ensuring that the value
101028  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
101029  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
101030  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
101031  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
101032  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
101033  *    returns zero when read
101034  */
101035 #define USB3_DB26_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB26_DB_stream_ID_SHIFT)) & USB3_DB26_DB_stream_ID_MASK)
101036 /*! @} */
101037 
101038 /*! @name DB27 - Doorbell Array */
101039 /*! @{ */
101040 #define USB3_DB27_DB_target_MASK                 (0xFFU)
101041 #define USB3_DB27_DB_target_SHIFT                (0U)
101042 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
101043  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
101044  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
101045  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
101046  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
101047  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
101048  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
101049  *    shall be cleared to zero
101050  */
101051 #define USB3_DB27_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB27_DB_target_SHIFT)) & USB3_DB27_DB_target_MASK)
101052 #define USB3_DB27_DB_stream_ID_MASK              (0xFFFF0000U)
101053 #define USB3_DB27_DB_stream_ID_SHIFT             (16U)
101054 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
101055  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
101056  *    doorbell reference is targeting. System software is responsible for ensuring that the value
101057  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
101058  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
101059  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
101060  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
101061  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
101062  *    returns zero when read
101063  */
101064 #define USB3_DB27_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB27_DB_stream_ID_SHIFT)) & USB3_DB27_DB_stream_ID_MASK)
101065 /*! @} */
101066 
101067 /*! @name DB28 - Doorbell Array */
101068 /*! @{ */
101069 #define USB3_DB28_DB_target_MASK                 (0xFFU)
101070 #define USB3_DB28_DB_target_SHIFT                (0U)
101071 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
101072  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
101073  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
101074  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
101075  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
101076  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
101077  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
101078  *    shall be cleared to zero
101079  */
101080 #define USB3_DB28_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB28_DB_target_SHIFT)) & USB3_DB28_DB_target_MASK)
101081 #define USB3_DB28_DB_stream_ID_MASK              (0xFFFF0000U)
101082 #define USB3_DB28_DB_stream_ID_SHIFT             (16U)
101083 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
101084  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
101085  *    doorbell reference is targeting. System software is responsible for ensuring that the value
101086  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
101087  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
101088  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
101089  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
101090  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
101091  *    returns zero when read
101092  */
101093 #define USB3_DB28_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB28_DB_stream_ID_SHIFT)) & USB3_DB28_DB_stream_ID_MASK)
101094 /*! @} */
101095 
101096 /*! @name DB29 - Doorbell Array */
101097 /*! @{ */
101098 #define USB3_DB29_DB_target_MASK                 (0xFFU)
101099 #define USB3_DB29_DB_target_SHIFT                (0U)
101100 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
101101  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
101102  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
101103  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
101104  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
101105  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
101106  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
101107  *    shall be cleared to zero
101108  */
101109 #define USB3_DB29_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB29_DB_target_SHIFT)) & USB3_DB29_DB_target_MASK)
101110 #define USB3_DB29_DB_stream_ID_MASK              (0xFFFF0000U)
101111 #define USB3_DB29_DB_stream_ID_SHIFT             (16U)
101112 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
101113  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
101114  *    doorbell reference is targeting. System software is responsible for ensuring that the value
101115  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
101116  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
101117  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
101118  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
101119  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
101120  *    returns zero when read
101121  */
101122 #define USB3_DB29_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB29_DB_stream_ID_SHIFT)) & USB3_DB29_DB_stream_ID_MASK)
101123 /*! @} */
101124 
101125 /*! @name DB30 - Doorbell Array */
101126 /*! @{ */
101127 #define USB3_DB30_DB_target_MASK                 (0xFFU)
101128 #define USB3_DB30_DB_target_SHIFT                (0U)
101129 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
101130  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
101131  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
101132  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
101133  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
101134  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
101135  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
101136  *    shall be cleared to zero
101137  */
101138 #define USB3_DB30_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB30_DB_target_SHIFT)) & USB3_DB30_DB_target_MASK)
101139 #define USB3_DB30_DB_stream_ID_MASK              (0xFFFF0000U)
101140 #define USB3_DB30_DB_stream_ID_SHIFT             (16U)
101141 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
101142  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
101143  *    doorbell reference is targeting. System software is responsible for ensuring that the value
101144  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
101145  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
101146  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
101147  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
101148  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
101149  *    returns zero when read
101150  */
101151 #define USB3_DB30_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB30_DB_stream_ID_SHIFT)) & USB3_DB30_DB_stream_ID_MASK)
101152 /*! @} */
101153 
101154 /*! @name DB31 - Doorbell Array */
101155 /*! @{ */
101156 #define USB3_DB31_DB_target_MASK                 (0xFFU)
101157 #define USB3_DB31_DB_target_SHIFT                (0U)
101158 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
101159  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
101160  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
101161  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
101162  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
101163  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
101164  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
101165  *    shall be cleared to zero
101166  */
101167 #define USB3_DB31_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB31_DB_target_SHIFT)) & USB3_DB31_DB_target_MASK)
101168 #define USB3_DB31_DB_stream_ID_MASK              (0xFFFF0000U)
101169 #define USB3_DB31_DB_stream_ID_SHIFT             (16U)
101170 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
101171  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
101172  *    doorbell reference is targeting. System software is responsible for ensuring that the value
101173  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
101174  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
101175  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
101176  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
101177  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
101178  *    returns zero when read
101179  */
101180 #define USB3_DB31_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB31_DB_stream_ID_SHIFT)) & USB3_DB31_DB_stream_ID_MASK)
101181 /*! @} */
101182 
101183 /*! @name DB32 - Doorbell Array */
101184 /*! @{ */
101185 #define USB3_DB32_DB_target_MASK                 (0xFFU)
101186 #define USB3_DB32_DB_target_SHIFT                (0U)
101187 /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell
101188  *    reference. The table below defines the xHC notification that is generated by ringing the doorbell.
101189  *    Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer
101190  *    Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN
101191  *    Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update
101192  *    32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be
101193  *    treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field
101194  *    shall be cleared to zero
101195  */
101196 #define USB3_DB32_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB32_DB_target_SHIFT)) & USB3_DB32_DB_target_MASK)
101197 #define USB3_DB32_DB_stream_ID_MASK              (0xFFFF0000U)
101198 #define USB3_DB32_DB_stream_ID_SHIFT             (16U)
101199 /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context
101200  *    Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the
101201  *    doorbell reference is targeting. System software is responsible for ensuring that the value
101202  *    written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535
101203  *    (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this
101204  *    field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
101205  *    written to this field, the doorbell reference shall be ignored. This field only applies to Device
101206  *    Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field
101207  *    returns zero when read
101208  */
101209 #define USB3_DB32_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB32_DB_stream_ID_SHIFT)) & USB3_DB32_DB_stream_ID_MASK)
101210 /*! @} */
101211 
101212 /*! @name XECP_PORT_CAP_REG - USB3 Extended capability */
101213 /*! @{ */
101214 #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_MASK (0xFFU)
101215 #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_SHIFT (0U)
101216 /*! XHCI_PORT_CAP_ID - XHCI_PORT_CAP_ID. Port capability ID
101217  */
101218 #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_SHIFT)) & USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_MASK)
101219 #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_MASK (0xFF00U)
101220 #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_SHIFT (8U)
101221 /*! XHCI_PORT_CAPABILITY_DW - XHCI_PORT_CAPABILITY_DW. Next Item Pointer. This field provides an
101222  *    offset pointing to the location of next item in the functions capability list
101223  */
101224 #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_SHIFT)) & USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_MASK)
101225 #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_MASK (0xFF0000U)
101226 #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_SHIFT (16U)
101227 /*! XHCI_PORT_CAP_REV - XHCI_PORT_CAP_REV : revision of the Port Capability structure
101228  */
101229 #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_SHIFT)) & USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_MASK)
101230 #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_MASK (0x1000000U)
101231 #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_SHIFT (24U)
101232 /*! LPM_2_STB_SWITCH_CAPABLE - xHC is capable of switching to stb_clk
101233  */
101234 #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_SHIFT)) & USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_MASK)
101235 #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_MASK (0x2000000U)
101236 #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_SHIFT (25U)
101237 /*! LPM_2_STB_SWITCH_EN - Enable switching to stb_clk
101238  */
101239 #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_SHIFT)) & USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_MASK)
101240 /*! @} */
101241 
101242 /*! @name XECP_PORT_1_REG - USB3 Extended capability */
101243 /*! @{ */
101244 #define USB3_XECP_PORT_1_REG_TRAINING_FAIL_MASK  (0x1U)
101245 #define USB3_XECP_PORT_1_REG_TRAINING_FAIL_SHIFT (0U)
101246 /*! TRAINING_FAIL - When reading: Link Polling training error flag status, When writing '1': clear
101247  *    the Link Polling training error flag, When writing '0': no effect
101248  */
101249 #define USB3_XECP_PORT_1_REG_TRAINING_FAIL(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_TRAINING_FAIL_SHIFT)) & USB3_XECP_PORT_1_REG_TRAINING_FAIL_MASK)
101250 #define USB3_XECP_PORT_1_REG_TERM_DEB_MAX_MASK   (0x6U)
101251 #define USB3_XECP_PORT_1_REG_TERM_DEB_MAX_SHIFT  (1U)
101252 /*! TERM_DEB_MAX - Number of the consecutive lack of Far-end Rx Termination detected that causes
101253  *    transition from SS.Inactive to RxDetect state
101254  */
101255 #define USB3_XECP_PORT_1_REG_TERM_DEB_MAX(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_TERM_DEB_MAX_SHIFT)) & USB3_XECP_PORT_1_REG_TERM_DEB_MAX_MASK)
101256 #define USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_MASK (0x8U)
101257 #define USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_SHIFT (3U)
101258 /*! U3_SPUR_LFPS_FIX - Enable filtering out spurious LFPS when entering U3 state
101259  */
101260 #define USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_SHIFT)) & USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_MASK)
101261 #define USB3_XECP_PORT_1_REG_SKP_OS_FIX_MASK     (0x10U)
101262 #define USB3_XECP_PORT_1_REG_SKP_OS_FIX_SHIFT    (4U)
101263 /*! SKP_OS_FIX - Change counting number of symbols for SKP OS insertion (only for the 1st SKP OS)
101264  */
101265 #define USB3_XECP_PORT_1_REG_SKP_OS_FIX(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_SKP_OS_FIX_SHIFT)) & USB3_XECP_PORT_1_REG_SKP_OS_FIX_MASK)
101266 #define USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_MASK (0x20U)
101267 #define USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_SHIFT (5U)
101268 /*! TTIME_FOR_RESET_EN - Enable tTimeForResetError timer
101269  */
101270 #define USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_SHIFT)) & USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_MASK)
101271 #define USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_MASK (0x7F00U)
101272 #define USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_SHIFT (8U)
101273 /*! U1_LFPS_MINGEN_TIME - Minimum U1 LFPS generation time. Written only if U1_LFPS_TIME_WR_STROBE is 1
101274  */
101275 #define USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_SHIFT)) & USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_MASK)
101276 #define USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_MASK (0x8000U)
101277 #define USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_SHIFT (15U)
101278 /*! U1_LFPS_TIME_WR_STROBE - Minimum U1 LFPS generation time write stobe. Returns '0' when read
101279  */
101280 #define USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_SHIFT)) & USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_MASK)
101281 /*! @} */
101282 
101283 /*! @name XECP_CDNS_DEBUG_BUS_CAP - xHCI Debug Bus Capability */
101284 /*! @{ */
101285 #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_MASK (0xFFU)
101286 #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_SHIFT (0U)
101287 /*! XHCI_DEBUG_BUS_CAP_ID - Capability ID, RO. This field identifies the extended capability. For xHCI Debug Bus its' value is 196
101288  */
101289 #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_MASK)
101290 #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_MASK (0xFF00U)
101291 #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_SHIFT (8U)
101292 /*! XHCI_DEBUG_BUS_DW - Next Capability Pointer, RO. This field indicates the location of the next
101293  *    capability with respect to the effective address of this capability
101294  */
101295 #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_MASK)
101296 #define USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_MASK (0x80000000U)
101297 #define USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_SHIFT (31U)
101298 /*! cpu_debug_en - Debug Bus Enable, RW. When 0, allows the xhci_debug_sel primary input to control
101299  *    selection of Debug Bus sources. When 1, allows the cpu_debug_bus_sel field in the
101300  *    XECP_CDNS_DEBUG_BUS_CTRL register to control selection of Debug Bus sources. Default value after reset is
101301  *    '0'
101302  */
101303 #define USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_MASK)
101304 /*! @} */
101305 
101306 /*! @name XECP_CDNS_DEBUG_BUS_CTRL - xHCI Debug Bus Control */
101307 /*! @{ */
101308 #define USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_MASK (0x1FU)
101309 #define USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_SHIFT (0U)
101310 /*! cpu_debug_bus_sel - Debug Bus Select, RW. Value of this field determines a source of Debug Bus. Default value after reset is 0
101311  */
101312 #define USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_MASK)
101313 /*! @} */
101314 
101315 /*! @name XECP_CDNS_DEBUG_BUS_STATUS - xHCI Debug Bus Status */
101316 /*! @{ */
101317 #define USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_MASK (0xFFFFFFFFU)
101318 #define USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_SHIFT (0U)
101319 /*! xhci_debug_bus - Debug Bus, RO. Debug Bus current value. Note for multi-bit probes, this
101320  *    register is only suitable for analysing a static value due to simplified clock domain synchronisation
101321  */
101322 #define USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_MASK)
101323 /*! @} */
101324 
101325 /*! @name XECP_PM_CAP - Extended Power Management capability */
101326 /*! @{ */
101327 #define USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_MASK     (0xFFU)
101328 #define USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_SHIFT    (0U)
101329 /*! XHCI_PM_CAP_ID - XHCI_PM_CAP_ID. Power Management capability ID
101330  */
101331 #define USB3_XECP_PM_CAP_XHCI_PM_CAP_ID(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_SHIFT)) & USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_MASK)
101332 #define USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_MASK (0xFF00U)
101333 #define USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_SHIFT (8U)
101334 /*! XHCI_PM_CAPABILITY_DW - XHCI_PM_CAPABILITY_DW. Next Item Pointer. This field provides an offset
101335  *    pointing to the location of next item in the functions capability list
101336  */
101337 #define USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_SHIFT)) & USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_MASK)
101338 #define USB3_XECP_PM_CAP_Version_MASK            (0x70000U)
101339 #define USB3_XECP_PM_CAP_Version_SHIFT           (16U)
101340 /*! Version - Power Management Capabilities: Version. Default = '011'. A value of '011' indicates
101341  *    that this function complies with revision 1.2 of the PCI Power Management Interface Specification
101342  */
101343 #define USB3_XECP_PM_CAP_Version(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_Version_SHIFT)) & USB3_XECP_PM_CAP_Version_MASK)
101344 #define USB3_XECP_PM_CAP_PME_clock_MASK          (0x80000U)
101345 #define USB3_XECP_PM_CAP_PME_clock_SHIFT         (19U)
101346 /*! PME_clock - Power Management Capabilities: PME Clock. Default = '0'. When this bit is a '1', it
101347  *    indicates that the function relies on the presence of the PCI clock for PME# operation. When
101348  *    this bit is a '0', it indicates that no PCI clock is required for the function to generate
101349  *    PME#. Functions that do not support PME# generation in any state must return '0' for this field
101350  */
101351 #define USB3_XECP_PM_CAP_PME_clock(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_PME_clock_SHIFT)) & USB3_XECP_PM_CAP_PME_clock_MASK)
101352 #define USB3_XECP_PM_CAP_reserved_MASK           (0x100000U)
101353 #define USB3_XECP_PM_CAP_reserved_SHIFT          (20U)
101354 /*! reserved - reserved
101355  */
101356 #define USB3_XECP_PM_CAP_reserved(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_reserved_SHIFT)) & USB3_XECP_PM_CAP_reserved_MASK)
101357 #define USB3_XECP_PM_CAP_DSI_MASK                (0x200000U)
101358 #define USB3_XECP_PM_CAP_DSI_SHIFT               (21U)
101359 /*! DSI - Power Management Capabilities: DSI. Default = device specific. The Device Specific
101360  *    Initialization bit indicates whether special initialization of this function is required (beyond the
101361  *    standard PCI configuration header) before the generic class device driver is able to use it.
101362  *    Note that this bit is not used by some operating systems. Microsoft Windows and Windows NT, for
101363  *    instance, do not use this bit to determine whether to use D3. Instead, they use the drivers
101364  *    capabilities to determine this. A '1' indicates that the function requires a device specific
101365  *    initialization sequence following transition to the D0 uninitialized state. For more information
101366  *    refer to Section 8.3. of PCI bus Power Management specification
101367  */
101368 #define USB3_XECP_PM_CAP_DSI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_DSI_SHIFT)) & USB3_XECP_PM_CAP_DSI_MASK)
101369 #define USB3_XECP_PM_CAP_AUX_CURRENT_MASK        (0x1C00000U)
101370 #define USB3_XECP_PM_CAP_AUX_CURRENT_SHIFT       (22U)
101371 /*! AUX_CURRENT - Power Management Capabilities: Aux_Current. Default = device specific. This 3 bit
101372  *    field reports the 3.3Vaux auxiliary current requirements for the PCI function. If the Data
101373  *    Register field of XECP_PM_PMCSR has been implemented by this function: - reads of this field must
101374  *    return a value of '000', - the Data Register takes precedence over this field for 3.3Vaux
101375  *    current requirement reporting. If PME# generation from D3cold is not supported by the function
101376  *    (XECP_PM_CAP[15]='0'), this field must return a value of '000' when read. For functions that
101377  *    support PME# from D3cold, and do not implement the Data Register, the following bit encoding for
101378  *    maximum current required apply : '111': 375 mA, '110': 320 mA, '101': 270 mA, '100': 220 mA,
101379  *    '011': 160 mA, '010': 100 mA, '001': 55 mA, '000': 0 (self powered)
101380  */
101381 #define USB3_XECP_PM_CAP_AUX_CURRENT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_AUX_CURRENT_SHIFT)) & USB3_XECP_PM_CAP_AUX_CURRENT_MASK)
101382 #define USB3_XECP_PM_CAP_D1_Support_MASK         (0x2000000U)
101383 #define USB3_XECP_PM_CAP_D1_Support_SHIFT        (25U)
101384 /*! D1_Support - Power Management Capabilities: D1_Support. Default = device specific. If this bit
101385  *    is a '1', this function supports the D1 Power Management State. Functions that do not support
101386  *    D1 must always return a value of '0' for this bit
101387  */
101388 #define USB3_XECP_PM_CAP_D1_Support(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_D1_Support_SHIFT)) & USB3_XECP_PM_CAP_D1_Support_MASK)
101389 #define USB3_XECP_PM_CAP_D2_Support_MASK         (0x4000000U)
101390 #define USB3_XECP_PM_CAP_D2_Support_SHIFT        (26U)
101391 /*! D2_Support - Power Management Capabilities: D2_Support. Default = device specific. If this bit
101392  *    is a '1', this function supports the D2 Power Management State. Functions that do not support
101393  *    D2 must always return a value of '0' for this bit
101394  */
101395 #define USB3_XECP_PM_CAP_D2_Support(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_D2_Support_SHIFT)) & USB3_XECP_PM_CAP_D2_Support_MASK)
101396 #define USB3_XECP_PM_CAP_PME_Support_MASK        (0xF8000000U)
101397 #define USB3_XECP_PM_CAP_PME_Support_SHIFT       (27U)
101398 /*! PME_Support - Power Management Capabilities: PME_Support. Default = device specific. This 5-bit
101399  *    field indicates the power states in which the function may assert PME#. A value of '0' for any
101400  *    bit indicates that the function is not capable of asserting the PME# signal while in that
101401  *    power state. Encodings: bit 0 set: X XXX1b - PME# can be asserted from D0, bit 1 set: X XX1Xb -
101402  *    PME# can be asserted from D1, bit 2 set: X X1XXb - PME# can be asserted from D2, bit 3 set: X
101403  *    1XXXb - PME# can be asserted from D3hot, bit 4 set: 1 XXXXb - PME# can be asserted from D3cold
101404  */
101405 #define USB3_XECP_PM_CAP_PME_Support(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_PME_Support_SHIFT)) & USB3_XECP_PM_CAP_PME_Support_MASK)
101406 /*! @} */
101407 
101408 /*! @name XECP_PM_PMCSR - Extended Power Management Control/Status */
101409 /*! @{ */
101410 #define USB3_XECP_PM_PMCSR_PowerState_MASK       (0x3U)
101411 #define USB3_XECP_PM_PMCSR_PowerState_SHIFT      (0U)
101412 /*! PowerState - Power Management Control/Status Register: PowerState. Default = zero. This 2-bit
101413  *    field is used both to determine the current power state of a function and to set the function
101414  *    into a new power state. Possible values: '00': D0, '01': D1, '10': D2, '11': D3hot. If software
101415  *    attempts to write an unsupported, optional state to this field, the write operation must
101416  *    complete normally on the bus; however, the data is discarded and no state change occurs
101417  */
101418 #define USB3_XECP_PM_PMCSR_PowerState(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_PowerState_SHIFT)) & USB3_XECP_PM_PMCSR_PowerState_MASK)
101419 #define USB3_XECP_PM_PMCSR_reserved1_MASK        (0x4U)
101420 #define USB3_XECP_PM_PMCSR_reserved1_SHIFT       (2U)
101421 /*! reserved1 - Power Management Control/Status Register: reserved
101422  */
101423 #define USB3_XECP_PM_PMCSR_reserved1(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_reserved1_SHIFT)) & USB3_XECP_PM_PMCSR_reserved1_MASK)
101424 #define USB3_XECP_PM_PMCSR_No_Soft_Reset_MASK    (0x8U)
101425 #define USB3_XECP_PM_PMCSR_No_Soft_Reset_SHIFT   (3U)
101426 /*! No_Soft_Reset - Power Management Control/Status Register: No_Soft_Reset. Default = device
101427  *    specific. When set to '1', this bit indicates that devices transitioning from D3hot to D0 because of
101428  *    PowerState commands do not perform an internal reset. Configuration Context is preserved.
101429  *    Upon transition from the D3hot to the D0 Initialized state, no additional operating system
101430  *    intervention is required to preserve Configuration Context beyond writing the PowerState bits. When
101431  *    cleared to '0', devices do perform an internal reset upon transitioning from D3hot to D0 via
101432  *    software control of the PowerState bits. Configuration Context is lost when performing the soft
101433  *    reset. Upon transition from the D3hot to the D0 state, full reinitialization sequence is
101434  *    needed to return the device to D0 Initialized. Regardless of this bit, devices that transition
101435  *    from D3hot to D0 by a system or bus segment reset will return to the device state D0
101436  *    Uninitialized with only PME context preserved if PME is supported and enabled
101437  */
101438 #define USB3_XECP_PM_PMCSR_No_Soft_Reset(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_No_Soft_Reset_SHIFT)) & USB3_XECP_PM_PMCSR_No_Soft_Reset_MASK)
101439 #define USB3_XECP_PM_PMCSR_reserved2_MASK        (0xF0U)
101440 #define USB3_XECP_PM_PMCSR_reserved2_SHIFT       (4U)
101441 /*! reserved2 - Power Management Control/Status Register: reserved
101442  */
101443 #define USB3_XECP_PM_PMCSR_reserved2(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_reserved2_SHIFT)) & USB3_XECP_PM_PMCSR_reserved2_MASK)
101444 #define USB3_XECP_PM_PMCSR_PME_En_MASK           (0x100U)
101445 #define USB3_XECP_PM_PMCSR_PME_En_SHIFT          (8U)
101446 /*! PME_En - Power Management Control/Status Register: PME_En. A '1' in this field enables the
101447  *    function to assert PME#. When '0', PME# assertion is disabled. This bit defaults to '0' if the
101448  *    function does not support PME# generation from D3cold. If the function supports PME# from D3cold,
101449  *    then this bit is sticky and must be explicitly cleared by the operating system each time it is
101450  *    initially loaded. Functions that do not support PME# generation from any D-state (i.e.,
101451  *    XECP_PM_CAP[15:11] = '00000'), may hardwire this bit to be read-only always returning a '0' when
101452  *    read by system software
101453  */
101454 #define USB3_XECP_PM_PMCSR_PME_En(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_PME_En_SHIFT)) & USB3_XECP_PM_PMCSR_PME_En_MASK)
101455 #define USB3_XECP_PM_PMCSR_data_select_MASK      (0x1E00U)
101456 #define USB3_XECP_PM_PMCSR_data_select_SHIFT     (9U)
101457 /*! data_select - Power Management Control/Status Register: Data_Select. Default = zero. This 4-bit
101458  *    field is used to select, which data is to be reported through the Data register and Data_Scale
101459  *    fields of XECP_PM_PMCSR register. This field is a required component of the Data register and
101460  *    must be implemented if the Data register is implemented. If the Data register field of
101461  *    XECP_PM_PMCSR is not implemented, this field should be read only and return zero when read. Refer to
101462  *    Section 3.2.6 of PCI bus Power Management for more details
101463  */
101464 #define USB3_XECP_PM_PMCSR_data_select(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_data_select_SHIFT)) & USB3_XECP_PM_PMCSR_data_select_MASK)
101465 #define USB3_XECP_PM_PMCSR_data_scale_MASK       (0x6000U)
101466 #define USB3_XECP_PM_PMCSR_data_scale_SHIFT      (13U)
101467 /*! data_scale - Power Management Control/Status Register: Data_Scale. Default = device specific.
101468  *    This 2-bit read-only field indicates the scaling factor to be used when interpreting the value
101469  *    of the Data register field of XECP_PM_PMCSR register. The value and meaning of this field will
101470  *    vary depending on which data value has been selected by the Data_Select field of this
101471  *    register. This field is a required component of the Data register and must be implemented if the Data
101472  *    register is implemented. If the Data register has not been implemented, this field must return
101473  *    zero when read. Refer to Section 3.2.6 of PCI bus Power Management specification for more
101474  *    details
101475  */
101476 #define USB3_XECP_PM_PMCSR_data_scale(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_data_scale_SHIFT)) & USB3_XECP_PM_PMCSR_data_scale_MASK)
101477 #define USB3_XECP_PM_PMCSR_pme_status_MASK       (0x8000U)
101478 #define USB3_XECP_PM_PMCSR_pme_status_SHIFT      (15U)
101479 /*! pme_status - Power Management Control/Status Register: PME_Status. This bit is set when the
101480  *    function would normally assert the PME# signal independent of the state of the PME_En bit. Writing
101481  *    a '1' to this bit will clear it and cause the function to stop asserting a PME# (if enabled).
101482  *    Writing a '0' has no effect. This bit defaults to '0' if the function does not support PME#
101483  *    generation from D3cold. If the function supports PME# from D3cold, then this bit is sticky and
101484  *    must be explicitly cleared by the operating system each time the operating system is initially
101485  *    loaded
101486  */
101487 #define USB3_XECP_PM_PMCSR_pme_status(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_pme_status_SHIFT)) & USB3_XECP_PM_PMCSR_pme_status_MASK)
101488 #define USB3_XECP_PM_PMCSR_reserved3_MASK        (0x3F0000U)
101489 #define USB3_XECP_PM_PMCSR_reserved3_SHIFT       (16U)
101490 /*! reserved3 - PMCSR Bridge Support Extensions: reserved
101491  */
101492 #define USB3_XECP_PM_PMCSR_reserved3(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_reserved3_SHIFT)) & USB3_XECP_PM_PMCSR_reserved3_MASK)
101493 #define USB3_XECP_PM_PMCSR_B2_B3_MASK            (0x400000U)
101494 #define USB3_XECP_PM_PMCSR_B2_B3_SHIFT           (22U)
101495 /*! B2_B3 - PMCSR Bridge Support Extensions: B2_B3# (B2/B3 support for D3hot). External strap or
101496  *    internally hardwired. The state of this bit determines the action that is to occur as a direct
101497  *    result of programming the function to D3hot. A '1' indicates that when the bridge function is
101498  *    programmed to D3hot, its secondary buss PCI clock will be stopped (B2). A '0' indicates that
101499  *    when the bridge function is programmed to D3hot, its secondary bus will have its power removed
101500  *    (B3). This bit is only meaningful if bit BPCC_En of XECP_PM_PMCSR register is a '1'. Refer to
101501  *    Section 4.7.1 of PCI bus Power Management specification for details
101502  */
101503 #define USB3_XECP_PM_PMCSR_B2_B3(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_B2_B3_SHIFT)) & USB3_XECP_PM_PMCSR_B2_B3_MASK)
101504 #define USB3_XECP_PM_PMCSR_BPCC_EN_MASK          (0x800000U)
101505 #define USB3_XECP_PM_PMCSR_BPCC_EN_SHIFT         (23U)
101506 /*! BPCC_EN - PMCSR Bridge Support Extensions: BPCC_En (Bus Power/Clock Control Enable). External
101507  *    strap or internally hardwired. A '1' indicates that the bus power/clock control mechanism as
101508  *    defined in Section 4.7.1 PCI bus Power Management specification is enabled. A '0' indicates that
101509  *    the bus power/clock control policies defined in Section 4.7.1 PCI bus Power Management
101510  *    specification have been disabled. When the Bus Power/Clock Control mechanism is disabled, the bridges
101511  *    Power Management Control/Status Register PowerState field cannot be used by the system
101512  *    software to control the power or clock of the bridges secondary bus
101513  */
101514 #define USB3_XECP_PM_PMCSR_BPCC_EN(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_BPCC_EN_SHIFT)) & USB3_XECP_PM_PMCSR_BPCC_EN_MASK)
101515 #define USB3_XECP_PM_PMCSR_data_register_MASK    (0xFF000000U)
101516 #define USB3_XECP_PM_PMCSR_data_register_SHIFT   (24U)
101517 /*! data_register - Data register. This register is used to report the state dependent data
101518  *    requested by the Data_Select field of XECP_PM_PMCSR register. The value of Data register is scaled by
101519  *    the value reported by the Data_Scale field of XECP_PM_PMCSR
101520  */
101521 #define USB3_XECP_PM_PMCSR_data_register(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_data_register_SHIFT)) & USB3_XECP_PM_PMCSR_data_register_MASK)
101522 /*! @} */
101523 
101524 /*! @name XECP_MSI_CAP - MSI configuration */
101525 /*! @{ */
101526 #define USB3_XECP_MSI_CAP_MSI_ID_MASK            (0xFFU)
101527 #define USB3_XECP_MSI_CAP_MSI_ID_SHIFT           (0U)
101528 /*! MSI_ID - Capability ID for Message Signaled Interrupts. The value of 05h in this field
101529  *    identifies the function as being MSI capable
101530  */
101531 #define USB3_XECP_MSI_CAP_MSI_ID(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_ID_SHIFT)) & USB3_XECP_MSI_CAP_MSI_ID_MASK)
101532 #define USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_MASK (0xFF00U)
101533 #define USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_SHIFT (8U)
101534 /*! XECP_MSI_CAP_OFFSET - Pointer to the next item in the capabilities list. A non-zero value in
101535  *    this field indicates a relative offset, in 32-bit words, from this 32-bit word to the beginning
101536  *    of the next extended capability
101537  */
101538 #define USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_SHIFT)) & USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_MASK)
101539 #define USB3_XECP_MSI_CAP_MSI_en_MASK            (0x10000U)
101540 #define USB3_XECP_MSI_CAP_MSI_en_SHIFT           (16U)
101541 /*! MSI_en - MSI Message Control: MSI enable. System configuration software sets this bit to enable
101542  *    MSI. A device driver is prohibited from writing this bit to mask a functions service request.
101543  *    If '0', the function is prohibited from using MSI to request service. This bits state after
101544  *    reset is '0' (MSI is disabled)
101545  */
101546 #define USB3_XECP_MSI_CAP_MSI_en(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_en_SHIFT)) & USB3_XECP_MSI_CAP_MSI_en_MASK)
101547 #define USB3_XECP_MSI_CAP_MSI_MMC_MASK           (0xE0000U)
101548 #define USB3_XECP_MSI_CAP_MSI_MMC_SHIFT          (17U)
101549 /*! MSI_MMC - MSI Message Control: Multiple Message Capable. System software reads this field to
101550  *    determine the number of requested vectors. The number of requested vectors must be aligned to a
101551  *    power of two (if a function requires three vectors, it requests four by initializing this field
101552  *    to '010'). The encoding is defined as: '000': 1, '001': 2, '010': 4, '011': 8, '100': 16,
101553  *    '101': 32, '110': Reserved, '111': Reserved. This field is read only.
101554  */
101555 #define USB3_XECP_MSI_CAP_MSI_MMC(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_MMC_SHIFT)) & USB3_XECP_MSI_CAP_MSI_MMC_MASK)
101556 #define USB3_XECP_MSI_CAP_MSI_MME_MASK           (0x700000U)
101557 #define USB3_XECP_MSI_CAP_MSI_MME_SHIFT          (20U)
101558 /*! MSI_MME - MSI Message Control: Multiple Message Enable. Software writes to this field to
101559  *    indicate the number of allocated vectors (equal to or less than the number of requested vectors). The
101560  *    number of allocated vectors is aligned to a power of two. If a function requests four vectors
101561  *    (indicated by a Multiple Message Capable encoding of 010), system software can allocate
101562  *    either four, two, or one vector by writing a '010', '001', or '000' to this field, respectively.
101563  *    When MSI is enabled, a function will be allocated at least one vector. The encoding is defined
101564  *    as: '000': 1, '001': 2, '010': 4, '011': 8, '100': 16, '101': 32, '110': Reserved, '111':
101565  *    Reserved. This fields state after reset is '000'
101566  */
101567 #define USB3_XECP_MSI_CAP_MSI_MME(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_MME_SHIFT)) & USB3_XECP_MSI_CAP_MSI_MME_MASK)
101568 #define USB3_XECP_MSI_CAP_AC64_MASK              (0x800000U)
101569 #define USB3_XECP_MSI_CAP_AC64_SHIFT             (23U)
101570 /*! AC64 - MSI Message Control: 64 bit address capable. If '1', the function is capable of
101571  *    generating sending a 64-bit message address. If '0', the function is not capable of generating sending
101572  *    a 64-bit message address. This bit is read only
101573  */
101574 #define USB3_XECP_MSI_CAP_AC64(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_AC64_SHIFT)) & USB3_XECP_MSI_CAP_AC64_MASK)
101575 #define USB3_XECP_MSI_CAP_per_vector_masking_MASK (0x1000000U)
101576 #define USB3_XECP_MSI_CAP_per_vector_masking_SHIFT (24U)
101577 /*! per_vector_masking - MSI Message Control: Per-vector masking capable. If '1', the function
101578  *    supports MSI per-vector masking. If '0', the function does not support MSI per-vector masking. This
101579  *    bit is read only. Not Supported in this configuration
101580  */
101581 #define USB3_XECP_MSI_CAP_per_vector_masking(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_per_vector_masking_SHIFT)) & USB3_XECP_MSI_CAP_per_vector_masking_MASK)
101582 /*! @} */
101583 
101584 /*! @name XECP_MSI_ADDR_L - Message Lower Address */
101585 /*! @{ */
101586 #define USB3_XECP_MSI_ADDR_L_reserved_MASK       (0x3U)
101587 #define USB3_XECP_MSI_ADDR_L_reserved_SHIFT      (0U)
101588 /*! reserved - Reserved. Always returns zero on read. Write operations have no effect. Those bits
101589  *    are driven to zero during the address phase
101590  */
101591 #define USB3_XECP_MSI_ADDR_L_reserved(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_ADDR_L_reserved_SHIFT)) & USB3_XECP_MSI_ADDR_L_reserved_MASK)
101592 #define USB3_XECP_MSI_ADDR_L_MSI_addr_low_MASK   (0xFFFFFFFCU)
101593 #define USB3_XECP_MSI_ADDR_L_MSI_addr_low_SHIFT  (2U)
101594 /*! MSI_addr_low - Message Lower Address for MSI. System-specified message address. If the Message
101595  *    Enable bit of MSI Message Control (bit 16 of the XCEP_MSI_CAP register) is set, the contents of
101596  *    this register specify the DWORD-aligned address for the MSI memory write transaction. Note:
101597  *    This field should not be written unless the Message Enable bit of MSI Message Control (bit 16
101598  *    of the XCEP_MSI_CAP register) is cleared. This field is read/write
101599  */
101600 #define USB3_XECP_MSI_ADDR_L_MSI_addr_low(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_ADDR_L_MSI_addr_low_SHIFT)) & USB3_XECP_MSI_ADDR_L_MSI_addr_low_MASK)
101601 /*! @} */
101602 
101603 /*! @name XECP_MSI_ADDR_H - Message Upper Address */
101604 /*! @{ */
101605 #define USB3_XECP_MSI_ADDR_H_MSI_addr_hi_MASK    (0xFFFFFFFFU)
101606 #define USB3_XECP_MSI_ADDR_H_MSI_addr_hi_SHIFT   (0U)
101607 /*! MSI_addr_hi - Message Upper Address for MSI. System-specified message upper address. Note: This
101608  *    field should not be written unless the Message Enable bit of MSI Message Control (bit 16 of
101609  *    the XCEP_MSI_CAP register) is cleared. This field is read/write
101610  */
101611 #define USB3_XECP_MSI_ADDR_H_MSI_addr_hi(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_ADDR_H_MSI_addr_hi_SHIFT)) & USB3_XECP_MSI_ADDR_H_MSI_addr_hi_MASK)
101612 /*! @} */
101613 
101614 /*! @name XECP_MSI_DATA - Message data */
101615 /*! @{ */
101616 #define USB3_XECP_MSI_DATA_MSI_data_MASK         (0xFFFFU)
101617 #define USB3_XECP_MSI_DATA_MSI_data_SHIFT        (0U)
101618 /*! MSI_data - System-specified message data. If the Message Enable bit of MSI Message Control (bit
101619  *    16 of the XCEP_MSI_CAP register) is set, the message data is driven onto the lower word (bits
101620  *    [15:0]) of the memory write transactions data phase. Bits [31:16] are driven to zero during
101621  *    the memory write transactions data phase. C/BE[3::0]# are asserted during the data phase of the
101622  *    memory write transaction. The Multiple Message Enable field of MSI Message Control (see
101623  *    MSI_MME field of XCEP_MSI_CAP register) defines the number of low order message data bits the
101624  *    function is permitted to modify to generate its system software allocated vectors. For example, a
101625  *    Multiple Message Enable encoding of '010' indicates the function has been allocated four vectors
101626  *    and is permitted to modify message data bits 1 and 0 (a function modifies the lower message
101627  *    data bits to generate the allocated number of vectors). If the Multiple Message Enable field is
101628  *    '000', the function is not permitted to modify the message data. Note: This field should not
101629  *    be written unless the Message Enable bit of MSI Message Control (bit 16 of the XCEP_MSI_CAP
101630  *    register) is cleared. This field is read/write
101631  */
101632 #define USB3_XECP_MSI_DATA_MSI_data(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_DATA_MSI_data_SHIFT)) & USB3_XECP_MSI_DATA_MSI_data_MASK)
101633 /*! @} */
101634 
101635 /*! @name XECP_AXI_CAP - AXI Master Wrapper Extended Capability */
101636 /*! @{ */
101637 #define USB3_XECP_AXI_CAP_AXI_CAP_ID_MASK        (0xFFU)
101638 #define USB3_XECP_AXI_CAP_AXI_CAP_ID_SHIFT       (0U)
101639 /*! AXI_CAP_ID - VEND_DEF_AXI_MASTER_WRAPPER_CAP_ID, RO. Vendor defined xHCI Extended Capability:
101640  *    0xC2. This field identifies the AXI wrapper xHCI Extended capability
101641  */
101642 #define USB3_XECP_AXI_CAP_AXI_CAP_ID(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_CAP_ID_SHIFT)) & USB3_XECP_AXI_CAP_AXI_CAP_ID_MASK)
101643 #define USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_MASK (0xFF00U)
101644 #define USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_SHIFT (8U)
101645 /*! XECP_AXI_CAP_OFFSET - Next capability Offset, RO. This field points to the xHC MMIO space offset
101646  *    of the next xHCI extended capability pointer. A value of 00h indicates the end of the
101647  *    extended capability list. A non-zero value in this register indicates a relative offset, in Dwords,
101648  *    from this Dword to the beginning of the next extended capability
101649  */
101650 #define USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_SHIFT)) & USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_MASK)
101651 #define USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_MASK (0x10000U)
101652 #define USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_SHIFT (16U)
101653 /*! AXI_ADDRESS_WIDTH_64 - AXI address bus width capability, RO. '0': 32-bit address bus width, '1': 64-bit address bus width
101654  */
101655 #define USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_SHIFT)) & USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_MASK)
101656 #define USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_MASK (0x400000U)
101657 #define USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_SHIFT (22U)
101658 /*! AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS - AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS, RO. Presents
101659  *    information about AXI byte burst capability: '0': no byte bursts, '1': byte bursts enabled
101660  */
101661 #define USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_SHIFT)) & USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_MASK)
101662 #define USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_MASK   (0x800000U)
101663 #define USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_SHIFT  (23U)
101664 /*! AXI_DISABLE_OOO - Disable Out-Of-Order R channel responses (AXI_MASTER_WRAPPER_DISABLE_OOO), RO.
101665  *    This relates to number of IDs used at AXI IF. If Out-Of-Order R channel responses are not
101666  *    disabled this count may be greater than one and in such a case the R channel responses may come
101667  *    Out-Of-Order. The flag gives information about number of used AXI IDs: '0': single ID, '1':
101668  *    multiple IDs
101669  */
101670 #define USB3_XECP_AXI_CAP_AXI_DISABLE_OOO(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_SHIFT)) & USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_MASK)
101671 #define USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_MASK (0x7000000U)
101672 #define USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_SHIFT (24U)
101673 /*! AXI_DATA_BUS_SIZE - AXI_DATA_WORD_SIZE, RO. AXI data buses size capability. It uses AXI AxSIZE
101674  *    Encoding. Values of 64-bit ('011') or 128-bit ('100') are supported through compile time
101675  *    configuration
101676  */
101677 #define USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_SHIFT)) & USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_MASK)
101678 #define USB3_XECP_AXI_CAP_AXI_ERROR_MASK         (0x20000000U)
101679 #define USB3_XECP_AXI_CAP_AXI_ERROR_SHIFT        (29U)
101680 /*! AXI_ERROR - AXI ERROR, RW1C. Provides an information about AXI ERROR response on B or R channel.
101681  *    This flag is cleared by writing '1' to it. Once set it is held until cleared. The condition
101682  *    setting this register will also assert HSE. This flag may be read by software while handling
101683  *    HSE assertion to determine if the case was AXI ERROR reponse
101684  */
101685 #define USB3_XECP_AXI_CAP_AXI_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_ERROR_SHIFT)) & USB3_XECP_AXI_CAP_AXI_ERROR_MASK)
101686 #define USB3_XECP_AXI_CAP_AXI_IDLE_MASK          (0x40000000U)
101687 #define USB3_XECP_AXI_CAP_AXI_IDLE_SHIFT         (30U)
101688 /*! AXI_IDLE - AXI IDLE, RO. Information about the AXI Master wrapper state: '0': no pending action
101689  *    required by the AXI Master wrapper, '1': the AXI Master wrapper has outstanding transactions.
101690  *    Note: HCH halted bit will not be asserted if the AXI Master wrapper is not idle
101691  */
101692 #define USB3_XECP_AXI_CAP_AXI_IDLE(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_IDLE_SHIFT)) & USB3_XECP_AXI_CAP_AXI_IDLE_MASK)
101693 #define USB3_XECP_AXI_CAP_AXI_HALT_MASK          (0x80000000U)
101694 #define USB3_XECP_AXI_CAP_AXI_HALT_SHIFT         (31U)
101695 /*! AXI_HALT - AXI HALT, RW. The AXI Master wrapper's control bit. When set, the AXI Master wrapper
101696  *    will complete current CORE REQ (or IRQ) and stop acknowledging next ones. If the xHC is
101697  *    stopped the AXI Master wrapper is halted automatically. If the xHC is started the AXI Master wrapper
101698  *    is resumed automatically. Software should set this bit to stop the AXI Master issuing new AXI
101699  *    transactions. It may then use the IDLE bit to determine when all previous transactions were
101700  *    completed. Note: The AXI Master wrapper will execute halted only if xHC stopped its internal
101701  *    operation
101702  */
101703 #define USB3_XECP_AXI_CAP_AXI_HALT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_HALT_SHIFT)) & USB3_XECP_AXI_CAP_AXI_HALT_MASK)
101704 /*! @} */
101705 
101706 /*! @name XECP_AXI_CFG0 - AXI Master Wrapper Extended Capability Configuration */
101707 /*! @{ */
101708 #define USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_MASK    (0x3FU)
101709 #define USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_SHIFT   (0U)
101710 /*! AXI_MAX_WR_OT - AXI MAX_WRITE_OUTSTANDING, RO. Maximum number of Outstanding Write Transactions
101711  *    initiated by the AXI Master wrapper in AW channel. The value written to this field should be
101712  *    the Maximum number of Outstanding Write Transactions initiated by the AXI Master wrapper minus
101713  *    1, thus the Maximum number of Outstanding Write Transactions is 1 more than the programmed
101714  *    value
101715  */
101716 #define USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_MASK)
101717 #define USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_MASK     (0xFF00U)
101718 #define USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_SHIFT    (8U)
101719 /*! AXI_WR_DEPTH - AXI WRITE_BUFFER_DEPTH, RO. Number of AXI Write beats that can be buffered by the
101720  *    AXI Master wrapper. The value written to this field should be the number of AXI Write beats
101721  *    that can be buffered by the AXI Master wrapper minus 1
101722  */
101723 #define USB3_XECP_AXI_CFG0_AXI_WR_DEPTH(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_MASK)
101724 #define USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_MASK    (0x3F0000U)
101725 #define USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_SHIFT   (16U)
101726 /*! AXI_MAX_RD_OT - AXI MAX_READ_OUTSTANDING, RO. Maximum number of Outstanding Read Transactions
101727  *    initiated by the AXI Master wrapper in AR channel. The value written to this field should be the
101728  *    Maximum number of Outstanding Read Transactions initiated by the AXI Master wrapper minus 1,
101729  *    thus the Maximum number of Outstanding Read Transactions is 1 more than the programmed value
101730  */
101731 #define USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_MASK)
101732 #define USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_MASK     (0xFF000000U)
101733 #define USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_SHIFT    (24U)
101734 /*! AXI_RD_DEPTH - AXI READ_BUFFER_DEPTH, RO. Number of AXI Read beats that can be buffered by the
101735  *    AXI Master wrapper. The value written to this field should be the Number of AXI Read beats that
101736  *    can be buffered by the AXI Master wrapper minus 1
101737  */
101738 #define USB3_XECP_AXI_CFG0_AXI_RD_DEPTH(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_MASK)
101739 /*! @} */
101740 
101741 /*! @name XECP_AXI_CTRL0 - AXI Master Wrapper Extended Capability Control */
101742 /*! @{ */
101743 #define USB3_XECP_AXI_CTRL0_AXI_BMAX_MASK        (0xFU)
101744 #define USB3_XECP_AXI_CTRL0_AXI_BMAX_SHIFT       (0U)
101745 /*! AXI_BMAX - AXI BMAX, RW. The register controls maximum burst length - it is used by the AXI
101746  *    Master wrapper to determine maximum value of AxLEN. It uses AXI AxLEN encoding. Default value is
101747  *    the maximum supported one and it is implementation specific. Writing value greater than maximum
101748  *    will result in setting the register to its defaults. This register can be written only when
101749  *    the AXI Master wrapper is halted (AXI_HALT set to '1') and idle (AXI_IDLE is '1'). Note: This
101750  *    register should only be written to during the register initialisation process
101751  */
101752 #define USB3_XECP_AXI_CTRL0_AXI_BMAX(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL0_AXI_BMAX_SHIFT)) & USB3_XECP_AXI_CTRL0_AXI_BMAX_MASK)
101753 /*! @} */
101754 
101755 /*! @name XECP_AXI_CTRL1 - AXI Master Wrapper Extended Capability Control */
101756 /*! @{ */
101757 #define USB3_XECP_AXI_CTRL1_AXI_WOT_MASK         (0x3FU)
101758 #define USB3_XECP_AXI_CTRL1_AXI_WOT_SHIFT        (0U)
101759 /*! AXI_WOT - AXI WRITE_OUTSTANDING, RW. Number of outstanding write transactions that can be
101760  *    initiated by the AXI Master wrapper. Default value of this field is MAX_WRITE_OUTSTANDING-1 (see
101761  *    AXI_MAX_WR_OT field of XECP_AXI_CFG0). Writing value greater than the default will result in
101762  *    setting the register to its defaults. This register can be written only when the AXI Master
101763  *    wrapper is halted (AXI_HALT set to '1') and idle (AXI_IDLE is '1'). The value written to this field
101764  *    should be the requested number of outstanding write transactions minus 1, thus the actual
101765  *    number of possible outstanding write transactions is one more than the programmed value. Note:
101766  *    This register should only be written to during the register initialisation process
101767  */
101768 #define USB3_XECP_AXI_CTRL1_AXI_WOT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL1_AXI_WOT_SHIFT)) & USB3_XECP_AXI_CTRL1_AXI_WOT_MASK)
101769 #define USB3_XECP_AXI_CTRL1_AXI_ROT_MASK         (0x3F0000U)
101770 #define USB3_XECP_AXI_CTRL1_AXI_ROT_SHIFT        (16U)
101771 /*! AXI_ROT - AXI READ_OUTSTANDING, RW. Number of outstanding read transactions that can be
101772  *    initiated by the AXI Master wrapper. Default value of this field is MAX_READ_OUTSTANDING-1 (see
101773  *    AXI_MAX_RD_OT field of XECP_AXI_CFG0 register). Writing value greater than the default will result
101774  *    in setting the register to its defaults. This register can be written only when the AXI Master
101775  *    wrapper is halted (AXI_HALT set to '1') and idle (AXI_IDLE is '1'). The value written to this
101776  *    field should be the requested number of outstanding read transactions minus 1, thus the actual
101777  *    number of possible outstanding read transactions is one more than the programmed value. Note:
101778  *    This register should only be written to during the register initialisation process
101779  */
101780 #define USB3_XECP_AXI_CTRL1_AXI_ROT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL1_AXI_ROT_SHIFT)) & USB3_XECP_AXI_CTRL1_AXI_ROT_MASK)
101781 /*! @} */
101782 
101783 /*! @name XECP_AXI_CTRL2 - AXI Master Wrapper Extended Capability Control */
101784 /*! @{ */
101785 #define USB3_XECP_AXI_CTRL2_AXI_WTHRES_MASK      (0x1FU)
101786 #define USB3_XECP_AXI_CTRL2_AXI_WTHRES_SHIFT     (0U)
101787 /*! AXI_WTHRES - AXI Write Buffer Threshold, RW. When performing an AXI write burst this field
101788  *    specifies the minimum number of required AXI beats buffered prior to starting the burst on AXI
101789  *    W-Channel by asserting wvalid. This allows a user to balance the requirement for minimal latency
101790  *    with the requirement for low bus utilisation during bursts. Burst lengths smaller than or equal
101791  *    to this threshold will be buffered completely and then output on W-Channel. Burst lengths
101792  *    greater than this threshold will output the burst on the W-Channel such that the first AXI_WTHRES
101793  *    beats will be continuously with no drop of WVALID, beats thereafter may or may not be
101794  *    continuous depending on availability of data. Legal values are between 1 and (AXI_WDD-1). A value of
101795  *    1 means that the burst is started on W-Channel as soon as any data is available without any
101796  *    additional delay. A value of 0 is reserved and should not be used as may lead to unpredictable
101797  *    behaviour. This register can be written only when the AXI Master wrapper is halted (AXI_HALT
101798  *    set to '1') and idle (AXI_IDLE is '1'). Note: This register should only be written to during the
101799  *    register initialisation process
101800  */
101801 #define USB3_XECP_AXI_CTRL2_AXI_WTHRES(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL2_AXI_WTHRES_SHIFT)) & USB3_XECP_AXI_CTRL2_AXI_WTHRES_MASK)
101802 /*! @} */
101803 
101804 /*! @name XECP_SUPP_USB2_CAP0 - xHCI Supported Protocol Capability */
101805 /*! @{ */
101806 #define USB3_XECP_SUPP_USB2_CAP0_PID_MASK        (0xFFU)
101807 #define USB3_XECP_SUPP_USB2_CAP0_PID_SHIFT       (0U)
101808 /*! PID - Capability ID. The value identifies the capability as Supported Protocol
101809  */
101810 #define USB3_XECP_SUPP_USB2_CAP0_PID(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_PID_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_PID_MASK)
101811 #define USB3_XECP_SUPP_USB2_CAP0_NextCapID_MASK  (0xFF00U)
101812 #define USB3_XECP_SUPP_USB2_CAP0_NextCapID_SHIFT (8U)
101813 /*! NextCapID - This field indicates the location of the next capability with respect to the
101814  *    effective address of this capability. Refer to Table 142 of xHCI specification for more information
101815  *    on this field
101816  */
101817 #define USB3_XECP_SUPP_USB2_CAP0_NextCapID(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_NextCapID_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_NextCapID_MASK)
101818 #define USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_MASK  (0xFF0000U)
101819 #define USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_SHIFT (16U)
101820 /*! Minor_Rev - Minor Specification Release Number in Binary-Coded Decimal (i.e.,version x.10 is
101821  *    10h). This field identifies the minor release number component of the specification with which
101822  *    the xHC is compliant
101823  */
101824 #define USB3_XECP_SUPP_USB2_CAP0_Minor_Rev(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_MASK)
101825 #define USB3_XECP_SUPP_USB2_CAP0_Major_Rev_MASK  (0xFF000000U)
101826 #define USB3_XECP_SUPP_USB2_CAP0_Major_Rev_SHIFT (24U)
101827 /*! Major_Rev - Major Specification Release Number in Binary-Coded Decimal (i.e.,version 3.x is
101828  *    03h). This field identifies the major release number component of the specification with which the
101829  *    xHC is compliant
101830  */
101831 #define USB3_XECP_SUPP_USB2_CAP0_Major_Rev(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_Major_Rev_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_Major_Rev_MASK)
101832 /*! @} */
101833 
101834 /*! @name XECP_SUPP_USB2_CAP1 - xHCI Supported Protocol Capability */
101835 /*! @{ */
101836 #define USB3_XECP_SUPP_USB2_CAP1_USB_STRING_MASK (0xFFFFFFFFU)
101837 #define USB3_XECP_SUPP_USB2_CAP1_USB_STRING_SHIFT (0U)
101838 /*! USB_STRING - Name String, RO. This field is a mnemonic name string that references the
101839  *    specification with which the xHC is compliant. Four ASCII characters may be defined. Allowed characters
101840  *    are: alphanumeric, space, and underscore. Alpha characters are case sensitive. Refer to
101841  *    section 7.2.2 of xHCI specification for defined values
101842  */
101843 #define USB3_XECP_SUPP_USB2_CAP1_USB_STRING(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP1_USB_STRING_SHIFT)) & USB3_XECP_SUPP_USB2_CAP1_USB_STRING_MASK)
101844 /*! @} */
101845 
101846 /*! @name XECP_SUPP_USB2_CAP2 - xHCI Supported Protocol Capability */
101847 /*! @{ */
101848 #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_MASK (0xFFU)
101849 #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_SHIFT (0U)
101850 /*! Compatible_Port_Offset - This field specifies the starting Port Number of Root Hub Ports that
101851  *    support this protocol. Valid values are 1 to MaxPorts
101852  */
101853 #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_MASK)
101854 #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_MASK (0xFF00U)
101855 #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_SHIFT (8U)
101856 /*! Compatible_Port_Count - This field identifies the number of consecutive Root Hub Ports (starting
101857  *    at the Compatible Port Offset) that support this protocol. Valid values are 1 to MaxPorts
101858  */
101859 #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_MASK)
101860 #define USB3_XECP_SUPP_USB2_CAP2_L1C_MASK        (0x10000U)
101861 #define USB3_XECP_SUPP_USB2_CAP2_L1C_SHIFT       (16U)
101862 /*! L1C - If '1'LPM is supported (mandatory in xHCI1_00). In xHCI specification this field is
101863  *    reserved RsvdP, see section 7.2.2.1.3
101864  */
101865 #define USB3_XECP_SUPP_USB2_CAP2_L1C(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_L1C_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_L1C_MASK)
101866 #define USB3_XECP_SUPP_USB2_CAP2_HSO_MASK        (0x20000U)
101867 #define USB3_XECP_SUPP_USB2_CAP2_HSO_SHIFT       (17U)
101868 /*! HSO - High-speed Only. Default = Implementation dependent. If this bit is cleared to '0', the
101869  *    USB2 ports described by this capability are Low-, Full-, and High-speed capable. If this bit is
101870  *    set to '1', the USB2 ports described by this capability are High-speed only, e.g. the ports do
101871  *    not support Low- or Full-speed operation. High-speed only implementations may introduce a
101872  *    Tier mismatch, refer to section 4.24.2 of xHCI specification for more information
101873  */
101874 #define USB3_XECP_SUPP_USB2_CAP2_HSO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_HSO_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_HSO_MASK)
101875 #define USB3_XECP_SUPP_USB2_CAP2_IHI_MASK        (0x40000U)
101876 #define USB3_XECP_SUPP_USB2_CAP2_IHI_SHIFT       (18U)
101877 /*! IHI - Integrated Hub Implemented. Default = Implementation dependent. If this bit is cleared to
101878  *    '0', the Root Hub to External xHC port mapping adheres to the default mapping described in
101879  *    section 4.24.2.1 of xHCI specification. If this bit is set to '1', the Root Hub to External xHC
101880  *    port mapping does not adhere to the default mapping described in section 4.24.2.1 of xHCI
101881  *    specification, and an ACPI or other mechanism is required to define the mapping
101882  */
101883 #define USB3_XECP_SUPP_USB2_CAP2_IHI(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_IHI_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_IHI_MASK)
101884 #define USB3_XECP_SUPP_USB2_CAP2_HLC_MASK        (0x80000U)
101885 #define USB3_XECP_SUPP_USB2_CAP2_HLC_SHIFT       (19U)
101886 /*! HLC - Hardware LPM Capability. Default = Implementation dependent. If this bit is set to '1',
101887  *    the ports described by this xHCI Supported Protocol Capability support hardware controlled USB2
101888  *    Link Power Management. Refer to section 4.23.5.1.1.1 of xHCI specification
101889  */
101890 #define USB3_XECP_SUPP_USB2_CAP2_HLC(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_HLC_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_HLC_MASK)
101891 #define USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_MASK   (0x100000U)
101892 #define USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_SHIFT  (20U)
101893 /*! HLC_BESL - HLC_BESL. In xHCI 1.0 specification this field is reserved RsvdP, see section
101894  *    7.2.2.1.3. The field is described in xHCI 1.1 specification: BESL LPM Capability (BLC), RO. Default =
101895  *    Implementation dependent. If this bit is set to '1', the ports described by this xHCI
101896  *    Supported Protocol Capability shall apply BESL timing to BESL and BESLD fields of the PORTPMSC and
101897  *    PORTHLPMC registers, as defined in Table 13. If this bit is cleared to '0', the ports described
101898  *    by this xHCI Supported Protocol Capability shall apply HIRD timing to BESL and BESLD fields of
101899  *    the PORTPMSC and PORTHLPMC registers, as defined in Table 13. Refer to section 4.23.5.1.1.1
101900  *    for more information. Note the BESL LMP Capability support (i.e. HLE = 1 and BLC = 1) shall be
101901  *    mandatory for all xHCI 1.1 compliant xHCs
101902  */
101903 #define USB3_XECP_SUPP_USB2_CAP2_HLC_BESL(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_MASK)
101904 #define USB3_XECP_SUPP_USB2_CAP2_PSIC_MASK       (0xF0000000U)
101905 #define USB3_XECP_SUPP_USB2_CAP2_PSIC_SHIFT      (28U)
101906 /*! PSIC - Protocol Speed ID Count: 3, USB 2.0 Speed (High, Full, Low). This field indicates the
101907  *    number of Protocol Speed ID (PSI) Dwords that the xHCI Supported Protocol Capability data
101908  *    structure contains. If this field is non-zero, then all speeds supported by the protocol shall be
101909  *    defined using PSI Dwords, i.e. no implied Speed ID mappings apply
101910  */
101911 #define USB3_XECP_SUPP_USB2_CAP2_PSIC(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_PSIC_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_PSIC_MASK)
101912 /*! @} */
101913 
101914 /*! @name XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE - Protocol Slot Type */
101915 /*! @{ */
101916 #define USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_MASK (0x1FU)
101917 #define USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_SHIFT (0U)
101918 /*! PST - This field specifies the Protocol Slot Type value, which may be specified when allocating
101919  *    Device Slots that support this protocol. Valid values are 0 to 31. Refer to sections 4.6.3 and
101920  *    7.2.2.1.4 of xHCI specification. The value of the Protocol Slot Type field declared by a xHCI
101921  *    Supported Protocol Capability structure is unique to an xHC implementation. Software shall
101922  *    not assume a fixed mapping of the Protocol Slot Type value to a specific type of Supported
101923  *    Protocol. Note that for compatibility reasons, the Protocol Slot Type value of 0 is the exception
101924  *    to this rule and reserved for the USB Protocol Device Slot type
101925  */
101926 #define USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_SHIFT)) & USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_MASK)
101927 /*! @} */
101928 
101929 /*! @name XECP_PSI_FULL_SPEED - Protocol Speed ID */
101930 /*! @{ */
101931 #define USB3_XECP_PSI_FULL_SPEED_PSIV_MASK       (0xFU)
101932 #define USB3_XECP_PSI_FULL_SPEED_PSIV_SHIFT      (0U)
101933 /*! PSIV - Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by
101934  *    this PSI Dword, then the value of this field shall be reported in the Port Speed field of
101935  *    PORTSC register (5.4.8 of xHCI specification) of a compatible port. Note, the PSIV value of 0 is
101936  *    reserved and shall not be defined by a PSI
101937  */
101938 #define USB3_XECP_PSI_FULL_SPEED_PSIV(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PSIV_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PSIV_MASK)
101939 #define USB3_XECP_PSI_FULL_SPEED_PSIE_MASK       (0x30U)
101940 #define USB3_XECP_PSI_FULL_SPEED_PSIE_SHIFT      (4U)
101941 /*! PSIE - Protocol Speed ID Exponent. This field defines the base 10 exponent times 3, that shall
101942  *    be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented
101943  *    by this PSI Dword. PSIE Values and corresponding bit rates: 0: Bits per second 1: Kb/s 2: Mb/s
101944  *    3: Gb/s
101945  */
101946 #define USB3_XECP_PSI_FULL_SPEED_PSIE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PSIE_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PSIE_MASK)
101947 #define USB3_XECP_PSI_FULL_SPEED_PLT_MASK        (0xC0U)
101948 #define USB3_XECP_PSI_FULL_SPEED_PLT_SHIFT       (6U)
101949 /*! PLT - PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric
101950  *    bit rate, and if asymmetric, then this field also indicates if this Dword defines the receive or
101951  *    transmit bit rate. Note that the Asymmetric PSI Dwords shall be paired, i.e. an Rx
101952  *    immediately followed by a Tx, and both Dwords shall define the same value for the PSIV. PLT Values and
101953  *    corresponding bit rate: 0: Symmetric (Single PSI Dword) 1: Reserved 2: Asymmetric Rx (Paired
101954  *    with Asymmetric Tx PSI Dword) 3: Asymmetric Tx (Immediately follows Rx Asymmetric PSI Dword)
101955  */
101956 #define USB3_XECP_PSI_FULL_SPEED_PLT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PLT_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PLT_MASK)
101957 #define USB3_XECP_PSI_FULL_SPEED_PFD_MASK        (0x100U)
101958 #define USB3_XECP_PSI_FULL_SPEED_PFD_SHIFT       (8U)
101959 /*! PFD - PSI Full-duplex. If this bit is '1' the link is full-duplex, and if '0' the link is half-duplex
101960  */
101961 #define USB3_XECP_PSI_FULL_SPEED_PFD(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PFD_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PFD_MASK)
101962 #define USB3_XECP_PSI_FULL_SPEED_PSIM_MASK       (0xFFFF0000U)
101963 #define USB3_XECP_PSI_FULL_SPEED_PSIM_SHIFT      (16U)
101964 /*! PSIM - Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the
101965  *    PSIE when calculating the maximum bit rate represented by this PSI Dword
101966  */
101967 #define USB3_XECP_PSI_FULL_SPEED_PSIM(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PSIM_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PSIM_MASK)
101968 /*! @} */
101969 
101970 /*! @name XECP_PSI_LOW_SPEED - Protocol Speed ID */
101971 /*! @{ */
101972 #define USB3_XECP_PSI_LOW_SPEED_PSIV_MASK        (0xFU)
101973 #define USB3_XECP_PSI_LOW_SPEED_PSIV_SHIFT       (0U)
101974 /*! PSIV - Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by
101975  *    this PSI Dword, then the value of this field shall be reported in the Port Speed field of
101976  *    PORTSC register (5.4.8 of xHCI specification) of a compatible port. Note, the PSIV value of 0 is
101977  *    reserved and shall not be defined by a PSI
101978  */
101979 #define USB3_XECP_PSI_LOW_SPEED_PSIV(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PSIV_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PSIV_MASK)
101980 #define USB3_XECP_PSI_LOW_SPEED_PSIE_MASK        (0x30U)
101981 #define USB3_XECP_PSI_LOW_SPEED_PSIE_SHIFT       (4U)
101982 /*! PSIE - Protocol Speed ID Exponent. This field defines the base 10 exponent times 3, that shall
101983  *    be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented
101984  *    by this PSI Dword. PSIE Values and corresponding bit rates: 0: Bits per second 1: Kb/s 2: Mb/s
101985  *    3: Gb/s
101986  */
101987 #define USB3_XECP_PSI_LOW_SPEED_PSIE(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PSIE_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PSIE_MASK)
101988 #define USB3_XECP_PSI_LOW_SPEED_PLT_MASK         (0xC0U)
101989 #define USB3_XECP_PSI_LOW_SPEED_PLT_SHIFT        (6U)
101990 /*! PLT - PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric
101991  *    bit rate, and if asymmetric, then this field also indicates if this Dword defines the receive or
101992  *    transmit bit rate. Note that the Asymmetric PSI Dwords shall be paired, i.e. an Rx
101993  *    immediately followed by a Tx, and both Dwords shall define the same value for the PSIV. PLT Values and
101994  *    corresponding bit rate: 0: Symmetric Single (PSI Dword) 1: Reserved 2: Asymmetric Rx (Paired
101995  *    with Asymmetric Tx PSI Dword) 3: Asymmetric Tx (Immediately follows Rx Asymmetric PSI Dword)
101996  */
101997 #define USB3_XECP_PSI_LOW_SPEED_PLT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PLT_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PLT_MASK)
101998 #define USB3_XECP_PSI_LOW_SPEED_PFD_MASK         (0x100U)
101999 #define USB3_XECP_PSI_LOW_SPEED_PFD_SHIFT        (8U)
102000 /*! PFD - PSI Full-duplex. If this bit is '1' the link is full-duplex, and if '0' the link is half-duplex
102001  */
102002 #define USB3_XECP_PSI_LOW_SPEED_PFD(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PFD_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PFD_MASK)
102003 #define USB3_XECP_PSI_LOW_SPEED_PSIM_MASK        (0xFFFF0000U)
102004 #define USB3_XECP_PSI_LOW_SPEED_PSIM_SHIFT       (16U)
102005 /*! PSIM - Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the
102006  *    PSIE when calculating the maximum bit rate represented by this PSI Dword
102007  */
102008 #define USB3_XECP_PSI_LOW_SPEED_PSIM(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PSIM_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PSIM_MASK)
102009 /*! @} */
102010 
102011 /*! @name XECP_PSI_HIGH_SPEED - Protocol Speed ID */
102012 /*! @{ */
102013 #define USB3_XECP_PSI_HIGH_SPEED_PSIV_MASK       (0xFU)
102014 #define USB3_XECP_PSI_HIGH_SPEED_PSIV_SHIFT      (0U)
102015 /*! PSIV - Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by
102016  *    this PSI Dword, then the value of this field shall be reported in the Port Speed field of
102017  *    PORTSC register (5.4.8 of xHCI specification) of a compatible port. Note, the PSIV value of 0 is
102018  *    reserved and shall not be defined by a PSI
102019  */
102020 #define USB3_XECP_PSI_HIGH_SPEED_PSIV(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PSIV_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PSIV_MASK)
102021 #define USB3_XECP_PSI_HIGH_SPEED_PSIE_MASK       (0x30U)
102022 #define USB3_XECP_PSI_HIGH_SPEED_PSIE_SHIFT      (4U)
102023 /*! PSIE - Protocol Speed ID Exponent. This field defines the base 10 exponent times 3, that shall
102024  *    be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented
102025  *    by this PSI Dword. PSIE Values and corresponding bit rates: 0: Bits per second 1: Kb/s 2: Mb/s
102026  *    3: Gb/s
102027  */
102028 #define USB3_XECP_PSI_HIGH_SPEED_PSIE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PSIE_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PSIE_MASK)
102029 #define USB3_XECP_PSI_HIGH_SPEED_PLT_MASK        (0xC0U)
102030 #define USB3_XECP_PSI_HIGH_SPEED_PLT_SHIFT       (6U)
102031 /*! PLT - PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric
102032  *    bit rate, and if asymmetric, then this field also indicates if this Dword defines the receive or
102033  *    transmit bit rate. Note that the Asymmetric PSI Dwords shall be paired, i.e. an Rx
102034  *    immediately followed by a Tx, and both Dwords shall define the same value for the PSIV. PLT Values and
102035  *    corresponding bit rate: 0: Symmetric Single (PSI Dword) 1: Reserved 2: Asymmetric Rx (Paired
102036  *    with Asymmetric Tx PSI Dword) 3: Asymmetric Tx (Immediately follows Rx Asymmetric PSI Dword)
102037  */
102038 #define USB3_XECP_PSI_HIGH_SPEED_PLT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PLT_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PLT_MASK)
102039 #define USB3_XECP_PSI_HIGH_SPEED_PFD_MASK        (0x100U)
102040 #define USB3_XECP_PSI_HIGH_SPEED_PFD_SHIFT       (8U)
102041 /*! PFD - PSI Full-duplex. If this bit is '1' the link is full-duplex, and if '0' the link is half-duplex
102042  */
102043 #define USB3_XECP_PSI_HIGH_SPEED_PFD(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PFD_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PFD_MASK)
102044 #define USB3_XECP_PSI_HIGH_SPEED_PSIM_MASK       (0xFFFF0000U)
102045 #define USB3_XECP_PSI_HIGH_SPEED_PSIM_SHIFT      (16U)
102046 /*! PSIM - Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the
102047  *    PSIE when calculating the maximum bit rate represented by this PSI Dword
102048  */
102049 #define USB3_XECP_PSI_HIGH_SPEED_PSIM(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PSIM_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PSIM_MASK)
102050 /*! @} */
102051 
102052 /*! @name XECP_SUPP_USB3_CAP0 - xHCI Supported Protocol Capability */
102053 /*! @{ */
102054 #define USB3_XECP_SUPP_USB3_CAP0_PID_MASK        (0xFFU)
102055 #define USB3_XECP_SUPP_USB3_CAP0_PID_SHIFT       (0U)
102056 /*! PID - Capability ID. The value identifies the capability as Supported Protocol
102057  */
102058 #define USB3_XECP_SUPP_USB3_CAP0_PID(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_PID_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_PID_MASK)
102059 #define USB3_XECP_SUPP_USB3_CAP0_NextCapID_MASK  (0xFF00U)
102060 #define USB3_XECP_SUPP_USB3_CAP0_NextCapID_SHIFT (8U)
102061 /*! NextCapID - This field indicates the location of the next capability with respect to the
102062  *    effective address of this capability. Refer to Table 142 of xHCI specification for more information
102063  *    on this field
102064  */
102065 #define USB3_XECP_SUPP_USB3_CAP0_NextCapID(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_NextCapID_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_NextCapID_MASK)
102066 #define USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_MASK  (0xFF0000U)
102067 #define USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_SHIFT (16U)
102068 /*! Minor_Rev - Minor Specification Release Number in Binary-Coded Decimal (i.e.,version x.10 is
102069  *    10h). This field identifies the minor release number component of the specification with which
102070  *    the xHC is compliant
102071  */
102072 #define USB3_XECP_SUPP_USB3_CAP0_Minor_Rev(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_MASK)
102073 #define USB3_XECP_SUPP_USB3_CAP0_Major_Rev_MASK  (0xFF000000U)
102074 #define USB3_XECP_SUPP_USB3_CAP0_Major_Rev_SHIFT (24U)
102075 /*! Major_Rev - Major Specification Release Number in Binary-Coded Decimal (i.e.,version 3.x is
102076  *    03h). This field identifies the major release number component of the specification with which the
102077  *    xHC is compliant
102078  */
102079 #define USB3_XECP_SUPP_USB3_CAP0_Major_Rev(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_Major_Rev_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_Major_Rev_MASK)
102080 /*! @} */
102081 
102082 /*! @name XECP_SUPP_USB3_CAP1 - xHCI Supported Protocol Capability */
102083 /*! @{ */
102084 #define USB3_XECP_SUPP_USB3_CAP1_USB_STRING_MASK (0xFFFFFFFFU)
102085 #define USB3_XECP_SUPP_USB3_CAP1_USB_STRING_SHIFT (0U)
102086 /*! USB_STRING - Name String, RO. This field is a mnemonic name string that references the
102087  *    specification with which the xHC is compliant. Four ASCII characters may be defined. Allowed characters
102088  *    are: alphanumeric, space, and underscore. Alpha characters are case sensitive. Refer to
102089  *    section 7.2.2 of xHCI specification for defined values
102090  */
102091 #define USB3_XECP_SUPP_USB3_CAP1_USB_STRING(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP1_USB_STRING_SHIFT)) & USB3_XECP_SUPP_USB3_CAP1_USB_STRING_MASK)
102092 /*! @} */
102093 
102094 /*! @name XECP_SUPP_USB3_CAP2 - xHCI Supported Protocol Capability; USB 3 */
102095 /*! @{ */
102096 #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_MASK (0xFFU)
102097 #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_SHIFT (0U)
102098 /*! Compatible_Port_Offset - This field specifies the starting Port Number of Root Hub Ports that
102099  *    support this protocol. Valid values are 1 to MaxPorts
102100  */
102101 #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_SHIFT)) & USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_MASK)
102102 #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_MASK (0xFF00U)
102103 #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_SHIFT (8U)
102104 /*! Compatible_Port_Count - This field identifies the number of consecutive Root Hub Ports (starting
102105  *    at the Compatible Port Offset) that support this protocol. Valid values are 1 to MaxPorts
102106  */
102107 #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_SHIFT)) & USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_MASK)
102108 #define USB3_XECP_SUPP_USB3_CAP2_PSIC_MASK       (0xF0000000U)
102109 #define USB3_XECP_SUPP_USB3_CAP2_PSIC_SHIFT      (28U)
102110 /*! PSIC - Protocol Speed ID CountCount : 1, USB 3.0 Speed (Super Speed). This field indicates the
102111  *    number of Protocol Speed ID (PSI) Dwords that the xHCI Supported Protocol Capability data
102112  *    structure contains. If this field is non-zero, then all speeds supported by the protocol shall be
102113  *    defined using PSI Dwords, i.e. no implied Speed ID mappings apply
102114  */
102115 #define USB3_XECP_SUPP_USB3_CAP2_PSIC(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP2_PSIC_SHIFT)) & USB3_XECP_SUPP_USB3_CAP2_PSIC_MASK)
102116 /*! @} */
102117 
102118 /*! @name XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE - Protocol Slot Type */
102119 /*! @{ */
102120 #define USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_MASK (0x1FU)
102121 #define USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_SHIFT (0U)
102122 /*! PST - This field specifies the Protocol Slot Type value, which may be specified when allocating
102123  *    Device Slots that support this protocol. Valid values are 0 to 31. Refer to sections 4.6.3 and
102124  *    7.2.2.1.4 of xHCI specification. The value of the Protocol Slot Type field declared by a xHCI
102125  *    Supported Protocol Capability structure is unique to an xHC implementation. Software shall
102126  *    not assume a fixed mapping of the Protocol Slot Type value to a specific type of Supported
102127  *    Protocol. Note that for compatibility reasons, the Protocol Slot Type value of 0 is the exception
102128  *    to this rule and reserved for the USB Protocol Device Slot type
102129  */
102130 #define USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_SHIFT)) & USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_MASK)
102131 /*! @} */
102132 
102133 /*! @name PSI_SUPER_SPEED - Protocol Speed ID */
102134 /*! @{ */
102135 #define USB3_PSI_SUPER_SPEED_PSIV_MASK           (0xFU)
102136 #define USB3_PSI_SUPER_SPEED_PSIV_SHIFT          (0U)
102137 /*! PSIV - Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by
102138  *    this PSI Dword, then the value of this field shall be reported in the Port Speed field of
102139  *    PORTSC register (5.4.8 of xHCI specification) of a compatible port. Note, the PSIV value of 0 is
102140  *    reserved and shall not be defined by a PSI
102141  */
102142 #define USB3_PSI_SUPER_SPEED_PSIV(x)             (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PSIV_SHIFT)) & USB3_PSI_SUPER_SPEED_PSIV_MASK)
102143 #define USB3_PSI_SUPER_SPEED_PSIE_MASK           (0x30U)
102144 #define USB3_PSI_SUPER_SPEED_PSIE_SHIFT          (4U)
102145 /*! PSIE - Protocol Speed ID Exponent. This field defines the base 10 exponent times 3, that shall
102146  *    be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented
102147  *    by this PSI Dword. PSIE Values and corresponding bit rates: 0: Bits per second 1: Kb/s 2: Mb/s
102148  *    3: Gb/s
102149  */
102150 #define USB3_PSI_SUPER_SPEED_PSIE(x)             (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PSIE_SHIFT)) & USB3_PSI_SUPER_SPEED_PSIE_MASK)
102151 #define USB3_PSI_SUPER_SPEED_PLT_MASK            (0xC0U)
102152 #define USB3_PSI_SUPER_SPEED_PLT_SHIFT           (6U)
102153 /*! PLT - PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric
102154  *    bit rate, and if asymmetric, then this field also indicates if this Dword defines the receive or
102155  *    transmit bit rate. Note that the Asymmetric PSI Dwords shall be paired, i.e. an Rx
102156  *    immediately followed by a Tx, and both Dwords shall define the same value for the PSIV. PLT Values and
102157  *    corresponding bit rate: 0: Symmetric Single (PSI Dword) 1: Reserved 2: Asymmetric Rx (Paired
102158  *    with Asymmetric Tx PSI Dword) 3: Asymmetric Tx (Immediately follows Rx Asymmetric PSI Dword)
102159  */
102160 #define USB3_PSI_SUPER_SPEED_PLT(x)              (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PLT_SHIFT)) & USB3_PSI_SUPER_SPEED_PLT_MASK)
102161 #define USB3_PSI_SUPER_SPEED_PFD_MASK            (0x100U)
102162 #define USB3_PSI_SUPER_SPEED_PFD_SHIFT           (8U)
102163 /*! PFD - PSI Full-duplex. If this bit is '1' the link is full-duplex, and if '0' the link is half-duplex
102164  */
102165 #define USB3_PSI_SUPER_SPEED_PFD(x)              (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PFD_SHIFT)) & USB3_PSI_SUPER_SPEED_PFD_MASK)
102166 #define USB3_PSI_SUPER_SPEED_PSIM_MASK           (0xFFFF0000U)
102167 #define USB3_PSI_SUPER_SPEED_PSIM_SHIFT          (16U)
102168 /*! PSIM - Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the
102169  *    PSIE when calculating the maximum bit rate represented by this PSI Dword
102170  */
102171 #define USB3_PSI_SUPER_SPEED_PSIM(x)             (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PSIM_SHIFT)) & USB3_PSI_SUPER_SPEED_PSIM_MASK)
102172 /*! @} */
102173 
102174 /*! @name XECP_CMDM_STS0 - Command Ring related status */
102175 /*! @{ */
102176 #define USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_MASK (0xFFU)
102177 #define USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_SHIFT (0U)
102178 /*! VEND_DEF_CMDM_CAP_ID_193 - Vendor defined capability ID. Command Ring Manager capability ID
102179  */
102180 #define USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_SHIFT)) & USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_MASK)
102181 #define USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_MASK (0xFF00U)
102182 #define USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_SHIFT (8U)
102183 /*! XECP_CMDM_NEXT_CAP_OFFSET - Next capability offset
102184  */
102185 #define USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_SHIFT)) & USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_MASK)
102186 #define USB3_XECP_CMDM_STS0_cmd_running_MASK     (0x10000U)
102187 #define USB3_XECP_CMDM_STS0_cmd_running_SHIFT    (16U)
102188 /*! cmd_running - Indicates that the command ring is running
102189  */
102190 #define USB3_XECP_CMDM_STS0_cmd_running(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmd_running_SHIFT)) & USB3_XECP_CMDM_STS0_cmd_running_MASK)
102191 #define USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_MASK (0x20000U)
102192 #define USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_SHIFT (17U)
102193 /*! host_cmd_db_rang_sticky - Indicates that command ring has a doorbell pending
102194  */
102195 #define USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_SHIFT)) & USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_MASK)
102196 #define USB3_XECP_CMDM_STS0_stopping_cmd_ring_MASK (0x40000U)
102197 #define USB3_XECP_CMDM_STS0_stopping_cmd_ring_SHIFT (18U)
102198 /*! stopping_cmd_ring - Indicates that a STOP on the Command Ring is in progress
102199  */
102200 #define USB3_XECP_CMDM_STS0_stopping_cmd_ring(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_stopping_cmd_ring_SHIFT)) & USB3_XECP_CMDM_STS0_stopping_cmd_ring_MASK)
102201 #define USB3_XECP_CMDM_STS0_trm_stall_req_MASK   (0x100000U)
102202 #define USB3_XECP_CMDM_STS0_trm_stall_req_SHIFT  (20U)
102203 /*! trm_stall_req - Indicates that transfer ring manager is issuing and EP state update due to stall received
102204  */
102205 #define USB3_XECP_CMDM_STS0_trm_stall_req(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_trm_stall_req_SHIFT)) & USB3_XECP_CMDM_STS0_trm_stall_req_MASK)
102206 #define USB3_XECP_CMDM_STS0_trm_eperr_upd_req_MASK (0x200000U)
102207 #define USB3_XECP_CMDM_STS0_trm_eperr_upd_req_SHIFT (21U)
102208 /*! trm_eperr_upd_req - Indicates that Transfer Ring Manager is issuing and EP update due to an EP error condition detected
102209  */
102210 #define USB3_XECP_CMDM_STS0_trm_eperr_upd_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_trm_eperr_upd_req_SHIFT)) & USB3_XECP_CMDM_STS0_trm_eperr_upd_req_MASK)
102211 #define USB3_XECP_CMDM_STS0_dbm_ep_upd_req_MASK  (0x400000U)
102212 #define USB3_XECP_CMDM_STS0_dbm_ep_upd_req_SHIFT (22U)
102213 /*! dbm_ep_upd_req - Indicates that Doorbell Manager is issuing and EP update due to a doorbell ring on an EP that is in stop state
102214  */
102215 #define USB3_XECP_CMDM_STS0_dbm_ep_upd_req(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_dbm_ep_upd_req_SHIFT)) & USB3_XECP_CMDM_STS0_dbm_ep_upd_req_MASK)
102216 #define USB3_XECP_CMDM_STS0_update_endpt_active_MASK (0x800000U)
102217 #define USB3_XECP_CMDM_STS0_update_endpt_active_SHIFT (23U)
102218 /*! update_endpt_active - Indicates that updating of EP state is in progress
102219  */
102220 #define USB3_XECP_CMDM_STS0_update_endpt_active(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_update_endpt_active_SHIFT)) & USB3_XECP_CMDM_STS0_update_endpt_active_MASK)
102221 #define USB3_XECP_CMDM_STS0_odma_address_dev_pending_MASK (0x1000000U)
102222 #define USB3_XECP_CMDM_STS0_odma_address_dev_pending_SHIFT (24U)
102223 /*! odma_address_dev_pending - Indicates that ODMA has an address device command in progress
102224  */
102225 #define USB3_XECP_CMDM_STS0_odma_address_dev_pending(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_odma_address_dev_pending_SHIFT)) & USB3_XECP_CMDM_STS0_odma_address_dev_pending_MASK)
102226 #define USB3_XECP_CMDM_STS0_odma_address_dev_done_MASK (0x2000000U)
102227 #define USB3_XECP_CMDM_STS0_odma_address_dev_done_SHIFT (25U)
102228 /*! odma_address_dev_done - Indicates that current address device command is done by ODMA
102229  */
102230 #define USB3_XECP_CMDM_STS0_odma_address_dev_done(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_odma_address_dev_done_SHIFT)) & USB3_XECP_CMDM_STS0_odma_address_dev_done_MASK)
102231 #define USB3_XECP_CMDM_STS0_cmdm_clr_db_req_MASK (0x4000000U)
102232 #define USB3_XECP_CMDM_STS0_cmdm_clr_db_req_SHIFT (26U)
102233 /*! cmdm_clr_db_req - Indicates that clearing an EP out of schedule is in progress
102234  */
102235 #define USB3_XECP_CMDM_STS0_cmdm_clr_db_req(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmdm_clr_db_req_SHIFT)) & USB3_XECP_CMDM_STS0_cmdm_clr_db_req_MASK)
102236 #define USB3_XECP_CMDM_STS0_cmdm_stop_req_MASK   (0x8000000U)
102237 #define USB3_XECP_CMDM_STS0_cmdm_stop_req_SHIFT  (27U)
102238 /*! cmdm_stop_req - Indicates that Command Ring stop command is in progress
102239  */
102240 #define USB3_XECP_CMDM_STS0_cmdm_stop_req(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmdm_stop_req_SHIFT)) & USB3_XECP_CMDM_STS0_cmdm_stop_req_MASK)
102241 #define USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_MASK (0x10000000U)
102242 #define USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_SHIFT (28U)
102243 /*! cmdm_cntx_lock_req - Indicates that Command Manager has requested a context lock
102244  */
102245 #define USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_SHIFT)) & USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_MASK)
102246 #define USB3_XECP_CMDM_STS0_trm_cntx_in_use_MASK (0x20000000U)
102247 #define USB3_XECP_CMDM_STS0_trm_cntx_in_use_SHIFT (29U)
102248 /*! trm_cntx_in_use - Indicates that TRM modules owns the context access currently
102249  */
102250 #define USB3_XECP_CMDM_STS0_trm_cntx_in_use(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_trm_cntx_in_use_SHIFT)) & USB3_XECP_CMDM_STS0_trm_cntx_in_use_MASK)
102251 #define USB3_XECP_CMDM_STS0_odma_cntx_in_use_MASK (0x40000000U)
102252 #define USB3_XECP_CMDM_STS0_odma_cntx_in_use_SHIFT (30U)
102253 /*! odma_cntx_in_use - Indicates that ODMA module currently owns currently the context access
102254  */
102255 #define USB3_XECP_CMDM_STS0_odma_cntx_in_use(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_odma_cntx_in_use_SHIFT)) & USB3_XECP_CMDM_STS0_odma_cntx_in_use_MASK)
102256 #define USB3_XECP_CMDM_STS0_idma_cntx_in_use_MASK (0x80000000U)
102257 #define USB3_XECP_CMDM_STS0_idma_cntx_in_use_SHIFT (31U)
102258 /*! idma_cntx_in_use - Indicates that IDMA module currently owns the context access :
102259  */
102260 #define USB3_XECP_CMDM_STS0_idma_cntx_in_use(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_idma_cntx_in_use_SHIFT)) & USB3_XECP_CMDM_STS0_idma_cntx_in_use_MASK)
102261 /*! @} */
102262 
102263 /*! @name XECP_CMDM_CTRL_REG1 - Command Manager Control */
102264 /*! @{ */
102265 #define USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_MASK (0x1U)
102266 #define USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_SHIFT (0U)
102267 /*! update_endpt_event_enable - '0': Disable generation of the completion event. '1': Enable the
102268  *    command manager to generate a completion event after an EP state update due to internal error.
102269  *    This bit is for test debug
102270  */
102271 #define USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_MASK)
102272 #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_MASK (0x2U)
102273 #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_SHIFT (1U)
102274 /*! force_bandwidth_fail - '0': Bandwidth calculation handled normally. '1': Forces a failure in the
102275  *    endpoint bandwidth calculation so that engine will reject a configure EP command
102276  */
102277 #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_MASK)
102278 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_MASK (0x4U)
102279 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_SHIFT (2U)
102280 /*! clr_cntx_4setdqptr - '0': Disable clearing internal TRM and DMA context during a set TR DQ
102281  *    pointer command. '1': Enable clearing internal TRM and DMA context during a set TR DQ pointer
102282  *    command
102283  */
102284 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_MASK)
102285 #define USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_MASK (0x8U)
102286 #define USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_SHIFT (3U)
102287 /*! addr_dev_slst_bsr_check_en - '0': Address device does not return the error for this condition.
102288  *    '1': Enable the EP state (default state) check with address device command with BSR. If failed,
102289  *    an event with context state error will be generated
102290  */
102291 #define USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_MASK)
102292 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_MASK (0x10U)
102293 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_SHIFT (4U)
102294 /*! clr_cntx_4rstdev - '0': Disable clearing internal TRM and DMA context during a reset device
102295  *    command. '1': Enable clearing internal TRM and DMA context during a reset device command
102296  */
102297 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_MASK)
102298 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_MASK (0x20U)
102299 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_SHIFT (5U)
102300 /*! clr_cntx_4enslot_reg - '0': Disable clearing internal TRM and DMA context during an enable slot
102301  *    command. '1': Enable clearing internal TRM and DMA context during an enable slot command
102302  */
102303 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_MASK)
102304 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_MASK (0x40U)
102305 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_SHIFT (6U)
102306 /*! clr_cntx_4enaddr - '0': Disable clearing internal TRM and DMA context during an address device
102307  *    command. '1': Enable clearing internal TRM and DMA context during an address device command
102308  */
102309 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_MASK)
102310 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_MASK (0x80U)
102311 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_SHIFT (7U)
102312 /*! clr_cntx_4encfgendpt - '0': Disable clearing internal TRM and DMA context during a configure
102313  *    endpoint command. '1': Enable clearing internal TRM and DMA context during a configure endpoint
102314  *    command
102315  */
102316 #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_MASK)
102317 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_MASK (0x100U)
102318 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_SHIFT (8U)
102319 /*! clr_ep_cntx_4en_slot - '0': Disable clearing other internal EP status signals during an enable
102320  *    slot command. '1': Enable clearing other internal EP related status signals such as EP
102321  *    scheduled array, credit stored per EP. etc., during an enable slot command
102322  */
102323 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_MASK)
102324 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_MASK (0x200U)
102325 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_SHIFT (9U)
102326 /*! clr_ep_cntx_4rst_endpt - '0': Disable clearing other internal EP status signals during a reset
102327  *    endpoint command. '1': Enable clearing other internal EP related status signals such as EP
102328  *    scheduled array, credit stored per EP. etc. during a reset endpoint command
102329  */
102330 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_MASK)
102331 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_MASK (0x400U)
102332 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_SHIFT (10U)
102333 /*! clr_ep_cntx_4rst_device - '0': Disable clearing other internal EP status signals during a reset
102334  *    device command. '1': Enable clearing other internal EP related status signals such as EP
102335  *    scheduled array, credit stored per EP, etc. during a reset device command
102336  */
102337 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_MASK)
102338 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_MASK (0x800U)
102339 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_SHIFT (11U)
102340 /*! clr_ep_cntx_4cfg_endpt - '0': Disable clearing other internal EP status signals during a
102341  *    configure endpoint command. '1': Enable clearing other internal EP related status signals such as EP
102342  *    scheduled array, credit stored per EP, etc. during a configure endpoint command
102343  */
102344 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_MASK)
102345 #define USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_MASK (0x1000U)
102346 #define USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_SHIFT (12U)
102347 /*! glob_tsp_en - '0': Disable the global context preservation. '1': Enable the internal context
102348  *    preservation for all commands that needs to preserve some of the internal context fields as a
102349  *    command with TSP would
102350  */
102351 #define USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_MASK)
102352 #define USB3_XECP_CMDM_CTRL_REG1_init_retry_MASK (0x2000U)
102353 #define USB3_XECP_CMDM_CTRL_REG1_init_retry_SHIFT (13U)
102354 /*! init_retry - init_retry. Reserved to always read value of '1'
102355  */
102356 #define USB3_XECP_CMDM_CTRL_REG1_init_retry(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_init_retry_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_init_retry_MASK)
102357 #define USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_MASK (0x4000U)
102358 #define USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_SHIFT (14U)
102359 /*! eval_epst_check_en - '0': Disable evaluating the endpoint state during an Evaluate Context
102360  *    command, '1': Enable EP state check during an Evaluate Context command. If failed, context error
102361  *    will be returned
102362  */
102363 #define USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_MASK)
102364 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_MASK (0x8000U)
102365 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_SHIFT (15U)
102366 /*! clr_ep_cntx_4dis_slot - '0': Disable clearing internal TRM and DMA context as well as the
102367  *    internal EP status signals during a disable slot command. '1': Enable clearing internal TRM and DMA
102368  *    context as well as the internal EP status signals during a disable slot command
102369  */
102370 #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_MASK)
102371 #define USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_MASK (0x10000U)
102372 #define USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_SHIFT (16U)
102373 /*! clr_split_state_with_tspset - This bit allows engine to reset the split states when reset
102374  *    endpoint with TSP is posted. The split state is an internal context field in DMA engine. '0':
102375  *    Indicates that reset endpoint with TSP will preserve the split state. '1': Indicates that the reset
102376  *    endpoint with TSP will not preserve the split state
102377  */
102378 #define USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_MASK)
102379 #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_MASK (0x20000U)
102380 #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_SHIFT (17U)
102381 /*! force_bandwidth_pass - force_bandwidth_pass
102382  */
102383 #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_MASK)
102384 #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_MASK (0x40000U)
102385 #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_SHIFT (18U)
102386 /*! force_bandwidth_sys_pass - force_bandwidth_sys_pass
102387  */
102388 #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_MASK)
102389 #define USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_MASK (0x80000U)
102390 #define USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_SHIFT (19U)
102391 /*! report_bandwidth_skip_scan - report_bandwidth_skip_scan
102392  */
102393 #define USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_MASK)
102394 #define USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_MASK (0x100000U)
102395 #define USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_SHIFT (20U)
102396 /*! enable_max_ep_cache - enable_max_ep_cache
102397  */
102398 #define USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_MASK)
102399 #define USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_MASK (0x200000U)
102400 #define USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_SHIFT (21U)
102401 /*! cfg_endpt_cntx_lock_dis - Context lock mechanism to ensure command manager has exclusive access
102402  *    to internal context. This is a disable bit to allow software to turn off the context lock for
102403  *    configure endpoint command. This is a test/debug feature. '1': indicates disabled. '0':
102404  *    Indicates enabled
102405  */
102406 #define USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_MASK)
102407 #define USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_MASK (0x400000U)
102408 #define USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_SHIFT (22U)
102409 /*! feature_retry_en - Enable the EOB and NPKT==0 (called NYET condition for USB3) to be used to
102410  *    update a retry bit during stream switching operation. This is an internal safety feature. It
102411  *    should be treated as reserved bit
102412  */
102413 #define USB3_XECP_CMDM_CTRL_REG1_feature_retry_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_MASK)
102414 #define USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_MASK (0x800000U)
102415 #define USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_SHIFT (23U)
102416 /*! eval_cntx_bw_scan_en - Enable the Host Controller's Bandwidth checks for the Evaluate Context Command. Rescan the BW during evaluate context
102417  */
102418 #define USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_MASK)
102419 #define USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_MASK (0xF000000U)
102420 #define USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_SHIFT (24U)
102421 /*! default_isoch_ep_bandwidth - Bandwidth calculation parameter: Default bandwidth for an Isochronous Endpoint
102422  */
102423 #define USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_MASK)
102424 #define USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_MASK (0xF0000000U)
102425 #define USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_SHIFT (28U)
102426 /*! default_intr_ep_bandwidth - Bandwidth calculation parameter: Default bandwidth for an Interrupt Endpoint
102427  */
102428 #define USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_MASK)
102429 /*! @} */
102430 
102431 /*! @name XECP_CMDM_CTRL_REG2 - Command Manager Control */
102432 /*! @{ */
102433 #define USB3_XECP_CMDM_CTRL_REG2_clr_st_MASK     (0x3FFFU)
102434 #define USB3_XECP_CMDM_CTRL_REG2_clr_st_SHIFT    (0U)
102435 /*! clr_st - Clear state machine present state: Setting a specified bit to '1', will reset the
102436  *    corresponding command manager state machine to the starting/idle state. bit-0: disable slot state
102437  *    machine; bit-1: enable slot state machine; bit-2: reset endpoint state machine; bit-3: reset
102438  *    device state machine; bit-4: command ring state machine; bit-5: stop endpoint state machine;
102439  *    bit-6: set dq pointer state machine; bit-7: force header state machine; bit-8: evaluate context
102440  *    state machine; bit-9: update endpoint state machine; bit-10: address device state machine;
102441  *    bit-11: port bandwidth state machine; bit-12: read output context state machine; bit-13: configure
102442  *    endpoint state machine;
102443  */
102444 #define USB3_XECP_CMDM_CTRL_REG2_clr_st(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_st_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_st_MASK)
102445 #define USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_MASK (0x4000U)
102446 #define USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_SHIFT (14U)
102447 /*! burst_size_default_en - When context is first initialized, it is assumed one remote NPKT. It is
102448  *    also assumed that max burst size as remote NPKT. This bit enables to assume max burst size as
102449  *    remote NPKT. '0': Assume 1 NPKT. '1': Assume max burst size as NPKT
102450  */
102451 #define USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_MASK)
102452 #define USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_MASK (0x8000U)
102453 #define USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_SHIFT (15U)
102454 /*! disable_stall_clr_ep - '0': Stall handling does clear the internal EP status signals. '1':
102455  *    Disable the clear function when stall response received
102456  */
102457 #define USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_MASK)
102458 #define USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_MASK (0x10000U)
102459 #define USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_SHIFT (16U)
102460 /*! increase_update_ep_priority_en - Increase Update EP priority over commands in the command ring
102461  *    to avoid prolonging STALL handling. '0': Pending commands have a higher priority than update
102462  *    endpoint processing. '1': Update endpoint processing in the command manager has a higher
102463  *    priority than pending commands. Note: Enabling this bit can prevent prolonged stall handling
102464  */
102465 #define USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_MASK)
102466 #define USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_MASK (0x20000U)
102467 #define USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_SHIFT (17U)
102468 /*! trm_break_loop_en - trm_break_loop_en. This is an internal safeguard register. It enables a
102469  *    different mechanism of handling stop endpoint command. It should be treated as a reserved field.
102470  *    The default should not be alternate unless specific purpose. '0': Disable. '1': Enable
102471  */
102472 #define USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_MASK)
102473 #define USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_MASK (0x40000U)
102474 #define USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_SHIFT (18U)
102475 /*! tsp_4set_dqptr_reg - '0': Disable sequence number preservation during set DQ pointer command.
102476  *    '1': Enable sequence number to be preserved during set DQ pointer command
102477  */
102478 #define USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_MASK)
102479 #define USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_MASK (0x80000U)
102480 #define USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_SHIFT (19U)
102481 /*! force_reset_endpt_reg - '0': Check the slot and endpoint state prior to processing a reset
102482  *    endpoint command. '1': Ignore the slot and endpoint state when processing a reset endpoint command
102483  */
102484 #define USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_MASK)
102485 #define USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_MASK (0x100000U)
102486 #define USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_SHIFT (20U)
102487 /*! set_dqptr_clr_ep_arys - '0': Disable clearing other internal EP status signals during a set DQ
102488  *    pointer command. '1': Enable clearing other internal EP status signals during a set DQ pointer
102489  *    command
102490  */
102491 #define USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_MASK)
102492 #define USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_MASK (0x200000U)
102493 #define USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_SHIFT (21U)
102494 /*! cmd_st_dis_reg - '0': Delay processing command ring TRB while internal context requests are
102495  *    pending. '1': Process command ring TRBs normally
102496  */
102497 #define USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_MASK)
102498 #define USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_MASK (0x400000U)
102499 #define USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_SHIFT (22U)
102500 /*! enable_bw_cal - '0': Disable hardware bandwidth calculations. '1': Enable hardware bandwidth calculations
102501  */
102502 #define USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_MASK)
102503 #define USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_MASK (0x800000U)
102504 #define USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_SHIFT (23U)
102505 /*! clr_cntx_4rst_endpt_reg - '0': Disable clearing internal TRM and DMA context during a reset
102506  *    endpoint command. '1': Enable clearing internal TRM and DMA context during a reset endpoint command
102507  */
102508 #define USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_MASK)
102509 #define USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_MASK (0x1000000U)
102510 #define USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_SHIFT (24U)
102511 /*! move_xfer_dqptr_2cpl_dqptr_en - '0': The internal context write DQ pointer moved to internal
102512  *    read pointer during reset EP command. '1': The write DQ pointer stays as it was during reset
102513  *    endpoint command
102514  */
102515 #define USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_MASK)
102516 #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_MASK (0x2000000U)
102517 #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_SHIFT (25U)
102518 /*! clr_ep_cntx_4stall_upd - '0': Disable clearing other internal EP status signal during stall
102519  *    handling. '1': Enable clearing other internal EP status signal during stall handling
102520  */
102521 #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_MASK)
102522 #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_MASK (0x4000000U)
102523 #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_SHIFT (26U)
102524 /*! clr_ep_cntx_4stop_endpt - '0': Disable clearing other internal per EP status signal during a
102525  *    stop endpoint command. '1': Enable clearing other internal per EP status signal during a stop
102526  *    endpoint command
102527  */
102528 #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_MASK)
102529 #define USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_MASK (0x8000000U)
102530 #define USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_SHIFT (27U)
102531 /*! all_clk_gate_dis - '0': Turn ON the TTE clock. '1': Turn OFF the TTE clock
102532  */
102533 #define USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_MASK)
102534 #define USB3_XECP_CMDM_CTRL_REG2_SRE_MASK        (0x10000000U)
102535 #define USB3_XECP_CMDM_CTRL_REG2_SRE_SHIFT       (28U)
102536 /*! SRE - Force and error on save command always. '0': do not force, '1': always force return save error
102537  */
102538 #define USB3_XECP_CMDM_CTRL_REG2_SRE(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_SRE_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_SRE_MASK)
102539 #define USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_MASK (0x20000000U)
102540 #define USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_SHIFT (29U)
102541 /*! slot_id_overide_en - Force '0' on slot ID when a command transfer event is generated. '0': not forced, '1': Forced to 0
102542  */
102543 #define USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_MASK)
102544 #define USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_MASK (0x40000000U)
102545 #define USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_SHIFT (30U)
102546 /*! stop_endpt_2ms_timeout_en - Enable a delay to stop endpoint command that is executed in XFER
102547  *    engine. '0': XFER engine will not wait. '1': XFER engine will always wait for 2 ms before it
102548  *    checks whether an EP transfer ring is at a stop of packet boundary
102549  */
102550 #define USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_MASK)
102551 #define USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_MASK (0x80000000U)
102552 #define USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_SHIFT (31U)
102553 /*! doing_2dw_ocntx_wr_en - Enable only to update the EP state to output context on every EP output
102554  *    context update condition. This is to allow to have a control over either update the entire
102555  *    EPoutput context field or only update the first two DWORDs. '0': update the entire output context
102556  *    field. '1': update only 2 DWORDs
102557  */
102558 #define USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_MASK)
102559 /*! @} */
102560 
102561 /*! @name XECP_CMDM_CTRL_REG3 - Command Manager Control */
102562 /*! @{ */
102563 #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_MASK (0xFFU)
102564 #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_SHIFT (0U)
102565 /*! DEFAULT_PORT_BANDWD_AVAIL - The default available bandwidth to advertise on each LS, FS, SS port
102566  *    in 10% increments (90%). Bandwidth calculation is a reserved field for PPT
102567  */
102568 #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_MASK)
102569 #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_MASK (0xFF00U)
102570 #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_SHIFT (8U)
102571 /*! DEFAULT_HS_BANDWD_AVAIL - The default available bandwidth to advertise on each HS port in 10%
102572  *    increments (80%). Bandwidth Calculation is a reserved field for PPT
102573  */
102574 #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_MASK)
102575 #define USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_MASK (0x30000U)
102576 #define USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_SHIFT (16U)
102577 /*! disable_slot_timer_select - These two bits specify the delay that we can have for disable slot
102578  *    state to be completed. We can delay the generation of the command transfer event during disable
102579  *    slot command. Possible values: '00': delay is disabled, '01': 100us delay, '10': 8ms delay,
102580  *    '11': 10ms delay
102581  */
102582 #define USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_MASK)
102583 #define USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_MASK (0x40000U)
102584 #define USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_SHIFT (18U)
102585 /*! clr_trm_dma_cntx_en - clr_trm_dma_cntx_en
102586  */
102587 #define USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_MASK)
102588 #define USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_MASK (0x80000U)
102589 #define USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_SHIFT (19U)
102590 /*! stop_2timeout_en - stop_2timeout_en. Stop transaction timeout
102591  */
102592 #define USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_MASK)
102593 #define USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_MASK (0x100000U)
102594 #define USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_SHIFT (20U)
102595 /*! break_cntx_lock_en - break_cntx_lock_en
102596  */
102597 #define USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_MASK)
102598 #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_MASK (0x200000U)
102599 #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_SHIFT (21U)
102600 /*! stop_ep_clr_stream_st_en - stop_ep_clr_stream_st_en. Enable stop endpoint command to return stream st to disabled (0) in EP context
102601  */
102602 #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_MASK)
102603 #define USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_MASK (0x400000U)
102604 #define USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_SHIFT (22U)
102605 /*! allow_clr_4stop - allow_clr_4stop
102606  */
102607 #define USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_MASK)
102608 #define USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_MASK (0x800000U)
102609 #define USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_SHIFT (23U)
102610 /*! stream_always_update_cntx - stream_always_update_cntx
102611  */
102612 #define USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_MASK)
102613 #define USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_MASK (0x1000000U)
102614 #define USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_SHIFT (24U)
102615 /*! set_burst_size_4prdc_dis - set_burst_size_4prdc_dis
102616  */
102617 #define USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_MASK)
102618 #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_MASK (0x2000000U)
102619 #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_SHIFT (25U)
102620 /*! stop_ep_clr_lcstream_id_en - stop_ep_clr_lcstream_id_en. Enable stop endpoint command to return stream st to disabled (0) in EP context
102621  */
102622 #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_MASK)
102623 #define USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_MASK (0x4000000U)
102624 #define USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_SHIFT (26U)
102625 /*! update_cntx_when_stopped - update_cntx_when_stopped. Allow setTRDQPtr cmd to update the local
102626  *    context anytime the EP is not running (otherwise checks CSTREAMID)
102627  */
102628 #define USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_MASK)
102629 #define USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_MASK (0x8000000U)
102630 #define USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_SHIFT (27U)
102631 /*! disable_setdqptr_clr_stream_st - disable_setdqptr_clr_stream_st. Disable setTRDQPtr from clearing the current stream state
102632  */
102633 #define USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_MASK)
102634 #define USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_MASK (0x10000000U)
102635 #define USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_SHIFT (28U)
102636 /*! disable_non0ep_cntx_clr - disable_non0ep_cntx_clr
102637  */
102638 #define USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_MASK)
102639 #define USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_MASK (0x20000000U)
102640 #define USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_SHIFT (29U)
102641 /*! extra_db_rm_4stop_en - extra_db_rm_4stop_en
102642  */
102643 #define USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_MASK)
102644 #define USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_MASK (0x40000000U)
102645 #define USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_SHIFT (30U)
102646 /*! ignore_hi_atomic_en - ignore_hi_atomic_en
102647  */
102648 #define USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_MASK)
102649 #define USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_MASK (0x80000000U)
102650 #define USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_SHIFT (31U)
102651 /*! frindex_wr_en - MFIndex register write enable. For debug purposes
102652  */
102653 #define USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_MASK)
102654 /*! @} */
102655 
102656 /*! @name XECP_HOST_CTRL_CAP - Host Control Capability */
102657 /*! @{ */
102658 #define USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_MASK (0xFFU)
102659 #define USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_SHIFT (0U)
102660 /*! VEND_DEF_HOST_CAP_ID_192 - Capability ID. This field identifies the xHCI Extended capability.
102661  *    192-255 are IDs available for vendor specific extensions to the xHCI
102662  */
102663 #define USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_SHIFT)) & USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_MASK)
102664 #define USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_MASK (0xFF00U)
102665 #define USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_SHIFT (8U)
102666 /*! XECP_HOST_NEXT_CAP_OFFSET - Next xHCI Extended Capability Pointer. This field points to the xHC
102667  *    MMIO space offset of the next xHCI extended capability pointer. A value of 00h indicates the
102668  *    end of the extended capability list. A non-zero value in this register indicates a relative
102669  *    offset, in Dwords, from this Dword to the beginning of the next extended capability. For example,
102670  *    assuming an effective address of this data structure is 350h and assuming a pointer value of
102671  *    068h, we can calculate the following effective address: 350h + (068h << 2) -> 350h + 1A0h ->
102672  *    4F0h
102673  */
102674 #define USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_SHIFT)) & USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_MASK)
102675 /*! @} */
102676 
102677 /*! @name XECP_HOST_CLR_MASK_REG - Override Endpoint Flow Control */
102678 /*! @{ */
102679 #define USB3_XECP_HOST_CLR_MASK_REG_EP_dir_MASK  (0x1U)
102680 #define USB3_XECP_HOST_CLR_MASK_REG_EP_dir_SHIFT (0U)
102681 /*! EP_dir - Indicates the direction of the Endpoint
102682  */
102683 #define USB3_XECP_HOST_CLR_MASK_REG_EP_dir(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_MASK_REG_EP_dir_SHIFT)) & USB3_XECP_HOST_CLR_MASK_REG_EP_dir_MASK)
102684 #define USB3_XECP_HOST_CLR_MASK_REG_EP_num_MASK  (0x1EU)
102685 #define USB3_XECP_HOST_CLR_MASK_REG_EP_num_SHIFT (1U)
102686 /*! EP_num - Endpoint number
102687  */
102688 #define USB3_XECP_HOST_CLR_MASK_REG_EP_num(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_MASK_REG_EP_num_SHIFT)) & USB3_XECP_HOST_CLR_MASK_REG_EP_num_MASK)
102689 #define USB3_XECP_HOST_CLR_MASK_REG_Slot_num_MASK (0x3E0U)
102690 #define USB3_XECP_HOST_CLR_MASK_REG_Slot_num_SHIFT (5U)
102691 /*! Slot_num - Slot number
102692  */
102693 #define USB3_XECP_HOST_CLR_MASK_REG_Slot_num(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_MASK_REG_Slot_num_SHIFT)) & USB3_XECP_HOST_CLR_MASK_REG_Slot_num_MASK)
102694 /*! @} */
102695 
102696 /*! @name XECP_HOST_CLR_IN_EP_VALID_REG - Clear Active IN EP ID Control */
102697 /*! @{ */
102698 #define USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_MASK (0xFFFFFFFFU)
102699 #define USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_SHIFT (0U)
102700 /*! port_num - This field indicates the port number
102701  */
102702 #define USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_SHIFT)) & USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_MASK)
102703 /*! @} */
102704 
102705 /*! @name XECP_HOST_CLR_PMASK_REG - Clear Poll Mask Control */
102706 /*! @{ */
102707 #define USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_MASK (0x1U)
102708 #define USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_SHIFT (0U)
102709 /*! EP_dir - Indicates the direction of the Endpoint
102710  */
102711 #define USB3_XECP_HOST_CLR_PMASK_REG_EP_dir(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_SHIFT)) & USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_MASK)
102712 #define USB3_XECP_HOST_CLR_PMASK_REG_EP_num_MASK (0x1EU)
102713 #define USB3_XECP_HOST_CLR_PMASK_REG_EP_num_SHIFT (1U)
102714 /*! EP_num - Endpoint number
102715  */
102716 #define USB3_XECP_HOST_CLR_PMASK_REG_EP_num(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_PMASK_REG_EP_num_SHIFT)) & USB3_XECP_HOST_CLR_PMASK_REG_EP_num_MASK)
102717 #define USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_MASK (0x3E0U)
102718 #define USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_SHIFT (5U)
102719 /*! Slot_num - Slot number
102720  */
102721 #define USB3_XECP_HOST_CLR_PMASK_REG_Slot_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_SHIFT)) & USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_MASK)
102722 /*! @} */
102723 
102724 /*! @name XECP_HOST_CTRL_OCRD_REG - Port Credit Control */
102725 /*! @{ */
102726 #define USB3_XECP_HOST_CTRL_OCRD_REG_port_num_MASK (0xFFU)
102727 #define USB3_XECP_HOST_CTRL_OCRD_REG_port_num_SHIFT (0U)
102728 /*! port_num - port number
102729  */
102730 #define USB3_XECP_HOST_CTRL_OCRD_REG_port_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_port_num_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_port_num_MASK)
102731 #define USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_MASK (0x4000000U)
102732 #define USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_SHIFT (26U)
102733 /*! st_upd_reg - Slot state control. st_upd_reg
102734  */
102735 #define USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_MASK)
102736 #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_MASK (0x8000000U)
102737 #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_SHIFT (27U)
102738 /*! minus_4rfifo - Indicates whether the subtract command operates on TX FIFO credit or RX FIFO credit
102739  */
102740 #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_MASK)
102741 #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_MASK (0x10000000U)
102742 #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_SHIFT (28U)
102743 /*! minus_ocrd - Subtract one credit from a port
102744  */
102745 #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_MASK)
102746 #define USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_MASK (0x20000000U)
102747 #define USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_SHIFT (29U)
102748 /*! plus_ocrd - Add one credit to a port
102749  */
102750 #define USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_MASK)
102751 #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_MASK (0x40000000U)
102752 #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_SHIFT (30U)
102753 /*! clr_cpl_st - Write '1' to force CPL state return to IDLE
102754  */
102755 #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_MASK)
102756 #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_MASK (0x80000000U)
102757 #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_SHIFT (31U)
102758 /*! clr_xfer_st - Write '1' to force XFER state return to IDLE
102759  */
102760 #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_MASK)
102761 /*! @} */
102762 
102763 /*! @name XECP_HOST_CTRL_TEST_BUS_LO - Test Bus Low */
102764 /*! @{ */
102765 #define USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_MASK (0xFFFFFFFFU)
102766 #define USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_SHIFT (0U)
102767 /*! TEST_BUS_LO - Host controller test bus low 32-bits.
102768  */
102769 #define USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_SHIFT)) & USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_MASK)
102770 /*! @} */
102771 
102772 /*! @name XECP_HOST_CTRL_TEST_BUS_HI - Test Bus High */
102773 /*! @{ */
102774 #define USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_MASK (0xFFFFFFFFU)
102775 #define USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_SHIFT (0U)
102776 /*! TEST_BUS_HI - Host controller test bus high 32-bits
102777  */
102778 #define USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_SHIFT)) & USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_MASK)
102779 /*! @} */
102780 
102781 /*! @name XECP_HOST_CTRL_TRM_REG1 - Host Control Transfer Manager */
102782 /*! @{ */
102783 #define USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_MASK (0x1U)
102784 #define USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_SHIFT (0U)
102785 /*! in_td_pace_enable - '0': Disable TD pacing for IN endpoint. '1': Enable TD pacing for IN endpoints
102786  */
102787 #define USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_MASK)
102788 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_MASK (0x2U)
102789 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_SHIFT (1U)
102790 /*! disable_fc_4inrdy - '0': Obey the NPKT0 and EOB flow control. '1': Ignore received flow control
102791  *    for implied NRDY (e.g EOB or NPKT=0) for USB3 only
102792  */
102793 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_MASK)
102794 #define USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_MASK (0x4U)
102795 #define USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_SHIFT (2U)
102796 /*! link_nop_sucess_en - '0': Process transaction errors due to CERR count reached or transaction
102797  *    timeout reported by the DMA engine. '1': Ignore transaction errors reported by the DMA engine
102798  */
102799 #define USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_MASK)
102800 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_MASK (0x8U)
102801 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_SHIFT (3U)
102802 /*! disable_stall - '0': Process stalls reported by the DMA engine. '1': Ignore stall response received reported by the DMA engine
102803  */
102804 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_MASK)
102805 #define USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_MASK (0x10U)
102806 #define USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_SHIFT (4U)
102807 /*! xport_crd_disable - This bit is designed to allow XFER engine to do a transfer without checking
102808  *    against the available port credit. '0': Advertises accurate buffer credit information to the
102809  *    scheduler. '1': Advertises non-zero buffer credits to the scheduler (e.g. never backpressure
102810  *    back on buffer credit information)
102811  */
102812 #define USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_MASK)
102813 #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_MASK (0x20U)
102814 #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_SHIFT (5U)
102815 /*! cpl_pkt_clr_mask_en - Enable a function, which clears a mask of an EP on any response of that
102816  *    EP. '0': Clear the scheduler mask normally, '1': Clear the scheduler mask on each received packet
102817  */
102818 #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_MASK)
102819 #define USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_MASK (0x40U)
102820 #define USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_SHIFT (6U)
102821 /*! en_bb_port_disable - '0': Babble errors will not disable the port. '1': Babble errors will
102822  *    disable the auto detect function This will allow engine to handle more than 4 TRBs per packet
102823  */
102824 #define USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_MASK)
102825 #define USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_MASK (0x80U)
102826 #define USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_SHIFT (7U)
102827 /*! npkt0_fc_disable - '0': USB3 responses with NumPkts equal to 0 will be treated as a flow control
102828  *    condition. '1': USB3 responses with NumPkts equal to 0 will not be treated as a flow control
102829  *    condition
102830  */
102831 #define USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_MASK)
102832 #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_MASK (0x100U)
102833 #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_SHIFT (8U)
102834 /*! trb_cache_invalide_en - '0': Disable internal TRB cache invalidation. '1': Enable internal TRB
102835  *    cache invalidation auto detect function. This will allow engine to handle more than 4 TRBs per
102836  *    packet
102837  */
102838 #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_MASK)
102839 #define USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_MASK (0x200U)
102840 #define USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_SHIFT (9U)
102841 /*! in_npkt_pace_disable - Setting this bit to '1' will force the transfer engine state machine to
102842  *    exit the CPL_WAIT state. This is designed to avoid unexpected deadlock in CPL_WAIT state
102843  */
102844 #define USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_MASK)
102845 #define USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_MASK (0x400U)
102846 #define USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_SHIFT (10U)
102847 /*! flush_2clr_valid_en - This bit is modified to support PPTB0, LPT and CP for a feature that we
102848  *    will clear the single IN EP array based on ISO flush or short flush. '0': Indicate that we do
102849  *    not need to clear IN EP array based on flush conditions. '1': indicate that we do clear IN EP
102850  *    array based on flush conditions
102851  */
102852 #define USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_MASK)
102853 #define USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_MASK (0x800U)
102854 #define USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_SHIFT (11U)
102855 /*! ctrl_reg_clr_bndry - Setting this bit to '1' will force the transfer engine to set the packet
102856  *    boundary flag. This flag is an important flag, which may cause a deadlock. This is a safety
102857  *    feature that we have plugged in
102858  */
102859 #define USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_MASK)
102860 #define USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_MASK (0x1000U)
102861 #define USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_SHIFT (12U)
102862 /*! ENT_en - '0': ENT bit is ignored. '1': ENT bit is processed. The transfer engine will service the next TRB
102863  */
102864 #define USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_MASK)
102865 #define USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_MASK (0x2000U)
102866 #define USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_SHIFT (13U)
102867 /*! single_burst_en - '0': Bulk and interrupt endpoints use burst size defined by endpoint context.
102868  *    '1: Force the Bulk and Interrupt endpoints to use a burst size of 1
102869  */
102870 #define USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_MASK)
102871 #define USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_MASK (0x4000U)
102872 #define USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_SHIFT (14U)
102873 /*! xfer_block_en - Not used. XFER engine has a new function that provides a support to ISO EP
102874  *    within a long PCIe delayed system. The long delay can cause missing service interval while pending
102875  *    response has not all been returned. This bit enables engine to identify a MSI condition and
102876  *    store the context bit for a pending response so that we can process a MSI event when pending
102877  *    response received. '0': disable this function, '1': enable this function
102878  */
102879 #define USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_MASK)
102880 #define USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_MASK (0x8000U)
102881 #define USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_SHIFT (15U)
102882 /*! iso_0len_lpf_en - Enables a special internal state branch condition for periodic EP during its
102883  *    transfer ring process. If we have identified that the next TRB is a non DMAnable TRB such as
102884  *    LINK TRB, or Event data TRB, then this bit enables XFER engine to continue process the next TRB
102885  *    as if the ENT bit of the TRB is set. '0': disable, '1': enable
102886  */
102887 #define USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_MASK)
102888 #define USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_MASK (0x10000U)
102889 #define USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_SHIFT (16U)
102890 /*! set_addr_err_en - '0': Disable error reporting if a SETUP TRB contains the following: bRequest =
102891  *    SET_ADDRES, bmRequestType = (DTD) Host-to-device, Type = Standard, Recipient = Device. '1':
102892  *    Enable error reporting for this case
102893  */
102894 #define USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_MASK)
102895 #define USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_MASK (0x20000U)
102896 #define USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_SHIFT (17U)
102897 /*! phase1_imd_en - Enable a special branch condition of the XFER ring process state. This is to
102898  *    ensure that we have a DMA request issued to DMA engine during a PHASE1 process of the TTE. '0':
102899  *    disabled, '1': enabled
102900  */
102901 #define USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_MASK)
102902 #define USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_MASK (0x40000U)
102903 #define USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_SHIFT (18U)
102904 /*! no_op_as_td - This bit is modified to enable the NO_OP TRB as a TD when Missing Service Interval
102905  *    Error has encountered. This is only for PPT B0, LPT and CB. '0': disable, '1': enable
102906  */
102907 #define USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_MASK)
102908 #define USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_MASK (0x80000U)
102909 #define USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_SHIFT (19U)
102910 /*! short_err_4msi_en - This bit is modified to enable a feature where we can control whether or not
102911  *    to report an event with completion code of Missed Service Error when a short packet response
102912  *    has been received not in the expected service interval. '0': Disable this function so that the
102913  *    xHC engine will report an event with completion code of Short packet indication and another
102914  *    event with MSE at the end of the TD, '1': Enables all completion event that supposedly is short
102915  *    to the MSE
102916  */
102917 #define USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_MASK)
102918 #define USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_MASK (0x100000U)
102919 #define USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_SHIFT (20U)
102920 /*! deadlock_detect_en - '0': Disable timeout of TRB error processing. '1': Enable timeout of a TRB
102921  *    processing in few critical states that possibly have a deadlock for unexpected reason. A
102922  *    vendor defined completion code is generated in the event of a timeout during TRB processing
102923  */
102924 #define USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_MASK)
102925 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_MASK (0x200000U)
102926 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_SHIFT (21U)
102927 /*! disable_erdy_drop - '0': Drop ERDYs received when not in a flow control state. '1': Do not drop
102928  *    ERDYs received when not in a flow control state. Note: We typically drop unexpected ERDY
102929  */
102930 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_MASK)
102931 #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_MASK (0x400000U)
102932 #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_SHIFT (22U)
102933 /*! cpl_db_rang_en - Setting this bit to '1' will force an internal doorbell ring on the EP that it has received a response
102934  */
102935 #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_MASK)
102936 #define USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_MASK (0x800000U)
102937 #define USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_SHIFT (23U)
102938 /*! write_erdp_lo - When ERDP register is updated by software, it is expected as an atomic function
102939  *    since this is a 64-bit register. It is expected, that the ERDP (64-bit register) is updated
102940  *    together when ERDP high 32 is written. We have this bit designed to ignore the atomic operation
102941  *    required from software for ERDP low 32 bits. When this bit is set to '1', it will update the
102942  *    ERDP low 32 bits when software issues a CPU write to the ERDP low 32 bits. '0': not ignore,
102943  *    '1': ignore atomic operation
102944  */
102945 #define USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_MASK)
102946 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_MASK (0x1000000U)
102947 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_SHIFT (24U)
102948 /*! disable_imd_4nodma - This is a special internal branch condition control in XFER engine which
102949  *    does the EP transfer ring process. When this bit is set, the XFER will not continue even if the
102950  *    next TRB is identified as a non DMA TRB. The engine will then wait for the next scheduled
102951  *    request for this EP. '0': Disable, '1': Enable the branch condition
102952  */
102953 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_MASK)
102954 #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_MASK (0x2000000U)
102955 #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_SHIFT (25U)
102956 /*! trb_err_rm_db_en - This is a special internal branch condition control in XFER engine which does
102957  *    the EP transfer ring process. When this bit is set a retry condition identified by completion
102958  *    engine will cause XFER engine to stop what it is currently in progress and start over from
102959  *    IDLE state. '0': Disable, '1': Enable the branch condition
102960  */
102961 #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_MASK)
102962 #define USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_MASK (0x4000000U)
102963 #define USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_SHIFT (26U)
102964 /*! ep_halt_2retry_en - This is a special internal condition enable for CPL engine which it enables
102965  *    all EP halt conditions detected to cause the proper actions in a response. '0': Disabled, '1':
102966  *    Enabled. Note: Only default condition of '1' is valid
102967  */
102968 #define USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_MASK)
102969 #define USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_MASK (0x8000000U)
102970 #define USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_SHIFT (27U)
102971 /*! enable_noop_upd - This bit has been modified for its usage since PPT A0. It is used to allow
102972  *    NO-OP TRB to be treated in a same way as link TRB. In other words, it will update the internal
102973  *    context when it is fetched while the internal context cache TRB FIFO is empty. '0': Disable the
102974  *    function, '1': Enable the cache function
102975  */
102976 #define USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_MASK)
102977 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_MASK (0x10000000U)
102978 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_SHIFT (28U)
102979 /*! disable_cpl_sst_ppipe_err - '0': Enable the error check, '1': Disable the error check for prime
102980  *    PIPE stream state. It will generate a transfer event with prime PIPE error completion code if
102981  *    an error is detected
102982  */
102983 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_MASK)
102984 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_MASK (0x20000000U)
102985 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_SHIFT (29U)
102986 /*! disable_cpl_sst_mdata_err - '0': Enable the error check. '1': Disable the error check for Data
102987  *    Move stream state. It will generate a transfer event with prime PIPE error completion code if
102988  *    an error is detected
102989  */
102990 #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_MASK)
102991 #define USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_MASK (0x40000000U)
102992 #define USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_SHIFT (30U)
102993 /*! usb2_nak_auto_detect_reg_en - '0': Disables a special function which detects NAK received and
102994  *    goes into a single packet pace mode so that we do not burst ahead. '1': Enables a special
102995  *    function which detects NAK received and goes into a single packet pace mode so that we do not burst
102996  *    ahead
102997  */
102998 #define USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_MASK)
102999 #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_MASK (0x80000000U)
103000 #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_SHIFT (31U)
103001 /*! trb_pace_en - Must be set to '0'
103002  */
103003 #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_MASK)
103004 /*! @} */
103005 
103006 /*! @name XECP_HOST_CTRL_SCH_REG1 - Host Control Scheduler */
103007 /*! @{ */
103008 #define USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_MASK (0x1U)
103009 #define USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_SHIFT (0U)
103010 /*! poll_delay_dis - Host Control Scheduler: Disable poll delay function
103011  */
103012 #define USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_MASK)
103013 #define USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_MASK (0x2U)
103014 #define USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_SHIFT (1U)
103015 /*! trm_active_in_ep_valid - Host Control Scheduler: Disable TRM active IN EP valid check function
103016  */
103017 #define USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_MASK)
103018 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_MASK  (0x4U)
103019 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_SHIFT (2U)
103020 /*! sch_2 - Host Control Scheduler: Disable TTE IN overlap
103021  */
103022 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_2(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_MASK)
103023 #define USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_MASK (0x8U)
103024 #define USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_SHIFT (3U)
103025 /*! tte_enable_introut_overlap_stop - Host Control Scheduler: tte_enable_introut_overlap_stop
103026  */
103027 #define USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_MASK)
103028 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_MASK (0x30U)
103029 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_SHIFT (4U)
103030 /*! sch_sort_pattern - Host Control Scheduler: Search priority. Possible values: '00': Sort by
103031  *    Interval then ISO over interrupt, '01','10','11': Experimental sort algorithms
103032  */
103033 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_MASK)
103034 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_MASK (0x40U)
103035 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_SHIFT (6U)
103036 /*! sch_async_out_max_perf - Host Control Scheduler: Enable maximal out performance (may cause unfairness or short term starvation)
103037  */
103038 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_MASK)
103039 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_MASK (0x80U)
103040 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_SHIFT (7U)
103041 /*! sch_async_1pkt_perf - Host Control Scheduler: Disable burst limit '1' for async in presence of another port periodic packets
103042  */
103043 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_MASK)
103044 #define USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_MASK (0x100U)
103045 #define USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_SHIFT (8U)
103046 /*! scratch_pad_en - Command Manager: Enables scratch pad function
103047  */
103048 #define USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_MASK)
103049 #define USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_MASK  (0x600U)
103050 #define USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_SHIFT (9U)
103051 /*! maxEP - Command Manager: Allow dynamically setting different max EP allowed. The max EP
103052  *    supported scales with the scratch pad size. This allows driver to allocate small memory sizes if it
103053  *    needed. 0: 32 EPs, 1: 16 EPs, 2: 8 EPs, 3: 4 EPs
103054  */
103055 #define USB3_XECP_HOST_CTRL_SCH_REG1_maxEP(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_MASK)
103056 #define USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_MASK (0x1800U)
103057 #define USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_SHIFT (11U)
103058 /*! cache_size_ctrl - Command Manager: Context cache enable
103059  */
103060 #define USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_MASK)
103061 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_MASK  (0x2000U)
103062 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_SHIFT (13U)
103063 /*! TTE_0 - TTE: Disable interrupt complete split limit to 3 micro frames
103064  */
103065 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_MASK)
103066 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_MASK  (0x4000U)
103067 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_SHIFT (14U)
103068 /*! TTE_1 - TTE: Disable checking of missed microframes
103069  */
103070 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_MASK)
103071 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_MASK  (0x8000U)
103072 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_SHIFT (15U)
103073 /*! TTE_2 - TTE: Disable split error request to TRM on unserved interrupt-INs
103074  */
103075 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_MASK)
103076 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_MASK  (0x30000U)
103077 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_SHIFT (16U)
103078 /*! TTE_3 - TTE: Reserved
103079  */
103080 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_MASK)
103081 #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_MASK (0x40000U)
103082 #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_SHIFT (18U)
103083 /*! disable_gl_hub_iso_fix - TTE: disable_gl_hub_iso_fix
103084  */
103085 #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_MASK)
103086 #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_MASK (0x80000U)
103087 #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_SHIFT (19U)
103088 /*! disable_gl_hub_int_fix - TTE: disable_gl_hub_int_fix
103089  */
103090 #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_MASK)
103091 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_MASK  (0x100000U)
103092 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_SHIFT (20U)
103093 /*! TTE_4 - TTE: Reserved
103094  */
103095 #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_MASK)
103096 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_MASK (0x200000U)
103097 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_SHIFT (21U)
103098 /*! sch_stop_serve_nc - Host Control Scheduler: Enable Stop serving packets to disabled port
103099  */
103100 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_MASK)
103101 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_MASK (0xC00000U)
103102 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_SHIFT (22U)
103103 /*! sch_cclk_prdc_done_check - Host Control Scheduler: sch_cclk_prdc_done_check
103104  */
103105 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_MASK)
103106 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_MASK (0x1000000U)
103107 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_SHIFT (24U)
103108 /*! sch_async_prdc_cc_dis - Host Control Scheduler: sch_async_prdc_cc_dis
103109  */
103110 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_MASK)
103111 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_MASK (0x2000000U)
103112 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_SHIFT (25U)
103113 /*! sch_tt_overlap_all_ins - Host Control Scheduler: sch_tt_overlap_all_ins
103114  */
103115 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_MASK)
103116 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_MASK (0x4000000U)
103117 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_SHIFT (26U)
103118 /*! sch_async_1pkt_split_pref - Host Control Scheduler: sch_async_1pkt_split_pref
103119  */
103120 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_MASK)
103121 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_MASK (0x8000000U)
103122 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_SHIFT (27U)
103123 /*! sch_block_pending_en - Host Control Scheduler: sch_block_pending_en
103124  */
103125 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_MASK)
103126 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_MASK (0xF0000000U)
103127 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_SHIFT (28U)
103128 /*! sch_limit_prdc - Host Control Scheduler: sch_limit_prdc
103129  */
103130 #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_MASK)
103131 /*! @} */
103132 
103133 /*! @name XECP_HOST_CTRL_ODMA_REG - Host Control ODMA */
103134 /*! @{ */
103135 #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_MASK (0x1U)
103136 #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_SHIFT (0U)
103137 /*! EP_trans_timeout_en - '0': Enables the EP Transaction Timeout Function, '1': Disables the EP Transaction Timeout Function
103138  */
103139 #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_MASK)
103140 #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_MASK (0x6U)
103141 #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_SHIFT (1U)
103142 /*! EP_trans_timeout_len - Controls the duration of the EP Transaction Timeout (depends on the
103143  *    settings of EP Transaction Base Timer (bit[12])). Possible values: 0: 64us ([12]=0) or 8ms ([12]=1)
103144  *    EP Transaction Timeout, 1: 32us ([12]=0) or 4ms ([12]=1) EP Transaction Timeout, 2: 16us
103145  *    ([12]=0) or 2ms ([12]=1) EP Transaction Timeout, 3: EP Transaction Timer is DISABLED
103146  */
103147 #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_MASK)
103148 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_MASK (0x8U)
103149 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_SHIFT (3U)
103150 /*! odma_rd_to_idle - Setting this field generates a pulse that returns the Out DMA Read Finite State Machine into the IDLE state
103151  */
103152 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_MASK)
103153 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_MASK (0x10U)
103154 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_SHIFT (4U)
103155 /*! odma_resp_to_idle - Setting this field generates a pulse that returns the Out DMA Response Finite State Machine into the IDLE state
103156  */
103157 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_MASK)
103158 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_MASK (0x20U)
103159 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_SHIFT (5U)
103160 /*! odma_completion_to_idle - Setting this field generates a pulse that returns the Out DMA Completion Finite State Machine into the IDLE state
103161  */
103162 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_MASK)
103163 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_MASK (0x40U)
103164 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_SHIFT (6U)
103165 /*! odma_set_addr_to_idle - Setting this field generates a pulse that returns the Out DMA Set Address Finite State Machine into the IDLE state
103166  */
103167 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_MASK)
103168 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_MASK (0x80U)
103169 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_SHIFT (7U)
103170 /*! odma_7 - Setting this field generates a pulse that implicitly returns all of the Out DMA ACK credits on all ports
103171  */
103172 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_7(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_MASK)
103173 #define USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_MASK (0x100U)
103174 #define USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_SHIFT (8U)
103175 /*! clear_cntx_locks - Setting this field generates a pulse that clears the ownership of the context
103176  *    semaphore that is shared between the Out DMA Response and Completion Finite State Machines
103177  */
103178 #define USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_MASK)
103179 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_MASK (0x200U)
103180 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_SHIFT (9U)
103181 /*! odma_9 - Setting this field prohibits the Set Address Finite State Machine from being flow
103182  *    controlled when an ACK with NPKT=0 is received in response to the SETUP DP initiated during
103183  *    SET_ADDRESS
103184  */
103185 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_9(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_MASK)
103186 #define USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_MASK (0x400U)
103187 #define USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_SHIFT (10U)
103188 /*! ep_timer_tick - Setting this field will disable the EP Transaction Timer function when the
103189  *    Command Manager is performing a Stop Endpoint Command or when the LTSSM is in Recovery
103190  */
103191 #define USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_MASK)
103192 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_MASK (0x800U)
103193 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_SHIFT (11U)
103194 /*! odma_11 - Setting this field will prohibit the Set Address Finite State Machine Credit Handshake with TTE Logic
103195  */
103196 #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_11(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_MASK)
103197 #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_MASK (0x1000U)
103198 #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_SHIFT (12U)
103199 /*! EP_base_timer - '0': Employs a 1us EP Transaction Base Timer. Enables a Timeout range from 16us
103200  *    to 64us '1': Employs a 125us EP Transaction Base Timer. Enables a Timeout range from 2ms to 8ms
103201  */
103202 #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_MASK)
103203 #define USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_MASK (0x2000U)
103204 #define USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_SHIFT (13U)
103205 /*! ACK_crd_check_en - '0': Disable the ACK credit check function '1': Enable the ACK credit check function that ODMA provides
103206  */
103207 #define USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_MASK)
103208 #define USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_MASK (0x4000U)
103209 #define USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_SHIFT (14U)
103210 /*! speed_up_timeout - '0': Disable the speed up transaction timeout function. '1': Enable the
103211  *    transaction timeout speed up based on no-connect detected on a particular port
103212  */
103213 #define USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_MASK)
103214 /*! @} */
103215 
103216 /*! @name XECP_HOST_CTRL_IDMA_REG - Host Control IDMA */
103217 /*! @{ */
103218 #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_MASK (0x1U)
103219 #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_SHIFT (0U)
103220 /*! EP_trans_timeout_en - '0': Enables the EP Transaction Timeout Function, '1': Disables the EP Transaction Timeout Function
103221  */
103222 #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_MASK)
103223 #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_MASK (0x6U)
103224 #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_SHIFT (1U)
103225 /*! EP_timer_tick - '00': 1us/125us/1ms/4ms EP Timer Tick '01': 2us/250us/2ms/8ms EP Timer Tick
103226  *    '10': 4us/500us/4ms/16ms EP Timer Tick '11': Disabled EP Timer Tick
103227  */
103228 #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_MASK)
103229 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_MASK (0x8U)
103230 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_SHIFT (3U)
103231 /*! idma_ptr_buf_room_restore_pulse - Setting this field generates a pulse that clears all the Read
103232  *    and Write Pointers associated with the various DMA Address FIFOs causing them to appear empty
103233  */
103234 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_MASK)
103235 #define USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_MASK (0x10U)
103236 #define USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_SHIFT (4U)
103237 /*! restore_rdp_credits_pulse - Setting this field generates a pulse that implicitly returns all of the IN DMA Data Packet credits on all ports
103238  */
103239 #define USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_MASK)
103240 #define USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_MASK (0x20U)
103241 #define USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_SHIFT (5U)
103242 /*! ack_pst_clr_pulse - Setting this field generates a pulse that returns the IN DMA Acknowledge Finite State Machine into the IDLE state
103243  */
103244 #define USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_MASK)
103245 #define USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_MASK (0x40U)
103246 #define USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_SHIFT (6U)
103247 /*! dm_pst_clr_pulse - Setting this field generates a pulse that returns the IN DMA Data Mover Finite State Machine into the IDLE state
103248  */
103249 #define USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_MASK)
103250 #define USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_MASK (0x80U)
103251 #define USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_SHIFT (7U)
103252 /*! clear_cntx_locks - Setting this field generates a pulse that clears the ownership of the context
103253  *    semaphore that is shared between the IN DMA Acknowledge and Data Mover Finite State Machines
103254  */
103255 #define USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_MASK)
103256 #define USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_MASK (0x100U)
103257 #define USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_SHIFT (8U)
103258 /*! compliance_iso_enable - Setting this field enables the Compliance Isochronous mode of operation.
103259  *    It bounds the upper limit on the NPKT field for all ISO Acknowledgments generated from the
103260  *    Host to the value of 2.
103261  */
103262 #define USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_MASK)
103263 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_MASK (0x200U)
103264 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_SHIFT (9U)
103265 /*! idma_9 - Setting this field will disable the EP Transaction Timer function when the Command
103266  *    Manager is performing a Stop Endpoint Command or when the LTSSM is in Recovery
103267  */
103268 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_9(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_MASK)
103269 #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_MASK (0x400U)
103270 #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_SHIFT (10U)
103271 /*! timer_tick0 - '0': Employs a 1us EP Transaction Base Timer. Enables a Timeout range from 16us to
103272  *    64us. '1': Employs a 125us EP Transaction Base Timer. Enables a Timeout range from 2ms to 8ms
103273  */
103274 #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_MASK)
103275 #define USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_MASK (0x800U)
103276 #define USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_SHIFT (11U)
103277 /*! seq_num_adj_on_nrdy - '0': Enable sequence number adjustment on NRDY received for USB3 when we
103278  *    are expecting a response. '1': Enable sequence number adjustment on any NRDY received for USB3.
103279  */
103280 #define USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_MASK)
103281 #define USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_MASK (0x1000U)
103282 #define USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_SHIFT (12U)
103283 /*! speed_up_timeout - '0': Disable the speed up transaction timeout function. '1': Enable the
103284  *    transaction timeout speed up based on no-connect detected on a particular port
103285  */
103286 #define USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_MASK)
103287 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_MASK (0x2000U)
103288 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_SHIFT (13U)
103289 /*! idma_13 - Disable dropping all deferred packets on ISO Endpoints
103290  */
103291 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_13(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_MASK)
103292 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_MASK (0x4000U)
103293 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_SHIFT (14U)
103294 /*! idma_14 - Disable drop spurious DP when EP is in flow conrtrol
103295  */
103296 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_14(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_MASK)
103297 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_MASK (0x8000U)
103298 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_SHIFT (15U)
103299 /*! idma_15 - Disable drop spurious DP when i_npkt==0
103300  */
103301 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_15(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_MASK)
103302 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_MASK (0x10000U)
103303 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_SHIFT (16U)
103304 /*! idma_ptr_buf_room_set - '0': Default IDMA Pointer Buffer Room to 8 : Requires strobe of
103305  *    host_ctrl_idma_reg[3](idma_ptr_buf_room_restore_pulse) to take effect, '1': Default IDMA Pointer
103306  *    Buffer Room to 4 : Requires strobe of host_ctrl_idma_reg[3](idma_ptr_buf_room_restore_pulse) to
103307  *    take effect
103308  */
103309 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_MASK)
103310 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_MASK (0x20000U)
103311 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_SHIFT (17U)
103312 /*! idma_17 - '0': All ACK ACKs are put in the Periodic Header FIFO in XPPE, '1': Only Periodic ACK
103313  *    ACKs are put in the Periodic Header FIFO in XPPE
103314  */
103315 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_17(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_MASK)
103316 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_MASK (0x40000U)
103317 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_SHIFT (18U)
103318 /*! idma_addr_fifo_flush_bit - Flush IDMA Address FIFO strobe
103319  */
103320 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_MASK)
103321 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_MASK (0xF80000U)
103322 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_SHIFT (19U)
103323 /*! idma_23_19 - Port Number of Address FIFO to Flush
103324  */
103325 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_MASK)
103326 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_MASK (0x1000000U)
103327 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_SHIFT (24U)
103328 /*! idma_24 - '0': Flush an Async Address FIFO, '1': Flush a Periodic Address FIFO
103329  */
103330 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_24(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_MASK)
103331 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_MASK (0x2000000U)
103332 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_SHIFT (25U)
103333 /*! idma_25 - Flush TTE Address FIFO
103334  */
103335 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_25(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_MASK)
103336 #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_MASK (0x4000000U)
103337 #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_SHIFT (26U)
103338 /*! timer_tick1 - Allows to select the EP Timer Tick to be either the 1us timer tick or the 125us
103339  *    timer tick or the 1ms timer tick or the 4ms timer tick based on the setting of this bit and bit
103340  *    10 of this register. The encoding is as follows (bit{[26],[10]}): '00' : 1us EP Timer Tick,
103341  *    '01' : 125us EP Timer Tick, '10' : 1ms EP Timer Tick, '11' : 4ms EP Timer Tick
103342  */
103343 #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_MASK)
103344 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_MASK (0x8000000U)
103345 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_SHIFT (27U)
103346 /*! idma_27 - '0': Drop Deferred Stream Reject TPs. (default) (Bug #5434), '1': Allow Deferred Stream Reject TPs
103347  */
103348 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_27(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_MASK)
103349 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_MASK (0x10000000U)
103350 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_SHIFT (28U)
103351 /*! idma_28 - '0': Drop Deferred Ack/Ack TPs. (default) (Bug #5481), '1': Allow Deferred Ack/Ack TPs
103352  */
103353 #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_28(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_MASK)
103354 #define USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_MASK (0x20000000U)
103355 #define USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_SHIFT (29U)
103356 /*! db_event_gen_en - Used in Doorbell Manager. '0': Do not generate an event. '1': Enable an event
103357  *    generated with completion code TRB_CMPL_ENDPOINT_NOT_ENABLED_ERR when a doorbell ring on an
103358  *    EP, which has not running or stop state.
103359  */
103360 #define USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_MASK)
103361 #define USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_MASK (0x40000000U)
103362 #define USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_SHIFT (30U)
103363 /*! event_priority - Used in Event Manager. '0': CPL Engine priority over XFER Manager, '1': XFER Manager priority over CPL Engine.
103364  */
103365 #define USB3_XECP_HOST_CTRL_IDMA_REG_event_priority(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_MASK)
103366 #define USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_MASK (0x80000000U)
103367 #define USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_SHIFT (31U)
103368 /*! event_fifo_dis - Used in Event Manager. '0': Enable single ring optimization, '1': Disable single ring optimization.
103369  */
103370 #define USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_MASK)
103371 /*! @} */
103372 
103373 /*! @name XECP_HOST_CTRL_PORT_CTRL - Global Port Control */
103374 /*! @{ */
103375 #define USB3_XECP_HOST_CTRL_PORT_CTRL_res1_MASK  (0xFU)
103376 #define USB3_XECP_HOST_CTRL_PORT_CTRL_res1_SHIFT (0U)
103377 /*! res1 - Reserved to 1 (reserved for PP)
103378  */
103379 #define USB3_XECP_HOST_CTRL_PORT_CTRL_res1(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_res1_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_res1_MASK)
103380 #define USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_MASK (0x1F0U)
103381 #define USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_SHIFT (4U)
103382 #define USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_MASK)
103383 #define USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_MASK (0x800U)
103384 #define USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_SHIFT (11U)
103385 /*! PCIe_gasket - Reserved to '1'. Note: An internal register bit for PCIe gasket. It is only valid for value of '1'
103386  */
103387 #define USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_MASK)
103388 #define USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_MASK (0x1000U)
103389 #define USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_SHIFT (12U)
103390 /*! enable_itp_xmt - Bit(s) of this field are designated to individually control each USB3 port to
103391  *    enable ITP transmission. 0: Do not Transmit any ITP. 1: Transmit ITP
103392  */
103393 #define USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_MASK)
103394 #define USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_MASK (0x1E000U)
103395 #define USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_SHIFT (13U)
103396 /*! hbuf_water_mark_reg_cclk - This 4-bit register is designed as a water mark for when to turn on
103397  *    link FC credit return disable. This is used in xhc_prot_rppe.v for receive buffer management.
103398  *    We have 8 header credit in per port receive buffer. When buffer received enough packets, it
103399  *    will need to disable the link credit FC return in order to balance the processing delay within
103400  *    DMA engine. 0: Always enable link credit FC return, 1-8: Water mark value.
103401  */
103402 #define USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_MASK)
103403 #define USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_MASK (0x20000U)
103404 #define USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_SHIFT (17U)
103405 /*! overflow_sys_err_en - '0': Disable error generation. '1': Enable to generate a host system error when receive buffer overflow on any ports
103406  */
103407 #define USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_MASK)
103408 #define USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_MASK (0x40000U)
103409 #define USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_SHIFT (18U)
103410 /*! rd_wr_addr_conflict_en - rd_wr_addr_conflict_en
103411  */
103412 #define USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_MASK)
103413 #define USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_MASK (0x80000U)
103414 #define USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_SHIFT (19U)
103415 /*! lock_header_data_en - lock_header_data_en
103416  */
103417 #define USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_MASK)
103418 /*! @} */
103419 
103420 /*! @name XECP_AUX_CTRL_REG - AUX Reset Control */
103421 /*! @{ */
103422 #define USB3_XECP_AUX_CTRL_REG_force_fd_rst_MASK (0x3U)
103423 #define USB3_XECP_AUX_CTRL_REG_force_fd_rst_SHIFT (0U)
103424 /*! force_fd_rst - Writing to this field a value of 2'b11 will cause a fundamental reset. The only valid write values are 2'b11 or 2'b00
103425  */
103426 #define USB3_XECP_AUX_CTRL_REG_force_fd_rst(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_force_fd_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_force_fd_rst_MASK)
103427 #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_MASK (0x4U)
103428 #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_SHIFT (2U)
103429 /*! ignore_perst_4fd_rst - When fundamental reset is asserted during AUX power up, if this bit is
103430  *    set, then we will ignore PERST# such that purely wait for timeout to deassert fundamental reset.
103431  */
103432 #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_MASK)
103433 #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_MASK (0x8U)
103434 #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_SHIFT (3U)
103435 /*! ignore_perst_4main_pwrup - When set to '1' ignore waiting for PERST# deassertion during main power show down.
103436  */
103437 #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_MASK)
103438 #define USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_MASK (0x10U)
103439 #define USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_SHIFT (4U)
103440 /*! pm_ctrl_main_rst_en - When set to '1' allow main power off condition to trigger a main power domain reset
103441  */
103442 #define USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_MASK)
103443 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_MASK (0x20U)
103444 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_SHIFT (5U)
103445 /*! ignore_main_pwrup_rst - When set to '1', it enables the reset isolation function that we have added during HC reset or Per port reset.
103446  */
103447 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_MASK)
103448 #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_MASK (0x40U)
103449 #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_SHIFT (6U)
103450 /*! ignore_warm_rst_2usb_phy - When set to '1' ignore warm reset to the USB PHY
103451  */
103452 #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_MASK)
103453 #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_MASK (0x80U)
103454 #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_SHIFT (7U)
103455 /*! ignore_hc_warm_rst_2usb_phy - When set to '1' ignore HC reset to the USB PHY
103456  */
103457 #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_MASK)
103458 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_MASK (0x100U)
103459 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_SHIFT (8U)
103460 /*! ignore_main_pwrup_2pcie_phy - When set to '1' ignore main power up reset to PCIe PHY
103461  */
103462 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_MASK)
103463 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_MASK (0x200U)
103464 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_SHIFT (9U)
103465 /*! ignore_main_pwrup_2pcore - When set to '1' ignore main power up reset to PCIe core
103466  */
103467 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_MASK)
103468 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_MASK (0x400U)
103469 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_SHIFT (10U)
103470 /*! ignore_main_pwrup_4u2port - When set to '1' ignore main power up reset to USB2 port logic
103471  */
103472 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_MASK)
103473 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_MASK (0x800U)
103474 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_SHIFT (11U)
103475 /*! ignore_main_pwrup_4u3port - When set to '1' ignore main power up reset to USB3 port logic
103476  */
103477 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_MASK)
103478 #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_MASK (0x1000U)
103479 #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_SHIFT (12U)
103480 /*! ignore_warm_rst_4u3port - When set to '1' ignore warm reset to the USB3 port logic
103481  */
103482 #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_MASK)
103483 #define USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_MASK (0x2000U)
103484 #define USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_SHIFT (13U)
103485 /*! ignore_hot_rst_4u3port - When set to '1' ignore hot reset to the USB3 port logic
103486  */
103487 #define USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_MASK)
103488 #define USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_MASK (0x4000U)
103489 #define USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_SHIFT (14U)
103490 /*! pcie_linkdown_rst_en - When set to '1' allow PCIe link down to cause a reset to the rest of the core as the HC reset would
103491  */
103492 #define USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_MASK)
103493 #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_MASK (0x8000U)
103494 #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_SHIFT (15U)
103495 /*! ignore_warm_rst_4uphy_pon - When set to '1' ignore warm reset of the portSC to the USB PHY power on reset
103496  */
103497 #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_MASK)
103498 #define USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_MASK (0x10000U)
103499 #define USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_SHIFT (16U)
103500 /*! ignore_mac_phy_pipe_rst - When set to '1' ignore the LTSSM of USB link state transition caused reset to USB PHY PIPE reset
103501  */
103502 #define USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_MASK)
103503 #define USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_MASK (0x20000U)
103504 #define USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_SHIFT (17U)
103505 /*! ignore_hc_rst_2pcie_phy - When set to '1' ignore HC reset to the PCIe PHY PIPE reset
103506  */
103507 #define USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_MASK)
103508 #define USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_MASK (0x40000U)
103509 #define USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_SHIFT (18U)
103510 /*! eeprom_load_on_main - When set to '1' enable EEPROM reload on every main power-up
103511  */
103512 #define USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_SHIFT)) & USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_MASK)
103513 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_MASK (0x80000U)
103514 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_SHIFT (19U)
103515 /*! ignore_main_pwrup_hc_2pcore - When set to '1' enable the HC liked reset caused by PCIe link down
103516  *    condition detected. If PCIe link down detected, a link down reset will always be fired to
103517  *    PCIe core.
103518  */
103519 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_MASK)
103520 #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_MASK (0x100000U)
103521 #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_SHIFT (20U)
103522 /*! ignore_hc_warm_rst_4uphy_pon - When set to '1' ignore HC reset to the USB PHY power-on reset
103523  */
103524 #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_MASK)
103525 #define USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_MASK (0x200000U)
103526 #define USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_SHIFT (21U)
103527 /*! ignore_hcreset_4usb2 - When set to '1' ignore HC reset to reset the USB2 Port logic
103528  */
103529 #define USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_MASK)
103530 #define USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_MASK (0x400000U)
103531 #define USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_SHIFT (22U)
103532 /*! cold_rst_n_pulse - When set to '1' allow software to fire a cold reset to USB port logic
103533  */
103534 #define USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_SHIFT)) & USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_MASK)
103535 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_MASK (0x800000U)
103536 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_SHIFT (23U)
103537 /*! ignore_main_pwrup_2usb_phy - When set to '1' ignore main powerup reset to USB PHY PIPE reset
103538  */
103539 #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_MASK)
103540 #define USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_MASK (0x1000000U)
103541 #define USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_SHIFT (24U)
103542 /*! ignore_linkdown_rst_4uport - When set to '1' ignore a port reset that is caused by a USB port link went down.
103543  */
103544 #define USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_MASK)
103545 #define USB3_XECP_AUX_CTRL_REG_fast_sim_rst_MASK (0x2000000U)
103546 #define USB3_XECP_AUX_CTRL_REG_fast_sim_rst_SHIFT (25U)
103547 /*! fast_sim_rst - This bit enables a speed up function or AUX reset at startup. Normally we wait
103548  *    for 20ms after AUX power level has reached. When in speed up mode, we wait only around 3-4us.
103549  *    '0: Disabled, '1: Enabled for fast sim
103550  */
103551 #define USB3_XECP_AUX_CTRL_REG_fast_sim_rst(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_fast_sim_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_fast_sim_rst_MASK)
103552 #define USB3_XECP_AUX_CTRL_REG_ignore_perst_en_MASK (0x4000000U)
103553 #define USB3_XECP_AUX_CTRL_REG_ignore_perst_en_SHIFT (26U)
103554 /*! ignore_perst_en - This bit disables the PERST# to cause an internal reset. '0: enable '1: disable the PERST#
103555  */
103556 #define USB3_XECP_AUX_CTRL_REG_ignore_perst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_perst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_perst_en_MASK)
103557 #define USB3_XECP_AUX_CTRL_REG_perst_4main_en_MASK (0x8000000U)
103558 #define USB3_XECP_AUX_CTRL_REG_perst_4main_en_SHIFT (27U)
103559 /*! perst_4main_en - This bit enables the internal reset control module to immediately start a reset
103560  *    assertion process when PERST# is deasserted without waiting for PCIe device is out of D3
103561  *    state. This is for warm reboot only. The PERST# can still have impact as a reset if the xHC is in
103562  *    D3 and allow PERST# as a powerup reset bit set. '0: disabled '1: enabled PERST# as an
103563  *    immediately reset
103564  */
103565 #define USB3_XECP_AUX_CTRL_REG_perst_4main_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_perst_4main_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_perst_4main_en_MASK)
103566 #define USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_MASK (0x10000000U)
103567 #define USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_SHIFT (28U)
103568 /*! perst_2pwdown_en - This bit enables the AUX PM control module to assert mac_phy_powerdown state
103569  *    to P1 as soon as PERST# is deasserted. If disabled, then the AUX PM control state will follow
103570  *    its nature cause to determine the power down states for PIPE. '0': disabled, '1': enabled.
103571  */
103572 #define USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_MASK)
103573 #define USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_MASK (0x20000000U)
103574 #define USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_SHIFT (29U)
103575 /*! pcie_phy_rst_sel - This bit enables AUX reset control module to assert the pcie_phy_reset either
103576  *    from PIPE reset or from Aux power up reset only. The pcie_phy_reset is an internal signal for
103577  *    CB PHY only. '0': Aux PowerUp Reset, '1': PIPE PHY reset
103578  */
103579 #define USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_SHIFT)) & USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_MASK)
103580 #define USB3_XECP_AUX_CTRL_REG_perst_filter_dis_MASK (0x40000000U)
103581 #define USB3_XECP_AUX_CTRL_REG_perst_filter_dis_SHIFT (30U)
103582 /*! perst_filter_dis - reserved. perst_filter_dis
103583  */
103584 #define USB3_XECP_AUX_CTRL_REG_perst_filter_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_perst_filter_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG_perst_filter_dis_MASK)
103585 /*! @} */
103586 
103587 /*! @name XECP_HOST_BW_OV_SS_REG - Super Speed Bandwidth Overload */
103588 /*! @{ */
103589 #define USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_MASK (0xFFFU)
103590 #define USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_SHIFT (0U)
103591 /*! ss_bw_calc - BW calculation: Overhead per packet for SS BW calculations. See white paper.
103592  */
103593 #define USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_MASK)
103594 #define USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_MASK (0xFFF000U)
103595 #define USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_SHIFT (12U)
103596 /*! max_tt_bw - Max. TT BW allowed. See white paper
103597  */
103598 #define USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_SHIFT)) & USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_MASK)
103599 /*! @} */
103600 
103601 /*! @name XECP_HOST_BW_OV_HS_REG - High Speed TT Bandwidth Overload */
103602 /*! @{ */
103603 #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_MASK (0xFFFU)
103604 #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_SHIFT (0U)
103605 /*! bw_ov_hs_tt - BW calculation: Overhead per packet for HS BW calculations. See white paper.
103606  */
103607 #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_SHIFT)) & USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_MASK)
103608 #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_MASK (0xFFF000U)
103609 #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_SHIFT (12U)
103610 /*! bw_ov_hs - BW calculation: Overhead per packet for HS-TT BW calculations. See white paper.
103611  */
103612 #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_SHIFT)) & USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_MASK)
103613 /*! @} */
103614 
103615 /*! @name XECP_HOST_BW_OV_FS_LS_REG - Bandwidth Overload Full and Low Speed */
103616 /*! @{ */
103617 #define USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_MASK (0xFFFU)
103618 #define USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_SHIFT (0U)
103619 /*! ls_bw_calc - BW calculation: Overhead per packet for LS BW calculations. See white paper.
103620  */
103621 #define USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_MASK)
103622 #define USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_MASK (0xFFF000U)
103623 #define USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_SHIFT (12U)
103624 /*! fs_bw_calc - BW calculation: Overhead per packet for FS BW calculations. See white paper.
103625  */
103626 #define USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_MASK)
103627 /*! @} */
103628 
103629 /*! @name XECP_HOST_BW_OV_SYS_REG - System Bandwidth Overload */
103630 /*! @{ */
103631 #define USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_MASK (0xFFFU)
103632 #define USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_SHIFT (0U)
103633 /*! sys_bw_calc - BW calculation: Overhead per packet for System BW calculations. See white paper.
103634  */
103635 #define USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_MASK)
103636 #define USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_MASK (0xFFF000U)
103637 #define USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_SHIFT (12U)
103638 /*! bw_ov_sys_tt - BW calculation: Overhead per TT packet for System BW calculations. See white paper.
103639  */
103640 #define USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_SHIFT)) & USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_MASK)
103641 /*! @} */
103642 
103643 /*! @name XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG - Scheduler Async Delay */
103644 /*! @{ */
103645 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_MASK (0x7U)
103646 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_SHIFT (0U)
103647 /*! ls_ctrl_delay_def - Low-Speed Control Delay Default (0=125us,1=250us,2=500us,3=1ms,)
103648  */
103649 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_MASK)
103650 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_MASK (0x8U)
103651 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_SHIFT (3U)
103652 /*! ls_ctrl_delay_en - Low-Speed Control Delay Enable
103653  */
103654 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_MASK)
103655 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_MASK (0x70U)
103656 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_SHIFT (4U)
103657 /*! fs_ctrl_delay_def - Full-Speed Control Default (0=125us,1=250us,2=500us,3=1ms,)
103658  */
103659 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_MASK)
103660 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_MASK (0x80U)
103661 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_SHIFT (7U)
103662 /*! fs_ctrl_delay_en - Full-Speed Control Delay Enable
103663  */
103664 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_MASK)
103665 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_MASK (0x700U)
103666 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_SHIFT (8U)
103667 /*! hs_ctrl_delay_def - High-Speed Control Delay Default (0=125us,1=250us,2=500us,3=1ms,)
103668  */
103669 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_MASK)
103670 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_MASK (0x800U)
103671 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_SHIFT (11U)
103672 /*! hs_ctrl_delay_en - High-Speed Control Delay Enable
103673  */
103674 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_MASK)
103675 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_MASK (0x7000U)
103676 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_SHIFT (12U)
103677 /*! fs_bulk_delay_def - Full-Speed Bulk Delay Default (0=125us,1=250us,2=500us,3=1ms,)
103678  */
103679 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_MASK)
103680 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_MASK (0x8000U)
103681 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_SHIFT (15U)
103682 /*! fs_bulk_delay_en - Full-Speed Bulk Delay Enable
103683  */
103684 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_MASK)
103685 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_MASK (0x70000U)
103686 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_SHIFT (16U)
103687 /*! hs_bulk_delay_def - High-Speed Bulk Delay Default (0=125us,1=250us,2=500us,3=1ms,)
103688  */
103689 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_MASK)
103690 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_MASK (0x80000U)
103691 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_SHIFT (19U)
103692 /*! hs_bulk_delay_en - High-Speed Bulk Delay Enable
103693  */
103694 #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_MASK)
103695 /*! @} */
103696 
103697 /*! @name XECP_UPORTS_PON_RST_REG - AUX Power PHY Reset */
103698 /*! @{ */
103699 #define USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_MASK (0xFU)
103700 #define USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_SHIFT (0U)
103701 /*! usb_phy_port_num - Indicates the port number of the USB PHY
103702  */
103703 #define USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_SHIFT)) & USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_MASK)
103704 /*! @} */
103705 
103706 /*! @name XECP_HOST_CTRL_TRM_REG3 - Host Control Transfer Manager (TRM) */
103707 /*! @{ */
103708 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_MASK (0x1U)
103709 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_SHIFT (0U)
103710 /*! cfg_en_cache - '0': Disable cache control, '1': Enable cache control
103711  */
103712 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_MASK)
103713 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_MASK (0x2U)
103714 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_SHIFT (1U)
103715 /*! cfg_en_lookahead - '0': Disable cache control lookahead, '1': Enable cache control lookahead
103716  */
103717 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_MASK)
103718 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_MASK (0x4U)
103719 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_SHIFT (2U)
103720 /*! cfg_en_hit_invalid - '0': Disable cache control hit invalid with invalid CS, '1': Enable cache control hit invalid with invalid CS
103721  */
103722 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_MASK)
103723 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_MASK (0x8U)
103724 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_SHIFT (3U)
103725 /*! cfg_cache_debug - cfg_cache_debug. Available when TRB_CACHE_DEBUG_EN is defined
103726  */
103727 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_MASK)
103728 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_MASK (0x30U)
103729 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_SHIFT (4U)
103730 /*! cfg_en_look_pos - Enable cache control trigger position lookahead
103731  */
103732 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_MASK)
103733 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_MASK (0x40U)
103734 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_SHIFT (6U)
103735 /*! cfg_en_defer_bc - '0': Disable cache control to defer misses on bulk/control EPs. '1': Enable
103736  *    cache control to defer misses on bulk/control EPs
103737  */
103738 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_MASK)
103739 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_MASK (0x80U)
103740 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_SHIFT (7U)
103741 /*! cfg_en_miss_double - '0': Do not enable cache control to double fetch on miss. '1': Enable cache control to double fetch on miss
103742  */
103743 #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_MASK)
103744 #define USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_MASK (0x100U)
103745 #define USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_SHIFT (8U)
103746 /*! cpl_extra_db_rang_en - cpl_extra_db_rang_en
103747  */
103748 #define USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_MASK)
103749 /*! @} */
103750 
103751 /*! @name XECP_AUX_CTRL_REG1 - AUX Power Management Control 1 */
103752 /*! @{ */
103753 #define USB3_XECP_AUX_CTRL_REG1_force_pm_state_MASK (0x1U)
103754 #define USB3_XECP_AUX_CTRL_REG1_force_pm_state_SHIFT (0U)
103755 /*! force_pm_state - When set to '1' force PM state to go to the state indicated in field pm_state
103756  *    (bits [4:1]). This bit is the force PM state register, it is a pulse only (read by software
103757  *    will always give '0')
103758  */
103759 #define USB3_XECP_AUX_CTRL_REG1_force_pm_state(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_force_pm_state_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_force_pm_state_MASK)
103760 #define USB3_XECP_AUX_CTRL_REG1_pm_state_MASK    (0x1EU)
103761 #define USB3_XECP_AUX_CTRL_REG1_pm_state_SHIFT   (1U)
103762 /*! pm_state - Forced power management state can be set here. States encoding: PM_ACTIVE : 4'h0;
103763  *    REQ_CLK_SWITCH_2AUX : 4'h1; DRIVE_PHY_2P2 : 4'h2; WAIT_4WAKE : 4'h3; WAIT_4PERST_DSRT : 4'h4;
103764  *    RATE_CHANGE_2FAST : 4'h5; REQ_CLK_SWITCH_2PCLK : 4'h6; PM_EXIT : 4'h7; WAIT_4PCLK : 4'h8;
103765  *    DRIVE_PHY_STATUS : 4'h9; PM_IDLE : 4'hA; PWRUP_REQ_CLK_SWITCH_2PCLK : 4'hB; RATE_CHANGE_2SLOW : 4'hC;
103766  *    WAIT_4LTSSM_WAIT_DONE : 4'hD; WAIT_4CLK_GATE : 4'hE; IN_P2_TIMEOUT : 4'hF; Those bits have
103767  *    also another functionality: [1]: always_wake_n_en, [2]: timeout_16ms_en, [3]:
103768  *    always_force_clk_sw_en, ![4]: rc_p2_exit_en
103769  */
103770 #define USB3_XECP_AUX_CTRL_REG1_pm_state(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_pm_state_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_pm_state_MASK)
103771 #define USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_MASK (0x20U)
103772 #define USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_SHIFT (5U)
103773 /*! enable_p2_enter - When set to '1' enables the remote wake function by allowing P2 clock/switching and P2 entering
103774  */
103775 #define USB3_XECP_AUX_CTRL_REG1_enable_p2_enter(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_MASK)
103776 #define USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_MASK (0x40U)
103777 #define USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_SHIFT (6U)
103778 /*! p2_overwrite_p1_en - When set to '1' enable P2 overwrite P1 when PCIe core has indicated the
103779  *    transition from P0 to P1. This is to enable entering the even lower power state.
103780  */
103781 #define USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_MASK)
103782 #define USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_MASK (0x80U)
103783 #define USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_SHIFT (7U)
103784 /*! ignore_aux_pme_en - When set to '1' ignore the aux_pm_en reg from PCIe core to continue the remote wake/clock switching support
103785  */
103786 #define USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_MASK)
103787 #define USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_MASK (0x100U)
103788 #define USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_SHIFT (8U)
103789 /*! phystatus_fall_timeout_en - When set to '1' enable PHY status timeout function, which is
103790  *    designed to cover the PCIePHY issue that we may have not be able to detect the PHY status toggle.
103791  *    This is a safety feature in case we have gotten into a deadlock during PHY status acknowledgement.
103792  */
103793 #define USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_MASK)
103794 #define USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_MASK (0x200U)
103795 #define USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_SHIFT (9U)
103796 /*! cclk_gate_disable - When set to '1' disable core clock gating based on low power state entered
103797  */
103798 #define USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_MASK)
103799 #define USB3_XECP_AUX_CTRL_REG1_new_ow_en_MASK   (0x400U)
103800 #define USB3_XECP_AUX_CTRL_REG1_new_ow_en_SHIFT  (10U)
103801 /*! new_ow_en - This bit allows the AUX PM control module to decide whether we entered into P2
103802  *    overwrite condition based on the power down state of the PCIe core is at P1 or the LTSSM of PCIe
103803  *    core is in L1. What we used to have is based on P1 of the PCIe core mac_phy_powerdown signal.
103804  *    This is not correct because LTSSM can be in RX detect to result a P1 of power down state. To
103805  *    preserve our old function, we add this chicken bit. '0': P2Pverwrite function based on PCIe core
103806  *    PIPE mac_phy_powerdown is in P1, '1': P2OverWrite function based on LTSSM in L1
103807  */
103808 #define USB3_XECP_AUX_CTRL_REG1_new_ow_en(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_new_ow_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_new_ow_en_MASK)
103809 #define USB3_XECP_AUX_CTRL_REG1_isolation_en_MASK (0x800U)
103810 #define USB3_XECP_AUX_CTRL_REG1_isolation_en_SHIFT (11U)
103811 /*! isolation_en - When set to '1' enable isolation function for dual power zone.
103812  */
103813 #define USB3_XECP_AUX_CTRL_REG1_isolation_en(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_isolation_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_isolation_en_MASK)
103814 #define USB3_XECP_AUX_CTRL_REG1_pme_status_en_MASK (0x1000U)
103815 #define USB3_XECP_AUX_CTRL_REG1_pme_status_en_SHIFT (12U)
103816 /*! pme_status_en - This bit enables the PCIe status function. '0': xHC as a PCIe device will not
103817  *    generate any PME nor report PME status. '1': xHC as a PCIe device will generate the PME message.
103818  */
103819 #define USB3_XECP_AUX_CTRL_REG1_pme_status_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_pme_status_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_pme_status_en_MASK)
103820 #define USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_MASK (0x2000U)
103821 #define USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_SHIFT (13U)
103822 /*! elecidle_mask_en - This bit enables the AUX PM control state machine to take over txelecidle
103823  *    signal of the PIPE during several special conditions. '0': Disable the mask. '1': Allow mask to
103824  *    mac_phy_txeleidle of PCIe core.
103825  */
103826 #define USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_MASK)
103827 #define USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_MASK (0x4000U)
103828 #define USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_SHIFT (14U)
103829 /*! cfg_pipe_rst_en - Cfg_pipe_rst_en_sync
103830  */
103831 #define USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_MASK)
103832 #define USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_MASK (0x8000U)
103833 #define USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_SHIFT (15U)
103834 /*! cfg_rxdet_p3_en - Cfg_rxdet_p3_en. Enable rxdet U3 mode
103835  */
103836 #define USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_MASK)
103837 #define USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_MASK (0x10000U)
103838 #define USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_SHIFT (16U)
103839 /*! cfg_clk_gate_dis - Cfg_clk_gate_dis
103840  */
103841 #define USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_MASK)
103842 #define USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_MASK (0x20000U)
103843 #define USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_SHIFT (17U)
103844 /*! cfg_usb_p2_en - Cfg_Usb_p2_en
103845  */
103846 #define USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_MASK)
103847 #define USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_MASK (0xC0000U)
103848 #define USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_SHIFT (18U)
103849 /*! cfg_iob_drivestrength - Controls the drive strength of the IO buffer. Set default IO Strength to 8ma
103850  */
103851 #define USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_MASK)
103852 #define USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_MASK (0x100000U)
103853 #define USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_SHIFT (20U)
103854 /*! cfg_pcie_txreg_pd - cfg_pcie_txreg_pd
103855  */
103856 #define USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_MASK)
103857 #define USB3_XECP_AUX_CTRL_REG1_clr_save_flag_MASK (0x200000U)
103858 #define USB3_XECP_AUX_CTRL_REG1_clr_save_flag_SHIFT (21U)
103859 #define USB3_XECP_AUX_CTRL_REG1_clr_save_flag(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_clr_save_flag_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_clr_save_flag_MASK)
103860 #define USB3_XECP_AUX_CTRL_REG1_reservedrw_MASK  (0x400000U)
103861 #define USB3_XECP_AUX_CTRL_REG1_reservedrw_SHIFT (22U)
103862 /*! reservedrw - reserved, RW
103863  */
103864 #define USB3_XECP_AUX_CTRL_REG1_reservedrw(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_reservedrw_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_reservedrw_MASK)
103865 #define USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_MASK (0x800000U)
103866 #define USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_SHIFT (23U)
103867 #define USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_MASK)
103868 #define USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_MASK  (0x1000000U)
103869 #define USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_SHIFT (24U)
103870 /*! clr_ssv_en - When set to '1' clear the SSV flag
103871  */
103872 #define USB3_XECP_AUX_CTRL_REG1_clr_ssv_en(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_MASK)
103873 #define USB3_XECP_AUX_CTRL_REG1_set_ssv_en_MASK  (0x2000000U)
103874 #define USB3_XECP_AUX_CTRL_REG1_set_ssv_en_SHIFT (25U)
103875 /*! set_ssv_en - When set to '1' set the SSV flag.
103876  */
103877 #define USB3_XECP_AUX_CTRL_REG1_set_ssv_en(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_set_ssv_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_set_ssv_en_MASK)
103878 #define USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_MASK (0x4000000U)
103879 #define USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_SHIFT (26U)
103880 /*! powerdown_p1_en - This is a test/control bit. This bit is designed to control the lowest
103881  *    powerdown state of the PCIe that AUX PM module signaled to PIPE is P1. '0': drive as normal
103882  *    operation. '1': always drive to P1 instead of P2
103883  */
103884 #define USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_MASK)
103885 #define USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_MASK (0x8000000U)
103886 #define USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_SHIFT (27U)
103887 /*! use_perst_4fd_rst - Enable AUX reset module to treat every PERST# as a fundamental reset '0': disabled, '1': enabled
103888  */
103889 #define USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_MASK)
103890 #define USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_MASK (0x10000000U)
103891 #define USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_SHIFT (28U)
103892 /*! direct_rate_pass_en - Disable the overwrite function in AUX PM control module for its initiated
103893  *    rate change. '0': allows AUX PM control module to initiate its PCIE rate change when it needs
103894  *    to enable P2 overwrite P1 function. '1': AUX PM control module will not alter the PCIe rate
103895  *    change function .
103896  */
103897 #define USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_MASK)
103898 #define USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_MASK (0x20000000U)
103899 #define USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_SHIFT (29U)
103900 /*! extend_phystatus_en - This bit is there for a bug fix where we need to ensure that phystatus did
103901  *    not get lost during the rate change where clock switch logic takes some cycles to complete;
103902  *    such that the PCie's core clock is at half of the PCIe PHY pclk. '0': not extended phystatus,
103903  *    '1': extended phystatus assertion
103904  */
103905 #define USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_MASK)
103906 #define USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_MASK (0x40000000U)
103907 #define USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_SHIFT (30U)
103908 /*! low_pwr_cclk_gate_en - This bit enables gate-off the core clock when AUX PM control is in low
103909  *    power state. '0': disable this function, '1': enabled to gate off the core clock.
103910  */
103911 #define USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_MASK)
103912 #define USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_MASK (0x80000000U)
103913 #define USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_SHIFT (31U)
103914 /*! d3_hot_pme_en - d3_hot_pme_en
103915  */
103916 #define USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_MASK)
103917 /*! @} */
103918 
103919 /*! @name XECP_HOST_CTRL_WATERMARK_REG - Port Watermark */
103920 /*! @{ */
103921 #define USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_MASK (0xFFFFU)
103922 #define USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_SHIFT (0U)
103923 /*! xbuf_water_mark - XBUF water mark
103924  */
103925 #define USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_SHIFT)) & USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_MASK)
103926 #define USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_MASK (0xFFFF0000U)
103927 #define USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_SHIFT (16U)
103928 /*! rbuf_water_mark - RBUF water mark
103929  */
103930 #define USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_SHIFT)) & USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_MASK)
103931 /*! @} */
103932 
103933 /*! @name XECP_HOST_CTRL_PORT_LINK_REG - SuperSpeed Port Link Control */
103934 /*! @{ */
103935 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_MASK (0x1U)
103936 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_SHIFT (0U)
103937 /*! cfg_dis_comp - '0': Enable link compliance mode, '1': Disable link compliance mode
103938  */
103939 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_MASK)
103940 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_MASK (0x2U)
103941 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_SHIFT (1U)
103942 /*! cfg_lpbk_mode - '0': Disable link loopback master mode, '1': Enable link loopback master mode
103943  */
103944 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_MASK)
103945 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_MASK (0x4U)
103946 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_SHIFT (2U)
103947 /*! cfg_u1_enable - '0': Normal operation mode, '1': Direct link to U1 from U0. This bit is for test
103948  *    purpose only. It shall be written '0' in normal operation mode.
103949  */
103950 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_MASK)
103951 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_MASK (0x8U)
103952 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_SHIFT (3U)
103953 /*! cfg_u2_enable - '0': Normal operation mode, '1': Direct link to U2 from U0. This bit is for test
103954  *    purpose only. It shall be written '0' in normal operation mode.
103955  */
103956 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_MASK)
103957 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_MASK (0x10U)
103958 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_SHIFT (4U)
103959 /*! cfg_symbol_err_en - '0': Disable detecting RxData error using RxStatus signal, '1': Enable detecting RxData error using RxStatus signal.
103960  */
103961 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_MASK)
103962 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_MASK (0x20U)
103963 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_SHIFT (5U)
103964 /*! cfg_dis_scrmb - '0': Enable link scrambler, '1': Disable link scrambler
103965  */
103966 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_MASK)
103967 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_MASK (0x40U)
103968 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_SHIFT (6U)
103969 /*! cfg_fast_training - '0': Normal operation mode, '1': Link fast training mode. This bit should be written '0' in normal operation.
103970  */
103971 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_MASK)
103972 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_MASK (0x80U)
103973 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_SHIFT (7U)
103974 /*! cfg_recovery - '0': Normal operation mode, '1': Direct link to Recovery from U0
103975  */
103976 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_MASK)
103977 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_MASK (0x100U)
103978 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_SHIFT (8U)
103979 /*! cfg_force_pm_accept - '0': Normal operation mode. '1': Force link to accept power management command
103980  */
103981 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_MASK)
103982 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_MASK (0xE00U)
103983 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_SHIFT (9U)
103984 /*! cfg_u3_recov_val - This value defines the minimum time for the link to stay in Polling.Active
103985  *    and Recovery.Active from U3. The granuity is 128us.
103986  */
103987 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_MASK)
103988 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_MASK (0x7000U)
103989 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_SHIFT (12U)
103990 /*! cfg_norm_recov_val - This value defines the minimum time for the link to stay in Recovery. Active other than from U3. The granuity is 128us
103991  */
103992 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_MASK)
103993 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_MASK (0x18000U)
103994 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_SHIFT (15U)
103995 /*! cfg_lowpower_latency - cfg_lowpower_latency
103996  */
103997 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_MASK)
103998 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_MASK (0xE0000U)
103999 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_SHIFT (17U)
104000 /*! dbg_mode_sel - Debug mode select: bit[0]: cfg_port_init_ctrl (if set to '1' tPortConfiguration <
104001  *    21us), bit[1]: cfg_relax_ts2_en, bit[2]: cfg_relax_lfps_en
104002  */
104003 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_MASK)
104004 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_MASK (0x100000U)
104005 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_SHIFT (20U)
104006 /*! link_err_cnt_slv_en - link_err_cnt_slv_en
104007  */
104008 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_MASK)
104009 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_MASK (0x1E00000U)
104010 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_SHIFT (21U)
104011 /*! force_comp_pattern - Compliance pattern to be forced to enter compliance mode. This value is for test purpose only.
104012  */
104013 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_MASK)
104014 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_MASK (0x2000000U)
104015 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_SHIFT (25U)
104016 /*! force_ltssm_u0 - '0': Normal operation mode, '1': Direct link to U0 This bit is for test purpose
104017  *    only. It shall be written '0' in normal operation mode.
104018  */
104019 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_MASK)
104020 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_MASK (0x4000000U)
104021 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_SHIFT (26U)
104022 /*! force_ltssm - '0': Normal operation mode, '1': Direct link to a specific state specified by
104023  *    force_ltssm_state field (bits [31:27]). This bit is for test purpose only. It shall be written '0'
104024  *    in normal operation mode.
104025  */
104026 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_MASK)
104027 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_MASK (0xF8000000U)
104028 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_SHIFT (27U)
104029 /*! force_ltssm_state - LTSSM state to be forced. This value is for test purpose only. Setting bit 4
104030  *    enables: cfg_relax_rxpolarity_en; Setting bit 3 enables: cfg_relax_linkfunc_en; Setting bit 2
104031  *    enables: cfg_link_func_en;
104032  */
104033 #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_MASK)
104034 /*! @} */
104035 
104036 /*! @name XECP_USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control */
104037 /*! @{ */
104038 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_MASK (0x1U)
104039 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_SHIFT (0U)
104040 /*! USB2_PM_DEBUG_QUICK_SIM - Short Timer Values For Simulation of USB2.0 parameters. Please refer to Integration Guide section on Debug Features
104041  */
104042 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_MASK)
104043 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_MASK (0x2U)
104044 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_SHIFT (1U)
104045 /*! USB2_PM_DEBUG_PHY_RST - Control PHY Reset Directly
104046  */
104047 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_MASK)
104048 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_MASK (0x4U)
104049 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_SHIFT (2U)
104050 /*! USB2_PM_DEBUG_PHY_RSTDISCON - Disable Clock Gate
104051  */
104052 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_MASK)
104053 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_MASK (0x8U)
104054 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_SHIFT (3U)
104055 /*! USB2_PM_DEBUG_PHY_CLKGATEDIS - Disable PHY suspend during disconnect
104056  */
104057 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_MASK)
104058 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_MASK (0x10U)
104059 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_SHIFT (4U)
104060 /*! USB2_PM_DEBUG_PHY_SUSDISALL - Disable PHY suspend for all states
104061  */
104062 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_MASK)
104063 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_MASK (0x20U)
104064 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_SHIFT (5U)
104065 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_MASK)
104066 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_MASK (0x40U)
104067 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_SHIFT (6U)
104068 /*! USB2_PM_DEBUG_FORCEPING - If retry on endpoint that should have PING, force the PING
104069  */
104070 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_MASK)
104071 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_MASK (0x80U)
104072 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_SHIFT (7U)
104073 /*! USB2_PM_DEBUG_DROPPING - If new ping on endpoint that already had PING, drop the PING
104074  */
104075 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_MASK)
104076 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_MASK (0x100U)
104077 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_SHIFT (8U)
104078 /*! USB2_PM_DEBUG_DIRECT_RESUME - Use FS/LS serial I/F to drive resume
104079  */
104080 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_MASK)
104081 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_MASK (0x200U)
104082 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_SHIFT (9U)
104083 /*! USB2_PM_DEBUG_DIS_ISO_PEEK - Disable waiting for last indication for USB2 ISO
104084  */
104085 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_MASK)
104086 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_MASK (0x400U)
104087 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_SHIFT (10U)
104088 /*! USB2_PM_DEBUG_DIS_PORT_ERR - Enable Remote Wake Resume Trap
104089  */
104090 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_MASK)
104091 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_MASK (0x800U)
104092 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_SHIFT (11U)
104093 /*! USB2_PM_DEBUG_ENABLE_DISC_WIN - Enable HS disconnect Window
104094  */
104095 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_MASK)
104096 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_MASK (0x1000U)
104097 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_SHIFT (12U)
104098 /*! USB2_PM_DEBUG_UTMIRST1 - Select UTMI Reset Source 1
104099  */
104100 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_MASK)
104101 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_MASK (0x2000U)
104102 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_SHIFT (13U)
104103 /*! USB2_PM_DEBUG_UTMIRST2 - Select UTMI Reset Source 2
104104  */
104105 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_MASK)
104106 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_MASK (0x4000U)
104107 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_SHIFT (14U)
104108 /*! USB2_PM_DEBUG_FS_LS_EXT_DISCON - Use UTMI HostDisconnect input for FS/LS
104109  */
104110 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_MASK)
104111 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_MASK (0x8000U)
104112 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_SHIFT (15U)
104113 /*! USB2_PM_DEBUG_SPLIT_192_LIMITDIS - Use to disable 192 byte limit checking on
104114  */
104115 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_MASK)
104116 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_MASK (0x10000U)
104117 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_SHIFT (16U)
104118 /*! USB2_PM_DEBUG_FORCE_FULL_SPEED - Set to reject device chirp and force full-speed
104119  */
104120 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_MASK)
104121 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_MASK (0x20000U)
104122 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_SHIFT (17U)
104123 /*! USB2_PM_DEBUG_EOP_DETECT - Set to enable full length SE0 detect
104124  */
104125 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_MASK)
104126 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_MASK (0x40000U)
104127 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_SHIFT (18U)
104128 /*! USB2_PM_DEBUG_ENABLE_FLUSH_TO - Set to enable flush state timeouts
104129  */
104130 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_MASK)
104131 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_MASK (0x80000U)
104132 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_SHIFT (19U)
104133 /*! USB2_PM_DEBUG_HW_LPM_ERRATA1 - Set to change the scale of HW LPM timeout to 256us increments
104134  */
104135 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_MASK)
104136 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_MASK (0x100000U)
104137 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_SHIFT (20U)
104138 /*! USB2_PM_DEBUG_HW_LPM_ERRATA - Set to switch the HIRD to BESL format
104139  */
104140 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_MASK)
104141 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_MASK (0x200000U)
104142 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_SHIFT (21U)
104143 /*! USB2_PM_DEBUG_RESUME_DEB_DIS - Clr to eliminate debounce on remote wake detect
104144  */
104145 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_MASK)
104146 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_MASK (0x400000U)
104147 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_SHIFT (22U)
104148 /*! USB2_PM_DEBUG_LATENCY_TOL_MSG - Latency Tolerance Scheme ('0'=when HWLPM is enabled / '1'=when L1 is active)
104149  */
104150 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_MASK)
104151 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_MASK (0x800000U)
104152 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SHIFT (23U)
104153 /*! USB2_PM_DEBUG - USB2_PM_DEBUG. usb2_link_mgr_debug
104154  */
104155 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_MASK)
104156 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_MASK (0xFF000000U)
104157 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_SHIFT (24U)
104158 /*! TIMER_DISCONNECT_DETECT_lo - Number of microseconds of SE0 in FS/LS mode to register disconnect had occurred. First 8 MSB
104159  */
104160 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_MASK)
104161 /*! @} */
104162 
104163 /*! @name XECP_USB2_LINK_MGR_CTRL_REG2 - USB2 Port Link Control */
104164 /*! @{ */
104165 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_MASK (0x1FU)
104166 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_SHIFT (0U)
104167 /*! TIMER_DISCONNECT_DETECT_hi - Number of microseconds of SE0 in FS/LS mode to register disconnect had occurred. Last 5 LSBs
104168  */
104169 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_MASK)
104170 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_MASK (0x3FFE0U)
104171 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_SHIFT (5U)
104172 /*! TIMER_CONNECT_DETECT - Number of microseconds of K/J in disconnected state to register connect has occurred. Last 5 LSBs
104173  */
104174 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_MASK)
104175 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_MASK (0x7FFC0000U)
104176 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_SHIFT (18U)
104177 /*! TIMER_CHIRP_K_DETECT - Number of microseconds of Chirp-K to register that a device is chirping
104178  */
104179 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_MASK)
104180 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_MASK (0x80000000U)
104181 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_SHIFT (31U)
104182 /*! TIMER_RESET_0 - Number of microseconds for total reset duration
104183  */
104184 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_MASK)
104185 /*! @} */
104186 
104187 /*! @name XECP_USB2_LINK_MGR_CTRL_REG3 - USB2 Port Link Control */
104188 /*! @{ */
104189 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_MASK (0x7FFFU)
104190 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_SHIFT (0U)
104191 /*! TIMER_RESET - Number of microseconds for total reset duration
104192  */
104193 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_MASK)
104194 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_MASK (0xFFF8000U)
104195 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_SHIFT (15U)
104196 /*! TIMER_U3_SETTLE - Number of microseconds after entering U3; linestate changes are ignored as bus settles
104197  */
104198 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_MASK)
104199 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_MASK (0xF0000000U)
104200 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_SHIFT (28U)
104201 /*! TIMER_U2_SETTLE - Number of microseconds after entering U2; linestate changes are ignored as bus settles. First 4 LSB
104202  */
104203 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_MASK)
104204 /*! @} */
104205 
104206 /*! @name XECP_USB2_LINK_MGR_CTRL_REG4 - USB2 Port Link Control */
104207 /*! @{ */
104208 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_MASK (0x1FFU)
104209 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_SHIFT (0U)
104210 /*! TIMER_U2_SETTLE - Number of microseconds after entering U2; linestate changes are ignored as bus settles. Last 9 MSB
104211  */
104212 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_MASK)
104213 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_MASK (0x1FFFE00U)
104214 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_SHIFT (9U)
104215 /*! TIMER_RESUME_U2_REFLECT - Number of microseconds after detecting U2 remote wake condition to reflect K
104216  */
104217 #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_MASK)
104218 /*! @} */
104219 
104220 /*! @name XECP_HOST_CTRL_BW_MAX_REG - USB2 Max Bandwidth Control */
104221 /*! @{ */
104222 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_MASK (0xFFU)
104223 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_SHIFT (0U)
104224 /*! fsls_max_bw - Max. Percentage BW allowed for FS/LS (default: 90)
104225  */
104226 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_MASK)
104227 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_MASK (0xFF00U)
104228 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_SHIFT (8U)
104229 /*! hs_max_bw - Max. Percentage BW allowed for HS (default: 80)
104230  */
104231 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_MASK)
104232 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_MASK (0xFF0000U)
104233 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_SHIFT (16U)
104234 /*! ss_max_bw - Max. Percentage BW allowed for SS (default: 80)
104235  */
104236 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_MASK)
104237 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_MASK (0xFF000000U)
104238 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_SHIFT (24U)
104239 /*! fsls_bhub_max_bw - Max. Percentage BW allowed for FS/LS behind hub (default: 90)
104240  */
104241 #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_MASK)
104242 /*! @} */
104243 
104244 /*! @name XECP_FPGA_REVISION_REG - FPGA_REVISION_REG */
104245 /*! @{ */
104246 #define USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_MASK (0xFFFFFFFFU)
104247 #define USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_SHIFT (0U)
104248 /*! FPGA_REVISION_REG_DEFAULT - FPGA_REVISION_REG_DEFAULT
104249  */
104250 #define USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_SHIFT)) & USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_MASK)
104251 /*! @} */
104252 
104253 /*! @name XECP_HOST_INTF_CTRL_REG - Host interface control */
104254 /*! @{ */
104255 #define USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_MASK (0x1U)
104256 #define USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_SHIFT (0U)
104257 /*! host_err_mask - host_err_mask. If set to '1' do not mask the host system error
104258  */
104259 #define USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_MASK)
104260 #define USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_MASK (0x2U)
104261 #define USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_SHIFT (1U)
104262 /*! hc_halt_timeout_en - hc_halt_timeout_en. An internal register bit used to control whether or not to use the hc halt status timer of 15ms
104263  */
104264 #define USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_MASK)
104265 #define USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_MASK (0x3CU)
104266 #define USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_SHIFT (2U)
104267 /*! host_intf_ctrl - host_intf_ctrl
104268  */
104269 #define USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_MASK)
104270 #define USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_MASK (0xC0U)
104271 #define USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_SHIFT (6U)
104272 /*! cfg_max_num_of_rd - cfg_max_num_of_rd. This is to control how many max number of read that we
104273  *    allow ODMA read to issue. '00': can issue 16 reads '10': can issue 8 reads '01': can issue 4
104274  *    reads
104275  */
104276 #define USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_MASK)
104277 #define USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_MASK (0x100U)
104278 #define USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_SHIFT (8U)
104279 /*! prot_hdr_rbuf_overflow_cclk - prot_hdr_rbuf_overflow_cclk
104280  */
104281 #define USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_MASK)
104282 /*! @} */
104283 
104284 /*! @name XECP_USBLEGSUP - USB Legacy Support Capability */
104285 /*! @{ */
104286 #define USB3_XECP_USBLEGSUP_CID_MASK             (0xFFU)
104287 #define USB3_XECP_USBLEGSUP_CID_SHIFT            (0U)
104288 /*! CID - USB Legacy Support Capability ID, RO. This capability provides the xHCI Pre-OS to OS
104289  *    Handoff Synchronization support capability
104290  */
104291 #define USB3_XECP_USBLEGSUP_CID(x)               (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_CID_SHIFT)) & USB3_XECP_USBLEGSUP_CID_MASK)
104292 #define USB3_XECP_USBLEGSUP_NextCP_MASK          (0xFF00U)
104293 #define USB3_XECP_USBLEGSUP_NextCP_SHIFT         (8U)
104294 /*! NextCP - Next Capability Pointer, RO. This field indicates the location of the next capability
104295  *    with respect to the effective address of this capability. A non-zero value in this register
104296  *    indicates a relative offset, in Dwords, from this Dword to the beginning of the next extended
104297  *    capability
104298  */
104299 #define USB3_XECP_USBLEGSUP_NextCP(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_NextCP_SHIFT)) & USB3_XECP_USBLEGSUP_NextCP_MASK)
104300 #define USB3_XECP_USBLEGSUP_HCBIOSOS_MASK        (0x10000U)
104301 #define USB3_XECP_USBLEGSUP_HCBIOSOS_SHIFT       (16U)
104302 /*! HCBIOSOS - HC BIOS Owned Semaphore (HCBIOSOS), RW. Default = '0'. The BIOS sets this bit to
104303  *    establish ownership of the xHC. System BIOS will set this bit to '0' in response to a request for
104304  *    ownership of the xHC by system software
104305  */
104306 #define USB3_XECP_USBLEGSUP_HCBIOSOS(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_HCBIOSOS_SHIFT)) & USB3_XECP_USBLEGSUP_HCBIOSOS_MASK)
104307 #define USB3_XECP_USBLEGSUP_HCOSOS_MASK          (0x1000000U)
104308 #define USB3_XECP_USBLEGSUP_HCOSOS_SHIFT         (24U)
104309 /*! HCOSOS - HC OS Owned Semaphore, RW. Default = '0'. System software sets this bit to request
104310  *    ownership of the xHC. Ownership is obtained when this bit reads as '1' and the HC BIOS Owned
104311  *    Semaphore bit (HCBIOSOS) reads as '0'
104312  */
104313 #define USB3_XECP_USBLEGSUP_HCOSOS(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_HCOSOS_SHIFT)) & USB3_XECP_USBLEGSUP_HCOSOS_MASK)
104314 /*! @} */
104315 
104316 /*! @name XECP_USBLEGCTLSTS - USB Legacy Support Control Status */
104317 /*! @{ */
104318 #define USB3_XECP_USBLEGCTLSTS_USBSMIE_MASK      (0x1U)
104319 #define USB3_XECP_USBLEGCTLSTS_USBSMIE_SHIFT     (0U)
104320 /*! USBSMIE - USB SMI Enable, RW. Default = '0'. When this bit is a '1', and the SMI on Event
104321  *    Interrupt bit (below) in this register is a '1', the host controller will issue an SMI immediately
104322  */
104323 #define USB3_XECP_USBLEGCTLSTS_USBSMIE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_USBSMIE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_USBSMIE_MASK)
104324 #define USB3_XECP_USBLEGCTLSTS_SMIHSEE_MASK      (0x10U)
104325 #define USB3_XECP_USBLEGCTLSTS_SMIHSEE_SHIFT     (4U)
104326 /*! SMIHSEE - SMI on Host System Error Enable, RW. Default = '0'. When this bit is a '1', and the
104327  *    SMI on Host System Error bit (below) in this register is a '1', the host controller will issue
104328  *    an SMI immediately
104329  */
104330 #define USB3_XECP_USBLEGCTLSTS_SMIHSEE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIHSEE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIHSEE_MASK)
104331 #define USB3_XECP_USBLEGCTLSTS_SMIOSOE_MASK      (0x2000U)
104332 #define USB3_XECP_USBLEGCTLSTS_SMIOSOE_SHIFT     (13U)
104333 /*! SMIOSOE - SMI on OS Ownership Enable, RW. Default = '0'. When this bit is a '1' AND the OS
104334  *    Ownership Change bit is '1', the host controller will issue an SMI
104335  */
104336 #define USB3_XECP_USBLEGCTLSTS_SMIOSOE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIOSOE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIOSOE_MASK)
104337 #define USB3_XECP_USBLEGCTLSTS_SMIPCICE_MASK     (0x4000U)
104338 #define USB3_XECP_USBLEGCTLSTS_SMIPCICE_SHIFT    (14U)
104339 /*! SMIPCICE - SMI on PCI Command Enable, RW. Default = '0'. When this bit is '1' and SMI on PCI
104340  *    Command is '1', then the host controller will issue an SMI
104341  */
104342 #define USB3_XECP_USBLEGCTLSTS_SMIPCICE(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIPCICE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIPCICE_MASK)
104343 #define USB3_XECP_USBLEGCTLSTS_SMIBARE_MASK      (0x8000U)
104344 #define USB3_XECP_USBLEGCTLSTS_SMIBARE_SHIFT     (15U)
104345 /*! SMIBARE - SMI on BAR Enable, RW. Default = '0'. When this bit is '1' and SMI on BAR is '1', then
104346  *    the host controller will issue an SMI
104347  */
104348 #define USB3_XECP_USBLEGCTLSTS_SMIBARE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIBARE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIBARE_MASK)
104349 #define USB3_XECP_USBLEGCTLSTS_SMIEI_MASK        (0x10000U)
104350 #define USB3_XECP_USBLEGCTLSTS_SMIEI_SHIFT       (16U)
104351 /*! SMIEI - SMI on Event Interrupt, RO. Default = '0'. Shadow bit of Event Interrupt (EINT) bit in
104352  *    the USBSTS register. Refer to Section 5.4.2 of xHCI specification for definition. This bit
104353  *    follows the state the Event Interrupt (EINT) bit in the USBSTS register, e.g. it automatically
104354  *    clears when EINT clears or set when EINT is set
104355  */
104356 #define USB3_XECP_USBLEGCTLSTS_SMIEI(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIEI_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIEI_MASK)
104357 #define USB3_XECP_USBLEGCTLSTS_SMIHSE_MASK       (0x100000U)
104358 #define USB3_XECP_USBLEGCTLSTS_SMIHSE_SHIFT      (20U)
104359 /*! SMIHSE - SMI on Host System Error, RO. Default = '0'. Shadow bit of Host System Error (HSE) bit
104360  *    in the USBSTS register. Refer to Section 5.4.2 of xHCI specification for definition and
104361  *    effects of the events associated with this bit being set to '1'. To clear this bit to a '0', system
104362  *    software shall write a '1' to the Host System Error (HSE) bit in the USBSTS
104363  */
104364 #define USB3_XECP_USBLEGCTLSTS_SMIHSE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIHSE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIHSE_MASK)
104365 #define USB3_XECP_USBLEGCTLSTS_SMIOSOC_MASK      (0x20000000U)
104366 #define USB3_XECP_USBLEGCTLSTS_SMIOSOC_SHIFT     (29U)
104367 /*! SMIOSOC - SMI on OS Ownership Change, RW1C. Default = '0'. This bit is set to '1' whenever the
104368  *    HC OS Owned Semaphore bit in the USBLEGSUP register transitions from '1' to a '0' or '0' to a
104369  *    '1'
104370  */
104371 #define USB3_XECP_USBLEGCTLSTS_SMIOSOC(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIOSOC_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIOSOC_MASK)
104372 #define USB3_XECP_USBLEGCTLSTS_SMIPCIC_MASK      (0x40000000U)
104373 #define USB3_XECP_USBLEGCTLSTS_SMIPCIC_SHIFT     (30U)
104374 /*! SMIPCIC - SMI on PCI Command, RW1C. Default = '0'. This bit is set to '1' whenever the PCI Command Register is written
104375  */
104376 #define USB3_XECP_USBLEGCTLSTS_SMIPCIC(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIPCIC_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIPCIC_MASK)
104377 #define USB3_XECP_USBLEGCTLSTS_SMIBAR_MASK       (0x80000000U)
104378 #define USB3_XECP_USBLEGCTLSTS_SMIBAR_SHIFT      (31U)
104379 /*! SMIBAR - SMI on BAR, RW1C. Default = '0'. This bit is set to '1' whenever the Base Address Register (BAR) is written
104380  */
104381 #define USB3_XECP_USBLEGCTLSTS_SMIBAR(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIBAR_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIBAR_MASK)
104382 /*! @} */
104383 
104384 /*! @name XECP_DCID - Debug Capability ID */
104385 /*! @{ */
104386 #define USB3_XECP_DCID_CapID_MASK                (0xFFU)
104387 #define USB3_XECP_DCID_CapID_SHIFT               (0U)
104388 /*! CapID - Debug capability ID, RO
104389  */
104390 #define USB3_XECP_DCID_CapID(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCID_CapID_SHIFT)) & USB3_XECP_DCID_CapID_MASK)
104391 #define USB3_XECP_DCID_NextCapID_MASK            (0xFF00U)
104392 #define USB3_XECP_DCID_NextCapID_SHIFT           (8U)
104393 /*! NextCapID - Next Capability Pointer, RO. Default = 0. This field indicates the location of the
104394  *    next capability with respect to the effective address of this capability. A non-zero value in
104395  *    this register indicates a relative offset, in Dwords, from this Dword to the beginning of the
104396  *    next extended capability
104397  */
104398 #define USB3_XECP_DCID_NextCapID(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCID_NextCapID_SHIFT)) & USB3_XECP_DCID_NextCapID_MASK)
104399 #define USB3_XECP_DCID_DCERST_Max_MASK           (0x1F0000U)
104400 #define USB3_XECP_DCID_DCERST_Max_SHIFT          (16U)
104401 /*! DCERST_Max - Debug Capability Event Ring Segment Table Max (DCERST Max), RO. Default = 3. Valid
104402  *    values are 0 to 15. This field determines the maximum value supported by the Debug Capability
104403  *    Event Ring Segment Table Base Size registers, where: The maximum number of Event Ring Segment
104404  *    Table entries = 2^DCERST_Max; e.g. if DCERST_Max = 7, then the Debug Capability Event Ring
104405  *    Segment Table(s) supports up to 128 entries, 15 then 32K entries, etc
104406  */
104407 #define USB3_XECP_DCID_DCERST_Max(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCID_DCERST_Max_SHIFT)) & USB3_XECP_DCID_DCERST_Max_MASK)
104408 /*! @} */
104409 
104410 /*! @name XECP_DCDB - Debug Capability Doorbell */
104411 /*! @{ */
104412 #define USB3_XECP_DCDB_DB_target_MASK            (0xFF00U)
104413 #define USB3_XECP_DCDB_DB_target_SHIFT           (8U)
104414 /*! DB_target - Doorbell Target (DB Target), RW. This field defines the target of the doorbell
104415  *    reference. Debug Capability notifications generated by ringing the doorbell: 0: Data EP 1 OUT
104416  *    Enqueue Pointer Update 1: Data EP 1 IN Enqueue Pointer Update 2: 255 Reserved; This field returns
104417  *    zero when read and it should be treated as undefined by software
104418  */
104419 #define USB3_XECP_DCDB_DB_target(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDB_DB_target_SHIFT)) & USB3_XECP_DCDB_DB_target_MASK)
104420 /*! @} */
104421 
104422 /*! @name XECP_DCERSTSZ - Debug Capability Event Ring Segment Table Size */
104423 /*! @{ */
104424 #define USB3_XECP_DCERSTSZ_ERSTSZ_MASK           (0xFFFFU)
104425 #define USB3_XECP_DCERSTSZ_ERSTSZ_SHIFT          (0U)
104426 /*! ERSTSZ - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of
104427  *    valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Debug
104428  *    Capability Event Ring Segment Table Base Address register. The maximum value supported by an xHC
104429  *    implementation for this register is defined by the DCERST_Max field in the DCID register.
104430  *    Software shall initialize this register before setting the Debug Capability Enable field in the
104431  *    DCCTRL register to '1'
104432  */
104433 #define USB3_XECP_DCERSTSZ_ERSTSZ(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERSTSZ_ERSTSZ_SHIFT)) & USB3_XECP_DCERSTSZ_ERSTSZ_MASK)
104434 /*! @} */
104435 
104436 /*! @name XECP_DCERSTBA_LOW - Debug Capability Event Ring Segment Table Base Address */
104437 /*! @{ */
104438 #define USB3_XECP_DCERSTBA_LOW_ERSTBA_L_MASK     (0xFFFFFFF0U)
104439 #define USB3_XECP_DCERSTBA_LOW_ERSTBA_L_SHIFT    (4U)
104440 /*! ERSTBA_L - Event Ring Segment Table Base Address Register RW. Default = 0. This field defines
104441  *    the high order bits of the start address of the Debug Capability Event Ring Segment Table.
104442  *    Software shall initialize this register before setting the Debug Capability Enable field in the
104443  *    DCCTRL register to '1'
104444  */
104445 #define USB3_XECP_DCERSTBA_LOW_ERSTBA_L(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERSTBA_LOW_ERSTBA_L_SHIFT)) & USB3_XECP_DCERSTBA_LOW_ERSTBA_L_MASK)
104446 /*! @} */
104447 
104448 /*! @name XECP_DCERSTBA_HIGH - Debug Capability Event Ring Segment Table Base Address */
104449 /*! @{ */
104450 #define USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_MASK    (0xFFFFFFFFU)
104451 #define USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_SHIFT   (0U)
104452 /*! ERSTBA_H - Event Ring Segment Table Base Address Register RW. Default = 0. This field defines
104453  *    the high order bits of the start address of the Debug Capability Event Ring Segment Table.
104454  *    Software shall initialize this register before setting the Debug Capability Enable field in the
104455  *    DCCTRL register to '1'
104456  */
104457 #define USB3_XECP_DCERSTBA_HIGH_ERSTBA_H(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_SHIFT)) & USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_MASK)
104458 /*! @} */
104459 
104460 /*! @name XECP_DCERDP_LOW - Debug Capability Event Ring Dequeue Pointer */
104461 /*! @{ */
104462 #define USB3_XECP_DCERDP_LOW_DESI_MASK           (0x7U)
104463 #define USB3_XECP_DCERDP_LOW_DESI_SHIFT          (0U)
104464 /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to
104465  *    accelerate checking the Event Ring full condition. This field is written with the low order 3 bits
104466  *    of the offset of the ERST entry which defines the Event Ring segment that the Event Ring
104467  *    Dequeue Pointer resides in
104468  */
104469 #define USB3_XECP_DCERDP_LOW_DESI(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERDP_LOW_DESI_SHIFT)) & USB3_XECP_DCERDP_LOW_DESI_MASK)
104470 #define USB3_XECP_DCERDP_LOW_Deq_Ptr_L_MASK      (0xFFFFFFF0U)
104471 #define USB3_XECP_DCERDP_LOW_Deq_Ptr_L_SHIFT     (4U)
104472 /*! Deq_Ptr_L - Dequeue Pointer, RW. Default = 0. This field defines the high order bits of the
104473  *    64-bit address of the current Debug Capability Event Ring Dequeue Pointer. Software shall
104474  *    initialize this register before setting the Debug Capability Enable field in the DCCTRL register to '1'
104475  */
104476 #define USB3_XECP_DCERDP_LOW_Deq_Ptr_L(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERDP_LOW_Deq_Ptr_L_SHIFT)) & USB3_XECP_DCERDP_LOW_Deq_Ptr_L_MASK)
104477 /*! @} */
104478 
104479 /*! @name XECP_DCERDP_HIGH - Debug Capability Event Ring Dequeue Pointer */
104480 /*! @{ */
104481 #define USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_MASK     (0xFFFFFFFFU)
104482 #define USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_SHIFT    (0U)
104483 /*! Deq_Ptr_H - Dequeue Pointer, RW. Default = 0. This field defines the high order bits of the
104484  *    64-bit address of the current Debug Capability Event Ring Dequeue Pointer. Software shall
104485  *    initialize this register before setting the Debug Capability Enable field in the DCCTRL register to '1'
104486  */
104487 #define USB3_XECP_DCERDP_HIGH_Deq_Ptr_H(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_SHIFT)) & USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_MASK)
104488 /*! @} */
104489 
104490 /*! @name XECP_DCCTRL - Debug Capability Control */
104491 /*! @{ */
104492 #define USB3_XECP_DCCTRL_DCR_MASK                (0x1U)
104493 #define USB3_XECP_DCCTRL_DCR_SHIFT               (0U)
104494 /*! DCR - DbC Run (DCR), RO. Default = '0'. When '0', Debug Device is not in the Configured state.
104495  *    When '1', Debug Device is in the Configured state and bulk Data pipe transactions are accepted
104496  *    by Debug Capability and routed to the IN and OUT Transfer Rings. A '0' to '1' transition of
104497  *    the Port Reset (DCPORTSC:PR) bit will clear this bit to '0'
104498  */
104499 #define USB3_XECP_DCCTRL_DCR(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DCR_SHIFT)) & USB3_XECP_DCCTRL_DCR_MASK)
104500 #define USB3_XECP_DCCTRL_LSE_MASK                (0x2U)
104501 #define USB3_XECP_DCCTRL_LSE_SHIFT               (1U)
104502 /*! LSE - Link Status Event Enable (LSE), RW. Default = '0'. Setting this bit to a '1' enables the
104503  *    Debug Capability to generate Port Status Change Events due the Port Link Status Change bit
104504  *    transitioning from a '0' to a '1'. Refer to section 4.19.2 of xHCI specification for more
104505  *    information
104506  */
104507 #define USB3_XECP_DCCTRL_LSE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_LSE_SHIFT)) & USB3_XECP_DCCTRL_LSE_MASK)
104508 #define USB3_XECP_DCCTRL_HOT_MASK                (0x4U)
104509 #define USB3_XECP_DCCTRL_HOT_SHIFT               (2U)
104510 /*! HOT - Halt OUT TR (HOT), RW1S. Default = '0'. While this bit is '1' the Debug Capability shall
104511  *    generate STALL TPs for all IN TPs received for the OUT TR. The Debug Capability shall clear
104512  *    this bit when a ClearFeature(ENDPOINT_HALT) request is received for the endpoint. This field is
104513  *    valid only when the Debug Capability is in Run Mode (DCR = 1). When not in Run Mode, this field
104514  *    shall return '0' when read, and writes will have no effect. Refer to section 7.6.4.3 of xHCI
104515  *    specification
104516  */
104517 #define USB3_XECP_DCCTRL_HOT(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_HOT_SHIFT)) & USB3_XECP_DCCTRL_HOT_MASK)
104518 #define USB3_XECP_DCCTRL_HIT_MASK                (0x8U)
104519 #define USB3_XECP_DCCTRL_HIT_SHIFT               (3U)
104520 /*! HIT - Halt IN TR (HIT), RW1S. Default = '0'. While this bit is '1' the Debug Capability shall
104521  *    generate STALL TPs for all OUT DPs received for the IN TR. The Debug Capability shall clear this
104522  *    bit when a ClearFeature(ENDPOINT_HALT) request is received for the endpoint. This field is
104523  *    valid only when the Debug Capability is in Run Mode (DCR = '1'). When not in Run Mode, this
104524  *    field shall return '0' when read, and writes will have no effect. Refer to section 7.6.4.3 of xHCI
104525  *    specification
104526  */
104527 #define USB3_XECP_DCCTRL_HIT(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_HIT_SHIFT)) & USB3_XECP_DCCTRL_HIT_MASK)
104528 #define USB3_XECP_DCCTRL_DRC_MASK                (0x10U)
104529 #define USB3_XECP_DCCTRL_DRC_SHIFT               (4U)
104530 /*! DRC - DbC Run Change (DRC), RW1C. Default = '0'. This bit shall be set to '1' when DCR bit is
104531  *    cleared to '0', i.e. by any DbC Port State transition that exits the DbC-Configured state. While
104532  *    this bit is '1' the Debug Capability Doorbell Register (DCDB) is disabled. Software shall
104533  *    clear this bit to re-enable the DCDB
104534  */
104535 #define USB3_XECP_DCCTRL_DRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DRC_SHIFT)) & USB3_XECP_DCCTRL_DRC_MASK)
104536 #define USB3_XECP_DCCTRL_DMaxBSize_MASK          (0xFF0000U)
104537 #define USB3_XECP_DCCTRL_DMaxBSize_SHIFT         (16U)
104538 /*! DMaxBSize - Debug Max Burst Size, RO. Default = xHC.Vendor defined. This field identifies the
104539  *    maximum burst size supported by the bulk endpoints of this DbC implementation
104540  */
104541 #define USB3_XECP_DCCTRL_DMaxBSize(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DMaxBSize_SHIFT)) & USB3_XECP_DCCTRL_DMaxBSize_MASK)
104542 #define USB3_XECP_DCCTRL_Dev_addr_MASK           (0x7F000000U)
104543 #define USB3_XECP_DCCTRL_Dev_addr_SHIFT          (24U)
104544 /*! Dev_addr - Device Address, RO. Default = 0. This field reports the USB device address assigned
104545  *    to the Debug Device during the enumeration process. This field is valid when the DbC Run bit is
104546  *    '1'
104547  */
104548 #define USB3_XECP_DCCTRL_Dev_addr(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_Dev_addr_SHIFT)) & USB3_XECP_DCCTRL_Dev_addr_MASK)
104549 #define USB3_XECP_DCCTRL_DCE_MASK                (0x80000000U)
104550 #define USB3_XECP_DCCTRL_DCE_SHIFT               (31U)
104551 /*! DCE - Debug Capability Enable, RW. Default = '0'. Setting this bit to a '1' enables xHCI USB
104552  *    Debug Capability operation. This bit is a '0' if the USB Debug Capability is disabled. Clearing
104553  *    this bit releases the Root Hub port assigned to the Debug Capability, and terminates any Debug
104554  *    Capability Transfer or Event Ring activity
104555  */
104556 #define USB3_XECP_DCCTRL_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DCE_SHIFT)) & USB3_XECP_DCCTRL_DCE_MASK)
104557 /*! @} */
104558 
104559 /*! @name XECP_DCST - Debug Capability Status */
104560 /*! @{ */
104561 #define USB3_XECP_DCST_ER_MASK                   (0x1U)
104562 #define USB3_XECP_DCST_ER_SHIFT                  (0U)
104563 /*! ER - Event Ring Not Empty, RO. Default = '0'. When '1', this field indicates that the Debug
104564  *    Capability Event Ring has a Transfer Event on it. It is automatically cleared to '0' by the xHC
104565  *    when the Debug Capability Event Ring is empty, i.e. the Debug Capability Enqueue Pointer is
104566  *    equal to the Debug Capability Event Ring Dequeue Pointer
104567  */
104568 #define USB3_XECP_DCST_ER(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCST_ER_SHIFT)) & USB3_XECP_DCST_ER_MASK)
104569 #define USB3_XECP_DCST_Dbgp_num_MASK             (0xFF000000U)
104570 #define USB3_XECP_DCST_Dbgp_num_SHIFT            (24U)
104571 /*! Dbgp_num - Debug Port Number, RO. Default = 0. This field provides the ID of the Root Hub port
104572  *    that the Debug Capability has been automatically attached to. The value is 0 when the Debug
104573  *    Capability is not attached to a Root Hub port
104574  */
104575 #define USB3_XECP_DCST_Dbgp_num(x)               (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCST_Dbgp_num_SHIFT)) & USB3_XECP_DCST_Dbgp_num_MASK)
104576 /*! @} */
104577 
104578 /*! @name XECP_DCPORTSC - Debug Capability Port Status and Control */
104579 /*! @{ */
104580 #define USB3_XECP_DCPORTSC_CCS_MASK              (0x1U)
104581 #define USB3_XECP_DCPORTSC_CCS_SHIFT             (0U)
104582 /*! CCS - Current Connect Status, RO. Default = '0'. '1' = A Root Hub port is connected to a Debug
104583  *    Host and assigned to the Debug Capability. '0' = No Debug Host is present. This value reflects
104584  *    the current state of the port, and may not correspond to the value reported by the Connect
104585  *    Status Change (CSC) field in the Port Status Change Event that was generated by a '0' to '1'
104586  *    transition of this bit. This flag is '0' if Debug Capability Enable (DCE) is '0'
104587  */
104588 #define USB3_XECP_DCPORTSC_CCS(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_CCS_SHIFT)) & USB3_XECP_DCPORTSC_CCS_MASK)
104589 #define USB3_XECP_DCPORTSC_PED_MASK              (0x2U)
104590 #define USB3_XECP_DCPORTSC_PED_SHIFT             (1U)
104591 /*! PED - Port Enabled/Disabled, RW. Default = '0'. '1' = Debug Capability Root Hub port is enabled.
104592  *    '0' = Debug Capability Root Hub port is disabled. This flag shall be set to '1' by a '0' to
104593  *    '1' transition of CCS or a '1' to '0' transition of the PR. When PED transitions from '1' to
104594  *    '0' due to the assertion of PR, the port's link shall transition to the Rx.Detect state. This
104595  *    flag may be used by software to enable or disable the operation of the Root Hub port assigned to
104596  *    the Debug Capability. The Debug Capability Root Hub port operation may be disabled by a fault
104597  *    condition (disconnect event or other fault condition, e.g. a LTSSM Polling substate timeout,
104598  *    tPortConfiguration timeout error, etc.), the assertion of DCPORTSC PR, or by software. When
104599  *    the port is disabled (PED = '0') the ports link shall enter the SS.Disabled state and remain
104600  *    there until PED is reasserted ('1') or DCE is negated ('0'). Note that the Root Hub port remains
104601  *    mapped to Debug Capability while PED = '0'. While PED = '0' the Debug Capability will appear
104602  *    to be disconnected to the Debug Host. Note, this bit is not affected by PORTSC PR bit
104603  *    transitions. This field is '0' if DCE or CCS are '0'
104604  */
104605 #define USB3_XECP_DCPORTSC_PED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PED_SHIFT)) & USB3_XECP_DCPORTSC_PED_MASK)
104606 #define USB3_XECP_DCPORTSC_PR_MASK               (0x10U)
104607 #define USB3_XECP_DCPORTSC_PR_SHIFT              (4U)
104608 /*! PR - Port Reset, RO. Default = '0'. '1' = Port is in Reset. '0' = Port is not in Reset. This bit
104609  *    is set to '1' when the bus reset sequence as defined in the USB Specification is detected on
104610  *    the Root Hub port assigned to the Debug capability. It is cleared when the bus reset sequence
104611  *    is completed by the Debug Host, and the DbC shall transition to the USB Default state. A '0'
104612  *    to '1' transition of this bit shall clear DCPORTSC PED (0). This field is '0' if DCE or CCS are
104613  *    '0'
104614  */
104615 #define USB3_XECP_DCPORTSC_PR(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PR_SHIFT)) & USB3_XECP_DCPORTSC_PR_MASK)
104616 #define USB3_XECP_DCPORTSC_PLS_MASK              (0x1E0U)
104617 #define USB3_XECP_DCPORTSC_PLS_SHIFT             (5U)
104618 /*! PLS - Port Link State, RO. Default = RxDetect. This field reflects its current link state. This
104619  *    field is only relevant when a Debug Host is attached (Debug Port Number > 0). Possible values:
104620  *    0: Link is in the U0 State 1: Link is in the U1 State 2: Link is in the U2 State 3: Link is
104621  *    in the U3 State (Device Suspended) 4: Link is in the Disabled State 5: Link is in the RxDetect
104622  *    State 6: Link is in the Inactive State 7: Link is in the Polling State 8: Link is in the
104623  *    Recovery State 9: Link is in the Hot Reset State 10-15: Reserved Note: Transitions between
104624  *    different states are not reflected until the transition is complete
104625  */
104626 #define USB3_XECP_DCPORTSC_PLS(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PLS_SHIFT)) & USB3_XECP_DCPORTSC_PLS_MASK)
104627 #define USB3_XECP_DCPORTSC_PortSpeed_MASK        (0x3C00U)
104628 #define USB3_XECP_DCPORTSC_PortSpeed_SHIFT       (10U)
104629 /*! PortSpeed - Port Speed, RO. Default = '0'. This field identifies the speed of the port. This
104630  *    field is only relevant when a Debug Host is attached (CCS = '1') in all other cases this field
104631  *    shall indicate Undefined Speed. Possible values: 0: Undefined Speed 1-15: Protocol Speed ID
104632  *    (PSI), refer to section 7.2.1 of xHCI specification for the definition of PSIs. Note: The Debug
104633  *    Capability does not support LS, FS, or HS operation
104634  */
104635 #define USB3_XECP_DCPORTSC_PortSpeed(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PortSpeed_SHIFT)) & USB3_XECP_DCPORTSC_PortSpeed_MASK)
104636 #define USB3_XECP_DCPORTSC_CSC_MASK              (0x20000U)
104637 #define USB3_XECP_DCPORTSC_CSC_SHIFT             (17U)
104638 /*! CSC - Connect Status Change, RW1C. Default = '0'. '1' = Change in CCS. '0' = No change.
104639  *    Indicates a change has occurred in the ports Current Connect Status. The xHC sets this bit to '1' for
104640  *    all changes to the Debug Device connect status, even if system software has not cleared an
104641  *    existing DbC Connect Status Change. For example, the insertion status changes twice before system
104642  *    software has cleared the changed condition, hardware will be setting an already-set bit
104643  *    (i.e., the bit will remain '1'). Software shall clear this bit by writing a '1' to it. This field
104644  *    is '0' if DCE is '0'
104645  */
104646 #define USB3_XECP_DCPORTSC_CSC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_CSC_SHIFT)) & USB3_XECP_DCPORTSC_CSC_MASK)
104647 #define USB3_XECP_DCPORTSC_PRC_MASK              (0x200000U)
104648 #define USB3_XECP_DCPORTSC_PRC_SHIFT             (21U)
104649 /*! PRC - Port Reset Change, RW1C. Default = '0'. This bit is set when reset processing on this port
104650  *    is complete (i.e. a '1' to '0' transition of PR). '0' = No change. '1' = Reset complete.
104651  *    Software shall clear this bit by writing a '1' to it. This field is '0' if DCE is '0'
104652  */
104653 #define USB3_XECP_DCPORTSC_PRC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PRC_SHIFT)) & USB3_XECP_DCPORTSC_PRC_MASK)
104654 #define USB3_XECP_DCPORTSC_PLC_MASK              (0x400000U)
104655 #define USB3_XECP_DCPORTSC_PLC_SHIFT             (22U)
104656 /*! PLC - Port Link State Change, RW1C. Default = '0'. This flag is set to '1' due to the following
104657  *    PLS transitions: U0 -> U3 (Suspend signaling detected from Debug Host) U3 -> U0 (Resume
104658  *    complete) Polling -> Disabled (Training Error) Ux or Recovery -> Inactive (Error) Software shall
104659  *    clear this bit by writing a '1' to it. This field is '0' if DCE is '0'
104660  */
104661 #define USB3_XECP_DCPORTSC_PLC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PLC_SHIFT)) & USB3_XECP_DCPORTSC_PLC_MASK)
104662 #define USB3_XECP_DCPORTSC_CEC_MASK              (0x800000U)
104663 #define USB3_XECP_DCPORTSC_CEC_SHIFT             (23U)
104664 /*! CEC - Port Config Error Change, RW1C. Default = '0'. This flag indicates that the port failed to
104665  *    configure its link partner. '0' = No change. '1' = Port Config Error detected. Software shall
104666  *    clear this bit by writing a '1' to it
104667  */
104668 #define USB3_XECP_DCPORTSC_CEC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_CEC_SHIFT)) & USB3_XECP_DCPORTSC_CEC_MASK)
104669 /*! @} */
104670 
104671 /*! @name XECP_DCCP_LOW - Debug Capability Context Pointer */
104672 /*! @{ */
104673 #define USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_MASK  (0xFFFFFFF0U)
104674 #define USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_SHIFT (4U)
104675 /*! DBGP_CNTX_PTR_L - Debug Capability Context Pointer Register, RW. Default = 0. This field defines
104676  *    the high order bits of the start address of the Debug Capability Context data structure
104677  *    (refer to section 7.6.9 of xHCI specification) associated with the Debug Capability. Software shall
104678  *    initialize this register before setting the Debug Capability Enable bit in the Debug
104679  *    Capability Control Register to '1'
104680  */
104681 #define USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_SHIFT)) & USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_MASK)
104682 /*! @} */
104683 
104684 /*! @name XECP_DCCP_HIGH - Debug Capability Context Pointer */
104685 /*! @{ */
104686 #define USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_MASK (0xFFFFFFFFU)
104687 #define USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_SHIFT (0U)
104688 /*! DBGP_CNTX_PTR_H - Debug Capability Context Pointer Register, RW. Default = 0. This field defines
104689  *    the high order bits of the start address of the Debug Capability Context data structure
104690  *    (refer to section 7.6.9 of xHCI specification) associated with the Debug Capability. Software shall
104691  *    initialize this register before setting the Debug Capability Enable bit in the Debug
104692  *    Capability Control Register to '1'
104693  */
104694 #define USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_SHIFT)) & USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_MASK)
104695 /*! @} */
104696 
104697 /*! @name XECP_DCDDI1 - Debug Capability Device Descriptor Info */
104698 /*! @{ */
104699 #define USB3_XECP_DCDDI1_DbC_PROT_MASK           (0xFFU)
104700 #define USB3_XECP_DCDDI1_DbC_PROT_SHIFT          (0U)
104701 /*! DbC_PROT - DbC Protocol, RW. This field is presented by the Debug Device in the USB Interface
104702  *    Descriptor bInterfaceProtocol field. 0: Debug Target vendor defined. 1: GNU Remote Debug Command
104703  *    Set supported. 2-255: Reserved
104704  */
104705 #define USB3_XECP_DCDDI1_DbC_PROT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI1_DbC_PROT_SHIFT)) & USB3_XECP_DCDDI1_DbC_PROT_MASK)
104706 #define USB3_XECP_DCDDI1_VID_MASK                (0xFFFF0000U)
104707 #define USB3_XECP_DCDDI1_VID_SHIFT               (16U)
104708 /*! VID - Vendor ID, RW. This field is presented by the Debug Device in the USB Device Descriptor idVendor field
104709  */
104710 #define USB3_XECP_DCDDI1_VID(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI1_VID_SHIFT)) & USB3_XECP_DCDDI1_VID_MASK)
104711 /*! @} */
104712 
104713 /*! @name XECP_DCDDI2 - The Debug Capability Device Descriptor */
104714 /*! @{ */
104715 #define USB3_XECP_DCDDI2_PROD_ID_MASK            (0xFFFFU)
104716 #define USB3_XECP_DCDDI2_PROD_ID_SHIFT           (0U)
104717 /*! PROD_ID - Product ID, RW. This field is presented by the Debug Device in the USB Device Descriptor idProduct field
104718  */
104719 #define USB3_XECP_DCDDI2_PROD_ID(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI2_PROD_ID_SHIFT)) & USB3_XECP_DCDDI2_PROD_ID_MASK)
104720 #define USB3_XECP_DCDDI2_DEV_REV_MASK            (0xFFFF0000U)
104721 #define USB3_XECP_DCDDI2_DEV_REV_SHIFT           (16U)
104722 /*! DEV_REV - Device Revision, RW. This field is presented by the Debug Device in the USB Device Descriptor bcdDevice field
104723  */
104724 #define USB3_XECP_DCDDI2_DEV_REV(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI2_DEV_REV_SHIFT)) & USB3_XECP_DCDDI2_DEV_REV_MASK)
104725 /*! @} */
104726 
104727 /*! @name USB_CONF - Global Configuration */
104728 /*! @{ */
104729 #define USB3_USB_CONF_CFGRST_MASK                (0x1U)
104730 #define USB3_USB_CONF_CFGRST_SHIFT               (0U)
104731 /*! CFGRST - Reset USB device configuration. Writing '1' to this bit resets USB device
104732  *    configuration, leaving only EP0 IN/OUT active (all other EP-related registers will be loaded with default
104733  *    values). Any configuration/interface change, including adding new IF, must be preceded with
104734  *    configuration reset, adding current IF's as well as new IF. Writing '0' has no effect. This bit
104735  *    is always '0' while reading
104736  */
104737 #define USB3_USB_CONF_CFGRST(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CFGRST_SHIFT)) & USB3_USB_CONF_CFGRST_MASK)
104738 #define USB3_USB_CONF_CFGSET_MASK                (0x2U)
104739 #define USB3_USB_CONF_CFGSET_SHIFT               (1U)
104740 /*! CFGSET - Set Configuration. Software writes '1' to this bit when it receives SET_CONFIGURATION
104741  *    request with non-zero configuration number. CPU sets this bit after setting requested
104742  *    configuration and before setting REQ_CMPL bit in the EP_CMD register. Configuration will be set
104743  *    internally in the hardware when REQ_CMPL bit will be set. Writing '0' has no effect. The actual
104744  *    configuration status can be checked in the USB_STS register. This bit is always '0' while reading
104745  */
104746 #define USB3_USB_CONF_CFGSET(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CFGSET_SHIFT)) & USB3_USB_CONF_CFGSET_MASK)
104747 #define USB3_USB_CONF_RESERVED0_MASK             (0x4U)
104748 #define USB3_USB_CONF_RESERVED0_SHIFT            (2U)
104749 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
104750  */
104751 #define USB3_USB_CONF_RESERVED0(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_RESERVED0_SHIFT)) & USB3_USB_CONF_RESERVED0_MASK)
104752 #define USB3_USB_CONF_USB3DIS_MASK               (0x8U)
104753 #define USB3_USB_CONF_USB3DIS_SHIFT              (3U)
104754 /*! USB3DIS - Disconnect USB device in SuperSpeed. Writing '1' to this bit disconnects USB in Super
104755  *    Speed. The actual USB connection status in the SS mode can be checked in the USB_STS register.
104756  *    If link is in U3 (SuperSpeed PHY clock is disabled) while software writes USB3DIS bit, first
104757  *    the hardware automatically wakes up the PHY to the P2 to turn on the PHY clock (clklink), and
104758  *    second, all operations related to device disconnection cease. Writing '0' has no effect. To
104759  *    connect disconnected device, CPU performs software reset (UCB_CFG.SWRST). This bit is always '0'
104760  *    while reading
104761  */
104762 #define USB3_USB_CONF_USB3DIS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_USB3DIS_SHIFT)) & USB3_USB_CONF_USB3DIS_MASK)
104763 #define USB3_USB_CONF_USB2DIS_MASK               (0x10U)
104764 #define USB3_USB_CONF_USB2DIS_SHIFT              (4U)
104765 /*! USB2DIS - Disconnect USB device in HS/FS. Writing '1' to this bit disconnects USB in HS/FS. The
104766  *    actual USB connection status in HS/FS can be checked in the USB_STS register. Writing '0' has
104767  *    no effect. To connect disconnected device, CPU performs software reset (UCB_CFG.SWRST). This
104768  *    bit is always '0' while reading
104769  */
104770 #define USB3_USB_CONF_USB2DIS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_USB2DIS_SHIFT)) & USB3_USB_CONF_USB2DIS_MASK)
104771 #define USB3_USB_CONF_LENDIAN_MASK               (0x20U)
104772 #define USB3_USB_CONF_LENDIAN_SHIFT              (5U)
104773 /*! LENDIAN - Little Endian access. Writing '1' to this bit sets Little Endian byte order for SFRs
104774  *    access. By default (after hardware reset), USBSS-DEV acts as little-endian device. Writing '0'
104775  *    has no effect. When both LENDIAN and BENDIAN bits are set to '1' while writing to USB_CONF
104776  *    register, the device behaviour is udefined. This bit is always '0' while reading
104777  */
104778 #define USB3_USB_CONF_LENDIAN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LENDIAN_SHIFT)) & USB3_USB_CONF_LENDIAN_MASK)
104779 #define USB3_USB_CONF_BENDIAN_MASK               (0x40U)
104780 #define USB3_USB_CONF_BENDIAN_SHIFT              (6U)
104781 /*! BENDIAN - Big Endian Access. Writing '1' to this bit sets Big Endian byte order for SFRs access.
104782  *    Writing '0' has no effect. When both LENDIAN and BENDIAN bits are set to '1' while writing to
104783  *    USB_CONF register, the device behaviour is udefined. This bit is always '0' while reading
104784  */
104785 #define USB3_USB_CONF_BENDIAN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_BENDIAN_SHIFT)) & USB3_USB_CONF_BENDIAN_MASK)
104786 #define USB3_USB_CONF_SWRST_MASK                 (0x80U)
104787 #define USB3_USB_CONF_SWRST_SHIFT                (7U)
104788 /*! SWRST - Device software reset. When set to 1, the entire USBSS-DEV is reset. The SWRST resets
104789  *    most flip-flops in entire USBSS-DEV. This bit is also used to connect disconnected device.
104790  *    Writing '0' has no effect
104791  */
104792 #define USB3_USB_CONF_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_SWRST_SHIFT)) & USB3_USB_CONF_SWRST_MASK)
104793 #define USB3_USB_CONF_DSING_MASK                 (0x100U)
104794 #define USB3_USB_CONF_DSING_SHIFT                (8U)
104795 /*! DSING - Singular DMA transfer mode. When set to '1', all DMA transfers are singular: when single
104796  *    TRB chain ends, the transfer ends. Writing '0' has no effect. This bit is always '0' while
104797  *    reading. The status of this settings can be check in the USB_STS.DTRANS bit
104798  */
104799 #define USB3_USB_CONF_DSING(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DSING_SHIFT)) & USB3_USB_CONF_DSING_MASK)
104800 #define USB3_USB_CONF_DMULT_MASK                 (0x200U)
104801 #define USB3_USB_CONF_DMULT_SHIFT                (9U)
104802 /*! DMULT - Multiple DMA transfers mode. When set to '1', all DMA transfers are multiple: when
104803  *    current TRB chain ends, the DMA checks if next TRB is ready and, if owner bit (C) is correct,
104804  *    starts next chain; otherwise, it stops current EP transfer. Writing '0' has no effect. This bit is
104805  *    always '0' while reading. The status of this settings can be check in the USB_STS.DTRANS bit
104806  */
104807 #define USB3_USB_CONF_DMULT(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DMULT_SHIFT)) & USB3_USB_CONF_DMULT_MASK)
104808 #define USB3_USB_CONF_DMAOFFEN_MASK              (0x400U)
104809 #define USB3_USB_CONF_DMAOFFEN_SHIFT             (10U)
104810 /*! DMAOFFEN - DMA clock turn-off enable. Writing '1' to this bit enables DMA clock turning-off when
104811  *    device exits U0 link state in SuperSpeed mode. When both DMAOFFDS and DMAOFFEN bits are set
104812  *    to '1' while writing to USB_CONF register, the device behaviour is udefined. This bit is always
104813  *    '0' while reading
104814  */
104815 #define USB3_USB_CONF_DMAOFFEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DMAOFFEN_SHIFT)) & USB3_USB_CONF_DMAOFFEN_MASK)
104816 #define USB3_USB_CONF_DMAOFFDS_MASK              (0x800U)
104817 #define USB3_USB_CONF_DMAOFFDS_SHIFT             (11U)
104818 /*! DMAOFFDS - DMA clock turn-off disable. Writing '1' to this bit disables DMA clock turning-off
104819  *    when device exits U0 link state in SuperSpeed mode. When both DMAOFFDS and DMAOFFEN bits are set
104820  *    to '1' while writing to USB_CONF register, the device behaviour is udefined. This bit is
104821  *    always '0' while reading
104822  */
104823 #define USB3_USB_CONF_DMAOFFDS(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DMAOFFDS_SHIFT)) & USB3_USB_CONF_DMAOFFDS_MASK)
104824 #define USB3_USB_CONF_CFORCE_FS_MASK             (0x1000U)
104825 #define USB3_USB_CONF_CFORCE_FS_SHIFT            (12U)
104826 /*! CFORCE_FS - Clear Force Full Speed. Writing '1' to this bit stop forcing Full Speed when
104827  *    USBSS-DEV operates in USB2.0 mode (stop disabling High Speed). When both SFORCE_FS and CFORCE_FS bits
104828  *    are set to '1' while writing to USB_CONF register, the device behaviour is udefined. The
104829  *    status of this settings can be check in the USB_STS.DISABLE_HS bit. This bit is always '0' while
104830  *    reading
104831  */
104832 #define USB3_USB_CONF_CFORCE_FS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CFORCE_FS_SHIFT)) & USB3_USB_CONF_CFORCE_FS_MASK)
104833 #define USB3_USB_CONF_SFORCE_FS_MASK             (0x2000U)
104834 #define USB3_USB_CONF_SFORCE_FS_SHIFT            (13U)
104835 /*! SFORCE_FS - Set Force Full Speed. Writing '1' to this bit forces Full Speed when USBSS-DEV
104836  *    operates in USB2.0 mode (disables High Speed). When both SFORCE_FS and CFORCE_FS bits are set to
104837  *    '1' while writing to USB_CONF register, the device behaviour is udefined. The status of this
104838  *    settings can be check in the USB_STS.DISABLE_HS bit. This bit is always '0' while reading
104839  */
104840 #define USB3_USB_CONF_SFORCE_FS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_SFORCE_FS_SHIFT)) & USB3_USB_CONF_SFORCE_FS_MASK)
104841 #define USB3_USB_CONF_DEVEN_MASK                 (0x4000U)
104842 #define USB3_USB_CONF_DEVEN_SHIFT                (14U)
104843 /*! DEVEN - Device enable. After Power-On-Reset the USBSS_DEV is disconnected from the USB bus. To
104844  *    connect the device into the USB bus the software has to write '1' to DEVEN bit - this couse
104845  *    connection of the VBUS input to the internal device logic and connetion to the USB bus as a
104846  *    result (inside of USBSS_DEV an internal VBUS is used which which is the and gate: VBUS input AND
104847  *    USB_STS.DEVS bit in SFRs). Writing '1' to the DEVEN bit sets to '1' the USB_STS.DEVS bit.
104848  *    Writing '0' has no effect. This bit is always '0' while reading
104849  */
104850 #define USB3_USB_CONF_DEVEN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DEVEN_SHIFT)) & USB3_USB_CONF_DEVEN_MASK)
104851 #define USB3_USB_CONF_DEVDS_MASK                 (0x8000U)
104852 #define USB3_USB_CONF_DEVDS_SHIFT                (15U)
104853 /*! DEVDS - Device disable. Writing '1' to the DEVDS bit sets to '0' the USB_STS.DEVS bit. Check
104854  *    also the DEVEN bit description. Writing '0' has no effect. This bit is always '0' while reading
104855  */
104856 #define USB3_USB_CONF_DEVDS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DEVDS_SHIFT)) & USB3_USB_CONF_DEVDS_MASK)
104857 #define USB3_USB_CONF_L1EN_MASK                  (0x10000U)
104858 #define USB3_USB_CONF_L1EN_SHIFT                 (16U)
104859 /*! L1EN - L1 LPM state entry enable (device side, HS/FS mode only). Writing '1' to this bit enables
104860  *    USB2.0 LPM to enter L1 state. Status of this bit can be checked in the USB_STS register.
104861  *    Writing '0' has no effect. When both L1EN and L1DS bits are set to '1' while writing to USB_CONF
104862  *    register, the device behaviour is udefined. This bit is always '0' while reading
104863  */
104864 #define USB3_USB_CONF_L1EN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_L1EN_SHIFT)) & USB3_USB_CONF_L1EN_MASK)
104865 #define USB3_USB_CONF_L1DS_MASK                  (0x20000U)
104866 #define USB3_USB_CONF_L1DS_SHIFT                 (17U)
104867 /*! L1DS - L1 LPM state entry disable (HS/FS mode only). Writing '1' to this bit disables USB2.0 LPM
104868  *    from entering L1 state. Status of this bit can be checked in the USB_STS register. Writing
104869  *    '0' has no effect. When both L1EN and L1DS bits are set to '1' while writing to USB_CONF
104870  *    register, the device behaviour is udefined. This bit is always '0' while reading
104871  */
104872 #define USB3_USB_CONF_L1DS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_L1DS_SHIFT)) & USB3_USB_CONF_L1DS_MASK)
104873 #define USB3_USB_CONF_CLK2OFFEN_MASK             (0x40000U)
104874 #define USB3_USB_CONF_CLK2OFFEN_SHIFT            (18U)
104875 /*! CLK2OFFEN - USB 2.0 clock gate disable. Writing '1' to this bit enables hsfs clock turning-off
104876  *    when device enters L2 LPM state in HS/FS mode. The actual 'USB 2.0 clock gate' status in can be
104877  *    checked in the USB_STS.USB2OFF register. When both CLK2OFFDS and CLK2OFFEN bits are set to
104878  *    '1' while writing to USB_CONF register, the device behaviour is udefined. This bit is always '0'
104879  *    while reading
104880  */
104881 #define USB3_USB_CONF_CLK2OFFEN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK2OFFEN_SHIFT)) & USB3_USB_CONF_CLK2OFFEN_MASK)
104882 #define USB3_USB_CONF_CLK2OFFDS_MASK             (0x80000U)
104883 #define USB3_USB_CONF_CLK2OFFDS_SHIFT            (19U)
104884 /*! CLK2OFFDS - USB 2.0 clock gate enable. Writing '1' to this bit disables hsfs clock turning-off
104885  *    when device enters L2 LPM state in HS/FS mode. The actual 'USB 2.0 clock gate' status in can be
104886  *    checked in the USB_STS.USB2OFF register. When both CLK2OFFDS and CLK2OFFEN bits are set to
104887  *    '1' while writing to USB_CONF register, the device behaviour is udefined. This bit is always '0'
104888  *    while reading
104889  */
104890 #define USB3_USB_CONF_CLK2OFFDS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK2OFFDS_SHIFT)) & USB3_USB_CONF_CLK2OFFDS_MASK)
104891 #define USB3_USB_CONF_LGO_L0_MASK                (0x100000U)
104892 #define USB3_USB_CONF_LGO_L0_SHIFT               (20U)
104893 /*! LGO_L0 - L0 LPM state entry request (HS/FS mode only). Writing '1' will trigger an attempt to
104894  *    perform transition to L0 LPM state. This bit will be automatically cleared to '0' after LPM
104895  *    enter L0 state. Result of the request (LPM enters L0 or not) can be verified by reading LPMST (LPM
104896  *    state) field in USB_STS register. Writing '0' has no effect. If the LPM is suspended (L2
104897  *    state) and CPU set this bit to'1', upstream will start driving resume signaling to indicate remote
104898  *    wakeup
104899  */
104900 #define USB3_USB_CONF_LGO_L0(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_L0_SHIFT)) & USB3_USB_CONF_LGO_L0_MASK)
104901 #define USB3_USB_CONF_CLK3OFFEN_MASK             (0x200000U)
104902 #define USB3_USB_CONF_CLK3OFFEN_SHIFT            (21U)
104903 /*! CLK3OFFEN - USB 3.0 clock gate disable. Writing '1' to this bit enables pclk clock turning-off
104904  *    when device enters U3 link state in SS mode. The actual 'USB 3.0 clock gate' status in can be
104905  *    checked in the USB_STS.USB3OFF register. When both CLK3OFFDS and CLK3OFFEN bits are set to '1'
104906  *    while writing to USB_CONF register, the device behaviour is udefined. This bit is always '0'
104907  *    while reading
104908  */
104909 #define USB3_USB_CONF_CLK3OFFEN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK3OFFEN_SHIFT)) & USB3_USB_CONF_CLK3OFFEN_MASK)
104910 #define USB3_USB_CONF_CLK3OFFDS_MASK             (0x400000U)
104911 #define USB3_USB_CONF_CLK3OFFDS_SHIFT            (22U)
104912 /*! CLK3OFFDS - USB 3.0 clock gate enable. Writing '1' to this bit disables pclk clock turning-off
104913  *    when device enters U3 link state in SS mode. The actual 'USB 3.0 clock gate' status in can be
104914  *    checked in the USB_STS.USB3OFF register. When both CLK3OFFDS and CLK3OFFEN bits are set to '1'
104915  *    while writing to USB_CONF register, the device behaviour is udefined. This bit is always '0'
104916  *    while reading
104917  */
104918 #define USB3_USB_CONF_CLK3OFFDS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK3OFFDS_SHIFT)) & USB3_USB_CONF_CLK3OFFDS_MASK)
104919 #define USB3_USB_CONF_RESERVED1_MASK             (0x800000U)
104920 #define USB3_USB_CONF_RESERVED1_SHIFT            (23U)
104921 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
104922  */
104923 #define USB3_USB_CONF_RESERVED1(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_RESERVED1_SHIFT)) & USB3_USB_CONF_RESERVED1_MASK)
104924 #define USB3_USB_CONF_U1EN_MASK                  (0x1000000U)
104925 #define USB3_USB_CONF_U1EN_SHIFT                 (24U)
104926 /*! U1EN - U1 state entry enable (device side, SS mode only), Writing '1' to this bit enables link
104927  *    layer to enter U1 state. Status of this bit can be checked in the USB_STS register. Writing '0'
104928  *    has no effect. When both U1EN and U1DS bits are set to '1' while writing to USB_CONF
104929  *    register, none of the operations associated with these bits will be performed. This bit is always '0'
104930  *    while reading
104931  */
104932 #define USB3_USB_CONF_U1EN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U1EN_SHIFT)) & USB3_USB_CONF_U1EN_MASK)
104933 #define USB3_USB_CONF_U1DS_MASK                  (0x2000000U)
104934 #define USB3_USB_CONF_U1DS_SHIFT                 (25U)
104935 /*! U1DS - U1 state entry disable (SS mode only). Writing '1' to this bit disables link layer from
104936  *    entering U1 state. Status of this bit can be checked in the USB_STS register. Writing '0' has
104937  *    no effect. When both U1EN and U1DS bits are set to '1' while writing to USB_CONF register, none
104938  *    of the operations associated with these bits will be performed. This bit is always '0' while
104939  *    reading
104940  */
104941 #define USB3_USB_CONF_U1DS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U1DS_SHIFT)) & USB3_USB_CONF_U1DS_MASK)
104942 #define USB3_USB_CONF_U2EN_MASK                  (0x4000000U)
104943 #define USB3_USB_CONF_U2EN_SHIFT                 (26U)
104944 /*! U2EN - U2 state entry enable (device side, SS mode only). Writing '1' to this bit enables link
104945  *    layer to enter U2 state. Status of this bit can be checked in the USB_STS register. Writing '0'
104946  *    has no effect. When both U2EN and U2DS bits are set to '1' while writing to USB_CONF
104947  *    register, the device behaviour is udefined. This bit is always '0' while reading
104948  */
104949 #define USB3_USB_CONF_U2EN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U2EN_SHIFT)) & USB3_USB_CONF_U2EN_MASK)
104950 #define USB3_USB_CONF_U2DS_MASK                  (0x8000000U)
104951 #define USB3_USB_CONF_U2DS_SHIFT                 (27U)
104952 /*! U2DS - U2 state entry disable (SS mode only). Writing '1' to this bit disables link layer from
104953  *    entering U2 state. Status of this bit can be checked in the USB_STS register. When both U2EN
104954  *    and U2DS bits are set to '1' while writing to USB_CONF register, the device behaviour is
104955  *    udefined. Writing '0' has no effect. This bit is always '0' while reading
104956  */
104957 #define USB3_USB_CONF_U2DS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U2DS_SHIFT)) & USB3_USB_CONF_U2DS_MASK)
104958 #define USB3_USB_CONF_LGO_U0_MASK                (0x10000000U)
104959 #define USB3_USB_CONF_LGO_U0_SHIFT               (28U)
104960 /*! LGO_U0 - U0 state entry request (SS mode only). Writing '1' will trigger an attempt to perform
104961  *    transition to U0 state. If the link is suspended (U3 state) and CPU set this bit to'1', link
104962  *    will start driving resume signaling on its upstream link to indicate remote wakeup. The Function
104963  *    Wake Notification should be send using USB_CMD.SDNFW bit. Writing '0' has no effect
104964  */
104965 #define USB3_USB_CONF_LGO_U0(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_U0_SHIFT)) & USB3_USB_CONF_LGO_U0_MASK)
104966 #define USB3_USB_CONF_LGO_U1_MASK                (0x20000000U)
104967 #define USB3_USB_CONF_LGO_U1_SHIFT               (29U)
104968 /*! LGO_U1 - U1 state entry request (SS mode only). Writing '1' will trigger an attempt to perform
104969  *    transition to U1 state. This bit will be automatically cleared to '0' after link layer finishes
104970  *    U1 request. Result of the request (link layer enters U1 or not) can be verified by reading
104971  *    LTS (link state) field in USB_STS register. Writing '1' has no effect when USB_STS.LGOU1ENS is
104972  *    set to '0'. Writing '0' has no effect
104973  */
104974 #define USB3_USB_CONF_LGO_U1(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_U1_SHIFT)) & USB3_USB_CONF_LGO_U1_MASK)
104975 #define USB3_USB_CONF_LGO_U2_MASK                (0x40000000U)
104976 #define USB3_USB_CONF_LGO_U2_SHIFT               (30U)
104977 /*! LGO_U2 - U2 state entry request (SS mode only). Writing '1' will trigger an attempt to perform
104978  *    transition to U2 state. This bit will be automatically cleared to '0' after link layer finishes
104979  *    U2 request. Result of the request (link layer enters U2 or not) can be verified by reading
104980  *    LTS (link state) field in USB_STS register. Writing '1' has no effect when USB_STS.LGOU2ENS is
104981  *    set to '0'. Writing '0' has no effect
104982  */
104983 #define USB3_USB_CONF_LGO_U2(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_U2_SHIFT)) & USB3_USB_CONF_LGO_U2_MASK)
104984 #define USB3_USB_CONF_LGO_SSINACT_MASK           (0x80000000U)
104985 #define USB3_USB_CONF_LGO_SSINACT_SHIFT          (31U)
104986 /*! LGO_SSINACT - SS.Inactive state entry request (SS mode only). This bit can be used only if
104987  *    USBSS-DEV is part of the CDNS USB OTG Controller (USB_CAP.OTG_READY bit is 1 while reading). In
104988  *    other cases should not be used and returns 0 when read. Writing '1' will trigger an attempt to
104989  *    perform transition to SS.Inactive state. Should be used only if Link is in U0 or Recovery state.
104990  *    This bit will be automatically cleared to '0' after link layer finishes SS.Inactive request.
104991  *    Result of the request (link layer enters SS.Inactive or not) can be verified by reading LTS
104992  *    (link state) field in USB_STS register. Writing '0' has no effect
104993  */
104994 #define USB3_USB_CONF_LGO_SSINACT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_SSINACT_SHIFT)) & USB3_USB_CONF_LGO_SSINACT_MASK)
104995 /*! @} */
104996 
104997 /*! @name USB_STS - Global Status */
104998 /*! @{ */
104999 #define USB3_USB_STS_CFGSTS_MASK                 (0x1U)
105000 #define USB3_USB_STS_CFGSTS_SHIFT                (0U)
105001 /*! CFGSTS - Configuration status. 1 - device is in the configured state 0 - device is not
105002  *    configured This bit set during SET_CONFIGURATION request means that status stage of this request was
105003  *    finished successfully, thus device configuration was finished successfully
105004  */
105005 #define USB3_USB_STS_CFGSTS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_CFGSTS_SHIFT)) & USB3_USB_STS_CFGSTS_MASK)
105006 #define USB3_USB_STS_MEM_OV_MASK                 (0x2U)
105007 #define USB3_USB_STS_MEM_OV_SHIFT                (1U)
105008 /*! MEM_OV - On-chip memory overflow. 0 - On-chip memory status OK 1 - On-chip memory overflow
105009  *    Memory overflow may occur if, during enumeration (SET_CONFIGURATION request) device software will
105010  *    try to turn on too many endpoints or will try to set too much endpoinds buffers (see
105011  *    EP_CFG.BUFFERING). After each completion of enumeration software should check this bit, and when a
105012  *    memory overflow occurred, software must delete current configuration (using USB_CONF.CFGRST bit)
105013  *    and then set the one that requires less on-chip memory. For available memory calculation, the
105014  *    CDNS_USBSSDEV_ATTACHED_MEM_SIZE define parameter is used
105015  */
105016 #define USB3_USB_STS_MEM_OV(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_MEM_OV_SHIFT)) & USB3_USB_STS_MEM_OV_MASK)
105017 #define USB3_USB_STS_USB3CONS_MASK               (0x4U)
105018 #define USB3_USB_STS_USB3CONS_SHIFT              (2U)
105019 /*! USB3CONS - SuperSpeed connection status. 0 - USB in SuperSpeed mode disconnected 1 - USB in SuperSpeed mode connected
105020  */
105021 #define USB3_USB_STS_USB3CONS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_USB3CONS_SHIFT)) & USB3_USB_STS_USB3CONS_MASK)
105022 #define USB3_USB_STS_DTRANS_MASK                 (0x8U)
105023 #define USB3_USB_STS_DTRANS_SHIFT                (3U)
105024 /*! DTRANS - DMA transfer configuration status. 0 - single request - Single TRB chain. Single
105025  *    request (DRDY/Doorbell) triggers DMA, which transfers single TRB chain only and ends the EP
105026  *    transfer. 1 - single request - Multiple TRB chain. Single request (DRDY/Doorbell) triggers DMA which
105027  *    transfers TRB chains until the owner of the new chain is not DMA (this causes a TRB error
105028  *    interrupt). This DMA transfer configuration settings can be changed by using bits USB_CONF.DSING
105029  *    and USB_CONF.DMULT
105030  */
105031 #define USB3_USB_STS_DTRANS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DTRANS_SHIFT)) & USB3_USB_STS_DTRANS_MASK)
105032 #define USB3_USB_STS_USBSPEED_MASK               (0x70U)
105033 #define USB3_USB_STS_USBSPEED_SHIFT              (4U)
105034 /*! USBSPEED - Device speed: 0: undef., 1: LowSpeed (not supported), 2: FullSpeed, 3: HighSpeed, 4: SuperSpeed, 5-7: Reserved
105035  */
105036 #define USB3_USB_STS_USBSPEED(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_USBSPEED_SHIFT)) & USB3_USB_STS_USBSPEED_MASK)
105037 #define USB3_USB_STS_ENDIAN_MIRROR_MASK          (0x80U)
105038 #define USB3_USB_STS_ENDIAN_MIRROR_SHIFT         (7U)
105039 /*! ENDIAN_MIRROR - Little/Big Endian byte order for SFR access. 0 - Little Endian order (default
105040  *    after hardware reset) 1 - Big Endian order Endian byte order for SFR access can be changed by
105041  *    setting BENDIAN or LEDNIAN bits in USB_CONF
105042  */
105043 #define USB3_USB_STS_ENDIAN_MIRROR(x)            (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_ENDIAN_MIRROR_SHIFT)) & USB3_USB_STS_ENDIAN_MIRROR_MASK)
105044 #define USB3_USB_STS_CLK2OFF_MASK                (0x100U)
105045 #define USB3_USB_STS_CLK2OFF_SHIFT               (8U)
105046 /*! CLK2OFF - HS/FS clock turn-off status. When CLK2OFF bit is '0', the utmisuspendm output signal
105047  *    is not set low in USB2.0 suspend state (L2 state), thus USB2.0 PHY does not turn off the hsfs
105048  *    clock 0 - hsfs clock is always on 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
105049  *    (default after hardware reset)
105050  */
105051 #define USB3_USB_STS_CLK2OFF(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_CLK2OFF_SHIFT)) & USB3_USB_STS_CLK2OFF_MASK)
105052 #define USB3_USB_STS_CLK3OFF_MASK                (0x200U)
105053 #define USB3_USB_STS_CLK3OFF_SHIFT               (9U)
105054 /*! CLK3OFF - PCLK clock turn-off status. When CLK3OFF bit is '0', the phypowerdown output signal is
105055  *    not set to '11' in U3 link state, thus USB3.0 PHY does not turn off the pclk clock. 0 - pclk
105056  *    clock is always on 1 - pclk clock turn-off in U3 (SS mode) is enabled (default after hardware
105057  *    reset)
105058  */
105059 #define USB3_USB_STS_CLK3OFF(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_CLK3OFF_SHIFT)) & USB3_USB_STS_CLK3OFF_MASK)
105060 #define USB3_USB_STS_IN_RST_MASK                 (0x400U)
105061 #define USB3_USB_STS_IN_RST_SHIFT                (10U)
105062 /*! IN_RST - Controler in reset state. This bit indicate that whole (in case of POR) or part of
105063  *    controller (in case of SWRST or USB resets) currently is in reset state. As controller has
105064  *    registers in both clock domains (system, and USB), internal reset synchronization between these
105065  *    domains may take longer than the cause of the reset (e.g active reset_n input). Thus it is
105066  *    recommended to check if controller is not in reset state, before software starts its operations
105067  *    (especially after POR). 0 - Internal reset is active 1 - Internal reset is not active and controller
105068  *    is fully operational
105069  */
105070 #define USB3_USB_STS_IN_RST(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_IN_RST_SHIFT)) & USB3_USB_STS_IN_RST_MASK)
105071 #define USB3_USB_STS_RESERVED0_MASK              (0x3800U)
105072 #define USB3_USB_STS_RESERVED0_SHIFT             (11U)
105073 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
105074  */
105075 #define USB3_USB_STS_RESERVED0(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_RESERVED0_SHIFT)) & USB3_USB_STS_RESERVED0_MASK)
105076 #define USB3_USB_STS_DEVS_MASK                   (0x4000U)
105077 #define USB3_USB_STS_DEVS_SHIFT                  (14U)
105078 /*! DEVS - Device enable Status 0 - USB device is disabled (VBUS input is disconnected from internal
105079  *    logic) 1 - USB device is enabled (VBUS input is connected to the internal logic) This bit can
105080  *    be changed by setting DEVEN or DEVDS bits in USB_CONF
105081  */
105082 #define USB3_USB_STS_DEVS(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DEVS_SHIFT)) & USB3_USB_STS_DEVS_MASK)
105083 #define USB3_USB_STS_ADDRESSED_MASK              (0x8000U)
105084 #define USB3_USB_STS_ADDRESSED_SHIFT             (15U)
105085 /*! ADDRESSED - Address status: 0 - USB device is default state 1 - USB device is at least in
105086  *    address state (Function Address was set by the SW)
105087  */
105088 #define USB3_USB_STS_ADDRESSED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_ADDRESSED_SHIFT)) & USB3_USB_STS_ADDRESSED_MASK)
105089 #define USB3_USB_STS_L1ENS_MASK                  (0x10000U)
105090 #define USB3_USB_STS_L1ENS_SHIFT                 (16U)
105091 /*! L1ENS - L1 LPM state enable status (valid for HS/FS mode only). 0 - Entering to L1 LPM state
105092  *    disabled 1 - Entering to L1 LPM state enabled
105093  */
105094 #define USB3_USB_STS_L1ENS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_L1ENS_SHIFT)) & USB3_USB_STS_L1ENS_MASK)
105095 #define USB3_USB_STS_VBUSS_MASK                  (0x20000U)
105096 #define USB3_USB_STS_VBUSS_SHIFT                 (17U)
105097 /*! VBUSS - Internal VBUS connection status. 0 - internal VBUS is not detected 1 - internal VBUS is detected
105098  */
105099 #define USB3_USB_STS_VBUSS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_VBUSS_SHIFT)) & USB3_USB_STS_VBUSS_MASK)
105100 #define USB3_USB_STS_LPMST_MASK                  (0xC0000U)
105101 #define USB3_USB_STS_LPMST_SHIFT                 (18U)
105102 /*! LPMST - HS/FS LPM state (valid for HS/FS mode only). This field reflects USBSS-DEV current LPM
105103  *    (used in HS/FS mode) state: 0 - L0 State 1 - L1 State 2 - L2 State 3 - L3 State
105104  */
105105 #define USB3_USB_STS_LPMST(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_LPMST_SHIFT)) & USB3_USB_STS_LPMST_MASK)
105106 #define USB3_USB_STS_USB2CONS_MASK               (0x100000U)
105107 #define USB3_USB_STS_USB2CONS_SHIFT              (20U)
105108 /*! USB2CONS - HS/FS mode connection enable status (valid for HS/FS mode only). 0 - the disconnect
105109  *    bit for HS/FS mode is set (USB_CONF.USB2DIS) 1 - the disconnect bit for HS/FS mode is not set
105110  *    (device can be connected in this mode) The actual connection status can be checked in the
105111  *    USB_STS.USBSPEED
105112  */
105113 #define USB3_USB_STS_USB2CONS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_USB2CONS_SHIFT)) & USB3_USB_STS_USB2CONS_MASK)
105114 #define USB3_USB_STS_DISABLE_HS_MASK             (0x200000U)
105115 #define USB3_USB_STS_DISABLE_HS_SHIFT            (21U)
105116 /*! DISABLE_HS - DisableHS status (valid for HS/FS mode only) 0 - High Speed operations in USB2.0
105117  *    (FS/HS) mode not disabled 1 - High Speed operations in USB2.0 (FS/HS) mode disabled
105118  */
105119 #define USB3_USB_STS_DISABLE_HS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DISABLE_HS_SHIFT)) & USB3_USB_STS_DISABLE_HS_MASK)
105120 #define USB3_USB_STS_RESERVED1_MASK              (0xC00000U)
105121 #define USB3_USB_STS_RESERVED1_SHIFT             (22U)
105122 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
105123  */
105124 #define USB3_USB_STS_RESERVED1(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_RESERVED1_SHIFT)) & USB3_USB_STS_RESERVED1_MASK)
105125 #define USB3_USB_STS_U1ENS_MASK                  (0x1000000U)
105126 #define USB3_USB_STS_U1ENS_SHIFT                 (24U)
105127 /*! U1ENS - U1 state enable status (valid in SS mode only): 0 - Entering to U1 state disabled 1 - Entering to U1 state enabled
105128  */
105129 #define USB3_USB_STS_U1ENS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_U1ENS_SHIFT)) & USB3_USB_STS_U1ENS_MASK)
105130 #define USB3_USB_STS_U2ENS_MASK                  (0x2000000U)
105131 #define USB3_USB_STS_U2ENS_SHIFT                 (25U)
105132 /*! U2ENS - U2 state enable status (valid in SS mode only): 0 - Entering to U2 state disabled 1 - Entering to U2 state enabled
105133  */
105134 #define USB3_USB_STS_U2ENS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_U2ENS_SHIFT)) & USB3_USB_STS_U2ENS_MASK)
105135 #define USB3_USB_STS_LST_MASK                    (0x3C000000U)
105136 #define USB3_USB_STS_LST_SHIFT                   (26U)
105137 /*! LST - SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current SuperSpeed link state:
105138  *    0 - U0 State 1 - U1 State 2 - U2 State 3 - U3 State (Device Suspended) 4 - Disabled State 5 -
105139  *    RxDetect State 6 - Inactive State 7 - Polling State 8 - Recovery State 9 - Hot Reset State 10
105140  *    - Compliance Mode State 11 - Loopback State 12:14 - Reserved 15 - Uninitialized
105141  */
105142 #define USB3_USB_STS_LST(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_LST_SHIFT)) & USB3_USB_STS_LST_MASK)
105143 #define USB3_USB_STS_DMAOFF_MASK                 (0x40000000U)
105144 #define USB3_USB_STS_DMAOFF_SHIFT                (30U)
105145 /*! DMAOFF - DMA clock turn-off status. DMA clock turn-off/enable status: 0 - DMA clock is always on
105146  *    (default after hardware reset) 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled
105147  */
105148 #define USB3_USB_STS_DMAOFF(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DMAOFF_SHIFT)) & USB3_USB_STS_DMAOFF_MASK)
105149 #define USB3_USB_STS_ENDIAN_MASK                 (0x80000000U)
105150 #define USB3_USB_STS_ENDIAN_SHIFT                (31U)
105151 /*! ENDIAN - SFR Endian status. Little/Big Endian byte order for SFR access: 0 - Little Endian order
105152  *    (default after hardware reset) 1 - Big Endian order
105153  */
105154 #define USB3_USB_STS_ENDIAN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_ENDIAN_SHIFT)) & USB3_USB_STS_ENDIAN_MASK)
105155 /*! @} */
105156 
105157 /*! @name USB_CMD - Global Command */
105158 /*! @{ */
105159 #define USB3_USB_CMD_SET_ADDR_MASK               (0x1U)
105160 #define USB3_USB_CMD_SET_ADDR_SHIFT              (0U)
105161 /*! SET_ADDR - Set Function Address. Writing the value '1 'to this bit causes the device is assigned
105162  *    to the USB Function Address according to the FADDR field. The device address must be saved by
105163  *    software when operating SET_ADDRESS request. After saving device address, software should set
105164  *    the EP_CMD.ERDY bit (as with all other requests) to quit the setup phase and then set bit
105165  *    EP_CMD.REQ_CMPL to confirm the status of the host phase. Writing '0 'has no effect. This bit is
105166  *    always '0' while reading
105167  */
105168 #define USB3_USB_CMD_SET_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SET_ADDR_SHIFT)) & USB3_USB_CMD_SET_ADDR_MASK)
105169 #define USB3_USB_CMD_FADDR_MASK                  (0xFEU)
105170 #define USB3_USB_CMD_FADDR_SHIFT                 (1U)
105171 /*! FADDR - Function Address. This field is saved to the device only when the field SET_ADDR is set
105172  *    '1 ' during write to USB_CMD register. Software is responsible for entering the address of the
105173  *    device during SET_ADDRESS request service. This field should be set immediately after the
105174  *    SETUP packet is decoded, and prior to confirmation of the status phase (what is done by bit
105175  *    EP_CMD.REQ_CMPL) Verify that the device successfully completed the SET_ADDRESS request and is in
105176  *    ADRESSED state (as defined in USB3 spec) can be realized by checking the bit USB_STS. ADRESSED.
105177  *    USB_CMD.FADDR field can also be read at any time. This field is always '0' while reading
105178  */
105179 #define USB3_USB_CMD_FADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_FADDR_SHIFT)) & USB3_USB_CMD_FADDR_MASK)
105180 #define USB3_USB_CMD_SDNFW_MASK                  (0x100U)
105181 #define USB3_USB_CMD_SDNFW_SHIFT                 (8U)
105182 /*! SDNFW - Send Function Wake Device Notification TP (SS mode only). Writing '1' will trigger an
105183  *    attempt to send 'Device Notification' with 'Interface' field set to DNFW_INT. This bit will be
105184  *    automatically cleared if the FW Notification TP is sent and only then the new FW Notification
105185  *    TP or the other TP (by means of SPKT or SDNLTM bits) can be send again. Writing '0' has no
105186  *    effect. This bit cannot be written by '1' simultaneously with SPKT and SDNLTM bits
105187  */
105188 #define USB3_USB_CMD_SDNFW(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SDNFW_SHIFT)) & USB3_USB_CMD_SDNFW_MASK)
105189 #define USB3_USB_CMD_STMODE_MASK                 (0x200U)
105190 #define USB3_USB_CMD_STMODE_SHIFT                (9U)
105191 /*! STMODE - Set Test Mode (HS/FS mode only). Writing the value '1 'to this bit causes the device
105192  *    enters into test mode selected by the TMODE_SEL field. Writing '0' has no effect. This bit is
105193  *    always '0' while reading
105194  */
105195 #define USB3_USB_CMD_STMODE(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_STMODE_SHIFT)) & USB3_USB_CMD_STMODE_MASK)
105196 #define USB3_USB_CMD_TMODE_SEL_MASK              (0xC00U)
105197 #define USB3_USB_CMD_TMODE_SEL_SHIFT             (10U)
105198 /*! TMODE_SEL - Test mode selector (HS/FS mode only). This field contains selected Test Mode -
105199  *    Device will enter this Test mode when '1' is written to STMODE. USB 2.0 Test mode selector: 00 -
105200  *    Test_J, 01 - Test_K, 10 - Test_SE0_NAK, 11 - Test_Packet This field is always '0' while reading
105201  */
105202 #define USB3_USB_CMD_TMODE_SEL(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_TMODE_SEL_SHIFT)) & USB3_USB_CMD_TMODE_SEL_MASK)
105203 #define USB3_USB_CMD_SDNLTM_MASK                 (0x1000U)
105204 #define USB3_USB_CMD_SDNLTM_SHIFT                (12U)
105205 /*! SDNLTM - Send Latency Tolerance Message Device Notification TP (SS mode only). Writing '1' will
105206  *    trigger an attempt to send Device Notification 'Latency Tolerance Message' with 'BELT' field
105207  *    set to DNLTM_BELT. This bit will be automatically cleared if the LTM Notification TP is sent
105208  *    and only then the new LTM Notification TP or the other TP (by means of SPKT or SDNFW bits) can
105209  *    be send again. Writing '0' has no effect. This bit cannot be written by '1' simultaneously with
105210  *    SPKT and SDNFW bits
105211  */
105212 #define USB3_USB_CMD_SDNLTM(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SDNLTM_SHIFT)) & USB3_USB_CMD_SDNLTM_MASK)
105213 #define USB3_USB_CMD_SPKT_MASK                   (0x2000U)
105214 #define USB3_USB_CMD_SPKT_SHIFT                  (13U)
105215 /*! SPKT - Send Custom Transaction Packet (SS mode only) Writing '1' will trigger an attempt to send
105216  *    Custom TP as defined in the USB3.0 specification. The packet contents that will be send as TP
105217  *    to the host must be previously prepared in the CPKT1 (will be sent as DWORD 0 in the TP),
105218  *    CPKT2 (will be sent as DWORD 1 in the TP) and CPKT3 (will be sent as DWORD 2 in the TP)
105219  *    registers. Note that TP DWORD 3 will be automatically inserted by the device controller. This bit will
105220  *    be automatically cleared if this TP is sent and only then the new Custom TP (by means of SPKT
105221  *    bit) or other Notification TP (by means of SDNLTM or SDNFW bits) can be send again. Writing 0
105222  *    has no effect. This bit cannot be written by 1 simultaneously with SDNLTM and SDNFW bits
105223  */
105224 #define USB3_USB_CMD_SPKT(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SPKT_SHIFT)) & USB3_USB_CMD_SPKT_MASK)
105225 #define USB3_USB_CMD_RESERVED0_MASK              (0xC000U)
105226 #define USB3_USB_CMD_RESERVED0_SHIFT             (14U)
105227 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
105228  */
105229 #define USB3_USB_CMD_RESERVED0(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_RESERVED0_SHIFT)) & USB3_USB_CMD_RESERVED0_MASK)
105230 #define USB3_USB_CMD_DNLTM_BELT_7_0_MASK         (0xFF0000U)
105231 #define USB3_USB_CMD_DNLTM_BELT_7_0_SHIFT        (16U)
105232 /*! DNLTM_BELT_7_0 - Device Notification 'Latency Tolerance Message' - BELT value [7:0] / Device
105233  *    Notification 'Function Wake' - Interface value (SS mode only). This field must be filled up
105234  *    before one of the USB_CMD.SDNLTM/SDNFW bits is set, and cannot be changed while
105235  *    USB_CMD.SDNLTM/SDNFW bits are not zero (Device Notification is being sent by the device controller). If user
105236  *    writes '1' to SDNFW bit the device will send Device Notification 'Function Wake' with
105237  *    'Interface[7:0]' field value equal to DNLTM_BELT_7_0. If user writes '1' to SDNLTM bit, the device will
105238  *    send Device Notification 'Latency Tolerance Message' with 'BELT[7:0]' field value equal to
105239  *    DNLTM_BELT_7_0. This field is always '0' while reading
105240  */
105241 #define USB3_USB_CMD_DNLTM_BELT_7_0(x)           (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_DNLTM_BELT_7_0_SHIFT)) & USB3_USB_CMD_DNLTM_BELT_7_0_MASK)
105242 #define USB3_USB_CMD_DNLTM_BELT_11_8_MASK        (0xF000000U)
105243 #define USB3_USB_CMD_DNLTM_BELT_11_8_SHIFT       (24U)
105244 /*! DNLTM_BELT_11_8 - Device Notification 'Latency Tolerance Message' - BELT value [11:8] (SS mode
105245  *    only). If user writes '1' to SDNLTM bit, the device will send Device Notification 'Latency
105246  *    Tolerance Message' with 'BELT[11:8]' field value equal to DNLTM_BELT_11_8. This field must be
105247  *    filled up before the USB_CMD.SDNLTM bit is set, and cannot be changed while USB_CMD.SDNLTM bit is
105248  *    not zero (Device Notification is being sent by the device controller) This field is always '0'
105249  *    while reading
105250  */
105251 #define USB3_USB_CMD_DNLTM_BELT_11_8(x)          (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_DNLTM_BELT_11_8_SHIFT)) & USB3_USB_CMD_DNLTM_BELT_11_8_MASK)
105252 #define USB3_USB_CMD_RESERVED1_MASK              (0xF0000000U)
105253 #define USB3_USB_CMD_RESERVED1_SHIFT             (28U)
105254 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
105255  */
105256 #define USB3_USB_CMD_RESERVED1(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_RESERVED1_SHIFT)) & USB3_USB_CMD_RESERVED1_MASK)
105257 /*! @} */
105258 
105259 /*! @name USB_IPTN - ITP Number */
105260 /*! @{ */
105261 #define USB3_USB_IPTN_ITPN_MASK                  (0x3FFFU)
105262 #define USB3_USB_IPTN_ITPN_SHIFT                 (0U)
105263 /*! ITPN - ITP(SS) / SOF (HS/FS) number. In SS mode this field represent number of last ITP received
105264  *    from host. In HS/FS mode this field represent number of last SOF received from host
105265  */
105266 #define USB3_USB_IPTN_ITPN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_IPTN_ITPN_SHIFT)) & USB3_USB_IPTN_ITPN_MASK)
105267 #define USB3_USB_IPTN_RESERVED_MASK              (0xFFFFC000U)
105268 #define USB3_USB_IPTN_RESERVED_SHIFT             (14U)
105269 /*! RESERVED - Reserved field. Write ignored. 0 when read
105270  */
105271 #define USB3_USB_IPTN_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IPTN_RESERVED_SHIFT)) & USB3_USB_IPTN_RESERVED_MASK)
105272 /*! @} */
105273 
105274 /*! @name USB_LPM - Link Power Management */
105275 /*! @{ */
105276 #define USB3_USB_LPM_HIRD_MASK                   (0xFU)
105277 #define USB3_USB_LPM_HIRD_SHIFT                  (0U)
105278 /*! HIRD - Host Initiated Resume Duration. This is the Resume duration from L1 LPM state, received
105279  *    from the host in the latest Extended Token packet. For more information see chapter: 'HS/FS
105280  *    mode - Link Power Management'
105281  */
105282 #define USB3_USB_LPM_HIRD(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_USB_LPM_HIRD_SHIFT)) & USB3_USB_LPM_HIRD_MASK)
105283 #define USB3_USB_LPM_BRW_MASK                    (0x10U)
105284 #define USB3_USB_LPM_BRW_SHIFT                   (4U)
105285 /*! BRW - Remote Wakeup Enable (bRemoteWake)
105286  */
105287 #define USB3_USB_LPM_BRW(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USB_LPM_BRW_SHIFT)) & USB3_USB_LPM_BRW_MASK)
105288 #define USB3_USB_LPM_RESERVED_MASK               (0xFFFFFFE0U)
105289 #define USB3_USB_LPM_RESERVED_SHIFT              (5U)
105290 /*! RESERVED - Reserved field. Write ignored. 0 when read
105291  */
105292 #define USB3_USB_LPM_RESERVED(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_LPM_RESERVED_SHIFT)) & USB3_USB_LPM_RESERVED_MASK)
105293 /*! @} */
105294 
105295 /*! @name USB_IEN - Interrupt Enable */
105296 /*! @{ */
105297 #define USB3_USB_IEN_CONIEN_MASK                 (0x1U)
105298 #define USB3_USB_IEN_CONIEN_SHIFT                (0U)
105299 /*! CONIEN - SS connection interrupt enable. This bit enables requesting a CONI interrupt
105300  */
105301 #define USB3_USB_IEN_CONIEN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_CONIEN_SHIFT)) & USB3_USB_IEN_CONIEN_MASK)
105302 #define USB3_USB_IEN_DISIEN_MASK                 (0x2U)
105303 #define USB3_USB_IEN_DISIEN_SHIFT                (1U)
105304 /*! DISIEN - SS disconnection interrupt enable. This bit enables requesting a DISI interrupt
105305  */
105306 #define USB3_USB_IEN_DISIEN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_DISIEN_SHIFT)) & USB3_USB_IEN_DISIEN_MASK)
105307 #define USB3_USB_IEN_UWRESIEN_MASK               (0x4U)
105308 #define USB3_USB_IEN_UWRESIEN_SHIFT              (2U)
105309 /*! UWRESIEN - USB SS warm reset interrupt enable. This bit enables requesting an UWRESI interrupt
105310  */
105311 #define USB3_USB_IEN_UWRESIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UWRESIEN_SHIFT)) & USB3_USB_IEN_UWRESIEN_MASK)
105312 #define USB3_USB_IEN_UHRESIEN_MASK               (0x8U)
105313 #define USB3_USB_IEN_UHRESIEN_SHIFT              (3U)
105314 /*! UHRESIEN - USB SS hot reset interrupt enable. This bit enables requesting an UHRESI interrupt
105315  */
105316 #define USB3_USB_IEN_UHRESIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UHRESIEN_SHIFT)) & USB3_USB_IEN_UHRESIEN_MASK)
105317 #define USB3_USB_IEN_U3ENTIEN_MASK               (0x10U)
105318 #define USB3_USB_IEN_U3ENTIEN_SHIFT              (4U)
105319 /*! U3ENTIEN - SS link U3 state enter interrupt enable (suspend). This bit enables requesting an U3ENTI interrupt
105320  */
105321 #define USB3_USB_IEN_U3ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U3ENTIEN_SHIFT)) & USB3_USB_IEN_U3ENTIEN_MASK)
105322 #define USB3_USB_IEN_U3EXTIEN_MASK               (0x20U)
105323 #define USB3_USB_IEN_U3EXTIEN_SHIFT              (5U)
105324 /*! U3EXTIEN - SS link U3 state exit interrupt enable (wakeup). This bit enables requesting an U3EXTI interrupt
105325  */
105326 #define USB3_USB_IEN_U3EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U3EXTIEN_SHIFT)) & USB3_USB_IEN_U3EXTIEN_MASK)
105327 #define USB3_USB_IEN_U2ENTIEN_MASK               (0x40U)
105328 #define USB3_USB_IEN_U2ENTIEN_SHIFT              (6U)
105329 /*! U2ENTIEN - SS link U2 state enter interrupt enable. This bit enables requesting an U2ENTI interrupt
105330  */
105331 #define USB3_USB_IEN_U2ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U2ENTIEN_SHIFT)) & USB3_USB_IEN_U2ENTIEN_MASK)
105332 #define USB3_USB_IEN_U2EXTIEN_MASK               (0x80U)
105333 #define USB3_USB_IEN_U2EXTIEN_SHIFT              (7U)
105334 /*! U2EXTIEN - SS link U2 state exit interrupt enable. This bit enables requesting an U2EXTI interrupt
105335  */
105336 #define USB3_USB_IEN_U2EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U2EXTIEN_SHIFT)) & USB3_USB_IEN_U2EXTIEN_MASK)
105337 #define USB3_USB_IEN_U1ENTIEN_MASK               (0x100U)
105338 #define USB3_USB_IEN_U1ENTIEN_SHIFT              (8U)
105339 /*! U1ENTIEN - SS link U1 state enter interrupt enable. This bit enables requesting an U1ENTI interrupt
105340  */
105341 #define USB3_USB_IEN_U1ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U1ENTIEN_SHIFT)) & USB3_USB_IEN_U1ENTIEN_MASK)
105342 #define USB3_USB_IEN_U1EXTIEN_MASK               (0x200U)
105343 #define USB3_USB_IEN_U1EXTIEN_SHIFT              (9U)
105344 /*! U1EXTIEN - SS link U1 state exit interrupt enable. This bit enables requesting an U1EXTI interrupt
105345  */
105346 #define USB3_USB_IEN_U1EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U1EXTIEN_SHIFT)) & USB3_USB_IEN_U1EXTIEN_MASK)
105347 #define USB3_USB_IEN_ITPIEN_MASK                 (0x400U)
105348 #define USB3_USB_IEN_ITPIEN_SHIFT                (10U)
105349 /*! ITPIEN - ITP/SOF packet detected interrupt enable. This bit enables requesting an ITPI interrupt
105350  */
105351 #define USB3_USB_IEN_ITPIEN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_ITPIEN_SHIFT)) & USB3_USB_IEN_ITPIEN_MASK)
105352 #define USB3_USB_IEN_WAKEIEN_MASK                (0x800U)
105353 #define USB3_USB_IEN_WAKEIEN_SHIFT               (11U)
105354 /*! WAKEIEN - Wakeup interrupt enable. This bit enables requesting a Wakeup interrupt
105355  */
105356 #define USB3_USB_IEN_WAKEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_WAKEIEN_SHIFT)) & USB3_USB_IEN_WAKEIEN_MASK)
105357 #define USB3_USB_IEN_SPKTIEN_MASK                (0x1000U)
105358 #define USB3_USB_IEN_SPKTIEN_SHIFT               (12U)
105359 /*! SPKTIEN - Send Custom Packet interrupt enable. This bit enables requesting a Send Custom Packet interrupt
105360  */
105361 #define USB3_USB_IEN_SPKTIEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_SPKTIEN_SHIFT)) & USB3_USB_IEN_SPKTIEN_MASK)
105362 #define USB3_USB_IEN_RESERVED0_MASK              (0xE000U)
105363 #define USB3_USB_IEN_RESERVED0_SHIFT             (13U)
105364 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
105365  */
105366 #define USB3_USB_IEN_RESERVED0(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED0_SHIFT)) & USB3_USB_IEN_RESERVED0_MASK)
105367 #define USB3_USB_IEN_CON2IEN_MASK                (0x10000U)
105368 #define USB3_USB_IEN_CON2IEN_SHIFT               (16U)
105369 /*! CON2IEN - HS/FS mode connection interrupt enable. This bit enables requesting a CON2I interrupt
105370  */
105371 #define USB3_USB_IEN_CON2IEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_CON2IEN_SHIFT)) & USB3_USB_IEN_CON2IEN_MASK)
105372 #define USB3_USB_IEN_DIS2IEN_MASK                (0x20000U)
105373 #define USB3_USB_IEN_DIS2IEN_SHIFT               (17U)
105374 /*! DIS2IEN - HS/FS mode disconnection interrupt enable. This bit enables requesting a DIS2I interrupt
105375  */
105376 #define USB3_USB_IEN_DIS2IEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_DIS2IEN_SHIFT)) & USB3_USB_IEN_DIS2IEN_MASK)
105377 #define USB3_USB_IEN_U2RESIEN_MASK               (0x40000U)
105378 #define USB3_USB_IEN_U2RESIEN_SHIFT              (18U)
105379 /*! U2RESIEN - USB reset (HS/FS mode) interrupt enable. This bit enables requesting an U2RESI interrupt
105380  */
105381 #define USB3_USB_IEN_U2RESIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U2RESIEN_SHIFT)) & USB3_USB_IEN_U2RESIEN_MASK)
105382 #define USB3_USB_IEN_RESERVED1_MASK              (0x80000U)
105383 #define USB3_USB_IEN_RESERVED1_SHIFT             (19U)
105384 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
105385  */
105386 #define USB3_USB_IEN_RESERVED1(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED1_SHIFT)) & USB3_USB_IEN_RESERVED1_MASK)
105387 #define USB3_USB_IEN_L2ENTIEN_MASK               (0x100000U)
105388 #define USB3_USB_IEN_L2ENTIEN_SHIFT              (20U)
105389 /*! L2ENTIEN - LPM L2 state enter interrupt enable. This bit enables requesting a L2ENTI interrupt
105390  */
105391 #define USB3_USB_IEN_L2ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L2ENTIEN_SHIFT)) & USB3_USB_IEN_L2ENTIEN_MASK)
105392 #define USB3_USB_IEN_L2EXTIEN_MASK               (0x200000U)
105393 #define USB3_USB_IEN_L2EXTIEN_SHIFT              (21U)
105394 /*! L2EXTIEN - LPM L2 state exit interrupt enable. This bit enables requesting a L2EXTI interrupt
105395  */
105396 #define USB3_USB_IEN_L2EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L2EXTIEN_SHIFT)) & USB3_USB_IEN_L2EXTIEN_MASK)
105397 #define USB3_USB_IEN_RESERVED2_MASK              (0xC00000U)
105398 #define USB3_USB_IEN_RESERVED2_SHIFT             (22U)
105399 /*! RESERVED2 - Reserved field. Write ignored. 0 when read
105400  */
105401 #define USB3_USB_IEN_RESERVED2(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED2_SHIFT)) & USB3_USB_IEN_RESERVED2_MASK)
105402 #define USB3_USB_IEN_L1ENTIEN_MASK               (0x1000000U)
105403 #define USB3_USB_IEN_L1ENTIEN_SHIFT              (24U)
105404 /*! L1ENTIEN - LPM L1 state enter interrupt enable. This bit enables requesting an L1ENTI interrupt
105405  */
105406 #define USB3_USB_IEN_L1ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L1ENTIEN_SHIFT)) & USB3_USB_IEN_L1ENTIEN_MASK)
105407 #define USB3_USB_IEN_L1EXTIEN_MASK               (0x2000000U)
105408 #define USB3_USB_IEN_L1EXTIEN_SHIFT              (25U)
105409 /*! L1EXTIEN - LPM L1 state exit interrupt enable. This bit enables requesting an L1EXTI interrupt
105410  */
105411 #define USB3_USB_IEN_L1EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L1EXTIEN_SHIFT)) & USB3_USB_IEN_L1EXTIEN_MASK)
105412 #define USB3_USB_IEN_CFGRESIEN_MASK              (0x4000000U)
105413 #define USB3_USB_IEN_CFGRESIEN_SHIFT             (26U)
105414 /*! CFGRESIEN - Configuration reset interrupt enable. This bit enables requesting a CFGRESI interrupt
105415  */
105416 #define USB3_USB_IEN_CFGRESIEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_CFGRESIEN_SHIFT)) & USB3_USB_IEN_CFGRESIEN_MASK)
105417 #define USB3_USB_IEN_RESERVED3_MASK              (0x8000000U)
105418 #define USB3_USB_IEN_RESERVED3_SHIFT             (27U)
105419 /*! RESERVED3 - Reserved field. Write ignored. 0 when read
105420  */
105421 #define USB3_USB_IEN_RESERVED3(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED3_SHIFT)) & USB3_USB_IEN_RESERVED3_MASK)
105422 #define USB3_USB_IEN_UWRESSIEN_MASK              (0x10000000U)
105423 #define USB3_USB_IEN_UWRESSIEN_SHIFT             (28U)
105424 /*! UWRESSIEN - Start of the USB SS warm reset interrupt enable. This bit enables requesting a UWRESSI interrupt
105425  */
105426 #define USB3_USB_IEN_UWRESSIEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UWRESSIEN_SHIFT)) & USB3_USB_IEN_UWRESSIEN_MASK)
105427 #define USB3_USB_IEN_UWRESEIEN_MASK              (0x20000000U)
105428 #define USB3_USB_IEN_UWRESEIEN_SHIFT             (29U)
105429 /*! UWRESEIEN - End of the USB SS warm reset interrupt enable. This bit enables requesting a UWRESEI interrupt
105430  */
105431 #define USB3_USB_IEN_UWRESEIEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UWRESEIEN_SHIFT)) & USB3_USB_IEN_UWRESEIEN_MASK)
105432 #define USB3_USB_IEN_RESERVED4_MASK              (0xC0000000U)
105433 #define USB3_USB_IEN_RESERVED4_SHIFT             (30U)
105434 /*! RESERVED4 - Reserved field. Write ignored. 0 when read
105435  */
105436 #define USB3_USB_IEN_RESERVED4(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED4_SHIFT)) & USB3_USB_IEN_RESERVED4_MASK)
105437 /*! @} */
105438 
105439 /*! @name USB_ISTS - Interrupt Status */
105440 /*! @{ */
105441 #define USB3_USB_ISTS_CONI_MASK                  (0x1U)
105442 #define USB3_USB_ISTS_CONI_SHIFT                 (0U)
105443 /*! CONI - SS connection detected This interrupt informs that SuperSpeed link was conncted to the
105444  *    USB line This interrupt is reported on the irqs[0] pin
105445  */
105446 #define USB3_USB_ISTS_CONI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_CONI_SHIFT)) & USB3_USB_ISTS_CONI_MASK)
105447 #define USB3_USB_ISTS_DISI_MASK                  (0x2U)
105448 #define USB3_USB_ISTS_DISI_SHIFT                 (1U)
105449 /*! DISI - SS disconnection detected This interrupt informs that SuperSpeed link was disconncted
105450  *    from the USB line. This interrupt is reported on the irqs[0] pin
105451  */
105452 #define USB3_USB_ISTS_DISI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_DISI_SHIFT)) & USB3_USB_ISTS_DISI_MASK)
105453 #define USB3_USB_ISTS_UWRESI_MASK                (0x4U)
105454 #define USB3_USB_ISTS_UWRESI_SHIFT               (2U)
105455 /*! UWRESI - USB SS warm reset detected This interrupt is requested after the SuperSpeed warm reset
105456  *    ends or when USBSS-DEVs LTSSM exits Polling.LFPS state. After this reset, SW should
105457  *    reininitialize the controller. This interrupt is reported on the irqs[0] pin
105458  */
105459 #define USB3_USB_ISTS_UWRESI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UWRESI_SHIFT)) & USB3_USB_ISTS_UWRESI_MASK)
105460 #define USB3_USB_ISTS_UHRESI_MASK                (0x8U)
105461 #define USB3_USB_ISTS_UHRESI_SHIFT               (3U)
105462 /*! UHRESI - USB SS hot reset detected This interrupt is requested after the SuperSpeed hot reset
105463  *    ends. This interrupt is reported on the irqs[0] pin
105464  */
105465 #define USB3_USB_ISTS_UHRESI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UHRESI_SHIFT)) & USB3_USB_ISTS_UHRESI_MASK)
105466 #define USB3_USB_ISTS_U3ENTI_MASK                (0x10U)
105467 #define USB3_USB_ISTS_U3ENTI_SHIFT               (4U)
105468 /*! U3ENTI - SS link U3 state enter detected (suspend) This interrupt informs that SuperSpeed link
105469  *    enter U3 state. This interrupt is reported on the irqs[0] pin
105470  */
105471 #define USB3_USB_ISTS_U3ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U3ENTI_SHIFT)) & USB3_USB_ISTS_U3ENTI_MASK)
105472 #define USB3_USB_ISTS_U3EXTI_MASK                (0x20U)
105473 #define USB3_USB_ISTS_U3EXTI_SHIFT               (5U)
105474 /*! U3EXTI - SS link U3 state exit detected (wakeup) This interrupt informs that SuperSpeed link
105475  *    exit U3 state. This interrupt is reported on the irqs[1] pin
105476  */
105477 #define USB3_USB_ISTS_U3EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U3EXTI_SHIFT)) & USB3_USB_ISTS_U3EXTI_MASK)
105478 #define USB3_USB_ISTS_U2ENTI_MASK                (0x40U)
105479 #define USB3_USB_ISTS_U2ENTI_SHIFT               (6U)
105480 /*! U2ENTI - SS link U2 state enter detected This interrupt informs that SuperSpeed link enter U2
105481  *    state. This interrupt is reported on the irqs[0] pin
105482  */
105483 #define USB3_USB_ISTS_U2ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U2ENTI_SHIFT)) & USB3_USB_ISTS_U2ENTI_MASK)
105484 #define USB3_USB_ISTS_U2EXTI_MASK                (0x80U)
105485 #define USB3_USB_ISTS_U2EXTI_SHIFT               (7U)
105486 /*! U2EXTI - SS link U2 state exit detected This interrupt informs that SuperSpeed link exit U2
105487  *    state. This interrupt is reported on the irqs[0] pin
105488  */
105489 #define USB3_USB_ISTS_U2EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U2EXTI_SHIFT)) & USB3_USB_ISTS_U2EXTI_MASK)
105490 #define USB3_USB_ISTS_U1ENTI_MASK                (0x100U)
105491 #define USB3_USB_ISTS_U1ENTI_SHIFT               (8U)
105492 /*! U1ENTI - SS link U1 state enter detected This interrupt informs that SuperSpeed link enter U1
105493  *    state. This interrupt is reported on the irqs[0] pin
105494  */
105495 #define USB3_USB_ISTS_U1ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U1ENTI_SHIFT)) & USB3_USB_ISTS_U1ENTI_MASK)
105496 #define USB3_USB_ISTS_U1EXTI_MASK                (0x200U)
105497 #define USB3_USB_ISTS_U1EXTI_SHIFT               (9U)
105498 /*! U1EXTI - SS link U1 state exit detected This interrupt informs that SuperSpeed link exit U1
105499  *    state. This interrupt is reported on the irqs[0] pin
105500  */
105501 #define USB3_USB_ISTS_U1EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U1EXTI_SHIFT)) & USB3_USB_ISTS_U1EXTI_MASK)
105502 #define USB3_USB_ISTS_ITPI_MASK                  (0x400U)
105503 #define USB3_USB_ISTS_ITPI_SHIFT                 (10U)
105504 /*! ITPI - ITP/SOF packet detected In SuperSpeed mode this interrupt informs that ITP packet was
105505  *    received. In FS/HS mode this interrupt informs that SOF was detected. This interrupt is reported
105506  *    on the irqs[0] pin
105507  */
105508 #define USB3_USB_ISTS_ITPI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_ITPI_SHIFT)) & USB3_USB_ISTS_ITPI_MASK)
105509 #define USB3_USB_ISTS_WAKEI_MASK                 (0x800U)
105510 #define USB3_USB_ISTS_WAKEI_SHIFT                (11U)
105511 /*! WAKEI - This interrupt informs that at wakeup pin appeared active state. This interrupt is reported on the irqs[1] pin
105512  */
105513 #define USB3_USB_ISTS_WAKEI(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_WAKEI_SHIFT)) & USB3_USB_ISTS_WAKEI_MASK)
105514 #define USB3_USB_ISTS_SPKTI_MASK                 (0x1000U)
105515 #define USB3_USB_ISTS_SPKTI_SHIFT                (12U)
105516 /*! SPKTI - Send Custom Packet This interrupt informs that Custom Packet prepared in the USB_CPKT1-3
105517  *    registers and triggered with USB_CMD.SPKT bit was already sent. This interrupt is reported on
105518  *    the irqs[0] pin
105519  */
105520 #define USB3_USB_ISTS_SPKTI(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_SPKTI_SHIFT)) & USB3_USB_ISTS_SPKTI_MASK)
105521 #define USB3_USB_ISTS_RESERVED0_MASK             (0xE000U)
105522 #define USB3_USB_ISTS_RESERVED0_SHIFT            (13U)
105523 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
105524  */
105525 #define USB3_USB_ISTS_RESERVED0(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED0_SHIFT)) & USB3_USB_ISTS_RESERVED0_MASK)
105526 #define USB3_USB_ISTS_CON2I_MASK                 (0x10000U)
105527 #define USB3_USB_ISTS_CON2I_SHIFT                (16U)
105528 /*! CON2I - HS/FS mode connection detected This interrupt informs that HS/FS upstream port was
105529  *    conncted to the USB line This interrupt is reported on the irqs[0] pin
105530  */
105531 #define USB3_USB_ISTS_CON2I(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_CON2I_SHIFT)) & USB3_USB_ISTS_CON2I_MASK)
105532 #define USB3_USB_ISTS_DIS2I_MASK                 (0x20000U)
105533 #define USB3_USB_ISTS_DIS2I_SHIFT                (17U)
105534 /*! DIS2I - HS/FS mode disconnection detected This interrupt informs that HS/FS upstream port was
105535  *    disconncted from the USB line. This interrupt is reported on the irqs[0] pin
105536  */
105537 #define USB3_USB_ISTS_DIS2I(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_DIS2I_SHIFT)) & USB3_USB_ISTS_DIS2I_MASK)
105538 #define USB3_USB_ISTS_U2RESI_MASK                (0x40000U)
105539 #define USB3_USB_ISTS_U2RESI_SHIFT               (18U)
105540 /*! U2RESI - USB reset (HS/FS mode) detected This interrupt is requested after the USB reset in
105541  *    HS/FS mode ends. This interrupt is reported on the irqs[0] pin
105542  */
105543 #define USB3_USB_ISTS_U2RESI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U2RESI_SHIFT)) & USB3_USB_ISTS_U2RESI_MASK)
105544 #define USB3_USB_ISTS_RESERVED1_MASK             (0x80000U)
105545 #define USB3_USB_ISTS_RESERVED1_SHIFT            (19U)
105546 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
105547  */
105548 #define USB3_USB_ISTS_RESERVED1(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED1_SHIFT)) & USB3_USB_ISTS_RESERVED1_MASK)
105549 #define USB3_USB_ISTS_L2ENTI_MASK                (0x100000U)
105550 #define USB3_USB_ISTS_L2ENTI_SHIFT               (20U)
105551 /*! L2ENTI - LPM L2 state enter detected This interrupt informs that HS/FS LPM enter L2 state. This
105552  *    interrupt is reported on the irqs[0] pin
105553  */
105554 #define USB3_USB_ISTS_L2ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L2ENTI_SHIFT)) & USB3_USB_ISTS_L2ENTI_MASK)
105555 #define USB3_USB_ISTS_L2EXTI_MASK                (0x200000U)
105556 #define USB3_USB_ISTS_L2EXTI_SHIFT               (21U)
105557 /*! L2EXTI - LPM L2 state exit detected This interrupt informs that HS/FS LPM exit L2 state. This
105558  *    interrupt is reported on the irqs[1] pin
105559  */
105560 #define USB3_USB_ISTS_L2EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L2EXTI_SHIFT)) & USB3_USB_ISTS_L2EXTI_MASK)
105561 #define USB3_USB_ISTS_RESERVED2_MASK             (0xC00000U)
105562 #define USB3_USB_ISTS_RESERVED2_SHIFT            (22U)
105563 /*! RESERVED2 - Reserved field. Write ignored. 0 when read
105564  */
105565 #define USB3_USB_ISTS_RESERVED2(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED2_SHIFT)) & USB3_USB_ISTS_RESERVED2_MASK)
105566 #define USB3_USB_ISTS_L1ENTI_MASK                (0x1000000U)
105567 #define USB3_USB_ISTS_L1ENTI_SHIFT               (24U)
105568 /*! L1ENTI - LPM L1 state enter detected This interrupt informs that HS/FS LPM enter L1 state. This
105569  *    interrupt is reported on the irqs[0] pin
105570  */
105571 #define USB3_USB_ISTS_L1ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L1ENTI_SHIFT)) & USB3_USB_ISTS_L1ENTI_MASK)
105572 #define USB3_USB_ISTS_L1EXTI_MASK                (0x2000000U)
105573 #define USB3_USB_ISTS_L1EXTI_SHIFT               (25U)
105574 /*! L1EXTI - LPM L1 state exit detected This interrupt informs that HS/FS LPM exit L1 state. This
105575  *    interrupt is reported on the irqs[0] pin
105576  */
105577 #define USB3_USB_ISTS_L1EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L1EXTI_SHIFT)) & USB3_USB_ISTS_L1EXTI_MASK)
105578 #define USB3_USB_ISTS_CFGRESI_MASK               (0x4000000U)
105579 #define USB3_USB_ISTS_CFGRESI_SHIFT              (26U)
105580 /*! CFGRESI - USB configuration reset detected. This interrupt is requested after the device
105581  *    internally resets its endpoints onfiguration. This is done after each USB reset (UWRESI, UWRESI or
105582  *    U2RESI), after each connection event (CONI, CON2I) and after configuration reset initiated by
105583  *    software (USB_CONF.CFGRST). Generally this interrupt is generated in the same time as mentioned
105584  *    interrupts, however due to internal clock domain synchronisation this configuration reset can
105585  *    be performed a little later, so one can use this interrupt to perform some software
105586  *    operations. This interrupt informs that controller did the following operations: disabled all non
105587  *    control endpoints, cleared all pending endpoints transfers and interrupts. The configuration reset
105588  *    does not clear general device configuration (set in USB_CONF) and EP0 configuration settings.
105589  *    This interrupt is reported on the irqs[0] pin
105590  */
105591 #define USB3_USB_ISTS_CFGRESI(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_CFGRESI_SHIFT)) & USB3_USB_ISTS_CFGRESI_MASK)
105592 #define USB3_USB_ISTS_RESERVED3_MASK             (0x8000000U)
105593 #define USB3_USB_ISTS_RESERVED3_SHIFT            (27U)
105594 /*! RESERVED3 - Reserved field. Write ignored. 0 when read
105595  */
105596 #define USB3_USB_ISTS_RESERVED3(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED3_SHIFT)) & USB3_USB_ISTS_RESERVED3_MASK)
105597 #define USB3_USB_ISTS_UWRESSI_MASK               (0x10000000U)
105598 #define USB3_USB_ISTS_UWRESSI_SHIFT              (28U)
105599 /*! UWRESSI - Start of the USB warm reset detected. This interrupt is requested as soon as the
105600  *    SuperSpeed warm reset signalling is detected. This interrupt is reported on the irqs[0] pin
105601  */
105602 #define USB3_USB_ISTS_UWRESSI(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UWRESSI_SHIFT)) & USB3_USB_ISTS_UWRESSI_MASK)
105603 #define USB3_USB_ISTS_UWRESEI_MASK               (0x20000000U)
105604 #define USB3_USB_ISTS_UWRESEI_SHIFT              (29U)
105605 /*! UWRESEI - End of the USB warm reset detected. This interrupt is requested after the SuperSpeed
105606  *    warm reset ends. This interrupt is reported on the irqs[0] pin
105607  */
105608 #define USB3_USB_ISTS_UWRESEI(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UWRESEI_SHIFT)) & USB3_USB_ISTS_UWRESEI_MASK)
105609 #define USB3_USB_ISTS_RESERVED4_MASK             (0xC0000000U)
105610 #define USB3_USB_ISTS_RESERVED4_SHIFT            (30U)
105611 /*! RESERVED4 - Reserved field. Write ignored. 0 when read
105612  */
105613 #define USB3_USB_ISTS_RESERVED4(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED4_SHIFT)) & USB3_USB_ISTS_RESERVED4_MASK)
105614 /*! @} */
105615 
105616 /*! @name EP_SEL - Endpoint Select */
105617 /*! @{ */
105618 #define USB3_EP_SEL_EPNO_MASK                    (0xFU)
105619 #define USB3_EP_SEL_EPNO_SHIFT                   (0U)
105620 /*! EPNO - Selected Endpoint number
105621  */
105622 #define USB3_EP_SEL_EPNO(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_EPNO_SHIFT)) & USB3_EP_SEL_EPNO_MASK)
105623 #define USB3_EP_SEL_RESERVED0_MASK               (0x70U)
105624 #define USB3_EP_SEL_RESERVED0_SHIFT              (4U)
105625 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
105626  */
105627 #define USB3_EP_SEL_RESERVED0(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_RESERVED0_SHIFT)) & USB3_EP_SEL_RESERVED0_MASK)
105628 #define USB3_EP_SEL_DIR_MASK                     (0x80U)
105629 #define USB3_EP_SEL_DIR_SHIFT                    (7U)
105630 /*! DIR - Selected Endpoint direction. 0-OUT Endpoint selected, 1-IN Endpoint selected
105631  */
105632 #define USB3_EP_SEL_DIR(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_DIR_SHIFT)) & USB3_EP_SEL_DIR_MASK)
105633 #define USB3_EP_SEL_RESERVED1_MASK               (0xFFFFFF00U)
105634 #define USB3_EP_SEL_RESERVED1_SHIFT              (8U)
105635 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
105636  */
105637 #define USB3_EP_SEL_RESERVED1(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_RESERVED1_SHIFT)) & USB3_EP_SEL_RESERVED1_MASK)
105638 /*! @} */
105639 
105640 /*! @name EP_TRADDR - Endpoint Transfer Ring Address */
105641 /*! @{ */
105642 #define USB3_EP_TRADDR_TRADDR_MASK               (0xFFFFFFFFU)
105643 #define USB3_EP_TRADDR_TRADDR_SHIFT              (0U)
105644 /*! TRADDR - Transfer Ring address. Address of transfer ring for endpoint selected by endpoint
105645  *    select register. Based on this address, DMA will fetch transfer descriptors from system memory.
105646  *    This register can be used as dequeue pointer. CPU can use this register (read it or write to it)
105647  *    only when endpoint is configured and enabled (using EP_CFG register)
105648  */
105649 #define USB3_EP_TRADDR_TRADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_TRADDR_TRADDR_SHIFT)) & USB3_EP_TRADDR_TRADDR_MASK)
105650 /*! @} */
105651 
105652 /*! @name EP_CFG - Endpoint Configuration */
105653 /*! @{ */
105654 #define USB3_EP_CFG_ENABLE_MASK                  (0x1U)
105655 #define USB3_EP_CFG_ENABLE_SHIFT                 (0U)
105656 /*! ENABLE - Endpoint enable. If endpoint is disabled (the ENABLE bit is cleared), the endpoint will
105657  *    not: - request any interrupts - start any transmission over the DMA Even if Endpoint is
105658  *    disabled, software can set DRDY bit for it, but the DMA transmission will not begin until the
105659  *    endpoint is enabled. 0: disabled 1: enabled Reset value of this bit for EP0 is 1, for other EP's is
105660  *    0
105661  */
105662 #define USB3_EP_CFG_ENABLE(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_ENABLE_SHIFT)) & USB3_EP_CFG_ENABLE_MASK)
105663 #define USB3_EP_CFG_EPTYPE_MASK                  (0x6U)
105664 #define USB3_EP_CFG_EPTYPE_SHIFT                 (1U)
105665 /*! EPTYPE - Endpoint type. 0: control, 1: isochronous, 2: bulk, 3: interrupt. Endpoint type is
105666  *    programmable, however, certain types of transmissions require hardware support that must be
105667  *    incorporated prior to implementation. That can be done only for selected endpoints. Selective
105668  *    inclusion of hardware support is to reduce the size of the controller. Accordingly: - Endpoint-type
105669  *    iso should be set by the software only for those endpoints for which isochronous transmission
105670  *    hardware support is enabled. - A bulk endpoint can handle transmission with Bulk Streams
105671  *    support only for those endpoints for which Bulk Stream transmission hardware support is enabled.
105672  *    For detailed description how to implement hardware support for ISO transfers or Bulk Stream
105673  *    transfers see chapter 'Endpoints Implementation'
105674  */
105675 #define USB3_EP_CFG_EPTYPE(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_EPTYPE_SHIFT)) & USB3_EP_CFG_EPTYPE_MASK)
105676 #define USB3_EP_CFG_STREAM_EN_MASK               (0x8U)
105677 #define USB3_EP_CFG_STREAM_EN_SHIFT              (3U)
105678 /*! STREAM_EN - Stream support enable (only in SS mode). This bit must be set to enable a stream
105679  *    transfes on a bulk endpoint 0: Stream support OFF 1: Stream support ON
105680  */
105681 #define USB3_EP_CFG_STREAM_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_STREAM_EN_SHIFT)) & USB3_EP_CFG_STREAM_EN_MASK)
105682 #define USB3_EP_CFG_TDL_CHK_MASK                 (0x10U)
105683 #define USB3_EP_CFG_TDL_CHK_SHIFT                (4U)
105684 /*! TDL_CHK - TDL check(only in SS mode for BULK OUT EP). This field has to be set for stream
105685  *    capable SS bulk endpoints and it can be set for other bulk endpoint. The OUT bulk endpoints If the
105686  *    TDL_CHK bit is set if the device takes the packets to the OUT endpoint only when the value of
105687  *    the TDL (EP_CMD.TDL) for this endpoint is different from zero. Each received packet for the
105688  *    particular endpoint decrements the value of a TDL. If the TDL_CHK bit is not set, then each
105689  *    packet from the host to the OUT endpoint is taken as long as it free space in the on-chip device
105690  *    buffers. The IN bulk endpoints This bit is is used by USBSS_DEV to set EOB bit when TDL
105691  *    (programmed value) reach zero. 0: Do not check the TDL value when sending/receiving packets to the
105692  *    endpoints 1: Check the TDL value when sending/receiving packets to the endpoint
105693  */
105694 #define USB3_EP_CFG_TDL_CHK(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_TDL_CHK_SHIFT)) & USB3_EP_CFG_TDL_CHK_MASK)
105695 #define USB3_EP_CFG_SID_CHK_MASK                 (0x20U)
105696 #define USB3_EP_CFG_SID_CHK_SHIFT                (5U)
105697 /*! SID_CHK - SID check(only in SS mode for BULK OUT EP) This field can be set only for SS bulk OUT
105698  *    endpoints with stream support enabled 1) If SID_CHK bit is set, the device checks whether the
105699  *    incoming packets from the host to the particular OUT endpoint have the SID field set to the
105700  *    expected value. If the packet has an expected SID value is then taken and stored in the on-chip
105701  *    device buffers. If the packet has a different SID than expected, then the packet is rejected
105702  *    (NRDY) and the SIDERROR interrupt is reported to the software. The value of the SID to which
105703  *    incoming packets will be compared, are written to the device during sending ERDY TP (EP_CMD.ERDY
105704  *    and EP_CMD.ERDY_SID). The SID value from the incoming packet that has been rejected and
105705  *    caused the SIDERR interrupt can be read from the EP_STS_SID register. 2) If SID_CHK bit is not set,
105706  *    then each packet from the host is taken to the on-chip buffers is transmitted by the DMA
105707  *    regardless of the SID field in the TD. 0: SID chceck at device input OFF 1: SID chceck at device
105708  *    input ON
105709  */
105710 #define USB3_EP_CFG_SID_CHK(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_SID_CHK_SHIFT)) & USB3_EP_CFG_SID_CHK_MASK)
105711 #define USB3_EP_CFG_RESERVED0_MASK               (0x40U)
105712 #define USB3_EP_CFG_RESERVED0_SHIFT              (6U)
105713 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
105714  */
105715 #define USB3_EP_CFG_RESERVED0(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_RESERVED0_SHIFT)) & USB3_EP_CFG_RESERVED0_MASK)
105716 #define USB3_EP_CFG_EPENDIAN_MASK                (0x80U)
105717 #define USB3_EP_CFG_EPENDIAN_SHIFT               (7U)
105718 /*! EPENDIAN - DMA transfer endianness. When the conversion is ON, the byte order within DWORD is
105719  *    inverted. While the bit is set, the software confirms that the transfer length is a
105720  *    multiplication of 4 bytes. Enabling the conversion is possible only when SUPPORT_ENDIANESS_CONV is
105721  *    defined. By default this parameter is not defined, so endianess conversion is disabled. 0: Endianess
105722  *    conversion OFF 1: Endianess conversion ON
105723  */
105724 #define USB3_EP_CFG_EPENDIAN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_EPENDIAN_SHIFT)) & USB3_EP_CFG_EPENDIAN_MASK)
105725 #define USB3_EP_CFG_MAXBURST_MASK                (0xF00U)
105726 #define USB3_EP_CFG_MAXBURST_SHIFT               (8U)
105727 /*! MAXBURST - Maximum Burst size. The maximum number of packets the endpoint can send or receive as
105728  *    part of a burst. Valid values are from 0 to 15. A value of 0 indicates that the endpoint can
105729  *    only burst one packet at a time, and a value of 15 indicates that the endpoint can burst up to
105730  *    16 packets at a time. For endpoints of type control this is set to 0. This field is
105731  *    meaningfull only in SuperSpeed mode
105732  */
105733 #define USB3_EP_CFG_MAXBURST(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_MAXBURST_SHIFT)) & USB3_EP_CFG_MAXBURST_MASK)
105734 #define USB3_EP_CFG_RESERVED1_MASK               (0x3000U)
105735 #define USB3_EP_CFG_RESERVED1_SHIFT              (12U)
105736 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
105737  */
105738 #define USB3_EP_CFG_RESERVED1(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_RESERVED1_SHIFT)) & USB3_EP_CFG_RESERVED1_MASK)
105739 #define USB3_EP_CFG_MULT_MASK                    (0xC000U)
105740 #define USB3_EP_CFG_MULT_SHIFT                   (14U)
105741 /*! MULT - ISO max burst SuperSpeed mode: A zero-based value that indicates the maximum number of
105742  *    bursts within a service interval that this endpoint supports. This field is only valid for
105743  *    isochronous endpoints. A value of zero indicates that the device supports one Burst of bMaxBurst
105744  *    packets per service interval. The max value that can be set in this field in SuperSpeed is '2'.
105745  *    HS/FS mode: This field indicates how many packets will be transferred during micro frame. In
105746  *    Full-Speed mode only one ISO IN packet can be transferred per endpoint, per frame, thus this
105747  *    field has to be always '0'. In High-Speed mode, up to three ISO IN packets can be transferred
105748  *    per endpoint, per microframe, so the max value that can be set in this field in HighSpeed is '2'
105749  */
105750 #define USB3_EP_CFG_MULT(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_MULT_SHIFT)) & USB3_EP_CFG_MULT_MASK)
105751 #define USB3_EP_CFG_MAXPKTSIZE_MASK              (0x7FF0000U)
105752 #define USB3_EP_CFG_MAXPKTSIZE_SHIFT             (16U)
105753 /*! MAXPKTSIZE - Max packet size. The maximum packet size this endpoint is capable of sending or
105754  *    receiving. SuperSpeed mode: For control endpoints, this field is set to 512. For bulk endpoint
105755  *    types, this field is set to 1024. For interrupt and isochronous endpoints, this field is set to
105756  *    1024 if this endpoint defines a value in the bMaxBurst field greater than zero. If the value
105757  *    in the bMaxBurst field is set to zero, then this field can have any value from 0 to 1024 for an
105758  *    isochronous endpoint, and 1 to 1024 for an interrupt endpoint. High Speed/Full Speed mode:
105759  *    For control endpoints, this field is set to 64. For other endpoint types this field can have any
105760  *    value from 0 to 1024
105761  */
105762 #define USB3_EP_CFG_MAXPKTSIZE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_MAXPKTSIZE_SHIFT)) & USB3_EP_CFG_MAXPKTSIZE_MASK)
105763 #define USB3_EP_CFG_BUFFERING_MASK               (0xF8000000U)
105764 #define USB3_EP_CFG_BUFFERING_SHIFT              (27U)
105765 /*! BUFFERING - Max number of buffered packets. The maximum number of packets the device can buffer
105766  *    in the on-chip memory for a specified endpoint. Valid values are from 0 to 15. Value 0 means
105767  *    that 1 on-chip buffer is available for the appropriate endpoint. Value 15 means that 16 on-chip
105768  *    buffers are available for the appropriate endpoint. Each IN endpoint has individual buffers
105769  *    associated with it. OUT endpoints have common buffers, so buffering for OUT endpoints is
105770  *    determined by the maximum buffering value along all enabled OUT endpoints. The number of possible
105771  *    endpoint buffers depends on the on-chip memory size and the size of endpoint buffers
105772  */
105773 #define USB3_EP_CFG_BUFFERING(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_BUFFERING_SHIFT)) & USB3_EP_CFG_BUFFERING_MASK)
105774 /*! @} */
105775 
105776 /*! @name EP_CMD - Endpoint Command */
105777 /*! @{ */
105778 #define USB3_EP_CMD_EPRST_MASK                   (0x1U)
105779 #define USB3_EP_CMD_EPRST_SHIFT                  (0U)
105780 /*! EPRST - Endpoint reset. 0: no effect 1: resets endpoint This command performs the following
105781  *    actions for particular endpoint: - clears DRDY bit and stops DMA transfer - clears on-chip buffers
105782  *    - clears sequence number in SS mode or Data Toggle in HS/FS mode This command does not clear
105783  *    Endpoint interrupt if already requested (irq[0] pin was asserted) thus it is recommended first
105784  *    to clear all interrupts from endpoint scheduled to reset. When EPRST operation is started
105785  *    ('1' is written), CPU must wait until this bit becomes again '0' (it indicates that HW finishes
105786  *    all internal opertations related to DFLUSH), and only then can proceed with next software
105787  *    operations. Additionally, when DMA already started processing TD for this EP, the EPRST command
105788  *    cause that DMA engine will once more access the descriptor in external memory. After endpoint
105789  *    reset the software is responsible for it to re-set the Endpoint TRADDR. Writing '0 'has no effect
105790  */
105791 #define USB3_EP_CMD_EPRST(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_EPRST_SHIFT)) & USB3_EP_CMD_EPRST_MASK)
105792 #define USB3_EP_CMD_SSTALL_MASK                  (0x2U)
105793 #define USB3_EP_CMD_SSTALL_SHIFT                 (1U)
105794 /*! SSTALL - Endpoint STALL set. Writing '1' to this bit cause the endpoint is halted. 0: no effect 1: STALLs endpoint
105795  */
105796 #define USB3_EP_CMD_SSTALL(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_SSTALL_SHIFT)) & USB3_EP_CMD_SSTALL_MASK)
105797 #define USB3_EP_CMD_CSTALL_MASK                  (0x4U)
105798 #define USB3_EP_CMD_CSTALL_SHIFT                 (2U)
105799 /*! CSTALL - Endpoint STALL clear. Writing '1' to this bit cause the endpoint becames not halted. 0:
105800  *    no effect 1: clears endpoint STALL
105801  */
105802 #define USB3_EP_CMD_CSTALL(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_CSTALL_SHIFT)) & USB3_EP_CMD_CSTALL_MASK)
105803 #define USB3_EP_CMD_ERDY_MASK                    (0x8U)
105804 #define USB3_EP_CMD_ERDY_SHIFT                   (3U)
105805 /*! ERDY - Send ERDY TP. Writing '1' to this bit forces the device to send ERDY TP with stream ID
105806  *    equal to ERDY_SID. This bit is necessary to support SS bulk stream transfers. This bit is also
105807  *    used during control transfers (in both modes: HS/FS and SS): writing '1' instruct device
105808  *    controller HW that it can exit from Setup Stage to the Data Stage (or directly to the Status Stage
105809  *    if USB Request is without Data Stage). However the ERDY packet is only actually sent in SS
105810  *    mode. Writing '0' has no effect
105811  */
105812 #define USB3_EP_CMD_ERDY(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_ERDY_SHIFT)) & USB3_EP_CMD_ERDY_MASK)
105813 #define USB3_EP_CMD_RESERVED_MASK                (0x10U)
105814 #define USB3_EP_CMD_RESERVED_SHIFT               (4U)
105815 /*! RESERVED - Reserved field. Write ignored. 0 when read
105816  */
105817 #define USB3_EP_CMD_RESERVED(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_RESERVED_SHIFT)) & USB3_EP_CMD_RESERVED_MASK)
105818 #define USB3_EP_CMD_REQ_CMPL_MASK                (0x20U)
105819 #define USB3_EP_CMD_REQ_CMPL_SHIFT               (5U)
105820 /*! REQ_CMPL - Request complete. 0 : no effect 1 : informs device that Request service is complete
105821  *    Bit valid only for endpoint 0. Writing '1' to this bit informs USBSS-DEV that software finished
105822  *    USB request service and device can send ACK answer for the Status Stage within USB request.
105823  *    This bit is automatically cleared by USBSS-DEV after device answers to the status stage with
105824  *    ACK or STALL. Until software do not set this bit, during proceeding current host request, the
105825  *    device will answer to the status stage with NRDY answer
105826  */
105827 #define USB3_EP_CMD_REQ_CMPL(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_REQ_CMPL_SHIFT)) & USB3_EP_CMD_REQ_CMPL_MASK)
105828 #define USB3_EP_CMD_DRDY_MASK                    (0x40U)
105829 #define USB3_EP_CMD_DRDY_SHIFT                   (6U)
105830 /*! DRDY - Transfer descriptor ready. Transfer Descriptor Ready for selected endpoint (0 - no
105831  *    effect, 1 - starts transfer). Writing '1' to this bit informs USBSS-DEV that in-system memory has
105832  *    prepared a new Transfer Descriptor for selected endpoints. If an IN endpoint is 'Not Ready'
105833  *    (NRDY=1 in Endpoint Status Register), then setting the DRDY bit (which is proceeded by DMA
105834  *    transfer to the on-chip buffers) will cause the device to send the ERDY packet. If the TRB error
105835  *    occurs, the DRDY bit is cleared and held in the low state until the TRBERR is not cleared (even if
105836  *    the DTRANS bit is set, the Multiple TRB chain mode is enabled). This bit is duplicated in the
105837  *    Doorbell register. Writing '1' to this bit while DESCMIS interrupt flag is set for the same
105838  *    endpoint will also clear the DESCMIS flag
105839  */
105840 #define USB3_EP_CMD_DRDY(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_DRDY_SHIFT)) & USB3_EP_CMD_DRDY_MASK)
105841 #define USB3_EP_CMD_DFLUSH_MASK                  (0x80U)
105842 #define USB3_EP_CMD_DFLUSH_SHIFT                 (7U)
105843 /*! DFLUSH - Data flush. Writing '1' to this bit performs the following actions for particular
105844  *    endpoint: - clears DRDY bit and stops DMA transfer - flush endpoint data from on chip buffers As in
105845  *    case of Endpoint reset (EPRST bit), after endpoint data flush the software is responsible for
105846  *    it to re-set the Endpoint TRADDR. When DFLUSH operation is started ('1' is written), CPU must
105847  *    wait until this bit becomes again '0' (it indicates that HW finishes all internal opertations
105848  *    related to DFLUSH), and only then can proceed with next software operations. Writing '0' has
105849  *    no effect
105850  */
105851 #define USB3_EP_CMD_DFLUSH(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_DFLUSH_SHIFT)) & USB3_EP_CMD_DFLUSH_MASK)
105852 #define USB3_EP_CMD_STDL_MASK                    (0x100U)
105853 #define USB3_EP_CMD_STDL_SHIFT                   (8U)
105854 /*! STDL - Transfer Descriptor Length write (used only for Bulk Stream capable endpoints in SS
105855  *    mode). Writing '1' to this bit writes to the device the TDL field. The bit is automatically cleared.
105856  */
105857 #define USB3_EP_CMD_STDL(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_STDL_SHIFT)) & USB3_EP_CMD_STDL_MASK)
105858 #define USB3_EP_CMD_TDL_MASK                     (0xFE00U)
105859 #define USB3_EP_CMD_TDL_SHIFT                    (9U)
105860 /*! TDL - Transfer Descriptor Length (used only in SS mode for bulk endpoints). Using the field TDL
105861  *    for bulk EP assumes TDL_CHK bit enabled. This field will be writen to the device when the
105862  *    EP_CMD.STDL bit is set to '1'. This field is used by the device when particular endpoint: - is
105863  *    configured as Stream capable (EP_CFG.STREAM_EN bit is set) or - the IOT interrupt is to be used
105864  *    This field should be written each time, when bit EP_CMD.DRDY is written (i.e. device is
105865  *    notified that new TD is ready). The written value should correspond to the prepared data size
105866  *    (multiple of endpoint MAXPKTSIZE eg. in KB for BULK EP) in the transfer descriptor (which has been
105867  *    prepared for this endpoint before DRDY bit is set) rounded up (if short packet expected). This
105868  *    field has to be written no later than DRDY (or Dorbel) bit. 1) For OUT endpoints device will
105869  *    decrement this field by one after each successful packet received from the host. 2) For IN
105870  *    endpoints device will decrement this field by one after each successful handshake packet received
105871  *    from the host. As long as this field is not decremented to zero, then for each response NRDY
105872  *    that device send to the host (e.g. due to temporary lack of space (OUT EP) / packets (IN EP) in
105873  *    the on-chip buffers), device will automatically send the ERDY package to the host as soon as
105874  *    free spece (OUT EP) / new packet (IN EP) will be available in the on-chip buffers. When the
105875  *    field TDL is decremented to zero then, it will mean that the device does not expect to have more
105876  *    packets from the host (OUT EP) / does not want to send more packets (IN EP). Then device
105877  *    generates IOT interrupt and from this moment ERDY TP will not be sent automatically if endpoint
105878  *    enters flow control. Additionally, if TDL_CHK is set (only for BULK EP), and TDL value is equal
105879  *    to zero, device will: - for OUT EP - not accept any data packet from host for particular EP,
105880  *    even if there are empty OUT buffers. In this case device answer with NRDY TP and NRDY interrupt
105881  *    will be requested. - for IN EP - send last programmed (according to the TDL field) with EOB
105882  *    bit set. Writing into this field any value at the time when the previous value of this field was
105883  *    not zero, will result in adding these two values
105884  */
105885 #define USB3_EP_CMD_TDL(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_TDL_SHIFT)) & USB3_EP_CMD_TDL_MASK)
105886 #define USB3_EP_CMD_ERDY_SID_MASK                (0xFFFF0000U)
105887 #define USB3_EP_CMD_ERDY_SID_SHIFT               (16U)
105888 /*! ERDY_SID - ERDY Stream ID value (used in SS mode). This field contains SID - it will be sent to
105889  *    host in ERDY packet (by writing '1' to ERDY). This field is meaningfull only in SuperSpeed mode
105890  */
105891 #define USB3_EP_CMD_ERDY_SID(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_ERDY_SID_SHIFT)) & USB3_EP_CMD_ERDY_SID_MASK)
105892 /*! @} */
105893 
105894 /*! @name EP_STS - Endpoint Status */
105895 /*! @{ */
105896 #define USB3_EP_STS_SETUP_MASK                   (0x1U)
105897 #define USB3_EP_STS_SETUP_SHIFT                  (0U)
105898 /*! SETUP - Setup transfer complete. Bit used only for EP0. If setup type transmission has been
105899  *    completed and data from host has been received and copied to system memory, this bit is set to '1'
105900  *    and interrupt is generated. Setup packet is applicable only to control transmissions (EP0).
105901  *    This interrupt can be masked by the corresponding bit in EP_STS_EN register. Writing '1' to
105902  *    this bit clears the interrupt
105903  */
105904 #define USB3_EP_STS_SETUP(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SETUP_SHIFT)) & USB3_EP_STS_SETUP_MASK)
105905 #define USB3_EP_STS_STALL_MASK                   (0x2U)
105906 #define USB3_EP_STS_STALL_SHIFT                  (1U)
105907 /*! STALL - Endpoint STALL status 0 - endpoint is not stalled 1 - endpoint is stalled This bit is
105908  *    not treated as an interrupt (not reported in the EP__ISTS register). This bit is read-only
105909  */
105910 #define USB3_EP_STS_STALL(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_STALL_SHIFT)) & USB3_EP_STS_STALL_MASK)
105911 #define USB3_EP_STS_IOC_MASK                     (0x4U)
105912 #define USB3_EP_STS_IOC_SHIFT                    (2U)
105913 /*! IOC - Interrupt On Complete When DMA transfer is completed and transfer descriptor is updated,
105914  *    then this bit is set to 1 and interrupt is generated. Enabling or disabling of this interrupt
105915  *    is realized by IOC bit in transfer descriptor. Additionally, this interrupt can be masked for a
105916  *    particular endpoint in EP__ISTS register. When in given transfer descriptor both interrupts
105917  *    (IOC and ISP interrupts) are enabled, then in the case of short packet, only one interrupt is
105918  *    generated - SP. Writing '1' to this bit clears the interrupt
105919  */
105920 #define USB3_EP_STS_IOC(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_IOC_SHIFT)) & USB3_EP_STS_IOC_MASK)
105921 #define USB3_EP_STS_ISP_MASK                     (0x8U)
105922 #define USB3_EP_STS_ISP_SHIFT                    (3U)
105923 /*! ISP - Interrupt on Short Packet. This bit is set to 1 and interrupt is generated when a transfer
105924  *    containing less data than MaxPacket for a given endpoint has been completed and transfer
105925  *    descriptor has been updated.Enabling or disabling of interrupt is realized by ISP bit in transfer
105926  *    descriptor. Additionally, this interrupt can be masked for a particular endpoint in EP__ISTS
105927  *    register. When in given transfer descriptor both interrupts are enabled (IOC and ISP), then in
105928  *    the case of short packet only one interrupt is generated - SP. Writing '1' to this bit clears
105929  *    the interrupt
105930  */
105931 #define USB3_EP_STS_ISP(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_ISP_SHIFT)) & USB3_EP_STS_ISP_MASK)
105932 #define USB3_EP_STS_DESCMIS_MASK                 (0x10U)
105933 #define USB3_EP_STS_DESCMIS_SHIFT                (4U)
105934 /*! DESCMIS - Transfer descriptor missing. This bit is set to 1 and interrupt is generated when any
105935  *    of the following conditions are met: - device is requested to send data to host and none of
105936  *    Transfer Descriptor is prepared (IN transfer) - device receives OUT packet and cannot transmit
105937  *    it using DMA as Transfer Descriptor has not been prepared (DRDY was not set) for it (OUT
105938  *    transfer) Note1: This interrupt is not generated for ISO IN endpoints. For such endpoints the ISOERR
105939  *    interrupt should be used. Note2: DMA will not start operating on transfer descriptor array
105940  *    until the OUT packet is received (or host requests IN packet) and processor has not previously
105941  *    notified DMA (by writing to EP_CMD register of DRDY register). Note2: For BULK OUT endpoints
105942  *    with TDL_CHK bit set this interrupt will not by requested as device will not accept any packet
105943  *    from host when TRB is not prepared (and TDL is not written with non-zero value). In this case
105944  *    the NRDY interrupt should be used instead of DESMIS. Writing '1' to this bit or writing '1' to
105945  *    EP_CMD.DRDY bit of endpoints which generated interrupt will delete the interrupt. This
105946  *    interrupt can be masked by the corresponding bit in EP_STS_EN register. Writing '1' to this bit
105947  *    clears the interrupt
105948  */
105949 #define USB3_EP_STS_DESCMIS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_DESCMIS_SHIFT)) & USB3_EP_STS_DESCMIS_MASK)
105950 #define USB3_EP_STS_STREAMR_MASK                 (0x20U)
105951 #define USB3_EP_STS_STREAMR_SHIFT                (5U)
105952 /*! STREAMR - Stream Rejected (used only in SS mode). This bit is set to '1' if device tries to
105953  *    initiate stream number and host does not accept it. Stream support is class-dependent. This
105954  *    interrupt can be masked by the corresponding bit in STREAMREN register. Writing '1' to this bit
105955  *    clears the interrupt
105956  */
105957 #define USB3_EP_STS_STREAMR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_STREAMR_SHIFT)) & USB3_EP_STS_STREAMR_MASK)
105958 #define USB3_EP_STS_MD_EXIT_MASK                 (0x40U)
105959 #define USB3_EP_STS_MD_EXIT_SHIFT                (6U)
105960 /*! MD_EXIT - EXIT from MOVE DATA State (used only for stream transfers in SS mode) This bit is set
105961  *    to '1' if stream capable endpoint exits from MOVE DATA state of Bulk IN/OUT Stream Ptrotocol
105962  *    State Machine (ISPSM/OSPSM). Stream support is class-dependent. This interrupt can be masked by
105963  *    the corresponding bit in MD_EXITEN register. Writing '1' to this bit clears the interrupt
105964  */
105965 #define USB3_EP_STS_MD_EXIT(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_MD_EXIT_SHIFT)) & USB3_EP_STS_MD_EXIT_MASK)
105966 #define USB3_EP_STS_TRBERR_MASK                  (0x80U)
105967 #define USB3_EP_STS_TRBERR_SHIFT                 (7U)
105968 /*! TRBERR - TRB error. This bit is set if DMA read corrupted TRB (wrong C bit value or TRB type).
105969  *    Address of the TRB is stored in the EP_TRADDR register. This interrupt can be masked by the
105970  *    corresponding bit in EP_STS_EN register. If this error occurs, the bit DRDY is cleared and held
105971  *    in the low state until the TRBERR is not cleared. To start the DMA again, the software has to
105972  *    clear this interrupt and set the DRDY bit once more. Writing '1' to this bit clears the
105973  *    interrupt
105974  */
105975 #define USB3_EP_STS_TRBERR(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_TRBERR_SHIFT)) & USB3_EP_STS_TRBERR_MASK)
105976 #define USB3_EP_STS_NRDY_MASK                    (0x100U)
105977 #define USB3_EP_STS_NRDY_SHIFT                   (8U)
105978 /*! NRDY - Not ready (used only in SS mode). This bit is automatically set to 1 when for some reason
105979  *    endpoint enters Flow Control. If ERDY is sent automatically by the endpoint (what is done
105980  *    when current TDL value is greater then zero), this interrupt bit is not automatically cleared
105981  *    (although the endpoint itself leaves FlowControl). Note: For BULK OUT endpoints with TDL_CHK bit
105982  *    seting this interrupt should be used instead of DESCMIS interrupt. See also DESCMIS
105983  *    description. Writing '1' to this bit clears the interrupt
105984  */
105985 #define USB3_EP_STS_NRDY(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_NRDY_SHIFT)) & USB3_EP_STS_NRDY_MASK)
105986 #define USB3_EP_STS_DBUSY_MASK                   (0x200U)
105987 #define USB3_EP_STS_DBUSY_SHIFT                  (9U)
105988 /*! DBUSY - DMA busy. This bit is set to '1' while the DMA services the endpoint. Through the
105989  *    service means either actual transmission of data between on-chip cache and system memory for
105990  *    particular endpoint or a pending data transmission which has already begun but was interrupted by
105991  *    endpoint with a higher priority. Such pending transmissions will begin automatically themselves
105992  *    after these higher priority. This bit is only a status bit (not an interrupt flag)
105993  */
105994 #define USB3_EP_STS_DBUSY(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_DBUSY_SHIFT)) & USB3_EP_STS_DBUSY_MASK)
105995 #define USB3_EP_STS_BUFFEMPTY_MASK               (0x400U)
105996 #define USB3_EP_STS_BUFFEMPTY_SHIFT              (10U)
105997 /*! BUFFEMPTY - Endpoint Buffer Empty. When this bit is set to '1', there are no packets for the
105998  *    particular endpoint in the on-chip buffers. This bit is only a status bit (not an interrupt flag)
105999  */
106000 #define USB3_EP_STS_BUFFEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_BUFFEMPTY_SHIFT)) & USB3_EP_STS_BUFFEMPTY_MASK)
106001 #define USB3_EP_STS_CCS_MASK                     (0x800U)
106002 #define USB3_EP_STS_CCS_SHIFT                    (11U)
106003 /*! CCS - Current Cycle Status. Informs about current value of C bit corresponding to DMA ownership
106004  *    of TRBs for selected endpoint. For more information about TRBs C bit see chapter 2.11.3. This
106005  *    bit is only a status bit (not an interrupt flag)
106006  */
106007 #define USB3_EP_STS_CCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_CCS_SHIFT)) & USB3_EP_STS_CCS_MASK)
106008 #define USB3_EP_STS_PRIME_MASK                   (0x1000U)
106009 #define USB3_EP_STS_PRIME_SHIFT                  (12U)
106010 /*! PRIME - Prime (used only in SS mode). This bit is set when the device receives the packet with
106011  *    PRIME ID. This interrupt can be masked by the corresponding bit in EP_STS_EN register. Writing
106012  *    '1' to this bit clears the interrupt
106013  */
106014 #define USB3_EP_STS_PRIME(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_PRIME_SHIFT)) & USB3_EP_STS_PRIME_MASK)
106015 #define USB3_EP_STS_SIDERR_MASK                  (0x2000U)
106016 #define USB3_EP_STS_SIDERR_SHIFT                 (13U)
106017 /*! SIDERR - Stream error (used only in SS mode) If host requested IN (sent OUT) packet with
106018  *    particular Stream ID, and device is actually programmed to transfer packets with different Stream ID
106019  *    (SID written in the EP_CMD.ERDY_SID field) the host IN request (OUT packet) is rejected (NRDY)
106020  *    and the SIDERR interrupt is requested. In case of IN direction, the SIDERR interrupt will not
106021  *    be requested when device is not prepared for any transfer (EP_CMD.TDL= 0 for this endpoint).
106022  *    In this case (and additionally when EP_CMD.DRDY= 0 and EP_STS.DBUSY=0), the DESCMIS interrupt
106023  *    will be requested. This interrupt can be masked by the corresponding bit in EP_STS_EN
106024  *    register. Writing '1' to this bit clears the interrupt
106025  */
106026 #define USB3_EP_STS_SIDERR(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SIDERR_SHIFT)) & USB3_EP_STS_SIDERR_MASK)
106027 #define USB3_EP_STS_OUTSMM_MASK                  (0x4000U)
106028 #define USB3_EP_STS_OUTSMM_SHIFT                 (14U)
106029 /*! OUTSMM - OUT size mismatch. This bit is set when host sends a different data size than device
106030  *    was anticipating (according to Data Length field in TRB). In such a case, the DMA updates length
106031  *    field in current TRB, updates TRADDR (next TRB address), and triggers the interrupt. DMA will
106032  *    not start processing TRB ring of this EP until its DRDY is set. This interrupt can be masked
106033  *    by the corresponding bit in EP_STS_EN register. Writing '1' to this bit clears the interrupt
106034  */
106035 #define USB3_EP_STS_OUTSMM(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_OUTSMM_SHIFT)) & USB3_EP_STS_OUTSMM_MASK)
106036 #define USB3_EP_STS_ISOERR_MASK                  (0x8000U)
106037 #define USB3_EP_STS_ISOERR_SHIFT                 (15U)
106038 /*! ISOERR - ISO transmission error. Error of isochronous transmission. This bit is set during data
106039  *    transmission to/from ISO endpoints while the last data transfer at PIPE IF is in current micro
106040  *    frame. For ISO IN endpoints: If host asks for data packet and device is not ready for sent
106041  *    data immediatelly, then ISOERR flag is set for particular endpoint and core sends a 0-length
106042  *    DATA packet to the host. The next data portion transfer (for the next micro frame) from system
106043  *    memory to on-chip buffers is automatically started (when EP_CMD.DRDY bit is set or DMA works in
106044  *    DMULT mode). For ISO OUT endpoints: When host issues an OUT data packet for the specific
106045  *    endpoint but the OUT buffers are full, then device is unable to receive data packet and the ISOERR
106046  *    flag is set. For more information about ISO trasfer see chapter 'Isochronous Transfers'. This
106047  *    interrupt can be masked by the corresponding bit in EP_STS_EN register. Writing '1' to this
106048  *    bit clears the interrupt
106049  */
106050 #define USB3_EP_STS_ISOERR(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_ISOERR_SHIFT)) & USB3_EP_STS_ISOERR_MASK)
106051 #define USB3_EP_STS_HOSTPP_MASK                  (0x10000U)
106052 #define USB3_EP_STS_HOSTPP_SHIFT                 (16U)
106053 /*! HOSTPP - Host Packet Pending (only for SS mode). Depending on whether the endpoint is enabled
106054  *    for streams or not, this bit behaves as follows: 1)For stream enabled bulk endpoints
106055  *    (EP_CFG.EPSTREAM_EN bit set): This bit reflects the PP bit in the last packet received from the host
106056  *    during Move Data state of the DOSPSM for the OUT endpoint. This bit is updated on exit from the
106057  *    MOVE DATA state of the DOSPSM and can be analyzed during servicing MD_EXIT interrupt for BULK
106058  *    OUT endpoint with Stream support enabled. If this bit is set to '0' during MD_EXIT interrupt, it
106059  *    means that the host terminated current stream. If this bit is set to '1' during MD_EXIT
106060  *    interrupt, it means that the host doesn't terminated current stream and still has data for this
106061  *    stream. 2)Non stream bulk endpoints (EP_CFG.EPSTREAM_EN bit not set): This bit reflects the PP
106062  *    bit in the packets received from the host. This bit is updated as long as the EP_CMD.TDL is
106063  *    nonzero and it can be analyzed during servicing IOT interrupt for BULK endpoints. This bit is only
106064  *    a status bit (not an interrupt flag)
106065  */
106066 #define USB3_EP_STS_HOSTPP(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_HOSTPP_SHIFT)) & USB3_EP_STS_HOSTPP_MASK)
106067 #define USB3_EP_STS_SPSMST_MASK                  (0x60000U)
106068 #define USB3_EP_STS_SPSMST_SHIFT                 (17U)
106069 /*! SPSMST - Stream Protocol State Machine State (only for Bulk stream endpoints) This field is
106070  *    valid only for stream capable bulk endpoints and reflects the current state of the Stream Protocol
106071  *    State Machine for selected endpoint: 0 - DISABLED 1 - IDLE 2 - START_STREAM 3 - MOVE_DATA
106072  *    Soft should check if the SPSM is in IDLE state before sending ERDY TP from stream EP (leading to
106073  *    the transition from IDE to START_STREAM) Before software will order to send an ERDY TP from
106074  *    stream capable endpoint (leading to the transition from IDLE to START_STREAM) it should first
106075  *    check if the SPSM is in IDLE state. This bit is only a status bit (not an interrupt flag)
106076  */
106077 #define USB3_EP_STS_SPSMST(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SPSMST_SHIFT)) & USB3_EP_STS_SPSMST_MASK)
106078 #define USB3_EP_STS_IOT_MASK                     (0x80000U)
106079 #define USB3_EP_STS_IOT_SHIFT                    (19U)
106080 /*! IOT - Interrupt On Transfer complete. This interrupt is generated when the field EP_CMD.TDL is
106081  *    decremented to zero. It means that the device - does not expect to have more packets from the
106082  *    host (OUT EP) - does not want to send more packets (IN EP) More information can be found in the
106083  *    description of EP_CMD.TDL field. Writing '1' to this bit clears the interrupt
106084  */
106085 #define USB3_EP_STS_IOT(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_IOT_SHIFT)) & USB3_EP_STS_IOT_MASK)
106086 #define USB3_EP_STS_RESERVED0_MASK               (0xF00000U)
106087 #define USB3_EP_STS_RESERVED0_SHIFT              (20U)
106088 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
106089  */
106090 #define USB3_EP_STS_RESERVED0(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_RESERVED0_SHIFT)) & USB3_EP_STS_RESERVED0_MASK)
106091 #define USB3_EP_STS_OUTQ_NO_MASK                 (0xF000000U)
106092 #define USB3_EP_STS_OUTQ_NO_SHIFT                (24U)
106093 /*! OUTQ_NO - OUT queue endpoint number. This field shows the number of the endpoint to which the
106094  *    packet, received by the host, currently is waiting to be transmitted by the DMA from the on-chip
106095  *    buffers to the system memory. As there is one buffers queue for all Out Endpoints, this field
106096  *    is not endpoint related, and thus it can be read regardless of current value stored in the
106097  *    EP_SEL register. This bit is only a status bit (not an interrupt flag)
106098  */
106099 #define USB3_EP_STS_OUTQ_NO(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_OUTQ_NO_SHIFT)) & USB3_EP_STS_OUTQ_NO_MASK)
106100 #define USB3_EP_STS_OUTQ_VAL_MASK                (0x10000000U)
106101 #define USB3_EP_STS_OUTQ_VAL_SHIFT               (28U)
106102 /*! OUTQ_VAL - OUT queue valid flag. This field indicates whether the endpoint number of the OUT
106103  *    packet waiting for transmission by the DMA, is valid or not. In other words, whether the packet
106104  *    queue is not empty. As there is one buffers queue for all Out Endpoints, this field is not
106105  *    endpoint related, and thus it can be read regardless of current value stored in the EP_SEL
106106  *    register. 0 - queue of out packets is empty thus OUTQ_NO is not valid 1 - queue of out packets is not
106107  *    empty thus OUTQ_NO is valid This bit is only a status bit (not an interrupt flag)
106108  */
106109 #define USB3_EP_STS_OUTQ_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_OUTQ_VAL_SHIFT)) & USB3_EP_STS_OUTQ_VAL_MASK)
106110 #define USB3_EP_STS_RESERVED1_MASK               (0x60000000U)
106111 #define USB3_EP_STS_RESERVED1_SHIFT              (29U)
106112 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
106113  */
106114 #define USB3_EP_STS_RESERVED1(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_RESERVED1_SHIFT)) & USB3_EP_STS_RESERVED1_MASK)
106115 #define USB3_EP_STS_STPWAIT_MASK                 (0x80000000U)
106116 #define USB3_EP_STS_STPWAIT_SHIFT                (31U)
106117 /*! STPWAIT - Bit used only for EP0. If setup packet is received correctly and stored in the on-chip
106118  *    buffer, this bit is set to 1 and interrupt is generated. Setup packet is applicable only to
106119  *    control transmissions (EP0). This interrupt can be masked by the corresponding bit in EP_STS_EN
106120  *    register. Writing '1' to this bit clears the interrupt
106121  */
106122 #define USB3_EP_STS_STPWAIT(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_STPWAIT_SHIFT)) & USB3_EP_STS_STPWAIT_MASK)
106123 /*! @} */
106124 
106125 /*! @name EP_STS_SID - Endpoint Status */
106126 /*! @{ */
106127 #define USB3_EP_STS_SID_SID_MASK                 (0xFFFFU)
106128 #define USB3_EP_STS_SID_SID_SHIFT                (0U)
106129 /*! SID - Stream ID (used only in SS mode). Stream ID of packet, which generates interrupt. The
106130  *    interrupts that update the SID field are: - SIDERR for EP OUT - SIDERR/DESCMIS for EP IN For the
106131  *    above interrupts, the values of the SID field reflects: - in case of SIDERR for EP OUT this
106132  *    field reflects the Stream ID of OUT packet sent by host which was rejected by the device, due to
106133  *    SID_CHK bit set - in case of SIDERR/DESCMIS for EP IN this field reflects the Stream ID of ACK
106134  *    TP sent by host which was rejected by the device
106135  */
106136 #define USB3_EP_STS_SID_SID(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SID_SID_SHIFT)) & USB3_EP_STS_SID_SID_MASK)
106137 #define USB3_EP_STS_SID_RESERVED_MASK            (0xFFFF0000U)
106138 #define USB3_EP_STS_SID_RESERVED_SHIFT           (16U)
106139 /*! RESERVED - Reserved field. Write ignored. 0 when read
106140  */
106141 #define USB3_EP_STS_SID_RESERVED(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SID_RESERVED_SHIFT)) & USB3_EP_STS_SID_RESERVED_MASK)
106142 /*! @} */
106143 
106144 /*! @name EP_STS_EN - Endpoint Status Register Enable */
106145 /*! @{ */
106146 #define USB3_EP_STS_EN_SETUPEN_MASK              (0x1U)
106147 #define USB3_EP_STS_EN_SETUPEN_SHIFT             (0U)
106148 /*! SETUPEN - Setup transfer complete. This bit enables the SETUP interrupt. Valid only for EP0
106149  */
106150 #define USB3_EP_STS_EN_SETUPEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_SETUPEN_SHIFT)) & USB3_EP_STS_EN_SETUPEN_MASK)
106151 #define USB3_EP_STS_EN_RESERVED0_MASK            (0xEU)
106152 #define USB3_EP_STS_EN_RESERVED0_SHIFT           (1U)
106153 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
106154  */
106155 #define USB3_EP_STS_EN_RESERVED0(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED0_SHIFT)) & USB3_EP_STS_EN_RESERVED0_MASK)
106156 #define USB3_EP_STS_EN_DESCMISEN_MASK            (0x10U)
106157 #define USB3_EP_STS_EN_DESCMISEN_SHIFT           (4U)
106158 /*! DESCMISEN - OUT transfer missing descriptor enable. This bit enables the DESCMIS interrupt
106159  */
106160 #define USB3_EP_STS_EN_DESCMISEN(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_DESCMISEN_SHIFT)) & USB3_EP_STS_EN_DESCMISEN_MASK)
106161 #define USB3_EP_STS_EN_STREAMREN_MASK            (0x20U)
106162 #define USB3_EP_STS_EN_STREAMREN_SHIFT           (5U)
106163 /*! STREAMREN - Stream Rejected enable. This bit enables the STREAMR interrupt
106164  */
106165 #define USB3_EP_STS_EN_STREAMREN(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_STREAMREN_SHIFT)) & USB3_EP_STS_EN_STREAMREN_MASK)
106166 #define USB3_EP_STS_EN_MD_EXITEN_MASK            (0x40U)
106167 #define USB3_EP_STS_EN_MD_EXITEN_SHIFT           (6U)
106168 /*! MD_EXITEN - Move Data Exit enable. This bit enables the MD_EXIT interrupt
106169  */
106170 #define USB3_EP_STS_EN_MD_EXITEN(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_MD_EXITEN_SHIFT)) & USB3_EP_STS_EN_MD_EXITEN_MASK)
106171 #define USB3_EP_STS_EN_TRBERREN_MASK             (0x80U)
106172 #define USB3_EP_STS_EN_TRBERREN_SHIFT            (7U)
106173 /*! TRBERREN - TRB enable. This bit enables the TRBERR interrupt
106174  */
106175 #define USB3_EP_STS_EN_TRBERREN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_TRBERREN_SHIFT)) & USB3_EP_STS_EN_TRBERREN_MASK)
106176 #define USB3_EP_STS_EN_NRDYEN_MASK               (0x100U)
106177 #define USB3_EP_STS_EN_NRDYEN_SHIFT              (8U)
106178 /*! NRDYEN - NRDY enable. This bit enables the NRDY interrupt
106179  */
106180 #define USB3_EP_STS_EN_NRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_NRDYEN_SHIFT)) & USB3_EP_STS_EN_NRDYEN_MASK)
106181 #define USB3_EP_STS_EN_RESERVED1_MASK            (0xE00U)
106182 #define USB3_EP_STS_EN_RESERVED1_SHIFT           (9U)
106183 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
106184  */
106185 #define USB3_EP_STS_EN_RESERVED1(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED1_SHIFT)) & USB3_EP_STS_EN_RESERVED1_MASK)
106186 #define USB3_EP_STS_EN_PRIMEEN_MASK              (0x1000U)
106187 #define USB3_EP_STS_EN_PRIMEEN_SHIFT             (12U)
106188 /*! PRIMEEN - Prime enable. This bit enables the PRIME interrupt
106189  */
106190 #define USB3_EP_STS_EN_PRIMEEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_PRIMEEN_SHIFT)) & USB3_EP_STS_EN_PRIMEEN_MASK)
106191 #define USB3_EP_STS_EN_SIDERREN_MASK             (0x2000U)
106192 #define USB3_EP_STS_EN_SIDERREN_SHIFT            (13U)
106193 /*! SIDERREN - Stream error enable. This bit enables the SIDERR interrupt
106194  */
106195 #define USB3_EP_STS_EN_SIDERREN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_SIDERREN_SHIFT)) & USB3_EP_STS_EN_SIDERREN_MASK)
106196 #define USB3_EP_STS_EN_OUTSMMEN_MASK             (0x4000U)
106197 #define USB3_EP_STS_EN_OUTSMMEN_SHIFT            (14U)
106198 /*! OUTSMMEN - OUT size mismatch enable. This bit enables the OUTSMM interrupt
106199  */
106200 #define USB3_EP_STS_EN_OUTSMMEN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_OUTSMMEN_SHIFT)) & USB3_EP_STS_EN_OUTSMMEN_MASK)
106201 #define USB3_EP_STS_EN_ISOERREN_MASK             (0x8000U)
106202 #define USB3_EP_STS_EN_ISOERREN_SHIFT            (15U)
106203 /*! ISOERREN - ISO transmission error enable. This bit enables the ISOERR interrupt
106204  */
106205 #define USB3_EP_STS_EN_ISOERREN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_ISOERREN_SHIFT)) & USB3_EP_STS_EN_ISOERREN_MASK)
106206 #define USB3_EP_STS_EN_RESERVED2_MASK            (0x70000U)
106207 #define USB3_EP_STS_EN_RESERVED2_SHIFT           (16U)
106208 /*! RESERVED2 - Reserved field. Write ignored. 0 when read
106209  */
106210 #define USB3_EP_STS_EN_RESERVED2(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED2_SHIFT)) & USB3_EP_STS_EN_RESERVED2_MASK)
106211 #define USB3_EP_STS_EN_IOTEN_MASK                (0x80000U)
106212 #define USB3_EP_STS_EN_IOTEN_SHIFT               (19U)
106213 /*! IOTEN - Interrupt on Transmission complete enable. This bit enables the IOT interrupt
106214  */
106215 #define USB3_EP_STS_EN_IOTEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_IOTEN_SHIFT)) & USB3_EP_STS_EN_IOTEN_MASK)
106216 #define USB3_EP_STS_EN_RESERVED3_MASK            (0x7FF00000U)
106217 #define USB3_EP_STS_EN_RESERVED3_SHIFT           (20U)
106218 /*! RESERVED3 - Reserved field. Write ignored. 0 when read
106219  */
106220 #define USB3_EP_STS_EN_RESERVED3(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED3_SHIFT)) & USB3_EP_STS_EN_RESERVED3_MASK)
106221 #define USB3_EP_STS_EN_STPWAITEN_MASK            (0x80000000U)
106222 #define USB3_EP_STS_EN_STPWAITEN_SHIFT           (31U)
106223 /*! STPWAITEN - Setup Wait interrupt enable. This bit enables the STPWAIT interrupt. Valid only for EP0
106224  */
106225 #define USB3_EP_STS_EN_STPWAITEN(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_STPWAITEN_SHIFT)) & USB3_EP_STS_EN_STPWAITEN_MASK)
106226 /*! @} */
106227 
106228 /*! @name DRBL - Doorbell Register */
106229 /*! @{ */
106230 #define USB3_DRBL_DRBL0O_MASK                    (0x1U)
106231 #define USB3_DRBL_DRBL0O_SHIFT                   (0U)
106232 /*! DRBL0O - DRBL0O
106233  */
106234 #define USB3_DRBL_DRBL0O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL0O_SHIFT)) & USB3_DRBL_DRBL0O_MASK)
106235 #define USB3_DRBL_DRBL1O_MASK                    (0x2U)
106236 #define USB3_DRBL_DRBL1O_SHIFT                   (1U)
106237 /*! DRBL1O - DRBL1O
106238  */
106239 #define USB3_DRBL_DRBL1O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL1O_SHIFT)) & USB3_DRBL_DRBL1O_MASK)
106240 #define USB3_DRBL_DRBL2O_MASK                    (0x4U)
106241 #define USB3_DRBL_DRBL2O_SHIFT                   (2U)
106242 /*! DRBL2O - DRBL2O
106243  */
106244 #define USB3_DRBL_DRBL2O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL2O_SHIFT)) & USB3_DRBL_DRBL2O_MASK)
106245 #define USB3_DRBL_DRBL3O_MASK                    (0x8U)
106246 #define USB3_DRBL_DRBL3O_SHIFT                   (3U)
106247 /*! DRBL3O - DRBL3O
106248  */
106249 #define USB3_DRBL_DRBL3O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL3O_SHIFT)) & USB3_DRBL_DRBL3O_MASK)
106250 #define USB3_DRBL_DRBL4O_MASK                    (0x10U)
106251 #define USB3_DRBL_DRBL4O_SHIFT                   (4U)
106252 /*! DRBL4O - DRBL4O
106253  */
106254 #define USB3_DRBL_DRBL4O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL4O_SHIFT)) & USB3_DRBL_DRBL4O_MASK)
106255 #define USB3_DRBL_DRBL5O_MASK                    (0x20U)
106256 #define USB3_DRBL_DRBL5O_SHIFT                   (5U)
106257 /*! DRBL5O - DRBL5O
106258  */
106259 #define USB3_DRBL_DRBL5O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL5O_SHIFT)) & USB3_DRBL_DRBL5O_MASK)
106260 #define USB3_DRBL_DRBL6O_MASK                    (0x40U)
106261 #define USB3_DRBL_DRBL6O_SHIFT                   (6U)
106262 /*! DRBL6O - DRBL6O
106263  */
106264 #define USB3_DRBL_DRBL6O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL6O_SHIFT)) & USB3_DRBL_DRBL6O_MASK)
106265 #define USB3_DRBL_DRBL7O_MASK                    (0x80U)
106266 #define USB3_DRBL_DRBL7O_SHIFT                   (7U)
106267 /*! DRBL7O - DRBL7O
106268  */
106269 #define USB3_DRBL_DRBL7O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL7O_SHIFT)) & USB3_DRBL_DRBL7O_MASK)
106270 #define USB3_DRBL_reserved8_MASK                 (0x100U)
106271 #define USB3_DRBL_reserved8_SHIFT                (8U)
106272 /*! reserved8 - reserved8
106273  */
106274 #define USB3_DRBL_reserved8(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved8_SHIFT)) & USB3_DRBL_reserved8_MASK)
106275 #define USB3_DRBL_reserved9_MASK                 (0x200U)
106276 #define USB3_DRBL_reserved9_SHIFT                (9U)
106277 /*! reserved9 - reserved9
106278  */
106279 #define USB3_DRBL_reserved9(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved9_SHIFT)) & USB3_DRBL_reserved9_MASK)
106280 #define USB3_DRBL_reserved10_MASK                (0x400U)
106281 #define USB3_DRBL_reserved10_SHIFT               (10U)
106282 /*! reserved10 - reserved10
106283  */
106284 #define USB3_DRBL_reserved10(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved10_SHIFT)) & USB3_DRBL_reserved10_MASK)
106285 #define USB3_DRBL_reserved11_MASK                (0x800U)
106286 #define USB3_DRBL_reserved11_SHIFT               (11U)
106287 /*! reserved11 - reserved11
106288  */
106289 #define USB3_DRBL_reserved11(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved11_SHIFT)) & USB3_DRBL_reserved11_MASK)
106290 #define USB3_DRBL_reserved12_MASK                (0x1000U)
106291 #define USB3_DRBL_reserved12_SHIFT               (12U)
106292 /*! reserved12 - reserved12
106293  */
106294 #define USB3_DRBL_reserved12(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved12_SHIFT)) & USB3_DRBL_reserved12_MASK)
106295 #define USB3_DRBL_reserved13_MASK                (0x2000U)
106296 #define USB3_DRBL_reserved13_SHIFT               (13U)
106297 /*! reserved13 - reserved13
106298  */
106299 #define USB3_DRBL_reserved13(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved13_SHIFT)) & USB3_DRBL_reserved13_MASK)
106300 #define USB3_DRBL_reserved14_MASK                (0x4000U)
106301 #define USB3_DRBL_reserved14_SHIFT               (14U)
106302 /*! reserved14 - reserved14
106303  */
106304 #define USB3_DRBL_reserved14(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved14_SHIFT)) & USB3_DRBL_reserved14_MASK)
106305 #define USB3_DRBL_reserved15_MASK                (0x8000U)
106306 #define USB3_DRBL_reserved15_SHIFT               (15U)
106307 /*! reserved15 - reserved15
106308  */
106309 #define USB3_DRBL_reserved15(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved15_SHIFT)) & USB3_DRBL_reserved15_MASK)
106310 #define USB3_DRBL_DRBL0I_MASK                    (0x10000U)
106311 #define USB3_DRBL_DRBL0I_SHIFT                   (16U)
106312 /*! DRBL0I - DRBL0I
106313  */
106314 #define USB3_DRBL_DRBL0I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL0I_SHIFT)) & USB3_DRBL_DRBL0I_MASK)
106315 #define USB3_DRBL_DRBL1I_MASK                    (0x20000U)
106316 #define USB3_DRBL_DRBL1I_SHIFT                   (17U)
106317 /*! DRBL1I - DRBL1I
106318  */
106319 #define USB3_DRBL_DRBL1I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL1I_SHIFT)) & USB3_DRBL_DRBL1I_MASK)
106320 #define USB3_DRBL_DRBL2I_MASK                    (0x40000U)
106321 #define USB3_DRBL_DRBL2I_SHIFT                   (18U)
106322 /*! DRBL2I - DRBL2I
106323  */
106324 #define USB3_DRBL_DRBL2I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL2I_SHIFT)) & USB3_DRBL_DRBL2I_MASK)
106325 #define USB3_DRBL_DRBL3I_MASK                    (0x80000U)
106326 #define USB3_DRBL_DRBL3I_SHIFT                   (19U)
106327 /*! DRBL3I - DRBL3I
106328  */
106329 #define USB3_DRBL_DRBL3I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL3I_SHIFT)) & USB3_DRBL_DRBL3I_MASK)
106330 #define USB3_DRBL_DRBL4I_MASK                    (0x100000U)
106331 #define USB3_DRBL_DRBL4I_SHIFT                   (20U)
106332 /*! DRBL4I - DRBL4I
106333  */
106334 #define USB3_DRBL_DRBL4I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL4I_SHIFT)) & USB3_DRBL_DRBL4I_MASK)
106335 #define USB3_DRBL_DRBL5I_MASK                    (0x200000U)
106336 #define USB3_DRBL_DRBL5I_SHIFT                   (21U)
106337 /*! DRBL5I - DRBL5I
106338  */
106339 #define USB3_DRBL_DRBL5I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL5I_SHIFT)) & USB3_DRBL_DRBL5I_MASK)
106340 #define USB3_DRBL_DRBL6I_MASK                    (0x400000U)
106341 #define USB3_DRBL_DRBL6I_SHIFT                   (22U)
106342 /*! DRBL6I - DRBL6I
106343  */
106344 #define USB3_DRBL_DRBL6I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL6I_SHIFT)) & USB3_DRBL_DRBL6I_MASK)
106345 #define USB3_DRBL_DRBL7I_MASK                    (0x800000U)
106346 #define USB3_DRBL_DRBL7I_SHIFT                   (23U)
106347 /*! DRBL7I - DRBL7I
106348  */
106349 #define USB3_DRBL_DRBL7I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL7I_SHIFT)) & USB3_DRBL_DRBL7I_MASK)
106350 #define USB3_DRBL_reserved24_MASK                (0x1000000U)
106351 #define USB3_DRBL_reserved24_SHIFT               (24U)
106352 /*! reserved24 - reserved24
106353  */
106354 #define USB3_DRBL_reserved24(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved24_SHIFT)) & USB3_DRBL_reserved24_MASK)
106355 #define USB3_DRBL_reserved25_MASK                (0x2000000U)
106356 #define USB3_DRBL_reserved25_SHIFT               (25U)
106357 /*! reserved25 - reserved25
106358  */
106359 #define USB3_DRBL_reserved25(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved25_SHIFT)) & USB3_DRBL_reserved25_MASK)
106360 #define USB3_DRBL_reserved26_MASK                (0x4000000U)
106361 #define USB3_DRBL_reserved26_SHIFT               (26U)
106362 /*! reserved26 - reserved26
106363  */
106364 #define USB3_DRBL_reserved26(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved26_SHIFT)) & USB3_DRBL_reserved26_MASK)
106365 #define USB3_DRBL_reserved27_MASK                (0x8000000U)
106366 #define USB3_DRBL_reserved27_SHIFT               (27U)
106367 /*! reserved27 - reserved27
106368  */
106369 #define USB3_DRBL_reserved27(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved27_SHIFT)) & USB3_DRBL_reserved27_MASK)
106370 #define USB3_DRBL_reserved28_MASK                (0x10000000U)
106371 #define USB3_DRBL_reserved28_SHIFT               (28U)
106372 /*! reserved28 - reserved28
106373  */
106374 #define USB3_DRBL_reserved28(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved28_SHIFT)) & USB3_DRBL_reserved28_MASK)
106375 #define USB3_DRBL_reserved29_MASK                (0x20000000U)
106376 #define USB3_DRBL_reserved29_SHIFT               (29U)
106377 /*! reserved29 - reserved29
106378  */
106379 #define USB3_DRBL_reserved29(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved29_SHIFT)) & USB3_DRBL_reserved29_MASK)
106380 #define USB3_DRBL_reserved30_MASK                (0x40000000U)
106381 #define USB3_DRBL_reserved30_SHIFT               (30U)
106382 /*! reserved30 - reserved30
106383  */
106384 #define USB3_DRBL_reserved30(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved30_SHIFT)) & USB3_DRBL_reserved30_MASK)
106385 #define USB3_DRBL_reserved31_MASK                (0x80000000U)
106386 #define USB3_DRBL_reserved31_SHIFT               (31U)
106387 /*! reserved31 - reserved31
106388  */
106389 #define USB3_DRBL_reserved31(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved31_SHIFT)) & USB3_DRBL_reserved31_MASK)
106390 /*! @} */
106391 
106392 /*! @name EP_IEN - Endpoints Interrupt Enable) */
106393 /*! @{ */
106394 #define USB3_EP_IEN_EOUTEN0_MASK                 (0x1U)
106395 #define USB3_EP_IEN_EOUTEN0_SHIFT                (0U)
106396 /*! EOUTEN0 - EOUTEN0
106397  */
106398 #define USB3_EP_IEN_EOUTEN0(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN0_SHIFT)) & USB3_EP_IEN_EOUTEN0_MASK)
106399 #define USB3_EP_IEN_EOUTEN1_MASK                 (0x2U)
106400 #define USB3_EP_IEN_EOUTEN1_SHIFT                (1U)
106401 /*! EOUTEN1 - EOUTEN1
106402  */
106403 #define USB3_EP_IEN_EOUTEN1(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN1_SHIFT)) & USB3_EP_IEN_EOUTEN1_MASK)
106404 #define USB3_EP_IEN_EOUTEN2_MASK                 (0x4U)
106405 #define USB3_EP_IEN_EOUTEN2_SHIFT                (2U)
106406 /*! EOUTEN2 - EOUTEN2
106407  */
106408 #define USB3_EP_IEN_EOUTEN2(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN2_SHIFT)) & USB3_EP_IEN_EOUTEN2_MASK)
106409 #define USB3_EP_IEN_EOUTEN3_MASK                 (0x8U)
106410 #define USB3_EP_IEN_EOUTEN3_SHIFT                (3U)
106411 /*! EOUTEN3 - EOUTEN3
106412  */
106413 #define USB3_EP_IEN_EOUTEN3(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN3_SHIFT)) & USB3_EP_IEN_EOUTEN3_MASK)
106414 #define USB3_EP_IEN_EOUTEN4_MASK                 (0x10U)
106415 #define USB3_EP_IEN_EOUTEN4_SHIFT                (4U)
106416 /*! EOUTEN4 - EOUTEN4
106417  */
106418 #define USB3_EP_IEN_EOUTEN4(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN4_SHIFT)) & USB3_EP_IEN_EOUTEN4_MASK)
106419 #define USB3_EP_IEN_EOUTEN5_MASK                 (0x20U)
106420 #define USB3_EP_IEN_EOUTEN5_SHIFT                (5U)
106421 /*! EOUTEN5 - EOUTEN5
106422  */
106423 #define USB3_EP_IEN_EOUTEN5(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN5_SHIFT)) & USB3_EP_IEN_EOUTEN5_MASK)
106424 #define USB3_EP_IEN_EOUTEN6_MASK                 (0x40U)
106425 #define USB3_EP_IEN_EOUTEN6_SHIFT                (6U)
106426 /*! EOUTEN6 - EOUTEN6
106427  */
106428 #define USB3_EP_IEN_EOUTEN6(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN6_SHIFT)) & USB3_EP_IEN_EOUTEN6_MASK)
106429 #define USB3_EP_IEN_EOUTEN7_MASK                 (0x80U)
106430 #define USB3_EP_IEN_EOUTEN7_SHIFT                (7U)
106431 /*! EOUTEN7 - EOUTEN7
106432  */
106433 #define USB3_EP_IEN_EOUTEN7(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN7_SHIFT)) & USB3_EP_IEN_EOUTEN7_MASK)
106434 #define USB3_EP_IEN_reserved8_MASK               (0x100U)
106435 #define USB3_EP_IEN_reserved8_SHIFT              (8U)
106436 /*! reserved8 - reserved8
106437  */
106438 #define USB3_EP_IEN_reserved8(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved8_SHIFT)) & USB3_EP_IEN_reserved8_MASK)
106439 #define USB3_EP_IEN_reserved9_MASK               (0x200U)
106440 #define USB3_EP_IEN_reserved9_SHIFT              (9U)
106441 /*! reserved9 - reserved9
106442  */
106443 #define USB3_EP_IEN_reserved9(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved9_SHIFT)) & USB3_EP_IEN_reserved9_MASK)
106444 #define USB3_EP_IEN_reserved10_MASK              (0x400U)
106445 #define USB3_EP_IEN_reserved10_SHIFT             (10U)
106446 /*! reserved10 - reserved10
106447  */
106448 #define USB3_EP_IEN_reserved10(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved10_SHIFT)) & USB3_EP_IEN_reserved10_MASK)
106449 #define USB3_EP_IEN_reserved11_MASK              (0x800U)
106450 #define USB3_EP_IEN_reserved11_SHIFT             (11U)
106451 /*! reserved11 - reserved11
106452  */
106453 #define USB3_EP_IEN_reserved11(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved11_SHIFT)) & USB3_EP_IEN_reserved11_MASK)
106454 #define USB3_EP_IEN_reserved12_MASK              (0x1000U)
106455 #define USB3_EP_IEN_reserved12_SHIFT             (12U)
106456 /*! reserved12 - reserved12
106457  */
106458 #define USB3_EP_IEN_reserved12(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved12_SHIFT)) & USB3_EP_IEN_reserved12_MASK)
106459 #define USB3_EP_IEN_reserved13_MASK              (0x2000U)
106460 #define USB3_EP_IEN_reserved13_SHIFT             (13U)
106461 /*! reserved13 - reserved13
106462  */
106463 #define USB3_EP_IEN_reserved13(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved13_SHIFT)) & USB3_EP_IEN_reserved13_MASK)
106464 #define USB3_EP_IEN_reserved14_MASK              (0x4000U)
106465 #define USB3_EP_IEN_reserved14_SHIFT             (14U)
106466 /*! reserved14 - reserved14
106467  */
106468 #define USB3_EP_IEN_reserved14(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved14_SHIFT)) & USB3_EP_IEN_reserved14_MASK)
106469 #define USB3_EP_IEN_reserved15_MASK              (0x8000U)
106470 #define USB3_EP_IEN_reserved15_SHIFT             (15U)
106471 /*! reserved15 - reserved15
106472  */
106473 #define USB3_EP_IEN_reserved15(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved15_SHIFT)) & USB3_EP_IEN_reserved15_MASK)
106474 #define USB3_EP_IEN_EINEN0_MASK                  (0x10000U)
106475 #define USB3_EP_IEN_EINEN0_SHIFT                 (16U)
106476 /*! EINEN0 - EINEN0
106477  */
106478 #define USB3_EP_IEN_EINEN0(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN0_SHIFT)) & USB3_EP_IEN_EINEN0_MASK)
106479 #define USB3_EP_IEN_EINEN1_MASK                  (0x20000U)
106480 #define USB3_EP_IEN_EINEN1_SHIFT                 (17U)
106481 /*! EINEN1 - EINEN1
106482  */
106483 #define USB3_EP_IEN_EINEN1(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN1_SHIFT)) & USB3_EP_IEN_EINEN1_MASK)
106484 #define USB3_EP_IEN_EINEN2_MASK                  (0x40000U)
106485 #define USB3_EP_IEN_EINEN2_SHIFT                 (18U)
106486 /*! EINEN2 - EINEN2
106487  */
106488 #define USB3_EP_IEN_EINEN2(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN2_SHIFT)) & USB3_EP_IEN_EINEN2_MASK)
106489 #define USB3_EP_IEN_EINEN3_MASK                  (0x80000U)
106490 #define USB3_EP_IEN_EINEN3_SHIFT                 (19U)
106491 /*! EINEN3 - EINEN3
106492  */
106493 #define USB3_EP_IEN_EINEN3(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN3_SHIFT)) & USB3_EP_IEN_EINEN3_MASK)
106494 #define USB3_EP_IEN_EINEN4_MASK                  (0x100000U)
106495 #define USB3_EP_IEN_EINEN4_SHIFT                 (20U)
106496 /*! EINEN4 - EINEN4
106497  */
106498 #define USB3_EP_IEN_EINEN4(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN4_SHIFT)) & USB3_EP_IEN_EINEN4_MASK)
106499 #define USB3_EP_IEN_EINEN5_MASK                  (0x200000U)
106500 #define USB3_EP_IEN_EINEN5_SHIFT                 (21U)
106501 /*! EINEN5 - EINEN5
106502  */
106503 #define USB3_EP_IEN_EINEN5(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN5_SHIFT)) & USB3_EP_IEN_EINEN5_MASK)
106504 #define USB3_EP_IEN_EINEN6_MASK                  (0x400000U)
106505 #define USB3_EP_IEN_EINEN6_SHIFT                 (22U)
106506 /*! EINEN6 - EINEN6
106507  */
106508 #define USB3_EP_IEN_EINEN6(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN6_SHIFT)) & USB3_EP_IEN_EINEN6_MASK)
106509 #define USB3_EP_IEN_EINEN7_MASK                  (0x800000U)
106510 #define USB3_EP_IEN_EINEN7_SHIFT                 (23U)
106511 /*! EINEN7 - EINEN7
106512  */
106513 #define USB3_EP_IEN_EINEN7(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN7_SHIFT)) & USB3_EP_IEN_EINEN7_MASK)
106514 #define USB3_EP_IEN_reserved24_MASK              (0x1000000U)
106515 #define USB3_EP_IEN_reserved24_SHIFT             (24U)
106516 /*! reserved24 - reserved24
106517  */
106518 #define USB3_EP_IEN_reserved24(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved24_SHIFT)) & USB3_EP_IEN_reserved24_MASK)
106519 #define USB3_EP_IEN_reserved25_MASK              (0x2000000U)
106520 #define USB3_EP_IEN_reserved25_SHIFT             (25U)
106521 /*! reserved25 - reserved25
106522  */
106523 #define USB3_EP_IEN_reserved25(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved25_SHIFT)) & USB3_EP_IEN_reserved25_MASK)
106524 #define USB3_EP_IEN_reserved26_MASK              (0x4000000U)
106525 #define USB3_EP_IEN_reserved26_SHIFT             (26U)
106526 /*! reserved26 - reserved26
106527  */
106528 #define USB3_EP_IEN_reserved26(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved26_SHIFT)) & USB3_EP_IEN_reserved26_MASK)
106529 #define USB3_EP_IEN_reserved27_MASK              (0x8000000U)
106530 #define USB3_EP_IEN_reserved27_SHIFT             (27U)
106531 /*! reserved27 - reserved27
106532  */
106533 #define USB3_EP_IEN_reserved27(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved27_SHIFT)) & USB3_EP_IEN_reserved27_MASK)
106534 #define USB3_EP_IEN_reserved28_MASK              (0x10000000U)
106535 #define USB3_EP_IEN_reserved28_SHIFT             (28U)
106536 /*! reserved28 - reserved28
106537  */
106538 #define USB3_EP_IEN_reserved28(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved28_SHIFT)) & USB3_EP_IEN_reserved28_MASK)
106539 #define USB3_EP_IEN_reserved29_MASK              (0x20000000U)
106540 #define USB3_EP_IEN_reserved29_SHIFT             (29U)
106541 /*! reserved29 - reserved29
106542  */
106543 #define USB3_EP_IEN_reserved29(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved29_SHIFT)) & USB3_EP_IEN_reserved29_MASK)
106544 #define USB3_EP_IEN_reserved30_MASK              (0x40000000U)
106545 #define USB3_EP_IEN_reserved30_SHIFT             (30U)
106546 /*! reserved30 - reserved30
106547  */
106548 #define USB3_EP_IEN_reserved30(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved30_SHIFT)) & USB3_EP_IEN_reserved30_MASK)
106549 #define USB3_EP_IEN_reserved31_MASK              (0x80000000U)
106550 #define USB3_EP_IEN_reserved31_SHIFT             (31U)
106551 /*! reserved31 - reserved31
106552  */
106553 #define USB3_EP_IEN_reserved31(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved31_SHIFT)) & USB3_EP_IEN_reserved31_MASK)
106554 /*! @} */
106555 
106556 /*! @name EP_ISTS - Endpoints Interrupt Status */
106557 /*! @{ */
106558 #define USB3_EP_ISTS_EOUT0_MASK                  (0x1U)
106559 #define USB3_EP_ISTS_EOUT0_SHIFT                 (0U)
106560 /*! EOUT0 - EOUT0
106561  */
106562 #define USB3_EP_ISTS_EOUT0(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT0_SHIFT)) & USB3_EP_ISTS_EOUT0_MASK)
106563 #define USB3_EP_ISTS_EOUT1_MASK                  (0x2U)
106564 #define USB3_EP_ISTS_EOUT1_SHIFT                 (1U)
106565 /*! EOUT1 - EOUT1
106566  */
106567 #define USB3_EP_ISTS_EOUT1(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT1_SHIFT)) & USB3_EP_ISTS_EOUT1_MASK)
106568 #define USB3_EP_ISTS_EOUT2_MASK                  (0x4U)
106569 #define USB3_EP_ISTS_EOUT2_SHIFT                 (2U)
106570 /*! EOUT2 - EOUT2
106571  */
106572 #define USB3_EP_ISTS_EOUT2(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT2_SHIFT)) & USB3_EP_ISTS_EOUT2_MASK)
106573 #define USB3_EP_ISTS_EOUT3_MASK                  (0x8U)
106574 #define USB3_EP_ISTS_EOUT3_SHIFT                 (3U)
106575 /*! EOUT3 - EOUT3
106576  */
106577 #define USB3_EP_ISTS_EOUT3(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT3_SHIFT)) & USB3_EP_ISTS_EOUT3_MASK)
106578 #define USB3_EP_ISTS_EOUT4_MASK                  (0x10U)
106579 #define USB3_EP_ISTS_EOUT4_SHIFT                 (4U)
106580 /*! EOUT4 - EOUT4
106581  */
106582 #define USB3_EP_ISTS_EOUT4(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT4_SHIFT)) & USB3_EP_ISTS_EOUT4_MASK)
106583 #define USB3_EP_ISTS_EOUT5_MASK                  (0x20U)
106584 #define USB3_EP_ISTS_EOUT5_SHIFT                 (5U)
106585 /*! EOUT5 - EOUT5
106586  */
106587 #define USB3_EP_ISTS_EOUT5(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT5_SHIFT)) & USB3_EP_ISTS_EOUT5_MASK)
106588 #define USB3_EP_ISTS_EOUT6_MASK                  (0x40U)
106589 #define USB3_EP_ISTS_EOUT6_SHIFT                 (6U)
106590 /*! EOUT6 - EOUT6
106591  */
106592 #define USB3_EP_ISTS_EOUT6(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT6_SHIFT)) & USB3_EP_ISTS_EOUT6_MASK)
106593 #define USB3_EP_ISTS_EOUT7_MASK                  (0x80U)
106594 #define USB3_EP_ISTS_EOUT7_SHIFT                 (7U)
106595 /*! EOUT7 - EOUT7
106596  */
106597 #define USB3_EP_ISTS_EOUT7(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT7_SHIFT)) & USB3_EP_ISTS_EOUT7_MASK)
106598 #define USB3_EP_ISTS_reserved8_MASK              (0x100U)
106599 #define USB3_EP_ISTS_reserved8_SHIFT             (8U)
106600 /*! reserved8 - reserved8
106601  */
106602 #define USB3_EP_ISTS_reserved8(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved8_SHIFT)) & USB3_EP_ISTS_reserved8_MASK)
106603 #define USB3_EP_ISTS_reserved9_MASK              (0x200U)
106604 #define USB3_EP_ISTS_reserved9_SHIFT             (9U)
106605 /*! reserved9 - reserved9
106606  */
106607 #define USB3_EP_ISTS_reserved9(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved9_SHIFT)) & USB3_EP_ISTS_reserved9_MASK)
106608 #define USB3_EP_ISTS_reserved10_MASK             (0x400U)
106609 #define USB3_EP_ISTS_reserved10_SHIFT            (10U)
106610 /*! reserved10 - reserved10
106611  */
106612 #define USB3_EP_ISTS_reserved10(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved10_SHIFT)) & USB3_EP_ISTS_reserved10_MASK)
106613 #define USB3_EP_ISTS_reserved11_MASK             (0x800U)
106614 #define USB3_EP_ISTS_reserved11_SHIFT            (11U)
106615 /*! reserved11 - reserved11
106616  */
106617 #define USB3_EP_ISTS_reserved11(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved11_SHIFT)) & USB3_EP_ISTS_reserved11_MASK)
106618 #define USB3_EP_ISTS_reserved12_MASK             (0x1000U)
106619 #define USB3_EP_ISTS_reserved12_SHIFT            (12U)
106620 /*! reserved12 - reserved12
106621  */
106622 #define USB3_EP_ISTS_reserved12(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved12_SHIFT)) & USB3_EP_ISTS_reserved12_MASK)
106623 #define USB3_EP_ISTS_reserved13_MASK             (0x2000U)
106624 #define USB3_EP_ISTS_reserved13_SHIFT            (13U)
106625 /*! reserved13 - reserved13
106626  */
106627 #define USB3_EP_ISTS_reserved13(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved13_SHIFT)) & USB3_EP_ISTS_reserved13_MASK)
106628 #define USB3_EP_ISTS_reserved14_MASK             (0x4000U)
106629 #define USB3_EP_ISTS_reserved14_SHIFT            (14U)
106630 /*! reserved14 - reserved14
106631  */
106632 #define USB3_EP_ISTS_reserved14(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved14_SHIFT)) & USB3_EP_ISTS_reserved14_MASK)
106633 #define USB3_EP_ISTS_reserved15_MASK             (0x8000U)
106634 #define USB3_EP_ISTS_reserved15_SHIFT            (15U)
106635 /*! reserved15 - reserved15
106636  */
106637 #define USB3_EP_ISTS_reserved15(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved15_SHIFT)) & USB3_EP_ISTS_reserved15_MASK)
106638 #define USB3_EP_ISTS_EIN0_MASK                   (0x10000U)
106639 #define USB3_EP_ISTS_EIN0_SHIFT                  (16U)
106640 /*! EIN0 - EIN0
106641  */
106642 #define USB3_EP_ISTS_EIN0(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN0_SHIFT)) & USB3_EP_ISTS_EIN0_MASK)
106643 #define USB3_EP_ISTS_EIN1_MASK                   (0x20000U)
106644 #define USB3_EP_ISTS_EIN1_SHIFT                  (17U)
106645 /*! EIN1 - EIN1
106646  */
106647 #define USB3_EP_ISTS_EIN1(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN1_SHIFT)) & USB3_EP_ISTS_EIN1_MASK)
106648 #define USB3_EP_ISTS_EIN2_MASK                   (0x40000U)
106649 #define USB3_EP_ISTS_EIN2_SHIFT                  (18U)
106650 /*! EIN2 - EIN2
106651  */
106652 #define USB3_EP_ISTS_EIN2(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN2_SHIFT)) & USB3_EP_ISTS_EIN2_MASK)
106653 #define USB3_EP_ISTS_EIN3_MASK                   (0x80000U)
106654 #define USB3_EP_ISTS_EIN3_SHIFT                  (19U)
106655 /*! EIN3 - EIN3
106656  */
106657 #define USB3_EP_ISTS_EIN3(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN3_SHIFT)) & USB3_EP_ISTS_EIN3_MASK)
106658 #define USB3_EP_ISTS_EIN4_MASK                   (0x100000U)
106659 #define USB3_EP_ISTS_EIN4_SHIFT                  (20U)
106660 /*! EIN4 - EIN4
106661  */
106662 #define USB3_EP_ISTS_EIN4(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN4_SHIFT)) & USB3_EP_ISTS_EIN4_MASK)
106663 #define USB3_EP_ISTS_EIN5_MASK                   (0x200000U)
106664 #define USB3_EP_ISTS_EIN5_SHIFT                  (21U)
106665 /*! EIN5 - EIN5
106666  */
106667 #define USB3_EP_ISTS_EIN5(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN5_SHIFT)) & USB3_EP_ISTS_EIN5_MASK)
106668 #define USB3_EP_ISTS_EIN6_MASK                   (0x400000U)
106669 #define USB3_EP_ISTS_EIN6_SHIFT                  (22U)
106670 /*! EIN6 - EIN6
106671  */
106672 #define USB3_EP_ISTS_EIN6(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN6_SHIFT)) & USB3_EP_ISTS_EIN6_MASK)
106673 #define USB3_EP_ISTS_EIN7_MASK                   (0x800000U)
106674 #define USB3_EP_ISTS_EIN7_SHIFT                  (23U)
106675 /*! EIN7 - EIN7
106676  */
106677 #define USB3_EP_ISTS_EIN7(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN7_SHIFT)) & USB3_EP_ISTS_EIN7_MASK)
106678 #define USB3_EP_ISTS_reserved24_MASK             (0x1000000U)
106679 #define USB3_EP_ISTS_reserved24_SHIFT            (24U)
106680 /*! reserved24 - reserved24
106681  */
106682 #define USB3_EP_ISTS_reserved24(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved24_SHIFT)) & USB3_EP_ISTS_reserved24_MASK)
106683 #define USB3_EP_ISTS_reserved25_MASK             (0x2000000U)
106684 #define USB3_EP_ISTS_reserved25_SHIFT            (25U)
106685 /*! reserved25 - reserved25
106686  */
106687 #define USB3_EP_ISTS_reserved25(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved25_SHIFT)) & USB3_EP_ISTS_reserved25_MASK)
106688 #define USB3_EP_ISTS_reserved26_MASK             (0x4000000U)
106689 #define USB3_EP_ISTS_reserved26_SHIFT            (26U)
106690 /*! reserved26 - reserved26
106691  */
106692 #define USB3_EP_ISTS_reserved26(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved26_SHIFT)) & USB3_EP_ISTS_reserved26_MASK)
106693 #define USB3_EP_ISTS_reserved27_MASK             (0x8000000U)
106694 #define USB3_EP_ISTS_reserved27_SHIFT            (27U)
106695 /*! reserved27 - reserved27
106696  */
106697 #define USB3_EP_ISTS_reserved27(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved27_SHIFT)) & USB3_EP_ISTS_reserved27_MASK)
106698 #define USB3_EP_ISTS_reserved28_MASK             (0x10000000U)
106699 #define USB3_EP_ISTS_reserved28_SHIFT            (28U)
106700 /*! reserved28 - reserved28
106701  */
106702 #define USB3_EP_ISTS_reserved28(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved28_SHIFT)) & USB3_EP_ISTS_reserved28_MASK)
106703 #define USB3_EP_ISTS_reserved29_MASK             (0x20000000U)
106704 #define USB3_EP_ISTS_reserved29_SHIFT            (29U)
106705 /*! reserved29 - reserved29
106706  */
106707 #define USB3_EP_ISTS_reserved29(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved29_SHIFT)) & USB3_EP_ISTS_reserved29_MASK)
106708 #define USB3_EP_ISTS_reserved30_MASK             (0x40000000U)
106709 #define USB3_EP_ISTS_reserved30_SHIFT            (30U)
106710 /*! reserved30 - reserved30
106711  */
106712 #define USB3_EP_ISTS_reserved30(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved30_SHIFT)) & USB3_EP_ISTS_reserved30_MASK)
106713 #define USB3_EP_ISTS_reserved31_MASK             (0x80000000U)
106714 #define USB3_EP_ISTS_reserved31_SHIFT            (31U)
106715 /*! reserved31 - reserved31
106716  */
106717 #define USB3_EP_ISTS_reserved31(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved31_SHIFT)) & USB3_EP_ISTS_reserved31_MASK)
106718 /*! @} */
106719 
106720 /*! @name USB_PWR - Global power configuration */
106721 /*! @{ */
106722 #define USB3_USB_PWR_PSO_EN_MASK                 (0x1U)
106723 #define USB3_USB_PWR_PSO_EN_SHIFT                (0U)
106724 /*! PSO_EN - Power Shut Off capability enable. Writing '1' to this bit enables dower domains
106725  *    switching capability and clears the PSO_DS bit. The Domain will be switched off if both PSO_EN will
106726  *    be set and the USB controller will be in the in the U3 state. It is recommended to set this bit
106727  *    in U3ENTI interrupt service, after software ensures that no data transfer is pending. If this
106728  *    bit will be always set, the controller will automatically switch off the power in the
106729  *    switchable PD after USB controller will enter U3 state
106730  */
106731 #define USB3_USB_PWR_PSO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_PSO_EN_SHIFT)) & USB3_USB_PWR_PSO_EN_MASK)
106732 #define USB3_USB_PWR_PSO_DS_MASK                 (0x2U)
106733 #define USB3_USB_PWR_PSO_DS_SHIFT                (1U)
106734 /*! PSO_DS - Power Shut Off capability disable. Writing '1' to this bit disables power domains
106735  *    switching capability and clears the PSO_EN bit. It is recommended to set this bit after during
106736  *    U3EXTI interrupt service
106737  */
106738 #define USB3_USB_PWR_PSO_DS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_PSO_DS_SHIFT)) & USB3_USB_PWR_PSO_DS_MASK)
106739 #define USB3_USB_PWR_RESERVED0_MASK              (0xFCU)
106740 #define USB3_USB_PWR_RESERVED0_SHIFT             (2U)
106741 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
106742  */
106743 #define USB3_USB_PWR_RESERVED0(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_RESERVED0_SHIFT)) & USB3_USB_PWR_RESERVED0_MASK)
106744 #define USB3_USB_PWR_STB_CLK_SWITCH_EN_MASK      (0x100U)
106745 #define USB3_USB_PWR_STB_CLK_SWITCH_EN_SHIFT     (8U)
106746 /*! STB_CLK_SWITCH_EN - Enables turning-off Reference Clock. This bit is optional and implemented
106747  *    only when support for OTG is implemented (indicated by OTG_READY bit set to 1)
106748  */
106749 #define USB3_USB_PWR_STB_CLK_SWITCH_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_STB_CLK_SWITCH_EN_SHIFT)) & USB3_USB_PWR_STB_CLK_SWITCH_EN_MASK)
106750 #define USB3_USB_PWR_STB_CLK_SWITCH_DONE_MASK    (0x200U)
106751 #define USB3_USB_PWR_STB_CLK_SWITCH_DONE_SHIFT   (9U)
106752 /*! STB_CLK_SWITCH_DONE - Status bit indicating that operation required by STB_CLK_SWITCH_EN write
106753  *    is completed. This bit is optional and implemented only when support for OTG is implemented
106754  *    (indicated by OTG_READY bit set to 1)
106755  */
106756 #define USB3_USB_PWR_STB_CLK_SWITCH_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_STB_CLK_SWITCH_DONE_SHIFT)) & USB3_USB_PWR_STB_CLK_SWITCH_DONE_MASK)
106757 #define USB3_USB_PWR_RESERVED1_MASK              (0x3FFFFC00U)
106758 #define USB3_USB_PWR_RESERVED1_SHIFT             (10U)
106759 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
106760  */
106761 #define USB3_USB_PWR_RESERVED1(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_RESERVED1_SHIFT)) & USB3_USB_PWR_RESERVED1_MASK)
106762 #define USB3_USB_PWR_FAST_REG_ACCESS_STAT_MASK   (0x40000000U)
106763 #define USB3_USB_PWR_FAST_REG_ACCESS_STAT_SHIFT  (30U)
106764 /*! FAST_REG_ACCESS_STAT - Fast Registers Access status. This bit informs if Fast Registers Access
106765  *    is enabled. It should be used as described in FAST_REG_ACCESS bit
106766  */
106767 #define USB3_USB_PWR_FAST_REG_ACCESS_STAT(x)     (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_FAST_REG_ACCESS_STAT_SHIFT)) & USB3_USB_PWR_FAST_REG_ACCESS_STAT_MASK)
106768 #define USB3_USB_PWR_FAST_REG_ACCESS_MASK        (0x80000000U)
106769 #define USB3_USB_PWR_FAST_REG_ACCESS_SHIFT       (31U)
106770 /*! FAST_REG_ACCESS - Fast Registers Access. When Device Port is in a low power state (U3/L2/Not
106771  *    Connected), accesses to registers listed in section 2.3 of USBSS-DEV design specification may
106772  *    take long time. In order to enable fast register access in that case, user can use this register
106773  *    in the following way: - set FAST_REG_ACCESS bit - wait until FAST_REG_ACCESS_STAT bit is set -
106774  *    perform required accesses - clear FAST_REG_ACCESS bit Note that to enable USBSS-DEV low power
106775  *    state entry (U3/L2), the FAST_REG_ACCESS bit has to be cleared
106776  */
106777 #define USB3_USB_PWR_FAST_REG_ACCESS(x)          (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_FAST_REG_ACCESS_SHIFT)) & USB3_USB_PWR_FAST_REG_ACCESS_MASK)
106778 /*! @} */
106779 
106780 /*! @name USB_CONF2 - USB configuration */
106781 /*! @{ */
106782 #define USB3_USB_CONF2_AHB_RETRY_EN_MASK         (0x1U)
106783 #define USB3_USB_CONF2_AHB_RETRY_EN_SHIFT        (0U)
106784 /*! AHB_RETRY_EN - AHB retry enable. This bit enables the AHB retrys for AHB slave interface. This
106785  *    bit has no effect when AHB slave interface is not implemented
106786  */
106787 #define USB3_USB_CONF2_AHB_RETRY_EN(x)           (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF2_AHB_RETRY_EN_SHIFT)) & USB3_USB_CONF2_AHB_RETRY_EN_MASK)
106788 #define USB3_USB_CONF2_RESERVED_MASK             (0xFFFFFFFEU)
106789 #define USB3_USB_CONF2_RESERVED_SHIFT            (1U)
106790 /*! RESERVED - Reserved field. Write ignored. 0 when read
106791  */
106792 #define USB3_USB_CONF2_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF2_RESERVED_SHIFT)) & USB3_USB_CONF2_RESERVED_MASK)
106793 /*! @} */
106794 
106795 /*! @name USB_CAP1 - USB Capability */
106796 /*! @{ */
106797 #define USB3_USB_CAP1_SFR_TYPE_MASK              (0xFU)
106798 #define USB3_USB_CAP1_SFR_TYPE_SHIFT             (0U)
106799 /*! SFR_TYPE - SFR Interface type. This field reflects type of SFR interface implemented: 0x0 - OCP,
106800  *    0x1 - AHB, 0x2 - PLB, 0x3 - AXI, 0x4-0xF - reserved
106801  */
106802 #define USB3_USB_CAP1_SFR_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_SFR_TYPE_SHIFT)) & USB3_USB_CAP1_SFR_TYPE_MASK)
106803 #define USB3_USB_CAP1_SFR_WIDTH_MASK             (0xF0U)
106804 #define USB3_USB_CAP1_SFR_WIDTH_SHIFT            (4U)
106805 /*! SFR_WIDTH - SFR Interface width. This field reflects width of SFR interface implemented: - 0x0:
106806  *    8 bit interface, - 0x1: 16 bit interface, - 0x2: 32 bit interface, - 0x3: 64 bit interface, -
106807  *    0x4-0xF: reserved
106808  */
106809 #define USB3_USB_CAP1_SFR_WIDTH(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_SFR_WIDTH_SHIFT)) & USB3_USB_CAP1_SFR_WIDTH_MASK)
106810 #define USB3_USB_CAP1_DMA_TYPE_MASK              (0xF00U)
106811 #define USB3_USB_CAP1_DMA_TYPE_SHIFT             (8U)
106812 /*! DMA_TYPE - DMA Interface type. This field reflects type of DMA interface implemented: - 0x0:
106813  *    OCP, - 0x1: AHB, - 0x2: PLB, - 0x3: AXI, - 0x4-0xF: reserved
106814  */
106815 #define USB3_USB_CAP1_DMA_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_DMA_TYPE_SHIFT)) & USB3_USB_CAP1_DMA_TYPE_MASK)
106816 #define USB3_USB_CAP1_DMA_WIDTH_MASK             (0xF000U)
106817 #define USB3_USB_CAP1_DMA_WIDTH_SHIFT            (12U)
106818 /*! DMA_WIDTH - DMA Interface width. This field reflects width of DMA interface implemented: - 0x0:
106819  *    reserved, - 0x1: reserved, - 0x2: 32 bit interface, - 0x3: 64 bit interface, - 0x4-0xF:
106820  *    reserved
106821  */
106822 #define USB3_USB_CAP1_DMA_WIDTH(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_DMA_WIDTH_SHIFT)) & USB3_USB_CAP1_DMA_WIDTH_MASK)
106823 #define USB3_USB_CAP1_U3PHY_TYPE_MASK            (0xF0000U)
106824 #define USB3_USB_CAP1_U3PHY_TYPE_SHIFT           (16U)
106825 /*! U3PHY_TYPE - USB3 PHY Interface type. This field reflects type of USB3 PHY interface
106826  *    implemented: - 0x0: USB PIPE, - 0x1: RMMI, - 0x2-0xF: reserved
106827  */
106828 #define USB3_USB_CAP1_U3PHY_TYPE(x)              (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U3PHY_TYPE_SHIFT)) & USB3_USB_CAP1_U3PHY_TYPE_MASK)
106829 #define USB3_USB_CAP1_U3PHY_WIDTH_MASK           (0xF00000U)
106830 #define USB3_USB_CAP1_U3PHY_WIDTH_SHIFT          (20U)
106831 /*! U3PHY_WIDTH - USB3 PHY Interface width. This field reflects width of USB3 PHY interface
106832  *    implemented: - 0x0: 8 bit PIPE interface, - 0x1: 16 bit PIPE interface, - 0x2: 32 bit PIPE interface,
106833  *    - 0x3: 64 bit PIPE interface, - 0x4-0xF: reserved. Note: When SSIC interface is implemented
106834  *    this field shows the width of internal PIPE interface. The RMMI interface is always 20-bit wide
106835  */
106836 #define USB3_USB_CAP1_U3PHY_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U3PHY_WIDTH_SHIFT)) & USB3_USB_CAP1_U3PHY_WIDTH_MASK)
106837 #define USB3_USB_CAP1_U2PHY_EN_MASK              (0x1000000U)
106838 #define USB3_USB_CAP1_U2PHY_EN_SHIFT             (24U)
106839 /*! U2PHY_EN - USB2 PHY Interface enable. This field informs if USB2 PHY interface is implemented: -
106840  *    interface NOT implemented: 0x0, - interface implemented: 0x1
106841  */
106842 #define USB3_USB_CAP1_U2PHY_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U2PHY_EN_SHIFT)) & USB3_USB_CAP1_U2PHY_EN_MASK)
106843 #define USB3_USB_CAP1_U2PHY_TYPE_MASK            (0x2000000U)
106844 #define USB3_USB_CAP1_U2PHY_TYPE_SHIFT           (25U)
106845 /*! U2PHY_TYPE - USB2 PHY Interface type. This field reflects type of USB2 PHY interface implemented: - UTMI: 0x0, - ULPI: 0x1
106846  */
106847 #define USB3_USB_CAP1_U2PHY_TYPE(x)              (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U2PHY_TYPE_SHIFT)) & USB3_USB_CAP1_U2PHY_TYPE_MASK)
106848 #define USB3_USB_CAP1_U2PHY_WIDTH_MASK           (0x4000000U)
106849 #define USB3_USB_CAP1_U2PHY_WIDTH_SHIFT          (26U)
106850 /*! U2PHY_WIDTH - USB2 PHY Interface width. This field reflects width of USB2 PHY interface
106851  *    implemented: - 8 bit interface: 0x0, - 16 bit interface: 0x1. Note: The ULPI interface is always 8-bit
106852  *    wide
106853  */
106854 #define USB3_USB_CAP1_U2PHY_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U2PHY_WIDTH_SHIFT)) & USB3_USB_CAP1_U2PHY_WIDTH_MASK)
106855 #define USB3_USB_CAP1_OTG_READY_MASK             (0x8000000U)
106856 #define USB3_USB_CAP1_OTG_READY_SHIFT            (27U)
106857 /*! OTG_READY - This field informs if device is OTG ready: - pure device mode: 0x0, - some features
106858  *    and ports for CDNS USB OTG controller are implemented: 0x1
106859  */
106860 #define USB3_USB_CAP1_OTG_READY(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_OTG_READY_SHIFT)) & USB3_USB_CAP1_OTG_READY_MASK)
106861 #define USB3_USB_CAP1_RESERVED_MASK              (0xF0000000U)
106862 #define USB3_USB_CAP1_RESERVED_SHIFT             (28U)
106863 /*! RESERVED - This field is reserved and it is always 0 when reading
106864  */
106865 #define USB3_USB_CAP1_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_RESERVED_SHIFT)) & USB3_USB_CAP1_RESERVED_MASK)
106866 /*! @} */
106867 
106868 /*! @name USB_CAP2 - USB Capability */
106869 /*! @{ */
106870 #define USB3_USB_CAP2_ACTUAL_MEM_SIZE_MASK       (0xFFU)
106871 #define USB3_USB_CAP2_ACTUAL_MEM_SIZE_SHIFT      (0U)
106872 /*! ACTUAL_MEM_SIZE - The actual size of the connected On-chip RAM memory in kB: - 0 means 256 kB
106873  *    (max supported mem size) - value other than 0 reflects the mem size in kB. This value reflects
106874  *    the CDNS_USBSSDEV_ATTACHED_MEM_SIZE parameter defined in the usbss_dev_defines.v file. This
106875  *    value has to be adequately set before synthesis by engineer who connects the on-chip memory for
106876  *    controller
106877  */
106878 #define USB3_USB_CAP2_ACTUAL_MEM_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP2_ACTUAL_MEM_SIZE_SHIFT)) & USB3_USB_CAP2_ACTUAL_MEM_SIZE_MASK)
106879 #define USB3_USB_CAP2_MAX_MEM_SIZE_MASK          (0x1F00U)
106880 #define USB3_USB_CAP2_MAX_MEM_SIZE_SHIFT         (8U)
106881 /*! MAX_MEM_SIZE - Max supported mem size. This field reflects width of on-chip RAM address bus
106882  *    width, which determines max supported mem size: 0x0-0x7 reserved, 0x8 - support for 4kB mem, 0x9 -
106883  *    support for 8kB mem, 0xA - support for 16kB mem, 0xB - support for 32kB mem, 0xC - support
106884  *    for 64kB mem, 0xD - support for 128kB mem, 0xE - support for 256kB mem, 0xF - reserved
106885  */
106886 #define USB3_USB_CAP2_MAX_MEM_SIZE(x)            (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP2_MAX_MEM_SIZE_SHIFT)) & USB3_USB_CAP2_MAX_MEM_SIZE_MASK)
106887 #define USB3_USB_CAP2_RESERVED_MASK              (0xFFFFE000U)
106888 #define USB3_USB_CAP2_RESERVED_SHIFT             (13U)
106889 /*! RESERVED - RESERVED
106890  */
106891 #define USB3_USB_CAP2_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP2_RESERVED_SHIFT)) & USB3_USB_CAP2_RESERVED_MASK)
106892 /*! @} */
106893 
106894 /*! @name USB_CAP3 - USB Capability */
106895 /*! @{ */
106896 #define USB3_USB_CAP3_EPOUT_N_MASK               (0xFFFFU)
106897 #define USB3_USB_CAP3_EPOUT_N_SHIFT              (0U)
106898 /*! EPOUT_N - EPOUT_N
106899  */
106900 #define USB3_USB_CAP3_EPOUT_N(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP3_EPOUT_N_SHIFT)) & USB3_USB_CAP3_EPOUT_N_MASK)
106901 #define USB3_USB_CAP3_EPIN_N_MASK                (0xFFFF0000U)
106902 #define USB3_USB_CAP3_EPIN_N_SHIFT               (16U)
106903 /*! EPIN_N - EPIN_N
106904  */
106905 #define USB3_USB_CAP3_EPIN_N(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP3_EPIN_N_SHIFT)) & USB3_USB_CAP3_EPIN_N_MASK)
106906 /*! @} */
106907 
106908 /*! @name USB_CAP4 - ISO HW support */
106909 /*! @{ */
106910 #define USB3_USB_CAP4_EPOUTI_N_MASK              (0xFFFFU)
106911 #define USB3_USB_CAP4_EPOUTI_N_SHIFT             (0U)
106912 /*! EPOUTI_N - EPOUTI_N
106913  */
106914 #define USB3_USB_CAP4_EPOUTI_N(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP4_EPOUTI_N_SHIFT)) & USB3_USB_CAP4_EPOUTI_N_MASK)
106915 #define USB3_USB_CAP4_EPINI_N_MASK               (0xFFFF0000U)
106916 #define USB3_USB_CAP4_EPINI_N_SHIFT              (16U)
106917 /*! EPINI_N - EPINI_N
106918  */
106919 #define USB3_USB_CAP4_EPINI_N(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP4_EPINI_N_SHIFT)) & USB3_USB_CAP4_EPINI_N_MASK)
106920 /*! @} */
106921 
106922 /*! @name USB_CAP5 - Bulk Stream HW */
106923 /*! @{ */
106924 #define USB3_USB_CAP5_EPOUTI_N_MASK              (0xFFFFU)
106925 #define USB3_USB_CAP5_EPOUTI_N_SHIFT             (0U)
106926 /*! EPOUTI_N - EPOUTI_N
106927  */
106928 #define USB3_USB_CAP5_EPOUTI_N(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP5_EPOUTI_N_SHIFT)) & USB3_USB_CAP5_EPOUTI_N_MASK)
106929 #define USB3_USB_CAP5_EPINI_N_MASK               (0xFFFF0000U)
106930 #define USB3_USB_CAP5_EPINI_N_SHIFT              (16U)
106931 /*! EPINI_N - EPINI_N
106932  */
106933 #define USB3_USB_CAP5_EPINI_N(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP5_EPINI_N_SHIFT)) & USB3_USB_CAP5_EPINI_N_MASK)
106934 /*! @} */
106935 
106936 /*! @name USB_CAP6 - Device controller version */
106937 /*! @{ */
106938 #define USB3_USB_CAP6_VERSION_MASK               (0xFFFFFFFFU)
106939 #define USB3_USB_CAP6_VERSION_SHIFT              (0U)
106940 /*! VERSION - VERSION
106941  */
106942 #define USB3_USB_CAP6_VERSION(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP6_VERSION_SHIFT)) & USB3_USB_CAP6_VERSION_MASK)
106943 /*! @} */
106944 
106945 /*! @name USB_CPKT1 - Custom Packet value */
106946 /*! @{ */
106947 #define USB3_USB_CPKT1_CPKT1_MASK                (0xFFFFFFFFU)
106948 #define USB3_USB_CPKT1_CPKT1_SHIFT               (0U)
106949 /*! CPKT1 - CPKT1
106950  */
106951 #define USB3_USB_CPKT1_CPKT1(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CPKT1_CPKT1_SHIFT)) & USB3_USB_CPKT1_CPKT1_MASK)
106952 /*! @} */
106953 
106954 /*! @name USB_CPKT2 - Custom Packet value */
106955 /*! @{ */
106956 #define USB3_USB_CPKT2_CPKT2_MASK                (0xFFFFFFFFU)
106957 #define USB3_USB_CPKT2_CPKT2_SHIFT               (0U)
106958 /*! CPKT2 - CPKT2
106959  */
106960 #define USB3_USB_CPKT2_CPKT2(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CPKT2_CPKT2_SHIFT)) & USB3_USB_CPKT2_CPKT2_MASK)
106961 /*! @} */
106962 
106963 /*! @name USB_CPKT3 - Custom Packet value */
106964 /*! @{ */
106965 #define USB3_USB_CPKT3_CPKT3_MASK                (0xFFFFFFFFU)
106966 #define USB3_USB_CPKT3_CPKT3_SHIFT               (0U)
106967 /*! CPKT3 - CPKT3
106968  */
106969 #define USB3_USB_CPKT3_CPKT3(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CPKT3_CPKT3_SHIFT)) & USB3_USB_CPKT3_CPKT3_MASK)
106970 /*! @} */
106971 
106972 /*! @name CFG_REG1 - VBUS debouncer Configuration */
106973 /*! @{ */
106974 #define USB3_CFG_REG1_DEBOUNCER_CNT_MASK         (0x3FFFFU)
106975 #define USB3_CFG_REG1_DEBOUNCER_CNT_SHIFT        (0U)
106976 /*! DEBOUNCER_CNT - This parameter defines the VBUS debouncer delay i.e. the time interval between
106977  *    the VBUS detection on device input and the start of using it internally. Resolution of this
106978  *    parameter is 128 ns. For simulation purposes it is recommended to set the value 1 (128ns) For
106979  *    synthesis purposes it is recommended to set the value 230000 (~30ms)
106980  */
106981 #define USB3_CFG_REG1_DEBOUNCER_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG1_DEBOUNCER_CNT_SHIFT)) & USB3_CFG_REG1_DEBOUNCER_CNT_MASK)
106982 #define USB3_CFG_REG1_RESERVED_MASK              (0xFFFC0000U)
106983 #define USB3_CFG_REG1_RESERVED_SHIFT             (18U)
106984 /*! RESERVED - Reserved field. Write ignored. 0 when read
106985  */
106986 #define USB3_CFG_REG1_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG1_RESERVED_SHIFT)) & USB3_CFG_REG1_RESERVED_MASK)
106987 /*! @} */
106988 
106989 /*! @name DBG_LINK1 - Link */
106990 /*! @{ */
106991 #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_MASK (0xFFU)
106992 #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SHIFT (0U)
106993 /*! LFPS_MIN_DET_U1_EXIT - LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum time
106994  *    required for decoding the received LFPS as an LFPS.U1_Exit. Example is shown in the chapter 4.
106995  *    This field is saved to the device only when the field LFPS_MIN_DET_U1_EXIT_SET is set to '1'
106996  *    during write to the DBG_LINK1 register. Resolution of this parameter is 8 ns. For simulation
106997  *    purposes it is recommended to set the value 36 (~300ns). For synthesis purposes it is recommended
106998  *    to set the value 36 (~300ns)
106999  */
107000 #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_MASK)
107001 #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK (0xFF00U)
107002 #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SHIFT (8U)
107003 /*! LFPS_MIN_GEN_U1_EXIT - LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for
107004  *    phytxelecidle deassertion when LFPS.U1_Exit signalling is generated as shown in the chapter
107005  *    4. This field is saved to the device only when the field LFPS_MIN_GEN_U1_EXIT_SET is set to '1'
107006  *    during write to the DBG_LINK1 register. Resolution of this parameter is 8 ns. For simulation
107007  *    purposes it is recommended to set the value 87 (~696ns) For synthesis purposes it is
107008  *    recommended to set the value 87 (~696ns)
107009  */
107010 #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK)
107011 #define USB3_DBG_LINK1_RXDET_BREAK_DIS_MASK      (0x10000U)
107012 #define USB3_DBG_LINK1_RXDET_BREAK_DIS_SHIFT     (16U)
107013 /*! RXDET_BREAK_DIS - RXDET_BREAK_DIS value This parameter configures terminating the Far-end
107014  *    Receiver termination detection sequence: '0': it is possible that USBSS_DEV will terminate Far-end
107015  *    receiver termination detection sequence '1': USBSS_DEV will not terminate Far-end receiver
107016  *    termination detection sequence The impact of the bit to the link behaviour is shown in chapter 4.
107017  *    This field is saved to the device only when the field RXDET_BREAK_DIS_SET is set to '1' during
107018  *    write to the DBG_LINK1
107019  */
107020 #define USB3_DBG_LINK1_RXDET_BREAK_DIS(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RXDET_BREAK_DIS_SHIFT)) & USB3_DBG_LINK1_RXDET_BREAK_DIS_MASK)
107021 #define USB3_DBG_LINK1_LFPS_GEN_PING_MASK        (0x3E0000U)
107022 #define USB3_DBG_LINK1_LFPS_GEN_PING_SHIFT       (17U)
107023 /*! LFPS_GEN_PING - LFPS_GEN_PING value This parameter configures the LFPS.Ping generation time as
107024  *    shown in the chapter 4. This field is saved to the device only when the field LFPS_GEN_PING_SET
107025  *    is set to '1' during write to the DBG_LINK1 register. Resolution of this parameter is 8 ns.
107026  *    For simulation purposes it is recommended to set the value 24 (~200ns) For synthesis purposes
107027  *    it is recommended to set the value 24 (~200ns)
107028  */
107029 #define USB3_DBG_LINK1_LFPS_GEN_PING(x)          (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_GEN_PING_SHIFT)) & USB3_DBG_LINK1_LFPS_GEN_PING_MASK)
107030 #define USB3_DBG_LINK1_RESERVED0_MASK            (0xC00000U)
107031 #define USB3_DBG_LINK1_RESERVED0_SHIFT           (22U)
107032 /*! RESERVED0 - Reserved field. Write ignored. 0 when read
107033  */
107034 #define USB3_DBG_LINK1_RESERVED0(x)              (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RESERVED0_SHIFT)) & USB3_DBG_LINK1_RESERVED0_MASK)
107035 #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_MASK (0x1000000U)
107036 #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_SHIFT (24U)
107037 /*! LFPS_MIN_DET_U1_EXIT_SET - Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
107038  *    LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically cleared. Writing
107039  *    '0' has no effect
107040  */
107041 #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_MASK)
107042 #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_MASK (0x2000000U)
107043 #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_SHIFT (25U)
107044 /*! LFPS_MIN_GEN_U1_EXIT_SET - Set the LFPS_MIN_GEN_U1_EXIT value Writing '1' to this bit writes the
107045  *    LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically cleared. Writing
107046  *    '0' has no effect
107047  */
107048 #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_MASK)
107049 #define USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_MASK  (0x4000000U)
107050 #define USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_SHIFT (26U)
107051 /*! RXDET_BREAK_DIS_SET - Set the RXDET_BREAK_DIS value Writing '1' to this bit writes the
107052  *    RXDET_BREAK_DIS field value to the device. This bit is automatically cleared. Writing '0' has no effect
107053  */
107054 #define USB3_DBG_LINK1_RXDET_BREAK_DIS_SET(x)    (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_SHIFT)) & USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_MASK)
107055 #define USB3_DBG_LINK1_LFPS_GEN_PING_SET_MASK    (0x8000000U)
107056 #define USB3_DBG_LINK1_LFPS_GEN_PING_SET_SHIFT   (27U)
107057 /*! LFPS_GEN_PING_SET - Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes the
107058  *    LFPS_GEN_PING field value to the device. This bit is automatically cleared. Writing '0' has no effect
107059  */
107060 #define USB3_DBG_LINK1_LFPS_GEN_PING_SET(x)      (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_GEN_PING_SET_SHIFT)) & USB3_DBG_LINK1_LFPS_GEN_PING_SET_MASK)
107061 #define USB3_DBG_LINK1_RESERVED1_MASK            (0xF0000000U)
107062 #define USB3_DBG_LINK1_RESERVED1_SHIFT           (28U)
107063 /*! RESERVED1 - Reserved field. Write ignored. 0 when read
107064  */
107065 #define USB3_DBG_LINK1_RESERVED1(x)              (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RESERVED1_SHIFT)) & USB3_DBG_LINK1_RESERVED1_MASK)
107066 /*! @} */
107067 
107068 /*! @name DBG_LINK2 - Link */
107069 /*! @{ */
107070 #define USB3_DBG_LINK2_RXEQTR_AVAL_MASK          (0xFFU)
107071 #define USB3_DBG_LINK2_RXEQTR_AVAL_SHIFT         (0U)
107072 /*! RXEQTR_AVAL - Rxeqtraining assertion value This parameter configures phyrxeqtraining asserting
107073  *    time as shown in the chapter 4. This field is saved to the device only when the field
107074  *    RXEQTR_AVAL_SET is set to '1' during write to the DBG_LINK2
107075  */
107076 #define USB3_DBG_LINK2_RXEQTR_AVAL(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_AVAL_SHIFT)) & USB3_DBG_LINK2_RXEQTR_AVAL_MASK)
107077 #define USB3_DBG_LINK2_RXEQTR_DVAL_MASK          (0xFF00U)
107078 #define USB3_DBG_LINK2_RXEQTR_DVAL_SHIFT         (8U)
107079 /*! RXEQTR_DVAL - Rxeqtraining deassertion value This parameter configures phyrxeqtraining
107080  *    deasserting time as shown in the chapter 4. This field is saved to the device only when the field
107081  *    RXEQTR_DVAL_SET is set to '1' during write to the DBG_LINK2
107082  */
107083 #define USB3_DBG_LINK2_RXEQTR_DVAL(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_DVAL_SHIFT)) & USB3_DBG_LINK2_RXEQTR_DVAL_MASK)
107084 #define USB3_DBG_LINK2_PHYRXVAL_DVAL_MASK        (0xFF0000U)
107085 #define USB3_DBG_LINK2_PHYRXVAL_DVAL_SHIFT       (16U)
107086 /*! PHYRXVAL_DVAL - Phyrxvalid latency deassertion value This parameter enables extending internal
107087  *    phyrxdata and phyrxdatak validity as shown in the chapter 4. This field is saved to the device
107088  *    only when the field PHYRXVAL_DVAL_SET is set to '1' during write to the DBG_LINK2
107089  */
107090 #define USB3_DBG_LINK2_PHYRXVAL_DVAL(x)          (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_PHYRXVAL_DVAL_SHIFT)) & USB3_DBG_LINK2_PHYRXVAL_DVAL_MASK)
107091 #define USB3_DBG_LINK2_TXDET_DVAL_MASK           (0x7000000U)
107092 #define USB3_DBG_LINK2_TXDET_DVAL_SHIFT          (24U)
107093 /*! TXDET_DVAL - TXDET deassertion value This parameter configures the phytxdetrx_loop deassertion
107094  *    time after phystatus deassertion during Far-end receiver termination sequence as shown in the
107095  *    chapter 4. This field is saved to the device only when the field TXDET_DVAL_SET is set to '1'
107096  *    during write to the DBG_LINK2
107097  */
107098 #define USB3_DBG_LINK2_TXDET_DVAL(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_TXDET_DVAL_SHIFT)) & USB3_DBG_LINK2_TXDET_DVAL_MASK)
107099 #define USB3_DBG_LINK2_RESERVED_MASK             (0x8000000U)
107100 #define USB3_DBG_LINK2_RESERVED_SHIFT            (27U)
107101 /*! RESERVED - Reserved field. Write ignored. 0 when read
107102  */
107103 #define USB3_DBG_LINK2_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RESERVED_SHIFT)) & USB3_DBG_LINK2_RESERVED_MASK)
107104 #define USB3_DBG_LINK2_RXEQTR_AVAL_SET_MASK      (0x10000000U)
107105 #define USB3_DBG_LINK2_RXEQTR_AVAL_SET_SHIFT     (28U)
107106 /*! RXEQTR_AVAL_SET - Set the rxeqtraining assertion value Writing '1' to this bit writes the
107107  *    RXEQTR_AVAL field value to the device. This bit is automatically cleared. Writing '0' has no effect
107108  */
107109 #define USB3_DBG_LINK2_RXEQTR_AVAL_SET(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_AVAL_SET_SHIFT)) & USB3_DBG_LINK2_RXEQTR_AVAL_SET_MASK)
107110 #define USB3_DBG_LINK2_RXEQTR_DVAL_SET_MASK      (0x20000000U)
107111 #define USB3_DBG_LINK2_RXEQTR_DVAL_SET_SHIFT     (29U)
107112 /*! RXEQTR_DVAL_SET - Set the rxeqtraining deassertion value Writing '1' to this bit writes the
107113  *    RXEQTR_DVAL field value to the device. This bit is automatically cleared. Writing '0' has no effect
107114  */
107115 #define USB3_DBG_LINK2_RXEQTR_DVAL_SET(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_DVAL_SET_SHIFT)) & USB3_DBG_LINK2_RXEQTR_DVAL_SET_MASK)
107116 #define USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_MASK    (0x40000000U)
107117 #define USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_SHIFT   (30U)
107118 /*! PHYRXVAL_DVAL_SET - Set the Phyrxvalid latency deassertion value Writing '1' to this bit writes
107119  *    the PHYRXVAL_DVAL field value to the device. This bit is automatically cleared. Writing '0'
107120  *    has no effect.0
107121  */
107122 #define USB3_DBG_LINK2_PHYRXVAL_DVAL_SET(x)      (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_SHIFT)) & USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_MASK)
107123 #define USB3_DBG_LINK2_TXDET_DVAL_SET_MASK       (0x80000000U)
107124 #define USB3_DBG_LINK2_TXDET_DVAL_SET_SHIFT      (31U)
107125 /*! TXDET_DVAL_SET - Set the TXDET deassertion value Writing '1' to this bit writes the TXDET_DVAL
107126  *    field value to the device. This bit is automatically cleared. Writing '0' has no effect
107127  */
107128 #define USB3_DBG_LINK2_TXDET_DVAL_SET(x)         (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_TXDET_DVAL_SET_SHIFT)) & USB3_DBG_LINK2_TXDET_DVAL_SET_MASK)
107129 /*! @} */
107130 
107131 /*! @name CFG_REG4 - USB3 Configuration */
107132 /*! @{ */
107133 #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_MASK (0xFFU)
107134 #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_SHIFT (0U)
107135 /*! RXDETECT_QUIET_TIMEOUT - RXDETECT_QUIET_TIMEOUT value Resolution of this parameter is selected
107136  *    by RXDETECT_QUIET_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value:
107137  *    - 11*100us =~1ms (SystemC device ENV) - 13*1us =~12us (VIP based ENV) For synthesis purposes
107138  *    it is recommended to set the value 121*100us =~12ms
107139  */
107140 #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_SHIFT)) & USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_MASK)
107141 #define USB3_CFG_REG4_RESERVED_MASK              (0x3FFFFF00U)
107142 #define USB3_CFG_REG4_RESERVED_SHIFT             (8U)
107143 /*! RESERVED - Reserved field. Write ignored. 0 when read
107144  */
107145 #define USB3_CFG_REG4_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG4_RESERVED_SHIFT)) & USB3_CFG_REG4_RESERVED_MASK)
107146 #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107147 #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_SHIFT (30U)
107148 /*! RXDETECT_QUIET_TIMEOUT_PRESCALE - PRESCALER for RXDETECT_QUIET_TIMEOUT : - 0x0 : 8ns (PHY pclk
107149  *    clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107150  */
107151 #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_MASK)
107152 /*! @} */
107153 
107154 /*! @name CFG_REG5 - USB3 Configuration */
107155 /*! @{ */
107156 #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_MASK  (0x7FFU)
107157 #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_SHIFT (0U)
107158 /*! U3_HDSK_FAIL_TIMEOUT - U3_HDSK_FAIL_TIMEOUT value Resolution of this parameter is selected by
107159  *    U3_HDSK_FAIL_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: -
107160  *    11*100us =~1ms (SystemC device ENV) - 11*100us =~1ms (VIP based ENV) For synthesis purposes it is
107161  *    recommended to set the value 1001*100us =~100ms
107162  */
107163 #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_SHIFT)) & USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_MASK)
107164 #define USB3_CFG_REG5_RESERVED_MASK              (0x3FFFF800U)
107165 #define USB3_CFG_REG5_RESERVED_SHIFT             (11U)
107166 /*! RESERVED - Reserved field. Write ignored. 0 when read
107167  */
107168 #define USB3_CFG_REG5_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG5_RESERVED_SHIFT)) & USB3_CFG_REG5_RESERVED_MASK)
107169 #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107170 #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_SHIFT (30U)
107171 /*! U3_HDSK_FAIL_TIMEOUT_PRESCALE - PRESCALER for U3_HDSK_FAIL_TIMEOUT : - 0x0 : 8ns (PHY pclk
107172  *    clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107173  */
107174 #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_MASK)
107175 /*! @} */
107176 
107177 /*! @name CFG_REG6 - Configuration Register 6 */
107178 /*! @{ */
107179 #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_MASK (0xFFU)
107180 #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_SHIFT (0U)
107181 /*! SSINACTIVE_QUIET_TIMEOUT - SSINACTIVE_QUIET_TIMEOUT value Resolution of this parameter is
107182  *    selected by SSINACTIVE_QUIET_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the
107183  *    value: - 11*100us =~1ms (SystemC device ENV) - 13*1us =~12us (VIP based ENV) For synthesis
107184  *    purposes it is recommended to set the value: - 121*100us =~12ms
107185  */
107186 #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_SHIFT)) & USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_MASK)
107187 #define USB3_CFG_REG6_RESERVED_MASK              (0x3FFFFF00U)
107188 #define USB3_CFG_REG6_RESERVED_SHIFT             (8U)
107189 /*! RESERVED - Reserved field. Write ignored. 0 when read
107190  */
107191 #define USB3_CFG_REG6_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG6_RESERVED_SHIFT)) & USB3_CFG_REG6_RESERVED_MASK)
107192 #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107193 #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_SHIFT (30U)
107194 /*! SSINACTIVE_QUIET_TIMEOUT_PRESCALE - PRESCALER for SSINACTIVE_QUIET_TIMEOUT value: - 0x0 : 8ns
107195  *    (PHY pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107196  */
107197 #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_MASK)
107198 /*! @} */
107199 
107200 /*! @name CFG_REG7 - USB3 Configuration */
107201 /*! @{ */
107202 #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_MASK  (0x1FFFU)
107203 #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_SHIFT (0U)
107204 /*! POLLING_LFPS_TIMEOUT - POLLING_LFPS_TIMEOUT value Resolution of this parameter is selected by
107205  *    POLLING_LFPS_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: -
107206  *    11*100us =~1ms (SystemC device ENV) - 481*1us =~480us (VIP based ENV) For synthesis purposes it
107207  *    is recommended to set the value: - 3601*100us =~360ms
107208  */
107209 #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_SHIFT)) & USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_MASK)
107210 #define USB3_CFG_REG7_RESERVED_MASK              (0x3FFFE000U)
107211 #define USB3_CFG_REG7_RESERVED_SHIFT             (13U)
107212 /*! RESERVED - Reserved field. Write ignored. 0 when read
107213  */
107214 #define USB3_CFG_REG7_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG7_RESERVED_SHIFT)) & USB3_CFG_REG7_RESERVED_MASK)
107215 #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107216 #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_SHIFT (30U)
107217 /*! POLLING_LFPS_TIMEOUT_PRESCALE - PRESCALER for POLLING_LFPS_TIMEOUT value: - 0x0 : 8ns (PHY pclk
107218  *    clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107219  */
107220 #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_MASK)
107221 /*! @} */
107222 
107223 /*! @name CFG_REG8 - USB3 Configuration */
107224 /*! @{ */
107225 #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_MASK (0x3FFU)
107226 #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_SHIFT (0U)
107227 /*! POLLING_ACTIVE_TIMEOUT - POLLING_ACTIVE_TIMEOUT value Resolution of this parameter is selected
107228  *    by POLLING_ACTIVE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value:
107229  *    - 11*100us =~1ms (SystemC device ENV) - 31*1us =~30us (VIP based ENV) For synthesis purposes
107230  *    it is recommended to set the value: - 121*100us =~12ms
107231  */
107232 #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_SHIFT)) & USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_MASK)
107233 #define USB3_CFG_REG8_RESERVED_MASK              (0x3FFFFC00U)
107234 #define USB3_CFG_REG8_RESERVED_SHIFT             (10U)
107235 /*! RESERVED - Reserved field. Write ignored. 0 when read
107236  */
107237 #define USB3_CFG_REG8_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG8_RESERVED_SHIFT)) & USB3_CFG_REG8_RESERVED_MASK)
107238 #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107239 #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_SHIFT (30U)
107240 /*! POLLING_ACTIVE_TIMEOUT_PRESCALE - PRESCALER for POLLING_ACTIVE_TIMEOUT value: - 0x0 : 8ns (PHY
107241  *    pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107242  */
107243 #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_MASK)
107244 /*! @} */
107245 
107246 /*! @name CFG_REG9 - USB3 Configuration */
107247 /*! @{ */
107248 #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_MASK  (0x1FU)
107249 #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_SHIFT (0U)
107250 /*! POLLING_IDLE_TIMEOUT - POLLING_IDLE_TIMEOUT value Resolution of this parameter is selected by
107251  *    POLLING_IDLE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: -
107252  *    21*100us =~2ms (SystemC device ENV) - 3*1us =~2us (VIP based ENV) For synthesis purposes it is
107253  *    recommended to set the value: - 21*100us =~2ms
107254  */
107255 #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_SHIFT)) & USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_MASK)
107256 #define USB3_CFG_REG9_RESERVED_MASK              (0x3FFFFFE0U)
107257 #define USB3_CFG_REG9_RESERVED_SHIFT             (5U)
107258 /*! RESERVED - Reserved field. Write ignored. 0 when read
107259  */
107260 #define USB3_CFG_REG9_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG9_RESERVED_SHIFT)) & USB3_CFG_REG9_RESERVED_MASK)
107261 #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107262 #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_SHIFT (30U)
107263 /*! POLLING_IDLE_TIMEOUT_PRESCALE - PRESCALER for POLLING_IDLE_TIMEOUT value: - 0x0 : 8ns (PHY pclk
107264  *    clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107265  */
107266 #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_MASK)
107267 /*! @} */
107268 
107269 /*! @name CFG_REG10 - USB3 Configuration */
107270 /*! @{ */
107271 #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_MASK (0xFFU)
107272 #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_SHIFT (0U)
107273 /*! POLLING_CONF_TIMEOUT - POLLING_CONF_TIMEOUT value Resolution of this parameter is selected by
107274  *    POLLING_CONF_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: -
107275  *    11*100us =~1ms (SystemC device ENV) - 31*1us =~30us (VIP based ENV) For synthesis purposes it is
107276  *    recommended to set the value: - 121*100us =~12ms
107277  */
107278 #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG10_POLLING_CONF_TIMEOUT_SHIFT)) & USB3_CFG_REG10_POLLING_CONF_TIMEOUT_MASK)
107279 #define USB3_CFG_REG10_RESERVED_MASK             (0x3FFFFF00U)
107280 #define USB3_CFG_REG10_RESERVED_SHIFT            (8U)
107281 /*! RESERVED - Reserved field. Write ignored. 0 when read
107282  */
107283 #define USB3_CFG_REG10_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG10_RESERVED_SHIFT)) & USB3_CFG_REG10_RESERVED_MASK)
107284 #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107285 #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_SHIFT (30U)
107286 /*! POLLING_CONF_TIMEOUT_PRESCALE - PRESCALER for POLLING_CONF_TIMEOUT value: - 0x0 : 8ns (PHY pclk
107287  *    clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107288  */
107289 #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_MASK)
107290 /*! @} */
107291 
107292 /*! @name CFG_REG11 - USB3 Configuration */
107293 /*! @{ */
107294 #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_MASK (0xFFU)
107295 #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_SHIFT (0U)
107296 /*! RECOVERY_ACTIVE_TIMEOUT - RECOVERY_ACTIVE_TIMEOUT value Resolution of this parameter is selected
107297  *    by RECOVERY_ACTIVE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the
107298  *    value: - 11*100us =~1ms (SystemC device ENV) - 101*1us =~100us (VIP based ENV) For synthesis
107299  *    purposes it is recommended to set the value: - 121*100us =~12ms
107300  */
107301 #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_SHIFT)) & USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_MASK)
107302 #define USB3_CFG_REG11_RESERVED_MASK             (0x3FFFFF00U)
107303 #define USB3_CFG_REG11_RESERVED_SHIFT            (8U)
107304 /*! RESERVED - Reserved field. Write ignored. 0 when read
107305  */
107306 #define USB3_CFG_REG11_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG11_RESERVED_SHIFT)) & USB3_CFG_REG11_RESERVED_MASK)
107307 #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107308 #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_SHIFT (30U)
107309 /*! RECOVERY_ACTIVE_TIMEOUT_PRESCALE - PRESCALER for RECOVERY_ACTIVE_TIMEOUT value: - 0x0 : 8ns (PHY
107310  *    pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107311  */
107312 #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_MASK)
107313 /*! @} */
107314 
107315 /*! @name CFG_REG12 - USB3 Configuration */
107316 /*! @{ */
107317 #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_MASK (0xFFU)
107318 #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_SHIFT (0U)
107319 /*! RECOVERY_CONF_TIMEOUT - RECOVERY_CONF_TIMEOUT value Resolution of this parameter is selected by
107320  *    RECOVERY_CONF_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: -
107321  *    11*100us =~1ms (SystemC device ENV) - 101*1us =~100us (VIP based ENV) For synthesis purposes
107322  *    it is recommended to set the value: - 61*100us =~6ms
107323  */
107324 #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_SHIFT)) & USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_MASK)
107325 #define USB3_CFG_REG12_RESERVED_MASK             (0x3FFFFF00U)
107326 #define USB3_CFG_REG12_RESERVED_SHIFT            (8U)
107327 /*! RESERVED - Reserved field. Write ignored. 0 when read
107328  */
107329 #define USB3_CFG_REG12_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG12_RESERVED_SHIFT)) & USB3_CFG_REG12_RESERVED_MASK)
107330 #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107331 #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_SHIFT (30U)
107332 /*! RECOVERY_CONF_TIMEOUT_PRESCALE - PRESCALER for RECOVERY_CONF_TIMEOUT value: - 0x0 : 8ns (PHY
107333  *    pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107334  */
107335 #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_MASK)
107336 /*! @} */
107337 
107338 /*! @name CFG_REG13 - USB3 Configuration */
107339 /*! @{ */
107340 #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_MASK (0x1FU)
107341 #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_SHIFT (0U)
107342 /*! RECOVERY_IDLE_TIMEOUT - RECOVERY_IDLE_TIMEOUT value Resolution of this parameter is selected by
107343  *    RECOVERY_IDLE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: -
107344  *    21*100us =~2ms (SystemC device ENV) - 3*1us =~3us (VIP based ENV) For synthesis purposes it is
107345  *    recommended to set the value: - 21*100us =~2ms
107346  */
107347 #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_SHIFT)) & USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_MASK)
107348 #define USB3_CFG_REG13_RESERVED_MASK             (0xFFFFFE0U)
107349 #define USB3_CFG_REG13_RESERVED_SHIFT            (5U)
107350 /*! RESERVED - Reserved field. Write ignored. 0 when read
107351  */
107352 #define USB3_CFG_REG13_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG13_RESERVED_SHIFT)) & USB3_CFG_REG13_RESERVED_MASK)
107353 #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107354 #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_SHIFT (30U)
107355 /*! RECOVERY_IDLE_TIMEOUT_PRESCALE - PRESCALER for RECOVERY_IDLE_TIMEOUT value: - 0x0 : 8ns (PHY
107356  *    pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107357  */
107358 #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_MASK)
107359 /*! @} */
107360 
107361 /*! @name CFG_REG14 - USB3 Configuration */
107362 /*! @{ */
107363 #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_MASK (0xFFU)
107364 #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_SHIFT (0U)
107365 /*! HOTRESET_ACTIVE_TIMEOUT - HOTRESET_ACTIVE_TIMEOUT value Resolution of this parameter is selected
107366  *    by HOTRESET_ACTIVE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the
107367  *    value: - 21*100us =~2ms (SystemC device ENV) - 13*1us =~13us (VIP based ENV) For synthesis
107368  *    purposes it is recommended to set the value: - 121*100us =~12ms
107369  */
107370 #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_SHIFT)) & USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_MASK)
107371 #define USB3_CFG_REG14_RESERVED_MASK             (0x3FFFFF00U)
107372 #define USB3_CFG_REG14_RESERVED_SHIFT            (8U)
107373 /*! RESERVED - Reserved field. Write ignored. 0 when read
107374  */
107375 #define USB3_CFG_REG14_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG14_RESERVED_SHIFT)) & USB3_CFG_REG14_RESERVED_MASK)
107376 #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107377 #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_SHIFT (30U)
107378 /*! HOTRESET_ACTIVE_TIMEOUT_PRESCALE - PRESCALER for HOTRESET_ACTIVE_TIMEOUT value: - 0x0 : 8ns (PHY
107379  *    pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107380  */
107381 #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_MASK)
107382 /*! @} */
107383 
107384 /*! @name CFG_REG15 - USB3 Configuration */
107385 /*! @{ */
107386 #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_MASK (0x1FU)
107387 #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_SHIFT (0U)
107388 /*! HOTRESET_EXIT_TIMEOUT - HOTRESET_EXIT_TIMEOUT value Resolution of this parameter is selected by
107389  *    HOTRESET_EXIT_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: -
107390  *    21*100us =~2ms (SystemC device ENV) - 3*1us =~3us (VIP based ENV) For synthesis purposes it is
107391  *    recommended to set the value: - 21*100us =~2ms
107392  */
107393 #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_SHIFT)) & USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_MASK)
107394 #define USB3_CFG_REG15_RESERVED_MASK             (0x3FFFFFE0U)
107395 #define USB3_CFG_REG15_RESERVED_SHIFT            (5U)
107396 /*! RESERVED - Reserved field. Write ignored. 0 when read
107397  */
107398 #define USB3_CFG_REG15_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG15_RESERVED_SHIFT)) & USB3_CFG_REG15_RESERVED_MASK)
107399 #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107400 #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_SHIFT (30U)
107401 /*! HOTRESET_EXIT_TIMEOUT_PRESCALE - PRESCALER for HOTRESET_EXIT_TIMEOUT value: - 0x0 : 8ns (PHY
107402  *    pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107403  */
107404 #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_MASK)
107405 /*! @} */
107406 
107407 /*! @name CFG_REG16 - USB3 Configuration */
107408 /*! @{ */
107409 #define USB3_CFG_REG16_LFPS_PING_REPEAT_MASK     (0xFFFU)
107410 #define USB3_CFG_REG16_LFPS_PING_REPEAT_SHIFT    (0U)
107411 /*! LFPS_PING_REPEAT - LFPS_PING_REPEAT value Resolution of this parameter is selected by
107412  *    LFPS_PING_REPEAT_PRESCALE. For simulation purposes it is recommended to set the value: - 6*100us =~0.5ms
107413  *    (SystemC device ENV) - 4*100us =~400us (VIP based ENV) For synthesis purposes it is
107414  *    recommended to set the value: - 2001*100us =~200ms
107415  */
107416 #define USB3_CFG_REG16_LFPS_PING_REPEAT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG16_LFPS_PING_REPEAT_SHIFT)) & USB3_CFG_REG16_LFPS_PING_REPEAT_MASK)
107417 #define USB3_CFG_REG16_RESERVED_MASK             (0x3FFFF000U)
107418 #define USB3_CFG_REG16_RESERVED_SHIFT            (12U)
107419 /*! RESERVED - Reserved field. Write ignored. 0 when read
107420  */
107421 #define USB3_CFG_REG16_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG16_RESERVED_SHIFT)) & USB3_CFG_REG16_RESERVED_MASK)
107422 #define USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_MASK (0xC0000000U)
107423 #define USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_SHIFT (30U)
107424 /*! LFPS_PING_REPEAT_PRESCALE - PRESCALER for LFPS_PING_REPEAT value: - 0x0 : 8ns (PHY pclk clock) -
107425  *    0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107426  */
107427 #define USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_SHIFT)) & USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_MASK)
107428 /*! @} */
107429 
107430 /*! @name CFG_REG17 - USB3 Configuration */
107431 /*! @{ */
107432 #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_MASK   (0x3FFU)
107433 #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_SHIFT  (0U)
107434 /*! PENDING_HP_TIMEOUT - PENDING_HP_TIMEOUT value Resolution of this parameter is selected by
107435  *    PENDING_HP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 437*8ns
107436  *    =~3.5us (SystemC device ENV) - 437*8ns =~3.5us (VIP based ENV) For synthesis purposes it is
107437  *    recommended to set the value: - 437*8ns =~3.5us
107438  */
107439 #define USB3_CFG_REG17_PENDING_HP_TIMEOUT(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG17_PENDING_HP_TIMEOUT_SHIFT)) & USB3_CFG_REG17_PENDING_HP_TIMEOUT_MASK)
107440 #define USB3_CFG_REG17_RESERVED_MASK             (0x3FFFFC00U)
107441 #define USB3_CFG_REG17_RESERVED_SHIFT            (10U)
107442 /*! RESERVED - Reserved field. Write ignored. 0 when read
107443  */
107444 #define USB3_CFG_REG17_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG17_RESERVED_SHIFT)) & USB3_CFG_REG17_RESERVED_MASK)
107445 #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107446 #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_SHIFT (30U)
107447 /*! PENDING_HP_TIMEOUT_PRESCALE - PRESCALER for PENDING_HP_TIMEOUT value: - 0x0 : 8ns (PHY pclk
107448  *    clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107449  */
107450 #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_MASK)
107451 /*! @} */
107452 
107453 /*! @name CFG_REG18 - USB3 Configuration */
107454 /*! @{ */
107455 #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_MASK    (0x7FU)
107456 #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_SHIFT   (0U)
107457 /*! CREDIT_HP_TIMEOUT - CREDIT_HP_TIMEOUT value Resolution of this parameter is selected by
107458  *    CREDIT_HP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us
107459  *    =~1ms (SystemC device ENV) - 11*100us =~1ms (VIP based ENV) For synthesis purposes it is
107460  *    recommended to set the value: - 52*100us =~5.1ms
107461  */
107462 #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG18_CREDIT_HP_TIMEOUT_SHIFT)) & USB3_CFG_REG18_CREDIT_HP_TIMEOUT_MASK)
107463 #define USB3_CFG_REG18_RESERVED_MASK             (0x3FFFFF80U)
107464 #define USB3_CFG_REG18_RESERVED_SHIFT            (7U)
107465 /*! RESERVED - Reserved field. Write ignored. 0 when read
107466  */
107467 #define USB3_CFG_REG18_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG18_RESERVED_SHIFT)) & USB3_CFG_REG18_RESERVED_MASK)
107468 #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107469 #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_SHIFT (30U)
107470 /*! CREDIT_HP_TIMEOUT_PRESCALE - PRESCALER for CREDIT_HP_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock)
107471  *    - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107472  */
107473 #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_MASK)
107474 /*! @} */
107475 
107476 /*! @name CFG_REG19 - USB3 Configuration */
107477 /*! @{ */
107478 #define USB3_CFG_REG19_LUP_TIMEOUT_MASK          (0x3FFU)
107479 #define USB3_CFG_REG19_LUP_TIMEOUT_SHIFT         (0U)
107480 /*! LUP_TIMEOUT - LUP_TIMEOUT value Resolution of this parameter is selected by
107481  *    LUP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*1us =~11us (SystemC device
107482  *    ENV) - 11*1us =~11us (VIP based ENV) For synthesis purposes it is recommended to set the
107483  *    value: - 11*1us =~11us
107484  */
107485 #define USB3_CFG_REG19_LUP_TIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG19_LUP_TIMEOUT_SHIFT)) & USB3_CFG_REG19_LUP_TIMEOUT_MASK)
107486 #define USB3_CFG_REG19_RESERVED_MASK             (0x3FFFFC00U)
107487 #define USB3_CFG_REG19_RESERVED_SHIFT            (10U)
107488 /*! RESERVED - Reserved field. Write ignored. 0 when read
107489  */
107490 #define USB3_CFG_REG19_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG19_RESERVED_SHIFT)) & USB3_CFG_REG19_RESERVED_MASK)
107491 #define USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107492 #define USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_SHIFT (30U)
107493 /*! LUP_TIMEOUT_PRESCALE - PRESCALER for LUP_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) - 0x1 : 1us
107494  *    - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107495  */
107496 #define USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_MASK)
107497 /*! @} */
107498 
107499 /*! @name CFG_REG20 - USB3 Configuration */
107500 /*! @{ */
107501 #define USB3_CFG_REG20_LDN_TIMEOUT_MASK          (0xFFU)
107502 #define USB3_CFG_REG20_LDN_TIMEOUT_SHIFT         (0U)
107503 /*! LDN_TIMEOUT - LDN_TIMEOUT value Resolution of this parameter is selected by
107504  *    LDN_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms (SystemC device
107505  *    ENV) - 129*1us =~129us (VIP based ENV) For synthesis purposes it is recommended to set the
107506  *    value: - 11*100us =~1ms
107507  */
107508 #define USB3_CFG_REG20_LDN_TIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG20_LDN_TIMEOUT_SHIFT)) & USB3_CFG_REG20_LDN_TIMEOUT_MASK)
107509 #define USB3_CFG_REG20_RESERVED_MASK             (0x3FFFFF00U)
107510 #define USB3_CFG_REG20_RESERVED_SHIFT            (8U)
107511 /*! RESERVED - Reserved field. Write ignored. 0 when read
107512  */
107513 #define USB3_CFG_REG20_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG20_RESERVED_SHIFT)) & USB3_CFG_REG20_RESERVED_MASK)
107514 #define USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107515 #define USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_SHIFT (30U)
107516 /*! LDN_TIMEOUT_PRESCALE - PRESCALER for LDN_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) - 0x1 : 1us
107517  *    - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107518  */
107519 #define USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_MASK)
107520 /*! @} */
107521 
107522 /*! @name CFG_REG21 - USB3 Configuration */
107523 /*! @{ */
107524 #define USB3_CFG_REG21_PM_LC_TIMEOUT_MASK        (0x3FFU)
107525 #define USB3_CFG_REG21_PM_LC_TIMEOUT_SHIFT       (0U)
107526 /*! PM_LC_TIMEOUT - PM_LC_TIMEOUT value Resolution of this parameter is selected by
107527  *    PM_LC_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 400*8ns =~3.2us (SystemC
107528  *    device ENV) - 400*8ns =~3.2us (VIP based ENV) For synthesis purposes it is recommended to set
107529  *    the value: - 400*8ns =~3.2us
107530  */
107531 #define USB3_CFG_REG21_PM_LC_TIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG21_PM_LC_TIMEOUT_SHIFT)) & USB3_CFG_REG21_PM_LC_TIMEOUT_MASK)
107532 #define USB3_CFG_REG21_RESERVED_MASK             (0x3FFFFC00U)
107533 #define USB3_CFG_REG21_RESERVED_SHIFT            (10U)
107534 /*! RESERVED - Reserved field. Write ignored. 0 when read
107535  */
107536 #define USB3_CFG_REG21_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG21_RESERVED_SHIFT)) & USB3_CFG_REG21_RESERVED_MASK)
107537 #define USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107538 #define USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_SHIFT (30U)
107539 /*! PM_LC_TIMEOUT_PRESCALE - PRESCALER for PM_LC_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) - 0x1 :
107540  *    1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107541  */
107542 #define USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_MASK)
107543 /*! @} */
107544 
107545 /*! @name CFG_REG22 - USB3 Configuration */
107546 /*! @{ */
107547 #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_MASK     (0x7FFU)
107548 #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_SHIFT    (0U)
107549 /*! PM_ENTRY_TIMEOUT - PM_ENTRY_TIMEOUT value Resolution of this parameter is selected by
107550  *    PM_ENTRY_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 800*8ns =~6.4us
107551  *    (SystemC device ENV) - 800*8ns =~6.4us (VIP based ENV) For synthesis purposes it is
107552  *    recommended to set the value: - 800*8ns =~6.4us
107553  */
107554 #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG22_PM_ENTRY_TIMEOUT_SHIFT)) & USB3_CFG_REG22_PM_ENTRY_TIMEOUT_MASK)
107555 #define USB3_CFG_REG22_RESERVED_MASK             (0x3FFFF800U)
107556 #define USB3_CFG_REG22_RESERVED_SHIFT            (11U)
107557 /*! RESERVED - Reserved field. Write ignored. 0 when read
107558  */
107559 #define USB3_CFG_REG22_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG22_RESERVED_SHIFT)) & USB3_CFG_REG22_RESERVED_MASK)
107560 #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107561 #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_SHIFT (30U)
107562 /*! PM_ENTRY_TIMEOUT_PRESCALE - PRESCALER for PM_ENTRY_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) -
107563  *    0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107564  */
107565 #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_MASK)
107566 /*! @} */
107567 
107568 /*! @name CFG_REG23 - USB3 Configuration */
107569 /*! @{ */
107570 #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_MASK      (0x7FU)
107571 #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_SHIFT     (0U)
107572 /*! UX_EXIT_TIMEOUT - UX_EXIT_TIMEOUT value Resolution of this parameter is selected by
107573  *    UX_EXIT_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 8*100us =~800us
107574  *    (SystemC device ENV) - 3*100us =~300us (VIP based ENV) For synthesis purposes it is recommended
107575  *    to set the value: - 62*100us =~6.2ms
107576  */
107577 #define USB3_CFG_REG23_UX_EXIT_TIMEOUT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG23_UX_EXIT_TIMEOUT_SHIFT)) & USB3_CFG_REG23_UX_EXIT_TIMEOUT_MASK)
107578 #define USB3_CFG_REG23_RESERVED_MASK             (0x3FFFFF80U)
107579 #define USB3_CFG_REG23_RESERVED_SHIFT            (7U)
107580 /*! RESERVED - Reserved field. Write ignored. 0 when read
107581  */
107582 #define USB3_CFG_REG23_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG23_RESERVED_SHIFT)) & USB3_CFG_REG23_RESERVED_MASK)
107583 #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107584 #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_SHIFT (30U)
107585 /*! UX_EXIT_TIMEOUT_PRESCALE - PRESCALER for UX_EXIT_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) -
107586  *    0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107587  */
107588 #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_MASK)
107589 /*! @} */
107590 
107591 /*! @name CFG_REG24 - USB3 Configuration */
107592 /*! @{ */
107593 #define USB3_CFG_REG24_LFPS_DET_RESET_MIN_MASK   (0x7FFFFFU)
107594 #define USB3_CFG_REG24_LFPS_DET_RESET_MIN_SHIFT  (0U)
107595 /*! LFPS_DET_RESET_MIN - LFPS_DET_RESET_MIN value Resolution of this parameter is 8 ns. For
107596  *    simulation purposes it is recommended to set the value 395833 (~3.16ms) For synthesis purposes it is
107597  *    recommended to set the value 2375000 (~19ms)
107598  */
107599 #define USB3_CFG_REG24_LFPS_DET_RESET_MIN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG24_LFPS_DET_RESET_MIN_SHIFT)) & USB3_CFG_REG24_LFPS_DET_RESET_MIN_MASK)
107600 #define USB3_CFG_REG24_RESERVED_MASK             (0xFF800000U)
107601 #define USB3_CFG_REG24_RESERVED_SHIFT            (23U)
107602 /*! RESERVED - Reserved field. Write ignored. 0 when read
107603  */
107604 #define USB3_CFG_REG24_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG24_RESERVED_SHIFT)) & USB3_CFG_REG24_RESERVED_MASK)
107605 /*! @} */
107606 
107607 /*! @name CFG_REG25 - USB3 Configuration */
107608 /*! @{ */
107609 #define USB3_CFG_REG25_LFPS_DET_RESET_MAX_MASK   (0xFFFFFFU)
107610 #define USB3_CFG_REG25_LFPS_DET_RESET_MAX_SHIFT  (0U)
107611 /*! LFPS_DET_RESET_MAX - LFPS_DET_RESET_MAX value Resolution of this parameter is 8 ns. For
107612  *    simulation purposes it is recommended to set the value 5000000 (~40ms) For synthesis purposes it is
107613  *    recommended to set the value 15000000 (~120ms)
107614  */
107615 #define USB3_CFG_REG25_LFPS_DET_RESET_MAX(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG25_LFPS_DET_RESET_MAX_SHIFT)) & USB3_CFG_REG25_LFPS_DET_RESET_MAX_MASK)
107616 #define USB3_CFG_REG25_RESERVED_MASK             (0xFF000000U)
107617 #define USB3_CFG_REG25_RESERVED_SHIFT            (24U)
107618 /*! RESERVED - Reserved field. Write ignored. 0 when read
107619  */
107620 #define USB3_CFG_REG25_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG25_RESERVED_SHIFT)) & USB3_CFG_REG25_RESERVED_MASK)
107621 /*! @} */
107622 
107623 /*! @name CFG_REG26 - USB3 Configuration */
107624 /*! @{ */
107625 #define USB3_CFG_REG26_LFPS_DET_POLLING_MIN_MASK (0x7FU)
107626 #define USB3_CFG_REG26_LFPS_DET_POLLING_MIN_SHIFT (0U)
107627 /*! LFPS_DET_POLLING_MIN - LFPS_DET_POLLING_MIN value Resolution of this parameter is 8 ns. For
107628  *    simulation purposes it is recommended to set the value 75 (~0.6us) For synthesis purposes it is
107629  *    recommended to set the value 75 (~0.6us)
107630  */
107631 #define USB3_CFG_REG26_LFPS_DET_POLLING_MIN(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG26_LFPS_DET_POLLING_MIN_SHIFT)) & USB3_CFG_REG26_LFPS_DET_POLLING_MIN_MASK)
107632 #define USB3_CFG_REG26_RESERVED_MASK             (0xFFFFFF80U)
107633 #define USB3_CFG_REG26_RESERVED_SHIFT            (7U)
107634 /*! RESERVED - Reserved field. Write ignored. 0 when read
107635  */
107636 #define USB3_CFG_REG26_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG26_RESERVED_SHIFT)) & USB3_CFG_REG26_RESERVED_MASK)
107637 /*! @} */
107638 
107639 /*! @name CFG_REG27 - USB3 Configuration */
107640 /*! @{ */
107641 #define USB3_CFG_REG27_LFPS_DET_POLLING_MAX_MASK (0xFFU)
107642 #define USB3_CFG_REG27_LFPS_DET_POLLING_MAX_SHIFT (0U)
107643 /*! LFPS_DET_POLLING_MAX - LFPS_DET_POLLING_MAX value Resolution of this parameter is 8 ns. For
107644  *    simulation purposes it is recommended to set the value 175 (~1.4us) For synthesis purposes it is
107645  *    recommended to set the value 175 (~1.4us)
107646  */
107647 #define USB3_CFG_REG27_LFPS_DET_POLLING_MAX(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG27_LFPS_DET_POLLING_MAX_SHIFT)) & USB3_CFG_REG27_LFPS_DET_POLLING_MAX_MASK)
107648 #define USB3_CFG_REG27_RESERVED_MASK             (0xFFFFFF00U)
107649 #define USB3_CFG_REG27_RESERVED_SHIFT            (8U)
107650 /*! RESERVED - Reserved field. Write ignored. 0 when read
107651  */
107652 #define USB3_CFG_REG27_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG27_RESERVED_SHIFT)) & USB3_CFG_REG27_RESERVED_MASK)
107653 /*! @} */
107654 
107655 /*! @name CFG_REG28 - USB3 Configuration */
107656 /*! @{ */
107657 #define USB3_CFG_REG28_LFPS_DET_PING_MIN_MASK    (0x7U)
107658 #define USB3_CFG_REG28_LFPS_DET_PING_MIN_SHIFT   (0U)
107659 /*! LFPS_DET_PING_MIN - LFPS_DET_PING_MIN value Resolution of this parameter is 8 ns. For simulation
107660  *    purposes it is recommended to set the value 4 (~40ns) For synthesis purposes it is
107661  *    recommended to set the value 4 (~40ns)
107662  */
107663 #define USB3_CFG_REG28_LFPS_DET_PING_MIN(x)      (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG28_LFPS_DET_PING_MIN_SHIFT)) & USB3_CFG_REG28_LFPS_DET_PING_MIN_MASK)
107664 #define USB3_CFG_REG28_RESERVED_MASK             (0xFFFFFFF8U)
107665 #define USB3_CFG_REG28_RESERVED_SHIFT            (3U)
107666 /*! RESERVED - Reserved field. Write ignored. 0 when read
107667  */
107668 #define USB3_CFG_REG28_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG28_RESERVED_SHIFT)) & USB3_CFG_REG28_RESERVED_MASK)
107669 /*! @} */
107670 
107671 /*! @name CFG_REG29 - USB3 Configuration */
107672 /*! @{ */
107673 #define USB3_CFG_REG29_LFPS_DET_PING_MAX_MASK    (0x1FU)
107674 #define USB3_CFG_REG29_LFPS_DET_PING_MAX_SHIFT   (0U)
107675 /*! LFPS_DET_PING_MAX - LFPS_DET_PING_MAX value Resolution of this parameter is 8 ns. For simulation
107676  *    purposes it is recommended to set the value 23 (~200ns) For synthesis purposes it is
107677  *    recommended to set the value 23 (~200ns)
107678  */
107679 #define USB3_CFG_REG29_LFPS_DET_PING_MAX(x)      (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG29_LFPS_DET_PING_MAX_SHIFT)) & USB3_CFG_REG29_LFPS_DET_PING_MAX_MASK)
107680 #define USB3_CFG_REG29_RESERVED_MASK             (0xFFFFFFE0U)
107681 #define USB3_CFG_REG29_RESERVED_SHIFT            (5U)
107682 /*! RESERVED - Reserved field. Write ignored. 0 when read
107683  */
107684 #define USB3_CFG_REG29_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG29_RESERVED_SHIFT)) & USB3_CFG_REG29_RESERVED_MASK)
107685 /*! @} */
107686 
107687 /*! @name CFG_REG30 - USB3 Configuration */
107688 /*! @{ */
107689 #define USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_MASK  (0x3FU)
107690 #define USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_SHIFT (0U)
107691 /*! LFPS_DET_U1EXIT_MIN - LFPS_DET_U1EXIT_MIN value Resolution of this parameter is 8 ns. For
107692  *    simulation purposes it is recommended to set the value 36 (~300ns) For synthesis purposes it is
107693  *    recommended to set the value 36 (~300ns)
107694  */
107695 #define USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_SHIFT)) & USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_MASK)
107696 #define USB3_CFG_REG30_RESERVED_MASK             (0xFFFFFFC0U)
107697 #define USB3_CFG_REG30_RESERVED_SHIFT            (6U)
107698 /*! RESERVED - Reserved field. Write ignored. 0 when read
107699  */
107700 #define USB3_CFG_REG30_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG30_RESERVED_SHIFT)) & USB3_CFG_REG30_RESERVED_MASK)
107701 /*! @} */
107702 
107703 /*! @name CFG_REG31 - USB3 Configuration */
107704 /*! @{ */
107705 #define USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_MASK  (0x7FU)
107706 #define USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_SHIFT (0U)
107707 /*! LFPS_DET_U1EXIT_MAX - LFPS_DET_U1EXIT_MAX value Resolution of this parameter is 8 ns. For
107708  *    simulation purposes it is recommended to set the value 111 (~900ns) For synthesis purposes it is
107709  *    recommended to set the value 111 (~900ns)
107710  */
107711 #define USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_SHIFT)) & USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_MASK)
107712 #define USB3_CFG_REG31_RESERVED_MASK             (0xFFFFFF80U)
107713 #define USB3_CFG_REG31_RESERVED_SHIFT            (7U)
107714 /*! RESERVED - Reserved field. Write ignored. 0 when read
107715  */
107716 #define USB3_CFG_REG31_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG31_RESERVED_SHIFT)) & USB3_CFG_REG31_RESERVED_MASK)
107717 /*! @} */
107718 
107719 /*! @name CFG_REG32 - USB3 Configuration */
107720 /*! @{ */
107721 #define USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_MASK  (0x3FU)
107722 #define USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_SHIFT (0U)
107723 /*! LFPS_DET_U2EXIT_MIN - LFPS_DET_U2EXIT_MIN value Resolution of this parameter is 8 ns. For
107724  *    simulation purposes it is recommended to set the value 36 (~300ns) For synthesis purposes it is
107725  *    recommended to set the value 36 (~300ns)
107726  */
107727 #define USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_SHIFT)) & USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_MASK)
107728 #define USB3_CFG_REG32_RESERVED_MASK             (0xFFFFFFC0U)
107729 #define USB3_CFG_REG32_RESERVED_SHIFT            (6U)
107730 /*! RESERVED - Reserved field. Write ignored. 0 when read
107731  */
107732 #define USB3_CFG_REG32_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG32_RESERVED_SHIFT)) & USB3_CFG_REG32_RESERVED_MASK)
107733 /*! @} */
107734 
107735 /*! @name CFG_REG33 - USB3 Configuration */
107736 /*! @{ */
107737 #define USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_MASK  (0x3FFFFU)
107738 #define USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_SHIFT (0U)
107739 /*! LFPS_DET_U2EXIT_MAX - LFPS_DET_U2EXIT_MAX value Resolution of this parameter is 8 ns. For
107740  *    simulation purposes it is recommended to set the value 250000 (~2ms) For synthesis purposes it is
107741  *    recommended to set the value 250000 (~2ms)
107742  */
107743 #define USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_SHIFT)) & USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_MASK)
107744 #define USB3_CFG_REG33_RESERVED_MASK             (0xFFFC0000U)
107745 #define USB3_CFG_REG33_RESERVED_SHIFT            (18U)
107746 /*! RESERVED - Reserved field. Write ignored. 0 when read
107747  */
107748 #define USB3_CFG_REG33_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG33_RESERVED_SHIFT)) & USB3_CFG_REG33_RESERVED_MASK)
107749 /*! @} */
107750 
107751 /*! @name CFG_REG34 - USB3 Configuration */
107752 /*! @{ */
107753 #define USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_MASK  (0x3FU)
107754 #define USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_SHIFT (0U)
107755 /*! LFPS_DET_U3EXIT_MIN - LFPS_DET_U3EXIT_MIN value Resolution of this parameter is 8 ns. For
107756  *    simulation purposes it is recommended to set the value 36 (~300ns) For synthesis purposes it is
107757  *    recommended to set the value 36 (~300ns)
107758  */
107759 #define USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_SHIFT)) & USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_MASK)
107760 #define USB3_CFG_REG34_RESERVED_MASK             (0xFFFFFFC0U)
107761 #define USB3_CFG_REG34_RESERVED_SHIFT            (6U)
107762 /*! RESERVED - Reserved field. Write ignored. 0 when read
107763  */
107764 #define USB3_CFG_REG34_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG34_RESERVED_SHIFT)) & USB3_CFG_REG34_RESERVED_MASK)
107765 /*! @} */
107766 
107767 /*! @name CFG_REG35 - USB3 Configuration */
107768 /*! @{ */
107769 #define USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_MASK  (0x1FFFFFU)
107770 #define USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_SHIFT (0U)
107771 /*! LFPS_DET_U3EXIT_MAX - LFPS_DET_U3EXIT_MAX value Resolution of this parameter is 8 ns. For
107772  *    simulation purposes it is recommended to set the value 1250000 (~10ms) For synthesis purposes it is
107773  *    recommended to set the value 1250000 (~10ms)
107774  */
107775 #define USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_SHIFT)) & USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_MASK)
107776 #define USB3_CFG_REG35_RESERVED_MASK             (0xFFE00000U)
107777 #define USB3_CFG_REG35_RESERVED_SHIFT            (21U)
107778 /*! RESERVED - Reserved field. Write ignored. 0 when read
107779  */
107780 #define USB3_CFG_REG35_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG35_RESERVED_SHIFT)) & USB3_CFG_REG35_RESERVED_MASK)
107781 /*! @} */
107782 
107783 /*! @name CFG_REG36 - USB3 Configuration */
107784 /*! @{ */
107785 #define USB3_CFG_REG36_LFPS_GEN_PING_MASK        (0x1FU)
107786 #define USB3_CFG_REG36_LFPS_GEN_PING_SHIFT       (0U)
107787 /*! LFPS_GEN_PING - LFPS_GEN_PING value Resolution of this parameter is 8 ns. For simulation
107788  *    purposes it is recommended to set the value 24 (~200ns) For synthesis purposes it is recommended to
107789  *    set the value 24 (~200ns)
107790  */
107791 #define USB3_CFG_REG36_LFPS_GEN_PING(x)          (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG36_LFPS_GEN_PING_SHIFT)) & USB3_CFG_REG36_LFPS_GEN_PING_MASK)
107792 #define USB3_CFG_REG36_RESERVED_MASK             (0xFFFFFFE0U)
107793 #define USB3_CFG_REG36_RESERVED_SHIFT            (5U)
107794 /*! RESERVED - Reserved field. Write ignored. 0 when read
107795  */
107796 #define USB3_CFG_REG36_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG36_RESERVED_SHIFT)) & USB3_CFG_REG36_RESERVED_MASK)
107797 /*! @} */
107798 
107799 /*! @name CFG_REG37 - USB3 Configuration */
107800 /*! @{ */
107801 #define USB3_CFG_REG37_LFPS_GEN_POLLING_MASK     (0xFFU)
107802 #define USB3_CFG_REG37_LFPS_GEN_POLLING_SHIFT    (0U)
107803 /*! LFPS_GEN_POLLING - LFPS_GEN_POLLING value Resolution of this parameter is 8 ns. For simulation
107804  *    purposes it is recommended to set the value 125 (~1us) For synthesis purposes it is recommended
107805  *    to set the value 125 (~1us)
107806  */
107807 #define USB3_CFG_REG37_LFPS_GEN_POLLING(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG37_LFPS_GEN_POLLING_SHIFT)) & USB3_CFG_REG37_LFPS_GEN_POLLING_MASK)
107808 #define USB3_CFG_REG37_RESERVED_MASK             (0xFFFFFF00U)
107809 #define USB3_CFG_REG37_RESERVED_SHIFT            (8U)
107810 /*! RESERVED - Reserved field. Write ignored. 0 when read
107811  */
107812 #define USB3_CFG_REG37_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG37_RESERVED_SHIFT)) & USB3_CFG_REG37_RESERVED_MASK)
107813 /*! @} */
107814 
107815 /*! @name CFG_REG38 - USB3 Configuration */
107816 /*! @{ */
107817 #define USB3_CFG_REG38_LFPS_GEN_U1EXIT_MASK      (0x3FFFFU)
107818 #define USB3_CFG_REG38_LFPS_GEN_U1EXIT_SHIFT     (0U)
107819 /*! LFPS_GEN_U1EXIT - LFPS_GEN_U1EXIT value Resolution of this parameter is 8 ns. For simulation
107820  *    purposes it is recommended to set the value 62500 (~500us) For synthesis purposes it is
107821  *    recommended to set the value 250000 (~2ms)
107822  */
107823 #define USB3_CFG_REG38_LFPS_GEN_U1EXIT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG38_LFPS_GEN_U1EXIT_SHIFT)) & USB3_CFG_REG38_LFPS_GEN_U1EXIT_MASK)
107824 #define USB3_CFG_REG38_RESERVED_MASK             (0xFFFC0000U)
107825 #define USB3_CFG_REG38_RESERVED_SHIFT            (18U)
107826 /*! RESERVED - Reserved field. Write ignored. 0 when read
107827  */
107828 #define USB3_CFG_REG38_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG38_RESERVED_SHIFT)) & USB3_CFG_REG38_RESERVED_MASK)
107829 /*! @} */
107830 
107831 /*! @name CFG_REG39 - USB3 Configuration */
107832 /*! @{ */
107833 #define USB3_CFG_REG39_LFPS_GEN_U3EXIT_MASK      (0x1FFFFFU)
107834 #define USB3_CFG_REG39_LFPS_GEN_U3EXIT_SHIFT     (0U)
107835 /*! LFPS_GEN_U3EXIT - LFPS_GEN_U3EXIT value Resolution of this parameter is 8 ns. For simulation
107836  *    purposes it is recommended to set the value 125000 (~1ms) For synthesis purposes it is
107837  *    recommended to set the value 1250000 (~10ms)
107838  */
107839 #define USB3_CFG_REG39_LFPS_GEN_U3EXIT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG39_LFPS_GEN_U3EXIT_SHIFT)) & USB3_CFG_REG39_LFPS_GEN_U3EXIT_MASK)
107840 #define USB3_CFG_REG39_RESERVED_MASK             (0xFFE00000U)
107841 #define USB3_CFG_REG39_RESERVED_SHIFT            (21U)
107842 /*! RESERVED - Reserved field. Write ignored. 0 when read
107843  */
107844 #define USB3_CFG_REG39_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG39_RESERVED_SHIFT)) & USB3_CFG_REG39_RESERVED_MASK)
107845 /*! @} */
107846 
107847 /*! @name CFG_REG40 - USB3 Configuration */
107848 /*! @{ */
107849 #define USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_MASK  (0x7FU)
107850 #define USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_SHIFT (0U)
107851 /*! LFPS_MIN_GEN_U1EXIT - LFPS_MIN_GEN_U1EXIT value Resolution of this parameter is 8 ns. For
107852  *    simulation purposes it is recommended to set the value 87 (~696ns) For synthesis purposes it is
107853  *    recommended to set the value 87 (~696ns)
107854  */
107855 #define USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_SHIFT)) & USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_MASK)
107856 #define USB3_CFG_REG40_RESERVED_MASK             (0xFFFFFF80U)
107857 #define USB3_CFG_REG40_RESERVED_SHIFT            (7U)
107858 /*! RESERVED - Reserved field. Write ignored. 0 when read
107859  */
107860 #define USB3_CFG_REG40_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG40_RESERVED_SHIFT)) & USB3_CFG_REG40_RESERVED_MASK)
107861 /*! @} */
107862 
107863 /*! @name CFG_REG41 - USB3 Configuration */
107864 /*! @{ */
107865 #define USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_MASK  (0x7FFFU)
107866 #define USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_SHIFT (0U)
107867 /*! LFPS_MIN_GEN_U2EXIT - LFPS_MIN_GEN_U2EXIT value Resolution of this parameter is 8 ns. For
107868  *    simulation purposes it is recommended to set the value 12500 (~100us) For synthesis purposes it is
107869  *    recommended to set the value 12500 (~100us)
107870  */
107871 #define USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_SHIFT)) & USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_MASK)
107872 #define USB3_CFG_REG41_RESERVED_MASK             (0xFFFF8000U)
107873 #define USB3_CFG_REG41_RESERVED_SHIFT            (15U)
107874 /*! RESERVED - Reserved field. Write ignored. 0 when read
107875  */
107876 #define USB3_CFG_REG41_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG41_RESERVED_SHIFT)) & USB3_CFG_REG41_RESERVED_MASK)
107877 /*! @} */
107878 
107879 /*! @name CFG_REG42 - USB3 Configuration */
107880 /*! @{ */
107881 #define USB3_CFG_REG42_LFPS_POLLING_REPEAT_MASK  (0x7FFU)
107882 #define USB3_CFG_REG42_LFPS_POLLING_REPEAT_SHIFT (0U)
107883 /*! LFPS_POLLING_REPEAT - LFPS_POLLING_REPEAT value Resolution of this parameter is 8 ns. For
107884  *    simulation purposes it is recommended to set the value 1250 (~10us) For synthesis purposes it is
107885  *    recommended to set the value 1250 (~10us)
107886  */
107887 #define USB3_CFG_REG42_LFPS_POLLING_REPEAT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG42_LFPS_POLLING_REPEAT_SHIFT)) & USB3_CFG_REG42_LFPS_POLLING_REPEAT_MASK)
107888 #define USB3_CFG_REG42_RESERVED_MASK             (0xFFFFF800U)
107889 #define USB3_CFG_REG42_RESERVED_SHIFT            (11U)
107890 /*! RESERVED - Reserved field. Write ignored. 0 when read
107891  */
107892 #define USB3_CFG_REG42_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG42_RESERVED_SHIFT)) & USB3_CFG_REG42_RESERVED_MASK)
107893 /*! @} */
107894 
107895 /*! @name CFG_REG43 - USB3 Configuration */
107896 /*! @{ */
107897 #define USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_MASK (0x7FFU)
107898 #define USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_SHIFT (0U)
107899 /*! LFPS_POLLING_MAX_TREPEAT - LFPS_POLLING_MAX_TREPEAT value Resolution of this parameter is 8 ns.
107900  *    For simulation purposes it is recommended to set the value 1750 (~14us) For synthesis purposes
107901  *    it is recommended to set the value 1750 (~14us)
107902  */
107903 #define USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_SHIFT)) & USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_MASK)
107904 #define USB3_CFG_REG43_RESERVED_MASK             (0xFFFFF800U)
107905 #define USB3_CFG_REG43_RESERVED_SHIFT            (11U)
107906 /*! RESERVED - Reserved field. Write ignored. 0 when read
107907  */
107908 #define USB3_CFG_REG43_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG43_RESERVED_SHIFT)) & USB3_CFG_REG43_RESERVED_MASK)
107909 /*! @} */
107910 
107911 /*! @name CFG_REG44 - USB3 Configuration */
107912 /*! @{ */
107913 #define USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_MASK (0x7FFU)
107914 #define USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_SHIFT (0U)
107915 /*! LFPS_POLLING_MIN_TREPEAT - LFPS_POLLING_MIN_TREPEAT value Resolution of this parameter is 8 ns.
107916  *    For simulation purposes it is recommended to set the value 748 (~6us) For synthesis purposes
107917  *    it is recommended to set the value 748 (~6us)
107918  */
107919 #define USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_SHIFT)) & USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_MASK)
107920 #define USB3_CFG_REG44_RESERVED_MASK             (0xFFFFF800U)
107921 #define USB3_CFG_REG44_RESERVED_SHIFT            (11U)
107922 /*! RESERVED - Reserved field. Write ignored. 0 when read
107923  */
107924 #define USB3_CFG_REG44_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG44_RESERVED_SHIFT)) & USB3_CFG_REG44_RESERVED_MASK)
107925 /*! @} */
107926 
107927 /*! @name CFG_REG45 - USB3 Configuration */
107928 /*! @{ */
107929 #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_MASK   (0x7FU)
107930 #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_SHIFT  (0U)
107931 /*! ITP_WAKEUP_TIMEOUT - ITP_WAKEUP_TIMEOUT value Resolution of this parameter is selected by
107932  *    ITP_WAKEUP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 101*1us
107933  *    =~100us (SystemC device ENV) - 101*1us =~100us (VIP based ENV) For synthesis purposes it is
107934  *    recommended to set the value: - 101*1us =~100us
107935  */
107936 #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_SHIFT)) & USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_MASK)
107937 #define USB3_CFG_REG45_RESERVED_MASK             (0x3FFFFF80U)
107938 #define USB3_CFG_REG45_RESERVED_SHIFT            (7U)
107939 /*! RESERVED - Reserved field. Write ignored. 0 when read
107940  */
107941 #define USB3_CFG_REG45_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG45_RESERVED_SHIFT)) & USB3_CFG_REG45_RESERVED_MASK)
107942 #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_MASK (0xC0000000U)
107943 #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_SHIFT (30U)
107944 /*! ITP_WAKEUP_TIMEOUT_PRESCALE - PRESCALER for ITP_WAKEUP_TIMEOUT value: - 0x0 : 8ns (PHY pclk
107945  *    clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
107946  */
107947 #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_MASK)
107948 /*! @} */
107949 
107950 /*! @name CFG_REG46 - USB3 Configuration */
107951 /*! @{ */
107952 #define USB3_CFG_REG46_TSEQ_QUANTITY_MASK        (0xFFFFU)
107953 #define USB3_CFG_REG46_TSEQ_QUANTITY_SHIFT       (0U)
107954 /*! TSEQ_QUANTITY - TSEQ_QUANTITY value This parameter defines the number of TSEQ training sequences
107955  *    to be sent during Polling.RxEq state. For simulation purposes it is recommended to set the
107956  *    value 655 For synthesis purposes it is recommended to set the value 65535
107957  */
107958 #define USB3_CFG_REG46_TSEQ_QUANTITY(x)          (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG46_TSEQ_QUANTITY_SHIFT)) & USB3_CFG_REG46_TSEQ_QUANTITY_MASK)
107959 #define USB3_CFG_REG46_RESERVED_MASK             (0xFFFF0000U)
107960 #define USB3_CFG_REG46_RESERVED_SHIFT            (16U)
107961 /*! RESERVED - Reserved field. Write ignored. 0 when read
107962  */
107963 #define USB3_CFG_REG46_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG46_RESERVED_SHIFT)) & USB3_CFG_REG46_RESERVED_MASK)
107964 /*! @} */
107965 
107966 /*! @name CFG_REG47 - USB3 Configuration */
107967 /*! @{ */
107968 #define USB3_CFG_REG47_ERDY_TIMEOUT_CNT_MASK     (0xFFFFFU)
107969 #define USB3_CFG_REG47_ERDY_TIMEOUT_CNT_SHIFT    (0U)
107970 /*! ERDY_TIMEOUT_CNT - ERDY_TIMEOUT_CNT value Resolution of this parameter is 1 us. For simulation
107971  *    purposes it is recommended to set the value 16 (~15 us) For synthesis purposes it is
107972  *    recommended to set the value ~512001 (~512ms)
107973  */
107974 #define USB3_CFG_REG47_ERDY_TIMEOUT_CNT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG47_ERDY_TIMEOUT_CNT_SHIFT)) & USB3_CFG_REG47_ERDY_TIMEOUT_CNT_MASK)
107975 #define USB3_CFG_REG47_RESERVED_MASK             (0xFFF00000U)
107976 #define USB3_CFG_REG47_RESERVED_SHIFT            (20U)
107977 /*! RESERVED - Reserved field. Write ignored. 0 when read
107978  */
107979 #define USB3_CFG_REG47_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG47_RESERVED_SHIFT)) & USB3_CFG_REG47_RESERVED_MASK)
107980 /*! @} */
107981 
107982 /*! @name CFG_REG48 - USB2 Configuration */
107983 /*! @{ */
107984 #define USB3_CFG_REG48_TWTRSTFS_J_CNT_MASK       (0x3FFFFU)
107985 #define USB3_CFG_REG48_TWTRSTFS_J_CNT_SHIFT      (0U)
107986 /*! TWTRSTFS_J_CNT - TWTRSTFS_J_CNT value Resolution of this parameter is 33.3 ns. For simulation
107987  *    purposes it is recommended to set the value 98304 (~3.28ms) For synthesis purposes it is
107988  *    recommended to set the value 98304 (~3.28ms)
107989  */
107990 #define USB3_CFG_REG48_TWTRSTFS_J_CNT(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG48_TWTRSTFS_J_CNT_SHIFT)) & USB3_CFG_REG48_TWTRSTFS_J_CNT_MASK)
107991 #define USB3_CFG_REG48_RESERVED_MASK             (0xFFFC0000U)
107992 #define USB3_CFG_REG48_RESERVED_SHIFT            (18U)
107993 /*! RESERVED - Reserved field. Write ignored. 0 when read
107994  */
107995 #define USB3_CFG_REG48_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG48_RESERVED_SHIFT)) & USB3_CFG_REG48_RESERVED_MASK)
107996 /*! @} */
107997 
107998 /*! @name CFG_REG49 - USB2 Configuration */
107999 /*! @{ */
108000 #define USB3_CFG_REG49_TUCH_CNT_MASK             (0xFFFFU)
108001 #define USB3_CFG_REG49_TUCH_CNT_SHIFT            (0U)
108002 /*! TUCH_CNT - TUCH_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes it is
108003  *    recommended to set the value 129 (~4.3us) For synthesis purposes it is recommended to set the
108004  *    value 35584 (~1.19ms)
108005  */
108006 #define USB3_CFG_REG49_TUCH_CNT(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG49_TUCH_CNT_SHIFT)) & USB3_CFG_REG49_TUCH_CNT_MASK)
108007 #define USB3_CFG_REG49_RESERVED_MASK             (0xFFFF0000U)
108008 #define USB3_CFG_REG49_RESERVED_SHIFT            (16U)
108009 /*! RESERVED - Reserved field. Write ignored. 0 when read
108010  */
108011 #define USB3_CFG_REG49_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG49_RESERVED_SHIFT)) & USB3_CFG_REG49_RESERVED_MASK)
108012 /*! @} */
108013 
108014 /*! @name CFG_REG50 - USB2 Configuration */
108015 /*! @{ */
108016 #define USB3_CFG_REG50_TWAITCHK_CNT_MASK         (0xFFFU)
108017 #define USB3_CFG_REG50_TWAITCHK_CNT_SHIFT        (0U)
108018 /*! TWAITCHK_CNT - TWAITCHK_CNT value Resolution of this parameter is 33.3 ns. For simulation
108019  *    purposes it is recommended to set the value 30 (~1us) For synthesis purposes it is recommended to
108020  *    set the value 2400 (~80us)
108021  */
108022 #define USB3_CFG_REG50_TWAITCHK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG50_TWAITCHK_CNT_SHIFT)) & USB3_CFG_REG50_TWAITCHK_CNT_MASK)
108023 #define USB3_CFG_REG50_RESERVED_MASK             (0xFFFFF000U)
108024 #define USB3_CFG_REG50_RESERVED_SHIFT            (12U)
108025 /*! RESERVED - Reserved field. Write ignored. 0 when read
108026  */
108027 #define USB3_CFG_REG50_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG50_RESERVED_SHIFT)) & USB3_CFG_REG50_RESERVED_MASK)
108028 /*! @} */
108029 
108030 /*! @name CFG_REG51 - USB2 Configuration */
108031 /*! @{ */
108032 #define USB3_CFG_REG51_TWTFS_CNT_MASK            (0x1FFFFU)
108033 #define USB3_CFG_REG51_TWTFS_CNT_SHIFT           (0U)
108034 /*! TWTFS_CNT - TWTFS_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes it
108035  *    is recommended to set the value 1000 (~33.3us) For synthesis purposes it is recommended to set
108036  *    the value 104963 (~3.5ms)
108037  */
108038 #define USB3_CFG_REG51_TWTFS_CNT(x)              (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG51_TWTFS_CNT_SHIFT)) & USB3_CFG_REG51_TWTFS_CNT_MASK)
108039 #define USB3_CFG_REG51_RESERVED_MASK             (0xFFFE0000U)
108040 #define USB3_CFG_REG51_RESERVED_SHIFT            (17U)
108041 /*! RESERVED - Reserved field. Write ignored. 0 when read
108042  */
108043 #define USB3_CFG_REG51_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG51_RESERVED_SHIFT)) & USB3_CFG_REG51_RESERVED_MASK)
108044 /*! @} */
108045 
108046 /*! @name CFG_REG52 - USB2 Configuration */
108047 /*! @{ */
108048 #define USB3_CFG_REG52_TWTREV_CNT_MASK           (0x1FFFFU)
108049 #define USB3_CFG_REG52_TWTREV_CNT_SHIFT          (0U)
108050 /*! TWTREV_CNT - TWTREV_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes
108051  *    it is recommended to set the value 90112 (~3ms) For synthesis purposes it is recommended to set
108052  *    the value 90112 (~3ms)
108053  */
108054 #define USB3_CFG_REG52_TWTREV_CNT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG52_TWTREV_CNT_SHIFT)) & USB3_CFG_REG52_TWTREV_CNT_MASK)
108055 #define USB3_CFG_REG52_RESERVED_MASK             (0xFFFE0000U)
108056 #define USB3_CFG_REG52_RESERVED_SHIFT            (17U)
108057 /*! RESERVED - Reserved field. Write ignored. 0 when read
108058  */
108059 #define USB3_CFG_REG52_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG52_RESERVED_SHIFT)) & USB3_CFG_REG52_RESERVED_MASK)
108060 /*! @} */
108061 
108062 /*! @name CFG_REG53 - USB2 Configuration */
108063 /*! @{ */
108064 #define USB3_CFG_REG53_TWTRSTHS_CNT_MASK         (0x7FFFU)
108065 #define USB3_CFG_REG53_TWTRSTHS_CNT_SHIFT        (0U)
108066 /*! TWTRSTHS_CNT - TWTRSTHS_CNT value Resolution of this parameter is 33.3 ns. For simulation
108067  *    purposes it is recommended to set the value 23552 (~785us) For synthesis purposes it is recommended
108068  *    to set the value 23552 (~785us)
108069  */
108070 #define USB3_CFG_REG53_TWTRSTHS_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG53_TWTRSTHS_CNT_SHIFT)) & USB3_CFG_REG53_TWTRSTHS_CNT_MASK)
108071 #define USB3_CFG_REG53_RESERVED_MASK             (0xFFFF8000U)
108072 #define USB3_CFG_REG53_RESERVED_SHIFT            (15U)
108073 /*! RESERVED - Reserved field. Write ignored. 0 when read
108074  */
108075 #define USB3_CFG_REG53_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG53_RESERVED_SHIFT)) & USB3_CFG_REG53_RESERVED_MASK)
108076 /*! @} */
108077 
108078 /*! @name CFG_REG54 - USB2 Configuration */
108079 /*! @{ */
108080 #define USB3_CFG_REG54_TWTRSM_CNT_MASK           (0x3FFFFU)
108081 #define USB3_CFG_REG54_TWTRSM_CNT_SHIFT          (0U)
108082 /*! TWTRSM_CNT - TWTRSM_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes
108083  *    it is recommended to set the value 150016 (~5ms) For synthesis purposes it is recommended to
108084  *    set the value 150016 (~5ms)
108085  */
108086 #define USB3_CFG_REG54_TWTRSM_CNT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG54_TWTRSM_CNT_SHIFT)) & USB3_CFG_REG54_TWTRSM_CNT_MASK)
108087 #define USB3_CFG_REG54_RESERVED_MASK             (0xFFFC0000U)
108088 #define USB3_CFG_REG54_RESERVED_SHIFT            (18U)
108089 /*! RESERVED - Reserved field. Write ignored. 0 when read
108090  */
108091 #define USB3_CFG_REG54_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG54_RESERVED_SHIFT)) & USB3_CFG_REG54_RESERVED_MASK)
108092 /*! @} */
108093 
108094 /*! @name CFG_REG55 - USB2 Configuration */
108095 /*! @{ */
108096 #define USB3_CFG_REG55_TDRSMUP_CNT_MASK          (0xFFFFU)
108097 #define USB3_CFG_REG55_TDRSMUP_CNT_SHIFT         (0U)
108098 /*! TDRSMUP_CNT - TDRSMUP_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes
108099  *    it is recommended to set the value 32768 (~1.1ms) For synthesis purposes it is recommended to
108100  *    set the value 32768 (~1.1ms)
108101  */
108102 #define USB3_CFG_REG55_TDRSMUP_CNT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG55_TDRSMUP_CNT_SHIFT)) & USB3_CFG_REG55_TDRSMUP_CNT_MASK)
108103 #define USB3_CFG_REG55_RESERVED_MASK             (0xFFFF0000U)
108104 #define USB3_CFG_REG55_RESERVED_SHIFT            (16U)
108105 /*! RESERVED - Reserved field. Write ignored. 0 when read
108106  */
108107 #define USB3_CFG_REG55_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG55_RESERVED_SHIFT)) & USB3_CFG_REG55_RESERVED_MASK)
108108 /*! @} */
108109 
108110 /*! @name CFG_REG56 - USB2 Configuration */
108111 /*! @{ */
108112 #define USB3_CFG_REG56_TOUTHS_CNT_MASK           (0x3FU)
108113 #define USB3_CFG_REG56_TOUTHS_CNT_SHIFT          (0U)
108114 /*! TOUTHS_CNT - TOUTHS_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes
108115  *    it is recommended to set the value 48 (~1.6us) For synthesis purposes it is recommended to set
108116  *    the value 48 (~1.6us)
108117  */
108118 #define USB3_CFG_REG56_TOUTHS_CNT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG56_TOUTHS_CNT_SHIFT)) & USB3_CFG_REG56_TOUTHS_CNT_MASK)
108119 #define USB3_CFG_REG56_RESERVED_MASK             (0xFFFFFFC0U)
108120 #define USB3_CFG_REG56_RESERVED_SHIFT            (6U)
108121 /*! RESERVED - Reserved field. Write ignored. 0 when read
108122  */
108123 #define USB3_CFG_REG56_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG56_RESERVED_SHIFT)) & USB3_CFG_REG56_RESERVED_MASK)
108124 /*! @} */
108125 
108126 /*! @name CFG_REG57 - USB3 Configuration */
108127 /*! @{ */
108128 #define USB3_CFG_REG57_LFPS_DEB_WIDTH_MASK       (0x3U)
108129 #define USB3_CFG_REG57_LFPS_DEB_WIDTH_SHIFT      (0U)
108130 /*! LFPS_DEB_WIDTH - LFPS_DEB_WIDTH value This parameter defines the LFPS debouncer delay. Only two
108131  *    values are allowed: 0x1 or 0x2. For simulation purposes it is recommended to set the value 1.
108132  *    For synthesis purposes it is recommended to set the value 2
108133  */
108134 #define USB3_CFG_REG57_LFPS_DEB_WIDTH(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG57_LFPS_DEB_WIDTH_SHIFT)) & USB3_CFG_REG57_LFPS_DEB_WIDTH_MASK)
108135 #define USB3_CFG_REG57_RESERVED_MASK             (0xFFFFFFFCU)
108136 #define USB3_CFG_REG57_RESERVED_SHIFT            (2U)
108137 /*! RESERVED - Reserved field. Write ignored. 0 when read
108138  */
108139 #define USB3_CFG_REG57_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG57_RESERVED_SHIFT)) & USB3_CFG_REG57_RESERVED_MASK)
108140 /*! @} */
108141 
108142 /*! @name CFG_REG58 - USB3 Configuration */
108143 /*! @{ */
108144 #define USB3_CFG_REG58_LFPS_GEN_U2EXIT_MASK      (0x3FFFFU)
108145 #define USB3_CFG_REG58_LFPS_GEN_U2EXIT_SHIFT     (0U)
108146 /*! LFPS_GEN_U2EXIT - LFPS_GEN_U2EXIT value Resolution of this parameter is 8 ns. For simulation
108147  *    purposes it is recommended to set the value 62500 (~500us) For synthesis purposes it is
108148  *    recommended to set the value 250000 (~2ms)
108149  */
108150 #define USB3_CFG_REG58_LFPS_GEN_U2EXIT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG58_LFPS_GEN_U2EXIT_SHIFT)) & USB3_CFG_REG58_LFPS_GEN_U2EXIT_MASK)
108151 #define USB3_CFG_REG58_RESERVED_MASK             (0xFFFC0000U)
108152 #define USB3_CFG_REG58_RESERVED_SHIFT            (18U)
108153 /*! RESERVED - Reserved field. Write ignored. 0 when read
108154  */
108155 #define USB3_CFG_REG58_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG58_RESERVED_SHIFT)) & USB3_CFG_REG58_RESERVED_MASK)
108156 /*! @} */
108157 
108158 /*! @name CFG_REG59 - USB3 Configuration */
108159 /*! @{ */
108160 #define USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_MASK  (0xFFFFU)
108161 #define USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_SHIFT (0U)
108162 /*! LFPS_MIN_GEN_U3EXIT - LFPS_MIN_GEN_U3EXIT value Resolution of this parameter is 8 ns. For
108163  *    simulation purposes it is recommended to set the value 12500 (~100us) For synthesis purposes it is
108164  *    recommended to set the value 12500 (~100us)
108165  */
108166 #define USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_SHIFT)) & USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_MASK)
108167 #define USB3_CFG_REG59_RESERVED_MASK             (0xFFFF0000U)
108168 #define USB3_CFG_REG59_RESERVED_SHIFT            (16U)
108169 /*! RESERVED - Reserved field. Write ignored. 0 when read
108170  */
108171 #define USB3_CFG_REG59_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG59_RESERVED_SHIFT)) & USB3_CFG_REG59_RESERVED_MASK)
108172 /*! @} */
108173 
108174 /*! @name CFG_REG60 - USB3 Configuration */
108175 /*! @{ */
108176 #define USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_MASK  (0x7FU)
108177 #define USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_SHIFT (0U)
108178 /*! PORT_CONFIG_TIMEOUT - PORT_CONFIG_TIMEOUT value Resolution of this parameter is 1 us. For
108179  *    simulation purposes it is recommended to set the value 21 (~20us) For synthesis purposes it is
108180  *    recommended to set the value 21 (~20us)
108181  */
108182 #define USB3_CFG_REG60_PORT_CONFIG_TIMEOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_SHIFT)) & USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_MASK)
108183 #define USB3_CFG_REG60_RESERVED_MASK             (0xFFFFFF80U)
108184 #define USB3_CFG_REG60_RESERVED_SHIFT            (7U)
108185 /*! RESERVED - Reserved field. Write ignored. 0 when read
108186  */
108187 #define USB3_CFG_REG60_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG60_RESERVED_SHIFT)) & USB3_CFG_REG60_RESERVED_MASK)
108188 /*! @} */
108189 
108190 /*! @name CFG_REG61 - USB3 Configuration */
108191 /*! @{ */
108192 #define USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_MASK (0x7FFU)
108193 #define USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_SHIFT (0U)
108194 /*! LFPS_POL_LFPS_TO_RXEQ - LFPS_POL_LFPS_TO_RXEQ value Resolution of this parameter is 8 ns. For
108195  *    simulation purposes it is recommended to set the value 250 (~2us) For synthesis purposes it is
108196  *    recommended to set the value 250 (~2us)
108197  */
108198 #define USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_SHIFT)) & USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_MASK)
108199 #define USB3_CFG_REG61_RESERVED_MASK             (0xFFFFF800U)
108200 #define USB3_CFG_REG61_RESERVED_SHIFT            (11U)
108201 /*! RESERVED - Reserved field. Write ignored. 0 when read
108202  */
108203 #define USB3_CFG_REG61_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG61_RESERVED_SHIFT)) & USB3_CFG_REG61_RESERVED_MASK)
108204 /*! @} */
108205 
108206 /*! @name CFG_REG62 - USB3 Configuration */
108207 /*! @{ */
108208 #define USB3_CFG_REG62_PHY_TX_LATENCY_MASK       (0x3FU)
108209 #define USB3_CFG_REG62_PHY_TX_LATENCY_SHIFT      (0U)
108210 /*! PHY_TX_LATENCY - PHY_TX_LATENCY value This parameter defines latency from when data appear on
108211  *    PIPE interface to channel + 3 time units (defined by PHY_TX_LATENCY_PRESCALE). For simulation
108212  *    purposes it is recommended to set the value 11. For synthesis purposes it is recommended to set
108213  *    the value 11
108214  */
108215 #define USB3_CFG_REG62_PHY_TX_LATENCY(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG62_PHY_TX_LATENCY_SHIFT)) & USB3_CFG_REG62_PHY_TX_LATENCY_MASK)
108216 #define USB3_CFG_REG62_RESERVED_MASK             (0x3FFFFFC0U)
108217 #define USB3_CFG_REG62_RESERVED_SHIFT            (6U)
108218 /*! RESERVED - Reserved field. Write ignored. 0 when read
108219  */
108220 #define USB3_CFG_REG62_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG62_RESERVED_SHIFT)) & USB3_CFG_REG62_RESERVED_MASK)
108221 #define USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_MASK (0xC0000000U)
108222 #define USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_SHIFT (30U)
108223 /*! PHY_TX_LATENCY_PRESCALE - PRESCALER for PHY_TX_LATENCY value: - 0x0 : 8ns (PHY pclk clock) - 0x1
108224  *    : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout
108225  */
108226 #define USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_SHIFT)) & USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_MASK)
108227 /*! @} */
108228 
108229 /*! @name CFG_REG63 - USB3 Configuration */
108230 /*! @{ */
108231 #define USB3_CFG_REG63_U2_INACTIVITY_TMOUT_MASK  (0x7FFFU)
108232 #define USB3_CFG_REG63_U2_INACTIVITY_TMOUT_SHIFT (0U)
108233 /*! U2_INACTIVITY_TMOUT - U2_INACTIVITY_TMOUT value Resolution of this parameter is 8 ns. For
108234  *    simulation purposes it is recommended to set the value: - 31999*8ns =~256us (SystemC device ENV) -
108235  *    249*8ns =~2us (VIP based ENV) For synthesis purposes it is recommended to set the value: -
108236  *    31999*8ns =~256us
108237  */
108238 #define USB3_CFG_REG63_U2_INACTIVITY_TMOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG63_U2_INACTIVITY_TMOUT_SHIFT)) & USB3_CFG_REG63_U2_INACTIVITY_TMOUT_MASK)
108239 #define USB3_CFG_REG63_RESERVED_MASK             (0xFFFF8000U)
108240 #define USB3_CFG_REG63_RESERVED_SHIFT            (15U)
108241 /*! RESERVED - Reserved field. Write ignored. 0 when read
108242  */
108243 #define USB3_CFG_REG63_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG63_RESERVED_SHIFT)) & USB3_CFG_REG63_RESERVED_MASK)
108244 /*! @} */
108245 
108246 /*! @name CFG_REG64 - USB2 Configuration */
108247 /*! @{ */
108248 #define USB3_CFG_REG64_TFILTSE0_MASK             (0x7FU)
108249 #define USB3_CFG_REG64_TFILTSE0_SHIFT            (0U)
108250 /*! TFILTSE0 - TFILTSE0 value Resolution of this parameter is 33.3ns. For simulation purposes it is
108251  *    recommended to set the value: - 74*33.3ns =~2.46us (SystemC device ENV) - 57*33.3ns =~1.9us
108252  *    (VIP based ENV) For synthesis purposes it is recommended to set the value: - 74*33.3ns =~2.46us
108253  */
108254 #define USB3_CFG_REG64_TFILTSE0(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG64_TFILTSE0_SHIFT)) & USB3_CFG_REG64_TFILTSE0_MASK)
108255 #define USB3_CFG_REG64_RESERVED_MASK             (0xFFFFFF80U)
108256 #define USB3_CFG_REG64_RESERVED_SHIFT            (7U)
108257 /*! RESERVED - Reserved field. Write ignored. 0 when read
108258  */
108259 #define USB3_CFG_REG64_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG64_RESERVED_SHIFT)) & USB3_CFG_REG64_RESERVED_MASK)
108260 /*! @} */
108261 
108262 /*! @name CFG_REG65 - USB2 Configuration */
108263 /*! @{ */
108264 #define USB3_CFG_REG65_TFILT_MASK                (0x7FU)
108265 #define USB3_CFG_REG65_TFILT_SHIFT               (0U)
108266 /*! TFILT - TFILT value Resolution of this parameter is 33.3 ns. For simulation purposes it is
108267  *    recommended to set the value: - 75*33.3ns =~2.5us (SystemC device ENV) - 57*33.3ns =~1.9us (VIP
108268  *    based ENV) For synthesis purposes it is recommended to set the value: - 75*33.3ns =~2.5us
108269  */
108270 #define USB3_CFG_REG65_TFILT(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG65_TFILT_SHIFT)) & USB3_CFG_REG65_TFILT_MASK)
108271 #define USB3_CFG_REG65_RESERVED_MASK             (0xFFFF8000U)
108272 #define USB3_CFG_REG65_RESERVED_SHIFT            (15U)
108273 /*! RESERVED - Reserved field. Write ignored. 0 when read
108274  */
108275 #define USB3_CFG_REG65_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG65_RESERVED_SHIFT)) & USB3_CFG_REG65_RESERVED_MASK)
108276 /*! @} */
108277 
108278 /*! @name CFG_REG66 - USB2 Configuration */
108279 /*! @{ */
108280 #define USB3_CFG_REG66_TWTRSTFS_SE0_MASK         (0x7FU)
108281 #define USB3_CFG_REG66_TWTRSTFS_SE0_SHIFT        (0U)
108282 /*! TWTRSTFS_SE0 - TWTRSTFS_SE0 value Resolution of this parameter is 33.3 ns. For simulation
108283  *    purposes it is recommended to set the value: - 73*33.3ns =~2.43us (SystemC device ENV) - 57*33.3ns
108284  *    =~1.9us (VIP based ENV) For synthesis purposes it is recommended to set the value: - 73*33.3ns
108285  *    =~2.43us
108286  */
108287 #define USB3_CFG_REG66_TWTRSTFS_SE0(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG66_TWTRSTFS_SE0_SHIFT)) & USB3_CFG_REG66_TWTRSTFS_SE0_MASK)
108288 #define USB3_CFG_REG66_RESERVED_MASK             (0xFFFF8000U)
108289 #define USB3_CFG_REG66_RESERVED_SHIFT            (15U)
108290 /*! RESERVED - Reserved field. Write ignored. 0 when read
108291  */
108292 #define USB3_CFG_REG66_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG66_RESERVED_SHIFT)) & USB3_CFG_REG66_RESERVED_MASK)
108293 /*! @} */
108294 
108295 /*! @name DMA_AXI_CTRL - DMA AXI Master Control */
108296 /*! @{ */
108297 #define USB3_DMA_AXI_CTRL_MARPROT_MASK           (0x7U)
108298 #define USB3_DMA_AXI_CTRL_MARPROT_SHIFT          (0U)
108299 /*! MARPROT - MARPROT
108300  */
108301 #define USB3_DMA_AXI_CTRL_MARPROT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MARPROT_SHIFT)) & USB3_DMA_AXI_CTRL_MARPROT_MASK)
108302 #define USB3_DMA_AXI_CTRL_RESERVED0_MASK         (0x8U)
108303 #define USB3_DMA_AXI_CTRL_RESERVED0_SHIFT        (3U)
108304 /*! RESERVED0 - RESERVED0
108305  */
108306 #define USB3_DMA_AXI_CTRL_RESERVED0(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED0_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED0_MASK)
108307 #define USB3_DMA_AXI_CTRL_MARCACHE_MASK          (0xF0U)
108308 #define USB3_DMA_AXI_CTRL_MARCACHE_SHIFT         (4U)
108309 /*! MARCACHE - MARCACHE
108310  */
108311 #define USB3_DMA_AXI_CTRL_MARCACHE(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MARCACHE_SHIFT)) & USB3_DMA_AXI_CTRL_MARCACHE_MASK)
108312 #define USB3_DMA_AXI_CTRL_MARLOCK_MASK           (0x300U)
108313 #define USB3_DMA_AXI_CTRL_MARLOCK_SHIFT          (8U)
108314 /*! MARLOCK - MARLOCK
108315  */
108316 #define USB3_DMA_AXI_CTRL_MARLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MARLOCK_SHIFT)) & USB3_DMA_AXI_CTRL_MARLOCK_MASK)
108317 #define USB3_DMA_AXI_CTRL_RESERVED1_MASK         (0xFC00U)
108318 #define USB3_DMA_AXI_CTRL_RESERVED1_SHIFT        (10U)
108319 /*! RESERVED1 - RESERVED1
108320  */
108321 #define USB3_DMA_AXI_CTRL_RESERVED1(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED1_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED1_MASK)
108322 #define USB3_DMA_AXI_CTRL_MAWPROT_MASK           (0x70000U)
108323 #define USB3_DMA_AXI_CTRL_MAWPROT_SHIFT          (16U)
108324 /*! MAWPROT - MAWPROT
108325  */
108326 #define USB3_DMA_AXI_CTRL_MAWPROT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MAWPROT_SHIFT)) & USB3_DMA_AXI_CTRL_MAWPROT_MASK)
108327 #define USB3_DMA_AXI_CTRL_RESERVED2_MASK         (0x80000U)
108328 #define USB3_DMA_AXI_CTRL_RESERVED2_SHIFT        (19U)
108329 /*! RESERVED2 - RESERVED2
108330  */
108331 #define USB3_DMA_AXI_CTRL_RESERVED2(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED2_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED2_MASK)
108332 #define USB3_DMA_AXI_CTRL_MAWCACHE_MASK          (0xF00000U)
108333 #define USB3_DMA_AXI_CTRL_MAWCACHE_SHIFT         (20U)
108334 /*! MAWCACHE - MAWCACHE
108335  */
108336 #define USB3_DMA_AXI_CTRL_MAWCACHE(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MAWCACHE_SHIFT)) & USB3_DMA_AXI_CTRL_MAWCACHE_MASK)
108337 #define USB3_DMA_AXI_CTRL_MAWLOCK_MASK           (0x3000000U)
108338 #define USB3_DMA_AXI_CTRL_MAWLOCK_SHIFT          (24U)
108339 /*! MAWLOCK - MAWLOCK
108340  */
108341 #define USB3_DMA_AXI_CTRL_MAWLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MAWLOCK_SHIFT)) & USB3_DMA_AXI_CTRL_MAWLOCK_MASK)
108342 #define USB3_DMA_AXI_CTRL_RESERVED3_MASK         (0xFC000000U)
108343 #define USB3_DMA_AXI_CTRL_RESERVED3_SHIFT        (26U)
108344 /*! RESERVED3 - RESERVED3
108345  */
108346 #define USB3_DMA_AXI_CTRL_RESERVED3(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED3_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED3_MASK)
108347 /*! @} */
108348 
108349 /*! @name DMA_AXI_ID - DMA AXI Master ID */
108350 /*! @{ */
108351 #define USB3_DMA_AXI_ID_MAW_ID_MASK              (0x1FU)
108352 #define USB3_DMA_AXI_ID_MAW_ID_SHIFT             (0U)
108353 /*! MAW_ID - MAW_ID
108354  */
108355 #define USB3_DMA_AXI_ID_MAW_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_MAW_ID_SHIFT)) & USB3_DMA_AXI_ID_MAW_ID_MASK)
108356 #define USB3_DMA_AXI_ID_RESERVED0_MASK           (0xFFE0U)
108357 #define USB3_DMA_AXI_ID_RESERVED0_SHIFT          (5U)
108358 /*! RESERVED0 - RESERVED0
108359  */
108360 #define USB3_DMA_AXI_ID_RESERVED0(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_RESERVED0_SHIFT)) & USB3_DMA_AXI_ID_RESERVED0_MASK)
108361 #define USB3_DMA_AXI_ID_MAR_ID_MASK              (0x1F0000U)
108362 #define USB3_DMA_AXI_ID_MAR_ID_SHIFT             (16U)
108363 /*! MAR_ID - MAR_ID
108364  */
108365 #define USB3_DMA_AXI_ID_MAR_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_MAR_ID_SHIFT)) & USB3_DMA_AXI_ID_MAR_ID_MASK)
108366 #define USB3_DMA_AXI_ID_RESERVED1_MASK           (0xFFE00000U)
108367 #define USB3_DMA_AXI_ID_RESERVED1_SHIFT          (21U)
108368 /*! RESERVED1 - RESERVED1
108369  */
108370 #define USB3_DMA_AXI_ID_RESERVED1(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_RESERVED1_SHIFT)) & USB3_DMA_AXI_ID_RESERVED1_MASK)
108371 /*! @} */
108372 
108373 /*! @name DMA_AXI_CAP - DMA AXI Master Extended Capability */
108374 /*! @{ */
108375 #define USB3_DMA_AXI_CAP_RESERVED0_MASK          (0xFFFFFU)
108376 #define USB3_DMA_AXI_CAP_RESERVED0_SHIFT         (0U)
108377 /*! RESERVED0 - RESERVED0
108378  */
108379 #define USB3_DMA_AXI_CAP_RESERVED0(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_RESERVED0_SHIFT)) & USB3_DMA_AXI_CAP_RESERVED0_MASK)
108380 #define USB3_DMA_AXI_CAP_AXI_DECERR_EN_MASK      (0x100000U)
108381 #define USB3_DMA_AXI_CAP_AXI_DECERR_EN_SHIFT     (20U)
108382 /*! AXI_DECERR_EN - This bit enables interrupt on AXI DECODE ERROR detection. When 1 and AXI_DECERR
108383  *    is 1 then AXI DECODE ERROR interrupt is requested. When 0 - disabled interrupt from this source
108384  */
108385 #define USB3_DMA_AXI_CAP_AXI_DECERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_DECERR_EN_SHIFT)) & USB3_DMA_AXI_CAP_AXI_DECERR_EN_MASK)
108386 #define USB3_DMA_AXI_CAP_AXI_SLVERR_EN_MASK      (0x200000U)
108387 #define USB3_DMA_AXI_CAP_AXI_SLVERR_EN_SHIFT     (21U)
108388 /*! AXI_SLVERR_EN - This bit enables interrupt on AXI SLAVE ERROR detection. When 1 and AXI_SLVERR
108389  *    is 1 then AXI SLAVE ERROR interrupt is requested. When 0 - disabled interrupt from this source
108390  */
108391 #define USB3_DMA_AXI_CAP_AXI_SLVERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_SLVERR_EN_SHIFT)) & USB3_DMA_AXI_CAP_AXI_SLVERR_EN_MASK)
108392 #define USB3_DMA_AXI_CAP_RESERVED1_MASK          (0xFC00000U)
108393 #define USB3_DMA_AXI_CAP_RESERVED1_SHIFT         (22U)
108394 /*! RESERVED1 - RESERVED1
108395  */
108396 #define USB3_DMA_AXI_CAP_RESERVED1(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_RESERVED1_SHIFT)) & USB3_DMA_AXI_CAP_RESERVED1_MASK)
108397 #define USB3_DMA_AXI_CAP_AXI_DECERR_MASK         (0x10000000U)
108398 #define USB3_DMA_AXI_CAP_AXI_DECERR_SHIFT        (28U)
108399 /*! AXI_DECERR - This bit provides an information about AXI DECODE ERROR response on B or R channel.
108400  *    This flag is cleared by writing '1' to it. Once set it is held until cleared
108401  */
108402 #define USB3_DMA_AXI_CAP_AXI_DECERR(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_DECERR_SHIFT)) & USB3_DMA_AXI_CAP_AXI_DECERR_MASK)
108403 #define USB3_DMA_AXI_CAP_AXI_SLVERR_MASK         (0x20000000U)
108404 #define USB3_DMA_AXI_CAP_AXI_SLVERR_SHIFT        (29U)
108405 /*! AXI_SLVERR - This bit provides an information about AXI SLAVE ERROR response on B or R channel.
108406  *    This flag is cleared by writing '1' to it. Once set it is held until cleared
108407  */
108408 #define USB3_DMA_AXI_CAP_AXI_SLVERR(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_SLVERR_SHIFT)) & USB3_DMA_AXI_CAP_AXI_SLVERR_MASK)
108409 #define USB3_DMA_AXI_CAP_AXI_IDLE_MASK           (0x40000000U)
108410 #define USB3_DMA_AXI_CAP_AXI_IDLE_SHIFT          (30U)
108411 /*! AXI_IDLE - This bit provides information about the AXI Master state: '1': no pending action
108412  *    required by the AXI Master wrapper, '0': the AXI Master wrapper has outstanding transactions
108413  */
108414 #define USB3_DMA_AXI_CAP_AXI_IDLE(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_IDLE_SHIFT)) & USB3_DMA_AXI_CAP_AXI_IDLE_MASK)
108415 #define USB3_DMA_AXI_CAP_RESERVED2_MASK          (0x80000000U)
108416 #define USB3_DMA_AXI_CAP_RESERVED2_SHIFT         (31U)
108417 /*! RESERVED2 - RESERVED2
108418  */
108419 #define USB3_DMA_AXI_CAP_RESERVED2(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_RESERVED2_SHIFT)) & USB3_DMA_AXI_CAP_RESERVED2_MASK)
108420 /*! @} */
108421 
108422 /*! @name DMA_AXI_CTRL0 - DMA AXI Master Control */
108423 /*! @{ */
108424 #define USB3_DMA_AXI_CTRL0_B_MAX_MASK            (0xFU)
108425 #define USB3_DMA_AXI_CTRL0_B_MAX_SHIFT           (0U)
108426 /*! B_MAX - The register controls maximum burst length - it is used by the AXI Master wrapper to
108427  *    determine maximum value of AxLEN. It uses AXI AxLEN encoding. Default value is the maximum
108428  *    supported one and it is implementation specific. Width of this register is the same as AxLEN signals
108429  *    width. Note: This register should only be written to during the register initialisation
108430  *    process
108431  */
108432 #define USB3_DMA_AXI_CTRL0_B_MAX(x)              (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL0_B_MAX_SHIFT)) & USB3_DMA_AXI_CTRL0_B_MAX_MASK)
108433 #define USB3_DMA_AXI_CTRL0_RESERVED_MASK         (0xFFFFFFF0U)
108434 #define USB3_DMA_AXI_CTRL0_RESERVED_SHIFT        (4U)
108435 /*! RESERVED - RESERVED
108436  */
108437 #define USB3_DMA_AXI_CTRL0_RESERVED(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL0_RESERVED_SHIFT)) & USB3_DMA_AXI_CTRL0_RESERVED_MASK)
108438 /*! @} */
108439 
108440 /*! @name DMA_AXI_CTRL1 - DMA AXI Master Control */
108441 /*! @{ */
108442 #define USB3_DMA_AXI_CTRL1_ROT_MASK              (0x1FU)
108443 #define USB3_DMA_AXI_CTRL1_ROT_SHIFT             (0U)
108444 /*! ROT - Number of outstanding read transactions that can be initiated by the AXI Master wrapper.
108445  *    Default value of this field is CDNS_USBSSDEV_AXI_WCD-1 (define parameter). The value written to
108446  *    this field should be the requested number of outstanding read transactions minus 1, thus the
108447  *    actual number of possible outstanding read transactions is one more than the programmed value.
108448  *    Note: This register should only be written to during the register initialization process
108449  */
108450 #define USB3_DMA_AXI_CTRL1_ROT(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_ROT_SHIFT)) & USB3_DMA_AXI_CTRL1_ROT_MASK)
108451 #define USB3_DMA_AXI_CTRL1_RESERVED0_MASK        (0xFFE0U)
108452 #define USB3_DMA_AXI_CTRL1_RESERVED0_SHIFT       (5U)
108453 /*! RESERVED0 - RESERVED0
108454  */
108455 #define USB3_DMA_AXI_CTRL1_RESERVED0(x)          (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_RESERVED0_SHIFT)) & USB3_DMA_AXI_CTRL1_RESERVED0_MASK)
108456 #define USB3_DMA_AXI_CTRL1_WOT_MASK              (0x1F0000U)
108457 #define USB3_DMA_AXI_CTRL1_WOT_SHIFT             (16U)
108458 /*! WOT - Number of outstanding write transactions that can be initiated by the AXI Master wrapper.
108459  *    Default value of this field is CDNS_USBSSDEV_AXI_WCD-1 (define parameter). The value written
108460  *    to this field should be the requested number of outstanding write transactions minus 1, thus
108461  *    the actual number of possible outstanding write transactions is one more than the programmed
108462  *    value. Note: This register should only be written to during the register initialization process
108463  */
108464 #define USB3_DMA_AXI_CTRL1_WOT(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_WOT_SHIFT)) & USB3_DMA_AXI_CTRL1_WOT_MASK)
108465 #define USB3_DMA_AXI_CTRL1_RESERVED1_MASK        (0xFFE00000U)
108466 #define USB3_DMA_AXI_CTRL1_RESERVED1_SHIFT       (21U)
108467 /*! RESERVED1 - RESERVED1
108468  */
108469 #define USB3_DMA_AXI_CTRL1_RESERVED1(x)          (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_RESERVED1_SHIFT)) & USB3_DMA_AXI_CTRL1_RESERVED1_MASK)
108470 /*! @} */
108471 
108472 
108473 /*!
108474  * @}
108475  */ /* end of group USB3_Register_Masks */
108476 
108477 
108478 /* USB3 - Peripheral instance base addresses */
108479 /** Peripheral CONNECTIVITY__USB3 base address */
108480 #define CONNECTIVITY__USB3_BASE                  (0x5B110000u)
108481 /** Peripheral CONNECTIVITY__USB3 base pointer */
108482 #define CONNECTIVITY__USB3                       ((USB3_Type *)CONNECTIVITY__USB3_BASE)
108483 /** Array initializer of USB3 peripheral base addresses */
108484 #define USB3_BASE_ADDRS                          { CONNECTIVITY__USB3_BASE }
108485 /** Array initializer of USB3 peripheral base pointers */
108486 #define USB3_BASE_PTRS                           { CONNECTIVITY__USB3 }
108487 /** Interrupt vectors for the USB3 peripheral type */
108488 #define USB3_IRQS                                { CONNECTIVITY_USB3_INT_IRQn }
108489 
108490 /*!
108491  * @}
108492  */ /* end of group USB3_Peripheral_Access_Layer */
108493 
108494 
108495 /* ----------------------------------------------------------------------------
108496    -- USBDCD Peripheral Access Layer
108497    ---------------------------------------------------------------------------- */
108498 
108499 /*!
108500  * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
108501  * @{
108502  */
108503 
108504 /** USBDCD - Register Layout Typedef */
108505 typedef struct {
108506   __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
108507   __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
108508   __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
108509   __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override Register, offset: 0xC */
108510   __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
108511   __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
108512   union {                                          /* offset: 0x18 */
108513     __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
108514     __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
108515   };
108516 } USBDCD_Type;
108517 
108518 /* ----------------------------------------------------------------------------
108519    -- USBDCD Register Masks
108520    ---------------------------------------------------------------------------- */
108521 
108522 /*!
108523  * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
108524  * @{
108525  */
108526 
108527 /*! @name CONTROL - Control register */
108528 /*! @{ */
108529 #define USBDCD_CONTROL_IACK_MASK                 (0x1U)
108530 #define USBDCD_CONTROL_IACK_SHIFT                (0U)
108531 /*! IACK - Interrupt Acknowledge
108532  *  0b0..Do not clear the interrupt.
108533  *  0b1..Clear the IF bit (interrupt flag).
108534  */
108535 #define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
108536 #define USBDCD_CONTROL_IF_MASK                   (0x100U)
108537 #define USBDCD_CONTROL_IF_SHIFT                  (8U)
108538 /*! IF - Interrupt Flag
108539  *  0b0..No interrupt is pending.
108540  *  0b1..An interrupt is pending.
108541  */
108542 #define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
108543 #define USBDCD_CONTROL_IE_MASK                   (0x10000U)
108544 #define USBDCD_CONTROL_IE_SHIFT                  (16U)
108545 /*! IE - Interrupt Enable
108546  *  0b0..Disable interrupts to the system.
108547  *  0b1..Enable interrupts to the system.
108548  */
108549 #define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
108550 #define USBDCD_CONTROL_BC12_MASK                 (0x20000U)
108551 #define USBDCD_CONTROL_BC12_SHIFT                (17U)
108552 /*! BC12 - BC12
108553  *  0b0..Compatible with BC1.1 (default)
108554  *  0b1..Compatible with BC1.2
108555  */
108556 #define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
108557 #define USBDCD_CONTROL_START_MASK                (0x1000000U)
108558 #define USBDCD_CONTROL_START_SHIFT               (24U)
108559 /*! START - Start Change Detection Sequence
108560  *  0b0..Do not start the sequence. Writes of this value have no effect.
108561  *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
108562  */
108563 #define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
108564 #define USBDCD_CONTROL_SR_MASK                   (0x2000000U)
108565 #define USBDCD_CONTROL_SR_SHIFT                  (25U)
108566 /*! SR - Software Reset
108567  *  0b0..Do not perform a software reset.
108568  *  0b1..Perform a software reset.
108569  */
108570 #define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
108571 /*! @} */
108572 
108573 /*! @name CLOCK - Clock register */
108574 /*! @{ */
108575 #define USBDCD_CLOCK_CLOCK_UNIT_MASK             (0x1U)
108576 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            (0U)
108577 /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
108578  *  0b0..kHz Speed (between 1 kHz and 1023 kHz)
108579  *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
108580  */
108581 #define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
108582 #define USBDCD_CLOCK_CLOCK_SPEED_MASK            (0xFFCU)
108583 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           (2U)
108584 /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary
108585  */
108586 #define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
108587 /*! @} */
108588 
108589 /*! @name STATUS - Status register */
108590 /*! @{ */
108591 #define USBDCD_STATUS_SEQ_RES_MASK               (0x30000U)
108592 #define USBDCD_STATUS_SEQ_RES_SHIFT              (16U)
108593 /*! SEQ_RES - Charger Detection Sequence Results
108594  *  0b00..No results to report.
108595  *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
108596  *  0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a
108597  *        DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type
108598  *        detection has completed.)
108599  *  0b11..Attached to a DCP.
108600  */
108601 #define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
108602 #define USBDCD_STATUS_SEQ_STAT_MASK              (0xC0000U)
108603 #define USBDCD_STATUS_SEQ_STAT_SHIFT             (18U)
108604 /*! SEQ_STAT - Charger Detection Sequence Status
108605  *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
108606  *  0b01..Data pin contact detection is complete.
108607  *  0b10..Charging port detection is complete.
108608  *  0b11..Charger type detection is complete.
108609  */
108610 #define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
108611 #define USBDCD_STATUS_ERR_MASK                   (0x100000U)
108612 #define USBDCD_STATUS_ERR_SHIFT                  (20U)
108613 /*! ERR - Error Flag
108614  *  0b0..No sequence errors.
108615  *  0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
108616  */
108617 #define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
108618 #define USBDCD_STATUS_TO_MASK                    (0x200000U)
108619 #define USBDCD_STATUS_TO_SHIFT                   (21U)
108620 /*! TO - Timeout Flag
108621  *  0b0..The detection sequence has not been running for over 1 s.
108622  *  0b1..It has been over 1 s since the data pin contact was detected and debounced.
108623  */
108624 #define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
108625 #define USBDCD_STATUS_ACTIVE_MASK                (0x400000U)
108626 #define USBDCD_STATUS_ACTIVE_SHIFT               (22U)
108627 /*! ACTIVE - Active Status Indicator
108628  *  0b0..The sequence is not running.
108629  *  0b1..The sequence is running.
108630  */
108631 #define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
108632 /*! @} */
108633 
108634 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
108635 /*! @{ */
108636 #define USBDCD_SIGNAL_OVERRIDE_PS_MASK           (0x3U)
108637 #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT          (0U)
108638 /*! PS - Phase Selection
108639  *  0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent
108640  *        unexpected conditions on USB_DP and USB_DM pins. (Default)
108641  *  0b01..Reserved, not for customer use.
108642  *  0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
108643  *  0b11..Reserved, not for customer use.
108644  */
108645 #define USBDCD_SIGNAL_OVERRIDE_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
108646 /*! @} */
108647 
108648 /*! @name TIMER0 - TIMER0 register */
108649 /*! @{ */
108650 #define USBDCD_TIMER0_TUNITCON_MASK              (0xFFFU)
108651 #define USBDCD_TIMER0_TUNITCON_SHIFT             (0U)
108652 /*! TUNITCON - Unit Connection Timer Elapse (in ms)
108653  */
108654 #define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
108655 #define USBDCD_TIMER0_TSEQ_INIT_MASK             (0x3FF0000U)
108656 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT            (16U)
108657 /*! TSEQ_INIT - Sequence Initiation Time
108658  */
108659 #define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
108660 /*! @} */
108661 
108662 /*! @name TIMER1 - TIMER1 register */
108663 /*! @{ */
108664 #define USBDCD_TIMER1_TVDPSRC_ON_MASK            (0x3FFU)
108665 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           (0U)
108666 /*! TVDPSRC_ON - Time Period Comparator Enabled
108667  */
108668 #define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
108669 #define USBDCD_TIMER1_TDCD_DBNC_MASK             (0x3FF0000U)
108670 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT            (16U)
108671 /*! TDCD_DBNC - Time Period to Debounce D+ Signal
108672  */
108673 #define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
108674 /*! @} */
108675 
108676 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
108677 /*! @{ */
108678 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK         (0xFU)
108679 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        (0U)
108680 /*! CHECK_DM - Time Before Check of D- Line
108681  */
108682 #define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
108683 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      (0x3FF0000U)
108684 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     (16U)
108685 /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
108686  */
108687 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
108688 /*! @} */
108689 
108690 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
108691 /*! @{ */
108692 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       (0x3FFU)
108693 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      (0U)
108694 /*! TVDMSRC_ON - TVDMSRC_ON
108695  */
108696 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
108697 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  (0x3FF0000U)
108698 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
108699 /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
108700  */
108701 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
108702 /*! @} */
108703 
108704 
108705 /*!
108706  * @}
108707  */ /* end of group USBDCD_Register_Masks */
108708 
108709 
108710 /* USBDCD - Peripheral instance base addresses */
108711 /** Peripheral CONNECTIVITY__USBDCD base address */
108712 #define CONNECTIVITY__USBDCD_BASE                (0x5B100800u)
108713 /** Peripheral CONNECTIVITY__USBDCD base pointer */
108714 #define CONNECTIVITY__USBDCD                     ((USBDCD_Type *)CONNECTIVITY__USBDCD_BASE)
108715 /** Array initializer of USBDCD peripheral base addresses */
108716 #define USBDCD_BASE_ADDRS                        { CONNECTIVITY__USBDCD_BASE }
108717 /** Array initializer of USBDCD peripheral base pointers */
108718 #define USBDCD_BASE_PTRS                         { CONNECTIVITY__USBDCD }
108719 
108720 /*!
108721  * @}
108722  */ /* end of group USBDCD_Peripheral_Access_Layer */
108723 
108724 
108725 /* ----------------------------------------------------------------------------
108726    -- USBNC Peripheral Access Layer
108727    ---------------------------------------------------------------------------- */
108728 
108729 /*!
108730  * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
108731  * @{
108732  */
108733 
108734 /** USBNC - Register Layout Typedef */
108735 typedef struct {
108736        uint8_t RESERVED_0[512];
108737   __IO uint32_t CTRL1;                             /**< , offset: 0x200 */
108738   __IO uint32_t CTRL2;                             /**< , offset: 0x204 */
108739        uint8_t RESERVED_1[40];
108740   __IO uint32_t PHY_CFG1;                          /**< USB OTG PHY Configuration Register 1, offset: 0x230 */
108741   __IO uint32_t PHY_CFG2;                          /**< USB OTG PHY Configuration Register 2, offset: 0x234 */
108742        uint8_t RESERVED_2[4];
108743   __I  uint32_t PHY_STATUS;                        /**< USB OTG PHY Status Register, offset: 0x23C */
108744        uint8_t RESERVED_3[16];
108745   __IO uint32_t ADP_CFG1;                          /**< , offset: 0x250 */
108746   __IO uint32_t ADP_CFG2;                          /**< , offset: 0x254 */
108747   __I  uint32_t ADP_STATUS;                        /**< , offset: 0x258 */
108748 } USBNC_Type;
108749 
108750 /* ----------------------------------------------------------------------------
108751    -- USBNC Register Masks
108752    ---------------------------------------------------------------------------- */
108753 
108754 /*!
108755  * @addtogroup USBNC_Register_Masks USBNC Register Masks
108756  * @{
108757  */
108758 
108759 /*! @name CTRL1 -  */
108760 /*! @{ */
108761 #define USBNC_CTRL1_OVER_CUR_DIS_MASK            (0x80U)
108762 #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT           (7U)
108763 /*! OVER_CUR_DIS
108764  *  0b1..Disables overcurrent detection
108765  *  0b0..Enables overcurrent detection
108766  */
108767 #define USBNC_CTRL1_OVER_CUR_DIS(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)
108768 #define USBNC_CTRL1_OVER_CUR_POL_MASK            (0x100U)
108769 #define USBNC_CTRL1_OVER_CUR_POL_SHIFT           (8U)
108770 /*! OVER_CUR_POL
108771  *  0b1..Low active (low on this signal represents an overcurrent condition)
108772  *  0b0..High active (high on this signal represents an overcurrent condition)
108773  */
108774 #define USBNC_CTRL1_OVER_CUR_POL(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)
108775 #define USBNC_CTRL1_PWR_POL_MASK                 (0x200U)
108776 #define USBNC_CTRL1_PWR_POL_SHIFT                (9U)
108777 /*! PWR_POL
108778  *  0b1..PMIC Power Pin is High active.
108779  *  0b0..PMIC Power Pin is Low active.
108780  */
108781 #define USBNC_CTRL1_PWR_POL(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)
108782 #define USBNC_CTRL1_WIE_MASK                     (0x400U)
108783 #define USBNC_CTRL1_WIE_SHIFT                    (10U)
108784 /*! WIE
108785  *  0b1..Interrupt Enabled
108786  *  0b0..Interrupt Disabled
108787  */
108788 #define USBNC_CTRL1_WIE(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)
108789 #define USBNC_CTRL1_WKUP_SW_EN_MASK              (0x4000U)
108790 #define USBNC_CTRL1_WKUP_SW_EN_SHIFT             (14U)
108791 /*! WKUP_SW_EN
108792  *  0b1..Enable
108793  *  0b0..Disable
108794  */
108795 #define USBNC_CTRL1_WKUP_SW_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)
108796 #define USBNC_CTRL1_WKUP_SW_MASK                 (0x8000U)
108797 #define USBNC_CTRL1_WKUP_SW_SHIFT                (15U)
108798 /*! WKUP_SW
108799  *  0b1..Force wake-up
108800  *  0b0..Inactive
108801  */
108802 #define USBNC_CTRL1_WKUP_SW(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)
108803 #define USBNC_CTRL1_WKUP_ID_EN_MASK              (0x10000U)
108804 #define USBNC_CTRL1_WKUP_ID_EN_SHIFT             (16U)
108805 /*! WKUP_ID_EN
108806  *  0b1..Enable
108807  *  0b0..Disable
108808  */
108809 #define USBNC_CTRL1_WKUP_ID_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)
108810 #define USBNC_CTRL1_WKUP_VBUS_EN_MASK            (0x20000U)
108811 #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT           (17U)
108812 /*! WKUP_VBUS_EN
108813  *  0b1..Enable
108814  *  0b0..Disable
108815  */
108816 #define USBNC_CTRL1_WKUP_VBUS_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)
108817 #define USBNC_CTRL1_WKUP_DPDM_EN_MASK            (0x20000000U)
108818 #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT           (29U)
108819 /*! WKUP_DPDM_EN
108820  *  0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
108821  *  0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
108822  */
108823 #define USBNC_CTRL1_WKUP_DPDM_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)
108824 #define USBNC_CTRL1_WIR_MASK                     (0x80000000U)
108825 #define USBNC_CTRL1_WIR_SHIFT                    (31U)
108826 /*! WIR
108827  *  0b1..Wake-up Interrupt Request received
108828  *  0b0..No wake-up interrupt request received
108829  */
108830 #define USBNC_CTRL1_WIR(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)
108831 /*! @} */
108832 
108833 /*! @name CTRL2 -  */
108834 /*! @{ */
108835 #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK         (0x3U)
108836 #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT        (0U)
108837 #define USBNC_CTRL2_VBUS_SOURCE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)
108838 #define USBNC_CTRL2_AUTURESUME_EN_MASK           (0x4U)
108839 #define USBNC_CTRL2_AUTURESUME_EN_SHIFT          (2U)
108840 /*! AUTURESUME_EN - Auto Resume Enable
108841  *  0b0..Default
108842  */
108843 #define USBNC_CTRL2_AUTURESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)
108844 #define USBNC_CTRL2_LOWSPEED_EN_MASK             (0x8U)
108845 #define USBNC_CTRL2_LOWSPEED_EN_SHIFT            (3U)
108846 /*! LOWSPEED_EN
108847  *  0b0..Default
108848  */
108849 #define USBNC_CTRL2_LOWSPEED_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)
108850 #define USBNC_CTRL2_TERMSEL_OVERRIDE_MASK        (0x10U)
108851 #define USBNC_CTRL2_TERMSEL_OVERRIDE_SHIFT       (4U)
108852 #define USBNC_CTRL2_TERMSEL_OVERRIDE(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_TERMSEL_OVERRIDE_SHIFT)) & USBNC_CTRL2_TERMSEL_OVERRIDE_MASK)
108853 #define USBNC_CTRL2_TERMSEL_OVERRIDEEN_MASK      (0x20U)
108854 #define USBNC_CTRL2_TERMSEL_OVERRIDEEN_SHIFT     (5U)
108855 /*! TERMSEL_OVERRIDEEN
108856  *  0b0..The state of the UTMI TermSelect signal to the USB PHY is set by the USB controller.
108857  *  0b1..The state of the UTMI TermSelect signal to the USB PHY is set by the value in the USBNC_x_CTRL2[TERMSEL_OVERRIDE] bit field.
108858  */
108859 #define USBNC_CTRL2_TERMSEL_OVERRIDEEN(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_TERMSEL_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_TERMSEL_OVERRIDEEN_MASK)
108860 #define USBNC_CTRL2_OPMODE_OVERRIDE_MASK         (0xC0U)
108861 #define USBNC_CTRL2_OPMODE_OVERRIDE_SHIFT        (6U)
108862 #define USBNC_CTRL2_OPMODE_OVERRIDE(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_OPMODE_OVERRIDE_SHIFT)) & USBNC_CTRL2_OPMODE_OVERRIDE_MASK)
108863 #define USBNC_CTRL2_OPMODE_OVERRIDEEN_MASK       (0x100U)
108864 #define USBNC_CTRL2_OPMODE_OVERRIDEEN_SHIFT      (8U)
108865 /*! OPMODE_OVERRIDEEN
108866  *  0b0..The state of the UTMI OpMode signals to the USB PHY is set by the USB controller.
108867  *  0b1..The state of the UTMI OpMode signals to the USB PHY is set by the values in the USBNC_x_CTRL2[OPMODE_OVERRIDE] bit field.
108868  */
108869 #define USBNC_CTRL2_OPMODE_OVERRIDEEN(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_OPMODE_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_OPMODE_OVERRIDEEN_MASK)
108870 #define USBNC_CTRL2_XCVRSEL_OVERRIDE_MASK        (0x600U)
108871 #define USBNC_CTRL2_XCVRSEL_OVERRIDE_SHIFT       (9U)
108872 #define USBNC_CTRL2_XCVRSEL_OVERRIDE(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_XCVRSEL_OVERRIDE_SHIFT)) & USBNC_CTRL2_XCVRSEL_OVERRIDE_MASK)
108873 #define USBNC_CTRL2_XCVRSEL_OVERRIDEEN_MASK      (0x800U)
108874 #define USBNC_CTRL2_XCVRSEL_OVERRIDEEN_SHIFT     (11U)
108875 /*! XCVRSEL_OVERRIDEEN
108876  *  0b0..The state of the UTMI XcvrSelect signals to the USB PHY is set by the USB controller.
108877  *  0b1..The state of the UTMI XcvrSelect signals to the USB PHY is set by the values in the USBNC_x_CTRL2[XCVRSEL_OVERRIDE] bit field.
108878  */
108879 #define USBNC_CTRL2_XCVRSEL_OVERRIDEEN(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_XCVRSEL_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_XCVRSEL_OVERRIDEEN_MASK)
108880 #define USBNC_CTRL2_DPPULLDOWN_OVERRIDE_MASK     (0x1000U)
108881 #define USBNC_CTRL2_DPPULLDOWN_OVERRIDE_SHIFT    (12U)
108882 /*! DPPULLDOWN_OVERRIDE
108883  *  0b0..DP pulldown resistor disabled
108884  *  0b1..DP pulldown resistor enabled
108885  */
108886 #define USBNC_CTRL2_DPPULLDOWN_OVERRIDE(x)       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DPPULLDOWN_OVERRIDE_SHIFT)) & USBNC_CTRL2_DPPULLDOWN_OVERRIDE_MASK)
108887 #define USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN_MASK   (0x2000U)
108888 #define USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN_SHIFT  (13U)
108889 /*! DPPULLDOWN_OVERRIDEEN
108890  *  0b0..USB controller enables/disables the DP pulldown resistor in the USB PHY.
108891  *  0b1..Use the value set by the USBNC_n_CTRL2[DPPULLDOWN_OVERRIDE] bit field to enable/disable the DP pulldown resistor in the USB PHY.
108892  */
108893 #define USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN(x)     (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN_MASK)
108894 #define USBNC_CTRL2_DMPULLDOWN_OVERRIDE_MASK     (0x4000U)
108895 #define USBNC_CTRL2_DMPULLDOWN_OVERRIDE_SHIFT    (14U)
108896 /*! DMPULLDOWN_OVERRIDE
108897  *  0b0..DM pulldown resistor disabled
108898  *  0b1..DM pulldown resistor enabled
108899  */
108900 #define USBNC_CTRL2_DMPULLDOWN_OVERRIDE(x)       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DMPULLDOWN_OVERRIDE_SHIFT)) & USBNC_CTRL2_DMPULLDOWN_OVERRIDE_MASK)
108901 #define USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN_MASK   (0x8000U)
108902 #define USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN_SHIFT  (15U)
108903 /*! DMPULLDOWN_OVERRIDEEN
108904  *  0b0..USB controller enables/disables the DM pulldown resistor in the USB PHY.
108905  *  0b1..Use the value set by the USBNC_n_CTRL2[DMPULLDOWN_OVERRIDE] bit field to enable/disable the DM pulldown resistor in the USB PHY.
108906  */
108907 #define USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN(x)     (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN_MASK)
108908 #define USBNC_CTRL2_DIG_ID_SEL_MASK              (0x100000U)
108909 #define USBNC_CTRL2_DIG_ID_SEL_SHIFT             (20U)
108910 /*! DIG_ID_SEL
108911  *  0b0..Use the USB_OTG*_ID pin for the USB OTG ID pin detection function(default)
108912  *  0b1..Use the pin configured by the IOMUXC_USB_OTG*_ID_SELECT_INPUT register for the USB OTG ID pin detection function
108913  */
108914 #define USBNC_CTRL2_DIG_ID_SEL(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DIG_ID_SEL_SHIFT)) & USBNC_CTRL2_DIG_ID_SEL_MASK)
108915 #define USBNC_CTRL2_UTMI_CLK_VLD_MASK            (0x80000000U)
108916 #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT           (31U)
108917 /*! UTMI_CLK_VLD
108918  *  0b0..UTMI clock to USB PHY is not toggling (Default)
108919  *  0b1..UTMI clock to USB PHY has toggled several times
108920  */
108921 #define USBNC_CTRL2_UTMI_CLK_VLD(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)
108922 /*! @} */
108923 
108924 /*! @name PHY_CFG1 - USB OTG PHY Configuration Register 1 */
108925 /*! @{ */
108926 #define USBNC_PHY_CFG1_COMMONONN_MASK            (0x1U)
108927 #define USBNC_PHY_CFG1_COMMONONN_SHIFT           (0U)
108928 /*! COMMONONN - Common Block Power-Down Control
108929  *  0b0..In Suspend or Sleep modes, the Bias and PLL blocks remain powered
108930  *  0b1..In Suspend or Sleep modes, the Bias and PLL blocks are powered down
108931  *  0b0..
108932  */
108933 #define USBNC_PHY_CFG1_COMMONONN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_COMMONONN_SHIFT)) & USBNC_PHY_CFG1_COMMONONN_MASK)
108934 #define USBNC_PHY_CFG1_FSEL_MASK                 (0xEU)
108935 #define USBNC_PHY_CFG1_FSEL_SHIFT                (1U)
108936 /*! FSEL - Reference Clock Frequency Select
108937  *  0b000..9.6 MHz
108938  *  0b001..10 MHz
108939  *  0b010..12 MHz
108940  *  0b011..19.2 MHz
108941  *  0b100..20 MHz
108942  *  0b101..24 MHz (only valid setting for this SOC)
108943  *  0b110..Reserved
108944  *  0b111..50 MHz
108945  */
108946 #define USBNC_PHY_CFG1_FSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_FSEL_SHIFT)) & USBNC_PHY_CFG1_FSEL_MASK)
108947 #define USBNC_PHY_CFG1_COMPDISTUNE0_MASK         (0x70U)
108948 #define USBNC_PHY_CFG1_COMPDISTUNE0_SHIFT        (4U)
108949 /*! COMPDISTUNE0 - Disconnect Threshold Adjustment
108950  *  0b000..-6%
108951  *  0b001..-4.5%
108952  *  0b010..-3%
108953  *  0b011..-1.5%
108954  *  0b100..Design default
108955  *  0b101..+1.5%
108956  *  0b110..+3%
108957  *  0b111..+4.5%
108958  */
108959 #define USBNC_PHY_CFG1_COMPDISTUNE0(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_COMPDISTUNE0_SHIFT)) & USBNC_PHY_CFG1_COMPDISTUNE0_MASK)
108960 #define USBNC_PHY_CFG1_SQRXTUNE0_MASK            (0x380U)
108961 #define USBNC_PHY_CFG1_SQRXTUNE0_SHIFT           (7U)
108962 /*! SQRXTUNE0 - Squelch Threshold Adjustment
108963  *  0b000..+15%
108964  *  0b001..+10%
108965  *  0b010..+5%
108966  *  0b011..Design default
108967  *  0b100..-5%
108968  *  0b101..-10%
108969  *  0b110..-15%
108970  *  0b111..-20%
108971  */
108972 #define USBNC_PHY_CFG1_SQRXTUNE0(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_SQRXTUNE0_SHIFT)) & USBNC_PHY_CFG1_SQRXTUNE0_MASK)
108973 #define USBNC_PHY_CFG1_OTGTUNE0_MASK             (0x1C00U)
108974 #define USBNC_PHY_CFG1_OTGTUNE0_SHIFT            (10U)
108975 /*! OTGTUNE0 - VBUS Valid Threshold Adjustment
108976  *  0b000..-6%
108977  *  0b001..-4.5%
108978  *  0b010..-3%
108979  *  0b011..-1.5%
108980  *  0b100..Design default
108981  *  0b101..+1.5%
108982  *  0b110..+3%
108983  *  0b111..+4.5%
108984  */
108985 #define USBNC_PHY_CFG1_OTGTUNE0(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_OTGTUNE0_SHIFT)) & USBNC_PHY_CFG1_OTGTUNE0_MASK)
108986 #define USBNC_PHY_CFG1_TXHSXVTUNE0_MASK          (0x6000U)
108987 #define USBNC_PHY_CFG1_TXHSXVTUNE0_SHIFT         (13U)
108988 /*! TXHSXVTUNE0 - Transmitter High-Speed Crossover Adjustment
108989  *  0b00..Reserved
108990  *  0b01..-15mV
108991  *  0b10..+15mV
108992  *  0b11..Design default
108993  */
108994 #define USBNC_PHY_CFG1_TXHSXVTUNE0(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXHSXVTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXHSXVTUNE0_MASK)
108995 #define USBNC_PHY_CFG1_TXFSLSTUNE0_MASK          (0xF0000U)
108996 #define USBNC_PHY_CFG1_TXFSLSTUNE0_SHIFT         (16U)
108997 /*! TXFSLSTUNE0 - FS/LS Source Impedance Adjustment
108998  *  0b0000..+5%
108999  *  0b0001..+2.5%
109000  *  0b0011..Design default
109001  *  0b0111..-2.5%
109002  *  0b1111..-5%
109003  */
109004 #define USBNC_PHY_CFG1_TXFSLSTUNE0(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXFSLSTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXFSLSTUNE0_MASK)
109005 #define USBNC_PHY_CFG1_TXVREFTUNE0_MASK          (0xF00000U)
109006 #define USBNC_PHY_CFG1_TXVREFTUNE0_SHIFT         (20U)
109007 /*! TXVREFTUNE0 - HS DC Voltage Level Adjustment
109008  *  0b0000..-6%
109009  *  0b0001..-4%
109010  *  0b0010..-2%
109011  *  0b0011..Design default
109012  *  0b0100..+2%
109013  *  0b0101..+4%
109014  *  0b0110..+6%
109015  *  0b0111..+8%
109016  *  0b1000..+10%
109017  *  0b1001..+12%
109018  *  0b1010..+14%
109019  *  0b1011..+16%
109020  *  0b1100..+18%
109021  *  0b1101..+20%
109022  *  0b1110..+22%
109023  *  0b1111..+24%
109024  */
109025 #define USBNC_PHY_CFG1_TXVREFTUNE0(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXVREFTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXVREFTUNE0_MASK)
109026 #define USBNC_PHY_CFG1_TXRISETUNE0_MASK          (0x3000000U)
109027 #define USBNC_PHY_CFG1_TXRISETUNE0_SHIFT         (24U)
109028 /*! TXRISETUNE0 - HS Transmitter Rise/Fall Time Adjustment
109029  *  0b00..-10%
109030  *  0b01..Design default
109031  *  0b10..+15%
109032  *  0b11..+20%
109033  */
109034 #define USBNC_PHY_CFG1_TXRISETUNE0(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXRISETUNE0_SHIFT)) & USBNC_PHY_CFG1_TXRISETUNE0_MASK)
109035 #define USBNC_PHY_CFG1_TXRESTUNE0_MASK           (0xC000000U)
109036 #define USBNC_PHY_CFG1_TXRESTUNE0_SHIFT          (26U)
109037 /*! TXRESTUNE0 - USB Source Impedance Adjustment
109038  *  0b00..Source impedance is increased by approximately 1.5 ohm
109039  *  0b01..Design default
109040  *  0b10..Source impedance is decreased by approximately 2 ohm
109041  *  0b11..Source impedance is decreased by approximately 4 ohm
109042  */
109043 #define USBNC_PHY_CFG1_TXRESTUNE0(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXRESTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXRESTUNE0_MASK)
109044 #define USBNC_PHY_CFG1_TXPREEMPAMPTUNE0_MASK     (0x30000000U)
109045 #define USBNC_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT    (28U)
109046 /*! TXPREEMPAMPTUNE0 - HS Treansmitter Pre-Emphasis Current Control
109047  *  0b00..HS Transmitter pre-emphasis is disabled
109048  *  0b01..HS Transmitter pre-emphasis circuit sources 1X pre-emphasis current (design default)
109049  *  0b10..HS Transmitter pre-emphasis circuit sources 2X pre-emphasis current
109050  *  0b11..HS Transmitter pre-emphasis circuit sources 3X pre-emphasis current
109051  */
109052 #define USBNC_PHY_CFG1_TXPREEMPAMPTUNE0(x)       (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXPREEMPAMPTUNE0_MASK)
109053 #define USBNC_PHY_CFG1_TXPREEMPPULSETUNE0_MASK   (0x40000000U)
109054 #define USBNC_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT  (30U)
109055 /*! TXPREEMPPULSETUNE0 - HS Transmitter Pre-Emphasis Duration Control
109056  *  0b0..2X, long pre-emphasis current duration (design default)
109057  *  0b1..1X, short pre-emphasis current duration
109058  */
109059 #define USBNC_PHY_CFG1_TXPREEMPPULSETUNE0(x)     (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT)) & USBNC_PHY_CFG1_TXPREEMPPULSETUNE0_MASK)
109060 #define USBNC_PHY_CFG1_CHRGDET_Megamix_MASK      (0x80000000U)
109061 #define USBNC_PHY_CFG1_CHRGDET_Megamix_SHIFT     (31U)
109062 /*! CHRGDET_Megamix - USB_OTG1_CHD_B output control
109063  *  0b0..The external state of USB_OTG1_CHD_B is only controlled by the state of the CHRGDET signal
109064  *  0b1..The external state of USB_OTG1_CHD_B is forced low
109065  */
109066 #define USBNC_PHY_CFG1_CHRGDET_Megamix(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_CHRGDET_Megamix_SHIFT)) & USBNC_PHY_CFG1_CHRGDET_Megamix_MASK)
109067 /*! @} */
109068 
109069 /*! @name PHY_CFG2 - USB OTG PHY Configuration Register 2 */
109070 /*! @{ */
109071 #define USBNC_PHY_CFG2_CHRGSEL_MASK              (0x1U)
109072 #define USBNC_PHY_CFG2_CHRGSEL_SHIFT             (0U)
109073 /*! CHRGSEL - Battery Charging Source Select
109074  *  0b0..VDP_SRC is connected to USB_OTG*_DP and IDM_SINK is connected to USB_OTG*_DN. Used for Primary Detection.
109075  *  0b1..VDM_SRC is connected to USB_OTG*_DN and IDP_SINK is connected to USB_OTG*_DP. Used for Secondary Detection.
109076  */
109077 #define USBNC_PHY_CFG2_CHRGSEL(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_CHRGSEL_SHIFT)) & USBNC_PHY_CFG2_CHRGSEL_MASK)
109078 #define USBNC_PHY_CFG2_VDATDETENB0_MASK          (0x2U)
109079 #define USBNC_PHY_CFG2_VDATDETENB0_SHIFT         (1U)
109080 /*! VDATDETENB0 - Battery Charging Detection Comparator Enable
109081  *  0b0..Battery Charging detection comparator connected to USB_OTG*_D* pin is disabled
109082  *  0b1..Battery Charging detection comparator connected to USB_OTG*_D* pin is enabled
109083  */
109084 #define USBNC_PHY_CFG2_VDATDETENB0(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_VDATDETENB0_SHIFT)) & USBNC_PHY_CFG2_VDATDETENB0_MASK)
109085 #define USBNC_PHY_CFG2_VDATSRCENB0_MASK          (0x4U)
109086 #define USBNC_PHY_CFG2_VDATSRCENB0_SHIFT         (2U)
109087 /*! VDATSRCENB0 - Battery Charging Source Select
109088  *  0b0..VD*_SRC and ID*_SINK are disabled
109089  *  0b1..VD*_SRC and ID*_SINK are enabled
109090  */
109091 #define USBNC_PHY_CFG2_VDATSRCENB0(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_VDATSRCENB0_SHIFT)) & USBNC_PHY_CFG2_VDATSRCENB0_MASK)
109092 #define USBNC_PHY_CFG2_DCDENB_MASK               (0x8U)
109093 #define USBNC_PHY_CFG2_DCDENB_SHIFT              (3U)
109094 /*! DCDENB - Data Contact Detection Enable
109095  *  0b0..IDP_SRC current and RDM_DWN pull-down resistance are disabled
109096  *  0b1..IDP_SRC current and RDM_DWN pull-down resistance are enabled
109097  */
109098 #define USBNC_PHY_CFG2_DCDENB(x)                 (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_DCDENB_SHIFT)) & USBNC_PHY_CFG2_DCDENB_MASK)
109099 #define USBNC_PHY_CFG2_ACAENB0_MASK              (0x10U)
109100 #define USBNC_PHY_CFG2_ACAENB0_SHIFT             (4U)
109101 /*! ACAENB0 - ACA USB_OTG*_ID Pin Resistance Detection Enable
109102  *  0b0..Disables detection of resistance on the USB_OTG*_ID pin
109103  *  0b1..Enables detection of resistance on the USB_OTG*_ID pin
109104  */
109105 #define USBNC_PHY_CFG2_ACAENB0(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_ACAENB0_SHIFT)) & USBNC_PHY_CFG2_ACAENB0_MASK)
109106 #define USBNC_PHY_CFG2_SLEEPM0_MASK              (0x20U)
109107 #define USBNC_PHY_CFG2_SLEEPM0_SHIFT             (5U)
109108 /*! SLEEPM0 - Sleep Mode Assertion
109109  *  0b0..Sleep mode
109110  *  0b1..Normal operating mode
109111  */
109112 #define USBNC_PHY_CFG2_SLEEPM0(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_SLEEPM0_SHIFT)) & USBNC_PHY_CFG2_SLEEPM0_MASK)
109113 #define USBNC_PHY_CFG2_LOOPBACKENB0_MASK         (0x40U)
109114 #define USBNC_PHY_CFG2_LOOPBACKENB0_SHIFT        (6U)
109115 /*! LOOPBACKENB0 - Loopback Test Enable
109116  *  0b0..During data transmission, the receive logic is disabled
109117  *  0b1..During data transmission, the receive logic is enabled
109118  */
109119 #define USBNC_PHY_CFG2_LOOPBACKENB0(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_LOOPBACKENB0_SHIFT)) & USBNC_PHY_CFG2_LOOPBACKENB0_MASK)
109120 #define USBNC_PHY_CFG2_TXBITSTUFFEN0_MASK        (0x100U)
109121 #define USBNC_PHY_CFG2_TXBITSTUFFEN0_SHIFT       (8U)
109122 /*! TXBITSTUFFEN0 - Low-Byte Transmit Bit-Stuffing Enable
109123  *  0b0..Bit stuffing is disabled
109124  *  0b1..Bit stuffing is enabled
109125  */
109126 #define USBNC_PHY_CFG2_TXBITSTUFFEN0(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_TXBITSTUFFEN0_SHIFT)) & USBNC_PHY_CFG2_TXBITSTUFFEN0_MASK)
109127 #define USBNC_PHY_CFG2_TXBITSTUFFENH0_MASK       (0x200U)
109128 #define USBNC_PHY_CFG2_TXBITSTUFFENH0_SHIFT      (9U)
109129 /*! TXBITSTUFFENH0 - High-Byte Transmit Bit-Stuffing Enable
109130  *  0b0..Bit stuffing is disabled
109131  *  0b1..Bit stuffing is enabled
109132  */
109133 #define USBNC_PHY_CFG2_TXBITSTUFFENH0(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_TXBITSTUFFENH0_SHIFT)) & USBNC_PHY_CFG2_TXBITSTUFFENH0_MASK)
109134 #define USBNC_PHY_CFG2_OTGDISABLE0_MASK          (0x400U)
109135 #define USBNC_PHY_CFG2_OTGDISABLE0_SHIFT         (10U)
109136 /*! OTGDISABLE0 - OTG Block Disable
109137  *  0b0..The OTG block is powered up
109138  *  0b1..The OTG block is powered down
109139  */
109140 #define USBNC_PHY_CFG2_OTGDISABLE0(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_OTGDISABLE0_SHIFT)) & USBNC_PHY_CFG2_OTGDISABLE0_MASK)
109141 #define USBNC_PHY_CFG2_ADPCHRG0_MASK             (0x800U)
109142 #define USBNC_PHY_CFG2_ADPCHRG0_SHIFT            (11U)
109143 /*! ADPCHRG0 - VBUS Input ADP Charge Enable
109144  *  0b0..Disables charging USB_OTG*_VBUS during ADP
109145  *  0b1..Disables charging USB_OTG*_VBUS during ADP
109146  */
109147 #define USBNC_PHY_CFG2_ADPCHRG0(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_ADPCHRG0_SHIFT)) & USBNC_PHY_CFG2_ADPCHRG0_MASK)
109148 #define USBNC_PHY_CFG2_ADPDISCHRG0_MASK          (0x1000U)
109149 #define USBNC_PHY_CFG2_ADPDISCHRG0_SHIFT         (12U)
109150 /*! ADPDISCHRG0 - VBUS Input ADP Discharge Enable
109151  *  0b0..Disables discharging USB_OTG*_VBUS during ADP
109152  *  0b1..Enables discharging USB_OTG*_VBUS during ADP
109153  */
109154 #define USBNC_PHY_CFG2_ADPDISCHRG0(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_ADPDISCHRG0_SHIFT)) & USBNC_PHY_CFG2_ADPDISCHRG0_MASK)
109155 #define USBNC_PHY_CFG2_ADPPRBENB0_MASK           (0x2000U)
109156 #define USBNC_PHY_CFG2_ADPPRBENB0_SHIFT          (13U)
109157 /*! ADPPRBENB0 - ADP Probe Enable
109158  *  0b0..ADP Probe comparator is disabled
109159  *  0b1..ADP Probe comparator is enabled
109160  */
109161 #define USBNC_PHY_CFG2_ADPPRBENB0(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_ADPPRBENB0_SHIFT)) & USBNC_PHY_CFG2_ADPPRBENB0_MASK)
109162 #define USBNC_PHY_CFG2_VBUSVLDEXTSEL0_MASK       (0x4000U)
109163 #define USBNC_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT      (14U)
109164 /*! VBUSVLDEXTSEL0 - External VBUS Valid Select
109165  *  0b0..The USB OTG PHY internal Session Valid comparator is used to enable the pull-up resistor on the USB_OTG*_DP pin
109166  *  0b1..The VBUSVLDEXT signal is used to enable the pull-up resistor on the USB_OTG*_DP pin
109167  */
109168 #define USBNC_PHY_CFG2_VBUSVLDEXTSEL0(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT)) & USBNC_PHY_CFG2_VBUSVLDEXTSEL0_MASK)
109169 #define USBNC_PHY_CFG2_VBUSVLDEXT_MASK           (0x8000U)
109170 #define USBNC_PHY_CFG2_VBUSVLDEXT_SHIFT          (15U)
109171 /*! VBUSVLDEXT - External VBUS Valid Indicator
109172  *  0b0..The VBUS signal sensed outside the USB OTG PHY is not valid, and the pull-up resistor on USB_OTG*_DP is disabled
109173  *  0b1..The VBUS signal sensed outside the USB OTG PHY is valid, and the pull-up resistor on USB_OTG*_DP is enabled
109174  */
109175 #define USBNC_PHY_CFG2_VBUSVLDEXT(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_VBUSVLDEXT_SHIFT)) & USBNC_PHY_CFG2_VBUSVLDEXT_MASK)
109176 #define USBNC_PHY_CFG2_DRVVBUS0_MASK             (0x10000U)
109177 #define USBNC_PHY_CFG2_DRVVBUS0_SHIFT            (16U)
109178 /*! DRVVBUS0 - VBUS Valid Comparator Enable
109179  *  0b0..The VBUS Valid comparator is disabled
109180  *  0b1..The VBUS Valid comparator is enabled
109181  */
109182 #define USBNC_PHY_CFG2_DRVVBUS0(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_DRVVBUS0_SHIFT)) & USBNC_PHY_CFG2_DRVVBUS0_MASK)
109183 /*! @} */
109184 
109185 /*! @name PHY_STATUS - USB OTG PHY Status Register */
109186 /*! @{ */
109187 #define USBNC_PHY_STATUS_LINE_STATE_MASK         (0x3U)
109188 #define USBNC_PHY_STATUS_LINE_STATE_SHIFT        (0U)
109189 /*! LINE_STATE - Line State Indicator outputs from USB OTG PHY
109190  *  0b00..SE0 (DP low, DN low)
109191  *  0b01..J state for high-speed and full-speed USB traffic; K state for low-speed USB traffic (DP high, DN low)
109192  *  0b10..K state for high-speed and full-speed USB traffic; J state for low-speed USB traffic (DP low, DN high)
109193  *  0b11..SE1 (DP high, DN high)
109194  */
109195 #define USBNC_PHY_STATUS_LINE_STATE(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_LINE_STATE_SHIFT)) & USBNC_PHY_STATUS_LINE_STATE_MASK)
109196 #define USBNC_PHY_STATUS_SESS_VLD_MASK           (0x4U)
109197 #define USBNC_PHY_STATUS_SESS_VLD_SHIFT          (2U)
109198 /*! SESS_VLD - OTG Device Session Valid Indicator from USB OTG PHY
109199  *  0b0..The voltage on USB_OTG*_VBUS is below the OTG Device Session Valid threshold
109200  *  0b1..The voltage on USB_OTG*_VBUS is above the OTG Device Session Valid threshold
109201  */
109202 #define USBNC_PHY_STATUS_SESS_VLD(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_SESS_VLD_SHIFT)) & USBNC_PHY_STATUS_SESS_VLD_MASK)
109203 #define USBNC_PHY_STATUS_VBUS_VLD_MASK           (0x8U)
109204 #define USBNC_PHY_STATUS_VBUS_VLD_SHIFT          (3U)
109205 /*! VBUS_VLD - VBUS Valid Indicator from USB OTG PHY
109206  *  0b0..The voltage on USB_OTG*_VBUS is below the VBUS Valid threshold
109207  *  0b1..The voltage on USB_OTG*_VBUS is above the VBUS Valid threshold
109208  */
109209 #define USBNC_PHY_STATUS_VBUS_VLD(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_VBUS_VLD_SHIFT)) & USBNC_PHY_STATUS_VBUS_VLD_MASK)
109210 #define USBNC_PHY_STATUS_ID_DIG_MASK             (0x10U)
109211 #define USBNC_PHY_STATUS_ID_DIG_SHIFT            (4U)
109212 /*! ID_DIG - Micro- or Mini- A/B Plug Indicator
109213  *  0b0..The connnected plug is a Micro- or Mini-A plug
109214  *  0b1..The connnected plug is a Micro- or Mini-B plug
109215  */
109216 #define USBNC_PHY_STATUS_ID_DIG(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_ID_DIG_SHIFT)) & USBNC_PHY_STATUS_ID_DIG_MASK)
109217 #define USBNC_PHY_STATUS_HOST_DISCONNECT_MASK    (0x20U)
109218 #define USBNC_PHY_STATUS_HOST_DISCONNECT_SHIFT   (5U)
109219 /*! HOST_DISCONNECT - Peripheral Disconnect Indicator
109220  *  0b0..Peripheral is connected
109221  *  0b1..No peripheral is connected
109222  */
109223 #define USBNC_PHY_STATUS_HOST_DISCONNECT(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_HOST_DISCONNECT_SHIFT)) & USBNC_PHY_STATUS_HOST_DISCONNECT_MASK)
109224 #define USBNC_PHY_STATUS_RIDC0_MASK              (0x1000000U)
109225 #define USBNC_PHY_STATUS_RIDC0_SHIFT             (24U)
109226 /*! RIDC0 - ACA USB_OTG*_ID Pin Resistance Indicator
109227  *  0b0..ACA OTG_ID pin resistance is >= RID_B (min) and <= RID_GND max
109228  *  0b1..ACA OTG_ID pin resistance is >= RID_C (min) and <= RID_C max
109229  */
109230 #define USBNC_PHY_STATUS_RIDC0(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDC0_SHIFT)) & USBNC_PHY_STATUS_RIDC0_MASK)
109231 #define USBNC_PHY_STATUS_RIDB0_MASK              (0x2000000U)
109232 #define USBNC_PHY_STATUS_RIDB0_SHIFT             (25U)
109233 /*! RIDB0 - ACA USB_OTG*_ID Pin Resistance Indicator
109234  *  0b0..ACA OTG_ID pin resistance is >= RID_A (min) and <= RID_C max
109235  *  0b1..ACA OTG_ID pin resistance is >= RID_B (min) and <= RID_B max
109236  */
109237 #define USBNC_PHY_STATUS_RIDB0(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDB0_SHIFT)) & USBNC_PHY_STATUS_RIDB0_MASK)
109238 #define USBNC_PHY_STATUS_RIDA0_MASK              (0x4000000U)
109239 #define USBNC_PHY_STATUS_RIDA0_SHIFT             (26U)
109240 /*! RIDA0 - ACA USB_OTG*_ID Pin Resistance Indicator
109241  *  0b0..ACA OTG_ID pin resistance is >= RID_FLOAT (min) and <= RID_B max
109242  *  0b1..ACA OTG_ID pin resistance is >= RID_A (min) and <= RID_A max
109243  */
109244 #define USBNC_PHY_STATUS_RIDA0(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDA0_SHIFT)) & USBNC_PHY_STATUS_RIDA0_MASK)
109245 #define USBNC_PHY_STATUS_RIDGND0_MASK            (0x8000000U)
109246 #define USBNC_PHY_STATUS_RIDGND0_SHIFT           (27U)
109247 /*! RIDGND0 - ACA USB_OTG*_ID Pin Resistance Indicator
109248  *  0b0..ACA OTG_ID pin resistance is >= RID_C (min)
109249  *  0b1..ACA OTG_ID pin resistance is <= RID_GND (max)
109250  */
109251 #define USBNC_PHY_STATUS_RIDGND0(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDGND0_SHIFT)) & USBNC_PHY_STATUS_RIDGND0_MASK)
109252 #define USBNC_PHY_STATUS_RIDFLOAT0_MASK          (0x10000000U)
109253 #define USBNC_PHY_STATUS_RIDFLOAT0_SHIFT         (28U)
109254 /*! RIDFLOAT0 - ACA USB_OTG*_ID Pin Resistance Indicator
109255  *  0b0..ACA OTG_ID pin resistance is <= RID_A (max)
109256  *  0b1..ACA OTG_ID pin resistance is >= RID_FLOAT (min)
109257  */
109258 #define USBNC_PHY_STATUS_RIDFLOAT0(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDFLOAT0_SHIFT)) & USBNC_PHY_STATUS_RIDFLOAT0_MASK)
109259 #define USBNC_PHY_STATUS_CHRGDET_MASK            (0x20000000U)
109260 #define USBNC_PHY_STATUS_CHRGDET_SHIFT           (29U)
109261 /*! CHRGDET - Battery Charger Detection Output
109262  *  0b0..VD* < VDAT_REF
109263  *  0b1..VD* > VDAT_REF
109264  */
109265 #define USBNC_PHY_STATUS_CHRGDET(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_CHRGDET_SHIFT)) & USBNC_PHY_STATUS_CHRGDET_MASK)
109266 #define USBNC_PHY_STATUS_ADPPRB0_MASK            (0x40000000U)
109267 #define USBNC_PHY_STATUS_ADPPRB0_SHIFT           (30U)
109268 /*! ADPPRB0 - ADP Probe Indicator
109269  *  0b0..The voltage on USB_OTG*_VBUS is below the ADP probing voltage
109270  *  0b1..The voltage on USB_OTG*_VBUS is above the ADP probing voltage
109271  */
109272 #define USBNC_PHY_STATUS_ADPPRB0(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_ADPPRB0_SHIFT)) & USBNC_PHY_STATUS_ADPPRB0_MASK)
109273 #define USBNC_PHY_STATUS_ADPSNS0_MASK            (0x80000000U)
109274 #define USBNC_PHY_STATUS_ADPSNS0_SHIFT           (31U)
109275 /*! ADPSNS0 - ADP Sense Indicator
109276  *  0b0..The voltage on USB_OTG*_VBUS is below the ADP sensing voltage
109277  *  0b1..The voltage on USB_OTG*_VBUS is above the ADP sensing voltage
109278  */
109279 #define USBNC_PHY_STATUS_ADPSNS0(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_ADPSNS0_SHIFT)) & USBNC_PHY_STATUS_ADPSNS0_MASK)
109280 /*! @} */
109281 
109282 /*! @name ADP_CFG1 -  */
109283 /*! @{ */
109284 #define USBNC_ADP_CFG1_ADP_WAIT_MASK             (0x3FFFFU)
109285 #define USBNC_ADP_CFG1_ADP_WAIT_SHIFT            (0U)
109286 /*! ADP_WAIT
109287  *  0b001100000000000000..Default
109288  */
109289 #define USBNC_ADP_CFG1_ADP_WAIT(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_WAIT_SHIFT)) & USBNC_ADP_CFG1_ADP_WAIT_MASK)
109290 #define USBNC_ADP_CFG1_TIMER_EN_MASK             (0x100000U)
109291 #define USBNC_ADP_CFG1_TIMER_EN_SHIFT            (20U)
109292 /*! TIMER_EN - ADP Timer Test Enable
109293  *  0b0..Default
109294  */
109295 #define USBNC_ADP_CFG1_TIMER_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_TIMER_EN_SHIFT)) & USBNC_ADP_CFG1_TIMER_EN_MASK)
109296 #define USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK       (0x200000U)
109297 #define USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT      (21U)
109298 /*! ADP_SNS_INT_EN - ADP Sense Interrupt Enable
109299  *  0b0..Default
109300  */
109301 #define USBNC_ADP_CFG1_ADP_SNS_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK)
109302 #define USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK       (0x400000U)
109303 #define USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT      (22U)
109304 /*! ADP_PRB_INT_EN
109305  *  0b0..Default
109306  */
109307 #define USBNC_ADP_CFG1_ADP_PRB_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK)
109308 #define USBNC_ADP_CFG1_ADP_PRB_EN_MASK           (0x800000U)
109309 #define USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT          (23U)
109310 /*! ADP_PRB_EN
109311  *  0b0..Default
109312  */
109313 #define USBNC_ADP_CFG1_ADP_PRB_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_PRB_EN_MASK)
109314 /*! @} */
109315 
109316 /*! @name ADP_CFG2 -  */
109317 /*! @{ */
109318 #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK       (0x7FU)
109319 #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT      (0U)
109320 /*! ADP_CHRG_DELTA
109321  *  0b0010000..Default
109322  */
109323 #define USBNC_ADP_CFG2_ADP_CHRG_DELTA(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK)
109324 #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK       (0x80U)
109325 #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT      (7U)
109326 /*! ADP_CHRG_SWCMP
109327  *  0b0..Default
109328  */
109329 #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK)
109330 #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK      (0xFF00U)
109331 #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT     (8U)
109332 /*! ADP_CHRG_SWTIME
109333  *  0b01000000..Default
109334  */
109335 #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK)
109336 #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK      (0xFF0000U)
109337 #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT     (16U)
109338 /*! ADP_DISCHG_TIME - ADP Discharge time
109339  *  0b01000110..Default
109340  */
109341 #define USBNC_ADP_CFG2_ADP_DISCHG_TIME(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT)) & USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK)
109342 /*! @} */
109343 
109344 /*! @name ADP_STATUS -  */
109345 /*! @{ */
109346 #define USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK       (0xFFU)
109347 #define USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT      (0U)
109348 /*! ADP_PRB_TIMR - ADP Probe Time
109349  *  0b00000000..Default
109350  */
109351 #define USBNC_ADP_STATUS_ADP_PRB_TIMR(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT)) & USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK)
109352 #define USBNC_ADP_STATUS_ADP_CNT_MASK            (0x3FFFF00U)
109353 #define USBNC_ADP_STATUS_ADP_CNT_SHIFT           (8U)
109354 /*! ADP_CNT - ADP Internal 18-bit Counter
109355  */
109356 #define USBNC_ADP_STATUS_ADP_CNT(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_CNT_SHIFT)) & USBNC_ADP_STATUS_ADP_CNT_MASK)
109357 #define USBNC_ADP_STATUS_ADP_SNS_INT_MASK        (0x4000000U)
109358 #define USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT       (26U)
109359 /*! ADP_SNS_INT - ADP Sense Interrupt Status
109360  *  0b0..Default
109361  */
109362 #define USBNC_ADP_STATUS_ADP_SNS_INT(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT)) & USBNC_ADP_STATUS_ADP_SNS_INT_MASK)
109363 #define USBNC_ADP_STATUS_ADP_PRB_INT_MASK        (0x8000000U)
109364 #define USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT       (27U)
109365 /*! ADP_PRB_INT - ADP Probe Interrupt Status
109366  *  0b0..Default
109367  */
109368 #define USBNC_ADP_STATUS_ADP_PRB_INT(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT)) & USBNC_ADP_STATUS_ADP_PRB_INT_MASK)
109369 /*! @} */
109370 
109371 
109372 /*!
109373  * @}
109374  */ /* end of group USBNC_Register_Masks */
109375 
109376 
109377 /* USBNC - Peripheral instance base addresses */
109378 /** Peripheral CONNECTIVITY__USBNC base address */
109379 #define CONNECTIVITY__USBNC_BASE                 (0x5B0D0000u)
109380 /** Peripheral CONNECTIVITY__USBNC base pointer */
109381 #define CONNECTIVITY__USBNC                      ((USBNC_Type *)CONNECTIVITY__USBNC_BASE)
109382 /** Array initializer of USBNC peripheral base addresses */
109383 #define USBNC_BASE_ADDRS                         { CONNECTIVITY__USBNC_BASE }
109384 /** Array initializer of USBNC peripheral base pointers */
109385 #define USBNC_BASE_PTRS                          { CONNECTIVITY__USBNC }
109386 
109387 /*!
109388  * @}
109389  */ /* end of group USBNC_Peripheral_Access_Layer */
109390 
109391 
109392 /* ----------------------------------------------------------------------------
109393    -- USBPHY Peripheral Access Layer
109394    ---------------------------------------------------------------------------- */
109395 
109396 /*!
109397  * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
109398  * @{
109399  */
109400 
109401 /** USBPHY - Register Layout Typedef */
109402 typedef struct {
109403   __IO uint32_t PWD;                               /**< USB PHY Power-Down Register, offset: 0x0 */
109404   __IO uint32_t PWD_SET;                           /**< USB PHY Power-Down Register, offset: 0x4 */
109405   __IO uint32_t PWD_CLR;                           /**< USB PHY Power-Down Register, offset: 0x8 */
109406   __IO uint32_t PWD_TOG;                           /**< USB PHY Power-Down Register, offset: 0xC */
109407   __IO uint32_t TX;                                /**< USB PHY Transmitter Control Register, offset: 0x10 */
109408   __IO uint32_t TX_SET;                            /**< USB PHY Transmitter Control Register, offset: 0x14 */
109409   __IO uint32_t TX_CLR;                            /**< USB PHY Transmitter Control Register, offset: 0x18 */
109410   __IO uint32_t TX_TOG;                            /**< USB PHY Transmitter Control Register, offset: 0x1C */
109411   __IO uint32_t RX;                                /**< USB PHY Receiver Control Register, offset: 0x20 */
109412   __IO uint32_t RX_SET;                            /**< USB PHY Receiver Control Register, offset: 0x24 */
109413   __IO uint32_t RX_CLR;                            /**< USB PHY Receiver Control Register, offset: 0x28 */
109414   __IO uint32_t RX_TOG;                            /**< USB PHY Receiver Control Register, offset: 0x2C */
109415   __IO uint32_t CTRL;                              /**< USB PHY General Control Register, offset: 0x30 */
109416   __IO uint32_t CTRL_SET;                          /**< USB PHY General Control Register, offset: 0x34 */
109417   __IO uint32_t CTRL_CLR;                          /**< USB PHY General Control Register, offset: 0x38 */
109418   __IO uint32_t CTRL_TOG;                          /**< USB PHY General Control Register, offset: 0x3C */
109419   __IO uint32_t STATUS;                            /**< USB PHY Status Register, offset: 0x40 */
109420        uint8_t RESERVED_0[12];
109421   __IO uint32_t DEBUG0;                            /**< USB PHY Debug Register 0, offset: 0x50 */
109422   __IO uint32_t DEBUG0_SET;                        /**< USB PHY Debug Register 0, offset: 0x54 */
109423   __IO uint32_t DEBUG0_CLR;                        /**< USB PHY Debug Register 0, offset: 0x58 */
109424   __IO uint32_t DEBUG0_TOG;                        /**< USB PHY Debug Register 0, offset: 0x5C */
109425        uint8_t RESERVED_1[16];
109426   __IO uint32_t DEBUG1;                            /**< UTMI Debug Status Register 1, offset: 0x70 */
109427   __IO uint32_t DEBUG1_SET;                        /**< UTMI Debug Status Register 1, offset: 0x74 */
109428   __IO uint32_t DEBUG1_CLR;                        /**< UTMI Debug Status Register 1, offset: 0x78 */
109429   __IO uint32_t DEBUG1_TOG;                        /**< UTMI Debug Status Register 1, offset: 0x7C */
109430   __I  uint32_t VERSION;                           /**< UTMI RTL Version, offset: 0x80 */
109431        uint8_t RESERVED_2[28];
109432   __IO uint32_t PLL_SIC;                           /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
109433   __IO uint32_t PLL_SIC_SET;                       /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
109434   __IO uint32_t PLL_SIC_CLR;                       /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
109435   __IO uint32_t PLL_SIC_TOG;                       /**< USB PHY PLL Control/Status Register, offset: 0xAC */
109436        uint8_t RESERVED_3[16];
109437   __IO uint32_t USB1_VBUS_DETECT;                  /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
109438   __IO uint32_t USB1_VBUS_DETECT_SET;              /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
109439   __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
109440   __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
109441   __I  uint32_t USB1_VBUS_DET_STAT;                /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
109442        uint8_t RESERVED_4[12];
109443   __IO uint32_t USB1_CHRG_DETECT;                  /**< USB PHY Charger Detect Control Register, offset: 0xE0 */
109444   __IO uint32_t USB1_CHRG_DETECT_SET;              /**< USB PHY Charger Detect Control Register, offset: 0xE4 */
109445   __IO uint32_t USB1_CHRG_DETECT_CLR;              /**< USB PHY Charger Detect Control Register, offset: 0xE8 */
109446   __IO uint32_t USB1_CHRG_DETECT_TOG;              /**< USB PHY Charger Detect Control Register, offset: 0xEC */
109447   __I  uint32_t USB1_CHRG_DET_STAT;                /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
109448        uint8_t RESERVED_5[12];
109449   __IO uint32_t ANACTRL;                           /**< USB PHY Analog Control Register, offset: 0x100 */
109450   __IO uint32_t ANACTRL_SET;                       /**< USB PHY Analog Control Register, offset: 0x104 */
109451   __IO uint32_t ANACTRL_CLR;                       /**< USB PHY Analog Control Register, offset: 0x108 */
109452   __IO uint32_t ANACTRL_TOG;                       /**< USB PHY Analog Control Register, offset: 0x10C */
109453   __IO uint32_t USB1_LOOPBACK;                     /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
109454   __IO uint32_t USB1_LOOPBACK_SET;                 /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
109455   __IO uint32_t USB1_LOOPBACK_CLR;                 /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
109456   __IO uint32_t USB1_LOOPBACK_TOG;                 /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
109457   __IO uint32_t USB1_LOOPBACK_HSFSCNT;             /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
109458   __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
109459   __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
109460   __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
109461   __IO uint32_t TRIM_OVERRIDE_EN;                  /**< USB PHY Trim Override Enable Register, offset: 0x130 */
109462   __IO uint32_t TRIM_OVERRIDE_EN_SET;              /**< USB PHY Trim Override Enable Register, offset: 0x134 */
109463   __IO uint32_t TRIM_OVERRIDE_EN_CLR;              /**< USB PHY Trim Override Enable Register, offset: 0x138 */
109464   __IO uint32_t TRIM_OVERRIDE_EN_TOG;              /**< USB PHY Trim Override Enable Register, offset: 0x13C */
109465 } USBPHY_Type;
109466 
109467 /* ----------------------------------------------------------------------------
109468    -- USBPHY Register Masks
109469    ---------------------------------------------------------------------------- */
109470 
109471 /*!
109472  * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
109473  * @{
109474  */
109475 
109476 /*! @name PWD - USB PHY Power-Down Register */
109477 /*! @{ */
109478 #define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
109479 #define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
109480 /*! TXPWDFS
109481  *  0b0..Normal operation.
109482  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
109483  */
109484 #define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
109485 #define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
109486 #define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
109487 /*! TXPWDIBIAS
109488  *  0b0..Normal operation
109489  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
109490  *       is in suspend mode. This effectively powers down the entire USB transmit path
109491  */
109492 #define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
109493 #define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
109494 #define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
109495 /*! TXPWDV2I
109496  *  0b0..Normal operation.
109497  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
109498  */
109499 #define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
109500 #define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
109501 #define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
109502 /*! RXPWDENV
109503  *  0b0..Normal operation.
109504  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
109505  */
109506 #define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
109507 #define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
109508 #define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
109509 /*! RXPWD1PT1
109510  *  0b0..Normal operation
109511  *  0b1..Power-down the USB full-speed differential receiver.
109512  */
109513 #define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
109514 #define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
109515 #define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
109516 /*! RXPWDDIFF
109517  *  0b0..Normal operation.
109518  *  0b1..Power-down the USB high-speed differential receiver
109519  */
109520 #define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
109521 #define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
109522 #define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
109523 /*! RXPWDRX
109524  *  0b0..Normal operation
109525  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
109526  */
109527 #define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
109528 /*! @} */
109529 
109530 /*! @name PWD_SET - USB PHY Power-Down Register */
109531 /*! @{ */
109532 #define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
109533 #define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
109534 /*! TXPWDFS
109535  *  0b0..Normal operation.
109536  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
109537  */
109538 #define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
109539 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
109540 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
109541 /*! TXPWDIBIAS
109542  *  0b0..Normal operation
109543  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
109544  *       is in suspend mode. This effectively powers down the entire USB transmit path
109545  */
109546 #define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
109547 #define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
109548 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
109549 /*! TXPWDV2I
109550  *  0b0..Normal operation.
109551  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
109552  */
109553 #define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
109554 #define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
109555 #define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
109556 /*! RXPWDENV
109557  *  0b0..Normal operation.
109558  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
109559  */
109560 #define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
109561 #define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
109562 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
109563 /*! RXPWD1PT1
109564  *  0b0..Normal operation
109565  *  0b1..Power-down the USB full-speed differential receiver.
109566  */
109567 #define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
109568 #define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
109569 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
109570 /*! RXPWDDIFF
109571  *  0b0..Normal operation.
109572  *  0b1..Power-down the USB high-speed differential receiver
109573  */
109574 #define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
109575 #define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
109576 #define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
109577 /*! RXPWDRX
109578  *  0b0..Normal operation
109579  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
109580  */
109581 #define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
109582 /*! @} */
109583 
109584 /*! @name PWD_CLR - USB PHY Power-Down Register */
109585 /*! @{ */
109586 #define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
109587 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
109588 /*! TXPWDFS
109589  *  0b0..Normal operation.
109590  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
109591  */
109592 #define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
109593 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
109594 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
109595 /*! TXPWDIBIAS
109596  *  0b0..Normal operation
109597  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
109598  *       is in suspend mode. This effectively powers down the entire USB transmit path
109599  */
109600 #define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
109601 #define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
109602 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
109603 /*! TXPWDV2I
109604  *  0b0..Normal operation.
109605  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
109606  */
109607 #define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
109608 #define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
109609 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
109610 /*! RXPWDENV
109611  *  0b0..Normal operation.
109612  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
109613  */
109614 #define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
109615 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
109616 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
109617 /*! RXPWD1PT1
109618  *  0b0..Normal operation
109619  *  0b1..Power-down the USB full-speed differential receiver.
109620  */
109621 #define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
109622 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
109623 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
109624 /*! RXPWDDIFF
109625  *  0b0..Normal operation.
109626  *  0b1..Power-down the USB high-speed differential receiver
109627  */
109628 #define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
109629 #define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
109630 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
109631 /*! RXPWDRX
109632  *  0b0..Normal operation
109633  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
109634  */
109635 #define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
109636 /*! @} */
109637 
109638 /*! @name PWD_TOG - USB PHY Power-Down Register */
109639 /*! @{ */
109640 #define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
109641 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
109642 /*! TXPWDFS
109643  *  0b0..Normal operation.
109644  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
109645  */
109646 #define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
109647 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
109648 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
109649 /*! TXPWDIBIAS
109650  *  0b0..Normal operation
109651  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
109652  *       is in suspend mode. This effectively powers down the entire USB transmit path
109653  */
109654 #define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
109655 #define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
109656 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
109657 /*! TXPWDV2I
109658  *  0b0..Normal operation.
109659  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
109660  */
109661 #define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
109662 #define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
109663 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
109664 /*! RXPWDENV
109665  *  0b0..Normal operation.
109666  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
109667  */
109668 #define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
109669 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
109670 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
109671 /*! RXPWD1PT1
109672  *  0b0..Normal operation
109673  *  0b1..Power-down the USB full-speed differential receiver.
109674  */
109675 #define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
109676 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
109677 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
109678 /*! RXPWDDIFF
109679  *  0b0..Normal operation.
109680  *  0b1..Power-down the USB high-speed differential receiver
109681  */
109682 #define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
109683 #define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
109684 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
109685 /*! RXPWDRX
109686  *  0b0..Normal operation
109687  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
109688  */
109689 #define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
109690 /*! @} */
109691 
109692 /*! @name TX - USB PHY Transmitter Control Register */
109693 /*! @{ */
109694 #define USBPHY_TX_D_CAL_MASK                     (0xFU)
109695 #define USBPHY_TX_D_CAL_SHIFT                    (0U)
109696 /*! D_CAL
109697  *  0b0000..Maximum current, approximately 19% above nominal.
109698  *  0b0111..Nominal
109699  *  0b1111..Minimum current, approximately 19% below nominal.
109700  */
109701 #define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
109702 #define USBPHY_TX_TXCAL45DM_MASK                 (0xF00U)
109703 #define USBPHY_TX_TXCAL45DM_SHIFT                (8U)
109704 /*! TXCAL45DM
109705  *  0b0000..+19.95%
109706  *  0b0001..+17.35%
109707  *  0b0010..+14.85%
109708  *  0b0011..+12.46%
109709  *  0b0100..+9.07%
109710  *  0b0101..+5.87%
109711  *  0b0110..+2.85%
109712  *  0b0111..0%
109713  *  0b1000..-2.70%
109714  *  0b1001..-5.25%
109715  *  0b1010..-7.67%
109716  *  0b1011..-9.98%
109717  *  0b1100..-12.17%
109718  *  0b1101..-14.25%
109719  *  0b1110..-18.14%
109720  *  0b1111..-21.68%
109721  */
109722 #define USBPHY_TX_TXCAL45DM(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
109723 #define USBPHY_TX_TXENCAL45DM_MASK               (0x2000U)
109724 #define USBPHY_TX_TXENCAL45DM_SHIFT              (13U)
109725 #define USBPHY_TX_TXENCAL45DM(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DM_SHIFT)) & USBPHY_TX_TXENCAL45DM_MASK)
109726 #define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
109727 #define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
109728 /*! TXCAL45DP
109729  *  0b0000..+19.95%
109730  *  0b0001..+17.35%
109731  *  0b0010..+14.85%
109732  *  0b0011..+12.46%
109733  *  0b0100..+9.07%
109734  *  0b0101..+5.87%
109735  *  0b0110..+2.85%
109736  *  0b0111..0%
109737  *  0b1000..-2.70%
109738  *  0b1001..-5.25%
109739  *  0b1010..-7.67%
109740  *  0b1011..-9.98%
109741  *  0b1100..-12.17%
109742  *  0b1101..-14.25%
109743  *  0b1110..-18.14%
109744  *  0b1111..-21.68%
109745  */
109746 #define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
109747 #define USBPHY_TX_TXENCAL45DP_MASK               (0x200000U)
109748 #define USBPHY_TX_TXENCAL45DP_SHIFT              (21U)
109749 #define USBPHY_TX_TXENCAL45DP(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK)
109750 /*! @} */
109751 
109752 /*! @name TX_SET - USB PHY Transmitter Control Register */
109753 /*! @{ */
109754 #define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
109755 #define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
109756 /*! D_CAL
109757  *  0b0000..Maximum current, approximately 19% above nominal.
109758  *  0b0111..Nominal
109759  *  0b1111..Minimum current, approximately 19% below nominal.
109760  */
109761 #define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
109762 #define USBPHY_TX_SET_TXCAL45DM_MASK             (0xF00U)
109763 #define USBPHY_TX_SET_TXCAL45DM_SHIFT            (8U)
109764 /*! TXCAL45DM
109765  *  0b0000..+19.95%
109766  *  0b0001..+17.35%
109767  *  0b0010..+14.85%
109768  *  0b0011..+12.46%
109769  *  0b0100..+9.07%
109770  *  0b0101..+5.87%
109771  *  0b0110..+2.85%
109772  *  0b0111..0%
109773  *  0b1000..-2.70%
109774  *  0b1001..-5.25%
109775  *  0b1010..-7.67%
109776  *  0b1011..-9.98%
109777  *  0b1100..-12.17%
109778  *  0b1101..-14.25%
109779  *  0b1110..-18.14%
109780  *  0b1111..-21.68%
109781  */
109782 #define USBPHY_TX_SET_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
109783 #define USBPHY_TX_SET_TXENCAL45DM_MASK           (0x2000U)
109784 #define USBPHY_TX_SET_TXENCAL45DM_SHIFT          (13U)
109785 #define USBPHY_TX_SET_TXENCAL45DM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DM_SHIFT)) & USBPHY_TX_SET_TXENCAL45DM_MASK)
109786 #define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
109787 #define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
109788 /*! TXCAL45DP
109789  *  0b0000..+19.95%
109790  *  0b0001..+17.35%
109791  *  0b0010..+14.85%
109792  *  0b0011..+12.46%
109793  *  0b0100..+9.07%
109794  *  0b0101..+5.87%
109795  *  0b0110..+2.85%
109796  *  0b0111..0%
109797  *  0b1000..-2.70%
109798  *  0b1001..-5.25%
109799  *  0b1010..-7.67%
109800  *  0b1011..-9.98%
109801  *  0b1100..-12.17%
109802  *  0b1101..-14.25%
109803  *  0b1110..-18.14%
109804  *  0b1111..-21.68%
109805  */
109806 #define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
109807 #define USBPHY_TX_SET_TXENCAL45DP_MASK           (0x200000U)
109808 #define USBPHY_TX_SET_TXENCAL45DP_SHIFT          (21U)
109809 #define USBPHY_TX_SET_TXENCAL45DP(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK)
109810 /*! @} */
109811 
109812 /*! @name TX_CLR - USB PHY Transmitter Control Register */
109813 /*! @{ */
109814 #define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
109815 #define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
109816 /*! D_CAL
109817  *  0b0000..Maximum current, approximately 19% above nominal.
109818  *  0b0111..Nominal
109819  *  0b1111..Minimum current, approximately 19% below nominal.
109820  */
109821 #define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
109822 #define USBPHY_TX_CLR_TXCAL45DM_MASK             (0xF00U)
109823 #define USBPHY_TX_CLR_TXCAL45DM_SHIFT            (8U)
109824 /*! TXCAL45DM
109825  *  0b0000..+19.95%
109826  *  0b0001..+17.35%
109827  *  0b0010..+14.85%
109828  *  0b0011..+12.46%
109829  *  0b0100..+9.07%
109830  *  0b0101..+5.87%
109831  *  0b0110..+2.85%
109832  *  0b0111..0%
109833  *  0b1000..-2.70%
109834  *  0b1001..-5.25%
109835  *  0b1010..-7.67%
109836  *  0b1011..-9.98%
109837  *  0b1100..-12.17%
109838  *  0b1101..-14.25%
109839  *  0b1110..-18.14%
109840  *  0b1111..-21.68%
109841  */
109842 #define USBPHY_TX_CLR_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
109843 #define USBPHY_TX_CLR_TXENCAL45DM_MASK           (0x2000U)
109844 #define USBPHY_TX_CLR_TXENCAL45DM_SHIFT          (13U)
109845 #define USBPHY_TX_CLR_TXENCAL45DM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DM_MASK)
109846 #define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
109847 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
109848 /*! TXCAL45DP
109849  *  0b0000..+19.95%
109850  *  0b0001..+17.35%
109851  *  0b0010..+14.85%
109852  *  0b0011..+12.46%
109853  *  0b0100..+9.07%
109854  *  0b0101..+5.87%
109855  *  0b0110..+2.85%
109856  *  0b0111..0%
109857  *  0b1000..-2.70%
109858  *  0b1001..-5.25%
109859  *  0b1010..-7.67%
109860  *  0b1011..-9.98%
109861  *  0b1100..-12.17%
109862  *  0b1101..-14.25%
109863  *  0b1110..-18.14%
109864  *  0b1111..-21.68%
109865  */
109866 #define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
109867 #define USBPHY_TX_CLR_TXENCAL45DP_MASK           (0x200000U)
109868 #define USBPHY_TX_CLR_TXENCAL45DP_SHIFT          (21U)
109869 #define USBPHY_TX_CLR_TXENCAL45DP(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK)
109870 /*! @} */
109871 
109872 /*! @name TX_TOG - USB PHY Transmitter Control Register */
109873 /*! @{ */
109874 #define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
109875 #define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
109876 /*! D_CAL
109877  *  0b0000..Maximum current, approximately 19% above nominal.
109878  *  0b0111..Nominal
109879  *  0b1111..Minimum current, approximately 19% below nominal.
109880  */
109881 #define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
109882 #define USBPHY_TX_TOG_TXCAL45DM_MASK             (0xF00U)
109883 #define USBPHY_TX_TOG_TXCAL45DM_SHIFT            (8U)
109884 /*! TXCAL45DM
109885  *  0b0000..+19.95%
109886  *  0b0001..+17.35%
109887  *  0b0010..+14.85%
109888  *  0b0011..+12.46%
109889  *  0b0100..+9.07%
109890  *  0b0101..+5.87%
109891  *  0b0110..+2.85%
109892  *  0b0111..0%
109893  *  0b1000..-2.70%
109894  *  0b1001..-5.25%
109895  *  0b1010..-7.67%
109896  *  0b1011..-9.98%
109897  *  0b1100..-12.17%
109898  *  0b1101..-14.25%
109899  *  0b1110..-18.14%
109900  *  0b1111..-21.68%
109901  */
109902 #define USBPHY_TX_TOG_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
109903 #define USBPHY_TX_TOG_TXENCAL45DM_MASK           (0x2000U)
109904 #define USBPHY_TX_TOG_TXENCAL45DM_SHIFT          (13U)
109905 #define USBPHY_TX_TOG_TXENCAL45DM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DM_MASK)
109906 #define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
109907 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
109908 /*! TXCAL45DP
109909  *  0b0000..+19.95%
109910  *  0b0001..+17.35%
109911  *  0b0010..+14.85%
109912  *  0b0011..+12.46%
109913  *  0b0100..+9.07%
109914  *  0b0101..+5.87%
109915  *  0b0110..+2.85%
109916  *  0b0111..0%
109917  *  0b1000..-2.70%
109918  *  0b1001..-5.25%
109919  *  0b1010..-7.67%
109920  *  0b1011..-9.98%
109921  *  0b1100..-12.17%
109922  *  0b1101..-14.25%
109923  *  0b1110..-18.14%
109924  *  0b1111..-21.68%
109925  */
109926 #define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
109927 #define USBPHY_TX_TOG_TXENCAL45DP_MASK           (0x200000U)
109928 #define USBPHY_TX_TOG_TXENCAL45DP_SHIFT          (21U)
109929 #define USBPHY_TX_TOG_TXENCAL45DP(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK)
109930 /*! @} */
109931 
109932 /*! @name RX - USB PHY Receiver Control Register */
109933 /*! @{ */
109934 #define USBPHY_RX_ENVADJ_MASK                    (0x7U)
109935 #define USBPHY_RX_ENVADJ_SHIFT                   (0U)
109936 /*! ENVADJ
109937  *  0b000..Trip-Level Voltage is 0.1000 V
109938  *  0b001..Trip-Level Voltage is 0.1125 V
109939  *  0b010..Trip-Level Voltage is 0.1250 V
109940  *  0b011..Trip-Level Voltage is 0.0875 V
109941  *  0b1xx..Reserved
109942  */
109943 #define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
109944 #define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
109945 #define USBPHY_RX_DISCONADJ_SHIFT                (4U)
109946 /*! DISCONADJ
109947  *  0b000..Trip-Level Voltage is 0.56875 V
109948  *  0b001..Trip-Level Voltage is 0.55000 V
109949  *  0b010..Trip-Level Voltage is 0.58125 V
109950  *  0b011..Trip-Level Voltage is 0.60000 V
109951  *  0b1xx..Reserved
109952  */
109953 #define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
109954 #define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
109955 #define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
109956 /*! RXDBYPASS
109957  *  0b0..Normal operation.
109958  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
109959  */
109960 #define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
109961 /*! @} */
109962 
109963 /*! @name RX_SET - USB PHY Receiver Control Register */
109964 /*! @{ */
109965 #define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
109966 #define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
109967 /*! ENVADJ
109968  *  0b000..Trip-Level Voltage is 0.1000 V
109969  *  0b001..Trip-Level Voltage is 0.1125 V
109970  *  0b010..Trip-Level Voltage is 0.1250 V
109971  *  0b011..Trip-Level Voltage is 0.0875 V
109972  *  0b1xx..Reserved
109973  */
109974 #define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
109975 #define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
109976 #define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
109977 /*! DISCONADJ
109978  *  0b000..Trip-Level Voltage is 0.56875 V
109979  *  0b001..Trip-Level Voltage is 0.55000 V
109980  *  0b010..Trip-Level Voltage is 0.58125 V
109981  *  0b011..Trip-Level Voltage is 0.60000 V
109982  *  0b1xx..Reserved
109983  */
109984 #define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
109985 #define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
109986 #define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
109987 /*! RXDBYPASS
109988  *  0b0..Normal operation.
109989  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
109990  */
109991 #define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
109992 /*! @} */
109993 
109994 /*! @name RX_CLR - USB PHY Receiver Control Register */
109995 /*! @{ */
109996 #define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
109997 #define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
109998 /*! ENVADJ
109999  *  0b000..Trip-Level Voltage is 0.1000 V
110000  *  0b001..Trip-Level Voltage is 0.1125 V
110001  *  0b010..Trip-Level Voltage is 0.1250 V
110002  *  0b011..Trip-Level Voltage is 0.0875 V
110003  *  0b1xx..Reserved
110004  */
110005 #define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
110006 #define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
110007 #define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
110008 /*! DISCONADJ
110009  *  0b000..Trip-Level Voltage is 0.56875 V
110010  *  0b001..Trip-Level Voltage is 0.55000 V
110011  *  0b010..Trip-Level Voltage is 0.58125 V
110012  *  0b011..Trip-Level Voltage is 0.60000 V
110013  *  0b1xx..Reserved
110014  */
110015 #define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
110016 #define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
110017 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
110018 /*! RXDBYPASS
110019  *  0b0..Normal operation.
110020  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
110021  */
110022 #define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
110023 /*! @} */
110024 
110025 /*! @name RX_TOG - USB PHY Receiver Control Register */
110026 /*! @{ */
110027 #define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
110028 #define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
110029 /*! ENVADJ
110030  *  0b000..Trip-Level Voltage is 0.1000 V
110031  *  0b001..Trip-Level Voltage is 0.1125 V
110032  *  0b010..Trip-Level Voltage is 0.1250 V
110033  *  0b011..Trip-Level Voltage is 0.0875 V
110034  *  0b1xx..Reserved
110035  */
110036 #define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
110037 #define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
110038 #define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
110039 /*! DISCONADJ
110040  *  0b000..Trip-Level Voltage is 0.56875 V
110041  *  0b001..Trip-Level Voltage is 0.55000 V
110042  *  0b010..Trip-Level Voltage is 0.58125 V
110043  *  0b011..Trip-Level Voltage is 0.60000 V
110044  *  0b1xx..Reserved
110045  */
110046 #define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
110047 #define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
110048 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
110049 /*! RXDBYPASS
110050  *  0b0..Normal operation.
110051  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
110052  */
110053 #define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
110054 /*! @} */
110055 
110056 /*! @name CTRL - USB PHY General Control Register */
110057 /*! @{ */
110058 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
110059 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
110060 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
110061 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
110062 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
110063 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
110064 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK          (0x10U)
110065 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT         (4U)
110066 /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
110067  *  0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
110068  *  0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
110069  */
110070 #define USBPHY_CTRL_ENDEVPLUGINDET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
110071 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
110072 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
110073 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
110074 #define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
110075 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
110076 #define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
110077 #define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
110078 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
110079 #define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
110080 #define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
110081 #define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
110082 #define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
110083 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
110084 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
110085 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
110086 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
110087 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
110088 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
110089 #define USBPHY_CTRL_FSDLL_RST_EN_MASK            (0x1000000U)
110090 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           (24U)
110091 #define USBPHY_CTRL_FSDLL_RST_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
110092 #define USBPHY_CTRL_OTG_ID_VALUE_MASK            (0x8000000U)
110093 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           (27U)
110094 #define USBPHY_CTRL_OTG_ID_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
110095 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
110096 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
110097 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
110098 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
110099 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
110100 #define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
110101 #define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
110102 #define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
110103 #define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
110104 #define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
110105 #define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
110106 #define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
110107 /*! @} */
110108 
110109 /*! @name CTRL_SET - USB PHY General Control Register */
110110 /*! @{ */
110111 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
110112 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
110113 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
110114 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
110115 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
110116 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
110117 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK      (0x10U)
110118 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT     (4U)
110119 /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
110120  *  0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
110121  *  0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
110122  */
110123 #define USBPHY_CTRL_SET_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
110124 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
110125 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
110126 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
110127 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
110128 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
110129 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
110130 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
110131 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
110132 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
110133 #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
110134 #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
110135 #define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
110136 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
110137 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
110138 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
110139 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
110140 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
110141 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
110142 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        (0x1000000U)
110143 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       (24U)
110144 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
110145 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        (0x8000000U)
110146 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       (27U)
110147 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
110148 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
110149 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
110150 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
110151 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
110152 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
110153 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
110154 #define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
110155 #define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
110156 #define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
110157 #define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
110158 #define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
110159 #define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
110160 /*! @} */
110161 
110162 /*! @name CTRL_CLR - USB PHY General Control Register */
110163 /*! @{ */
110164 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
110165 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
110166 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
110167 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
110168 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
110169 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
110170 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK      (0x10U)
110171 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT     (4U)
110172 /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
110173  *  0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
110174  *  0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
110175  */
110176 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
110177 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
110178 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
110179 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
110180 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
110181 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
110182 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
110183 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
110184 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
110185 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
110186 #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
110187 #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
110188 #define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
110189 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
110190 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
110191 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
110192 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
110193 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
110194 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
110195 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        (0x1000000U)
110196 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       (24U)
110197 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
110198 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        (0x8000000U)
110199 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       (27U)
110200 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
110201 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
110202 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
110203 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
110204 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
110205 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
110206 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
110207 #define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
110208 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
110209 #define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
110210 #define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
110211 #define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
110212 #define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
110213 /*! @} */
110214 
110215 /*! @name CTRL_TOG - USB PHY General Control Register */
110216 /*! @{ */
110217 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
110218 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
110219 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
110220 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
110221 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
110222 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
110223 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK      (0x10U)
110224 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT     (4U)
110225 /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
110226  *  0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
110227  *  0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
110228  */
110229 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
110230 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
110231 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
110232 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
110233 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
110234 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
110235 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
110236 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
110237 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
110238 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
110239 #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
110240 #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
110241 #define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
110242 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
110243 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
110244 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
110245 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
110246 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
110247 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
110248 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        (0x1000000U)
110249 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       (24U)
110250 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
110251 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        (0x8000000U)
110252 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       (27U)
110253 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
110254 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
110255 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
110256 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
110257 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
110258 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
110259 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
110260 #define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
110261 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
110262 #define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
110263 #define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
110264 #define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
110265 #define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
110266 /*! @} */
110267 
110268 /*! @name STATUS - USB PHY Status Register */
110269 /*! @{ */
110270 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
110271 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
110272 /*! HOSTDISCONDETECT_STATUS
110273  *  0b0..USB cable disconnect has not been detected at the local host
110274  *  0b1..USB cable disconnect has been detected at the local host
110275  */
110276 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
110277 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
110278 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
110279 /*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection
110280  *  0b0..No attachment to a USB host is detected
110281  *  0b1..Cable attachment to a USB host is detected
110282  */
110283 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
110284 #define USBPHY_STATUS_OTGID_STATUS_MASK          (0x100U)
110285 #define USBPHY_STATUS_OTGID_STATUS_SHIFT         (8U)
110286 #define USBPHY_STATUS_OTGID_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
110287 #define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
110288 #define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
110289 #define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
110290 /*! @} */
110291 
110292 /*! @name DEBUG0 - USB PHY Debug Register 0 */
110293 /*! @{ */
110294 #define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK          (0x1U)
110295 #define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT         (0U)
110296 #define USBPHY_DEBUG0_OTGIDPIOLOCK(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK)
110297 #define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK  (0x2U)
110298 #define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U)
110299 #define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK)
110300 #define USBPHY_DEBUG0_HSTPULLDOWN_MASK           (0xCU)
110301 #define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT          (2U)
110302 #define USBPHY_DEBUG0_HSTPULLDOWN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK)
110303 #define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK         (0x30U)
110304 #define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT        (4U)
110305 #define USBPHY_DEBUG0_ENHSTPULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK)
110306 #define USBPHY_DEBUG0_TX2RXCOUNT_MASK            (0xF00U)
110307 #define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT           (8U)
110308 #define USBPHY_DEBUG0_TX2RXCOUNT(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK)
110309 #define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK          (0x1000U)
110310 #define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT         (12U)
110311 #define USBPHY_DEBUG0_ENTX2RXCOUNT(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK)
110312 #define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK     (0x1F0000U)
110313 #define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT    (16U)
110314 #define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK)
110315 #define USBPHY_DEBUG0_ENSQUELCHRESET_MASK        (0x1000000U)
110316 #define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT       (24U)
110317 #define USBPHY_DEBUG0_ENSQUELCHRESET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK)
110318 #define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK    (0x1E000000U)
110319 #define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT   (25U)
110320 #define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK)
110321 #define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK     (0x20000000U)
110322 #define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT    (29U)
110323 #define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK)
110324 #define USBPHY_DEBUG0_CLKGATE_MASK               (0x40000000U)
110325 #define USBPHY_DEBUG0_CLKGATE_SHIFT              (30U)
110326 #define USBPHY_DEBUG0_CLKGATE(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK)
110327 /*! @} */
110328 
110329 /*! @name DEBUG0_SET - USB PHY Debug Register 0 */
110330 /*! @{ */
110331 #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK      (0x1U)
110332 #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT     (0U)
110333 #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK)
110334 #define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
110335 #define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
110336 #define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK)
110337 #define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK       (0xCU)
110338 #define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT      (2U)
110339 #define USBPHY_DEBUG0_SET_HSTPULLDOWN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK)
110340 #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK     (0x30U)
110341 #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT    (4U)
110342 #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK)
110343 #define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK        (0xF00U)
110344 #define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT       (8U)
110345 #define USBPHY_DEBUG0_SET_TX2RXCOUNT(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK)
110346 #define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK      (0x1000U)
110347 #define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT     (12U)
110348 #define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK)
110349 #define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
110350 #define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U)
110351 #define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK)
110352 #define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK    (0x1000000U)
110353 #define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT   (24U)
110354 #define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK)
110355 #define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
110356 #define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U)
110357 #define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK)
110358 #define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
110359 #define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U)
110360 #define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK)
110361 #define USBPHY_DEBUG0_SET_CLKGATE_MASK           (0x40000000U)
110362 #define USBPHY_DEBUG0_SET_CLKGATE_SHIFT          (30U)
110363 #define USBPHY_DEBUG0_SET_CLKGATE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK)
110364 /*! @} */
110365 
110366 /*! @name DEBUG0_CLR - USB PHY Debug Register 0 */
110367 /*! @{ */
110368 #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK      (0x1U)
110369 #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT     (0U)
110370 #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK)
110371 #define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
110372 #define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
110373 #define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK)
110374 #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK       (0xCU)
110375 #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT      (2U)
110376 #define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK)
110377 #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK     (0x30U)
110378 #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT    (4U)
110379 #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK)
110380 #define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK        (0xF00U)
110381 #define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT       (8U)
110382 #define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK)
110383 #define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK      (0x1000U)
110384 #define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT     (12U)
110385 #define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK)
110386 #define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
110387 #define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
110388 #define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK)
110389 #define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK    (0x1000000U)
110390 #define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT   (24U)
110391 #define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK)
110392 #define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
110393 #define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
110394 #define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK)
110395 #define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
110396 #define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
110397 #define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK)
110398 #define USBPHY_DEBUG0_CLR_CLKGATE_MASK           (0x40000000U)
110399 #define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT          (30U)
110400 #define USBPHY_DEBUG0_CLR_CLKGATE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK)
110401 /*! @} */
110402 
110403 /*! @name DEBUG0_TOG - USB PHY Debug Register 0 */
110404 /*! @{ */
110405 #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK      (0x1U)
110406 #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT     (0U)
110407 #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK)
110408 #define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
110409 #define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
110410 #define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK)
110411 #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK       (0xCU)
110412 #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT      (2U)
110413 #define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK)
110414 #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK     (0x30U)
110415 #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT    (4U)
110416 #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK)
110417 #define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK        (0xF00U)
110418 #define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT       (8U)
110419 #define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK)
110420 #define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK      (0x1000U)
110421 #define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT     (12U)
110422 #define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK)
110423 #define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
110424 #define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
110425 #define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK)
110426 #define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK    (0x1000000U)
110427 #define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT   (24U)
110428 #define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK)
110429 #define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
110430 #define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
110431 #define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK)
110432 #define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
110433 #define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
110434 #define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK)
110435 #define USBPHY_DEBUG0_TOG_CLKGATE_MASK           (0x40000000U)
110436 #define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT          (30U)
110437 #define USBPHY_DEBUG0_TOG_CLKGATE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK)
110438 /*! @} */
110439 
110440 /*! @name DEBUG1 - UTMI Debug Status Register 1 */
110441 /*! @{ */
110442 #define USBPHY_DEBUG1_ENTAILADJVD_MASK           (0x6000U)
110443 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          (13U)
110444 /*! ENTAILADJVD
110445  *  0b00..Delay is nominal
110446  *  0b01..Delay is +20%
110447  *  0b10..Delay is -20%
110448  *  0b11..Delay is -40%
110449  */
110450 #define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
110451 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
110452 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT  (18U)
110453 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
110454  */
110455 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)
110456 #define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK      (0x600000U)
110457 #define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT     (21U)
110458 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
110459  */
110460 #define USBPHY_DEBUG1_USB2_REFBIAS_TST(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)
110461 /*! @} */
110462 
110463 /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
110464 /*! @{ */
110465 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       (0x6000U)
110466 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      (13U)
110467 /*! ENTAILADJVD
110468  *  0b00..Delay is nominal
110469  *  0b01..Delay is +20%
110470  *  0b10..Delay is -20%
110471  *  0b11..Delay is -40%
110472  */
110473 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
110474 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
110475 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)
110476 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
110477  */
110478 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)
110479 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK  (0x600000U)
110480 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)
110481 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
110482  */
110483 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)
110484 /*! @} */
110485 
110486 /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
110487 /*! @{ */
110488 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       (0x6000U)
110489 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      (13U)
110490 /*! ENTAILADJVD
110491  *  0b00..Delay is nominal
110492  *  0b01..Delay is +20%
110493  *  0b10..Delay is -20%
110494  *  0b11..Delay is -40%
110495  */
110496 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
110497 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
110498 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)
110499 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
110500  */
110501 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)
110502 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK  (0x600000U)
110503 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)
110504 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
110505  */
110506 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)
110507 /*! @} */
110508 
110509 /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
110510 /*! @{ */
110511 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       (0x6000U)
110512 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      (13U)
110513 /*! ENTAILADJVD
110514  *  0b00..Delay is nominal
110515  *  0b01..Delay is +20%
110516  *  0b10..Delay is -20%
110517  *  0b11..Delay is -40%
110518  */
110519 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
110520 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
110521 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)
110522 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
110523  */
110524 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)
110525 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK  (0x600000U)
110526 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)
110527 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
110528  */
110529 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)
110530 /*! @} */
110531 
110532 /*! @name VERSION - UTMI RTL Version */
110533 /*! @{ */
110534 #define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
110535 #define USBPHY_VERSION_STEP_SHIFT                (0U)
110536 #define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
110537 #define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
110538 #define USBPHY_VERSION_MINOR_SHIFT               (16U)
110539 #define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
110540 #define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
110541 #define USBPHY_VERSION_MAJOR_SHIFT               (24U)
110542 #define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
110543 /*! @} */
110544 
110545 /*! @name PLL_SIC - USB PHY PLL Control/Status Register */
110546 /*! @{ */
110547 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK      (0x40U)
110548 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT     (6U)
110549 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
110550 #define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
110551 #define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
110552 #define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
110553 #define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
110554 #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
110555 #define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
110556 #define USBPHY_PLL_SIC_PLL_BYPASS_MASK           (0x10000U)
110557 #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT          (16U)
110558 #define USBPHY_PLL_SIC_PLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
110559 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK      (0x80000U)
110560 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT     (19U)
110561 /*! REFBIAS_PWD_SEL
110562  *  0b0..Selects PLL_POWER to control the reference bias
110563  *  0b1..Selects REFBIAS_PWD to control the reference bias.
110564  */
110565 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
110566 #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK          (0x100000U)
110567 #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT         (20U)
110568 /*! REFBIAS_PWD - Power down the reference bias
110569  */
110570 #define USBPHY_PLL_SIC_REFBIAS_PWD(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
110571 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK       (0x200000U)
110572 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT      (21U)
110573 #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
110574 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x1C00000U)
110575 #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (22U)
110576 /*! PLL_DIV_SEL
110577  *  0b000..Divide by 13
110578  *  0b001..Divide by 15
110579  *  0b010..Divide by 16
110580  *  0b011..Divide by 20
110581  *  0b100..Divide by 22
110582  *  0b101..Divide by 25
110583  *  0b110..Divide by 30
110584  *  0b111..Divide by 240
110585  */
110586 #define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
110587 #define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
110588 #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
110589 /*! PLL_LOCK
110590  *  0b0..PLL is not currently locked
110591  *  0b1..PLL is currently locked
110592  */
110593 #define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
110594 /*! @} */
110595 
110596 /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
110597 /*! @{ */
110598 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK  (0x40U)
110599 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
110600 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
110601 #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
110602 #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
110603 #define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
110604 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
110605 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
110606 #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
110607 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK       (0x10000U)
110608 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT      (16U)
110609 #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
110610 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK  (0x80000U)
110611 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
110612 /*! REFBIAS_PWD_SEL
110613  *  0b0..Selects PLL_POWER to control the reference bias
110614  *  0b1..Selects REFBIAS_PWD to control the reference bias.
110615  */
110616 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
110617 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK      (0x100000U)
110618 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT     (20U)
110619 /*! REFBIAS_PWD - Power down the reference bias
110620  */
110621 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
110622 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK   (0x200000U)
110623 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT  (21U)
110624 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
110625 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x1C00000U)
110626 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (22U)
110627 /*! PLL_DIV_SEL
110628  *  0b000..Divide by 13
110629  *  0b001..Divide by 15
110630  *  0b010..Divide by 16
110631  *  0b011..Divide by 20
110632  *  0b100..Divide by 22
110633  *  0b101..Divide by 25
110634  *  0b110..Divide by 30
110635  *  0b111..Divide by 240
110636  */
110637 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
110638 #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
110639 #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
110640 /*! PLL_LOCK
110641  *  0b0..PLL is not currently locked
110642  *  0b1..PLL is currently locked
110643  */
110644 #define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
110645 /*! @} */
110646 
110647 /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
110648 /*! @{ */
110649 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK  (0x40U)
110650 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
110651 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
110652 #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
110653 #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
110654 #define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
110655 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
110656 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
110657 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
110658 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK       (0x10000U)
110659 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT      (16U)
110660 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
110661 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK  (0x80000U)
110662 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
110663 /*! REFBIAS_PWD_SEL
110664  *  0b0..Selects PLL_POWER to control the reference bias
110665  *  0b1..Selects REFBIAS_PWD to control the reference bias.
110666  */
110667 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
110668 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK      (0x100000U)
110669 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT     (20U)
110670 /*! REFBIAS_PWD - Power down the reference bias
110671  */
110672 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
110673 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK   (0x200000U)
110674 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT  (21U)
110675 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
110676 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x1C00000U)
110677 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (22U)
110678 /*! PLL_DIV_SEL
110679  *  0b000..Divide by 13
110680  *  0b001..Divide by 15
110681  *  0b010..Divide by 16
110682  *  0b011..Divide by 20
110683  *  0b100..Divide by 22
110684  *  0b101..Divide by 25
110685  *  0b110..Divide by 30
110686  *  0b111..Divide by 240
110687  */
110688 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
110689 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
110690 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
110691 /*! PLL_LOCK
110692  *  0b0..PLL is not currently locked
110693  *  0b1..PLL is currently locked
110694  */
110695 #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
110696 /*! @} */
110697 
110698 /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
110699 /*! @{ */
110700 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK  (0x40U)
110701 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
110702 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
110703 #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
110704 #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
110705 #define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
110706 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
110707 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
110708 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
110709 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK       (0x10000U)
110710 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT      (16U)
110711 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
110712 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK  (0x80000U)
110713 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
110714 /*! REFBIAS_PWD_SEL
110715  *  0b0..Selects PLL_POWER to control the reference bias
110716  *  0b1..Selects REFBIAS_PWD to control the reference bias.
110717  */
110718 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
110719 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK      (0x100000U)
110720 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT     (20U)
110721 /*! REFBIAS_PWD - Power down the reference bias
110722  */
110723 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
110724 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK   (0x200000U)
110725 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT  (21U)
110726 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
110727 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x1C00000U)
110728 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (22U)
110729 /*! PLL_DIV_SEL
110730  *  0b000..Divide by 13
110731  *  0b001..Divide by 15
110732  *  0b010..Divide by 16
110733  *  0b011..Divide by 20
110734  *  0b100..Divide by 22
110735  *  0b101..Divide by 25
110736  *  0b110..Divide by 30
110737  *  0b111..Divide by 240
110738  */
110739 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
110740 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
110741 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
110742 /*! PLL_LOCK
110743  *  0b0..PLL is not currently locked
110744  *  0b1..PLL is currently locked
110745  */
110746 #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
110747 /*! @} */
110748 
110749 /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
110750 /*! @{ */
110751 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
110752 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
110753 /*! VBUSVALID_THRESH
110754  *  0b000..4.0 V
110755  *  0b001..4.1 V
110756  *  0b010..4.2 V
110757  *  0b011..4.3 V
110758  *  0b100..4.4 V (Default)
110759  *  0b101..4.5 V
110760  *  0b110..4.6 V
110761  *  0b111..4.7 V
110762  */
110763 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
110764 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
110765 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
110766 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
110767  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
110768  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
110769  */
110770 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
110771 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
110772 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
110773 /*! SESSEND_OVERRIDE - Override value for SESSEND
110774  */
110775 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
110776 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
110777 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
110778 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
110779  */
110780 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
110781 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
110782 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
110783 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
110784  */
110785 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
110786 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
110787 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
110788 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
110789  */
110790 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
110791 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
110792 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
110793 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
110794  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
110795  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
110796  */
110797 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
110798 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
110799 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
110800 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
110801  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
110802  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
110803  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
110804  *  0b11..Reserved, do not use
110805  */
110806 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
110807 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
110808 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
110809 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
110810  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
110811  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
110812  */
110813 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
110814 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK  (0x100000U)
110815 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
110816 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
110817  *  0b0..Powers down the VBUS_VALID comparator
110818  *  0b1..Enables the VBUS_VALID comparator (default)
110819  */
110820 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
110821 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
110822 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
110823 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
110824  *  0b0..VBUS discharge resistor is disabled (Default)
110825  *  0b1..VBUS discharge resistor is enabled
110826  */
110827 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
110828 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
110829 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
110830 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
110831  *  0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
110832  *  0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
110833  */
110834 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
110835 /*! @} */
110836 
110837 /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
110838 /*! @{ */
110839 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
110840 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
110841 /*! VBUSVALID_THRESH
110842  *  0b000..4.0 V
110843  *  0b001..4.1 V
110844  *  0b010..4.2 V
110845  *  0b011..4.3 V
110846  *  0b100..4.4 V (Default)
110847  *  0b101..4.5 V
110848  *  0b110..4.6 V
110849  *  0b111..4.7 V
110850  */
110851 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
110852 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
110853 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
110854 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
110855  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
110856  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
110857  */
110858 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
110859 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
110860 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
110861 /*! SESSEND_OVERRIDE - Override value for SESSEND
110862  */
110863 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
110864 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
110865 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
110866 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
110867  */
110868 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
110869 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
110870 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
110871 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
110872  */
110873 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
110874 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
110875 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
110876 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
110877  */
110878 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
110879 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
110880 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
110881 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
110882  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
110883  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
110884  */
110885 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
110886 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
110887 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
110888 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
110889  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
110890  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
110891  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
110892  *  0b11..Reserved, do not use
110893  */
110894 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
110895 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
110896 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
110897 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
110898  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
110899  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
110900  */
110901 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
110902 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U)
110903 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
110904 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
110905  *  0b0..Powers down the VBUS_VALID comparator
110906  *  0b1..Enables the VBUS_VALID comparator (default)
110907  */
110908 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
110909 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
110910 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
110911 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
110912  *  0b0..VBUS discharge resistor is disabled (Default)
110913  *  0b1..VBUS discharge resistor is enabled
110914  */
110915 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
110916 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
110917 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
110918 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
110919  *  0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
110920  *  0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
110921  */
110922 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
110923 /*! @} */
110924 
110925 /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
110926 /*! @{ */
110927 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
110928 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
110929 /*! VBUSVALID_THRESH
110930  *  0b000..4.0 V
110931  *  0b001..4.1 V
110932  *  0b010..4.2 V
110933  *  0b011..4.3 V
110934  *  0b100..4.4 V (Default)
110935  *  0b101..4.5 V
110936  *  0b110..4.6 V
110937  *  0b111..4.7 V
110938  */
110939 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
110940 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
110941 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
110942 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
110943  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
110944  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
110945  */
110946 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
110947 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
110948 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
110949 /*! SESSEND_OVERRIDE - Override value for SESSEND
110950  */
110951 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
110952 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
110953 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
110954 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
110955  */
110956 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
110957 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
110958 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
110959 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
110960  */
110961 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
110962 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
110963 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
110964 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
110965  */
110966 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
110967 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
110968 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
110969 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
110970  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
110971  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
110972  */
110973 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
110974 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
110975 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
110976 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
110977  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
110978  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
110979  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
110980  *  0b11..Reserved, do not use
110981  */
110982 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
110983 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
110984 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
110985 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
110986  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
110987  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
110988  */
110989 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
110990 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U)
110991 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
110992 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
110993  *  0b0..Powers down the VBUS_VALID comparator
110994  *  0b1..Enables the VBUS_VALID comparator (default)
110995  */
110996 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
110997 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
110998 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
110999 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
111000  *  0b0..VBUS discharge resistor is disabled (Default)
111001  *  0b1..VBUS discharge resistor is enabled
111002  */
111003 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
111004 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
111005 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
111006 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
111007  *  0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
111008  *  0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
111009  */
111010 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
111011 /*! @} */
111012 
111013 /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
111014 /*! @{ */
111015 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
111016 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
111017 /*! VBUSVALID_THRESH
111018  *  0b000..4.0 V
111019  *  0b001..4.1 V
111020  *  0b010..4.2 V
111021  *  0b011..4.3 V
111022  *  0b100..4.4 V (Default)
111023  *  0b101..4.5 V
111024  *  0b110..4.6 V
111025  *  0b111..4.7 V
111026  */
111027 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
111028 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
111029 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
111030 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
111031  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
111032  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
111033  */
111034 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
111035 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
111036 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
111037 /*! SESSEND_OVERRIDE - Override value for SESSEND
111038  */
111039 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
111040 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
111041 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
111042 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
111043  */
111044 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
111045 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
111046 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
111047 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
111048  */
111049 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
111050 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
111051 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
111052 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
111053  */
111054 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
111055 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
111056 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
111057 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
111058  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
111059  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
111060  */
111061 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
111062 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
111063 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
111064 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
111065  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
111066  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
111067  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
111068  *  0b11..Reserved, do not use
111069  */
111070 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
111071 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
111072 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
111073 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
111074  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
111075  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
111076  */
111077 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
111078 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U)
111079 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
111080 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
111081  *  0b0..Powers down the VBUS_VALID comparator
111082  *  0b1..Enables the VBUS_VALID comparator (default)
111083  */
111084 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
111085 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
111086 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
111087 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
111088  *  0b0..VBUS discharge resistor is disabled (Default)
111089  *  0b1..VBUS discharge resistor is enabled
111090  */
111091 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
111092 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
111093 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
111094 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
111095  *  0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
111096  *  0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
111097  */
111098 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
111099 /*! @} */
111100 
111101 /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
111102 /*! @{ */
111103 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
111104 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT  (0U)
111105 /*! SESSEND - Session End indicator
111106  *  0b0..The VBUS voltage is above the Session Valid threshold
111107  *  0b1..The VBUS voltage is below the Session Valid threshold
111108  */
111109 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
111110 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK    (0x2U)
111111 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
111112 /*! BVALID - B-Device Session Valid status
111113  *  0b0..The VBUS voltage is below the Session Valid threshold
111114  *  0b1..The VBUS voltage is above the Session Valid threshold
111115  */
111116 #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
111117 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK    (0x4U)
111118 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
111119 /*! AVALID - A-Device Session Valid status
111120  *  0b0..The VBUS voltage is below the Session Valid threshold
111121  *  0b1..The VBUS voltage is above the Session Valid threshold
111122  */
111123 #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
111124 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
111125 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
111126 /*! VBUS_VALID - VBUS voltage status
111127  *  0b0..VBUS is below the comparator threshold
111128  *  0b1..VBUS is above the comparator threshold
111129  */
111130 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
111131 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
111132 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
111133 /*! VBUS_VALID_3V - VBUS_VALID_3V detector status
111134  *  0b0..VBUS voltage is below VBUS_VALID_3V threshold
111135  *  0b1..VBUS voltage is above VBUS_VALID_3V threshold
111136  */
111137 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
111138 /*! @} */
111139 
111140 /*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */
111141 /*! @{ */
111142 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK   (0x4U)
111143 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT  (2U)
111144 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)
111145 #define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK   (0x800000U)
111146 #define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT  (23U)
111147 /*! BGR_IBIAS - USB charge detector bias current reference
111148  *  0b0..Bias current is derived from the USB PHY internal current generator.
111149  *  0b1..Bias current is derived from the reference generator of the bandgap.
111150  */
111151 #define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK)
111152 /*! @} */
111153 
111154 /*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */
111155 /*! @{ */
111156 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
111157 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
111158 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)
111159 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U)
111160 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U)
111161 /*! BGR_IBIAS - USB charge detector bias current reference
111162  *  0b0..Bias current is derived from the USB PHY internal current generator.
111163  *  0b1..Bias current is derived from the reference generator of the bandgap.
111164  */
111165 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK)
111166 /*! @} */
111167 
111168 /*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */
111169 /*! @{ */
111170 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
111171 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
111172 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)
111173 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U)
111174 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U)
111175 /*! BGR_IBIAS - USB charge detector bias current reference
111176  *  0b0..Bias current is derived from the USB PHY internal current generator.
111177  *  0b1..Bias current is derived from the reference generator of the bandgap.
111178  */
111179 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK)
111180 /*! @} */
111181 
111182 /*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */
111183 /*! @{ */
111184 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
111185 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
111186 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)
111187 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U)
111188 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U)
111189 /*! BGR_IBIAS - USB charge detector bias current reference
111190  *  0b0..Bias current is derived from the USB PHY internal current generator.
111191  *  0b1..Bias current is derived from the reference generator of the bandgap.
111192  */
111193 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK)
111194 /*! @} */
111195 
111196 /*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
111197 /*! @{ */
111198 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
111199 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
111200 /*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output
111201  *  0b0..No USB cable attachment has been detected
111202  *  0b1..A USB cable attachment between the device and host has been detected
111203  */
111204 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
111205 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
111206 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
111207 /*! CHRG_DETECTED - Battery Charging Primary Detection phase output
111208  *  0b0..Standard Downstream Port (SDP) has been detected
111209  *  0b1..Charging Port has been detected
111210  */
111211 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
111212 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK  (0x4U)
111213 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
111214 /*! DM_STATE
111215  *  0b0..USB_DM pin voltage is < 0.8V
111216  *  0b1..USB_DM pin voltage is > 2.0V
111217  */
111218 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
111219 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK  (0x8U)
111220 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
111221 /*! DP_STATE
111222  *  0b0..USB_DP pin voltage is < 0.8V
111223  *  0b1..USB_DP pin voltage is > 2.0V
111224  */
111225 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
111226 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
111227 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
111228 /*! SECDET_DCP - Battery Charging Secondary Detection phase output
111229  *  0b0..Charging Downstream Port (CDP) has been detected
111230  *  0b1..Downstream Charging Port (DCP) has been detected
111231  */
111232 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
111233 /*! @} */
111234 
111235 /*! @name ANACTRL - USB PHY Analog Control Register */
111236 /*! @{ */
111237 #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
111238 #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
111239 /*! DEV_PULLDOWN
111240  *  0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
111241  *  0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
111242  */
111243 #define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
111244 /*! @} */
111245 
111246 /*! @name ANACTRL_SET - USB PHY Analog Control Register */
111247 /*! @{ */
111248 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
111249 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
111250 /*! DEV_PULLDOWN
111251  *  0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
111252  *  0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
111253  */
111254 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
111255 /*! @} */
111256 
111257 /*! @name ANACTRL_CLR - USB PHY Analog Control Register */
111258 /*! @{ */
111259 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
111260 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
111261 /*! DEV_PULLDOWN
111262  *  0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
111263  *  0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
111264  */
111265 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
111266 /*! @} */
111267 
111268 /*! @name ANACTRL_TOG - USB PHY Analog Control Register */
111269 /*! @{ */
111270 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
111271 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
111272 /*! DEV_PULLDOWN
111273  *  0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
111274  *  0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
111275  */
111276 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
111277 /*! @} */
111278 
111279 /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
111280 /*! @{ */
111281 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
111282 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
111283 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
111284 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK  (0x2U)
111285 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
111286 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
111287 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK  (0x4U)
111288 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
111289 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
111290 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
111291 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
111292 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
111293 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
111294 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
111295 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
111296 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK     (0x20U)
111297 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT    (5U)
111298 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
111299 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK    (0x40U)
111300 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT   (6U)
111301 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
111302 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK  (0x80U)
111303 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
111304 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
111305 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK  (0x100U)
111306 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
111307 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
111308 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
111309 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
111310 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
111311 #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK         (0xFF0000U)
111312 #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT        (16U)
111313 #define USBPHY_USB1_LOOPBACK_TSTPKT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
111314 /*! @} */
111315 
111316 /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
111317 /*! @{ */
111318 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
111319 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
111320 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
111321 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
111322 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
111323 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
111324 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
111325 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
111326 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
111327 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
111328 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
111329 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
111330 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
111331 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
111332 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
111333 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
111334 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
111335 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
111336 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
111337 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
111338 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
111339 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
111340 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
111341 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
111342 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
111343 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
111344 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
111345 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
111346 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
111347 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
111348 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK     (0xFF0000U)
111349 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT    (16U)
111350 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
111351 /*! @} */
111352 
111353 /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
111354 /*! @{ */
111355 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
111356 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
111357 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
111358 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
111359 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
111360 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
111361 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
111362 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
111363 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
111364 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
111365 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
111366 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
111367 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
111368 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
111369 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
111370 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
111371 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
111372 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
111373 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
111374 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
111375 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
111376 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
111377 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
111378 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
111379 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
111380 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
111381 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
111382 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
111383 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
111384 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
111385 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK     (0xFF0000U)
111386 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT    (16U)
111387 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
111388 /*! @} */
111389 
111390 /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
111391 /*! @{ */
111392 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
111393 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
111394 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
111395 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
111396 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
111397 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
111398 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
111399 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
111400 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
111401 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
111402 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
111403 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
111404 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
111405 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
111406 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
111407 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
111408 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
111409 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
111410 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
111411 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
111412 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
111413 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
111414 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
111415 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
111416 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
111417 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
111418 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
111419 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
111420 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
111421 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
111422 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK     (0xFF0000U)
111423 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT    (16U)
111424 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
111425 /*! @} */
111426 
111427 /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
111428 /*! @{ */
111429 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
111430 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
111431 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
111432 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
111433 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
111434 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
111435 /*! @} */
111436 
111437 /*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
111438 /*! @{ */
111439 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
111440 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
111441 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
111442 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
111443 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
111444 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
111445 /*! @} */
111446 
111447 /*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
111448 /*! @{ */
111449 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
111450 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
111451 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
111452 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
111453 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
111454 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
111455 /*! @} */
111456 
111457 /*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
111458 /*! @{ */
111459 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
111460 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
111461 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
111462 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
111463 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
111464 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
111465 /*! @} */
111466 
111467 /*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
111468 /*! @{ */
111469 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
111470 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
111471 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
111472 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
111473 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
111474 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
111475 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
111476 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
111477 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
111478 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
111479 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
111480 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
111481 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
111482 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
111483 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK)
111484 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
111485 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
111486 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
111487  */
111488 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
111489 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
111490 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
111491 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
111492  */
111493 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK)
111494 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
111495 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
111496 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK)
111497 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
111498 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
111499 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK)
111500 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
111501 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
111502 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
111503 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
111504 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
111505 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
111506 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
111507 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
111508 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
111509 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
111510 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
111511 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
111512 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
111513 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
111514 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK)
111515 /*! @} */
111516 
111517 /*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
111518 /*! @{ */
111519 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
111520 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
111521 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
111522 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
111523 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
111524 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
111525 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
111526 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
111527 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
111528 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
111529 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
111530 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
111531 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
111532 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
111533 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK)
111534 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
111535 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
111536 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
111537  */
111538 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
111539 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
111540 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
111541 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
111542  */
111543 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK)
111544 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
111545 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
111546 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK)
111547 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
111548 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
111549 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK)
111550 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
111551 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
111552 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
111553 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
111554 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
111555 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
111556 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
111557 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
111558 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
111559 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
111560 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
111561 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
111562 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
111563 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
111564 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK)
111565 /*! @} */
111566 
111567 /*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
111568 /*! @{ */
111569 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
111570 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
111571 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
111572 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
111573 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
111574 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
111575 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
111576 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
111577 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
111578 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
111579 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
111580 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
111581 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
111582 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
111583 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK)
111584 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
111585 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
111586 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
111587  */
111588 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
111589 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
111590 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
111591 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
111592  */
111593 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK)
111594 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
111595 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
111596 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK)
111597 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
111598 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
111599 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK)
111600 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
111601 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
111602 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
111603 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
111604 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
111605 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
111606 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
111607 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
111608 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
111609 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
111610 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
111611 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
111612 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
111613 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
111614 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK)
111615 /*! @} */
111616 
111617 /*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
111618 /*! @{ */
111619 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
111620 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
111621 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
111622 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
111623 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
111624 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
111625 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
111626 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
111627 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
111628 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
111629 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
111630 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
111631 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
111632 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
111633 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK)
111634 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
111635 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
111636 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
111637  */
111638 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
111639 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
111640 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
111641 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
111642  */
111643 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK)
111644 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
111645 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
111646 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK)
111647 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
111648 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
111649 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK)
111650 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
111651 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
111652 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
111653 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
111654 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
111655 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
111656 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
111657 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
111658 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
111659 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
111660 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
111661 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
111662 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
111663 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
111664 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK)
111665 /*! @} */
111666 
111667 
111668 /*!
111669  * @}
111670  */ /* end of group USBPHY_Register_Masks */
111671 
111672 
111673 /* USBPHY - Peripheral instance base addresses */
111674 /** Peripheral CONNECTIVITY__USBPHY base address */
111675 #define CONNECTIVITY__USBPHY_BASE                (0x5B100000u)
111676 /** Peripheral CONNECTIVITY__USBPHY base pointer */
111677 #define CONNECTIVITY__USBPHY                     ((USBPHY_Type *)CONNECTIVITY__USBPHY_BASE)
111678 /** Array initializer of USBPHY peripheral base addresses */
111679 #define USBPHY_BASE_ADDRS                        { CONNECTIVITY__USBPHY_BASE }
111680 /** Array initializer of USBPHY peripheral base pointers */
111681 #define USBPHY_BASE_PTRS                         { CONNECTIVITY__USBPHY }
111682 
111683 /*!
111684  * @}
111685  */ /* end of group USBPHY_Peripheral_Access_Layer */
111686 
111687 
111688 /* ----------------------------------------------------------------------------
111689    -- USDHC Peripheral Access Layer
111690    ---------------------------------------------------------------------------- */
111691 
111692 /*!
111693  * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
111694  * @{
111695  */
111696 
111697 /** USDHC - Register Layout Typedef */
111698 typedef struct {
111699   __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
111700   __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
111701   __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
111702   __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
111703   __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
111704   __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
111705   __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
111706   __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
111707   __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
111708   __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
111709   __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
111710   __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
111711   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
111712   __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
111713   __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
111714   __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
111715   __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
111716   __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
111717   __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
111718        uint8_t RESERVED_0[4];
111719   __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
111720   __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
111721   __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
111722        uint8_t RESERVED_1[4];
111723   __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
111724   __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
111725   __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
111726        uint8_t RESERVED_2[4];
111727   __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL control, offset: 0x70 */
111728   __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL status, offset: 0x74 */
111729        uint8_t RESERVED_3[72];
111730   __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
111731   __IO uint32_t MMC_BOOT;                          /**< MMC Boot, offset: 0xC4 */
111732   __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
111733   __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
111734        uint8_t RESERVED_4[48];
111735        uint32_t CQE;                               /**< Command Queue, offset: 0x100 */
111736 } USDHC_Type;
111737 
111738 /* ----------------------------------------------------------------------------
111739    -- USDHC Register Masks
111740    ---------------------------------------------------------------------------- */
111741 
111742 /*!
111743  * @addtogroup USDHC_Register_Masks USDHC Register Masks
111744  * @{
111745  */
111746 
111747 /*! @name DS_ADDR - DMA System Address */
111748 /*! @{ */
111749 #define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
111750 #define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
111751 /*! DS_ADDR - System address
111752  */
111753 #define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
111754 /*! @} */
111755 
111756 /*! @name BLK_ATT - Block Attributes */
111757 /*! @{ */
111758 #define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
111759 #define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
111760 /*! BLKSIZE - Transfer block size
111761  *  0b1000000000000..4096 bytes
111762  *  0b0100000000000..2048 bytes
111763  *  0b0001000000000..512 bytes
111764  *  0b0000111111111..511 bytes
111765  *  0b0000000000100..4 bytes
111766  *  0b0000000000011..3 bytes
111767  *  0b0000000000010..2 bytes
111768  *  0b0000000000001..1 byte
111769  *  0b0000000000000..No data transfer
111770  */
111771 #define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
111772 #define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
111773 #define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
111774 /*! BLKCNT - Blocks count for current transfer
111775  *  0b1111111111111111..65535 blocks
111776  *  0b0000000000000010..2 blocks
111777  *  0b0000000000000001..1 block
111778  *  0b0000000000000000..Stop count
111779  */
111780 #define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
111781 /*! @} */
111782 
111783 /*! @name CMD_ARG - Command Argument */
111784 /*! @{ */
111785 #define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
111786 #define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
111787 /*! CMDARG - Command argument
111788  */
111789 #define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
111790 /*! @} */
111791 
111792 /*! @name CMD_XFR_TYP - Command Transfer Type */
111793 /*! @{ */
111794 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
111795 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
111796 /*! RSPTYP - Response type select
111797  *  0b00..No response
111798  *  0b01..Response length 136
111799  *  0b10..Response length 48
111800  *  0b11..Response length 48, check busy after response
111801  */
111802 #define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
111803 #define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
111804 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
111805 /*! CCCEN - Command CRC check enable
111806  *  0b1..Enables command CRC check
111807  *  0b0..Disables command CRC check
111808  */
111809 #define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
111810 #define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
111811 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
111812 /*! CICEN - Command index check enable
111813  *  0b1..Enables command index check
111814  *  0b0..Disable command index check
111815  */
111816 #define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
111817 #define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
111818 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
111819 /*! DPSEL - Data present select
111820  *  0b1..Data present
111821  *  0b0..No data present
111822  */
111823 #define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
111824 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
111825 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
111826 /*! CMDTYP - Command type
111827  *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
111828  *  0b10..Resume CMD52 for writing function select in CCCR
111829  *  0b01..Suspend CMD52 for writing bus suspend in CCCR
111830  *  0b00..Normal other commands
111831  */
111832 #define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
111833 #define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
111834 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
111835 /*! CMDINX - Command index
111836  */
111837 #define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
111838 /*! @} */
111839 
111840 /*! @name CMD_RSP0 - Command Response0 */
111841 /*! @{ */
111842 #define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
111843 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
111844 /*! CMDRSP0 - Command response 0
111845  */
111846 #define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
111847 /*! @} */
111848 
111849 /*! @name CMD_RSP1 - Command Response1 */
111850 /*! @{ */
111851 #define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
111852 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
111853 /*! CMDRSP1 - Command response 1
111854  */
111855 #define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
111856 /*! @} */
111857 
111858 /*! @name CMD_RSP2 - Command Response2 */
111859 /*! @{ */
111860 #define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
111861 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
111862 /*! CMDRSP2 - Command response 2
111863  */
111864 #define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
111865 /*! @} */
111866 
111867 /*! @name CMD_RSP3 - Command Response3 */
111868 /*! @{ */
111869 #define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
111870 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
111871 /*! CMDRSP3 - Command response 3
111872  */
111873 #define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
111874 /*! @} */
111875 
111876 /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
111877 /*! @{ */
111878 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
111879 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
111880 /*! DATCONT - Data content
111881  */
111882 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
111883 /*! @} */
111884 
111885 /*! @name PRES_STATE - Present State */
111886 /*! @{ */
111887 #define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
111888 #define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
111889 /*! CIHB - Command inhibit (CMD)
111890  *  0b1..Cannot issue command
111891  *  0b0..Can issue command using only CMD line
111892  */
111893 #define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
111894 #define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
111895 #define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
111896 /*! CDIHB - Command inhibit (DATA)
111897  *  0b1..Cannot issue command that uses the DATA line
111898  *  0b0..Can issue command that uses the DATA line
111899  */
111900 #define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
111901 #define USDHC_PRES_STATE_DLA_MASK                (0x4U)
111902 #define USDHC_PRES_STATE_DLA_SHIFT               (2U)
111903 /*! DLA - Data line active
111904  *  0b1..DATA line active
111905  *  0b0..DATA line inactive
111906  */
111907 #define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
111908 #define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
111909 #define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
111910 /*! SDSTB - SD clock stable
111911  *  0b1..Clock is stable.
111912  *  0b0..Clock is changing frequency and not stable.
111913  */
111914 #define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
111915 #define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
111916 #define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
111917 /*! IPGOFF - Peripheral clock gated off internally
111918  *  0b1..Peripheral clock is gated off.
111919  *  0b0..Peripheral clock is active.
111920  */
111921 #define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
111922 #define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
111923 #define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
111924 /*! HCKOFF - HCLK gated off internally
111925  *  0b1..HCLK is gated off.
111926  *  0b0..HCLK is active.
111927  */
111928 #define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
111929 #define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
111930 #define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
111931 /*! PEROFF - IPG_PERCLK gated off internally
111932  *  0b1..IPG_PERCLK is gated off.
111933  *  0b0..IPG_PERCLK is active.
111934  */
111935 #define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
111936 #define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
111937 #define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
111938 /*! SDOFF - SD clock gated off internally
111939  *  0b1..SD clock is gated off.
111940  *  0b0..SD clock is active.
111941  */
111942 #define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
111943 #define USDHC_PRES_STATE_WTA_MASK                (0x100U)
111944 #define USDHC_PRES_STATE_WTA_SHIFT               (8U)
111945 /*! WTA - Write transfer active
111946  *  0b1..Transferring data
111947  *  0b0..No valid data
111948  */
111949 #define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
111950 #define USDHC_PRES_STATE_RTA_MASK                (0x200U)
111951 #define USDHC_PRES_STATE_RTA_SHIFT               (9U)
111952 /*! RTA - Read transfer active
111953  *  0b1..Transferring data
111954  *  0b0..No valid data
111955  */
111956 #define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
111957 #define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
111958 #define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
111959 /*! BWEN - Buffer write enable
111960  *  0b1..Write enable
111961  *  0b0..Write disable
111962  */
111963 #define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
111964 #define USDHC_PRES_STATE_BREN_MASK               (0x800U)
111965 #define USDHC_PRES_STATE_BREN_SHIFT              (11U)
111966 /*! BREN - Buffer read enable
111967  *  0b1..Read enable
111968  *  0b0..Read disable
111969  */
111970 #define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
111971 #define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
111972 #define USDHC_PRES_STATE_RTR_SHIFT               (12U)
111973 /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)
111974  *  0b1..Sampling clock needs re-tuning
111975  *  0b0..Fixed or well tuned sampling clock
111976  */
111977 #define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
111978 #define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
111979 #define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
111980 /*! TSCD - Tape select change done
111981  *  0b1..Delay cell select change is finished.
111982  *  0b0..Delay cell select change is not finished.
111983  */
111984 #define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
111985 #define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
111986 #define USDHC_PRES_STATE_CINST_SHIFT             (16U)
111987 /*! CINST - Card inserted
111988  *  0b1..Card inserted
111989  *  0b0..Power on reset or no card
111990  */
111991 #define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
111992 #define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
111993 #define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
111994 /*! CDPL - Card detect pin level
111995  *  0b1..Card present (CD_B = 0)
111996  *  0b0..No card present (CD_B = 1)
111997  */
111998 #define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
111999 #define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
112000 #define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
112001 /*! WPSPL - Write protect switch pin level
112002  *  0b1..Write enabled (WP = 0)
112003  *  0b0..Write protected (WP = 1)
112004  */
112005 #define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
112006 #define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
112007 #define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
112008 /*! CLSL - CMD line signal level
112009  */
112010 #define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
112011 #define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
112012 #define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
112013 /*! DLSL - DATA[7:0] line signal level
112014  *  0b00000111..Data 7 line signal level
112015  *  0b00000110..Data 6 line signal level
112016  *  0b00000101..Data 5 line signal level
112017  *  0b00000100..Data 4 line signal level
112018  *  0b00000011..Data 3 line signal level
112019  *  0b00000010..Data 2 line signal level
112020  *  0b00000001..Data 1 line signal level
112021  *  0b00000000..Data 0 line signal level
112022  */
112023 #define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
112024 /*! @} */
112025 
112026 /*! @name PROT_CTRL - Protocol Control */
112027 /*! @{ */
112028 #define USDHC_PROT_CTRL_LCTL_MASK                (0x1U)
112029 #define USDHC_PROT_CTRL_LCTL_SHIFT               (0U)
112030 /*! LCTL - LED control
112031  *  0b1..LED on
112032  *  0b0..LED off
112033  */
112034 #define USDHC_PROT_CTRL_LCTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
112035 #define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
112036 #define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
112037 /*! DTW - Data transfer width
112038  *  0b10..8-bit mode
112039  *  0b01..4-bit mode
112040  *  0b00..1-bit mode
112041  *  0b11..Reserved
112042  */
112043 #define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
112044 #define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
112045 #define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
112046 /*! D3CD - DATA3 as card detection pin
112047  *  0b1..DATA3 as card detection pin
112048  *  0b0..DATA3 does not monitor card insertion
112049  */
112050 #define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
112051 #define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
112052 #define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
112053 /*! EMODE - Endian mode
112054  *  0b00..Big endian mode
112055  *  0b01..Half word big endian mode
112056  *  0b10..Little endian mode
112057  *  0b11..Reserved
112058  */
112059 #define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
112060 #define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
112061 #define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
112062 /*! CDTL - Card detect test level
112063  *  0b1..Card detect test level is 1, card inserted
112064  *  0b0..Card detect test level is 0, no card inserted
112065  */
112066 #define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
112067 #define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
112068 #define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
112069 /*! CDSS - Card detect signal selection
112070  *  0b1..Card detection test level is selected (for test purpose).
112071  *  0b0..Card detection level is selected (for normal purpose).
112072  */
112073 #define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
112074 #define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
112075 #define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
112076 /*! DMASEL - DMA select
112077  *  0b00..No DMA or simple DMA is selected.
112078  *  0b01..ADMA1 is selected.
112079  *  0b10..ADMA2 is selected.
112080  *  0b11..Reserved
112081  */
112082 #define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
112083 #define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
112084 #define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
112085 /*! SABGREQ - Stop at block gap request
112086  *  0b1..Stop
112087  *  0b0..Transfer
112088  */
112089 #define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
112090 #define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
112091 #define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
112092 /*! CREQ - Continue request
112093  *  0b1..Restart
112094  *  0b0..No effect
112095  */
112096 #define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
112097 #define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
112098 #define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
112099 /*! RWCTL - Read wait control
112100  *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
112101  *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
112102  */
112103 #define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
112104 #define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
112105 #define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
112106 /*! IABG - Interrupt at block gap
112107  *  0b1..Enables interrupt at block gap
112108  *  0b0..Disables interrupt at block gap
112109  */
112110 #define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
112111 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
112112 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
112113 /*! RD_DONE_NO_8CLK - Read performed number 8 clock
112114  */
112115 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
112116 #define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
112117 #define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
112118 /*! WECINT - Wakeup event enable on card interrupt
112119  *  0b1..Enables wakeup event enable on card interrupt
112120  *  0b0..Disables wakeup event enable on card interrupt
112121  */
112122 #define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
112123 #define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
112124 #define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
112125 /*! WECINS - Wakeup event enable on SD card insertion
112126  *  0b1..Enable wakeup event enable on SD card insertion
112127  *  0b0..Disable wakeup event enable on SD card insertion
112128  */
112129 #define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
112130 #define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
112131 #define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
112132 /*! WECRM - Wakeup event enable on SD card removal
112133  *  0b1..Enables wakeup event enable on SD card removal
112134  *  0b0..Disables wakeup event enable on SD card removal
112135  */
112136 #define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
112137 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
112138 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
112139 /*! NON_EXACT_BLK_RD - Non-exact block read
112140  *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
112141  *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
112142  */
112143 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
112144 /*! @} */
112145 
112146 /*! @name SYS_CTRL - System Control */
112147 /*! @{ */
112148 #define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
112149 #define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
112150 /*! DVS - Divisor
112151  *  0b0000..Divide-by-1
112152  *  0b0001..Divide-by-2
112153  *  0b1110..Divide-by-15
112154  *  0b1111..Divide-by-16
112155  */
112156 #define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
112157 #define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
112158 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
112159 /*! SDCLKFS - SDCLK frequency select
112160  */
112161 #define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
112162 #define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
112163 #define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
112164 /*! DTOCV - Data timeout counter value
112165  *  0b1111..SDCLK x 2 29
112166  *  0b1110..SDCLK x 2 28
112167  *  0b1101..SDCLK x 2 27
112168  *  0b1100..SDCLK x 2 26
112169  *  0b1011..SDCLK x 2 25
112170  *  0b1010..SDCLK x 2 24
112171  *  0b1001..SDCLK x 2 23
112172  *  0b1000..SDCLK x 2 22
112173  *  0b0111..SDCLK x 2 21
112174  *  0b0110..SDCLK x 2 20
112175  *  0b0101..SDCLK x 2 19
112176  *  0b0100..SDCLK x 2 18
112177  *  0b0011..SDCLK x 2 17
112178  *  0b0010..SDCLK x 2 16
112179  *  0b0001..SDCLK x 2 15
112180  *  0b0000..SDCLK x 2 14
112181  */
112182 #define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
112183 #define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
112184 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
112185 /*! IPP_RST_N - Hardware reset
112186  */
112187 #define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
112188 #define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
112189 #define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
112190 /*! RSTA - Software reset for all
112191  *  0b1..Reset
112192  *  0b0..No reset
112193  */
112194 #define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
112195 #define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
112196 #define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
112197 /*! RSTC - Software reset for CMD line
112198  *  0b1..Reset
112199  *  0b0..No reset
112200  */
112201 #define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
112202 #define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
112203 #define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
112204 /*! RSTD - Software reset for data line
112205  *  0b1..Reset
112206  *  0b0..No reset
112207  */
112208 #define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
112209 #define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
112210 #define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
112211 /*! INITA - Initialization active
112212  */
112213 #define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
112214 #define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
112215 #define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
112216 /*! RSTT - Reset tuning
112217  */
112218 #define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
112219 /*! @} */
112220 
112221 /*! @name INT_STATUS - Interrupt Status */
112222 /*! @{ */
112223 #define USDHC_INT_STATUS_CC_MASK                 (0x1U)
112224 #define USDHC_INT_STATUS_CC_SHIFT                (0U)
112225 /*! CC - Command complete
112226  *  0b1..Command complete
112227  *  0b0..Command not complete
112228  */
112229 #define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
112230 #define USDHC_INT_STATUS_TC_MASK                 (0x2U)
112231 #define USDHC_INT_STATUS_TC_SHIFT                (1U)
112232 /*! TC - Transfer complete
112233  *  0b1..Transfer complete
112234  *  0b0..Transfer does not complete
112235  */
112236 #define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
112237 #define USDHC_INT_STATUS_BGE_MASK                (0x4U)
112238 #define USDHC_INT_STATUS_BGE_SHIFT               (2U)
112239 /*! BGE - Block gap event
112240  *  0b1..Transaction stopped at block gap
112241  *  0b0..No block gap event
112242  */
112243 #define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
112244 #define USDHC_INT_STATUS_DINT_MASK               (0x8U)
112245 #define USDHC_INT_STATUS_DINT_SHIFT              (3U)
112246 /*! DINT - DMA interrupt
112247  *  0b1..DMA interrupt is generated.
112248  *  0b0..No DMA interrupt
112249  */
112250 #define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
112251 #define USDHC_INT_STATUS_BWR_MASK                (0x10U)
112252 #define USDHC_INT_STATUS_BWR_SHIFT               (4U)
112253 /*! BWR - Buffer write ready
112254  *  0b1..Ready to write buffer
112255  *  0b0..Not ready to write buffer
112256  */
112257 #define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
112258 #define USDHC_INT_STATUS_BRR_MASK                (0x20U)
112259 #define USDHC_INT_STATUS_BRR_SHIFT               (5U)
112260 /*! BRR - Buffer read ready
112261  *  0b1..Ready to read buffer
112262  *  0b0..Not ready to read buffer
112263  */
112264 #define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
112265 #define USDHC_INT_STATUS_CINS_MASK               (0x40U)
112266 #define USDHC_INT_STATUS_CINS_SHIFT              (6U)
112267 /*! CINS - Card insertion
112268  *  0b1..Card inserted
112269  *  0b0..Card state unstable or removed
112270  */
112271 #define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
112272 #define USDHC_INT_STATUS_CRM_MASK                (0x80U)
112273 #define USDHC_INT_STATUS_CRM_SHIFT               (7U)
112274 /*! CRM - Card removal
112275  *  0b1..Card removed
112276  *  0b0..Card state unstable or inserted
112277  */
112278 #define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
112279 #define USDHC_INT_STATUS_CINT_MASK               (0x100U)
112280 #define USDHC_INT_STATUS_CINT_SHIFT              (8U)
112281 /*! CINT - Card interrupt
112282  *  0b1..Generate card interrupt
112283  *  0b0..No card interrupt
112284  */
112285 #define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
112286 #define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
112287 #define USDHC_INT_STATUS_RTE_SHIFT               (12U)
112288 /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
112289  *  0b1..Re-tuning should be performed.
112290  *  0b0..Re-tuning is not required.
112291  */
112292 #define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
112293 #define USDHC_INT_STATUS_TP_MASK                 (0x2000U)
112294 #define USDHC_INT_STATUS_TP_SHIFT                (13U)
112295 /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)
112296  */
112297 #define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
112298 #define USDHC_INT_STATUS_CQI_MASK                (0x4000U)
112299 #define USDHC_INT_STATUS_CQI_SHIFT               (14U)
112300 /*! CQI - Command queuing interrupt
112301  */
112302 #define USDHC_INT_STATUS_CQI(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK)
112303 #define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
112304 #define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
112305 /*! CTOE - Command timeout error
112306  *  0b1..Time out
112307  *  0b0..No error
112308  */
112309 #define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
112310 #define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
112311 #define USDHC_INT_STATUS_CCE_SHIFT               (17U)
112312 /*! CCE - Command CRC error
112313  *  0b1..CRC error generated
112314  *  0b0..No error
112315  */
112316 #define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
112317 #define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
112318 #define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
112319 /*! CEBE - Command end bit error
112320  *  0b1..End bit error generated
112321  *  0b0..No error
112322  */
112323 #define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
112324 #define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
112325 #define USDHC_INT_STATUS_CIE_SHIFT               (19U)
112326 /*! CIE - Command index error
112327  *  0b1..Error
112328  *  0b0..No error
112329  */
112330 #define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
112331 #define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
112332 #define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
112333 /*! DTOE - Data timeout error
112334  *  0b1..Time out
112335  *  0b0..No error
112336  */
112337 #define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
112338 #define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
112339 #define USDHC_INT_STATUS_DCE_SHIFT               (21U)
112340 /*! DCE - Data CRC error
112341  *  0b1..Error
112342  *  0b0..No error
112343  */
112344 #define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
112345 #define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
112346 #define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
112347 /*! DEBE - Data end bit error
112348  *  0b1..Error
112349  *  0b0..No error
112350  */
112351 #define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
112352 #define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
112353 #define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
112354 /*! AC12E - Auto CMD12 error
112355  *  0b1..Error
112356  *  0b0..No error
112357  */
112358 #define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
112359 #define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
112360 #define USDHC_INT_STATUS_TNE_SHIFT               (26U)
112361 /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
112362  */
112363 #define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
112364 #define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
112365 #define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
112366 /*! DMAE - DMA error
112367  *  0b1..Error
112368  *  0b0..No error
112369  */
112370 #define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
112371 /*! @} */
112372 
112373 /*! @name INT_STATUS_EN - Interrupt Status Enable */
112374 /*! @{ */
112375 #define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
112376 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
112377 /*! CCSEN - Command complete status enable
112378  *  0b1..Enabled
112379  *  0b0..Masked
112380  */
112381 #define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
112382 #define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
112383 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
112384 /*! TCSEN - Transfer complete status enable
112385  *  0b1..Enabled
112386  *  0b0..Masked
112387  */
112388 #define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
112389 #define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
112390 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
112391 /*! BGESEN - Block gap event status enable
112392  *  0b1..Enabled
112393  *  0b0..Masked
112394  */
112395 #define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
112396 #define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
112397 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
112398 /*! DINTSEN - DMA interrupt status enable
112399  *  0b1..Enabled
112400  *  0b0..Masked
112401  */
112402 #define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
112403 #define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
112404 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
112405 /*! BWRSEN - Buffer write ready status enable
112406  *  0b1..Enabled
112407  *  0b0..Masked
112408  */
112409 #define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
112410 #define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
112411 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
112412 /*! BRRSEN - Buffer read ready status enable
112413  *  0b1..Enabled
112414  *  0b0..Masked
112415  */
112416 #define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
112417 #define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
112418 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
112419 /*! CINSSEN - Card insertion status enable
112420  *  0b1..Enabled
112421  *  0b0..Masked
112422  */
112423 #define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
112424 #define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
112425 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
112426 /*! CRMSEN - Card removal status enable
112427  *  0b1..Enabled
112428  *  0b0..Masked
112429  */
112430 #define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
112431 #define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
112432 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
112433 /*! CINTSEN - Card interrupt status enable
112434  *  0b1..Enabled
112435  *  0b0..Masked
112436  */
112437 #define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
112438 #define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
112439 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
112440 /*! RTESEN - Re-tuning event status enable
112441  *  0b1..Enabled
112442  *  0b0..Masked
112443  */
112444 #define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
112445 #define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x2000U)
112446 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (13U)
112447 /*! TPSEN - Tuning pass status enable
112448  *  0b1..Enabled
112449  *  0b0..Masked
112450  */
112451 #define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
112452 #define USDHC_INT_STATUS_EN_CQISEN_MASK          (0x4000U)
112453 #define USDHC_INT_STATUS_EN_CQISEN_SHIFT         (14U)
112454 /*! CQISEN - Command queuing status enable
112455  *  0b1..Enabled
112456  *  0b0..Masked
112457  */
112458 #define USDHC_INT_STATUS_EN_CQISEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK)
112459 #define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
112460 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
112461 /*! CTOESEN - Command timeout error status enable
112462  *  0b1..Enabled
112463  *  0b0..Masked
112464  */
112465 #define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
112466 #define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
112467 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
112468 /*! CCESEN - Command CRC error status enable
112469  *  0b1..Enabled
112470  *  0b0..Masked
112471  */
112472 #define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
112473 #define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
112474 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
112475 /*! CEBESEN - Command end bit error status enable
112476  *  0b1..Enabled
112477  *  0b0..Masked
112478  */
112479 #define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
112480 #define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
112481 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
112482 /*! CIESEN - Command index error status enable
112483  *  0b1..Enabled
112484  *  0b0..Masked
112485  */
112486 #define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
112487 #define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
112488 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
112489 /*! DTOESEN - Data timeout error status enable
112490  *  0b1..Enabled
112491  *  0b0..Masked
112492  */
112493 #define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
112494 #define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
112495 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
112496 /*! DCESEN - Data CRC error status enable
112497  *  0b1..Enabled
112498  *  0b0..Masked
112499  */
112500 #define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
112501 #define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
112502 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
112503 /*! DEBESEN - Data end bit error status enable
112504  *  0b1..Enabled
112505  *  0b0..Masked
112506  */
112507 #define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
112508 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
112509 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
112510 /*! AC12ESEN - Auto CMD12 error status enable
112511  *  0b1..Enabled
112512  *  0b0..Masked
112513  */
112514 #define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
112515 #define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
112516 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
112517 /*! TNESEN - Tuning error status enable
112518  *  0b1..Enabled
112519  *  0b0..Masked
112520  */
112521 #define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
112522 #define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
112523 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
112524 /*! DMAESEN - DMA error status enable
112525  *  0b1..Enabled
112526  *  0b0..Masked
112527  */
112528 #define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
112529 /*! @} */
112530 
112531 /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
112532 /*! @{ */
112533 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
112534 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
112535 /*! CCIEN - Command complete interrupt enable
112536  *  0b1..Enabled
112537  *  0b0..Masked
112538  */
112539 #define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
112540 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
112541 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
112542 /*! TCIEN - Transfer complete interrupt enable
112543  *  0b1..Enabled
112544  *  0b0..Masked
112545  */
112546 #define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
112547 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
112548 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
112549 /*! BGEIEN - Block gap event interrupt enable
112550  *  0b1..Enabled
112551  *  0b0..Masked
112552  */
112553 #define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
112554 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
112555 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
112556 /*! DINTIEN - DMA interrupt enable
112557  *  0b1..Enabled
112558  *  0b0..Masked
112559  */
112560 #define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
112561 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
112562 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
112563 /*! BWRIEN - Buffer write ready interrupt enable
112564  *  0b1..Enabled
112565  *  0b0..Masked
112566  */
112567 #define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
112568 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
112569 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
112570 /*! BRRIEN - Buffer read ready interrupt enable
112571  *  0b1..Enabled
112572  *  0b0..Masked
112573  */
112574 #define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
112575 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
112576 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
112577 /*! CINSIEN - Card insertion interrupt enable
112578  *  0b1..Enabled
112579  *  0b0..Masked
112580  */
112581 #define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
112582 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
112583 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
112584 /*! CRMIEN - Card removal interrupt enable
112585  *  0b1..Enabled
112586  *  0b0..Masked
112587  */
112588 #define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
112589 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
112590 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
112591 /*! CINTIEN - Card interrupt enable
112592  *  0b1..Enabled
112593  *  0b0..Masked
112594  */
112595 #define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
112596 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
112597 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
112598 /*! RTEIEN - Re-tuning event interrupt enable
112599  *  0b1..Enabled
112600  *  0b0..Masked
112601  */
112602 #define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
112603 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x2000U)
112604 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (13U)
112605 /*! TPIEN - Tuning pass interrupt enable
112606  *  0b1..Enabled
112607  *  0b0..Masked
112608  */
112609 #define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
112610 #define USDHC_INT_SIGNAL_EN_CQIIEN_MASK          (0x4000U)
112611 #define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT         (14U)
112612 /*! CQIIEN - Command queuing signal enable
112613  *  0b1..Enabled
112614  *  0b0..Masked
112615  */
112616 #define USDHC_INT_SIGNAL_EN_CQIIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK)
112617 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
112618 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
112619 /*! CTOEIEN - Command timeout error interrupt enable
112620  *  0b1..Enabled
112621  *  0b0..Masked
112622  */
112623 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
112624 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
112625 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
112626 /*! CCEIEN - Command CRC error interrupt enable
112627  *  0b1..Enabled
112628  *  0b0..Masked
112629  */
112630 #define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
112631 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
112632 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
112633 /*! CEBEIEN - Command end bit error interrupt enable
112634  *  0b1..Enabled
112635  *  0b0..Masked
112636  */
112637 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
112638 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
112639 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
112640 /*! CIEIEN - Command index error interrupt enable
112641  *  0b1..Enabled
112642  *  0b0..Masked
112643  */
112644 #define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
112645 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
112646 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
112647 /*! DTOEIEN - Data timeout error interrupt enable
112648  *  0b1..Enabled
112649  *  0b0..Masked
112650  */
112651 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
112652 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
112653 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
112654 /*! DCEIEN - Data CRC error interrupt enable
112655  *  0b1..Enabled
112656  *  0b0..Masked
112657  */
112658 #define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
112659 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
112660 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
112661 /*! DEBEIEN - Data end bit error interrupt enable
112662  *  0b1..Enabled
112663  *  0b0..Masked
112664  */
112665 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
112666 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
112667 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
112668 /*! AC12EIEN - Auto CMD12 error interrupt enable
112669  *  0b1..Enabled
112670  *  0b0..Masked
112671  */
112672 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
112673 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
112674 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
112675 /*! TNEIEN - Tuning error interrupt enable
112676  *  0b1..Enabled
112677  *  0b0..Masked
112678  */
112679 #define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
112680 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
112681 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
112682 /*! DMAEIEN - DMA error interrupt enable
112683  *  0b1..Enable
112684  *  0b0..Masked
112685  */
112686 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
112687 /*! @} */
112688 
112689 /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
112690 /*! @{ */
112691 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
112692 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
112693 /*! AC12NE - Auto CMD12 not executed
112694  *  0b1..Not executed
112695  *  0b0..Executed
112696  */
112697 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
112698 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
112699 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
112700 /*! AC12TOE - Auto CMD12 / 23 timeout error
112701  *  0b1..Time out
112702  *  0b0..No error
112703  */
112704 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
112705 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
112706 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
112707 /*! AC12EBE - Auto CMD12 / 23 end bit error
112708  *  0b1..End bit error generated
112709  *  0b0..No error
112710  */
112711 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
112712 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
112713 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
112714 /*! AC12CE - Auto CMD12 / 23 CRC error
112715  *  0b1..CRC error met in Auto CMD12/23 response
112716  *  0b0..No CRC error
112717  */
112718 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
112719 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
112720 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
112721 /*! AC12IE - Auto CMD12 / 23 index error
112722  *  0b1..Error, the CMD index in response is not CMD12/23
112723  *  0b0..No error
112724  */
112725 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
112726 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
112727 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
112728 /*! CNIBAC12E - Command not issued by Auto CMD12 error
112729  *  0b1..Not issued
112730  *  0b0..No error
112731  */
112732 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
112733 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
112734 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
112735 /*! EXECUTE_TUNING - Execute tuning
112736  */
112737 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
112738 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
112739 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
112740 /*! SMP_CLK_SEL - Sample clock select
112741  *  0b1..Tuned clock is used to sample data
112742  *  0b0..Fixed clock is used to sample data
112743  */
112744 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
112745 /*! @} */
112746 
112747 /*! @name HOST_CTRL_CAP - Host Controller Capabilities */
112748 /*! @{ */
112749 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
112750 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
112751 /*! SDR50_SUPPORT - SDR50 support
112752  */
112753 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
112754 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
112755 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
112756 /*! SDR104_SUPPORT - SDR104 support
112757  */
112758 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
112759 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
112760 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
112761 /*! DDR50_SUPPORT - DDR50 support
112762  */
112763 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
112764 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
112765 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
112766 /*! TIME_COUNT_RETUNING - Time counter for retuning
112767  */
112768 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
112769 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
112770 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
112771 /*! USE_TUNING_SDR50 - Use Tuning for SDR50
112772  *  0b1..SDR50 requires tuning.
112773  *  0b0..SDR does not require tuning.
112774  */
112775 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
112776 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK   (0xC000U)
112777 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT  (14U)
112778 /*! RETUNING_MODE - Retuning Mode
112779  *  0b00..Mode 1
112780  *  0b01..Mode 2
112781  *  0b10..Mode 3
112782  *  0b11..Reserved
112783  */
112784 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
112785 #define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
112786 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
112787 /*! MBL - Max block length
112788  *  0b000..512 bytes
112789  *  0b001..1024 bytes
112790  *  0b010..2048 bytes
112791  *  0b011..4096 bytes
112792  */
112793 #define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
112794 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
112795 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
112796 /*! ADMAS - ADMA support
112797  *  0b1..Advanced DMA supported
112798  *  0b0..Advanced DMA not supported
112799  */
112800 #define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
112801 #define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
112802 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
112803 /*! HSS - High speed support
112804  *  0b1..High speed supported
112805  *  0b0..High speed not supported
112806  */
112807 #define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
112808 #define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
112809 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
112810 /*! DMAS - DMA support
112811  *  0b1..DMA supported
112812  *  0b0..DMA not supported
112813  */
112814 #define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
112815 #define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
112816 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
112817 /*! SRS - Suspend / resume support
112818  *  0b1..Supported
112819  *  0b0..Not supported
112820  */
112821 #define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
112822 #define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
112823 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
112824 /*! VS33 - Voltage support 3.3 V
112825  *  0b1..3.3 V supported
112826  *  0b0..3.3 V not supported
112827  */
112828 #define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
112829 #define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
112830 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
112831 /*! VS30 - Voltage support 3.0 V
112832  *  0b1..3.0 V supported
112833  *  0b0..3.0 V not supported
112834  */
112835 #define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
112836 #define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
112837 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
112838 /*! VS18 - Voltage support 1.8 V
112839  *  0b1..1.8 V supported
112840  *  0b0..1.8 V not supported
112841  */
112842 #define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
112843 /*! @} */
112844 
112845 /*! @name WTMK_LVL - Watermark Level */
112846 /*! @{ */
112847 #define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
112848 #define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
112849 /*! RD_WML - Read watermark level
112850  */
112851 #define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
112852 #define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
112853 #define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
112854 /*! WR_WML - Write watermark level
112855  */
112856 #define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
112857 /*! @} */
112858 
112859 /*! @name MIX_CTRL - Mixer Control */
112860 /*! @{ */
112861 #define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
112862 #define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
112863 /*! DMAEN - DMA enable
112864  *  0b1..Enable
112865  *  0b0..Disable
112866  */
112867 #define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
112868 #define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
112869 #define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
112870 /*! BCEN - Block count enable
112871  *  0b1..Enable
112872  *  0b0..Disable
112873  */
112874 #define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
112875 #define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
112876 #define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
112877 /*! AC12EN - Auto CMD12 enable
112878  *  0b1..Enable
112879  *  0b0..Disable
112880  */
112881 #define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
112882 #define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
112883 #define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
112884 /*! DDR_EN - Dual data rate mode selection
112885  */
112886 #define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
112887 #define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
112888 #define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
112889 /*! DTDSEL - Data transfer direction select
112890  *  0b1..Read (Card to host)
112891  *  0b0..Write (Host to card)
112892  */
112893 #define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
112894 #define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
112895 #define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
112896 /*! MSBSEL - Multi / Single block select
112897  *  0b1..Multiple blocks
112898  *  0b0..Single block
112899  */
112900 #define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
112901 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
112902 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
112903 /*! NIBBLE_POS - Nibble position indication
112904  */
112905 #define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
112906 #define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
112907 #define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
112908 /*! AC23EN - Auto CMD23 enable
112909  */
112910 #define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
112911 #define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
112912 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
112913 /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
112914  *  0b1..Execute tuning
112915  *  0b0..Not tuned or tuning completed
112916  */
112917 #define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
112918 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
112919 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
112920 /*! SMP_CLK_SEL - Clock selection
112921  *  0b1..Tuned clock is used to sample data / cmd
112922  *  0b0..Fixed clock is used to sample data / cmd
112923  */
112924 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
112925 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
112926 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
112927 /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
112928  *  0b1..Enable auto tuning
112929  *  0b0..Disable auto tuning
112930  */
112931 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
112932 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
112933 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
112934 /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
112935  *  0b1..Feedback clock comes from the ipp_card_clk_out
112936  *  0b0..Feedback clock comes from the loopback CLK
112937  */
112938 #define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
112939 #define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
112940 #define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
112941 /*! HS400_MODE - Enable HS400 mode
112942  */
112943 #define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
112944 #define USDHC_MIX_CTRL_EN_HS400_MODE_MASK        (0x8000000U)
112945 #define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT       (27U)
112946 /*! EN_HS400_MODE - Enable enhance HS400 mode
112947  */
112948 #define USDHC_MIX_CTRL_EN_HS400_MODE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK)
112949 /*! @} */
112950 
112951 /*! @name FORCE_EVENT - Force Event */
112952 /*! @{ */
112953 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
112954 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
112955 /*! FEVTAC12NE - Force event auto command 12 not executed
112956  */
112957 #define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
112958 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
112959 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
112960 /*! FEVTAC12TOE - Force event auto command 12 time out error
112961  */
112962 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
112963 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
112964 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
112965 /*! FEVTAC12CE - Force event auto command 12 CRC error
112966  */
112967 #define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
112968 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
112969 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
112970 /*! FEVTAC12EBE - Force event Auto Command 12 end bit error
112971  */
112972 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
112973 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
112974 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
112975 /*! FEVTAC12IE - Force event Auto Command 12 index error
112976  */
112977 #define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
112978 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
112979 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
112980 /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error
112981  */
112982 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
112983 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
112984 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
112985 /*! FEVTCTOE - Force event command time out error
112986  */
112987 #define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
112988 #define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
112989 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
112990 /*! FEVTCCE - Force event command CRC error
112991  */
112992 #define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
112993 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
112994 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
112995 /*! FEVTCEBE - Force event command end bit error
112996  */
112997 #define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
112998 #define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
112999 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
113000 /*! FEVTCIE - Force event command index error
113001  */
113002 #define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
113003 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
113004 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
113005 /*! FEVTDTOE - Force event data time out error
113006  */
113007 #define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
113008 #define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
113009 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
113010 /*! FEVTDCE - Force event data CRC error
113011  */
113012 #define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
113013 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
113014 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
113015 /*! FEVTDEBE - Force event data end bit error
113016  */
113017 #define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
113018 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
113019 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
113020 /*! FEVTAC12E - Force event Auto Command 12 error
113021  */
113022 #define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
113023 #define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
113024 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
113025 /*! FEVTTNE - Force tuning error
113026  */
113027 #define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
113028 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
113029 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
113030 /*! FEVTDMAE - Force event DMA error
113031  */
113032 #define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
113033 #define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
113034 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
113035 /*! FEVTCINT - Force event card interrupt
113036  */
113037 #define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
113038 /*! @} */
113039 
113040 /*! @name ADMA_ERR_STATUS - ADMA Error Status */
113041 /*! @{ */
113042 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
113043 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
113044 /*! ADMAES - ADMA error state (when ADMA error is occurred)
113045  */
113046 #define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
113047 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
113048 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
113049 /*! ADMALME - ADMA length mismatch error
113050  *  0b1..Error
113051  *  0b0..No error
113052  */
113053 #define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
113054 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
113055 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
113056 /*! ADMADCE - ADMA descriptor error
113057  *  0b1..Error
113058  *  0b0..No error
113059  */
113060 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
113061 /*! @} */
113062 
113063 /*! @name ADMA_SYS_ADDR - ADMA System Address */
113064 /*! @{ */
113065 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
113066 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
113067 /*! ADS_ADDR - ADMA system address
113068  */
113069 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
113070 /*! @} */
113071 
113072 /*! @name DLL_CTRL - DLL (Delay Line) Control */
113073 /*! @{ */
113074 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
113075 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
113076 /*! DLL_CTRL_ENABLE - DLL and delay chain
113077  */
113078 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
113079 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
113080 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
113081 /*! DLL_CTRL_RESET - DLL reset
113082  */
113083 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
113084 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
113085 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
113086 /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line
113087  */
113088 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
113089 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
113090 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
113091 /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0
113092  */
113093 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
113094 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
113095 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
113096 /*! DLL_CTRL_GATE_UPDATE - DLL gate update
113097  */
113098 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
113099 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
113100 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
113101 /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override
113102  */
113103 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
113104 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
113105 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
113106 /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val
113107  */
113108 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
113109 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
113110 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
113111 /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1
113112  */
113113 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
113114 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
113115 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
113116 /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval
113117  */
113118 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
113119 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
113120 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
113121 /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval
113122  */
113123 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
113124 /*! @} */
113125 
113126 /*! @name DLL_STATUS - DLL Status */
113127 /*! @{ */
113128 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
113129 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
113130 /*! DLL_STS_SLV_LOCK - Slave delay-line lock status
113131  */
113132 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
113133 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
113134 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
113135 /*! DLL_STS_REF_LOCK - Reference DLL lock status
113136  */
113137 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
113138 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
113139 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
113140 /*! DLL_STS_SLV_SEL - Slave delay line select status
113141  */
113142 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
113143 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
113144 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
113145 /*! DLL_STS_REF_SEL - Reference delay line select taps
113146  */
113147 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
113148 /*! @} */
113149 
113150 /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
113151 /*! @{ */
113152 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
113153 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
113154 /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST
113155  */
113156 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
113157 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
113158 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
113159 /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT
113160  */
113161 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
113162 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
113163 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
113164 /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE
113165  */
113166 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
113167 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
113168 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
113169 /*! NXT_ERR - NXT error
113170  */
113171 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
113172 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
113173 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
113174 /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST
113175  */
113176 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
113177 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
113178 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
113179 /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT
113180  */
113181 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
113182 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
113183 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
113184 /*! TAP_SEL_PRE - TAP_SEL_PRE
113185  */
113186 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
113187 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
113188 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
113189 /*! PRE_ERR - PRE error
113190  */
113191 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
113192 /*! @} */
113193 
113194 /*! @name STROBE_DLL_CTRL - Strobe DLL control */
113195 /*! @{ */
113196 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
113197 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
113198 /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable
113199  */
113200 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
113201 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
113202 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
113203 /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset
113204  */
113205 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
113206 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
113207 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
113208 /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated
113209  */
113210 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
113211 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U)
113212 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
113213 /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target
113214  */
113215 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
113216 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U)
113217 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U)
113218 /*! STROBE_DLL_CTRL_GATE_UPDATE_0 - Strobe DLL control gate update
113219  */
113220 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK)
113221 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U)
113222 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U)
113223 /*! STROBE_DLL_CTRL_GATE_UPDATE_1 - Strobe DLL control gate update
113224  */
113225 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK)
113226 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
113227 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
113228 /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override
113229  */
113230 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
113231 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
113232 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
113233 /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value
113234  */
113235 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
113236 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
113237 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
113238 /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval
113239  */
113240 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
113241 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
113242 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
113243 /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval
113244  */
113245 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
113246 /*! @} */
113247 
113248 /*! @name STROBE_DLL_STATUS - Strobe DLL status */
113249 /*! @{ */
113250 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
113251 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
113252 /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock
113253  */
113254 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
113255 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
113256 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
113257 /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock
113258  */
113259 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
113260 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
113261 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
113262 /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select
113263  */
113264 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
113265 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
113266 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
113267 /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select
113268  */
113269 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
113270 /*! @} */
113271 
113272 /*! @name VEND_SPEC - Vendor Specific Register */
113273 /*! @{ */
113274 #define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
113275 #define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
113276 /*! VSELECT - Voltage selection
113277  *  0b1..Change the voltage to low voltage range, around 1.8 V
113278  *  0b0..Change the voltage to high voltage range, around 3.0 V
113279  */
113280 #define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
113281 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
113282 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
113283 /*! CONFLICT_CHK_EN - Conflict check enable
113284  *  0b0..Conflict check disable
113285  *  0b1..Conflict check enable
113286  */
113287 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
113288 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
113289 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
113290 /*! AC12_WR_CHKBUSY_EN - Check busy enable
113291  *  0b0..Do not check busy after auto CMD12 for write data packet
113292  *  0b1..Check busy after auto CMD12 for write data packet
113293  */
113294 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
113295 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
113296 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
113297 /*! FRC_SDCLK_ON - Force CLK
113298  *  0b0..CLK active or inactive is fully controlled by the hardware.
113299  *  0b1..Force CLK active
113300  */
113301 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
113302 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
113303 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
113304 /*! CRC_CHK_DIS - CRC Check Disable
113305  *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
113306  *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
113307  */
113308 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
113309 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
113310 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
113311 /*! CMD_BYTE_EN - Byte access
113312  *  0b0..Disable
113313  *  0b1..Enable
113314  */
113315 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
113316 /*! @} */
113317 
113318 /*! @name MMC_BOOT - MMC Boot */
113319 /*! @{ */
113320 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
113321 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
113322 /*! DTOCV_ACK - DTOCV_ACK
113323  *  0b0000..SDCLK x 2^32
113324  *  0b0001..SDCLK x 2^33
113325  *  0b0010..SDCLK x 2^18
113326  *  0b0011..SDCLK x 2^19
113327  *  0b0100..SDCLK x 2^20
113328  *  0b0101..SDCLK x 2^21
113329  *  0b0110..SDCLK x 2^22
113330  *  0b0111..SDCLK x 2^23
113331  *  0b1110..SDCLK x 2^30
113332  *  0b1111..SDCLK x 2^31
113333  */
113334 #define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
113335 #define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
113336 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
113337 /*! BOOT_ACK - BOOT ACK
113338  *  0b0..No ack
113339  *  0b1..Ack
113340  */
113341 #define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
113342 #define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
113343 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
113344 /*! BOOT_MODE - Boot mode
113345  *  0b0..Normal boot
113346  *  0b1..Alternative boot
113347  */
113348 #define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
113349 #define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
113350 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
113351 /*! BOOT_EN - Boot enable
113352  *  0b0..Fast boot disable
113353  *  0b1..Fast boot enable
113354  */
113355 #define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
113356 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
113357 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
113358 /*! AUTO_SABG_EN - Auto stop at block gap
113359  */
113360 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
113361 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
113362 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
113363 /*! DISABLE_TIME_OUT - Time out
113364  *  0b0..Enable time out
113365  *  0b1..Disable time out
113366  */
113367 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
113368 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
113369 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
113370 /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode
113371  */
113372 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
113373 /*! @} */
113374 
113375 /*! @name VEND_SPEC2 - Vendor Specific 2 Register */
113376 /*! @{ */
113377 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
113378 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
113379 /*! CARD_INT_D3_TEST - Card interrupt detection test
113380  *  0b0..Check the card interrupt only when DATA3 is high.
113381  *  0b1..Check the card interrupt by ignoring the status of DATA3.
113382  */
113383 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
113384 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     (0x10U)
113385 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    (4U)
113386 /*! TUNING_8bit_EN - Tuning 8bit enable
113387  */
113388 #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
113389 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     (0x20U)
113390 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    (5U)
113391 /*! TUNING_1bit_EN - Tuning 1bit enable
113392  */
113393 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
113394 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
113395 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
113396 /*! TUNING_CMD_EN - Tuning command enable
113397  *  0b0..Auto tuning circuit does not check the CMD line.
113398  *  0b1..Auto tuning circuit checks the CMD line.
113399  */
113400 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
113401 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
113402 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
113403 /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable
113404  */
113405 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
113406 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
113407 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
113408 /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable
113409  */
113410 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
113411 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
113412 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
113413 /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
113414  *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
113415  *  0b0..Disable
113416  */
113417 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
113418 #define USDHC_VEND_SPEC2_EN_32K_CLK_MASK         (0x8000U)
113419 #define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT        (15U)
113420 /*! EN_32K_CLK - Enable 32khz clock for card detection
113421  */
113422 #define USDHC_VEND_SPEC2_EN_32K_CLK(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK)
113423 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK      (0xFFFF0000U)
113424 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT     (16U)
113425 /*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock
113426  */
113427 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK)
113428 /*! @} */
113429 
113430 /*! @name TUNING_CTRL - Tuning Control */
113431 /*! @{ */
113432 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0xFFU)
113433 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
113434 /*! TUNING_START_TAP - Tuning start
113435  */
113436 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
113437 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
113438 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
113439 /*! TUNING_COUNTER - Tuning counter
113440  */
113441 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
113442 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
113443 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
113444 /*! TUNING_STEP - TUNING_STEP
113445  */
113446 #define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
113447 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
113448 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
113449 /*! TUNING_WINDOW - Data window
113450  */
113451 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
113452 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
113453 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
113454 /*! STD_TUNING_EN - Standard tuning circuit and procedure enable
113455  */
113456 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
113457 /*! @} */
113458 
113459 
113460 /*!
113461  * @}
113462  */ /* end of group USDHC_Register_Masks */
113463 
113464 
113465 /* USDHC - Peripheral instance base addresses */
113466 /** Peripheral CONNECTIVITY__USDHC0 base address */
113467 #define CONNECTIVITY__USDHC0_BASE                (0x5B010000u)
113468 /** Peripheral CONNECTIVITY__USDHC0 base pointer */
113469 #define CONNECTIVITY__USDHC0                     ((USDHC_Type *)CONNECTIVITY__USDHC0_BASE)
113470 /** Peripheral CONNECTIVITY__USDHC1 base address */
113471 #define CONNECTIVITY__USDHC1_BASE                (0x5B020000u)
113472 /** Peripheral CONNECTIVITY__USDHC1 base pointer */
113473 #define CONNECTIVITY__USDHC1                     ((USDHC_Type *)CONNECTIVITY__USDHC1_BASE)
113474 /** Peripheral CONNECTIVITY__USDHC2 base address */
113475 #define CONNECTIVITY__USDHC2_BASE                (0x5B030000u)
113476 /** Peripheral CONNECTIVITY__USDHC2 base pointer */
113477 #define CONNECTIVITY__USDHC2                     ((USDHC_Type *)CONNECTIVITY__USDHC2_BASE)
113478 /** Array initializer of USDHC peripheral base addresses */
113479 #define USDHC_BASE_ADDRS                         { CONNECTIVITY__USDHC0_BASE, CONNECTIVITY__USDHC1_BASE, CONNECTIVITY__USDHC2_BASE }
113480 /** Array initializer of USDHC peripheral base pointers */
113481 #define USDHC_BASE_PTRS                          { CONNECTIVITY__USDHC0, CONNECTIVITY__USDHC1, CONNECTIVITY__USDHC2 }
113482 /** Interrupt vectors for the USDHC peripheral type */
113483 #define USDHC_IRQS                               { CONNECTIVITY_USDHC0_INT_IRQn, CONNECTIVITY_USDHC1_INT_IRQn, CONNECTIVITY_USDHC2_INT_IRQn }
113484 
113485 /*!
113486  * @}
113487  */ /* end of group USDHC_Peripheral_Access_Layer */
113488 
113489 
113490 /* ----------------------------------------------------------------------------
113491    -- VPU_CSR Peripheral Access Layer
113492    ---------------------------------------------------------------------------- */
113493 
113494 /*!
113495  * @addtogroup VPU_CSR_Peripheral_Access_Layer VPU_CSR Peripheral Access Layer
113496  * @{
113497  */
113498 
113499 /** VPU_CSR - Register Layout Typedef */
113500 typedef struct {
113501   __IO uint32_t CM0PX_ADDR_OFFSET;                 /**< CM0Px Boot vector address offset, offset: 0x0 */
113502   __IO uint32_t CM0PX_CPUWAIT;                     /**< CM0Px CPUWAIT signal control, offset: 0x4 */
113503   __IO uint32_t CM0PX_CTL;                         /**< CM0Px Control register, offset: 0x8 */
113504   __I  uint32_t CM0PX_STAT;                        /**< CM0Px Status register, offset: 0xC */
113505   struct {                                         /* offset: 0x10 */
113506     __IO uint32_t RW;                                /**< CM0Px Interrupt register, offset: 0x10 */
113507     __IO uint32_t SET;                               /**< CM0Px Interrupt register, offset: 0x14 */
113508     __IO uint32_t CLR;                               /**< CM0Px Interrupt register, offset: 0x18 */
113509     __IO uint32_t TOG;                               /**< CM0Px Interrupt register, offset: 0x1C */
113510   } CM0PX_INT;
113511   __I  uint32_t CM0PX_INT_STAT;                    /**< CM0Px Interrupt status register, offset: 0x20 */
113512   __IO uint32_t CM0PX_INT_EN;                      /**< CM0Px Interrupt enable register, offset: 0x24 */
113513   __IO uint32_t EXT_INT_OVR;                       /**< External interrupt override register, offset: 0x28 */
113514 } VPU_CSR_Type;
113515 
113516 /* ----------------------------------------------------------------------------
113517    -- VPU_CSR Register Masks
113518    ---------------------------------------------------------------------------- */
113519 
113520 /*!
113521  * @addtogroup VPU_CSR_Register_Masks VPU_CSR Register Masks
113522  * @{
113523  */
113524 
113525 /*! @name CM0PX_ADDR_OFFSET - CM0Px Boot vector address offset */
113526 /*! @{ */
113527 #define VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET_MASK    (0xFFFFFFFFU)
113528 #define VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET_SHIFT   (0U)
113529 /*! OFFSET - CM0Px output address bus offset
113530  */
113531 #define VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET(x)      (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET_SHIFT)) & VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET_MASK)
113532 /*! @} */
113533 
113534 /*! @name CM0PX_CPUWAIT - CM0Px CPUWAIT signal control */
113535 /*! @{ */
113536 #define VPU_CSR_CM0PX_CPUWAIT_CPW_MASK           (0x1U)
113537 #define VPU_CSR_CM0PX_CPUWAIT_CPW_SHIFT          (0U)
113538 /*! CPW - Control CM0Px CPUWAIT input signal
113539  *  0b0..Processor is running
113540  *  0b1..Processor is waiting
113541  */
113542 #define VPU_CSR_CM0PX_CPUWAIT_CPW(x)             (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CPUWAIT_CPW_SHIFT)) & VPU_CSR_CM0PX_CPUWAIT_CPW_MASK)
113543 /*! @} */
113544 
113545 /*! @name CM0PX_CTL - CM0Px Control register */
113546 /*! @{ */
113547 #define VPU_CSR_CM0PX_CTL_REV_MASK               (0x1U)
113548 #define VPU_CSR_CM0PX_CTL_REV_SHIFT              (0U)
113549 /*! REV
113550  *  0b0..No override
113551  *  0b1..RXEV is forced low
113552  */
113553 #define VPU_CSR_CM0PX_CTL_REV(x)                 (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_REV_SHIFT)) & VPU_CSR_CM0PX_CTL_REV_MASK)
113554 #define VPU_CSR_CM0PX_CTL_TEV_MASK               (0x2U)
113555 #define VPU_CSR_CM0PX_CTL_TEV_SHIFT              (1U)
113556 /*! TEV - Override TXEV output signal
113557  *  0b0..No override
113558  *  0b1..TXEV is forced low
113559  */
113560 #define VPU_CSR_CM0PX_CTL_TEV(x)                 (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_TEV_SHIFT)) & VPU_CSR_CM0PX_CTL_TEV_MASK)
113561 #define VPU_CSR_CM0PX_CTL_ILT_MASK               (0x3FCU)
113562 #define VPU_CSR_CM0PX_CTL_ILT_SHIFT              (2U)
113563 /*! ILT - Control CM0Px IRQLATENCY[7:0] input
113564  */
113565 #define VPU_CSR_CM0PX_CTL_ILT(x)                 (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_ILT_SHIFT)) & VPU_CSR_CM0PX_CTL_ILT_MASK)
113566 #define VPU_CSR_CM0PX_CTL_CLR_MASK               (0x400U)
113567 #define VPU_CSR_CM0PX_CTL_CLR_SHIFT              (10U)
113568 /*! CLR - Clear LPCAC data cache
113569  *  0b0..Disable clear
113570  *  0b1..Enable clear
113571  */
113572 #define VPU_CSR_CM0PX_CTL_CLR(x)                 (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_CLR_SHIFT)) & VPU_CSR_CM0PX_CTL_CLR_MASK)
113573 #define VPU_CSR_CM0PX_CTL_NAL_MASK               (0x800U)
113574 #define VPU_CSR_CM0PX_CTL_NAL_SHIFT              (11U)
113575 /*! NAL - Disable LPCAC data cache allocation
113576  *  0b0..Enable LPCAC data cache allocation
113577  *  0b1..Disable LPCAC data cache allocation
113578  */
113579 #define VPU_CSR_CM0PX_CTL_NAL(x)                 (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_NAL_SHIFT)) & VPU_CSR_CM0PX_CTL_NAL_MASK)
113580 #define VPU_CSR_CM0PX_CTL_DWB_MASK               (0x1000U)
113581 #define VPU_CSR_CM0PX_CTL_DWB_SHIFT              (12U)
113582 /*! DWB - Disable LPCAC write buffer
113583  *  0b0..Enable write buffer
113584  *  0b1..Disable write buffer
113585  */
113586 #define VPU_CSR_CM0PX_CTL_DWB(x)                 (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_DWB_SHIFT)) & VPU_CSR_CM0PX_CTL_DWB_MASK)
113587 #define VPU_CSR_CM0PX_CTL_DIS_MASK               (0x2000U)
113588 #define VPU_CSR_CM0PX_CTL_DIS_SHIFT              (13U)
113589 /*! DIS - Disable LPCAC
113590  *  0b0..Enable LPCAC
113591  *  0b1..Disable LPCAC
113592  */
113593 #define VPU_CSR_CM0PX_CTL_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_DIS_SHIFT)) & VPU_CSR_CM0PX_CTL_DIS_MASK)
113594 #define VPU_CSR_CM0PX_CTL_MCT_MASK               (0x4000U)
113595 #define VPU_CSR_CM0PX_CTL_MCT_SHIFT              (14U)
113596 /*! MCT - Disable CACHE_MAP and force all memory space to be cached
113597  *  0b0..CACHE_MAP enable
113598  *  0b1..CACHE_MAP disable
113599  */
113600 #define VPU_CSR_CM0PX_CTL_MCT(x)                 (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_MCT_SHIFT)) & VPU_CSR_CM0PX_CTL_MCT_MASK)
113601 /*! @} */
113602 
113603 /*! @name CM0PX_STAT - CM0Px Status register */
113604 /*! @{ */
113605 #define VPU_CSR_CM0PX_STAT_LKP_MASK              (0x1U)
113606 #define VPU_CSR_CM0PX_STAT_LKP_SHIFT             (0U)
113607 /*! LKP - CM0Px LOCKUP output signal value
113608  */
113609 #define VPU_CSR_CM0PX_STAT_LKP(x)                (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_STAT_LKP_SHIFT)) & VPU_CSR_CM0PX_STAT_LKP_MASK)
113610 /*! @} */
113611 
113612 /*! @name CM0PX_INT - CM0Px Interrupt register */
113613 /*! @{ */
113614 #define VPU_CSR_CM0PX_INT_INT_MASK               (0x1FU)
113615 #define VPU_CSR_CM0PX_INT_INT_SHIFT              (0U)
113616 /*! INT - CM0Px CSR interrupt register. CSR interrupt register is ORed with MFD/VENC interrupts.
113617  */
113618 #define VPU_CSR_CM0PX_INT_INT(x)                 (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_INT_INT_SHIFT)) & VPU_CSR_CM0PX_INT_INT_MASK)
113619 /*! @} */
113620 
113621 /*! @name CM0PX_INT_STAT - CM0Px Interrupt status register */
113622 /*! @{ */
113623 #define VPU_CSR_CM0PX_INT_STAT_IST_MASK          (0x1FU)
113624 #define VPU_CSR_CM0PX_INT_STAT_IST_SHIFT         (0U)
113625 /*! IST - CM0Px CSR override interrupt status. CSR interrupt register interrupt is ORed with MFD/VENC interrupts.
113626  */
113627 #define VPU_CSR_CM0PX_INT_STAT_IST(x)            (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_INT_STAT_IST_SHIFT)) & VPU_CSR_CM0PX_INT_STAT_IST_MASK)
113628 /*! @} */
113629 
113630 /*! @name CM0PX_INT_EN - CM0Px Interrupt enable register */
113631 /*! @{ */
113632 #define VPU_CSR_CM0PX_INT_EN_IEN_MASK            (0x1FU)
113633 #define VPU_CSR_CM0PX_INT_EN_IEN_SHIFT           (0U)
113634 /*! IEN - CM0Px interrupt enable. Enable MFD/VENC and override interrupts.
113635  */
113636 #define VPU_CSR_CM0PX_INT_EN_IEN(x)              (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_INT_EN_IEN_SHIFT)) & VPU_CSR_CM0PX_INT_EN_IEN_MASK)
113637 /*! @} */
113638 
113639 /*! @name EXT_INT_OVR - External interrupt override register */
113640 /*! @{ */
113641 #define VPU_CSR_EXT_INT_OVR_IOV_MASK             (0x1FU)
113642 #define VPU_CSR_EXT_INT_OVR_IOV_SHIFT            (0U)
113643 /*! IOV - Enable MFD/VENC and override external interrupts.
113644  */
113645 #define VPU_CSR_EXT_INT_OVR_IOV(x)               (((uint32_t)(((uint32_t)(x)) << VPU_CSR_EXT_INT_OVR_IOV_SHIFT)) & VPU_CSR_EXT_INT_OVR_IOV_MASK)
113646 /*! @} */
113647 
113648 
113649 /*!
113650  * @}
113651  */ /* end of group VPU_CSR_Register_Masks */
113652 
113653 
113654 /* VPU_CSR - Peripheral instance base addresses */
113655 /** Peripheral VPU_CSR0 base address */
113656 #define VPU_CSR0_BASE                            (0x2D040000u)
113657 /** Peripheral VPU_CSR0 base pointer */
113658 #define VPU_CSR0                                 ((VPU_CSR_Type *)VPU_CSR0_BASE)
113659 /** Peripheral VPU_CSR1 base address */
113660 #define VPU_CSR1_BASE                            (0x2D050000u)
113661 /** Peripheral VPU_CSR1 base pointer */
113662 #define VPU_CSR1                                 ((VPU_CSR_Type *)VPU_CSR1_BASE)
113663 /** Array initializer of VPU_CSR peripheral base addresses */
113664 #define VPU_CSR_BASE_ADDRS                       { VPU_CSR0_BASE, VPU_CSR1_BASE }
113665 /** Array initializer of VPU_CSR peripheral base pointers */
113666 #define VPU_CSR_BASE_PTRS                        { VPU_CSR0, VPU_CSR1 }
113667 
113668 /*!
113669  * @}
113670  */ /* end of group VPU_CSR_Peripheral_Access_Layer */
113671 
113672 
113673 /* ----------------------------------------------------------------------------
113674    -- WDOG Peripheral Access Layer
113675    ---------------------------------------------------------------------------- */
113676 
113677 /*!
113678  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
113679  * @{
113680  */
113681 
113682 /** WDOG - Register Layout Typedef */
113683 typedef struct {
113684   __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
113685   __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
113686   __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
113687   __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
113688 } WDOG_Type;
113689 
113690 /* ----------------------------------------------------------------------------
113691    -- WDOG Register Masks
113692    ---------------------------------------------------------------------------- */
113693 
113694 /*!
113695  * @addtogroup WDOG_Register_Masks WDOG Register Masks
113696  * @{
113697  */
113698 
113699 /*! @name CS - Watchdog Control and Status Register */
113700 /*! @{ */
113701 #define WDOG_CS_STOP_MASK                        (0x1U)
113702 #define WDOG_CS_STOP_SHIFT                       (0U)
113703 /*! STOP - Stop Enable
113704  *  0b0..Watchdog disabled in chip stop mode.
113705  *  0b1..Watchdog enabled in chip stop mode.
113706  */
113707 #define WDOG_CS_STOP(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK)
113708 #define WDOG_CS_WAIT_MASK                        (0x2U)
113709 #define WDOG_CS_WAIT_SHIFT                       (1U)
113710 /*! WAIT - Wait Enable
113711  *  0b0..Watchdog disabled in chip wait mode.
113712  *  0b1..Watchdog enabled in chip wait mode.
113713  */
113714 #define WDOG_CS_WAIT(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK)
113715 #define WDOG_CS_DBG_MASK                         (0x4U)
113716 #define WDOG_CS_DBG_SHIFT                        (2U)
113717 /*! DBG - Debug Enable
113718  *  0b0..Watchdog disabled in chip debug mode.
113719  *  0b1..Watchdog enabled in chip debug mode.
113720  */
113721 #define WDOG_CS_DBG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK)
113722 #define WDOG_CS_TST_MASK                         (0x18U)
113723 #define WDOG_CS_TST_SHIFT                        (3U)
113724 /*! TST - Watchdog Test
113725  *  0b00..Watchdog test mode disabled.
113726  *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
113727  *        use this setting to indicate that the watchdog is functioning normally in user mode.
113728  *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
113729  *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
113730  */
113731 #define WDOG_CS_TST(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK)
113732 #define WDOG_CS_UPDATE_MASK                      (0x20U)
113733 #define WDOG_CS_UPDATE_SHIFT                     (5U)
113734 /*! UPDATE - Allow updates
113735  *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
113736  *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
113737  */
113738 #define WDOG_CS_UPDATE(x)                        (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK)
113739 #define WDOG_CS_INT_MASK                         (0x40U)
113740 #define WDOG_CS_INT_SHIFT                        (6U)
113741 /*! INT - Watchdog Interrupt
113742  *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
113743  *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
113744  */
113745 #define WDOG_CS_INT(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK)
113746 #define WDOG_CS_EN_MASK                          (0x80U)
113747 #define WDOG_CS_EN_SHIFT                         (7U)
113748 /*! EN - Watchdog Enable
113749  *  0b0..Watchdog disabled.
113750  *  0b1..Watchdog enabled.
113751  */
113752 #define WDOG_CS_EN(x)                            (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK)
113753 #define WDOG_CS_CLK_MASK                         (0x300U)
113754 #define WDOG_CS_CLK_SHIFT                        (8U)
113755 /*! CLK - Watchdog Clock
113756  *  0b00..Bus clock
113757  *  0b01..LPO clock
113758  *  0b10..INTCLK (internal clock)
113759  *  0b11..ERCLK (external reference clock)
113760  */
113761 #define WDOG_CS_CLK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK)
113762 #define WDOG_CS_RCS_MASK                         (0x400U)
113763 #define WDOG_CS_RCS_SHIFT                        (10U)
113764 /*! RCS - Reconfiguration Success
113765  *  0b0..Reconfiguring WDOG.
113766  *  0b1..Reconfiguration is successful.
113767  */
113768 #define WDOG_CS_RCS(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK)
113769 #define WDOG_CS_ULK_MASK                         (0x800U)
113770 #define WDOG_CS_ULK_SHIFT                        (11U)
113771 /*! ULK - Unlock status
113772  *  0b0..WDOG is locked.
113773  *  0b1..WDOG is unlocked.
113774  */
113775 #define WDOG_CS_ULK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK)
113776 #define WDOG_CS_PRES_MASK                        (0x1000U)
113777 #define WDOG_CS_PRES_SHIFT                       (12U)
113778 /*! PRES - Watchdog prescaler
113779  *  0b0..256 prescaler disabled.
113780  *  0b1..256 prescaler enabled.
113781  */
113782 #define WDOG_CS_PRES(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK)
113783 #define WDOG_CS_CMD32EN_MASK                     (0x2000U)
113784 #define WDOG_CS_CMD32EN_SHIFT                    (13U)
113785 /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
113786  *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
113787  *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
113788  */
113789 #define WDOG_CS_CMD32EN(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK)
113790 #define WDOG_CS_FLG_MASK                         (0x4000U)
113791 #define WDOG_CS_FLG_SHIFT                        (14U)
113792 /*! FLG - Watchdog Interrupt Flag
113793  *  0b0..No interrupt occurred.
113794  *  0b1..An interrupt occurred.
113795  */
113796 #define WDOG_CS_FLG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK)
113797 #define WDOG_CS_WIN_MASK                         (0x8000U)
113798 #define WDOG_CS_WIN_SHIFT                        (15U)
113799 /*! WIN - Watchdog Window
113800  *  0b0..Window mode disabled.
113801  *  0b1..Window mode enabled.
113802  */
113803 #define WDOG_CS_WIN(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK)
113804 /*! @} */
113805 
113806 /*! @name CNT - Watchdog Counter Register */
113807 /*! @{ */
113808 #define WDOG_CNT_CNTLOW_MASK                     (0xFFU)
113809 #define WDOG_CNT_CNTLOW_SHIFT                    (0U)
113810 /*! CNTLOW - Low byte of the Watchdog Counter
113811  */
113812 #define WDOG_CNT_CNTLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK)
113813 #define WDOG_CNT_CNTHIGH_MASK                    (0xFF00U)
113814 #define WDOG_CNT_CNTHIGH_SHIFT                   (8U)
113815 /*! CNTHIGH - High byte of the Watchdog Counter
113816  */
113817 #define WDOG_CNT_CNTHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK)
113818 /*! @} */
113819 
113820 /*! @name TOVAL - Watchdog Timeout Value Register */
113821 /*! @{ */
113822 #define WDOG_TOVAL_TOVALLOW_MASK                 (0xFFU)
113823 #define WDOG_TOVAL_TOVALLOW_SHIFT                (0U)
113824 /*! TOVALLOW - Low byte of the timeout value
113825  */
113826 #define WDOG_TOVAL_TOVALLOW(x)                   (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK)
113827 #define WDOG_TOVAL_TOVALHIGH_MASK                (0xFF00U)
113828 #define WDOG_TOVAL_TOVALHIGH_SHIFT               (8U)
113829 /*! TOVALHIGH - High byte of the timeout value
113830  */
113831 #define WDOG_TOVAL_TOVALHIGH(x)                  (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK)
113832 /*! @} */
113833 
113834 /*! @name WIN - Watchdog Window Register */
113835 /*! @{ */
113836 #define WDOG_WIN_WINLOW_MASK                     (0xFFU)
113837 #define WDOG_WIN_WINLOW_SHIFT                    (0U)
113838 /*! WINLOW - Low byte of Watchdog Window
113839  */
113840 #define WDOG_WIN_WINLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK)
113841 #define WDOG_WIN_WINHIGH_MASK                    (0xFF00U)
113842 #define WDOG_WIN_WINHIGH_SHIFT                   (8U)
113843 /*! WINHIGH - High byte of Watchdog Window
113844  */
113845 #define WDOG_WIN_WINHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK)
113846 /*! @} */
113847 
113848 
113849 /*!
113850  * @}
113851  */ /* end of group WDOG_Register_Masks */
113852 
113853 
113854 /* WDOG - Peripheral instance base addresses */
113855 /** Peripheral CM4__WDOG base address */
113856 #define CM4__WDOG_BASE                           (0x41420000u)
113857 /** Peripheral CM4__WDOG base pointer */
113858 #define CM4__WDOG                                ((WDOG_Type *)CM4__WDOG_BASE)
113859 /** Peripheral SCU__WDOG base address */
113860 #define SCU__WDOG_BASE                           (0x33420000u)
113861 /** Peripheral SCU__WDOG base pointer */
113862 #define SCU__WDOG                                ((WDOG_Type *)SCU__WDOG_BASE)
113863 /** Array initializer of WDOG peripheral base addresses */
113864 #define WDOG_BASE_ADDRS                          { CM4__WDOG_BASE, SCU__WDOG_BASE }
113865 /** Array initializer of WDOG peripheral base pointers */
113866 #define WDOG_BASE_PTRS                           { CM4__WDOG, SCU__WDOG }
113867 /* Extra definition */
113868 #define WDOG_UPDATE_KEY                          (0xD928C520U)
113869 #define WDOG_REFRESH_KEY                         (0xB480A602U)
113870 
113871 
113872 /*!
113873  * @}
113874  */ /* end of group WDOG_Peripheral_Access_Layer */
113875 
113876 
113877 /*
113878 ** End of section using anonymous unions
113879 */
113880 
113881 #if defined(__ARMCC_VERSION)
113882   #if (__ARMCC_VERSION >= 6010050)
113883     #pragma clang diagnostic pop
113884   #else
113885     #pragma pop
113886   #endif
113887 #elif defined(__GNUC__)
113888   /* leave anonymous unions enabled */
113889 #elif defined(__IAR_SYSTEMS_ICC__)
113890   #pragma language=default
113891 #else
113892   #error Not supported compiler type
113893 #endif
113894 
113895 /*!
113896  * @}
113897  */ /* end of group Peripheral_access_layer */
113898 
113899 
113900 /* ----------------------------------------------------------------------------
113901    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
113902    ---------------------------------------------------------------------------- */
113903 
113904 /*!
113905  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
113906  * @{
113907  */
113908 
113909 #if defined(__ARMCC_VERSION)
113910   #if (__ARMCC_VERSION >= 6010050)
113911     #pragma clang system_header
113912   #endif
113913 #elif defined(__IAR_SYSTEMS_ICC__)
113914   #pragma system_include
113915 #endif
113916 
113917 /**
113918  * @brief Mask and left-shift a bit field value for use in a register bit range.
113919  * @param field Name of the register bit field.
113920  * @param value Value of the bit field.
113921  * @return Masked and shifted value.
113922  */
113923 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
113924 /**
113925  * @brief Mask and right-shift a register value to extract a bit field value.
113926  * @param field Name of the register bit field.
113927  * @param value Value of the register.
113928  * @return Masked and shifted bit field value.
113929  */
113930 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
113931 
113932 /*!
113933  * @}
113934  */ /* end of group Bit_Field_Generic_Macros */
113935 
113936 
113937 /* ----------------------------------------------------------------------------
113938    -- SDK Compatibility
113939    ---------------------------------------------------------------------------- */
113940 
113941 /*!
113942  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
113943  * @{
113944  */
113945 
113946 /* No SDK compatibility issues. */
113947 
113948 /*!
113949  * @}
113950  */ /* end of group SDK_Compatibility_Symbols */
113951 
113952 
113953 #endif  /* _MIMX8QX1_CM4_H_ */
113954 
113955