1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2024-03-21 4 ** Build: b240524 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2024-03-21) 18 ** Initial version. 19 ** 20 ** ################################################################### 21 */ 22 23 #ifndef _MCXW716A_FEATURES_H_ 24 #define _MCXW716A_FEATURES_H_ 25 26 /* SOC module features */ 27 28 /* @brief AXBS availability on the SoC. */ 29 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 30 /* @brief BRIC availability on the SoC. */ 31 #define FSL_FEATURE_SOC_BRIC_COUNT (1) 32 /* @brief CIU2 availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CIU2_COUNT (1) 34 /* @brief CMC availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CMC_COUNT (1) 36 /* @brief CRC availability on the SoC. */ 37 #define FSL_FEATURE_SOC_CRC_COUNT (1) 38 /* @brief EDMA availability on the SoC. */ 39 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 40 /* @brief EWM availability on the SoC. */ 41 #define FSL_FEATURE_SOC_EWM_COUNT (1) 42 /* @brief FLEXIO availability on the SoC. */ 43 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 44 /* @brief GPIO availability on the SoC. */ 45 #define FSL_FEATURE_SOC_GPIO_COUNT (4) 46 /* @brief SPC availability on the SoC. */ 47 #define FSL_FEATURE_SOC_SPC_COUNT (1) 48 /* @brief I3C availability on the SoC. */ 49 #define FSL_FEATURE_SOC_I3C_COUNT (1) 50 /* @brief LPADC availability on the SoC. */ 51 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 52 /* @brief LPCMP availability on the SoC. */ 53 #define FSL_FEATURE_SOC_LPCMP_COUNT (2) 54 /* @brief LPI2C availability on the SoC. */ 55 #define FSL_FEATURE_SOC_LPI2C_COUNT (2) 56 /* @brief LPIT availability on the SoC. */ 57 #define FSL_FEATURE_SOC_LPIT_COUNT (1) 58 /* @brief LPSPI availability on the SoC. */ 59 #define FSL_FEATURE_SOC_LPSPI_COUNT (2) 60 /* @brief LPTMR availability on the SoC. */ 61 #define FSL_FEATURE_SOC_LPTMR_COUNT (2) 62 /* @brief LPUART availability on the SoC. */ 63 #define FSL_FEATURE_SOC_LPUART_COUNT (2) 64 /* @brief LTC availability on the SoC. */ 65 #define FSL_FEATURE_SOC_LTC_COUNT (1) 66 /* @brief MCM availability on the SoC. */ 67 #define FSL_FEATURE_SOC_MCM_COUNT (1) 68 /* @brief MSCM availability on the SoC. */ 69 #define FSL_FEATURE_SOC_MSCM_COUNT (1) 70 /* @brief PORT availability on the SoC. */ 71 #define FSL_FEATURE_SOC_PORT_COUNT (4) 72 /* @brief RTC availability on the SoC. */ 73 #define FSL_FEATURE_SOC_RTC_COUNT (1) 74 /* @brief SCG availability on the SoC. */ 75 #define FSL_FEATURE_SOC_SCG_COUNT (1) 76 /* @brief SEMA42 availability on the SoC. */ 77 #define FSL_FEATURE_SOC_SEMA42_COUNT (1) 78 /* @brief SFA availability on the SoC. */ 79 #define FSL_FEATURE_SOC_SFA_COUNT (2) 80 /* @brief SYSPM availability on the SoC. */ 81 #define FSL_FEATURE_SOC_SYSPM_COUNT (1) 82 /* @brief TPM availability on the SoC. */ 83 #define FSL_FEATURE_SOC_TPM_COUNT (3) 84 /* @brief TRGMUX availability on the SoC. */ 85 #define FSL_FEATURE_SOC_TRGMUX_COUNT (1) 86 /* @brief TSTMR availability on the SoC. */ 87 #define FSL_FEATURE_SOC_TSTMR_COUNT (1) 88 /* @brief VREF availability on the SoC. */ 89 #define FSL_FEATURE_SOC_VREF_COUNT (1) 90 /* @brief WDOG availability on the SoC. */ 91 #define FSL_FEATURE_SOC_WDOG_COUNT (2) 92 /* @brief WUU availability on the SoC. */ 93 #define FSL_FEATURE_SOC_WUU_COUNT (1) 94 /* @brief ZLL availability on the SoC. */ 95 #define FSL_FEATURE_SOC_ZLL_COUNT (1) 96 97 /* LPADC module features */ 98 99 /* @brief FIFO availability on the SoC. */ 100 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 101 /* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ 102 #define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) 103 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 104 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 105 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 106 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 107 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 108 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 109 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 110 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 111 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 112 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 113 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 114 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 115 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 116 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 117 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 118 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 119 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 120 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 121 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 122 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 123 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 124 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 125 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 126 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 127 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 128 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 129 /* @brief Has offset trim (register OFSTRIM). */ 130 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 131 /* @brief OFSTRIM availability on the SoC. */ 132 #define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) 133 /* @brief Has Trigger status register. */ 134 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 135 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 136 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 137 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 138 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 139 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 140 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 141 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 142 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 143 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 144 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 145 /* @brief Conversion averaged bitfiled width. */ 146 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 147 /* @brief Has B side channels. */ 148 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 149 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 150 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) 151 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 152 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) 153 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 154 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) 155 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 156 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 157 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 158 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) 159 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 160 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) 161 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 162 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) 163 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 164 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) 165 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 166 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) 167 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 168 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) 169 /* @brief Has internal temperature sensor. */ 170 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 171 /* @brief Temperature sensor parameter A (slope). */ 172 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (787U) 173 /* @brief Temperature sensor parameter B (offset). */ 174 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (289U) 175 /* @brief Temperature sensor parameter Alpha. */ 176 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.1f) 177 /* @brief The buffer size of temperature sensor. */ 178 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) 179 180 /* CCM32K module features */ 181 182 /* @brief Has Amplifier gain fine adjustment bits (register bit OSC32K_CTRL[FINE_AMP_GAIN]). */ 183 #define FSL_FEATURE_CCM32K_HAS_FINE_AMP_GAIN (0) 184 /* @brief Has CGC32K register. */ 185 #define FSL_FEATURE_CCM32K_HAS_CGC32K (1) 186 /* @brief Has CLKMON_CTRL register. */ 187 #define FSL_FEATURE_CCM32K_HAS_CLKMON_CTRL (1) 188 189 /* CMC module features */ 190 191 /* @brief Has on chip TCMC0 */ 192 #define FSL_FEATURE_CMC_HAS_TCMC0 (0) 193 /* @brief Has on chip SYSRAM0 */ 194 #define FSL_FEATURE_CMC_HAS_SYSRAM0 (0) 195 /* @brief Has on chip SYSRAM1 */ 196 #define FSL_FEATURE_CMC_HAS_SYSRAM1 (0) 197 /* @brief Has RSTCNT register */ 198 #define FSL_FEATURE_CMC_HAS_RSTCNT_REGISTER (1) 199 /* @brief Does not have SRAMCTL register */ 200 #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) 201 202 /* EDMA module features */ 203 204 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 205 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) 206 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 207 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 208 /* @brief Has DMA_Error interrupt vector. */ 209 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) 210 /* @brief Has register access permission. */ 211 #define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1) 212 /* @brief If dma has common clock gate */ 213 #define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (1) 214 /* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ 215 #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) 216 /* @brief Has no EMI access bit (MP_CSR). */ 217 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EMI (0) 218 /* @brief Has no EBW access bit (MP_CSR). */ 219 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) 220 /* @brief Has channel mux control */ 221 #define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) 222 /* @brief Has EDMA arbitration group (CHn_GRPRI). */ 223 #define FSL_FEATURE_EDMA_HAS_ARBITRATION_GROUP (1) 224 225 /* ELE_MUA module features */ 226 227 /* @brief Has ELEMU SEMA4 status register (SEMA4_SR). */ 228 #define FSL_FEATURE_ELEMU_HAS_SEMA4_STATUS_REGISTER (1) 229 /* @brief EDGELOCK availabilty on the soc. */ 230 #define FSL_FEATURE_EDGELOCK (1) 231 232 /* EWM module features */ 233 234 /* @brief Has clock select (register CLKCTRL). */ 235 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 236 /* @brief Has clock prescaler (register CLKPRESCALER). */ 237 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 238 239 /* FLEXIO module features */ 240 241 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 242 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 243 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 244 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 245 /* @brief Has pin input output related registers */ 246 #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) 247 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 248 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 249 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 250 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 251 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 252 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 253 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 254 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 255 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 256 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 257 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 258 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 259 /* @brief Reset value of the FLEXIO_VERID register */ 260 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) 261 /* @brief Reset value of the FLEXIO_PARAM register */ 262 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) 263 /* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ 264 #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) 265 266 /* MSF1 module features */ 267 268 /* @brief Is the flash module msf1? */ 269 #define FSL_FEATURE_FLASH_IS_MSF1 (1u) 270 /* @brief P-Flash start address. */ 271 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000u) 272 /* @brief Flash IFR0 start address. */ 273 #define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x02000000u) 274 /* @brief Flash IFR0 size. */ 275 #define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000u) 276 /* @brief P-Flash block count. */ 277 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1u) 278 /* @brief P-Flash block size. */ 279 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000u) 280 /* @brief P-Flash block size. */ 281 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE_512KB (0x80000u) 282 /* @brief Flash sector size. */ 283 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (8192u) 284 /* @brief Flash page size. */ 285 #define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128u) 286 /* @brief Flash phrase size. */ 287 #define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16u) 288 /* @brief RF P-Flash start address. */ 289 #define FSL_FEATURE_RF_FLASH_PFLASH_START_ADDRESS (0x48800000u) 290 /* @brief RF Flash IFR0 start address. */ 291 #define FSL_FEATURE_RF_FLASH_IFR0_START_ADDRESS (0x48840000u) 292 /* @brief RF P-Flash block count. */ 293 #define FSL_FEATURE_RF_FLASH_PFLASH_BLOCK_COUNT (1u) 294 /* @brief RF P-Flash block size. */ 295 #define FSL_FEATURE_RF_FLASH_PFLASH_BLOCK_SIZE (0x40000u) 296 /* @brief RF P-Flash IFR0 size. */ 297 #define FSL_FEATURE_RF_FLASH_IFR0_SIZE (0x8000u) 298 299 /* GPIO module features */ 300 301 /* @brief Has GPIO attribute checker register (GACR). */ 302 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 303 /* @brief Has GPIO version ID register (VERID). */ 304 #define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) 305 /* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ 306 #define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) 307 /* @brief Has GPIO port input disable register (PIDR). */ 308 #define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) 309 /* @brief Has GPIO interrupt/DMA request/trigger output selection. */ 310 #define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) 311 312 /* I3C module features */ 313 314 /* @brief SOC has no reset driver. */ 315 #define FSL_FEATURE_I3C_HAS_NO_RESET (1) 316 317 /* LPCMP module features */ 318 319 /* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ 320 #define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) 321 322 /* LPI2C module features */ 323 324 /* @brief Has separate DMA RX and TX requests. */ 325 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 326 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 327 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 328 329 /* LPIT module features */ 330 331 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 332 #define FSL_FEATURE_LPIT_TIMER_COUNT (4) 333 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 334 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) 335 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 336 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) 337 338 /* LPSPI module features */ 339 340 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 341 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) 342 /* @brief Has separate DMA RX and TX requests. */ 343 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 344 /* @brief Has CCR1 (related to existence of registers CCR1). */ 345 #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) 346 /* @brief Has no PCSCFG bit in CFGR1 register */ 347 #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) 348 /* @brief Has no WIDTH bits in TCR register */ 349 #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) 350 351 /* LPTMR module features */ 352 353 /* @brief Has shared interrupt handler with another LPTMR module. */ 354 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 355 /* @brief Whether LPTMR counter is 32 bits width. */ 356 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) 357 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 358 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) 359 /* @brief Do not has prescaler clock source 0. */ 360 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) 361 /* @brief Do not has prescaler clock source 1. */ 362 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (1) 363 /* @brief Do not has prescaler clock source 2. */ 364 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) 365 /* @brief Do not has prescaler clock source 3. */ 366 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (1) 367 368 /* LPUART module features */ 369 370 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 371 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 372 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 373 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 374 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 375 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 376 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 377 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 378 /* @brief Has 32-bit register MODIR */ 379 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 380 /* @brief Hardware flow control (RTS, CTS) is supported. */ 381 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 382 /* @brief Infrared (modulation) is supported. */ 383 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 384 /* @brief 2 bits long stop bit is available. */ 385 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 386 /* @brief If 10-bit mode is supported. */ 387 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 388 /* @brief If 7-bit mode is supported. */ 389 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 390 /* @brief Baud rate fine adjustment is available. */ 391 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 392 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 393 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 394 /* @brief Baud rate oversampling is available. */ 395 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 396 /* @brief Baud rate oversampling is available. */ 397 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 398 /* @brief Peripheral type. */ 399 #define FSL_FEATURE_LPUART_IS_SCI (1) 400 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 401 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) 402 /* @brief Supports two match addresses to filter incoming frames. */ 403 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 404 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 405 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 406 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 407 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 408 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 409 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 410 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 411 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 412 /* @brief Has improved smart card (ISO7816 protocol) support. */ 413 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 414 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 415 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 416 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 417 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 418 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 419 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 420 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 421 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 422 /* @brief Has separate DMA RX and TX requests. */ 423 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 424 /* @brief Has separate RX and TX interrupts. */ 425 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 426 /* @brief Has LPAURT_PARAM. */ 427 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 428 /* @brief Has LPUART_VERID. */ 429 #define FSL_FEATURE_LPUART_HAS_VERID (1) 430 /* @brief Has LPUART_GLOBAL. */ 431 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 432 /* @brief Has LPUART_PINCFG. */ 433 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 434 /* @brief Has register MODEM Control. */ 435 #define FSL_FEATURE_LPUART_HAS_MCR (0) 436 /* @brief Has register Half Duplex Control. */ 437 #define FSL_FEATURE_LPUART_HAS_HDCR (0) 438 /* @brief Has register Timeout. */ 439 #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) 440 441 /* LTC module features */ 442 443 /* @brief LTC module supports DES algorithm. */ 444 #define FSL_FEATURE_LTC_HAS_DES (0) 445 /* @brief LTC module supports PKHA algorithm. */ 446 #define FSL_FEATURE_LTC_HAS_PKHA (0) 447 /* @brief LTC module supports SHA algorithm. */ 448 #define FSL_FEATURE_LTC_HAS_SHA (0) 449 /* @brief LTC module supports AES GCM mode. */ 450 #define FSL_FEATURE_LTC_HAS_GCM (0) 451 /* @brief LTC module supports DPAMS registers. */ 452 #define FSL_FEATURE_LTC_HAS_DPAMS (0) 453 /* @brief LTC module supports AES with 24 bytes key. */ 454 #define FSL_FEATURE_LTC_HAS_AES192 (0) 455 /* @brief LTC module supports AES with 32 bytes key. */ 456 #define FSL_FEATURE_LTC_HAS_AES256 (0) 457 /* @brief LTC module has no clock control bit. */ 458 #define FSL_FEATURE_LTC_HAS_NO_CLOCK_CONTROL_BIT (1) 459 460 /* MCM module features */ 461 462 /* @brief Has L1 cache. */ 463 #define FSL_FEATURE_HAS_L1CACHE (1) 464 465 /* PORT module features */ 466 467 /* @brief Has control lock (register bit PCR[LK]). */ 468 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 469 /* @brief Has open drain control (register bit PCR[ODE]). */ 470 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 471 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 472 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 473 /* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ 474 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) 475 /* @brief Has pull resistor selection available. */ 476 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 477 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 478 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 479 /* @brief Has slew rate control (register bit PCR[SRE]). */ 480 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 481 /* @brief Has passive filter (register bit field PCR[PFE]). */ 482 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 483 /* @brief Do not has interrupt control (register ISFR). */ 484 #define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) 485 /* @brief Has pull value (register bit field PCR[PV]). */ 486 #define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) 487 /* @brief Has drive strength1 control (register bit PCR[DSE1]). */ 488 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) 489 /* @brief Has version ID register (register VERID). */ 490 #define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) 491 /* @brief Has voltage range control (register bit CONFIG[RANGE]). */ 492 #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) 493 /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ 494 #define FSL_FEATURE_PORT_SUPPORT_EFT (1) 495 /* @brief Has drive strength control (register bit PCR[DSE]). */ 496 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 497 /* @brief Defines width of PCR[MUX] field. */ 498 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) 499 /* @brief Has dedicated interrupt vector. */ 500 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 501 /* @brief Has independent interrupt control(register ICR). */ 502 #define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) 503 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 504 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 505 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 506 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 507 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 508 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 509 510 /* SFA module features */ 511 512 /* @brief CTRL Has CUT_PIN_EN (bitfield CTRL[CUT_PIN_EN]). */ 513 #define FSL_FEATURE_SFA_CTRL_HAS_CUT_PIN_ENn(x) \ 514 (((x) == SFA0) ? (1) : \ 515 (((x) == RF_SFA) ? (0) : (-1))) 516 /* @brief CTRL_EXT has CUT_PIN_EN (bitfield CTRL_EXT[CUT_PIN_EN]). */ 517 #define FSL_FEATURE_SFA_CTRL_EXT_HAS_CUT_PIN_EN (0) 518 /* @brief Trigger selection is configured outside the SFA peripheral. */ 519 #define FSL_FEATURE_SFA_TRIGGER_SELECTION_OUTSIDEn(x) \ 520 (((x) == SFA0) ? (0) : \ 521 (((x) == RF_SFA) ? (1) : (-1))) 522 /* @brief SFA instance support trigger. */ 523 #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) \ 524 (((x) == SFA0) ? (0) : \ 525 (((x) == RF_SFA) ? (1) : (-1))) 526 /* @brief SFA instance support interrupt. */ 527 #define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ 528 (((x) == SFA0) ? (1) : \ 529 (((x) == RF_SFA) ? (0) : (-1))) 530 531 /* RTC module features */ 532 533 /* @brief Has no supervisor access bit (CR). */ 534 #define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) 535 /* @brief Has no oscillator enable bit (CR). */ 536 #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) 537 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 538 #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) 539 /* @brief Has Clock Pin Enable field. */ 540 #define FSL_FEATURE_RTC_HAS_CPE (1) 541 /* @brief Has Tamper Interrupt Register (register TIR). */ 542 #define FSL_FEATURE_RTC_HAS_TIR (1) 543 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 544 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (1) 545 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 546 #define FSL_FEATURE_RTC_HAS_TIR_SIE (1) 547 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 548 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (1) 549 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 550 #define FSL_FEATURE_RTC_HAS_SR_TIDF (1) 551 /* @brief Has Tamper Detect Register (register TDR). */ 552 #define FSL_FEATURE_RTC_HAS_TDR (1) 553 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 554 #define FSL_FEATURE_RTC_HAS_TDR_TPF (1) 555 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 556 #define FSL_FEATURE_RTC_HAS_TDR_STF (1) 557 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 558 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (1) 559 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 560 #define FSL_FEATURE_RTC_HAS_TTSR (1) 561 /* @brief Has Pin Configuration Register (register PCR). */ 562 #define FSL_FEATURE_RTC_HAS_PCR (1) 563 564 /* SEMA42 module features */ 565 566 /* @brief Gate counts */ 567 #define FSL_FEATURE_SEMA42_GATE_COUNT (16) 568 569 /* SPC module features */ 570 571 /* @brief Has 2P4G power domain. */ 572 #define FSL_FEATURE_SPC_HAS_2P4G_POWER_DOMAIN (1) 573 /* @brief Has SPC_CFG. */ 574 #define FSL_FEATURE_SPC_HAS_CFG_REGISTER (1) 575 /* @brief Has core ldo vdd driver strength (register bit ACTIVE_CFG[CORELDO_VDD_DS]). */ 576 #define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) 577 /* @brief Has bias enable (register bit LP_CFG[WBIAS_EN]). */ 578 #define FSL_FEATURE_SPC_HAS_WBIAS_EN (0) 579 /* @brief Set CORELDO_VDD_LVL to 0 then regulate to Under Drive Voltage (0.95v). */ 580 #define FSL_FEATURE_SPC_LDO_VOLTAGE_LEVEL_DECREASE (0) 581 /* @brief Set DCDC_VDD_LVL to 0 then regulate to Low Under Voltage (1.25v). */ 582 #define FSL_FEATURE_SPC_DCDC_VOLTAGE_LEVEL_DECREASE (0) 583 584 /* SYSPM module features */ 585 586 /* @brief Temperature sensor parameter A (slope). */ 587 #define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) 588 /* @brief Temperature sensor parameter B (offset). */ 589 #define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) 590 /* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ 591 #define FSL_FEATURE_SYSPM_PMCR_COUNT (2) 592 593 /* SysTick module features */ 594 595 /* @brief Systick has external reference clock. */ 596 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 597 /* @brief Systick external reference clock is core clock divided by this value. */ 598 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 599 600 /* TPM module features */ 601 602 /* @brief Number of channels. */ 603 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ 604 (((x) == TPM0) ? (6) : \ 605 (((x) == TPM1) ? (6) : \ 606 (((x) == TPM2) ? (2) : (-1)))) 607 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 608 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 609 /* @brief Has TPM_PARAM. */ 610 #define FSL_FEATURE_TPM_HAS_PARAM (1) 611 /* @brief Has TPM_VERID. */ 612 #define FSL_FEATURE_TPM_HAS_VERID (1) 613 /* @brief Has TPM_GLOBAL. */ 614 #define FSL_FEATURE_TPM_HAS_GLOBAL (1) 615 /* @brief Has TPM_TRIG. */ 616 #define FSL_FEATURE_TPM_HAS_TRIG (1) 617 /* @brief Whether TRIG register has effect. */ 618 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ 619 (((x) == TPM0) ? (1) : \ 620 (((x) == TPM1) ? (1) : \ 621 (((x) == TPM2) ? (0) : (-1)))) 622 /* @brief Has global time base enable. */ 623 #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) 624 /* @brief Has counter pause on trigger. */ 625 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 626 /* @brief Has global time base sync. */ 627 #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_SYNC (1) 628 /* @brief Has external trigger selection. */ 629 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 630 /* @brief Has TPM_COMBINE register. */ 631 #define FSL_FEATURE_TPM_HAS_COMBINE (1) 632 /* @brief Whether COMBINE register has effect. */ 633 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) 634 /* @brief Has TPM_POL. */ 635 #define FSL_FEATURE_TPM_HAS_POL (1) 636 /* @brief Whether POL register has effect. */ 637 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ 638 (((x) == TPM2) ? (0) : \ 639 (((x) == TPM0) ? (1) : \ 640 (((x) == TPM1) ? (1) : (-1)))) 641 /* @brief Has TPM_FILTER register. */ 642 #define FSL_FEATURE_TPM_HAS_FILTER (1) 643 /* @brief Whether FILTER register has effect. */ 644 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) 645 /* @brief Has TPM_QDCTRL register. */ 646 #define FSL_FEATURE_TPM_HAS_QDCTRL (1) 647 /* @brief Whether QDCTRL register has effect. */ 648 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ 649 (((x) == TPM2) ? (0) : \ 650 (((x) == TPM0) ? (1) : \ 651 (((x) == TPM1) ? (1) : (-1)))) 652 /* @brief Has pause level select. */ 653 #define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (1) 654 /* @brief Whether 32 bits counter has effect. */ 655 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (1) 656 657 /* TRGMUX module features */ 658 659 /* No feature definitions */ 660 661 /* VREF module features */ 662 663 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 664 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (0) 665 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 666 #define FSL_FEATURE_VREF_HAS_COMPENSATION (0) 667 /* @brief If high/low buffer mode supported */ 668 #define FSL_FEATURE_VREF_MODE_LV_TYPE (0) 669 /* @brief Module has also low reference (registers VREFL/VREFH) */ 670 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 671 /* @brief Has VREF_TRM4. */ 672 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 673 674 /* WDOG module features */ 675 676 /* @brief Watchdog is available. */ 677 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 678 /* @brief WDOG_CNT can be 32-bit written. */ 679 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) 680 681 /* WUU module features */ 682 683 /* No feature definitions */ 684 685 #endif /* _MCXW716A_FEATURES_H_ */ 686 687
