1 /*
2 ** ###################################################################
3 **     Processors:          LPC55S69JBD100_cm33_core1
4 **                          LPC55S69JBD64_cm33_core1
5 **                          LPC55S69JEV98_cm33_core1
6 **
7 **     Compilers:           GNU C Compiler
8 **                          IAR ANSI C/C++ Compiler for ARM
9 **                          Keil ARM C/C++ Compiler
10 **                          MCUXpresso Compiler
11 **
12 **     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
13 **     Version:             rev. 1.1, 2019-05-16
14 **     Build:               b220718
15 **
16 **     Abstract:
17 **         CMSIS Peripheral Access Layer for LPC55S69_cm33_core1
18 **
19 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
20 **     Copyright 2016-2022 NXP
21 **     All rights reserved.
22 **
23 **     SPDX-License-Identifier: BSD-3-Clause
24 **
25 **     http:                 www.nxp.com
26 **     mail:                 support@nxp.com
27 **
28 **     Revisions:
29 **     - rev. 1.0 (2018-08-22)
30 **         Initial version based on v0.2UM
31 **     - rev. 1.1 (2019-05-16)
32 **         Initial A1 version based on v1.3UM
33 **
34 ** ###################################################################
35 */
36 
37 /*!
38  * @file LPC55S69_cm33_core1.h
39  * @version 1.1
40  * @date 2019-05-16
41  * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core1
42  *
43  * CMSIS Peripheral Access Layer for LPC55S69_cm33_core1
44  */
45 
46 #ifndef _LPC55S69_CM33_CORE1_H_
47 #define _LPC55S69_CM33_CORE1_H_                  /**< Symbol preventing repeated inclusion */
48 
49 /** Memory map major version (memory maps with equal major version number are
50  * compatible) */
51 #define MCU_MEM_MAP_VERSION 0x0100U
52 /** Memory map minor version */
53 #define MCU_MEM_MAP_VERSION_MINOR 0x0001U
54 
55 
56 /* ----------------------------------------------------------------------------
57    -- Interrupt vector numbers
58    ---------------------------------------------------------------------------- */
59 
60 /*!
61  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
62  * @{
63  */
64 
65 /** Interrupt Number Definitions */
66 #define NUMBER_OF_INT_VECTORS 76                 /**< Number of interrupts in the Vector table */
67 
68 typedef enum IRQn {
69   /* Auxiliary constants */
70   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
71 
72   /* Core interrupts */
73   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
74   HardFault_IRQn               = -13,              /**< Cortex-M33 SV Hard Fault Interrupt */
75   MemoryManagement_IRQn        = -12,              /**< Cortex-M33 Memory Management Interrupt */
76   BusFault_IRQn                = -11,              /**< Cortex-M33 Bus Fault Interrupt */
77   UsageFault_IRQn              = -10,              /**< Cortex-M33 Usage Fault Interrupt */
78   SecureFault_IRQn             = -9,               /**< Cortex-M33 Secure Fault Interrupt */
79   SVCall_IRQn                  = -5,               /**< Cortex-M33 SV Call Interrupt */
80   DebugMonitor_IRQn            = -4,               /**< Cortex-M33 Debug Monitor Interrupt */
81   PendSV_IRQn                  = -2,               /**< Cortex-M33 Pend SV Interrupt */
82   SysTick_IRQn                 = -1,               /**< Cortex-M33 System Tick Interrupt */
83 
84   /* Device specific interrupts */
85   WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect, Flash interrupt */
86   DMA0_IRQn                    = 1,                /**< DMA0 controller */
87   GINT0_IRQn                   = 2,                /**< GPIO group 0 */
88   GINT1_IRQn                   = 3,                /**< GPIO group 1 */
89   PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
90   PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
91   PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
92   PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
93   UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
94   MRT0_IRQn                    = 9,                /**< Multi-rate timer */
95   CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
96   CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
97   SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
98   CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
99   FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
100   FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
101   FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
102   FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
103   FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
104   FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
105   FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
106   FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
107   ADC0_IRQn                    = 22,               /**< ADC0  */
108   Reserved39_IRQn              = 23,               /**< Reserved interrupt */
109   ACMP_IRQn                    = 24,               /**< ACMP  interrupts */
110   Reserved41_IRQn              = 25,               /**< Reserved interrupt */
111   Reserved42_IRQn              = 26,               /**< Reserved interrupt */
112   USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
113   USB0_IRQn                    = 28,               /**< USB device */
114   RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
115   Reserved46_IRQn              = 30,               /**< Reserved interrupt */
116   MAILBOX_IRQn                 = 31,               /**< WAKEUP,Mailbox interrupt (present on selected devices) */
117   PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
118   PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
119   PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
120   PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
121   CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
122   CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
123   OS_EVENT_IRQn                = 38,               /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
124   Reserved55_IRQn              = 39,               /**< Reserved interrupt */
125   Reserved56_IRQn              = 40,               /**< Reserved interrupt */
126   Reserved57_IRQn              = 41,               /**< Reserved interrupt */
127   SDIO_IRQn                    = 42,               /**< SD/MMC  */
128   Reserved59_IRQn              = 43,               /**< Reserved interrupt */
129   Reserved60_IRQn              = 44,               /**< Reserved interrupt */
130   Reserved61_IRQn              = 45,               /**< Reserved interrupt */
131   USB1_PHY_IRQn                = 46,               /**< USB1_PHY */
132   USB1_IRQn                    = 47,               /**< USB1 interrupt */
133   USB1_NEEDCLK_IRQn            = 48,               /**< USB1 activity */
134   SEC_HYPERVISOR_CALL_IRQn     = 49,               /**< SEC_HYPERVISOR_CALL interrupt */
135   SEC_GPIO_INT0_IRQ0_IRQn      = 50,               /**< SEC_GPIO_INT0_IRQ0 interrupt */
136   SEC_GPIO_INT0_IRQ1_IRQn      = 51,               /**< SEC_GPIO_INT0_IRQ1 interrupt */
137   PLU_IRQn                     = 52,               /**< PLU interrupt */
138   SEC_VIO_IRQn                 = 53,               /**< SEC_VIO interrupt */
139   HASHCRYPT_IRQn               = 54,               /**< HASHCRYPT interrupt */
140   CASER_IRQn                   = 55,               /**< CASPER interrupt */
141   PUF_IRQn                     = 56,               /**< PUF interrupt */
142   PQ_IRQn                      = 57,               /**< PQ interrupt */
143   DMA1_IRQn                    = 58,               /**< DMA1 interrupt */
144   FLEXCOMM8_IRQn               = 59                /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */
145 } IRQn_Type;
146 
147 /*!
148  * @}
149  */ /* end of group Interrupt_vector_numbers */
150 
151 
152 /* ----------------------------------------------------------------------------
153    -- Cortex M33 Core Configuration
154    ---------------------------------------------------------------------------- */
155 
156 /*!
157  * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
158  * @{
159  */
160 
161 #define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
162 #define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
163 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
164 #define __FPU_PRESENT                  0         /**< Defines if an FPU is present or not */
165 #define __DSP_PRESENT                  0         /**< Defines if Armv8-M Mainline core supports DSP instructions */
166 #define __SAUREGION_PRESENT            0         /**< Defines if an SAU is present or not */
167 
168 #include "core_cm33.h"                 /* Core Peripheral Access Layer */
169 #include "system_LPC55S69_cm33_core1.h" /* Device specific configuration file */
170 
171 /*!
172  * @}
173  */ /* end of group Cortex_Core_Configuration */
174 
175 
176 /* ----------------------------------------------------------------------------
177    -- Mapping Information
178    ---------------------------------------------------------------------------- */
179 
180 /*!
181  * @addtogroup Mapping_Information Mapping Information
182  * @{
183  */
184 
185 /** Mapping Information */
186 /*!
187  * @addtogroup dma_request
188  * @{
189  */
190 
191 /*******************************************************************************
192  * Definitions
193  ******************************************************************************/
194 
195 /*!
196  * @brief Structure for the DMA hardware request
197  *
198  * Defines the structure for the DMA hardware request collections. The user can configure the
199  * hardware request to trigger the DMA transfer accordingly. The index
200  * of the hardware request varies according  to the to SoC.
201  */
202 typedef enum _dma_request_source
203 {
204     kDma0RequestHashCrypt           = 0U,          /**< HashCrypt */
205     kDma1RequestHashCrypt           = 0U,          /**< HashCrypt */
206     kDma0RequestNoDMARequest1       = 1U,          /**< No DMA request 1 */
207     kDma1RequestNoDMARequest1       = 1U,          /**< No DMA request 1 */
208     kDma0RequestFlexcomm8Rx         = 2U,          /**< Flexcomm Interface 8 RX */
209     kDma1RequestFlexcomm8Rx         = 2U,          /**< Flexcomm Interface 8 RX */
210     kDma0RequestFlexcomm8Tx         = 3U,          /**< Flexcomm Interface 8 TX */
211     kDma1RequestFlexcomm8Tx         = 3U,          /**< Flexcomm Interface 8 TX */
212     kDma0RequestFlexcomm0Rx         = 4U,          /**< Flexcomm Interface 0 RX/I2C Slave */
213     kDma1RequestFlexcomm0Rx         = 4U,          /**< Flexcomm Interface 0 RX/I2C Slave */
214     kDma0RequestFlexcomm0Tx         = 5U,          /**< Flexcomm Interface 0 TX/I2C Master */
215     kDma1RequestFlexcomm0Tx         = 5U,          /**< Flexcomm Interface 0 TX/I2C Master */
216     kDma0RequestFlexcomm1Rx         = 6U,          /**< Flexcomm Interface 1 RX/I2C Slave */
217     kDma1RequestFlexcomm1Rx         = 6U,          /**< Flexcomm Interface 1 RX/I2C Slave */
218     kDma0RequestFlexcomm1Tx         = 7U,          /**< Flexcomm Interface 1 TX/I2C Master */
219     kDma1RequestFlexcomm1Tx         = 7U,          /**< Flexcomm Interface 1 TX/I2C Master */
220     kDma0RequestFlexcomm3Rx         = 8U,          /**< Flexcomm Interface 3 RX/I2C Slave */
221     kDma1RequestFlexcomm3Rx         = 8U,          /**< Flexcomm Interface 3 RX/I2C Slave */
222     kDma0RequestFlexcomm3Tx         = 9U,          /**< Flexcomm Interface 3 TX/I2C Master */
223     kDma1RequestFlexcomm3Tx         = 9U,          /**< Flexcomm Interface 3 TX/I2C Master */
224     kDma0RequestFlexcomm2Rx         = 10U,         /**< Flexcomm Interface 2 RX/I2C Slave */
225     kDma0RequestFlexcomm2Tx         = 11U,         /**< Flexcomm Interface 2 TX/I2C Master */
226     kDma0RequestFlexcomm4Rx         = 12U,         /**< Flexcomm Interface 4 RX/I2C Slave */
227     kDma0RequestFlexcomm4Tx         = 13U,         /**< Flexcomm Interface 4 TX/I2C Master */
228     kDma0RequestFlexcomm5Rx         = 14U,         /**< Flexcomm Interface 5 RX/I2C Slave */
229     kDma0RequestFlexcomm5Tx         = 15U,         /**< Flexcomm Interface 5 TX/I2C Master */
230     kDma0RequestFlexcomm6Rx         = 16U,         /**< Flexcomm Interface 6 RX/I2C Slave */
231     kDma0RequestFlexcomm6Tx         = 17U,         /**< Flexcomm Interface 6 TX/I2C Master */
232     kDma0RequestFlexcomm7Rx         = 18U,         /**< Flexcomm Interface 7 RX/I2C Slave */
233     kDma0RequestFlexcomm7Tx         = 19U,         /**< Flexcomm Interface 7 TX/I2C Master */
234     kDma0RequestNoDMARequest20      = 20U,         /**< No DMA request 20 */
235     kDma0RequestADC0FIFO0           = 21U,         /**< ADC0 FIFO 0 */
236     kDma0RequestADC0FIFO1           = 22U,         /**< ADC0 FIFO 1 */
237 } dma_request_source_t;
238 
239 /* @} */
240 
241 
242 /*!
243  * @}
244  */ /* end of group Mapping_Information */
245 
246 
247 /* ----------------------------------------------------------------------------
248    -- Device Peripheral Access Layer
249    ---------------------------------------------------------------------------- */
250 
251 /*!
252  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
253  * @{
254  */
255 
256 
257 /*
258 ** Start of section using anonymous unions
259 */
260 
261 #if defined(__ARMCC_VERSION)
262   #if (__ARMCC_VERSION >= 6010050)
263     #pragma clang diagnostic push
264   #else
265     #pragma push
266     #pragma anon_unions
267   #endif
268 #elif defined(__GNUC__)
269   /* anonymous unions are enabled by default */
270 #elif defined(__IAR_SYSTEMS_ICC__)
271   #pragma language=extended
272 #else
273   #error Not supported compiler type
274 #endif
275 
276 /* ----------------------------------------------------------------------------
277    -- ADC Peripheral Access Layer
278    ---------------------------------------------------------------------------- */
279 
280 /*!
281  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
282  * @{
283  */
284 
285 /** ADC - Register Layout Typedef */
286 typedef struct {
287   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
288   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
289        uint8_t RESERVED_0[8];
290   __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
291   __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
292   __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
293   __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
294   __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
295   __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
296        uint8_t RESERVED_1[12];
297   __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
298   __IO uint32_t TSTAT;                             /**< Trigger Status Register, offset: 0x38 */
299        uint8_t RESERVED_2[4];
300   __IO uint32_t OFSTRIM;                           /**< ADC Offset Trim Register, offset: 0x40 */
301        uint8_t RESERVED_3[92];
302   __IO uint32_t TCTRL[16];                         /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
303   __IO uint32_t FCTRL[2];                          /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
304        uint8_t RESERVED_4[8];
305   __I  uint32_t GCC[2];                            /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
306   __IO uint32_t GCR[2];                            /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
307   struct {                                         /* offset: 0x100, array step: 0x8 */
308     __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
309     __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
310   } CMD[15];
311        uint8_t RESERVED_5[136];
312   __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
313        uint8_t RESERVED_6[240];
314   __I  uint32_t RESFIFO[2];                        /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
315        uint8_t RESERVED_7[248];
316   __IO uint32_t CAL_GAR[33];                       /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
317        uint8_t RESERVED_8[124];
318   __IO uint32_t CAL_GBR[33];                       /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
319        uint8_t RESERVED_9[2680];
320   __IO uint32_t TST;                               /**< ADC Test Register, offset: 0xFFC */
321 } ADC_Type;
322 
323 /* ----------------------------------------------------------------------------
324    -- ADC Register Masks
325    ---------------------------------------------------------------------------- */
326 
327 /*!
328  * @addtogroup ADC_Register_Masks ADC Register Masks
329  * @{
330  */
331 
332 /*! @name VERID - Version ID Register */
333 /*! @{ */
334 
335 #define ADC_VERID_RES_MASK                       (0x1U)
336 #define ADC_VERID_RES_SHIFT                      (0U)
337 /*! RES - Resolution
338  *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
339  *  0b1..Up to 16-bit differential/16-bit single ended resolution supported.
340  */
341 #define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
342 
343 #define ADC_VERID_DIFFEN_MASK                    (0x2U)
344 #define ADC_VERID_DIFFEN_SHIFT                   (1U)
345 /*! DIFFEN - Differential Supported
346  *  0b0..Differential operation not supported.
347  *  0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.
348  */
349 #define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
350 
351 #define ADC_VERID_MVI_MASK                       (0x8U)
352 #define ADC_VERID_MVI_SHIFT                      (3U)
353 /*! MVI - Multi Vref Implemented
354  *  0b0..Single voltage reference high (VREFH) input supported.
355  *  0b1..Multiple voltage reference high (VREFH) inputs supported.
356  */
357 #define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
358 
359 #define ADC_VERID_CSW_MASK                       (0x70U)
360 #define ADC_VERID_CSW_SHIFT                      (4U)
361 /*! CSW - Channel Scale Width
362  *  0b000..Channel scaling not supported.
363  *  0b001..Channel scaling supported. 1-bit CSCALE control field.
364  *  0b110..Channel scaling supported. 6-bit CSCALE control field.
365  */
366 #define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
367 
368 #define ADC_VERID_VR1RNGI_MASK                   (0x100U)
369 #define ADC_VERID_VR1RNGI_SHIFT                  (8U)
370 /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
371  *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
372  *  0b1..Range control required. CFG[VREF1RNG] is implemented.
373  */
374 #define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
375 
376 #define ADC_VERID_IADCKI_MASK                    (0x200U)
377 #define ADC_VERID_IADCKI_SHIFT                   (9U)
378 /*! IADCKI - Internal ADC Clock implemented
379  *  0b0..Internal clock source not implemented.
380  *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
381  */
382 #define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
383 
384 #define ADC_VERID_CALOFSI_MASK                   (0x400U)
385 #define ADC_VERID_CALOFSI_SHIFT                  (10U)
386 /*! CALOFSI - Calibration Function Implemented
387  *  0b0..Calibration Not Implemented.
388  *  0b1..Calibration Implemented.
389  */
390 #define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
391 
392 #define ADC_VERID_NUM_SEC_MASK                   (0x800U)
393 #define ADC_VERID_NUM_SEC_SHIFT                  (11U)
394 /*! NUM_SEC - Number of Single Ended Outputs Supported
395  *  0b0..This design supports one single ended conversion at a time.
396  *  0b1..This design supports two simultanious single ended conversions.
397  */
398 #define ADC_VERID_NUM_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
399 
400 #define ADC_VERID_NUM_FIFO_MASK                  (0x7000U)
401 #define ADC_VERID_NUM_FIFO_SHIFT                 (12U)
402 /*! NUM_FIFO - Number of FIFOs
403  *  0b000..N/A
404  *  0b001..This design supports one result FIFO.
405  *  0b010..This design supports two result FIFOs.
406  *  0b011..This design supports three result FIFOs.
407  *  0b100..This design supports four result FIFOs.
408  */
409 #define ADC_VERID_NUM_FIFO(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
410 
411 #define ADC_VERID_MINOR_MASK                     (0xFF0000U)
412 #define ADC_VERID_MINOR_SHIFT                    (16U)
413 /*! MINOR - Minor Version Number
414  */
415 #define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
416 
417 #define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
418 #define ADC_VERID_MAJOR_SHIFT                    (24U)
419 /*! MAJOR - Major Version Number
420  */
421 #define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
422 /*! @} */
423 
424 /*! @name PARAM - Parameter Register */
425 /*! @{ */
426 
427 #define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
428 #define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
429 /*! TRIG_NUM - Trigger Number
430  */
431 #define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
432 
433 #define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
434 #define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
435 /*! FIFOSIZE - Result FIFO Depth
436  *  0b00000001..Result FIFO depth = 1 dataword.
437  *  0b00000100..Result FIFO depth = 4 datawords.
438  *  0b00001000..Result FIFO depth = 8 datawords.
439  *  0b00010000..Result FIFO depth = 16 datawords.
440  *  0b00100000..Result FIFO depth = 32 datawords.
441  *  0b01000000..Result FIFO depth = 64 datawords.
442  */
443 #define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
444 
445 #define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
446 #define ADC_PARAM_CV_NUM_SHIFT                   (16U)
447 /*! CV_NUM - Compare Value Number
448  */
449 #define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
450 
451 #define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
452 #define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
453 /*! CMD_NUM - Command Buffer Number
454  */
455 #define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
456 /*! @} */
457 
458 /*! @name CTRL - ADC Control Register */
459 /*! @{ */
460 
461 #define ADC_CTRL_ADCEN_MASK                      (0x1U)
462 #define ADC_CTRL_ADCEN_SHIFT                     (0U)
463 /*! ADCEN - ADC Enable
464  *  0b0..ADC is disabled.
465  *  0b1..ADC is enabled.
466  */
467 #define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
468 
469 #define ADC_CTRL_RST_MASK                        (0x2U)
470 #define ADC_CTRL_RST_SHIFT                       (1U)
471 /*! RST - Software Reset
472  *  0b0..ADC logic is not reset.
473  *  0b1..ADC logic is reset.
474  */
475 #define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
476 
477 #define ADC_CTRL_DOZEN_MASK                      (0x4U)
478 #define ADC_CTRL_DOZEN_SHIFT                     (2U)
479 /*! DOZEN - Doze Enable
480  *  0b0..ADC is enabled in Doze mode.
481  *  0b1..ADC is disabled in Doze mode.
482  */
483 #define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
484 
485 #define ADC_CTRL_CAL_REQ_MASK                    (0x8U)
486 #define ADC_CTRL_CAL_REQ_SHIFT                   (3U)
487 /*! CAL_REQ - Auto-Calibration Request
488  *  0b0..No request for auto-calibration has been made.
489  *  0b1..A request for auto-calibration has been made
490  */
491 #define ADC_CTRL_CAL_REQ(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
492 
493 #define ADC_CTRL_CALOFS_MASK                     (0x10U)
494 #define ADC_CTRL_CALOFS_SHIFT                    (4U)
495 /*! CALOFS - Configure for offset calibration function
496  *  0b0..Calibration function disabled
497  *  0b1..Request for offset calibration function
498  */
499 #define ADC_CTRL_CALOFS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
500 
501 #define ADC_CTRL_RSTFIFO0_MASK                   (0x100U)
502 #define ADC_CTRL_RSTFIFO0_SHIFT                  (8U)
503 /*! RSTFIFO0 - Reset FIFO 0
504  *  0b0..No effect.
505  *  0b1..FIFO 0 is reset.
506  */
507 #define ADC_CTRL_RSTFIFO0(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
508 
509 #define ADC_CTRL_RSTFIFO1_MASK                   (0x200U)
510 #define ADC_CTRL_RSTFIFO1_SHIFT                  (9U)
511 /*! RSTFIFO1 - Reset FIFO 1
512  *  0b0..No effect.
513  *  0b1..FIFO 1 is reset.
514  */
515 #define ADC_CTRL_RSTFIFO1(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
516 
517 #define ADC_CTRL_CAL_AVGS_MASK                   (0x70000U)
518 #define ADC_CTRL_CAL_AVGS_SHIFT                  (16U)
519 /*! CAL_AVGS - Auto-Calibration Averages
520  *  0b000..Single conversion.
521  *  0b001..2 conversions averaged.
522  *  0b010..4 conversions averaged.
523  *  0b011..8 conversions averaged.
524  *  0b100..16 conversions averaged.
525  *  0b101..32 conversions averaged.
526  *  0b110..64 conversions averaged.
527  *  0b111..128 conversions averaged.
528  */
529 #define ADC_CTRL_CAL_AVGS(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
530 /*! @} */
531 
532 /*! @name STAT - ADC Status Register */
533 /*! @{ */
534 
535 #define ADC_STAT_RDY0_MASK                       (0x1U)
536 #define ADC_STAT_RDY0_SHIFT                      (0U)
537 /*! RDY0 - Result FIFO 0 Ready Flag
538  *  0b0..Result FIFO 0 data level not above watermark level.
539  *  0b1..Result FIFO 0 holding data above watermark level.
540  */
541 #define ADC_STAT_RDY0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
542 
543 #define ADC_STAT_FOF0_MASK                       (0x2U)
544 #define ADC_STAT_FOF0_SHIFT                      (1U)
545 /*! FOF0 - Result FIFO 0 Overflow Flag
546  *  0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
547  *  0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
548  */
549 #define ADC_STAT_FOF0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
550 
551 #define ADC_STAT_RDY1_MASK                       (0x4U)
552 #define ADC_STAT_RDY1_SHIFT                      (2U)
553 /*! RDY1 - Result FIFO1 Ready Flag
554  *  0b0..Result FIFO1 data level not above watermark level.
555  *  0b1..Result FIFO1 holding data above watermark level.
556  */
557 #define ADC_STAT_RDY1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
558 
559 #define ADC_STAT_FOF1_MASK                       (0x8U)
560 #define ADC_STAT_FOF1_SHIFT                      (3U)
561 /*! FOF1 - Result FIFO1 Overflow Flag
562  *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
563  *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
564  */
565 #define ADC_STAT_FOF1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
566 
567 #define ADC_STAT_TEXC_INT_MASK                   (0x100U)
568 #define ADC_STAT_TEXC_INT_SHIFT                  (8U)
569 /*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
570  *  0b0..No trigger exceptions have occurred.
571  *  0b1..A trigger exception has occurred and is pending acknowledgement.
572  */
573 #define ADC_STAT_TEXC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
574 
575 #define ADC_STAT_TCOMP_INT_MASK                  (0x200U)
576 #define ADC_STAT_TCOMP_INT_SHIFT                 (9U)
577 /*! TCOMP_INT - Interrupt Flag For Trigger Completion
578  *  0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
579  *  0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
580  */
581 #define ADC_STAT_TCOMP_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
582 
583 #define ADC_STAT_CAL_RDY_MASK                    (0x400U)
584 #define ADC_STAT_CAL_RDY_SHIFT                   (10U)
585 /*! CAL_RDY - Calibration Ready
586  *  0b0..Calibration is incomplete or hasn't been ran.
587  *  0b1..The ADC is calibrated.
588  */
589 #define ADC_STAT_CAL_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
590 
591 #define ADC_STAT_ADC_ACTIVE_MASK                 (0x800U)
592 #define ADC_STAT_ADC_ACTIVE_SHIFT                (11U)
593 /*! ADC_ACTIVE - ADC Active
594  *  0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
595  *  0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
596  */
597 #define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
598 
599 #define ADC_STAT_TRGACT_MASK                     (0xF0000U)
600 #define ADC_STAT_TRGACT_SHIFT                    (16U)
601 /*! TRGACT - Trigger Active
602  *  0b0000..Command (sequence) associated with Trigger 0 currently being executed.
603  *  0b0001..Command (sequence) associated with Trigger 1 currently being executed.
604  *  0b0010..Command (sequence) associated with Trigger 2 currently being executed.
605  *  0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed.
606  */
607 #define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
608 
609 #define ADC_STAT_CMDACT_MASK                     (0xF000000U)
610 #define ADC_STAT_CMDACT_SHIFT                    (24U)
611 /*! CMDACT - Command Active
612  *  0b0000..No command is currently in progress.
613  *  0b0001..Command 1 currently being executed.
614  *  0b0010..Command 2 currently being executed.
615  *  0b0011-0b1111..Associated command number is currently being executed.
616  */
617 #define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
618 /*! @} */
619 
620 /*! @name IE - Interrupt Enable Register */
621 /*! @{ */
622 
623 #define ADC_IE_FWMIE0_MASK                       (0x1U)
624 #define ADC_IE_FWMIE0_SHIFT                      (0U)
625 /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
626  *  0b0..FIFO 0 watermark interrupts are not enabled.
627  *  0b1..FIFO 0 watermark interrupts are enabled.
628  */
629 #define ADC_IE_FWMIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
630 
631 #define ADC_IE_FOFIE0_MASK                       (0x2U)
632 #define ADC_IE_FOFIE0_SHIFT                      (1U)
633 /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
634  *  0b0..FIFO 0 overflow interrupts are not enabled.
635  *  0b1..FIFO 0 overflow interrupts are enabled.
636  */
637 #define ADC_IE_FOFIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
638 
639 #define ADC_IE_FWMIE1_MASK                       (0x4U)
640 #define ADC_IE_FWMIE1_SHIFT                      (2U)
641 /*! FWMIE1 - FIFO1 Watermark Interrupt Enable
642  *  0b0..FIFO1 watermark interrupts are not enabled.
643  *  0b1..FIFO1 watermark interrupts are enabled.
644  */
645 #define ADC_IE_FWMIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
646 
647 #define ADC_IE_FOFIE1_MASK                       (0x8U)
648 #define ADC_IE_FOFIE1_SHIFT                      (3U)
649 /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
650  *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
651  *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
652  */
653 #define ADC_IE_FOFIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
654 
655 #define ADC_IE_TEXC_IE_MASK                      (0x100U)
656 #define ADC_IE_TEXC_IE_SHIFT                     (8U)
657 /*! TEXC_IE - Trigger Exception Interrupt Enable
658  *  0b0..Trigger exception interrupts are disabled.
659  *  0b1..Trigger exception interrupts are enabled.
660  */
661 #define ADC_IE_TEXC_IE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
662 
663 #define ADC_IE_TCOMP_IE_MASK                     (0xFFFF0000U)
664 #define ADC_IE_TCOMP_IE_SHIFT                    (16U)
665 /*! TCOMP_IE - Trigger Completion Interrupt Enable
666  *  0b0000000000000000..Trigger completion interrupts are disabled.
667  *  0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only.
668  *  0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only.
669  *  0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled.
670  *  0b1111111111111111..Trigger completion interrupts are enabled for every trigger source.
671  */
672 #define ADC_IE_TCOMP_IE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
673 /*! @} */
674 
675 /*! @name DE - DMA Enable Register */
676 /*! @{ */
677 
678 #define ADC_DE_FWMDE0_MASK                       (0x1U)
679 #define ADC_DE_FWMDE0_SHIFT                      (0U)
680 /*! FWMDE0 - FIFO 0 Watermark DMA Enable
681  *  0b0..DMA request disabled.
682  *  0b1..DMA request enabled.
683  */
684 #define ADC_DE_FWMDE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
685 
686 #define ADC_DE_FWMDE1_MASK                       (0x2U)
687 #define ADC_DE_FWMDE1_SHIFT                      (1U)
688 /*! FWMDE1 - FIFO1 Watermark DMA Enable
689  *  0b0..DMA request disabled.
690  *  0b1..DMA request enabled.
691  */
692 #define ADC_DE_FWMDE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
693 /*! @} */
694 
695 /*! @name CFG - ADC Configuration Register */
696 /*! @{ */
697 
698 #define ADC_CFG_TPRICTRL_MASK                    (0x3U)
699 #define ADC_CFG_TPRICTRL_SHIFT                   (0U)
700 /*! TPRICTRL - ADC trigger priority control
701  *  0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
702  *        and the new command specified by the trigger is started.
703  *  0b01..If a higher priority trigger is received during command processing, the current command is stopped after
704  *        after completing the current conversion. If averaging is enabled, the averaging loop will be completed.
705  *        However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
706  *  0b10..If a higher priority trigger is received during command processing, the current command will be
707  *        completed (averaging, looping, compare) before servicing the higher priority trigger.
708  *  0b11..RESERVED
709  */
710 #define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
711 
712 #define ADC_CFG_PWRSEL_MASK                      (0x30U)
713 #define ADC_CFG_PWRSEL_SHIFT                     (4U)
714 /*! PWRSEL - Power Configuration Select
715  *  0b00..Lowest power setting.
716  *  0b01..Higher power setting than 0b0.
717  *  0b10..Higher power setting than 0b1.
718  *  0b11..Highest power setting.
719  */
720 #define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
721 
722 #define ADC_CFG_REFSEL_MASK                      (0xC0U)
723 #define ADC_CFG_REFSEL_SHIFT                     (6U)
724 /*! REFSEL - Voltage Reference Selection
725  *  0b00..(Default) Option 1 setting.
726  *  0b01..Option 2 setting.
727  *  0b10..Option 3 setting.
728  *  0b11..Reserved
729  */
730 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
731 
732 #define ADC_CFG_TRES_MASK                        (0x100U)
733 #define ADC_CFG_TRES_SHIFT                       (8U)
734 /*! TRES - Trigger Resume Enable
735  *  0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted.
736  *  0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted.
737  */
738 #define ADC_CFG_TRES(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
739 
740 #define ADC_CFG_TCMDRES_MASK                     (0x200U)
741 #define ADC_CFG_TCMDRES_SHIFT                    (9U)
742 /*! TCMDRES - Trigger Command Resume
743  *  0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted.
744  *  0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception.
745  */
746 #define ADC_CFG_TCMDRES(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
747 
748 #define ADC_CFG_HPT_EXDI_MASK                    (0x400U)
749 #define ADC_CFG_HPT_EXDI_SHIFT                   (10U)
750 /*! HPT_EXDI - High Priority Trigger Exception Disable
751  *  0b0..High priority trigger exceptions are enabled.
752  *  0b1..High priority trigger exceptions are disabled.
753  */
754 #define ADC_CFG_HPT_EXDI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
755 
756 #define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
757 #define ADC_CFG_PUDLY_SHIFT                      (16U)
758 /*! PUDLY - Power Up Delay
759  */
760 #define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
761 
762 #define ADC_CFG_PWREN_MASK                       (0x10000000U)
763 #define ADC_CFG_PWREN_SHIFT                      (28U)
764 /*! PWREN - ADC Analog Pre-Enable
765  *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
766  *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
767  *       of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
768  *       is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
769  *       After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
770  *       executed.
771  */
772 #define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
773 /*! @} */
774 
775 /*! @name PAUSE - ADC Pause Register */
776 /*! @{ */
777 
778 #define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
779 #define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
780 /*! PAUSEDLY - Pause Delay
781  */
782 #define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
783 
784 #define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
785 #define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
786 /*! PAUSEEN - PAUSE Option Enable
787  *  0b0..Pause operation disabled
788  *  0b1..Pause operation enabled
789  */
790 #define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
791 /*! @} */
792 
793 /*! @name SWTRIG - Software Trigger Register */
794 /*! @{ */
795 
796 #define ADC_SWTRIG_SWT0_MASK                     (0x1U)
797 #define ADC_SWTRIG_SWT0_SHIFT                    (0U)
798 /*! SWT0 - Software trigger 0 event
799  *  0b0..No trigger 0 event generated.
800  *  0b1..Trigger 0 event generated.
801  */
802 #define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
803 
804 #define ADC_SWTRIG_SWT1_MASK                     (0x2U)
805 #define ADC_SWTRIG_SWT1_SHIFT                    (1U)
806 /*! SWT1 - Software trigger 1 event
807  *  0b0..No trigger 1 event generated.
808  *  0b1..Trigger 1 event generated.
809  */
810 #define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
811 
812 #define ADC_SWTRIG_SWT2_MASK                     (0x4U)
813 #define ADC_SWTRIG_SWT2_SHIFT                    (2U)
814 /*! SWT2 - Software trigger 2 event
815  *  0b0..No trigger 2 event generated.
816  *  0b1..Trigger 2 event generated.
817  */
818 #define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
819 
820 #define ADC_SWTRIG_SWT3_MASK                     (0x8U)
821 #define ADC_SWTRIG_SWT3_SHIFT                    (3U)
822 /*! SWT3 - Software trigger 3 event
823  *  0b0..No trigger 3 event generated.
824  *  0b1..Trigger 3 event generated.
825  */
826 #define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
827 
828 #define ADC_SWTRIG_SWT4_MASK                     (0x10U)
829 #define ADC_SWTRIG_SWT4_SHIFT                    (4U)
830 /*! SWT4 - Software trigger 4 event
831  *  0b0..No trigger 4 event generated.
832  *  0b1..Trigger 4 event generated.
833  */
834 #define ADC_SWTRIG_SWT4(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
835 
836 #define ADC_SWTRIG_SWT5_MASK                     (0x20U)
837 #define ADC_SWTRIG_SWT5_SHIFT                    (5U)
838 /*! SWT5 - Software trigger 5 event
839  *  0b0..No trigger 5 event generated.
840  *  0b1..Trigger 5 event generated.
841  */
842 #define ADC_SWTRIG_SWT5(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
843 
844 #define ADC_SWTRIG_SWT6_MASK                     (0x40U)
845 #define ADC_SWTRIG_SWT6_SHIFT                    (6U)
846 /*! SWT6 - Software trigger 6 event
847  *  0b0..No trigger 6 event generated.
848  *  0b1..Trigger 6 event generated.
849  */
850 #define ADC_SWTRIG_SWT6(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
851 
852 #define ADC_SWTRIG_SWT7_MASK                     (0x80U)
853 #define ADC_SWTRIG_SWT7_SHIFT                    (7U)
854 /*! SWT7 - Software trigger 7 event
855  *  0b0..No trigger 7 event generated.
856  *  0b1..Trigger 7 event generated.
857  */
858 #define ADC_SWTRIG_SWT7(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
859 
860 #define ADC_SWTRIG_SWT8_MASK                     (0x100U)
861 #define ADC_SWTRIG_SWT8_SHIFT                    (8U)
862 /*! SWT8 - Software trigger 8 event
863  *  0b0..No trigger 8 event generated.
864  *  0b1..Trigger 8 event generated.
865  */
866 #define ADC_SWTRIG_SWT8(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)
867 
868 #define ADC_SWTRIG_SWT9_MASK                     (0x200U)
869 #define ADC_SWTRIG_SWT9_SHIFT                    (9U)
870 /*! SWT9 - Software trigger 9 event
871  *  0b0..No trigger 9 event generated.
872  *  0b1..Trigger 9 event generated.
873  */
874 #define ADC_SWTRIG_SWT9(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)
875 
876 #define ADC_SWTRIG_SWT10_MASK                    (0x400U)
877 #define ADC_SWTRIG_SWT10_SHIFT                   (10U)
878 /*! SWT10 - Software trigger 10 event
879  *  0b0..No trigger 10 event generated.
880  *  0b1..Trigger 10 event generated.
881  */
882 #define ADC_SWTRIG_SWT10(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)
883 
884 #define ADC_SWTRIG_SWT11_MASK                    (0x800U)
885 #define ADC_SWTRIG_SWT11_SHIFT                   (11U)
886 /*! SWT11 - Software trigger 11 event
887  *  0b0..No trigger 11 event generated.
888  *  0b1..Trigger 11 event generated.
889  */
890 #define ADC_SWTRIG_SWT11(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)
891 
892 #define ADC_SWTRIG_SWT12_MASK                    (0x1000U)
893 #define ADC_SWTRIG_SWT12_SHIFT                   (12U)
894 /*! SWT12 - Software trigger 12 event
895  *  0b0..No trigger 12 event generated.
896  *  0b1..Trigger 12 event generated.
897  */
898 #define ADC_SWTRIG_SWT12(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)
899 
900 #define ADC_SWTRIG_SWT13_MASK                    (0x2000U)
901 #define ADC_SWTRIG_SWT13_SHIFT                   (13U)
902 /*! SWT13 - Software trigger 13 event
903  *  0b0..No trigger 13 event generated.
904  *  0b1..Trigger 13 event generated.
905  */
906 #define ADC_SWTRIG_SWT13(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)
907 
908 #define ADC_SWTRIG_SWT14_MASK                    (0x4000U)
909 #define ADC_SWTRIG_SWT14_SHIFT                   (14U)
910 /*! SWT14 - Software trigger 14 event
911  *  0b0..No trigger 14 event generated.
912  *  0b1..Trigger 14 event generated.
913  */
914 #define ADC_SWTRIG_SWT14(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)
915 
916 #define ADC_SWTRIG_SWT15_MASK                    (0x8000U)
917 #define ADC_SWTRIG_SWT15_SHIFT                   (15U)
918 /*! SWT15 - Software trigger 15 event
919  *  0b0..No trigger 15 event generated.
920  *  0b1..Trigger 15 event generated.
921  */
922 #define ADC_SWTRIG_SWT15(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)
923 /*! @} */
924 
925 /*! @name TSTAT - Trigger Status Register */
926 /*! @{ */
927 
928 #define ADC_TSTAT_TEXC_NUM_MASK                  (0xFFFFU)
929 #define ADC_TSTAT_TEXC_NUM_SHIFT                 (0U)
930 /*! TEXC_NUM - Trigger Exception Number
931  *  0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
932  *  0b0000000000000001..Trigger 0 has been interrupted by a high priority exception.
933  *  0b0000000000000010..Trigger 1 has been interrupted by a high priority exception.
934  *  0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception.
935  *  0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception.
936  */
937 #define ADC_TSTAT_TEXC_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
938 
939 #define ADC_TSTAT_TCOMP_FLAG_MASK                (0xFFFF0000U)
940 #define ADC_TSTAT_TCOMP_FLAG_SHIFT               (16U)
941 /*! TCOMP_FLAG - Trigger Completion Flag
942  *  0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled.
943  *  0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
944  *  0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
945  *  0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts.
946  *  0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
947  */
948 #define ADC_TSTAT_TCOMP_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
949 /*! @} */
950 
951 /*! @name OFSTRIM - ADC Offset Trim Register */
952 /*! @{ */
953 
954 #define ADC_OFSTRIM_OFSTRIM_A_MASK               (0x1FU)
955 #define ADC_OFSTRIM_OFSTRIM_A_SHIFT              (0U)
956 /*! OFSTRIM_A - Trim for offset
957  */
958 #define ADC_OFSTRIM_OFSTRIM_A(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)
959 
960 #define ADC_OFSTRIM_OFSTRIM_B_MASK               (0x1F0000U)
961 #define ADC_OFSTRIM_OFSTRIM_B_SHIFT              (16U)
962 /*! OFSTRIM_B - Trim for offset
963  */
964 #define ADC_OFSTRIM_OFSTRIM_B(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
965 /*! @} */
966 
967 /*! @name TCTRL - Trigger Control Register */
968 /*! @{ */
969 
970 #define ADC_TCTRL_HTEN_MASK                      (0x1U)
971 #define ADC_TCTRL_HTEN_SHIFT                     (0U)
972 /*! HTEN - Trigger enable
973  *  0b0..Hardware trigger source disabled
974  *  0b1..Hardware trigger source enabled
975  */
976 #define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
977 
978 #define ADC_TCTRL_FIFO_SEL_A_MASK                (0x2U)
979 #define ADC_TCTRL_FIFO_SEL_A_SHIFT               (1U)
980 /*! FIFO_SEL_A - SAR Result Destination For Channel A
981  *  0b0..Result written to FIFO 0
982  *  0b1..Result written to FIFO 1
983  */
984 #define ADC_TCTRL_FIFO_SEL_A(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
985 
986 #define ADC_TCTRL_FIFO_SEL_B_MASK                (0x4U)
987 #define ADC_TCTRL_FIFO_SEL_B_SHIFT               (2U)
988 /*! FIFO_SEL_B - SAR Result Destination For Channel B
989  *  0b0..Result written to FIFO 0
990  *  0b1..Result written to FIFO 1
991  */
992 #define ADC_TCTRL_FIFO_SEL_B(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)
993 
994 #define ADC_TCTRL_TPRI_MASK                      (0xF00U)
995 #define ADC_TCTRL_TPRI_SHIFT                     (8U)
996 /*! TPRI - Trigger priority setting
997  *  0b0000..Set to highest priority, Level 1
998  *  0b0001-0b1110..Set to corresponding priority level
999  *  0b1111..Set to lowest priority, Level 16
1000  */
1001 #define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1002 
1003 #define ADC_TCTRL_RSYNC_MASK                     (0x8000U)
1004 #define ADC_TCTRL_RSYNC_SHIFT                    (15U)
1005 /*! RSYNC - Trigger Resync
1006  */
1007 #define ADC_TCTRL_RSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
1008 
1009 #define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
1010 #define ADC_TCTRL_TDLY_SHIFT                     (16U)
1011 /*! TDLY - Trigger delay select
1012  */
1013 #define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1014 
1015 #define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
1016 #define ADC_TCTRL_TCMD_SHIFT                     (24U)
1017 /*! TCMD - Trigger command select
1018  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1019  *  0b0001..CMD1 is executed
1020  *  0b0010-0b1110..Corresponding CMD is executed
1021  *  0b1111..CMD15 is executed
1022  */
1023 #define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1024 /*! @} */
1025 
1026 /* The count of ADC_TCTRL */
1027 #define ADC_TCTRL_COUNT                          (16U)
1028 
1029 /*! @name FCTRL - FIFO Control Register */
1030 /*! @{ */
1031 
1032 #define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
1033 #define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
1034 /*! FCOUNT - Result FIFO counter
1035  */
1036 #define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
1037 
1038 #define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
1039 #define ADC_FCTRL_FWMARK_SHIFT                   (16U)
1040 /*! FWMARK - Watermark level selection
1041  */
1042 #define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
1043 /*! @} */
1044 
1045 /* The count of ADC_FCTRL */
1046 #define ADC_FCTRL_COUNT                          (2U)
1047 
1048 /*! @name GCC - Gain Calibration Control */
1049 /*! @{ */
1050 
1051 #define ADC_GCC_GAIN_CAL_MASK                    (0xFFFFU)
1052 #define ADC_GCC_GAIN_CAL_SHIFT                   (0U)
1053 /*! GAIN_CAL - Gain Calibration Value
1054  */
1055 #define ADC_GCC_GAIN_CAL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
1056 
1057 #define ADC_GCC_RDY_MASK                         (0x1000000U)
1058 #define ADC_GCC_RDY_SHIFT                        (24U)
1059 /*! RDY - Gain Calibration Value Valid
1060  *  0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.
1061  *  0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.
1062  */
1063 #define ADC_GCC_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
1064 /*! @} */
1065 
1066 /* The count of ADC_GCC */
1067 #define ADC_GCC_COUNT                            (2U)
1068 
1069 /*! @name GCR - Gain Calculation Result */
1070 /*! @{ */
1071 
1072 #define ADC_GCR_GCALR_MASK                       (0xFFFFU)
1073 #define ADC_GCR_GCALR_SHIFT                      (0U)
1074 /*! GCALR - Gain Calculation Result
1075  */
1076 #define ADC_GCR_GCALR(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
1077 
1078 #define ADC_GCR_RDY_MASK                         (0x1000000U)
1079 #define ADC_GCR_RDY_SHIFT                        (24U)
1080 /*! RDY - Gain Calculation Ready
1081  *  0b0..The gain offset calculation value is invalid.
1082  *  0b1..The gain calibration value is valid.
1083  */
1084 #define ADC_GCR_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
1085 /*! @} */
1086 
1087 /* The count of ADC_GCR */
1088 #define ADC_GCR_COUNT                            (2U)
1089 
1090 /*! @name CMDL - ADC Command Low Buffer Register */
1091 /*! @{ */
1092 
1093 #define ADC_CMDL_ADCH_MASK                       (0x1FU)
1094 #define ADC_CMDL_ADCH_SHIFT                      (0U)
1095 /*! ADCH - Input channel select
1096  *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1097  *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1098  *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1099  *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1100  *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1101  *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1102  *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1103  */
1104 #define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1105 
1106 #define ADC_CMDL_CTYPE_MASK                      (0x60U)
1107 #define ADC_CMDL_CTYPE_SHIFT                     (5U)
1108 /*! CTYPE - Conversion Type
1109  *  0b00..Single-Ended Mode. Only A side channel is converted.
1110  *  0b01..Single-Ended Mode. Only B side channel is converted.
1111  *  0b10..Differential Mode. A-B.
1112  *  0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
1113  */
1114 #define ADC_CMDL_CTYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
1115 
1116 #define ADC_CMDL_MODE_MASK                       (0x80U)
1117 #define ADC_CMDL_MODE_SHIFT                      (7U)
1118 /*! MODE - Select resolution of conversions
1119  *  0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
1120  *  0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
1121  */
1122 #define ADC_CMDL_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
1123 /*! @} */
1124 
1125 /* The count of ADC_CMDL */
1126 #define ADC_CMDL_COUNT                           (15U)
1127 
1128 /*! @name CMDH - ADC Command High Buffer Register */
1129 /*! @{ */
1130 
1131 #define ADC_CMDH_CMPEN_MASK                      (0x3U)
1132 #define ADC_CMDH_CMPEN_SHIFT                     (0U)
1133 /*! CMPEN - Compare Function Enable
1134  *  0b00..Compare disabled.
1135  *  0b01..Reserved
1136  *  0b10..Compare enabled. Store on true.
1137  *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1138  */
1139 #define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1140 
1141 #define ADC_CMDH_WAIT_TRIG_MASK                  (0x4U)
1142 #define ADC_CMDH_WAIT_TRIG_SHIFT                 (2U)
1143 /*! WAIT_TRIG - Wait for trigger assertion before execution.
1144  *  0b0..This command will be automatically executed.
1145  *  0b1..The active trigger must be asserted again before executing this command.
1146  */
1147 #define ADC_CMDH_WAIT_TRIG(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
1148 
1149 #define ADC_CMDH_LWI_MASK                        (0x80U)
1150 #define ADC_CMDH_LWI_SHIFT                       (7U)
1151 /*! LWI - Loop with Increment
1152  *  0b0..Auto channel increment disabled
1153  *  0b1..Auto channel increment enabled
1154  */
1155 #define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1156 
1157 #define ADC_CMDH_STS_MASK                        (0x700U)
1158 #define ADC_CMDH_STS_SHIFT                       (8U)
1159 /*! STS - Sample Time Select
1160  *  0b000..Minimum sample time of 3 ADCK cycles.
1161  *  0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1162  *  0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1163  *  0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1164  *  0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1165  *  0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1166  *  0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1167  *  0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1168  */
1169 #define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1170 
1171 #define ADC_CMDH_AVGS_MASK                       (0x7000U)
1172 #define ADC_CMDH_AVGS_SHIFT                      (12U)
1173 /*! AVGS - Hardware Average Select
1174  *  0b000..Single conversion.
1175  *  0b001..2 conversions averaged.
1176  *  0b010..4 conversions averaged.
1177  *  0b011..8 conversions averaged.
1178  *  0b100..16 conversions averaged.
1179  *  0b101..32 conversions averaged.
1180  *  0b110..64 conversions averaged.
1181  *  0b111..128 conversions averaged.
1182  */
1183 #define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1184 
1185 #define ADC_CMDH_LOOP_MASK                       (0xF0000U)
1186 #define ADC_CMDH_LOOP_SHIFT                      (16U)
1187 /*! LOOP - Loop Count Select
1188  *  0b0000..Looping not enabled. Command executes 1 time.
1189  *  0b0001..Loop 1 time. Command executes 2 times.
1190  *  0b0010..Loop 2 times. Command executes 3 times.
1191  *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1192  *  0b1111..Loop 15 times. Command executes 16 times.
1193  */
1194 #define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1195 
1196 #define ADC_CMDH_NEXT_MASK                       (0xF000000U)
1197 #define ADC_CMDH_NEXT_SHIFT                      (24U)
1198 /*! NEXT - Next Command Select
1199  *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1200  *          trigger pending, begin command associated with lower priority trigger.
1201  *  0b0001..Select CMD1 command buffer register as next command.
1202  *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
1203  *  0b1111..Select CMD15 command buffer register as next command.
1204  */
1205 #define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1206 /*! @} */
1207 
1208 /* The count of ADC_CMDH */
1209 #define ADC_CMDH_COUNT                           (15U)
1210 
1211 /*! @name CV - Compare Value Register */
1212 /*! @{ */
1213 
1214 #define ADC_CV_CVL_MASK                          (0xFFFFU)
1215 #define ADC_CV_CVL_SHIFT                         (0U)
1216 /*! CVL - Compare Value Low.
1217  */
1218 #define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1219 
1220 #define ADC_CV_CVH_MASK                          (0xFFFF0000U)
1221 #define ADC_CV_CVH_SHIFT                         (16U)
1222 /*! CVH - Compare Value High.
1223  */
1224 #define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1225 /*! @} */
1226 
1227 /* The count of ADC_CV */
1228 #define ADC_CV_COUNT                             (4U)
1229 
1230 /*! @name RESFIFO - ADC Data Result FIFO Register */
1231 /*! @{ */
1232 
1233 #define ADC_RESFIFO_D_MASK                       (0xFFFFU)
1234 #define ADC_RESFIFO_D_SHIFT                      (0U)
1235 /*! D - Data result
1236  */
1237 #define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1238 
1239 #define ADC_RESFIFO_TSRC_MASK                    (0xF0000U)
1240 #define ADC_RESFIFO_TSRC_SHIFT                   (16U)
1241 /*! TSRC - Trigger Source
1242  *  0b0000..Trigger source 0 initiated this conversion.
1243  *  0b0001..Trigger source 1 initiated this conversion.
1244  *  0b0010-0b1110..Corresponding trigger source initiated this conversion.
1245  *  0b1111..Trigger source 15 initiated this conversion.
1246  */
1247 #define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1248 
1249 #define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
1250 #define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
1251 /*! LOOPCNT - Loop count value
1252  *  0b0000..Result is from initial conversion in command.
1253  *  0b0001..Result is from second conversion in command.
1254  *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1255  *  0b1111..Result is from 16th conversion in command.
1256  */
1257 #define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1258 
1259 #define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
1260 #define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
1261 /*! CMDSRC - Command Buffer Source
1262  *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1263  *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1264  *  0b0001..CMD1 buffer used as control settings for this conversion.
1265  *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1266  *  0b1111..CMD15 buffer used as control settings for this conversion.
1267  */
1268 #define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1269 
1270 #define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
1271 #define ADC_RESFIFO_VALID_SHIFT                  (31U)
1272 /*! VALID - FIFO entry is valid
1273  *  0b0..FIFO is empty. Discard any read from RESFIFO.
1274  *  0b1..FIFO record read from RESFIFO is valid.
1275  */
1276 #define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1277 /*! @} */
1278 
1279 /* The count of ADC_RESFIFO */
1280 #define ADC_RESFIFO_COUNT                        (2U)
1281 
1282 /*! @name CAL_GAR - Calibration General A-Side Registers */
1283 /*! @{ */
1284 
1285 #define ADC_CAL_GAR_CAL_GAR_VAL_MASK             (0xFFFFU)
1286 #define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT            (0U)
1287 /*! CAL_GAR_VAL - Calibration General A Side Register Element
1288  */
1289 #define ADC_CAL_GAR_CAL_GAR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
1290 /*! @} */
1291 
1292 /* The count of ADC_CAL_GAR */
1293 #define ADC_CAL_GAR_COUNT                        (33U)
1294 
1295 /*! @name CAL_GBR - Calibration General B-Side Registers */
1296 /*! @{ */
1297 
1298 #define ADC_CAL_GBR_CAL_GBR_VAL_MASK             (0xFFFFU)
1299 #define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT            (0U)
1300 /*! CAL_GBR_VAL - Calibration General B Side Register Element
1301  */
1302 #define ADC_CAL_GBR_CAL_GBR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
1303 /*! @} */
1304 
1305 /* The count of ADC_CAL_GBR */
1306 #define ADC_CAL_GBR_COUNT                        (33U)
1307 
1308 /*! @name TST - ADC Test Register */
1309 /*! @{ */
1310 
1311 #define ADC_TST_CST_LONG_MASK                    (0x1U)
1312 #define ADC_TST_CST_LONG_SHIFT                   (0U)
1313 /*! CST_LONG - Calibration Sample Time Long
1314  *  0b0..Normal sample time. Minimum sample time of 3 ADCK cycles.
1315  *  0b1..Increased sample time. 67 ADCK cycles total sample time.
1316  */
1317 #define ADC_TST_CST_LONG(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK)
1318 
1319 #define ADC_TST_FOFFM_MASK                       (0x100U)
1320 #define ADC_TST_FOFFM_SHIFT                      (8U)
1321 /*! FOFFM - Force M-side positive offset
1322  *  0b0..Normal operation. No forced offset.
1323  *  0b1..Test configuration. Forced positive offset on MDAC.
1324  */
1325 #define ADC_TST_FOFFM(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK)
1326 
1327 #define ADC_TST_FOFFP_MASK                       (0x200U)
1328 #define ADC_TST_FOFFP_SHIFT                      (9U)
1329 /*! FOFFP - Force P-side positive offset
1330  *  0b0..Normal operation. No forced offset.
1331  *  0b1..Test configuration. Forced positive offset on PDAC.
1332  */
1333 #define ADC_TST_FOFFP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK)
1334 
1335 #define ADC_TST_FOFFM2_MASK                      (0x400U)
1336 #define ADC_TST_FOFFM2_SHIFT                     (10U)
1337 /*! FOFFM2 - Force M-side negative offset
1338  *  0b0..Normal operation. No forced offset.
1339  *  0b1..Test configuration. Forced negative offset on MDAC.
1340  */
1341 #define ADC_TST_FOFFM2(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK)
1342 
1343 #define ADC_TST_FOFFP2_MASK                      (0x800U)
1344 #define ADC_TST_FOFFP2_SHIFT                     (11U)
1345 /*! FOFFP2 - Force P-side negative offset
1346  *  0b0..Normal operation. No forced offset.
1347  *  0b1..Test configuration. Forced negative offset on PDAC.
1348  */
1349 #define ADC_TST_FOFFP2(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK)
1350 
1351 #define ADC_TST_TESTEN_MASK                      (0x800000U)
1352 #define ADC_TST_TESTEN_SHIFT                     (23U)
1353 /*! TESTEN - Enable test configuration
1354  *  0b0..Normal operation. Test configuration not enabled.
1355  *  0b1..Hardware BIST Test in progress.
1356  */
1357 #define ADC_TST_TESTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK)
1358 /*! @} */
1359 
1360 
1361 /*!
1362  * @}
1363  */ /* end of group ADC_Register_Masks */
1364 
1365 
1366 /* ADC - Peripheral instance base addresses */
1367 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
1368   /** Peripheral ADC0 base address */
1369   #define ADC0_BASE                                (0x500A0000u)
1370   /** Peripheral ADC0 base address */
1371   #define ADC0_BASE_NS                             (0x400A0000u)
1372   /** Peripheral ADC0 base pointer */
1373   #define ADC0                                     ((ADC_Type *)ADC0_BASE)
1374   /** Peripheral ADC0 base pointer */
1375   #define ADC0_NS                                  ((ADC_Type *)ADC0_BASE_NS)
1376   /** Array initializer of ADC peripheral base addresses */
1377   #define ADC_BASE_ADDRS                           { ADC0_BASE }
1378   /** Array initializer of ADC peripheral base pointers */
1379   #define ADC_BASE_PTRS                            { ADC0 }
1380   /** Array initializer of ADC peripheral base addresses */
1381   #define ADC_BASE_ADDRS_NS                        { ADC0_BASE_NS }
1382   /** Array initializer of ADC peripheral base pointers */
1383   #define ADC_BASE_PTRS_NS                         { ADC0_NS }
1384 #else
1385   /** Peripheral ADC0 base address */
1386   #define ADC0_BASE                                (0x400A0000u)
1387   /** Peripheral ADC0 base pointer */
1388   #define ADC0                                     ((ADC_Type *)ADC0_BASE)
1389   /** Array initializer of ADC peripheral base addresses */
1390   #define ADC_BASE_ADDRS                           { ADC0_BASE }
1391   /** Array initializer of ADC peripheral base pointers */
1392   #define ADC_BASE_PTRS                            { ADC0 }
1393 #endif
1394 /** Interrupt vectors for the ADC peripheral type */
1395 #define ADC_IRQS                                 { ADC0_IRQn }
1396 
1397 /*!
1398  * @}
1399  */ /* end of group ADC_Peripheral_Access_Layer */
1400 
1401 
1402 /* ----------------------------------------------------------------------------
1403    -- AHB_SECURE_CTRL Peripheral Access Layer
1404    ---------------------------------------------------------------------------- */
1405 
1406 /*!
1407  * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer
1408  * @{
1409  */
1410 
1411 /** AHB_SECURE_CTRL - Register Layout Typedef */
1412 typedef struct {
1413   struct {                                         /* offset: 0x0, array step: 0x30 */
1414     __IO uint32_t SLAVE_RULE;                        /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */
1415          uint8_t RESERVED_0[12];
1416     __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3];        /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */
1417          uint8_t RESERVED_1[4];
1418     __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4];          /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */
1419   } SEC_CTRL_FLASH_ROM[1];
1420   struct {                                         /* offset: 0x30, array step: 0x14 */
1421     __IO uint32_t SLAVE_RULE;                        /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */
1422          uint8_t RESERVED_0[12];
1423     __IO uint32_t MEM_RULE[1];                       /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */
1424   } SEC_CTRL_RAMX[1];
1425        uint8_t RESERVED_0[12];
1426   struct {                                         /* offset: 0x50, array step: 0x18 */
1427     __IO uint32_t SLAVE_RULE;                        /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */
1428          uint8_t RESERVED_0[12];
1429     __IO uint32_t MEM_RULE[2];                       /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */
1430   } SEC_CTRL_RAM0[1];
1431        uint8_t RESERVED_1[8];
1432   struct {                                         /* offset: 0x70, array step: 0x18 */
1433     __IO uint32_t SLAVE_RULE;                        /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */
1434          uint8_t RESERVED_0[12];
1435     __IO uint32_t MEM_RULE[2];                       /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */
1436   } SEC_CTRL_RAM1[1];
1437        uint8_t RESERVED_2[8];
1438   struct {                                         /* offset: 0x90, array step: 0x18 */
1439     __IO uint32_t SLAVE_RULE;                        /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */
1440          uint8_t RESERVED_0[12];
1441     __IO uint32_t MEM_RULE[2];                       /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */
1442   } SEC_CTRL_RAM2[1];
1443        uint8_t RESERVED_3[8];
1444   struct {                                         /* offset: 0xB0, array step: 0x18 */
1445     __IO uint32_t SLAVE_RULE;                        /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */
1446          uint8_t RESERVED_0[12];
1447     __IO uint32_t MEM_RULE[2];                       /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */
1448   } SEC_CTRL_RAM3[1];
1449        uint8_t RESERVED_4[8];
1450   struct {                                         /* offset: 0xD0, array step: 0x14 */
1451     __IO uint32_t SLAVE_RULE;                        /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */
1452          uint8_t RESERVED_0[12];
1453     __IO uint32_t MEM_RULE[1];                       /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */
1454   } SEC_CTRL_RAM4[1];
1455        uint8_t RESERVED_5[12];
1456   struct {                                         /* offset: 0xF0, array step: 0x30 */
1457     __IO uint32_t SLAVE_RULE;                        /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */
1458          uint8_t RESERVED_0[12];
1459     __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0;    /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */
1460     __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1;    /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */
1461     __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2;    /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */
1462          uint8_t RESERVED_1[4];
1463     __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0;    /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */
1464     __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1;    /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */
1465     __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2;    /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */
1466     __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3;    /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */
1467   } SEC_CTRL_APB_BRIDGE[1];
1468   __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE;    /**< Security access rules for AHB peripherals., offset: 0x120 */
1469   __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE;    /**< Security access rules for AHB peripherals., offset: 0x124 */
1470        uint8_t RESERVED_6[8];
1471   __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE;    /**< Security access rules for AHB peripherals., offset: 0x130 */
1472   __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE;    /**< Security access rules for AHB peripherals., offset: 0x134 */
1473        uint8_t RESERVED_7[8];
1474   struct {                                         /* offset: 0x140, array step: 0x14 */
1475     __IO uint32_t SLAVE0_RULE;                       /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */
1476     __IO uint32_t SLAVE1_RULE;                       /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */
1477          uint8_t RESERVED_0[8];
1478     __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1];   /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */
1479   } SEC_CTRL_AHB_PORT10[1];
1480        uint8_t RESERVED_8[12];
1481   struct {                                         /* offset: 0x160, array step: 0x14 */
1482     __IO uint32_t SLAVE_RULE;                        /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */
1483          uint8_t RESERVED_0[12];
1484     __IO uint32_t MEM_RULE[1];                       /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */
1485   } SEC_CTRL_USB_HS[1];
1486        uint8_t RESERVED_9[3212];
1487   __I  uint32_t SEC_VIO_ADDR[12];                  /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */
1488        uint8_t RESERVED_10[80];
1489   __I  uint32_t SEC_VIO_MISC_INFO[12];             /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */
1490        uint8_t RESERVED_11[80];
1491   __IO uint32_t SEC_VIO_INFO_VALID;                /**< security violation address/information registers valid flags, offset: 0xF00 */
1492        uint8_t RESERVED_12[124];
1493   __IO uint32_t SEC_GPIO_MASK0;                    /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */
1494   __IO uint32_t SEC_GPIO_MASK1;                    /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */
1495        uint8_t RESERVED_13[8];
1496   __IO uint32_t SEC_CPU_INT_MASK0;                 /**< Secure Interrupt mask for CPU1, offset: 0xF90 */
1497   __IO uint32_t SEC_CPU_INT_MASK1;                 /**< Secure Interrupt mask for CPU1, offset: 0xF94 */
1498        uint8_t RESERVED_14[36];
1499   __IO uint32_t SEC_MASK_LOCK;                     /**< Security General Purpose register access control., offset: 0xFBC */
1500        uint8_t RESERVED_15[16];
1501   __IO uint32_t MASTER_SEC_LEVEL;                  /**< master secure level register, offset: 0xFD0 */
1502   __IO uint32_t MASTER_SEC_ANTI_POL_REG;           /**< master secure level anti-pole register, offset: 0xFD4 */
1503        uint8_t RESERVED_16[20];
1504   __IO uint32_t CPU0_LOCK_REG;                     /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */
1505   __IO uint32_t CPU1_LOCK_REG;                     /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */
1506        uint8_t RESERVED_17[4];
1507   __IO uint32_t MISC_CTRL_DP_REG;                  /**< secure control duplicate register, offset: 0xFF8 */
1508   __IO uint32_t MISC_CTRL_REG;                     /**< secure control register, offset: 0xFFC */
1509 } AHB_SECURE_CTRL_Type;
1510 
1511 /* ----------------------------------------------------------------------------
1512    -- AHB_SECURE_CTRL Register Masks
1513    ---------------------------------------------------------------------------- */
1514 
1515 /*!
1516  * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks
1517  * @{
1518  */
1519 
1520 /*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */
1521 /*! @{ */
1522 
1523 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U)
1524 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U)
1525 /*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF
1526  *  0b00..Non-secure and Non-priviledge user access allowed.
1527  *  0b01..Non-secure and Privilege access allowed.
1528  *  0b10..Secure and Non-priviledge user access allowed.
1529  *  0b11..Secure and Priviledge user access allowed.
1530  */
1531 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK)
1532 
1533 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U)
1534 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U)
1535 /*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF
1536  *  0b00..Non-secure and Non-priviledge user access allowed.
1537  *  0b01..Non-secure and Privilege access allowed.
1538  *  0b10..Secure and Non-priviledge user access allowed.
1539  *  0b11..Secure and Priviledge user access allowed.
1540  */
1541 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK)
1542 /*! @} */
1543 
1544 /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */
1545 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U)
1546 
1547 /*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */
1548 /*! @{ */
1549 
1550 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U)
1551 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U)
1552 /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1553  *  0b00..Non-secure and Non-priviledge user access allowed.
1554  *  0b01..Non-secure and Privilege access allowed.
1555  *  0b10..Secure and Non-priviledge user access allowed.
1556  *  0b11..Secure and Priviledge user access allowed.
1557  */
1558 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK)
1559 
1560 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U)
1561 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U)
1562 /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1563  *  0b00..Non-secure and Non-priviledge user access allowed.
1564  *  0b01..Non-secure and Privilege access allowed.
1565  *  0b10..Secure and Non-priviledge user access allowed.
1566  *  0b11..Secure and Priviledge user access allowed.
1567  */
1568 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK)
1569 
1570 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U)
1571 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U)
1572 /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1573  *  0b00..Non-secure and Non-priviledge user access allowed.
1574  *  0b01..Non-secure and Privilege access allowed.
1575  *  0b10..Secure and Non-priviledge user access allowed.
1576  *  0b11..Secure and Priviledge user access allowed.
1577  */
1578 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK)
1579 
1580 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U)
1581 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U)
1582 /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1583  *  0b00..Non-secure and Non-priviledge user access allowed.
1584  *  0b01..Non-secure and Privilege access allowed.
1585  *  0b10..Secure and Non-priviledge user access allowed.
1586  *  0b11..Secure and Priviledge user access allowed.
1587  */
1588 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK)
1589 
1590 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U)
1591 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U)
1592 /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1593  *  0b00..Non-secure and Non-priviledge user access allowed.
1594  *  0b01..Non-secure and Privilege access allowed.
1595  *  0b10..Secure and Non-priviledge user access allowed.
1596  *  0b11..Secure and Priviledge user access allowed.
1597  */
1598 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK)
1599 
1600 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U)
1601 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U)
1602 /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1603  *  0b00..Non-secure and Non-priviledge user access allowed.
1604  *  0b01..Non-secure and Privilege access allowed.
1605  *  0b10..Secure and Non-priviledge user access allowed.
1606  *  0b11..Secure and Priviledge user access allowed.
1607  */
1608 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK)
1609 
1610 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U)
1611 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U)
1612 /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1613  *  0b00..Non-secure and Non-priviledge user access allowed.
1614  *  0b01..Non-secure and Privilege access allowed.
1615  *  0b10..Secure and Non-priviledge user access allowed.
1616  *  0b11..Secure and Priviledge user access allowed.
1617  */
1618 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK)
1619 
1620 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U)
1621 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U)
1622 /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1623  *  0b00..Non-secure and Non-priviledge user access allowed.
1624  *  0b01..Non-secure and Privilege access allowed.
1625  *  0b10..Secure and Non-priviledge user access allowed.
1626  *  0b11..Secure and Priviledge user access allowed.
1627  */
1628 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK)
1629 /*! @} */
1630 
1631 /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1632 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U)
1633 
1634 /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1635 #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U)
1636 
1637 /*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */
1638 /*! @{ */
1639 
1640 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U)
1641 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U)
1642 /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1643  *  0b00..Non-secure and Non-priviledge user access allowed.
1644  *  0b01..Non-secure and Privilege access allowed.
1645  *  0b10..Secure and Non-priviledge user access allowed.
1646  *  0b11..Secure and Priviledge user access allowed.
1647  */
1648 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK)
1649 
1650 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U)
1651 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U)
1652 /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1653  *  0b00..Non-secure and Non-priviledge user access allowed.
1654  *  0b01..Non-secure and Privilege access allowed.
1655  *  0b10..Secure and Non-priviledge user access allowed.
1656  *  0b11..Secure and Priviledge user access allowed.
1657  */
1658 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK)
1659 
1660 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U)
1661 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U)
1662 /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1663  *  0b00..Non-secure and Non-priviledge user access allowed.
1664  *  0b01..Non-secure and Privilege access allowed.
1665  *  0b10..Secure and Non-priviledge user access allowed.
1666  *  0b11..Secure and Priviledge user access allowed.
1667  */
1668 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK)
1669 
1670 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U)
1671 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U)
1672 /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1673  *  0b00..Non-secure and Non-priviledge user access allowed.
1674  *  0b01..Non-secure and Privilege access allowed.
1675  *  0b10..Secure and Non-priviledge user access allowed.
1676  *  0b11..Secure and Priviledge user access allowed.
1677  */
1678 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK)
1679 
1680 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U)
1681 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U)
1682 /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1683  *  0b00..Non-secure and Non-priviledge user access allowed.
1684  *  0b01..Non-secure and Privilege access allowed.
1685  *  0b10..Secure and Non-priviledge user access allowed.
1686  *  0b11..Secure and Priviledge user access allowed.
1687  */
1688 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK)
1689 
1690 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U)
1691 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U)
1692 /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1693  *  0b00..Non-secure and Non-priviledge user access allowed.
1694  *  0b01..Non-secure and Privilege access allowed.
1695  *  0b10..Secure and Non-priviledge user access allowed.
1696  *  0b11..Secure and Priviledge user access allowed.
1697  */
1698 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK)
1699 
1700 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U)
1701 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U)
1702 /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1703  *  0b00..Non-secure and Non-priviledge user access allowed.
1704  *  0b01..Non-secure and Privilege access allowed.
1705  *  0b10..Secure and Non-priviledge user access allowed.
1706  *  0b11..Secure and Priviledge user access allowed.
1707  */
1708 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK)
1709 
1710 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U)
1711 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U)
1712 /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1713  *  0b00..Non-secure and Non-priviledge user access allowed.
1714  *  0b01..Non-secure and Privilege access allowed.
1715  *  0b10..Secure and Non-priviledge user access allowed.
1716  *  0b11..Secure and Priviledge user access allowed.
1717  */
1718 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK)
1719 /*! @} */
1720 
1721 /* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1722 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U)
1723 
1724 /* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1725 #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U)
1726 
1727 /*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */
1728 /*! @{ */
1729 
1730 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U)
1731 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U)
1732 /*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF
1733  *  0b00..Non-secure and Non-priviledge user access allowed.
1734  *  0b01..Non-secure and Privilege access allowed.
1735  *  0b10..Secure and Non-priviledge user access allowed.
1736  *  0b11..Secure and Priviledge user access allowed.
1737  */
1738 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK)
1739 /*! @} */
1740 
1741 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */
1742 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U)
1743 
1744 /*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */
1745 /*! @{ */
1746 
1747 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U)
1748 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U)
1749 /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1750  *  0b00..Non-secure and Non-priviledge user access allowed.
1751  *  0b01..Non-secure and Privilege access allowed.
1752  *  0b10..Secure and Non-priviledge user access allowed.
1753  *  0b11..Secure and Priviledge user access allowed.
1754  */
1755 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK)
1756 
1757 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U)
1758 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U)
1759 /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1760  *  0b00..Non-secure and Non-priviledge user access allowed.
1761  *  0b01..Non-secure and Privilege access allowed.
1762  *  0b10..Secure and Non-priviledge user access allowed.
1763  *  0b11..Secure and Priviledge user access allowed.
1764  */
1765 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK)
1766 
1767 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U)
1768 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U)
1769 /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1770  *  0b00..Non-secure and Non-priviledge user access allowed.
1771  *  0b01..Non-secure and Privilege access allowed.
1772  *  0b10..Secure and Non-priviledge user access allowed.
1773  *  0b11..Secure and Priviledge user access allowed.
1774  */
1775 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK)
1776 
1777 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U)
1778 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U)
1779 /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1780  *  0b00..Non-secure and Non-priviledge user access allowed.
1781  *  0b01..Non-secure and Privilege access allowed.
1782  *  0b10..Secure and Non-priviledge user access allowed.
1783  *  0b11..Secure and Priviledge user access allowed.
1784  */
1785 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK)
1786 
1787 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U)
1788 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U)
1789 /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1790  *  0b00..Non-secure and Non-priviledge user access allowed.
1791  *  0b01..Non-secure and Privilege access allowed.
1792  *  0b10..Secure and Non-priviledge user access allowed.
1793  *  0b11..Secure and Priviledge user access allowed.
1794  */
1795 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK)
1796 
1797 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U)
1798 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U)
1799 /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1800  *  0b00..Non-secure and Non-priviledge user access allowed.
1801  *  0b01..Non-secure and Privilege access allowed.
1802  *  0b10..Secure and Non-priviledge user access allowed.
1803  *  0b11..Secure and Priviledge user access allowed.
1804  */
1805 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK)
1806 
1807 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U)
1808 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U)
1809 /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1810  *  0b00..Non-secure and Non-priviledge user access allowed.
1811  *  0b01..Non-secure and Privilege access allowed.
1812  *  0b10..Secure and Non-priviledge user access allowed.
1813  *  0b11..Secure and Priviledge user access allowed.
1814  */
1815 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK)
1816 
1817 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U)
1818 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U)
1819 /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1820  *  0b00..Non-secure and Non-priviledge user access allowed.
1821  *  0b01..Non-secure and Privilege access allowed.
1822  *  0b10..Secure and Non-priviledge user access allowed.
1823  *  0b11..Secure and Priviledge user access allowed.
1824  */
1825 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK)
1826 /*! @} */
1827 
1828 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1829 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U)
1830 
1831 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1832 #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U)
1833 
1834 /*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */
1835 /*! @{ */
1836 
1837 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U)
1838 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U)
1839 /*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF
1840  *  0b00..Non-secure and Non-priviledge user access allowed.
1841  *  0b01..Non-secure and Privilege access allowed.
1842  *  0b10..Secure and Non-priviledge user access allowed.
1843  *  0b11..Secure and Priviledge user access allowed.
1844  */
1845 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK)
1846 /*! @} */
1847 
1848 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */
1849 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U)
1850 
1851 /*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */
1852 /*! @{ */
1853 
1854 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U)
1855 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U)
1856 /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1857  *  0b00..Non-secure and Non-priviledge user access allowed.
1858  *  0b01..Non-secure and Privilege access allowed.
1859  *  0b10..Secure and Non-priviledge user access allowed.
1860  *  0b11..Secure and Priviledge user access allowed.
1861  */
1862 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK)
1863 
1864 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U)
1865 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U)
1866 /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1867  *  0b00..Non-secure and Non-priviledge user access allowed.
1868  *  0b01..Non-secure and Privilege access allowed.
1869  *  0b10..Secure and Non-priviledge user access allowed.
1870  *  0b11..Secure and Priviledge user access allowed.
1871  */
1872 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK)
1873 
1874 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U)
1875 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U)
1876 /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1877  *  0b00..Non-secure and Non-priviledge user access allowed.
1878  *  0b01..Non-secure and Privilege access allowed.
1879  *  0b10..Secure and Non-priviledge user access allowed.
1880  *  0b11..Secure and Priviledge user access allowed.
1881  */
1882 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK)
1883 
1884 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U)
1885 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U)
1886 /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1887  *  0b00..Non-secure and Non-priviledge user access allowed.
1888  *  0b01..Non-secure and Privilege access allowed.
1889  *  0b10..Secure and Non-priviledge user access allowed.
1890  *  0b11..Secure and Priviledge user access allowed.
1891  */
1892 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK)
1893 
1894 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U)
1895 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U)
1896 /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1897  *  0b00..Non-secure and Non-priviledge user access allowed.
1898  *  0b01..Non-secure and Privilege access allowed.
1899  *  0b10..Secure and Non-priviledge user access allowed.
1900  *  0b11..Secure and Priviledge user access allowed.
1901  */
1902 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK)
1903 
1904 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U)
1905 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U)
1906 /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1907  *  0b00..Non-secure and Non-priviledge user access allowed.
1908  *  0b01..Non-secure and Privilege access allowed.
1909  *  0b10..Secure and Non-priviledge user access allowed.
1910  *  0b11..Secure and Priviledge user access allowed.
1911  */
1912 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK)
1913 
1914 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U)
1915 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U)
1916 /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1917  *  0b00..Non-secure and Non-priviledge user access allowed.
1918  *  0b01..Non-secure and Privilege access allowed.
1919  *  0b10..Secure and Non-priviledge user access allowed.
1920  *  0b11..Secure and Priviledge user access allowed.
1921  */
1922 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK)
1923 
1924 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U)
1925 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U)
1926 /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1927  *  0b00..Non-secure and Non-priviledge user access allowed.
1928  *  0b01..Non-secure and Privilege access allowed.
1929  *  0b10..Secure and Non-priviledge user access allowed.
1930  *  0b11..Secure and Priviledge user access allowed.
1931  */
1932 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK)
1933 /*! @} */
1934 
1935 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1936 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U)
1937 
1938 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1939 #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U)
1940 
1941 /*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */
1942 /*! @{ */
1943 
1944 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U)
1945 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U)
1946 /*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0
1947  *  0b00..Non-secure and Non-priviledge user access allowed.
1948  *  0b01..Non-secure and Privilege access allowed.
1949  *  0b10..Secure and Non-priviledge user access allowed.
1950  *  0b11..Secure and Priviledge user access allowed.
1951  */
1952 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK)
1953 /*! @} */
1954 
1955 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */
1956 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U)
1957 
1958 /*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */
1959 /*! @{ */
1960 
1961 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U)
1962 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U)
1963 /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1964  *  0b00..Non-secure and Non-priviledge user access allowed.
1965  *  0b01..Non-secure and Privilege access allowed.
1966  *  0b10..Secure and Non-priviledge user access allowed.
1967  *  0b11..Secure and Priviledge user access allowed.
1968  */
1969 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK)
1970 
1971 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U)
1972 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U)
1973 /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1974  *  0b00..Non-secure and Non-priviledge user access allowed.
1975  *  0b01..Non-secure and Privilege access allowed.
1976  *  0b10..Secure and Non-priviledge user access allowed.
1977  *  0b11..Secure and Priviledge user access allowed.
1978  */
1979 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK)
1980 
1981 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U)
1982 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U)
1983 /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1984  *  0b00..Non-secure and Non-priviledge user access allowed.
1985  *  0b01..Non-secure and Privilege access allowed.
1986  *  0b10..Secure and Non-priviledge user access allowed.
1987  *  0b11..Secure and Priviledge user access allowed.
1988  */
1989 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK)
1990 
1991 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U)
1992 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U)
1993 /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1994  *  0b00..Non-secure and Non-priviledge user access allowed.
1995  *  0b01..Non-secure and Privilege access allowed.
1996  *  0b10..Secure and Non-priviledge user access allowed.
1997  *  0b11..Secure and Priviledge user access allowed.
1998  */
1999 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK)
2000 
2001 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U)
2002 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U)
2003 /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
2004  *  0b00..Non-secure and Non-priviledge user access allowed.
2005  *  0b01..Non-secure and Privilege access allowed.
2006  *  0b10..Secure and Non-priviledge user access allowed.
2007  *  0b11..Secure and Priviledge user access allowed.
2008  */
2009 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK)
2010 
2011 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U)
2012 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U)
2013 /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
2014  *  0b00..Non-secure and Non-priviledge user access allowed.
2015  *  0b01..Non-secure and Privilege access allowed.
2016  *  0b10..Secure and Non-priviledge user access allowed.
2017  *  0b11..Secure and Priviledge user access allowed.
2018  */
2019 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK)
2020 
2021 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U)
2022 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U)
2023 /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
2024  *  0b00..Non-secure and Non-priviledge user access allowed.
2025  *  0b01..Non-secure and Privilege access allowed.
2026  *  0b10..Secure and Non-priviledge user access allowed.
2027  *  0b11..Secure and Priviledge user access allowed.
2028  */
2029 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK)
2030 
2031 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U)
2032 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U)
2033 /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
2034  *  0b00..Non-secure and Non-priviledge user access allowed.
2035  *  0b01..Non-secure and Privilege access allowed.
2036  *  0b10..Secure and Non-priviledge user access allowed.
2037  *  0b11..Secure and Priviledge user access allowed.
2038  */
2039 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK)
2040 /*! @} */
2041 
2042 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
2043 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U)
2044 
2045 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
2046 #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U)
2047 
2048 /*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */
2049 /*! @{ */
2050 
2051 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U)
2052 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U)
2053 /*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF
2054  *  0b00..Non-secure and Non-priviledge user access allowed.
2055  *  0b01..Non-secure and Privilege access allowed.
2056  *  0b10..Secure and Non-priviledge user access allowed.
2057  *  0b11..Secure and Priviledge user access allowed.
2058  */
2059 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK)
2060 /*! @} */
2061 
2062 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */
2063 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U)
2064 
2065 /*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */
2066 /*! @{ */
2067 
2068 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U)
2069 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U)
2070 /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
2071  *  0b00..Non-secure and Non-priviledge user access allowed.
2072  *  0b01..Non-secure and Privilege access allowed.
2073  *  0b10..Secure and Non-priviledge user access allowed.
2074  *  0b11..Secure and Priviledge user access allowed.
2075  */
2076 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK)
2077 
2078 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U)
2079 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U)
2080 /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
2081  *  0b00..Non-secure and Non-priviledge user access allowed.
2082  *  0b01..Non-secure and Privilege access allowed.
2083  *  0b10..Secure and Non-priviledge user access allowed.
2084  *  0b11..Secure and Priviledge user access allowed.
2085  */
2086 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK)
2087 
2088 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U)
2089 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U)
2090 /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
2091  *  0b00..Non-secure and Non-priviledge user access allowed.
2092  *  0b01..Non-secure and Privilege access allowed.
2093  *  0b10..Secure and Non-priviledge user access allowed.
2094  *  0b11..Secure and Priviledge user access allowed.
2095  */
2096 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK)
2097 
2098 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U)
2099 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U)
2100 /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
2101  *  0b00..Non-secure and Non-priviledge user access allowed.
2102  *  0b01..Non-secure and Privilege access allowed.
2103  *  0b10..Secure and Non-priviledge user access allowed.
2104  *  0b11..Secure and Priviledge user access allowed.
2105  */
2106 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK)
2107 
2108 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U)
2109 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U)
2110 /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
2111  *  0b00..Non-secure and Non-priviledge user access allowed.
2112  *  0b01..Non-secure and Privilege access allowed.
2113  *  0b10..Secure and Non-priviledge user access allowed.
2114  *  0b11..Secure and Priviledge user access allowed.
2115  */
2116 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK)
2117 
2118 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U)
2119 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U)
2120 /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
2121  *  0b00..Non-secure and Non-priviledge user access allowed.
2122  *  0b01..Non-secure and Privilege access allowed.
2123  *  0b10..Secure and Non-priviledge user access allowed.
2124  *  0b11..Secure and Priviledge user access allowed.
2125  */
2126 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK)
2127 
2128 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U)
2129 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U)
2130 /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
2131  *  0b00..Non-secure and Non-priviledge user access allowed.
2132  *  0b01..Non-secure and Privilege access allowed.
2133  *  0b10..Secure and Non-priviledge user access allowed.
2134  *  0b11..Secure and Priviledge user access allowed.
2135  */
2136 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK)
2137 
2138 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U)
2139 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U)
2140 /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
2141  *  0b00..Non-secure and Non-priviledge user access allowed.
2142  *  0b01..Non-secure and Privilege access allowed.
2143  *  0b10..Secure and Non-priviledge user access allowed.
2144  *  0b11..Secure and Priviledge user access allowed.
2145  */
2146 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK)
2147 /*! @} */
2148 
2149 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
2150 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U)
2151 
2152 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
2153 #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U)
2154 
2155 /*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */
2156 /*! @{ */
2157 
2158 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U)
2159 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U)
2160 /*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF
2161  *  0b00..Non-secure and Non-priviledge user access allowed.
2162  *  0b01..Non-secure and Privilege access allowed.
2163  *  0b10..Secure and Non-priviledge user access allowed.
2164  *  0b11..Secure and Priviledge user access allowed.
2165  */
2166 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK)
2167 /*! @} */
2168 
2169 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */
2170 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U)
2171 
2172 /*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */
2173 /*! @{ */
2174 
2175 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U)
2176 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U)
2177 /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
2178  *  0b00..Non-secure and Non-priviledge user access allowed.
2179  *  0b01..Non-secure and Privilege access allowed.
2180  *  0b10..Secure and Non-priviledge user access allowed.
2181  *  0b11..Secure and Priviledge user access allowed.
2182  */
2183 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK)
2184 
2185 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U)
2186 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U)
2187 /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
2188  *  0b00..Non-secure and Non-priviledge user access allowed.
2189  *  0b01..Non-secure and Privilege access allowed.
2190  *  0b10..Secure and Non-priviledge user access allowed.
2191  *  0b11..Secure and Priviledge user access allowed.
2192  */
2193 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK)
2194 
2195 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U)
2196 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U)
2197 /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
2198  *  0b00..Non-secure and Non-priviledge user access allowed.
2199  *  0b01..Non-secure and Privilege access allowed.
2200  *  0b10..Secure and Non-priviledge user access allowed.
2201  *  0b11..Secure and Priviledge user access allowed.
2202  */
2203 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK)
2204 
2205 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U)
2206 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U)
2207 /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
2208  *  0b00..Non-secure and Non-priviledge user access allowed.
2209  *  0b01..Non-secure and Privilege access allowed.
2210  *  0b10..Secure and Non-priviledge user access allowed.
2211  *  0b11..Secure and Priviledge user access allowed.
2212  */
2213 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK)
2214 
2215 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U)
2216 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U)
2217 /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
2218  *  0b00..Non-secure and Non-priviledge user access allowed.
2219  *  0b01..Non-secure and Privilege access allowed.
2220  *  0b10..Secure and Non-priviledge user access allowed.
2221  *  0b11..Secure and Priviledge user access allowed.
2222  */
2223 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK)
2224 
2225 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U)
2226 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U)
2227 /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
2228  *  0b00..Non-secure and Non-priviledge user access allowed.
2229  *  0b01..Non-secure and Privilege access allowed.
2230  *  0b10..Secure and Non-priviledge user access allowed.
2231  *  0b11..Secure and Priviledge user access allowed.
2232  */
2233 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK)
2234 
2235 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U)
2236 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U)
2237 /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
2238  *  0b00..Non-secure and Non-priviledge user access allowed.
2239  *  0b01..Non-secure and Privilege access allowed.
2240  *  0b10..Secure and Non-priviledge user access allowed.
2241  *  0b11..Secure and Priviledge user access allowed.
2242  */
2243 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK)
2244 
2245 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U)
2246 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U)
2247 /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
2248  *  0b00..Non-secure and Non-priviledge user access allowed.
2249  *  0b01..Non-secure and Privilege access allowed.
2250  *  0b10..Secure and Non-priviledge user access allowed.
2251  *  0b11..Secure and Priviledge user access allowed.
2252  */
2253 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK)
2254 /*! @} */
2255 
2256 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */
2257 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U)
2258 
2259 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */
2260 #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U)
2261 
2262 /*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */
2263 /*! @{ */
2264 
2265 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U)
2266 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U)
2267 /*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF
2268  *  0b00..Non-secure and Non-priviledge user access allowed.
2269  *  0b01..Non-secure and Privilege access allowed.
2270  *  0b10..Secure and Non-priviledge user access allowed.
2271  *  0b11..Secure and Priviledge user access allowed.
2272  */
2273 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK)
2274 /*! @} */
2275 
2276 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */
2277 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U)
2278 
2279 /*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */
2280 /*! @{ */
2281 
2282 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U)
2283 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U)
2284 /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
2285  *  0b00..Non-secure and Non-priviledge user access allowed.
2286  *  0b01..Non-secure and Privilege access allowed.
2287  *  0b10..Secure and Non-priviledge user access allowed.
2288  *  0b11..Secure and Priviledge user access allowed.
2289  */
2290 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK)
2291 
2292 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U)
2293 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U)
2294 /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
2295  *  0b00..Non-secure and Non-priviledge user access allowed.
2296  *  0b01..Non-secure and Privilege access allowed.
2297  *  0b10..Secure and Non-priviledge user access allowed.
2298  *  0b11..Secure and Priviledge user access allowed.
2299  */
2300 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK)
2301 
2302 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U)
2303 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U)
2304 /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
2305  *  0b00..Non-secure and Non-priviledge user access allowed.
2306  *  0b01..Non-secure and Privilege access allowed.
2307  *  0b10..Secure and Non-priviledge user access allowed.
2308  *  0b11..Secure and Priviledge user access allowed.
2309  */
2310 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK)
2311 
2312 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U)
2313 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U)
2314 /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
2315  *  0b00..Non-secure and Non-priviledge user access allowed.
2316  *  0b01..Non-secure and Privilege access allowed.
2317  *  0b10..Secure and Non-priviledge user access allowed.
2318  *  0b11..Secure and Priviledge user access allowed.
2319  */
2320 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK)
2321 /*! @} */
2322 
2323 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */
2324 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U)
2325 
2326 /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */
2327 #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U)
2328 
2329 /*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */
2330 /*! @{ */
2331 
2332 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U)
2333 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U)
2334 /*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0
2335  *  0b00..Non-secure and Non-priviledge user access allowed.
2336  *  0b01..Non-secure and Privilege access allowed.
2337  *  0b10..Secure and Non-priviledge user access allowed.
2338  *  0b11..Secure and Priviledge user access allowed.
2339  */
2340 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK)
2341 
2342 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U)
2343 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U)
2344 /*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1
2345  *  0b00..Non-secure and Non-priviledge user access allowed.
2346  *  0b01..Non-secure and Privilege access allowed.
2347  *  0b10..Secure and Non-priviledge user access allowed.
2348  *  0b11..Secure and Priviledge user access allowed.
2349  */
2350 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK)
2351 /*! @} */
2352 
2353 /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */
2354 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U)
2355 
2356 /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2357 /*! @{ */
2358 
2359 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U)
2360 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U)
2361 /*! SYSCON_RULE - System Configuration
2362  *  0b00..Non-secure and Non-priviledge user access allowed.
2363  *  0b01..Non-secure and Privilege access allowed.
2364  *  0b10..Secure and Non-priviledge user access allowed.
2365  *  0b11..Secure and Priviledge user access allowed.
2366  */
2367 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK)
2368 
2369 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U)
2370 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U)
2371 /*! IOCON_RULE - I/O Configuration
2372  *  0b00..Non-secure and Non-priviledge user access allowed.
2373  *  0b01..Non-secure and Privilege access allowed.
2374  *  0b10..Secure and Non-priviledge user access allowed.
2375  *  0b11..Secure and Priviledge user access allowed.
2376  */
2377 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK)
2378 
2379 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U)
2380 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U)
2381 /*! GINT0_RULE - GPIO input Interrupt 0
2382  *  0b00..Non-secure and Non-priviledge user access allowed.
2383  *  0b01..Non-secure and Privilege access allowed.
2384  *  0b10..Secure and Non-priviledge user access allowed.
2385  *  0b11..Secure and Priviledge user access allowed.
2386  */
2387 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK)
2388 
2389 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U)
2390 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U)
2391 /*! GINT1_RULE - GPIO input Interrupt 1
2392  *  0b00..Non-secure and Non-priviledge user access allowed.
2393  *  0b01..Non-secure and Privilege access allowed.
2394  *  0b10..Secure and Non-priviledge user access allowed.
2395  *  0b11..Secure and Priviledge user access allowed.
2396  */
2397 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK)
2398 
2399 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U)
2400 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U)
2401 /*! PINT_RULE - Pin Interrupt and Pattern match
2402  *  0b00..Non-secure and Non-priviledge user access allowed.
2403  *  0b01..Non-secure and Privilege access allowed.
2404  *  0b10..Secure and Non-priviledge user access allowed.
2405  *  0b11..Secure and Priviledge user access allowed.
2406  */
2407 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK)
2408 
2409 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U)
2410 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U)
2411 /*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match
2412  *  0b00..Non-secure and Non-priviledge user access allowed.
2413  *  0b01..Non-secure and Privilege access allowed.
2414  *  0b10..Secure and Non-priviledge user access allowed.
2415  *  0b11..Secure and Priviledge user access allowed.
2416  */
2417 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK)
2418 
2419 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U)
2420 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U)
2421 /*! INPUTMUX_RULE - Peripheral input multiplexing
2422  *  0b00..Non-secure and Non-priviledge user access allowed.
2423  *  0b01..Non-secure and Privilege access allowed.
2424  *  0b10..Secure and Non-priviledge user access allowed.
2425  *  0b11..Secure and Priviledge user access allowed.
2426  */
2427 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK)
2428 /*! @} */
2429 
2430 /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */
2431 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U)
2432 
2433 /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2434 /*! @{ */
2435 
2436 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U)
2437 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U)
2438 /*! CTIMER0_RULE - Standard counter/Timer 0
2439  *  0b00..Non-secure and Non-priviledge user access allowed.
2440  *  0b01..Non-secure and Privilege access allowed.
2441  *  0b10..Secure and Non-priviledge user access allowed.
2442  *  0b11..Secure and Priviledge user access allowed.
2443  */
2444 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK)
2445 
2446 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U)
2447 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U)
2448 /*! CTIMER1_RULE - Standard counter/Timer 1
2449  *  0b00..Non-secure and Non-priviledge user access allowed.
2450  *  0b01..Non-secure and Privilege access allowed.
2451  *  0b10..Secure and Non-priviledge user access allowed.
2452  *  0b11..Secure and Priviledge user access allowed.
2453  */
2454 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK)
2455 
2456 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U)
2457 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U)
2458 /*! WWDT_RULE - Windiwed wtachdog Timer
2459  *  0b00..Non-secure and Non-priviledge user access allowed.
2460  *  0b01..Non-secure and Privilege access allowed.
2461  *  0b10..Secure and Non-priviledge user access allowed.
2462  *  0b11..Secure and Priviledge user access allowed.
2463  */
2464 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK)
2465 
2466 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U)
2467 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U)
2468 /*! MRT_RULE - Multi-rate Timer
2469  *  0b00..Non-secure and Non-priviledge user access allowed.
2470  *  0b01..Non-secure and Privilege access allowed.
2471  *  0b10..Secure and Non-priviledge user access allowed.
2472  *  0b11..Secure and Priviledge user access allowed.
2473  */
2474 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK)
2475 
2476 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U)
2477 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U)
2478 /*! UTICK_RULE - Micro-Timer
2479  *  0b00..Non-secure and Non-priviledge user access allowed.
2480  *  0b01..Non-secure and Privilege access allowed.
2481  *  0b10..Secure and Non-priviledge user access allowed.
2482  *  0b11..Secure and Priviledge user access allowed.
2483  */
2484 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK)
2485 /*! @} */
2486 
2487 /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */
2488 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U)
2489 
2490 /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2491 /*! @{ */
2492 
2493 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U)
2494 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U)
2495 /*! ANACTRL_RULE - Analog Modules controller
2496  *  0b00..Non-secure and Non-priviledge user access allowed.
2497  *  0b01..Non-secure and Privilege access allowed.
2498  *  0b10..Secure and Non-priviledge user access allowed.
2499  *  0b11..Secure and Priviledge user access allowed.
2500  */
2501 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK)
2502 /*! @} */
2503 
2504 /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */
2505 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U)
2506 
2507 /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2508 /*! @{ */
2509 
2510 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U)
2511 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U)
2512 /*! PMC_RULE - Power Management Controller
2513  *  0b00..Non-secure and Non-priviledge user access allowed.
2514  *  0b01..Non-secure and Privilege access allowed.
2515  *  0b10..Secure and Non-priviledge user access allowed.
2516  *  0b11..Secure and Priviledge user access allowed.
2517  */
2518 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK)
2519 
2520 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U)
2521 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U)
2522 /*! SYSCTRL_RULE - System Controller
2523  *  0b00..Non-secure and Non-priviledge user access allowed.
2524  *  0b01..Non-secure and Privilege access allowed.
2525  *  0b10..Secure and Non-priviledge user access allowed.
2526  *  0b11..Secure and Priviledge user access allowed.
2527  */
2528 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK)
2529 /*! @} */
2530 
2531 /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */
2532 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U)
2533 
2534 /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2535 /*! @{ */
2536 
2537 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U)
2538 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U)
2539 /*! CTIMER2_RULE - Standard counter/Timer 2
2540  *  0b00..Non-secure and Non-priviledge user access allowed.
2541  *  0b01..Non-secure and Privilege access allowed.
2542  *  0b10..Secure and Non-priviledge user access allowed.
2543  *  0b11..Secure and Priviledge user access allowed.
2544  */
2545 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK)
2546 
2547 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U)
2548 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U)
2549 /*! CTIMER3_RULE - Standard counter/Timer 3
2550  *  0b00..Non-secure and Non-priviledge user access allowed.
2551  *  0b01..Non-secure and Privilege access allowed.
2552  *  0b10..Secure and Non-priviledge user access allowed.
2553  *  0b11..Secure and Priviledge user access allowed.
2554  */
2555 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK)
2556 
2557 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U)
2558 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U)
2559 /*! CTIMER4_RULE - Standard counter/Timer 4
2560  *  0b00..Non-secure and Non-priviledge user access allowed.
2561  *  0b01..Non-secure and Privilege access allowed.
2562  *  0b10..Secure and Non-priviledge user access allowed.
2563  *  0b11..Secure and Priviledge user access allowed.
2564  */
2565 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK)
2566 
2567 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U)
2568 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U)
2569 /*! RTC_RULE - Real Time Counter
2570  *  0b00..Non-secure and Non-priviledge user access allowed.
2571  *  0b01..Non-secure and Privilege access allowed.
2572  *  0b10..Secure and Non-priviledge user access allowed.
2573  *  0b11..Secure and Priviledge user access allowed.
2574  */
2575 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK)
2576 
2577 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U)
2578 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U)
2579 /*! OSEVENT_RULE - OS Event Timer
2580  *  0b00..Non-secure and Non-priviledge user access allowed.
2581  *  0b01..Non-secure and Privilege access allowed.
2582  *  0b10..Secure and Non-priviledge user access allowed.
2583  *  0b11..Secure and Priviledge user access allowed.
2584  */
2585 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK)
2586 /*! @} */
2587 
2588 /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */
2589 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U)
2590 
2591 /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2592 /*! @{ */
2593 
2594 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U)
2595 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U)
2596 /*! FLASH_CTRL_RULE - Flash Controller
2597  *  0b00..Non-secure and Non-priviledge user access allowed.
2598  *  0b01..Non-secure and Privilege access allowed.
2599  *  0b10..Secure and Non-priviledge user access allowed.
2600  *  0b11..Secure and Priviledge user access allowed.
2601  */
2602 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK)
2603 
2604 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U)
2605 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U)
2606 /*! PRINCE_RULE - Prince
2607  *  0b00..Non-secure and Non-priviledge user access allowed.
2608  *  0b01..Non-secure and Privilege access allowed.
2609  *  0b10..Secure and Non-priviledge user access allowed.
2610  *  0b11..Secure and Priviledge user access allowed.
2611  */
2612 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK)
2613 /*! @} */
2614 
2615 /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */
2616 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U)
2617 
2618 /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2619 /*! @{ */
2620 
2621 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U)
2622 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U)
2623 /*! USBHPHY_RULE - USB High Speed Phy controller
2624  *  0b00..Non-secure and Non-priviledge user access allowed.
2625  *  0b01..Non-secure and Privilege access allowed.
2626  *  0b10..Secure and Non-priviledge user access allowed.
2627  *  0b11..Secure and Priviledge user access allowed.
2628  */
2629 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK)
2630 
2631 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U)
2632 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U)
2633 /*! RNG_RULE - True Random Number Generator
2634  *  0b00..Non-secure and Non-priviledge user access allowed.
2635  *  0b01..Non-secure and Privilege access allowed.
2636  *  0b10..Secure and Non-priviledge user access allowed.
2637  *  0b11..Secure and Priviledge user access allowed.
2638  */
2639 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK)
2640 
2641 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U)
2642 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U)
2643 /*! PUF_RULE - PUF
2644  *  0b00..Non-secure and Non-priviledge user access allowed.
2645  *  0b01..Non-secure and Privilege access allowed.
2646  *  0b10..Secure and Non-priviledge user access allowed.
2647  *  0b11..Secure and Priviledge user access allowed.
2648  */
2649 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK)
2650 
2651 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U)
2652 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U)
2653 /*! PLU_RULE - Programmable Look-Up logic
2654  *  0b00..Non-secure and Non-priviledge user access allowed.
2655  *  0b01..Non-secure and Privilege access allowed.
2656  *  0b10..Secure and Non-priviledge user access allowed.
2657  *  0b11..Secure and Priviledge user access allowed.
2658  */
2659 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK)
2660 /*! @} */
2661 
2662 /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */
2663 #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U)
2664 
2665 /*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */
2666 /*! @{ */
2667 
2668 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U)
2669 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U)
2670 /*! DMA0_RULE - DMA Controller
2671  *  0b00..Non-secure and Non-priviledge user access allowed.
2672  *  0b01..Non-secure and Privilege access allowed.
2673  *  0b10..Secure and Non-priviledge user access allowed.
2674  *  0b11..Secure and Priviledge user access allowed.
2675  */
2676 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK)
2677 
2678 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U)
2679 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U)
2680 /*! FS_USB_DEV_RULE - USB Full-speed device
2681  *  0b00..Non-secure and Non-priviledge user access allowed.
2682  *  0b01..Non-secure and Privilege access allowed.
2683  *  0b10..Secure and Non-priviledge user access allowed.
2684  *  0b11..Secure and Priviledge user access allowed.
2685  */
2686 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK)
2687 
2688 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U)
2689 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U)
2690 /*! SCT_RULE - SCTimer
2691  *  0b00..Non-secure and Non-priviledge user access allowed.
2692  *  0b01..Non-secure and Privilege access allowed.
2693  *  0b10..Secure and Non-priviledge user access allowed.
2694  *  0b11..Secure and Priviledge user access allowed.
2695  */
2696 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK)
2697 
2698 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U)
2699 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U)
2700 /*! FLEXCOMM0_RULE - Flexcomm interface 0
2701  *  0b00..Non-secure and Non-priviledge user access allowed.
2702  *  0b01..Non-secure and Privilege access allowed.
2703  *  0b10..Secure and Non-priviledge user access allowed.
2704  *  0b11..Secure and Priviledge user access allowed.
2705  */
2706 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK)
2707 
2708 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U)
2709 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U)
2710 /*! FLEXCOMM1_RULE - Flexcomm interface 1
2711  *  0b00..Non-secure and Non-priviledge user access allowed.
2712  *  0b01..Non-secure and Privilege access allowed.
2713  *  0b10..Secure and Non-priviledge user access allowed.
2714  *  0b11..Secure and Priviledge user access allowed.
2715  */
2716 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK)
2717 /*! @} */
2718 
2719 /*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */
2720 /*! @{ */
2721 
2722 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U)
2723 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U)
2724 /*! FLEXCOMM2_RULE - Flexcomm interface 2
2725  *  0b00..Non-secure and Non-priviledge user access allowed.
2726  *  0b01..Non-secure and Privilege access allowed.
2727  *  0b10..Secure and Non-priviledge user access allowed.
2728  *  0b11..Secure and Priviledge user access allowed.
2729  */
2730 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK)
2731 
2732 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U)
2733 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U)
2734 /*! FLEXCOMM3_RULE - Flexcomm interface 3
2735  *  0b00..Non-secure and Non-priviledge user access allowed.
2736  *  0b01..Non-secure and Privilege access allowed.
2737  *  0b10..Secure and Non-priviledge user access allowed.
2738  *  0b11..Secure and Priviledge user access allowed.
2739  */
2740 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK)
2741 
2742 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U)
2743 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U)
2744 /*! FLEXCOMM4_RULE - Flexcomm interface 4
2745  *  0b00..Non-secure and Non-priviledge user access allowed.
2746  *  0b01..Non-secure and Privilege access allowed.
2747  *  0b10..Secure and Non-priviledge user access allowed.
2748  *  0b11..Secure and Priviledge user access allowed.
2749  */
2750 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK)
2751 
2752 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U)
2753 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U)
2754 /*! MAILBOX_RULE - Inter CPU communication Mailbox
2755  *  0b00..Non-secure and Non-priviledge user access allowed.
2756  *  0b01..Non-secure and Privilege access allowed.
2757  *  0b10..Secure and Non-priviledge user access allowed.
2758  *  0b11..Secure and Priviledge user access allowed.
2759  */
2760 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK)
2761 
2762 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U)
2763 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U)
2764 /*! GPIO0_RULE - High Speed GPIO
2765  *  0b00..Non-secure and Non-priviledge user access allowed.
2766  *  0b01..Non-secure and Privilege access allowed.
2767  *  0b10..Secure and Non-priviledge user access allowed.
2768  *  0b11..Secure and Priviledge user access allowed.
2769  */
2770 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK)
2771 /*! @} */
2772 
2773 /*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */
2774 /*! @{ */
2775 
2776 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U)
2777 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U)
2778 /*! USB_HS_DEV_RULE - USB high Speed device registers
2779  *  0b00..Non-secure and Non-priviledge user access allowed.
2780  *  0b01..Non-secure and Privilege access allowed.
2781  *  0b10..Secure and Non-priviledge user access allowed.
2782  *  0b11..Secure and Priviledge user access allowed.
2783  */
2784 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK)
2785 
2786 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U)
2787 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U)
2788 /*! CRC_RULE - CRC engine
2789  *  0b00..Non-secure and Non-priviledge user access allowed.
2790  *  0b01..Non-secure and Privilege access allowed.
2791  *  0b10..Secure and Non-priviledge user access allowed.
2792  *  0b11..Secure and Priviledge user access allowed.
2793  */
2794 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK)
2795 
2796 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U)
2797 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U)
2798 /*! FLEXCOMM5_RULE - Flexcomm interface 5
2799  *  0b00..Non-secure and Non-priviledge user access allowed.
2800  *  0b01..Non-secure and Privilege access allowed.
2801  *  0b10..Secure and Non-priviledge user access allowed.
2802  *  0b11..Secure and Priviledge user access allowed.
2803  */
2804 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK)
2805 
2806 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U)
2807 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U)
2808 /*! FLEXCOMM6_RULE - Flexcomm interface 6
2809  *  0b00..Non-secure and Non-priviledge user access allowed.
2810  *  0b01..Non-secure and Privilege access allowed.
2811  *  0b10..Secure and Non-priviledge user access allowed.
2812  *  0b11..Secure and Priviledge user access allowed.
2813  */
2814 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK)
2815 /*! @} */
2816 
2817 /*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */
2818 /*! @{ */
2819 
2820 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U)
2821 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U)
2822 /*! FLEXCOMM7_RULE - Flexcomm interface 7
2823  *  0b00..Non-secure and Non-priviledge user access allowed.
2824  *  0b01..Non-secure and Privilege access allowed.
2825  *  0b10..Secure and Non-priviledge user access allowed.
2826  *  0b11..Secure and Priviledge user access allowed.
2827  */
2828 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK)
2829 
2830 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U)
2831 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U)
2832 /*! SDIO_RULE - SDMMC card interface
2833  *  0b00..Non-secure and Non-priviledge user access allowed.
2834  *  0b01..Non-secure and Privilege access allowed.
2835  *  0b10..Secure and Non-priviledge user access allowed.
2836  *  0b11..Secure and Priviledge user access allowed.
2837  */
2838 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK)
2839 
2840 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U)
2841 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U)
2842 /*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP)
2843  *  0b00..Non-secure and Non-priviledge user access allowed.
2844  *  0b01..Non-secure and Privilege access allowed.
2845  *  0b10..Secure and Non-priviledge user access allowed.
2846  *  0b11..Secure and Priviledge user access allowed.
2847  */
2848 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK)
2849 
2850 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U)
2851 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U)
2852 /*! HS_LSPI_RULE - High Speed SPI
2853  *  0b00..Non-secure and Non-priviledge user access allowed.
2854  *  0b01..Non-secure and Privilege access allowed.
2855  *  0b10..Secure and Non-priviledge user access allowed.
2856  *  0b11..Secure and Priviledge user access allowed.
2857  */
2858 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK)
2859 /*! @} */
2860 
2861 /*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */
2862 /*! @{ */
2863 
2864 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U)
2865 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U)
2866 /*! ADC_RULE - ADC
2867  *  0b00..Non-secure and Non-priviledge user access allowed.
2868  *  0b01..Non-secure and Privilege access allowed.
2869  *  0b10..Secure and Non-priviledge user access allowed.
2870  *  0b11..Secure and Priviledge user access allowed.
2871  */
2872 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK)
2873 
2874 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U)
2875 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U)
2876 /*! USB_FS_HOST_RULE - USB Full Speed Host registers.
2877  *  0b00..Non-secure and Non-priviledge user access allowed.
2878  *  0b01..Non-secure and Privilege access allowed.
2879  *  0b10..Secure and Non-priviledge user access allowed.
2880  *  0b11..Secure and Priviledge user access allowed.
2881  */
2882 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK)
2883 
2884 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U)
2885 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U)
2886 /*! USB_HS_HOST_RULE - USB High speed host registers
2887  *  0b00..Non-secure and Non-priviledge user access allowed.
2888  *  0b01..Non-secure and Privilege access allowed.
2889  *  0b10..Secure and Non-priviledge user access allowed.
2890  *  0b11..Secure and Priviledge user access allowed.
2891  */
2892 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK)
2893 
2894 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U)
2895 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U)
2896 /*! HASH_RULE - SHA-2 crypto registers
2897  *  0b00..Non-secure and Non-priviledge user access allowed.
2898  *  0b01..Non-secure and Privilege access allowed.
2899  *  0b10..Secure and Non-priviledge user access allowed.
2900  *  0b11..Secure and Priviledge user access allowed.
2901  */
2902 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK)
2903 
2904 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U)
2905 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U)
2906 /*! CASPER_RULE - RSA/ECC crypto accelerator
2907  *  0b00..Non-secure and Non-priviledge user access allowed.
2908  *  0b01..Non-secure and Privilege access allowed.
2909  *  0b10..Secure and Non-priviledge user access allowed.
2910  *  0b11..Secure and Priviledge user access allowed.
2911  */
2912 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK)
2913 
2914 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U)
2915 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U)
2916 /*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator)
2917  *  0b00..Non-secure and Non-priviledge user access allowed.
2918  *  0b01..Non-secure and Privilege access allowed.
2919  *  0b10..Secure and Non-priviledge user access allowed.
2920  *  0b11..Secure and Priviledge user access allowed.
2921  */
2922 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK)
2923 
2924 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U)
2925 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U)
2926 /*! DMA1_RULE - DMA Controller (Secure)
2927  *  0b00..Non-secure and Non-priviledge user access allowed.
2928  *  0b01..Non-secure and Privilege access allowed.
2929  *  0b10..Secure and Non-priviledge user access allowed.
2930  *  0b11..Secure and Priviledge user access allowed.
2931  */
2932 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK)
2933 /*! @} */
2934 
2935 /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */
2936 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U)
2937 
2938 /*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */
2939 /*! @{ */
2940 
2941 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U)
2942 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U)
2943 /*! GPIO1_RULE - Secure High Speed GPIO
2944  *  0b00..Non-secure and Non-priviledge user access allowed.
2945  *  0b01..Non-secure and Privilege access allowed.
2946  *  0b10..Secure and Non-priviledge user access allowed.
2947  *  0b11..Secure and Priviledge user access allowed.
2948  */
2949 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK)
2950 
2951 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U)
2952 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U)
2953 /*! AHB_SEC_CTRL_RULE - AHB Secure Controller
2954  *  0b00..Non-secure and Non-priviledge user access allowed.
2955  *  0b01..Non-secure and Privilege access allowed.
2956  *  0b10..Secure and Non-priviledge user access allowed.
2957  *  0b11..Secure and Priviledge user access allowed.
2958  */
2959 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK)
2960 /*! @} */
2961 
2962 /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */
2963 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U)
2964 
2965 /*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */
2966 /*! @{ */
2967 
2968 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U)
2969 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U)
2970 /*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF
2971  *  0b00..Non-secure and Non-priviledge user access allowed.
2972  *  0b01..Non-secure and Privilege access allowed.
2973  *  0b10..Secure and Non-priviledge user access allowed.
2974  *  0b11..Secure and Priviledge user access allowed.
2975  */
2976 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK)
2977 
2978 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U)
2979 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U)
2980 /*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF
2981  *  0b00..Non-secure and Non-priviledge user access allowed.
2982  *  0b01..Non-secure and Privilege access allowed.
2983  *  0b10..Secure and Non-priviledge user access allowed.
2984  *  0b11..Secure and Priviledge user access allowed.
2985  */
2986 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK)
2987 
2988 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U)
2989 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U)
2990 /*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF
2991  *  0b00..Non-secure and Non-priviledge user access allowed.
2992  *  0b01..Non-secure and Privilege access allowed.
2993  *  0b10..Secure and Non-priviledge user access allowed.
2994  *  0b11..Secure and Priviledge user access allowed.
2995  */
2996 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK)
2997 
2998 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U)
2999 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U)
3000 /*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF
3001  *  0b00..Non-secure and Non-priviledge user access allowed.
3002  *  0b01..Non-secure and Privilege access allowed.
3003  *  0b10..Secure and Non-priviledge user access allowed.
3004  *  0b11..Secure and Priviledge user access allowed.
3005  */
3006 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK)
3007 /*! @} */
3008 
3009 /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
3010 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U)
3011 
3012 /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
3013 #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U)
3014 
3015 /*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */
3016 /*! @{ */
3017 
3018 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U)
3019 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U)
3020 /*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF
3021  *  0b00..Non-secure and Non-priviledge user access allowed.
3022  *  0b01..Non-secure and Privilege access allowed.
3023  *  0b10..Secure and Non-priviledge user access allowed.
3024  *  0b11..Secure and Priviledge user access allowed.
3025  */
3026 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK)
3027 /*! @} */
3028 
3029 /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */
3030 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U)
3031 
3032 /*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */
3033 /*! @{ */
3034 
3035 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U)
3036 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U)
3037 /*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF
3038  *  0b00..Non-secure and Non-priviledge user access allowed.
3039  *  0b01..Non-secure and Privilege access allowed.
3040  *  0b10..Secure and Non-priviledge user access allowed.
3041  *  0b11..Secure and Priviledge user access allowed.
3042  */
3043 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK)
3044 
3045 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U)
3046 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U)
3047 /*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF
3048  *  0b00..Non-secure and Non-priviledge user access allowed.
3049  *  0b01..Non-secure and Privilege access allowed.
3050  *  0b10..Secure and Non-priviledge user access allowed.
3051  *  0b11..Secure and Priviledge user access allowed.
3052  */
3053 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK)
3054 
3055 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U)
3056 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U)
3057 /*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF
3058  *  0b00..Non-secure and Non-priviledge user access allowed.
3059  *  0b01..Non-secure and Privilege access allowed.
3060  *  0b10..Secure and Non-priviledge user access allowed.
3061  *  0b11..Secure and Priviledge user access allowed.
3062  */
3063 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK)
3064 
3065 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U)
3066 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U)
3067 /*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF
3068  *  0b00..Non-secure and Non-priviledge user access allowed.
3069  *  0b01..Non-secure and Privilege access allowed.
3070  *  0b10..Secure and Non-priviledge user access allowed.
3071  *  0b11..Secure and Priviledge user access allowed.
3072  */
3073 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK)
3074 /*! @} */
3075 
3076 /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
3077 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U)
3078 
3079 /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
3080 #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U)
3081 
3082 /*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */
3083 /*! @{ */
3084 
3085 #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU)
3086 #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U)
3087 /*! SEC_VIO_ADDR - security violation address for AHB port
3088  */
3089 #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
3090 /*! @} */
3091 
3092 /* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */
3093 #define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT       (12U)
3094 
3095 /*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */
3096 /*! @{ */
3097 
3098 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
3099 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
3100 /*! SEC_VIO_INFO_WRITE - security violation access read/write indicator.
3101  *  0b0..Read access.
3102  *  0b1..Write access.
3103  */
3104 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
3105 
3106 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
3107 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
3108 /*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator.
3109  *  0b0..Code access.
3110  *  0b1..Data access.
3111  */
3112 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
3113 
3114 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
3115 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
3116 /*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
3117  */
3118 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
3119 
3120 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)
3121 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
3122 /*! SEC_VIO_INFO_MASTER - security violation master number
3123  *  0b0000..CPU0 Code.
3124  *  0b0001..CPU0 System.
3125  *  0b0010..CPU1 Data.
3126  *  0b0011..CPU1 System.
3127  *  0b0100..USB-HS Device.
3128  *  0b0101..SDMA0.
3129  *  0b1000..SDIO.
3130  *  0b1001..PowerQuad.
3131  *  0b1010..HASH.
3132  *  0b1011..USB-FS Host.
3133  *  0b1100..SDMA1.
3134  */
3135 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
3136 /*! @} */
3137 
3138 /* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */
3139 #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT  (12U)
3140 
3141 /*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */
3142 /*! @{ */
3143 
3144 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
3145 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
3146 /*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear.
3147  *  0b0..Not valid.
3148  *  0b1..Valid (violation occurred).
3149  */
3150 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
3151 
3152 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
3153 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
3154 /*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear.
3155  *  0b0..Not valid.
3156  *  0b1..Valid (violation occurred).
3157  */
3158 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
3159 
3160 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
3161 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
3162 /*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear.
3163  *  0b0..Not valid.
3164  *  0b1..Valid (violation occurred).
3165  */
3166 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
3167 
3168 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
3169 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
3170 /*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear.
3171  *  0b0..Not valid.
3172  *  0b1..Valid (violation occurred).
3173  */
3174 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
3175 
3176 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
3177 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
3178 /*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear.
3179  *  0b0..Not valid.
3180  *  0b1..Valid (violation occurred).
3181  */
3182 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
3183 
3184 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
3185 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
3186 /*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear.
3187  *  0b0..Not valid.
3188  *  0b1..Valid (violation occurred).
3189  */
3190 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
3191 
3192 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
3193 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
3194 /*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear.
3195  *  0b0..Not valid.
3196  *  0b1..Valid (violation occurred).
3197  */
3198 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
3199 
3200 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
3201 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
3202 /*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear.
3203  *  0b0..Not valid.
3204  *  0b1..Valid (violation occurred).
3205  */
3206 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
3207 
3208 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
3209 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
3210 /*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear.
3211  *  0b0..Not valid.
3212  *  0b1..Valid (violation occurred).
3213  */
3214 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
3215 
3216 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
3217 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
3218 /*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear.
3219  *  0b0..Not valid.
3220  *  0b1..Valid (violation occurred).
3221  */
3222 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
3223 
3224 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
3225 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
3226 /*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear.
3227  *  0b0..Not valid.
3228  *  0b1..Valid (violation occurred).
3229  */
3230 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)
3231 
3232 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
3233 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
3234 /*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear.
3235  *  0b0..Not valid.
3236  *  0b1..Valid (violation occurred).
3237  */
3238 #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)
3239 /*! @} */
3240 
3241 /*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */
3242 /*! @{ */
3243 
3244 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U)
3245 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U)
3246 /*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0
3247  *  0b1..Pin state is readable by non-secure world.
3248  *  0b0..Pin state is blocked to non-secure world.
3249  */
3250 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)
3251 
3252 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U)
3253 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U)
3254 /*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1
3255  *  0b1..Pin state is readable by non-secure world.
3256  *  0b0..Pin state is blocked to non-secure world.
3257  */
3258 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)
3259 
3260 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U)
3261 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U)
3262 /*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2
3263  *  0b1..Pin state is readable by non-secure world.
3264  *  0b0..Pin state is blocked to non-secure world.
3265  */
3266 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)
3267 
3268 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U)
3269 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U)
3270 /*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3
3271  *  0b1..Pin state is readable by non-secure world.
3272  *  0b0..Pin state is blocked to non-secure world.
3273  */
3274 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)
3275 
3276 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U)
3277 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U)
3278 /*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4
3279  *  0b1..Pin state is readable by non-secure world.
3280  *  0b0..Pin state is blocked to non-secure world.
3281  */
3282 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)
3283 
3284 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U)
3285 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U)
3286 /*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5
3287  *  0b1..Pin state is readable by non-secure world.
3288  *  0b0..Pin state is blocked to non-secure world.
3289  */
3290 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)
3291 
3292 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U)
3293 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U)
3294 /*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6
3295  *  0b1..Pin state is readable by non-secure world.
3296  *  0b0..Pin state is blocked to non-secure world.
3297  */
3298 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)
3299 
3300 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U)
3301 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U)
3302 /*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7
3303  *  0b1..Pin state is readable by non-secure world.
3304  *  0b0..Pin state is blocked to non-secure world.
3305  */
3306 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)
3307 
3308 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U)
3309 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U)
3310 /*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8
3311  *  0b1..Pin state is readable by non-secure world.
3312  *  0b0..Pin state is blocked to non-secure world.
3313  */
3314 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)
3315 
3316 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U)
3317 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U)
3318 /*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9
3319  *  0b1..Pin state is readable by non-secure world.
3320  *  0b0..Pin state is blocked to non-secure world.
3321  */
3322 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)
3323 
3324 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U)
3325 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U)
3326 /*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10
3327  *  0b1..Pin state is readable by non-secure world.
3328  *  0b0..Pin state is blocked to non-secure world.
3329  */
3330 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)
3331 
3332 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U)
3333 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U)
3334 /*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11
3335  *  0b1..Pin state is readable by non-secure world.
3336  *  0b0..Pin state is blocked to non-secure world.
3337  */
3338 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)
3339 
3340 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
3341 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U)
3342 /*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12
3343  *  0b1..Pin state is readable by non-secure world.
3344  *  0b0..Pin state is blocked to non-secure world.
3345  */
3346 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)
3347 
3348 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
3349 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U)
3350 /*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13
3351  *  0b1..Pin state is readable by non-secure world.
3352  *  0b0..Pin state is blocked to non-secure world.
3353  */
3354 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)
3355 
3356 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
3357 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U)
3358 /*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14
3359  *  0b1..Pin state is readable by non-secure world.
3360  *  0b0..Pin state is blocked to non-secure world.
3361  */
3362 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)
3363 
3364 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
3365 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U)
3366 /*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15
3367  *  0b1..Pin state is readable by non-secure world.
3368  *  0b0..Pin state is blocked to non-secure world.
3369  */
3370 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)
3371 
3372 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
3373 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U)
3374 /*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16
3375  *  0b1..Pin state is readable by non-secure world.
3376  *  0b0..Pin state is blocked to non-secure world.
3377  */
3378 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)
3379 
3380 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
3381 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U)
3382 /*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17
3383  *  0b1..Pin state is readable by non-secure world.
3384  *  0b0..Pin state is blocked to non-secure world.
3385  */
3386 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)
3387 
3388 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
3389 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U)
3390 /*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18
3391  *  0b1..Pin state is readable by non-secure world.
3392  *  0b0..Pin state is blocked to non-secure world.
3393  */
3394 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)
3395 
3396 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
3397 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U)
3398 /*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19
3399  *  0b1..Pin state is readable by non-secure world.
3400  *  0b0..Pin state is blocked to non-secure world.
3401  */
3402 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)
3403 
3404 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
3405 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U)
3406 /*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20
3407  *  0b1..Pin state is readable by non-secure world.
3408  *  0b0..Pin state is blocked to non-secure world.
3409  */
3410 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)
3411 
3412 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
3413 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U)
3414 /*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21
3415  *  0b1..Pin state is readable by non-secure world.
3416  *  0b0..Pin state is blocked to non-secure world.
3417  */
3418 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)
3419 
3420 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
3421 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U)
3422 /*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22
3423  *  0b1..Pin state is readable by non-secure world.
3424  *  0b0..Pin state is blocked to non-secure world.
3425  */
3426 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)
3427 
3428 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
3429 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U)
3430 /*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23
3431  *  0b1..Pin state is readable by non-secure world.
3432  *  0b0..Pin state is blocked to non-secure world.
3433  */
3434 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)
3435 
3436 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
3437 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U)
3438 /*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24
3439  *  0b1..Pin state is readable by non-secure world.
3440  *  0b0..Pin state is blocked to non-secure world.
3441  */
3442 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)
3443 
3444 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
3445 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U)
3446 /*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25
3447  *  0b1..Pin state is readable by non-secure world.
3448  *  0b0..Pin state is blocked to non-secure world.
3449  */
3450 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)
3451 
3452 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
3453 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U)
3454 /*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26
3455  *  0b1..Pin state is readable by non-secure world.
3456  *  0b0..Pin state is blocked to non-secure world.
3457  */
3458 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)
3459 
3460 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
3461 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U)
3462 /*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27
3463  *  0b1..Pin state is readable by non-secure world.
3464  *  0b0..Pin state is blocked to non-secure world.
3465  */
3466 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)
3467 
3468 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
3469 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U)
3470 /*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28
3471  *  0b1..Pin state is readable by non-secure world.
3472  *  0b0..Pin state is blocked to non-secure world.
3473  */
3474 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)
3475 
3476 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
3477 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U)
3478 /*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29
3479  *  0b1..Pin state is readable by non-secure world.
3480  *  0b0..Pin state is blocked to non-secure world.
3481  */
3482 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)
3483 
3484 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
3485 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U)
3486 /*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30
3487  *  0b1..Pin state is readable by non-secure world.
3488  *  0b0..Pin state is blocked to non-secure world.
3489  */
3490 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)
3491 
3492 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
3493 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U)
3494 /*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31
3495  *  0b1..Pin state is readable by non-secure world.
3496  *  0b0..Pin state is blocked to non-secure world.
3497  */
3498 #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)
3499 /*! @} */
3500 
3501 /*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */
3502 /*! @{ */
3503 
3504 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U)
3505 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U)
3506 /*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0
3507  *  0b1..Pin state is readable by non-secure world.
3508  *  0b0..Pin state is blocked to non-secure world.
3509  */
3510 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)
3511 
3512 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U)
3513 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U)
3514 /*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1
3515  *  0b1..Pin state is readable by non-secure world.
3516  *  0b0..Pin state is blocked to non-secure world.
3517  */
3518 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)
3519 
3520 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U)
3521 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U)
3522 /*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2
3523  *  0b1..Pin state is readable by non-secure world.
3524  *  0b0..Pin state is blocked to non-secure world.
3525  */
3526 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)
3527 
3528 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U)
3529 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U)
3530 /*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3
3531  *  0b1..Pin state is readable by non-secure world.
3532  *  0b0..Pin state is blocked to non-secure world.
3533  */
3534 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)
3535 
3536 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U)
3537 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U)
3538 /*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4
3539  *  0b1..Pin state is readable by non-secure world.
3540  *  0b0..Pin state is blocked to non-secure world.
3541  */
3542 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)
3543 
3544 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U)
3545 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U)
3546 /*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5
3547  *  0b1..Pin state is readable by non-secure world.
3548  *  0b0..Pin state is blocked to non-secure world.
3549  */
3550 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)
3551 
3552 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U)
3553 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U)
3554 /*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6
3555  *  0b1..Pin state is readable by non-secure world.
3556  *  0b0..Pin state is blocked to non-secure world.
3557  */
3558 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)
3559 
3560 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U)
3561 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U)
3562 /*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7
3563  *  0b1..Pin state is readable by non-secure world.
3564  *  0b0..Pin state is blocked to non-secure world.
3565  */
3566 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)
3567 
3568 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U)
3569 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U)
3570 /*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8
3571  *  0b1..Pin state is readable by non-secure world.
3572  *  0b0..Pin state is blocked to non-secure world.
3573  */
3574 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)
3575 
3576 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U)
3577 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U)
3578 /*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9
3579  *  0b1..Pin state is readable by non-secure world.
3580  *  0b0..Pin state is blocked to non-secure world.
3581  */
3582 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)
3583 
3584 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U)
3585 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U)
3586 /*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10
3587  *  0b1..Pin state is readable by non-secure world.
3588  *  0b0..Pin state is blocked to non-secure world.
3589  */
3590 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)
3591 
3592 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U)
3593 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U)
3594 /*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11
3595  *  0b1..Pin state is readable by non-secure world.
3596  *  0b0..Pin state is blocked to non-secure world.
3597  */
3598 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)
3599 
3600 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
3601 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U)
3602 /*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12
3603  *  0b1..Pin state is readable by non-secure world.
3604  *  0b0..Pin state is blocked to non-secure world.
3605  */
3606 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)
3607 
3608 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
3609 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U)
3610 /*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13
3611  *  0b1..Pin state is readable by non-secure world.
3612  *  0b0..Pin state is blocked to non-secure world.
3613  */
3614 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)
3615 
3616 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
3617 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U)
3618 /*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14
3619  *  0b1..Pin state is readable by non-secure world.
3620  *  0b0..Pin state is blocked to non-secure world.
3621  */
3622 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)
3623 
3624 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
3625 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U)
3626 /*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15
3627  *  0b1..Pin state is readable by non-secure world.
3628  *  0b0..Pin state is blocked to non-secure world.
3629  */
3630 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)
3631 
3632 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
3633 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U)
3634 /*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16
3635  *  0b1..Pin state is readable by non-secure world.
3636  *  0b0..Pin state is blocked to non-secure world.
3637  */
3638 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)
3639 
3640 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
3641 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U)
3642 /*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17
3643  *  0b1..Pin state is readable by non-secure world.
3644  *  0b0..Pin state is blocked to non-secure world.
3645  */
3646 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)
3647 
3648 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
3649 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U)
3650 /*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18
3651  *  0b1..Pin state is readable by non-secure world.
3652  *  0b0..Pin state is blocked to non-secure world.
3653  */
3654 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)
3655 
3656 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
3657 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U)
3658 /*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19
3659  *  0b1..Pin state is readable by non-secure world.
3660  *  0b0..Pin state is blocked to non-secure world.
3661  */
3662 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)
3663 
3664 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
3665 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U)
3666 /*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20
3667  *  0b1..Pin state is readable by non-secure world.
3668  *  0b0..Pin state is blocked to non-secure world.
3669  */
3670 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)
3671 
3672 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
3673 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U)
3674 /*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21
3675  *  0b1..Pin state is readable by non-secure world.
3676  *  0b0..Pin state is blocked to non-secure world.
3677  */
3678 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)
3679 
3680 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
3681 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U)
3682 /*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22
3683  *  0b1..Pin state is readable by non-secure world.
3684  *  0b0..Pin state is blocked to non-secure world.
3685  */
3686 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)
3687 
3688 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
3689 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U)
3690 /*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23
3691  *  0b1..Pin state is readable by non-secure world.
3692  *  0b0..Pin state is blocked to non-secure world.
3693  */
3694 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)
3695 
3696 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
3697 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U)
3698 /*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24
3699  *  0b1..Pin state is readable by non-secure world.
3700  *  0b0..Pin state is blocked to non-secure world.
3701  */
3702 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)
3703 
3704 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
3705 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U)
3706 /*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25
3707  *  0b1..Pin state is readable by non-secure world.
3708  *  0b0..Pin state is blocked to non-secure world.
3709  */
3710 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)
3711 
3712 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
3713 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U)
3714 /*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26
3715  *  0b1..Pin state is readable by non-secure world.
3716  *  0b0..Pin state is blocked to non-secure world.
3717  */
3718 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)
3719 
3720 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
3721 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U)
3722 /*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27
3723  *  0b1..Pin state is readable by non-secure world.
3724  *  0b0..Pin state is blocked to non-secure world.
3725  */
3726 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)
3727 
3728 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
3729 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U)
3730 /*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28
3731  *  0b1..Pin state is readable by non-secure world.
3732  *  0b0..Pin state is blocked to non-secure world.
3733  */
3734 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)
3735 
3736 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
3737 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U)
3738 /*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29
3739  *  0b1..Pin state is readable by non-secure world.
3740  *  0b0..Pin state is blocked to non-secure world.
3741  */
3742 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)
3743 
3744 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
3745 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U)
3746 /*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30
3747  *  0b1..Pin state is readable by non-secure world.
3748  *  0b0..Pin state is blocked to non-secure world.
3749  */
3750 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)
3751 
3752 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
3753 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U)
3754 /*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31
3755  *  0b1..Pin state is readable by non-secure world.
3756  *  0b0..Pin state is blocked to non-secure world.
3757  */
3758 #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)
3759 /*! @} */
3760 
3761 /*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */
3762 /*! @{ */
3763 
3764 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U)
3765 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U)
3766 /*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts
3767  *  0b0..Interrupt is blocked to CPU1.
3768  *  0b1..Interrupt is readable by CPU1.
3769  */
3770 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK)
3771 
3772 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U)
3773 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U)
3774 /*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt.
3775  *  0b0..Interrupt is blocked to CPU1.
3776  *  0b1..Interrupt is readable by CPU1.
3777  */
3778 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK)
3779 
3780 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U)
3781 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U)
3782 /*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt.
3783  *  0b0..Interrupt is blocked to CPU1.
3784  *  0b1..Interrupt is readable by CPU1.
3785  */
3786 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK)
3787 
3788 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U)
3789 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U)
3790 /*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt.
3791  *  0b0..Interrupt is blocked to CPU1.
3792  *  0b1..Interrupt is readable by CPU1.
3793  */
3794 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK)
3795 
3796 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U)
3797 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U)
3798 /*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt.
3799  *  0b0..Interrupt is blocked to CPU1.
3800  *  0b1..Interrupt is readable by CPU1.
3801  */
3802 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK)
3803 
3804 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U)
3805 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U)
3806 /*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt.
3807  *  0b0..Interrupt is blocked to CPU1.
3808  *  0b1..Interrupt is readable by CPU1.
3809  */
3810 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK)
3811 
3812 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U)
3813 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U)
3814 /*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt.
3815  *  0b0..Interrupt is blocked to CPU1.
3816  *  0b1..Interrupt is readable by CPU1.
3817  */
3818 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK)
3819 
3820 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U)
3821 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U)
3822 /*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt.
3823  *  0b0..Interrupt is blocked to CPU1.
3824  *  0b1..Interrupt is readable by CPU1.
3825  */
3826 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK)
3827 
3828 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U)
3829 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U)
3830 /*! UTICK_IRQ - Micro Tick Timer interrupt.
3831  *  0b0..Interrupt is blocked to CPU1.
3832  *  0b1..Interrupt is readable by CPU1.
3833  */
3834 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK)
3835 
3836 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U)
3837 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U)
3838 /*! MRT_IRQ - Multi-Rate Timer interrupt.
3839  *  0b0..Interrupt is blocked to CPU1.
3840  *  0b1..Interrupt is readable by CPU1.
3841  */
3842 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK)
3843 
3844 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U)
3845 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U)
3846 /*! CTIMER0_IRQ - Standard counter/timer 0 interrupt.
3847  *  0b0..Interrupt is blocked to CPU1.
3848  *  0b1..Interrupt is readable by CPU1.
3849  */
3850 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK)
3851 
3852 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U)
3853 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U)
3854 /*! CTIMER1_IRQ - Standard counter/timer 1 interrupt.
3855  *  0b0..Interrupt is blocked to CPU1.
3856  *  0b1..Interrupt is readable by CPU1.
3857  */
3858 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK)
3859 
3860 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U)
3861 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U)
3862 /*! SCT_IRQ - SCTimer/PWM interrupt.
3863  *  0b0..Interrupt is blocked to CPU1.
3864  *  0b1..Interrupt is readable by CPU1.
3865  */
3866 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK)
3867 
3868 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U)
3869 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U)
3870 /*! CTIMER3_IRQ - Standard counter/timer 3 interrupt.
3871  *  0b0..Interrupt is blocked to CPU1.
3872  *  0b1..Interrupt is readable by CPU1.
3873  */
3874 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK)
3875 
3876 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U)
3877 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U)
3878 /*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S).
3879  *  0b0..Interrupt is blocked to CPU1.
3880  *  0b1..Interrupt is readable by CPU1.
3881  */
3882 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK)
3883 
3884 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U)
3885 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U)
3886 /*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S).
3887  *  0b0..Interrupt is blocked to CPU1.
3888  *  0b1..Interrupt is readable by CPU1.
3889  */
3890 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK)
3891 
3892 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U)
3893 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U)
3894 /*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S).
3895  *  0b0..Interrupt is blocked to CPU1.
3896  *  0b1..Interrupt is readable by CPU1.
3897  */
3898 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK)
3899 
3900 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U)
3901 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U)
3902 /*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S).
3903  *  0b0..Interrupt is blocked to CPU1.
3904  *  0b1..Interrupt is readable by CPU1.
3905  */
3906 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK)
3907 
3908 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U)
3909 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U)
3910 /*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S).
3911  *  0b0..Interrupt is blocked to CPU1.
3912  *  0b1..Interrupt is readable by CPU1.
3913  */
3914 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK)
3915 
3916 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U)
3917 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U)
3918 /*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S).
3919  *  0b0..Interrupt is blocked to CPU1.
3920  *  0b1..Interrupt is readable by CPU1.
3921  */
3922 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK)
3923 
3924 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U)
3925 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U)
3926 /*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S).
3927  *  0b0..Interrupt is blocked to CPU1.
3928  *  0b1..Interrupt is readable by CPU1.
3929  */
3930 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK)
3931 
3932 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U)
3933 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U)
3934 /*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S).
3935  *  0b0..Interrupt is blocked to CPU1.
3936  *  0b1..Interrupt is readable by CPU1.
3937  */
3938 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK)
3939 
3940 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U)
3941 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U)
3942 /*! ADC_IRQ - General Purpose ADC interrupt.
3943  *  0b0..Interrupt is blocked to CPU1.
3944  *  0b1..Interrupt is readable by CPU1.
3945  */
3946 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK)
3947 
3948 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U)
3949 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U)
3950 /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
3951  *  0b0..Interrupt is blocked to CPU1.
3952  *  0b1..Interrupt is readable by CPU1.
3953  */
3954 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK)
3955 
3956 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U)
3957 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U)
3958 /*! ACMP_IRQ - Analog Comparator interrupt.
3959  *  0b0..Interrupt is blocked to CPU1.
3960  *  0b1..Interrupt is readable by CPU1.
3961  */
3962 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK)
3963 
3964 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U)
3965 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U)
3966 /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
3967  *  0b0..Interrupt is blocked to CPU1.
3968  *  0b1..Interrupt is readable by CPU1.
3969  */
3970 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK)
3971 
3972 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U)
3973 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U)
3974 /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
3975  *  0b0..Interrupt is blocked to CPU1.
3976  *  0b1..Interrupt is readable by CPU1.
3977  */
3978 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK)
3979 
3980 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U)
3981 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U)
3982 /*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt.
3983  *  0b0..Interrupt is blocked to CPU1.
3984  *  0b1..Interrupt is readable by CPU1.
3985  */
3986 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK)
3987 
3988 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U)
3989 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U)
3990 /*! USB0_IRQ - USB Full Speed Controller interrupt.
3991  *  0b0..Interrupt is blocked to CPU1.
3992  *  0b1..Interrupt is readable by CPU1.
3993  */
3994 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK)
3995 
3996 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U)
3997 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U)
3998 /*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ
3999  *  0b0..Interrupt is blocked to CPU1.
4000  *  0b1..Interrupt is readable by CPU1.
4001  */
4002 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK)
4003 
4004 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U)
4005 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U)
4006 /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
4007  *  0b0..Interrupt is blocked to CPU1.
4008  *  0b1..Interrupt is readable by CPU1.
4009  */
4010 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK)
4011 
4012 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U)
4013 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U)
4014 /*! MAILBOX_IRQ - Mailbox interrupt.
4015  *  0b0..Interrupt is blocked to CPU1.
4016  *  0b1..Interrupt is readable by CPU1.
4017  */
4018 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK)
4019 /*! @} */
4020 
4021 /*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */
4022 /*! @{ */
4023 
4024 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U)
4025 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U)
4026 /*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt.
4027  *  0b0..Interrupt is blocked to CPU1.
4028  *  0b1..Interrupt is readable by CPU1.
4029  */
4030 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK)
4031 
4032 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U)
4033 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U)
4034 /*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt.
4035  *  0b0..Interrupt is blocked to CPU1.
4036  *  0b1..Interrupt is readable by CPU1.
4037  */
4038 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK)
4039 
4040 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U)
4041 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U)
4042 /*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt.
4043  *  0b0..Interrupt is blocked to CPU1.
4044  *  0b1..Interrupt is readable by CPU1.
4045  */
4046 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK)
4047 
4048 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U)
4049 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U)
4050 /*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt.
4051  *  0b0..Interrupt is blocked to CPU1.
4052  *  0b1..Interrupt is readable by CPU1.
4053  */
4054 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK)
4055 
4056 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U)
4057 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U)
4058 /*! CTIMER2_IRQ - Standard counter/timer 2 interrupt.
4059  *  0b0..Interrupt is blocked to CPU1.
4060  *  0b1..Interrupt is readable by CPU1.
4061  */
4062 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK)
4063 
4064 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U)
4065 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U)
4066 /*! CTIMER4_IRQ - Standard counter/timer 4 interrupt.
4067  *  0b0..Interrupt is blocked to CPU1.
4068  *  0b1..Interrupt is readable by CPU1.
4069  */
4070 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK)
4071 
4072 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U)
4073 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U)
4074 /*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts
4075  *  0b0..Interrupt is blocked to CPU1.
4076  *  0b1..Interrupt is readable by CPU1.
4077  */
4078 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK)
4079 
4080 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U)
4081 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U)
4082 /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
4083  *  0b0..Interrupt is blocked to CPU1.
4084  *  0b1..Interrupt is readable by CPU1.
4085  */
4086 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK)
4087 
4088 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U)
4089 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U)
4090 /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
4091  *  0b0..Interrupt is blocked to CPU1.
4092  *  0b1..Interrupt is readable by CPU1.
4093  */
4094 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK)
4095 
4096 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U)
4097 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U)
4098 /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
4099  *  0b0..Interrupt is blocked to CPU1.
4100  *  0b1..Interrupt is readable by CPU1.
4101  */
4102 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK)
4103 
4104 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U)
4105 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U)
4106 /*! SDIO_IRQ - SDIO Controller interrupt.
4107  *  0b0..Interrupt is blocked to CPU1.
4108  *  0b1..Interrupt is readable by CPU1.
4109  */
4110 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK)
4111 
4112 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U)
4113 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U)
4114 /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
4115  *  0b0..Interrupt is blocked to CPU1.
4116  *  0b1..Interrupt is readable by CPU1.
4117  */
4118 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK)
4119 
4120 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U)
4121 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U)
4122 /*! RESERVED4 - Reserved. Read value is undefined, only zero should be written.
4123  *  0b0..Interrupt is blocked to CPU1.
4124  *  0b1..Interrupt is readable by CPU1.
4125  */
4126 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK)
4127 
4128 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U)
4129 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U)
4130 /*! RESERVED5 - Reserved. Read value is undefined, only zero should be written.
4131  *  0b0..Interrupt is blocked to CPU1.
4132  *  0b1..Interrupt is readable by CPU1.
4133  */
4134 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK)
4135 
4136 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U)
4137 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U)
4138 /*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt.
4139  *  0b0..Interrupt is blocked to CPU1.
4140  *  0b1..Interrupt is readable by CPU1.
4141  */
4142 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK)
4143 
4144 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U)
4145 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U)
4146 /*! USB1_IRQ - USB High Speed Controller interrupt.
4147  *  0b0..Interrupt is blocked to CPU1.
4148  *  0b1..Interrupt is readable by CPU1.
4149  */
4150 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK)
4151 
4152 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U)
4153 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U)
4154 /*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt.
4155  *  0b0..Interrupt is blocked to CPU1.
4156  *  0b1..Interrupt is readable by CPU1.
4157  */
4158 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK)
4159 
4160 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U)
4161 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U)
4162 /*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt.
4163  *  0b0..Interrupt is blocked to CPU1.
4164  *  0b1..Interrupt is readable by CPU1.
4165  */
4166 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK)
4167 
4168 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U)
4169 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U)
4170 /*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt.
4171  *  0b0..Interrupt is blocked to CPU1.
4172  *  0b1..Interrupt is readable by CPU1.
4173  */
4174 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK)
4175 
4176 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U)
4177 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U)
4178 /*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt.
4179  *  0b0..Interrupt is blocked to CPU1.
4180  *  0b1..Interrupt is readable by CPU1.
4181  */
4182 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK)
4183 
4184 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U)
4185 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U)
4186 /*! PLU_IRQ - Programmable Look-Up Controller interrupt.
4187  *  0b0..Interrupt is blocked to CPU1.
4188  *  0b1..Interrupt is readable by CPU1.
4189  */
4190 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK)
4191 
4192 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U)
4193 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U)
4194 /*! SEC_VIO_IRQ - Security Violation interrupt.
4195  *  0b0..Interrupt is blocked to CPU1.
4196  *  0b1..Interrupt is readable by CPU1.
4197  */
4198 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK)
4199 
4200 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U)
4201 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U)
4202 /*! SHA_IRQ - HASH-AES interrupt.
4203  *  0b0..Interrupt is blocked to CPU1.
4204  *  0b1..Interrupt is readable by CPU1.
4205  */
4206 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK)
4207 
4208 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U)
4209 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U)
4210 /*! CASPER_IRQ - CASPER interrupt.
4211  *  0b0..Interrupt is blocked to CPU1.
4212  *  0b1..Interrupt is readable by CPU1.
4213  */
4214 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK)
4215 
4216 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U)
4217 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U)
4218 /*! PUFKEY_IRQ - PUF interrupt.
4219  *  0b0..Interrupt is blocked to CPU1.
4220  *  0b1..Interrupt is readable by CPU1.
4221  */
4222 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK)
4223 
4224 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U)
4225 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U)
4226 /*! PQ_IRQ - Power Quad interrupt.
4227  *  0b0..Interrupt is blocked to CPU1.
4228  *  0b1..Interrupt is readable by CPU1.
4229  */
4230 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK)
4231 
4232 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U)
4233 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U)
4234 /*! SDMA1_IRQ - System DMA 1 (Secure) interrupt
4235  *  0b0..Interrupt is blocked to CPU1.
4236  *  0b1..Interrupt is readable by CPU1.
4237  */
4238 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK)
4239 
4240 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U)
4241 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U)
4242 /*! LSPI_HS_IRQ - High Speed SPI interrupt
4243  *  0b0..Interrupt is blocked to CPU1.
4244  *  0b1..Interrupt is readable by CPU1.
4245  */
4246 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK)
4247 /*! @} */
4248 
4249 /*! @name SEC_MASK_LOCK - Security General Purpose register access control. */
4250 /*! @{ */
4251 
4252 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)
4253 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)
4254 /*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock.
4255  *  0b10..Writable.
4256  *  0b01..Restricted mode.
4257  */
4258 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK)
4259 
4260 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)
4261 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)
4262 /*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock.
4263  *  0b10..Writable.
4264  *  0b01..Restricted mode.
4265  */
4266 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK)
4267 
4268 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U)
4269 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U)
4270 /*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock.
4271  *  0b10..Writable.
4272  *  0b01..Restricted mode.
4273  */
4274 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK)
4275 
4276 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U)
4277 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U)
4278 /*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock.
4279  *  0b10..Writable.
4280  *  0b01..Restricted mode.
4281  */
4282 #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK)
4283 /*! @} */
4284 
4285 /*! @name MASTER_SEC_LEVEL - master secure level register */
4286 /*! @{ */
4287 
4288 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U)
4289 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U)
4290 /*! CPU1C - Micro-Cortex M33 (CPU1) Code bus.
4291  *  0b00..Non-secure and Non-priviledge user access allowed.
4292  *  0b01..Non-secure and Privilege access allowed.
4293  *  0b10..Secure and Non-priviledge user access allowed.
4294  *  0b11..Secure and Priviledge user access allowed.
4295  */
4296 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK)
4297 
4298 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U)
4299 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U)
4300 /*! CPU1S - Micro-Cortex M33 (CPU1) System bus.
4301  *  0b00..Non-secure and Non-priviledge user access allowed.
4302  *  0b01..Non-secure and Privilege access allowed.
4303  *  0b10..Secure and Non-priviledge user access allowed.
4304  *  0b11..Secure and Priviledge user access allowed.
4305  */
4306 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK)
4307 
4308 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U)
4309 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U)
4310 /*! USBFSD - USB Full Speed Device.
4311  *  0b00..Non-secure and Non-priviledge user access allowed.
4312  *  0b01..Non-secure and Privilege access allowed.
4313  *  0b10..Secure and Non-priviledge user access allowed.
4314  *  0b11..Secure and Priviledge user access allowed.
4315  */
4316 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK)
4317 
4318 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U)
4319 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U)
4320 /*! SDMA0 - System DMA 0.
4321  *  0b00..Non-secure and Non-priviledge user access allowed.
4322  *  0b01..Non-secure and Privilege access allowed.
4323  *  0b10..Secure and Non-priviledge user access allowed.
4324  *  0b11..Secure and Priviledge user access allowed.
4325  */
4326 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK)
4327 
4328 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U)
4329 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U)
4330 /*! SDIO - SDIO.
4331  *  0b00..Non-secure and Non-priviledge user access allowed.
4332  *  0b01..Non-secure and Privilege access allowed.
4333  *  0b10..Secure and Non-priviledge user access allowed.
4334  *  0b11..Secure and Priviledge user access allowed.
4335  */
4336 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK)
4337 
4338 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U)
4339 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U)
4340 /*! PQ - Power Quad.
4341  *  0b00..Non-secure and Non-priviledge user access allowed.
4342  *  0b01..Non-secure and Privilege access allowed.
4343  *  0b10..Secure and Non-priviledge user access allowed.
4344  *  0b11..Secure and Priviledge user access allowed.
4345  */
4346 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x)   (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK)
4347 
4348 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U)
4349 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U)
4350 /*! HASH - Hash.
4351  *  0b00..Non-secure and Non-priviledge user access allowed.
4352  *  0b01..Non-secure and Privilege access allowed.
4353  *  0b10..Secure and Non-priviledge user access allowed.
4354  *  0b11..Secure and Priviledge user access allowed.
4355  */
4356 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK)
4357 
4358 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U)
4359 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U)
4360 /*! USBFSH - USB Full speed Host.
4361  *  0b00..Non-secure and Non-priviledge user access allowed.
4362  *  0b01..Non-secure and Privilege access allowed.
4363  *  0b10..Secure and Non-priviledge user access allowed.
4364  *  0b11..Secure and Priviledge user access allowed.
4365  */
4366 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK)
4367 
4368 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U)
4369 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U)
4370 /*! SDMA1 - System DMA 1 security level.
4371  *  0b00..Non-secure and Non-priviledge user access allowed.
4372  *  0b01..Non-secure and Privilege access allowed.
4373  *  0b10..Secure and Non-priviledge user access allowed.
4374  *  0b11..Secure and Priviledge user access allowed.
4375  */
4376 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK)
4377 
4378 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
4379 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
4380 /*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock.
4381  *  0b10..Writable.
4382  *  0b01..Restricted mode.
4383  */
4384 #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
4385 /*! @} */
4386 
4387 /*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */
4388 /*! @{ */
4389 
4390 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U)
4391 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U)
4392 /*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C)
4393  *  0b11..Non-secure and Non-priviledge user access allowed.
4394  *  0b10..Non-secure and Privilege access allowed.
4395  *  0b01..Secure and Non-priviledge user access allowed.
4396  *  0b00..Secure and Priviledge user access allowed.
4397  */
4398 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK)
4399 
4400 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U)
4401 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U)
4402 /*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S)
4403  *  0b11..Non-secure and Non-priviledge user access allowed.
4404  *  0b10..Non-secure and Privilege access allowed.
4405  *  0b01..Secure and Non-priviledge user access allowed.
4406  *  0b00..Secure and Priviledge user access allowed.
4407  */
4408 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK)
4409 
4410 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U)
4411 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U)
4412 /*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD)
4413  *  0b11..Non-secure and Non-priviledge user access allowed.
4414  *  0b10..Non-secure and Privilege access allowed.
4415  *  0b01..Secure and Non-priviledge user access allowed.
4416  *  0b00..Secure and Priviledge user access allowed.
4417  */
4418 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK)
4419 
4420 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U)
4421 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U)
4422 /*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0)
4423  *  0b11..Non-secure and Non-priviledge user access allowed.
4424  *  0b10..Non-secure and Privilege access allowed.
4425  *  0b01..Secure and Non-priviledge user access allowed.
4426  *  0b00..Secure and Priviledge user access allowed.
4427  */
4428 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK)
4429 
4430 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U)
4431 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U)
4432 /*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO)
4433  *  0b11..Non-secure and Non-priviledge user access allowed.
4434  *  0b10..Non-secure and Privilege access allowed.
4435  *  0b01..Secure and Non-priviledge user access allowed.
4436  *  0b00..Secure and Priviledge user access allowed.
4437  */
4438 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK)
4439 
4440 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U)
4441 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U)
4442 /*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ)
4443  *  0b11..Non-secure and Non-priviledge user access allowed.
4444  *  0b10..Non-secure and Privilege access allowed.
4445  *  0b01..Secure and Non-priviledge user access allowed.
4446  *  0b00..Secure and Priviledge user access allowed.
4447  */
4448 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK)
4449 
4450 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U)
4451 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U)
4452 /*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH)
4453  *  0b11..Non-secure and Non-priviledge user access allowed.
4454  *  0b10..Non-secure and Privilege access allowed.
4455  *  0b01..Secure and Non-priviledge user access allowed.
4456  *  0b00..Secure and Priviledge user access allowed.
4457  */
4458 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK)
4459 
4460 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U)
4461 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U)
4462 /*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH)
4463  *  0b11..Non-secure and Non-priviledge user access allowed.
4464  *  0b10..Non-secure and Privilege access allowed.
4465  *  0b01..Secure and Non-priviledge user access allowed.
4466  *  0b00..Secure and Priviledge user access allowed.
4467  */
4468 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK)
4469 
4470 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U)
4471 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U)
4472 /*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1)
4473  *  0b11..Non-secure and Non-priviledge user access allowed.
4474  *  0b10..Non-secure and Privilege access allowed.
4475  *  0b01..Secure and Non-priviledge user access allowed.
4476  *  0b00..Secure and Priviledge user access allowed.
4477  */
4478 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK)
4479 
4480 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
4481 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
4482 /*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock.
4483  *  0b10..Writable.
4484  *  0b01..Restricted mode.
4485  */
4486 #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
4487 /*! @} */
4488 
4489 /*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */
4490 /*! @{ */
4491 
4492 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
4493 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
4494 /*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock.
4495  *  0b10..Writable.
4496  *  0b01..Restricted mode.
4497  */
4498 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK)
4499 
4500 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
4501 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
4502 /*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock.
4503  *  0b10..Writable.
4504  *  0b01..Restricted mode.
4505  */
4506 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK)
4507 
4508 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
4509 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
4510 /*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock.
4511  *  0b10..Writable.
4512  *  0b01..Restricted mode.
4513  */
4514 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK)
4515 
4516 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)
4517 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U)
4518 /*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock.
4519  *  0b10..Writable.
4520  *  0b01..Restricted mode.
4521  */
4522 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK)
4523 
4524 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U)
4525 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U)
4526 /*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock.
4527  *  0b10..Writable.
4528  *  0b01..Restricted mode.
4529  */
4530 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK)
4531 
4532 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U)
4533 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U)
4534 /*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock.
4535  *  0b10..Writable.
4536  *  0b01..Restricted mode.
4537  */
4538 #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK)
4539 /*! @} */
4540 
4541 /*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */
4542 /*! @{ */
4543 
4544 #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
4545 #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
4546 /*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock.
4547  *  0b10..Writable.
4548  *  0b01..Restricted mode.
4549  */
4550 #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK)
4551 
4552 #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
4553 #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
4554 /*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock.
4555  *  0b10..Writable.
4556  *  0b01..Restricted mode.
4557  */
4558 #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK)
4559 
4560 #define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U)
4561 #define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U)
4562 /*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock.
4563  *  0b10..Writable.
4564  *  0b01..Restricted mode.
4565  */
4566 #define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK)
4567 /*! @} */
4568 
4569 /*! @name MISC_CTRL_DP_REG - secure control duplicate register */
4570 /*! @{ */
4571 
4572 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U)
4573 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
4574 /*! WRITE_LOCK - Write lock.
4575  *  0b10..Secure control registers can be written.
4576  *  0b01..Restricted mode.
4577  */
4578 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
4579 
4580 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
4581 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
4582 /*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
4583  *  0b10..Disable check.
4584  *  0b01..Restricted mode.
4585  */
4586 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
4587 
4588 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
4589 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
4590 /*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
4591  *  0b10..Disable check.
4592  *  0b01..Restricted mode.
4593  */
4594 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
4595 
4596 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
4597 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
4598 /*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
4599  *  0b10..Disable check.
4600  *  0b01..Restricted mode.
4601  */
4602 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
4603 
4604 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
4605 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
4606 /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
4607  *  0b10..Enable abort fort secure checker.
4608  *  0b01..Disable abort fort secure checker.
4609  */
4610 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
4611 
4612 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
4613 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
4614 /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
4615  *  0b10..Simple master in strict mode.
4616  *  0b01..Simple master in tier mode.
4617  */
4618 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
4619 
4620 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
4621 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
4622 /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
4623  *  0b10..Smart master in strict mode.
4624  *  0b01..Smart master in tier mode.
4625  */
4626 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
4627 
4628 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
4629 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
4630 /*! IDAU_ALL_NS - Disable IDAU.
4631  *  0b10..IDAU is enabled.
4632  *  0b01..IDAU is disable.
4633  */
4634 #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
4635 /*! @} */
4636 
4637 /*! @name MISC_CTRL_REG - secure control register */
4638 /*! @{ */
4639 
4640 #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U)
4641 #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U)
4642 /*! WRITE_LOCK - Write lock.
4643  *  0b10..Secure control registers can be written.
4644  *  0b01..Restricted mode.
4645  */
4646 #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)
4647 
4648 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
4649 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
4650 /*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
4651  *  0b10..Disable check.
4652  *  0b01..Enabled (restricted mode)
4653  */
4654 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
4655 
4656 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
4657 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
4658 /*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
4659  *  0b10..Disable check.
4660  *  0b01..Enabled (restricted mode)
4661  */
4662 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
4663 
4664 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
4665 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
4666 /*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
4667  *  0b10..Disable check.
4668  *  0b01..Enabled (restricted mode)
4669  */
4670 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
4671 
4672 #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
4673 #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
4674 /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
4675  *  0b10..Enable abort fort secure checker.
4676  *  0b01..Disable abort fort secure checker.
4677  */
4678 #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
4679 
4680 #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
4681 #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
4682 /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
4683  *  0b10..Simple master in strict mode.
4684  *  0b01..Simple master in tier mode.
4685  */
4686 #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
4687 
4688 #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
4689 #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
4690 /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
4691  *  0b10..Smart master in strict mode.
4692  *  0b01..Smart master in tier mode.
4693  */
4694 #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
4695 
4696 #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U)
4697 #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U)
4698 /*! IDAU_ALL_NS - Disable IDAU.
4699  *  0b10..IDAU is enabled.
4700  *  0b01..IDAU is disable.
4701  */
4702 #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
4703 /*! @} */
4704 
4705 
4706 /*!
4707  * @}
4708  */ /* end of group AHB_SECURE_CTRL_Register_Masks */
4709 
4710 
4711 /* AHB_SECURE_CTRL - Peripheral instance base addresses */
4712 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
4713   /** Peripheral AHB_SECURE_CTRL base address */
4714   #define AHB_SECURE_CTRL_BASE                     (0x500AC000u)
4715   /** Peripheral AHB_SECURE_CTRL base address */
4716   #define AHB_SECURE_CTRL_BASE_NS                  (0x400AC000u)
4717   /** Peripheral AHB_SECURE_CTRL base pointer */
4718   #define AHB_SECURE_CTRL                          ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
4719   /** Peripheral AHB_SECURE_CTRL base pointer */
4720   #define AHB_SECURE_CTRL_NS                       ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)
4721   /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4722   #define AHB_SECURE_CTRL_BASE_ADDRS               { AHB_SECURE_CTRL_BASE }
4723   /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4724   #define AHB_SECURE_CTRL_BASE_PTRS                { AHB_SECURE_CTRL }
4725   /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4726   #define AHB_SECURE_CTRL_BASE_ADDRS_NS            { AHB_SECURE_CTRL_BASE_NS }
4727   /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4728   #define AHB_SECURE_CTRL_BASE_PTRS_NS             { AHB_SECURE_CTRL_NS }
4729 #else
4730   /** Peripheral AHB_SECURE_CTRL base address */
4731   #define AHB_SECURE_CTRL_BASE                     (0x400AC000u)
4732   /** Peripheral AHB_SECURE_CTRL base pointer */
4733   #define AHB_SECURE_CTRL                          ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
4734   /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4735   #define AHB_SECURE_CTRL_BASE_ADDRS               { AHB_SECURE_CTRL_BASE }
4736   /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4737   #define AHB_SECURE_CTRL_BASE_PTRS                { AHB_SECURE_CTRL }
4738 #endif
4739 /* AHB_SECURE_CTRL Mirror address */
4740 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
4741   /** Peripheral AHB_SECURE_CTRL base address */
4742   #define AHB_SECURE_CTRL_ALIAS1_BASE              (0x500AD000u)
4743   /** Peripheral AHB_SECURE_CTRL base address */
4744   #define AHB_SECURE_CTRL_ALIAS1_BASE_NS           (0x400AD000u)
4745   /** Peripheral AHB_SECURE_CTRL base pointer */
4746   #define AHB_SECURE_CTRL_ALIAS1                   ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE)
4747   /** Peripheral AHB_SECURE_CTRL base pointer */
4748   #define AHB_SECURE_CTRL_ALIAS1_NS                ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE_NS)
4749   /** Peripheral AHB_SECURE_CTRL base address */
4750   #define AHB_SECURE_CTRL_ALIAS2_BASE              (0x500AE000u)
4751   /** Peripheral AHB_SECURE_CTRL base address */
4752   #define AHB_SECURE_CTRL_ALIAS2_BASE_NS           (0x400AE000u)
4753   /** Peripheral AHB_SECURE_CTRL base pointer */
4754   #define AHB_SECURE_CTRL_ALIAS2                   ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE)
4755   /** Peripheral AHB_SECURE_CTRL base pointer */
4756   #define AHB_SECURE_CTRL_ALIAS2_NS                ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE_NS)
4757   /** Peripheral AHB_SECURE_CTRL base address */
4758   #define AHB_SECURE_CTRL_ALIAS3_BASE              (0x500AF000u)
4759   /** Peripheral AHB_SECURE_CTRL base address */
4760   #define AHB_SECURE_CTRL_ALIAS3_BASE_NS           (0x400AF000u)
4761   /** Peripheral AHB_SECURE_CTRL base pointer */
4762   #define AHB_SECURE_CTRL_ALIAS3                   ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE)
4763   /** Peripheral AHB_SECURE_CTRL base pointer */
4764   #define AHB_SECURE_CTRL_ALIAS3_NS                ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE_NS)
4765 #else
4766   /** Peripheral AHB_SECURE_CTRL base address */
4767   #define AHB_SECURE_CTRL_ALIAS1_BASE              (0x400AD000u)
4768   /** Peripheral AHB_SECURE_CTRL base pointer */
4769   #define AHB_SECURE_CTRL_ALIAS1                   ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE)
4770   /** Peripheral AHB_SECURE_CTRL base address */
4771   #define AHB_SECURE_CTRL_ALIAS2_BASE              (0x400AE000u)
4772   /** Peripheral AHB_SECURE_CTRL base pointer */
4773   #define AHB_SECURE_CTRL_ALIAS2                   ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE)
4774   /** Peripheral AHB_SECURE_CTRL base address */
4775   #define AHB_SECURE_CTRL_ALIAS3_BASE              (0x400AF000u)
4776   /** Peripheral AHB_SECURE_CTRL base pointer */
4777   #define AHB_SECURE_CTRL_ALIAS3                   ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE)
4778  #endif
4779 
4780 
4781 /*!
4782  * @}
4783  */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */
4784 
4785 
4786 /* ----------------------------------------------------------------------------
4787    -- ANACTRL Peripheral Access Layer
4788    ---------------------------------------------------------------------------- */
4789 
4790 /*!
4791  * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer
4792  * @{
4793  */
4794 
4795 /** ANACTRL - Register Layout Typedef */
4796 typedef struct {
4797   __IO uint32_t ANALOG_CTRL_CFG;                   /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */
4798   __I  uint32_t ANALOG_CTRL_STATUS;                /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */
4799        uint8_t RESERVED_0[4];
4800   __IO uint32_t FREQ_ME_CTRL;                      /**< Frequency Measure function control register, offset: 0xC */
4801   __IO uint32_t FRO192M_CTRL;                      /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */
4802   __I  uint32_t FRO192M_STATUS;                    /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */
4803   __IO uint32_t ADC_CTRL;                          /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */
4804        uint8_t RESERVED_1[4];
4805   __IO uint32_t XO32M_CTRL;                        /**< High speed Crystal Oscillator Control register, offset: 0x20 */
4806   __I  uint32_t XO32M_STATUS;                      /**< High speed Crystal Oscillator Status register, offset: 0x24 */
4807        uint8_t RESERVED_2[8];
4808   __IO uint32_t BOD_DCDC_INT_CTRL;                 /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */
4809   __I  uint32_t BOD_DCDC_INT_STATUS;               /**< BoDs & DCDC interrupts status register, offset: 0x34 */
4810        uint8_t RESERVED_3[8];
4811   __IO uint32_t RINGO0_CTRL;                       /**< First Ring Oscillator module control register., offset: 0x40 */
4812   __IO uint32_t RINGO1_CTRL;                       /**< Second Ring Oscillator module control register., offset: 0x44 */
4813   __IO uint32_t RINGO2_CTRL;                       /**< Third Ring Oscillator module control register., offset: 0x48 */
4814        uint8_t RESERVED_4[100];
4815   __IO uint32_t LDO_XO32M;                         /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */
4816   __IO uint32_t AUX_BIAS;                          /**< AUX_BIAS, offset: 0xB4 */
4817        uint8_t RESERVED_5[72];
4818   __IO uint32_t USBHS_PHY_CTRL;                    /**< USB High Speed Phy Control, offset: 0x100 */
4819   __IO uint32_t USBHS_PHY_TRIM;                    /**< USB High Speed Phy Trim values, offset: 0x104 */
4820 } ANACTRL_Type;
4821 
4822 /* ----------------------------------------------------------------------------
4823    -- ANACTRL Register Masks
4824    ---------------------------------------------------------------------------- */
4825 
4826 /*!
4827  * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks
4828  * @{
4829  */
4830 
4831 /*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */
4832 /*! @{ */
4833 
4834 #define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U)
4835 #define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U)
4836 /*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source.
4837  *  0b0..FRO192M trimming and 'Enable' comes from eFUSE.
4838  *  0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers.
4839  */
4840 #define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK)
4841 /*! @} */
4842 
4843 /*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */
4844 /*! @{ */
4845 
4846 #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U)
4847 #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U)
4848 /*! FLASH_PWRDWN - Flash Power Down status.
4849  *  0b0..Flash is not in power down mode.
4850  *  0b1..Flash is in power down mode.
4851  */
4852 #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK)
4853 
4854 #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U)
4855 #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U)
4856 /*! FLASH_INIT_ERROR - Flash initialization error status.
4857  *  0b0..No error.
4858  *  0b1..At least one error occured during flash initialization..
4859  */
4860 #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK)
4861 /*! @} */
4862 
4863 /*! @name FREQ_ME_CTRL - Frequency Measure function control register */
4864 /*! @{ */
4865 
4866 #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK   (0x7FFFFFFFU)
4867 #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT  (0U)
4868 /*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale
4869  */
4870 #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x)     (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK)
4871 
4872 #define ANACTRL_FREQ_ME_CTRL_PROG_MASK           (0x80000000U)
4873 #define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT          (31U)
4874 /*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit
4875  *    when the measurement cycle has completed and there is valid capture data in the CAPVAL field
4876  *    (bits 30:0).
4877  */
4878 #define ANACTRL_FREQ_ME_CTRL_PROG(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK)
4879 /*! @} */
4880 
4881 /*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */
4882 /*! @{ */
4883 
4884 #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK   (0x4000U)
4885 #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT  (14U)
4886 /*! ENA_12MHZCLK - 12 MHz clock control.
4887  *  0b0..12 MHz clock is disabled.
4888  *  0b1..12 MHz clock is enabled.
4889  */
4890 #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x)     (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK)
4891 
4892 #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK   (0x8000U)
4893 #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT  (15U)
4894 /*! ENA_48MHZCLK - 48 MHz clock control.
4895  *  0b0..Reserved.
4896  *  0b1..48 MHz clock is enabled.
4897  */
4898 #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x)     (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK)
4899 
4900 #define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK       (0xFF0000U)
4901 #define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT      (16U)
4902 /*! DAC_TRIM - Frequency trim.
4903  */
4904 #define ANACTRL_FRO192M_CTRL_DAC_TRIM(x)         (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK)
4905 
4906 #define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK      (0x1000000U)
4907 #define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT     (24U)
4908 /*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode,
4909  *    the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF
4910  *    packets.
4911  */
4912 #define ANACTRL_FRO192M_CTRL_USBCLKADJ(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK)
4913 
4914 #define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK      (0x2000000U)
4915 #define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT     (25U)
4916 /*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0.
4917  */
4918 #define ANACTRL_FRO192M_CTRL_USBMODCHG(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK)
4919 
4920 #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK   (0x40000000U)
4921 #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT  (30U)
4922 /*! ENA_96MHZCLK - 96 MHz clock control.
4923  *  0b0..96 MHz clock is disabled.
4924  *  0b1..96 MHz clock is enabled.
4925  */
4926 #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x)     (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK)
4927 
4928 #define ANACTRL_FRO192M_CTRL_WRTRIM_MASK         (0x80000000U)
4929 #define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT        (31U)
4930 /*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields.
4931  */
4932 #define ANACTRL_FRO192M_CTRL_WRTRIM(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK)
4933 /*! @} */
4934 
4935 /*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */
4936 /*! @{ */
4937 
4938 #define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK    (0x1U)
4939 #define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT   (0U)
4940 /*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled.
4941  *  0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available).
4942  *  0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by
4943  *       FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK).
4944  */
4945 #define ANACTRL_FRO192M_STATUS_CLK_VALID(x)      (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK)
4946 
4947 #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK    (0x2U)
4948 #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT   (1U)
4949 /*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses
4950  *    the threshold voltage of a SLVT transistor, this output signal will go high. It is also
4951  *    possible to observe the clk_valid signal.
4952  */
4953 #define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x)      (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK)
4954 /*! @} */
4955 
4956 /*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */
4957 /*! @{ */
4958 
4959 #define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK      (0x1U)
4960 #define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT     (0U)
4961 /*! VBATDIVENABLE - Switch On/Off VBAT divider branch.
4962  *  0b0..VBAT divider branch is disabled.
4963  *  0b1..VBAT divider branch is enabled.
4964  */
4965 #define ANACTRL_ADC_CTRL_VBATDIVENABLE(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK)
4966 /*! @} */
4967 
4968 /*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */
4969 /*! @{ */
4970 
4971 #define ANACTRL_XO32M_CTRL_SLAVE_MASK            (0x10U)
4972 #define ANACTRL_XO32M_CTRL_SLAVE_SHIFT           (4U)
4973 /*! SLAVE - Xo in slave mode.
4974  */
4975 #define ANACTRL_XO32M_CTRL_SLAVE(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK)
4976 
4977 #define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK       (0x7F00U)
4978 #define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT      (8U)
4979 /*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin
4980  */
4981 #define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x)         (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK)
4982 
4983 #define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK      (0x3F8000U)
4984 #define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT     (15U)
4985 /*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin
4986  */
4987 #define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK)
4988 
4989 #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U)
4990 #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U)
4991 /*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level.
4992  *  0b0..XO AC buffer bypass is disabled.
4993  *  0b1..XO AC buffer bypass is enabled.
4994  */
4995 #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK)
4996 
4997 #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U)
4998 #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U)
4999 /*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL.
5000  *  0b0..High speed Crystal oscillator output to USB HS PLL is disabled.
5001  *  0b1..High speed Crystal oscillator output to USB HS PLL is enabled.
5002  */
5003 #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK)
5004 
5005 #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U)
5006 #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U)
5007 /*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system.
5008  *  0b0..High speed Crystal oscillator output to CPU system is disabled.
5009  *  0b1..High speed Crystal oscillator output to CPU system is enabled.
5010  */
5011 #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK)
5012 /*! @} */
5013 
5014 /*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */
5015 /*! @{ */
5016 
5017 #define ANACTRL_XO32M_STATUS_XO_READY_MASK       (0x1U)
5018 #define ANACTRL_XO32M_STATUS_XO_READY_SHIFT      (0U)
5019 /*! XO_READY - Indicates XO out frequency statibilty.
5020  *  0b0..XO output frequency is not yet stable.
5021  *  0b1..XO output frequency is stable.
5022  */
5023 #define ANACTRL_XO32M_STATUS_XO_READY(x)         (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK)
5024 /*! @} */
5025 
5026 /*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */
5027 /*! @{ */
5028 
5029 #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U)
5030 #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U)
5031 /*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control.
5032  *  0b0..BOD VBAT interrupt is disabled.
5033  *  0b1..BOD VBAT interrupt is enabled.
5034  */
5035 #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK)
5036 
5037 #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U)
5038 #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U)
5039 /*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit.
5040  */
5041 #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK)
5042 
5043 #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U)
5044 #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U)
5045 /*! BODCORE_INT_ENABLE - BOD CORE interrupt control.
5046  *  0b0..BOD CORE interrupt is disabled.
5047  *  0b1..BOD CORE interrupt is enabled.
5048  */
5049 #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK)
5050 
5051 #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U)
5052 #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U)
5053 /*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit.
5054  */
5055 #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK)
5056 
5057 #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U)
5058 #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U)
5059 /*! DCDC_INT_ENABLE - DCDC interrupt control.
5060  *  0b0..DCDC interrupt is disabled.
5061  *  0b1..DCDC interrupt is enabled.
5062  */
5063 #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK)
5064 
5065 #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U)
5066 #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U)
5067 /*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit.
5068  */
5069 #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK)
5070 /*! @} */
5071 
5072 /*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */
5073 /*! @{ */
5074 
5075 #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U)
5076 #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U)
5077 /*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable.
5078  *  0b0..No interrupt pending..
5079  *  0b1..Interrupt pending..
5080  */
5081 #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK)
5082 
5083 #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U)
5084 #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U)
5085 /*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable.
5086  *  0b0..No interrupt pending..
5087  *  0b1..Interrupt pending..
5088  */
5089 #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK)
5090 
5091 #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U)
5092 #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U)
5093 /*! BODVBAT_VAL - Current value of BOD VBAT power status output.
5094  *  0b0..VBAT voltage level is below the threshold.
5095  *  0b1..VBAT voltage level is above the threshold.
5096  */
5097 #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK)
5098 
5099 #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U)
5100 #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U)
5101 /*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable.
5102  *  0b0..No interrupt pending..
5103  *  0b1..Interrupt pending..
5104  */
5105 #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK)
5106 
5107 #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U)
5108 #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U)
5109 /*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable.
5110  *  0b0..No interrupt pending..
5111  *  0b1..Interrupt pending..
5112  */
5113 #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK)
5114 
5115 #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U)
5116 #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U)
5117 /*! BODCORE_VAL - Current value of BOD CORE power status output.
5118  *  0b0..CORE voltage level is below the threshold.
5119  *  0b1..CORE voltage level is above the threshold.
5120  */
5121 #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK)
5122 
5123 #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U)
5124 #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U)
5125 /*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable.
5126  *  0b0..No interrupt pending..
5127  *  0b1..Interrupt pending..
5128  */
5129 #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK)
5130 
5131 #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U)
5132 #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U)
5133 /*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable.
5134  *  0b0..No interrupt pending..
5135  *  0b1..Interrupt pending..
5136  */
5137 #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK)
5138 
5139 #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U)
5140 #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U)
5141 /*! DCDC_VAL - Current value of DCDC power status output.
5142  *  0b0..DCDC output Voltage is below the targeted regulation level.
5143  *  0b1..DCDC output Voltage is above the targeted regulation level.
5144  */
5145 #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x)  (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK)
5146 /*! @} */
5147 
5148 /*! @name RINGO0_CTRL - First Ring Oscillator module control register. */
5149 /*! @{ */
5150 
5151 #define ANACTRL_RINGO0_CTRL_SL_MASK              (0x1U)
5152 #define ANACTRL_RINGO0_CTRL_SL_SHIFT             (0U)
5153 /*! SL - Select short or long ringo (for all ringos types).
5154  *  0b0..Select short ringo (few elements).
5155  *  0b1..Select long ringo (many elements).
5156  */
5157 #define ANACTRL_RINGO0_CTRL_SL(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK)
5158 
5159 #define ANACTRL_RINGO0_CTRL_FS_MASK              (0x2U)
5160 #define ANACTRL_RINGO0_CTRL_FS_SHIFT             (1U)
5161 /*! FS - Ringo frequency output divider.
5162  *  0b0..High frequency output (frequency lower than 100 MHz).
5163  *  0b1..Low frequency output (frequency lower than 10 MHz).
5164  */
5165 #define ANACTRL_RINGO0_CTRL_FS(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK)
5166 
5167 #define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK         (0xCU)
5168 #define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT        (2U)
5169 /*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control.
5170  *  0b00..Normal mode.
5171  *  0b01..P-Monitor mode. Measure with weak P transistor.
5172  *  0b10..P-Monitor mode. Measure with weak N transistor.
5173  *  0b11..Don't use.
5174  */
5175 #define ANACTRL_RINGO0_CTRL_SWN_SWP(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK)
5176 
5177 #define ANACTRL_RINGO0_CTRL_PD_MASK              (0x10U)
5178 #define ANACTRL_RINGO0_CTRL_PD_SHIFT             (4U)
5179 /*! PD - Ringo module Power control.
5180  *  0b0..The Ringo module is enabled.
5181  *  0b1..The Ringo module is disabled.
5182  */
5183 #define ANACTRL_RINGO0_CTRL_PD(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK)
5184 
5185 #define ANACTRL_RINGO0_CTRL_E_ND0_MASK           (0x20U)
5186 #define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT          (5U)
5187 /*! E_ND0 - First NAND2-based ringo control.
5188  *  0b0..First NAND2-based ringo is disabled.
5189  *  0b1..First NAND2-based ringo is enabled.
5190  */
5191 #define ANACTRL_RINGO0_CTRL_E_ND0(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK)
5192 
5193 #define ANACTRL_RINGO0_CTRL_E_ND1_MASK           (0x40U)
5194 #define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT          (6U)
5195 /*! E_ND1 - Second NAND2-based ringo control.
5196  *  0b0..Second NAND2-based ringo is disabled.
5197  *  0b1..Second NAND2-based ringo is enabled.
5198  */
5199 #define ANACTRL_RINGO0_CTRL_E_ND1(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK)
5200 
5201 #define ANACTRL_RINGO0_CTRL_E_NR0_MASK           (0x80U)
5202 #define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT          (7U)
5203 /*! E_NR0 - First NOR2-based ringo control.
5204  *  0b0..First NOR2-based ringo is disabled.
5205  *  0b1..First NOR2-based ringo is enabled.
5206  */
5207 #define ANACTRL_RINGO0_CTRL_E_NR0(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK)
5208 
5209 #define ANACTRL_RINGO0_CTRL_E_NR1_MASK           (0x100U)
5210 #define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT          (8U)
5211 /*! E_NR1 - Second NOR2-based ringo control.
5212  *  0b0..Second NORD2-based ringo is disabled.
5213  *  0b1..Second NORD2-based ringo is enabled.
5214  */
5215 #define ANACTRL_RINGO0_CTRL_E_NR1(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK)
5216 
5217 #define ANACTRL_RINGO0_CTRL_E_IV0_MASK           (0x200U)
5218 #define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT          (9U)
5219 /*! E_IV0 - First Inverter-based ringo control.
5220  *  0b0..First INV-based ringo is disabled.
5221  *  0b1..First INV-based ringo is enabled.
5222  */
5223 #define ANACTRL_RINGO0_CTRL_E_IV0(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK)
5224 
5225 #define ANACTRL_RINGO0_CTRL_E_IV1_MASK           (0x400U)
5226 #define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT          (10U)
5227 /*! E_IV1 - Second Inverter-based ringo control.
5228  *  0b0..Second INV-based ringo is disabled.
5229  *  0b1..Second INV-based ringo is enabled.
5230  */
5231 #define ANACTRL_RINGO0_CTRL_E_IV1(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK)
5232 
5233 #define ANACTRL_RINGO0_CTRL_E_PN0_MASK           (0x800U)
5234 #define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT          (11U)
5235 /*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control.
5236  *  0b0..First PN-based ringo is disabled.
5237  *  0b1..First PN-based ringo is enabled.
5238  */
5239 #define ANACTRL_RINGO0_CTRL_E_PN0(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK)
5240 
5241 #define ANACTRL_RINGO0_CTRL_E_PN1_MASK           (0x1000U)
5242 #define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT          (12U)
5243 /*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control.
5244  *  0b0..Second PN-based ringo is disabled.
5245  *  0b1..Second PN-based ringo is enabled.
5246  */
5247 #define ANACTRL_RINGO0_CTRL_E_PN1(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK)
5248 
5249 #define ANACTRL_RINGO0_CTRL_DIVISOR_MASK         (0xF0000U)
5250 #define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT        (16U)
5251 /*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
5252  */
5253 #define ANACTRL_RINGO0_CTRL_DIVISOR(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK)
5254 
5255 #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK  (0x80000000U)
5256 #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
5257 /*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
5258  *    value, cleared when the change is complete.
5259  */
5260 #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x)    (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK)
5261 /*! @} */
5262 
5263 /*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */
5264 /*! @{ */
5265 
5266 #define ANACTRL_RINGO1_CTRL_S_MASK               (0x1U)
5267 #define ANACTRL_RINGO1_CTRL_S_SHIFT              (0U)
5268 /*! S - Select short or long ringo (for all ringos types).
5269  *  0b0..Select short ringo (few elements).
5270  *  0b1..Select long ringo (many elements).
5271  */
5272 #define ANACTRL_RINGO1_CTRL_S(x)                 (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK)
5273 
5274 #define ANACTRL_RINGO1_CTRL_FS_MASK              (0x2U)
5275 #define ANACTRL_RINGO1_CTRL_FS_SHIFT             (1U)
5276 /*! FS - Ringo frequency output divider.
5277  *  0b0..High frequency output (frequency lower than 100 MHz).
5278  *  0b1..Low frequency output (frequency lower than 10 MHz).
5279  */
5280 #define ANACTRL_RINGO1_CTRL_FS(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK)
5281 
5282 #define ANACTRL_RINGO1_CTRL_PD_MASK              (0x4U)
5283 #define ANACTRL_RINGO1_CTRL_PD_SHIFT             (2U)
5284 /*! PD - Ringo module Power control.
5285  *  0b0..The Ringo module is enabled.
5286  *  0b1..The Ringo module is disabled.
5287  */
5288 #define ANACTRL_RINGO1_CTRL_PD(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK)
5289 
5290 #define ANACTRL_RINGO1_CTRL_E_R24_MASK           (0x8U)
5291 #define ANACTRL_RINGO1_CTRL_E_R24_SHIFT          (3U)
5292 /*! E_R24 - .
5293  *  0b0..Ringo is disabled.
5294  *  0b1..Ringo is enabled.
5295  */
5296 #define ANACTRL_RINGO1_CTRL_E_R24(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK)
5297 
5298 #define ANACTRL_RINGO1_CTRL_E_R35_MASK           (0x10U)
5299 #define ANACTRL_RINGO1_CTRL_E_R35_SHIFT          (4U)
5300 /*! E_R35 - .
5301  *  0b0..Ringo is disabled.
5302  *  0b1..Ringo is enabled.
5303  */
5304 #define ANACTRL_RINGO1_CTRL_E_R35(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK)
5305 
5306 #define ANACTRL_RINGO1_CTRL_E_M2_MASK            (0x20U)
5307 #define ANACTRL_RINGO1_CTRL_E_M2_SHIFT           (5U)
5308 /*! E_M2 - Metal 2 (M2) monitor control.
5309  *  0b0..Ringo is disabled.
5310  *  0b1..Ringo is enabled.
5311  */
5312 #define ANACTRL_RINGO1_CTRL_E_M2(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK)
5313 
5314 #define ANACTRL_RINGO1_CTRL_E_M3_MASK            (0x40U)
5315 #define ANACTRL_RINGO1_CTRL_E_M3_SHIFT           (6U)
5316 /*! E_M3 - Metal 3 (M3) monitor control.
5317  *  0b0..Ringo is disabled.
5318  *  0b1..Ringo is enabled.
5319  */
5320 #define ANACTRL_RINGO1_CTRL_E_M3(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK)
5321 
5322 #define ANACTRL_RINGO1_CTRL_E_M4_MASK            (0x80U)
5323 #define ANACTRL_RINGO1_CTRL_E_M4_SHIFT           (7U)
5324 /*! E_M4 - Metal 4 (M4) monitor control.
5325  *  0b0..Ringo is disabled.
5326  *  0b1..Ringo is enabled.
5327  */
5328 #define ANACTRL_RINGO1_CTRL_E_M4(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK)
5329 
5330 #define ANACTRL_RINGO1_CTRL_E_M5_MASK            (0x100U)
5331 #define ANACTRL_RINGO1_CTRL_E_M5_SHIFT           (8U)
5332 /*! E_M5 - Metal 5 (M5) monitor control.
5333  *  0b0..Ringo is disabled.
5334  *  0b1..Ringo is enabled.
5335  */
5336 #define ANACTRL_RINGO1_CTRL_E_M5(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK)
5337 
5338 #define ANACTRL_RINGO1_CTRL_DIVISOR_MASK         (0xF0000U)
5339 #define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT        (16U)
5340 /*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
5341  */
5342 #define ANACTRL_RINGO1_CTRL_DIVISOR(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK)
5343 
5344 #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK  (0x80000000U)
5345 #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
5346 /*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
5347  *    value, cleared when the change is complete.
5348  */
5349 #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x)    (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK)
5350 /*! @} */
5351 
5352 /*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */
5353 /*! @{ */
5354 
5355 #define ANACTRL_RINGO2_CTRL_S_MASK               (0x1U)
5356 #define ANACTRL_RINGO2_CTRL_S_SHIFT              (0U)
5357 /*! S - Select short or long ringo (for all ringos types).
5358  *  0b0..Select short ringo (few elements).
5359  *  0b1..Select long ringo (many elements).
5360  */
5361 #define ANACTRL_RINGO2_CTRL_S(x)                 (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK)
5362 
5363 #define ANACTRL_RINGO2_CTRL_FS_MASK              (0x2U)
5364 #define ANACTRL_RINGO2_CTRL_FS_SHIFT             (1U)
5365 /*! FS - Ringo frequency output divider.
5366  *  0b0..High frequency output (frequency lower than 100 MHz).
5367  *  0b1..Low frequency output (frequency lower than 10 MHz).
5368  */
5369 #define ANACTRL_RINGO2_CTRL_FS(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK)
5370 
5371 #define ANACTRL_RINGO2_CTRL_PD_MASK              (0x4U)
5372 #define ANACTRL_RINGO2_CTRL_PD_SHIFT             (2U)
5373 /*! PD - Ringo module Power control.
5374  *  0b0..The Ringo module is enabled.
5375  *  0b1..The Ringo module is disabled.
5376  */
5377 #define ANACTRL_RINGO2_CTRL_PD(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK)
5378 
5379 #define ANACTRL_RINGO2_CTRL_E_R24_MASK           (0x8U)
5380 #define ANACTRL_RINGO2_CTRL_E_R24_SHIFT          (3U)
5381 /*! E_R24 - .
5382  *  0b0..Ringo is disabled.
5383  *  0b1..Ringo is enabled.
5384  */
5385 #define ANACTRL_RINGO2_CTRL_E_R24(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK)
5386 
5387 #define ANACTRL_RINGO2_CTRL_E_R35_MASK           (0x10U)
5388 #define ANACTRL_RINGO2_CTRL_E_R35_SHIFT          (4U)
5389 /*! E_R35 - .
5390  *  0b0..Ringo is disabled.
5391  *  0b1..Ringo is enabled.
5392  */
5393 #define ANACTRL_RINGO2_CTRL_E_R35(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK)
5394 
5395 #define ANACTRL_RINGO2_CTRL_E_M2_MASK            (0x20U)
5396 #define ANACTRL_RINGO2_CTRL_E_M2_SHIFT           (5U)
5397 /*! E_M2 - Metal 2 (M2) monitor control.
5398  *  0b0..Ringo is disabled.
5399  *  0b1..Ringo is enabled.
5400  */
5401 #define ANACTRL_RINGO2_CTRL_E_M2(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK)
5402 
5403 #define ANACTRL_RINGO2_CTRL_E_M3_MASK            (0x40U)
5404 #define ANACTRL_RINGO2_CTRL_E_M3_SHIFT           (6U)
5405 /*! E_M3 - Metal 3 (M3) monitor control.
5406  *  0b0..Ringo is disabled.
5407  *  0b1..Ringo is enabled.
5408  */
5409 #define ANACTRL_RINGO2_CTRL_E_M3(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK)
5410 
5411 #define ANACTRL_RINGO2_CTRL_E_M4_MASK            (0x80U)
5412 #define ANACTRL_RINGO2_CTRL_E_M4_SHIFT           (7U)
5413 /*! E_M4 - Metal 4 (M4) monitor control.
5414  *  0b0..Ringo is disabled.
5415  *  0b1..Ringo is enabled.
5416  */
5417 #define ANACTRL_RINGO2_CTRL_E_M4(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK)
5418 
5419 #define ANACTRL_RINGO2_CTRL_E_M5_MASK            (0x100U)
5420 #define ANACTRL_RINGO2_CTRL_E_M5_SHIFT           (8U)
5421 /*! E_M5 - Metal 5 (M5) monitor control.
5422  *  0b0..Ringo is disabled.
5423  *  0b1..Ringo is enabled.
5424  */
5425 #define ANACTRL_RINGO2_CTRL_E_M5(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK)
5426 
5427 #define ANACTRL_RINGO2_CTRL_DIVISOR_MASK         (0xF0000U)
5428 #define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT        (16U)
5429 /*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
5430  */
5431 #define ANACTRL_RINGO2_CTRL_DIVISOR(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK)
5432 
5433 #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK  (0x80000000U)
5434 #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
5435 /*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
5436  *    value, cleared when the change is complete.
5437  */
5438 #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x)    (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK)
5439 /*! @} */
5440 
5441 /*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */
5442 /*! @{ */
5443 
5444 #define ANACTRL_LDO_XO32M_BYPASS_MASK            (0x2U)
5445 #define ANACTRL_LDO_XO32M_BYPASS_SHIFT           (1U)
5446 /*! BYPASS - Activate LDO bypass.
5447  *  0b0..Disable bypass mode (for normal operations).
5448  *  0b1..Activate LDO bypass.
5449  */
5450 #define ANACTRL_LDO_XO32M_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK)
5451 
5452 #define ANACTRL_LDO_XO32M_HIGHZ_MASK             (0x4U)
5453 #define ANACTRL_LDO_XO32M_HIGHZ_SHIFT            (2U)
5454 /*! HIGHZ - .
5455  *  0b0..Output in High normal state.
5456  *  0b1..Output in High Impedance state.
5457  */
5458 #define ANACTRL_LDO_XO32M_HIGHZ(x)               (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK)
5459 
5460 #define ANACTRL_LDO_XO32M_VOUT_MASK              (0x38U)
5461 #define ANACTRL_LDO_XO32M_VOUT_SHIFT             (3U)
5462 /*! VOUT - Sets the LDO output level.
5463  *  0b000..0.750 V.
5464  *  0b001..0.775 V.
5465  *  0b010..0.800 V.
5466  *  0b011..0.825 V.
5467  *  0b100..0.850 V.
5468  *  0b101..0.875 V.
5469  *  0b110..0.900 V.
5470  *  0b111..0.925 V.
5471  */
5472 #define ANACTRL_LDO_XO32M_VOUT(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK)
5473 
5474 #define ANACTRL_LDO_XO32M_IBIAS_MASK             (0xC0U)
5475 #define ANACTRL_LDO_XO32M_IBIAS_SHIFT            (6U)
5476 /*! IBIAS - Adjust the biasing current.
5477  */
5478 #define ANACTRL_LDO_XO32M_IBIAS(x)               (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK)
5479 
5480 #define ANACTRL_LDO_XO32M_STABMODE_MASK          (0x300U)
5481 #define ANACTRL_LDO_XO32M_STABMODE_SHIFT         (8U)
5482 /*! STABMODE - Stability configuration.
5483  */
5484 #define ANACTRL_LDO_XO32M_STABMODE(x)            (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK)
5485 /*! @} */
5486 
5487 /*! @name AUX_BIAS - AUX_BIAS */
5488 /*! @{ */
5489 
5490 #define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK       (0x2U)
5491 #define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT      (1U)
5492 /*! VREF1VENABLE - Control output of 1V reference voltage.
5493  *  0b0..Output of 1V reference voltage buffer is bypassed.
5494  *  0b1..Output of 1V reference voltage is enabled.
5495  */
5496 #define ANACTRL_AUX_BIAS_VREF1VENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK)
5497 
5498 #define ANACTRL_AUX_BIAS_ITRIM_MASK              (0x7CU)
5499 #define ANACTRL_AUX_BIAS_ITRIM_SHIFT             (2U)
5500 /*! ITRIM - current trimming control word.
5501  */
5502 #define ANACTRL_AUX_BIAS_ITRIM(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK)
5503 
5504 #define ANACTRL_AUX_BIAS_PTATITRIM_MASK          (0xF80U)
5505 #define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT         (7U)
5506 /*! PTATITRIM - current trimming control word for ptat current.
5507  */
5508 #define ANACTRL_AUX_BIAS_PTATITRIM(x)            (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK)
5509 
5510 #define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK         (0x1F000U)
5511 #define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT        (12U)
5512 /*! VREF1VTRIM - voltage trimming control word.
5513  */
5514 #define ANACTRL_AUX_BIAS_VREF1VTRIM(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK)
5515 
5516 #define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK    (0xE0000U)
5517 #define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT   (17U)
5518 /*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror.
5519  */
5520 #define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x)      (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK)
5521 
5522 #define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK         (0x100000U)
5523 #define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT        (20U)
5524 /*! ITRIMCTRL0 - Control bit to configure trimming state of mirror.
5525  */
5526 #define ANACTRL_AUX_BIAS_ITRIMCTRL0(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK)
5527 
5528 #define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK         (0x200000U)
5529 #define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT        (21U)
5530 /*! ITRIMCTRL1 - Control bit to configure trimming state of mirror.
5531  */
5532 #define ANACTRL_AUX_BIAS_ITRIMCTRL1(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK)
5533 /*! @} */
5534 
5535 /*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */
5536 /*! @{ */
5537 
5538 #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U)
5539 #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U)
5540 /*! usb_vbusvalid_ext - Override value for Vbus if using external detectors.
5541  */
5542 #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK)
5543 
5544 #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK   (0x2U)
5545 #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT  (1U)
5546 /*! usb_id_ext - Override value for ID if using external detectors.
5547  */
5548 #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x)     (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK)
5549 /*! @} */
5550 
5551 /*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */
5552 /*! @{ */
5553 
5554 #define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U)
5555 #define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U)
5556 /*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator.
5557  */
5558 #define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK)
5559 
5560 #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU)
5561 #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U)
5562 /*! trim_usbphy_tx_d_cal - .
5563  */
5564 #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK)
5565 
5566 #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U)
5567 #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U)
5568 /*! trim_usbphy_tx_cal45dp - .
5569  */
5570 #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK)
5571 
5572 #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U)
5573 #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U)
5574 /*! trim_usbphy_tx_cal45dm - .
5575  */
5576 #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK)
5577 
5578 #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U)
5579 #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U)
5580 /*! trim_usb2_refbias_tst - .
5581  */
5582 #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK)
5583 
5584 #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U)
5585 #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U)
5586 /*! trim_usb2_refbias_vbgadj - .
5587  */
5588 #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK)
5589 
5590 #define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U)
5591 #define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U)
5592 /*! trim_pll_ctrl0_div_sel - .
5593  */
5594 #define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK)
5595 /*! @} */
5596 
5597 
5598 /*!
5599  * @}
5600  */ /* end of group ANACTRL_Register_Masks */
5601 
5602 
5603 /* ANACTRL - Peripheral instance base addresses */
5604 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
5605   /** Peripheral ANACTRL base address */
5606   #define ANACTRL_BASE                             (0x50013000u)
5607   /** Peripheral ANACTRL base address */
5608   #define ANACTRL_BASE_NS                          (0x40013000u)
5609   /** Peripheral ANACTRL base pointer */
5610   #define ANACTRL                                  ((ANACTRL_Type *)ANACTRL_BASE)
5611   /** Peripheral ANACTRL base pointer */
5612   #define ANACTRL_NS                               ((ANACTRL_Type *)ANACTRL_BASE_NS)
5613   /** Array initializer of ANACTRL peripheral base addresses */
5614   #define ANACTRL_BASE_ADDRS                       { ANACTRL_BASE }
5615   /** Array initializer of ANACTRL peripheral base pointers */
5616   #define ANACTRL_BASE_PTRS                        { ANACTRL }
5617   /** Array initializer of ANACTRL peripheral base addresses */
5618   #define ANACTRL_BASE_ADDRS_NS                    { ANACTRL_BASE_NS }
5619   /** Array initializer of ANACTRL peripheral base pointers */
5620   #define ANACTRL_BASE_PTRS_NS                     { ANACTRL_NS }
5621 #else
5622   /** Peripheral ANACTRL base address */
5623   #define ANACTRL_BASE                             (0x40013000u)
5624   /** Peripheral ANACTRL base pointer */
5625   #define ANACTRL                                  ((ANACTRL_Type *)ANACTRL_BASE)
5626   /** Array initializer of ANACTRL peripheral base addresses */
5627   #define ANACTRL_BASE_ADDRS                       { ANACTRL_BASE }
5628   /** Array initializer of ANACTRL peripheral base pointers */
5629   #define ANACTRL_BASE_PTRS                        { ANACTRL }
5630 #endif
5631 
5632 /*!
5633  * @}
5634  */ /* end of group ANACTRL_Peripheral_Access_Layer */
5635 
5636 
5637 /* ----------------------------------------------------------------------------
5638    -- CASPER Peripheral Access Layer
5639    ---------------------------------------------------------------------------- */
5640 
5641 /*!
5642  * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer
5643  * @{
5644  */
5645 
5646 /** CASPER - Register Layout Typedef */
5647 typedef struct {
5648   __IO uint32_t CTRL0;                             /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */
5649   __IO uint32_t CTRL1;                             /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */
5650   __IO uint32_t LOADER;                            /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */
5651   __IO uint32_t STATUS;                            /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */
5652   __IO uint32_t INTENSET;                          /**< Sets interrupts, offset: 0x10 */
5653   __IO uint32_t INTENCLR;                          /**< Clears interrupts, offset: 0x14 */
5654   __I  uint32_t INTSTAT;                           /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */
5655        uint8_t RESERVED_0[4];
5656   __IO uint32_t AREG;                              /**< A register, offset: 0x20 */
5657   __IO uint32_t BREG;                              /**< B register, offset: 0x24 */
5658   __IO uint32_t CREG;                              /**< C register, offset: 0x28 */
5659   __IO uint32_t DREG;                              /**< D register, offset: 0x2C */
5660   __IO uint32_t RES0;                              /**< Result register 0, offset: 0x30 */
5661   __IO uint32_t RES1;                              /**< Result register 1, offset: 0x34 */
5662   __IO uint32_t RES2;                              /**< Result register 2, offset: 0x38 */
5663   __IO uint32_t RES3;                              /**< Result register 3, offset: 0x3C */
5664        uint8_t RESERVED_1[32];
5665   __IO uint32_t MASK;                              /**< Optional mask register, offset: 0x60 */
5666   __IO uint32_t REMASK;                            /**< Optional re-mask register, offset: 0x64 */
5667        uint8_t RESERVED_2[24];
5668   __IO uint32_t LOCK;                              /**< Security lock register, offset: 0x80 */
5669 } CASPER_Type;
5670 
5671 /* ----------------------------------------------------------------------------
5672    -- CASPER Register Masks
5673    ---------------------------------------------------------------------------- */
5674 
5675 /*!
5676  * @addtogroup CASPER_Register_Masks CASPER Register Masks
5677  * @{
5678  */
5679 
5680 /*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */
5681 /*! @{ */
5682 
5683 #define CASPER_CTRL0_ABBPAIR_MASK                (0x1U)
5684 #define CASPER_CTRL0_ABBPAIR_SHIFT               (0U)
5685 /*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up
5686  *  0b0..Bank-pair 0 (1st)
5687  *  0b1..Bank-pair 1 (2nd)
5688  */
5689 #define CASPER_CTRL0_ABBPAIR(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK)
5690 
5691 #define CASPER_CTRL0_ABOFF_MASK                  (0x1FFCU)
5692 #define CASPER_CTRL0_ABOFF_SHIFT                 (2U)
5693 /*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code
5694  *    sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed
5695  *    if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up
5696  */
5697 #define CASPER_CTRL0_ABOFF(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK)
5698 
5699 #define CASPER_CTRL0_CDBPAIR_MASK                (0x10000U)
5700 #define CASPER_CTRL0_CDBPAIR_SHIFT               (16U)
5701 /*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up
5702  *  0b0..Bank-pair 0 (1st)
5703  *  0b1..Bank-pair 1 (2nd)
5704  */
5705 #define CASPER_CTRL0_CDBPAIR(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK)
5706 
5707 #define CASPER_CTRL0_CDOFF_MASK                  (0x1FFC0000U)
5708 #define CASPER_CTRL0_CDOFF_SHIFT                 (18U)
5709 /*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees
5710  *    (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32
5711  *    bit operation. Ideally not in the same RAM as the AB values
5712  */
5713 #define CASPER_CTRL0_CDOFF(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK)
5714 /*! @} */
5715 
5716 /*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */
5717 /*! @{ */
5718 
5719 #define CASPER_CTRL1_ITER_MASK                   (0xFFU)
5720 #define CASPER_CTRL1_ITER_SHIFT                  (0U)
5721 /*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate.
5722  */
5723 #define CASPER_CTRL1_ITER(x)                     (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK)
5724 
5725 #define CASPER_CTRL1_MODE_MASK                   (0xFF00U)
5726 #define CASPER_CTRL1_MODE_SHIFT                  (8U)
5727 /*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active.
5728  */
5729 #define CASPER_CTRL1_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
5730 
5731 #define CASPER_CTRL1_RESBPAIR_MASK               (0x10000U)
5732 #define CASPER_CTRL1_RESBPAIR_SHIFT              (16U)
5733 /*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally
5734  *    this is not the same bank as ABBPAIR (when 4-up supported)
5735  *  0b0..Bank-pair 0 (1st)
5736  *  0b1..Bank-pair 1 (2nd)
5737  */
5738 #define CASPER_CTRL1_RESBPAIR(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK)
5739 
5740 #define CASPER_CTRL1_RESOFF_MASK                 (0x1FFC0000U)
5741 #define CASPER_CTRL1_RESOFF_SHIFT                (18U)
5742 /*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally
5743  *    not in the same RAM as the AB and CD values
5744  */
5745 #define CASPER_CTRL1_RESOFF(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK)
5746 
5747 #define CASPER_CTRL1_CSKIP_MASK                  (0xC0000000U)
5748 #define CASPER_CTRL1_CSKIP_SHIFT                 (30U)
5749 /*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0:
5750  *  0b00..No Skip
5751  *  0b01..Skip if Carry is 1
5752  *  0b10..Skip if Carry is 0
5753  *  0b11..Set CTRLOFF to CDOFF and Skip
5754  */
5755 #define CASPER_CTRL1_CSKIP(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK)
5756 /*! @} */
5757 
5758 /*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */
5759 /*! @{ */
5760 
5761 #define CASPER_LOADER_COUNT_MASK                 (0xFFU)
5762 #define CASPER_LOADER_COUNT_SHIFT                (0U)
5763 /*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one
5764  *    op - does not iterate, write N means N control pairs to load
5765  */
5766 #define CASPER_LOADER_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK)
5767 
5768 #define CASPER_LOADER_CTRLBPAIR_MASK             (0x10000U)
5769 #define CASPER_LOADER_CTRLBPAIR_SHIFT            (16U)
5770 /*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not
5771  *    matter which bank is used as this is loaded when not performing an operation.
5772  *  0b0..Bank-pair 0 (1st)
5773  *  0b1..Bank-pair 1 (2nd)
5774  */
5775 #define CASPER_LOADER_CTRLBPAIR(x)               (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK)
5776 
5777 #define CASPER_LOADER_CTRLOFF_MASK               (0x1FFC0000U)
5778 #define CASPER_LOADER_CTRLOFF_SHIFT              (18U)
5779 /*! CTRLOFF - DWord Offset of CTRL pair to load next.
5780  */
5781 #define CASPER_LOADER_CTRLOFF(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK)
5782 /*! @} */
5783 
5784 /*! @name STATUS - Indicates operational status and would contain the carry bit if used. */
5785 /*! @{ */
5786 
5787 #define CASPER_STATUS_DONE_MASK                  (0x1U)
5788 #define CASPER_STATUS_DONE_SHIFT                 (0U)
5789 /*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear.
5790  *  0b0..Busy or just cleared
5791  *  0b1..Completed last operation
5792  */
5793 #define CASPER_STATUS_DONE(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK)
5794 
5795 #define CASPER_STATUS_CARRY_MASK                 (0x10U)
5796 #define CASPER_STATUS_CARRY_SHIFT                (4U)
5797 /*! CARRY - Last carry value if operation produced a carry bit
5798  *  0b0..Carry was 0 or no carry
5799  *  0b1..Carry was 1
5800  */
5801 #define CASPER_STATUS_CARRY(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK)
5802 
5803 #define CASPER_STATUS_BUSY_MASK                  (0x20U)
5804 #define CASPER_STATUS_BUSY_SHIFT                 (5U)
5805 /*! BUSY - Indicates if the accelerator is busy performing an operation
5806  *  0b0..Not busy - is idle
5807  *  0b1..Is busy
5808  */
5809 #define CASPER_STATUS_BUSY(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK)
5810 /*! @} */
5811 
5812 /*! @name INTENSET - Sets interrupts */
5813 /*! @{ */
5814 
5815 #define CASPER_INTENSET_DONE_MASK                (0x1U)
5816 #define CASPER_INTENSET_DONE_SHIFT               (0U)
5817 /*! DONE - Set if the accelerator should interrupt when done.
5818  *  0b0..Do not interrupt when done
5819  *  0b1..Interrupt when done
5820  */
5821 #define CASPER_INTENSET_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK)
5822 /*! @} */
5823 
5824 /*! @name INTENCLR - Clears interrupts */
5825 /*! @{ */
5826 
5827 #define CASPER_INTENCLR_DONE_MASK                (0x1U)
5828 #define CASPER_INTENCLR_DONE_SHIFT               (0U)
5829 /*! DONE - Written to clear an interrupt set with INTENSET.
5830  *  0b0..If written 0, ignored
5831  *  0b1..If written 1, do not Interrupt when done
5832  */
5833 #define CASPER_INTENCLR_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK)
5834 /*! @} */
5835 
5836 /*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */
5837 /*! @{ */
5838 
5839 #define CASPER_INTSTAT_DONE_MASK                 (0x1U)
5840 #define CASPER_INTSTAT_DONE_SHIFT                (0U)
5841 /*! DONE - If set, interrupt is caused by accelerator being done.
5842  *  0b0..Not caused by accelerator being done
5843  *  0b1..Caused by accelerator being done
5844  */
5845 #define CASPER_INTSTAT_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK)
5846 /*! @} */
5847 
5848 /*! @name AREG - A register */
5849 /*! @{ */
5850 
5851 #define CASPER_AREG_REG_VALUE_MASK               (0xFFFFFFFFU)
5852 #define CASPER_AREG_REG_VALUE_SHIFT              (0U)
5853 /*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
5854  *    but is available when accelerator not busy.
5855  */
5856 #define CASPER_AREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK)
5857 /*! @} */
5858 
5859 /*! @name BREG - B register */
5860 /*! @{ */
5861 
5862 #define CASPER_BREG_REG_VALUE_MASK               (0xFFFFFFFFU)
5863 #define CASPER_BREG_REG_VALUE_SHIFT              (0U)
5864 /*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
5865  *    but is available when accelerator not busy.
5866  */
5867 #define CASPER_BREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK)
5868 /*! @} */
5869 
5870 /*! @name CREG - C register */
5871 /*! @{ */
5872 
5873 #define CASPER_CREG_REG_VALUE_MASK               (0xFFFFFFFFU)
5874 #define CASPER_CREG_REG_VALUE_SHIFT              (0U)
5875 /*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
5876  *    but is available when accelerator not busy.
5877  */
5878 #define CASPER_CREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK)
5879 /*! @} */
5880 
5881 /*! @name DREG - D register */
5882 /*! @{ */
5883 
5884 #define CASPER_DREG_REG_VALUE_MASK               (0xFFFFFFFFU)
5885 #define CASPER_DREG_REG_VALUE_SHIFT              (0U)
5886 /*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
5887  *    but is available when accelerator not busy.
5888  */
5889 #define CASPER_DREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK)
5890 /*! @} */
5891 
5892 /*! @name RES0 - Result register 0 */
5893 /*! @{ */
5894 
5895 #define CASPER_RES0_REG_VALUE_MASK               (0xFFFFFFFFU)
5896 #define CASPER_RES0_REG_VALUE_SHIFT              (0U)
5897 /*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
5898  *    written or read by application, but is available when accelerator not busy.
5899  */
5900 #define CASPER_RES0_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK)
5901 /*! @} */
5902 
5903 /*! @name RES1 - Result register 1 */
5904 /*! @{ */
5905 
5906 #define CASPER_RES1_REG_VALUE_MASK               (0xFFFFFFFFU)
5907 #define CASPER_RES1_REG_VALUE_SHIFT              (0U)
5908 /*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
5909  *    written or read by application, but is available when accelerator not busy.
5910  */
5911 #define CASPER_RES1_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK)
5912 /*! @} */
5913 
5914 /*! @name RES2 - Result register 2 */
5915 /*! @{ */
5916 
5917 #define CASPER_RES2_REG_VALUE_MASK               (0xFFFFFFFFU)
5918 #define CASPER_RES2_REG_VALUE_SHIFT              (0U)
5919 /*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
5920  *    written or read by application, but is available when accelerator not busy.
5921  */
5922 #define CASPER_RES2_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK)
5923 /*! @} */
5924 
5925 /*! @name RES3 - Result register 3 */
5926 /*! @{ */
5927 
5928 #define CASPER_RES3_REG_VALUE_MASK               (0xFFFFFFFFU)
5929 #define CASPER_RES3_REG_VALUE_SHIFT              (0U)
5930 /*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
5931  *    written or read by application, but is available when accelerator not busy.
5932  */
5933 #define CASPER_RES3_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK)
5934 /*! @} */
5935 
5936 /*! @name MASK - Optional mask register */
5937 /*! @{ */
5938 
5939 #define CASPER_MASK_MASK_MASK                    (0xFFFFFFFFU)
5940 #define CASPER_MASK_MASK_SHIFT                   (0U)
5941 /*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values
5942  */
5943 #define CASPER_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK)
5944 /*! @} */
5945 
5946 /*! @name REMASK - Optional re-mask register */
5947 /*! @{ */
5948 
5949 #define CASPER_REMASK_MASK_MASK                  (0xFFFFFFFFU)
5950 #define CASPER_REMASK_MASK_SHIFT                 (0U)
5951 /*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values
5952  */
5953 #define CASPER_REMASK_MASK(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK)
5954 /*! @} */
5955 
5956 /*! @name LOCK - Security lock register */
5957 /*! @{ */
5958 
5959 #define CASPER_LOCK_LOCK_MASK                    (0x1U)
5960 #define CASPER_LOCK_LOCK_SHIFT                   (0U)
5961 /*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock.
5962  *  0b0..unlock
5963  *  0b1..Lock to current security level
5964  */
5965 #define CASPER_LOCK_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK)
5966 
5967 #define CASPER_LOCK_KEY_MASK                     (0x1FFF0U)
5968 #define CASPER_LOCK_KEY_SHIFT                    (4U)
5969 /*! KEY - Must be written as 0x73D to change the register.
5970  *  0b0011100111101..If set during write, will allow lock or unlock
5971  */
5972 #define CASPER_LOCK_KEY(x)                       (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK)
5973 /*! @} */
5974 
5975 
5976 /*!
5977  * @}
5978  */ /* end of group CASPER_Register_Masks */
5979 
5980 
5981 /* CASPER - Peripheral instance base addresses */
5982 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
5983   /** Peripheral CASPER base address */
5984   #define CASPER_BASE                              (0x500A5000u)
5985   /** Peripheral CASPER base address */
5986   #define CASPER_BASE_NS                           (0x400A5000u)
5987   /** Peripheral CASPER base pointer */
5988   #define CASPER                                   ((CASPER_Type *)CASPER_BASE)
5989   /** Peripheral CASPER base pointer */
5990   #define CASPER_NS                                ((CASPER_Type *)CASPER_BASE_NS)
5991   /** Array initializer of CASPER peripheral base addresses */
5992   #define CASPER_BASE_ADDRS                        { CASPER_BASE }
5993   /** Array initializer of CASPER peripheral base pointers */
5994   #define CASPER_BASE_PTRS                         { CASPER }
5995   /** Array initializer of CASPER peripheral base addresses */
5996   #define CASPER_BASE_ADDRS_NS                     { CASPER_BASE_NS }
5997   /** Array initializer of CASPER peripheral base pointers */
5998   #define CASPER_BASE_PTRS_NS                      { CASPER_NS }
5999 #else
6000   /** Peripheral CASPER base address */
6001   #define CASPER_BASE                              (0x400A5000u)
6002   /** Peripheral CASPER base pointer */
6003   #define CASPER                                   ((CASPER_Type *)CASPER_BASE)
6004   /** Array initializer of CASPER peripheral base addresses */
6005   #define CASPER_BASE_ADDRS                        { CASPER_BASE }
6006   /** Array initializer of CASPER peripheral base pointers */
6007   #define CASPER_BASE_PTRS                         { CASPER }
6008 #endif
6009 /** Interrupt vectors for the CASPER peripheral type */
6010 #define CASPER_IRQS                              { CASER_IRQn }
6011 
6012 /*!
6013  * @}
6014  */ /* end of group CASPER_Peripheral_Access_Layer */
6015 
6016 
6017 /* ----------------------------------------------------------------------------
6018    -- CRC Peripheral Access Layer
6019    ---------------------------------------------------------------------------- */
6020 
6021 /*!
6022  * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
6023  * @{
6024  */
6025 
6026 /** CRC - Register Layout Typedef */
6027 typedef struct {
6028   __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
6029   __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
6030   union {                                          /* offset: 0x8 */
6031     __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
6032     __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
6033   };
6034 } CRC_Type;
6035 
6036 /* ----------------------------------------------------------------------------
6037    -- CRC Register Masks
6038    ---------------------------------------------------------------------------- */
6039 
6040 /*!
6041  * @addtogroup CRC_Register_Masks CRC Register Masks
6042  * @{
6043  */
6044 
6045 /*! @name MODE - CRC mode register */
6046 /*! @{ */
6047 
6048 #define CRC_MODE_CRC_POLY_MASK                   (0x3U)
6049 #define CRC_MODE_CRC_POLY_SHIFT                  (0U)
6050 /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
6051  */
6052 #define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
6053 
6054 #define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
6055 #define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
6056 /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
6057  */
6058 #define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
6059 
6060 #define CRC_MODE_CMPL_WR_MASK                    (0x8U)
6061 #define CRC_MODE_CMPL_WR_SHIFT                   (3U)
6062 /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
6063  */
6064 #define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
6065 
6066 #define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
6067 #define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
6068 /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
6069  */
6070 #define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
6071 
6072 #define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
6073 #define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
6074 /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
6075  */
6076 #define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
6077 /*! @} */
6078 
6079 /*! @name SEED - CRC seed register */
6080 /*! @{ */
6081 
6082 #define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
6083 #define CRC_SEED_CRC_SEED_SHIFT                  (0U)
6084 /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
6085  *    selected bit order and 1's complement pre-processes. A write access to this register will
6086  *    overrule the CRC calculation in progresses.
6087  */
6088 #define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
6089 /*! @} */
6090 
6091 /*! @name SUM - CRC checksum register */
6092 /*! @{ */
6093 
6094 #define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
6095 #define CRC_SUM_CRC_SUM_SHIFT                    (0U)
6096 /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
6097  */
6098 #define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
6099 /*! @} */
6100 
6101 /*! @name WR_DATA - CRC data register */
6102 /*! @{ */
6103 
6104 #define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
6105 #define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
6106 /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
6107  *    selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
6108  *    accept back-to-back transactions.
6109  */
6110 #define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
6111 /*! @} */
6112 
6113 
6114 /*!
6115  * @}
6116  */ /* end of group CRC_Register_Masks */
6117 
6118 
6119 /* CRC - Peripheral instance base addresses */
6120 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
6121   /** Peripheral CRC_ENGINE base address */
6122   #define CRC_ENGINE_BASE                          (0x50095000u)
6123   /** Peripheral CRC_ENGINE base address */
6124   #define CRC_ENGINE_BASE_NS                       (0x40095000u)
6125   /** Peripheral CRC_ENGINE base pointer */
6126   #define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
6127   /** Peripheral CRC_ENGINE base pointer */
6128   #define CRC_ENGINE_NS                            ((CRC_Type *)CRC_ENGINE_BASE_NS)
6129   /** Array initializer of CRC peripheral base addresses */
6130   #define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
6131   /** Array initializer of CRC peripheral base pointers */
6132   #define CRC_BASE_PTRS                            { CRC_ENGINE }
6133   /** Array initializer of CRC peripheral base addresses */
6134   #define CRC_BASE_ADDRS_NS                        { CRC_ENGINE_BASE_NS }
6135   /** Array initializer of CRC peripheral base pointers */
6136   #define CRC_BASE_PTRS_NS                         { CRC_ENGINE_NS }
6137 #else
6138   /** Peripheral CRC_ENGINE base address */
6139   #define CRC_ENGINE_BASE                          (0x40095000u)
6140   /** Peripheral CRC_ENGINE base pointer */
6141   #define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
6142   /** Array initializer of CRC peripheral base addresses */
6143   #define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
6144   /** Array initializer of CRC peripheral base pointers */
6145   #define CRC_BASE_PTRS                            { CRC_ENGINE }
6146 #endif
6147 
6148 /*!
6149  * @}
6150  */ /* end of group CRC_Peripheral_Access_Layer */
6151 
6152 
6153 /* ----------------------------------------------------------------------------
6154    -- CTIMER Peripheral Access Layer
6155    ---------------------------------------------------------------------------- */
6156 
6157 /*!
6158  * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
6159  * @{
6160  */
6161 
6162 /** CTIMER - Register Layout Typedef */
6163 typedef struct {
6164   __IO uint32_t IR;                                /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
6165   __IO uint32_t TCR;                               /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
6166   __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
6167   __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
6168   __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
6169   __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
6170   __IO uint32_t MR[4];                             /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
6171   __IO uint32_t CCR;                               /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
6172   __I  uint32_t CR[4];                             /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
6173   __IO uint32_t EMR;                               /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
6174        uint8_t RESERVED_0[48];
6175   __IO uint32_t CTCR;                              /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
6176   __IO uint32_t PWMC;                              /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */
6177   __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
6178 } CTIMER_Type;
6179 
6180 /* ----------------------------------------------------------------------------
6181    -- CTIMER Register Masks
6182    ---------------------------------------------------------------------------- */
6183 
6184 /*!
6185  * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
6186  * @{
6187  */
6188 
6189 /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
6190 /*! @{ */
6191 
6192 #define CTIMER_IR_MR0INT_MASK                    (0x1U)
6193 #define CTIMER_IR_MR0INT_SHIFT                   (0U)
6194 /*! MR0INT - Interrupt flag for match channel 0.
6195  */
6196 #define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
6197 
6198 #define CTIMER_IR_MR1INT_MASK                    (0x2U)
6199 #define CTIMER_IR_MR1INT_SHIFT                   (1U)
6200 /*! MR1INT - Interrupt flag for match channel 1.
6201  */
6202 #define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
6203 
6204 #define CTIMER_IR_MR2INT_MASK                    (0x4U)
6205 #define CTIMER_IR_MR2INT_SHIFT                   (2U)
6206 /*! MR2INT - Interrupt flag for match channel 2.
6207  */
6208 #define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
6209 
6210 #define CTIMER_IR_MR3INT_MASK                    (0x8U)
6211 #define CTIMER_IR_MR3INT_SHIFT                   (3U)
6212 /*! MR3INT - Interrupt flag for match channel 3.
6213  */
6214 #define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
6215 
6216 #define CTIMER_IR_CR0INT_MASK                    (0x10U)
6217 #define CTIMER_IR_CR0INT_SHIFT                   (4U)
6218 /*! CR0INT - Interrupt flag for capture channel 0 event.
6219  */
6220 #define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
6221 
6222 #define CTIMER_IR_CR1INT_MASK                    (0x20U)
6223 #define CTIMER_IR_CR1INT_SHIFT                   (5U)
6224 /*! CR1INT - Interrupt flag for capture channel 1 event.
6225  */
6226 #define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
6227 
6228 #define CTIMER_IR_CR2INT_MASK                    (0x40U)
6229 #define CTIMER_IR_CR2INT_SHIFT                   (6U)
6230 /*! CR2INT - Interrupt flag for capture channel 2 event.
6231  */
6232 #define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
6233 
6234 #define CTIMER_IR_CR3INT_MASK                    (0x80U)
6235 #define CTIMER_IR_CR3INT_SHIFT                   (7U)
6236 /*! CR3INT - Interrupt flag for capture channel 3 event.
6237  */
6238 #define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
6239 /*! @} */
6240 
6241 /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
6242 /*! @{ */
6243 
6244 #define CTIMER_TCR_CEN_MASK                      (0x1U)
6245 #define CTIMER_TCR_CEN_SHIFT                     (0U)
6246 /*! CEN - Counter enable.
6247  *  0b0..Disabled.The counters are disabled.
6248  *  0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
6249  */
6250 #define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
6251 
6252 #define CTIMER_TCR_CRST_MASK                     (0x2U)
6253 #define CTIMER_TCR_CRST_SHIFT                    (1U)
6254 /*! CRST - Counter reset.
6255  *  0b0..Disabled. Do nothing.
6256  *  0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
6257  *       the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
6258  */
6259 #define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
6260 /*! @} */
6261 
6262 /*! @name TC - Timer Counter */
6263 /*! @{ */
6264 
6265 #define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
6266 #define CTIMER_TC_TCVAL_SHIFT                    (0U)
6267 /*! TCVAL - Timer counter value.
6268  */
6269 #define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
6270 /*! @} */
6271 
6272 /*! @name PR - Prescale Register */
6273 /*! @{ */
6274 
6275 #define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
6276 #define CTIMER_PR_PRVAL_SHIFT                    (0U)
6277 /*! PRVAL - Prescale counter value.
6278  */
6279 #define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
6280 /*! @} */
6281 
6282 /*! @name PC - Prescale Counter */
6283 /*! @{ */
6284 
6285 #define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
6286 #define CTIMER_PC_PCVAL_SHIFT                    (0U)
6287 /*! PCVAL - Prescale counter value.
6288  */
6289 #define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
6290 /*! @} */
6291 
6292 /*! @name MCR - Match Control Register */
6293 /*! @{ */
6294 
6295 #define CTIMER_MCR_MR0I_MASK                     (0x1U)
6296 #define CTIMER_MCR_MR0I_SHIFT                    (0U)
6297 /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
6298  */
6299 #define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
6300 
6301 #define CTIMER_MCR_MR0R_MASK                     (0x2U)
6302 #define CTIMER_MCR_MR0R_SHIFT                    (1U)
6303 /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
6304  */
6305 #define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
6306 
6307 #define CTIMER_MCR_MR0S_MASK                     (0x4U)
6308 #define CTIMER_MCR_MR0S_SHIFT                    (2U)
6309 /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
6310  */
6311 #define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
6312 
6313 #define CTIMER_MCR_MR1I_MASK                     (0x8U)
6314 #define CTIMER_MCR_MR1I_SHIFT                    (3U)
6315 /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
6316  */
6317 #define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
6318 
6319 #define CTIMER_MCR_MR1R_MASK                     (0x10U)
6320 #define CTIMER_MCR_MR1R_SHIFT                    (4U)
6321 /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
6322  */
6323 #define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
6324 
6325 #define CTIMER_MCR_MR1S_MASK                     (0x20U)
6326 #define CTIMER_MCR_MR1S_SHIFT                    (5U)
6327 /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
6328  */
6329 #define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
6330 
6331 #define CTIMER_MCR_MR2I_MASK                     (0x40U)
6332 #define CTIMER_MCR_MR2I_SHIFT                    (6U)
6333 /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
6334  */
6335 #define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
6336 
6337 #define CTIMER_MCR_MR2R_MASK                     (0x80U)
6338 #define CTIMER_MCR_MR2R_SHIFT                    (7U)
6339 /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
6340  */
6341 #define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
6342 
6343 #define CTIMER_MCR_MR2S_MASK                     (0x100U)
6344 #define CTIMER_MCR_MR2S_SHIFT                    (8U)
6345 /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
6346  */
6347 #define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
6348 
6349 #define CTIMER_MCR_MR3I_MASK                     (0x200U)
6350 #define CTIMER_MCR_MR3I_SHIFT                    (9U)
6351 /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
6352  */
6353 #define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
6354 
6355 #define CTIMER_MCR_MR3R_MASK                     (0x400U)
6356 #define CTIMER_MCR_MR3R_SHIFT                    (10U)
6357 /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
6358  */
6359 #define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
6360 
6361 #define CTIMER_MCR_MR3S_MASK                     (0x800U)
6362 #define CTIMER_MCR_MR3S_SHIFT                    (11U)
6363 /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
6364  */
6365 #define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
6366 
6367 #define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
6368 #define CTIMER_MCR_MR0RL_SHIFT                   (24U)
6369 /*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
6370  *    (either via a match event or a write to bit 1 of the TCR).
6371  */
6372 #define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
6373 
6374 #define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
6375 #define CTIMER_MCR_MR1RL_SHIFT                   (25U)
6376 /*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
6377  *    (either via a match event or a write to bit 1 of the TCR).
6378  */
6379 #define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
6380 
6381 #define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
6382 #define CTIMER_MCR_MR2RL_SHIFT                   (26U)
6383 /*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
6384  *    (either via a match event or a write to bit 1 of the TCR).
6385  */
6386 #define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
6387 
6388 #define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
6389 #define CTIMER_MCR_MR3RL_SHIFT                   (27U)
6390 /*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
6391  *    (either via a match event or a write to bit 1 of the TCR).
6392  */
6393 #define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
6394 /*! @} */
6395 
6396 /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
6397 /*! @{ */
6398 
6399 #define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
6400 #define CTIMER_MR_MATCH_SHIFT                    (0U)
6401 /*! MATCH - Timer counter match value.
6402  */
6403 #define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
6404 /*! @} */
6405 
6406 /* The count of CTIMER_MR */
6407 #define CTIMER_MR_COUNT                          (4U)
6408 
6409 /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
6410 /*! @{ */
6411 
6412 #define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
6413 #define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
6414 /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
6415  *    the contents of TC. 0 = disabled. 1 = enabled.
6416  */
6417 #define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
6418 
6419 #define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
6420 #define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
6421 /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
6422  *    the contents of TC. 0 = disabled. 1 = enabled.
6423  */
6424 #define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
6425 
6426 #define CTIMER_CCR_CAP0I_MASK                    (0x4U)
6427 #define CTIMER_CCR_CAP0I_SHIFT                   (2U)
6428 /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
6429  */
6430 #define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
6431 
6432 #define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
6433 #define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
6434 /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
6435  *    the contents of TC. 0 = disabled. 1 = enabled.
6436  */
6437 #define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
6438 
6439 #define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
6440 #define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
6441 /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
6442  *    the contents of TC. 0 = disabled. 1 = enabled.
6443  */
6444 #define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
6445 
6446 #define CTIMER_CCR_CAP1I_MASK                    (0x20U)
6447 #define CTIMER_CCR_CAP1I_SHIFT                   (5U)
6448 /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
6449  */
6450 #define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
6451 
6452 #define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
6453 #define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
6454 /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
6455  *    the contents of TC. 0 = disabled. 1 = enabled.
6456  */
6457 #define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
6458 
6459 #define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
6460 #define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
6461 /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
6462  *    the contents of TC. 0 = disabled. 1 = enabled.
6463  */
6464 #define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
6465 
6466 #define CTIMER_CCR_CAP2I_MASK                    (0x100U)
6467 #define CTIMER_CCR_CAP2I_SHIFT                   (8U)
6468 /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
6469  */
6470 #define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
6471 
6472 #define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
6473 #define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
6474 /*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
6475  *    the contents of TC. 0 = disabled. 1 = enabled.
6476  */
6477 #define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
6478 
6479 #define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
6480 #define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
6481 /*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
6482  *    the contents of TC. 0 = disabled. 1 = enabled.
6483  */
6484 #define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
6485 
6486 #define CTIMER_CCR_CAP3I_MASK                    (0x800U)
6487 #define CTIMER_CCR_CAP3I_SHIFT                   (11U)
6488 /*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
6489  */
6490 #define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
6491 /*! @} */
6492 
6493 /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
6494 /*! @{ */
6495 
6496 #define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
6497 #define CTIMER_CR_CAP_SHIFT                      (0U)
6498 /*! CAP - Timer counter capture value.
6499  */
6500 #define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
6501 /*! @} */
6502 
6503 /* The count of CTIMER_CR */
6504 #define CTIMER_CR_COUNT                          (4U)
6505 
6506 /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
6507 /*! @{ */
6508 
6509 #define CTIMER_EMR_EM0_MASK                      (0x1U)
6510 #define CTIMER_EMR_EM0_SHIFT                     (0U)
6511 /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
6512  *    is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
6513  *    go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
6514  *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
6515  */
6516 #define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
6517 
6518 #define CTIMER_EMR_EM1_MASK                      (0x2U)
6519 #define CTIMER_EMR_EM1_SHIFT                     (1U)
6520 /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
6521  *    is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
6522  *    go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
6523  *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
6524  */
6525 #define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
6526 
6527 #define CTIMER_EMR_EM2_MASK                      (0x4U)
6528 #define CTIMER_EMR_EM2_SHIFT                     (2U)
6529 /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
6530  *    is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
6531  *    go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
6532  *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
6533  */
6534 #define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
6535 
6536 #define CTIMER_EMR_EM3_MASK                      (0x8U)
6537 #define CTIMER_EMR_EM3_SHIFT                     (3U)
6538 /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
6539  *    is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
6540  *    go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
6541  *    if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
6542  */
6543 #define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
6544 
6545 #define CTIMER_EMR_EMC0_MASK                     (0x30U)
6546 #define CTIMER_EMR_EMC0_SHIFT                    (4U)
6547 /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
6548  *  0b00..Do Nothing.
6549  *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
6550  *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
6551  *  0b11..Toggle. Toggle the corresponding External Match bit/output.
6552  */
6553 #define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
6554 
6555 #define CTIMER_EMR_EMC1_MASK                     (0xC0U)
6556 #define CTIMER_EMR_EMC1_SHIFT                    (6U)
6557 /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
6558  *  0b00..Do Nothing.
6559  *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
6560  *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
6561  *  0b11..Toggle. Toggle the corresponding External Match bit/output.
6562  */
6563 #define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
6564 
6565 #define CTIMER_EMR_EMC2_MASK                     (0x300U)
6566 #define CTIMER_EMR_EMC2_SHIFT                    (8U)
6567 /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
6568  *  0b00..Do Nothing.
6569  *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
6570  *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
6571  *  0b11..Toggle. Toggle the corresponding External Match bit/output.
6572  */
6573 #define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
6574 
6575 #define CTIMER_EMR_EMC3_MASK                     (0xC00U)
6576 #define CTIMER_EMR_EMC3_SHIFT                    (10U)
6577 /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
6578  *  0b00..Do Nothing.
6579  *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
6580  *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
6581  *  0b11..Toggle. Toggle the corresponding External Match bit/output.
6582  */
6583 #define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
6584 /*! @} */
6585 
6586 /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
6587 /*! @{ */
6588 
6589 #define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
6590 #define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
6591 /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
6592  *    Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
6593  *    is incremented when the Prescale Counter matches the Prescale Register.
6594  *  0b00..Timer Mode. Incremented every rising APB bus clock edge.
6595  *  0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
6596  *  0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
6597  *  0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
6598  */
6599 #define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
6600 
6601 #define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
6602 #define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
6603 /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
6604  *    CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
6605  *    in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
6606  *    programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
6607  *    same timer.
6608  *  0b00..Channel 0. CAPn.0 for CTIMERn
6609  *  0b01..Channel 1. CAPn.1 for CTIMERn
6610  *  0b10..Channel 2. CAPn.2 for CTIMERn
6611  *  0b11..Channel 3. CAPn.3 for CTIMERn
6612  */
6613 #define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
6614 
6615 #define CTIMER_CTCR_ENCC_MASK                    (0x10U)
6616 #define CTIMER_CTCR_ENCC_SHIFT                   (4U)
6617 /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
6618  *    capture-edge event specified in bits 7:5 occurs.
6619  */
6620 #define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
6621 
6622 #define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
6623 #define CTIMER_CTCR_SELCC_SHIFT                  (5U)
6624 /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
6625  *    timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
6626  *    0x3 and 0x6 to 0x7 are reserved.
6627  *  0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
6628  *  0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
6629  *  0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
6630  *  0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
6631  *  0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
6632  *  0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
6633  */
6634 #define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
6635 /*! @} */
6636 
6637 /*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */
6638 /*! @{ */
6639 
6640 #define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
6641 #define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
6642 /*! PWMEN0 - PWM mode enable for channel0.
6643  *  0b0..Match. CTIMERn_MAT0 is controlled by EM0.
6644  *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
6645  */
6646 #define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
6647 
6648 #define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
6649 #define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
6650 /*! PWMEN1 - PWM mode enable for channel1.
6651  *  0b0..Match. CTIMERn_MAT01 is controlled by EM1.
6652  *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
6653  */
6654 #define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
6655 
6656 #define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
6657 #define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
6658 /*! PWMEN2 - PWM mode enable for channel2.
6659  *  0b0..Match. CTIMERn_MAT2 is controlled by EM2.
6660  *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
6661  */
6662 #define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
6663 
6664 #define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
6665 #define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
6666 /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
6667  *  0b0..Match. CTIMERn_MAT3 is controlled by EM3.
6668  *  0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
6669  */
6670 #define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
6671 /*! @} */
6672 
6673 /*! @name MSR - Match Shadow Register */
6674 /*! @{ */
6675 
6676 #define CTIMER_MSR_SHADOW_MASK                   (0xFFFFFFFFU)
6677 #define CTIMER_MSR_SHADOW_SHIFT                  (0U)
6678 /*! SHADOW - Timer counter match shadow value.
6679  */
6680 #define CTIMER_MSR_SHADOW(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK)
6681 /*! @} */
6682 
6683 /* The count of CTIMER_MSR */
6684 #define CTIMER_MSR_COUNT                         (4U)
6685 
6686 
6687 /*!
6688  * @}
6689  */ /* end of group CTIMER_Register_Masks */
6690 
6691 
6692 /* CTIMER - Peripheral instance base addresses */
6693 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
6694   /** Peripheral CTIMER0 base address */
6695   #define CTIMER0_BASE                             (0x50008000u)
6696   /** Peripheral CTIMER0 base address */
6697   #define CTIMER0_BASE_NS                          (0x40008000u)
6698   /** Peripheral CTIMER0 base pointer */
6699   #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
6700   /** Peripheral CTIMER0 base pointer */
6701   #define CTIMER0_NS                               ((CTIMER_Type *)CTIMER0_BASE_NS)
6702   /** Peripheral CTIMER1 base address */
6703   #define CTIMER1_BASE                             (0x50009000u)
6704   /** Peripheral CTIMER1 base address */
6705   #define CTIMER1_BASE_NS                          (0x40009000u)
6706   /** Peripheral CTIMER1 base pointer */
6707   #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
6708   /** Peripheral CTIMER1 base pointer */
6709   #define CTIMER1_NS                               ((CTIMER_Type *)CTIMER1_BASE_NS)
6710   /** Peripheral CTIMER2 base address */
6711   #define CTIMER2_BASE                             (0x50028000u)
6712   /** Peripheral CTIMER2 base address */
6713   #define CTIMER2_BASE_NS                          (0x40028000u)
6714   /** Peripheral CTIMER2 base pointer */
6715   #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
6716   /** Peripheral CTIMER2 base pointer */
6717   #define CTIMER2_NS                               ((CTIMER_Type *)CTIMER2_BASE_NS)
6718   /** Peripheral CTIMER3 base address */
6719   #define CTIMER3_BASE                             (0x50029000u)
6720   /** Peripheral CTIMER3 base address */
6721   #define CTIMER3_BASE_NS                          (0x40029000u)
6722   /** Peripheral CTIMER3 base pointer */
6723   #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
6724   /** Peripheral CTIMER3 base pointer */
6725   #define CTIMER3_NS                               ((CTIMER_Type *)CTIMER3_BASE_NS)
6726   /** Peripheral CTIMER4 base address */
6727   #define CTIMER4_BASE                             (0x5002A000u)
6728   /** Peripheral CTIMER4 base address */
6729   #define CTIMER4_BASE_NS                          (0x4002A000u)
6730   /** Peripheral CTIMER4 base pointer */
6731   #define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
6732   /** Peripheral CTIMER4 base pointer */
6733   #define CTIMER4_NS                               ((CTIMER_Type *)CTIMER4_BASE_NS)
6734   /** Array initializer of CTIMER peripheral base addresses */
6735   #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
6736   /** Array initializer of CTIMER peripheral base pointers */
6737   #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
6738   /** Array initializer of CTIMER peripheral base addresses */
6739   #define CTIMER_BASE_ADDRS_NS                     { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS }
6740   /** Array initializer of CTIMER peripheral base pointers */
6741   #define CTIMER_BASE_PTRS_NS                      { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS }
6742 #else
6743   /** Peripheral CTIMER0 base address */
6744   #define CTIMER0_BASE                             (0x40008000u)
6745   /** Peripheral CTIMER0 base pointer */
6746   #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
6747   /** Peripheral CTIMER1 base address */
6748   #define CTIMER1_BASE                             (0x40009000u)
6749   /** Peripheral CTIMER1 base pointer */
6750   #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
6751   /** Peripheral CTIMER2 base address */
6752   #define CTIMER2_BASE                             (0x40028000u)
6753   /** Peripheral CTIMER2 base pointer */
6754   #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
6755   /** Peripheral CTIMER3 base address */
6756   #define CTIMER3_BASE                             (0x40029000u)
6757   /** Peripheral CTIMER3 base pointer */
6758   #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
6759   /** Peripheral CTIMER4 base address */
6760   #define CTIMER4_BASE                             (0x4002A000u)
6761   /** Peripheral CTIMER4 base pointer */
6762   #define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
6763   /** Array initializer of CTIMER peripheral base addresses */
6764   #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
6765   /** Array initializer of CTIMER peripheral base pointers */
6766   #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
6767 #endif
6768 /** Interrupt vectors for the CTIMER peripheral type */
6769 #define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
6770 /* Backward compatibility for bitfield SHADOW */
6771 #define CTIMER_MSR_MATCH_SHADOW_MASK   CTIMER_MSR_SHADOW_MASK
6772 #define CTIMER_MSR_MATCH_SHADOW_SHIFT   CTIMER_MSR_SHADOW_SHIFT
6773 #define CTIMER_MSR_MATCH_SHADOW   CTIMER_MSR_SHADOW
6774 
6775 
6776 /*!
6777  * @}
6778  */ /* end of group CTIMER_Peripheral_Access_Layer */
6779 
6780 
6781 /* ----------------------------------------------------------------------------
6782    -- DBGMAILBOX Peripheral Access Layer
6783    ---------------------------------------------------------------------------- */
6784 
6785 /*!
6786  * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer
6787  * @{
6788  */
6789 
6790 /** DBGMAILBOX - Register Layout Typedef */
6791 typedef struct {
6792   __IO uint32_t CSW;                               /**< CRC mode register, offset: 0x0 */
6793   __IO uint32_t REQUEST;                           /**< CRC seed register, offset: 0x4 */
6794   __IO uint32_t RETURN;                            /**< Return value from ROM., offset: 0x8 */
6795        uint8_t RESERVED_0[240];
6796   __I  uint32_t ID;                                /**< Identification register, offset: 0xFC */
6797 } DBGMAILBOX_Type;
6798 
6799 /* ----------------------------------------------------------------------------
6800    -- DBGMAILBOX Register Masks
6801    ---------------------------------------------------------------------------- */
6802 
6803 /*!
6804  * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks
6805  * @{
6806  */
6807 
6808 /*! @name CSW - CRC mode register */
6809 /*! @{ */
6810 
6811 #define DBGMAILBOX_CSW_RESYNCH_REQ_MASK          (0x1U)
6812 #define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT         (0U)
6813 /*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation
6814  */
6815 #define DBGMAILBOX_CSW_RESYNCH_REQ(x)            (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK)
6816 
6817 #define DBGMAILBOX_CSW_REQ_PENDING_MASK          (0x2U)
6818 #define DBGMAILBOX_CSW_REQ_PENDING_SHIFT         (1U)
6819 /*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST)
6820  */
6821 #define DBGMAILBOX_CSW_REQ_PENDING(x)            (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK)
6822 
6823 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK           (0x4U)
6824 #define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT          (2U)
6825 /*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM)
6826  */
6827 #define DBGMAILBOX_CSW_DBG_OR_ERR(x)             (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
6828 
6829 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK           (0x8U)
6830 #define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT          (3U)
6831 /*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM)
6832  */
6833 #define DBGMAILBOX_CSW_AHB_OR_ERR(x)             (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
6834 
6835 #define DBGMAILBOX_CSW_SOFT_RESET_MASK           (0x10U)
6836 #define DBGMAILBOX_CSW_SOFT_RESET_SHIFT          (4U)
6837 /*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to
6838  *    this bit will cause a soft reset for DM.
6839  */
6840 #define DBGMAILBOX_CSW_SOFT_RESET(x)             (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK)
6841 
6842 #define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK       (0x20U)
6843 #define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT      (5U)
6844 /*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is
6845  *    not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event)
6846  */
6847 #define DBGMAILBOX_CSW_CHIP_RESET_REQ(x)         (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK)
6848 /*! @} */
6849 
6850 /*! @name REQUEST - CRC seed register */
6851 /*! @{ */
6852 
6853 #define DBGMAILBOX_REQUEST_REQ_MASK              (0xFFFFFFFFU)
6854 #define DBGMAILBOX_REQUEST_REQ_SHIFT             (0U)
6855 /*! REQ - Request Value
6856  */
6857 #define DBGMAILBOX_REQUEST_REQ(x)                (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK)
6858 /*! @} */
6859 
6860 /*! @name RETURN - Return value from ROM. */
6861 /*! @{ */
6862 
6863 #define DBGMAILBOX_RETURN_RET_MASK               (0xFFFFFFFFU)
6864 #define DBGMAILBOX_RETURN_RET_SHIFT              (0U)
6865 /*! RET - The Return value from ROM.
6866  */
6867 #define DBGMAILBOX_RETURN_RET(x)                 (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK)
6868 /*! @} */
6869 
6870 /*! @name ID - Identification register */
6871 /*! @{ */
6872 
6873 #define DBGMAILBOX_ID_ID_MASK                    (0xFFFFFFFFU)
6874 #define DBGMAILBOX_ID_ID_SHIFT                   (0U)
6875 /*! ID - Identification value.
6876  */
6877 #define DBGMAILBOX_ID_ID(x)                      (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK)
6878 /*! @} */
6879 
6880 
6881 /*!
6882  * @}
6883  */ /* end of group DBGMAILBOX_Register_Masks */
6884 
6885 
6886 /* DBGMAILBOX - Peripheral instance base addresses */
6887 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
6888   /** Peripheral DBGMAILBOX base address */
6889   #define DBGMAILBOX_BASE                          (0x5009C000u)
6890   /** Peripheral DBGMAILBOX base address */
6891   #define DBGMAILBOX_BASE_NS                       (0x4009C000u)
6892   /** Peripheral DBGMAILBOX base pointer */
6893   #define DBGMAILBOX                               ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
6894   /** Peripheral DBGMAILBOX base pointer */
6895   #define DBGMAILBOX_NS                            ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS)
6896   /** Array initializer of DBGMAILBOX peripheral base addresses */
6897   #define DBGMAILBOX_BASE_ADDRS                    { DBGMAILBOX_BASE }
6898   /** Array initializer of DBGMAILBOX peripheral base pointers */
6899   #define DBGMAILBOX_BASE_PTRS                     { DBGMAILBOX }
6900   /** Array initializer of DBGMAILBOX peripheral base addresses */
6901   #define DBGMAILBOX_BASE_ADDRS_NS                 { DBGMAILBOX_BASE_NS }
6902   /** Array initializer of DBGMAILBOX peripheral base pointers */
6903   #define DBGMAILBOX_BASE_PTRS_NS                  { DBGMAILBOX_NS }
6904 #else
6905   /** Peripheral DBGMAILBOX base address */
6906   #define DBGMAILBOX_BASE                          (0x4009C000u)
6907   /** Peripheral DBGMAILBOX base pointer */
6908   #define DBGMAILBOX                               ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
6909   /** Array initializer of DBGMAILBOX peripheral base addresses */
6910   #define DBGMAILBOX_BASE_ADDRS                    { DBGMAILBOX_BASE }
6911   /** Array initializer of DBGMAILBOX peripheral base pointers */
6912   #define DBGMAILBOX_BASE_PTRS                     { DBGMAILBOX }
6913 #endif
6914 
6915 /*!
6916  * @}
6917  */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */
6918 
6919 
6920 /* ----------------------------------------------------------------------------
6921    -- DMA Peripheral Access Layer
6922    ---------------------------------------------------------------------------- */
6923 
6924 /*!
6925  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
6926  * @{
6927  */
6928 
6929 /** DMA - Register Layout Typedef */
6930 typedef struct {
6931   __IO uint32_t CTRL;                              /**< DMA control., offset: 0x0 */
6932   __I  uint32_t INTSTAT;                           /**< Interrupt status., offset: 0x4 */
6933   __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table., offset: 0x8 */
6934        uint8_t RESERVED_0[20];
6935   struct {                                         /* offset: 0x20, array step: 0x5C */
6936     __IO uint32_t ENABLESET;                         /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
6937          uint8_t RESERVED_0[4];
6938     __O  uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
6939          uint8_t RESERVED_1[4];
6940     __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
6941          uint8_t RESERVED_2[4];
6942     __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
6943          uint8_t RESERVED_3[4];
6944     __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
6945          uint8_t RESERVED_4[4];
6946     __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
6947          uint8_t RESERVED_5[4];
6948     __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
6949          uint8_t RESERVED_6[4];
6950     __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
6951          uint8_t RESERVED_7[4];
6952     __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
6953          uint8_t RESERVED_8[4];
6954     __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
6955          uint8_t RESERVED_9[4];
6956     __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
6957          uint8_t RESERVED_10[4];
6958     __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
6959   } COMMON[1];
6960        uint8_t RESERVED_1[900];
6961   struct {                                         /* offset: 0x400, array step: 0x10 */
6962     __IO uint32_t CFG;                               /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
6963     __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
6964     __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
6965          uint8_t RESERVED_0[4];
6966   } CHANNEL[23];
6967 } DMA_Type;
6968 
6969 /* ----------------------------------------------------------------------------
6970    -- DMA Register Masks
6971    ---------------------------------------------------------------------------- */
6972 
6973 /*!
6974  * @addtogroup DMA_Register_Masks DMA Register Masks
6975  * @{
6976  */
6977 
6978 /*! @name CTRL - DMA control. */
6979 /*! @{ */
6980 
6981 #define DMA_CTRL_ENABLE_MASK                     (0x1U)
6982 #define DMA_CTRL_ENABLE_SHIFT                    (0U)
6983 /*! ENABLE - DMA controller master enable.
6984  *  0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
6985  *       disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
6986  *  0b1..Enabled. The DMA controller is enabled.
6987  */
6988 #define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
6989 /*! @} */
6990 
6991 /*! @name INTSTAT - Interrupt status. */
6992 /*! @{ */
6993 
6994 #define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
6995 #define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
6996 /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
6997  *  0b0..Not pending. No enabled interrupts are pending.
6998  *  0b1..Pending. At least one enabled interrupt is pending.
6999  */
7000 #define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
7001 
7002 #define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
7003 #define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
7004 /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
7005  *  0b0..Not pending. No error interrupts are pending.
7006  *  0b1..Pending. At least one error interrupt is pending.
7007  */
7008 #define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
7009 /*! @} */
7010 
7011 /*! @name SRAMBASE - SRAM address of the channel configuration table. */
7012 /*! @{ */
7013 
7014 #define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
7015 #define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
7016 /*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
7017  *    table must begin on a 512 byte boundary.
7018  */
7019 #define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
7020 /*! @} */
7021 
7022 /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
7023 /*! @{ */
7024 
7025 #define DMA_COMMON_ENABLESET_ENA_MASK            (0xFFFFFFFFU)
7026 #define DMA_COMMON_ENABLESET_ENA_SHIFT           (0U)
7027 /*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
7028  *    number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
7029  */
7030 #define DMA_COMMON_ENABLESET_ENA(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
7031 /*! @} */
7032 
7033 /* The count of DMA_COMMON_ENABLESET */
7034 #define DMA_COMMON_ENABLESET_COUNT               (1U)
7035 
7036 /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
7037 /*! @{ */
7038 
7039 #define DMA_COMMON_ENABLECLR_CLR_MASK            (0xFFFFFFFFU)
7040 #define DMA_COMMON_ENABLECLR_CLR_SHIFT           (0U)
7041 /*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
7042  *    the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
7043  *    are reserved.
7044  */
7045 #define DMA_COMMON_ENABLECLR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
7046 /*! @} */
7047 
7048 /* The count of DMA_COMMON_ENABLECLR */
7049 #define DMA_COMMON_ENABLECLR_COUNT               (1U)
7050 
7051 /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
7052 /*! @{ */
7053 
7054 #define DMA_COMMON_ACTIVE_ACT_MASK               (0xFFFFFFFFU)
7055 #define DMA_COMMON_ACTIVE_ACT_SHIFT              (0U)
7056 /*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
7057  *    number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
7058  */
7059 #define DMA_COMMON_ACTIVE_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
7060 /*! @} */
7061 
7062 /* The count of DMA_COMMON_ACTIVE */
7063 #define DMA_COMMON_ACTIVE_COUNT                  (1U)
7064 
7065 /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
7066 /*! @{ */
7067 
7068 #define DMA_COMMON_BUSY_BSY_MASK                 (0xFFFFFFFFU)
7069 #define DMA_COMMON_BUSY_BSY_SHIFT                (0U)
7070 /*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
7071  *    number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
7072  */
7073 #define DMA_COMMON_BUSY_BSY(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
7074 /*! @} */
7075 
7076 /* The count of DMA_COMMON_BUSY */
7077 #define DMA_COMMON_BUSY_COUNT                    (1U)
7078 
7079 /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
7080 /*! @{ */
7081 
7082 #define DMA_COMMON_ERRINT_ERR_MASK               (0xFFFFFFFFU)
7083 #define DMA_COMMON_ERRINT_ERR_SHIFT              (0U)
7084 /*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
7085  *    bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
7086  *    not active. 1 = error interrupt is active.
7087  */
7088 #define DMA_COMMON_ERRINT_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
7089 /*! @} */
7090 
7091 /* The count of DMA_COMMON_ERRINT */
7092 #define DMA_COMMON_ERRINT_COUNT                  (1U)
7093 
7094 /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
7095 /*! @{ */
7096 
7097 #define DMA_COMMON_INTENSET_INTEN_MASK           (0xFFFFFFFFU)
7098 #define DMA_COMMON_INTENSET_INTEN_SHIFT          (0U)
7099 /*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
7100  *    number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
7101  *    interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
7102  */
7103 #define DMA_COMMON_INTENSET_INTEN(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
7104 /*! @} */
7105 
7106 /* The count of DMA_COMMON_INTENSET */
7107 #define DMA_COMMON_INTENSET_COUNT                (1U)
7108 
7109 /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
7110 /*! @{ */
7111 
7112 #define DMA_COMMON_INTENCLR_CLR_MASK             (0xFFFFFFFFU)
7113 #define DMA_COMMON_INTENCLR_CLR_SHIFT            (0U)
7114 /*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
7115  *    corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
7116  *    reserved.
7117  */
7118 #define DMA_COMMON_INTENCLR_CLR(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
7119 /*! @} */
7120 
7121 /* The count of DMA_COMMON_INTENCLR */
7122 #define DMA_COMMON_INTENCLR_COUNT                (1U)
7123 
7124 /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
7125 /*! @{ */
7126 
7127 #define DMA_COMMON_INTA_IA_MASK                  (0xFFFFFFFFU)
7128 #define DMA_COMMON_INTA_IA_SHIFT                 (0U)
7129 /*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
7130  *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
7131  *    interrupt A is not active. 1 = the DMA channel interrupt A is active.
7132  */
7133 #define DMA_COMMON_INTA_IA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
7134 /*! @} */
7135 
7136 /* The count of DMA_COMMON_INTA */
7137 #define DMA_COMMON_INTA_COUNT                    (1U)
7138 
7139 /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
7140 /*! @{ */
7141 
7142 #define DMA_COMMON_INTB_IB_MASK                  (0xFFFFFFFFU)
7143 #define DMA_COMMON_INTB_IB_SHIFT                 (0U)
7144 /*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
7145  *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
7146  *    interrupt B is not active. 1 = the DMA channel interrupt B is active.
7147  */
7148 #define DMA_COMMON_INTB_IB(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
7149 /*! @} */
7150 
7151 /* The count of DMA_COMMON_INTB */
7152 #define DMA_COMMON_INTB_COUNT                    (1U)
7153 
7154 /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
7155 /*! @{ */
7156 
7157 #define DMA_COMMON_SETVALID_SV_MASK              (0xFFFFFFFFU)
7158 #define DMA_COMMON_SETVALID_SV_SHIFT             (0U)
7159 /*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
7160  *    = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
7161  *    VALIDPENDING control bit for DMA channel n
7162  */
7163 #define DMA_COMMON_SETVALID_SV(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
7164 /*! @} */
7165 
7166 /* The count of DMA_COMMON_SETVALID */
7167 #define DMA_COMMON_SETVALID_COUNT                (1U)
7168 
7169 /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
7170 /*! @{ */
7171 
7172 #define DMA_COMMON_SETTRIG_TRIG_MASK             (0xFFFFFFFFU)
7173 #define DMA_COMMON_SETTRIG_TRIG_SHIFT            (0U)
7174 /*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
7175  *    of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
7176  *    sets the TRIG bit for DMA channel n.
7177  */
7178 #define DMA_COMMON_SETTRIG_TRIG(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
7179 /*! @} */
7180 
7181 /* The count of DMA_COMMON_SETTRIG */
7182 #define DMA_COMMON_SETTRIG_COUNT                 (1U)
7183 
7184 /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
7185 /*! @{ */
7186 
7187 #define DMA_COMMON_ABORT_ABORTCTRL_MASK          (0xFFFFFFFFU)
7188 #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT         (0U)
7189 /*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
7190  *    1 = aborts DMA operations on channel n.
7191  */
7192 #define DMA_COMMON_ABORT_ABORTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
7193 /*! @} */
7194 
7195 /* The count of DMA_COMMON_ABORT */
7196 #define DMA_COMMON_ABORT_COUNT                   (1U)
7197 
7198 /*! @name CHANNEL_CFG - Configuration register for DMA channel . */
7199 /*! @{ */
7200 
7201 #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
7202 #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
7203 /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
7204  *    move, any peripheral DMA request associated with that channel can be disabled to prevent any
7205  *    interaction between the peripheral and the DMA controller.
7206  *  0b0..Disabled. Peripheral DMA requests are disabled.
7207  *  0b1..Enabled. Peripheral DMA requests are enabled.
7208  */
7209 #define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
7210 
7211 #define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
7212 #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
7213 /*! HWTRIGEN - Hardware Triggering Enable for this channel.
7214  *  0b0..Disabled. Hardware triggering is not used.
7215  *  0b1..Enabled. Use hardware triggering.
7216  */
7217 #define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
7218 
7219 #define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
7220 #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
7221 /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
7222  *  0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
7223  *  0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
7224  */
7225 #define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
7226 
7227 #define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
7228 #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
7229 /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
7230  *  0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
7231  *  0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
7232  *       0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
7233  *       trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
7234  *       is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
7235  *       current BURSTPOWER length are completed.
7236  */
7237 #define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
7238 
7239 #define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
7240 #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
7241 /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
7242  *  0b0..Single transfer. Hardware trigger causes a single transfer.
7243  *  0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
7244  *       burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
7245  *       hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
7246  *       complete.
7247  */
7248 #define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
7249 
7250 #define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
7251 #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
7252 /*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
7253  *    SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
7254  *    When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
7255  *    transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
7256  *    contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
7257  *    Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
7258  *    1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
7259  *    total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
7260  *    multiple of the burst size.
7261  */
7262 #define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
7263 
7264 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
7265 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
7266 /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
7267  *    'wrapped', meaning that the source address range for each burst will be the same. As an example, this
7268  *    could be used to read several sequential registers from a peripheral for each DMA burst,
7269  *    reading the same registers again for each burst.
7270  *  0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
7271  *  0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
7272  */
7273 #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
7274 
7275 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
7276 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
7277 /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
7278  *    'wrapped', meaning that the destination address range for each burst will be the same. As an
7279  *    example, this could be used to write several sequential registers to a peripheral for each DMA
7280  *    burst, writing the same registers again for each burst.
7281  *  0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
7282  *  0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
7283  */
7284 #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
7285 
7286 #define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
7287 #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
7288 /*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
7289  *    levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
7290  */
7291 #define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
7292 /*! @} */
7293 
7294 /* The count of DMA_CHANNEL_CFG */
7295 #define DMA_CHANNEL_CFG_COUNT                    (23U)
7296 
7297 /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
7298 /*! @{ */
7299 
7300 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
7301 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
7302 /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
7303  *    corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
7304  *  0b0..No effect. No effect on DMA operation.
7305  *  0b1..Valid pending.
7306  */
7307 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
7308 
7309 #define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
7310 #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
7311 /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
7312  *    cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
7313  *  0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
7314  *  0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
7315  */
7316 #define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
7317 /*! @} */
7318 
7319 /* The count of DMA_CHANNEL_CTLSTAT */
7320 #define DMA_CHANNEL_CTLSTAT_COUNT                (23U)
7321 
7322 /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
7323 /*! @{ */
7324 
7325 #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
7326 #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
7327 /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
7328  *    is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
7329  *  0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
7330  *  0b1..Valid. The current channel descriptor is considered valid.
7331  */
7332 #define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
7333 
7334 #define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
7335 #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
7336 /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
7337  *    descriptor is exhausted. Reloading allows ping-pong and linked transfers.
7338  *  0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
7339  *  0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
7340  */
7341 #define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
7342 
7343 #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
7344 #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
7345 /*! SWTRIG - Software Trigger.
7346  *  0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
7347  *       the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
7348  *  0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
7349  *       be used with level triggering when TRIGBURST = 0.
7350  */
7351 #define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
7352 
7353 #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
7354 #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
7355 /*! CLRTRIG - Clear Trigger.
7356  *  0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
7357  *  0b1..Cleared. The trigger is cleared when this descriptor is exhausted
7358  */
7359 #define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
7360 
7361 #define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
7362 #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
7363 /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
7364  *    interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
7365  *    convention, interrupt A may be used when only one interrupt flag is needed.
7366  *  0b0..No effect.
7367  *  0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
7368  */
7369 #define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
7370 
7371 #define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
7372 #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
7373 /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
7374  *    interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
7375  *    convention, interrupt A may be used when only one interrupt flag is needed.
7376  *  0b0..No effect.
7377  *  0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
7378  */
7379 #define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
7380 
7381 #define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
7382 #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
7383 /*! WIDTH - Transfer width used for this DMA channel.
7384  *  0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
7385  *  0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
7386  *  0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
7387  *  0b11..Reserved. Reserved setting, do not use.
7388  */
7389 #define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
7390 
7391 #define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
7392 #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
7393 /*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
7394  *  0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
7395  *  0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
7396  *        the usual case when the source is memory.
7397  *  0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
7398  *  0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
7399  */
7400 #define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
7401 
7402 #define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
7403 #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
7404 /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
7405  *  0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
7406  *        the destination is a peripheral device.
7407  *  0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
7408  *        This is the usual case when the destination is memory.
7409  *  0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
7410  *  0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
7411  */
7412 #define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
7413 
7414 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
7415 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
7416 /*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
7417  *    transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
7418  *    uses this bit field during transfer to count down. Hence, it cannot be used by software to read
7419  *    back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
7420  *    transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
7421  *    1,024 transfers will be performed.
7422  */
7423 #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
7424 /*! @} */
7425 
7426 /* The count of DMA_CHANNEL_XFERCFG */
7427 #define DMA_CHANNEL_XFERCFG_COUNT                (23U)
7428 
7429 
7430 /*!
7431  * @}
7432  */ /* end of group DMA_Register_Masks */
7433 
7434 
7435 /* DMA - Peripheral instance base addresses */
7436 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
7437   /** Peripheral DMA0 base address */
7438   #define DMA0_BASE                                (0x50082000u)
7439   /** Peripheral DMA0 base address */
7440   #define DMA0_BASE_NS                             (0x40082000u)
7441   /** Peripheral DMA0 base pointer */
7442   #define DMA0                                     ((DMA_Type *)DMA0_BASE)
7443   /** Peripheral DMA0 base pointer */
7444   #define DMA0_NS                                  ((DMA_Type *)DMA0_BASE_NS)
7445   /** Peripheral DMA1 base address */
7446   #define DMA1_BASE                                (0x500A7000u)
7447   /** Peripheral DMA1 base address */
7448   #define DMA1_BASE_NS                             (0x400A7000u)
7449   /** Peripheral DMA1 base pointer */
7450   #define DMA1                                     ((DMA_Type *)DMA1_BASE)
7451   /** Peripheral DMA1 base pointer */
7452   #define DMA1_NS                                  ((DMA_Type *)DMA1_BASE_NS)
7453   /** Array initializer of DMA peripheral base addresses */
7454   #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
7455   /** Array initializer of DMA peripheral base pointers */
7456   #define DMA_BASE_PTRS                            { DMA0, DMA1 }
7457   /** Array initializer of DMA peripheral base addresses */
7458   #define DMA_BASE_ADDRS_NS                        { DMA0_BASE_NS, DMA1_BASE_NS }
7459   /** Array initializer of DMA peripheral base pointers */
7460   #define DMA_BASE_PTRS_NS                         { DMA0_NS, DMA1_NS }
7461 #else
7462   /** Peripheral DMA0 base address */
7463   #define DMA0_BASE                                (0x40082000u)
7464   /** Peripheral DMA0 base pointer */
7465   #define DMA0                                     ((DMA_Type *)DMA0_BASE)
7466   /** Peripheral DMA1 base address */
7467   #define DMA1_BASE                                (0x400A7000u)
7468   /** Peripheral DMA1 base pointer */
7469   #define DMA1                                     ((DMA_Type *)DMA1_BASE)
7470   /** Array initializer of DMA peripheral base addresses */
7471   #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
7472   /** Array initializer of DMA peripheral base pointers */
7473   #define DMA_BASE_PTRS                            { DMA0, DMA1 }
7474 #endif
7475 /** Interrupt vectors for the DMA peripheral type */
7476 #define DMA_IRQS                                 { DMA0_IRQn, DMA1_IRQn }
7477 
7478 /*!
7479  * @}
7480  */ /* end of group DMA_Peripheral_Access_Layer */
7481 
7482 
7483 /* ----------------------------------------------------------------------------
7484    -- FLASH Peripheral Access Layer
7485    ---------------------------------------------------------------------------- */
7486 
7487 /*!
7488  * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer
7489  * @{
7490  */
7491 
7492 /** FLASH - Register Layout Typedef */
7493 typedef struct {
7494   __O  uint32_t CMD;                               /**< command register, offset: 0x0 */
7495   __O  uint32_t EVENT;                             /**< event register, offset: 0x4 */
7496        uint8_t RESERVED_0[8];
7497   __IO uint32_t STARTA;                            /**< start (or only) address for next flash command, offset: 0x10 */
7498   __IO uint32_t STOPA;                             /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */
7499        uint8_t RESERVED_1[104];
7500   __IO uint32_t DATAW[4];                          /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */
7501        uint8_t RESERVED_2[3912];
7502   __O  uint32_t INT_CLR_ENABLE;                    /**< Clear interrupt enable bits, offset: 0xFD8 */
7503   __O  uint32_t INT_SET_ENABLE;                    /**< Set interrupt enable bits, offset: 0xFDC */
7504   __I  uint32_t INT_STATUS;                        /**< Interrupt status bits, offset: 0xFE0 */
7505   __I  uint32_t INT_ENABLE;                        /**< Interrupt enable bits, offset: 0xFE4 */
7506   __O  uint32_t INT_CLR_STATUS;                    /**< Clear interrupt status bits, offset: 0xFE8 */
7507   __O  uint32_t INT_SET_STATUS;                    /**< Set interrupt status bits, offset: 0xFEC */
7508        uint8_t RESERVED_3[12];
7509   __I  uint32_t MODULE_ID;                         /**< Controller+Memory module identification, offset: 0xFFC */
7510 } FLASH_Type;
7511 
7512 /* ----------------------------------------------------------------------------
7513    -- FLASH Register Masks
7514    ---------------------------------------------------------------------------- */
7515 
7516 /*!
7517  * @addtogroup FLASH_Register_Masks FLASH Register Masks
7518  * @{
7519  */
7520 
7521 /*! @name CMD - command register */
7522 /*! @{ */
7523 
7524 #define FLASH_CMD_CMD_MASK                       (0xFFFFFFFFU)
7525 #define FLASH_CMD_CMD_SHIFT                      (0U)
7526 /*! CMD - command register.
7527  */
7528 #define FLASH_CMD_CMD(x)                         (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK)
7529 /*! @} */
7530 
7531 /*! @name EVENT - event register */
7532 /*! @{ */
7533 
7534 #define FLASH_EVENT_RST_MASK                     (0x1U)
7535 #define FLASH_EVENT_RST_SHIFT                    (0U)
7536 /*! RST - When bit is set, the controller and flash are reset.
7537  */
7538 #define FLASH_EVENT_RST(x)                       (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK)
7539 
7540 #define FLASH_EVENT_WAKEUP_MASK                  (0x2U)
7541 #define FLASH_EVENT_WAKEUP_SHIFT                 (1U)
7542 /*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active.
7543  */
7544 #define FLASH_EVENT_WAKEUP(x)                    (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK)
7545 
7546 #define FLASH_EVENT_ABORT_MASK                   (0x4U)
7547 #define FLASH_EVENT_ABORT_SHIFT                  (2U)
7548 /*! ABORT - When bit is set, a running program/erase command is aborted.
7549  */
7550 #define FLASH_EVENT_ABORT(x)                     (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK)
7551 /*! @} */
7552 
7553 /*! @name STARTA - start (or only) address for next flash command */
7554 /*! @{ */
7555 
7556 #define FLASH_STARTA_STARTA_MASK                 (0x3FFFFU)
7557 #define FLASH_STARTA_STARTA_SHIFT                (0U)
7558 /*! STARTA - Address / Start address for commands that take an address (range) as a parameter.
7559  */
7560 #define FLASH_STARTA_STARTA(x)                   (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK)
7561 /*! @} */
7562 
7563 /*! @name STOPA - end address for next flash command, if command operates on address ranges */
7564 /*! @{ */
7565 
7566 #define FLASH_STOPA_STOPA_MASK                   (0x3FFFFU)
7567 #define FLASH_STOPA_STOPA_SHIFT                  (0U)
7568 /*! STOPA - Stop address for commands that take an address range as a parameter (the word specified
7569  *    by STOPA is included in the address range).
7570  */
7571 #define FLASH_STOPA_STOPA(x)                     (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK)
7572 /*! @} */
7573 
7574 /*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */
7575 /*! @{ */
7576 
7577 #define FLASH_DATAW_DATAW_MASK                   (0xFFFFFFFFU)
7578 #define FLASH_DATAW_DATAW_SHIFT                  (0U)
7579 #define FLASH_DATAW_DATAW(x)                     (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK)
7580 /*! @} */
7581 
7582 /* The count of FLASH_DATAW */
7583 #define FLASH_DATAW_COUNT                        (4U)
7584 
7585 /*! @name INT_CLR_ENABLE - Clear interrupt enable bits */
7586 /*! @{ */
7587 
7588 #define FLASH_INT_CLR_ENABLE_FAIL_MASK           (0x1U)
7589 #define FLASH_INT_CLR_ENABLE_FAIL_SHIFT          (0U)
7590 /*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
7591  */
7592 #define FLASH_INT_CLR_ENABLE_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK)
7593 
7594 #define FLASH_INT_CLR_ENABLE_ERR_MASK            (0x2U)
7595 #define FLASH_INT_CLR_ENABLE_ERR_SHIFT           (1U)
7596 /*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
7597  */
7598 #define FLASH_INT_CLR_ENABLE_ERR(x)              (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK)
7599 
7600 #define FLASH_INT_CLR_ENABLE_DONE_MASK           (0x4U)
7601 #define FLASH_INT_CLR_ENABLE_DONE_SHIFT          (2U)
7602 /*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
7603  */
7604 #define FLASH_INT_CLR_ENABLE_DONE(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK)
7605 
7606 #define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK        (0x8U)
7607 #define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT       (3U)
7608 /*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
7609  */
7610 #define FLASH_INT_CLR_ENABLE_ECC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK)
7611 /*! @} */
7612 
7613 /*! @name INT_SET_ENABLE - Set interrupt enable bits */
7614 /*! @{ */
7615 
7616 #define FLASH_INT_SET_ENABLE_FAIL_MASK           (0x1U)
7617 #define FLASH_INT_SET_ENABLE_FAIL_SHIFT          (0U)
7618 /*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
7619  */
7620 #define FLASH_INT_SET_ENABLE_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK)
7621 
7622 #define FLASH_INT_SET_ENABLE_ERR_MASK            (0x2U)
7623 #define FLASH_INT_SET_ENABLE_ERR_SHIFT           (1U)
7624 /*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
7625  */
7626 #define FLASH_INT_SET_ENABLE_ERR(x)              (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK)
7627 
7628 #define FLASH_INT_SET_ENABLE_DONE_MASK           (0x4U)
7629 #define FLASH_INT_SET_ENABLE_DONE_SHIFT          (2U)
7630 /*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
7631  */
7632 #define FLASH_INT_SET_ENABLE_DONE(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK)
7633 
7634 #define FLASH_INT_SET_ENABLE_ECC_ERR_MASK        (0x8U)
7635 #define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT       (3U)
7636 /*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
7637  */
7638 #define FLASH_INT_SET_ENABLE_ECC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK)
7639 /*! @} */
7640 
7641 /*! @name INT_STATUS - Interrupt status bits */
7642 /*! @{ */
7643 
7644 #define FLASH_INT_STATUS_FAIL_MASK               (0x1U)
7645 #define FLASH_INT_STATUS_FAIL_SHIFT              (0U)
7646 /*! FAIL - This status bit is set if execution of a (legal) command failed.
7647  */
7648 #define FLASH_INT_STATUS_FAIL(x)                 (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK)
7649 
7650 #define FLASH_INT_STATUS_ERR_MASK                (0x2U)
7651 #define FLASH_INT_STATUS_ERR_SHIFT               (1U)
7652 /*! ERR - This status bit is set if execution of an illegal command is detected.
7653  */
7654 #define FLASH_INT_STATUS_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK)
7655 
7656 #define FLASH_INT_STATUS_DONE_MASK               (0x4U)
7657 #define FLASH_INT_STATUS_DONE_SHIFT              (2U)
7658 /*! DONE - This status bit is set at the end of command execution.
7659  */
7660 #define FLASH_INT_STATUS_DONE(x)                 (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK)
7661 
7662 #define FLASH_INT_STATUS_ECC_ERR_MASK            (0x8U)
7663 #define FLASH_INT_STATUS_ECC_ERR_SHIFT           (3U)
7664 /*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested
7665  *    read, or a speculative read, or reads performed by a controller command), a correctable or
7666  *    uncorrectable error is detected by ECC decoding logic.
7667  */
7668 #define FLASH_INT_STATUS_ECC_ERR(x)              (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK)
7669 /*! @} */
7670 
7671 /*! @name INT_ENABLE - Interrupt enable bits */
7672 /*! @{ */
7673 
7674 #define FLASH_INT_ENABLE_FAIL_MASK               (0x1U)
7675 #define FLASH_INT_ENABLE_FAIL_SHIFT              (0U)
7676 /*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
7677  */
7678 #define FLASH_INT_ENABLE_FAIL(x)                 (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK)
7679 
7680 #define FLASH_INT_ENABLE_ERR_MASK                (0x2U)
7681 #define FLASH_INT_ENABLE_ERR_SHIFT               (1U)
7682 /*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
7683  */
7684 #define FLASH_INT_ENABLE_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK)
7685 
7686 #define FLASH_INT_ENABLE_DONE_MASK               (0x4U)
7687 #define FLASH_INT_ENABLE_DONE_SHIFT              (2U)
7688 /*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
7689  */
7690 #define FLASH_INT_ENABLE_DONE(x)                 (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK)
7691 
7692 #define FLASH_INT_ENABLE_ECC_ERR_MASK            (0x8U)
7693 #define FLASH_INT_ENABLE_ECC_ERR_SHIFT           (3U)
7694 /*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
7695  */
7696 #define FLASH_INT_ENABLE_ECC_ERR(x)              (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK)
7697 /*! @} */
7698 
7699 /*! @name INT_CLR_STATUS - Clear interrupt status bits */
7700 /*! @{ */
7701 
7702 #define FLASH_INT_CLR_STATUS_FAIL_MASK           (0x1U)
7703 #define FLASH_INT_CLR_STATUS_FAIL_SHIFT          (0U)
7704 /*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
7705  */
7706 #define FLASH_INT_CLR_STATUS_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK)
7707 
7708 #define FLASH_INT_CLR_STATUS_ERR_MASK            (0x2U)
7709 #define FLASH_INT_CLR_STATUS_ERR_SHIFT           (1U)
7710 /*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
7711  */
7712 #define FLASH_INT_CLR_STATUS_ERR(x)              (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK)
7713 
7714 #define FLASH_INT_CLR_STATUS_DONE_MASK           (0x4U)
7715 #define FLASH_INT_CLR_STATUS_DONE_SHIFT          (2U)
7716 /*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
7717  */
7718 #define FLASH_INT_CLR_STATUS_DONE(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK)
7719 
7720 #define FLASH_INT_CLR_STATUS_ECC_ERR_MASK        (0x8U)
7721 #define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT       (3U)
7722 /*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
7723  */
7724 #define FLASH_INT_CLR_STATUS_ECC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK)
7725 /*! @} */
7726 
7727 /*! @name INT_SET_STATUS - Set interrupt status bits */
7728 /*! @{ */
7729 
7730 #define FLASH_INT_SET_STATUS_FAIL_MASK           (0x1U)
7731 #define FLASH_INT_SET_STATUS_FAIL_SHIFT          (0U)
7732 /*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
7733  */
7734 #define FLASH_INT_SET_STATUS_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK)
7735 
7736 #define FLASH_INT_SET_STATUS_ERR_MASK            (0x2U)
7737 #define FLASH_INT_SET_STATUS_ERR_SHIFT           (1U)
7738 /*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
7739  */
7740 #define FLASH_INT_SET_STATUS_ERR(x)              (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK)
7741 
7742 #define FLASH_INT_SET_STATUS_DONE_MASK           (0x4U)
7743 #define FLASH_INT_SET_STATUS_DONE_SHIFT          (2U)
7744 /*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
7745  */
7746 #define FLASH_INT_SET_STATUS_DONE(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK)
7747 
7748 #define FLASH_INT_SET_STATUS_ECC_ERR_MASK        (0x8U)
7749 #define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT       (3U)
7750 /*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
7751  */
7752 #define FLASH_INT_SET_STATUS_ECC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK)
7753 /*! @} */
7754 
7755 /*! @name MODULE_ID - Controller+Memory module identification */
7756 /*! @{ */
7757 
7758 #define FLASH_MODULE_ID_APERTURE_MASK            (0xFFU)
7759 #define FLASH_MODULE_ID_APERTURE_SHIFT           (0U)
7760 /*! APERTURE - Aperture i.
7761  */
7762 #define FLASH_MODULE_ID_APERTURE(x)              (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK)
7763 
7764 #define FLASH_MODULE_ID_MINOR_REV_MASK           (0xF00U)
7765 #define FLASH_MODULE_ID_MINOR_REV_SHIFT          (8U)
7766 /*! MINOR_REV - Minor revision i.
7767  */
7768 #define FLASH_MODULE_ID_MINOR_REV(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK)
7769 
7770 #define FLASH_MODULE_ID_MAJOR_REV_MASK           (0xF000U)
7771 #define FLASH_MODULE_ID_MAJOR_REV_SHIFT          (12U)
7772 /*! MAJOR_REV - Major revision i.
7773  */
7774 #define FLASH_MODULE_ID_MAJOR_REV(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK)
7775 
7776 #define FLASH_MODULE_ID_ID_MASK                  (0xFFFF0000U)
7777 #define FLASH_MODULE_ID_ID_SHIFT                 (16U)
7778 /*! ID - Identifier.
7779  */
7780 #define FLASH_MODULE_ID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK)
7781 /*! @} */
7782 
7783 
7784 /*!
7785  * @}
7786  */ /* end of group FLASH_Register_Masks */
7787 
7788 
7789 /* FLASH - Peripheral instance base addresses */
7790 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
7791   /** Peripheral FLASH base address */
7792   #define FLASH_BASE                               (0x50034000u)
7793   /** Peripheral FLASH base address */
7794   #define FLASH_BASE_NS                            (0x40034000u)
7795   /** Peripheral FLASH base pointer */
7796   #define FLASH                                    ((FLASH_Type *)FLASH_BASE)
7797   /** Peripheral FLASH base pointer */
7798   #define FLASH_NS                                 ((FLASH_Type *)FLASH_BASE_NS)
7799   /** Array initializer of FLASH peripheral base addresses */
7800   #define FLASH_BASE_ADDRS                         { FLASH_BASE }
7801   /** Array initializer of FLASH peripheral base pointers */
7802   #define FLASH_BASE_PTRS                          { FLASH }
7803   /** Array initializer of FLASH peripheral base addresses */
7804   #define FLASH_BASE_ADDRS_NS                      { FLASH_BASE_NS }
7805   /** Array initializer of FLASH peripheral base pointers */
7806   #define FLASH_BASE_PTRS_NS                       { FLASH_NS }
7807 #else
7808   /** Peripheral FLASH base address */
7809   #define FLASH_BASE                               (0x40034000u)
7810   /** Peripheral FLASH base pointer */
7811   #define FLASH                                    ((FLASH_Type *)FLASH_BASE)
7812   /** Array initializer of FLASH peripheral base addresses */
7813   #define FLASH_BASE_ADDRS                         { FLASH_BASE }
7814   /** Array initializer of FLASH peripheral base pointers */
7815   #define FLASH_BASE_PTRS                          { FLASH }
7816 #endif
7817 
7818 /*!
7819  * @}
7820  */ /* end of group FLASH_Peripheral_Access_Layer */
7821 
7822 
7823 /* ----------------------------------------------------------------------------
7824    -- FLASH_CFPA Peripheral Access Layer
7825    ---------------------------------------------------------------------------- */
7826 
7827 /*!
7828  * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer
7829  * @{
7830  */
7831 
7832 /** FLASH_CFPA - Register Layout Typedef */
7833 typedef struct {
7834   __IO uint32_t HEADER;                            /**< , offset: 0x0 */
7835   __IO uint32_t VERSION;                           /**< , offset: 0x4 */
7836   __IO uint32_t S_FW_VERSION;                      /**< Secure firmware version (Monotonic counter), offset: 0x8 */
7837   __IO uint32_t NS_FW_VERSION;                     /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */
7838   __IO uint32_t IMAGE_KEY_REVOKE;                  /**< Image key revocation ID (Monotonic counter), offset: 0x10 */
7839        uint8_t RESERVED_0[4];
7840   __IO uint32_t ROTKH_REVOKE;                      /**< , offset: 0x18 */
7841   __IO uint32_t VENDOR_USAGE;                      /**< , offset: 0x1C */
7842   __IO uint32_t DCFG_CC_SOCU_PIN;                  /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */
7843   __IO uint32_t DCFG_CC_SOCU_DFLT;                 /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */
7844   __IO uint32_t ENABLE_FA_MODE;                    /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */
7845   __IO uint32_t CMPA_PROG_IN_PROGRESS;             /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */
7846   union {                                          /* offset: 0x30 */
7847     __IO uint32_t PRINCE_REGION0_IV_CODE[14];        /**< , array offset: 0x30, array step: 0x4 */
7848     struct {                                         /* offset: 0x30 */
7849       __IO uint32_t PRINCE_REGION0_IV_HEADER0;         /**< , offset: 0x30 */
7850       __IO uint32_t PRINCE_REGION0_IV_HEADER1;         /**< , offset: 0x34 */
7851       __IO uint32_t PRINCE_REGION0_IV_BODY[12];        /**< , array offset: 0x38, array step: 0x4 */
7852     } PRINCE_REGION0_IV_CODE_CORE;
7853   };
7854   union {                                          /* offset: 0x68 */
7855     __IO uint32_t PRINCE_REGION1_IV_CODE[14];        /**< , array offset: 0x68, array step: 0x4 */
7856     struct {                                         /* offset: 0x68 */
7857       __IO uint32_t PRINCE_REGION1_IV_HEADER0;         /**< , offset: 0x68 */
7858       __IO uint32_t PRINCE_REGION1_IV_HEADER1;         /**< , offset: 0x6C */
7859       __IO uint32_t PRINCE_REGION1_IV_BODY[12];        /**< , array offset: 0x70, array step: 0x4 */
7860     } PRINCE_REGION1_IV_CODE_CORE;
7861   };
7862   union {                                          /* offset: 0xA0 */
7863     __IO uint32_t PRINCE_REGION2_IV_CODE[14];        /**< , array offset: 0xA0, array step: 0x4 */
7864     struct {                                         /* offset: 0xA0 */
7865       __IO uint32_t PRINCE_REGION2_IV_HEADER0;         /**< , offset: 0xA0 */
7866       __IO uint32_t PRINCE_REGION2_IV_HEADER1;         /**< , offset: 0xA4 */
7867       __IO uint32_t PRINCE_REGION2_IV_BODY[12];        /**< , array offset: 0xA8, array step: 0x4 */
7868     } PRINCE_REGION2_IV_CODE_CORE;
7869   };
7870        uint8_t RESERVED_1[40];
7871   __IO uint32_t CUSTOMER_DEFINED[56];              /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */
7872   __IO uint32_t SHA256_DIGEST[8];                  /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */
7873 } FLASH_CFPA_Type;
7874 
7875 /* ----------------------------------------------------------------------------
7876    -- FLASH_CFPA Register Masks
7877    ---------------------------------------------------------------------------- */
7878 
7879 /*!
7880  * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks
7881  * @{
7882  */
7883 
7884 /*! @name HEADER -  */
7885 /*! @{ */
7886 
7887 #define FLASH_CFPA_HEADER_FIELD_MASK             (0xFFFFFFFFU)
7888 #define FLASH_CFPA_HEADER_FIELD_SHIFT            (0U)
7889 #define FLASH_CFPA_HEADER_FIELD(x)               (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK)
7890 /*! @} */
7891 
7892 /*! @name VERSION -  */
7893 /*! @{ */
7894 
7895 #define FLASH_CFPA_VERSION_FIELD_MASK            (0xFFFFFFFFU)
7896 #define FLASH_CFPA_VERSION_FIELD_SHIFT           (0U)
7897 #define FLASH_CFPA_VERSION_FIELD(x)              (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK)
7898 /*! @} */
7899 
7900 /*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */
7901 /*! @{ */
7902 
7903 #define FLASH_CFPA_S_FW_VERSION_FIELD_MASK       (0xFFFFFFFFU)
7904 #define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT      (0U)
7905 #define FLASH_CFPA_S_FW_VERSION_FIELD(x)         (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK)
7906 /*! @} */
7907 
7908 /*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */
7909 /*! @{ */
7910 
7911 #define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK      (0xFFFFFFFFU)
7912 #define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT     (0U)
7913 #define FLASH_CFPA_NS_FW_VERSION_FIELD(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK)
7914 /*! @} */
7915 
7916 /*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */
7917 /*! @{ */
7918 
7919 #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK   (0xFFFFFFFFU)
7920 #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT  (0U)
7921 #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK)
7922 /*! @} */
7923 
7924 /*! @name ROTKH_REVOKE -  */
7925 /*! @{ */
7926 
7927 #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK    (0x3U)
7928 #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT   (0U)
7929 /*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
7930  */
7931 #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK)
7932 
7933 #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK    (0xCU)
7934 #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT   (2U)
7935 /*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
7936  */
7937 #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK)
7938 
7939 #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK    (0x30U)
7940 #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT   (4U)
7941 /*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
7942  */
7943 #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK)
7944 
7945 #define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK    (0xC0U)
7946 #define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT   (6U)
7947 /*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
7948  */
7949 #define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK)
7950 /*! @} */
7951 
7952 /*! @name VENDOR_USAGE -  */
7953 /*! @{ */
7954 
7955 #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU)
7956 #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U)
7957 /*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE.
7958  */
7959 #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK)
7960 
7961 #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U)
7962 #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U)
7963 /*! INVERSE_VALUE - inverse value of bits [15:0]
7964  */
7965 #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK)
7966 /*! @} */
7967 
7968 /*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */
7969 /*! @{ */
7970 
7971 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK   (0x1U)
7972 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT  (0U)
7973 /*! NIDEN - Non Secure non-invasive debug enable
7974  *  0b0..Use DAP to enable
7975  *  0b1..Fixed state
7976  */
7977 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK)
7978 
7979 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK   (0x2U)
7980 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT  (1U)
7981 /*! DBGEN - Non Secure debug enable
7982  *  0b0..Use DAP to enable
7983  *  0b1..Fixed state
7984  */
7985 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK)
7986 
7987 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U)
7988 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U)
7989 /*! SPNIDEN - Secure non-invasive debug enable
7990  *  0b0..Use DAP to enable
7991  *  0b1..Fixed state
7992  */
7993 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x)   (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK)
7994 
7995 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK  (0x8U)
7996 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U)
7997 /*! SPIDEN - Secure invasive debug enable
7998  *  0b0..Use DAP to enable
7999  *  0b1..Fixed state
8000  */
8001 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK)
8002 
8003 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK   (0x10U)
8004 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT  (4U)
8005 /*! TAPEN - JTAG TAP enable
8006  *  0b0..Use DAP to enable
8007  *  0b1..Fixed state
8008  */
8009 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK)
8010 
8011 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U)
8012 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U)
8013 /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable
8014  *  0b0..Use DAP to enable
8015  *  0b1..Fixed state
8016  */
8017 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK)
8018 
8019 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U)
8020 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U)
8021 /*! ISP_CMD_EN - ISP Boot Command enable
8022  *  0b0..Use DAP to enable
8023  *  0b1..Fixed state
8024  */
8025 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK)
8026 
8027 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U)
8028 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U)
8029 /*! FA_CMD_EN - FA Command enable
8030  *  0b0..Use DAP to enable
8031  *  0b1..Fixed state
8032  */
8033 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK)
8034 
8035 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U)
8036 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U)
8037 /*! ME_CMD_EN - Flash Mass Erase Command enable
8038  *  0b0..Use DAP to enable
8039  *  0b1..Fixed state
8040  */
8041 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK)
8042 
8043 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U)
8044 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U)
8045 /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable
8046  *  0b0..Use DAP to enable
8047  *  0b1..Fixed state
8048  */
8049 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK)
8050 
8051 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U)
8052 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U)
8053 /*! UUID_CHECK - Enforce UUID match during Debug authentication.
8054  */
8055 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK)
8056 
8057 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U)
8058 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U)
8059 /*! INVERSE_VALUE - inverse value of bits [15:0]
8060  */
8061 #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK)
8062 /*! @} */
8063 
8064 /*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */
8065 /*! @{ */
8066 
8067 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK  (0x1U)
8068 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U)
8069 /*! NIDEN - Non Secure non-invasive debug fixed state
8070  *  0b0..Disable
8071  *  0b1..Enable
8072  */
8073 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK)
8074 
8075 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK  (0x2U)
8076 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U)
8077 /*! DBGEN - Non Secure debug fixed state
8078  *  0b0..Disable
8079  *  0b1..Enable
8080  */
8081 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK)
8082 
8083 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U)
8084 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U)
8085 /*! SPNIDEN - Secure non-invasive debug fixed state
8086  *  0b0..Disable
8087  *  0b1..Enable
8088  */
8089 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK)
8090 
8091 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U)
8092 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U)
8093 /*! SPIDEN - Secure invasive debug fixed state
8094  *  0b0..Disable
8095  *  0b1..Enable
8096  */
8097 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x)   (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK)
8098 
8099 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK  (0x10U)
8100 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U)
8101 /*! TAPEN - JTAG TAP fixed state
8102  *  0b0..Disable
8103  *  0b1..Enable
8104  */
8105 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK)
8106 
8107 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U)
8108 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U)
8109 /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state
8110  *  0b0..Disable
8111  *  0b1..Enable
8112  */
8113 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK)
8114 
8115 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U)
8116 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U)
8117 /*! ISP_CMD_EN - ISP Boot Command fixed state
8118  *  0b0..Disable
8119  *  0b1..Enable
8120  */
8121 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK)
8122 
8123 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U)
8124 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U)
8125 /*! FA_CMD_EN - FA Command fixed state
8126  *  0b0..Disable
8127  *  0b1..Enable
8128  */
8129 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK)
8130 
8131 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U)
8132 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U)
8133 /*! ME_CMD_EN - Flash Mass Erase Command fixed state
8134  *  0b0..Disable
8135  *  0b1..Enable
8136  */
8137 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK)
8138 
8139 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U)
8140 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U)
8141 /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state
8142  *  0b0..Disable
8143  *  0b1..Enable
8144  */
8145 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK)
8146 
8147 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U)
8148 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U)
8149 /*! INVERSE_VALUE - inverse value of bits [15:0]
8150  */
8151 #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK)
8152 /*! @} */
8153 
8154 /*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */
8155 /*! @{ */
8156 
8157 #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK     (0xFFFFFFFFU)
8158 #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT    (0U)
8159 #define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x)       (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK)
8160 /*! @} */
8161 
8162 /*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */
8163 /*! @{ */
8164 
8165 #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU)
8166 #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U)
8167 #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK)
8168 /*! @} */
8169 
8170 /*! @name PRINCE_REGION0_IV_CODE -  */
8171 /*! @{ */
8172 
8173 #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU)
8174 #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U)
8175 #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK)
8176 /*! @} */
8177 
8178 /* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */
8179 #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT  (14U)
8180 
8181 /*! @name PRINCE_REGION0_IV_HEADER0 -  */
8182 /*! @{ */
8183 
8184 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)
8185 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U)
8186 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK)
8187 /*! @} */
8188 
8189 /*! @name PRINCE_REGION0_IV_HEADER1 -  */
8190 /*! @{ */
8191 
8192 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U)
8193 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U)
8194 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK)
8195 
8196 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U)
8197 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U)
8198 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK)
8199 
8200 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U)
8201 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U)
8202 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK)
8203 /*! @} */
8204 
8205 /*! @name PRINCE_REGION0_IV_BODY -  */
8206 /*! @{ */
8207 
8208 #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU)
8209 #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U)
8210 #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK)
8211 /*! @} */
8212 
8213 /* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */
8214 #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT  (12U)
8215 
8216 /*! @name PRINCE_REGION1_IV_CODE -  */
8217 /*! @{ */
8218 
8219 #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU)
8220 #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U)
8221 #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK)
8222 /*! @} */
8223 
8224 /* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */
8225 #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT  (14U)
8226 
8227 /*! @name PRINCE_REGION1_IV_HEADER0 -  */
8228 /*! @{ */
8229 
8230 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)
8231 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U)
8232 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK)
8233 /*! @} */
8234 
8235 /*! @name PRINCE_REGION1_IV_HEADER1 -  */
8236 /*! @{ */
8237 
8238 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U)
8239 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U)
8240 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK)
8241 
8242 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U)
8243 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U)
8244 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK)
8245 
8246 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U)
8247 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U)
8248 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK)
8249 /*! @} */
8250 
8251 /*! @name PRINCE_REGION1_IV_BODY -  */
8252 /*! @{ */
8253 
8254 #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU)
8255 #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U)
8256 #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK)
8257 /*! @} */
8258 
8259 /* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */
8260 #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT  (12U)
8261 
8262 /*! @name PRINCE_REGION2_IV_CODE -  */
8263 /*! @{ */
8264 
8265 #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU)
8266 #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U)
8267 #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK)
8268 /*! @} */
8269 
8270 /* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */
8271 #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT  (14U)
8272 
8273 /*! @name PRINCE_REGION2_IV_HEADER0 -  */
8274 /*! @{ */
8275 
8276 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)
8277 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U)
8278 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK)
8279 /*! @} */
8280 
8281 /*! @name PRINCE_REGION2_IV_HEADER1 -  */
8282 /*! @{ */
8283 
8284 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U)
8285 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U)
8286 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK)
8287 
8288 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U)
8289 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U)
8290 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK)
8291 
8292 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U)
8293 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U)
8294 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK)
8295 /*! @} */
8296 
8297 /*! @name PRINCE_REGION2_IV_BODY -  */
8298 /*! @{ */
8299 
8300 #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU)
8301 #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U)
8302 #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK)
8303 /*! @} */
8304 
8305 /* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */
8306 #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT  (12U)
8307 
8308 /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */
8309 /*! @{ */
8310 
8311 #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK   (0xFFFFFFFFU)
8312 #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT  (0U)
8313 #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK)
8314 /*! @} */
8315 
8316 /* The count of FLASH_CFPA_CUSTOMER_DEFINED */
8317 #define FLASH_CFPA_CUSTOMER_DEFINED_COUNT        (56U)
8318 
8319 /*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */
8320 /*! @{ */
8321 
8322 #define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK      (0xFFFFFFFFU)
8323 #define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT     (0U)
8324 #define FLASH_CFPA_SHA256_DIGEST_FIELD(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK)
8325 /*! @} */
8326 
8327 /* The count of FLASH_CFPA_SHA256_DIGEST */
8328 #define FLASH_CFPA_SHA256_DIGEST_COUNT           (8U)
8329 
8330 
8331 /*!
8332  * @}
8333  */ /* end of group FLASH_CFPA_Register_Masks */
8334 
8335 
8336 /* FLASH_CFPA - Peripheral instance base addresses */
8337 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
8338   /** Peripheral FLASH_CFPA0 base address */
8339   #define FLASH_CFPA0_BASE                         (0x1009E000u)
8340   /** Peripheral FLASH_CFPA0 base address */
8341   #define FLASH_CFPA0_BASE_NS                      (0x9E000u)
8342   /** Peripheral FLASH_CFPA0 base pointer */
8343   #define FLASH_CFPA0                              ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)
8344   /** Peripheral FLASH_CFPA0 base pointer */
8345   #define FLASH_CFPA0_NS                           ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS)
8346   /** Peripheral FLASH_CFPA1 base address */
8347   #define FLASH_CFPA1_BASE                         (0x1009E200u)
8348   /** Peripheral FLASH_CFPA1 base address */
8349   #define FLASH_CFPA1_BASE_NS                      (0x9E200u)
8350   /** Peripheral FLASH_CFPA1 base pointer */
8351   #define FLASH_CFPA1                              ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)
8352   /** Peripheral FLASH_CFPA1 base pointer */
8353   #define FLASH_CFPA1_NS                           ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS)
8354   /** Peripheral FLASH_CFPA_SCRATCH base address */
8355   #define FLASH_CFPA_SCRATCH_BASE                  (0x1009DE00u)
8356   /** Peripheral FLASH_CFPA_SCRATCH base address */
8357   #define FLASH_CFPA_SCRATCH_BASE_NS               (0x9DE00u)
8358   /** Peripheral FLASH_CFPA_SCRATCH base pointer */
8359   #define FLASH_CFPA_SCRATCH                       ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)
8360   /** Peripheral FLASH_CFPA_SCRATCH base pointer */
8361   #define FLASH_CFPA_SCRATCH_NS                    ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS)
8362   /** Array initializer of FLASH_CFPA peripheral base addresses */
8363   #define FLASH_CFPA_BASE_ADDRS                    { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE }
8364   /** Array initializer of FLASH_CFPA peripheral base pointers */
8365   #define FLASH_CFPA_BASE_PTRS                     { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH }
8366   /** Array initializer of FLASH_CFPA peripheral base addresses */
8367   #define FLASH_CFPA_BASE_ADDRS_NS                 { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS }
8368   /** Array initializer of FLASH_CFPA peripheral base pointers */
8369   #define FLASH_CFPA_BASE_PTRS_NS                  { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS }
8370 #else
8371   /** Peripheral FLASH_CFPA0 base address */
8372   #define FLASH_CFPA0_BASE                         (0x9E000u)
8373   /** Peripheral FLASH_CFPA0 base pointer */
8374   #define FLASH_CFPA0                              ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)
8375   /** Peripheral FLASH_CFPA1 base address */
8376   #define FLASH_CFPA1_BASE                         (0x9E200u)
8377   /** Peripheral FLASH_CFPA1 base pointer */
8378   #define FLASH_CFPA1                              ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)
8379   /** Peripheral FLASH_CFPA_SCRATCH base address */
8380   #define FLASH_CFPA_SCRATCH_BASE                  (0x9DE00u)
8381   /** Peripheral FLASH_CFPA_SCRATCH base pointer */
8382   #define FLASH_CFPA_SCRATCH                       ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)
8383   /** Array initializer of FLASH_CFPA peripheral base addresses */
8384   #define FLASH_CFPA_BASE_ADDRS                    { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE }
8385   /** Array initializer of FLASH_CFPA peripheral base pointers */
8386   #define FLASH_CFPA_BASE_PTRS                     { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH }
8387 #endif
8388 
8389 /*!
8390  * @}
8391  */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */
8392 
8393 
8394 /* ----------------------------------------------------------------------------
8395    -- FLASH_CMPA Peripheral Access Layer
8396    ---------------------------------------------------------------------------- */
8397 
8398 /*!
8399  * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer
8400  * @{
8401  */
8402 
8403 /** FLASH_CMPA - Register Layout Typedef */
8404 typedef struct {
8405   __IO uint32_t BOOT_CFG;                          /**< , offset: 0x0 */
8406   __IO uint32_t SPI_FLASH_CFG;                     /**< , offset: 0x4 */
8407   __IO uint32_t USB_ID;                            /**< , offset: 0x8 */
8408   __IO uint32_t SDIO_CFG;                          /**< , offset: 0xC */
8409   __IO uint32_t CC_SOCU_PIN;                       /**< , offset: 0x10 */
8410   __IO uint32_t CC_SOCU_DFLT;                      /**< , offset: 0x14 */
8411   __IO uint32_t VENDOR_USAGE;                      /**< , offset: 0x18 */
8412   __IO uint32_t SECURE_BOOT_CFG;                   /**< Secure boot configuration flags., offset: 0x1C */
8413   __IO uint32_t PRINCE_BASE_ADDR;                  /**< , offset: 0x20 */
8414   __IO uint32_t PRINCE_SR_0;                       /**< Region 0, sub-region enable, offset: 0x24 */
8415   __IO uint32_t PRINCE_SR_1;                       /**< Region 1, sub-region enable, offset: 0x28 */
8416   __IO uint32_t PRINCE_SR_2;                       /**< Region 2, sub-region enable, offset: 0x2C */
8417   __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM;          /**< Xtal 32kHz capabank triming., offset: 0x30 */
8418   __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM;          /**< Xtal 16MHz capabank triming., offset: 0x34 */
8419        uint8_t RESERVED_0[24];
8420   __IO uint32_t ROTKH[8];                          /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */
8421        uint8_t RESERVED_1[144];
8422   __IO uint32_t CUSTOMER_DEFINED[56];              /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */
8423   __IO uint32_t SHA256_DIGEST[8];                  /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */
8424 } FLASH_CMPA_Type;
8425 
8426 /* ----------------------------------------------------------------------------
8427    -- FLASH_CMPA Register Masks
8428    ---------------------------------------------------------------------------- */
8429 
8430 /*!
8431  * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks
8432  * @{
8433  */
8434 
8435 /*! @name BOOT_CFG -  */
8436 /*! @{ */
8437 
8438 #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U)
8439 #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U)
8440 /*! DEFAULT_ISP_MODE - Default ISP mode:
8441  *  0b000..Auto ISP
8442  *  0b001..USB_HID_ISP
8443  *  0b010..UART ISP
8444  *  0b011..SPI Slave ISP
8445  *  0b100..I2C Slave ISP
8446  *  0b111..Disable ISP fall through
8447  */
8448 #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK)
8449 
8450 #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK      (0x180U)
8451 #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT     (7U)
8452 /*! BOOT_SPEED - Core clock:
8453  *  0b00..Defined by NMPA.SYSTEM_SPEED_CODE
8454  *  0b01..96MHz FRO
8455  *  0b10..48MHz FRO
8456  */
8457 #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK)
8458 
8459 #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U)
8460 #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U)
8461 /*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle
8462  *    rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO
8463  *    pin
8464  */
8465 #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK)
8466 /*! @} */
8467 
8468 /*! @name SPI_FLASH_CFG -  */
8469 /*! @{ */
8470 
8471 #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU)
8472 #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U)
8473 /*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field.
8474  */
8475 #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK)
8476 /*! @} */
8477 
8478 /*! @name USB_ID -  */
8479 /*! @{ */
8480 
8481 #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK     (0xFFFFU)
8482 #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT    (0U)
8483 #define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x)       (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK)
8484 
8485 #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK    (0xFFFF0000U)
8486 #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT   (16U)
8487 #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK)
8488 /*! @} */
8489 
8490 /*! @name SDIO_CFG -  */
8491 /*! @{ */
8492 
8493 #define FLASH_CMPA_SDIO_CFG_FIELD_MASK           (0xFFFFFFFFU)
8494 #define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT          (0U)
8495 #define FLASH_CMPA_SDIO_CFG_FIELD(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK)
8496 /*! @} */
8497 
8498 /*! @name CC_SOCU_PIN -  */
8499 /*! @{ */
8500 
8501 #define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK        (0x1U)
8502 #define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT       (0U)
8503 /*! NIDEN - Non Secure non-invasive debug enable
8504  *  0b0..Use DAP to enable
8505  *  0b1..Fixed state
8506  */
8507 #define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK)
8508 
8509 #define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK        (0x2U)
8510 #define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT       (1U)
8511 /*! DBGEN - Non Secure debug enable
8512  *  0b0..Use DAP to enable
8513  *  0b1..Fixed state
8514  */
8515 #define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK)
8516 
8517 #define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK      (0x4U)
8518 #define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT     (2U)
8519 /*! SPNIDEN - Secure non-invasive debug enable
8520  *  0b0..Use DAP to enable
8521  *  0b1..Fixed state
8522  */
8523 #define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK)
8524 
8525 #define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK       (0x8U)
8526 #define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT      (3U)
8527 /*! SPIDEN - Secure invasive debug enable
8528  *  0b0..Use DAP to enable
8529  *  0b1..Fixed state
8530  */
8531 #define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x)         (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK)
8532 
8533 #define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK        (0x10U)
8534 #define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT       (4U)
8535 /*! TAPEN - JTAG TAP enable
8536  *  0b0..Use DAP to enable
8537  *  0b1..Fixed state
8538  */
8539 #define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK)
8540 
8541 #define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK   (0x20U)
8542 #define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT  (5U)
8543 /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable
8544  *  0b0..Use DAP to enable
8545  *  0b1..Fixed state
8546  */
8547 #define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK)
8548 
8549 #define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK   (0x40U)
8550 #define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT  (6U)
8551 /*! ISP_CMD_EN - ISP Boot Command enable
8552  *  0b0..Use DAP to enable
8553  *  0b1..Fixed state
8554  */
8555 #define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK)
8556 
8557 #define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK    (0x80U)
8558 #define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT   (7U)
8559 /*! FA_CMD_EN - FA Command enable
8560  *  0b0..Use DAP to enable
8561  *  0b1..Fixed state
8562  */
8563 #define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK)
8564 
8565 #define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK    (0x100U)
8566 #define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT   (8U)
8567 /*! ME_CMD_EN - Flash Mass Erase Command enable
8568  *  0b0..Use DAP to enable
8569  *  0b1..Fixed state
8570  */
8571 #define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK)
8572 
8573 #define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK   (0x200U)
8574 #define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT  (9U)
8575 /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable
8576  *  0b0..Use DAP to enable
8577  *  0b1..Fixed state
8578  */
8579 #define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK)
8580 
8581 #define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK   (0x8000U)
8582 #define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT  (15U)
8583 /*! UUID_CHECK - Enforce UUID match during Debug authentication.
8584  */
8585 #define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK)
8586 
8587 #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U)
8588 #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U)
8589 /*! INVERSE_VALUE - inverse value of bits [15:0]
8590  */
8591 #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK)
8592 /*! @} */
8593 
8594 /*! @name CC_SOCU_DFLT -  */
8595 /*! @{ */
8596 
8597 #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK       (0x1U)
8598 #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT      (0U)
8599 /*! NIDEN - Non Secure non-invasive debug fixed state
8600  *  0b0..Disable
8601  *  0b1..Enable
8602  */
8603 #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x)         (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK)
8604 
8605 #define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK       (0x2U)
8606 #define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT      (1U)
8607 /*! DBGEN - Non Secure debug fixed state
8608  *  0b0..Disable
8609  *  0b1..Enable
8610  */
8611 #define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x)         (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK)
8612 
8613 #define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK     (0x4U)
8614 #define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT    (2U)
8615 /*! SPNIDEN - Secure non-invasive debug fixed state
8616  *  0b0..Disable
8617  *  0b1..Enable
8618  */
8619 #define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x)       (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK)
8620 
8621 #define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK      (0x8U)
8622 #define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT     (3U)
8623 /*! SPIDEN - Secure invasive debug fixed state
8624  *  0b0..Disable
8625  *  0b1..Enable
8626  */
8627 #define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK)
8628 
8629 #define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK       (0x10U)
8630 #define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT      (4U)
8631 /*! TAPEN - JTAG TAP fixed state
8632  *  0b0..Disable
8633  *  0b1..Enable
8634  */
8635 #define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x)         (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK)
8636 
8637 #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK  (0x20U)
8638 #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U)
8639 /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state
8640  *  0b0..Disable
8641  *  0b1..Enable
8642  */
8643 #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK)
8644 
8645 #define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK  (0x40U)
8646 #define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U)
8647 /*! ISP_CMD_EN - ISP Boot Command fixed state
8648  *  0b0..Disable
8649  *  0b1..Enable
8650  */
8651 #define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK)
8652 
8653 #define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK   (0x80U)
8654 #define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT  (7U)
8655 /*! FA_CMD_EN - FA Command fixed state
8656  *  0b0..Disable
8657  *  0b1..Enable
8658  */
8659 #define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK)
8660 
8661 #define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK   (0x100U)
8662 #define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT  (8U)
8663 /*! ME_CMD_EN - Flash Mass Erase Command fixed state
8664  *  0b0..Disable
8665  *  0b1..Enable
8666  */
8667 #define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK)
8668 
8669 #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK  (0x200U)
8670 #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U)
8671 /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state
8672  *  0b0..Disable
8673  *  0b1..Enable
8674  */
8675 #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK)
8676 
8677 #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U)
8678 #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U)
8679 /*! INVERSE_VALUE - inverse value of bits [15:0]
8680  */
8681 #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK)
8682 /*! @} */
8683 
8684 /*! @name VENDOR_USAGE -  */
8685 /*! @{ */
8686 
8687 #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U)
8688 #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U)
8689 /*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area.
8690  */
8691 #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK)
8692 /*! @} */
8693 
8694 /*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */
8695 /*! @{ */
8696 
8697 #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK    (0x3U)
8698 #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT   (0U)
8699 /*! RSA4K - Use RSA4096 keys only.
8700  *  0b00..Allow RSA2048 and higher
8701  *  0b01..RSA4096 only
8702  *  0b10..RSA4096 only
8703  *  0b11..RSA4096 only
8704  */
8705 #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK)
8706 
8707 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU)
8708 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U)
8709 /*! DICE_INC_NXP_CFG - Include NXP area in DICE computation.
8710  *  0b00..not included
8711  *  0b01..included
8712  *  0b10..included
8713  *  0b11..included
8714  */
8715 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK)
8716 
8717 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U)
8718 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U)
8719 /*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation.
8720  *  0b00..not included
8721  *  0b01..included
8722  *  0b10..included
8723  *  0b11..included
8724  */
8725 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK)
8726 
8727 #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U)
8728 #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U)
8729 /*! SKIP_DICE - Skip DICE computation
8730  *  0b00..Enable DICE
8731  *  0b01..Disable DICE
8732  *  0b10..Disable DICE
8733  *  0b11..Disable DICE
8734  */
8735 #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK)
8736 
8737 #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U)
8738 #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U)
8739 /*! TZM_IMAGE_TYPE - TrustZone-M mode
8740  *  0b00..TZ-M image mode is taken from application image header
8741  *  0b01..TZ-M disabled image, boots to non-secure mode
8742  *  0b10..TZ-M enabled image, boots to secure mode
8743  *  0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header
8744  */
8745 #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK)
8746 
8747 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U)
8748 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U)
8749 /*! BLOCK_SET_KEY - Block PUF key code generation
8750  *  0b00..Allow PUF Key Code generation
8751  *  0b01..Disable PUF Key Code generation
8752  *  0b10..Disable PUF Key Code generation
8753  *  0b11..Disable PUF Key Code generation
8754  */
8755 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK)
8756 
8757 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U)
8758 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U)
8759 /*! BLOCK_ENROLL - Block PUF enrollement
8760  *  0b00..Allow PUF enroll operation
8761  *  0b01..Disable PUF enroll operation
8762  *  0b10..Disable PUF enroll operation
8763  *  0b11..Disable PUF enroll operation
8764  */
8765 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK)
8766 
8767 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U)
8768 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U)
8769 /*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE
8770  */
8771 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK)
8772 
8773 #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U)
8774 #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U)
8775 /*! SEC_BOOT_EN - Secure boot enable
8776  *  0b00..Plain image (internal flash with or without CRC)
8777  *  0b01..Boot signed images. (internal flash, RSA signed)
8778  *  0b10..Boot signed images. (internal flash, RSA signed)
8779  *  0b11..Boot signed images. (internal flash, RSA signed)
8780  */
8781 #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK)
8782 /*! @} */
8783 
8784 /*! @name PRINCE_BASE_ADDR -  */
8785 /*! @{ */
8786 
8787 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU)
8788 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U)
8789 /*! ADDR0_PRG - Programmable portion of the base address of region 0
8790  */
8791 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK)
8792 
8793 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U)
8794 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U)
8795 /*! ADDR1_PRG - Programmable portion of the base address of region 1
8796  */
8797 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK)
8798 
8799 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U)
8800 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U)
8801 /*! ADDR2_PRG - Programmable portion of the base address of region 2
8802  */
8803 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK)
8804 
8805 #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U)
8806 #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U)
8807 /*! LOCK_REG0 - Lock PRINCE region0 settings
8808  *  0b00..Region is not locked
8809  *  0b01..Region is locked
8810  *  0b10..Region is locked
8811  *  0b11..Region is locked
8812  */
8813 #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK)
8814 
8815 #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U)
8816 #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U)
8817 /*! LOCK_REG1 - Lock PRINCE region1 settings
8818  *  0b00..Region is not locked
8819  *  0b01..Region is locked
8820  *  0b10..Region is locked
8821  *  0b11..Region is locked
8822  */
8823 #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK)
8824 
8825 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U)
8826 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U)
8827 /*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together
8828  *  0b00..Region is disabled
8829  *  0b01..Region is enabled
8830  *  0b10..Region is enabled
8831  *  0b11..Region is enabled
8832  */
8833 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK)
8834 
8835 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U)
8836 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U)
8837 /*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together
8838  *  0b00..Region is disabled
8839  *  0b01..Region is enabled
8840  *  0b10..Region is enabled
8841  *  0b11..Region is enabled
8842  */
8843 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK)
8844 
8845 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U)
8846 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U)
8847 /*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together
8848  *  0b00..Region is disabled
8849  *  0b01..Region is enabled
8850  *  0b10..Region is enabled
8851  *  0b11..Region is enabled
8852  */
8853 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK)
8854 /*! @} */
8855 
8856 /*! @name PRINCE_SR_0 - Region 0, sub-region enable */
8857 /*! @{ */
8858 
8859 #define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK        (0xFFFFFFFFU)
8860 #define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT       (0U)
8861 #define FLASH_CMPA_PRINCE_SR_0_FIELD(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK)
8862 /*! @} */
8863 
8864 /*! @name PRINCE_SR_1 - Region 1, sub-region enable */
8865 /*! @{ */
8866 
8867 #define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK        (0xFFFFFFFFU)
8868 #define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT       (0U)
8869 #define FLASH_CMPA_PRINCE_SR_1_FIELD(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK)
8870 /*! @} */
8871 
8872 /*! @name PRINCE_SR_2 - Region 2, sub-region enable */
8873 /*! @{ */
8874 
8875 #define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK        (0xFFFFFFFFU)
8876 #define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT       (0U)
8877 #define FLASH_CMPA_PRINCE_SR_2_FIELD(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK)
8878 /*! @} */
8879 
8880 /*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */
8881 /*! @{ */
8882 
8883 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U)
8884 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U)
8885 /*! TRIM_VALID - XTAL 32kHz capa bank trimmings
8886  *  0b0..Capa Bank trimmings not valid. Default trimmings value are used
8887  *  0b1..Capa Bank trimmings valid
8888  */
8889 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK)
8890 
8891 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU)
8892 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U)
8893 /*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600.
8894  */
8895 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK)
8896 
8897 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U)
8898 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U)
8899 /*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600.
8900  */
8901 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK)
8902 
8903 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U)
8904 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U)
8905 /*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600.
8906  */
8907 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK)
8908 /*! @} */
8909 
8910 /*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */
8911 /*! @{ */
8912 
8913 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U)
8914 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U)
8915 /*! TRIM_VALID - XTAL 16MHz capa bank trimmings
8916  *  0b0..Capa Bank trimmings not valid. Default trimmings value are used
8917  *  0b1..Capa Bank trimmings valid
8918  */
8919 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK)
8920 
8921 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU)
8922 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U)
8923 /*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600.
8924  */
8925 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK)
8926 
8927 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U)
8928 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U)
8929 /*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600.
8930  */
8931 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK)
8932 
8933 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U)
8934 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U)
8935 /*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600.
8936  */
8937 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK)
8938 /*! @} */
8939 
8940 /*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */
8941 /*! @{ */
8942 
8943 #define FLASH_CMPA_ROTKH_FIELD_MASK              (0xFFFFFFFFU)
8944 #define FLASH_CMPA_ROTKH_FIELD_SHIFT             (0U)
8945 #define FLASH_CMPA_ROTKH_FIELD(x)                (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK)
8946 /*! @} */
8947 
8948 /* The count of FLASH_CMPA_ROTKH */
8949 #define FLASH_CMPA_ROTKH_COUNT                   (8U)
8950 
8951 /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */
8952 /*! @{ */
8953 
8954 #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK   (0xFFFFFFFFU)
8955 #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT  (0U)
8956 #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK)
8957 /*! @} */
8958 
8959 /* The count of FLASH_CMPA_CUSTOMER_DEFINED */
8960 #define FLASH_CMPA_CUSTOMER_DEFINED_COUNT        (56U)
8961 
8962 /*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */
8963 /*! @{ */
8964 
8965 #define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK      (0xFFFFFFFFU)
8966 #define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT     (0U)
8967 #define FLASH_CMPA_SHA256_DIGEST_FIELD(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK)
8968 /*! @} */
8969 
8970 /* The count of FLASH_CMPA_SHA256_DIGEST */
8971 #define FLASH_CMPA_SHA256_DIGEST_COUNT           (8U)
8972 
8973 
8974 /*!
8975  * @}
8976  */ /* end of group FLASH_CMPA_Register_Masks */
8977 
8978 
8979 /* FLASH_CMPA - Peripheral instance base addresses */
8980 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
8981   /** Peripheral FLASH_CMPA base address */
8982   #define FLASH_CMPA_BASE                          (0x1009E400u)
8983   /** Peripheral FLASH_CMPA base address */
8984   #define FLASH_CMPA_BASE_NS                       (0x9E400u)
8985   /** Peripheral FLASH_CMPA base pointer */
8986   #define FLASH_CMPA                               ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)
8987   /** Peripheral FLASH_CMPA base pointer */
8988   #define FLASH_CMPA_NS                            ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS)
8989   /** Array initializer of FLASH_CMPA peripheral base addresses */
8990   #define FLASH_CMPA_BASE_ADDRS                    { FLASH_CMPA_BASE }
8991   /** Array initializer of FLASH_CMPA peripheral base pointers */
8992   #define FLASH_CMPA_BASE_PTRS                     { FLASH_CMPA }
8993   /** Array initializer of FLASH_CMPA peripheral base addresses */
8994   #define FLASH_CMPA_BASE_ADDRS_NS                 { FLASH_CMPA_BASE_NS }
8995   /** Array initializer of FLASH_CMPA peripheral base pointers */
8996   #define FLASH_CMPA_BASE_PTRS_NS                  { FLASH_CMPA_NS }
8997 #else
8998   /** Peripheral FLASH_CMPA base address */
8999   #define FLASH_CMPA_BASE                          (0x9E400u)
9000   /** Peripheral FLASH_CMPA base pointer */
9001   #define FLASH_CMPA                               ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)
9002   /** Array initializer of FLASH_CMPA peripheral base addresses */
9003   #define FLASH_CMPA_BASE_ADDRS                    { FLASH_CMPA_BASE }
9004   /** Array initializer of FLASH_CMPA peripheral base pointers */
9005   #define FLASH_CMPA_BASE_PTRS                     { FLASH_CMPA }
9006 #endif
9007 
9008 /*!
9009  * @}
9010  */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */
9011 
9012 
9013 /* ----------------------------------------------------------------------------
9014    -- FLASH_KEY_STORE Peripheral Access Layer
9015    ---------------------------------------------------------------------------- */
9016 
9017 /*!
9018  * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer
9019  * @{
9020  */
9021 
9022 /** FLASH_KEY_STORE - Register Layout Typedef */
9023 typedef struct {
9024   struct {                                         /* offset: 0x0 */
9025     __IO uint32_t HEADER;                            /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */
9026     __IO uint32_t PUF_DISCHARGE_TIME_IN_MS;          /**< puf discharge time in ms., offset: 0x4 */
9027   } KEY_STORE_HEADER;
9028   __IO uint32_t ACTIVATION_CODE[298];              /**< ., array offset: 0x8, array step: 0x4 */
9029   union {                                          /* offset: 0x4B0 */
9030     __IO uint32_t SBKEY_KEY_CODE[14];                /**< ., array offset: 0x4B0, array step: 0x4 */
9031     struct {                                         /* offset: 0x4B0 */
9032       __IO uint32_t SBKEY_HEADER0;                     /**< ., offset: 0x4B0 */
9033       __IO uint32_t SBKEY_HEADER1;                     /**< ., offset: 0x4B4 */
9034       __IO uint32_t SBKEY_BODY[12];                    /**< ., array offset: 0x4B8, array step: 0x4 */
9035     } SBKEY_KEY_CODE_CORE;
9036   };
9037   union {                                          /* offset: 0x4E8 */
9038     __IO uint32_t USER_KEK_KEY_CODE[14];             /**< ., array offset: 0x4E8, array step: 0x4 */
9039     struct {                                         /* offset: 0x4E8 */
9040       __IO uint32_t USER_KEK_HEADER0;                  /**< ., offset: 0x4E8 */
9041       __IO uint32_t USER_KEK_HEADER1;                  /**< ., offset: 0x4EC */
9042       __IO uint32_t USER_KEK_BODY[12];                 /**< ., array offset: 0x4F0, array step: 0x4 */
9043     } USER_KEK_KEY_CODE_CORE;
9044   };
9045   union {                                          /* offset: 0x520 */
9046     __IO uint32_t UDS_KEY_CODE[14];                  /**< ., array offset: 0x520, array step: 0x4 */
9047     struct {                                         /* offset: 0x520 */
9048       __IO uint32_t UDS_HEADER0;                       /**< ., offset: 0x520 */
9049       __IO uint32_t UDS_HEADER1;                       /**< ., offset: 0x524 */
9050       __IO uint32_t UDS_BODY[12];                      /**< ., array offset: 0x528, array step: 0x4 */
9051     } UDS_KEY_CODE_CORE;
9052   };
9053   union {                                          /* offset: 0x558 */
9054     __IO uint32_t PRINCE_REGION0_KEY_CODE[14];       /**< ., array offset: 0x558, array step: 0x4 */
9055     struct {                                         /* offset: 0x558 */
9056       __IO uint32_t PRINCE_REGION0_HEADER0;            /**< ., offset: 0x558 */
9057       __IO uint32_t PRINCE_REGION0_HEADER1;            /**< ., offset: 0x55C */
9058       __IO uint32_t PRINCE_REGION0_BODY[12];           /**< ., array offset: 0x560, array step: 0x4 */
9059     } PRINCE_REGION0_KEY_CODE_CORE;
9060   };
9061   union {                                          /* offset: 0x590 */
9062     __IO uint32_t PRINCE_REGION1_KEY_CODE[14];       /**< ., array offset: 0x590, array step: 0x4 */
9063     struct {                                         /* offset: 0x590 */
9064       __IO uint32_t PRINCE_REGION1_HEADER0;            /**< ., offset: 0x590 */
9065       __IO uint32_t PRINCE_REGION1_HEADER1;            /**< ., offset: 0x594 */
9066       __IO uint32_t PRINCE_REGION1_BODY[12];           /**< ., array offset: 0x598, array step: 0x4 */
9067     } PRINCE_REGION1_KEY_CODE_CORE;
9068   };
9069   union {                                          /* offset: 0x5C8 */
9070     __IO uint32_t PRINCE_REGION2_KEY_CODE[14];       /**< ., array offset: 0x5C8, array step: 0x4 */
9071     struct {                                         /* offset: 0x5C8 */
9072       __IO uint32_t PRINCE_REGION2_HEADER0;            /**< ., offset: 0x5C8 */
9073       __IO uint32_t PRINCE_REGION2_HEADER1;            /**< ., offset: 0x5CC */
9074       __IO uint32_t PRINCE_REGION2_BODY[12];           /**< ., array offset: 0x5D0, array step: 0x4 */
9075     } PRINCE_REGION2_KEY_CODE_CORE;
9076   };
9077 } FLASH_KEY_STORE_Type;
9078 
9079 /* ----------------------------------------------------------------------------
9080    -- FLASH_KEY_STORE Register Masks
9081    ---------------------------------------------------------------------------- */
9082 
9083 /*!
9084  * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks
9085  * @{
9086  */
9087 
9088 /*! @name HEADER - Valid Key Sore Header : 0x95959595 */
9089 /*! @{ */
9090 
9091 #define FLASH_KEY_STORE_HEADER_FIELD_MASK        (0xFFFFFFFFU)
9092 #define FLASH_KEY_STORE_HEADER_FIELD_SHIFT       (0U)
9093 /*! FIELD - .
9094  */
9095 #define FLASH_KEY_STORE_HEADER_FIELD(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK)
9096 /*! @} */
9097 
9098 /*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */
9099 /*! @{ */
9100 
9101 #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU)
9102 #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U)
9103 /*! FIELD - .
9104  */
9105 #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK)
9106 /*! @} */
9107 
9108 /*! @name ACTIVATION_CODE - . */
9109 /*! @{ */
9110 
9111 #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU)
9112 #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U)
9113 /*! FIELD - .
9114  */
9115 #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK)
9116 /*! @} */
9117 
9118 /* The count of FLASH_KEY_STORE_ACTIVATION_CODE */
9119 #define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT    (298U)
9120 
9121 /*! @name SBKEY_KEY_CODE - . */
9122 /*! @{ */
9123 
9124 #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
9125 #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U)
9126 /*! FIELD - .
9127  */
9128 #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK)
9129 /*! @} */
9130 
9131 /* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */
9132 #define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT     (14U)
9133 
9134 /*! @name SBKEY_HEADER0 - . */
9135 /*! @{ */
9136 
9137 #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU)
9138 #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U)
9139 /*! FIELD - .
9140  */
9141 #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x)   (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK)
9142 /*! @} */
9143 
9144 /*! @name SBKEY_HEADER1 - . */
9145 /*! @{ */
9146 
9147 #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK  (0x3U)
9148 #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U)
9149 /*! TYPE - .
9150  */
9151 #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK)
9152 
9153 #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U)
9154 #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U)
9155 /*! INDEX - .
9156  */
9157 #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x)   (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK)
9158 
9159 #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK  (0x3F000000U)
9160 #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U)
9161 /*! SIZE - .
9162  */
9163 #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK)
9164 /*! @} */
9165 
9166 /*! @name SBKEY_BODY - . */
9167 /*! @{ */
9168 
9169 #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK    (0xFFFFFFFFU)
9170 #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT   (0U)
9171 /*! FIELD - .
9172  */
9173 #define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK)
9174 /*! @} */
9175 
9176 /* The count of FLASH_KEY_STORE_SBKEY_BODY */
9177 #define FLASH_KEY_STORE_SBKEY_BODY_COUNT         (12U)
9178 
9179 /*! @name USER_KEK_KEY_CODE - . */
9180 /*! @{ */
9181 
9182 #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
9183 #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U)
9184 /*! FIELD - .
9185  */
9186 #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK)
9187 /*! @} */
9188 
9189 /* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */
9190 #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT  (14U)
9191 
9192 /*! @name USER_KEK_HEADER0 - . */
9193 /*! @{ */
9194 
9195 #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU)
9196 #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U)
9197 /*! FIELD - .
9198  */
9199 #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK)
9200 /*! @} */
9201 
9202 /*! @name USER_KEK_HEADER1 - . */
9203 /*! @{ */
9204 
9205 #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U)
9206 #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U)
9207 /*! TYPE - .
9208  */
9209 #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK)
9210 
9211 #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U)
9212 #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U)
9213 /*! INDEX - .
9214  */
9215 #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK)
9216 
9217 #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U)
9218 #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U)
9219 /*! SIZE - .
9220  */
9221 #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK)
9222 /*! @} */
9223 
9224 /*! @name USER_KEK_BODY - . */
9225 /*! @{ */
9226 
9227 #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU)
9228 #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U)
9229 /*! FIELD - .
9230  */
9231 #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x)   (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK)
9232 /*! @} */
9233 
9234 /* The count of FLASH_KEY_STORE_USER_KEK_BODY */
9235 #define FLASH_KEY_STORE_USER_KEK_BODY_COUNT      (12U)
9236 
9237 /*! @name UDS_KEY_CODE - . */
9238 /*! @{ */
9239 
9240 #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK  (0xFFFFFFFFU)
9241 #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U)
9242 /*! FIELD - .
9243  */
9244 #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x)    (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK)
9245 /*! @} */
9246 
9247 /* The count of FLASH_KEY_STORE_UDS_KEY_CODE */
9248 #define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT       (14U)
9249 
9250 /*! @name UDS_HEADER0 - . */
9251 /*! @{ */
9252 
9253 #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK   (0xFFFFFFFFU)
9254 #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT  (0U)
9255 /*! FIELD - .
9256  */
9257 #define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK)
9258 /*! @} */
9259 
9260 /*! @name UDS_HEADER1 - . */
9261 /*! @{ */
9262 
9263 #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK    (0x3U)
9264 #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT   (0U)
9265 /*! TYPE - .
9266  */
9267 #define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK)
9268 
9269 #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK   (0xF00U)
9270 #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT  (8U)
9271 /*! INDEX - .
9272  */
9273 #define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK)
9274 
9275 #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK    (0x3F000000U)
9276 #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT   (24U)
9277 /*! SIZE - .
9278  */
9279 #define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK)
9280 /*! @} */
9281 
9282 /*! @name UDS_BODY - . */
9283 /*! @{ */
9284 
9285 #define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK      (0xFFFFFFFFU)
9286 #define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT     (0U)
9287 /*! FIELD - .
9288  */
9289 #define FLASH_KEY_STORE_UDS_BODY_FIELD(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK)
9290 /*! @} */
9291 
9292 /* The count of FLASH_KEY_STORE_UDS_BODY */
9293 #define FLASH_KEY_STORE_UDS_BODY_COUNT           (12U)
9294 
9295 /*! @name PRINCE_REGION0_KEY_CODE - . */
9296 /*! @{ */
9297 
9298 #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
9299 #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U)
9300 /*! FIELD - .
9301  */
9302 #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK)
9303 /*! @} */
9304 
9305 /* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */
9306 #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U)
9307 
9308 /*! @name PRINCE_REGION0_HEADER0 - . */
9309 /*! @{ */
9310 
9311 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU)
9312 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U)
9313 /*! FIELD - .
9314  */
9315 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK)
9316 /*! @} */
9317 
9318 /*! @name PRINCE_REGION0_HEADER1 - . */
9319 /*! @{ */
9320 
9321 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U)
9322 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U)
9323 /*! TYPE - .
9324  */
9325 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK)
9326 
9327 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U)
9328 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U)
9329 /*! INDEX - .
9330  */
9331 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK)
9332 
9333 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U)
9334 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U)
9335 /*! SIZE - .
9336  */
9337 #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK)
9338 /*! @} */
9339 
9340 /*! @name PRINCE_REGION0_BODY - . */
9341 /*! @{ */
9342 
9343 #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU)
9344 #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U)
9345 /*! FIELD - .
9346  */
9347 #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK)
9348 /*! @} */
9349 
9350 /* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */
9351 #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U)
9352 
9353 /*! @name PRINCE_REGION1_KEY_CODE - . */
9354 /*! @{ */
9355 
9356 #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
9357 #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U)
9358 /*! FIELD - .
9359  */
9360 #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK)
9361 /*! @} */
9362 
9363 /* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */
9364 #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U)
9365 
9366 /*! @name PRINCE_REGION1_HEADER0 - . */
9367 /*! @{ */
9368 
9369 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU)
9370 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U)
9371 /*! FIELD - .
9372  */
9373 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK)
9374 /*! @} */
9375 
9376 /*! @name PRINCE_REGION1_HEADER1 - . */
9377 /*! @{ */
9378 
9379 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U)
9380 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U)
9381 /*! TYPE - .
9382  */
9383 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK)
9384 
9385 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U)
9386 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U)
9387 /*! INDEX - .
9388  */
9389 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK)
9390 
9391 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U)
9392 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U)
9393 /*! SIZE - .
9394  */
9395 #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK)
9396 /*! @} */
9397 
9398 /*! @name PRINCE_REGION1_BODY - . */
9399 /*! @{ */
9400 
9401 #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU)
9402 #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U)
9403 /*! FIELD - .
9404  */
9405 #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK)
9406 /*! @} */
9407 
9408 /* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */
9409 #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U)
9410 
9411 /*! @name PRINCE_REGION2_KEY_CODE - . */
9412 /*! @{ */
9413 
9414 #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
9415 #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U)
9416 /*! FIELD - .
9417  */
9418 #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK)
9419 /*! @} */
9420 
9421 /* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */
9422 #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U)
9423 
9424 /*! @name PRINCE_REGION2_HEADER0 - . */
9425 /*! @{ */
9426 
9427 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU)
9428 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U)
9429 /*! FIELD - .
9430  */
9431 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK)
9432 /*! @} */
9433 
9434 /*! @name PRINCE_REGION2_HEADER1 - . */
9435 /*! @{ */
9436 
9437 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U)
9438 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U)
9439 /*! TYPE - .
9440  */
9441 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK)
9442 
9443 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U)
9444 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U)
9445 /*! INDEX - .
9446  */
9447 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK)
9448 
9449 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U)
9450 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U)
9451 /*! SIZE - .
9452  */
9453 #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK)
9454 /*! @} */
9455 
9456 /*! @name PRINCE_REGION2_BODY - . */
9457 /*! @{ */
9458 
9459 #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU)
9460 #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U)
9461 /*! FIELD - .
9462  */
9463 #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK)
9464 /*! @} */
9465 
9466 /* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */
9467 #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U)
9468 
9469 
9470 /*!
9471  * @}
9472  */ /* end of group FLASH_KEY_STORE_Register_Masks */
9473 
9474 
9475 /* FLASH_KEY_STORE - Peripheral instance base addresses */
9476 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
9477   /** Peripheral FLASH_KEY_STORE base address */
9478   #define FLASH_KEY_STORE_BASE                     (0x1009E600u)
9479   /** Peripheral FLASH_KEY_STORE base address */
9480   #define FLASH_KEY_STORE_BASE_NS                  (0x9E600u)
9481   /** Peripheral FLASH_KEY_STORE base pointer */
9482   #define FLASH_KEY_STORE                          ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)
9483   /** Peripheral FLASH_KEY_STORE base pointer */
9484   #define FLASH_KEY_STORE_NS                       ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS)
9485   /** Array initializer of FLASH_KEY_STORE peripheral base addresses */
9486   #define FLASH_KEY_STORE_BASE_ADDRS               { FLASH_KEY_STORE_BASE }
9487   /** Array initializer of FLASH_KEY_STORE peripheral base pointers */
9488   #define FLASH_KEY_STORE_BASE_PTRS                { FLASH_KEY_STORE }
9489   /** Array initializer of FLASH_KEY_STORE peripheral base addresses */
9490   #define FLASH_KEY_STORE_BASE_ADDRS_NS            { FLASH_KEY_STORE_BASE_NS }
9491   /** Array initializer of FLASH_KEY_STORE peripheral base pointers */
9492   #define FLASH_KEY_STORE_BASE_PTRS_NS             { FLASH_KEY_STORE_NS }
9493 #else
9494   /** Peripheral FLASH_KEY_STORE base address */
9495   #define FLASH_KEY_STORE_BASE                     (0x9E600u)
9496   /** Peripheral FLASH_KEY_STORE base pointer */
9497   #define FLASH_KEY_STORE                          ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)
9498   /** Array initializer of FLASH_KEY_STORE peripheral base addresses */
9499   #define FLASH_KEY_STORE_BASE_ADDRS               { FLASH_KEY_STORE_BASE }
9500   /** Array initializer of FLASH_KEY_STORE peripheral base pointers */
9501   #define FLASH_KEY_STORE_BASE_PTRS                { FLASH_KEY_STORE }
9502 #endif
9503 
9504 /*!
9505  * @}
9506  */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */
9507 
9508 
9509 /* ----------------------------------------------------------------------------
9510    -- FLEXCOMM Peripheral Access Layer
9511    ---------------------------------------------------------------------------- */
9512 
9513 /*!
9514  * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
9515  * @{
9516  */
9517 
9518 /** FLEXCOMM - Register Layout Typedef */
9519 typedef struct {
9520        uint8_t RESERVED_0[4088];
9521   __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
9522   __I  uint32_t PID;                               /**< Peripheral identification register., offset: 0xFFC */
9523 } FLEXCOMM_Type;
9524 
9525 /* ----------------------------------------------------------------------------
9526    -- FLEXCOMM Register Masks
9527    ---------------------------------------------------------------------------- */
9528 
9529 /*!
9530  * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
9531  * @{
9532  */
9533 
9534 /*! @name PSELID - Peripheral Select and Flexcomm ID register. */
9535 /*! @{ */
9536 
9537 #define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
9538 #define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
9539 /*! PERSEL - Peripheral Select. This field is writable by software.
9540  *  0b000..No peripheral selected.
9541  *  0b001..USART function selected.
9542  *  0b010..SPI function selected.
9543  *  0b011..I2C function selected.
9544  *  0b100..I2S transmit function selected.
9545  *  0b101..I2S receive function selected.
9546  *  0b110..Reserved
9547  *  0b111..Reserved
9548  */
9549 #define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
9550 
9551 #define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
9552 #define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
9553 /*! LOCK - Lock the peripheral select. This field is writable by software.
9554  *  0b0..Peripheral select can be changed by software.
9555  *  0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.
9556  */
9557 #define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
9558 
9559 #define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
9560 #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
9561 /*! USARTPRESENT - USART present indicator. This field is Read-only.
9562  *  0b0..This Flexcomm does not include the USART function.
9563  *  0b1..This Flexcomm includes the USART function.
9564  */
9565 #define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
9566 
9567 #define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
9568 #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
9569 /*! SPIPRESENT - SPI present indicator. This field is Read-only.
9570  *  0b0..This Flexcomm does not include the SPI function.
9571  *  0b1..This Flexcomm includes the SPI function.
9572  */
9573 #define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
9574 
9575 #define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
9576 #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
9577 /*! I2CPRESENT - I2C present indicator. This field is Read-only.
9578  *  0b0..This Flexcomm does not include the I2C function.
9579  *  0b1..This Flexcomm includes the I2C function.
9580  */
9581 #define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
9582 
9583 #define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
9584 #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
9585 /*! I2SPRESENT - I 2S present indicator. This field is Read-only.
9586  *  0b0..This Flexcomm does not include the I2S function.
9587  *  0b1..This Flexcomm includes the I2S function.
9588  */
9589 #define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
9590 
9591 #define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
9592 #define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
9593 /*! ID - Flexcomm ID.
9594  */
9595 #define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
9596 /*! @} */
9597 
9598 /*! @name PID - Peripheral identification register. */
9599 /*! @{ */
9600 
9601 #define FLEXCOMM_PID_APERTURE_MASK               (0xFFU)
9602 #define FLEXCOMM_PID_APERTURE_SHIFT              (0U)
9603 /*! APERTURE - size aperture for the register port on the bus (APB or AHB).
9604  */
9605 #define FLEXCOMM_PID_APERTURE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK)
9606 
9607 #define FLEXCOMM_PID_MINOR_REV_MASK              (0xF00U)
9608 #define FLEXCOMM_PID_MINOR_REV_SHIFT             (8U)
9609 /*! MINOR_REV - Minor revision of module implementation.
9610  */
9611 #define FLEXCOMM_PID_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK)
9612 
9613 #define FLEXCOMM_PID_MAJOR_REV_MASK              (0xF000U)
9614 #define FLEXCOMM_PID_MAJOR_REV_SHIFT             (12U)
9615 /*! MAJOR_REV - Major revision of module implementation.
9616  */
9617 #define FLEXCOMM_PID_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK)
9618 
9619 #define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
9620 #define FLEXCOMM_PID_ID_SHIFT                    (16U)
9621 /*! ID - Module identifier for the selected function.
9622  */
9623 #define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
9624 /*! @} */
9625 
9626 
9627 /*!
9628  * @}
9629  */ /* end of group FLEXCOMM_Register_Masks */
9630 
9631 
9632 /* FLEXCOMM - Peripheral instance base addresses */
9633 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
9634   /** Peripheral FLEXCOMM0 base address */
9635   #define FLEXCOMM0_BASE                           (0x50086000u)
9636   /** Peripheral FLEXCOMM0 base address */
9637   #define FLEXCOMM0_BASE_NS                        (0x40086000u)
9638   /** Peripheral FLEXCOMM0 base pointer */
9639   #define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
9640   /** Peripheral FLEXCOMM0 base pointer */
9641   #define FLEXCOMM0_NS                             ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS)
9642   /** Peripheral FLEXCOMM1 base address */
9643   #define FLEXCOMM1_BASE                           (0x50087000u)
9644   /** Peripheral FLEXCOMM1 base address */
9645   #define FLEXCOMM1_BASE_NS                        (0x40087000u)
9646   /** Peripheral FLEXCOMM1 base pointer */
9647   #define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
9648   /** Peripheral FLEXCOMM1 base pointer */
9649   #define FLEXCOMM1_NS                             ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS)
9650   /** Peripheral FLEXCOMM2 base address */
9651   #define FLEXCOMM2_BASE                           (0x50088000u)
9652   /** Peripheral FLEXCOMM2 base address */
9653   #define FLEXCOMM2_BASE_NS                        (0x40088000u)
9654   /** Peripheral FLEXCOMM2 base pointer */
9655   #define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
9656   /** Peripheral FLEXCOMM2 base pointer */
9657   #define FLEXCOMM2_NS                             ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS)
9658   /** Peripheral FLEXCOMM3 base address */
9659   #define FLEXCOMM3_BASE                           (0x50089000u)
9660   /** Peripheral FLEXCOMM3 base address */
9661   #define FLEXCOMM3_BASE_NS                        (0x40089000u)
9662   /** Peripheral FLEXCOMM3 base pointer */
9663   #define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
9664   /** Peripheral FLEXCOMM3 base pointer */
9665   #define FLEXCOMM3_NS                             ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS)
9666   /** Peripheral FLEXCOMM4 base address */
9667   #define FLEXCOMM4_BASE                           (0x5008A000u)
9668   /** Peripheral FLEXCOMM4 base address */
9669   #define FLEXCOMM4_BASE_NS                        (0x4008A000u)
9670   /** Peripheral FLEXCOMM4 base pointer */
9671   #define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
9672   /** Peripheral FLEXCOMM4 base pointer */
9673   #define FLEXCOMM4_NS                             ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS)
9674   /** Peripheral FLEXCOMM5 base address */
9675   #define FLEXCOMM5_BASE                           (0x50096000u)
9676   /** Peripheral FLEXCOMM5 base address */
9677   #define FLEXCOMM5_BASE_NS                        (0x40096000u)
9678   /** Peripheral FLEXCOMM5 base pointer */
9679   #define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
9680   /** Peripheral FLEXCOMM5 base pointer */
9681   #define FLEXCOMM5_NS                             ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS)
9682   /** Peripheral FLEXCOMM6 base address */
9683   #define FLEXCOMM6_BASE                           (0x50097000u)
9684   /** Peripheral FLEXCOMM6 base address */
9685   #define FLEXCOMM6_BASE_NS                        (0x40097000u)
9686   /** Peripheral FLEXCOMM6 base pointer */
9687   #define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
9688   /** Peripheral FLEXCOMM6 base pointer */
9689   #define FLEXCOMM6_NS                             ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS)
9690   /** Peripheral FLEXCOMM7 base address */
9691   #define FLEXCOMM7_BASE                           (0x50098000u)
9692   /** Peripheral FLEXCOMM7 base address */
9693   #define FLEXCOMM7_BASE_NS                        (0x40098000u)
9694   /** Peripheral FLEXCOMM7 base pointer */
9695   #define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
9696   /** Peripheral FLEXCOMM7 base pointer */
9697   #define FLEXCOMM7_NS                             ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS)
9698   /** Peripheral FLEXCOMM8 base address */
9699   #define FLEXCOMM8_BASE                           (0x5009F000u)
9700   /** Peripheral FLEXCOMM8 base address */
9701   #define FLEXCOMM8_BASE_NS                        (0x4009F000u)
9702   /** Peripheral FLEXCOMM8 base pointer */
9703   #define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
9704   /** Peripheral FLEXCOMM8 base pointer */
9705   #define FLEXCOMM8_NS                             ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS)
9706   /** Array initializer of FLEXCOMM peripheral base addresses */
9707   #define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE }
9708   /** Array initializer of FLEXCOMM peripheral base pointers */
9709   #define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 }
9710   /** Array initializer of FLEXCOMM peripheral base addresses */
9711   #define FLEXCOMM_BASE_ADDRS_NS                   { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS }
9712   /** Array initializer of FLEXCOMM peripheral base pointers */
9713   #define FLEXCOMM_BASE_PTRS_NS                    { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS }
9714 #else
9715   /** Peripheral FLEXCOMM0 base address */
9716   #define FLEXCOMM0_BASE                           (0x40086000u)
9717   /** Peripheral FLEXCOMM0 base pointer */
9718   #define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
9719   /** Peripheral FLEXCOMM1 base address */
9720   #define FLEXCOMM1_BASE                           (0x40087000u)
9721   /** Peripheral FLEXCOMM1 base pointer */
9722   #define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
9723   /** Peripheral FLEXCOMM2 base address */
9724   #define FLEXCOMM2_BASE                           (0x40088000u)
9725   /** Peripheral FLEXCOMM2 base pointer */
9726   #define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
9727   /** Peripheral FLEXCOMM3 base address */
9728   #define FLEXCOMM3_BASE                           (0x40089000u)
9729   /** Peripheral FLEXCOMM3 base pointer */
9730   #define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
9731   /** Peripheral FLEXCOMM4 base address */
9732   #define FLEXCOMM4_BASE                           (0x4008A000u)
9733   /** Peripheral FLEXCOMM4 base pointer */
9734   #define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
9735   /** Peripheral FLEXCOMM5 base address */
9736   #define FLEXCOMM5_BASE                           (0x40096000u)
9737   /** Peripheral FLEXCOMM5 base pointer */
9738   #define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
9739   /** Peripheral FLEXCOMM6 base address */
9740   #define FLEXCOMM6_BASE                           (0x40097000u)
9741   /** Peripheral FLEXCOMM6 base pointer */
9742   #define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
9743   /** Peripheral FLEXCOMM7 base address */
9744   #define FLEXCOMM7_BASE                           (0x40098000u)
9745   /** Peripheral FLEXCOMM7 base pointer */
9746   #define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
9747   /** Peripheral FLEXCOMM8 base address */
9748   #define FLEXCOMM8_BASE                           (0x4009F000u)
9749   /** Peripheral FLEXCOMM8 base pointer */
9750   #define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
9751   /** Array initializer of FLEXCOMM peripheral base addresses */
9752   #define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE }
9753   /** Array initializer of FLEXCOMM peripheral base pointers */
9754   #define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 }
9755 #endif
9756 /** Interrupt vectors for the FLEXCOMM peripheral type */
9757 #define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn }
9758 
9759 /*!
9760  * @}
9761  */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
9762 
9763 
9764 /* ----------------------------------------------------------------------------
9765    -- GINT Peripheral Access Layer
9766    ---------------------------------------------------------------------------- */
9767 
9768 /*!
9769  * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
9770  * @{
9771  */
9772 
9773 /** GINT - Register Layout Typedef */
9774 typedef struct {
9775   __IO uint32_t CTRL;                              /**< GPIO grouped interrupt control register, offset: 0x0 */
9776        uint8_t RESERVED_0[28];
9777   __IO uint32_t PORT_POL[2];                       /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
9778        uint8_t RESERVED_1[24];
9779   __IO uint32_t PORT_ENA[2];                       /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
9780 } GINT_Type;
9781 
9782 /* ----------------------------------------------------------------------------
9783    -- GINT Register Masks
9784    ---------------------------------------------------------------------------- */
9785 
9786 /*!
9787  * @addtogroup GINT_Register_Masks GINT Register Masks
9788  * @{
9789  */
9790 
9791 /*! @name CTRL - GPIO grouped interrupt control register */
9792 /*! @{ */
9793 
9794 #define GINT_CTRL_INT_MASK                       (0x1U)
9795 #define GINT_CTRL_INT_SHIFT                      (0U)
9796 /*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
9797  *  0b0..No request. No interrupt request is pending.
9798  *  0b1..Request active. Interrupt request is active.
9799  */
9800 #define GINT_CTRL_INT(x)                         (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
9801 
9802 #define GINT_CTRL_COMB_MASK                      (0x2U)
9803 #define GINT_CTRL_COMB_SHIFT                     (1U)
9804 /*! COMB - Combine enabled inputs for group interrupt
9805  *  0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
9806  *  0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
9807  */
9808 #define GINT_CTRL_COMB(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
9809 
9810 #define GINT_CTRL_TRIG_MASK                      (0x4U)
9811 #define GINT_CTRL_TRIG_SHIFT                     (2U)
9812 /*! TRIG - Group interrupt trigger
9813  *  0b0..Edge-triggered.
9814  *  0b1..Level-triggered.
9815  */
9816 #define GINT_CTRL_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
9817 /*! @} */
9818 
9819 /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
9820 /*! @{ */
9821 
9822 #define GINT_PORT_POL_POL_MASK                   (0xFFFFFFFFU)
9823 #define GINT_PORT_POL_POL_SHIFT                  (0U)
9824 /*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n
9825  *    of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to
9826  *    the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin
9827  *    contributes to the group interrupt.
9828  */
9829 #define GINT_PORT_POL_POL(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
9830 /*! @} */
9831 
9832 /* The count of GINT_PORT_POL */
9833 #define GINT_PORT_POL_COUNT                      (2U)
9834 
9835 /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
9836 /*! @{ */
9837 
9838 #define GINT_PORT_ENA_ENA_MASK                   (0xFFFFFFFFU)
9839 #define GINT_PORT_ENA_ENA_SHIFT                  (0U)
9840 /*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the
9841  *    port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is
9842  *    enabled and contributes to the grouped interrupt.
9843  */
9844 #define GINT_PORT_ENA_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
9845 /*! @} */
9846 
9847 /* The count of GINT_PORT_ENA */
9848 #define GINT_PORT_ENA_COUNT                      (2U)
9849 
9850 
9851 /*!
9852  * @}
9853  */ /* end of group GINT_Register_Masks */
9854 
9855 
9856 /* GINT - Peripheral instance base addresses */
9857 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
9858   /** Peripheral GINT0 base address */
9859   #define GINT0_BASE                               (0x50002000u)
9860   /** Peripheral GINT0 base address */
9861   #define GINT0_BASE_NS                            (0x40002000u)
9862   /** Peripheral GINT0 base pointer */
9863   #define GINT0                                    ((GINT_Type *)GINT0_BASE)
9864   /** Peripheral GINT0 base pointer */
9865   #define GINT0_NS                                 ((GINT_Type *)GINT0_BASE_NS)
9866   /** Peripheral GINT1 base address */
9867   #define GINT1_BASE                               (0x50003000u)
9868   /** Peripheral GINT1 base address */
9869   #define GINT1_BASE_NS                            (0x40003000u)
9870   /** Peripheral GINT1 base pointer */
9871   #define GINT1                                    ((GINT_Type *)GINT1_BASE)
9872   /** Peripheral GINT1 base pointer */
9873   #define GINT1_NS                                 ((GINT_Type *)GINT1_BASE_NS)
9874   /** Array initializer of GINT peripheral base addresses */
9875   #define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
9876   /** Array initializer of GINT peripheral base pointers */
9877   #define GINT_BASE_PTRS                           { GINT0, GINT1 }
9878   /** Array initializer of GINT peripheral base addresses */
9879   #define GINT_BASE_ADDRS_NS                       { GINT0_BASE_NS, GINT1_BASE_NS }
9880   /** Array initializer of GINT peripheral base pointers */
9881   #define GINT_BASE_PTRS_NS                        { GINT0_NS, GINT1_NS }
9882 #else
9883   /** Peripheral GINT0 base address */
9884   #define GINT0_BASE                               (0x40002000u)
9885   /** Peripheral GINT0 base pointer */
9886   #define GINT0                                    ((GINT_Type *)GINT0_BASE)
9887   /** Peripheral GINT1 base address */
9888   #define GINT1_BASE                               (0x40003000u)
9889   /** Peripheral GINT1 base pointer */
9890   #define GINT1                                    ((GINT_Type *)GINT1_BASE)
9891   /** Array initializer of GINT peripheral base addresses */
9892   #define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
9893   /** Array initializer of GINT peripheral base pointers */
9894   #define GINT_BASE_PTRS                           { GINT0, GINT1 }
9895 #endif
9896 /** Interrupt vectors for the GINT peripheral type */
9897 #define GINT_IRQS                                { GINT0_IRQn, GINT1_IRQn }
9898 
9899 /*!
9900  * @}
9901  */ /* end of group GINT_Peripheral_Access_Layer */
9902 
9903 
9904 /* ----------------------------------------------------------------------------
9905    -- GPIO Peripheral Access Layer
9906    ---------------------------------------------------------------------------- */
9907 
9908 /*!
9909  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
9910  * @{
9911  */
9912 
9913 /** GPIO - Register Layout Typedef */
9914 typedef struct {
9915   __IO uint8_t B[2][32];                           /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
9916        uint8_t RESERVED_0[4032];
9917   __IO uint32_t W[2][32];                          /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
9918        uint8_t RESERVED_1[3840];
9919   __IO uint32_t DIR[2];                            /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */
9920        uint8_t RESERVED_2[120];
9921   __IO uint32_t MASK[2];                           /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */
9922        uint8_t RESERVED_3[120];
9923   __IO uint32_t PIN[2];                            /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */
9924        uint8_t RESERVED_4[120];
9925   __IO uint32_t MPIN[2];                           /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */
9926        uint8_t RESERVED_5[120];
9927   __IO uint32_t SET[2];                            /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */
9928        uint8_t RESERVED_6[120];
9929   __O  uint32_t CLR[2];                            /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */
9930        uint8_t RESERVED_7[120];
9931   __O  uint32_t NOT[2];                            /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */
9932        uint8_t RESERVED_8[120];
9933   __O  uint32_t DIRSET[2];                         /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
9934        uint8_t RESERVED_9[120];
9935   __O  uint32_t DIRCLR[2];                         /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
9936        uint8_t RESERVED_10[120];
9937   __O  uint32_t DIRNOT[2];                         /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
9938 } GPIO_Type;
9939 
9940 /* ----------------------------------------------------------------------------
9941    -- GPIO Register Masks
9942    ---------------------------------------------------------------------------- */
9943 
9944 /*!
9945  * @addtogroup GPIO_Register_Masks GPIO Register Masks
9946  * @{
9947  */
9948 
9949 /*! @name B - Byte pin registers for all port GPIO pins */
9950 /*! @{ */
9951 
9952 #define GPIO_B_PBYTE_MASK                        (0x1U)
9953 #define GPIO_B_PBYTE_SHIFT                       (0U)
9954 /*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
9955  *    except that pins configured as analog I/O always read as 0. One register for each port pin.
9956  *    Supported pins depends on the specific device and package. Write: loads the pin's output bit.
9957  *    One register for each port pin. Supported pins depends on the specific device and package.
9958  */
9959 #define GPIO_B_PBYTE(x)                          (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
9960 /*! @} */
9961 
9962 /* The count of GPIO_B */
9963 #define GPIO_B_COUNT                             (2U)
9964 
9965 /* The count of GPIO_B */
9966 #define GPIO_B_COUNT2                            (32U)
9967 
9968 /*! @name W - Word pin registers for all port GPIO pins */
9969 /*! @{ */
9970 
9971 #define GPIO_W_PWORD_MASK                        (0xFFFFFFFFU)
9972 #define GPIO_W_PWORD_SHIFT                       (0U)
9973 /*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
9974  *    HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
9975  *    read. Writing any value other than 0 will set the output bit. One register for each port pin.
9976  *    Supported pins depends on the specific device and package.
9977  */
9978 #define GPIO_W_PWORD(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
9979 /*! @} */
9980 
9981 /* The count of GPIO_W */
9982 #define GPIO_W_COUNT                             (2U)
9983 
9984 /* The count of GPIO_W */
9985 #define GPIO_W_COUNT2                            (32U)
9986 
9987 /*! @name DIR - Direction registers for all port GPIO pins */
9988 /*! @{ */
9989 
9990 #define GPIO_DIR_DIRP_MASK                       (0xFFFFFFFFU)
9991 #define GPIO_DIR_DIRP_SHIFT                      (0U)
9992 /*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
9993  *    pins depends on the specific device and package. 0 = input. 1 = output.
9994  */
9995 #define GPIO_DIR_DIRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
9996 /*! @} */
9997 
9998 /* The count of GPIO_DIR */
9999 #define GPIO_DIR_COUNT                           (2U)
10000 
10001 /*! @name MASK - Mask register for all port GPIO pins */
10002 /*! @{ */
10003 
10004 #define GPIO_MASK_MASKP_MASK                     (0xFFFFFFFFU)
10005 #define GPIO_MASK_MASKP_SHIFT                    (0U)
10006 /*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
10007  *    PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 =
10008  *    Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
10009  *    not affected.
10010  */
10011 #define GPIO_MASK_MASKP(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
10012 /*! @} */
10013 
10014 /* The count of GPIO_MASK */
10015 #define GPIO_MASK_COUNT                          (2U)
10016 
10017 /*! @name PIN - Port pin register for all port GPIO pins */
10018 /*! @{ */
10019 
10020 #define GPIO_PIN_PORT_MASK                       (0xFFFFFFFFU)
10021 #define GPIO_PIN_PORT_SHIFT                      (0U)
10022 /*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
10023  *    pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
10024  *    1 = Read: pin is high; write: set output bit.
10025  */
10026 #define GPIO_PIN_PORT(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
10027 /*! @} */
10028 
10029 /* The count of GPIO_PIN */
10030 #define GPIO_PIN_COUNT                           (2U)
10031 
10032 /*! @name MPIN - Masked port register for all port GPIO pins */
10033 /*! @{ */
10034 
10035 #define GPIO_MPIN_MPORTP_MASK                    (0xFFFFFFFFU)
10036 #define GPIO_MPIN_MPORTP_SHIFT                   (0U)
10037 /*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
10038  *    the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
10039  *    register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
10040  *    = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
10041  *    if the corresponding bit in the MASK register is 0.
10042  */
10043 #define GPIO_MPIN_MPORTP(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
10044 /*! @} */
10045 
10046 /* The count of GPIO_MPIN */
10047 #define GPIO_MPIN_COUNT                          (2U)
10048 
10049 /*! @name SET - Write: Set register for port. Read: output bits for port */
10050 /*! @{ */
10051 
10052 #define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
10053 #define GPIO_SET_SETP_SHIFT                      (0U)
10054 /*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
10055  *    the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
10056  *    bit; write: set output bit.
10057  */
10058 #define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
10059 /*! @} */
10060 
10061 /* The count of GPIO_SET */
10062 #define GPIO_SET_COUNT                           (2U)
10063 
10064 /*! @name CLR - Clear port for all port GPIO pins */
10065 /*! @{ */
10066 
10067 #define GPIO_CLR_CLRP_MASK                       (0xFFFFFFFFU)
10068 #define GPIO_CLR_CLRP_SHIFT                      (0U)
10069 /*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
10070  *    specific device and package. 0 = No operation. 1 = Clear output bit.
10071  */
10072 #define GPIO_CLR_CLRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
10073 /*! @} */
10074 
10075 /* The count of GPIO_CLR */
10076 #define GPIO_CLR_COUNT                           (2U)
10077 
10078 /*! @name NOT - Toggle port for all port GPIO pins */
10079 /*! @{ */
10080 
10081 #define GPIO_NOT_NOTP_MASK                       (0xFFFFFFFFU)
10082 #define GPIO_NOT_NOTP_SHIFT                      (0U)
10083 /*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
10084  *    specific device and package. 0 = no operation. 1 = Toggle output bit.
10085  */
10086 #define GPIO_NOT_NOTP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
10087 /*! @} */
10088 
10089 /* The count of GPIO_NOT */
10090 #define GPIO_NOT_COUNT                           (2U)
10091 
10092 /*! @name DIRSET - Set pin direction bits for port */
10093 /*! @{ */
10094 
10095 #define GPIO_DIRSET_DIRSETP_MASK                 (0xFFFFFFFFU)
10096 #define GPIO_DIRSET_DIRSETP_SHIFT                (0U)
10097 /*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
10098  *    the specific device and package. 0 = No operation. 1 = Set direction bit.
10099  */
10100 #define GPIO_DIRSET_DIRSETP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
10101 /*! @} */
10102 
10103 /* The count of GPIO_DIRSET */
10104 #define GPIO_DIRSET_COUNT                        (2U)
10105 
10106 /*! @name DIRCLR - Clear pin direction bits for port */
10107 /*! @{ */
10108 
10109 #define GPIO_DIRCLR_DIRCLRP_MASK                 (0xFFFFFFFFU)
10110 #define GPIO_DIRCLR_DIRCLRP_SHIFT                (0U)
10111 /*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
10112  *    the specific device and package. 0 = No operation. 1 = Clear direction bit.
10113  */
10114 #define GPIO_DIRCLR_DIRCLRP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
10115 /*! @} */
10116 
10117 /* The count of GPIO_DIRCLR */
10118 #define GPIO_DIRCLR_COUNT                        (2U)
10119 
10120 /*! @name DIRNOT - Toggle pin direction bits for port */
10121 /*! @{ */
10122 
10123 #define GPIO_DIRNOT_DIRNOTP_MASK                 (0xFFFFFFFFU)
10124 #define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
10125 /*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
10126  *    on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
10127  */
10128 #define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
10129 /*! @} */
10130 
10131 /* The count of GPIO_DIRNOT */
10132 #define GPIO_DIRNOT_COUNT                        (2U)
10133 
10134 
10135 /*!
10136  * @}
10137  */ /* end of group GPIO_Register_Masks */
10138 
10139 
10140 /* GPIO - Peripheral instance base addresses */
10141 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
10142   /** Peripheral GPIO base address */
10143   #define GPIO_BASE                                (0x5008C000u)
10144   /** Peripheral GPIO base address */
10145   #define GPIO_BASE_NS                             (0x4008C000u)
10146   /** Peripheral GPIO base pointer */
10147   #define GPIO                                     ((GPIO_Type *)GPIO_BASE)
10148   /** Peripheral GPIO base pointer */
10149   #define GPIO_NS                                  ((GPIO_Type *)GPIO_BASE_NS)
10150   /** Peripheral SECGPIO base address */
10151   #define SECGPIO_BASE                             (0x500A8000u)
10152   /** Peripheral SECGPIO base address */
10153   #define SECGPIO_BASE_NS                          (0x400A8000u)
10154   /** Peripheral SECGPIO base pointer */
10155   #define SECGPIO                                  ((GPIO_Type *)SECGPIO_BASE)
10156   /** Peripheral SECGPIO base pointer */
10157   #define SECGPIO_NS                               ((GPIO_Type *)SECGPIO_BASE_NS)
10158   /** Array initializer of GPIO peripheral base addresses */
10159   #define GPIO_BASE_ADDRS                          { GPIO_BASE, SECGPIO_BASE }
10160   /** Array initializer of GPIO peripheral base pointers */
10161   #define GPIO_BASE_PTRS                           { GPIO, SECGPIO }
10162   /** Array initializer of GPIO peripheral base addresses */
10163   #define GPIO_BASE_ADDRS_NS                       { GPIO_BASE_NS, SECGPIO_BASE_NS }
10164   /** Array initializer of GPIO peripheral base pointers */
10165   #define GPIO_BASE_PTRS_NS                        { GPIO_NS, SECGPIO_NS }
10166 #else
10167   /** Peripheral GPIO base address */
10168   #define GPIO_BASE                                (0x4008C000u)
10169   /** Peripheral GPIO base pointer */
10170   #define GPIO                                     ((GPIO_Type *)GPIO_BASE)
10171   /** Peripheral SECGPIO base address */
10172   #define SECGPIO_BASE                             (0x400A8000u)
10173   /** Peripheral SECGPIO base pointer */
10174   #define SECGPIO                                  ((GPIO_Type *)SECGPIO_BASE)
10175   /** Array initializer of GPIO peripheral base addresses */
10176   #define GPIO_BASE_ADDRS                          { GPIO_BASE, SECGPIO_BASE }
10177   /** Array initializer of GPIO peripheral base pointers */
10178   #define GPIO_BASE_PTRS                           { GPIO, SECGPIO }
10179 #endif
10180 
10181 /*!
10182  * @}
10183  */ /* end of group GPIO_Peripheral_Access_Layer */
10184 
10185 
10186 /* ----------------------------------------------------------------------------
10187    -- HASHCRYPT Peripheral Access Layer
10188    ---------------------------------------------------------------------------- */
10189 
10190 /*!
10191  * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer
10192  * @{
10193  */
10194 
10195 /** HASHCRYPT - Register Layout Typedef */
10196 typedef struct {
10197   __IO uint32_t CTRL;                              /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */
10198   __IO uint32_t STATUS;                            /**< Indicates status of Hash peripheral., offset: 0x4 */
10199   __IO uint32_t INTENSET;                          /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */
10200   __IO uint32_t INTENCLR;                          /**< Write 1 to clear interrupts., offset: 0xC */
10201   __IO uint32_t MEMCTRL;                           /**< Setup Master to access memory (if available), offset: 0x10 */
10202   __IO uint32_t MEMADDR;                           /**< Address to start memory access from (if available)., offset: 0x14 */
10203        uint8_t RESERVED_0[8];
10204   __O  uint32_t INDATA;                            /**< Input of 16 words at a time to load up buffer., offset: 0x20 */
10205   __O  uint32_t ALIAS[7];                          /**< , array offset: 0x24, array step: 0x4 */
10206   __I  uint32_t DIGEST0[8];                        /**< , array offset: 0x40, array step: 0x4 */
10207        uint8_t RESERVED_1[32];
10208   __IO uint32_t CRYPTCFG;                          /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */
10209   __I  uint32_t CONFIG;                            /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */
10210        uint8_t RESERVED_2[4];
10211   __IO uint32_t LOCK;                              /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */
10212   __O  uint32_t MASK[4];                           /**< , array offset: 0x90, array step: 0x4 */
10213 } HASHCRYPT_Type;
10214 
10215 /* ----------------------------------------------------------------------------
10216    -- HASHCRYPT Register Masks
10217    ---------------------------------------------------------------------------- */
10218 
10219 /*!
10220  * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks
10221  * @{
10222  */
10223 
10224 /*! @name CTRL - Control register to enable and operate Hash and Crypto */
10225 /*! @{ */
10226 
10227 #define HASHCRYPT_CTRL_MODE_MASK                 (0x7U)
10228 #define HASHCRYPT_CTRL_MODE_SHIFT                (0U)
10229 /*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if
10230  *    specific modes beyond SHA1 and SHA2-256 are available.
10231  *  0b000..Disabled
10232  *  0b001..SHA1 is enabled
10233  *  0b010..SHA2-256 is enabled
10234  *  0b100..AES if available (see also CRYPTCFG register for more controls)
10235  *  0b101..ICB-AES if available (see also CRYPTCFG register for more controls)
10236  */
10237 #define HASHCRYPT_CTRL_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK)
10238 
10239 #define HASHCRYPT_CTRL_NEW_HASH_MASK             (0x10U)
10240 #define HASHCRYPT_CTRL_NEW_HASH_SHIFT            (4U)
10241 /*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING
10242  *    Status bit will clear for a cycle during the initialization from New=1.
10243  *  0b1..Starts a new Hash/Crypto and initializes the Digest/Result.
10244  */
10245 #define HASHCRYPT_CTRL_NEW_HASH(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK)
10246 
10247 #define HASHCRYPT_CTRL_DMA_I_MASK                (0x100U)
10248 #define HASHCRYPT_CTRL_DMA_I_SHIFT               (8U)
10249 /*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words
10250  *    and then will process the Hash. If Cryptographic, it will load as many words as needed,
10251  *    including key if not already loaded. It will then request again. Normal model is that the DMA
10252  *    interrupts the processor when its length expires. Note that if the processor will write the key and
10253  *    optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be
10254  *    expected to load those for the 1st block (when needed).
10255  *  0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used.
10256  *  0b1..DMA will push in the data.
10257  */
10258 #define HASHCRYPT_CTRL_DMA_I(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK)
10259 
10260 #define HASHCRYPT_CTRL_DMA_O_MASK                (0x200U)
10261 #define HASHCRYPT_CTRL_DMA_O_SHIFT               (9U)
10262 /*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the
10263  *    DMA has to know to switch direction and the locations. This can be used for crypto uses.
10264  *  0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt.
10265  */
10266 #define HASHCRYPT_CTRL_DMA_O(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK)
10267 
10268 #define HASHCRYPT_CTRL_HASHSWPB_MASK             (0x1000U)
10269 #define HASHCRYPT_CTRL_HASHSWPB_SHIFT            (12U)
10270 /*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB
10271  *    is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For
10272  *    cryptographic swapping, see the CRYPTCFG register.
10273  */
10274 #define HASHCRYPT_CTRL_HASHSWPB(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK)
10275 /*! @} */
10276 
10277 /*! @name STATUS - Indicates status of Hash peripheral. */
10278 /*! @{ */
10279 
10280 #define HASHCRYPT_STATUS_WAITING_MASK            (0x1U)
10281 #define HASHCRYPT_STATUS_WAITING_SHIFT           (0U)
10282 /*! WAITING - If 1, the block is waiting for more data to process.
10283  *  0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set
10284  *       if IsLast is set nor will it set until at least 1 word is read of the output.
10285  *  0b1..Waiting for data to be written in (16 words)
10286  */
10287 #define HASHCRYPT_STATUS_WAITING(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK)
10288 
10289 #define HASHCRYPT_STATUS_DIGEST_MASK             (0x2U)
10290 #define HASHCRYPT_STATUS_DIGEST_SHIFT            (1U)
10291 /*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block
10292  *    already started. For Cryptographic uses, this will be set for each block processed, indicating
10293  *    OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared
10294  *    when any data is written, when New is written, for Cryptographic uses when the last word is read
10295  *    out, or when the block is disabled.
10296  *  0b0..No Digest is ready
10297  *  0b1..Digest is ready. Application may read it or may write more data
10298  */
10299 #define HASHCRYPT_STATUS_DIGEST(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK)
10300 
10301 #define HASHCRYPT_STATUS_ERROR_MASK              (0x4U)
10302 #define HASHCRYPT_STATUS_ERROR_SHIFT             (2U)
10303 /*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA
10304  *    was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT
10305  *    field will indicate which block it was on.
10306  *  0b0..No error.
10307  *  0b1..An error occurred since last cleared (written 1 to clear).
10308  */
10309 #define HASHCRYPT_STATUS_ERROR(x)                (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK)
10310 
10311 #define HASHCRYPT_STATUS_NEEDKEY_MASK            (0x10U)
10312 #define HASHCRYPT_STATUS_NEEDKEY_SHIFT           (4U)
10313 /*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING)
10314  *  0b0..No Key is needed and writes will not be treated as Key
10315  *  0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING.
10316  */
10317 #define HASHCRYPT_STATUS_NEEDKEY(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK)
10318 
10319 #define HASHCRYPT_STATUS_NEEDIV_MASK             (0x20U)
10320 #define HASHCRYPT_STATUS_NEEDIV_SHIFT            (5U)
10321 /*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING)
10322  *  0b0..No IV/Nonce is needed, either because written already or because not needed.
10323  *  0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING.
10324  */
10325 #define HASHCRYPT_STATUS_NEEDIV(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK)
10326 
10327 #define HASHCRYPT_STATUS_ICBIDX_MASK             (0x3F0000U)
10328 #define HASHCRYPT_STATUS_ICBIDX_SHIFT            (16U)
10329 /*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from
10330  *    CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0,
10331  *    it has to compute the full ICB, quicker when not 0.
10332  */
10333 #define HASHCRYPT_STATUS_ICBIDX(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK)
10334 /*! @} */
10335 
10336 /*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */
10337 /*! @{ */
10338 
10339 #define HASHCRYPT_INTENSET_WAITING_MASK          (0x1U)
10340 #define HASHCRYPT_INTENSET_WAITING_SHIFT         (0U)
10341 /*! WAITING - Indicates if should interrupt when waiting for data input.
10342  *  0b0..Will not interrupt when waiting.
10343  *  0b1..Will interrupt when waiting
10344  */
10345 #define HASHCRYPT_INTENSET_WAITING(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK)
10346 
10347 #define HASHCRYPT_INTENSET_DIGEST_MASK           (0x2U)
10348 #define HASHCRYPT_INTENSET_DIGEST_SHIFT          (1U)
10349 /*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence).
10350  *  0b0..Will not interrupt when Digest is ready
10351  *  0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done).
10352  */
10353 #define HASHCRYPT_INTENSET_DIGEST(x)             (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK)
10354 
10355 #define HASHCRYPT_INTENSET_ERROR_MASK            (0x4U)
10356 #define HASHCRYPT_INTENSET_ERROR_SHIFT           (2U)
10357 /*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status)
10358  *  0b0..Will not interrupt on Error.
10359  *  0b1..Will interrupt on Error (until cleared).
10360  */
10361 #define HASHCRYPT_INTENSET_ERROR(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK)
10362 /*! @} */
10363 
10364 /*! @name INTENCLR - Write 1 to clear interrupts. */
10365 /*! @{ */
10366 
10367 #define HASHCRYPT_INTENCLR_WAITING_MASK          (0x1U)
10368 #define HASHCRYPT_INTENCLR_WAITING_SHIFT         (0U)
10369 /*! WAITING - Write 1 to clear mask.
10370  */
10371 #define HASHCRYPT_INTENCLR_WAITING(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK)
10372 
10373 #define HASHCRYPT_INTENCLR_DIGEST_MASK           (0x2U)
10374 #define HASHCRYPT_INTENCLR_DIGEST_SHIFT          (1U)
10375 /*! DIGEST - Write 1 to clear mask.
10376  */
10377 #define HASHCRYPT_INTENCLR_DIGEST(x)             (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK)
10378 
10379 #define HASHCRYPT_INTENCLR_ERROR_MASK            (0x4U)
10380 #define HASHCRYPT_INTENCLR_ERROR_SHIFT           (2U)
10381 /*! ERROR - Write 1 to clear mask.
10382  */
10383 #define HASHCRYPT_INTENCLR_ERROR(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK)
10384 /*! @} */
10385 
10386 /*! @name MEMCTRL - Setup Master to access memory (if available) */
10387 /*! @{ */
10388 
10389 #define HASHCRYPT_MEMCTRL_MASTER_MASK            (0x1U)
10390 #define HASHCRYPT_MEMCTRL_MASTER_SHIFT           (0U)
10391 /*! MASTER - Enables mastering.
10392  *  0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA.
10393  *  0b1..Mastering is enabled and DMA and INDATA should not be used.
10394  */
10395 #define HASHCRYPT_MEMCTRL_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK)
10396 
10397 #define HASHCRYPT_MEMCTRL_COUNT_MASK             (0x7FF0000U)
10398 #define HASHCRYPT_MEMCTRL_COUNT_SHIFT            (16U)
10399 /*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks
10400  *    to copy starting at MEMADDR. This register will decrement after each block is copied, ending
10401  *    in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA
10402  *    interrupt will occur on ever block. If a bus error occurs, it will stop with this field set
10403  *    to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit)
10404  *    blocks to hash.
10405  */
10406 #define HASHCRYPT_MEMCTRL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK)
10407 /*! @} */
10408 
10409 /*! @name MEMADDR - Address to start memory access from (if available). */
10410 /*! @{ */
10411 
10412 #define HASHCRYPT_MEMADDR_BASE_MASK              (0xFFFFFFFFU)
10413 #define HASHCRYPT_MEMADDR_BASE_SHIFT             (0U)
10414 /*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will
10415  *    advance as it processes the words. If it fails with a bus error, the register will contain
10416  *    the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be
10417  *    able to address SPIFI.
10418  */
10419 #define HASHCRYPT_MEMADDR_BASE(x)                (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK)
10420 /*! @} */
10421 
10422 /*! @name INDATA - Input of 16 words at a time to load up buffer. */
10423 /*! @{ */
10424 
10425 #define HASHCRYPT_INDATA_DATA_MASK               (0xFFFFFFFFU)
10426 #define HASHCRYPT_INDATA_DATA_SHIFT              (0U)
10427 /*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this
10428  *    block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as
10429  *    bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block
10430  *    will swap the word to restore into big endian.
10431  */
10432 #define HASHCRYPT_INDATA_DATA(x)                 (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK)
10433 /*! @} */
10434 
10435 /*! @name ALIAS -  */
10436 /*! @{ */
10437 
10438 #define HASHCRYPT_ALIAS_DATA_MASK                (0xFFFFFFFFU)
10439 #define HASHCRYPT_ALIAS_DATA_SHIFT               (0U)
10440 /*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this
10441  *    block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as
10442  *    bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block
10443  *    will swap the word to restore into big endian.
10444  */
10445 #define HASHCRYPT_ALIAS_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK)
10446 /*! @} */
10447 
10448 /* The count of HASHCRYPT_ALIAS */
10449 #define HASHCRYPT_ALIAS_COUNT                    (7U)
10450 
10451 /*! @name DIGEST0 -  */
10452 /*! @{ */
10453 
10454 #define HASHCRYPT_DIGEST0_DIGEST_MASK            (0xFFFFFFFFU)
10455 #define HASHCRYPT_DIGEST0_DIGEST_SHIFT           (0U)
10456 /*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1.
10457  */
10458 #define HASHCRYPT_DIGEST0_DIGEST(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK)
10459 /*! @} */
10460 
10461 /* The count of HASHCRYPT_DIGEST0 */
10462 #define HASHCRYPT_DIGEST0_COUNT                  (8U)
10463 
10464 /*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */
10465 /*! @{ */
10466 
10467 #define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK       (0x1U)
10468 #define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT      (0U)
10469 /*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read
10470  *    in normal little endian - Least significant word 1st. Note: only if allowed by configuration.
10471  */
10472 #define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x)         (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK)
10473 
10474 #define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK          (0x2U)
10475 #define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT         (1U)
10476 /*! SWAPKEY - If 1, will Swap the key input (bytes in each word).
10477  */
10478 #define HASHCRYPT_CRYPTCFG_SWAPKEY(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK)
10479 
10480 #define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK          (0x4U)
10481 #define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT         (2U)
10482 /*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word).
10483  */
10484 #define HASHCRYPT_CRYPTCFG_SWAPDAT(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK)
10485 
10486 #define HASHCRYPT_CRYPTCFG_MSW1ST_MASK           (0x8U)
10487 #define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT          (3U)
10488 /*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian.
10489  *    Note: only if allowed by configuration.
10490  */
10491 #define HASHCRYPT_CRYPTCFG_MSW1ST(x)             (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK)
10492 
10493 #define HASHCRYPT_CRYPTCFG_AESMODE_MASK          (0x30U)
10494 #define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT         (4U)
10495 /*! AESMODE - AES Cipher mode to use if plain AES
10496  *  0b00..ECB - used as is
10497  *  0b01..CBC mode (see details on IV/nonce)
10498  *  0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS.
10499  *  0b11..reserved
10500  */
10501 #define HASHCRYPT_CRYPTCFG_AESMODE(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK)
10502 
10503 #define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK       (0x40U)
10504 #define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT      (6U)
10505 /*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB
10506  *  0b0..Encrypt
10507  *  0b1..Decrypt
10508  */
10509 #define HASHCRYPT_CRYPTCFG_AESDECRYPT(x)         (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK)
10510 
10511 #define HASHCRYPT_CRYPTCFG_AESSECRET_MASK        (0x80U)
10512 #define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT       (7U)
10513 /*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are
10514  *    used, only the highest level is permitted to select this.
10515  *  0b0..User key provided in normal way
10516  *  0b1..Secret key provided in hidden way by HW
10517  */
10518 #define HASHCRYPT_CRYPTCFG_AESSECRET(x)          (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK)
10519 
10520 #define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK         (0x300U)
10521 #define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT        (8U)
10522 /*! AESKEYSZ - Sets the AES key size
10523  *  0b00..128 bit key
10524  *  0b01..192 bit key
10525  *  0b10..256 bit key
10526  *  0b11..reserved
10527  */
10528 #define HASHCRYPT_CRYPTCFG_AESKEYSZ(x)           (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK)
10529 
10530 #define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK        (0x1C00U)
10531 #define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT       (10U)
10532 /*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for
10533  *    Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if
10534  *    using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other
10535  *    use CTR should use ECB directly and do its own XOR and so on.
10536  */
10537 #define HASHCRYPT_CRYPTCFG_AESCTRPOS(x)          (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK)
10538 
10539 #define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK       (0x10000U)
10540 #define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT      (16U)
10541 /*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash".
10542  */
10543 #define HASHCRYPT_CRYPTCFG_STREAMLAST(x)         (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK)
10544 
10545 #define HASHCRYPT_CRYPTCFG_ICBSZ_MASK            (0x300000U)
10546 #define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT           (20U)
10547 /*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the
10548  *    counter is assumed to occupy the low order bits of the IV.
10549  *  0b00..32 bits of the IV/ctr are used (from 127:96)
10550  *  0b01..64 bits of the IV/ctr are used (from 127:64)
10551  *  0b10..96 bits of the IV/ctr are used (from 127:32)
10552  *  0b11..All 128 bits of the IV/ctr are used
10553  */
10554 #define HASHCRYPT_CRYPTCFG_ICBSZ(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK)
10555 
10556 #define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK          (0xC00000U)
10557 #define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT         (22U)
10558 /*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new
10559  *    IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st.
10560  *  0b00..8 blocks
10561  *  0b01..16 blocks
10562  *  0b10..32 blocks
10563  *  0b11..64 blocks
10564  */
10565 #define HASHCRYPT_CRYPTCFG_ICBSTRM(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK)
10566 /*! @} */
10567 
10568 /*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */
10569 /*! @{ */
10570 
10571 #define HASHCRYPT_CONFIG_DUAL_MASK               (0x1U)
10572 #define HASHCRYPT_CONFIG_DUAL_SHIFT              (0U)
10573 /*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit
10574  */
10575 #define HASHCRYPT_CONFIG_DUAL(x)                 (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK)
10576 
10577 #define HASHCRYPT_CONFIG_DMA_MASK                (0x2U)
10578 #define HASHCRYPT_CONFIG_DMA_SHIFT               (1U)
10579 /*! DMA - 1 if DMA is connected
10580  */
10581 #define HASHCRYPT_CONFIG_DMA(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK)
10582 
10583 #define HASHCRYPT_CONFIG_AHB_MASK                (0x8U)
10584 #define HASHCRYPT_CONFIG_AHB_SHIFT               (3U)
10585 /*! AHB - 1 if AHB Master is enabled
10586  */
10587 #define HASHCRYPT_CONFIG_AHB(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK)
10588 
10589 #define HASHCRYPT_CONFIG_AES_MASK                (0x40U)
10590 #define HASHCRYPT_CONFIG_AES_SHIFT               (6U)
10591 /*! AES - 1 if AES 128 included
10592  */
10593 #define HASHCRYPT_CONFIG_AES(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK)
10594 
10595 #define HASHCRYPT_CONFIG_AESKEY_MASK             (0x80U)
10596 #define HASHCRYPT_CONFIG_AESKEY_SHIFT            (7U)
10597 /*! AESKEY - 1 if AES 192 and 256 also included
10598  */
10599 #define HASHCRYPT_CONFIG_AESKEY(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK)
10600 
10601 #define HASHCRYPT_CONFIG_SECRET_MASK             (0x100U)
10602 #define HASHCRYPT_CONFIG_SECRET_SHIFT            (8U)
10603 /*! SECRET - 1 if AES Secret key available
10604  */
10605 #define HASHCRYPT_CONFIG_SECRET(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK)
10606 
10607 #define HASHCRYPT_CONFIG_ICB_MASK                (0x800U)
10608 #define HASHCRYPT_CONFIG_ICB_SHIFT               (11U)
10609 /*! ICB - 1 if ICB over AES included
10610  */
10611 #define HASHCRYPT_CONFIG_ICB(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK)
10612 /*! @} */
10613 
10614 /*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */
10615 /*! @{ */
10616 
10617 #define HASHCRYPT_LOCK_SECLOCK_MASK              (0x3U)
10618 #define HASHCRYPT_LOCK_SECLOCK_SHIFT             (0U)
10619 /*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock.
10620  *    If locked already, may only write if at same or higher security level as lock. Reads as: 0 if
10621  *    unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the
10622  *    only readable registers if locked and current state is lower than lock level.
10623  *  0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests.
10624  *  0b01..Locks to the current security level. AHB Master will issue requests at this level.
10625  */
10626 #define HASHCRYPT_LOCK_SECLOCK(x)                (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK)
10627 
10628 #define HASHCRYPT_LOCK_PATTERN_MASK              (0xFFF0U)
10629 #define HASHCRYPT_LOCK_PATTERN_SHIFT             (4U)
10630 /*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0
10631  */
10632 #define HASHCRYPT_LOCK_PATTERN(x)                (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK)
10633 /*! @} */
10634 
10635 /*! @name MASK -  */
10636 /*! @{ */
10637 
10638 #define HASHCRYPT_MASK_MASK_MASK                 (0xFFFFFFFFU)
10639 #define HASHCRYPT_MASK_MASK_SHIFT                (0U)
10640 /*! MASK - A random word.
10641  */
10642 #define HASHCRYPT_MASK_MASK(x)                   (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK)
10643 /*! @} */
10644 
10645 /* The count of HASHCRYPT_MASK */
10646 #define HASHCRYPT_MASK_COUNT                     (4U)
10647 
10648 
10649 /*!
10650  * @}
10651  */ /* end of group HASHCRYPT_Register_Masks */
10652 
10653 
10654 /* HASHCRYPT - Peripheral instance base addresses */
10655 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
10656   /** Peripheral HASHCRYPT base address */
10657   #define HASHCRYPT_BASE                           (0x500A4000u)
10658   /** Peripheral HASHCRYPT base address */
10659   #define HASHCRYPT_BASE_NS                        (0x400A4000u)
10660   /** Peripheral HASHCRYPT base pointer */
10661   #define HASHCRYPT                                ((HASHCRYPT_Type *)HASHCRYPT_BASE)
10662   /** Peripheral HASHCRYPT base pointer */
10663   #define HASHCRYPT_NS                             ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS)
10664   /** Array initializer of HASHCRYPT peripheral base addresses */
10665   #define HASHCRYPT_BASE_ADDRS                     { HASHCRYPT_BASE }
10666   /** Array initializer of HASHCRYPT peripheral base pointers */
10667   #define HASHCRYPT_BASE_PTRS                      { HASHCRYPT }
10668   /** Array initializer of HASHCRYPT peripheral base addresses */
10669   #define HASHCRYPT_BASE_ADDRS_NS                  { HASHCRYPT_BASE_NS }
10670   /** Array initializer of HASHCRYPT peripheral base pointers */
10671   #define HASHCRYPT_BASE_PTRS_NS                   { HASHCRYPT_NS }
10672 #else
10673   /** Peripheral HASHCRYPT base address */
10674   #define HASHCRYPT_BASE                           (0x400A4000u)
10675   /** Peripheral HASHCRYPT base pointer */
10676   #define HASHCRYPT                                ((HASHCRYPT_Type *)HASHCRYPT_BASE)
10677   /** Array initializer of HASHCRYPT peripheral base addresses */
10678   #define HASHCRYPT_BASE_ADDRS                     { HASHCRYPT_BASE }
10679   /** Array initializer of HASHCRYPT peripheral base pointers */
10680   #define HASHCRYPT_BASE_PTRS                      { HASHCRYPT }
10681 #endif
10682 
10683 /*!
10684  * @}
10685  */ /* end of group HASHCRYPT_Peripheral_Access_Layer */
10686 
10687 
10688 /* ----------------------------------------------------------------------------
10689    -- I2C Peripheral Access Layer
10690    ---------------------------------------------------------------------------- */
10691 
10692 /*!
10693  * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
10694  * @{
10695  */
10696 
10697 /** I2C - Register Layout Typedef */
10698 typedef struct {
10699        uint8_t RESERVED_0[2048];
10700   __IO uint32_t CFG;                               /**< Configuration for shared functions., offset: 0x800 */
10701   __IO uint32_t STAT;                              /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
10702   __IO uint32_t INTENSET;                          /**< Interrupt Enable Set and read register., offset: 0x808 */
10703   __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register., offset: 0x80C */
10704   __IO uint32_t TIMEOUT;                           /**< Time-out value register., offset: 0x810 */
10705   __IO uint32_t CLKDIV;                            /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
10706   __I  uint32_t INTSTAT;                           /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
10707        uint8_t RESERVED_1[4];
10708   __IO uint32_t MSTCTL;                            /**< Master control register., offset: 0x820 */
10709   __IO uint32_t MSTTIME;                           /**< Master timing configuration., offset: 0x824 */
10710   __IO uint32_t MSTDAT;                            /**< Combined Master receiver and transmitter data register., offset: 0x828 */
10711        uint8_t RESERVED_2[20];
10712   __IO uint32_t SLVCTL;                            /**< Slave control register., offset: 0x840 */
10713   __IO uint32_t SLVDAT;                            /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
10714   __IO uint32_t SLVADR[4];                         /**< Slave address register., array offset: 0x848, array step: 0x4 */
10715   __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for address 0., offset: 0x858 */
10716        uint8_t RESERVED_3[36];
10717   __I  uint32_t MONRXDAT;                          /**< Monitor receiver data register., offset: 0x880 */
10718        uint8_t RESERVED_4[1912];
10719   __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
10720 } I2C_Type;
10721 
10722 /* ----------------------------------------------------------------------------
10723    -- I2C Register Masks
10724    ---------------------------------------------------------------------------- */
10725 
10726 /*!
10727  * @addtogroup I2C_Register_Masks I2C Register Masks
10728  * @{
10729  */
10730 
10731 /*! @name CFG - Configuration for shared functions. */
10732 /*! @{ */
10733 
10734 #define I2C_CFG_MSTEN_MASK                       (0x1U)
10735 #define I2C_CFG_MSTEN_SHIFT                      (0U)
10736 /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
10737  *    changed, but the Master function is internally reset.
10738  *  0b0..Disabled. The I2C Master function is disabled.
10739  *  0b1..Enabled. The I2C Master function is enabled.
10740  */
10741 #define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
10742 
10743 #define I2C_CFG_SLVEN_MASK                       (0x2U)
10744 #define I2C_CFG_SLVEN_SHIFT                      (1U)
10745 /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
10746  *    changed, but the Slave function is internally reset.
10747  *  0b0..Disabled. The I2C slave function is disabled.
10748  *  0b1..Enabled. The I2C slave function is enabled.
10749  */
10750 #define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
10751 
10752 #define I2C_CFG_MONEN_MASK                       (0x4U)
10753 #define I2C_CFG_MONEN_SHIFT                      (2U)
10754 /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
10755  *    changed, but the Monitor function is internally reset.
10756  *  0b0..Disabled. The I2C Monitor function is disabled.
10757  *  0b1..Enabled. The I2C Monitor function is enabled.
10758  */
10759 #define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
10760 
10761 #define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
10762 #define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
10763 /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
10764  *  0b0..Disabled. Time-out function is disabled.
10765  *  0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
10766  *       interrupts if they are enabled. Typically, only one time-out will be used in a system.
10767  */
10768 #define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
10769 
10770 #define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
10771 #define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
10772 /*! MONCLKSTR - Monitor function Clock Stretching.
10773  *  0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
10774  *       to read data provided by the Monitor function before it is overwritten. This mode may be used when
10775  *       non-invasive monitoring is critical.
10776  *  0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
10777  *       read all incoming data supplied by the Monitor function.
10778  */
10779 #define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
10780 
10781 #define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
10782 #define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
10783 /*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive
10784  *    and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies
10785  *    to all functions: Master, Slave, and Monitor.
10786  *  0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the
10787  *       extent that the pin electronics support these modes. Any changes that need to be made to the pin controls,
10788  *       such as changing the drive strength or filtering, must be made by software via the IOCON register associated
10789  *       with each I2C pin,
10790  *  0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support
10791  *       High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more
10792  *       information.
10793  */
10794 #define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
10795 /*! @} */
10796 
10797 /*! @name STAT - Status register for Master, Slave, and Monitor functions. */
10798 /*! @{ */
10799 
10800 #define I2C_STAT_MSTPENDING_MASK                 (0x1U)
10801 #define I2C_STAT_MSTPENDING_SHIFT                (0U)
10802 /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
10803  *    the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
10804  *    type of software service if any the master expects. This flag will cause an interrupt when set
10805  *    if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
10806  *    an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
10807  *    state, and no communication is needed, mask this interrupt.
10808  *  0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
10809  *  0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
10810  *       idle state, it is waiting to receive or transmit data or the NACK bit.
10811  */
10812 #define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
10813 
10814 #define I2C_STAT_MSTSTATE_MASK                   (0xEU)
10815 #define I2C_STAT_MSTSTATE_SHIFT                  (1U)
10816 /*! MSTSTATE - Master State code. The master state code reflects the master state when the
10817  *    MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
10818  *    indicates a specific required service for the Master function. All other values are reserved. See
10819  *    Table 400 for details of state values and appropriate responses.
10820  *  0b000..Idle. The Master function is available to be used for a new transaction.
10821  *  0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
10822  *  0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
10823  *  0b011..NACK Address. Slave NACKed address.
10824  *  0b100..NACK Data. Slave NACKed transmitted data.
10825  */
10826 #define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
10827 
10828 #define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
10829 #define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
10830 /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
10831  *    this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
10832  *  0b0..No Arbitration Loss has occurred.
10833  *  0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
10834  *       function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
10835  *       or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
10836  */
10837 #define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
10838 
10839 #define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
10840 #define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
10841 /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
10842  *    this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
10843  *  0b0..No Start/Stop Error has occurred.
10844  *  0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
10845  *       not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
10846  *       idle state, no action is required. A request for a Start could be made, or software could attempt to insure
10847  *       that the bus has not stalled.
10848  */
10849 #define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
10850 
10851 #define I2C_STAT_SLVPENDING_MASK                 (0x100U)
10852 #define I2C_STAT_SLVPENDING_SHIFT                (8U)
10853 /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
10854  *    communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
10855  *    enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
10856  *    SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
10857  *    automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
10858  *    when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
10859  *    25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
10860  *    detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
10861  *    also be detected automatically, since the address must be acknowledged before the clock can be
10862  *    stretched.
10863  *  0b0..In progress. The Slave function does not currently need service.
10864  *  0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
10865  */
10866 #define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
10867 
10868 #define I2C_STAT_SLVSTATE_MASK                   (0x600U)
10869 #define I2C_STAT_SLVSTATE_SHIFT                  (9U)
10870 /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
10871  *    the Slave function. All other values are reserved. See Table 401 for state values and actions.
10872  *    note that the occurrence of some states and how they are handled are affected by DMA mode and
10873  *    Automatic Operation modes.
10874  *  0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
10875  *  0b01..Slave receive. Received data is available (Slave Receiver mode).
10876  *  0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
10877  */
10878 #define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
10879 
10880 #define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
10881 #define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
10882 /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
10883  *    This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
10884  *    operation. This read-only flag reflects the slave function status in real time.
10885  *  0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
10886  *  0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
10887  *       Power-down mode could be entered at this time.
10888  */
10889 #define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
10890 
10891 #define I2C_STAT_SLVIDX_MASK                     (0x3000U)
10892 #define I2C_STAT_SLVIDX_SHIFT                    (12U)
10893 /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
10894  *    selected by receiving an address that matches one of the slave addresses defined by any enabled
10895  *    slave address registers, and provides an identification of the address that was matched. It is
10896  *    possible that more than one address could be matched, but only one match can be reported here.
10897  *  0b00..Address 0. Slave address 0 was matched.
10898  *  0b01..Address 1. Slave address 1 was matched.
10899  *  0b10..Address 2. Slave address 2 was matched.
10900  *  0b11..Address 3. Slave address 3 was matched.
10901  */
10902 #define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
10903 
10904 #define I2C_STAT_SLVSEL_MASK                     (0x4000U)
10905 #define I2C_STAT_SLVSEL_SHIFT                    (14U)
10906 /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
10907  *    function to acknowledge the address, or when the address has been automatically acknowledged.
10908  *    It is cleared when another address cycle presents an address that does not match an enabled
10909  *    address on the Slave function, when slave software decides to NACK a matched address, when
10910  *    there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
10911  *    Automatic Operation. SLVSEL is not cleared if software NACKs data.
10912  *  0b0..Not selected. The Slave function is not currently selected.
10913  *  0b1..Selected. The Slave function is currently selected.
10914  */
10915 #define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
10916 
10917 #define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
10918 #define I2C_STAT_SLVDESEL_SHIFT                  (15U)
10919 /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
10920  *    INTENSET. This flag can be cleared by writing a 1 to this bit.
10921  *  0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
10922  *       selected. That information can be found in the SLVSEL flag.
10923  *  0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
10924  *       changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
10925  */
10926 #define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
10927 
10928 #define I2C_STAT_MONRDY_MASK                     (0x10000U)
10929 #define I2C_STAT_MONRDY_SHIFT                    (16U)
10930 /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
10931  *  0b0..No data. The Monitor function does not currently have data available.
10932  *  0b1..Data waiting. The Monitor function has data waiting to be read.
10933  */
10934 #define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
10935 
10936 #define I2C_STAT_MONOV_MASK                      (0x20000U)
10937 #define I2C_STAT_MONOV_SHIFT                     (17U)
10938 /*! MONOV - Monitor Overflow flag.
10939  *  0b0..No overrun. Monitor data has not overrun.
10940  *  0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
10941  *       enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
10942  */
10943 #define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
10944 
10945 #define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
10946 #define I2C_STAT_MONACTIVE_SHIFT                 (18U)
10947 /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
10948  *    be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
10949  *    more recently than a bus Stop.
10950  *  0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
10951  *  0b1..Active. The Monitor function considers the I2C bus to be active.
10952  */
10953 #define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
10954 
10955 #define I2C_STAT_MONIDLE_MASK                    (0x80000U)
10956 #define I2C_STAT_MONIDLE_SHIFT                   (19U)
10957 /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
10958  *    from active to inactive. This can be used by software to decide when to process data
10959  *    accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
10960  *    INTENSET register. The flag can be cleared by writing a 1 to this bit.
10961  *  0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
10962  *  0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
10963  */
10964 #define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
10965 
10966 #define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
10967 #define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
10968 /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
10969  *    longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
10970  *    edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
10971  *    is idle.
10972  *  0b0..No time-out. I2C bus events have not caused a time-out.
10973  *  0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
10974  */
10975 #define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
10976 
10977 #define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
10978 #define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
10979 /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
10980  *    time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
10981  *  0b0..No time-out. SCL low time has not caused a time-out.
10982  *  0b1..Time-out. SCL low time has caused a time-out.
10983  */
10984 #define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
10985 /*! @} */
10986 
10987 /*! @name INTENSET - Interrupt Enable Set and read register. */
10988 /*! @{ */
10989 
10990 #define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
10991 #define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
10992 /*! MSTPENDINGEN - Master Pending interrupt Enable.
10993  *  0b0..Disabled. The MstPending interrupt is disabled.
10994  *  0b1..Enabled. The MstPending interrupt is enabled.
10995  */
10996 #define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
10997 
10998 #define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
10999 #define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
11000 /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
11001  *  0b0..Disabled. The MstArbLoss interrupt is disabled.
11002  *  0b1..Enabled. The MstArbLoss interrupt is enabled.
11003  */
11004 #define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
11005 
11006 #define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
11007 #define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
11008 /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
11009  *  0b0..Disabled. The MstStStpErr interrupt is disabled.
11010  *  0b1..Enabled. The MstStStpErr interrupt is enabled.
11011  */
11012 #define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
11013 
11014 #define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
11015 #define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
11016 /*! SLVPENDINGEN - Slave Pending interrupt Enable.
11017  *  0b0..Disabled. The SlvPending interrupt is disabled.
11018  *  0b1..Enabled. The SlvPending interrupt is enabled.
11019  */
11020 #define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
11021 
11022 #define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
11023 #define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
11024 /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
11025  *  0b0..Disabled. The SlvNotStr interrupt is disabled.
11026  *  0b1..Enabled. The SlvNotStr interrupt is enabled.
11027  */
11028 #define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
11029 
11030 #define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
11031 #define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
11032 /*! SLVDESELEN - Slave Deselect interrupt Enable.
11033  *  0b0..Disabled. The SlvDeSel interrupt is disabled.
11034  *  0b1..Enabled. The SlvDeSel interrupt is enabled.
11035  */
11036 #define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
11037 
11038 #define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
11039 #define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
11040 /*! MONRDYEN - Monitor data Ready interrupt Enable.
11041  *  0b0..Disabled. The MonRdy interrupt is disabled.
11042  *  0b1..Enabled. The MonRdy interrupt is enabled.
11043  */
11044 #define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
11045 
11046 #define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
11047 #define I2C_INTENSET_MONOVEN_SHIFT               (17U)
11048 /*! MONOVEN - Monitor Overrun interrupt Enable.
11049  *  0b0..Disabled. The MonOv interrupt is disabled.
11050  *  0b1..Enabled. The MonOv interrupt is enabled.
11051  */
11052 #define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
11053 
11054 #define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
11055 #define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
11056 /*! MONIDLEEN - Monitor Idle interrupt Enable.
11057  *  0b0..Disabled. The MonIdle interrupt is disabled.
11058  *  0b1..Enabled. The MonIdle interrupt is enabled.
11059  */
11060 #define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
11061 
11062 #define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
11063 #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
11064 /*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
11065  *  0b0..Disabled. The Event time-out interrupt is disabled.
11066  *  0b1..Enabled. The Event time-out interrupt is enabled.
11067  */
11068 #define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
11069 
11070 #define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
11071 #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
11072 /*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
11073  *  0b0..Disabled. The SCL time-out interrupt is disabled.
11074  *  0b1..Enabled. The SCL time-out interrupt is enabled.
11075  */
11076 #define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
11077 /*! @} */
11078 
11079 /*! @name INTENCLR - Interrupt Enable Clear register. */
11080 /*! @{ */
11081 
11082 #define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
11083 #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
11084 /*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
11085  *    bit in the INTENSET register if implemented.
11086  */
11087 #define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
11088 
11089 #define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
11090 #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
11091 /*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
11092  */
11093 #define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
11094 
11095 #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
11096 #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
11097 /*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
11098  */
11099 #define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
11100 
11101 #define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
11102 #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
11103 /*! SLVPENDINGCLR - Slave Pending interrupt clear.
11104  */
11105 #define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
11106 
11107 #define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
11108 #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
11109 /*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
11110  */
11111 #define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
11112 
11113 #define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
11114 #define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
11115 /*! SLVDESELCLR - Slave Deselect interrupt clear.
11116  */
11117 #define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
11118 
11119 #define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
11120 #define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
11121 /*! MONRDYCLR - Monitor data Ready interrupt clear.
11122  */
11123 #define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
11124 
11125 #define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
11126 #define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
11127 /*! MONOVCLR - Monitor Overrun interrupt clear.
11128  */
11129 #define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
11130 
11131 #define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
11132 #define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
11133 /*! MONIDLECLR - Monitor Idle interrupt clear.
11134  */
11135 #define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
11136 
11137 #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
11138 #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
11139 /*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
11140  */
11141 #define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
11142 
11143 #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
11144 #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
11145 /*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
11146  */
11147 #define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
11148 /*! @} */
11149 
11150 /*! @name TIMEOUT - Time-out value register. */
11151 /*! @{ */
11152 
11153 #define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
11154 #define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
11155 /*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
11156  *    time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
11157  */
11158 #define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
11159 
11160 #define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
11161 #define I2C_TIMEOUT_TO_SHIFT                     (4U)
11162 /*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
11163  *    function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
11164  *    disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
11165  *    time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
11166  *    32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
11167  *    I2C function clock.
11168  */
11169 #define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
11170 /*! @} */
11171 
11172 /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
11173 /*! @{ */
11174 
11175 #define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
11176 #define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
11177 /*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
11178  *    need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
11179  *    FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
11180  *    divided by 65,536 before use.
11181  */
11182 #define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
11183 /*! @} */
11184 
11185 /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
11186 /*! @{ */
11187 
11188 #define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
11189 #define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
11190 /*! MSTPENDING - Master Pending.
11191  */
11192 #define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
11193 
11194 #define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
11195 #define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
11196 /*! MSTARBLOSS - Master Arbitration Loss flag.
11197  */
11198 #define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
11199 
11200 #define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
11201 #define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
11202 /*! MSTSTSTPERR - Master Start/Stop Error flag.
11203  */
11204 #define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
11205 
11206 #define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
11207 #define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
11208 /*! SLVPENDING - Slave Pending.
11209  */
11210 #define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
11211 
11212 #define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
11213 #define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
11214 /*! SLVNOTSTR - Slave Not Stretching status.
11215  */
11216 #define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
11217 
11218 #define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
11219 #define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
11220 /*! SLVDESEL - Slave Deselected flag.
11221  */
11222 #define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
11223 
11224 #define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
11225 #define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
11226 /*! MONRDY - Monitor Ready.
11227  */
11228 #define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
11229 
11230 #define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
11231 #define I2C_INTSTAT_MONOV_SHIFT                  (17U)
11232 /*! MONOV - Monitor Overflow flag.
11233  */
11234 #define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
11235 
11236 #define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
11237 #define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
11238 /*! MONIDLE - Monitor Idle flag.
11239  */
11240 #define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
11241 
11242 #define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
11243 #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
11244 /*! EVENTTIMEOUT - Event time-out Interrupt flag.
11245  */
11246 #define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
11247 
11248 #define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
11249 #define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
11250 /*! SCLTIMEOUT - SCL time-out Interrupt flag.
11251  */
11252 #define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
11253 /*! @} */
11254 
11255 /*! @name MSTCTL - Master control register. */
11256 /*! @{ */
11257 
11258 #define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
11259 #define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
11260 /*! MSTCONTINUE - Master Continue. This bit is write-only.
11261  *  0b0..No effect.
11262  *  0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing
11263  *       transmit data, reading received data, or any other housekeeping related to the next bus operation.
11264  */
11265 #define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
11266 
11267 #define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
11268 #define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
11269 /*! MSTSTART - Master Start control. This bit is write-only.
11270  *  0b0..No effect.
11271  *  0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
11272  */
11273 #define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
11274 
11275 #define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
11276 #define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
11277 /*! MSTSTOP - Master Stop control. This bit is write-only.
11278  *  0b0..No effect.
11279  *  0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
11280  *       if the master is receiving data from the slave (Master Receiver mode).
11281  */
11282 #define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
11283 
11284 #define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
11285 #define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
11286 /*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type
11287  *    operations such as Start, address, Stop, and address match must always be done with software,
11288  *    typically via an interrupt. Address acknowledgement must also be done by software except when
11289  *    the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by
11290  *    hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA
11291  *    must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is
11292  *    read/write.
11293  *  0b0..Disable. No DMA requests are generated for master operation.
11294  *  0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
11295  *       Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
11296  */
11297 #define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
11298 /*! @} */
11299 
11300 /*! @name MSTTIME - Master timing configuration. */
11301 /*! @{ */
11302 
11303 #define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
11304 #define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
11305 /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
11306  *    master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
11307  *    corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
11308  *    tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
11309  *  0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
11310  *  0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
11311  *  0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
11312  *  0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
11313  *  0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
11314  *  0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
11315  *  0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
11316  *  0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
11317  */
11318 #define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
11319 
11320 #define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
11321 #define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
11322 /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
11323  *    master on SCL. Other masters in a multi-master system could shorten this time. This
11324  *    corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
11325  *    tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
11326  *  0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
11327  *  0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
11328  *  0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
11329  *  0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
11330  *  0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
11331  *  0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
11332  *  0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
11333  *  0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
11334  */
11335 #define I2C_MSTTIME_MSTSCLHIGH(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
11336 /*! @} */
11337 
11338 /*! @name MSTDAT - Combined Master receiver and transmitter data register. */
11339 /*! @{ */
11340 
11341 #define I2C_MSTDAT_DATA_MASK                     (0xFFU)
11342 #define I2C_MSTDAT_DATA_SHIFT                    (0U)
11343 /*! DATA - Master function data register. Read: read the most recently received data for the Master
11344  *    function. Write: transmit data using the Master function.
11345  */
11346 #define I2C_MSTDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
11347 /*! @} */
11348 
11349 /*! @name SLVCTL - Slave control register. */
11350 /*! @{ */
11351 
11352 #define I2C_SLVCTL_SLVCONTINUE_MASK              (0x1U)
11353 #define I2C_SLVCTL_SLVCONTINUE_SHIFT             (0U)
11354 /*! SLVCONTINUE - Slave Continue.
11355  *  0b0..No effect.
11356  *  0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag
11357  *       in the STAT register. This must be done after writing transmit data, reading received data, or any other
11358  *       housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE
11359  *       should not be set unless SLVPENDING = 1.
11360  */
11361 #define I2C_SLVCTL_SLVCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
11362 
11363 #define I2C_SLVCTL_SLVNACK_MASK                  (0x2U)
11364 #define I2C_SLVCTL_SLVNACK_SHIFT                 (1U)
11365 /*! SLVNACK - Slave NACK.
11366  *  0b0..No effect.
11367  *  0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
11368  */
11369 #define I2C_SLVCTL_SLVNACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
11370 
11371 #define I2C_SLVCTL_SLVDMA_MASK                   (0x8U)
11372 #define I2C_SLVCTL_SLVDMA_SHIFT                  (3U)
11373 /*! SLVDMA - Slave DMA enable.
11374  *  0b0..Disabled. No DMA requests are issued for Slave mode operation.
11375  *  0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
11376  */
11377 #define I2C_SLVCTL_SLVDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
11378 
11379 #define I2C_SLVCTL_AUTOACK_MASK                  (0x100U)
11380 #define I2C_SLVCTL_AUTOACK_SHIFT                 (8U)
11381 /*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches
11382  *    SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA
11383  *    to allow processing of the data without intervention. If this bit is clear and a header
11384  *    matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or
11385  *    interrupt.
11386  *  0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching
11387  *       address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
11388  *  0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,
11389  *       allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does
11390  *       not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK
11391  *       is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
11392  */
11393 #define I2C_SLVCTL_AUTOACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
11394 
11395 #define I2C_SLVCTL_AUTOMATCHREAD_MASK            (0x200U)
11396 #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT           (9U)
11397 /*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write
11398  *    request on the next header with an address matching SLVADR0. Since DMA needs to be configured to
11399  *    match the transfer direction, the direction needs to be specified. This bit allows a direction to
11400  *    be chosen for the next operation.
11401  *  0b0..The expected next operation in Automatic Mode is an I2C write.
11402  *  0b1..The expected next operation in Automatic Mode is an I2C read.
11403  */
11404 #define I2C_SLVCTL_AUTOMATCHREAD(x)              (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
11405 /*! @} */
11406 
11407 /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
11408 /*! @{ */
11409 
11410 #define I2C_SLVDAT_DATA_MASK                     (0xFFU)
11411 #define I2C_SLVDAT_DATA_SHIFT                    (0U)
11412 /*! DATA - Slave function data register. Read: read the most recently received data for the Slave
11413  *    function. Write: transmit data using the Slave function.
11414  */
11415 #define I2C_SLVDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
11416 /*! @} */
11417 
11418 /*! @name SLVADR - Slave address register. */
11419 /*! @{ */
11420 
11421 #define I2C_SLVADR_SADISABLE_MASK                (0x1U)
11422 #define I2C_SLVADR_SADISABLE_SHIFT               (0U)
11423 /*! SADISABLE - Slave Address n Disable.
11424  *  0b0..Enabled. Slave Address n is enabled.
11425  *  0b1..Ignored Slave Address n is ignored.
11426  */
11427 #define I2C_SLVADR_SADISABLE(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
11428 
11429 #define I2C_SLVADR_SLVADR_MASK                   (0xFEU)
11430 #define I2C_SLVADR_SLVADR_SHIFT                  (1U)
11431 /*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
11432  */
11433 #define I2C_SLVADR_SLVADR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
11434 
11435 #define I2C_SLVADR_AUTONACK_MASK                 (0x8000U)
11436 #define I2C_SLVADR_AUTONACK_SHIFT                (15U)
11437 /*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows
11438  *    software to ignore I2C traffic while handling previous I2C data or other operations.
11439  *  0b0..Normal operation, matching I2C addresses are not ignored.
11440  *  0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches
11441  *       SLVADRn, and AUTOMATCHREAD matches the direction.
11442  */
11443 #define I2C_SLVADR_AUTONACK(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
11444 /*! @} */
11445 
11446 /* The count of I2C_SLVADR */
11447 #define I2C_SLVADR_COUNT                         (4U)
11448 
11449 /*! @name SLVQUAL0 - Slave Qualification for address 0. */
11450 /*! @{ */
11451 
11452 #define I2C_SLVQUAL0_QUALMODE0_MASK              (0x1U)
11453 #define I2C_SLVQUAL0_QUALMODE0_SHIFT             (0U)
11454 /*! QUALMODE0 - Qualify mode for slave address 0.
11455  *  0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
11456  *  0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
11457  */
11458 #define I2C_SLVQUAL0_QUALMODE0(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
11459 
11460 #define I2C_SLVQUAL0_SLVQUAL0_MASK               (0xFEU)
11461 #define I2C_SLVQUAL0_SLVQUAL0_SHIFT              (1U)
11462 /*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
11463  *    be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
11464  *    set to 1 will cause an automatic match of the corresponding bit of the received address when it
11465  *    is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for
11466  *    address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
11467  *    (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
11468  */
11469 #define I2C_SLVQUAL0_SLVQUAL0(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
11470 /*! @} */
11471 
11472 /*! @name MONRXDAT - Monitor receiver data register. */
11473 /*! @{ */
11474 
11475 #define I2C_MONRXDAT_MONRXDAT_MASK               (0xFFU)
11476 #define I2C_MONRXDAT_MONRXDAT_SHIFT              (0U)
11477 /*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
11478  */
11479 #define I2C_MONRXDAT_MONRXDAT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
11480 
11481 #define I2C_MONRXDAT_MONSTART_MASK               (0x100U)
11482 #define I2C_MONRXDAT_MONSTART_SHIFT              (8U)
11483 /*! MONSTART - Monitor Received Start.
11484  *  0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
11485  *  0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
11486  */
11487 #define I2C_MONRXDAT_MONSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
11488 
11489 #define I2C_MONRXDAT_MONRESTART_MASK             (0x200U)
11490 #define I2C_MONRXDAT_MONRESTART_SHIFT            (9U)
11491 /*! MONRESTART - Monitor Received Repeated Start.
11492  *  0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
11493  *  0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
11494  */
11495 #define I2C_MONRXDAT_MONRESTART(x)               (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
11496 
11497 #define I2C_MONRXDAT_MONNACK_MASK                (0x400U)
11498 #define I2C_MONRXDAT_MONNACK_SHIFT               (10U)
11499 /*! MONNACK - Monitor Received NACK.
11500  *  0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
11501  *  0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
11502  */
11503 #define I2C_MONRXDAT_MONNACK(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
11504 /*! @} */
11505 
11506 /*! @name ID - Peripheral identification register. */
11507 /*! @{ */
11508 
11509 #define I2C_ID_APERTURE_MASK                     (0xFFU)
11510 #define I2C_ID_APERTURE_SHIFT                    (0U)
11511 /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
11512  */
11513 #define I2C_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
11514 
11515 #define I2C_ID_MINOR_REV_MASK                    (0xF00U)
11516 #define I2C_ID_MINOR_REV_SHIFT                   (8U)
11517 /*! MINOR_REV - Minor revision of module implementation.
11518  */
11519 #define I2C_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
11520 
11521 #define I2C_ID_MAJOR_REV_MASK                    (0xF000U)
11522 #define I2C_ID_MAJOR_REV_SHIFT                   (12U)
11523 /*! MAJOR_REV - Major revision of module implementation.
11524  */
11525 #define I2C_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
11526 
11527 #define I2C_ID_ID_MASK                           (0xFFFF0000U)
11528 #define I2C_ID_ID_SHIFT                          (16U)
11529 /*! ID - Module identifier for the selected function.
11530  */
11531 #define I2C_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
11532 /*! @} */
11533 
11534 
11535 /*!
11536  * @}
11537  */ /* end of group I2C_Register_Masks */
11538 
11539 
11540 /* I2C - Peripheral instance base addresses */
11541 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
11542   /** Peripheral I2C0 base address */
11543   #define I2C0_BASE                                (0x50086000u)
11544   /** Peripheral I2C0 base address */
11545   #define I2C0_BASE_NS                             (0x40086000u)
11546   /** Peripheral I2C0 base pointer */
11547   #define I2C0                                     ((I2C_Type *)I2C0_BASE)
11548   /** Peripheral I2C0 base pointer */
11549   #define I2C0_NS                                  ((I2C_Type *)I2C0_BASE_NS)
11550   /** Peripheral I2C1 base address */
11551   #define I2C1_BASE                                (0x50087000u)
11552   /** Peripheral I2C1 base address */
11553   #define I2C1_BASE_NS                             (0x40087000u)
11554   /** Peripheral I2C1 base pointer */
11555   #define I2C1                                     ((I2C_Type *)I2C1_BASE)
11556   /** Peripheral I2C1 base pointer */
11557   #define I2C1_NS                                  ((I2C_Type *)I2C1_BASE_NS)
11558   /** Peripheral I2C2 base address */
11559   #define I2C2_BASE                                (0x50088000u)
11560   /** Peripheral I2C2 base address */
11561   #define I2C2_BASE_NS                             (0x40088000u)
11562   /** Peripheral I2C2 base pointer */
11563   #define I2C2                                     ((I2C_Type *)I2C2_BASE)
11564   /** Peripheral I2C2 base pointer */
11565   #define I2C2_NS                                  ((I2C_Type *)I2C2_BASE_NS)
11566   /** Peripheral I2C3 base address */
11567   #define I2C3_BASE                                (0x50089000u)
11568   /** Peripheral I2C3 base address */
11569   #define I2C3_BASE_NS                             (0x40089000u)
11570   /** Peripheral I2C3 base pointer */
11571   #define I2C3                                     ((I2C_Type *)I2C3_BASE)
11572   /** Peripheral I2C3 base pointer */
11573   #define I2C3_NS                                  ((I2C_Type *)I2C3_BASE_NS)
11574   /** Peripheral I2C4 base address */
11575   #define I2C4_BASE                                (0x5008A000u)
11576   /** Peripheral I2C4 base address */
11577   #define I2C4_BASE_NS                             (0x4008A000u)
11578   /** Peripheral I2C4 base pointer */
11579   #define I2C4                                     ((I2C_Type *)I2C4_BASE)
11580   /** Peripheral I2C4 base pointer */
11581   #define I2C4_NS                                  ((I2C_Type *)I2C4_BASE_NS)
11582   /** Peripheral I2C5 base address */
11583   #define I2C5_BASE                                (0x50096000u)
11584   /** Peripheral I2C5 base address */
11585   #define I2C5_BASE_NS                             (0x40096000u)
11586   /** Peripheral I2C5 base pointer */
11587   #define I2C5                                     ((I2C_Type *)I2C5_BASE)
11588   /** Peripheral I2C5 base pointer */
11589   #define I2C5_NS                                  ((I2C_Type *)I2C5_BASE_NS)
11590   /** Peripheral I2C6 base address */
11591   #define I2C6_BASE                                (0x50097000u)
11592   /** Peripheral I2C6 base address */
11593   #define I2C6_BASE_NS                             (0x40097000u)
11594   /** Peripheral I2C6 base pointer */
11595   #define I2C6                                     ((I2C_Type *)I2C6_BASE)
11596   /** Peripheral I2C6 base pointer */
11597   #define I2C6_NS                                  ((I2C_Type *)I2C6_BASE_NS)
11598   /** Peripheral I2C7 base address */
11599   #define I2C7_BASE                                (0x50098000u)
11600   /** Peripheral I2C7 base address */
11601   #define I2C7_BASE_NS                             (0x40098000u)
11602   /** Peripheral I2C7 base pointer */
11603   #define I2C7                                     ((I2C_Type *)I2C7_BASE)
11604   /** Peripheral I2C7 base pointer */
11605   #define I2C7_NS                                  ((I2C_Type *)I2C7_BASE_NS)
11606   /** Array initializer of I2C peripheral base addresses */
11607   #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }
11608   /** Array initializer of I2C peripheral base pointers */
11609   #define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }
11610   /** Array initializer of I2C peripheral base addresses */
11611   #define I2C_BASE_ADDRS_NS                        { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS }
11612   /** Array initializer of I2C peripheral base pointers */
11613   #define I2C_BASE_PTRS_NS                         { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS }
11614 #else
11615   /** Peripheral I2C0 base address */
11616   #define I2C0_BASE                                (0x40086000u)
11617   /** Peripheral I2C0 base pointer */
11618   #define I2C0                                     ((I2C_Type *)I2C0_BASE)
11619   /** Peripheral I2C1 base address */
11620   #define I2C1_BASE                                (0x40087000u)
11621   /** Peripheral I2C1 base pointer */
11622   #define I2C1                                     ((I2C_Type *)I2C1_BASE)
11623   /** Peripheral I2C2 base address */
11624   #define I2C2_BASE                                (0x40088000u)
11625   /** Peripheral I2C2 base pointer */
11626   #define I2C2                                     ((I2C_Type *)I2C2_BASE)
11627   /** Peripheral I2C3 base address */
11628   #define I2C3_BASE                                (0x40089000u)
11629   /** Peripheral I2C3 base pointer */
11630   #define I2C3                                     ((I2C_Type *)I2C3_BASE)
11631   /** Peripheral I2C4 base address */
11632   #define I2C4_BASE                                (0x4008A000u)
11633   /** Peripheral I2C4 base pointer */
11634   #define I2C4                                     ((I2C_Type *)I2C4_BASE)
11635   /** Peripheral I2C5 base address */
11636   #define I2C5_BASE                                (0x40096000u)
11637   /** Peripheral I2C5 base pointer */
11638   #define I2C5                                     ((I2C_Type *)I2C5_BASE)
11639   /** Peripheral I2C6 base address */
11640   #define I2C6_BASE                                (0x40097000u)
11641   /** Peripheral I2C6 base pointer */
11642   #define I2C6                                     ((I2C_Type *)I2C6_BASE)
11643   /** Peripheral I2C7 base address */
11644   #define I2C7_BASE                                (0x40098000u)
11645   /** Peripheral I2C7 base pointer */
11646   #define I2C7                                     ((I2C_Type *)I2C7_BASE)
11647   /** Array initializer of I2C peripheral base addresses */
11648   #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }
11649   /** Array initializer of I2C peripheral base pointers */
11650   #define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }
11651 #endif
11652 /** Interrupt vectors for the I2C peripheral type */
11653 #define I2C_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
11654 
11655 /*!
11656  * @}
11657  */ /* end of group I2C_Peripheral_Access_Layer */
11658 
11659 
11660 /* ----------------------------------------------------------------------------
11661    -- I2S Peripheral Access Layer
11662    ---------------------------------------------------------------------------- */
11663 
11664 /*!
11665  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
11666  * @{
11667  */
11668 
11669 /** I2S - Register Layout Typedef */
11670 typedef struct {
11671        uint8_t RESERVED_0[3072];
11672   __IO uint32_t CFG1;                              /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
11673   __IO uint32_t CFG2;                              /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
11674   __IO uint32_t STAT;                              /**< Status register for the primary channel pair., offset: 0xC08 */
11675        uint8_t RESERVED_1[16];
11676   __IO uint32_t DIV;                               /**< Clock divider, used by all channel pairs., offset: 0xC1C */
11677        uint8_t RESERVED_2[480];
11678   __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
11679   __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
11680   __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
11681        uint8_t RESERVED_3[4];
11682   __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
11683   __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
11684   __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
11685        uint8_t RESERVED_4[4];
11686   __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
11687   __O  uint32_t FIFOWR48H;                         /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
11688        uint8_t RESERVED_5[8];
11689   __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
11690   __I  uint32_t FIFORD48H;                         /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
11691        uint8_t RESERVED_6[8];
11692   __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
11693   __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
11694   __I  uint32_t FIFOSIZE;                          /**< FIFO size register, offset: 0xE48 */
11695        uint8_t RESERVED_7[432];
11696   __I  uint32_t ID;                                /**< I2S Module identification, offset: 0xFFC */
11697 } I2S_Type;
11698 
11699 /* ----------------------------------------------------------------------------
11700    -- I2S Register Masks
11701    ---------------------------------------------------------------------------- */
11702 
11703 /*!
11704  * @addtogroup I2S_Register_Masks I2S Register Masks
11705  * @{
11706  */
11707 
11708 /*! @name CFG1 - Configuration register 1 for the primary channel pair. */
11709 /*! @{ */
11710 
11711 #define I2S_CFG1_MAINENABLE_MASK                 (0x1U)
11712 #define I2S_CFG1_MAINENABLE_SHIFT                (0U)
11713 /*! MAINENABLE - Main enable for I 2S function in this Flexcomm
11714  *  0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags
11715  *       are reset. No other channel pairs can be enabled.
11716  *  0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.
11717  */
11718 #define I2S_CFG1_MAINENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
11719 
11720 #define I2S_CFG1_DATAPAUSE_MASK                  (0x2U)
11721 #define I2S_CFG1_DATAPAUSE_SHIFT                 (1U)
11722 /*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer
11723  *    and the FIFO. This could be done in order to change streams, or while restarting after a data
11724  *    underflow or overflow. When paused, FIFO operations can be done without corrupting data that is
11725  *    in the process of being sent or received. Once a data pause has been requested, the interface
11726  *    may need to complete sending data that was in progress before interrupting the flow of data.
11727  *    Software must check that the pause is actually in effect before taking action. This is done by
11728  *    monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer
11729  *    will resume at the beginning of the next frame.
11730  *  0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused.
11731  *  0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1.
11732  */
11733 #define I2S_CFG1_DATAPAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
11734 
11735 #define I2S_CFG1_PAIRCOUNT_MASK                  (0xCU)
11736 #define I2S_CFG1_PAIRCOUNT_SHIFT                 (2U)
11737 /*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field
11738  *    whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this
11739  *    Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs
11740  *    in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.
11741  *  0b00..1 I2S channel pairs in this flexcomm
11742  *  0b01..2 I2S channel pairs in this flexcomm
11743  *  0b10..3 I2S channel pairs in this flexcomm
11744  *  0b11..4 I2S channel pairs in this flexcomm
11745  */
11746 #define I2S_CFG1_PAIRCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
11747 
11748 #define I2S_CFG1_MSTSLVCFG_MASK                  (0x30U)
11749 #define I2S_CFG1_MSTSLVCFG_SHIFT                 (4U)
11750 /*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.
11751  *  0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data.
11752  *  0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of
11753  *        SCK, when divided from the Flexcomm function clock.
11754  *  0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data.
11755  *  0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices.
11756  */
11757 #define I2S_CFG1_MSTSLVCFG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
11758 
11759 #define I2S_CFG1_MODE_MASK                       (0xC0U)
11760 #define I2S_CFG1_MODE_SHIFT                      (6U)
11761 /*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all
11762  *    supported cases. See Formats and modes for examples.
11763  *  0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece
11764  *        of left channel data occurring during the first phase, and one pieces of right channel data occurring
11765  *        during the second phase. In this mode, the data region begins one clock after the leading WS edge for the
11766  *        frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If
11767  *        FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right.
11768  *  0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0.
11769  *  0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame.
11770  *  0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame.
11771  */
11772 #define I2S_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
11773 
11774 #define I2S_CFG1_RIGHTLOW_MASK                   (0x100U)
11775 #define I2S_CFG1_RIGHTLOW_SHIFT                  (8U)
11776 /*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left
11777  *    and right channel data as it is transferred to or from the FIFO. This bit is not used if the
11778  *    data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10
11779  *    of this register) = 1, the one channel to be used is the nominally the left channel. POSITION
11780  *    can still place that data in the frame where right channel data is normally located. if all
11781  *    enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.
11782  *  0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO
11783  *       bits 31:16 are used for the right channel.
11784  *  0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO
11785  *       bits 15:0 are used for the right channel.
11786  */
11787 #define I2S_CFG1_RIGHTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
11788 
11789 #define I2S_CFG1_LEFTJUST_MASK                   (0x200U)
11790 #define I2S_CFG1_LEFTJUST_SHIFT                  (9U)
11791 /*! LEFTJUST - Left Justify data.
11792  *  0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting
11793  *       from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data
11794  *       in the stream on the data bus.
11795  *  0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting
11796  *       from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would
11797  *       correspond to left justified data in the stream on the data bus.
11798  */
11799 #define I2S_CFG1_LEFTJUST(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
11800 
11801 #define I2S_CFG1_ONECHANNEL_MASK                 (0x400U)
11802 #define I2S_CFG1_ONECHANNEL_SHIFT                (10U)
11803 /*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit
11804  *    applies only to the first I2S channel pair. Other channel pairs may select this mode
11805  *    independently in their separate CFG1 registers.
11806  *  0b0..I2S data for this channel pair is treated as left and right channels.
11807  *  0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this
11808  *       pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a
11809  *       clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel
11810  *       of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side
11811  *       (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data
11812  *       for the single channel of data is placed at the clock defined by POSITION.
11813  */
11814 #define I2S_CFG1_ONECHANNEL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
11815 
11816 #define I2S_CFG1_SCK_POL_MASK                    (0x1000U)
11817 #define I2S_CFG1_SCK_POL_SHIFT                   (12U)
11818 /*! SCK_POL - SCK polarity.
11819  *  0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S).
11820  *  0b1..Data is launched on SCK rising edges and sampled on SCK falling edges.
11821  */
11822 #define I2S_CFG1_SCK_POL(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
11823 
11824 #define I2S_CFG1_WS_POL_MASK                     (0x2000U)
11825 #define I2S_CFG1_WS_POL_SHIFT                    (13U)
11826 /*! WS_POL - WS polarity.
11827  *  0b0..Data frames begin at a falling edge of WS (standard for classic I2S).
11828  *  0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S).
11829  */
11830 #define I2S_CFG1_WS_POL(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
11831 
11832 #define I2S_CFG1_DATALEN_MASK                    (0x1F0000U)
11833 #define I2S_CFG1_DATALEN_SHIFT                   (16U)
11834 /*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or
11835  *    received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received
11836  *    from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the
11837  *    I2S: Determines the size of data transfers between the FIFO and the I2S
11838  *    serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of
11839  *    right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse
11840  *    at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to
11841  *    0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F =
11842  *    data is 32 bits in length
11843  */
11844 #define I2S_CFG1_DATALEN(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
11845 /*! @} */
11846 
11847 /*! @name CFG2 - Configuration register 2 for the primary channel pair. */
11848 /*! @{ */
11849 
11850 #define I2S_CFG2_FRAMELEN_MASK                   (0x1FFU)
11851 #define I2S_CFG2_FRAMELEN_SHIFT                  (0U)
11852 /*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the
11853  *    frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported
11854  *    0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is
11855  *    512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in
11856  *    mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger
11857  *    than DATALEN in order for the WS pulse to be generated correctly.
11858  */
11859 #define I2S_CFG2_FRAMELEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
11860 
11861 #define I2S_CFG2_POSITION_MASK                   (0x1FF0000U)
11862 #define I2S_CFG2_POSITION_SHIFT                  (16U)
11863 /*! POSITION - Data Position. Defines the location within the frame of the data for this channel
11864  *    pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION
11865  *    defines the location of data in both the left phase and right phase, starting one clock after
11866  *    the WS edge. In other modes, POSITION defines the location of data within the entire frame.
11867  *    ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The
11868  *    combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels
11869  *    do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit
11870  *    position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS
11871  *    phase. 0x002 = data begins at bit position 2 within the frame or WS phase.
11872  */
11873 #define I2S_CFG2_POSITION(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
11874 /*! @} */
11875 
11876 /*! @name STAT - Status register for the primary channel pair. */
11877 /*! @{ */
11878 
11879 #define I2S_STAT_BUSY_MASK                       (0x1U)
11880 #define I2S_STAT_BUSY_SHIFT                      (0U)
11881 /*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair.
11882  *  0b0..The transmitter/receiver for channel pair is currently idle.
11883  *  0b1..The transmitter/receiver for channel pair is currently processing data.
11884  */
11885 #define I2S_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
11886 
11887 #define I2S_STAT_SLVFRMERR_MASK                  (0x2U)
11888 #define I2S_STAT_SLVFRMERR_SHIFT                 (1U)
11889 /*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as
11890  *    a slave. An error indicates that the incoming WS signal did not transition as expected due to
11891  *    a mismatch between FRAMELEN and the actual incoming I2S stream.
11892  *  0b0..No error has been recorded.
11893  *  0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position.
11894  */
11895 #define I2S_STAT_SLVFRMERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
11896 
11897 #define I2S_STAT_LR_MASK                         (0x4U)
11898 #define I2S_STAT_LR_SHIFT                        (2U)
11899 /*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to
11900  *    be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data
11901  *    being processed for the currently busy channel pair.
11902  *  0b0..Left channel.
11903  *  0b1..Right channel.
11904  */
11905 #define I2S_STAT_LR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
11906 
11907 #define I2S_STAT_DATAPAUSED_MASK                 (0x8U)
11908 #define I2S_STAT_DATAPAUSED_SHIFT                (3U)
11909 /*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels
11910  *  0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for
11911  *       an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register.
11912  *  0b1..A data pause has been requested and is now in force.
11913  */
11914 #define I2S_STAT_DATAPAUSED(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
11915 /*! @} */
11916 
11917 /*! @name DIV - Clock divider, used by all channel pairs. */
11918 /*! @{ */
11919 
11920 #define I2S_DIV_DIV_MASK                         (0xFFFU)
11921 #define I2S_DIV_DIV_SHIFT                        (0U)
11922 /*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The
11923  *    Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2.
11924  *    0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is
11925  *    divided by 4,096.
11926  */
11927 #define I2S_DIV_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
11928 /*! @} */
11929 
11930 /*! @name FIFOCFG - FIFO configuration and enable register. */
11931 /*! @{ */
11932 
11933 #define I2S_FIFOCFG_ENABLETX_MASK                (0x1U)
11934 #define I2S_FIFOCFG_ENABLETX_SHIFT               (0U)
11935 /*! ENABLETX - Enable the transmit FIFO.
11936  *  0b0..The transmit FIFO is not enabled.
11937  *  0b1..The transmit FIFO is enabled.
11938  */
11939 #define I2S_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
11940 
11941 #define I2S_FIFOCFG_ENABLERX_MASK                (0x2U)
11942 #define I2S_FIFOCFG_ENABLERX_SHIFT               (1U)
11943 /*! ENABLERX - Enable the receive FIFO.
11944  *  0b0..The receive FIFO is not enabled.
11945  *  0b1..The receive FIFO is enabled.
11946  */
11947 #define I2S_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
11948 
11949 #define I2S_FIFOCFG_TXI2SE0_MASK                 (0x4U)
11950 #define I2S_FIFOCFG_TXI2SE0_SHIFT                (2U)
11951 /*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX
11952  *    FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is
11953  *    cleared, new data is provided, and the I2S is un-paused.
11954  *  0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24
11955  *       bits or less, or when MONO = 1 for this channel pair.
11956  *  0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.
11957  */
11958 #define I2S_FIFOCFG_TXI2SE0(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
11959 
11960 #define I2S_FIFOCFG_PACK48_MASK                  (0x8U)
11961 #define I2S_FIFOCFG_PACK48_SHIFT                 (3U)
11962 /*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
11963  *  0b0..48-bit I2S FIFO entries are handled as all 24-bit values.
11964  *  0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.
11965  */
11966 #define I2S_FIFOCFG_PACK48(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
11967 
11968 #define I2S_FIFOCFG_SIZE_MASK                    (0x30U)
11969 #define I2S_FIFOCFG_SIZE_SHIFT                   (4U)
11970 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
11971  *    entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
11972  */
11973 #define I2S_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
11974 
11975 #define I2S_FIFOCFG_DMATX_MASK                   (0x1000U)
11976 #define I2S_FIFOCFG_DMATX_SHIFT                  (12U)
11977 /*! DMATX - DMA configuration for transmit.
11978  *  0b0..DMA is not used for the transmit function.
11979  *  0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
11980  */
11981 #define I2S_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
11982 
11983 #define I2S_FIFOCFG_DMARX_MASK                   (0x2000U)
11984 #define I2S_FIFOCFG_DMARX_SHIFT                  (13U)
11985 /*! DMARX - DMA configuration for receive.
11986  *  0b0..DMA is not used for the receive function.
11987  *  0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
11988  */
11989 #define I2S_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
11990 
11991 #define I2S_FIFOCFG_WAKETX_MASK                  (0x4000U)
11992 #define I2S_FIFOCFG_WAKETX_SHIFT                 (14U)
11993 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
11994  *    modes (up to power-down, as long as the peripheral function works in that power mode) without
11995  *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
11996  *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
11997  *    Wake-up control register.
11998  *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
11999  *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
12000  *       FIFOTRIG, even when the TXLVL interrupt is not enabled.
12001  */
12002 #define I2S_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
12003 
12004 #define I2S_FIFOCFG_WAKERX_MASK                  (0x8000U)
12005 #define I2S_FIFOCFG_WAKERX_SHIFT                 (15U)
12006 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
12007  *    modes (up to power-down, as long as the peripheral function works in that power mode) without
12008  *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
12009  *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
12010  *    Wake-up control register.
12011  *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
12012  *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
12013  *       FIFOTRIG, even when the RXLVL interrupt is not enabled.
12014  */
12015 #define I2S_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
12016 
12017 #define I2S_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
12018 #define I2S_FIFOCFG_EMPTYTX_SHIFT                (16U)
12019 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
12020  */
12021 #define I2S_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
12022 
12023 #define I2S_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
12024 #define I2S_FIFOCFG_EMPTYRX_SHIFT                (17U)
12025 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
12026  */
12027 #define I2S_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
12028 /*! @} */
12029 
12030 /*! @name FIFOSTAT - FIFO status register. */
12031 /*! @{ */
12032 
12033 #define I2S_FIFOSTAT_TXERR_MASK                  (0x1U)
12034 #define I2S_FIFOSTAT_TXERR_SHIFT                 (0U)
12035 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
12036  *    caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
12037  *    needed. Cleared by writing a 1 to this bit.
12038  */
12039 #define I2S_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
12040 
12041 #define I2S_FIFOSTAT_RXERR_MASK                  (0x2U)
12042 #define I2S_FIFOSTAT_RXERR_SHIFT                 (1U)
12043 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
12044  *    not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
12045  */
12046 #define I2S_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
12047 
12048 #define I2S_FIFOSTAT_PERINT_MASK                 (0x8U)
12049 #define I2S_FIFOSTAT_PERINT_SHIFT                (3U)
12050 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
12051  *    an interrupt. The details can be found by reading the peripheral's STAT register.
12052  */
12053 #define I2S_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
12054 
12055 #define I2S_FIFOSTAT_TXEMPTY_MASK                (0x10U)
12056 #define I2S_FIFOSTAT_TXEMPTY_SHIFT               (4U)
12057 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
12058  */
12059 #define I2S_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
12060 
12061 #define I2S_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
12062 #define I2S_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
12063 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
12064  *    written. When 0, the transmit FIFO is full and another write would cause it to overflow.
12065  */
12066 #define I2S_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
12067 
12068 #define I2S_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
12069 #define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
12070 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
12071  */
12072 #define I2S_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
12073 
12074 #define I2S_FIFOSTAT_RXFULL_MASK                 (0x80U)
12075 #define I2S_FIFOSTAT_RXFULL_SHIFT                (7U)
12076 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
12077  *    prevent the peripheral from causing an overflow.
12078  */
12079 #define I2S_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
12080 
12081 #define I2S_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
12082 #define I2S_FIFOSTAT_TXLVL_SHIFT                 (8U)
12083 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
12084  *    and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
12085  *    the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
12086  *    0.
12087  */
12088 #define I2S_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
12089 
12090 #define I2S_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
12091 #define I2S_FIFOSTAT_RXLVL_SHIFT                 (16U)
12092 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
12093  *    RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
12094  *    point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
12095  *    1.
12096  */
12097 #define I2S_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
12098 /*! @} */
12099 
12100 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
12101 /*! @{ */
12102 
12103 #define I2S_FIFOTRIG_TXLVLENA_MASK               (0x1U)
12104 #define I2S_FIFOTRIG_TXLVLENA_SHIFT              (0U)
12105 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
12106  *    in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
12107  *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
12108  *  0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
12109  */
12110 #define I2S_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
12111 
12112 #define I2S_FIFOTRIG_RXLVLENA_MASK               (0x2U)
12113 #define I2S_FIFOTRIG_RXLVLENA_SHIFT              (1U)
12114 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
12115  *    in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
12116  *  0b0..Receive FIFO level does not generate a FIFO level trigger.
12117  *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
12118  */
12119 #define I2S_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
12120 
12121 #define I2S_FIFOTRIG_TXLVL_MASK                  (0xF00U)
12122 #define I2S_FIFOTRIG_TXLVL_SHIFT                 (8U)
12123 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
12124  *    to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
12125  *    the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
12126  *    becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
12127  *    FIFO level decreases to 15 entries (is no longer full).
12128  */
12129 #define I2S_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
12130 
12131 #define I2S_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
12132 #define I2S_FIFOTRIG_RXLVL_SHIFT                 (16U)
12133 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
12134  *    is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
12135  *    can wake up the device just enough to perform DMA, then return to the reduced power mode. See
12136  *    Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
12137  *    longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
12138  *    FIFO has received 16 entries (has become full).
12139  */
12140 #define I2S_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
12141 /*! @} */
12142 
12143 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
12144 /*! @{ */
12145 
12146 #define I2S_FIFOINTENSET_TXERR_MASK              (0x1U)
12147 #define I2S_FIFOINTENSET_TXERR_SHIFT             (0U)
12148 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
12149  *  0b0..No interrupt will be generated for a transmit error.
12150  *  0b1..An interrupt will be generated when a transmit error occurs.
12151  */
12152 #define I2S_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
12153 
12154 #define I2S_FIFOINTENSET_RXERR_MASK              (0x2U)
12155 #define I2S_FIFOINTENSET_RXERR_SHIFT             (1U)
12156 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
12157  *  0b0..No interrupt will be generated for a receive error.
12158  *  0b1..An interrupt will be generated when a receive error occurs.
12159  */
12160 #define I2S_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
12161 
12162 #define I2S_FIFOINTENSET_TXLVL_MASK              (0x4U)
12163 #define I2S_FIFOINTENSET_TXLVL_SHIFT             (2U)
12164 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
12165  *    specified by the TXLVL field in the FIFOTRIG register.
12166  *  0b0..No interrupt will be generated based on the TX FIFO level.
12167  *  0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
12168  *       to the level specified by TXLVL in the FIFOTRIG register.
12169  */
12170 #define I2S_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
12171 
12172 #define I2S_FIFOINTENSET_RXLVL_MASK              (0x8U)
12173 #define I2S_FIFOINTENSET_RXLVL_SHIFT             (3U)
12174 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
12175  *    specified by the TXLVL field in the FIFOTRIG register.
12176  *  0b0..No interrupt will be generated based on the RX FIFO level.
12177  *  0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
12178  *       increases to the level specified by RXLVL in the FIFOTRIG register.
12179  */
12180 #define I2S_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
12181 /*! @} */
12182 
12183 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
12184 /*! @{ */
12185 
12186 #define I2S_FIFOINTENCLR_TXERR_MASK              (0x1U)
12187 #define I2S_FIFOINTENCLR_TXERR_SHIFT             (0U)
12188 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
12189  */
12190 #define I2S_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
12191 
12192 #define I2S_FIFOINTENCLR_RXERR_MASK              (0x2U)
12193 #define I2S_FIFOINTENCLR_RXERR_SHIFT             (1U)
12194 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
12195  */
12196 #define I2S_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
12197 
12198 #define I2S_FIFOINTENCLR_TXLVL_MASK              (0x4U)
12199 #define I2S_FIFOINTENCLR_TXLVL_SHIFT             (2U)
12200 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
12201  */
12202 #define I2S_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
12203 
12204 #define I2S_FIFOINTENCLR_RXLVL_MASK              (0x8U)
12205 #define I2S_FIFOINTENCLR_RXLVL_SHIFT             (3U)
12206 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
12207  */
12208 #define I2S_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
12209 /*! @} */
12210 
12211 /*! @name FIFOINTSTAT - FIFO interrupt status register. */
12212 /*! @{ */
12213 
12214 #define I2S_FIFOINTSTAT_TXERR_MASK               (0x1U)
12215 #define I2S_FIFOINTSTAT_TXERR_SHIFT              (0U)
12216 /*! TXERR - TX FIFO error.
12217  */
12218 #define I2S_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
12219 
12220 #define I2S_FIFOINTSTAT_RXERR_MASK               (0x2U)
12221 #define I2S_FIFOINTSTAT_RXERR_SHIFT              (1U)
12222 /*! RXERR - RX FIFO error.
12223  */
12224 #define I2S_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
12225 
12226 #define I2S_FIFOINTSTAT_TXLVL_MASK               (0x4U)
12227 #define I2S_FIFOINTSTAT_TXLVL_SHIFT              (2U)
12228 /*! TXLVL - Transmit FIFO level interrupt.
12229  */
12230 #define I2S_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
12231 
12232 #define I2S_FIFOINTSTAT_RXLVL_MASK               (0x8U)
12233 #define I2S_FIFOINTSTAT_RXLVL_SHIFT              (3U)
12234 /*! RXLVL - Receive FIFO level interrupt.
12235  */
12236 #define I2S_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
12237 
12238 #define I2S_FIFOINTSTAT_PERINT_MASK              (0x10U)
12239 #define I2S_FIFOINTSTAT_PERINT_SHIFT             (4U)
12240 /*! PERINT - Peripheral interrupt.
12241  */
12242 #define I2S_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
12243 /*! @} */
12244 
12245 /*! @name FIFOWR - FIFO write data. */
12246 /*! @{ */
12247 
12248 #define I2S_FIFOWR_TXDATA_MASK                   (0xFFFFFFFFU)
12249 #define I2S_FIFOWR_TXDATA_SHIFT                  (0U)
12250 /*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details.
12251  */
12252 #define I2S_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
12253 /*! @} */
12254 
12255 /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
12256 /*! @{ */
12257 
12258 #define I2S_FIFOWR48H_TXDATA_MASK                (0xFFFFFFU)
12259 #define I2S_FIFOWR48H_TXDATA_SHIFT               (0U)
12260 /*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details.
12261  */
12262 #define I2S_FIFOWR48H_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
12263 /*! @} */
12264 
12265 /*! @name FIFORD - FIFO read data. */
12266 /*! @{ */
12267 
12268 #define I2S_FIFORD_RXDATA_MASK                   (0xFFFFFFFFU)
12269 #define I2S_FIFORD_RXDATA_SHIFT                  (0U)
12270 /*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details.
12271  */
12272 #define I2S_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
12273 /*! @} */
12274 
12275 /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
12276 /*! @{ */
12277 
12278 #define I2S_FIFORD48H_RXDATA_MASK                (0xFFFFFFU)
12279 #define I2S_FIFORD48H_RXDATA_SHIFT               (0U)
12280 /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
12281  */
12282 #define I2S_FIFORD48H_RXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
12283 /*! @} */
12284 
12285 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
12286 /*! @{ */
12287 
12288 #define I2S_FIFORDNOPOP_RXDATA_MASK              (0xFFFFFFFFU)
12289 #define I2S_FIFORDNOPOP_RXDATA_SHIFT             (0U)
12290 /*! RXDATA - Received data from the FIFO.
12291  */
12292 #define I2S_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
12293 /*! @} */
12294 
12295 /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
12296 /*! @{ */
12297 
12298 #define I2S_FIFORD48HNOPOP_RXDATA_MASK           (0xFFFFFFU)
12299 #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT          (0U)
12300 /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
12301  */
12302 #define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
12303 /*! @} */
12304 
12305 /*! @name FIFOSIZE - FIFO size register */
12306 /*! @{ */
12307 
12308 #define I2S_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)
12309 #define I2S_FIFOSIZE_FIFOSIZE_SHIFT              (0U)
12310 /*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries.
12311  */
12312 #define I2S_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK)
12313 /*! @} */
12314 
12315 /*! @name ID - I2S Module identification */
12316 /*! @{ */
12317 
12318 #define I2S_ID_APERTURE_MASK                     (0xFFU)
12319 #define I2S_ID_APERTURE_SHIFT                    (0U)
12320 /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
12321  */
12322 #define I2S_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK)
12323 
12324 #define I2S_ID_MINOR_REV_MASK                    (0xF00U)
12325 #define I2S_ID_MINOR_REV_SHIFT                   (8U)
12326 /*! MINOR_REV - Minor revision of module implementation, starting at 0.
12327  */
12328 #define I2S_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK)
12329 
12330 #define I2S_ID_MAJOR_REV_MASK                    (0xF000U)
12331 #define I2S_ID_MAJOR_REV_SHIFT                   (12U)
12332 /*! MAJOR_REV - Major revision of module implementation, starting at 0.
12333  */
12334 #define I2S_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK)
12335 
12336 #define I2S_ID_ID_MASK                           (0xFFFF0000U)
12337 #define I2S_ID_ID_SHIFT                          (16U)
12338 /*! ID - Unique module identifier for this IP block.
12339  */
12340 #define I2S_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
12341 /*! @} */
12342 
12343 
12344 /*!
12345  * @}
12346  */ /* end of group I2S_Register_Masks */
12347 
12348 
12349 /* I2S - Peripheral instance base addresses */
12350 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
12351   /** Peripheral I2S0 base address */
12352   #define I2S0_BASE                                (0x50086000u)
12353   /** Peripheral I2S0 base address */
12354   #define I2S0_BASE_NS                             (0x40086000u)
12355   /** Peripheral I2S0 base pointer */
12356   #define I2S0                                     ((I2S_Type *)I2S0_BASE)
12357   /** Peripheral I2S0 base pointer */
12358   #define I2S0_NS                                  ((I2S_Type *)I2S0_BASE_NS)
12359   /** Peripheral I2S1 base address */
12360   #define I2S1_BASE                                (0x50087000u)
12361   /** Peripheral I2S1 base address */
12362   #define I2S1_BASE_NS                             (0x40087000u)
12363   /** Peripheral I2S1 base pointer */
12364   #define I2S1                                     ((I2S_Type *)I2S1_BASE)
12365   /** Peripheral I2S1 base pointer */
12366   #define I2S1_NS                                  ((I2S_Type *)I2S1_BASE_NS)
12367   /** Peripheral I2S2 base address */
12368   #define I2S2_BASE                                (0x50088000u)
12369   /** Peripheral I2S2 base address */
12370   #define I2S2_BASE_NS                             (0x40088000u)
12371   /** Peripheral I2S2 base pointer */
12372   #define I2S2                                     ((I2S_Type *)I2S2_BASE)
12373   /** Peripheral I2S2 base pointer */
12374   #define I2S2_NS                                  ((I2S_Type *)I2S2_BASE_NS)
12375   /** Peripheral I2S3 base address */
12376   #define I2S3_BASE                                (0x50089000u)
12377   /** Peripheral I2S3 base address */
12378   #define I2S3_BASE_NS                             (0x40089000u)
12379   /** Peripheral I2S3 base pointer */
12380   #define I2S3                                     ((I2S_Type *)I2S3_BASE)
12381   /** Peripheral I2S3 base pointer */
12382   #define I2S3_NS                                  ((I2S_Type *)I2S3_BASE_NS)
12383   /** Peripheral I2S4 base address */
12384   #define I2S4_BASE                                (0x5008A000u)
12385   /** Peripheral I2S4 base address */
12386   #define I2S4_BASE_NS                             (0x4008A000u)
12387   /** Peripheral I2S4 base pointer */
12388   #define I2S4                                     ((I2S_Type *)I2S4_BASE)
12389   /** Peripheral I2S4 base pointer */
12390   #define I2S4_NS                                  ((I2S_Type *)I2S4_BASE_NS)
12391   /** Peripheral I2S5 base address */
12392   #define I2S5_BASE                                (0x50096000u)
12393   /** Peripheral I2S5 base address */
12394   #define I2S5_BASE_NS                             (0x40096000u)
12395   /** Peripheral I2S5 base pointer */
12396   #define I2S5                                     ((I2S_Type *)I2S5_BASE)
12397   /** Peripheral I2S5 base pointer */
12398   #define I2S5_NS                                  ((I2S_Type *)I2S5_BASE_NS)
12399   /** Peripheral I2S6 base address */
12400   #define I2S6_BASE                                (0x50097000u)
12401   /** Peripheral I2S6 base address */
12402   #define I2S6_BASE_NS                             (0x40097000u)
12403   /** Peripheral I2S6 base pointer */
12404   #define I2S6                                     ((I2S_Type *)I2S6_BASE)
12405   /** Peripheral I2S6 base pointer */
12406   #define I2S6_NS                                  ((I2S_Type *)I2S6_BASE_NS)
12407   /** Peripheral I2S7 base address */
12408   #define I2S7_BASE                                (0x50098000u)
12409   /** Peripheral I2S7 base address */
12410   #define I2S7_BASE_NS                             (0x40098000u)
12411   /** Peripheral I2S7 base pointer */
12412   #define I2S7                                     ((I2S_Type *)I2S7_BASE)
12413   /** Peripheral I2S7 base pointer */
12414   #define I2S7_NS                                  ((I2S_Type *)I2S7_BASE_NS)
12415   /** Array initializer of I2S peripheral base addresses */
12416   #define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE }
12417   /** Array initializer of I2S peripheral base pointers */
12418   #define I2S_BASE_PTRS                            { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 }
12419   /** Array initializer of I2S peripheral base addresses */
12420   #define I2S_BASE_ADDRS_NS                        { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS }
12421   /** Array initializer of I2S peripheral base pointers */
12422   #define I2S_BASE_PTRS_NS                         { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS }
12423 #else
12424   /** Peripheral I2S0 base address */
12425   #define I2S0_BASE                                (0x40086000u)
12426   /** Peripheral I2S0 base pointer */
12427   #define I2S0                                     ((I2S_Type *)I2S0_BASE)
12428   /** Peripheral I2S1 base address */
12429   #define I2S1_BASE                                (0x40087000u)
12430   /** Peripheral I2S1 base pointer */
12431   #define I2S1                                     ((I2S_Type *)I2S1_BASE)
12432   /** Peripheral I2S2 base address */
12433   #define I2S2_BASE                                (0x40088000u)
12434   /** Peripheral I2S2 base pointer */
12435   #define I2S2                                     ((I2S_Type *)I2S2_BASE)
12436   /** Peripheral I2S3 base address */
12437   #define I2S3_BASE                                (0x40089000u)
12438   /** Peripheral I2S3 base pointer */
12439   #define I2S3                                     ((I2S_Type *)I2S3_BASE)
12440   /** Peripheral I2S4 base address */
12441   #define I2S4_BASE                                (0x4008A000u)
12442   /** Peripheral I2S4 base pointer */
12443   #define I2S4                                     ((I2S_Type *)I2S4_BASE)
12444   /** Peripheral I2S5 base address */
12445   #define I2S5_BASE                                (0x40096000u)
12446   /** Peripheral I2S5 base pointer */
12447   #define I2S5                                     ((I2S_Type *)I2S5_BASE)
12448   /** Peripheral I2S6 base address */
12449   #define I2S6_BASE                                (0x40097000u)
12450   /** Peripheral I2S6 base pointer */
12451   #define I2S6                                     ((I2S_Type *)I2S6_BASE)
12452   /** Peripheral I2S7 base address */
12453   #define I2S7_BASE                                (0x40098000u)
12454   /** Peripheral I2S7 base pointer */
12455   #define I2S7                                     ((I2S_Type *)I2S7_BASE)
12456   /** Array initializer of I2S peripheral base addresses */
12457   #define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE }
12458   /** Array initializer of I2S peripheral base pointers */
12459   #define I2S_BASE_PTRS                            { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 }
12460 #endif
12461 /** Interrupt vectors for the I2S peripheral type */
12462 #define I2S_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
12463 
12464 /*!
12465  * @}
12466  */ /* end of group I2S_Peripheral_Access_Layer */
12467 
12468 
12469 /* ----------------------------------------------------------------------------
12470    -- INPUTMUX Peripheral Access Layer
12471    ---------------------------------------------------------------------------- */
12472 
12473 /*!
12474  * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
12475  * @{
12476  */
12477 
12478 /** INPUTMUX - Register Layout Typedef */
12479 typedef struct {
12480   __IO uint32_t SCT0_INMUX[7];                     /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */
12481        uint8_t RESERVED_0[4];
12482   __IO uint32_t TIMER0CAPTSEL[4];                  /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */
12483        uint8_t RESERVED_1[16];
12484   __IO uint32_t TIMER1CAPTSEL[4];                  /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */
12485        uint8_t RESERVED_2[16];
12486   __IO uint32_t TIMER2CAPTSEL[4];                  /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */
12487        uint8_t RESERVED_3[80];
12488   __IO uint32_t PINTSEL[8];                        /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
12489   __IO uint32_t DMA0_ITRIG_INMUX[23];              /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */
12490        uint8_t RESERVED_4[36];
12491   __IO uint32_t DMA0_OTRIG_INMUX[4];               /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */
12492        uint8_t RESERVED_5[16];
12493   __IO uint32_t FREQMEAS_REF;                      /**< Selection for frequency measurement reference clock, offset: 0x180 */
12494   __IO uint32_t FREQMEAS_TARGET;                   /**< Selection for frequency measurement target clock, offset: 0x184 */
12495        uint8_t RESERVED_6[24];
12496   __IO uint32_t TIMER3CAPTSEL[4];                  /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */
12497        uint8_t RESERVED_7[16];
12498   __IO uint32_t TIMER4CAPTSEL[4];                  /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */
12499        uint8_t RESERVED_8[16];
12500   __IO uint32_t PINTSECSEL[2];                     /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */
12501        uint8_t RESERVED_9[24];
12502   __IO uint32_t DMA1_ITRIG_INMUX[10];              /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */
12503        uint8_t RESERVED_10[24];
12504   __IO uint32_t DMA1_OTRIG_INMUX[4];               /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */
12505        uint8_t RESERVED_11[1264];
12506   __IO uint32_t DMA0_REQ_ENA;                      /**< Enable DMA0 requests, offset: 0x740 */
12507        uint8_t RESERVED_12[4];
12508   __O  uint32_t DMA0_REQ_ENA_SET;                  /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */
12509        uint8_t RESERVED_13[4];
12510   __O  uint32_t DMA0_REQ_ENA_CLR;                  /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */
12511        uint8_t RESERVED_14[12];
12512   __IO uint32_t DMA1_REQ_ENA;                      /**< Enable DMA1 requests, offset: 0x760 */
12513        uint8_t RESERVED_15[4];
12514   __O  uint32_t DMA1_REQ_ENA_SET;                  /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */
12515        uint8_t RESERVED_16[4];
12516   __O  uint32_t DMA1_REQ_ENA_CLR;                  /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */
12517        uint8_t RESERVED_17[12];
12518   __IO uint32_t DMA0_ITRIG_ENA;                    /**< Enable DMA0 triggers, offset: 0x780 */
12519        uint8_t RESERVED_18[4];
12520   __O  uint32_t DMA0_ITRIG_ENA_SET;                /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */
12521        uint8_t RESERVED_19[4];
12522   __O  uint32_t DMA0_ITRIG_ENA_CLR;                /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */
12523        uint8_t RESERVED_20[12];
12524   __IO uint32_t DMA1_ITRIG_ENA;                    /**< Enable DMA1 triggers, offset: 0x7A0 */
12525        uint8_t RESERVED_21[4];
12526   __O  uint32_t DMA1_ITRIG_ENA_SET;                /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */
12527        uint8_t RESERVED_22[4];
12528   __O  uint32_t DMA1_ITRIG_ENA_CLR;                /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */
12529 } INPUTMUX_Type;
12530 
12531 /* ----------------------------------------------------------------------------
12532    -- INPUTMUX Register Masks
12533    ---------------------------------------------------------------------------- */
12534 
12535 /*!
12536  * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
12537  * @{
12538  */
12539 
12540 /*! @name SCT0_INMUX - Input mux register for SCT0 input */
12541 /*! @{ */
12542 
12543 #define INPUTMUX_SCT0_INMUX_INP_N_MASK           (0x1FU)
12544 #define INPUTMUX_SCT0_INMUX_INP_N_SHIFT          (0U)
12545 /*! INP_N - Input number to SCT0 inputs 0 to 6..
12546  *  0b00000..SCT_GPI0 function selected from IOCON register
12547  *  0b00001..SCT_GPI1 function selected from IOCON register
12548  *  0b00010..SCT_GPI2 function selected from IOCON register
12549  *  0b00011..SCT_GPI3 function selected from IOCON register
12550  *  0b00100..SCT_GPI4 function selected from IOCON register
12551  *  0b00101..SCT_GPI5 function selected from IOCON register
12552  *  0b00110..SCT_GPI6 function selected from IOCON register
12553  *  0b00111..SCT_GPI7 function selected from IOCON register
12554  *  0b01000..T0_OUT0 ctimer 0 match[0] output
12555  *  0b01001..T1_OUT0 ctimer 1 match[0] output
12556  *  0b01010..T2_OUT0 ctimer 2 match[0] output
12557  *  0b01011..T3_OUT0 ctimer 3 match[0] output
12558  *  0b01100..T4_OUT0 ctimer 4 match[0] output
12559  *  0b01101..ADC_IRQ interrupt request from ADC
12560  *  0b01110..GPIOINT_BMATCH
12561  *  0b01111..USB0_FRAME_TOGGLE
12562  *  0b10000..USB1_FRAME_TOGGLE
12563  *  0b10001..COMP_OUTPUT output from analog comparator
12564  *  0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing
12565  *  0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing
12566  *  0b10100..I2S_SHARED_WS[0] output from I2S pin sharing
12567  *  0b10101..I2S_SHARED_WS[1] output from I2S pin sharing
12568  *  0b10110..ARM_TXEV interrupt event from cpu0 or cpu1
12569  *  0b10111..DEBUG_HALTED from cpu0 or cpu1
12570  *  0b11000-0b11111..None
12571  */
12572 #define INPUTMUX_SCT0_INMUX_INP_N(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
12573 /*! @} */
12574 
12575 /* The count of INPUTMUX_SCT0_INMUX */
12576 #define INPUTMUX_SCT0_INMUX_COUNT                (7U)
12577 
12578 /*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */
12579 /*! @{ */
12580 
12581 #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK      (0x1FU)
12582 #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT     (0U)
12583 /*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4
12584  *  0b00000..CT_INP0 function selected from IOCON register
12585  *  0b00001..CT_INP1 function selected from IOCON register
12586  *  0b00010..CT_INP2 function selected from IOCON register
12587  *  0b00011..CT_INP3 function selected from IOCON register
12588  *  0b00100..CT_INP4 function selected from IOCON register
12589  *  0b00101..CT_INP5 function selected from IOCON register
12590  *  0b00110..CT_INP6 function selected from IOCON register
12591  *  0b00111..CT_INP7 function selected from IOCON register
12592  *  0b01000..CT_INP8 function selected from IOCON register
12593  *  0b01001..CT_INP9 function selected from IOCON register
12594  *  0b01010..CT_INP10 function selected from IOCON register
12595  *  0b01011..CT_INP11 function selected from IOCON register
12596  *  0b01100..CT_INP12 function selected from IOCON register
12597  *  0b01101..CT_INP13 function selected from IOCON register
12598  *  0b01110..CT_INP14 function selected from IOCON register
12599  *  0b01111..CT_INP15 function selected from IOCON register
12600  *  0b10000..CT_INP16 function selected from IOCON register
12601  *  0b10001..None
12602  *  0b10010..None
12603  *  0b10011..None
12604  *  0b10100..USB0_FRAME_TOGGLE
12605  *  0b10101..USB1_FRAME_TOGGLE
12606  *  0b10110..COMP_OUTPUT output from analog comparator
12607  *  0b10111..I2S_SHARED_WS[0] output from I2S pin sharing
12608  *  0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
12609  *  0b11001-0b11111..None
12610  */
12611 #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK)
12612 /*! @} */
12613 
12614 /* The count of INPUTMUX_TIMER0CAPTSEL */
12615 #define INPUTMUX_TIMER0CAPTSEL_COUNT             (4U)
12616 
12617 /*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */
12618 /*! @{ */
12619 
12620 #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK      (0x1FU)
12621 #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT     (0U)
12622 /*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4
12623  *  0b00000..CT_INP0 function selected from IOCON register
12624  *  0b00001..CT_INP1 function selected from IOCON register
12625  *  0b00010..CT_INP2 function selected from IOCON register
12626  *  0b00011..CT_INP3 function selected from IOCON register
12627  *  0b00100..CT_INP4 function selected from IOCON register
12628  *  0b00101..CT_INP5 function selected from IOCON register
12629  *  0b00110..CT_INP6 function selected from IOCON register
12630  *  0b00111..CT_INP7 function selected from IOCON register
12631  *  0b01000..CT_INP8 function selected from IOCON register
12632  *  0b01001..CT_INP9 function selected from IOCON register
12633  *  0b01010..CT_INP10 function selected from IOCON register
12634  *  0b01011..CT_INP11 function selected from IOCON register
12635  *  0b01100..CT_INP12 function selected from IOCON register
12636  *  0b01101..CT_INP13 function selected from IOCON register
12637  *  0b01110..CT_INP14 function selected from IOCON register
12638  *  0b01111..CT_INP15 function selected from IOCON register
12639  *  0b10000..CT_INP16 function selected from IOCON register
12640  *  0b10001..None
12641  *  0b10010..None
12642  *  0b10011..None
12643  *  0b10100..USB0_FRAME_TOGGLE
12644  *  0b10101..USB1_FRAME_TOGGLE
12645  *  0b10110..COMP_OUTPUT output from analog comparator
12646  *  0b10111..I2S_SHARED_WS[0] output from I2S pin sharing
12647  *  0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
12648  *  0b11001-0b11111..None
12649  */
12650 #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK)
12651 /*! @} */
12652 
12653 /* The count of INPUTMUX_TIMER1CAPTSEL */
12654 #define INPUTMUX_TIMER1CAPTSEL_COUNT             (4U)
12655 
12656 /*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */
12657 /*! @{ */
12658 
12659 #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK      (0x1FU)
12660 #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT     (0U)
12661 /*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4
12662  *  0b00000..CT_INP0 function selected from IOCON register
12663  *  0b00001..CT_INP1 function selected from IOCON register
12664  *  0b00010..CT_INP2 function selected from IOCON register
12665  *  0b00011..CT_INP3 function selected from IOCON register
12666  *  0b00100..CT_INP4 function selected from IOCON register
12667  *  0b00101..CT_INP5 function selected from IOCON register
12668  *  0b00110..CT_INP6 function selected from IOCON register
12669  *  0b00111..CT_INP7 function selected from IOCON register
12670  *  0b01000..CT_INP8 function selected from IOCON register
12671  *  0b01001..CT_INP9 function selected from IOCON register
12672  *  0b01010..CT_INP10 function selected from IOCON register
12673  *  0b01011..CT_INP11 function selected from IOCON register
12674  *  0b01100..CT_INP12 function selected from IOCON register
12675  *  0b01101..CT_INP13 function selected from IOCON register
12676  *  0b01110..CT_INP14 function selected from IOCON register
12677  *  0b01111..CT_INP15 function selected from IOCON register
12678  *  0b10000..CT_INP16 function selected from IOCON register
12679  *  0b10001..None
12680  *  0b10010..None
12681  *  0b10011..None
12682  *  0b10100..USB0_FRAME_TOGGLE
12683  *  0b10101..USB1_FRAME_TOGGLE
12684  *  0b10110..COMP_OUTPUT output from analog comparator
12685  *  0b10111..I2S_SHARED_WS[0] output from I2S pin sharing
12686  *  0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
12687  *  0b11001-0b11111..None
12688  */
12689 #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK)
12690 /*! @} */
12691 
12692 /* The count of INPUTMUX_TIMER2CAPTSEL */
12693 #define INPUTMUX_TIMER2CAPTSEL_COUNT             (4U)
12694 
12695 /*! @name PINTSEL - Pin interrupt select register */
12696 /*! @{ */
12697 
12698 #define INPUTMUX_PINTSEL_INTPIN_MASK             (0x7FU)
12699 #define INPUTMUX_PINTSEL_INTPIN_SHIFT            (0U)
12700 /*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN =
12701  *    (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
12702  */
12703 #define INPUTMUX_PINTSEL_INTPIN(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
12704 /*! @} */
12705 
12706 /* The count of INPUTMUX_PINTSEL */
12707 #define INPUTMUX_PINTSEL_COUNT                   (8U)
12708 
12709 /*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */
12710 /*! @{ */
12711 
12712 #define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK       (0x1FU)
12713 #define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT      (0U)
12714 /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
12715  *  0b00000..Pin interrupt 0
12716  *  0b00001..Pin interrupt 1
12717  *  0b00010..Pin interrupt 2
12718  *  0b00011..Pin interrupt 3
12719  *  0b00100..Timer CTIMER0 Match 0
12720  *  0b00101..Timer CTIMER0 Match 1
12721  *  0b00110..Timer CTIMER1 Match 0
12722  *  0b00111..Timer CTIMER1 Match 1
12723  *  0b01000..Timer CTIMER2 Match 0
12724  *  0b01001..Timer CTIMER2 Match 1
12725  *  0b01010..Timer CTIMER3 Match 0
12726  *  0b01011..Timer CTIMER3 Match 1
12727  *  0b01100..Timer CTIMER4 Match 0
12728  *  0b01101..Timer CTIMER4 Match 1
12729  *  0b01110..COMP_OUTPUT
12730  *  0b01111..DMA0 output trigger mux 0
12731  *  0b10000..DMA0 output trigger mux 1
12732  *  0b10001..DMA0 output trigger mux 1
12733  *  0b10010..DMA0 output trigger mux 3
12734  *  0b10011..SCT0 DMA request 0
12735  *  0b10100..SCT0 DMA request 1
12736  *  0b10101..HASH DMA RX trigger
12737  *  0b10110-0b11111..None
12738  */
12739 #define INPUTMUX_DMA0_ITRIG_INMUX_INP(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK)
12740 /*! @} */
12741 
12742 /* The count of INPUTMUX_DMA0_ITRIG_INMUX */
12743 #define INPUTMUX_DMA0_ITRIG_INMUX_COUNT          (23U)
12744 
12745 /*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */
12746 /*! @{ */
12747 
12748 #define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK       (0x1FU)
12749 #define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT      (0U)
12750 /*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22).
12751  */
12752 #define INPUTMUX_DMA0_OTRIG_INMUX_INP(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK)
12753 /*! @} */
12754 
12755 /* The count of INPUTMUX_DMA0_OTRIG_INMUX */
12756 #define INPUTMUX_DMA0_OTRIG_INMUX_COUNT          (4U)
12757 
12758 /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
12759 /*! @{ */
12760 
12761 #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK         (0x1FU)
12762 #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT        (0U)
12763 /*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock:
12764  *  0b00000..External main crystal oscilator (Clock_in).
12765  *  0b00001..FRO 12MHz clock.
12766  *  0b00010..FRO 96MHz clock.
12767  *  0b00011..Watchdog oscillator / FRO1MHz clock.
12768  *  0b00100..32 kHz oscillator (32k_clk) clock.
12769  *  0b00101..main clock (main_clock).
12770  *  0b00110..FREQME_GPIO_CLK_A.
12771  *  0b00111..FREQME_GPIO_CLK_B.
12772  */
12773 #define INPUTMUX_FREQMEAS_REF_CLKIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
12774 /*! @} */
12775 
12776 /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
12777 /*! @{ */
12778 
12779 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK      (0x1FU)
12780 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT     (0U)
12781 /*! CLKIN - Clock source number (decimal value) for frequency measure function target clock:
12782  *  0b00000..External main crystal oscilator (Clock_in).
12783  *  0b00001..FRO 12MHz clock.
12784  *  0b00010..FRO 96MHz clock.
12785  *  0b00011..Watchdog oscillator / FRO1MHz clock.
12786  *  0b00100..32 kHz oscillator (32k_clk) clock.
12787  *  0b00101..main clock (main_clock).
12788  *  0b00110..FREQME_GPIO_CLK_A.
12789  *  0b00111..FREQME_GPIO_CLK_B.
12790  */
12791 #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
12792 /*! @} */
12793 
12794 /*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */
12795 /*! @{ */
12796 
12797 #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK      (0x1FU)
12798 #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT     (0U)
12799 /*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4
12800  *  0b00000..CT_INP0 function selected from IOCON register
12801  *  0b00001..CT_INP1 function selected from IOCON register
12802  *  0b00010..CT_INP2 function selected from IOCON register
12803  *  0b00011..CT_INP3 function selected from IOCON register
12804  *  0b00100..CT_INP4 function selected from IOCON register
12805  *  0b00101..CT_INP5 function selected from IOCON register
12806  *  0b00110..CT_INP6 function selected from IOCON register
12807  *  0b00111..CT_INP7 function selected from IOCON register
12808  *  0b01000..CT_INP8 function selected from IOCON register
12809  *  0b01001..CT_INP9 function selected from IOCON register
12810  *  0b01010..CT_INP10 function selected from IOCON register
12811  *  0b01011..CT_INP11 function selected from IOCON register
12812  *  0b01100..CT_INP12 function selected from IOCON register
12813  *  0b01101..CT_INP13 function selected from IOCON register
12814  *  0b01110..CT_INP14 function selected from IOCON register
12815  *  0b01111..CT_INP15 function selected from IOCON register
12816  *  0b10000..CT_INP16 function selected from IOCON register
12817  *  0b10001..CT_INP17 function selected from IOCON register
12818  *  0b10010..CT_INP18 function selected from IOCON register
12819  *  0b10011..CT_INP19 function selected from IOCON register
12820  *  0b10100..USB0_FRAME_TOGGLE
12821  *  0b10101..USB1_FRAME_TOGGLE
12822  *  0b10110..COMP_OUTPUT output from analog comparator
12823  *  0b10111..I2S_SHARED_WS[0] output from I2S pin sharing
12824  *  0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
12825  *  0b11001-0b11111..None
12826  */
12827 #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK)
12828 /*! @} */
12829 
12830 /* The count of INPUTMUX_TIMER3CAPTSEL */
12831 #define INPUTMUX_TIMER3CAPTSEL_COUNT             (4U)
12832 
12833 /*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */
12834 /*! @{ */
12835 
12836 #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK      (0x1FU)
12837 #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT     (0U)
12838 /*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4
12839  *  0b00000..CT_INP0 function selected from IOCON register
12840  *  0b00001..CT_INP1 function selected from IOCON register
12841  *  0b00010..CT_INP2 function selected from IOCON register
12842  *  0b00011..CT_INP3 function selected from IOCON register
12843  *  0b00100..CT_INP4 function selected from IOCON register
12844  *  0b00101..CT_INP5 function selected from IOCON register
12845  *  0b00110..CT_INP6 function selected from IOCON register
12846  *  0b00111..CT_INP7 function selected from IOCON register
12847  *  0b01000..CT_INP8 function selected from IOCON register
12848  *  0b01001..CT_INP9 function selected from IOCON register
12849  *  0b01010..CT_INP10 function selected from IOCON register
12850  *  0b01011..CT_INP11 function selected from IOCON register
12851  *  0b01100..CT_INP12 function selected from IOCON register
12852  *  0b01101..CT_INP13 function selected from IOCON register
12853  *  0b01110..CT_INP14 function selected from IOCON register
12854  *  0b01111..CT_INP15 function selected from IOCON register
12855  *  0b10000..CT_INP16 function selected from IOCON register
12856  *  0b10001..CT_INP17 function selected from IOCON register
12857  *  0b10010..CT_INP18 function selected from IOCON register
12858  *  0b10011..CT_INP19 function selected from IOCON register
12859  *  0b10100..USB0_FRAME_TOGGLE
12860  *  0b10101..USB1_FRAME_TOGGLE
12861  *  0b10110..COMP_OUTPUT output from analog comparator
12862  *  0b10111..I2S_SHARED_WS[0] output from I2S pin sharing
12863  *  0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
12864  *  0b11001-0b11111..None
12865  */
12866 #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK)
12867 /*! @} */
12868 
12869 /* The count of INPUTMUX_TIMER4CAPTSEL */
12870 #define INPUTMUX_TIMER4CAPTSEL_COUNT             (4U)
12871 
12872 /*! @name PINTSECSEL - Pin interrupt secure select register */
12873 /*! @{ */
12874 
12875 #define INPUTMUX_PINTSECSEL_INTPIN_MASK          (0x3FU)
12876 #define INPUTMUX_PINTSECSEL_INTPIN_SHIFT         (0U)
12877 /*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x:
12878  *    INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31.
12879  */
12880 #define INPUTMUX_PINTSECSEL_INTPIN(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK)
12881 /*! @} */
12882 
12883 /* The count of INPUTMUX_PINTSECSEL */
12884 #define INPUTMUX_PINTSECSEL_COUNT                (2U)
12885 
12886 /*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */
12887 /*! @{ */
12888 
12889 #define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK       (0xFU)
12890 #define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT      (0U)
12891 /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
12892  *  0b0000..Pin interrupt 0
12893  *  0b0001..Pin interrupt 1
12894  *  0b0010..Pin interrupt 2
12895  *  0b0011..Pin interrupt 3
12896  *  0b0100..Timer CTIMER0 Match 0
12897  *  0b0101..Timer CTIMER0 Match 1
12898  *  0b0110..Timer CTIMER2 Match 0
12899  *  0b0111..Timer CTIMER4 Match 0
12900  *  0b1000..DMA1 output trigger mux 0
12901  *  0b1001..DMA1 output trigger mux 1
12902  *  0b1010..DMA1 output trigger mux 2
12903  *  0b1011..DMA1 output trigger mux 3
12904  *  0b1100..SCT0 DMA request 0
12905  *  0b1101..SCT0 DMA request 1
12906  *  0b1110..HASH DMA RX trigger
12907  *  0b1111..None
12908  */
12909 #define INPUTMUX_DMA1_ITRIG_INMUX_INP(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK)
12910 /*! @} */
12911 
12912 /* The count of INPUTMUX_DMA1_ITRIG_INMUX */
12913 #define INPUTMUX_DMA1_ITRIG_INMUX_COUNT          (10U)
12914 
12915 /*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */
12916 /*! @{ */
12917 
12918 #define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK       (0xFU)
12919 #define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT      (0U)
12920 /*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9).
12921  */
12922 #define INPUTMUX_DMA1_OTRIG_INMUX_INP(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK)
12923 /*! @} */
12924 
12925 /* The count of INPUTMUX_DMA1_OTRIG_INMUX */
12926 #define INPUTMUX_DMA1_OTRIG_INMUX_COUNT          (4U)
12927 
12928 /*! @name DMA0_REQ_ENA - Enable DMA0 requests */
12929 /*! @{ */
12930 
12931 #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK       (0x7FFFFFU)
12932 #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT      (0U)
12933 /*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
12934  */
12935 #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK)
12936 /*! @} */
12937 
12938 /*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */
12939 /*! @{ */
12940 
12941 #define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK       (0x7FFFFFU)
12942 #define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT      (0U)
12943 /*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register
12944  */
12945 #define INPUTMUX_DMA0_REQ_ENA_SET_SET(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK)
12946 /*! @} */
12947 
12948 /*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */
12949 /*! @{ */
12950 
12951 #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK       (0x7FFFFFU)
12952 #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT      (0U)
12953 /*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register
12954  */
12955 #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK)
12956 /*! @} */
12957 
12958 /*! @name DMA1_REQ_ENA - Enable DMA1 requests */
12959 /*! @{ */
12960 
12961 #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK       (0x3FFU)
12962 #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT      (0U)
12963 /*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
12964  */
12965 #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK)
12966 /*! @} */
12967 
12968 /*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */
12969 /*! @{ */
12970 
12971 #define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK       (0x3FFU)
12972 #define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT      (0U)
12973 /*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register
12974  */
12975 #define INPUTMUX_DMA1_REQ_ENA_SET_SET(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK)
12976 /*! @} */
12977 
12978 /*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */
12979 /*! @{ */
12980 
12981 #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK       (0x3FFU)
12982 #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT      (0U)
12983 /*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register
12984  */
12985 #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK)
12986 /*! @} */
12987 
12988 /*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */
12989 /*! @{ */
12990 
12991 #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK   (0x3FFFFFU)
12992 #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT  (0U)
12993 /*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
12994  */
12995 #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK)
12996 /*! @} */
12997 
12998 /*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */
12999 /*! @{ */
13000 
13001 #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK     (0x3FFFFFU)
13002 #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT    (0U)
13003 /*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no
13004  *    change in DMA0_ITRIG_ENA register
13005  */
13006 #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK)
13007 /*! @} */
13008 
13009 /*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */
13010 /*! @{ */
13011 
13012 #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK     (0x3FFFFFU)
13013 #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT    (0U)
13014 /*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no
13015  *    change in DMA0_ITRIG_ENA register
13016  */
13017 #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK)
13018 /*! @} */
13019 
13020 /*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */
13021 /*! @{ */
13022 
13023 #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK   (0x7FFFU)
13024 #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT  (0U)
13025 /*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
13026  */
13027 #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK)
13028 /*! @} */
13029 
13030 /*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */
13031 /*! @{ */
13032 
13033 #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK     (0x7FFFU)
13034 #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT    (0U)
13035 /*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no
13036  *    change in DMA1_ITRIG_ENA register
13037  */
13038 #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK)
13039 /*! @} */
13040 
13041 /*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */
13042 /*! @{ */
13043 
13044 #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK     (0x7FFFU)
13045 #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT    (0U)
13046 /*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no
13047  *    change in DMA1_ITRIG_ENA register
13048  */
13049 #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK)
13050 /*! @} */
13051 
13052 
13053 /*!
13054  * @}
13055  */ /* end of group INPUTMUX_Register_Masks */
13056 
13057 
13058 /* INPUTMUX - Peripheral instance base addresses */
13059 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
13060   /** Peripheral INPUTMUX base address */
13061   #define INPUTMUX_BASE                            (0x50006000u)
13062   /** Peripheral INPUTMUX base address */
13063   #define INPUTMUX_BASE_NS                         (0x40006000u)
13064   /** Peripheral INPUTMUX base pointer */
13065   #define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
13066   /** Peripheral INPUTMUX base pointer */
13067   #define INPUTMUX_NS                              ((INPUTMUX_Type *)INPUTMUX_BASE_NS)
13068   /** Array initializer of INPUTMUX peripheral base addresses */
13069   #define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
13070   /** Array initializer of INPUTMUX peripheral base pointers */
13071   #define INPUTMUX_BASE_PTRS                       { INPUTMUX }
13072   /** Array initializer of INPUTMUX peripheral base addresses */
13073   #define INPUTMUX_BASE_ADDRS_NS                   { INPUTMUX_BASE_NS }
13074   /** Array initializer of INPUTMUX peripheral base pointers */
13075   #define INPUTMUX_BASE_PTRS_NS                    { INPUTMUX_NS }
13076 #else
13077   /** Peripheral INPUTMUX base address */
13078   #define INPUTMUX_BASE                            (0x40006000u)
13079   /** Peripheral INPUTMUX base pointer */
13080   #define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
13081   /** Array initializer of INPUTMUX peripheral base addresses */
13082   #define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
13083   /** Array initializer of INPUTMUX peripheral base pointers */
13084   #define INPUTMUX_BASE_PTRS                       { INPUTMUX }
13085 #endif
13086 
13087 /*!
13088  * @}
13089  */ /* end of group INPUTMUX_Peripheral_Access_Layer */
13090 
13091 
13092 /* ----------------------------------------------------------------------------
13093    -- IOCON Peripheral Access Layer
13094    ---------------------------------------------------------------------------- */
13095 
13096 /*!
13097  * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
13098  * @{
13099  */
13100 
13101 /** IOCON - Register Layout Typedef */
13102 typedef struct {
13103   __IO uint32_t PIO[2][32];                        /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
13104 } IOCON_Type;
13105 
13106 /* ----------------------------------------------------------------------------
13107    -- IOCON Register Masks
13108    ---------------------------------------------------------------------------- */
13109 
13110 /*!
13111  * @addtogroup IOCON_Register_Masks IOCON Register Masks
13112  * @{
13113  */
13114 
13115 /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */
13116 /*! @{ */
13117 
13118 #define IOCON_PIO_FUNC_MASK                      (0xFU)
13119 #define IOCON_PIO_FUNC_SHIFT                     (0U)
13120 /*! FUNC - Selects pin function.
13121  *  0b0000..Alternative connection 0.
13122  *  0b0001..Alternative connection 1.
13123  *  0b0010..Alternative connection 2.
13124  *  0b0011..Alternative connection 3.
13125  *  0b0100..Alternative connection 4.
13126  *  0b0101..Alternative connection 5.
13127  *  0b0110..Alternative connection 6.
13128  *  0b0111..Alternative connection 7.
13129  */
13130 #define IOCON_PIO_FUNC(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
13131 
13132 #define IOCON_PIO_MODE_MASK                      (0x30U)
13133 #define IOCON_PIO_MODE_SHIFT                     (4U)
13134 /*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
13135  *  0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
13136  *  0b01..Pull-down. Pull-down resistor enabled.
13137  *  0b10..Pull-up. Pull-up resistor enabled.
13138  *  0b11..Repeater. Repeater mode.
13139  */
13140 #define IOCON_PIO_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
13141 
13142 #define IOCON_PIO_SLEW_MASK                      (0x40U)
13143 #define IOCON_PIO_SLEW_SHIFT                     (6U)
13144 /*! SLEW - Driver slew rate.
13145  *  0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously.
13146  *  0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details.
13147  */
13148 #define IOCON_PIO_SLEW(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
13149 
13150 #define IOCON_PIO_INVERT_MASK                    (0x80U)
13151 #define IOCON_PIO_INVERT_SHIFT                   (7U)
13152 /*! INVERT - Input polarity.
13153  *  0b0..Disabled. Input function is not inverted.
13154  *  0b1..Enabled. Input is function inverted.
13155  */
13156 #define IOCON_PIO_INVERT(x)                      (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
13157 
13158 #define IOCON_PIO_DIGIMODE_MASK                  (0x100U)
13159 #define IOCON_PIO_DIGIMODE_SHIFT                 (8U)
13160 /*! DIGIMODE - Select Digital mode.
13161  *  0b0..Disable digital mode. Digital input set to 0.
13162  *  0b1..Enable Digital mode. Digital input is enabled.
13163  */
13164 #define IOCON_PIO_DIGIMODE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
13165 
13166 #define IOCON_PIO_OD_MASK                        (0x200U)
13167 #define IOCON_PIO_OD_SHIFT                       (9U)
13168 /*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0).
13169  *  0b0..Normal. Normal push-pull output
13170  *  0b1..Open-drain. Simulated open-drain output (high drive disabled).
13171  */
13172 #define IOCON_PIO_OD(x)                          (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
13173 
13174 #define IOCON_PIO_ASW_MASK                       (0x400U)
13175 #define IOCON_PIO_ASW_SHIFT                      (10U)
13176 /*! ASW - Analog switch input control.
13177  *  0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed
13178  *       (enabled). For the other pins, analog switch is open (disabled).
13179  *  0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled)
13180  */
13181 #define IOCON_PIO_ASW(x)                         (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK)
13182 
13183 #define IOCON_PIO_SSEL_MASK                      (0x800U)
13184 #define IOCON_PIO_SSEL_SHIFT                     (11U)
13185 /*! SSEL - Supply Selection bit.
13186  *  0b0..3V3 Signaling in I2C Mode.
13187  *  0b1..1V8 Signaling in I2C Mode.
13188  */
13189 #define IOCON_PIO_SSEL(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK)
13190 
13191 #define IOCON_PIO_FILTEROFF_MASK                 (0x1000U)
13192 #define IOCON_PIO_FILTEROFF_SHIFT                (12U)
13193 /*! FILTEROFF - Controls input glitch filter.
13194  *  0b0..Filter enabled.
13195  *  0b1..Filter disabled.
13196  */
13197 #define IOCON_PIO_FILTEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
13198 
13199 #define IOCON_PIO_ECS_MASK                       (0x2000U)
13200 #define IOCON_PIO_ECS_SHIFT                      (13U)
13201 /*! ECS - Pull-up current source enable in I2C mode.
13202  *  0b1..Enabled. Pull resistor is conencted.
13203  *  0b0..Disabled. IO is in open drain cell.
13204  */
13205 #define IOCON_PIO_ECS(x)                         (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK)
13206 
13207 #define IOCON_PIO_EGP_MASK                       (0x4000U)
13208 #define IOCON_PIO_EGP_SHIFT                      (14U)
13209 /*! EGP - Switch between GPIO mode and I2C mode.
13210  *  0b0..I2C mode.
13211  *  0b1..GPIO mode.
13212  */
13213 #define IOCON_PIO_EGP(x)                         (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK)
13214 
13215 #define IOCON_PIO_I2CFILTER_MASK                 (0x8000U)
13216 #define IOCON_PIO_I2CFILTER_SHIFT                (15U)
13217 /*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation.
13218  *  0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C.
13219  *  0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C.
13220  */
13221 #define IOCON_PIO_I2CFILTER(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
13222 /*! @} */
13223 
13224 /* The count of IOCON_PIO */
13225 #define IOCON_PIO_COUNT                          (2U)
13226 
13227 /* The count of IOCON_PIO */
13228 #define IOCON_PIO_COUNT2                         (32U)
13229 
13230 
13231 /*!
13232  * @}
13233  */ /* end of group IOCON_Register_Masks */
13234 
13235 
13236 /* IOCON - Peripheral instance base addresses */
13237 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
13238   /** Peripheral IOCON base address */
13239   #define IOCON_BASE                               (0x50001000u)
13240   /** Peripheral IOCON base address */
13241   #define IOCON_BASE_NS                            (0x40001000u)
13242   /** Peripheral IOCON base pointer */
13243   #define IOCON                                    ((IOCON_Type *)IOCON_BASE)
13244   /** Peripheral IOCON base pointer */
13245   #define IOCON_NS                                 ((IOCON_Type *)IOCON_BASE_NS)
13246   /** Array initializer of IOCON peripheral base addresses */
13247   #define IOCON_BASE_ADDRS                         { IOCON_BASE }
13248   /** Array initializer of IOCON peripheral base pointers */
13249   #define IOCON_BASE_PTRS                          { IOCON }
13250   /** Array initializer of IOCON peripheral base addresses */
13251   #define IOCON_BASE_ADDRS_NS                      { IOCON_BASE_NS }
13252   /** Array initializer of IOCON peripheral base pointers */
13253   #define IOCON_BASE_PTRS_NS                       { IOCON_NS }
13254 #else
13255   /** Peripheral IOCON base address */
13256   #define IOCON_BASE                               (0x40001000u)
13257   /** Peripheral IOCON base pointer */
13258   #define IOCON                                    ((IOCON_Type *)IOCON_BASE)
13259   /** Array initializer of IOCON peripheral base addresses */
13260   #define IOCON_BASE_ADDRS                         { IOCON_BASE }
13261   /** Array initializer of IOCON peripheral base pointers */
13262   #define IOCON_BASE_PTRS                          { IOCON }
13263 #endif
13264 
13265 /*!
13266  * @}
13267  */ /* end of group IOCON_Peripheral_Access_Layer */
13268 
13269 
13270 /* ----------------------------------------------------------------------------
13271    -- MAILBOX Peripheral Access Layer
13272    ---------------------------------------------------------------------------- */
13273 
13274 /*!
13275  * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer
13276  * @{
13277  */
13278 
13279 /** MAILBOX - Register Layout Typedef */
13280 typedef struct {
13281   struct {                                         /* offset: 0x0, array step: 0x10 */
13282     __IO uint32_t IRQ;                               /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */
13283     __O  uint32_t IRQSET;                            /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */
13284     __O  uint32_t IRQCLR;                            /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */
13285          uint8_t RESERVED_0[4];
13286   } MBOXIRQ[2];
13287        uint8_t RESERVED_0[216];
13288   __IO uint32_t MUTEX;                             /**< Mutual exclusion register[1], offset: 0xF8 */
13289 } MAILBOX_Type;
13290 
13291 /* ----------------------------------------------------------------------------
13292    -- MAILBOX Register Masks
13293    ---------------------------------------------------------------------------- */
13294 
13295 /*!
13296  * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks
13297  * @{
13298  */
13299 
13300 /*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */
13301 /*! @{ */
13302 
13303 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK          (0xFFFFFFFFU)
13304 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT         (0U)
13305 /*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller.
13306  */
13307 #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x)            (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK)
13308 /*! @} */
13309 
13310 /* The count of MAILBOX_MBOXIRQ_IRQ */
13311 #define MAILBOX_MBOXIRQ_IRQ_COUNT                (2U)
13312 
13313 /*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */
13314 /*! @{ */
13315 
13316 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK    (0xFFFFFFFFU)
13317 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT   (0U)
13318 /*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register.
13319  */
13320 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x)      (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK)
13321 /*! @} */
13322 
13323 /* The count of MAILBOX_MBOXIRQ_IRQSET */
13324 #define MAILBOX_MBOXIRQ_IRQSET_COUNT             (2U)
13325 
13326 /*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */
13327 /*! @{ */
13328 
13329 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK    (0xFFFFFFFFU)
13330 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT   (0U)
13331 /*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register.
13332  */
13333 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x)      (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK)
13334 /*! @} */
13335 
13336 /* The count of MAILBOX_MBOXIRQ_IRQCLR */
13337 #define MAILBOX_MBOXIRQ_IRQCLR_COUNT             (2U)
13338 
13339 /*! @name MUTEX - Mutual exclusion register[1] */
13340 /*! @{ */
13341 
13342 #define MAILBOX_MUTEX_EX_MASK                    (0x1U)
13343 #define MAILBOX_MUTEX_EX_SHIFT                   (0U)
13344 /*! EX - Cleared when read, set when written. See usage description above.
13345  */
13346 #define MAILBOX_MUTEX_EX(x)                      (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK)
13347 /*! @} */
13348 
13349 
13350 /*!
13351  * @}
13352  */ /* end of group MAILBOX_Register_Masks */
13353 
13354 
13355 /* MAILBOX - Peripheral instance base addresses */
13356 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
13357   /** Peripheral MAILBOX base address */
13358   #define MAILBOX_BASE                             (0x5008B000u)
13359   /** Peripheral MAILBOX base address */
13360   #define MAILBOX_BASE_NS                          (0x4008B000u)
13361   /** Peripheral MAILBOX base pointer */
13362   #define MAILBOX                                  ((MAILBOX_Type *)MAILBOX_BASE)
13363   /** Peripheral MAILBOX base pointer */
13364   #define MAILBOX_NS                               ((MAILBOX_Type *)MAILBOX_BASE_NS)
13365   /** Array initializer of MAILBOX peripheral base addresses */
13366   #define MAILBOX_BASE_ADDRS                       { MAILBOX_BASE }
13367   /** Array initializer of MAILBOX peripheral base pointers */
13368   #define MAILBOX_BASE_PTRS                        { MAILBOX }
13369   /** Array initializer of MAILBOX peripheral base addresses */
13370   #define MAILBOX_BASE_ADDRS_NS                    { MAILBOX_BASE_NS }
13371   /** Array initializer of MAILBOX peripheral base pointers */
13372   #define MAILBOX_BASE_PTRS_NS                     { MAILBOX_NS }
13373 #else
13374   /** Peripheral MAILBOX base address */
13375   #define MAILBOX_BASE                             (0x4008B000u)
13376   /** Peripheral MAILBOX base pointer */
13377   #define MAILBOX                                  ((MAILBOX_Type *)MAILBOX_BASE)
13378   /** Array initializer of MAILBOX peripheral base addresses */
13379   #define MAILBOX_BASE_ADDRS                       { MAILBOX_BASE }
13380   /** Array initializer of MAILBOX peripheral base pointers */
13381   #define MAILBOX_BASE_PTRS                        { MAILBOX }
13382 #endif
13383 /** Interrupt vectors for the MAILBOX peripheral type */
13384 #define MAILBOX_IRQS                             { MAILBOX_IRQn }
13385 
13386 /*!
13387  * @}
13388  */ /* end of group MAILBOX_Peripheral_Access_Layer */
13389 
13390 
13391 /* ----------------------------------------------------------------------------
13392    -- MRT Peripheral Access Layer
13393    ---------------------------------------------------------------------------- */
13394 
13395 /*!
13396  * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
13397  * @{
13398  */
13399 
13400 /** MRT - Register Layout Typedef */
13401 typedef struct {
13402   struct {                                         /* offset: 0x0, array step: 0x10 */
13403     __IO uint32_t INTVAL;                            /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
13404     __I  uint32_t TIMER;                             /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
13405     __IO uint32_t CTRL;                              /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
13406     __IO uint32_t STAT;                              /**< MRT Status register., array offset: 0xC, array step: 0x10 */
13407   } CHANNEL[4];
13408        uint8_t RESERVED_0[176];
13409   __IO uint32_t MODCFG;                            /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
13410   __I  uint32_t IDLE_CH;                           /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
13411   __IO uint32_t IRQ_FLAG;                          /**< Global interrupt flag register, offset: 0xF8 */
13412 } MRT_Type;
13413 
13414 /* ----------------------------------------------------------------------------
13415    -- MRT Register Masks
13416    ---------------------------------------------------------------------------- */
13417 
13418 /*!
13419  * @addtogroup MRT_Register_Masks MRT Register Masks
13420  * @{
13421  */
13422 
13423 /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
13424 /*! @{ */
13425 
13426 #define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
13427 #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
13428 /*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
13429  *    channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
13430  *    this bit field starts the timer immediately. If the timer is running, writing a zero to this
13431  *    bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
13432  *    stops at the end of the time interval.
13433  */
13434 #define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
13435 
13436 #define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
13437 #define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
13438 /*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
13439  *    This bit is write-only. Reading this bit always returns 0.
13440  *  0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
13441  *       time interval if the repeat mode is selected.
13442  *  0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
13443  */
13444 #define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
13445 /*! @} */
13446 
13447 /* The count of MRT_CHANNEL_INTVAL */
13448 #define MRT_CHANNEL_INTVAL_COUNT                 (4U)
13449 
13450 /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
13451 /*! @{ */
13452 
13453 #define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
13454 #define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
13455 /*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
13456  *    register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
13457  *    or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
13458  *    register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
13459  *    returns -1 (0x00FF FFFF).
13460  */
13461 #define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
13462 /*! @} */
13463 
13464 /* The count of MRT_CHANNEL_TIMER */
13465 #define MRT_CHANNEL_TIMER_COUNT                  (4U)
13466 
13467 /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
13468 /*! @{ */
13469 
13470 #define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
13471 #define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
13472 /*! INTEN - Enable the TIMERn interrupt.
13473  *  0b0..Disabled. TIMERn interrupt is disabled.
13474  *  0b1..Enabled. TIMERn interrupt is enabled.
13475  */
13476 #define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
13477 
13478 #define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
13479 #define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
13480 /*! MODE - Selects timer mode.
13481  *  0b00..Repeat interrupt mode.
13482  *  0b01..One-shot interrupt mode.
13483  *  0b10..One-shot stall mode.
13484  *  0b11..Reserved.
13485  */
13486 #define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
13487 /*! @} */
13488 
13489 /* The count of MRT_CHANNEL_CTRL */
13490 #define MRT_CHANNEL_CTRL_COUNT                   (4U)
13491 
13492 /*! @name CHANNEL_STAT - MRT Status register. */
13493 /*! @{ */
13494 
13495 #define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
13496 #define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
13497 /*! INTFLAG - Monitors the interrupt flag.
13498  *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
13499  *  0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
13500  *       the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
13501  *       are raised. Writing a 1 to this bit clears the interrupt request.
13502  */
13503 #define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
13504 
13505 #define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
13506 #define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
13507 /*! RUN - Indicates the state of TIMERn. This bit is read-only.
13508  *  0b0..Idle state. TIMERn is stopped.
13509  *  0b1..Running. TIMERn is running.
13510  */
13511 #define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
13512 
13513 #define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
13514 #define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
13515 /*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG
13516  *    register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating
13517  *    modes.
13518  *  0b0..This channel is not in use.
13519  *  0b1..This channel is in use.
13520  */
13521 #define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
13522 /*! @} */
13523 
13524 /* The count of MRT_CHANNEL_STAT */
13525 #define MRT_CHANNEL_STAT_COUNT                   (4U)
13526 
13527 /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
13528 /*! @{ */
13529 
13530 #define MRT_MODCFG_NOC_MASK                      (0xFU)
13531 #define MRT_MODCFG_NOC_SHIFT                     (0U)
13532 /*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
13533  */
13534 #define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
13535 
13536 #define MRT_MODCFG_NOB_MASK                      (0x1F0U)
13537 #define MRT_MODCFG_NOB_SHIFT                     (4U)
13538 /*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.)
13539  */
13540 #define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
13541 
13542 #define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
13543 #define MRT_MODCFG_MULTITASK_SHIFT               (31U)
13544 /*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
13545  *  0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
13546  *  0b1..Multi-task mode.
13547  */
13548 #define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
13549 /*! @} */
13550 
13551 /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
13552 /*! @{ */
13553 
13554 #define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
13555 #define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
13556 /*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
13557  *    positioned such that it can be used as an offset from the MRT base address in order to access
13558  *    the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
13559  *    text above for more details.
13560  */
13561 #define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
13562 /*! @} */
13563 
13564 /*! @name IRQ_FLAG - Global interrupt flag register */
13565 /*! @{ */
13566 
13567 #define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
13568 #define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
13569 /*! GFLAG0 - Monitors the interrupt flag of TIMER0.
13570  *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
13571  *  0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
13572  *       the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
13573  *       interrupt are raised. Writing a 1 to this bit clears the interrupt request.
13574  */
13575 #define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
13576 
13577 #define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
13578 #define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
13579 /*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
13580  */
13581 #define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
13582 
13583 #define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
13584 #define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
13585 /*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.
13586  */
13587 #define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
13588 
13589 #define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
13590 #define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
13591 /*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.
13592  */
13593 #define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
13594 /*! @} */
13595 
13596 
13597 /*!
13598  * @}
13599  */ /* end of group MRT_Register_Masks */
13600 
13601 
13602 /* MRT - Peripheral instance base addresses */
13603 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
13604   /** Peripheral MRT0 base address */
13605   #define MRT0_BASE                                (0x5000D000u)
13606   /** Peripheral MRT0 base address */
13607   #define MRT0_BASE_NS                             (0x4000D000u)
13608   /** Peripheral MRT0 base pointer */
13609   #define MRT0                                     ((MRT_Type *)MRT0_BASE)
13610   /** Peripheral MRT0 base pointer */
13611   #define MRT0_NS                                  ((MRT_Type *)MRT0_BASE_NS)
13612   /** Array initializer of MRT peripheral base addresses */
13613   #define MRT_BASE_ADDRS                           { MRT0_BASE }
13614   /** Array initializer of MRT peripheral base pointers */
13615   #define MRT_BASE_PTRS                            { MRT0 }
13616   /** Array initializer of MRT peripheral base addresses */
13617   #define MRT_BASE_ADDRS_NS                        { MRT0_BASE_NS }
13618   /** Array initializer of MRT peripheral base pointers */
13619   #define MRT_BASE_PTRS_NS                         { MRT0_NS }
13620 #else
13621   /** Peripheral MRT0 base address */
13622   #define MRT0_BASE                                (0x4000D000u)
13623   /** Peripheral MRT0 base pointer */
13624   #define MRT0                                     ((MRT_Type *)MRT0_BASE)
13625   /** Array initializer of MRT peripheral base addresses */
13626   #define MRT_BASE_ADDRS                           { MRT0_BASE }
13627   /** Array initializer of MRT peripheral base pointers */
13628   #define MRT_BASE_PTRS                            { MRT0 }
13629 #endif
13630 /** Interrupt vectors for the MRT peripheral type */
13631 #define MRT_IRQS                                 { MRT0_IRQn }
13632 
13633 /*!
13634  * @}
13635  */ /* end of group MRT_Peripheral_Access_Layer */
13636 
13637 
13638 /* ----------------------------------------------------------------------------
13639    -- OSTIMER Peripheral Access Layer
13640    ---------------------------------------------------------------------------- */
13641 
13642 /*!
13643  * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer
13644  * @{
13645  */
13646 
13647 /** OSTIMER - Register Layout Typedef */
13648 typedef struct {
13649   __I  uint32_t EVTIMERL;                          /**< EVTIMER Low Register, offset: 0x0 */
13650   __I  uint32_t EVTIMERH;                          /**< EVTIMER High Register, offset: 0x4 */
13651   __I  uint32_t CAPTURE_L;                         /**< Capture Low Register, offset: 0x8 */
13652   __I  uint32_t CAPTURE_H;                         /**< Capture High Register, offset: 0xC */
13653   __IO uint32_t MATCH_L;                           /**< Match Low Register, offset: 0x10 */
13654   __IO uint32_t MATCH_H;                           /**< Match High Register, offset: 0x14 */
13655        uint8_t RESERVED_0[4];
13656   __IO uint32_t OSEVENT_CTRL;                      /**< OS_EVENT TIMER Control Register, offset: 0x1C */
13657 } OSTIMER_Type;
13658 
13659 /* ----------------------------------------------------------------------------
13660    -- OSTIMER Register Masks
13661    ---------------------------------------------------------------------------- */
13662 
13663 /*!
13664  * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks
13665  * @{
13666  */
13667 
13668 /*! @name EVTIMERL - EVTIMER Low Register */
13669 /*! @{ */
13670 
13671 #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
13672 #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
13673 /*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits
13674  *    EVTIMER. Note: There is only one EVTIMER, readable from all domains.
13675  */
13676 #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
13677 /*! @} */
13678 
13679 /*! @name EVTIMERH - EVTIMER High Register */
13680 /*! @{ */
13681 
13682 #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU)
13683 #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
13684 /*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits
13685  *    EVTIMER. Note there is only one EVTIMER, readable from all domains.
13686  */
13687 #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
13688 /*! @} */
13689 
13690 /*! @name CAPTURE_L - Capture Low Register */
13691 /*! @{ */
13692 
13693 #define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK     (0xFFFFFFFFU)
13694 #define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT    (0U)
13695 /*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at
13696  *    the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();").
13697  */
13698 #define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK)
13699 /*! @} */
13700 
13701 /*! @name CAPTURE_H - Capture High Register */
13702 /*! @{ */
13703 
13704 #define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK     (0x3FFU)
13705 #define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT    (0U)
13706 /*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at
13707  *    the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();").
13708  */
13709 #define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK)
13710 /*! @} */
13711 
13712 /*! @name MATCH_L - Match Low Register */
13713 /*! @{ */
13714 
13715 #define OSTIMER_MATCH_L_MATCH_VALUE_MASK         (0xFFFFFFFFU)
13716 #define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT        (0U)
13717 /*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central
13718  *    EVTIMER. When a match occurs, an interrupt request is generated if enabled.
13719  */
13720 #define OSTIMER_MATCH_L_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK)
13721 /*! @} */
13722 
13723 /*! @name MATCH_H - Match High Register */
13724 /*! @{ */
13725 
13726 #define OSTIMER_MATCH_H_MATCH_VALUE_MASK         (0x3FFU)
13727 #define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT        (0U)
13728 /*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared
13729  *    against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled.
13730  */
13731 #define OSTIMER_MATCH_H_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK)
13732 /*! @} */
13733 
13734 /*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */
13735 /*! @{ */
13736 
13737 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
13738 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
13739 /*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and
13740  *    the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes
13741  *    to clear this bit are asynchronous. It should be done before a new match value is written into
13742  *    the MATCH_L/H registers.
13743  */
13744 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)
13745 
13746 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
13747 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
13748 /*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will
13749  *    be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests
13750  *    due to the OSTIMER_INTR flag are blocked.
13751  */
13752 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x)   (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)
13753 
13754 #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK   (0x4U)
13755 #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT  (2U)
13756 /*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In
13757  *    typical applications it should not be necessary to test this bit. [1]
13758  */
13759 #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x)     (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)
13760 /*! @} */
13761 
13762 
13763 /*!
13764  * @}
13765  */ /* end of group OSTIMER_Register_Masks */
13766 
13767 
13768 /* OSTIMER - Peripheral instance base addresses */
13769 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
13770   /** Peripheral OSTIMER base address */
13771   #define OSTIMER_BASE                             (0x5002D000u)
13772   /** Peripheral OSTIMER base address */
13773   #define OSTIMER_BASE_NS                          (0x4002D000u)
13774   /** Peripheral OSTIMER base pointer */
13775   #define OSTIMER                                  ((OSTIMER_Type *)OSTIMER_BASE)
13776   /** Peripheral OSTIMER base pointer */
13777   #define OSTIMER_NS                               ((OSTIMER_Type *)OSTIMER_BASE_NS)
13778   /** Array initializer of OSTIMER peripheral base addresses */
13779   #define OSTIMER_BASE_ADDRS                       { OSTIMER_BASE }
13780   /** Array initializer of OSTIMER peripheral base pointers */
13781   #define OSTIMER_BASE_PTRS                        { OSTIMER }
13782   /** Array initializer of OSTIMER peripheral base addresses */
13783   #define OSTIMER_BASE_ADDRS_NS                    { OSTIMER_BASE_NS }
13784   /** Array initializer of OSTIMER peripheral base pointers */
13785   #define OSTIMER_BASE_PTRS_NS                     { OSTIMER_NS }
13786 #else
13787   /** Peripheral OSTIMER base address */
13788   #define OSTIMER_BASE                             (0x4002D000u)
13789   /** Peripheral OSTIMER base pointer */
13790   #define OSTIMER                                  ((OSTIMER_Type *)OSTIMER_BASE)
13791   /** Array initializer of OSTIMER peripheral base addresses */
13792   #define OSTIMER_BASE_ADDRS                       { OSTIMER_BASE }
13793   /** Array initializer of OSTIMER peripheral base pointers */
13794   #define OSTIMER_BASE_PTRS                        { OSTIMER }
13795 #endif
13796 /** Interrupt vectors for the OSTIMER peripheral type */
13797 #define OSTIMER_IRQS                             { OS_EVENT_IRQn }
13798 
13799 /*!
13800  * @}
13801  */ /* end of group OSTIMER_Peripheral_Access_Layer */
13802 
13803 
13804 /* ----------------------------------------------------------------------------
13805    -- PINT Peripheral Access Layer
13806    ---------------------------------------------------------------------------- */
13807 
13808 /*!
13809  * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
13810  * @{
13811  */
13812 
13813 /** PINT - Register Layout Typedef */
13814 typedef struct {
13815   __IO uint32_t ISEL;                              /**< Pin Interrupt Mode register, offset: 0x0 */
13816   __IO uint32_t IENR;                              /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
13817   __O  uint32_t SIENR;                             /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
13818   __O  uint32_t CIENR;                             /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
13819   __IO uint32_t IENF;                              /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
13820   __O  uint32_t SIENF;                             /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
13821   __O  uint32_t CIENF;                             /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
13822   __IO uint32_t RISE;                              /**< Pin interrupt rising edge register, offset: 0x1C */
13823   __IO uint32_t FALL;                              /**< Pin interrupt falling edge register, offset: 0x20 */
13824   __IO uint32_t IST;                               /**< Pin interrupt status register, offset: 0x24 */
13825   __IO uint32_t PMCTRL;                            /**< Pattern match interrupt control register, offset: 0x28 */
13826   __IO uint32_t PMSRC;                             /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
13827   __IO uint32_t PMCFG;                             /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
13828 } PINT_Type;
13829 
13830 /* ----------------------------------------------------------------------------
13831    -- PINT Register Masks
13832    ---------------------------------------------------------------------------- */
13833 
13834 /*!
13835  * @addtogroup PINT_Register_Masks PINT Register Masks
13836  * @{
13837  */
13838 
13839 /*! @name ISEL - Pin Interrupt Mode register */
13840 /*! @{ */
13841 
13842 #define PINT_ISEL_PMODE_MASK                     (0xFFU)
13843 #define PINT_ISEL_PMODE_SHIFT                    (0U)
13844 /*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt
13845  *    selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
13846  */
13847 #define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
13848 /*! @} */
13849 
13850 /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
13851 /*! @{ */
13852 
13853 #define PINT_IENR_ENRL_MASK                      (0xFFU)
13854 #define PINT_IENR_ENRL_SHIFT                     (0U)
13855 /*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the
13856  *    pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable
13857  *    rising edge or level interrupt.
13858  */
13859 #define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
13860 /*! @} */
13861 
13862 /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
13863 /*! @{ */
13864 
13865 #define PINT_SIENR_SETENRL_MASK                  (0xFFU)
13866 #define PINT_SIENR_SETENRL_SHIFT                 (0U)
13867 /*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n
13868  *    sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
13869  */
13870 #define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
13871 /*! @} */
13872 
13873 /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
13874 /*! @{ */
13875 
13876 #define PINT_CIENR_CENRL_MASK                    (0xFFU)
13877 #define PINT_CIENR_CENRL_SHIFT                   (0U)
13878 /*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit
13879  *    n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level
13880  *    interrupt.
13881  */
13882 #define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
13883 /*! @} */
13884 
13885 /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
13886 /*! @{ */
13887 
13888 #define PINT_IENF_ENAF_MASK                      (0xFFU)
13889 #define PINT_IENF_ENAF_SHIFT                     (0U)
13890 /*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.
13891  *    Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt
13892  *    or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active
13893  *    interrupt level HIGH.
13894  */
13895 #define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
13896 /*! @} */
13897 
13898 /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
13899 /*! @{ */
13900 
13901 #define PINT_SIENF_SETENAF_MASK                  (0xFFU)
13902 #define PINT_SIENF_SETENAF_SHIFT                 (0U)
13903 /*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n
13904  *    sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable
13905  *    falling edge interrupt.
13906  */
13907 #define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
13908 /*! @} */
13909 
13910 /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
13911 /*! @{ */
13912 
13913 #define PINT_CIENF_CENAF_MASK                    (0xFFU)
13914 #define PINT_CIENF_CENAF_SHIFT                   (0U)
13915 /*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n
13916  *    clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or
13917  *    falling edge interrupt disabled.
13918  */
13919 #define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
13920 /*! @} */
13921 
13922 /*! @name RISE - Pin interrupt rising edge register */
13923 /*! @{ */
13924 
13925 #define PINT_RISE_RDET_MASK                      (0xFFU)
13926 #define PINT_RISE_RDET_SHIFT                     (0U)
13927 /*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read
13928  *    0: No rising edge has been detected on this pin since Reset or the last time a one was written
13929  *    to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the
13930  *    last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
13931  */
13932 #define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
13933 /*! @} */
13934 
13935 /*! @name FALL - Pin interrupt falling edge register */
13936 /*! @{ */
13937 
13938 #define PINT_FALL_FDET_MASK                      (0xFFU)
13939 #define PINT_FALL_FDET_SHIFT                     (0U)
13940 /*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read
13941  *    0: No falling edge has been detected on this pin since Reset or the last time a one was
13942  *    written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or
13943  *    the last time a one was written to this bit. Write 1: clear falling edge detection for this
13944  *    pin.
13945  */
13946 #define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
13947 /*! @} */
13948 
13949 /*! @name IST - Pin interrupt status register */
13950 /*! @{ */
13951 
13952 #define PINT_IST_PSTAT_MASK                      (0xFFU)
13953 #define PINT_IST_PSTAT_SHIFT                     (0U)
13954 /*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts
13955  *    the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for
13956  *    this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this
13957  *    interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.
13958  *    Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
13959  */
13960 #define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
13961 /*! @} */
13962 
13963 /*! @name PMCTRL - Pattern match interrupt control register */
13964 /*! @{ */
13965 
13966 #define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
13967 #define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
13968 /*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
13969  *  0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
13970  *  0b1..Pattern match. Interrupts are driven in response to pattern matches.
13971  */
13972 #define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
13973 
13974 #define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
13975 #define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
13976 /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
13977  *  0b0..Disabled. RXEV output to the CPU is disabled.
13978  *  0b1..Enabled. RXEV output to the CPU is enabled.
13979  */
13980 #define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
13981 
13982 #define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
13983 #define PINT_PMCTRL_PMAT_SHIFT                   (24U)
13984 /*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field
13985  *    indicates that the corresponding product term is matched by the current state of the appropriate
13986  *    inputs.
13987  */
13988 #define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
13989 /*! @} */
13990 
13991 /*! @name PMSRC - Pattern match interrupt bit-slice source register */
13992 /*! @{ */
13993 
13994 #define PINT_PMSRC_SRC0_MASK                     (0x700U)
13995 #define PINT_PMSRC_SRC0_SHIFT                    (8U)
13996 /*! SRC0 - Selects the input source for bit slice 0
13997  *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
13998  *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
13999  *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
14000  *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
14001  *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
14002  *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
14003  *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
14004  *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
14005  */
14006 #define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
14007 
14008 #define PINT_PMSRC_SRC1_MASK                     (0x3800U)
14009 #define PINT_PMSRC_SRC1_SHIFT                    (11U)
14010 /*! SRC1 - Selects the input source for bit slice 1
14011  *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
14012  *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
14013  *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
14014  *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
14015  *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
14016  *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
14017  *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
14018  *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
14019  */
14020 #define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
14021 
14022 #define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
14023 #define PINT_PMSRC_SRC2_SHIFT                    (14U)
14024 /*! SRC2 - Selects the input source for bit slice 2
14025  *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
14026  *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
14027  *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
14028  *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
14029  *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
14030  *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
14031  *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
14032  *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
14033  */
14034 #define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
14035 
14036 #define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
14037 #define PINT_PMSRC_SRC3_SHIFT                    (17U)
14038 /*! SRC3 - Selects the input source for bit slice 3
14039  *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
14040  *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
14041  *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
14042  *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
14043  *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
14044  *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
14045  *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
14046  *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
14047  */
14048 #define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
14049 
14050 #define PINT_PMSRC_SRC4_MASK                     (0x700000U)
14051 #define PINT_PMSRC_SRC4_SHIFT                    (20U)
14052 /*! SRC4 - Selects the input source for bit slice 4
14053  *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
14054  *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
14055  *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
14056  *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
14057  *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
14058  *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
14059  *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
14060  *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
14061  */
14062 #define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
14063 
14064 #define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
14065 #define PINT_PMSRC_SRC5_SHIFT                    (23U)
14066 /*! SRC5 - Selects the input source for bit slice 5
14067  *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
14068  *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
14069  *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
14070  *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
14071  *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
14072  *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
14073  *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
14074  *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
14075  */
14076 #define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
14077 
14078 #define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
14079 #define PINT_PMSRC_SRC6_SHIFT                    (26U)
14080 /*! SRC6 - Selects the input source for bit slice 6
14081  *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
14082  *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
14083  *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
14084  *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
14085  *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
14086  *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
14087  *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
14088  *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
14089  */
14090 #define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
14091 
14092 #define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
14093 #define PINT_PMSRC_SRC7_SHIFT                    (29U)
14094 /*! SRC7 - Selects the input source for bit slice 7
14095  *  0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
14096  *  0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
14097  *  0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
14098  *  0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
14099  *  0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
14100  *  0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
14101  *  0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
14102  *  0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
14103  */
14104 #define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
14105 /*! @} */
14106 
14107 /*! @name PMCFG - Pattern match interrupt bit slice configuration register */
14108 /*! @{ */
14109 
14110 #define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
14111 #define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
14112 /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
14113  *  0b0..No effect. Slice 0 is not an endpoint.
14114  *  0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
14115  */
14116 #define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
14117 
14118 #define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
14119 #define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
14120 /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
14121  *  0b0..No effect. Slice 1 is not an endpoint.
14122  *  0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
14123  */
14124 #define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
14125 
14126 #define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
14127 #define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
14128 /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
14129  *  0b0..No effect. Slice 2 is not an endpoint.
14130  *  0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
14131  */
14132 #define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
14133 
14134 #define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
14135 #define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
14136 /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
14137  *  0b0..No effect. Slice 3 is not an endpoint.
14138  *  0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
14139  */
14140 #define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
14141 
14142 #define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
14143 #define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
14144 /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
14145  *  0b0..No effect. Slice 4 is not an endpoint.
14146  *  0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
14147  */
14148 #define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
14149 
14150 #define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
14151 #define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
14152 /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
14153  *  0b0..No effect. Slice 5 is not an endpoint.
14154  *  0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
14155  */
14156 #define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
14157 
14158 #define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
14159 #define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
14160 /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
14161  *  0b0..No effect. Slice 6 is not an endpoint.
14162  *  0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
14163  */
14164 #define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
14165 
14166 #define PINT_PMCFG_CFG0_MASK                     (0x700U)
14167 #define PINT_PMCFG_CFG0_SHIFT                    (8U)
14168 /*! CFG0 - Specifies the match contribution condition for bit slice 0.
14169  *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
14170  *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
14171  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14172  *         PMSRC registers are written to.
14173  *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
14174  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14175  *         PMSRC registers are written to.
14176  *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
14177  *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
14178  *         cleared when the PMCFG or the PMSRC registers are written to.
14179  *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
14180  *  0b101..Low level. Match occurs when there is a low level on the specified input.
14181  *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
14182  *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
14183  *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
14184  *         is cleared after one clock cycle.
14185  */
14186 #define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
14187 
14188 #define PINT_PMCFG_CFG1_MASK                     (0x3800U)
14189 #define PINT_PMCFG_CFG1_SHIFT                    (11U)
14190 /*! CFG1 - Specifies the match contribution condition for bit slice 1.
14191  *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
14192  *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
14193  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14194  *         PMSRC registers are written to.
14195  *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
14196  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14197  *         PMSRC registers are written to.
14198  *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
14199  *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
14200  *         cleared when the PMCFG or the PMSRC registers are written to.
14201  *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
14202  *  0b101..Low level. Match occurs when there is a low level on the specified input.
14203  *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
14204  *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
14205  *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
14206  *         is cleared after one clock cycle.
14207  */
14208 #define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
14209 
14210 #define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
14211 #define PINT_PMCFG_CFG2_SHIFT                    (14U)
14212 /*! CFG2 - Specifies the match contribution condition for bit slice 2.
14213  *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
14214  *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
14215  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14216  *         PMSRC registers are written to.
14217  *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
14218  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14219  *         PMSRC registers are written to.
14220  *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
14221  *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
14222  *         cleared when the PMCFG or the PMSRC registers are written to.
14223  *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
14224  *  0b101..Low level. Match occurs when there is a low level on the specified input.
14225  *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
14226  *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
14227  *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
14228  *         is cleared after one clock cycle.
14229  */
14230 #define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
14231 
14232 #define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
14233 #define PINT_PMCFG_CFG3_SHIFT                    (17U)
14234 /*! CFG3 - Specifies the match contribution condition for bit slice 3.
14235  *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
14236  *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
14237  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14238  *         PMSRC registers are written to.
14239  *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
14240  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14241  *         PMSRC registers are written to.
14242  *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
14243  *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
14244  *         cleared when the PMCFG or the PMSRC registers are written to.
14245  *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
14246  *  0b101..Low level. Match occurs when there is a low level on the specified input.
14247  *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
14248  *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
14249  *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
14250  *         is cleared after one clock cycle.
14251  */
14252 #define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
14253 
14254 #define PINT_PMCFG_CFG4_MASK                     (0x700000U)
14255 #define PINT_PMCFG_CFG4_SHIFT                    (20U)
14256 /*! CFG4 - Specifies the match contribution condition for bit slice 4.
14257  *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
14258  *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
14259  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14260  *         PMSRC registers are written to.
14261  *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
14262  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14263  *         PMSRC registers are written to.
14264  *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
14265  *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
14266  *         cleared when the PMCFG or the PMSRC registers are written to.
14267  *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
14268  *  0b101..Low level. Match occurs when there is a low level on the specified input.
14269  *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
14270  *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
14271  *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
14272  *         is cleared after one clock cycle.
14273  */
14274 #define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
14275 
14276 #define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
14277 #define PINT_PMCFG_CFG5_SHIFT                    (23U)
14278 /*! CFG5 - Specifies the match contribution condition for bit slice 5.
14279  *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
14280  *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
14281  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14282  *         PMSRC registers are written to.
14283  *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
14284  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14285  *         PMSRC registers are written to.
14286  *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
14287  *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
14288  *         cleared when the PMCFG or the PMSRC registers are written to.
14289  *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
14290  *  0b101..Low level. Match occurs when there is a low level on the specified input.
14291  *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
14292  *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
14293  *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
14294  *         is cleared after one clock cycle.
14295  */
14296 #define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
14297 
14298 #define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
14299 #define PINT_PMCFG_CFG6_SHIFT                    (26U)
14300 /*! CFG6 - Specifies the match contribution condition for bit slice 6.
14301  *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
14302  *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
14303  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14304  *         PMSRC registers are written to.
14305  *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
14306  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14307  *         PMSRC registers are written to.
14308  *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
14309  *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
14310  *         cleared when the PMCFG or the PMSRC registers are written to.
14311  *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
14312  *  0b101..Low level. Match occurs when there is a low level on the specified input.
14313  *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
14314  *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
14315  *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
14316  *         is cleared after one clock cycle.
14317  */
14318 #define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
14319 
14320 #define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
14321 #define PINT_PMCFG_CFG7_SHIFT                    (29U)
14322 /*! CFG7 - Specifies the match contribution condition for bit slice 7.
14323  *  0b000..Constant HIGH. This bit slice always contributes to a product term match.
14324  *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
14325  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14326  *         PMSRC registers are written to.
14327  *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
14328  *         time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
14329  *         PMSRC registers are written to.
14330  *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
14331  *         has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
14332  *         cleared when the PMCFG or the PMSRC registers are written to.
14333  *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
14334  *  0b101..Low level. Match occurs when there is a low level on the specified input.
14335  *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
14336  *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
14337  *         falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
14338  *         is cleared after one clock cycle.
14339  */
14340 #define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
14341 /*! @} */
14342 
14343 
14344 /*!
14345  * @}
14346  */ /* end of group PINT_Register_Masks */
14347 
14348 
14349 /* PINT - Peripheral instance base addresses */
14350 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
14351   /** Peripheral PINT base address */
14352   #define PINT_BASE                                (0x50004000u)
14353   /** Peripheral PINT base address */
14354   #define PINT_BASE_NS                             (0x40004000u)
14355   /** Peripheral PINT base pointer */
14356   #define PINT                                     ((PINT_Type *)PINT_BASE)
14357   /** Peripheral PINT base pointer */
14358   #define PINT_NS                                  ((PINT_Type *)PINT_BASE_NS)
14359   /** Peripheral SECPINT base address */
14360   #define SECPINT_BASE                             (0x50005000u)
14361   /** Peripheral SECPINT base address */
14362   #define SECPINT_BASE_NS                          (0x40005000u)
14363   /** Peripheral SECPINT base pointer */
14364   #define SECPINT                                  ((PINT_Type *)SECPINT_BASE)
14365   /** Peripheral SECPINT base pointer */
14366   #define SECPINT_NS                               ((PINT_Type *)SECPINT_BASE_NS)
14367   /** Array initializer of PINT peripheral base addresses */
14368   #define PINT_BASE_ADDRS                          { PINT_BASE, SECPINT_BASE }
14369   /** Array initializer of PINT peripheral base pointers */
14370   #define PINT_BASE_PTRS                           { PINT, SECPINT }
14371   /** Array initializer of PINT peripheral base addresses */
14372   #define PINT_BASE_ADDRS_NS                       { PINT_BASE_NS, SECPINT_BASE_NS }
14373   /** Array initializer of PINT peripheral base pointers */
14374   #define PINT_BASE_PTRS_NS                        { PINT_NS, SECPINT_NS }
14375 #else
14376   /** Peripheral PINT base address */
14377   #define PINT_BASE                                (0x40004000u)
14378   /** Peripheral PINT base pointer */
14379   #define PINT                                     ((PINT_Type *)PINT_BASE)
14380   /** Peripheral SECPINT base address */
14381   #define SECPINT_BASE                             (0x40005000u)
14382   /** Peripheral SECPINT base pointer */
14383   #define SECPINT                                  ((PINT_Type *)SECPINT_BASE)
14384   /** Array initializer of PINT peripheral base addresses */
14385   #define PINT_BASE_ADDRS                          { PINT_BASE, SECPINT_BASE }
14386   /** Array initializer of PINT peripheral base pointers */
14387   #define PINT_BASE_PTRS                           { PINT, SECPINT }
14388 #endif
14389 /** Interrupt vectors for the PINT peripheral type */
14390 #define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn }
14391 
14392 /*!
14393  * @}
14394  */ /* end of group PINT_Peripheral_Access_Layer */
14395 
14396 
14397 /* ----------------------------------------------------------------------------
14398    -- PLU Peripheral Access Layer
14399    ---------------------------------------------------------------------------- */
14400 
14401 /*!
14402  * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer
14403  * @{
14404  */
14405 
14406 /** PLU - Register Layout Typedef */
14407 typedef struct {
14408   struct {                                         /* offset: 0x0, array step: 0x20 */
14409     __IO uint32_t INP_MUX[5];                        /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */
14410          uint8_t RESERVED_0[12];
14411   } LUT[26];
14412        uint8_t RESERVED_0[1216];
14413   __IO uint32_t LUT_TRUTH[26];                     /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */
14414        uint8_t RESERVED_1[152];
14415   __I  uint32_t OUTPUTS;                           /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */
14416   __IO uint32_t WAKEINT_CTRL;                      /**< Wakeup interrupt control for PLU, offset: 0x904 */
14417        uint8_t RESERVED_2[760];
14418   __IO uint32_t OUTPUT_MUX[8];                     /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */
14419 } PLU_Type;
14420 
14421 /* ----------------------------------------------------------------------------
14422    -- PLU Register Masks
14423    ---------------------------------------------------------------------------- */
14424 
14425 /*!
14426  * @addtogroup PLU_Register_Masks PLU Register Masks
14427  * @{
14428  */
14429 
14430 /*! @name LUT_INP_MUX - LUTn input x MUX */
14431 /*! @{ */
14432 
14433 #define PLU_LUT_INP_MUX_LUTn_INPx_MASK           (0x3FU)
14434 #define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT          (0U)
14435 /*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot
14436  *    associated with the output from LUTn itself is tied low.
14437  *  0b000000..The PLU primary inputs 0.
14438  *  0b000001..The PLU primary inputs 1.
14439  *  0b000010..The PLU primary inputs 2.
14440  *  0b000011..The PLU primary inputs 3.
14441  *  0b000100..The PLU primary inputs 4.
14442  *  0b000101..The PLU primary inputs 5.
14443  *  0b000110..The output of LUT0.
14444  *  0b000111..The output of LUT1.
14445  *  0b001000..The output of LUT2.
14446  *  0b001001..The output of LUT3.
14447  *  0b001010..The output of LUT4.
14448  *  0b001011..The output of LUT5.
14449  *  0b001100..The output of LUT6.
14450  *  0b001101..The output of LUT7.
14451  *  0b001110..The output of LUT8.
14452  *  0b001111..The output of LUT9.
14453  *  0b010000..The output of LUT10.
14454  *  0b010001..The output of LUT11.
14455  *  0b010010..The output of LUT12.
14456  *  0b010011..The output of LUT13.
14457  *  0b010100..The output of LUT14.
14458  *  0b010101..The output of LUT15.
14459  *  0b010110..The output of LUT16.
14460  *  0b010111..The output of LUT17.
14461  *  0b011000..The output of LUT18.
14462  *  0b011001..The output of LUT19.
14463  *  0b011010..The output of LUT20.
14464  *  0b011011..The output of LUT21.
14465  *  0b011100..The output of LUT22.
14466  *  0b011101..The output of LUT23.
14467  *  0b011110..The output of LUT24.
14468  *  0b011111..The output of LUT25.
14469  *  0b100000..state(0).
14470  *  0b100001..state(1).
14471  *  0b100010..state(2).
14472  *  0b100011..state(3).
14473  */
14474 #define PLU_LUT_INP_MUX_LUTn_INPx(x)             (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK)
14475 /*! @} */
14476 
14477 /* The count of PLU_LUT_INP_MUX */
14478 #define PLU_LUT_INP_MUX_COUNT                    (26U)
14479 
14480 /* The count of PLU_LUT_INP_MUX */
14481 #define PLU_LUT_INP_MUX_COUNT2                   (5U)
14482 
14483 /*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */
14484 /*! @{ */
14485 
14486 #define PLU_LUT_TRUTH_LUTn_TRUTH_MASK            (0xFFFFFFFFU)
14487 #define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT           (0U)
14488 /*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25..
14489  */
14490 #define PLU_LUT_TRUTH_LUTn_TRUTH(x)              (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK)
14491 /*! @} */
14492 
14493 /* The count of PLU_LUT_TRUTH */
14494 #define PLU_LUT_TRUTH_COUNT                      (26U)
14495 
14496 /*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */
14497 /*! @{ */
14498 
14499 #define PLU_OUTPUTS_OUTPUT_STATE_MASK            (0xFFU)
14500 #define PLU_OUTPUTS_OUTPUT_STATE_SHIFT           (0U)
14501 /*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs..
14502  */
14503 #define PLU_OUTPUTS_OUTPUT_STATE(x)              (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK)
14504 /*! @} */
14505 
14506 /*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */
14507 /*! @{ */
14508 
14509 #define PLU_WAKEINT_CTRL_MASK_MASK               (0xFFU)
14510 #define PLU_WAKEINT_CTRL_MASK_SHIFT              (0U)
14511 /*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt)
14512  */
14513 #define PLU_WAKEINT_CTRL_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK)
14514 
14515 #define PLU_WAKEINT_CTRL_FILTER_MODE_MASK        (0x300U)
14516 #define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT       (8U)
14517 /*! FILTER_MODE - control input of the PLU, add filtering for glitch.
14518  *  0b00..Bypass mode.
14519  *  0b01..Filter 1 clock period.
14520  *  0b10..Filter 2 clock period.
14521  *  0b11..Filter 3 clock period.
14522  */
14523 #define PLU_WAKEINT_CTRL_FILTER_MODE(x)          (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK)
14524 
14525 #define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK      (0xC00U)
14526 #define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT     (10U)
14527 /*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel.
14528  *  0b00..Selects the 1 MHz low-power oscillator as the filter clock.
14529  *  0b01..Selects the 12 Mhz FRO as the filter clock.
14530  *  0b10..Selects a third filter clock source, if provided.
14531  *  0b11..Reserved.
14532  */
14533 #define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x)        (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK)
14534 
14535 #define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK       (0x1000U)
14536 #define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT      (12U)
14537 /*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR
14538  */
14539 #define PLU_WAKEINT_CTRL_LATCH_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK)
14540 
14541 #define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK         (0x2000U)
14542 #define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT        (13U)
14543 /*! INTR_CLEAR - Write to clear wakeint_latched
14544  */
14545 #define PLU_WAKEINT_CTRL_INTR_CLEAR(x)           (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)
14546 /*! @} */
14547 
14548 /*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */
14549 /*! @{ */
14550 
14551 #define PLU_OUTPUT_MUX_OUTPUTn_MASK              (0x1FU)
14552 #define PLU_OUTPUT_MUX_OUTPUTn_SHIFT             (0U)
14553 /*! OUTPUTn - Selects the source to be connected to PLU Output 7.
14554  *  0b00000..The PLU output 0.
14555  *  0b00001..The PLU output 1.
14556  *  0b00010..The PLU output 2.
14557  *  0b00011..The PLU output 3.
14558  *  0b00100..The PLU output 4.
14559  *  0b00101..The PLU output 5.
14560  *  0b00110..The PLU output 6.
14561  *  0b00111..The PLU output 7.
14562  *  0b01000..The PLU output 8.
14563  *  0b01001..The PLU output 9.
14564  *  0b01010..The PLU output 10.
14565  *  0b01011..The PLU output 11.
14566  *  0b01100..The PLU output 12.
14567  *  0b01101..The PLU output 13.
14568  *  0b01110..The PLU output 14.
14569  *  0b01111..The PLU output 15.
14570  *  0b10000..The PLU output 16.
14571  *  0b10001..The PLU output 17.
14572  *  0b10010..The PLU output 18.
14573  *  0b10011..The PLU output 19.
14574  *  0b10100..The PLU output 20.
14575  *  0b10101..The PLU output 21.
14576  *  0b10110..The PLU output 22.
14577  *  0b10111..The PLU output 23.
14578  *  0b11000..The PLU output 24.
14579  *  0b11001..The PLU output 25.
14580  *  0b11010..state(0).
14581  *  0b11011..state(1).
14582  *  0b11100..state(2).
14583  *  0b11101..state(3).
14584  */
14585 #define PLU_OUTPUT_MUX_OUTPUTn(x)                (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK)
14586 /*! @} */
14587 
14588 /* The count of PLU_OUTPUT_MUX */
14589 #define PLU_OUTPUT_MUX_COUNT                     (8U)
14590 
14591 
14592 /*!
14593  * @}
14594  */ /* end of group PLU_Register_Masks */
14595 
14596 
14597 /* PLU - Peripheral instance base addresses */
14598 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
14599   /** Peripheral PLU base address */
14600   #define PLU_BASE                                 (0x5003D000u)
14601   /** Peripheral PLU base address */
14602   #define PLU_BASE_NS                              (0x4003D000u)
14603   /** Peripheral PLU base pointer */
14604   #define PLU                                      ((PLU_Type *)PLU_BASE)
14605   /** Peripheral PLU base pointer */
14606   #define PLU_NS                                   ((PLU_Type *)PLU_BASE_NS)
14607   /** Array initializer of PLU peripheral base addresses */
14608   #define PLU_BASE_ADDRS                           { PLU_BASE }
14609   /** Array initializer of PLU peripheral base pointers */
14610   #define PLU_BASE_PTRS                            { PLU }
14611   /** Array initializer of PLU peripheral base addresses */
14612   #define PLU_BASE_ADDRS_NS                        { PLU_BASE_NS }
14613   /** Array initializer of PLU peripheral base pointers */
14614   #define PLU_BASE_PTRS_NS                         { PLU_NS }
14615 #else
14616   /** Peripheral PLU base address */
14617   #define PLU_BASE                                 (0x4003D000u)
14618   /** Peripheral PLU base pointer */
14619   #define PLU                                      ((PLU_Type *)PLU_BASE)
14620   /** Array initializer of PLU peripheral base addresses */
14621   #define PLU_BASE_ADDRS                           { PLU_BASE }
14622   /** Array initializer of PLU peripheral base pointers */
14623   #define PLU_BASE_PTRS                            { PLU }
14624 #endif
14625 
14626 /*!
14627  * @}
14628  */ /* end of group PLU_Peripheral_Access_Layer */
14629 
14630 
14631 /* ----------------------------------------------------------------------------
14632    -- PMC Peripheral Access Layer
14633    ---------------------------------------------------------------------------- */
14634 
14635 /*!
14636  * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
14637  * @{
14638  */
14639 
14640 /** PMC - Register Layout Typedef */
14641 typedef struct {
14642        uint8_t RESERVED_0[4];
14643   __I  uint32_t STATUS;                            /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */
14644   __IO uint32_t RESETCTRL;                         /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */
14645        uint8_t RESERVED_1[4];
14646   __IO uint32_t DCDC0;                             /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */
14647   __IO uint32_t DCDC1;                             /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */
14648        uint8_t RESERVED_2[4];
14649   __IO uint32_t LDOPMU;                            /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */
14650        uint8_t RESERVED_3[16];
14651   __IO uint32_t BODVBAT;                           /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */
14652        uint8_t RESERVED_4[12];
14653   __IO uint32_t REFFASTWKUP;                       /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */
14654        uint8_t RESERVED_5[8];
14655   __IO uint32_t XTAL32K;                           /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */
14656   __IO uint32_t COMP;                              /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */
14657        uint8_t RESERVED_6[16];
14658   __IO uint32_t WAKEUPIOCTRL;                      /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */
14659   __IO uint32_t WAKEIOCAUSE;                       /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */
14660        uint8_t RESERVED_7[8];
14661   __IO uint32_t STATUSCLK;                         /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */
14662        uint8_t RESERVED_8[12];
14663   __IO uint32_t AOREG1;                            /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */
14664        uint8_t RESERVED_9[8];
14665   __IO uint32_t MISCCTRL;                          /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */
14666        uint8_t RESERVED_10[4];
14667   __IO uint32_t RTCOSC32K;                         /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */
14668   __IO uint32_t OSTIMERr;                          /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'OSTIMER' */
14669        uint8_t RESERVED_11[24];
14670   __IO uint32_t PDRUNCFG0;                         /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */
14671        uint8_t RESERVED_12[4];
14672   __O  uint32_t PDRUNCFGSET0;                      /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */
14673        uint8_t RESERVED_13[4];
14674   __O  uint32_t PDRUNCFGCLR0;                      /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */
14675        uint8_t RESERVED_14[8];
14676   __IO uint32_t SRAMCTRL;                          /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */
14677 } PMC_Type;
14678 
14679 /* ----------------------------------------------------------------------------
14680    -- PMC Register Masks
14681    ---------------------------------------------------------------------------- */
14682 
14683 /*!
14684  * @addtogroup PMC_Register_Masks PMC Register Masks
14685  * @{
14686  */
14687 
14688 /*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */
14689 /*! @{ */
14690 
14691 #define PMC_STATUS_BOOTMODE_MASK                 (0xC0000U)
14692 #define PMC_STATUS_BOOTMODE_SHIFT                (18U)
14693 /*! BOOTMODE - Latest IC Boot cause:.
14694  *  0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset).
14695  *  0b01..Latest IC boot was from DEEP SLEEP low power mode.
14696  *  0b10..Latest IC boot was from POWER DOWN low power mode.
14697  *  0b11..Latest IC boot was from DEEP POWER DOWN low power mode.
14698  */
14699 #define PMC_STATUS_BOOTMODE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK)
14700 /*! @} */
14701 
14702 /*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
14703 /*! @{ */
14704 
14705 #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK  (0x1U)
14706 #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U)
14707 /*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer).
14708  *  0b0..Reset event from DEEP POWER DOWN mode is disable.
14709  *  0b1..Reset event from DEEP POWER DOWN mode is enable.
14710  */
14711 #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x)    (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK)
14712 
14713 #define PMC_RESETCTRL_BODVBATRESETENABLE_MASK    (0x2U)
14714 #define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT   (1U)
14715 /*! BODVBATRESETENABLE - BOD VBAT reset enable.
14716  *  0b0..BOD VBAT reset is disable.
14717  *  0b1..BOD VBAT reset is enable.
14718  */
14719 #define PMC_RESETCTRL_BODVBATRESETENABLE(x)      (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)
14720 
14721 #define PMC_RESETCTRL_BODCORERESETENABLE_MASK    (0x4U)
14722 #define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT   (2U)
14723 /*! BODCORERESETENABLE - BOD CORE reset enable.
14724  *  0b0..BOD CORE reset is disable.
14725  *  0b1..BOD CORE reset is enable.
14726  */
14727 #define PMC_RESETCTRL_BODCORERESETENABLE(x)      (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK)
14728 
14729 #define PMC_RESETCTRL_SWRRESETENABLE_MASK        (0x8U)
14730 #define PMC_RESETCTRL_SWRRESETENABLE_SHIFT       (3U)
14731 /*! SWRRESETENABLE - Software reset enable.
14732  *  0b0..Software reset is disable.
14733  *  0b1..Software reset is enable.
14734  */
14735 #define PMC_RESETCTRL_SWRRESETENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK)
14736 /*! @} */
14737 
14738 /*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
14739 /*! @{ */
14740 
14741 #define PMC_DCDC0_RC_MASK                        (0x3FU)
14742 #define PMC_DCDC0_RC_SHIFT                       (0U)
14743 /*! RC - Constant On-Time calibration.
14744  */
14745 #define PMC_DCDC0_RC(x)                          (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK)
14746 
14747 #define PMC_DCDC0_ICOMP_MASK                     (0xC0U)
14748 #define PMC_DCDC0_ICOMP_SHIFT                    (6U)
14749 /*! ICOMP - Select the type of ZCD comparator.
14750  */
14751 #define PMC_DCDC0_ICOMP(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK)
14752 
14753 #define PMC_DCDC0_ISEL_MASK                      (0x300U)
14754 #define PMC_DCDC0_ISEL_SHIFT                     (8U)
14755 /*! ISEL - Alter Internal biasing currents.
14756  */
14757 #define PMC_DCDC0_ISEL(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK)
14758 
14759 #define PMC_DCDC0_ICENABLE_MASK                  (0x400U)
14760 #define PMC_DCDC0_ICENABLE_SHIFT                 (10U)
14761 /*! ICENABLE - Selection of auto scaling of COT period with variations in VDD.
14762  */
14763 #define PMC_DCDC0_ICENABLE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK)
14764 
14765 #define PMC_DCDC0_TMOS_MASK                      (0xF800U)
14766 #define PMC_DCDC0_TMOS_SHIFT                     (11U)
14767 /*! TMOS - One-shot generator reference current trimming signal.
14768  */
14769 #define PMC_DCDC0_TMOS(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK)
14770 
14771 #define PMC_DCDC0_DISABLEISENSE_MASK             (0x10000U)
14772 #define PMC_DCDC0_DISABLEISENSE_SHIFT            (16U)
14773 /*! DISABLEISENSE - Disable Current sensing.
14774  */
14775 #define PMC_DCDC0_DISABLEISENSE(x)               (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK)
14776 
14777 #define PMC_DCDC0_VOUT_MASK                      (0x1E0000U)
14778 #define PMC_DCDC0_VOUT_SHIFT                     (17U)
14779 /*! VOUT - Set output regulation voltage.
14780  *  0b0000..0.95 V.
14781  *  0b0001..0.975 V.
14782  *  0b0010..1 V.
14783  *  0b0011..1.025 V.
14784  *  0b0100..1.05 V.
14785  *  0b0101..1.075 V.
14786  *  0b0110..1.1 V.
14787  *  0b0111..1.125 V.
14788  *  0b1000..1.15 V.
14789  *  0b1001..1.175 V.
14790  *  0b1010..1.2 V.
14791  */
14792 #define PMC_DCDC0_VOUT(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK)
14793 
14794 #define PMC_DCDC0_SLICINGENABLE_MASK             (0x200000U)
14795 #define PMC_DCDC0_SLICINGENABLE_SHIFT            (21U)
14796 /*! SLICINGENABLE - Enable staggered switching of power switches.
14797  */
14798 #define PMC_DCDC0_SLICINGENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK)
14799 
14800 #define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK       (0x400000U)
14801 #define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT      (22U)
14802 /*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time.
14803  */
14804 #define PMC_DCDC0_INDUCTORCLAMPENABLE(x)         (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK)
14805 
14806 #define PMC_DCDC0_VOUT_PWD_MASK                  (0x7800000U)
14807 #define PMC_DCDC0_VOUT_PWD_SHIFT                 (23U)
14808 /*! VOUT_PWD - Set output regulation voltage during Deep Sleep.
14809  */
14810 #define PMC_DCDC0_VOUT_PWD(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK)
14811 /*! @} */
14812 
14813 /*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
14814 /*! @{ */
14815 
14816 #define PMC_DCDC1_RTRIMOFFET_MASK                (0xFU)
14817 #define PMC_DCDC1_RTRIMOFFET_SHIFT               (0U)
14818 /*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator.
14819  */
14820 #define PMC_DCDC1_RTRIMOFFET(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK)
14821 
14822 #define PMC_DCDC1_RSENSETRIM_MASK                (0xF0U)
14823 #define PMC_DCDC1_RSENSETRIM_SHIFT               (4U)
14824 /*! RSENSETRIM - Adjust Max inductor peak current limiting.
14825  */
14826 #define PMC_DCDC1_RSENSETRIM(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK)
14827 
14828 #define PMC_DCDC1_DTESTENABLE_MASK               (0x100U)
14829 #define PMC_DCDC1_DTESTENABLE_SHIFT              (8U)
14830 /*! DTESTENABLE - Enable Digital test signals.
14831  */
14832 #define PMC_DCDC1_DTESTENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK)
14833 
14834 #define PMC_DCDC1_SETCURVE_MASK                  (0x600U)
14835 #define PMC_DCDC1_SETCURVE_SHIFT                 (9U)
14836 /*! SETCURVE - Bandgap calibration parameter.
14837  */
14838 #define PMC_DCDC1_SETCURVE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK)
14839 
14840 #define PMC_DCDC1_SETDC_MASK                     (0x7800U)
14841 #define PMC_DCDC1_SETDC_SHIFT                    (11U)
14842 /*! SETDC - Bandgap calibration parameter.
14843  */
14844 #define PMC_DCDC1_SETDC(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK)
14845 
14846 #define PMC_DCDC1_DTESTSEL_MASK                  (0x38000U)
14847 #define PMC_DCDC1_DTESTSEL_SHIFT                 (15U)
14848 /*! DTESTSEL - Select the output signal for test.
14849  */
14850 #define PMC_DCDC1_DTESTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK)
14851 
14852 #define PMC_DCDC1_ISCALEENABLE_MASK              (0x40000U)
14853 #define PMC_DCDC1_ISCALEENABLE_SHIFT             (18U)
14854 /*! ISCALEENABLE - Modify COT behavior.
14855  */
14856 #define PMC_DCDC1_ISCALEENABLE(x)                (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK)
14857 
14858 #define PMC_DCDC1_FORCEBYPASS_MASK               (0x80000U)
14859 #define PMC_DCDC1_FORCEBYPASS_SHIFT              (19U)
14860 /*! FORCEBYPASS - Force bypass mode.
14861  */
14862 #define PMC_DCDC1_FORCEBYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK)
14863 
14864 #define PMC_DCDC1_TRIMAUTOCOT_MASK               (0xF00000U)
14865 #define PMC_DCDC1_TRIMAUTOCOT_SHIFT              (20U)
14866 /*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation.
14867  */
14868 #define PMC_DCDC1_TRIMAUTOCOT(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK)
14869 
14870 #define PMC_DCDC1_FORCEFULLCYCLE_MASK            (0x1000000U)
14871 #define PMC_DCDC1_FORCEFULLCYCLE_SHIFT           (24U)
14872 /*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle.
14873  */
14874 #define PMC_DCDC1_FORCEFULLCYCLE(x)              (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK)
14875 
14876 #define PMC_DCDC1_LCENABLE_MASK                  (0x2000000U)
14877 #define PMC_DCDC1_LCENABLE_SHIFT                 (25U)
14878 /*! LCENABLE - Change the range of the peak detector of current inside the inductor.
14879  */
14880 #define PMC_DCDC1_LCENABLE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK)
14881 
14882 #define PMC_DCDC1_TOFF_MASK                      (0x7C000000U)
14883 #define PMC_DCDC1_TOFF_SHIFT                     (26U)
14884 /*! TOFF - Constant Off-Time calibration input.
14885  */
14886 #define PMC_DCDC1_TOFF(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK)
14887 
14888 #define PMC_DCDC1_TOFFENABLE_MASK                (0x80000000U)
14889 #define PMC_DCDC1_TOFFENABLE_SHIFT               (31U)
14890 /*! TOFFENABLE - Enable Constant Off-Time feature.
14891  */
14892 #define PMC_DCDC1_TOFFENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK)
14893 /*! @} */
14894 
14895 /*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
14896 /*! @{ */
14897 
14898 #define PMC_LDOPMU_VADJ_MASK                     (0x1FU)
14899 #define PMC_LDOPMU_VADJ_SHIFT                    (0U)
14900 /*! VADJ - Sets the Always-On domain LDO output level.
14901  *  0b00000..1.22 V.
14902  *  0b00001..0.7 V.
14903  *  0b00010..0.725 V.
14904  *  0b00011..0.75 V.
14905  *  0b00100..0.775 V.
14906  *  0b00101..0.8 V.
14907  *  0b00110..0.825 V.
14908  *  0b00111..0.85 V.
14909  *  0b01000..0.875 V.
14910  *  0b01001..0.9 V.
14911  *  0b01010..0.96 V.
14912  *  0b01011..0.97 V.
14913  *  0b01100..0.98 V.
14914  *  0b01101..0.99 V.
14915  *  0b01110..1 V.
14916  *  0b01111..1.01 V.
14917  *  0b10000..1.02 V.
14918  *  0b10001..1.03 V.
14919  *  0b10010..1.04 V.
14920  *  0b10011..1.05 V.
14921  *  0b10100..1.06 V.
14922  *  0b10101..1.07 V.
14923  *  0b10110..1.08 V.
14924  *  0b10111..1.09 V.
14925  *  0b11000..1.1 V.
14926  *  0b11001..1.11 V.
14927  *  0b11010..1.12 V.
14928  *  0b11011..1.13 V.
14929  *  0b11100..1.14 V.
14930  *  0b11101..1.15 V.
14931  *  0b11110..1.16 V.
14932  *  0b11111..1.22 V.
14933  */
14934 #define PMC_LDOPMU_VADJ(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK)
14935 
14936 #define PMC_LDOPMU_VADJ_PWD_MASK                 (0x3E0U)
14937 #define PMC_LDOPMU_VADJ_PWD_SHIFT                (5U)
14938 /*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes.
14939  */
14940 #define PMC_LDOPMU_VADJ_PWD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK)
14941 
14942 #define PMC_LDOPMU_VADJ_BOOST_MASK               (0x7C00U)
14943 #define PMC_LDOPMU_VADJ_BOOST_SHIFT              (10U)
14944 /*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level.
14945  */
14946 #define PMC_LDOPMU_VADJ_BOOST(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK)
14947 
14948 #define PMC_LDOPMU_VADJ_BOOST_PWD_MASK           (0xF8000U)
14949 #define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT          (15U)
14950 /*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes.
14951  */
14952 #define PMC_LDOPMU_VADJ_BOOST_PWD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK)
14953 
14954 #define PMC_LDOPMU_BOOST_ENA_MASK                (0x1000000U)
14955 #define PMC_LDOPMU_BOOST_ENA_SHIFT               (24U)
14956 /*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode.
14957  *  0b0..LDO AO Boost Mode is disable.
14958  *  0b1..LDO AO Boost Mode is enable.
14959  */
14960 #define PMC_LDOPMU_BOOST_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK)
14961 
14962 #define PMC_LDOPMU_BOOST_ENA_PWD_MASK            (0x2000000U)
14963 #define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT           (25U)
14964 /*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN).
14965  *  0b0..LDO AO Boost Mode is disable.
14966  *  0b1..LDO AO Boost Mode is enable.
14967  */
14968 #define PMC_LDOPMU_BOOST_ENA_PWD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK)
14969 /*! @} */
14970 
14971 /*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */
14972 /*! @{ */
14973 
14974 #define PMC_BODVBAT_TRIGLVL_MASK                 (0x1FU)
14975 #define PMC_BODVBAT_TRIGLVL_SHIFT                (0U)
14976 /*! TRIGLVL - BoD trigger level.
14977  *  0b00000..1.00 V.
14978  *  0b00001..1.10 V.
14979  *  0b00010..1.20 V.
14980  *  0b00011..1.30 V.
14981  *  0b00100..1.40 V.
14982  *  0b00101..1.50 V.
14983  *  0b00110..1.60 V.
14984  *  0b00111..1.65 V.
14985  *  0b01000..1.70 V.
14986  *  0b01001..1.75 V.
14987  *  0b01010..1.80 V.
14988  *  0b01011..1.90 V.
14989  *  0b01100..2.00 V.
14990  *  0b01101..2.10 V.
14991  *  0b01110..2.20 V.
14992  *  0b01111..2.30 V.
14993  *  0b10000..2.40 V.
14994  *  0b10001..2.50 V.
14995  *  0b10010..2.60 V.
14996  *  0b10011..2.70 V.
14997  *  0b10100..2.806 V.
14998  *  0b10101..2.90 V.
14999  *  0b10110..3.00 V.
15000  *  0b10111..3.10 V.
15001  *  0b11000..3.20 V.
15002  *  0b11001..3.30 V.
15003  *  0b11010..3.30 V.
15004  *  0b11011..3.30 V.
15005  *  0b11100..3.30 V.
15006  *  0b11101..3.30 V.
15007  *  0b11110..3.30 V.
15008  *  0b11111..3.30 V.
15009  */
15010 #define PMC_BODVBAT_TRIGLVL(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK)
15011 
15012 #define PMC_BODVBAT_HYST_MASK                    (0x60U)
15013 #define PMC_BODVBAT_HYST_SHIFT                   (5U)
15014 /*! HYST - BoD Hysteresis control.
15015  *  0b00..25 mV.
15016  *  0b01..50 mV.
15017  *  0b10..75 mV.
15018  *  0b11..100 mV.
15019  */
15020 #define PMC_BODVBAT_HYST(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK)
15021 /*! @} */
15022 
15023 /*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */
15024 /*! @{ */
15025 
15026 #define PMC_REFFASTWKUP_LPWKUP_MASK              (0x1U)
15027 #define PMC_REFFASTWKUP_LPWKUP_SHIFT             (0U)
15028 /*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): .
15029  *  0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode.
15030  *  0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode.
15031  */
15032 #define PMC_REFFASTWKUP_LPWKUP(x)                (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK)
15033 
15034 #define PMC_REFFASTWKUP_HWWKUP_MASK              (0x2U)
15035 #define PMC_REFFASTWKUP_HWWKUP_SHIFT             (1U)
15036 /*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: .
15037  *  0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset.
15038  *  0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset.
15039  */
15040 #define PMC_REFFASTWKUP_HWWKUP(x)                (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK)
15041 /*! @} */
15042 
15043 /*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */
15044 /*! @{ */
15045 
15046 #define PMC_XTAL32K_IREF_MASK                    (0x6U)
15047 #define PMC_XTAL32K_IREF_SHIFT                   (1U)
15048 /*! IREF - reference output current selection inputs.
15049  */
15050 #define PMC_XTAL32K_IREF(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK)
15051 
15052 #define PMC_XTAL32K_TEST_MASK                    (0x8U)
15053 #define PMC_XTAL32K_TEST_SHIFT                   (3U)
15054 /*! TEST - Oscillator Test Mode.
15055  */
15056 #define PMC_XTAL32K_TEST(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK)
15057 
15058 #define PMC_XTAL32K_IBIAS_MASK                   (0x30U)
15059 #define PMC_XTAL32K_IBIAS_SHIFT                  (4U)
15060 /*! IBIAS - bias current selection inputs.
15061  */
15062 #define PMC_XTAL32K_IBIAS(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK)
15063 
15064 #define PMC_XTAL32K_AMPL_MASK                    (0xC0U)
15065 #define PMC_XTAL32K_AMPL_SHIFT                   (6U)
15066 /*! AMPL - oscillator amplitude selection inputs.
15067  */
15068 #define PMC_XTAL32K_AMPL(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK)
15069 
15070 #define PMC_XTAL32K_CAPBANKIN_MASK               (0x7F00U)
15071 #define PMC_XTAL32K_CAPBANKIN_SHIFT              (8U)
15072 /*! CAPBANKIN - Capa bank setting input.
15073  */
15074 #define PMC_XTAL32K_CAPBANKIN(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK)
15075 
15076 #define PMC_XTAL32K_CAPBANKOUT_MASK              (0x3F8000U)
15077 #define PMC_XTAL32K_CAPBANKOUT_SHIFT             (15U)
15078 /*! CAPBANKOUT - Capa bank setting output.
15079  */
15080 #define PMC_XTAL32K_CAPBANKOUT(x)                (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK)
15081 
15082 #define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK      (0x400000U)
15083 #define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT     (22U)
15084 /*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set.
15085  *  0b0..Sourced from CAPTESTSTART.
15086  *  0b1..Sourced from calibration.
15087  */
15088 #define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x)        (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK)
15089 
15090 #define PMC_XTAL32K_CAPTESTSTART_MASK            (0x800000U)
15091 #define PMC_XTAL32K_CAPTESTSTART_SHIFT           (23U)
15092 /*! CAPTESTSTART - Start test.
15093  */
15094 #define PMC_XTAL32K_CAPTESTSTART(x)              (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK)
15095 
15096 #define PMC_XTAL32K_CAPTESTENABLE_MASK           (0x1000000U)
15097 #define PMC_XTAL32K_CAPTESTENABLE_SHIFT          (24U)
15098 /*! CAPTESTENABLE - Enable signal for cap test.
15099  */
15100 #define PMC_XTAL32K_CAPTESTENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK)
15101 
15102 #define PMC_XTAL32K_CAPTESTOSCINSEL_MASK         (0x2000000U)
15103 #define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT        (25U)
15104 /*! CAPTESTOSCINSEL - Select the input for test.
15105  *  0b0..Oscillator output pin (osc_out).
15106  *  0b1..Oscillator input pin (osc_in).
15107  */
15108 #define PMC_XTAL32K_CAPTESTOSCINSEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK)
15109 /*! @} */
15110 
15111 /*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
15112 /*! @{ */
15113 
15114 #define PMC_COMP_HYST_MASK                       (0x2U)
15115 #define PMC_COMP_HYST_SHIFT                      (1U)
15116 /*! HYST - Hysteris when hyst = '1'.
15117  *  0b0..Hysteresis is disable.
15118  *  0b1..Hysteresis is enable.
15119  */
15120 #define PMC_COMP_HYST(x)                         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK)
15121 
15122 #define PMC_COMP_VREFINPUT_MASK                  (0x4U)
15123 #define PMC_COMP_VREFINPUT_SHIFT                 (2U)
15124 /*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder).
15125  *  0b0..Select internal VREF.
15126  *  0b1..Select VDDA.
15127  */
15128 #define PMC_COMP_VREFINPUT(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK)
15129 
15130 #define PMC_COMP_LOWPOWER_MASK                   (0x8U)
15131 #define PMC_COMP_LOWPOWER_SHIFT                  (3U)
15132 /*! LOWPOWER - Low power mode.
15133  *  0b0..High speed mode.
15134  *  0b1..Low power mode (Low speed).
15135  */
15136 #define PMC_COMP_LOWPOWER(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK)
15137 
15138 #define PMC_COMP_PMUX_MASK                       (0x70U)
15139 #define PMC_COMP_PMUX_SHIFT                      (4U)
15140 /*! PMUX - Control word for P multiplexer:.
15141  *  0b000..VREF (See fiedl VREFINPUT).
15142  *  0b001..Pin P0_0.
15143  *  0b010..Pin P0_9.
15144  *  0b011..Pin P0_18.
15145  *  0b100..Pin P1_14.
15146  *  0b101..Pin P2_23.
15147  */
15148 #define PMC_COMP_PMUX(x)                         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK)
15149 
15150 #define PMC_COMP_NMUX_MASK                       (0x380U)
15151 #define PMC_COMP_NMUX_SHIFT                      (7U)
15152 /*! NMUX - Control word for N multiplexer:.
15153  *  0b000..VREF (See field VREFINPUT).
15154  *  0b001..Pin P0_0.
15155  *  0b010..Pin P0_9.
15156  *  0b011..Pin P0_18.
15157  *  0b100..Pin P1_14.
15158  *  0b101..Pin P2_23.
15159  */
15160 #define PMC_COMP_NMUX(x)                         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK)
15161 
15162 #define PMC_COMP_VREF_MASK                       (0x7C00U)
15163 #define PMC_COMP_VREF_SHIFT                      (10U)
15164 /*! VREF - Control reference voltage step, per steps of (VREFINPUT/31).
15165  */
15166 #define PMC_COMP_VREF(x)                         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK)
15167 
15168 #define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK       (0x30000U)
15169 #define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT      (16U)
15170 /*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output.
15171  *  0b00..Bypass mode.
15172  *  0b01..Filter 1 clock period.
15173  *  0b10..Filter 2 clock period.
15174  *  0b11..Filter 3 clock period.
15175  */
15176 #define PMC_COMP_FILTERCGF_SAMPLEMODE(x)         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)
15177 
15178 #define PMC_COMP_FILTERCGF_CLKDIV_MASK           (0x1C0000U)
15179 #define PMC_COMP_FILTERCGF_CLKDIV_SHIFT          (18U)
15180 /*! FILTERCGF_CLKDIV - Filter Clock divider.
15181  *  0b000..Filter clock period duration equals 1 Analog Comparator clock period.
15182  *  0b001..Filter clock period duration equals 2 Analog Comparator clock period.
15183  *  0b010..Filter clock period duration equals 4 Analog Comparator clock period.
15184  *  0b011..Filter clock period duration equals 8 Analog Comparator clock period.
15185  *  0b100..Filter clock period duration equals 16 Analog Comparator clock period.
15186  *  0b101..Filter clock period duration equals 32 Analog Comparator clock period.
15187  *  0b110..Filter clock period duration equals 64 Analog Comparator clock period.
15188  *  0b111..Filter clock period duration equals 128 Analog Comparator clock period.
15189  */
15190 #define PMC_COMP_FILTERCGF_CLKDIV(x)             (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK)
15191 /*! @} */
15192 
15193 /*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */
15194 /*! @{ */
15195 
15196 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK  (0x1U)
15197 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U)
15198 /*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:.
15199  *  0b0..Rising edge detection is disable.
15200  *  0b1..Rising edge detection is enable.
15201  */
15202 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK)
15203 
15204 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U)
15205 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U)
15206 /*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:.
15207  *  0b0..Falling edge detection is disable.
15208  *  0b1..Falling edge detection is enable.
15209  */
15210 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK)
15211 
15212 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK  (0x4U)
15213 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U)
15214 /*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:.
15215  *  0b0..Rising edge detection is disable.
15216  *  0b1..Rising edge detection is enable.
15217  */
15218 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK)
15219 
15220 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U)
15221 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U)
15222 /*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:.
15223  *  0b0..Falling edge detection is disable.
15224  *  0b1..Falling edge detection is enable.
15225  */
15226 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK)
15227 
15228 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK  (0x10U)
15229 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U)
15230 /*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:.
15231  *  0b0..Rising edge detection is disable.
15232  *  0b1..Rising edge detection is enable.
15233  */
15234 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK)
15235 
15236 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U)
15237 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U)
15238 /*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:.
15239  *  0b0..Falling edge detection is disable.
15240  *  0b1..Falling edge detection is enable.
15241  */
15242 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK)
15243 
15244 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK  (0x40U)
15245 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U)
15246 /*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:.
15247  *  0b0..Rising edge detection is disable.
15248  *  0b1..Rising edge detection is enable.
15249  */
15250 #define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK)
15251 
15252 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U)
15253 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U)
15254 /*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:.
15255  *  0b0..Falling edge detection is disable.
15256  *  0b1..Falling edge detection is enable.
15257  */
15258 #define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK)
15259 
15260 #define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK        (0x100U)
15261 #define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT       (8U)
15262 /*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode
15263  */
15264 #define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x)          (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK)
15265 
15266 #define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK        (0x200U)
15267 #define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT       (9U)
15268 /*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode
15269  */
15270 #define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x)          (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK)
15271 
15272 #define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK        (0x400U)
15273 #define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT       (10U)
15274 /*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode
15275  */
15276 #define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x)          (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK)
15277 
15278 #define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK        (0x800U)
15279 #define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT       (11U)
15280 /*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode
15281  */
15282 #define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x)          (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK)
15283 /*! @} */
15284 
15285 /*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */
15286 /*! @{ */
15287 
15288 #define PMC_WAKEIOCAUSE_WAKEUP0_MASK             (0x1U)
15289 #define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT            (0U)
15290 /*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode.
15291  *  0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0.
15292  *  0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0.
15293  */
15294 #define PMC_WAKEIOCAUSE_WAKEUP0(x)               (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK)
15295 
15296 #define PMC_WAKEIOCAUSE_WAKEUP1_MASK             (0x2U)
15297 #define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT            (1U)
15298 /*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode.
15299  *  0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1.
15300  *  0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1.
15301  */
15302 #define PMC_WAKEIOCAUSE_WAKEUP1(x)               (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK)
15303 
15304 #define PMC_WAKEIOCAUSE_WAKEUP2_MASK             (0x4U)
15305 #define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT            (2U)
15306 /*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode.
15307  *  0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2.
15308  *  0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2.
15309  */
15310 #define PMC_WAKEIOCAUSE_WAKEUP2(x)               (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK)
15311 
15312 #define PMC_WAKEIOCAUSE_WAKEUP3_MASK             (0x8U)
15313 #define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT            (3U)
15314 /*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode.
15315  *  0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3.
15316  *  0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3.
15317  */
15318 #define PMC_WAKEIOCAUSE_WAKEUP3(x)               (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK)
15319 /*! @} */
15320 
15321 /*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */
15322 /*! @{ */
15323 
15324 #define PMC_STATUSCLK_XTAL32KOK_MASK             (0x1U)
15325 #define PMC_STATUSCLK_XTAL32KOK_SHIFT            (0U)
15326 /*! XTAL32KOK - XTAL oscillator 32 K OK signal.
15327  */
15328 #define PMC_STATUSCLK_XTAL32KOK(x)               (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK)
15329 
15330 #define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK     (0x4U)
15331 #define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT    (2U)
15332 /*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator.
15333  *  0b0..No oscillation failure has been detetced since the last time this bit has been cleared.
15334  *  0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.
15335  */
15336 #define PMC_STATUSCLK_XTAL32KOSCFAILURE(x)       (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK)
15337 /*! @} */
15338 
15339 /*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */
15340 /*! @{ */
15341 
15342 #define PMC_AOREG1_POR_MASK                      (0x10U)
15343 #define PMC_AOREG1_POR_SHIFT                     (4U)
15344 /*! POR - The last chip reset was caused by a Power On Reset.
15345  */
15346 #define PMC_AOREG1_POR(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK)
15347 
15348 #define PMC_AOREG1_PADRESET_MASK                 (0x20U)
15349 #define PMC_AOREG1_PADRESET_SHIFT                (5U)
15350 /*! PADRESET - The last chip reset was caused by a Pin Reset.
15351  */
15352 #define PMC_AOREG1_PADRESET(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK)
15353 
15354 #define PMC_AOREG1_BODRESET_MASK                 (0x40U)
15355 #define PMC_AOREG1_BODRESET_SHIFT                (6U)
15356 /*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD.
15357  */
15358 #define PMC_AOREG1_BODRESET(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK)
15359 
15360 #define PMC_AOREG1_SYSTEMRESET_MASK              (0x80U)
15361 #define PMC_AOREG1_SYSTEMRESET_SHIFT             (7U)
15362 /*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU.
15363  */
15364 #define PMC_AOREG1_SYSTEMRESET(x)                (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK)
15365 
15366 #define PMC_AOREG1_WDTRESET_MASK                 (0x100U)
15367 #define PMC_AOREG1_WDTRESET_SHIFT                (8U)
15368 /*! WDTRESET - The last chip reset was caused by the Watchdog Timer.
15369  */
15370 #define PMC_AOREG1_WDTRESET(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK)
15371 
15372 #define PMC_AOREG1_SWRRESET_MASK                 (0x200U)
15373 #define PMC_AOREG1_SWRRESET_SHIFT                (9U)
15374 /*! SWRRESET - The last chip reset was caused by a Software event.
15375  */
15376 #define PMC_AOREG1_SWRRESET(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK)
15377 
15378 #define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK        (0x400U)
15379 #define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT       (10U)
15380 /*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode.
15381  */
15382 #define PMC_AOREG1_DPDRESET_WAKEUPIO(x)          (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK)
15383 
15384 #define PMC_AOREG1_DPDRESET_RTC_MASK             (0x800U)
15385 #define PMC_AOREG1_DPDRESET_RTC_SHIFT            (11U)
15386 /*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode.
15387  */
15388 #define PMC_AOREG1_DPDRESET_RTC(x)               (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK)
15389 
15390 #define PMC_AOREG1_DPDRESET_OSTIMER_MASK         (0x1000U)
15391 #define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT        (12U)
15392 /*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode.
15393  */
15394 #define PMC_AOREG1_DPDRESET_OSTIMER(x)           (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK)
15395 
15396 #define PMC_AOREG1_BOOTERRORCOUNTER_MASK         (0xF0000U)
15397 #define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT        (16U)
15398 /*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter.
15399  */
15400 #define PMC_AOREG1_BOOTERRORCOUNTER(x)           (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK)
15401 /*! @} */
15402 
15403 /*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
15404 /*! @{ */
15405 
15406 #define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK        (0x1U)
15407 #define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT       (0U)
15408 /*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source.
15409  *  0b0..LDO DEEP Sleep uses Flash buffer biasing as reference.
15410  *  0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference.
15411  */
15412 #define PMC_MISCCTRL_LDODEEPSLEEPREF(x)          (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK)
15413 
15414 #define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK        (0x2U)
15415 #define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT       (1U)
15416 /*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode.
15417  *  0b0..LDO MEM High Z mode is disabled.
15418  *  0b1..LDO MEM High Z mode is enabled.
15419  */
15420 #define PMC_MISCCTRL_LDOMEMHIGHZMODE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK)
15421 
15422 #define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK       (0x4U)
15423 #define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT      (2U)
15424 #define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x)         (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK)
15425 
15426 #define PMC_MISCCTRL_MISCCTRL_3_8_MASK           (0xF8U)
15427 #define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT          (3U)
15428 /*! MISCCTRL_3_8 - Reserved.
15429  */
15430 #define PMC_MISCCTRL_MISCCTRL_3_8(x)             (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK)
15431 
15432 #define PMC_MISCCTRL_MODEWAKEUP0_MASK            (0x100U)
15433 #define PMC_MISCCTRL_MODEWAKEUP0_SHIFT           (8U)
15434 /*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode
15435  */
15436 #define PMC_MISCCTRL_MODEWAKEUP0(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK)
15437 
15438 #define PMC_MISCCTRL_MODEWAKEUP1_MASK            (0x200U)
15439 #define PMC_MISCCTRL_MODEWAKEUP1_SHIFT           (9U)
15440 /*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode
15441  */
15442 #define PMC_MISCCTRL_MODEWAKEUP1(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK)
15443 
15444 #define PMC_MISCCTRL_MODEWAKEUP2_MASK            (0x400U)
15445 #define PMC_MISCCTRL_MODEWAKEUP2_SHIFT           (10U)
15446 /*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode
15447  */
15448 #define PMC_MISCCTRL_MODEWAKEUP2(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK)
15449 
15450 #define PMC_MISCCTRL_MODEWAKEUP3_MASK            (0x800U)
15451 #define PMC_MISCCTRL_MODEWAKEUP3_SHIFT           (11U)
15452 /*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode
15453  */
15454 #define PMC_MISCCTRL_MODEWAKEUP3(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK)
15455 
15456 #define PMC_MISCCTRL_DISABLE_BLEED_MASK          (0x1000U)
15457 #define PMC_MISCCTRL_DISABLE_BLEED_SHIFT         (12U)
15458 /*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the
15459  *    Low Power Software only in DEEP SLEEP low power mode.
15460  *  0b0..LDO_MEM bleed current is enabled.
15461  *  0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared
15462  *       after wake up from Deep SLeep low power mode.
15463  */
15464 #define PMC_MISCCTRL_DISABLE_BLEED(x)            (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK)
15465 
15466 #define PMC_MISCCTRL_MISCCTRL_13_14_MASK         (0x6000U)
15467 #define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT        (13U)
15468 /*! MISCCTRL_13_14 - Reserved.
15469  */
15470 #define PMC_MISCCTRL_MISCCTRL_13_14(x)           (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK)
15471 
15472 #define PMC_MISCCTRL_WAKUPIO_RST_MASK            (0x8000U)
15473 #define PMC_MISCCTRL_WAKUPIO_RST_SHIFT           (15U)
15474 /*! WAKUPIO_RST - WAKEUP IO event detector reset control.
15475  *  0b1..Wakeup IO is reset.
15476  *  0b0..Wakeup IO is not reset.
15477  */
15478 #define PMC_MISCCTRL_WAKUPIO_RST(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK)
15479 /*! @} */
15480 
15481 /*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */
15482 /*! @{ */
15483 
15484 #define PMC_RTCOSC32K_SEL_MASK                   (0x1U)
15485 #define PMC_RTCOSC32K_SEL_SHIFT                  (0U)
15486 /*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) .
15487  *  0b0..FRO 32 KHz.
15488  *  0b1..XTAL 32KHz.
15489  */
15490 #define PMC_RTCOSC32K_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK)
15491 
15492 #define PMC_RTCOSC32K_CLK1KHZDIV_MASK            (0xEU)
15493 #define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT           (1U)
15494 /*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV.
15495  */
15496 #define PMC_RTCOSC32K_CLK1KHZDIV(x)              (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK)
15497 
15498 #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK   (0x8000U)
15499 #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT  (15U)
15500 /*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag.
15501  */
15502 #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x)     (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK)
15503 
15504 #define PMC_RTCOSC32K_CLK1HZDIV_MASK             (0x7FF0000U)
15505 #define PMC_RTCOSC32K_CLK1HZDIV_SHIFT            (16U)
15506 /*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV.
15507  */
15508 #define PMC_RTCOSC32K_CLK1HZDIV(x)               (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK)
15509 
15510 #define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK         (0x40000000U)
15511 #define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT        (30U)
15512 /*! CLK1HZDIVHALT - Halts the divider counter.
15513  */
15514 #define PMC_RTCOSC32K_CLK1HZDIVHALT(x)           (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK)
15515 
15516 #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK    (0x80000000U)
15517 #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT   (31U)
15518 /*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag.
15519  */
15520 #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x)      (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK)
15521 /*! @} */
15522 
15523 /*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */
15524 /*! @{ */
15525 
15526 #define PMC_OSTIMER_SOFTRESET_MASK               (0x1U)
15527 #define PMC_OSTIMER_SOFTRESET_SHIFT              (0U)
15528 /*! SOFTRESET - Active high reset.
15529  */
15530 #define PMC_OSTIMER_SOFTRESET(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK)
15531 
15532 #define PMC_OSTIMER_CLOCKENABLE_MASK             (0x2U)
15533 #define PMC_OSTIMER_CLOCKENABLE_SHIFT            (1U)
15534 /*! CLOCKENABLE - Enable OSTIMER 32 KHz clock.
15535  */
15536 #define PMC_OSTIMER_CLOCKENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK)
15537 
15538 #define PMC_OSTIMER_DPDWAKEUPENABLE_MASK         (0x4U)
15539 #define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT        (2U)
15540 /*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode).
15541  */
15542 #define PMC_OSTIMER_DPDWAKEUPENABLE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK)
15543 
15544 #define PMC_OSTIMER_OSC32KPD_MASK                (0x8U)
15545 #define PMC_OSTIMER_OSC32KPD_SHIFT               (3U)
15546 /*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K.
15547  */
15548 #define PMC_OSTIMER_OSC32KPD(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK)
15549 /*! @} */
15550 
15551 /*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
15552 /*! @{ */
15553 
15554 #define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK          (0x8U)
15555 #define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT         (3U)
15556 /*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD).
15557  *  0b0..BOD VBAT is powered.
15558  *  0b1..BOD VBAT is powered down.
15559  */
15560 #define PMC_PDRUNCFG0_PDEN_BODVBAT(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK)
15561 
15562 #define PMC_PDRUNCFG0_PDEN_FRO32K_MASK           (0x40U)
15563 #define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT          (6U)
15564 /*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz.
15565  *  0b0..FRO32KHz is powered.
15566  *  0b1..FRO32KHz is powered down.
15567  */
15568 #define PMC_PDRUNCFG0_PDEN_FRO32K(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)
15569 
15570 #define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK          (0x80U)
15571 #define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT         (7U)
15572 /*! PDEN_XTAL32K - Controls power to crystal 32 KHz.
15573  *  0b0..Crystal 32KHz is powered.
15574  *  0b1..Crystal 32KHz is powered down.
15575  */
15576 #define PMC_PDRUNCFG0_PDEN_XTAL32K(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)
15577 
15578 #define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK          (0x100U)
15579 #define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT         (8U)
15580 /*! PDEN_XTAL32M - Controls power to high speed crystal.
15581  *  0b0..High speed crystal is powered.
15582  *  0b1..High speed crystal is powered down.
15583  */
15584 #define PMC_PDRUNCFG0_PDEN_XTAL32M(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK)
15585 
15586 #define PMC_PDRUNCFG0_PDEN_PLL0_MASK             (0x200U)
15587 #define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT            (9U)
15588 /*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0).
15589  *  0b0..PLL0 is powered.
15590  *  0b1..PLL0 is powered down.
15591  */
15592 #define PMC_PDRUNCFG0_PDEN_PLL0(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK)
15593 
15594 #define PMC_PDRUNCFG0_PDEN_PLL1_MASK             (0x400U)
15595 #define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT            (10U)
15596 /*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1).
15597  *  0b0..PLL1 is powered.
15598  *  0b1..PLL1 is powered down.
15599  */
15600 #define PMC_PDRUNCFG0_PDEN_PLL1(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK)
15601 
15602 #define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK         (0x800U)
15603 #define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT        (11U)
15604 /*! PDEN_USBFSPHY - Controls power to USB Full Speed phy.
15605  *  0b0..USB Full Speed phy is powered.
15606  *  0b1..USB Full Speed phy is powered down.
15607  */
15608 #define PMC_PDRUNCFG0_PDEN_USBFSPHY(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK)
15609 
15610 #define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK         (0x1000U)
15611 #define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT        (12U)
15612 /*! PDEN_USBHSPHY - Controls power to USB High Speed Phy.
15613  *  0b0..USB HS phy is powered.
15614  *  0b1..USB HS phy is powered down.
15615  */
15616 #define PMC_PDRUNCFG0_PDEN_USBHSPHY(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK)
15617 
15618 #define PMC_PDRUNCFG0_PDEN_COMP_MASK             (0x2000U)
15619 #define PMC_PDRUNCFG0_PDEN_COMP_SHIFT            (13U)
15620 /*! PDEN_COMP - Controls power to Analog Comparator.
15621  *  0b0..Analog Comparator is powered.
15622  *  0b1..Analog Comparator is powered down.
15623  */
15624 #define PMC_PDRUNCFG0_PDEN_COMP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK)
15625 
15626 #define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK         (0x40000U)
15627 #define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT        (18U)
15628 /*! PDEN_LDOUSBHS - Controls power to USB high speed LDO.
15629  *  0b0..USB high speed LDO is powered.
15630  *  0b1..USB high speed LDO is powered down.
15631  */
15632 #define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK)
15633 
15634 #define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK          (0x80000U)
15635 #define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT         (19U)
15636 /*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS)
15637  *  0b0..auxiliary biasing is powered.
15638  *  0b1..auxiliary biasing is powered down.
15639  */
15640 #define PMC_PDRUNCFG0_PDEN_AUXBIAS(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK)
15641 
15642 #define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK         (0x100000U)
15643 #define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT        (20U)
15644 /*! PDEN_LDOXO32M - Controls power to high speed crystal LDO.
15645  *  0b0..High speed crystal LDO is powered.
15646  *  0b1..High speed crystal LDO is powered down.
15647  */
15648 #define PMC_PDRUNCFG0_PDEN_LDOXO32M(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK)
15649 
15650 #define PMC_PDRUNCFG0_PDEN_RNG_MASK              (0x400000U)
15651 #define PMC_PDRUNCFG0_PDEN_RNG_SHIFT             (22U)
15652 /*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources.
15653  *  0b0..TRNG clocks are powered.
15654  *  0b1..TRNG clocks are powered down.
15655  */
15656 #define PMC_PDRUNCFG0_PDEN_RNG(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK)
15657 
15658 #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK        (0x800000U)
15659 #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT       (23U)
15660 /*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module.
15661  *  0b0..PLL0 Sread spectrum module is powered.
15662  *  0b1..PLL0 Sread spectrum module is powered down.
15663  */
15664 #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK)
15665 /*! @} */
15666 
15667 /*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
15668 /*! @{ */
15669 
15670 #define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK       (0xFFFFFFFFU)
15671 #define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT      (0U)
15672 /*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
15673  */
15674 #define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK)
15675 /*! @} */
15676 
15677 /*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
15678 /*! @{ */
15679 
15680 #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK       (0xFFFFFFFFU)
15681 #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT      (0U)
15682 /*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
15683  */
15684 #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK)
15685 /*! @} */
15686 
15687 /*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */
15688 /*! @{ */
15689 
15690 #define PMC_SRAMCTRL_SMB_MASK                    (0x3U)
15691 #define PMC_SRAMCTRL_SMB_SHIFT                   (0U)
15692 /*! SMB - Source Biasing voltage.
15693  *  0b00..Low leakage.
15694  *  0b01..Medium leakage.
15695  *  0b10..Highest leakage.
15696  *  0b11..Disable.
15697  */
15698 #define PMC_SRAMCTRL_SMB(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK)
15699 
15700 #define PMC_SRAMCTRL_RM_MASK                     (0x1CU)
15701 #define PMC_SRAMCTRL_RM_SHIFT                    (2U)
15702 /*! RM - Read Margin control settings.
15703  */
15704 #define PMC_SRAMCTRL_RM(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK)
15705 
15706 #define PMC_SRAMCTRL_WM_MASK                     (0xE0U)
15707 #define PMC_SRAMCTRL_WM_SHIFT                    (5U)
15708 /*! WM - Write Margin control settings.
15709  */
15710 #define PMC_SRAMCTRL_WM(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK)
15711 
15712 #define PMC_SRAMCTRL_WRME_MASK                   (0x100U)
15713 #define PMC_SRAMCTRL_WRME_SHIFT                  (8U)
15714 /*! WRME - Write read margin enable.
15715  */
15716 #define PMC_SRAMCTRL_WRME(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK)
15717 /*! @} */
15718 
15719 
15720 /*!
15721  * @}
15722  */ /* end of group PMC_Register_Masks */
15723 
15724 
15725 /* PMC - Peripheral instance base addresses */
15726 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
15727   /** Peripheral PMC base address */
15728   #define PMC_BASE                                 (0x50020000u)
15729   /** Peripheral PMC base address */
15730   #define PMC_BASE_NS                              (0x40020000u)
15731   /** Peripheral PMC base pointer */
15732   #define PMC                                      ((PMC_Type *)PMC_BASE)
15733   /** Peripheral PMC base pointer */
15734   #define PMC_NS                                   ((PMC_Type *)PMC_BASE_NS)
15735   /** Array initializer of PMC peripheral base addresses */
15736   #define PMC_BASE_ADDRS                           { PMC_BASE }
15737   /** Array initializer of PMC peripheral base pointers */
15738   #define PMC_BASE_PTRS                            { PMC }
15739   /** Array initializer of PMC peripheral base addresses */
15740   #define PMC_BASE_ADDRS_NS                        { PMC_BASE_NS }
15741   /** Array initializer of PMC peripheral base pointers */
15742   #define PMC_BASE_PTRS_NS                         { PMC_NS }
15743 #else
15744   /** Peripheral PMC base address */
15745   #define PMC_BASE                                 (0x40020000u)
15746   /** Peripheral PMC base pointer */
15747   #define PMC                                      ((PMC_Type *)PMC_BASE)
15748   /** Array initializer of PMC peripheral base addresses */
15749   #define PMC_BASE_ADDRS                           { PMC_BASE }
15750   /** Array initializer of PMC peripheral base pointers */
15751   #define PMC_BASE_PTRS                            { PMC }
15752 #endif
15753 
15754 /*!
15755  * @}
15756  */ /* end of group PMC_Peripheral_Access_Layer */
15757 
15758 
15759 /* ----------------------------------------------------------------------------
15760    -- POWERQUAD Peripheral Access Layer
15761    ---------------------------------------------------------------------------- */
15762 
15763 /*!
15764  * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer
15765  * @{
15766  */
15767 
15768 /** POWERQUAD - Register Layout Typedef */
15769 typedef struct {
15770   __IO uint32_t OUTBASE;                           /**< Base address register for output region, offset: 0x0 */
15771   __IO uint32_t OUTFORMAT;                         /**< Output format, offset: 0x4 */
15772   __IO uint32_t TMPBASE;                           /**< Base address register for temp region, offset: 0x8 */
15773   __IO uint32_t TMPFORMAT;                         /**< Temp format, offset: 0xC */
15774   __IO uint32_t INABASE;                           /**< Base address register for input A region, offset: 0x10 */
15775   __IO uint32_t INAFORMAT;                         /**< Input A format, offset: 0x14 */
15776   __IO uint32_t INBBASE;                           /**< Base address register for input B region, offset: 0x18 */
15777   __IO uint32_t INBFORMAT;                         /**< Input B format, offset: 0x1C */
15778        uint8_t RESERVED_0[224];
15779   __IO uint32_t CONTROL;                           /**< PowerQuad Control register, offset: 0x100 */
15780   __IO uint32_t LENGTH;                            /**< Length register, offset: 0x104 */
15781   __IO uint32_t CPPRE;                             /**< Pre-scale register, offset: 0x108 */
15782   __IO uint32_t MISC;                              /**< Misc register, offset: 0x10C */
15783   __IO uint32_t CURSORY;                           /**< Cursory register, offset: 0x110 */
15784        uint8_t RESERVED_1[108];
15785   __IO uint32_t CORDIC_X;                          /**< Cordic input X register, offset: 0x180 */
15786   __IO uint32_t CORDIC_Y;                          /**< Cordic input Y register, offset: 0x184 */
15787   __IO uint32_t CORDIC_Z;                          /**< Cordic input Z register, offset: 0x188 */
15788   __IO uint32_t ERRSTAT;                           /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */
15789   __IO uint32_t INTREN;                            /**< INTERRUPT enable register, offset: 0x190 */
15790   __IO uint32_t EVENTEN;                           /**< Event Enable register, offset: 0x194 */
15791   __IO uint32_t INTRSTAT;                          /**< INTERRUPT STATUS register, offset: 0x198 */
15792        uint8_t RESERVED_2[100];
15793   __IO uint32_t GPREG[16];                         /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */
15794   __IO uint32_t COMPREG[8];                        /**< Compute register bank, array offset: 0x240, array step: 0x4 */
15795 } POWERQUAD_Type;
15796 
15797 /* ----------------------------------------------------------------------------
15798    -- POWERQUAD Register Masks
15799    ---------------------------------------------------------------------------- */
15800 
15801 /*!
15802  * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks
15803  * @{
15804  */
15805 
15806 /*! @name OUTBASE - Base address register for output region */
15807 /*! @{ */
15808 
15809 #define POWERQUAD_OUTBASE_OUTBASE_MASK           (0xFFFFFFFFU)
15810 #define POWERQUAD_OUTBASE_OUTBASE_SHIFT          (0U)
15811 /*! outbase - Base address register for the output region
15812  */
15813 #define POWERQUAD_OUTBASE_OUTBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)
15814 /*! @} */
15815 
15816 /*! @name OUTFORMAT - Output format */
15817 /*! @{ */
15818 
15819 #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK   (0x3U)
15820 #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT  (0U)
15821 /*! out_formatint - Output Internal format (00: q15; 01:q31; 10:float)
15822  */
15823 #define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)
15824 
15825 #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK   (0x30U)
15826 #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT  (4U)
15827 /*! out_formatext - Output External format (00: q15; 01:q31; 10:float)
15828  */
15829 #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)
15830 
15831 #define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK      (0xFF00U)
15832 #define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT     (8U)
15833 /*! out_scaler - Output Scaler value (for scaled 'q31' formats)
15834  */
15835 #define POWERQUAD_OUTFORMAT_OUT_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)
15836 /*! @} */
15837 
15838 /*! @name TMPBASE - Base address register for temp region */
15839 /*! @{ */
15840 
15841 #define POWERQUAD_TMPBASE_TMPBASE_MASK           (0xFFFFFFFFU)
15842 #define POWERQUAD_TMPBASE_TMPBASE_SHIFT          (0U)
15843 /*! tmpbase - Base address register for the temporary region
15844  */
15845 #define POWERQUAD_TMPBASE_TMPBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)
15846 /*! @} */
15847 
15848 /*! @name TMPFORMAT - Temp format */
15849 /*! @{ */
15850 
15851 #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK   (0x3U)
15852 #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT  (0U)
15853 /*! tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float)
15854  */
15855 #define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)
15856 
15857 #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK   (0x30U)
15858 #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT  (4U)
15859 /*! tmp_formatext - Temp External format (00: q15; 01:q31; 10:float)
15860  */
15861 #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)
15862 
15863 #define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK      (0xFF00U)
15864 #define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT     (8U)
15865 /*! tmp_scaler - Temp Scaler value (for scaled 'q31' formats)
15866  */
15867 #define POWERQUAD_TMPFORMAT_TMP_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)
15868 /*! @} */
15869 
15870 /*! @name INABASE - Base address register for input A region */
15871 /*! @{ */
15872 
15873 #define POWERQUAD_INABASE_INABASE_MASK           (0xFFFFFFFFU)
15874 #define POWERQUAD_INABASE_INABASE_SHIFT          (0U)
15875 /*! inabase - Base address register for the input A region
15876  */
15877 #define POWERQUAD_INABASE_INABASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)
15878 /*! @} */
15879 
15880 /*! @name INAFORMAT - Input A format */
15881 /*! @{ */
15882 
15883 #define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK   (0x3U)
15884 #define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT  (0U)
15885 /*! ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float)
15886  */
15887 #define POWERQUAD_INAFORMAT_INA_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)
15888 
15889 #define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK   (0x30U)
15890 #define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT  (4U)
15891 /*! ina_formatext - Input A External format (00: q15; 01:q31; 10:float)
15892  */
15893 #define POWERQUAD_INAFORMAT_INA_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)
15894 
15895 #define POWERQUAD_INAFORMAT_INA_SCALER_MASK      (0xFF00U)
15896 #define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT     (8U)
15897 /*! ina_scaler - Input A Scaler value (for scaled 'q31' formats)
15898  */
15899 #define POWERQUAD_INAFORMAT_INA_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)
15900 /*! @} */
15901 
15902 /*! @name INBBASE - Base address register for input B region */
15903 /*! @{ */
15904 
15905 #define POWERQUAD_INBBASE_INBBASE_MASK           (0xFFFFFFFFU)
15906 #define POWERQUAD_INBBASE_INBBASE_SHIFT          (0U)
15907 /*! inbbase - Base address register for the input B region
15908  */
15909 #define POWERQUAD_INBBASE_INBBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)
15910 /*! @} */
15911 
15912 /*! @name INBFORMAT - Input B format */
15913 /*! @{ */
15914 
15915 #define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK   (0x3U)
15916 #define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT  (0U)
15917 /*! inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float)
15918  */
15919 #define POWERQUAD_INBFORMAT_INB_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)
15920 
15921 #define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK   (0x30U)
15922 #define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT  (4U)
15923 /*! inb_formatext - Input B External format (00: q15; 01:q31; 10:float)
15924  */
15925 #define POWERQUAD_INBFORMAT_INB_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)
15926 
15927 #define POWERQUAD_INBFORMAT_INB_SCALER_MASK      (0xFF00U)
15928 #define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT     (8U)
15929 /*! inb_scaler - Input B Scaler value (for scaled 'q31' formats)
15930  */
15931 #define POWERQUAD_INBFORMAT_INB_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)
15932 /*! @} */
15933 
15934 /*! @name CONTROL - PowerQuad Control register */
15935 /*! @{ */
15936 
15937 #define POWERQUAD_CONTROL_DECODE_OPCODE_MASK     (0xFU)
15938 #define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT    (0U)
15939 /*! decode_opcode - opcode specific to decode_machine
15940  */
15941 #define POWERQUAD_CONTROL_DECODE_OPCODE(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)
15942 
15943 #define POWERQUAD_CONTROL_DECODE_MACHINE_MASK    (0xF0U)
15944 #define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT   (4U)
15945 /*! decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA
15946  */
15947 #define POWERQUAD_CONTROL_DECODE_MACHINE(x)      (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)
15948 
15949 #define POWERQUAD_CONTROL_INST_BUSY_MASK         (0x80000000U)
15950 #define POWERQUAD_CONTROL_INST_BUSY_SHIFT        (31U)
15951 /*! inst_busy - Instruction busy signal when high indicates processing is on
15952  */
15953 #define POWERQUAD_CONTROL_INST_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)
15954 /*! @} */
15955 
15956 /*! @name LENGTH - Length register */
15957 /*! @{ */
15958 
15959 #define POWERQUAD_LENGTH_INST_LENGTH_MASK        (0xFFFFFFFFU)
15960 #define POWERQUAD_LENGTH_INST_LENGTH_SHIFT       (0U)
15961 /*! inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength =
15962  *    inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b =
15963  *    inst_length[20:16]
15964  */
15965 #define POWERQUAD_LENGTH_INST_LENGTH(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)
15966 /*! @} */
15967 
15968 /*! @name CPPRE - Pre-scale register */
15969 /*! @{ */
15970 
15971 #define POWERQUAD_CPPRE_CPPRE_IN_MASK            (0xFFU)
15972 #define POWERQUAD_CPPRE_CPPRE_IN_SHIFT           (0U)
15973 /*! cppre_in - co-processor scaling of input
15974  */
15975 #define POWERQUAD_CPPRE_CPPRE_IN(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)
15976 
15977 #define POWERQUAD_CPPRE_CPPRE_OUT_MASK           (0xFF00U)
15978 #define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT          (8U)
15979 /*! cppre_out - co-processor fixed point output
15980  */
15981 #define POWERQUAD_CPPRE_CPPRE_OUT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)
15982 
15983 #define POWERQUAD_CPPRE_CPPRE_SAT_MASK           (0x10000U)
15984 #define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT          (16U)
15985 /*! cppre_sat - 1 : forces sub-32 bit saturation
15986  */
15987 #define POWERQUAD_CPPRE_CPPRE_SAT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)
15988 
15989 #define POWERQUAD_CPPRE_CPPRE_SAT8_MASK          (0x20000U)
15990 #define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT         (17U)
15991 /*! cppre_sat8 - 0 = 8bits, 1 = 16bits
15992  */
15993 #define POWERQUAD_CPPRE_CPPRE_SAT8(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)
15994 /*! @} */
15995 
15996 /*! @name MISC - Misc register */
15997 /*! @{ */
15998 
15999 #define POWERQUAD_MISC_INST_MISC_MASK            (0xFFFFFFFFU)
16000 #define POWERQUAD_MISC_INST_MISC_SHIFT           (0U)
16001 /*! inst_misc - Misc register. For Matrix : Used for scale factor
16002  */
16003 #define POWERQUAD_MISC_INST_MISC(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)
16004 /*! @} */
16005 
16006 /*! @name CURSORY - Cursory register */
16007 /*! @{ */
16008 
16009 #define POWERQUAD_CURSORY_CURSORY_MASK           (0x1U)
16010 #define POWERQUAD_CURSORY_CURSORY_SHIFT          (0U)
16011 /*! cursory - 1 : Enable cursory mode
16012  */
16013 #define POWERQUAD_CURSORY_CURSORY(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)
16014 /*! @} */
16015 
16016 /*! @name CORDIC_X - Cordic input X register */
16017 /*! @{ */
16018 
16019 #define POWERQUAD_CORDIC_X_CORDIC_X_MASK         (0xFFFFFFFFU)
16020 #define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT        (0U)
16021 /*! cordic_x - Cordic input x
16022  */
16023 #define POWERQUAD_CORDIC_X_CORDIC_X(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)
16024 /*! @} */
16025 
16026 /*! @name CORDIC_Y - Cordic input Y register */
16027 /*! @{ */
16028 
16029 #define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK         (0xFFFFFFFFU)
16030 #define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT        (0U)
16031 /*! cordic_y - Cordic input y
16032  */
16033 #define POWERQUAD_CORDIC_Y_CORDIC_Y(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)
16034 /*! @} */
16035 
16036 /*! @name CORDIC_Z - Cordic input Z register */
16037 /*! @{ */
16038 
16039 #define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK         (0xFFFFFFFFU)
16040 #define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT        (0U)
16041 /*! cordic_z - Cordic input z
16042  */
16043 #define POWERQUAD_CORDIC_Z_CORDIC_Z(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)
16044 /*! @} */
16045 
16046 /*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */
16047 /*! @{ */
16048 
16049 #define POWERQUAD_ERRSTAT_OVERFLOW_MASK          (0x1U)
16050 #define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT         (0U)
16051 /*! OVERFLOW - overflow
16052  */
16053 #define POWERQUAD_ERRSTAT_OVERFLOW(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)
16054 
16055 #define POWERQUAD_ERRSTAT_NAN_MASK               (0x2U)
16056 #define POWERQUAD_ERRSTAT_NAN_SHIFT              (1U)
16057 /*! NAN - nan
16058  */
16059 #define POWERQUAD_ERRSTAT_NAN(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)
16060 
16061 #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK     (0x4U)
16062 #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT    (2U)
16063 /*! FIXEDOVERFLOW - fixed_pt_overflow
16064  */
16065 #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)
16066 
16067 #define POWERQUAD_ERRSTAT_UNDERFLOW_MASK         (0x8U)
16068 #define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT        (3U)
16069 /*! UNDERFLOW - underflow
16070  */
16071 #define POWERQUAD_ERRSTAT_UNDERFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)
16072 
16073 #define POWERQUAD_ERRSTAT_BUSERROR_MASK          (0x10U)
16074 #define POWERQUAD_ERRSTAT_BUSERROR_SHIFT         (4U)
16075 /*! BUSERROR - bus_error
16076  */
16077 #define POWERQUAD_ERRSTAT_BUSERROR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)
16078 /*! @} */
16079 
16080 /*! @name INTREN - INTERRUPT enable register */
16081 /*! @{ */
16082 
16083 #define POWERQUAD_INTREN_INTR_OFLOW_MASK         (0x1U)
16084 #define POWERQUAD_INTREN_INTR_OFLOW_SHIFT        (0U)
16085 /*! intr_oflow - 1 : Enable interrupt on Floating point overflow
16086  */
16087 #define POWERQUAD_INTREN_INTR_OFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)
16088 
16089 #define POWERQUAD_INTREN_INTR_NAN_MASK           (0x2U)
16090 #define POWERQUAD_INTREN_INTR_NAN_SHIFT          (1U)
16091 /*! intr_nan - 1 : Enable interrupt on Floating point NaN
16092  */
16093 #define POWERQUAD_INTREN_INTR_NAN(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)
16094 
16095 #define POWERQUAD_INTREN_INTR_FIXED_MASK         (0x4U)
16096 #define POWERQUAD_INTREN_INTR_FIXED_SHIFT        (2U)
16097 /*! intr_fixed - 1: Enable interrupt on Fixed point Overflow
16098  */
16099 #define POWERQUAD_INTREN_INTR_FIXED(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)
16100 
16101 #define POWERQUAD_INTREN_INTR_UFLOW_MASK         (0x8U)
16102 #define POWERQUAD_INTREN_INTR_UFLOW_SHIFT        (3U)
16103 /*! intr_uflow - 1 : Enable interrupt on Subnormal truncation
16104  */
16105 #define POWERQUAD_INTREN_INTR_UFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)
16106 
16107 #define POWERQUAD_INTREN_INTR_BERR_MASK          (0x10U)
16108 #define POWERQUAD_INTREN_INTR_BERR_SHIFT         (4U)
16109 /*! intr_berr - 1: Enable interrupt on AHBM Buss Error
16110  */
16111 #define POWERQUAD_INTREN_INTR_BERR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)
16112 
16113 #define POWERQUAD_INTREN_INTR_COMP_MASK          (0x80U)
16114 #define POWERQUAD_INTREN_INTR_COMP_SHIFT         (7U)
16115 /*! intr_comp - 1: Enable interrupt on instruction completion
16116  */
16117 #define POWERQUAD_INTREN_INTR_COMP(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)
16118 /*! @} */
16119 
16120 /*! @name EVENTEN - Event Enable register */
16121 /*! @{ */
16122 
16123 #define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK       (0x1U)
16124 #define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT      (0U)
16125 /*! event_oflow - 1 : Enable event trigger on Floating point overflow
16126  */
16127 #define POWERQUAD_EVENTEN_EVENT_OFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)
16128 
16129 #define POWERQUAD_EVENTEN_EVENT_NAN_MASK         (0x2U)
16130 #define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT        (1U)
16131 /*! event_nan - 1 : Enable event trigger on Floating point NaN
16132  */
16133 #define POWERQUAD_EVENTEN_EVENT_NAN(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)
16134 
16135 #define POWERQUAD_EVENTEN_EVENT_FIXED_MASK       (0x4U)
16136 #define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT      (2U)
16137 /*! event_fixed - 1: Enable event trigger on Fixed point Overflow
16138  */
16139 #define POWERQUAD_EVENTEN_EVENT_FIXED(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)
16140 
16141 #define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK       (0x8U)
16142 #define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT      (3U)
16143 /*! event_uflow - 1 : Enable event trigger on Subnormal truncation
16144  */
16145 #define POWERQUAD_EVENTEN_EVENT_UFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)
16146 
16147 #define POWERQUAD_EVENTEN_EVENT_BERR_MASK        (0x10U)
16148 #define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT       (4U)
16149 /*! event_berr - 1: Enable event trigger on AHBM Buss Error
16150  */
16151 #define POWERQUAD_EVENTEN_EVENT_BERR(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)
16152 
16153 #define POWERQUAD_EVENTEN_EVENT_COMP_MASK        (0x80U)
16154 #define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT       (7U)
16155 /*! event_comp - 1: Enable event trigger on instruction completion
16156  */
16157 #define POWERQUAD_EVENTEN_EVENT_COMP(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)
16158 /*! @} */
16159 
16160 /*! @name INTRSTAT - INTERRUPT STATUS register */
16161 /*! @{ */
16162 
16163 #define POWERQUAD_INTRSTAT_INTR_STAT_MASK        (0x1U)
16164 #define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT       (0U)
16165 /*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit
16166  */
16167 #define POWERQUAD_INTRSTAT_INTR_STAT(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)
16168 /*! @} */
16169 
16170 /*! @name GPREG - General purpose register bank N. */
16171 /*! @{ */
16172 
16173 #define POWERQUAD_GPREG_GPREG_MASK               (0xFFFFFFFFU)
16174 #define POWERQUAD_GPREG_GPREG_SHIFT              (0U)
16175 /*! gpreg - General purpose register bank
16176  */
16177 #define POWERQUAD_GPREG_GPREG(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)
16178 /*! @} */
16179 
16180 /* The count of POWERQUAD_GPREG */
16181 #define POWERQUAD_GPREG_COUNT                    (16U)
16182 
16183 /*! @name COMPREGS_COMPREG - Compute register bank */
16184 /*! @{ */
16185 
16186 #define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK  (0xFFFFFFFFU)
16187 #define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U)
16188 /*! compreg - Compute register bank
16189  */
16190 #define POWERQUAD_COMPREGS_COMPREG_COMPREG(x)    (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)
16191 /*! @} */
16192 
16193 /* The count of POWERQUAD_COMPREGS_COMPREG */
16194 #define POWERQUAD_COMPREGS_COMPREG_COUNT         (8U)
16195 
16196 
16197 /*!
16198  * @}
16199  */ /* end of group POWERQUAD_Register_Masks */
16200 
16201 
16202 /* POWERQUAD - Peripheral instance base addresses */
16203 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
16204   /** Peripheral POWERQUAD base address */
16205   #define POWERQUAD_BASE                           (0x500A6000u)
16206   /** Peripheral POWERQUAD base address */
16207   #define POWERQUAD_BASE_NS                        (0x400A6000u)
16208   /** Peripheral POWERQUAD base pointer */
16209   #define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
16210   /** Peripheral POWERQUAD base pointer */
16211   #define POWERQUAD_NS                             ((POWERQUAD_Type *)POWERQUAD_BASE_NS)
16212   /** Array initializer of POWERQUAD peripheral base addresses */
16213   #define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
16214   /** Array initializer of POWERQUAD peripheral base pointers */
16215   #define POWERQUAD_BASE_PTRS                      { POWERQUAD }
16216   /** Array initializer of POWERQUAD peripheral base addresses */
16217   #define POWERQUAD_BASE_ADDRS_NS                  { POWERQUAD_BASE_NS }
16218   /** Array initializer of POWERQUAD peripheral base pointers */
16219   #define POWERQUAD_BASE_PTRS_NS                   { POWERQUAD_NS }
16220 #else
16221   /** Peripheral POWERQUAD base address */
16222   #define POWERQUAD_BASE                           (0x400A6000u)
16223   /** Peripheral POWERQUAD base pointer */
16224   #define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
16225   /** Array initializer of POWERQUAD peripheral base addresses */
16226   #define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
16227   /** Array initializer of POWERQUAD peripheral base pointers */
16228   #define POWERQUAD_BASE_PTRS                      { POWERQUAD }
16229 #endif
16230 
16231 /*!
16232  * @}
16233  */ /* end of group POWERQUAD_Peripheral_Access_Layer */
16234 
16235 
16236 /* ----------------------------------------------------------------------------
16237    -- PRINCE Peripheral Access Layer
16238    ---------------------------------------------------------------------------- */
16239 
16240 /*!
16241  * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer
16242  * @{
16243  */
16244 
16245 /** PRINCE - Register Layout Typedef */
16246 typedef struct {
16247   __IO uint32_t ENC_ENABLE;                        /**< Encryption Enable register, offset: 0x0 */
16248   __O  uint32_t MASK_LSB;                          /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */
16249   __O  uint32_t MASK_MSB;                          /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */
16250   __IO uint32_t LOCK;                              /**< Lock register, offset: 0xC */
16251   __O  uint32_t IV_LSB0;                           /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */
16252   __O  uint32_t IV_MSB0;                           /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */
16253   __IO uint32_t BASE_ADDR0;                        /**< Base Address for region 0 register, offset: 0x18 */
16254   __IO uint32_t SR_ENABLE0;                        /**< Sub-Region Enable register for region 0, offset: 0x1C */
16255   __O  uint32_t IV_LSB1;                           /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */
16256   __O  uint32_t IV_MSB1;                           /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */
16257   __IO uint32_t BASE_ADDR1;                        /**< Base Address for region 1 register, offset: 0x28 */
16258   __IO uint32_t SR_ENABLE1;                        /**< Sub-Region Enable register for region 1, offset: 0x2C */
16259   __O  uint32_t IV_LSB2;                           /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */
16260   __O  uint32_t IV_MSB2;                           /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */
16261   __IO uint32_t BASE_ADDR2;                        /**< Base Address for region 2 register, offset: 0x38 */
16262   __IO uint32_t SR_ENABLE2;                        /**< Sub-Region Enable register for region 2, offset: 0x3C */
16263 } PRINCE_Type;
16264 
16265 /* ----------------------------------------------------------------------------
16266    -- PRINCE Register Masks
16267    ---------------------------------------------------------------------------- */
16268 
16269 /*!
16270  * @addtogroup PRINCE_Register_Masks PRINCE Register Masks
16271  * @{
16272  */
16273 
16274 /*! @name ENC_ENABLE - Encryption Enable register */
16275 /*! @{ */
16276 
16277 #define PRINCE_ENC_ENABLE_EN_MASK                (0x1U)
16278 #define PRINCE_ENC_ENABLE_EN_SHIFT               (0U)
16279 /*! EN - Encryption Enable.
16280  *  0b0..Encryption of writes to the flash controller DATAW* registers is disabled.
16281  *  0b1..Encryption of writes to the flash controller DATAW* registers is enabled.
16282  */
16283 #define PRINCE_ENC_ENABLE_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK)
16284 /*! @} */
16285 
16286 /*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */
16287 /*! @{ */
16288 
16289 #define PRINCE_MASK_LSB_MASKVAL_MASK             (0xFFFFFFFFU)
16290 #define PRINCE_MASK_LSB_MASKVAL_SHIFT            (0U)
16291 /*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask.
16292  */
16293 #define PRINCE_MASK_LSB_MASKVAL(x)               (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK)
16294 /*! @} */
16295 
16296 /*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */
16297 /*! @{ */
16298 
16299 #define PRINCE_MASK_MSB_MASKVAL_MASK             (0xFFFFFFFFU)
16300 #define PRINCE_MASK_MSB_MASKVAL_SHIFT            (0U)
16301 /*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask.
16302  */
16303 #define PRINCE_MASK_MSB_MASKVAL(x)               (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK)
16304 /*! @} */
16305 
16306 /*! @name LOCK - Lock register */
16307 /*! @{ */
16308 
16309 #define PRINCE_LOCK_LOCKREG0_MASK                (0x1U)
16310 #define PRINCE_LOCK_LOCKREG0_SHIFT               (0U)
16311 /*! LOCKREG0 - Lock Region 0 registers.
16312  *  0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable..
16313  *  0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable..
16314  */
16315 #define PRINCE_LOCK_LOCKREG0(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK)
16316 
16317 #define PRINCE_LOCK_LOCKREG1_MASK                (0x2U)
16318 #define PRINCE_LOCK_LOCKREG1_SHIFT               (1U)
16319 /*! LOCKREG1 - Lock Region 1 registers.
16320  *  0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable..
16321  *  0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable..
16322  */
16323 #define PRINCE_LOCK_LOCKREG1(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK)
16324 
16325 #define PRINCE_LOCK_LOCKREG2_MASK                (0x4U)
16326 #define PRINCE_LOCK_LOCKREG2_SHIFT               (2U)
16327 /*! LOCKREG2 - Lock Region 2 registers.
16328  *  0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable..
16329  *  0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable..
16330  */
16331 #define PRINCE_LOCK_LOCKREG2(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK)
16332 
16333 #define PRINCE_LOCK_LOCKMASK_MASK                (0x100U)
16334 #define PRINCE_LOCK_LOCKMASK_SHIFT               (8U)
16335 /*! LOCKMASK - Lock the Mask registers.
16336  *  0b0..Disabled. MASK_LSB, and MASK_MSB are writable..
16337  *  0b1..Enabled. MASK_LSB, and MASK_MSB are not writable..
16338  */
16339 #define PRINCE_LOCK_LOCKMASK(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK)
16340 /*! @} */
16341 
16342 /*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */
16343 /*! @{ */
16344 
16345 #define PRINCE_IV_LSB0_IVVAL_MASK                (0xFFFFFFFFU)
16346 #define PRINCE_IV_LSB0_IVVAL_SHIFT               (0U)
16347 /*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
16348  */
16349 #define PRINCE_IV_LSB0_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK)
16350 /*! @} */
16351 
16352 /*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */
16353 /*! @{ */
16354 
16355 #define PRINCE_IV_MSB0_IVVAL_MASK                (0xFFFFFFFFU)
16356 #define PRINCE_IV_MSB0_IVVAL_SHIFT               (0U)
16357 /*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
16358  */
16359 #define PRINCE_IV_MSB0_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK)
16360 /*! @} */
16361 
16362 /*! @name BASE_ADDR0 - Base Address for region 0 register */
16363 /*! @{ */
16364 
16365 #define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK        (0x3FFFFU)
16366 #define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT       (0U)
16367 /*! ADDR_FIXED - Fixed portion of the base address of region 0.
16368  */
16369 #define PRINCE_BASE_ADDR0_ADDR_FIXED(x)          (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK)
16370 
16371 #define PRINCE_BASE_ADDR0_ADDR_PRG_MASK          (0xC0000U)
16372 #define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT         (18U)
16373 /*! ADDR_PRG - Programmable portion of the base address of region 0.
16374  */
16375 #define PRINCE_BASE_ADDR0_ADDR_PRG(x)            (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK)
16376 /*! @} */
16377 
16378 /*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */
16379 /*! @{ */
16380 
16381 #define PRINCE_SR_ENABLE0_EN_MASK                (0xFFFFFFFFU)
16382 #define PRINCE_SR_ENABLE0_EN_SHIFT               (0U)
16383 /*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0.
16384  */
16385 #define PRINCE_SR_ENABLE0_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK)
16386 /*! @} */
16387 
16388 /*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */
16389 /*! @{ */
16390 
16391 #define PRINCE_IV_LSB1_IVVAL_MASK                (0xFFFFFFFFU)
16392 #define PRINCE_IV_LSB1_IVVAL_SHIFT               (0U)
16393 /*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
16394  */
16395 #define PRINCE_IV_LSB1_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK)
16396 /*! @} */
16397 
16398 /*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */
16399 /*! @{ */
16400 
16401 #define PRINCE_IV_MSB1_IVVAL_MASK                (0xFFFFFFFFU)
16402 #define PRINCE_IV_MSB1_IVVAL_SHIFT               (0U)
16403 /*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
16404  */
16405 #define PRINCE_IV_MSB1_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK)
16406 /*! @} */
16407 
16408 /*! @name BASE_ADDR1 - Base Address for region 1 register */
16409 /*! @{ */
16410 
16411 #define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK        (0x3FFFFU)
16412 #define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT       (0U)
16413 /*! ADDR_FIXED - Fixed portion of the base address of region 1.
16414  */
16415 #define PRINCE_BASE_ADDR1_ADDR_FIXED(x)          (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK)
16416 
16417 #define PRINCE_BASE_ADDR1_ADDR_PRG_MASK          (0xC0000U)
16418 #define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT         (18U)
16419 /*! ADDR_PRG - Programmable portion of the base address of region 1.
16420  */
16421 #define PRINCE_BASE_ADDR1_ADDR_PRG(x)            (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK)
16422 /*! @} */
16423 
16424 /*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */
16425 /*! @{ */
16426 
16427 #define PRINCE_SR_ENABLE1_EN_MASK                (0xFFFFFFFFU)
16428 #define PRINCE_SR_ENABLE1_EN_SHIFT               (0U)
16429 /*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1.
16430  */
16431 #define PRINCE_SR_ENABLE1_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK)
16432 /*! @} */
16433 
16434 /*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */
16435 /*! @{ */
16436 
16437 #define PRINCE_IV_LSB2_IVVAL_MASK                (0xFFFFFFFFU)
16438 #define PRINCE_IV_LSB2_IVVAL_SHIFT               (0U)
16439 /*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
16440  */
16441 #define PRINCE_IV_LSB2_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK)
16442 /*! @} */
16443 
16444 /*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */
16445 /*! @{ */
16446 
16447 #define PRINCE_IV_MSB2_IVVAL_MASK                (0xFFFFFFFFU)
16448 #define PRINCE_IV_MSB2_IVVAL_SHIFT               (0U)
16449 /*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
16450  */
16451 #define PRINCE_IV_MSB2_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK)
16452 /*! @} */
16453 
16454 /*! @name BASE_ADDR2 - Base Address for region 2 register */
16455 /*! @{ */
16456 
16457 #define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK        (0x3FFFFU)
16458 #define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT       (0U)
16459 /*! ADDR_FIXED - Fixed portion of the base address of region 2.
16460  */
16461 #define PRINCE_BASE_ADDR2_ADDR_FIXED(x)          (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK)
16462 
16463 #define PRINCE_BASE_ADDR2_ADDR_PRG_MASK          (0xC0000U)
16464 #define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT         (18U)
16465 /*! ADDR_PRG - Programmable portion of the base address of region 2.
16466  */
16467 #define PRINCE_BASE_ADDR2_ADDR_PRG(x)            (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK)
16468 /*! @} */
16469 
16470 /*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */
16471 /*! @{ */
16472 
16473 #define PRINCE_SR_ENABLE2_EN_MASK                (0xFFFFFFFFU)
16474 #define PRINCE_SR_ENABLE2_EN_SHIFT               (0U)
16475 /*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2.
16476  */
16477 #define PRINCE_SR_ENABLE2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK)
16478 /*! @} */
16479 
16480 
16481 /*!
16482  * @}
16483  */ /* end of group PRINCE_Register_Masks */
16484 
16485 
16486 /* PRINCE - Peripheral instance base addresses */
16487 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
16488   /** Peripheral PRINCE base address */
16489   #define PRINCE_BASE                              (0x50035000u)
16490   /** Peripheral PRINCE base address */
16491   #define PRINCE_BASE_NS                           (0x40035000u)
16492   /** Peripheral PRINCE base pointer */
16493   #define PRINCE                                   ((PRINCE_Type *)PRINCE_BASE)
16494   /** Peripheral PRINCE base pointer */
16495   #define PRINCE_NS                                ((PRINCE_Type *)PRINCE_BASE_NS)
16496   /** Array initializer of PRINCE peripheral base addresses */
16497   #define PRINCE_BASE_ADDRS                        { PRINCE_BASE }
16498   /** Array initializer of PRINCE peripheral base pointers */
16499   #define PRINCE_BASE_PTRS                         { PRINCE }
16500   /** Array initializer of PRINCE peripheral base addresses */
16501   #define PRINCE_BASE_ADDRS_NS                     { PRINCE_BASE_NS }
16502   /** Array initializer of PRINCE peripheral base pointers */
16503   #define PRINCE_BASE_PTRS_NS                      { PRINCE_NS }
16504 #else
16505   /** Peripheral PRINCE base address */
16506   #define PRINCE_BASE                              (0x40035000u)
16507   /** Peripheral PRINCE base pointer */
16508   #define PRINCE                                   ((PRINCE_Type *)PRINCE_BASE)
16509   /** Array initializer of PRINCE peripheral base addresses */
16510   #define PRINCE_BASE_ADDRS                        { PRINCE_BASE }
16511   /** Array initializer of PRINCE peripheral base pointers */
16512   #define PRINCE_BASE_PTRS                         { PRINCE }
16513 #endif
16514 
16515 /*!
16516  * @}
16517  */ /* end of group PRINCE_Peripheral_Access_Layer */
16518 
16519 
16520 /* ----------------------------------------------------------------------------
16521    -- PUF Peripheral Access Layer
16522    ---------------------------------------------------------------------------- */
16523 
16524 /*!
16525  * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
16526  * @{
16527  */
16528 
16529 /** PUF - Register Layout Typedef */
16530 typedef struct {
16531   __IO uint32_t CTRL;                              /**< PUF Control register, offset: 0x0 */
16532   __IO uint32_t KEYINDEX;                          /**< PUF Key Index register, offset: 0x4 */
16533   __IO uint32_t KEYSIZE;                           /**< PUF Key Size register, offset: 0x8 */
16534        uint8_t RESERVED_0[20];
16535   __I  uint32_t STAT;                              /**< PUF Status register, offset: 0x20 */
16536        uint8_t RESERVED_1[4];
16537   __I  uint32_t ALLOW;                             /**< PUF Allow register, offset: 0x28 */
16538        uint8_t RESERVED_2[20];
16539   __O  uint32_t KEYINPUT;                          /**< PUF Key Input register, offset: 0x40 */
16540   __O  uint32_t CODEINPUT;                         /**< PUF Code Input register, offset: 0x44 */
16541   __I  uint32_t CODEOUTPUT;                        /**< PUF Code Output register, offset: 0x48 */
16542        uint8_t RESERVED_3[20];
16543   __I  uint32_t KEYOUTINDEX;                       /**< PUF Key Output Index register, offset: 0x60 */
16544   __I  uint32_t KEYOUTPUT;                         /**< PUF Key Output register, offset: 0x64 */
16545        uint8_t RESERVED_4[116];
16546   __IO uint32_t IFSTAT;                            /**< PUF Interface Status and clear register, offset: 0xDC */
16547        uint8_t RESERVED_5[28];
16548   __I  uint32_t VERSION;                           /**< PUF version register., offset: 0xFC */
16549   __IO uint32_t INTEN;                             /**< PUF Interrupt Enable, offset: 0x100 */
16550   __IO uint32_t INTSTAT;                           /**< PUF interrupt status, offset: 0x104 */
16551   __IO uint32_t PWRCTRL;                           /**< PUF RAM Power Control, offset: 0x108 */
16552   __IO uint32_t CFG;                               /**< PUF config register for block bits, offset: 0x10C */
16553        uint8_t RESERVED_6[240];
16554   __IO uint32_t KEYLOCK;                           /**< Only reset in case of full IC reset, offset: 0x200 */
16555   __IO uint32_t KEYENABLE;                         /**< , offset: 0x204 */
16556   __O  uint32_t KEYRESET;                          /**< Reinitialize Keys shift registers counters, offset: 0x208 */
16557   __IO uint32_t IDXBLK_L;                          /**< , offset: 0x20C */
16558   __IO uint32_t IDXBLK_H_DP;                       /**< , offset: 0x210 */
16559   __O  uint32_t KEYMASK[4];                        /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */
16560        uint8_t RESERVED_7[48];
16561   __IO uint32_t IDXBLK_H;                          /**< , offset: 0x254 */
16562   __IO uint32_t IDXBLK_L_DP;                       /**< , offset: 0x258 */
16563   __I  uint32_t SHIFT_STATUS;                      /**< , offset: 0x25C */
16564 } PUF_Type;
16565 
16566 /* ----------------------------------------------------------------------------
16567    -- PUF Register Masks
16568    ---------------------------------------------------------------------------- */
16569 
16570 /*!
16571  * @addtogroup PUF_Register_Masks PUF Register Masks
16572  * @{
16573  */
16574 
16575 /*! @name CTRL - PUF Control register */
16576 /*! @{ */
16577 
16578 #define PUF_CTRL_ZEROIZE_MASK                    (0x1U)
16579 #define PUF_CTRL_ZEROIZE_SHIFT                   (0U)
16580 /*! zeroize - Begin Zeroize operation for PUF and go to Error state
16581  */
16582 #define PUF_CTRL_ZEROIZE(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
16583 
16584 #define PUF_CTRL_ENROLL_MASK                     (0x2U)
16585 #define PUF_CTRL_ENROLL_SHIFT                    (1U)
16586 /*! enroll - Begin Enroll operation
16587  */
16588 #define PUF_CTRL_ENROLL(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
16589 
16590 #define PUF_CTRL_START_MASK                      (0x4U)
16591 #define PUF_CTRL_START_SHIFT                     (2U)
16592 /*! start - Begin Start operation
16593  */
16594 #define PUF_CTRL_START(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
16595 
16596 #define PUF_CTRL_GENERATEKEY_MASK                (0x8U)
16597 #define PUF_CTRL_GENERATEKEY_SHIFT               (3U)
16598 /*! GENERATEKEY - Begin Set Intrinsic Key operation
16599  */
16600 #define PUF_CTRL_GENERATEKEY(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
16601 
16602 #define PUF_CTRL_SETKEY_MASK                     (0x10U)
16603 #define PUF_CTRL_SETKEY_SHIFT                    (4U)
16604 /*! SETKEY - Begin Set User Key operation
16605  */
16606 #define PUF_CTRL_SETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
16607 
16608 #define PUF_CTRL_GETKEY_MASK                     (0x40U)
16609 #define PUF_CTRL_GETKEY_SHIFT                    (6U)
16610 /*! GETKEY - Begin Get Key operation
16611  */
16612 #define PUF_CTRL_GETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
16613 /*! @} */
16614 
16615 /*! @name KEYINDEX - PUF Key Index register */
16616 /*! @{ */
16617 
16618 #define PUF_KEYINDEX_KEYIDX_MASK                 (0xFU)
16619 #define PUF_KEYINDEX_KEYIDX_SHIFT                (0U)
16620 /*! KEYIDX - Key index for Set Key operations
16621  */
16622 #define PUF_KEYINDEX_KEYIDX(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
16623 /*! @} */
16624 
16625 /*! @name KEYSIZE - PUF Key Size register */
16626 /*! @{ */
16627 
16628 #define PUF_KEYSIZE_KEYSIZE_MASK                 (0x3FU)
16629 #define PUF_KEYSIZE_KEYSIZE_SHIFT                (0U)
16630 /*! KEYSIZE - Key size for Set Key operations
16631  */
16632 #define PUF_KEYSIZE_KEYSIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
16633 /*! @} */
16634 
16635 /*! @name STAT - PUF Status register */
16636 /*! @{ */
16637 
16638 #define PUF_STAT_BUSY_MASK                       (0x1U)
16639 #define PUF_STAT_BUSY_SHIFT                      (0U)
16640 /*! busy - Indicates that operation is in progress
16641  */
16642 #define PUF_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
16643 
16644 #define PUF_STAT_SUCCESS_MASK                    (0x2U)
16645 #define PUF_STAT_SUCCESS_SHIFT                   (1U)
16646 /*! SUCCESS - Last operation was successful
16647  */
16648 #define PUF_STAT_SUCCESS(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
16649 
16650 #define PUF_STAT_ERROR_MASK                      (0x4U)
16651 #define PUF_STAT_ERROR_SHIFT                     (2U)
16652 /*! error - PUF is in the Error state and no operations can be performed
16653  */
16654 #define PUF_STAT_ERROR(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
16655 
16656 #define PUF_STAT_KEYINREQ_MASK                   (0x10U)
16657 #define PUF_STAT_KEYINREQ_SHIFT                  (4U)
16658 /*! KEYINREQ - Request for next part of key
16659  */
16660 #define PUF_STAT_KEYINREQ(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
16661 
16662 #define PUF_STAT_KEYOUTAVAIL_MASK                (0x20U)
16663 #define PUF_STAT_KEYOUTAVAIL_SHIFT               (5U)
16664 /*! KEYOUTAVAIL - Next part of key is available
16665  */
16666 #define PUF_STAT_KEYOUTAVAIL(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
16667 
16668 #define PUF_STAT_CODEINREQ_MASK                  (0x40U)
16669 #define PUF_STAT_CODEINREQ_SHIFT                 (6U)
16670 /*! CODEINREQ - Request for next part of AC/KC
16671  */
16672 #define PUF_STAT_CODEINREQ(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
16673 
16674 #define PUF_STAT_CODEOUTAVAIL_MASK               (0x80U)
16675 #define PUF_STAT_CODEOUTAVAIL_SHIFT              (7U)
16676 /*! CODEOUTAVAIL - Next part of AC/KC is available
16677  */
16678 #define PUF_STAT_CODEOUTAVAIL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
16679 /*! @} */
16680 
16681 /*! @name ALLOW - PUF Allow register */
16682 /*! @{ */
16683 
16684 #define PUF_ALLOW_ALLOWENROLL_MASK               (0x1U)
16685 #define PUF_ALLOW_ALLOWENROLL_SHIFT              (0U)
16686 /*! ALLOWENROLL - Enroll operation is allowed
16687  */
16688 #define PUF_ALLOW_ALLOWENROLL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
16689 
16690 #define PUF_ALLOW_ALLOWSTART_MASK                (0x2U)
16691 #define PUF_ALLOW_ALLOWSTART_SHIFT               (1U)
16692 /*! ALLOWSTART - Start operation is allowed
16693  */
16694 #define PUF_ALLOW_ALLOWSTART(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
16695 
16696 #define PUF_ALLOW_ALLOWSETKEY_MASK               (0x4U)
16697 #define PUF_ALLOW_ALLOWSETKEY_SHIFT              (2U)
16698 /*! ALLOWSETKEY - Set Key operations are allowed
16699  */
16700 #define PUF_ALLOW_ALLOWSETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
16701 
16702 #define PUF_ALLOW_ALLOWGETKEY_MASK               (0x8U)
16703 #define PUF_ALLOW_ALLOWGETKEY_SHIFT              (3U)
16704 /*! ALLOWGETKEY - Get Key operation is allowed
16705  */
16706 #define PUF_ALLOW_ALLOWGETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
16707 /*! @} */
16708 
16709 /*! @name KEYINPUT - PUF Key Input register */
16710 /*! @{ */
16711 
16712 #define PUF_KEYINPUT_KEYIN_MASK                  (0xFFFFFFFFU)
16713 #define PUF_KEYINPUT_KEYIN_SHIFT                 (0U)
16714 /*! KEYIN - Key input data
16715  */
16716 #define PUF_KEYINPUT_KEYIN(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
16717 /*! @} */
16718 
16719 /*! @name CODEINPUT - PUF Code Input register */
16720 /*! @{ */
16721 
16722 #define PUF_CODEINPUT_CODEIN_MASK                (0xFFFFFFFFU)
16723 #define PUF_CODEINPUT_CODEIN_SHIFT               (0U)
16724 /*! CODEIN - AC/KC input data
16725  */
16726 #define PUF_CODEINPUT_CODEIN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
16727 /*! @} */
16728 
16729 /*! @name CODEOUTPUT - PUF Code Output register */
16730 /*! @{ */
16731 
16732 #define PUF_CODEOUTPUT_CODEOUT_MASK              (0xFFFFFFFFU)
16733 #define PUF_CODEOUTPUT_CODEOUT_SHIFT             (0U)
16734 /*! CODEOUT - AC/KC output data
16735  */
16736 #define PUF_CODEOUTPUT_CODEOUT(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
16737 /*! @} */
16738 
16739 /*! @name KEYOUTINDEX - PUF Key Output Index register */
16740 /*! @{ */
16741 
16742 #define PUF_KEYOUTINDEX_KEYOUTIDX_MASK           (0xFU)
16743 #define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT          (0U)
16744 /*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register
16745  */
16746 #define PUF_KEYOUTINDEX_KEYOUTIDX(x)             (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
16747 /*! @} */
16748 
16749 /*! @name KEYOUTPUT - PUF Key Output register */
16750 /*! @{ */
16751 
16752 #define PUF_KEYOUTPUT_KEYOUT_MASK                (0xFFFFFFFFU)
16753 #define PUF_KEYOUTPUT_KEYOUT_SHIFT               (0U)
16754 /*! KEYOUT - Key output data
16755  */
16756 #define PUF_KEYOUTPUT_KEYOUT(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
16757 /*! @} */
16758 
16759 /*! @name IFSTAT - PUF Interface Status and clear register */
16760 /*! @{ */
16761 
16762 #define PUF_IFSTAT_ERROR_MASK                    (0x1U)
16763 #define PUF_IFSTAT_ERROR_SHIFT                   (0U)
16764 /*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit
16765  */
16766 #define PUF_IFSTAT_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
16767 /*! @} */
16768 
16769 /*! @name VERSION - PUF version register. */
16770 /*! @{ */
16771 
16772 #define PUF_VERSION_VERSION_MASK                 (0xFFFFFFFFU)
16773 #define PUF_VERSION_VERSION_SHIFT                (0U)
16774 /*! VERSION - Version of the PUF module.
16775  */
16776 #define PUF_VERSION_VERSION(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK)
16777 /*! @} */
16778 
16779 /*! @name INTEN - PUF Interrupt Enable */
16780 /*! @{ */
16781 
16782 #define PUF_INTEN_READYEN_MASK                   (0x1U)
16783 #define PUF_INTEN_READYEN_SHIFT                  (0U)
16784 /*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
16785  */
16786 #define PUF_INTEN_READYEN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
16787 
16788 #define PUF_INTEN_SUCCESEN_MASK                  (0x2U)
16789 #define PUF_INTEN_SUCCESEN_SHIFT                 (1U)
16790 /*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
16791  */
16792 #define PUF_INTEN_SUCCESEN(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK)
16793 
16794 #define PUF_INTEN_ERROREN_MASK                   (0x4U)
16795 #define PUF_INTEN_ERROREN_SHIFT                  (2U)
16796 /*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
16797  */
16798 #define PUF_INTEN_ERROREN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
16799 
16800 #define PUF_INTEN_KEYINREQEN_MASK                (0x10U)
16801 #define PUF_INTEN_KEYINREQEN_SHIFT               (4U)
16802 /*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
16803  */
16804 #define PUF_INTEN_KEYINREQEN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
16805 
16806 #define PUF_INTEN_KEYOUTAVAILEN_MASK             (0x20U)
16807 #define PUF_INTEN_KEYOUTAVAILEN_SHIFT            (5U)
16808 /*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
16809  */
16810 #define PUF_INTEN_KEYOUTAVAILEN(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
16811 
16812 #define PUF_INTEN_CODEINREQEN_MASK               (0x40U)
16813 #define PUF_INTEN_CODEINREQEN_SHIFT              (6U)
16814 /*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
16815  */
16816 #define PUF_INTEN_CODEINREQEN(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
16817 
16818 #define PUF_INTEN_CODEOUTAVAILEN_MASK            (0x80U)
16819 #define PUF_INTEN_CODEOUTAVAILEN_SHIFT           (7U)
16820 /*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
16821  */
16822 #define PUF_INTEN_CODEOUTAVAILEN(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
16823 /*! @} */
16824 
16825 /*! @name INTSTAT - PUF interrupt status */
16826 /*! @{ */
16827 
16828 #define PUF_INTSTAT_READY_MASK                   (0x1U)
16829 #define PUF_INTSTAT_READY_SHIFT                  (0U)
16830 /*! READY - Triggers on falling edge of busy, write 1 to clear
16831  */
16832 #define PUF_INTSTAT_READY(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
16833 
16834 #define PUF_INTSTAT_SUCCESS_MASK                 (0x2U)
16835 #define PUF_INTSTAT_SUCCESS_SHIFT                (1U)
16836 /*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears
16837  */
16838 #define PUF_INTSTAT_SUCCESS(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
16839 
16840 #define PUF_INTSTAT_ERROR_MASK                   (0x4U)
16841 #define PUF_INTSTAT_ERROR_SHIFT                  (2U)
16842 /*! ERROR - Level sensitive interrupt, cleared when interrupt source clears
16843  */
16844 #define PUF_INTSTAT_ERROR(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
16845 
16846 #define PUF_INTSTAT_KEYINREQ_MASK                (0x10U)
16847 #define PUF_INTSTAT_KEYINREQ_SHIFT               (4U)
16848 /*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears
16849  */
16850 #define PUF_INTSTAT_KEYINREQ(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
16851 
16852 #define PUF_INTSTAT_KEYOUTAVAIL_MASK             (0x20U)
16853 #define PUF_INTSTAT_KEYOUTAVAIL_SHIFT            (5U)
16854 /*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears
16855  */
16856 #define PUF_INTSTAT_KEYOUTAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
16857 
16858 #define PUF_INTSTAT_CODEINREQ_MASK               (0x40U)
16859 #define PUF_INTSTAT_CODEINREQ_SHIFT              (6U)
16860 /*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears
16861  */
16862 #define PUF_INTSTAT_CODEINREQ(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
16863 
16864 #define PUF_INTSTAT_CODEOUTAVAIL_MASK            (0x80U)
16865 #define PUF_INTSTAT_CODEOUTAVAIL_SHIFT           (7U)
16866 /*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears
16867  */
16868 #define PUF_INTSTAT_CODEOUTAVAIL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
16869 /*! @} */
16870 
16871 /*! @name PWRCTRL - PUF RAM Power Control */
16872 /*! @{ */
16873 
16874 #define PUF_PWRCTRL_RAMON_MASK                   (0x1U)
16875 #define PUF_PWRCTRL_RAMON_SHIFT                  (0U)
16876 /*! RAMON - Power on the PUF RAM.
16877  */
16878 #define PUF_PWRCTRL_RAMON(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK)
16879 
16880 #define PUF_PWRCTRL_RAMSTAT_MASK                 (0x2U)
16881 #define PUF_PWRCTRL_RAMSTAT_SHIFT                (1U)
16882 /*! RAMSTAT - PUF RAM status.
16883  */
16884 #define PUF_PWRCTRL_RAMSTAT(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK)
16885 /*! @} */
16886 
16887 /*! @name CFG - PUF config register for block bits */
16888 /*! @{ */
16889 
16890 #define PUF_CFG_BLOCKENROLL_SETKEY_MASK          (0x1U)
16891 #define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT         (0U)
16892 /*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset.
16893  */
16894 #define PUF_CFG_BLOCKENROLL_SETKEY(x)            (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK)
16895 
16896 #define PUF_CFG_BLOCKKEYOUTPUT_MASK              (0x2U)
16897 #define PUF_CFG_BLOCKKEYOUTPUT_SHIFT             (1U)
16898 /*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset.
16899  */
16900 #define PUF_CFG_BLOCKKEYOUTPUT(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK)
16901 /*! @} */
16902 
16903 /*! @name KEYLOCK - Only reset in case of full IC reset */
16904 /*! @{ */
16905 
16906 #define PUF_KEYLOCK_KEY0_MASK                    (0x3U)
16907 #define PUF_KEYLOCK_KEY0_SHIFT                   (0U)
16908 /*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01,
16909  *    11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once
16910  *    this field is written with a value different from '10', its value can no longer be modified
16911  *    until un Power On Reset occurs."
16912  */
16913 #define PUF_KEYLOCK_KEY0(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK)
16914 
16915 #define PUF_KEYLOCK_KEY1_MASK                    (0xCU)
16916 #define PUF_KEYLOCK_KEY1_SHIFT                   (2U)
16917 /*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01,
16918  *    11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once
16919  *    this field is written with a value different from '10', its value can no longer be modified
16920  *    until un Power On Reset occurs."
16921  */
16922 #define PUF_KEYLOCK_KEY1(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK)
16923 
16924 #define PUF_KEYLOCK_KEY2_MASK                    (0x30U)
16925 #define PUF_KEYLOCK_KEY2_SHIFT                   (4U)
16926 /*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01,
16927  *    11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once
16928  *    this field is written with a value different from '10', its value can no longer be modified
16929  *    until un Power On Reset occurs."
16930  */
16931 #define PUF_KEYLOCK_KEY2(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK)
16932 
16933 #define PUF_KEYLOCK_KEY3_MASK                    (0xC0U)
16934 #define PUF_KEYLOCK_KEY3_SHIFT                   (6U)
16935 /*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01,
16936  *    11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once
16937  *    this field is written with a value different from '10', its value can no longer be modified
16938  *    until un Power On Reset occurs."
16939  */
16940 #define PUF_KEYLOCK_KEY3(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK)
16941 /*! @} */
16942 
16943 /*! @name KEYENABLE -  */
16944 /*! @{ */
16945 
16946 #define PUF_KEYENABLE_KEY0_MASK                  (0x3U)
16947 #define PUF_KEYENABLE_KEY0_SHIFT                 (0U)
16948 /*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11
16949  *    : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register."
16950  */
16951 #define PUF_KEYENABLE_KEY0(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK)
16952 
16953 #define PUF_KEYENABLE_KEY1_MASK                  (0xCU)
16954 #define PUF_KEYENABLE_KEY1_SHIFT                 (2U)
16955 /*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11
16956  *    : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register."
16957  */
16958 #define PUF_KEYENABLE_KEY1(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK)
16959 
16960 #define PUF_KEYENABLE_KEY2_MASK                  (0x30U)
16961 #define PUF_KEYENABLE_KEY2_SHIFT                 (4U)
16962 /*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11
16963  *    : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register."
16964  */
16965 #define PUF_KEYENABLE_KEY2(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK)
16966 
16967 #define PUF_KEYENABLE_KEY3_MASK                  (0xC0U)
16968 #define PUF_KEYENABLE_KEY3_SHIFT                 (6U)
16969 /*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11
16970  *    : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register."
16971  */
16972 #define PUF_KEYENABLE_KEY3(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK)
16973 /*! @} */
16974 
16975 /*! @name KEYRESET - Reinitialize Keys shift registers counters */
16976 /*! @{ */
16977 
16978 #define PUF_KEYRESET_KEY0_MASK                   (0x3U)
16979 #define PUF_KEYRESET_KEY0_SHIFT                  (0U)
16980 /*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key.
16981  */
16982 #define PUF_KEYRESET_KEY0(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK)
16983 
16984 #define PUF_KEYRESET_KEY1_MASK                   (0xCU)
16985 #define PUF_KEYRESET_KEY1_SHIFT                  (2U)
16986 /*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key.
16987  */
16988 #define PUF_KEYRESET_KEY1(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK)
16989 
16990 #define PUF_KEYRESET_KEY2_MASK                   (0x30U)
16991 #define PUF_KEYRESET_KEY2_SHIFT                  (4U)
16992 /*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key.
16993  */
16994 #define PUF_KEYRESET_KEY2(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK)
16995 
16996 #define PUF_KEYRESET_KEY3_MASK                   (0xC0U)
16997 #define PUF_KEYRESET_KEY3_SHIFT                  (6U)
16998 /*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key.
16999  */
17000 #define PUF_KEYRESET_KEY3(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK)
17001 /*! @} */
17002 
17003 /*! @name IDXBLK_L -  */
17004 /*! @{ */
17005 
17006 #define PUF_IDXBLK_L_IDX1_MASK                   (0xCU)
17007 #define PUF_IDXBLK_L_IDX1_SHIFT                  (2U)
17008 /*! IDX1 - Use to block PUF index 1
17009  */
17010 #define PUF_IDXBLK_L_IDX1(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK)
17011 
17012 #define PUF_IDXBLK_L_IDX2_MASK                   (0x30U)
17013 #define PUF_IDXBLK_L_IDX2_SHIFT                  (4U)
17014 /*! IDX2 - Use to block PUF index 2
17015  */
17016 #define PUF_IDXBLK_L_IDX2(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK)
17017 
17018 #define PUF_IDXBLK_L_IDX3_MASK                   (0xC0U)
17019 #define PUF_IDXBLK_L_IDX3_SHIFT                  (6U)
17020 /*! IDX3 - Use to block PUF index 3
17021  */
17022 #define PUF_IDXBLK_L_IDX3(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK)
17023 
17024 #define PUF_IDXBLK_L_IDX4_MASK                   (0x300U)
17025 #define PUF_IDXBLK_L_IDX4_SHIFT                  (8U)
17026 /*! IDX4 - Use to block PUF index 4
17027  */
17028 #define PUF_IDXBLK_L_IDX4(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK)
17029 
17030 #define PUF_IDXBLK_L_IDX5_MASK                   (0xC00U)
17031 #define PUF_IDXBLK_L_IDX5_SHIFT                  (10U)
17032 /*! IDX5 - Use to block PUF index 5
17033  */
17034 #define PUF_IDXBLK_L_IDX5(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK)
17035 
17036 #define PUF_IDXBLK_L_IDX6_MASK                   (0x3000U)
17037 #define PUF_IDXBLK_L_IDX6_SHIFT                  (12U)
17038 /*! IDX6 - Use to block PUF index 6
17039  */
17040 #define PUF_IDXBLK_L_IDX6(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK)
17041 
17042 #define PUF_IDXBLK_L_IDX7_MASK                   (0xC000U)
17043 #define PUF_IDXBLK_L_IDX7_SHIFT                  (14U)
17044 /*! IDX7 - Use to block PUF index 7
17045  */
17046 #define PUF_IDXBLK_L_IDX7(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK)
17047 
17048 #define PUF_IDXBLK_L_LOCK_IDX_MASK               (0xC0000000U)
17049 #define PUF_IDXBLK_L_LOCK_IDX_SHIFT              (30U)
17050 /*! LOCK_IDX - Lock 0 to 7 PUF key indexes
17051  */
17052 #define PUF_IDXBLK_L_LOCK_IDX(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK)
17053 /*! @} */
17054 
17055 /*! @name IDXBLK_H_DP -  */
17056 /*! @{ */
17057 
17058 #define PUF_IDXBLK_H_DP_IDX8_MASK                (0x3U)
17059 #define PUF_IDXBLK_H_DP_IDX8_SHIFT               (0U)
17060 /*! IDX8 - Use to block PUF index 8
17061  */
17062 #define PUF_IDXBLK_H_DP_IDX8(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK)
17063 
17064 #define PUF_IDXBLK_H_DP_IDX9_MASK                (0xCU)
17065 #define PUF_IDXBLK_H_DP_IDX9_SHIFT               (2U)
17066 /*! IDX9 - Use to block PUF index 9
17067  */
17068 #define PUF_IDXBLK_H_DP_IDX9(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
17069 
17070 #define PUF_IDXBLK_H_DP_IDX10_MASK               (0x30U)
17071 #define PUF_IDXBLK_H_DP_IDX10_SHIFT              (4U)
17072 /*! IDX10 - Use to block PUF index 10
17073  */
17074 #define PUF_IDXBLK_H_DP_IDX10(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK)
17075 
17076 #define PUF_IDXBLK_H_DP_IDX11_MASK               (0xC0U)
17077 #define PUF_IDXBLK_H_DP_IDX11_SHIFT              (6U)
17078 /*! IDX11 - Use to block PUF index 11
17079  */
17080 #define PUF_IDXBLK_H_DP_IDX11(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK)
17081 
17082 #define PUF_IDXBLK_H_DP_IDX12_MASK               (0x300U)
17083 #define PUF_IDXBLK_H_DP_IDX12_SHIFT              (8U)
17084 /*! IDX12 - Use to block PUF index 12
17085  */
17086 #define PUF_IDXBLK_H_DP_IDX12(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK)
17087 
17088 #define PUF_IDXBLK_H_DP_IDX13_MASK               (0xC00U)
17089 #define PUF_IDXBLK_H_DP_IDX13_SHIFT              (10U)
17090 /*! IDX13 - Use to block PUF index 13
17091  */
17092 #define PUF_IDXBLK_H_DP_IDX13(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK)
17093 
17094 #define PUF_IDXBLK_H_DP_IDX14_MASK               (0x3000U)
17095 #define PUF_IDXBLK_H_DP_IDX14_SHIFT              (12U)
17096 /*! IDX14 - Use to block PUF index 14
17097  */
17098 #define PUF_IDXBLK_H_DP_IDX14(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK)
17099 
17100 #define PUF_IDXBLK_H_DP_IDX15_MASK               (0xC000U)
17101 #define PUF_IDXBLK_H_DP_IDX15_SHIFT              (14U)
17102 /*! IDX15 - Use to block PUF index 15
17103  */
17104 #define PUF_IDXBLK_H_DP_IDX15(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK)
17105 /*! @} */
17106 
17107 /*! @name KEYMASK - Only reset in case of full IC reset */
17108 /*! @{ */
17109 
17110 #define PUF_KEYMASK_KEYMASK_MASK                 (0xFFFFFFFFU)
17111 #define PUF_KEYMASK_KEYMASK_SHIFT                (0U)
17112 #define PUF_KEYMASK_KEYMASK(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
17113 /*! @} */
17114 
17115 /* The count of PUF_KEYMASK */
17116 #define PUF_KEYMASK_COUNT                        (4U)
17117 
17118 /*! @name IDXBLK_H -  */
17119 /*! @{ */
17120 
17121 #define PUF_IDXBLK_H_IDX8_MASK                   (0x3U)
17122 #define PUF_IDXBLK_H_IDX8_SHIFT                  (0U)
17123 /*! IDX8 - Use to block PUF index 8
17124  */
17125 #define PUF_IDXBLK_H_IDX8(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK)
17126 
17127 #define PUF_IDXBLK_H_IDX9_MASK                   (0xCU)
17128 #define PUF_IDXBLK_H_IDX9_SHIFT                  (2U)
17129 /*! IDX9 - Use to block PUF index 9
17130  */
17131 #define PUF_IDXBLK_H_IDX9(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK)
17132 
17133 #define PUF_IDXBLK_H_IDX10_MASK                  (0x30U)
17134 #define PUF_IDXBLK_H_IDX10_SHIFT                 (4U)
17135 /*! IDX10 - Use to block PUF index 10
17136  */
17137 #define PUF_IDXBLK_H_IDX10(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK)
17138 
17139 #define PUF_IDXBLK_H_IDX11_MASK                  (0xC0U)
17140 #define PUF_IDXBLK_H_IDX11_SHIFT                 (6U)
17141 /*! IDX11 - Use to block PUF index 11
17142  */
17143 #define PUF_IDXBLK_H_IDX11(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK)
17144 
17145 #define PUF_IDXBLK_H_IDX12_MASK                  (0x300U)
17146 #define PUF_IDXBLK_H_IDX12_SHIFT                 (8U)
17147 /*! IDX12 - Use to block PUF index 12
17148  */
17149 #define PUF_IDXBLK_H_IDX12(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK)
17150 
17151 #define PUF_IDXBLK_H_IDX13_MASK                  (0xC00U)
17152 #define PUF_IDXBLK_H_IDX13_SHIFT                 (10U)
17153 /*! IDX13 - Use to block PUF index 13
17154  */
17155 #define PUF_IDXBLK_H_IDX13(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK)
17156 
17157 #define PUF_IDXBLK_H_IDX14_MASK                  (0x3000U)
17158 #define PUF_IDXBLK_H_IDX14_SHIFT                 (12U)
17159 /*! IDX14 - Use to block PUF index 14
17160  */
17161 #define PUF_IDXBLK_H_IDX14(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK)
17162 
17163 #define PUF_IDXBLK_H_IDX15_MASK                  (0xC000U)
17164 #define PUF_IDXBLK_H_IDX15_SHIFT                 (14U)
17165 /*! IDX15 - Use to block PUF index 15
17166  */
17167 #define PUF_IDXBLK_H_IDX15(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK)
17168 
17169 #define PUF_IDXBLK_H_LOCK_IDX_MASK               (0xC0000000U)
17170 #define PUF_IDXBLK_H_LOCK_IDX_SHIFT              (30U)
17171 /*! LOCK_IDX - Lock 8 to 15 PUF key indexes
17172  */
17173 #define PUF_IDXBLK_H_LOCK_IDX(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK)
17174 /*! @} */
17175 
17176 /*! @name IDXBLK_L_DP -  */
17177 /*! @{ */
17178 
17179 #define PUF_IDXBLK_L_DP_IDX1_MASK                (0xCU)
17180 #define PUF_IDXBLK_L_DP_IDX1_SHIFT               (2U)
17181 /*! IDX1 - Use to block PUF index 1
17182  */
17183 #define PUF_IDXBLK_L_DP_IDX1(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK)
17184 
17185 #define PUF_IDXBLK_L_DP_IDX2_MASK                (0x30U)
17186 #define PUF_IDXBLK_L_DP_IDX2_SHIFT               (4U)
17187 /*! IDX2 - Use to block PUF index 2
17188  */
17189 #define PUF_IDXBLK_L_DP_IDX2(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK)
17190 
17191 #define PUF_IDXBLK_L_DP_IDX3_MASK                (0xC0U)
17192 #define PUF_IDXBLK_L_DP_IDX3_SHIFT               (6U)
17193 /*! IDX3 - Use to block PUF index 3
17194  */
17195 #define PUF_IDXBLK_L_DP_IDX3(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK)
17196 
17197 #define PUF_IDXBLK_L_DP_IDX4_MASK                (0x300U)
17198 #define PUF_IDXBLK_L_DP_IDX4_SHIFT               (8U)
17199 /*! IDX4 - Use to block PUF index 4
17200  */
17201 #define PUF_IDXBLK_L_DP_IDX4(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK)
17202 
17203 #define PUF_IDXBLK_L_DP_IDX5_MASK                (0xC00U)
17204 #define PUF_IDXBLK_L_DP_IDX5_SHIFT               (10U)
17205 /*! IDX5 - Use to block PUF index 5
17206  */
17207 #define PUF_IDXBLK_L_DP_IDX5(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
17208 
17209 #define PUF_IDXBLK_L_DP_IDX6_MASK                (0x3000U)
17210 #define PUF_IDXBLK_L_DP_IDX6_SHIFT               (12U)
17211 /*! IDX6 - Use to block PUF index 6
17212  */
17213 #define PUF_IDXBLK_L_DP_IDX6(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK)
17214 
17215 #define PUF_IDXBLK_L_DP_IDX7_MASK                (0xC000U)
17216 #define PUF_IDXBLK_L_DP_IDX7_SHIFT               (14U)
17217 /*! IDX7 - Use to block PUF index 7
17218  */
17219 #define PUF_IDXBLK_L_DP_IDX7(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK)
17220 /*! @} */
17221 
17222 /*! @name SHIFT_STATUS -  */
17223 /*! @{ */
17224 
17225 #define PUF_SHIFT_STATUS_KEY0_MASK               (0xFU)
17226 #define PUF_SHIFT_STATUS_KEY0_SHIFT              (0U)
17227 /*! KEY0 - Index counter from key 0 shift register
17228  */
17229 #define PUF_SHIFT_STATUS_KEY0(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK)
17230 
17231 #define PUF_SHIFT_STATUS_KEY1_MASK               (0xF0U)
17232 #define PUF_SHIFT_STATUS_KEY1_SHIFT              (4U)
17233 /*! KEY1 - Index counter from key 1 shift register
17234  */
17235 #define PUF_SHIFT_STATUS_KEY1(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK)
17236 
17237 #define PUF_SHIFT_STATUS_KEY2_MASK               (0xF00U)
17238 #define PUF_SHIFT_STATUS_KEY2_SHIFT              (8U)
17239 /*! KEY2 - Index counter from key 2 shift register
17240  */
17241 #define PUF_SHIFT_STATUS_KEY2(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK)
17242 
17243 #define PUF_SHIFT_STATUS_KEY3_MASK               (0xF000U)
17244 #define PUF_SHIFT_STATUS_KEY3_SHIFT              (12U)
17245 /*! KEY3 - Index counter from key 3 shift register
17246  */
17247 #define PUF_SHIFT_STATUS_KEY3(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK)
17248 /*! @} */
17249 
17250 
17251 /*!
17252  * @}
17253  */ /* end of group PUF_Register_Masks */
17254 
17255 
17256 /* PUF - Peripheral instance base addresses */
17257 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
17258   /** Peripheral PUF base address */
17259   #define PUF_BASE                                 (0x5003B000u)
17260   /** Peripheral PUF base address */
17261   #define PUF_BASE_NS                              (0x4003B000u)
17262   /** Peripheral PUF base pointer */
17263   #define PUF                                      ((PUF_Type *)PUF_BASE)
17264   /** Peripheral PUF base pointer */
17265   #define PUF_NS                                   ((PUF_Type *)PUF_BASE_NS)
17266   /** Array initializer of PUF peripheral base addresses */
17267   #define PUF_BASE_ADDRS                           { PUF_BASE }
17268   /** Array initializer of PUF peripheral base pointers */
17269   #define PUF_BASE_PTRS                            { PUF }
17270   /** Array initializer of PUF peripheral base addresses */
17271   #define PUF_BASE_ADDRS_NS                        { PUF_BASE_NS }
17272   /** Array initializer of PUF peripheral base pointers */
17273   #define PUF_BASE_PTRS_NS                         { PUF_NS }
17274 #else
17275   /** Peripheral PUF base address */
17276   #define PUF_BASE                                 (0x4003B000u)
17277   /** Peripheral PUF base pointer */
17278   #define PUF                                      ((PUF_Type *)PUF_BASE)
17279   /** Array initializer of PUF peripheral base addresses */
17280   #define PUF_BASE_ADDRS                           { PUF_BASE }
17281   /** Array initializer of PUF peripheral base pointers */
17282   #define PUF_BASE_PTRS                            { PUF }
17283 #endif
17284 /** Interrupt vectors for the PUF peripheral type */
17285 #define PUF_IRQS                                 { PUF_IRQn }
17286 
17287 /*!
17288  * @}
17289  */ /* end of group PUF_Peripheral_Access_Layer */
17290 
17291 
17292 /* ----------------------------------------------------------------------------
17293    -- RNG Peripheral Access Layer
17294    ---------------------------------------------------------------------------- */
17295 
17296 /*!
17297  * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
17298  * @{
17299  */
17300 
17301 /** RNG - Register Layout Typedef */
17302 typedef struct {
17303   __I  uint32_t RANDOM_NUMBER;                     /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */
17304        uint8_t RESERVED_0[4];
17305   __I  uint32_t COUNTER_VAL;                       /**< , offset: 0x8 */
17306   __IO uint32_t COUNTER_CFG;                       /**< , offset: 0xC */
17307   __IO uint32_t ONLINE_TEST_CFG;                   /**< , offset: 0x10 */
17308   __I  uint32_t ONLINE_TEST_VAL;                   /**< , offset: 0x14 */
17309        uint8_t RESERVED_1[4068];
17310   __I  uint32_t MODULEID;                          /**< IP identifier, offset: 0xFFC */
17311 } RNG_Type;
17312 
17313 /* ----------------------------------------------------------------------------
17314    -- RNG Register Masks
17315    ---------------------------------------------------------------------------- */
17316 
17317 /*!
17318  * @addtogroup RNG_Register_Masks RNG Register Masks
17319  * @{
17320  */
17321 
17322 /*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */
17323 /*! @{ */
17324 
17325 #define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK     (0xFFFFFFFFU)
17326 #define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT    (0U)
17327 /*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read.
17328  */
17329 #define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x)       (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK)
17330 /*! @} */
17331 
17332 /*! @name COUNTER_VAL -  */
17333 /*! @{ */
17334 
17335 #define RNG_COUNTER_VAL_CLK_RATIO_MASK           (0xFFU)
17336 #define RNG_COUNTER_VAL_CLK_RATIO_SHIFT          (0U)
17337 /*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock
17338  *    frequency for evaluation and certification purposes.
17339  */
17340 #define RNG_COUNTER_VAL_CLK_RATIO(x)             (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK)
17341 
17342 #define RNG_COUNTER_VAL_REFRESH_CNT_MASK         (0x1F00U)
17343 #define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT        (8U)
17344 /*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER.
17345  */
17346 #define RNG_COUNTER_VAL_REFRESH_CNT(x)           (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK)
17347 /*! @} */
17348 
17349 /*! @name COUNTER_CFG -  */
17350 /*! @{ */
17351 
17352 #define RNG_COUNTER_CFG_MODE_MASK                (0x3U)
17353 #define RNG_COUNTER_CFG_MODE_SHIFT               (0U)
17354 /*! MODE - 00: disabled 01: update once.
17355  */
17356 #define RNG_COUNTER_CFG_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK)
17357 
17358 #define RNG_COUNTER_CFG_CLOCK_SEL_MASK           (0x1CU)
17359 #define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT          (2U)
17360 /*! CLOCK_SEL - Selects the internal clock on which to compute statistics.
17361  */
17362 #define RNG_COUNTER_CFG_CLOCK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK)
17363 
17364 #define RNG_COUNTER_CFG_SHIFT4X_MASK             (0xE0U)
17365 #define RNG_COUNTER_CFG_SHIFT4X_SHIFT            (5U)
17366 /*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'.
17367  */
17368 #define RNG_COUNTER_CFG_SHIFT4X(x)               (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK)
17369 /*! @} */
17370 
17371 /*! @name ONLINE_TEST_CFG -  */
17372 /*! @{ */
17373 
17374 #define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK        (0x1U)
17375 #define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT       (0U)
17376 /*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER.
17377  */
17378 #define RNG_ONLINE_TEST_CFG_ACTIVATE(x)          (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK)
17379 
17380 #define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK        (0x6U)
17381 #define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT       (1U)
17382 /*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one
17383  *    or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10:
17384  *    RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this
17385  *    field.
17386  */
17387 #define RNG_ONLINE_TEST_CFG_DATA_SEL(x)          (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK)
17388 /*! @} */
17389 
17390 /*! @name ONLINE_TEST_VAL -  */
17391 /*! @{ */
17392 
17393 #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU)
17394 #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U)
17395 /*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'.
17396  */
17397 #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x)  (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK)
17398 
17399 #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U)
17400 #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U)
17401 /*! MIN_CHI_SQUARED - This field is reset when 'activate'==0.
17402  */
17403 #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x)   (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK)
17404 
17405 #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U)
17406 #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U)
17407 /*! MAX_CHI_SQUARED - This field is reset when 'activate'==0.
17408  */
17409 #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x)   (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK)
17410 /*! @} */
17411 
17412 /*! @name MODULEID - IP identifier */
17413 /*! @{ */
17414 
17415 #define RNG_MODULEID_APERTURE_MASK               (0xFFU)
17416 #define RNG_MODULEID_APERTURE_SHIFT              (0U)
17417 /*! APERTURE - Aperture i.
17418  */
17419 #define RNG_MODULEID_APERTURE(x)                 (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK)
17420 
17421 #define RNG_MODULEID_MIN_REV_MASK                (0xF00U)
17422 #define RNG_MODULEID_MIN_REV_SHIFT               (8U)
17423 /*! MIN_REV - Minor revision i.
17424  */
17425 #define RNG_MODULEID_MIN_REV(x)                  (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK)
17426 
17427 #define RNG_MODULEID_MAJ_REV_MASK                (0xF000U)
17428 #define RNG_MODULEID_MAJ_REV_SHIFT               (12U)
17429 /*! MAJ_REV - Major revision i.
17430  */
17431 #define RNG_MODULEID_MAJ_REV(x)                  (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK)
17432 
17433 #define RNG_MODULEID_ID_MASK                     (0xFFFF0000U)
17434 #define RNG_MODULEID_ID_SHIFT                    (16U)
17435 /*! ID - Identifier.
17436  */
17437 #define RNG_MODULEID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK)
17438 /*! @} */
17439 
17440 
17441 /*!
17442  * @}
17443  */ /* end of group RNG_Register_Masks */
17444 
17445 
17446 /* RNG - Peripheral instance base addresses */
17447 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
17448   /** Peripheral RNG base address */
17449   #define RNG_BASE                                 (0x5003A000u)
17450   /** Peripheral RNG base address */
17451   #define RNG_BASE_NS                              (0x4003A000u)
17452   /** Peripheral RNG base pointer */
17453   #define RNG                                      ((RNG_Type *)RNG_BASE)
17454   /** Peripheral RNG base pointer */
17455   #define RNG_NS                                   ((RNG_Type *)RNG_BASE_NS)
17456   /** Array initializer of RNG peripheral base addresses */
17457   #define RNG_BASE_ADDRS                           { RNG_BASE }
17458   /** Array initializer of RNG peripheral base pointers */
17459   #define RNG_BASE_PTRS                            { RNG }
17460   /** Array initializer of RNG peripheral base addresses */
17461   #define RNG_BASE_ADDRS_NS                        { RNG_BASE_NS }
17462   /** Array initializer of RNG peripheral base pointers */
17463   #define RNG_BASE_PTRS_NS                         { RNG_NS }
17464 #else
17465   /** Peripheral RNG base address */
17466   #define RNG_BASE                                 (0x4003A000u)
17467   /** Peripheral RNG base pointer */
17468   #define RNG                                      ((RNG_Type *)RNG_BASE)
17469   /** Array initializer of RNG peripheral base addresses */
17470   #define RNG_BASE_ADDRS                           { RNG_BASE }
17471   /** Array initializer of RNG peripheral base pointers */
17472   #define RNG_BASE_PTRS                            { RNG }
17473 #endif
17474 
17475 /*!
17476  * @}
17477  */ /* end of group RNG_Peripheral_Access_Layer */
17478 
17479 
17480 /* ----------------------------------------------------------------------------
17481    -- RTC Peripheral Access Layer
17482    ---------------------------------------------------------------------------- */
17483 
17484 /*!
17485  * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
17486  * @{
17487  */
17488 
17489 /** RTC - Register Layout Typedef */
17490 typedef struct {
17491   __IO uint32_t CTRL;                              /**< RTC control register, offset: 0x0 */
17492   __IO uint32_t MATCH;                             /**< RTC match register, offset: 0x4 */
17493   __IO uint32_t COUNT;                             /**< RTC counter register, offset: 0x8 */
17494   __IO uint32_t WAKE;                              /**< High-resolution/wake-up timer control register, offset: 0xC */
17495   __I  uint32_t SUBSEC;                            /**< Sub-second counter register, offset: 0x10 */
17496        uint8_t RESERVED_0[44];
17497   __IO uint32_t GPREG[8];                          /**< General Purpose register, array offset: 0x40, array step: 0x4 */
17498 } RTC_Type;
17499 
17500 /* ----------------------------------------------------------------------------
17501    -- RTC Register Masks
17502    ---------------------------------------------------------------------------- */
17503 
17504 /*!
17505  * @addtogroup RTC_Register_Masks RTC Register Masks
17506  * @{
17507  */
17508 
17509 /*! @name CTRL - RTC control register */
17510 /*! @{ */
17511 
17512 #define RTC_CTRL_SWRESET_MASK                    (0x1U)
17513 #define RTC_CTRL_SWRESET_SHIFT                   (0U)
17514 /*! SWRESET - Software reset control
17515  *  0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.
17516  *  0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value
17517  *       except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes
17518  *       to set any of the other bits within this register. Do not attempt to write to any bits of this register at
17519  *       the same time that the reset bit is being cleared.
17520  */
17521 #define RTC_CTRL_SWRESET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
17522 
17523 #define RTC_CTRL_ALARM1HZ_MASK                   (0x4U)
17524 #define RTC_CTRL_ALARM1HZ_SHIFT                  (2U)
17525 /*! ALARM1HZ - RTC 1 Hz timer alarm flag status.
17526  *  0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
17527  *  0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt
17528  *       request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.
17529  */
17530 #define RTC_CTRL_ALARM1HZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
17531 
17532 #define RTC_CTRL_WAKE1KHZ_MASK                   (0x8U)
17533 #define RTC_CTRL_WAKE1KHZ_SHIFT                  (3U)
17534 /*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status.
17535  *  0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
17536  *  0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up
17537  *       interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.
17538  */
17539 #define RTC_CTRL_WAKE1KHZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
17540 
17541 #define RTC_CTRL_ALARMDPD_EN_MASK                (0x10U)
17542 #define RTC_CTRL_ALARMDPD_EN_SHIFT               (4U)
17543 /*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down.
17544  *  0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.
17545  *  0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.
17546  */
17547 #define RTC_CTRL_ALARMDPD_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
17548 
17549 #define RTC_CTRL_WAKEDPD_EN_MASK                 (0x20U)
17550 #define RTC_CTRL_WAKEDPD_EN_SHIFT                (5U)
17551 /*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down.
17552  *  0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
17553  *  0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.
17554  */
17555 #define RTC_CTRL_WAKEDPD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
17556 
17557 #define RTC_CTRL_RTC1KHZ_EN_MASK                 (0x40U)
17558 #define RTC_CTRL_RTC1KHZ_EN_SHIFT                (6U)
17559 /*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz
17560  *    timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
17561  *  0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
17562  *  0b1..Enable. The 1 kHz RTC timer is enabled.
17563  */
17564 #define RTC_CTRL_RTC1KHZ_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
17565 
17566 #define RTC_CTRL_RTC_EN_MASK                     (0x80U)
17567 #define RTC_CTRL_RTC_EN_SHIFT                    (7U)
17568 /*! RTC_EN - RTC enable.
17569  *  0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should
17570  *       be 0 when writing to load a value in the RTC counter register.
17571  *  0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate
17572  *       operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the
17573  *       high-resolution, 1 kHz clock, set bit 6 in this register.
17574  */
17575 #define RTC_CTRL_RTC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
17576 
17577 #define RTC_CTRL_RTC_OSC_PD_MASK                 (0x100U)
17578 #define RTC_CTRL_RTC_OSC_PD_SHIFT                (8U)
17579 /*! RTC_OSC_PD - RTC oscillator power-down control.
17580  *  0b0..See RTC_OSC_BYPASS
17581  *  0b1..RTC oscillator is powered-down.
17582  */
17583 #define RTC_CTRL_RTC_OSC_PD(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
17584 
17585 #define RTC_CTRL_RTC_OSC_BYPASS_MASK             (0x200U)
17586 #define RTC_CTRL_RTC_OSC_BYPASS_SHIFT            (9U)
17587 /*! RTC_OSC_BYPASS - RTC oscillator bypass control.
17588  *  0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins.
17589  *  0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin.
17590  */
17591 #define RTC_CTRL_RTC_OSC_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK)
17592 
17593 #define RTC_CTRL_RTC_SUBSEC_ENA_MASK             (0x400U)
17594 #define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT            (10U)
17595 /*! RTC_SUBSEC_ENA - RTC Sub-second counter control.
17596  *  0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD
17597  *       reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second
17598  *       counter, this bit will always read-back as a '0'.
17599  *  0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first
17600  *       one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is
17601  *       set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip
17602  *       exits deep power-down mode.
17603  */
17604 #define RTC_CTRL_RTC_SUBSEC_ENA(x)               (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK)
17605 /*! @} */
17606 
17607 /*! @name MATCH - RTC match register */
17608 /*! @{ */
17609 
17610 #define RTC_MATCH_MATVAL_MASK                    (0xFFFFFFFFU)
17611 #define RTC_MATCH_MATVAL_SHIFT                   (0U)
17612 /*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the
17613  *    alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.
17614  */
17615 #define RTC_MATCH_MATVAL(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
17616 /*! @} */
17617 
17618 /*! @name COUNT - RTC counter register */
17619 /*! @{ */
17620 
17621 #define RTC_COUNT_VAL_MASK                       (0xFFFFFFFFU)
17622 #define RTC_COUNT_VAL_SHIFT                      (0U)
17623 /*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial
17624  *    value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC
17625  *    Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this
17626  *    register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after
17627  *    the RTC_EN bit is set.
17628  */
17629 #define RTC_COUNT_VAL(x)                         (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
17630 /*! @} */
17631 
17632 /*! @name WAKE - High-resolution/wake-up timer control register */
17633 /*! @{ */
17634 
17635 #define RTC_WAKE_VAL_MASK                        (0xFFFFU)
17636 #define RTC_WAKE_VAL_SHIFT                       (0U)
17637 /*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads
17638  *    a start count value into the wake-up timer and initializes a count-down sequence. Do not write
17639  *    to this register while counting is in progress.
17640  */
17641 #define RTC_WAKE_VAL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
17642 /*! @} */
17643 
17644 /*! @name SUBSEC - Sub-second counter register */
17645 /*! @{ */
17646 
17647 #define RTC_SUBSEC_SUBSEC_MASK                   (0x7FFFU)
17648 #define RTC_SUBSEC_SUBSEC_SHIFT                  (0U)
17649 /*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is
17650  *    cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz
17651  *    rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This
17652  *    counter must be re-enabled after exiting deep power-down mode or after the main RTC module is
17653  *    disabled and re-enabled. On modules not equipped with a sub-second counter, this register
17654  *    will read-back as all zeroes.
17655  */
17656 #define RTC_SUBSEC_SUBSEC(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK)
17657 /*! @} */
17658 
17659 /*! @name GPREG - General Purpose register */
17660 /*! @{ */
17661 
17662 #define RTC_GPREG_GPDATA_MASK                    (0xFFFFFFFFU)
17663 #define RTC_GPREG_GPDATA_SHIFT                   (0U)
17664 /*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
17665  */
17666 #define RTC_GPREG_GPDATA(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
17667 /*! @} */
17668 
17669 /* The count of RTC_GPREG */
17670 #define RTC_GPREG_COUNT                          (8U)
17671 
17672 
17673 /*!
17674  * @}
17675  */ /* end of group RTC_Register_Masks */
17676 
17677 
17678 /* RTC - Peripheral instance base addresses */
17679 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
17680   /** Peripheral RTC base address */
17681   #define RTC_BASE                                 (0x5002C000u)
17682   /** Peripheral RTC base address */
17683   #define RTC_BASE_NS                              (0x4002C000u)
17684   /** Peripheral RTC base pointer */
17685   #define RTC                                      ((RTC_Type *)RTC_BASE)
17686   /** Peripheral RTC base pointer */
17687   #define RTC_NS                                   ((RTC_Type *)RTC_BASE_NS)
17688   /** Array initializer of RTC peripheral base addresses */
17689   #define RTC_BASE_ADDRS                           { RTC_BASE }
17690   /** Array initializer of RTC peripheral base pointers */
17691   #define RTC_BASE_PTRS                            { RTC }
17692   /** Array initializer of RTC peripheral base addresses */
17693   #define RTC_BASE_ADDRS_NS                        { RTC_BASE_NS }
17694   /** Array initializer of RTC peripheral base pointers */
17695   #define RTC_BASE_PTRS_NS                         { RTC_NS }
17696 #else
17697   /** Peripheral RTC base address */
17698   #define RTC_BASE                                 (0x4002C000u)
17699   /** Peripheral RTC base pointer */
17700   #define RTC                                      ((RTC_Type *)RTC_BASE)
17701   /** Array initializer of RTC peripheral base addresses */
17702   #define RTC_BASE_ADDRS                           { RTC_BASE }
17703   /** Array initializer of RTC peripheral base pointers */
17704   #define RTC_BASE_PTRS                            { RTC }
17705 #endif
17706 /** Interrupt vectors for the RTC peripheral type */
17707 #define RTC_IRQS                                 { RTC_IRQn }
17708 
17709 /*!
17710  * @}
17711  */ /* end of group RTC_Peripheral_Access_Layer */
17712 
17713 
17714 /* ----------------------------------------------------------------------------
17715    -- SCT Peripheral Access Layer
17716    ---------------------------------------------------------------------------- */
17717 
17718 /*!
17719  * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
17720  * @{
17721  */
17722 
17723 /** SCT - Register Layout Typedef */
17724 typedef struct {
17725   __IO uint32_t CONFIG;                            /**< SCT configuration register, offset: 0x0 */
17726   union {                                          /* offset: 0x4 */
17727     struct {                                         /* offset: 0x4 */
17728       __IO uint16_t CTRLL;                             /**< SCT_CTRLL register, offset: 0x4 */
17729       __IO uint16_t CTRLH;                             /**< SCT_CTRLH register, offset: 0x6 */
17730     } CTRL_ACCESS16BIT;
17731     __IO uint32_t CTRL;                              /**< SCT control register, offset: 0x4 */
17732   };
17733   union {                                          /* offset: 0x8 */
17734     struct {                                         /* offset: 0x8 */
17735       __IO uint16_t LIMITL;                            /**< SCT_LIMITL register, offset: 0x8 */
17736       __IO uint16_t LIMITH;                            /**< SCT_LIMITH register, offset: 0xA */
17737     } LIMIT_ACCESS16BIT;
17738     __IO uint32_t LIMIT;                             /**< SCT limit event select register, offset: 0x8 */
17739   };
17740   union {                                          /* offset: 0xC */
17741     struct {                                         /* offset: 0xC */
17742       __IO uint16_t HALTL;                             /**< SCT_HALTL register, offset: 0xC */
17743       __IO uint16_t HALTH;                             /**< SCT_HALTH register, offset: 0xE */
17744     } HALT_ACCESS16BIT;
17745     __IO uint32_t HALT;                              /**< SCT halt event select register, offset: 0xC */
17746   };
17747   union {                                          /* offset: 0x10 */
17748     struct {                                         /* offset: 0x10 */
17749       __IO uint16_t STOPL;                             /**< SCT_STOPL register, offset: 0x10 */
17750       __IO uint16_t STOPH;                             /**< SCT_STOPH register, offset: 0x12 */
17751     } STOP_ACCESS16BIT;
17752     __IO uint32_t STOP;                              /**< SCT stop event select register, offset: 0x10 */
17753   };
17754   union {                                          /* offset: 0x14 */
17755     struct {                                         /* offset: 0x14 */
17756       __IO uint16_t STARTL;                            /**< SCT_STARTL register, offset: 0x14 */
17757       __IO uint16_t STARTH;                            /**< SCT_STARTH register, offset: 0x16 */
17758     } START_ACCESS16BIT;
17759     __IO uint32_t START;                             /**< SCT start event select register, offset: 0x14 */
17760   };
17761        uint8_t RESERVED_0[40];
17762   union {                                          /* offset: 0x40 */
17763     struct {                                         /* offset: 0x40 */
17764       __IO uint16_t COUNTL;                            /**< SCT_COUNTL register, offset: 0x40 */
17765       __IO uint16_t COUNTH;                            /**< SCT_COUNTH register, offset: 0x42 */
17766     } COUNT_ACCESS16BIT;
17767     __IO uint32_t COUNT;                             /**< SCT counter register, offset: 0x40 */
17768   };
17769   union {                                          /* offset: 0x44 */
17770     struct {                                         /* offset: 0x44 */
17771       __IO uint16_t STATEL;                            /**< SCT_STATEL register, offset: 0x44 */
17772       __IO uint16_t STATEH;                            /**< SCT_STATEH register, offset: 0x46 */
17773     } STATE_ACCESS16BIT;
17774     __IO uint32_t STATE;                             /**< SCT state register, offset: 0x44 */
17775   };
17776   __I  uint32_t INPUT;                             /**< SCT input register, offset: 0x48 */
17777   union {                                          /* offset: 0x4C */
17778     struct {                                         /* offset: 0x4C */
17779       __IO uint16_t REGMODEL;                          /**< SCT_REGMODEL register, offset: 0x4C */
17780       __IO uint16_t REGMODEH;                          /**< SCT_REGMODEH register, offset: 0x4E */
17781     } REGMODE_ACCESS16BIT;
17782     __IO uint32_t REGMODE;                           /**< SCT match/capture mode register, offset: 0x4C */
17783   };
17784   __IO uint32_t OUTPUT;                            /**< SCT output register, offset: 0x50 */
17785   __IO uint32_t OUTPUTDIRCTRL;                     /**< SCT output counter direction control register, offset: 0x54 */
17786   __IO uint32_t RES;                               /**< SCT conflict resolution register, offset: 0x58 */
17787   __IO uint32_t DMAREQ0;                           /**< SCT DMA request 0 register, offset: 0x5C */
17788   __IO uint32_t DMAREQ1;                           /**< SCT DMA request 1 register, offset: 0x60 */
17789        uint8_t RESERVED_1[140];
17790   __IO uint32_t EVEN;                              /**< SCT event interrupt enable register, offset: 0xF0 */
17791   __IO uint32_t EVFLAG;                            /**< SCT event flag register, offset: 0xF4 */
17792   __IO uint32_t CONEN;                             /**< SCT conflict interrupt enable register, offset: 0xF8 */
17793   __IO uint32_t CONFLAG;                           /**< SCT conflict flag register, offset: 0xFC */
17794   union {                                          /* offset: 0x100 */
17795     union {                                          /* offset: 0x100, array step: 0x4 */
17796       struct {                                         /* offset: 0x100, array step: 0x4 */
17797         __IO uint16_t CAPL;                              /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
17798         __IO uint16_t CAPH;                              /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
17799       } CAP_ACCESS16BIT[16];
17800       __IO uint32_t CAP[16];                           /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
17801     };
17802     union {                                          /* offset: 0x100, array step: 0x4 */
17803       struct {                                         /* offset: 0x100, array step: 0x4 */
17804         __IO uint16_t MATCHL;                            /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
17805         __IO uint16_t MATCHH;                            /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
17806       } MATCH_ACCESS16BIT[16];
17807       __IO uint32_t MATCH[16];                         /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
17808     };
17809   };
17810        uint8_t RESERVED_2[192];
17811   union {                                          /* offset: 0x200 */
17812     union {                                          /* offset: 0x200, array step: 0x4 */
17813       struct {                                         /* offset: 0x200, array step: 0x4 */
17814         __IO uint16_t CAPCTRLL;                          /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
17815         __IO uint16_t CAPCTRLH;                          /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
17816       } CAPCTRL_ACCESS16BIT[16];
17817       __IO uint32_t CAPCTRL[16];                       /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
17818     };
17819     union {                                          /* offset: 0x200, array step: 0x4 */
17820       struct {                                         /* offset: 0x200, array step: 0x4 */
17821         __IO uint16_t MATCHRELL;                         /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
17822         __IO uint16_t MATCHRELH;                         /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
17823       } MATCHREL_ACCESS16BIT[16];
17824       __IO uint32_t MATCHREL[16];                      /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
17825     };
17826   };
17827        uint8_t RESERVED_3[192];
17828   struct {                                         /* offset: 0x300, array step: 0x8 */
17829     __IO uint32_t STATE;                             /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
17830     __IO uint32_t CTRL;                              /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
17831   } EV[16];
17832        uint8_t RESERVED_4[384];
17833   struct {                                         /* offset: 0x500, array step: 0x8 */
17834     __IO uint32_t SET;                               /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
17835     __IO uint32_t CLR;                               /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
17836   } OUT[10];
17837 } SCT_Type;
17838 
17839 /* ----------------------------------------------------------------------------
17840    -- SCT Register Masks
17841    ---------------------------------------------------------------------------- */
17842 
17843 /*!
17844  * @addtogroup SCT_Register_Masks SCT Register Masks
17845  * @{
17846  */
17847 
17848 /*! @name CONFIG - SCT configuration register */
17849 /*! @{ */
17850 
17851 #define SCT_CONFIG_UNIFY_MASK                    (0x1U)
17852 #define SCT_CONFIG_UNIFY_SHIFT                   (0U)
17853 /*! UNIFY - SCT operation
17854  *  0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
17855  *  0b1..The SCT operates as a unified 32-bit counter.
17856  */
17857 #define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
17858 
17859 #define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
17860 #define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
17861 /*! CLKMODE - SCT clock mode
17862  *  0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
17863  *  0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
17864  *        only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
17865  *        minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
17866  *        high-performance, sampled-clock mode.
17867  *  0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the
17868  *        counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
17869  *        clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
17870  *  0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
17871  *        field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
17872  *        clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
17873  *        the system clock.
17874  */
17875 #define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
17876 
17877 #define SCT_CONFIG_CKSEL_MASK                    (0x78U)
17878 #define SCT_CONFIG_CKSEL_SHIFT                   (3U)
17879 /*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent
17880  *    on the CLKMODE bit selection in this register.
17881  *  0b0000..Rising edges on input 0.
17882  *  0b0001..Falling edges on input 0.
17883  *  0b0010..Rising edges on input 1.
17884  *  0b0011..Falling edges on input 1.
17885  *  0b0100..Rising edges on input 2.
17886  *  0b0101..Falling edges on input 2.
17887  *  0b0110..Rising edges on input 3.
17888  *  0b0111..Falling edges on input 3.
17889  *  0b1000..Rising edges on input 4.
17890  *  0b1001..Falling edges on input 4.
17891  *  0b1010..Rising edges on input 5.
17892  *  0b1011..Falling edges on input 5.
17893  *  0b1100..Rising edges on input 6.
17894  *  0b1101..Falling edges on input 6.
17895  *  0b1110..Rising edges on input 7.
17896  *  0b1111..Falling edges on input 7.
17897  */
17898 #define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
17899 
17900 #define SCT_CONFIG_NORELOAD_L_MASK               (0x80U)
17901 #define SCT_CONFIG_NORELOAD_L_SHIFT              (7U)
17902 /*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their
17903  *    respective reload registers. Setting this bit eliminates the need to write to the reload
17904  *    registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any
17905  *    time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
17906  */
17907 #define SCT_CONFIG_NORELOAD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
17908 
17909 #define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
17910 #define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
17911 /*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their
17912  *    respective reload registers. Setting this bit eliminates the need to write to the reload
17913  *    registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at
17914  *    any time. This bit is not used when the UNIFY bit is set.
17915  */
17916 #define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
17917 
17918 #define SCT_CONFIG_INSYNC_MASK                   (0x1E00U)
17919 #define SCT_CONFIG_INSYNC_SHIFT                  (9U)
17920 /*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all
17921  *    other bits are reserved. A 1 in one of these bits subjects the corresponding input to
17922  *    synchronization to the SCT clock, before it is used to create an event. If an input is known to
17923  *    already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note:
17924  *    The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input
17925  *    clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation.
17926  *    It does not apply to the clock input specified in the CKSEL field.
17927  */
17928 #define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
17929 
17930 #define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
17931 #define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
17932 /*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto
17933  *    LIMIT condition without the need to define an associated event. As with any LIMIT event, this
17934  *    automatic limit causes the counter to be cleared to zero in unidirectional mode or to change
17935  *    the direction of count in bi-directional mode. Software can write to set or clear this bit at
17936  *    any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
17937  */
17938 #define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
17939 
17940 #define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
17941 #define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
17942 /*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a
17943  *    de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event,
17944  *    this automatic limit causes the counter to be cleared to zero in unidirectional mode or to
17945  *    change the direction of count in bi-directional mode. Software can write to set or clear this bit
17946  *    at any time. This bit is not used when the UNIFY bit is set.
17947  */
17948 #define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
17949 /*! @} */
17950 
17951 /*! @name CTRLL - SCT_CTRLL register */
17952 /*! @{ */
17953 
17954 #define SCT_CTRLL_DOWN_L_MASK                    (0x1U)
17955 #define SCT_CTRLL_DOWN_L_SHIFT                   (0U)
17956 /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
17957  *    when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
17958  *    when the counter is counting down and a limit condition occurs or when the counter reaches 0.
17959  */
17960 #define SCT_CTRLL_DOWN_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)
17961 
17962 #define SCT_CTRLL_STOP_L_MASK                    (0x2U)
17963 #define SCT_CTRLL_STOP_L_SHIFT                   (1U)
17964 /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
17965  *    related to the counter can occur. If a designated start event occurs, this bit is cleared and
17966  *    counting resumes.
17967  */
17968 #define SCT_CTRLL_STOP_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)
17969 
17970 #define SCT_CTRLL_HALT_L_MASK                    (0x4U)
17971 #define SCT_CTRLL_HALT_L_SHIFT                   (2U)
17972 /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
17973  *    reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
17974  *    remove the halt condition while keeping the SCT in the stop condition (not running) with a
17975  *    single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
17976  *    only software can clear this bit to restore counter operation. This bit is set on reset.
17977  */
17978 #define SCT_CTRLL_HALT_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)
17979 
17980 #define SCT_CTRLL_CLRCTR_L_MASK                  (0x8U)
17981 #define SCT_CTRLL_CLRCTR_L_SHIFT                 (3U)
17982 /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
17983  */
17984 #define SCT_CTRLL_CLRCTR_L(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)
17985 
17986 #define SCT_CTRLL_BIDIR_L_MASK                   (0x10U)
17987 #define SCT_CTRLL_BIDIR_L_SHIFT                  (4U)
17988 /*! BIDIR_L - L or unified counter direction select
17989  *  0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
17990  *  0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
17991  */
17992 #define SCT_CTRLL_BIDIR_L(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)
17993 
17994 #define SCT_CTRLL_PRE_L_MASK                     (0x1FE0U)
17995 #define SCT_CTRLL_PRE_L_SHIFT                    (5U)
17996 /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
17997  *    counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
17998  *    Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
17999  */
18000 #define SCT_CTRLL_PRE_L(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
18001 /*! @} */
18002 
18003 /*! @name CTRLH - SCT_CTRLH register */
18004 /*! @{ */
18005 
18006 #define SCT_CTRLH_DOWN_H_MASK                    (0x1U)
18007 #define SCT_CTRLH_DOWN_H_SHIFT                   (0U)
18008 /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
18009  *    counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
18010  *    when the counter is counting down and a limit condition occurs or when the counter reaches 0.
18011  */
18012 #define SCT_CTRLH_DOWN_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)
18013 
18014 #define SCT_CTRLH_STOP_H_MASK                    (0x2U)
18015 #define SCT_CTRLH_STOP_H_SHIFT                   (1U)
18016 /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
18017  *    the counter can occur. If such an event matches the mask in the Start register, this bit is
18018  *    cleared and counting resumes.
18019  */
18020 #define SCT_CTRLH_STOP_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)
18021 
18022 #define SCT_CTRLH_HALT_H_MASK                    (0x4U)
18023 #define SCT_CTRLH_HALT_H_SHIFT                   (2U)
18024 /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
18025  *    this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
18026  *    halt condition while keeping the SCT in the stop condition (not running) with a single write to
18027  *    this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
18028  *    can only be cleared by software to restore counter operation. This bit is set on reset.
18029  */
18030 #define SCT_CTRLH_HALT_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)
18031 
18032 #define SCT_CTRLH_CLRCTR_H_MASK                  (0x8U)
18033 #define SCT_CTRLH_CLRCTR_H_SHIFT                 (3U)
18034 /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
18035  */
18036 #define SCT_CTRLH_CLRCTR_H(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)
18037 
18038 #define SCT_CTRLH_BIDIR_H_MASK                   (0x10U)
18039 #define SCT_CTRLH_BIDIR_H_SHIFT                  (4U)
18040 /*! BIDIR_H - Direction select
18041  *  0b0..The H counter counts up to its limit condition, then is cleared to zero.
18042  *  0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
18043  */
18044 #define SCT_CTRLH_BIDIR_H(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)
18045 
18046 #define SCT_CTRLH_PRE_H_MASK                     (0x1FE0U)
18047 #define SCT_CTRLH_PRE_H_SHIFT                    (5U)
18048 /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
18049  *    The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
18050  *    counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
18051  */
18052 #define SCT_CTRLH_PRE_H(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
18053 /*! @} */
18054 
18055 /*! @name CTRL - SCT control register */
18056 /*! @{ */
18057 
18058 #define SCT_CTRL_DOWN_L_MASK                     (0x1U)
18059 #define SCT_CTRL_DOWN_L_SHIFT                    (0U)
18060 /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
18061  *    when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
18062  *    when the counter is counting down and a limit condition occurs or when the counter reaches 0.
18063  */
18064 #define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
18065 
18066 #define SCT_CTRL_STOP_L_MASK                     (0x2U)
18067 #define SCT_CTRL_STOP_L_SHIFT                    (1U)
18068 /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
18069  *    related to the counter can occur. If a designated start event occurs, this bit is cleared and
18070  *    counting resumes.
18071  */
18072 #define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
18073 
18074 #define SCT_CTRL_HALT_L_MASK                     (0x4U)
18075 #define SCT_CTRL_HALT_L_SHIFT                    (2U)
18076 /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
18077  *    reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
18078  *    remove the halt condition while keeping the SCT in the stop condition (not running) with a
18079  *    single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
18080  *    only software can clear this bit to restore counter operation. This bit is set on reset.
18081  */
18082 #define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
18083 
18084 #define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
18085 #define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
18086 /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
18087  */
18088 #define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
18089 
18090 #define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
18091 #define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
18092 /*! BIDIR_L - L or unified counter direction select
18093  *  0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
18094  *  0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
18095  */
18096 #define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
18097 
18098 #define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
18099 #define SCT_CTRL_PRE_L_SHIFT                     (5U)
18100 /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
18101  *    counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
18102  *    Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
18103  */
18104 #define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
18105 
18106 #define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
18107 #define SCT_CTRL_DOWN_H_SHIFT                    (16U)
18108 /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
18109  *    counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
18110  *    when the counter is counting down and a limit condition occurs or when the counter reaches 0.
18111  */
18112 #define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
18113 
18114 #define SCT_CTRL_STOP_H_MASK                     (0x20000U)
18115 #define SCT_CTRL_STOP_H_SHIFT                    (17U)
18116 /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
18117  *    the counter can occur. If such an event matches the mask in the Start register, this bit is
18118  *    cleared and counting resumes.
18119  */
18120 #define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
18121 
18122 #define SCT_CTRL_HALT_H_MASK                     (0x40000U)
18123 #define SCT_CTRL_HALT_H_SHIFT                    (18U)
18124 /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
18125  *    this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
18126  *    halt condition while keeping the SCT in the stop condition (not running) with a single write to
18127  *    this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
18128  *    can only be cleared by software to restore counter operation. This bit is set on reset.
18129  */
18130 #define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
18131 
18132 #define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
18133 #define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
18134 /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
18135  */
18136 #define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
18137 
18138 #define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
18139 #define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
18140 /*! BIDIR_H - Direction select
18141  *  0b0..The H counter counts up to its limit condition, then is cleared to zero.
18142  *  0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
18143  */
18144 #define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
18145 
18146 #define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
18147 #define SCT_CTRL_PRE_H_SHIFT                     (21U)
18148 /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
18149  *    The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
18150  *    counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
18151  */
18152 #define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
18153 /*! @} */
18154 
18155 /*! @name LIMITL - SCT_LIMITL register */
18156 /*! @{ */
18157 
18158 #define SCT_LIMITL_LIMITL_MASK                   (0xFFFFU)
18159 #define SCT_LIMITL_LIMITL_SHIFT                  (0U)
18160 #define SCT_LIMITL_LIMITL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
18161 /*! @} */
18162 
18163 /*! @name LIMITH - SCT_LIMITH register */
18164 /*! @{ */
18165 
18166 #define SCT_LIMITH_LIMITH_MASK                   (0xFFFFU)
18167 #define SCT_LIMITH_LIMITH_SHIFT                  (0U)
18168 #define SCT_LIMITH_LIMITH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
18169 /*! @} */
18170 
18171 /*! @name LIMIT - SCT limit event select register */
18172 /*! @{ */
18173 
18174 #define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
18175 #define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
18176 /*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter
18177  *    (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
18178  */
18179 #define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
18180 
18181 #define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
18182 #define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
18183 /*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit
18184  *    16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
18185  */
18186 #define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
18187 /*! @} */
18188 
18189 /*! @name HALTL - SCT_HALTL register */
18190 /*! @{ */
18191 
18192 #define SCT_HALTL_HALTL_MASK                     (0xFFFFU)
18193 #define SCT_HALTL_HALTL_SHIFT                    (0U)
18194 #define SCT_HALTL_HALTL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
18195 /*! @} */
18196 
18197 /*! @name HALTH - SCT_HALTH register */
18198 /*! @{ */
18199 
18200 #define SCT_HALTH_HALTH_MASK                     (0xFFFFU)
18201 #define SCT_HALTH_HALTH_SHIFT                    (0U)
18202 #define SCT_HALTH_HALTH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
18203 /*! @} */
18204 
18205 /*! @name HALT - SCT halt event select register */
18206 /*! @{ */
18207 
18208 #define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
18209 #define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
18210 /*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0,
18211  *    event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
18212  */
18213 #define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
18214 
18215 #define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
18216 #define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
18217 /*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16,
18218  *    event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
18219  */
18220 #define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
18221 /*! @} */
18222 
18223 /*! @name STOPL - SCT_STOPL register */
18224 /*! @{ */
18225 
18226 #define SCT_STOPL_STOPL_MASK                     (0xFFFFU)
18227 #define SCT_STOPL_STOPL_SHIFT                    (0U)
18228 #define SCT_STOPL_STOPL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
18229 /*! @} */
18230 
18231 /*! @name STOPH - SCT_STOPH register */
18232 /*! @{ */
18233 
18234 #define SCT_STOPH_STOPH_MASK                     (0xFFFFU)
18235 #define SCT_STOPH_STOPH_SHIFT                    (0U)
18236 #define SCT_STOPH_STOPH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
18237 /*! @} */
18238 
18239 /*! @name STOP - SCT stop event select register */
18240 /*! @{ */
18241 
18242 #define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
18243 #define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
18244 /*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0,
18245  *    event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
18246  */
18247 #define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
18248 
18249 #define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
18250 #define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
18251 /*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16,
18252  *    event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
18253  */
18254 #define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
18255 /*! @} */
18256 
18257 /*! @name STARTL - SCT_STARTL register */
18258 /*! @{ */
18259 
18260 #define SCT_STARTL_STARTL_MASK                   (0xFFFFU)
18261 #define SCT_STARTL_STARTL_SHIFT                  (0U)
18262 #define SCT_STARTL_STARTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
18263 /*! @} */
18264 
18265 /*! @name STARTH - SCT_STARTH register */
18266 /*! @{ */
18267 
18268 #define SCT_STARTH_STARTH_MASK                   (0xFFFFU)
18269 #define SCT_STARTH_STARTH_SHIFT                  (0U)
18270 #define SCT_STARTH_STARTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
18271 /*! @} */
18272 
18273 /*! @name START - SCT start event select register */
18274 /*! @{ */
18275 
18276 #define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
18277 #define SCT_START_STARTMSK_L_SHIFT               (0U)
18278 /*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit
18279  *    0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
18280  */
18281 #define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
18282 
18283 #define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
18284 #define SCT_START_STARTMSK_H_SHIFT               (16U)
18285 /*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit
18286  *    16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
18287  */
18288 #define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
18289 /*! @} */
18290 
18291 /*! @name COUNTL - SCT_COUNTL register */
18292 /*! @{ */
18293 
18294 #define SCT_COUNTL_COUNTL_MASK                   (0xFFFFU)
18295 #define SCT_COUNTL_COUNTL_SHIFT                  (0U)
18296 #define SCT_COUNTL_COUNTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
18297 /*! @} */
18298 
18299 /*! @name COUNTH - SCT_COUNTH register */
18300 /*! @{ */
18301 
18302 #define SCT_COUNTH_COUNTH_MASK                   (0xFFFFU)
18303 #define SCT_COUNTH_COUNTH_SHIFT                  (0U)
18304 #define SCT_COUNTH_COUNTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
18305 /*! @} */
18306 
18307 /*! @name COUNT - SCT counter register */
18308 /*! @{ */
18309 
18310 #define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
18311 #define SCT_COUNT_CTR_L_SHIFT                    (0U)
18312 /*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write
18313  *    the lower 16 bits of the 32-bit unified counter.
18314  */
18315 #define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
18316 
18317 #define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
18318 #define SCT_COUNT_CTR_H_SHIFT                    (16U)
18319 /*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write
18320  *    the upper 16 bits of the 32-bit unified counter.
18321  */
18322 #define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
18323 /*! @} */
18324 
18325 /*! @name STATEL - SCT_STATEL register */
18326 /*! @{ */
18327 
18328 #define SCT_STATEL_STATEL_MASK                   (0xFFFFU)
18329 #define SCT_STATEL_STATEL_SHIFT                  (0U)
18330 #define SCT_STATEL_STATEL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
18331 /*! @} */
18332 
18333 /*! @name STATEH - SCT_STATEH register */
18334 /*! @{ */
18335 
18336 #define SCT_STATEH_STATEH_MASK                   (0xFFFFU)
18337 #define SCT_STATEH_STATEH_SHIFT                  (0U)
18338 #define SCT_STATEH_STATEH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
18339 /*! @} */
18340 
18341 /*! @name STATE - SCT state register */
18342 /*! @{ */
18343 
18344 #define SCT_STATE_STATE_L_MASK                   (0x1FU)
18345 #define SCT_STATE_STATE_L_SHIFT                  (0U)
18346 /*! STATE_L - State variable.
18347  */
18348 #define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
18349 
18350 #define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
18351 #define SCT_STATE_STATE_H_SHIFT                  (16U)
18352 /*! STATE_H - State variable.
18353  */
18354 #define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
18355 /*! @} */
18356 
18357 /*! @name INPUT - SCT input register */
18358 /*! @{ */
18359 
18360 #define SCT_INPUT_AIN0_MASK                      (0x1U)
18361 #define SCT_INPUT_AIN0_SHIFT                     (0U)
18362 /*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
18363  */
18364 #define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
18365 
18366 #define SCT_INPUT_AIN1_MASK                      (0x2U)
18367 #define SCT_INPUT_AIN1_SHIFT                     (1U)
18368 /*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
18369  */
18370 #define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
18371 
18372 #define SCT_INPUT_AIN2_MASK                      (0x4U)
18373 #define SCT_INPUT_AIN2_SHIFT                     (2U)
18374 /*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
18375  */
18376 #define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
18377 
18378 #define SCT_INPUT_AIN3_MASK                      (0x8U)
18379 #define SCT_INPUT_AIN3_SHIFT                     (3U)
18380 /*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
18381  */
18382 #define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
18383 
18384 #define SCT_INPUT_AIN4_MASK                      (0x10U)
18385 #define SCT_INPUT_AIN4_SHIFT                     (4U)
18386 /*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge.
18387  */
18388 #define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
18389 
18390 #define SCT_INPUT_AIN5_MASK                      (0x20U)
18391 #define SCT_INPUT_AIN5_SHIFT                     (5U)
18392 /*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge.
18393  */
18394 #define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
18395 
18396 #define SCT_INPUT_AIN6_MASK                      (0x40U)
18397 #define SCT_INPUT_AIN6_SHIFT                     (6U)
18398 /*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge.
18399  */
18400 #define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
18401 
18402 #define SCT_INPUT_AIN7_MASK                      (0x80U)
18403 #define SCT_INPUT_AIN7_SHIFT                     (7U)
18404 /*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge.
18405  */
18406 #define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
18407 
18408 #define SCT_INPUT_AIN8_MASK                      (0x100U)
18409 #define SCT_INPUT_AIN8_SHIFT                     (8U)
18410 /*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge.
18411  */
18412 #define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
18413 
18414 #define SCT_INPUT_AIN9_MASK                      (0x200U)
18415 #define SCT_INPUT_AIN9_SHIFT                     (9U)
18416 /*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge.
18417  */
18418 #define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
18419 
18420 #define SCT_INPUT_AIN10_MASK                     (0x400U)
18421 #define SCT_INPUT_AIN10_SHIFT                    (10U)
18422 /*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge.
18423  */
18424 #define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
18425 
18426 #define SCT_INPUT_AIN11_MASK                     (0x800U)
18427 #define SCT_INPUT_AIN11_SHIFT                    (11U)
18428 /*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge.
18429  */
18430 #define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
18431 
18432 #define SCT_INPUT_AIN12_MASK                     (0x1000U)
18433 #define SCT_INPUT_AIN12_SHIFT                    (12U)
18434 /*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge.
18435  */
18436 #define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
18437 
18438 #define SCT_INPUT_AIN13_MASK                     (0x2000U)
18439 #define SCT_INPUT_AIN13_SHIFT                    (13U)
18440 /*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge.
18441  */
18442 #define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
18443 
18444 #define SCT_INPUT_AIN14_MASK                     (0x4000U)
18445 #define SCT_INPUT_AIN14_SHIFT                    (14U)
18446 /*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge.
18447  */
18448 #define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
18449 
18450 #define SCT_INPUT_AIN15_MASK                     (0x8000U)
18451 #define SCT_INPUT_AIN15_SHIFT                    (15U)
18452 /*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge.
18453  */
18454 #define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
18455 
18456 #define SCT_INPUT_SIN0_MASK                      (0x10000U)
18457 #define SCT_INPUT_SIN0_SHIFT                     (16U)
18458 /*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
18459  */
18460 #define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
18461 
18462 #define SCT_INPUT_SIN1_MASK                      (0x20000U)
18463 #define SCT_INPUT_SIN1_SHIFT                     (17U)
18464 /*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
18465  */
18466 #define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
18467 
18468 #define SCT_INPUT_SIN2_MASK                      (0x40000U)
18469 #define SCT_INPUT_SIN2_SHIFT                     (18U)
18470 /*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
18471  */
18472 #define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
18473 
18474 #define SCT_INPUT_SIN3_MASK                      (0x80000U)
18475 #define SCT_INPUT_SIN3_SHIFT                     (19U)
18476 /*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
18477  */
18478 #define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
18479 
18480 #define SCT_INPUT_SIN4_MASK                      (0x100000U)
18481 #define SCT_INPUT_SIN4_SHIFT                     (20U)
18482 /*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC.
18483  */
18484 #define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
18485 
18486 #define SCT_INPUT_SIN5_MASK                      (0x200000U)
18487 #define SCT_INPUT_SIN5_SHIFT                     (21U)
18488 /*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC.
18489  */
18490 #define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
18491 
18492 #define SCT_INPUT_SIN6_MASK                      (0x400000U)
18493 #define SCT_INPUT_SIN6_SHIFT                     (22U)
18494 /*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC.
18495  */
18496 #define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
18497 
18498 #define SCT_INPUT_SIN7_MASK                      (0x800000U)
18499 #define SCT_INPUT_SIN7_SHIFT                     (23U)
18500 /*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC.
18501  */
18502 #define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
18503 
18504 #define SCT_INPUT_SIN8_MASK                      (0x1000000U)
18505 #define SCT_INPUT_SIN8_SHIFT                     (24U)
18506 /*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC.
18507  */
18508 #define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
18509 
18510 #define SCT_INPUT_SIN9_MASK                      (0x2000000U)
18511 #define SCT_INPUT_SIN9_SHIFT                     (25U)
18512 /*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC.
18513  */
18514 #define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
18515 
18516 #define SCT_INPUT_SIN10_MASK                     (0x4000000U)
18517 #define SCT_INPUT_SIN10_SHIFT                    (26U)
18518 /*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC.
18519  */
18520 #define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
18521 
18522 #define SCT_INPUT_SIN11_MASK                     (0x8000000U)
18523 #define SCT_INPUT_SIN11_SHIFT                    (27U)
18524 /*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC.
18525  */
18526 #define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
18527 
18528 #define SCT_INPUT_SIN12_MASK                     (0x10000000U)
18529 #define SCT_INPUT_SIN12_SHIFT                    (28U)
18530 /*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC.
18531  */
18532 #define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
18533 
18534 #define SCT_INPUT_SIN13_MASK                     (0x20000000U)
18535 #define SCT_INPUT_SIN13_SHIFT                    (29U)
18536 /*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC.
18537  */
18538 #define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
18539 
18540 #define SCT_INPUT_SIN14_MASK                     (0x40000000U)
18541 #define SCT_INPUT_SIN14_SHIFT                    (30U)
18542 /*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC.
18543  */
18544 #define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
18545 
18546 #define SCT_INPUT_SIN15_MASK                     (0x80000000U)
18547 #define SCT_INPUT_SIN15_SHIFT                    (31U)
18548 /*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC.
18549  */
18550 #define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
18551 /*! @} */
18552 
18553 /*! @name REGMODEL - SCT_REGMODEL register */
18554 /*! @{ */
18555 
18556 #define SCT_REGMODEL_REGMODEL_MASK               (0xFFFFU)
18557 #define SCT_REGMODEL_REGMODEL_SHIFT              (0U)
18558 #define SCT_REGMODEL_REGMODEL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)
18559 /*! @} */
18560 
18561 /*! @name REGMODEH - SCT_REGMODEH register */
18562 /*! @{ */
18563 
18564 #define SCT_REGMODEH_REGMODEH_MASK               (0xFFFFU)
18565 #define SCT_REGMODEH_REGMODEH_SHIFT              (0U)
18566 #define SCT_REGMODEH_REGMODEH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)
18567 /*! @} */
18568 
18569 /*! @name REGMODE - SCT match/capture mode register */
18570 /*! @{ */
18571 
18572 #define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
18573 #define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
18574 /*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1,
18575  *    etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
18576  *    match register. 1 = register operates as capture register.
18577  */
18578 #define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
18579 
18580 #define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
18581 #define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
18582 /*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit
18583  *    17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
18584  *    match registers. 1 = register operates as capture registers.
18585  */
18586 #define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
18587 /*! @} */
18588 
18589 /*! @name OUTPUT - SCT output register */
18590 /*! @{ */
18591 
18592 #define SCT_OUTPUT_OUT_MASK                      (0xFFFFU)
18593 #define SCT_OUTPUT_OUT_SHIFT                     (0U)
18594 /*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the
18595  *    corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
18596  *    outputs in this SCT.
18597  */
18598 #define SCT_OUTPUT_OUT(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
18599 /*! @} */
18600 
18601 /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
18602 /*! @{ */
18603 
18604 #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
18605 #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
18606 /*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
18607  *  0b00..Set and clear do not depend on the direction of any counter.
18608  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18609  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18610  */
18611 #define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
18612 
18613 #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
18614 #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
18615 /*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
18616  *  0b00..Set and clear do not depend on the direction of any counter.
18617  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18618  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18619  */
18620 #define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
18621 
18622 #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
18623 #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
18624 /*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
18625  *  0b00..Set and clear do not depend on the direction of any counter.
18626  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18627  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18628  */
18629 #define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
18630 
18631 #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
18632 #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
18633 /*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
18634  *  0b00..Set and clear do not depend on the direction of any counter.
18635  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18636  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18637  */
18638 #define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
18639 
18640 #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
18641 #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
18642 /*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
18643  *  0b00..Set and clear do not depend on the direction of any counter.
18644  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18645  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18646  */
18647 #define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
18648 
18649 #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
18650 #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
18651 /*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
18652  *  0b00..Set and clear do not depend on the direction of any counter.
18653  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18654  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18655  */
18656 #define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
18657 
18658 #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
18659 #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
18660 /*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
18661  *  0b00..Set and clear do not depend on the direction of any counter.
18662  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18663  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18664  */
18665 #define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
18666 
18667 #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
18668 #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
18669 /*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.
18670  *  0b00..Set and clear do not depend on the direction of any counter.
18671  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18672  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18673  */
18674 #define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
18675 
18676 #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
18677 #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
18678 /*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.
18679  *  0b00..Set and clear do not depend on the direction of any counter.
18680  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18681  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18682  */
18683 #define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
18684 
18685 #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
18686 #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
18687 /*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.
18688  *  0b00..Set and clear do not depend on the direction of any counter.
18689  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18690  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18691  */
18692 #define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
18693 
18694 #define SCT_OUTPUTDIRCTRL_SETCLR10_MASK          (0x300000U)
18695 #define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT         (20U)
18696 /*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.
18697  *  0b00..Set and clear do not depend on the direction of any counter.
18698  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18699  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18700  */
18701 #define SCT_OUTPUTDIRCTRL_SETCLR10(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
18702 
18703 #define SCT_OUTPUTDIRCTRL_SETCLR11_MASK          (0xC00000U)
18704 #define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT         (22U)
18705 /*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.
18706  *  0b00..Set and clear do not depend on the direction of any counter.
18707  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18708  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18709  */
18710 #define SCT_OUTPUTDIRCTRL_SETCLR11(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
18711 
18712 #define SCT_OUTPUTDIRCTRL_SETCLR12_MASK          (0x3000000U)
18713 #define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT         (24U)
18714 /*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
18715  *  0b00..Set and clear do not depend on the direction of any counter.
18716  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18717  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18718  */
18719 #define SCT_OUTPUTDIRCTRL_SETCLR12(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
18720 
18721 #define SCT_OUTPUTDIRCTRL_SETCLR13_MASK          (0xC000000U)
18722 #define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT         (26U)
18723 /*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.
18724  *  0b00..Set and clear do not depend on the direction of any counter.
18725  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18726  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18727  */
18728 #define SCT_OUTPUTDIRCTRL_SETCLR13(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
18729 
18730 #define SCT_OUTPUTDIRCTRL_SETCLR14_MASK          (0x30000000U)
18731 #define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT         (28U)
18732 /*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.
18733  *  0b00..Set and clear do not depend on the direction of any counter.
18734  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18735  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18736  */
18737 #define SCT_OUTPUTDIRCTRL_SETCLR14(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
18738 
18739 #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK          (0xC0000000U)
18740 #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT         (30U)
18741 /*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.
18742  *  0b00..Set and clear do not depend on the direction of any counter.
18743  *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
18744  *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
18745  */
18746 #define SCT_OUTPUTDIRCTRL_SETCLR15(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
18747 /*! @} */
18748 
18749 /*! @name RES - SCT conflict resolution register */
18750 /*! @{ */
18751 
18752 #define SCT_RES_O0RES_MASK                       (0x3U)
18753 #define SCT_RES_O0RES_SHIFT                      (0U)
18754 /*! O0RES - Effect of simultaneous set and clear on output 0.
18755  *  0b00..No change.
18756  *  0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
18757  *  0b10..Clear output (or set based on the SETCLR0 field).
18758  *  0b11..Toggle output.
18759  */
18760 #define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
18761 
18762 #define SCT_RES_O1RES_MASK                       (0xCU)
18763 #define SCT_RES_O1RES_SHIFT                      (2U)
18764 /*! O1RES - Effect of simultaneous set and clear on output 1.
18765  *  0b00..No change.
18766  *  0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
18767  *  0b10..Clear output (or set based on the SETCLR1 field).
18768  *  0b11..Toggle output.
18769  */
18770 #define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
18771 
18772 #define SCT_RES_O2RES_MASK                       (0x30U)
18773 #define SCT_RES_O2RES_SHIFT                      (4U)
18774 /*! O2RES - Effect of simultaneous set and clear on output 2.
18775  *  0b00..No change.
18776  *  0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
18777  *  0b10..Clear output n (or set based on the SETCLR2 field).
18778  *  0b11..Toggle output.
18779  */
18780 #define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
18781 
18782 #define SCT_RES_O3RES_MASK                       (0xC0U)
18783 #define SCT_RES_O3RES_SHIFT                      (6U)
18784 /*! O3RES - Effect of simultaneous set and clear on output 3.
18785  *  0b00..No change.
18786  *  0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
18787  *  0b10..Clear output (or set based on the SETCLR3 field).
18788  *  0b11..Toggle output.
18789  */
18790 #define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
18791 
18792 #define SCT_RES_O4RES_MASK                       (0x300U)
18793 #define SCT_RES_O4RES_SHIFT                      (8U)
18794 /*! O4RES - Effect of simultaneous set and clear on output 4.
18795  *  0b00..No change.
18796  *  0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).
18797  *  0b10..Clear output (or set based on the SETCLR4 field).
18798  *  0b11..Toggle output.
18799  */
18800 #define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
18801 
18802 #define SCT_RES_O5RES_MASK                       (0xC00U)
18803 #define SCT_RES_O5RES_SHIFT                      (10U)
18804 /*! O5RES - Effect of simultaneous set and clear on output 5.
18805  *  0b00..No change.
18806  *  0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).
18807  *  0b10..Clear output (or set based on the SETCLR5 field).
18808  *  0b11..Toggle output.
18809  */
18810 #define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
18811 
18812 #define SCT_RES_O6RES_MASK                       (0x3000U)
18813 #define SCT_RES_O6RES_SHIFT                      (12U)
18814 /*! O6RES - Effect of simultaneous set and clear on output 6.
18815  *  0b00..No change.
18816  *  0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).
18817  *  0b10..Clear output (or set based on the SETCLR6 field).
18818  *  0b11..Toggle output.
18819  */
18820 #define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
18821 
18822 #define SCT_RES_O7RES_MASK                       (0xC000U)
18823 #define SCT_RES_O7RES_SHIFT                      (14U)
18824 /*! O7RES - Effect of simultaneous set and clear on output 7.
18825  *  0b00..No change.
18826  *  0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).
18827  *  0b10..Clear output n (or set based on the SETCLR7 field).
18828  *  0b11..Toggle output.
18829  */
18830 #define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
18831 
18832 #define SCT_RES_O8RES_MASK                       (0x30000U)
18833 #define SCT_RES_O8RES_SHIFT                      (16U)
18834 /*! O8RES - Effect of simultaneous set and clear on output 8.
18835  *  0b00..No change.
18836  *  0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).
18837  *  0b10..Clear output (or set based on the SETCLR8 field).
18838  *  0b11..Toggle output.
18839  */
18840 #define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
18841 
18842 #define SCT_RES_O9RES_MASK                       (0xC0000U)
18843 #define SCT_RES_O9RES_SHIFT                      (18U)
18844 /*! O9RES - Effect of simultaneous set and clear on output 9.
18845  *  0b00..No change.
18846  *  0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).
18847  *  0b10..Clear output (or set based on the SETCLR9 field).
18848  *  0b11..Toggle output.
18849  */
18850 #define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
18851 
18852 #define SCT_RES_O10RES_MASK                      (0x300000U)
18853 #define SCT_RES_O10RES_SHIFT                     (20U)
18854 /*! O10RES - Effect of simultaneous set and clear on output 10.
18855  *  0b00..No change.
18856  *  0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).
18857  *  0b10..Clear output (or set based on the SETCLR10 field).
18858  *  0b11..Toggle output.
18859  */
18860 #define SCT_RES_O10RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
18861 
18862 #define SCT_RES_O11RES_MASK                      (0xC00000U)
18863 #define SCT_RES_O11RES_SHIFT                     (22U)
18864 /*! O11RES - Effect of simultaneous set and clear on output 11.
18865  *  0b00..No change.
18866  *  0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).
18867  *  0b10..Clear output (or set based on the SETCLR11 field).
18868  *  0b11..Toggle output.
18869  */
18870 #define SCT_RES_O11RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
18871 
18872 #define SCT_RES_O12RES_MASK                      (0x3000000U)
18873 #define SCT_RES_O12RES_SHIFT                     (24U)
18874 /*! O12RES - Effect of simultaneous set and clear on output 12.
18875  *  0b00..No change.
18876  *  0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).
18877  *  0b10..Clear output (or set based on the SETCLR12 field).
18878  *  0b11..Toggle output.
18879  */
18880 #define SCT_RES_O12RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
18881 
18882 #define SCT_RES_O13RES_MASK                      (0xC000000U)
18883 #define SCT_RES_O13RES_SHIFT                     (26U)
18884 /*! O13RES - Effect of simultaneous set and clear on output 13.
18885  *  0b00..No change.
18886  *  0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).
18887  *  0b10..Clear output (or set based on the SETCLR13 field).
18888  *  0b11..Toggle output.
18889  */
18890 #define SCT_RES_O13RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
18891 
18892 #define SCT_RES_O14RES_MASK                      (0x30000000U)
18893 #define SCT_RES_O14RES_SHIFT                     (28U)
18894 /*! O14RES - Effect of simultaneous set and clear on output 14.
18895  *  0b00..No change.
18896  *  0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).
18897  *  0b10..Clear output (or set based on the SETCLR14 field).
18898  *  0b11..Toggle output.
18899  */
18900 #define SCT_RES_O14RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
18901 
18902 #define SCT_RES_O15RES_MASK                      (0xC0000000U)
18903 #define SCT_RES_O15RES_SHIFT                     (30U)
18904 /*! O15RES - Effect of simultaneous set and clear on output 15.
18905  *  0b00..No change.
18906  *  0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).
18907  *  0b10..Clear output (or set based on the SETCLR15 field).
18908  *  0b11..Toggle output.
18909  */
18910 #define SCT_RES_O15RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
18911 /*! @} */
18912 
18913 /*! @name DMAREQ0 - SCT DMA request 0 register */
18914 /*! @{ */
18915 
18916 #define SCT_DMAREQ0_DEV_0_MASK                   (0xFFFFU)
18917 #define SCT_DMAREQ0_DEV_0_SHIFT                  (0U)
18918 /*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1,
18919  *    etc.). The number of bits = number of events in this SCT.
18920  */
18921 #define SCT_DMAREQ0_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
18922 
18923 #define SCT_DMAREQ0_DRL0_MASK                    (0x40000000U)
18924 #define SCT_DMAREQ0_DRL0_SHIFT                   (30U)
18925 /*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
18926  */
18927 #define SCT_DMAREQ0_DRL0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
18928 
18929 #define SCT_DMAREQ0_DRQ0_MASK                    (0x80000000U)
18930 #define SCT_DMAREQ0_DRQ0_SHIFT                   (31U)
18931 /*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA
18932  *    channel is enabled and properly set up, it is unlikely that software will see this flag, it will
18933  *    be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
18934  *    setup.
18935  */
18936 #define SCT_DMAREQ0_DRQ0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
18937 /*! @} */
18938 
18939 /*! @name DMAREQ1 - SCT DMA request 1 register */
18940 /*! @{ */
18941 
18942 #define SCT_DMAREQ1_DEV_1_MASK                   (0xFFFFU)
18943 #define SCT_DMAREQ1_DEV_1_SHIFT                  (0U)
18944 /*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1,
18945  *    etc.). The number of bits = number of events in this SCT.
18946  */
18947 #define SCT_DMAREQ1_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
18948 
18949 #define SCT_DMAREQ1_DRL1_MASK                    (0x40000000U)
18950 #define SCT_DMAREQ1_DRL1_SHIFT                   (30U)
18951 /*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
18952  */
18953 #define SCT_DMAREQ1_DRL1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
18954 
18955 #define SCT_DMAREQ1_DRQ1_MASK                    (0x80000000U)
18956 #define SCT_DMAREQ1_DRQ1_SHIFT                   (31U)
18957 /*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA
18958  *    channel is enabled and properly set up, it is unlikely that software will see this flag, it will
18959  *    be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
18960  *    setup.
18961  */
18962 #define SCT_DMAREQ1_DRQ1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
18963 /*! @} */
18964 
18965 /*! @name EVEN - SCT event interrupt enable register */
18966 /*! @{ */
18967 
18968 #define SCT_EVEN_IEN_MASK                        (0xFFFFU)
18969 #define SCT_EVEN_IEN_SHIFT                       (0U)
18970 /*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are
18971  *    both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in
18972  *    this SCT.
18973  */
18974 #define SCT_EVEN_IEN(x)                          (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
18975 /*! @} */
18976 
18977 /*! @name EVFLAG - SCT event flag register */
18978 /*! @{ */
18979 
18980 #define SCT_EVFLAG_FLAG_MASK                     (0xFFFFU)
18981 #define SCT_EVFLAG_FLAG_SHIFT                    (0U)
18982 /*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit
18983  *    (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
18984  */
18985 #define SCT_EVFLAG_FLAG(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
18986 /*! @} */
18987 
18988 /*! @name CONEN - SCT conflict interrupt enable register */
18989 /*! @{ */
18990 
18991 #define SCT_CONEN_NCEN_MASK                      (0xFFFFU)
18992 #define SCT_CONEN_NCEN_SHIFT                     (0U)
18993 /*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag
18994  *    register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
18995  *    outputs in this SCT.
18996  */
18997 #define SCT_CONEN_NCEN(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
18998 /*! @} */
18999 
19000 /*! @name CONFLAG - SCT conflict flag register */
19001 /*! @{ */
19002 
19003 #define SCT_CONFLAG_NCFLAG_MASK                  (0xFFFFU)
19004 #define SCT_CONFLAG_NCFLAG_SHIFT                 (0U)
19005 /*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was
19006  *    last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits =
19007  *    number of outputs in this SCT.
19008  */
19009 #define SCT_CONFLAG_NCFLAG(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
19010 
19011 #define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
19012 #define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
19013 /*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE
19014  *    L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write
19015  *    to certain L and H registers can be half successful and half unsuccessful.
19016  */
19017 #define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
19018 
19019 #define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
19020 #define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
19021 /*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or
19022  *    the Output register when the H counter was not halted.
19023  */
19024 #define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
19025 /*! @} */
19026 
19027 /*! @name CAPL - SCT_CAPL register */
19028 /*! @{ */
19029 
19030 #define SCT_CAPL_CAPL_MASK                       (0xFFFFU)
19031 #define SCT_CAPL_CAPL_SHIFT                      (0U)
19032 #define SCT_CAPL_CAPL(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
19033 /*! @} */
19034 
19035 /* The count of SCT_CAPL */
19036 #define SCT_CAPL_COUNT                           (16U)
19037 
19038 /*! @name CAPH - SCT_CAPH register */
19039 /*! @{ */
19040 
19041 #define SCT_CAPH_CAPH_MASK                       (0xFFFFU)
19042 #define SCT_CAPH_CAPH_SHIFT                      (0U)
19043 #define SCT_CAPH_CAPH(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
19044 /*! @} */
19045 
19046 /* The count of SCT_CAPH */
19047 #define SCT_CAPH_COUNT                           (16U)
19048 
19049 /*! @name CAP - SCT capture register of capture channel */
19050 /*! @{ */
19051 
19052 #define SCT_CAP_CAPn_L_MASK                      (0xFFFFU)
19053 #define SCT_CAP_CAPn_L_SHIFT                     (0U)
19054 /*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
19055  *    When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last
19056  *    captured.
19057  */
19058 #define SCT_CAP_CAPn_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
19059 
19060 #define SCT_CAP_CAPn_H_MASK                      (0xFFFF0000U)
19061 #define SCT_CAP_CAPn_H_SHIFT                     (16U)
19062 /*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
19063  *    When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last
19064  *    captured.
19065  */
19066 #define SCT_CAP_CAPn_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
19067 /*! @} */
19068 
19069 /* The count of SCT_CAP */
19070 #define SCT_CAP_COUNT                            (16U)
19071 
19072 /*! @name MATCHL - SCT_MATCHL register */
19073 /*! @{ */
19074 
19075 #define SCT_MATCHL_MATCHL_MASK                   (0xFFFFU)
19076 #define SCT_MATCHL_MATCHL_SHIFT                  (0U)
19077 #define SCT_MATCHL_MATCHL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
19078 /*! @} */
19079 
19080 /* The count of SCT_MATCHL */
19081 #define SCT_MATCHL_COUNT                         (16U)
19082 
19083 /*! @name MATCHH - SCT_MATCHH register */
19084 /*! @{ */
19085 
19086 #define SCT_MATCHH_MATCHH_MASK                   (0xFFFFU)
19087 #define SCT_MATCHH_MATCHH_SHIFT                  (0U)
19088 #define SCT_MATCHH_MATCHH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
19089 /*! @} */
19090 
19091 /* The count of SCT_MATCHH */
19092 #define SCT_MATCHH_COUNT                         (16U)
19093 
19094 /*! @name MATCH - SCT match value register of match channels */
19095 /*! @{ */
19096 
19097 #define SCT_MATCH_MATCHn_L_MASK                  (0xFFFFU)
19098 #define SCT_MATCH_MATCHn_L_SHIFT                 (0U)
19099 /*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When
19100  *    UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified
19101  *    counter.
19102  */
19103 #define SCT_MATCH_MATCHn_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
19104 
19105 #define SCT_MATCH_MATCHn_H_MASK                  (0xFFFF0000U)
19106 #define SCT_MATCH_MATCHn_H_SHIFT                 (16U)
19107 /*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When
19108  *    UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified
19109  *    counter.
19110  */
19111 #define SCT_MATCH_MATCHn_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
19112 /*! @} */
19113 
19114 /* The count of SCT_MATCH */
19115 #define SCT_MATCH_COUNT                          (16U)
19116 
19117 /*! @name CAPCTRLL - SCT_CAPCTRLL register */
19118 /*! @{ */
19119 
19120 #define SCT_CAPCTRLL_CAPCTRLL_MASK               (0xFFFFU)
19121 #define SCT_CAPCTRLL_CAPCTRLL_SHIFT              (0U)
19122 #define SCT_CAPCTRLL_CAPCTRLL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
19123 /*! @} */
19124 
19125 /* The count of SCT_CAPCTRLL */
19126 #define SCT_CAPCTRLL_COUNT                       (16U)
19127 
19128 /*! @name CAPCTRLH - SCT_CAPCTRLH register */
19129 /*! @{ */
19130 
19131 #define SCT_CAPCTRLH_CAPCTRLH_MASK               (0xFFFFU)
19132 #define SCT_CAPCTRLH_CAPCTRLH_SHIFT              (0U)
19133 #define SCT_CAPCTRLH_CAPCTRLH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
19134 /*! @} */
19135 
19136 /* The count of SCT_CAPCTRLH */
19137 #define SCT_CAPCTRLH_COUNT                       (16U)
19138 
19139 /*! @name CAPCTRL - SCT capture control register */
19140 /*! @{ */
19141 
19142 #define SCT_CAPCTRL_CAPCONn_L_MASK               (0xFFFFU)
19143 #define SCT_CAPCTRL_CAPCONn_L_SHIFT              (0U)
19144 /*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1)
19145  *    register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of
19146  *    match/captures in this SCT.
19147  */
19148 #define SCT_CAPCTRL_CAPCONn_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
19149 
19150 #define SCT_CAPCTRL_CAPCONn_H_MASK               (0xFFFF0000U)
19151 #define SCT_CAPCTRL_CAPCONn_H_SHIFT              (16U)
19152 /*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event
19153  *    0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
19154  */
19155 #define SCT_CAPCTRL_CAPCONn_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
19156 /*! @} */
19157 
19158 /* The count of SCT_CAPCTRL */
19159 #define SCT_CAPCTRL_COUNT                        (16U)
19160 
19161 /*! @name MATCHRELL - SCT_MATCHRELL register */
19162 /*! @{ */
19163 
19164 #define SCT_MATCHRELL_MATCHRELL_MASK             (0xFFFFU)
19165 #define SCT_MATCHRELL_MATCHRELL_SHIFT            (0U)
19166 #define SCT_MATCHRELL_MATCHRELL(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
19167 /*! @} */
19168 
19169 /* The count of SCT_MATCHRELL */
19170 #define SCT_MATCHRELL_COUNT                      (16U)
19171 
19172 /*! @name MATCHRELH - SCT_MATCHRELH register */
19173 /*! @{ */
19174 
19175 #define SCT_MATCHRELH_MATCHRELH_MASK             (0xFFFFU)
19176 #define SCT_MATCHRELH_MATCHRELH_SHIFT            (0U)
19177 #define SCT_MATCHRELH_MATCHRELH(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
19178 /*! @} */
19179 
19180 /* The count of SCT_MATCHRELH */
19181 #define SCT_MATCHRELH_COUNT                      (16U)
19182 
19183 /*! @name MATCHREL - SCT match reload value register */
19184 /*! @{ */
19185 
19186 #define SCT_MATCHREL_RELOADn_L_MASK              (0xFFFFU)
19187 #define SCT_MATCHREL_RELOADn_L_SHIFT             (0U)
19188 /*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.
19189  *    When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn
19190  *    register.
19191  */
19192 #define SCT_MATCHREL_RELOADn_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
19193 
19194 #define SCT_MATCHREL_RELOADn_H_MASK              (0xFFFF0000U)
19195 #define SCT_MATCHREL_RELOADn_H_SHIFT             (16U)
19196 /*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When
19197  *    UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn
19198  *    register.
19199  */
19200 #define SCT_MATCHREL_RELOADn_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
19201 /*! @} */
19202 
19203 /* The count of SCT_MATCHREL */
19204 #define SCT_MATCHREL_COUNT                       (16U)
19205 
19206 /*! @name EV_STATE - SCT event state register 0 */
19207 /*! @{ */
19208 
19209 #define SCT_EV_STATE_STATEMSKn_MASK              (0xFFFFU)
19210 #define SCT_EV_STATE_STATEMSKn_SHIFT             (0U)
19211 /*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT
19212  *    bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
19213  *    bits = number of states in this SCT.
19214  */
19215 #define SCT_EV_STATE_STATEMSKn(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
19216 /*! @} */
19217 
19218 /* The count of SCT_EV_STATE */
19219 #define SCT_EV_STATE_COUNT                       (16U)
19220 
19221 /*! @name EV_CTRL - SCT event control register 0 */
19222 /*! @{ */
19223 
19224 #define SCT_EV_CTRL_MATCHSEL_MASK                (0xFU)
19225 #define SCT_EV_CTRL_MATCHSEL_SHIFT               (0U)
19226 /*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur
19227  *    only when the counter selected by the HEVENT bit is running.
19228  */
19229 #define SCT_EV_CTRL_MATCHSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
19230 
19231 #define SCT_EV_CTRL_HEVENT_MASK                  (0x10U)
19232 #define SCT_EV_CTRL_HEVENT_SHIFT                 (4U)
19233 /*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.
19234  *  0b0..Selects the L state and the L match register selected by MATCHSEL.
19235  *  0b1..Selects the H state and the H match register selected by MATCHSEL.
19236  */
19237 #define SCT_EV_CTRL_HEVENT(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
19238 
19239 #define SCT_EV_CTRL_OUTSEL_MASK                  (0x20U)
19240 #define SCT_EV_CTRL_OUTSEL_SHIFT                 (5U)
19241 /*! OUTSEL - Input/output select
19242  *  0b0..Selects the inputs selected by IOSEL.
19243  *  0b1..Selects the outputs selected by IOSEL.
19244  */
19245 #define SCT_EV_CTRL_OUTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
19246 
19247 #define SCT_EV_CTRL_IOSEL_MASK                   (0x3C0U)
19248 #define SCT_EV_CTRL_IOSEL_SHIFT                  (6U)
19249 /*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not
19250  *    select an input in this register if CKMODE is 1x. In this case the clock input is an implicit
19251  *    ingredient of every event.
19252  */
19253 #define SCT_EV_CTRL_IOSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
19254 
19255 #define SCT_EV_CTRL_IOCOND_MASK                  (0xC00U)
19256 #define SCT_EV_CTRL_IOCOND_SHIFT                 (10U)
19257 /*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the
19258  *    conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state
19259  *    detection, an input must have a minimum pulse width of at least one SCT clock period .
19260  *  0b00..LOW
19261  *  0b01..Rise
19262  *  0b10..Fall
19263  *  0b11..HIGH
19264  */
19265 #define SCT_EV_CTRL_IOCOND(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
19266 
19267 #define SCT_EV_CTRL_COMBMODE_MASK                (0x3000U)
19268 #define SCT_EV_CTRL_COMBMODE_SHIFT               (12U)
19269 /*! COMBMODE - Selects how the specified match and I/O condition are used and combined.
19270  *  0b00..OR. The event occurs when either the specified match or I/O condition occurs.
19271  *  0b01..MATCH. Uses the specified match only.
19272  *  0b10..IO. Uses the specified I/O condition only.
19273  *  0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
19274  */
19275 #define SCT_EV_CTRL_COMBMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
19276 
19277 #define SCT_EV_CTRL_STATELD_MASK                 (0x4000U)
19278 #define SCT_EV_CTRL_STATELD_SHIFT                (14U)
19279 /*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this
19280  *    event is the highest-numbered event occurring for that state.
19281  *  0b0..STATEV value is added into STATE (the carry-out is ignored).
19282  *  0b1..STATEV value is loaded into STATE.
19283  */
19284 #define SCT_EV_CTRL_STATELD(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
19285 
19286 #define SCT_EV_CTRL_STATEV_MASK                  (0xF8000U)
19287 #define SCT_EV_CTRL_STATEV_SHIFT                 (15U)
19288 /*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on
19289  *    STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and
19290  *    STATEV are both zero, there is no change to the STATE value.
19291  */
19292 #define SCT_EV_CTRL_STATEV(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
19293 
19294 #define SCT_EV_CTRL_MATCHMEM_MASK                (0x100000U)
19295 #define SCT_EV_CTRL_MATCHMEM_SHIFT               (20U)
19296 /*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the
19297  *    triggering of this event, then a match is considered to be active whenever the counter value is
19298  *    GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR
19299  *    EQUAL TO the match value when counting down. If this bit is zero, a match is only be active
19300  *    during the cycle when the counter is equal to the match value.
19301  */
19302 #define SCT_EV_CTRL_MATCHMEM(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
19303 
19304 #define SCT_EV_CTRL_DIRECTION_MASK               (0x600000U)
19305 #define SCT_EV_CTRL_DIRECTION_SHIFT              (21U)
19306 /*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters
19307  *    are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
19308  *  0b00..Direction independent. This event is triggered regardless of the count direction.
19309  *  0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
19310  *  0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
19311  */
19312 #define SCT_EV_CTRL_DIRECTION(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
19313 /*! @} */
19314 
19315 /* The count of SCT_EV_CTRL */
19316 #define SCT_EV_CTRL_COUNT                        (16U)
19317 
19318 /*! @name OUT_SET - SCT output 0 set register */
19319 /*! @{ */
19320 
19321 #define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
19322 #define SCT_OUT_SET_SET_SHIFT                    (0U)
19323 /*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output
19324  *    0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
19325  *    counter is used in bi-directional mode, it is possible to reverse the action specified by the
19326  *    output set and clear registers when counting down, See the OUTPUTCTRL register.
19327  */
19328 #define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
19329 /*! @} */
19330 
19331 /* The count of SCT_OUT_SET */
19332 #define SCT_OUT_SET_COUNT                        (10U)
19333 
19334 /*! @name OUT_CLR - SCT output 0 clear register */
19335 /*! @{ */
19336 
19337 #define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
19338 #define SCT_OUT_CLR_CLR_SHIFT                    (0U)
19339 /*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0
19340  *    = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
19341  *    counter is used in bi-directional mode, it is possible to reverse the action specified by the
19342  *    output set and clear registers when counting down, See the OUTPUTCTRL register.
19343  */
19344 #define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
19345 /*! @} */
19346 
19347 /* The count of SCT_OUT_CLR */
19348 #define SCT_OUT_CLR_COUNT                        (10U)
19349 
19350 
19351 /*!
19352  * @}
19353  */ /* end of group SCT_Register_Masks */
19354 
19355 
19356 /* SCT - Peripheral instance base addresses */
19357 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
19358   /** Peripheral SCT0 base address */
19359   #define SCT0_BASE                                (0x50085000u)
19360   /** Peripheral SCT0 base address */
19361   #define SCT0_BASE_NS                             (0x40085000u)
19362   /** Peripheral SCT0 base pointer */
19363   #define SCT0                                     ((SCT_Type *)SCT0_BASE)
19364   /** Peripheral SCT0 base pointer */
19365   #define SCT0_NS                                  ((SCT_Type *)SCT0_BASE_NS)
19366   /** Array initializer of SCT peripheral base addresses */
19367   #define SCT_BASE_ADDRS                           { SCT0_BASE }
19368   /** Array initializer of SCT peripheral base pointers */
19369   #define SCT_BASE_PTRS                            { SCT0 }
19370   /** Array initializer of SCT peripheral base addresses */
19371   #define SCT_BASE_ADDRS_NS                        { SCT0_BASE_NS }
19372   /** Array initializer of SCT peripheral base pointers */
19373   #define SCT_BASE_PTRS_NS                         { SCT0_NS }
19374 #else
19375   /** Peripheral SCT0 base address */
19376   #define SCT0_BASE                                (0x40085000u)
19377   /** Peripheral SCT0 base pointer */
19378   #define SCT0                                     ((SCT_Type *)SCT0_BASE)
19379   /** Array initializer of SCT peripheral base addresses */
19380   #define SCT_BASE_ADDRS                           { SCT0_BASE }
19381   /** Array initializer of SCT peripheral base pointers */
19382   #define SCT_BASE_PTRS                            { SCT0 }
19383 #endif
19384 /** Interrupt vectors for the SCT peripheral type */
19385 #define SCT_IRQS                                 { SCT0_IRQn }
19386 
19387 /*!
19388  * @}
19389  */ /* end of group SCT_Peripheral_Access_Layer */
19390 
19391 
19392 /* ----------------------------------------------------------------------------
19393    -- SDIF Peripheral Access Layer
19394    ---------------------------------------------------------------------------- */
19395 
19396 /*!
19397  * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer
19398  * @{
19399  */
19400 
19401 /** SDIF - Register Layout Typedef */
19402 typedef struct {
19403   __IO uint32_t CTRL;                              /**< Control register, offset: 0x0 */
19404   __IO uint32_t PWREN;                             /**< Power Enable register, offset: 0x4 */
19405   __IO uint32_t CLKDIV;                            /**< Clock Divider register, offset: 0x8 */
19406        uint8_t RESERVED_0[4];
19407   __IO uint32_t CLKENA;                            /**< Clock Enable register, offset: 0x10 */
19408   __IO uint32_t TMOUT;                             /**< Time-out register, offset: 0x14 */
19409   __IO uint32_t CTYPE;                             /**< Card Type register, offset: 0x18 */
19410   __IO uint32_t BLKSIZ;                            /**< Block Size register, offset: 0x1C */
19411   __IO uint32_t BYTCNT;                            /**< Byte Count register, offset: 0x20 */
19412   __IO uint32_t INTMASK;                           /**< Interrupt Mask register, offset: 0x24 */
19413   __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x28 */
19414   __IO uint32_t CMD;                               /**< Command register, offset: 0x2C */
19415   __IO uint32_t RESP[4];                           /**< Response register, array offset: 0x30, array step: 0x4 */
19416   __IO uint32_t MINTSTS;                           /**< Masked Interrupt Status register, offset: 0x40 */
19417   __IO uint32_t RINTSTS;                           /**< Raw Interrupt Status register, offset: 0x44 */
19418   __IO uint32_t STATUS;                            /**< Status register, offset: 0x48 */
19419   __IO uint32_t FIFOTH;                            /**< FIFO Threshold Watermark register, offset: 0x4C */
19420   __IO uint32_t CDETECT;                           /**< Card Detect register, offset: 0x50 */
19421   __IO uint32_t WRTPRT;                            /**< Write Protect register, offset: 0x54 */
19422        uint8_t RESERVED_1[4];
19423   __IO uint32_t TCBCNT;                            /**< Transferred CIU Card Byte Count register, offset: 0x5C */
19424   __IO uint32_t TBBCNT;                            /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
19425   __IO uint32_t DEBNCE;                            /**< Debounce Count register, offset: 0x64 */
19426        uint8_t RESERVED_2[16];
19427   __IO uint32_t RST_N;                             /**< Hardware Reset, offset: 0x78 */
19428        uint8_t RESERVED_3[4];
19429   __IO uint32_t BMOD;                              /**< Bus Mode register, offset: 0x80 */
19430   __IO uint32_t PLDMND;                            /**< Poll Demand register, offset: 0x84 */
19431   __IO uint32_t DBADDR;                            /**< Descriptor List Base Address register, offset: 0x88 */
19432   __IO uint32_t IDSTS;                             /**< Internal DMAC Status register, offset: 0x8C */
19433   __IO uint32_t IDINTEN;                           /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
19434   __IO uint32_t DSCADDR;                           /**< Current Host Descriptor Address register, offset: 0x94 */
19435   __IO uint32_t BUFADDR;                           /**< Current Buffer Descriptor Address register, offset: 0x98 */
19436        uint8_t RESERVED_4[100];
19437   __IO uint32_t CARDTHRCTL;                        /**< Card Threshold Control, offset: 0x100 */
19438   __IO uint32_t BACKENDPWR;                        /**< Power control, offset: 0x104 */
19439        uint8_t RESERVED_5[248];
19440   __IO uint32_t FIFO[64];                          /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
19441 } SDIF_Type;
19442 
19443 /* ----------------------------------------------------------------------------
19444    -- SDIF Register Masks
19445    ---------------------------------------------------------------------------- */
19446 
19447 /*!
19448  * @addtogroup SDIF_Register_Masks SDIF Register Masks
19449  * @{
19450  */
19451 
19452 /*! @name CTRL - Control register */
19453 /*! @{ */
19454 
19455 #define SDIF_CTRL_CONTROLLER_RESET_MASK          (0x1U)
19456 #define SDIF_CTRL_CONTROLLER_RESET_SHIFT         (0U)
19457 /*! CONTROLLER_RESET - Controller reset.
19458  */
19459 #define SDIF_CTRL_CONTROLLER_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
19460 
19461 #define SDIF_CTRL_FIFO_RESET_MASK                (0x2U)
19462 #define SDIF_CTRL_FIFO_RESET_SHIFT               (1U)
19463 /*! FIFO_RESET - Fifo reset.
19464  */
19465 #define SDIF_CTRL_FIFO_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
19466 
19467 #define SDIF_CTRL_DMA_RESET_MASK                 (0x4U)
19468 #define SDIF_CTRL_DMA_RESET_SHIFT                (2U)
19469 /*! DMA_RESET - DMA reset.
19470  */
19471 #define SDIF_CTRL_DMA_RESET(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
19472 
19473 #define SDIF_CTRL_INT_ENABLE_MASK                (0x10U)
19474 #define SDIF_CTRL_INT_ENABLE_SHIFT               (4U)
19475 /*! INT_ENABLE - Global interrupt enable/disable bit.
19476  */
19477 #define SDIF_CTRL_INT_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
19478 
19479 #define SDIF_CTRL_READ_WAIT_MASK                 (0x40U)
19480 #define SDIF_CTRL_READ_WAIT_SHIFT                (6U)
19481 /*! READ_WAIT - Read/wait.
19482  */
19483 #define SDIF_CTRL_READ_WAIT(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
19484 
19485 #define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK         (0x80U)
19486 #define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT        (7U)
19487 /*! SEND_IRQ_RESPONSE - Send irq response.
19488  */
19489 #define SDIF_CTRL_SEND_IRQ_RESPONSE(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
19490 
19491 #define SDIF_CTRL_ABORT_READ_DATA_MASK           (0x100U)
19492 #define SDIF_CTRL_ABORT_READ_DATA_SHIFT          (8U)
19493 /*! ABORT_READ_DATA - Abort read data.
19494  */
19495 #define SDIF_CTRL_ABORT_READ_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
19496 
19497 #define SDIF_CTRL_SEND_CCSD_MASK                 (0x200U)
19498 #define SDIF_CTRL_SEND_CCSD_SHIFT                (9U)
19499 /*! SEND_CCSD - Send ccsd.
19500  */
19501 #define SDIF_CTRL_SEND_CCSD(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
19502 
19503 #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK       (0x400U)
19504 #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT      (10U)
19505 /*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd.
19506  */
19507 #define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
19508 
19509 #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
19510 #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
19511 /*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status.
19512  */
19513 #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
19514 
19515 #define SDIF_CTRL_CARD_VOLTAGE_A0_MASK           (0x10000U)
19516 #define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT          (16U)
19517 /*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin.
19518  */
19519 #define SDIF_CTRL_CARD_VOLTAGE_A0(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
19520 
19521 #define SDIF_CTRL_CARD_VOLTAGE_A1_MASK           (0x20000U)
19522 #define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT          (17U)
19523 /*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin.
19524  */
19525 #define SDIF_CTRL_CARD_VOLTAGE_A1(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
19526 
19527 #define SDIF_CTRL_CARD_VOLTAGE_A2_MASK           (0x40000U)
19528 #define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT          (18U)
19529 /*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin.
19530  */
19531 #define SDIF_CTRL_CARD_VOLTAGE_A2(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
19532 
19533 #define SDIF_CTRL_USE_INTERNAL_DMAC_MASK         (0x2000000U)
19534 #define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT        (25U)
19535 /*! USE_INTERNAL_DMAC - SD/MMC DMA use.
19536  */
19537 #define SDIF_CTRL_USE_INTERNAL_DMAC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
19538 /*! @} */
19539 
19540 /*! @name PWREN - Power Enable register */
19541 /*! @{ */
19542 
19543 #define SDIF_PWREN_POWER_ENABLE0_MASK            (0x1U)
19544 #define SDIF_PWREN_POWER_ENABLE0_SHIFT           (0U)
19545 /*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait
19546  *    for regulator/switch ramp-up time before trying to initialize card 0.
19547  */
19548 #define SDIF_PWREN_POWER_ENABLE0(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK)
19549 
19550 #define SDIF_PWREN_POWER_ENABLE1_MASK            (0x2U)
19551 #define SDIF_PWREN_POWER_ENABLE1_SHIFT           (1U)
19552 /*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait
19553  *    for regulator/switch ramp-up time before trying to initialize card 1.
19554  */
19555 #define SDIF_PWREN_POWER_ENABLE1(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK)
19556 /*! @} */
19557 
19558 /*! @name CLKDIV - Clock Divider register */
19559 /*! @{ */
19560 
19561 #define SDIF_CLKDIV_CLK_DIVIDER0_MASK            (0xFFU)
19562 #define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT           (0U)
19563 /*! CLK_DIVIDER0 - Clock divider-0 value.
19564  */
19565 #define SDIF_CLKDIV_CLK_DIVIDER0(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
19566 /*! @} */
19567 
19568 /*! @name CLKENA - Clock Enable register */
19569 /*! @{ */
19570 
19571 #define SDIF_CLKENA_CCLK0_ENABLE_MASK            (0x1U)
19572 #define SDIF_CLKENA_CCLK0_ENABLE_SHIFT           (0U)
19573 /*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock.
19574  */
19575 #define SDIF_CLKENA_CCLK0_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK)
19576 
19577 #define SDIF_CLKENA_CCLK1_ENABLE_MASK            (0x2U)
19578 #define SDIF_CLKENA_CCLK1_ENABLE_SHIFT           (1U)
19579 /*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock.
19580  */
19581 #define SDIF_CLKENA_CCLK1_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK)
19582 
19583 #define SDIF_CLKENA_CCLK0_LOW_POWER_MASK         (0x10000U)
19584 #define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT        (16U)
19585 /*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock.
19586  */
19587 #define SDIF_CLKENA_CCLK0_LOW_POWER(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK)
19588 
19589 #define SDIF_CLKENA_CCLK1_LOW_POWER_MASK         (0x20000U)
19590 #define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT        (17U)
19591 /*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock.
19592  */
19593 #define SDIF_CLKENA_CCLK1_LOW_POWER(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK)
19594 /*! @} */
19595 
19596 /*! @name TMOUT - Time-out register */
19597 /*! @{ */
19598 
19599 #define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK         (0xFFU)
19600 #define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT        (0U)
19601 /*! RESPONSE_TIMEOUT - Response time-out value.
19602  */
19603 #define SDIF_TMOUT_RESPONSE_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
19604 
19605 #define SDIF_TMOUT_DATA_TIMEOUT_MASK             (0xFFFFFF00U)
19606 #define SDIF_TMOUT_DATA_TIMEOUT_SHIFT            (8U)
19607 /*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out.
19608  */
19609 #define SDIF_TMOUT_DATA_TIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
19610 /*! @} */
19611 
19612 /*! @name CTYPE - Card Type register */
19613 /*! @{ */
19614 
19615 #define SDIF_CTYPE_CARD0_WIDTH0_MASK             (0x1U)
19616 #define SDIF_CTYPE_CARD0_WIDTH0_SHIFT            (0U)
19617 /*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit
19618  *    modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set
19619  *    to 0).
19620  */
19621 #define SDIF_CTYPE_CARD0_WIDTH0(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK)
19622 
19623 #define SDIF_CTYPE_CARD1_WIDTH0_MASK             (0x2U)
19624 #define SDIF_CTYPE_CARD1_WIDTH0_SHIFT            (1U)
19625 /*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit
19626  *    modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set
19627  *    to 0).
19628  */
19629 #define SDIF_CTYPE_CARD1_WIDTH0(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK)
19630 
19631 #define SDIF_CTYPE_CARD0_WIDTH1_MASK             (0x10000U)
19632 #define SDIF_CTYPE_CARD0_WIDTH1_SHIFT            (16U)
19633 /*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
19634  */
19635 #define SDIF_CTYPE_CARD0_WIDTH1(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK)
19636 
19637 #define SDIF_CTYPE_CARD1_WIDTH1_MASK             (0x20000U)
19638 #define SDIF_CTYPE_CARD1_WIDTH1_SHIFT            (17U)
19639 /*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
19640  */
19641 #define SDIF_CTYPE_CARD1_WIDTH1(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK)
19642 /*! @} */
19643 
19644 /*! @name BLKSIZ - Block Size register */
19645 /*! @{ */
19646 
19647 #define SDIF_BLKSIZ_BLOCK_SIZE_MASK              (0xFFFFU)
19648 #define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT             (0U)
19649 /*! BLOCK_SIZE - Block size.
19650  */
19651 #define SDIF_BLKSIZ_BLOCK_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
19652 /*! @} */
19653 
19654 /*! @name BYTCNT - Byte Count register */
19655 /*! @{ */
19656 
19657 #define SDIF_BYTCNT_BYTE_COUNT_MASK              (0xFFFFFFFFU)
19658 #define SDIF_BYTCNT_BYTE_COUNT_SHIFT             (0U)
19659 /*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers.
19660  */
19661 #define SDIF_BYTCNT_BYTE_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
19662 /*! @} */
19663 
19664 /*! @name INTMASK - Interrupt Mask register */
19665 /*! @{ */
19666 
19667 #define SDIF_INTMASK_CDET_MASK                   (0x1U)
19668 #define SDIF_INTMASK_CDET_SHIFT                  (0U)
19669 /*! CDET - Card detect.
19670  */
19671 #define SDIF_INTMASK_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
19672 
19673 #define SDIF_INTMASK_RE_MASK                     (0x2U)
19674 #define SDIF_INTMASK_RE_SHIFT                    (1U)
19675 /*! RE - Response error.
19676  */
19677 #define SDIF_INTMASK_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
19678 
19679 #define SDIF_INTMASK_CDONE_MASK                  (0x4U)
19680 #define SDIF_INTMASK_CDONE_SHIFT                 (2U)
19681 /*! CDONE - Command done.
19682  */
19683 #define SDIF_INTMASK_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
19684 
19685 #define SDIF_INTMASK_DTO_MASK                    (0x8U)
19686 #define SDIF_INTMASK_DTO_SHIFT                   (3U)
19687 /*! DTO - Data transfer over.
19688  */
19689 #define SDIF_INTMASK_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
19690 
19691 #define SDIF_INTMASK_TXDR_MASK                   (0x10U)
19692 #define SDIF_INTMASK_TXDR_SHIFT                  (4U)
19693 /*! TXDR - Transmit FIFO data request.
19694  */
19695 #define SDIF_INTMASK_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
19696 
19697 #define SDIF_INTMASK_RXDR_MASK                   (0x20U)
19698 #define SDIF_INTMASK_RXDR_SHIFT                  (5U)
19699 /*! RXDR - Receive FIFO data request.
19700  */
19701 #define SDIF_INTMASK_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
19702 
19703 #define SDIF_INTMASK_RCRC_MASK                   (0x40U)
19704 #define SDIF_INTMASK_RCRC_SHIFT                  (6U)
19705 /*! RCRC - Response CRC error.
19706  */
19707 #define SDIF_INTMASK_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
19708 
19709 #define SDIF_INTMASK_DCRC_MASK                   (0x80U)
19710 #define SDIF_INTMASK_DCRC_SHIFT                  (7U)
19711 /*! DCRC - Data CRC error.
19712  */
19713 #define SDIF_INTMASK_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
19714 
19715 #define SDIF_INTMASK_RTO_MASK                    (0x100U)
19716 #define SDIF_INTMASK_RTO_SHIFT                   (8U)
19717 /*! RTO - Response time-out.
19718  */
19719 #define SDIF_INTMASK_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
19720 
19721 #define SDIF_INTMASK_DRTO_MASK                   (0x200U)
19722 #define SDIF_INTMASK_DRTO_SHIFT                  (9U)
19723 /*! DRTO - Data read time-out.
19724  */
19725 #define SDIF_INTMASK_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
19726 
19727 #define SDIF_INTMASK_HTO_MASK                    (0x400U)
19728 #define SDIF_INTMASK_HTO_SHIFT                   (10U)
19729 /*! HTO - Data starvation-by-host time-out (HTO).
19730  */
19731 #define SDIF_INTMASK_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
19732 
19733 #define SDIF_INTMASK_FRUN_MASK                   (0x800U)
19734 #define SDIF_INTMASK_FRUN_SHIFT                  (11U)
19735 /*! FRUN - FIFO underrun/overrun error.
19736  */
19737 #define SDIF_INTMASK_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
19738 
19739 #define SDIF_INTMASK_HLE_MASK                    (0x1000U)
19740 #define SDIF_INTMASK_HLE_SHIFT                   (12U)
19741 /*! HLE - Hardware locked write error.
19742  */
19743 #define SDIF_INTMASK_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
19744 
19745 #define SDIF_INTMASK_SBE_MASK                    (0x2000U)
19746 #define SDIF_INTMASK_SBE_SHIFT                   (13U)
19747 /*! SBE - Start-bit error.
19748  */
19749 #define SDIF_INTMASK_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
19750 
19751 #define SDIF_INTMASK_ACD_MASK                    (0x4000U)
19752 #define SDIF_INTMASK_ACD_SHIFT                   (14U)
19753 /*! ACD - Auto command done.
19754  */
19755 #define SDIF_INTMASK_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
19756 
19757 #define SDIF_INTMASK_EBE_MASK                    (0x8000U)
19758 #define SDIF_INTMASK_EBE_SHIFT                   (15U)
19759 /*! EBE - End-bit error (read)/Write no CRC.
19760  */
19761 #define SDIF_INTMASK_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
19762 
19763 #define SDIF_INTMASK_SDIO_INT_MASK_MASK          (0x10000U)
19764 #define SDIF_INTMASK_SDIO_INT_MASK_SHIFT         (16U)
19765 /*! SDIO_INT_MASK - Mask SDIO interrupt.
19766  */
19767 #define SDIF_INTMASK_SDIO_INT_MASK(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
19768 /*! @} */
19769 
19770 /*! @name CMDARG - Command Argument register */
19771 /*! @{ */
19772 
19773 #define SDIF_CMDARG_CMD_ARG_MASK                 (0xFFFFFFFFU)
19774 #define SDIF_CMDARG_CMD_ARG_SHIFT                (0U)
19775 /*! CMD_ARG - Value indicates command argument to be passed to card.
19776  */
19777 #define SDIF_CMDARG_CMD_ARG(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
19778 /*! @} */
19779 
19780 /*! @name CMD - Command register */
19781 /*! @{ */
19782 
19783 #define SDIF_CMD_CMD_INDEX_MASK                  (0x3FU)
19784 #define SDIF_CMD_CMD_INDEX_SHIFT                 (0U)
19785 /*! CMD_INDEX - Command index.
19786  */
19787 #define SDIF_CMD_CMD_INDEX(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
19788 
19789 #define SDIF_CMD_RESPONSE_EXPECT_MASK            (0x40U)
19790 #define SDIF_CMD_RESPONSE_EXPECT_SHIFT           (6U)
19791 /*! RESPONSE_EXPECT - Response expect.
19792  */
19793 #define SDIF_CMD_RESPONSE_EXPECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
19794 
19795 #define SDIF_CMD_RESPONSE_LENGTH_MASK            (0x80U)
19796 #define SDIF_CMD_RESPONSE_LENGTH_SHIFT           (7U)
19797 /*! RESPONSE_LENGTH - Response length.
19798  */
19799 #define SDIF_CMD_RESPONSE_LENGTH(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
19800 
19801 #define SDIF_CMD_CHECK_RESPONSE_CRC_MASK         (0x100U)
19802 #define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT        (8U)
19803 /*! CHECK_RESPONSE_CRC - Check response CRC.
19804  */
19805 #define SDIF_CMD_CHECK_RESPONSE_CRC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
19806 
19807 #define SDIF_CMD_DATA_EXPECTED_MASK              (0x200U)
19808 #define SDIF_CMD_DATA_EXPECTED_SHIFT             (9U)
19809 /*! DATA_EXPECTED - Data expected.
19810  */
19811 #define SDIF_CMD_DATA_EXPECTED(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
19812 
19813 #define SDIF_CMD_READ_WRITE_MASK                 (0x400U)
19814 #define SDIF_CMD_READ_WRITE_SHIFT                (10U)
19815 /*! READ_WRITE - read/write.
19816  */
19817 #define SDIF_CMD_READ_WRITE(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
19818 
19819 #define SDIF_CMD_TRANSFER_MODE_MASK              (0x800U)
19820 #define SDIF_CMD_TRANSFER_MODE_SHIFT             (11U)
19821 /*! TRANSFER_MODE - Transfer mode.
19822  */
19823 #define SDIF_CMD_TRANSFER_MODE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
19824 
19825 #define SDIF_CMD_SEND_AUTO_STOP_MASK             (0x1000U)
19826 #define SDIF_CMD_SEND_AUTO_STOP_SHIFT            (12U)
19827 /*! SEND_AUTO_STOP - Send auto stop.
19828  */
19829 #define SDIF_CMD_SEND_AUTO_STOP(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
19830 
19831 #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK      (0x2000U)
19832 #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT     (13U)
19833 /*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete.
19834  */
19835 #define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
19836 
19837 #define SDIF_CMD_STOP_ABORT_CMD_MASK             (0x4000U)
19838 #define SDIF_CMD_STOP_ABORT_CMD_SHIFT            (14U)
19839 /*! STOP_ABORT_CMD - Stop abort command.
19840  */
19841 #define SDIF_CMD_STOP_ABORT_CMD(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
19842 
19843 #define SDIF_CMD_SEND_INITIALIZATION_MASK        (0x8000U)
19844 #define SDIF_CMD_SEND_INITIALIZATION_SHIFT       (15U)
19845 /*! SEND_INITIALIZATION - Send initialization.
19846  */
19847 #define SDIF_CMD_SEND_INITIALIZATION(x)          (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
19848 
19849 #define SDIF_CMD_CARD_NUMBER_MASK                (0x1F0000U)
19850 #define SDIF_CMD_CARD_NUMBER_SHIFT               (16U)
19851 /*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed
19852  *  0b00000..Command will be execute on SDCARD 0
19853  *  0b00001..Command will be execute on SDCARD 1
19854  */
19855 #define SDIF_CMD_CARD_NUMBER(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK)
19856 
19857 #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
19858 #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
19859 /*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only.
19860  */
19861 #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
19862 
19863 #define SDIF_CMD_READ_CEATA_DEVICE_MASK          (0x400000U)
19864 #define SDIF_CMD_READ_CEATA_DEVICE_SHIFT         (22U)
19865 /*! READ_CEATA_DEVICE - Read ceata device.
19866  */
19867 #define SDIF_CMD_READ_CEATA_DEVICE(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
19868 
19869 #define SDIF_CMD_CCS_EXPECTED_MASK               (0x800000U)
19870 #define SDIF_CMD_CCS_EXPECTED_SHIFT              (23U)
19871 /*! CCS_EXPECTED - CCS expected.
19872  */
19873 #define SDIF_CMD_CCS_EXPECTED(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
19874 
19875 #define SDIF_CMD_ENABLE_BOOT_MASK                (0x1000000U)
19876 #define SDIF_CMD_ENABLE_BOOT_SHIFT               (24U)
19877 /*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode.
19878  */
19879 #define SDIF_CMD_ENABLE_BOOT(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
19880 
19881 #define SDIF_CMD_EXPECT_BOOT_ACK_MASK            (0x2000000U)
19882 #define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT           (25U)
19883 /*! EXPECT_BOOT_ACK - Expect Boot Acknowledge.
19884  */
19885 #define SDIF_CMD_EXPECT_BOOT_ACK(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
19886 
19887 #define SDIF_CMD_DISABLE_BOOT_MASK               (0x4000000U)
19888 #define SDIF_CMD_DISABLE_BOOT_SHIFT              (26U)
19889 /*! DISABLE_BOOT - Disable Boot.
19890  */
19891 #define SDIF_CMD_DISABLE_BOOT(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
19892 
19893 #define SDIF_CMD_BOOT_MODE_MASK                  (0x8000000U)
19894 #define SDIF_CMD_BOOT_MODE_SHIFT                 (27U)
19895 /*! BOOT_MODE - Boot Mode.
19896  */
19897 #define SDIF_CMD_BOOT_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
19898 
19899 #define SDIF_CMD_VOLT_SWITCH_MASK                (0x10000000U)
19900 #define SDIF_CMD_VOLT_SWITCH_SHIFT               (28U)
19901 /*! VOLT_SWITCH - Voltage switch bit.
19902  */
19903 #define SDIF_CMD_VOLT_SWITCH(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
19904 
19905 #define SDIF_CMD_USE_HOLD_REG_MASK               (0x20000000U)
19906 #define SDIF_CMD_USE_HOLD_REG_SHIFT              (29U)
19907 /*! USE_HOLD_REG - Use Hold Register.
19908  */
19909 #define SDIF_CMD_USE_HOLD_REG(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
19910 
19911 #define SDIF_CMD_START_CMD_MASK                  (0x80000000U)
19912 #define SDIF_CMD_START_CMD_SHIFT                 (31U)
19913 /*! START_CMD - Start command.
19914  */
19915 #define SDIF_CMD_START_CMD(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
19916 /*! @} */
19917 
19918 /*! @name RESP - Response register */
19919 /*! @{ */
19920 
19921 #define SDIF_RESP_RESPONSE_MASK                  (0xFFFFFFFFU)
19922 #define SDIF_RESP_RESPONSE_SHIFT                 (0U)
19923 /*! RESPONSE - Bits of response.
19924  */
19925 #define SDIF_RESP_RESPONSE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
19926 /*! @} */
19927 
19928 /* The count of SDIF_RESP */
19929 #define SDIF_RESP_COUNT                          (4U)
19930 
19931 /*! @name MINTSTS - Masked Interrupt Status register */
19932 /*! @{ */
19933 
19934 #define SDIF_MINTSTS_CDET_MASK                   (0x1U)
19935 #define SDIF_MINTSTS_CDET_SHIFT                  (0U)
19936 /*! CDET - Card detect.
19937  */
19938 #define SDIF_MINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
19939 
19940 #define SDIF_MINTSTS_RE_MASK                     (0x2U)
19941 #define SDIF_MINTSTS_RE_SHIFT                    (1U)
19942 /*! RE - Response error.
19943  */
19944 #define SDIF_MINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
19945 
19946 #define SDIF_MINTSTS_CDONE_MASK                  (0x4U)
19947 #define SDIF_MINTSTS_CDONE_SHIFT                 (2U)
19948 /*! CDONE - Command done.
19949  */
19950 #define SDIF_MINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
19951 
19952 #define SDIF_MINTSTS_DTO_MASK                    (0x8U)
19953 #define SDIF_MINTSTS_DTO_SHIFT                   (3U)
19954 /*! DTO - Data transfer over.
19955  */
19956 #define SDIF_MINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
19957 
19958 #define SDIF_MINTSTS_TXDR_MASK                   (0x10U)
19959 #define SDIF_MINTSTS_TXDR_SHIFT                  (4U)
19960 /*! TXDR - Transmit FIFO data request.
19961  */
19962 #define SDIF_MINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
19963 
19964 #define SDIF_MINTSTS_RXDR_MASK                   (0x20U)
19965 #define SDIF_MINTSTS_RXDR_SHIFT                  (5U)
19966 /*! RXDR - Receive FIFO data request.
19967  */
19968 #define SDIF_MINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
19969 
19970 #define SDIF_MINTSTS_RCRC_MASK                   (0x40U)
19971 #define SDIF_MINTSTS_RCRC_SHIFT                  (6U)
19972 /*! RCRC - Response CRC error.
19973  */
19974 #define SDIF_MINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
19975 
19976 #define SDIF_MINTSTS_DCRC_MASK                   (0x80U)
19977 #define SDIF_MINTSTS_DCRC_SHIFT                  (7U)
19978 /*! DCRC - Data CRC error.
19979  */
19980 #define SDIF_MINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
19981 
19982 #define SDIF_MINTSTS_RTO_MASK                    (0x100U)
19983 #define SDIF_MINTSTS_RTO_SHIFT                   (8U)
19984 /*! RTO - Response time-out.
19985  */
19986 #define SDIF_MINTSTS_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
19987 
19988 #define SDIF_MINTSTS_DRTO_MASK                   (0x200U)
19989 #define SDIF_MINTSTS_DRTO_SHIFT                  (9U)
19990 /*! DRTO - Data read time-out.
19991  */
19992 #define SDIF_MINTSTS_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
19993 
19994 #define SDIF_MINTSTS_HTO_MASK                    (0x400U)
19995 #define SDIF_MINTSTS_HTO_SHIFT                   (10U)
19996 /*! HTO - Data starvation-by-host time-out (HTO).
19997  */
19998 #define SDIF_MINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
19999 
20000 #define SDIF_MINTSTS_FRUN_MASK                   (0x800U)
20001 #define SDIF_MINTSTS_FRUN_SHIFT                  (11U)
20002 /*! FRUN - FIFO underrun/overrun error.
20003  */
20004 #define SDIF_MINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
20005 
20006 #define SDIF_MINTSTS_HLE_MASK                    (0x1000U)
20007 #define SDIF_MINTSTS_HLE_SHIFT                   (12U)
20008 /*! HLE - Hardware locked write error.
20009  */
20010 #define SDIF_MINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
20011 
20012 #define SDIF_MINTSTS_SBE_MASK                    (0x2000U)
20013 #define SDIF_MINTSTS_SBE_SHIFT                   (13U)
20014 /*! SBE - Start-bit error.
20015  */
20016 #define SDIF_MINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
20017 
20018 #define SDIF_MINTSTS_ACD_MASK                    (0x4000U)
20019 #define SDIF_MINTSTS_ACD_SHIFT                   (14U)
20020 /*! ACD - Auto command done.
20021  */
20022 #define SDIF_MINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
20023 
20024 #define SDIF_MINTSTS_EBE_MASK                    (0x8000U)
20025 #define SDIF_MINTSTS_EBE_SHIFT                   (15U)
20026 /*! EBE - End-bit error (read)/write no CRC.
20027  */
20028 #define SDIF_MINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
20029 
20030 #define SDIF_MINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
20031 #define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
20032 /*! SDIO_INTERRUPT - Interrupt from SDIO card.
20033  */
20034 #define SDIF_MINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
20035 /*! @} */
20036 
20037 /*! @name RINTSTS - Raw Interrupt Status register */
20038 /*! @{ */
20039 
20040 #define SDIF_RINTSTS_CDET_MASK                   (0x1U)
20041 #define SDIF_RINTSTS_CDET_SHIFT                  (0U)
20042 /*! CDET - Card detect.
20043  */
20044 #define SDIF_RINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
20045 
20046 #define SDIF_RINTSTS_RE_MASK                     (0x2U)
20047 #define SDIF_RINTSTS_RE_SHIFT                    (1U)
20048 /*! RE - Response error.
20049  */
20050 #define SDIF_RINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
20051 
20052 #define SDIF_RINTSTS_CDONE_MASK                  (0x4U)
20053 #define SDIF_RINTSTS_CDONE_SHIFT                 (2U)
20054 /*! CDONE - Command done.
20055  */
20056 #define SDIF_RINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
20057 
20058 #define SDIF_RINTSTS_DTO_MASK                    (0x8U)
20059 #define SDIF_RINTSTS_DTO_SHIFT                   (3U)
20060 /*! DTO - Data transfer over.
20061  */
20062 #define SDIF_RINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
20063 
20064 #define SDIF_RINTSTS_TXDR_MASK                   (0x10U)
20065 #define SDIF_RINTSTS_TXDR_SHIFT                  (4U)
20066 /*! TXDR - Transmit FIFO data request.
20067  */
20068 #define SDIF_RINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
20069 
20070 #define SDIF_RINTSTS_RXDR_MASK                   (0x20U)
20071 #define SDIF_RINTSTS_RXDR_SHIFT                  (5U)
20072 /*! RXDR - Receive FIFO data request.
20073  */
20074 #define SDIF_RINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
20075 
20076 #define SDIF_RINTSTS_RCRC_MASK                   (0x40U)
20077 #define SDIF_RINTSTS_RCRC_SHIFT                  (6U)
20078 /*! RCRC - Response CRC error.
20079  */
20080 #define SDIF_RINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
20081 
20082 #define SDIF_RINTSTS_DCRC_MASK                   (0x80U)
20083 #define SDIF_RINTSTS_DCRC_SHIFT                  (7U)
20084 /*! DCRC - Data CRC error.
20085  */
20086 #define SDIF_RINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
20087 
20088 #define SDIF_RINTSTS_RTO_BAR_MASK                (0x100U)
20089 #define SDIF_RINTSTS_RTO_BAR_SHIFT               (8U)
20090 /*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR).
20091  */
20092 #define SDIF_RINTSTS_RTO_BAR(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
20093 
20094 #define SDIF_RINTSTS_DRTO_BDS_MASK               (0x200U)
20095 #define SDIF_RINTSTS_DRTO_BDS_SHIFT              (9U)
20096 /*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS).
20097  */
20098 #define SDIF_RINTSTS_DRTO_BDS(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
20099 
20100 #define SDIF_RINTSTS_HTO_MASK                    (0x400U)
20101 #define SDIF_RINTSTS_HTO_SHIFT                   (10U)
20102 /*! HTO - Data starvation-by-host time-out (HTO).
20103  */
20104 #define SDIF_RINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
20105 
20106 #define SDIF_RINTSTS_FRUN_MASK                   (0x800U)
20107 #define SDIF_RINTSTS_FRUN_SHIFT                  (11U)
20108 /*! FRUN - FIFO underrun/overrun error.
20109  */
20110 #define SDIF_RINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
20111 
20112 #define SDIF_RINTSTS_HLE_MASK                    (0x1000U)
20113 #define SDIF_RINTSTS_HLE_SHIFT                   (12U)
20114 /*! HLE - Hardware locked write error.
20115  */
20116 #define SDIF_RINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
20117 
20118 #define SDIF_RINTSTS_SBE_MASK                    (0x2000U)
20119 #define SDIF_RINTSTS_SBE_SHIFT                   (13U)
20120 /*! SBE - Start-bit error.
20121  */
20122 #define SDIF_RINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
20123 
20124 #define SDIF_RINTSTS_ACD_MASK                    (0x4000U)
20125 #define SDIF_RINTSTS_ACD_SHIFT                   (14U)
20126 /*! ACD - Auto command done.
20127  */
20128 #define SDIF_RINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
20129 
20130 #define SDIF_RINTSTS_EBE_MASK                    (0x8000U)
20131 #define SDIF_RINTSTS_EBE_SHIFT                   (15U)
20132 /*! EBE - End-bit error (read)/write no CRC.
20133  */
20134 #define SDIF_RINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
20135 
20136 #define SDIF_RINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
20137 #define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
20138 /*! SDIO_INTERRUPT - Interrupt from SDIO card.
20139  */
20140 #define SDIF_RINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
20141 /*! @} */
20142 
20143 /*! @name STATUS - Status register */
20144 /*! @{ */
20145 
20146 #define SDIF_STATUS_FIFO_RX_WATERMARK_MASK       (0x1U)
20147 #define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT      (0U)
20148 /*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer.
20149  */
20150 #define SDIF_STATUS_FIFO_RX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
20151 
20152 #define SDIF_STATUS_FIFO_TX_WATERMARK_MASK       (0x2U)
20153 #define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT      (1U)
20154 /*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer.
20155  */
20156 #define SDIF_STATUS_FIFO_TX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
20157 
20158 #define SDIF_STATUS_FIFO_EMPTY_MASK              (0x4U)
20159 #define SDIF_STATUS_FIFO_EMPTY_SHIFT             (2U)
20160 /*! FIFO_EMPTY - FIFO is empty status.
20161  */
20162 #define SDIF_STATUS_FIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
20163 
20164 #define SDIF_STATUS_FIFO_FULL_MASK               (0x8U)
20165 #define SDIF_STATUS_FIFO_FULL_SHIFT              (3U)
20166 /*! FIFO_FULL - FIFO is full status.
20167  */
20168 #define SDIF_STATUS_FIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
20169 
20170 #define SDIF_STATUS_CMDFSMSTATES_MASK            (0xF0U)
20171 #define SDIF_STATUS_CMDFSMSTATES_SHIFT           (4U)
20172 /*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx
20173  *    cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 -
20174  *    Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp
20175  *    crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The
20176  *    command FSM state is represented using 19 bits.
20177  */
20178 #define SDIF_STATUS_CMDFSMSTATES(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
20179 
20180 #define SDIF_STATUS_DATA_3_STATUS_MASK           (0x100U)
20181 #define SDIF_STATUS_DATA_3_STATUS_SHIFT          (8U)
20182 /*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.
20183  */
20184 #define SDIF_STATUS_DATA_3_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
20185 
20186 #define SDIF_STATUS_DATA_BUSY_MASK               (0x200U)
20187 #define SDIF_STATUS_DATA_BUSY_SHIFT              (9U)
20188 /*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.
20189  */
20190 #define SDIF_STATUS_DATA_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
20191 
20192 #define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK      (0x400U)
20193 #define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT     (10U)
20194 /*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy.
20195  */
20196 #define SDIF_STATUS_DATA_STATE_MC_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
20197 
20198 #define SDIF_STATUS_RESPONSE_INDEX_MASK          (0x1F800U)
20199 #define SDIF_STATUS_RESPONSE_INDEX_SHIFT         (11U)
20200 /*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core.
20201  */
20202 #define SDIF_STATUS_RESPONSE_INDEX(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
20203 
20204 #define SDIF_STATUS_FIFO_COUNT_MASK              (0x3FFE0000U)
20205 #define SDIF_STATUS_FIFO_COUNT_SHIFT             (17U)
20206 /*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO.
20207  */
20208 #define SDIF_STATUS_FIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
20209 
20210 #define SDIF_STATUS_DMA_ACK_MASK                 (0x40000000U)
20211 #define SDIF_STATUS_DMA_ACK_SHIFT                (30U)
20212 /*! DMA_ACK - DMA acknowledge signal state.
20213  */
20214 #define SDIF_STATUS_DMA_ACK(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
20215 
20216 #define SDIF_STATUS_DMA_REQ_MASK                 (0x80000000U)
20217 #define SDIF_STATUS_DMA_REQ_SHIFT                (31U)
20218 /*! DMA_REQ - DMA request signal state.
20219  */
20220 #define SDIF_STATUS_DMA_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
20221 /*! @} */
20222 
20223 /*! @name FIFOTH - FIFO Threshold Watermark register */
20224 /*! @{ */
20225 
20226 #define SDIF_FIFOTH_TX_WMARK_MASK                (0xFFFU)
20227 #define SDIF_FIFOTH_TX_WMARK_SHIFT               (0U)
20228 /*! TX_WMARK - FIFO threshold watermark level when transmitting data to card.
20229  */
20230 #define SDIF_FIFOTH_TX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
20231 
20232 #define SDIF_FIFOTH_RX_WMARK_MASK                (0xFFF0000U)
20233 #define SDIF_FIFOTH_RX_WMARK_SHIFT               (16U)
20234 /*! RX_WMARK - FIFO threshold watermark level when receiving data to card.
20235  */
20236 #define SDIF_FIFOTH_RX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
20237 
20238 #define SDIF_FIFOTH_DMA_MTS_MASK                 (0x70000000U)
20239 #define SDIF_FIFOTH_DMA_MTS_SHIFT                (28U)
20240 /*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller
20241  *    multiple-transaction-size SRC/DEST_MSIZE.
20242  */
20243 #define SDIF_FIFOTH_DMA_MTS(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
20244 /*! @} */
20245 
20246 /*! @name CDETECT - Card Detect register */
20247 /*! @{ */
20248 
20249 #define SDIF_CDETECT_CARD0_DETECT_MASK           (0x1U)
20250 #define SDIF_CDETECT_CARD0_DETECT_SHIFT          (0U)
20251 /*! CARD0_DETECT - Card 0 detect
20252  */
20253 #define SDIF_CDETECT_CARD0_DETECT(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK)
20254 
20255 #define SDIF_CDETECT_CARD1_DETECT_MASK           (0x2U)
20256 #define SDIF_CDETECT_CARD1_DETECT_SHIFT          (1U)
20257 /*! CARD1_DETECT - Card 1 detect
20258  */
20259 #define SDIF_CDETECT_CARD1_DETECT(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK)
20260 /*! @} */
20261 
20262 /*! @name WRTPRT - Write Protect register */
20263 /*! @{ */
20264 
20265 #define SDIF_WRTPRT_WRITE_PROTECT_MASK           (0x1U)
20266 #define SDIF_WRTPRT_WRITE_PROTECT_SHIFT          (0U)
20267 /*! WRITE_PROTECT - Write protect.
20268  */
20269 #define SDIF_WRTPRT_WRITE_PROTECT(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
20270 /*! @} */
20271 
20272 /*! @name TCBCNT - Transferred CIU Card Byte Count register */
20273 /*! @{ */
20274 
20275 #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK   (0xFFFFFFFFU)
20276 #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT  (0U)
20277 /*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card.
20278  */
20279 #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
20280 /*! @} */
20281 
20282 /*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
20283 /*! @{ */
20284 
20285 #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK   (0xFFFFFFFFU)
20286 #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT  (0U)
20287 /*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO.
20288  */
20289 #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
20290 /*! @} */
20291 
20292 /*! @name DEBNCE - Debounce Count register */
20293 /*! @{ */
20294 
20295 #define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK          (0xFFFFFFU)
20296 #define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT         (0U)
20297 /*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.
20298  */
20299 #define SDIF_DEBNCE_DEBOUNCE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
20300 /*! @} */
20301 
20302 /*! @name RST_N - Hardware Reset */
20303 /*! @{ */
20304 
20305 #define SDIF_RST_N_CARD_RESET_MASK               (0x1U)
20306 #define SDIF_RST_N_CARD_RESET_SHIFT              (0U)
20307 /*! CARD_RESET - Hardware reset.
20308  */
20309 #define SDIF_RST_N_CARD_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
20310 /*! @} */
20311 
20312 /*! @name BMOD - Bus Mode register */
20313 /*! @{ */
20314 
20315 #define SDIF_BMOD_SWR_MASK                       (0x1U)
20316 #define SDIF_BMOD_SWR_SHIFT                      (0U)
20317 /*! SWR - Software Reset.
20318  */
20319 #define SDIF_BMOD_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
20320 
20321 #define SDIF_BMOD_FB_MASK                        (0x2U)
20322 #define SDIF_BMOD_FB_SHIFT                       (1U)
20323 /*! FB - Fixed Burst.
20324  */
20325 #define SDIF_BMOD_FB(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
20326 
20327 #define SDIF_BMOD_DSL_MASK                       (0x7CU)
20328 #define SDIF_BMOD_DSL_SHIFT                      (2U)
20329 /*! DSL - Descriptor Skip Length.
20330  */
20331 #define SDIF_BMOD_DSL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
20332 
20333 #define SDIF_BMOD_DE_MASK                        (0x80U)
20334 #define SDIF_BMOD_DE_SHIFT                       (7U)
20335 /*! DE - SD/MMC DMA Enable.
20336  */
20337 #define SDIF_BMOD_DE(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
20338 
20339 #define SDIF_BMOD_PBL_MASK                       (0x700U)
20340 #define SDIF_BMOD_PBL_SHIFT                      (8U)
20341 /*! PBL - Programmable Burst Length.
20342  */
20343 #define SDIF_BMOD_PBL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
20344 /*! @} */
20345 
20346 /*! @name PLDMND - Poll Demand register */
20347 /*! @{ */
20348 
20349 #define SDIF_PLDMND_PD_MASK                      (0xFFFFFFFFU)
20350 #define SDIF_PLDMND_PD_SHIFT                     (0U)
20351 /*! PD - Poll Demand.
20352  */
20353 #define SDIF_PLDMND_PD(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
20354 /*! @} */
20355 
20356 /*! @name DBADDR - Descriptor List Base Address register */
20357 /*! @{ */
20358 
20359 #define SDIF_DBADDR_SDL_MASK                     (0xFFFFFFFFU)
20360 #define SDIF_DBADDR_SDL_SHIFT                    (0U)
20361 /*! SDL - Start of Descriptor List.
20362  */
20363 #define SDIF_DBADDR_SDL(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
20364 /*! @} */
20365 
20366 /*! @name IDSTS - Internal DMAC Status register */
20367 /*! @{ */
20368 
20369 #define SDIF_IDSTS_TI_MASK                       (0x1U)
20370 #define SDIF_IDSTS_TI_SHIFT                      (0U)
20371 /*! TI - Transmit Interrupt.
20372  */
20373 #define SDIF_IDSTS_TI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
20374 
20375 #define SDIF_IDSTS_RI_MASK                       (0x2U)
20376 #define SDIF_IDSTS_RI_SHIFT                      (1U)
20377 /*! RI - Receive Interrupt.
20378  */
20379 #define SDIF_IDSTS_RI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
20380 
20381 #define SDIF_IDSTS_FBE_MASK                      (0x4U)
20382 #define SDIF_IDSTS_FBE_SHIFT                     (2U)
20383 /*! FBE - Fatal Bus Error Interrupt.
20384  */
20385 #define SDIF_IDSTS_FBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
20386 
20387 #define SDIF_IDSTS_DU_MASK                       (0x10U)
20388 #define SDIF_IDSTS_DU_SHIFT                      (4U)
20389 /*! DU - Descriptor Unavailable Interrupt.
20390  */
20391 #define SDIF_IDSTS_DU(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
20392 
20393 #define SDIF_IDSTS_CES_MASK                      (0x20U)
20394 #define SDIF_IDSTS_CES_SHIFT                     (5U)
20395 /*! CES - Card Error Summary.
20396  */
20397 #define SDIF_IDSTS_CES(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
20398 
20399 #define SDIF_IDSTS_NIS_MASK                      (0x100U)
20400 #define SDIF_IDSTS_NIS_SHIFT                     (8U)
20401 /*! NIS - Normal Interrupt Summary.
20402  */
20403 #define SDIF_IDSTS_NIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
20404 
20405 #define SDIF_IDSTS_AIS_MASK                      (0x200U)
20406 #define SDIF_IDSTS_AIS_SHIFT                     (9U)
20407 /*! AIS - Abnormal Interrupt Summary.
20408  */
20409 #define SDIF_IDSTS_AIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
20410 
20411 #define SDIF_IDSTS_EB_MASK                       (0x1C00U)
20412 #define SDIF_IDSTS_EB_SHIFT                      (10U)
20413 /*! EB - Error Bits.
20414  */
20415 #define SDIF_IDSTS_EB(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
20416 
20417 #define SDIF_IDSTS_FSM_MASK                      (0x1E000U)
20418 #define SDIF_IDSTS_FSM_SHIFT                     (13U)
20419 /*! FSM - DMAC state machine present state.
20420  */
20421 #define SDIF_IDSTS_FSM(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
20422 /*! @} */
20423 
20424 /*! @name IDINTEN - Internal DMAC Interrupt Enable register */
20425 /*! @{ */
20426 
20427 #define SDIF_IDINTEN_TI_MASK                     (0x1U)
20428 #define SDIF_IDINTEN_TI_SHIFT                    (0U)
20429 /*! TI - Transmit Interrupt Enable.
20430  */
20431 #define SDIF_IDINTEN_TI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
20432 
20433 #define SDIF_IDINTEN_RI_MASK                     (0x2U)
20434 #define SDIF_IDINTEN_RI_SHIFT                    (1U)
20435 /*! RI - Receive Interrupt Enable.
20436  */
20437 #define SDIF_IDINTEN_RI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
20438 
20439 #define SDIF_IDINTEN_FBE_MASK                    (0x4U)
20440 #define SDIF_IDINTEN_FBE_SHIFT                   (2U)
20441 /*! FBE - Fatal Bus Error Enable.
20442  */
20443 #define SDIF_IDINTEN_FBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
20444 
20445 #define SDIF_IDINTEN_DU_MASK                     (0x10U)
20446 #define SDIF_IDINTEN_DU_SHIFT                    (4U)
20447 /*! DU - Descriptor Unavailable Interrupt.
20448  */
20449 #define SDIF_IDINTEN_DU(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
20450 
20451 #define SDIF_IDINTEN_CES_MASK                    (0x20U)
20452 #define SDIF_IDINTEN_CES_SHIFT                   (5U)
20453 /*! CES - Card Error summary Interrupt Enable.
20454  */
20455 #define SDIF_IDINTEN_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
20456 
20457 #define SDIF_IDINTEN_NIS_MASK                    (0x100U)
20458 #define SDIF_IDINTEN_NIS_SHIFT                   (8U)
20459 /*! NIS - Normal Interrupt Summary Enable.
20460  */
20461 #define SDIF_IDINTEN_NIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
20462 
20463 #define SDIF_IDINTEN_AIS_MASK                    (0x200U)
20464 #define SDIF_IDINTEN_AIS_SHIFT                   (9U)
20465 /*! AIS - Abnormal Interrupt Summary Enable.
20466  */
20467 #define SDIF_IDINTEN_AIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
20468 /*! @} */
20469 
20470 /*! @name DSCADDR - Current Host Descriptor Address register */
20471 /*! @{ */
20472 
20473 #define SDIF_DSCADDR_HDA_MASK                    (0xFFFFFFFFU)
20474 #define SDIF_DSCADDR_HDA_SHIFT                   (0U)
20475 /*! HDA - Host Descriptor Address Pointer.
20476  */
20477 #define SDIF_DSCADDR_HDA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
20478 /*! @} */
20479 
20480 /*! @name BUFADDR - Current Buffer Descriptor Address register */
20481 /*! @{ */
20482 
20483 #define SDIF_BUFADDR_HBA_MASK                    (0xFFFFFFFFU)
20484 #define SDIF_BUFADDR_HBA_SHIFT                   (0U)
20485 /*! HBA - Host Buffer Address Pointer.
20486  */
20487 #define SDIF_BUFADDR_HBA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
20488 /*! @} */
20489 
20490 /*! @name CARDTHRCTL - Card Threshold Control */
20491 /*! @{ */
20492 
20493 #define SDIF_CARDTHRCTL_CARDRDTHREN_MASK         (0x1U)
20494 #define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT        (0U)
20495 /*! CARDRDTHREN - Card Read Threshold Enable.
20496  */
20497 #define SDIF_CARDTHRCTL_CARDRDTHREN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
20498 
20499 #define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK         (0x2U)
20500 #define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT        (1U)
20501 /*! BSYCLRINTEN - Busy Clear Interrupt Enable.
20502  */
20503 #define SDIF_CARDTHRCTL_BSYCLRINTEN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
20504 
20505 #define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK       (0xFF0000U)
20506 #define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT      (16U)
20507 /*! CARDTHRESHOLD - Card Threshold size.
20508  */
20509 #define SDIF_CARDTHRCTL_CARDTHRESHOLD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
20510 /*! @} */
20511 
20512 /*! @name BACKENDPWR - Power control */
20513 /*! @{ */
20514 
20515 #define SDIF_BACKENDPWR_BACKENDPWR_MASK          (0x1U)
20516 #define SDIF_BACKENDPWR_BACKENDPWR_SHIFT         (0U)
20517 /*! BACKENDPWR - Back-end Power control for card application.
20518  */
20519 #define SDIF_BACKENDPWR_BACKENDPWR(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
20520 /*! @} */
20521 
20522 /*! @name FIFO - SDIF FIFO */
20523 /*! @{ */
20524 
20525 #define SDIF_FIFO_DATA_MASK                      (0xFFFFFFFFU)
20526 #define SDIF_FIFO_DATA_SHIFT                     (0U)
20527 /*! DATA - SDIF FIFO.
20528  */
20529 #define SDIF_FIFO_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
20530 /*! @} */
20531 
20532 /* The count of SDIF_FIFO */
20533 #define SDIF_FIFO_COUNT                          (64U)
20534 
20535 
20536 /*!
20537  * @}
20538  */ /* end of group SDIF_Register_Masks */
20539 
20540 
20541 /* SDIF - Peripheral instance base addresses */
20542 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
20543   /** Peripheral SDIF base address */
20544   #define SDIF_BASE                                (0x5009B000u)
20545   /** Peripheral SDIF base address */
20546   #define SDIF_BASE_NS                             (0x4009B000u)
20547   /** Peripheral SDIF base pointer */
20548   #define SDIF                                     ((SDIF_Type *)SDIF_BASE)
20549   /** Peripheral SDIF base pointer */
20550   #define SDIF_NS                                  ((SDIF_Type *)SDIF_BASE_NS)
20551   /** Array initializer of SDIF peripheral base addresses */
20552   #define SDIF_BASE_ADDRS                          { SDIF_BASE }
20553   /** Array initializer of SDIF peripheral base pointers */
20554   #define SDIF_BASE_PTRS                           { SDIF }
20555   /** Array initializer of SDIF peripheral base addresses */
20556   #define SDIF_BASE_ADDRS_NS                       { SDIF_BASE_NS }
20557   /** Array initializer of SDIF peripheral base pointers */
20558   #define SDIF_BASE_PTRS_NS                        { SDIF_NS }
20559 #else
20560   /** Peripheral SDIF base address */
20561   #define SDIF_BASE                                (0x4009B000u)
20562   /** Peripheral SDIF base pointer */
20563   #define SDIF                                     ((SDIF_Type *)SDIF_BASE)
20564   /** Array initializer of SDIF peripheral base addresses */
20565   #define SDIF_BASE_ADDRS                          { SDIF_BASE }
20566   /** Array initializer of SDIF peripheral base pointers */
20567   #define SDIF_BASE_PTRS                           { SDIF }
20568 #endif
20569 /** Interrupt vectors for the SDIF peripheral type */
20570 #define SDIF_IRQS                                { SDIO_IRQn }
20571 
20572 /*!
20573  * @}
20574  */ /* end of group SDIF_Peripheral_Access_Layer */
20575 
20576 
20577 /* ----------------------------------------------------------------------------
20578    -- SPI Peripheral Access Layer
20579    ---------------------------------------------------------------------------- */
20580 
20581 /*!
20582  * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
20583  * @{
20584  */
20585 
20586 /** SPI - Register Layout Typedef */
20587 typedef struct {
20588        uint8_t RESERVED_0[1024];
20589   __IO uint32_t CFG;                               /**< SPI Configuration register, offset: 0x400 */
20590   __IO uint32_t DLY;                               /**< SPI Delay register, offset: 0x404 */
20591   __IO uint32_t STAT;                              /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
20592   __IO uint32_t INTENSET;                          /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
20593   __O  uint32_t INTENCLR;                          /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
20594        uint8_t RESERVED_1[16];
20595   __IO uint32_t DIV;                               /**< SPI clock Divider, offset: 0x424 */
20596   __I  uint32_t INTSTAT;                           /**< SPI Interrupt Status, offset: 0x428 */
20597        uint8_t RESERVED_2[2516];
20598   __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
20599   __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
20600   __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
20601        uint8_t RESERVED_3[4];
20602   __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
20603   __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
20604   __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
20605        uint8_t RESERVED_4[4];
20606   __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
20607        uint8_t RESERVED_5[12];
20608   __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
20609        uint8_t RESERVED_6[12];
20610   __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
20611        uint8_t RESERVED_7[4];
20612   __I  uint32_t FIFOSIZE;                          /**< FIFO size register, offset: 0xE48 */
20613        uint8_t RESERVED_8[432];
20614   __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
20615 } SPI_Type;
20616 
20617 /* ----------------------------------------------------------------------------
20618    -- SPI Register Masks
20619    ---------------------------------------------------------------------------- */
20620 
20621 /*!
20622  * @addtogroup SPI_Register_Masks SPI Register Masks
20623  * @{
20624  */
20625 
20626 /*! @name CFG - SPI Configuration register */
20627 /*! @{ */
20628 
20629 #define SPI_CFG_ENABLE_MASK                      (0x1U)
20630 #define SPI_CFG_ENABLE_SHIFT                     (0U)
20631 /*! ENABLE - SPI enable.
20632  *  0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
20633  *  0b1..Enabled. The SPI is enabled for operation.
20634  */
20635 #define SPI_CFG_ENABLE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
20636 
20637 #define SPI_CFG_MASTER_MASK                      (0x4U)
20638 #define SPI_CFG_MASTER_SHIFT                     (2U)
20639 /*! MASTER - Master mode select.
20640  *  0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
20641  *  0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
20642  */
20643 #define SPI_CFG_MASTER(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
20644 
20645 #define SPI_CFG_LSBF_MASK                        (0x8U)
20646 #define SPI_CFG_LSBF_SHIFT                       (3U)
20647 /*! LSBF - LSB First mode enable.
20648  *  0b0..Standard. Data is transmitted and received in standard MSB first order.
20649  *  0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
20650  */
20651 #define SPI_CFG_LSBF(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
20652 
20653 #define SPI_CFG_CPHA_MASK                        (0x10U)
20654 #define SPI_CFG_CPHA_SHIFT                       (4U)
20655 /*! CPHA - Clock Phase select.
20656  *  0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock
20657  *       changes away from the rest state). Data is changed on the following edge.
20658  *  0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock
20659  *       changes away from the rest state). Data is captured on the following edge.
20660  */
20661 #define SPI_CFG_CPHA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
20662 
20663 #define SPI_CFG_CPOL_MASK                        (0x20U)
20664 #define SPI_CFG_CPOL_SHIFT                       (5U)
20665 /*! CPOL - Clock Polarity select.
20666  *  0b0..Low. The rest state of the clock (between transfers) is low.
20667  *  0b1..High. The rest state of the clock (between transfers) is high.
20668  */
20669 #define SPI_CFG_CPOL(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
20670 
20671 #define SPI_CFG_LOOP_MASK                        (0x80U)
20672 #define SPI_CFG_LOOP_SHIFT                       (7U)
20673 /*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit
20674  *    and receive data connected together to allow simple software testing.
20675  *  0b0..Disabled.
20676  *  0b1..Enabled.
20677  */
20678 #define SPI_CFG_LOOP(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
20679 
20680 #define SPI_CFG_SPOL0_MASK                       (0x100U)
20681 #define SPI_CFG_SPOL0_SHIFT                      (8U)
20682 /*! SPOL0 - SSEL0 Polarity select.
20683  *  0b0..Low. The SSEL0 pin is active low.
20684  *  0b1..High. The SSEL0 pin is active high.
20685  */
20686 #define SPI_CFG_SPOL0(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
20687 
20688 #define SPI_CFG_SPOL1_MASK                       (0x200U)
20689 #define SPI_CFG_SPOL1_SHIFT                      (9U)
20690 /*! SPOL1 - SSEL1 Polarity select.
20691  *  0b0..Low. The SSEL1 pin is active low.
20692  *  0b1..High. The SSEL1 pin is active high.
20693  */
20694 #define SPI_CFG_SPOL1(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
20695 
20696 #define SPI_CFG_SPOL2_MASK                       (0x400U)
20697 #define SPI_CFG_SPOL2_SHIFT                      (10U)
20698 /*! SPOL2 - SSEL2 Polarity select.
20699  *  0b0..Low. The SSEL2 pin is active low.
20700  *  0b1..High. The SSEL2 pin is active high.
20701  */
20702 #define SPI_CFG_SPOL2(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
20703 
20704 #define SPI_CFG_SPOL3_MASK                       (0x800U)
20705 #define SPI_CFG_SPOL3_SHIFT                      (11U)
20706 /*! SPOL3 - SSEL3 Polarity select.
20707  *  0b0..Low. The SSEL3 pin is active low.
20708  *  0b1..High. The SSEL3 pin is active high.
20709  */
20710 #define SPI_CFG_SPOL3(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
20711 /*! @} */
20712 
20713 /*! @name DLY - SPI Delay register */
20714 /*! @{ */
20715 
20716 #define SPI_DLY_PRE_DELAY_MASK                   (0xFU)
20717 #define SPI_DLY_PRE_DELAY_SHIFT                  (0U)
20718 /*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data
20719  *    transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This
20720  *    is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI
20721  *    clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are
20722  *    inserted.
20723  */
20724 #define SPI_DLY_PRE_DELAY(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
20725 
20726 #define SPI_DLY_POST_DELAY_MASK                  (0xF0U)
20727 #define SPI_DLY_POST_DELAY_SHIFT                 (4U)
20728 /*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL
20729  *    deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock
20730  *    times are inserted. 0xF = 15 SPI clock times are inserted.
20731  */
20732 #define SPI_DLY_POST_DELAY(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
20733 
20734 #define SPI_DLY_FRAME_DELAY_MASK                 (0xF00U)
20735 #define SPI_DLY_FRAME_DELAY_SHIFT                (8U)
20736 /*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current
20737  *    frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1
20738  *    = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock
20739  *    times are inserted.
20740  */
20741 #define SPI_DLY_FRAME_DELAY(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
20742 
20743 #define SPI_DLY_TRANSFER_DELAY_MASK              (0xF000U)
20744 #define SPI_DLY_TRANSFER_DELAY_SHIFT             (12U)
20745 /*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between
20746  *    transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1
20747  *    = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that
20748  *    SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16
20749  *    SPI clock times.
20750  */
20751 #define SPI_DLY_TRANSFER_DELAY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
20752 /*! @} */
20753 
20754 /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
20755 /*! @{ */
20756 
20757 #define SPI_STAT_SSA_MASK                        (0x10U)
20758 #define SPI_STAT_SSA_SHIFT                       (4U)
20759 /*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from
20760  *    deasserted to asserted, in both master and slave modes. This allows determining when the SPI
20761  *    transmit/receive functions become busy, and allows waking up the device from reduced power modes when a
20762  *    slave mode access begins. This flag is cleared by software.
20763  */
20764 #define SPI_STAT_SSA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
20765 
20766 #define SPI_STAT_SSD_MASK                        (0x20U)
20767 #define SPI_STAT_SSD_SHIFT                       (5U)
20768 /*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to
20769  *    deasserted, in both master and slave modes. This allows determining when the SPI
20770  *    transmit/receive functions become idle. This flag is cleared by software.
20771  */
20772 #define SPI_STAT_SSD(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
20773 
20774 #define SPI_STAT_STALLED_MASK                    (0x40U)
20775 #define SPI_STAT_STALLED_SHIFT                   (6U)
20776 /*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition.
20777  */
20778 #define SPI_STAT_STALLED(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
20779 
20780 #define SPI_STAT_ENDTRANSFER_MASK                (0x80U)
20781 #define SPI_STAT_ENDTRANSFER_SHIFT               (7U)
20782 /*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current
20783  *    transfer when the transmitter finishes any activity already in progress, as if the EOT flag
20784  *    had been set prior to the last transmission. This capability is included to support cases where
20785  *    it is not known when transmit data is written that it will be the end of a transfer. The bit
20786  *    is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end
20787  *    of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
20788  */
20789 #define SPI_STAT_ENDTRANSFER(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
20790 
20791 #define SPI_STAT_MSTIDLE_MASK                    (0x100U)
20792 #define SPI_STAT_MSTIDLE_SHIFT                   (8U)
20793 /*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle.
20794  *    This means that the transmit holding register is empty and the transmitter is not in the
20795  *    process of sending data.
20796  */
20797 #define SPI_STAT_MSTIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
20798 /*! @} */
20799 
20800 /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
20801 /*! @{ */
20802 
20803 #define SPI_INTENSET_SSAEN_MASK                  (0x10U)
20804 #define SPI_INTENSET_SSAEN_SHIFT                 (4U)
20805 /*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.
20806  *  0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
20807  *  0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
20808  */
20809 #define SPI_INTENSET_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
20810 
20811 #define SPI_INTENSET_SSDEN_MASK                  (0x20U)
20812 #define SPI_INTENSET_SSDEN_SHIFT                 (5U)
20813 /*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.
20814  *  0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
20815  *  0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
20816  */
20817 #define SPI_INTENSET_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
20818 
20819 #define SPI_INTENSET_MSTIDLEEN_MASK              (0x100U)
20820 #define SPI_INTENSET_MSTIDLEEN_SHIFT             (8U)
20821 /*! MSTIDLEEN - Master idle interrupt enable.
20822  *  0b0..No interrupt will be generated when the SPI master function is idle.
20823  *  0b1..An interrupt will be generated when the SPI master function is fully idle.
20824  */
20825 #define SPI_INTENSET_MSTIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
20826 /*! @} */
20827 
20828 /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
20829 /*! @{ */
20830 
20831 #define SPI_INTENCLR_SSAEN_MASK                  (0x10U)
20832 #define SPI_INTENCLR_SSAEN_SHIFT                 (4U)
20833 /*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register.
20834  */
20835 #define SPI_INTENCLR_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
20836 
20837 #define SPI_INTENCLR_SSDEN_MASK                  (0x20U)
20838 #define SPI_INTENCLR_SSDEN_SHIFT                 (5U)
20839 /*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register.
20840  */
20841 #define SPI_INTENCLR_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
20842 
20843 #define SPI_INTENCLR_MSTIDLE_MASK                (0x100U)
20844 #define SPI_INTENCLR_MSTIDLE_SHIFT               (8U)
20845 /*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register.
20846  */
20847 #define SPI_INTENCLR_MSTIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
20848 /*! @} */
20849 
20850 /*! @name DIV - SPI clock Divider */
20851 /*! @{ */
20852 
20853 #define SPI_DIV_DIVVAL_MASK                      (0xFFFFU)
20854 #define SPI_DIV_DIVVAL_SHIFT                     (0U)
20855 /*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the
20856  *    SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1,
20857  *    the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results
20858  *    in FCLK/65536.
20859  */
20860 #define SPI_DIV_DIVVAL(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
20861 /*! @} */
20862 
20863 /*! @name INTSTAT - SPI Interrupt Status */
20864 /*! @{ */
20865 
20866 #define SPI_INTSTAT_SSA_MASK                     (0x10U)
20867 #define SPI_INTSTAT_SSA_SHIFT                    (4U)
20868 /*! SSA - Slave Select Assert.
20869  */
20870 #define SPI_INTSTAT_SSA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
20871 
20872 #define SPI_INTSTAT_SSD_MASK                     (0x20U)
20873 #define SPI_INTSTAT_SSD_SHIFT                    (5U)
20874 /*! SSD - Slave Select Deassert.
20875  */
20876 #define SPI_INTSTAT_SSD(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
20877 
20878 #define SPI_INTSTAT_MSTIDLE_MASK                 (0x100U)
20879 #define SPI_INTSTAT_MSTIDLE_SHIFT                (8U)
20880 /*! MSTIDLE - Master Idle status flag.
20881  */
20882 #define SPI_INTSTAT_MSTIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
20883 /*! @} */
20884 
20885 /*! @name FIFOCFG - FIFO configuration and enable register. */
20886 /*! @{ */
20887 
20888 #define SPI_FIFOCFG_ENABLETX_MASK                (0x1U)
20889 #define SPI_FIFOCFG_ENABLETX_SHIFT               (0U)
20890 /*! ENABLETX - Enable the transmit FIFO.
20891  *  0b0..The transmit FIFO is not enabled.
20892  *  0b1..The transmit FIFO is enabled.
20893  */
20894 #define SPI_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
20895 
20896 #define SPI_FIFOCFG_ENABLERX_MASK                (0x2U)
20897 #define SPI_FIFOCFG_ENABLERX_SHIFT               (1U)
20898 /*! ENABLERX - Enable the receive FIFO.
20899  *  0b0..The receive FIFO is not enabled.
20900  *  0b1..The receive FIFO is enabled.
20901  */
20902 #define SPI_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
20903 
20904 #define SPI_FIFOCFG_SIZE_MASK                    (0x30U)
20905 #define SPI_FIFOCFG_SIZE_SHIFT                   (4U)
20906 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
20907  *    entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
20908  */
20909 #define SPI_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
20910 
20911 #define SPI_FIFOCFG_DMATX_MASK                   (0x1000U)
20912 #define SPI_FIFOCFG_DMATX_SHIFT                  (12U)
20913 /*! DMATX - DMA configuration for transmit.
20914  *  0b0..DMA is not used for the transmit function.
20915  *  0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
20916  */
20917 #define SPI_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
20918 
20919 #define SPI_FIFOCFG_DMARX_MASK                   (0x2000U)
20920 #define SPI_FIFOCFG_DMARX_SHIFT                  (13U)
20921 /*! DMARX - DMA configuration for receive.
20922  *  0b0..DMA is not used for the receive function.
20923  *  0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
20924  */
20925 #define SPI_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
20926 
20927 #define SPI_FIFOCFG_WAKETX_MASK                  (0x4000U)
20928 #define SPI_FIFOCFG_WAKETX_SHIFT                 (14U)
20929 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
20930  *    modes (up to power-down, as long as the peripheral function works in that power mode) without
20931  *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
20932  *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
20933  *    Wake-up control register.
20934  *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
20935  *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
20936  *       FIFOTRIG, even when the TXLVL interrupt is not enabled.
20937  */
20938 #define SPI_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
20939 
20940 #define SPI_FIFOCFG_WAKERX_MASK                  (0x8000U)
20941 #define SPI_FIFOCFG_WAKERX_SHIFT                 (15U)
20942 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
20943  *    modes (up to power-down, as long as the peripheral function works in that power mode) without
20944  *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
20945  *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
20946  *    Wake-up control register.
20947  *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
20948  *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
20949  *       FIFOTRIG, even when the RXLVL interrupt is not enabled.
20950  */
20951 #define SPI_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
20952 
20953 #define SPI_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
20954 #define SPI_FIFOCFG_EMPTYTX_SHIFT                (16U)
20955 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
20956  */
20957 #define SPI_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
20958 
20959 #define SPI_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
20960 #define SPI_FIFOCFG_EMPTYRX_SHIFT                (17U)
20961 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
20962  */
20963 #define SPI_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
20964 /*! @} */
20965 
20966 /*! @name FIFOSTAT - FIFO status register. */
20967 /*! @{ */
20968 
20969 #define SPI_FIFOSTAT_TXERR_MASK                  (0x1U)
20970 #define SPI_FIFOSTAT_TXERR_SHIFT                 (0U)
20971 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
20972  *    caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
20973  *    needed. Cleared by writing a 1 to this bit.
20974  */
20975 #define SPI_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
20976 
20977 #define SPI_FIFOSTAT_RXERR_MASK                  (0x2U)
20978 #define SPI_FIFOSTAT_RXERR_SHIFT                 (1U)
20979 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
20980  *    not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
20981  */
20982 #define SPI_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
20983 
20984 #define SPI_FIFOSTAT_PERINT_MASK                 (0x8U)
20985 #define SPI_FIFOSTAT_PERINT_SHIFT                (3U)
20986 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
20987  *    an interrupt. The details can be found by reading the peripheral's STAT register.
20988  */
20989 #define SPI_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
20990 
20991 #define SPI_FIFOSTAT_TXEMPTY_MASK                (0x10U)
20992 #define SPI_FIFOSTAT_TXEMPTY_SHIFT               (4U)
20993 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
20994  */
20995 #define SPI_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
20996 
20997 #define SPI_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
20998 #define SPI_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
20999 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
21000  *    written. When 0, the transmit FIFO is full and another write would cause it to overflow.
21001  */
21002 #define SPI_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
21003 
21004 #define SPI_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
21005 #define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
21006 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
21007  */
21008 #define SPI_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
21009 
21010 #define SPI_FIFOSTAT_RXFULL_MASK                 (0x80U)
21011 #define SPI_FIFOSTAT_RXFULL_SHIFT                (7U)
21012 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
21013  *    prevent the peripheral from causing an overflow.
21014  */
21015 #define SPI_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
21016 
21017 #define SPI_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
21018 #define SPI_FIFOSTAT_TXLVL_SHIFT                 (8U)
21019 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
21020  *    and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
21021  *    the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
21022  *    0.
21023  */
21024 #define SPI_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
21025 
21026 #define SPI_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
21027 #define SPI_FIFOSTAT_RXLVL_SHIFT                 (16U)
21028 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
21029  *    RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
21030  *    point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
21031  *    1.
21032  */
21033 #define SPI_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
21034 /*! @} */
21035 
21036 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
21037 /*! @{ */
21038 
21039 #define SPI_FIFOTRIG_TXLVLENA_MASK               (0x1U)
21040 #define SPI_FIFOTRIG_TXLVLENA_SHIFT              (0U)
21041 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
21042  *    in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
21043  *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
21044  *  0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
21045  */
21046 #define SPI_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
21047 
21048 #define SPI_FIFOTRIG_RXLVLENA_MASK               (0x2U)
21049 #define SPI_FIFOTRIG_RXLVLENA_SHIFT              (1U)
21050 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
21051  *    in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
21052  *  0b0..Receive FIFO level does not generate a FIFO level trigger.
21053  *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
21054  */
21055 #define SPI_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
21056 
21057 #define SPI_FIFOTRIG_TXLVL_MASK                  (0xF00U)
21058 #define SPI_FIFOTRIG_TXLVL_SHIFT                 (8U)
21059 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
21060  *    to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
21061  *    the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
21062  *    becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
21063  *    FIFO level decreases to 15 entries (is no longer full).
21064  */
21065 #define SPI_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
21066 
21067 #define SPI_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
21068 #define SPI_FIFOTRIG_RXLVL_SHIFT                 (16U)
21069 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
21070  *    is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
21071  *    can wake up the device just enough to perform DMA, then return to the reduced power mode. See
21072  *    Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
21073  *    longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
21074  *    FIFO has received 16 entries (has become full).
21075  */
21076 #define SPI_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
21077 /*! @} */
21078 
21079 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
21080 /*! @{ */
21081 
21082 #define SPI_FIFOINTENSET_TXERR_MASK              (0x1U)
21083 #define SPI_FIFOINTENSET_TXERR_SHIFT             (0U)
21084 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
21085  *  0b0..No interrupt will be generated for a transmit error.
21086  *  0b1..An interrupt will be generated when a transmit error occurs.
21087  */
21088 #define SPI_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
21089 
21090 #define SPI_FIFOINTENSET_RXERR_MASK              (0x2U)
21091 #define SPI_FIFOINTENSET_RXERR_SHIFT             (1U)
21092 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
21093  *  0b0..No interrupt will be generated for a receive error.
21094  *  0b1..An interrupt will be generated when a receive error occurs.
21095  */
21096 #define SPI_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
21097 
21098 #define SPI_FIFOINTENSET_TXLVL_MASK              (0x4U)
21099 #define SPI_FIFOINTENSET_TXLVL_SHIFT             (2U)
21100 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
21101  *    specified by the TXLVL field in the FIFOTRIG register.
21102  *  0b0..No interrupt will be generated based on the TX FIFO level.
21103  *  0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
21104  *       to the level specified by TXLVL in the FIFOTRIG register.
21105  */
21106 #define SPI_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
21107 
21108 #define SPI_FIFOINTENSET_RXLVL_MASK              (0x8U)
21109 #define SPI_FIFOINTENSET_RXLVL_SHIFT             (3U)
21110 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
21111  *    specified by the TXLVL field in the FIFOTRIG register.
21112  *  0b0..No interrupt will be generated based on the RX FIFO level.
21113  *  0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
21114  *       increases to the level specified by RXLVL in the FIFOTRIG register.
21115  */
21116 #define SPI_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
21117 /*! @} */
21118 
21119 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
21120 /*! @{ */
21121 
21122 #define SPI_FIFOINTENCLR_TXERR_MASK              (0x1U)
21123 #define SPI_FIFOINTENCLR_TXERR_SHIFT             (0U)
21124 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
21125  */
21126 #define SPI_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
21127 
21128 #define SPI_FIFOINTENCLR_RXERR_MASK              (0x2U)
21129 #define SPI_FIFOINTENCLR_RXERR_SHIFT             (1U)
21130 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
21131  */
21132 #define SPI_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
21133 
21134 #define SPI_FIFOINTENCLR_TXLVL_MASK              (0x4U)
21135 #define SPI_FIFOINTENCLR_TXLVL_SHIFT             (2U)
21136 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
21137  */
21138 #define SPI_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
21139 
21140 #define SPI_FIFOINTENCLR_RXLVL_MASK              (0x8U)
21141 #define SPI_FIFOINTENCLR_RXLVL_SHIFT             (3U)
21142 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
21143  */
21144 #define SPI_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
21145 /*! @} */
21146 
21147 /*! @name FIFOINTSTAT - FIFO interrupt status register. */
21148 /*! @{ */
21149 
21150 #define SPI_FIFOINTSTAT_TXERR_MASK               (0x1U)
21151 #define SPI_FIFOINTSTAT_TXERR_SHIFT              (0U)
21152 /*! TXERR - TX FIFO error.
21153  */
21154 #define SPI_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
21155 
21156 #define SPI_FIFOINTSTAT_RXERR_MASK               (0x2U)
21157 #define SPI_FIFOINTSTAT_RXERR_SHIFT              (1U)
21158 /*! RXERR - RX FIFO error.
21159  */
21160 #define SPI_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
21161 
21162 #define SPI_FIFOINTSTAT_TXLVL_MASK               (0x4U)
21163 #define SPI_FIFOINTSTAT_TXLVL_SHIFT              (2U)
21164 /*! TXLVL - Transmit FIFO level interrupt.
21165  */
21166 #define SPI_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
21167 
21168 #define SPI_FIFOINTSTAT_RXLVL_MASK               (0x8U)
21169 #define SPI_FIFOINTSTAT_RXLVL_SHIFT              (3U)
21170 /*! RXLVL - Receive FIFO level interrupt.
21171  */
21172 #define SPI_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
21173 
21174 #define SPI_FIFOINTSTAT_PERINT_MASK              (0x10U)
21175 #define SPI_FIFOINTSTAT_PERINT_SHIFT             (4U)
21176 /*! PERINT - Peripheral interrupt.
21177  */
21178 #define SPI_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
21179 /*! @} */
21180 
21181 /*! @name FIFOWR - FIFO write data. */
21182 /*! @{ */
21183 
21184 #define SPI_FIFOWR_TXDATA_MASK                   (0xFFFFU)
21185 #define SPI_FIFOWR_TXDATA_SHIFT                  (0U)
21186 /*! TXDATA - Transmit data to the FIFO.
21187  */
21188 #define SPI_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
21189 
21190 #define SPI_FIFOWR_TXSSEL0_N_MASK                (0x10000U)
21191 #define SPI_FIFOWR_TXSSEL0_N_SHIFT               (16U)
21192 /*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.
21193  *  0b0..SSEL0 asserted.
21194  *  0b1..SSEL0 not asserted.
21195  */
21196 #define SPI_FIFOWR_TXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
21197 
21198 #define SPI_FIFOWR_TXSSEL1_N_MASK                (0x20000U)
21199 #define SPI_FIFOWR_TXSSEL1_N_SHIFT               (17U)
21200 /*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.
21201  *  0b0..SSEL1 asserted.
21202  *  0b1..SSEL1 not asserted.
21203  */
21204 #define SPI_FIFOWR_TXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
21205 
21206 #define SPI_FIFOWR_TXSSEL2_N_MASK                (0x40000U)
21207 #define SPI_FIFOWR_TXSSEL2_N_SHIFT               (18U)
21208 /*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.
21209  *  0b0..SSEL2 asserted.
21210  *  0b1..SSEL2 not asserted.
21211  */
21212 #define SPI_FIFOWR_TXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
21213 
21214 #define SPI_FIFOWR_TXSSEL3_N_MASK                (0x80000U)
21215 #define SPI_FIFOWR_TXSSEL3_N_SHIFT               (19U)
21216 /*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.
21217  *  0b0..SSEL3 asserted.
21218  *  0b1..SSEL3 not asserted.
21219  */
21220 #define SPI_FIFOWR_TXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
21221 
21222 #define SPI_FIFOWR_EOT_MASK                      (0x100000U)
21223 #define SPI_FIFOWR_EOT_SHIFT                     (20U)
21224 /*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain
21225  *    so far at least the time specified by the Transfer_delay value in the DLY register.
21226  *  0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
21227  *  0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
21228  */
21229 #define SPI_FIFOWR_EOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
21230 
21231 #define SPI_FIFOWR_EOF_MASK                      (0x200000U)
21232 #define SPI_FIFOWR_EOF_SHIFT                     (21U)
21233 /*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value
21234  *    in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay
21235  *    value = 0. This control can be used as part of the support for frame lengths greater than 16
21236  *    bits.
21237  *  0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.
21238  *  0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be
21239  *       inserted before subsequent data is transmitted.
21240  */
21241 #define SPI_FIFOWR_EOF(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
21242 
21243 #define SPI_FIFOWR_RXIGNORE_MASK                 (0x400000U)
21244 #define SPI_FIFOWR_RXIGNORE_SHIFT                (22U)
21245 /*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to
21246  *    read unneeded data from the receiver. Setting this bit simplifies the transmit process and can
21247  *    be used with the DMA.
21248  *  0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit
21249  *       will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data
21250  *       is not read before new data is received.
21251  *  0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received
21252  *       data. No receiver flags are generated.
21253  */
21254 #define SPI_FIFOWR_RXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
21255 
21256 #define SPI_FIFOWR_LEN_MASK                      (0xF000000U)
21257 #define SPI_FIFOWR_LEN_SHIFT                     (24U)
21258 /*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths
21259  *    greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved.
21260  *    0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data
21261  *    transfer is 16 bits in length.
21262  */
21263 #define SPI_FIFOWR_LEN(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
21264 /*! @} */
21265 
21266 /*! @name FIFORD - FIFO read data. */
21267 /*! @{ */
21268 
21269 #define SPI_FIFORD_RXDATA_MASK                   (0xFFFFU)
21270 #define SPI_FIFORD_RXDATA_SHIFT                  (0U)
21271 /*! RXDATA - Received data from the FIFO.
21272  */
21273 #define SPI_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
21274 
21275 #define SPI_FIFORD_RXSSEL0_N_MASK                (0x10000U)
21276 #define SPI_FIFORD_RXSSEL0_N_SHIFT               (16U)
21277 /*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved
21278  *    along with received data. The value will reflect the SSEL0 pin for both master and slave
21279  *    operation. A zero indicates that a slave select is active. The actual polarity of each slave select
21280  *    pin is configured by the related SPOL bit in CFG.
21281  */
21282 #define SPI_FIFORD_RXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
21283 
21284 #define SPI_FIFORD_RXSSEL1_N_MASK                (0x20000U)
21285 #define SPI_FIFORD_RXSSEL1_N_SHIFT               (17U)
21286 /*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved
21287  *    along with received data. The value will reflect the SSEL1 pin for both master and slave
21288  *    operation. A zero indicates that a slave select is active. The actual polarity of each slave select
21289  *    pin is configured by the related SPOL bit in CFG.
21290  */
21291 #define SPI_FIFORD_RXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
21292 
21293 #define SPI_FIFORD_RXSSEL2_N_MASK                (0x40000U)
21294 #define SPI_FIFORD_RXSSEL2_N_SHIFT               (18U)
21295 /*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved
21296  *    along with received data. The value will reflect the SSEL2 pin for both master and slave
21297  *    operation. A zero indicates that a slave select is active. The actual polarity of each slave select
21298  *    pin is configured by the related SPOL bit in CFG.
21299  */
21300 #define SPI_FIFORD_RXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
21301 
21302 #define SPI_FIFORD_RXSSEL3_N_MASK                (0x80000U)
21303 #define SPI_FIFORD_RXSSEL3_N_SHIFT               (19U)
21304 /*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
21305  *    along with received data. The value will reflect the SSEL3 pin for both master and slave
21306  *    operation. A zero indicates that a slave select is active. The actual polarity of each slave select
21307  *    pin is configured by the related SPOL bit in CFG.
21308  */
21309 #define SPI_FIFORD_RXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
21310 
21311 #define SPI_FIFORD_SOT_MASK                      (0x100000U)
21312 #define SPI_FIFORD_SOT_SHIFT                     (20U)
21313 /*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
21314  *    from deasserted to asserted (i.e., any previous transfer has ended). This information can be
21315  *    used to identify the first piece of data in cases where the transfer length is greater than 16
21316  *    bits.
21317  */
21318 #define SPI_FIFORD_SOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
21319 /*! @} */
21320 
21321 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
21322 /*! @{ */
21323 
21324 #define SPI_FIFORDNOPOP_RXDATA_MASK              (0xFFFFU)
21325 #define SPI_FIFORDNOPOP_RXDATA_SHIFT             (0U)
21326 /*! RXDATA - Received data from the FIFO.
21327  */
21328 #define SPI_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
21329 
21330 #define SPI_FIFORDNOPOP_RXSSEL0_N_MASK           (0x10000U)
21331 #define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT          (16U)
21332 /*! RXSSEL0_N - Slave Select for receive.
21333  */
21334 #define SPI_FIFORDNOPOP_RXSSEL0_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
21335 
21336 #define SPI_FIFORDNOPOP_RXSSEL1_N_MASK           (0x20000U)
21337 #define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT          (17U)
21338 /*! RXSSEL1_N - Slave Select for receive.
21339  */
21340 #define SPI_FIFORDNOPOP_RXSSEL1_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
21341 
21342 #define SPI_FIFORDNOPOP_RXSSEL2_N_MASK           (0x40000U)
21343 #define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT          (18U)
21344 /*! RXSSEL2_N - Slave Select for receive.
21345  */
21346 #define SPI_FIFORDNOPOP_RXSSEL2_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
21347 
21348 #define SPI_FIFORDNOPOP_RXSSEL3_N_MASK           (0x80000U)
21349 #define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT          (19U)
21350 /*! RXSSEL3_N - Slave Select for receive.
21351  */
21352 #define SPI_FIFORDNOPOP_RXSSEL3_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
21353 
21354 #define SPI_FIFORDNOPOP_SOT_MASK                 (0x100000U)
21355 #define SPI_FIFORDNOPOP_SOT_SHIFT                (20U)
21356 /*! SOT - Start of transfer flag.
21357  */
21358 #define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
21359 /*! @} */
21360 
21361 /*! @name FIFOSIZE - FIFO size register */
21362 /*! @{ */
21363 
21364 #define SPI_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)
21365 #define SPI_FIFOSIZE_FIFOSIZE_SHIFT              (0U)
21366 /*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries.
21367  */
21368 #define SPI_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK)
21369 /*! @} */
21370 
21371 /*! @name ID - Peripheral identification register. */
21372 /*! @{ */
21373 
21374 #define SPI_ID_APERTURE_MASK                     (0xFFU)
21375 #define SPI_ID_APERTURE_SHIFT                    (0U)
21376 /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
21377  */
21378 #define SPI_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
21379 
21380 #define SPI_ID_MINOR_REV_MASK                    (0xF00U)
21381 #define SPI_ID_MINOR_REV_SHIFT                   (8U)
21382 /*! MINOR_REV - Minor revision of module implementation.
21383  */
21384 #define SPI_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
21385 
21386 #define SPI_ID_MAJOR_REV_MASK                    (0xF000U)
21387 #define SPI_ID_MAJOR_REV_SHIFT                   (12U)
21388 /*! MAJOR_REV - Major revision of module implementation.
21389  */
21390 #define SPI_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
21391 
21392 #define SPI_ID_ID_MASK                           (0xFFFF0000U)
21393 #define SPI_ID_ID_SHIFT                          (16U)
21394 /*! ID - Module identifier for the selected function.
21395  */
21396 #define SPI_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
21397 /*! @} */
21398 
21399 
21400 /*!
21401  * @}
21402  */ /* end of group SPI_Register_Masks */
21403 
21404 
21405 /* SPI - Peripheral instance base addresses */
21406 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
21407   /** Peripheral SPI0 base address */
21408   #define SPI0_BASE                                (0x50086000u)
21409   /** Peripheral SPI0 base address */
21410   #define SPI0_BASE_NS                             (0x40086000u)
21411   /** Peripheral SPI0 base pointer */
21412   #define SPI0                                     ((SPI_Type *)SPI0_BASE)
21413   /** Peripheral SPI0 base pointer */
21414   #define SPI0_NS                                  ((SPI_Type *)SPI0_BASE_NS)
21415   /** Peripheral SPI1 base address */
21416   #define SPI1_BASE                                (0x50087000u)
21417   /** Peripheral SPI1 base address */
21418   #define SPI1_BASE_NS                             (0x40087000u)
21419   /** Peripheral SPI1 base pointer */
21420   #define SPI1                                     ((SPI_Type *)SPI1_BASE)
21421   /** Peripheral SPI1 base pointer */
21422   #define SPI1_NS                                  ((SPI_Type *)SPI1_BASE_NS)
21423   /** Peripheral SPI2 base address */
21424   #define SPI2_BASE                                (0x50088000u)
21425   /** Peripheral SPI2 base address */
21426   #define SPI2_BASE_NS                             (0x40088000u)
21427   /** Peripheral SPI2 base pointer */
21428   #define SPI2                                     ((SPI_Type *)SPI2_BASE)
21429   /** Peripheral SPI2 base pointer */
21430   #define SPI2_NS                                  ((SPI_Type *)SPI2_BASE_NS)
21431   /** Peripheral SPI3 base address */
21432   #define SPI3_BASE                                (0x50089000u)
21433   /** Peripheral SPI3 base address */
21434   #define SPI3_BASE_NS                             (0x40089000u)
21435   /** Peripheral SPI3 base pointer */
21436   #define SPI3                                     ((SPI_Type *)SPI3_BASE)
21437   /** Peripheral SPI3 base pointer */
21438   #define SPI3_NS                                  ((SPI_Type *)SPI3_BASE_NS)
21439   /** Peripheral SPI4 base address */
21440   #define SPI4_BASE                                (0x5008A000u)
21441   /** Peripheral SPI4 base address */
21442   #define SPI4_BASE_NS                             (0x4008A000u)
21443   /** Peripheral SPI4 base pointer */
21444   #define SPI4                                     ((SPI_Type *)SPI4_BASE)
21445   /** Peripheral SPI4 base pointer */
21446   #define SPI4_NS                                  ((SPI_Type *)SPI4_BASE_NS)
21447   /** Peripheral SPI5 base address */
21448   #define SPI5_BASE                                (0x50096000u)
21449   /** Peripheral SPI5 base address */
21450   #define SPI5_BASE_NS                             (0x40096000u)
21451   /** Peripheral SPI5 base pointer */
21452   #define SPI5                                     ((SPI_Type *)SPI5_BASE)
21453   /** Peripheral SPI5 base pointer */
21454   #define SPI5_NS                                  ((SPI_Type *)SPI5_BASE_NS)
21455   /** Peripheral SPI6 base address */
21456   #define SPI6_BASE                                (0x50097000u)
21457   /** Peripheral SPI6 base address */
21458   #define SPI6_BASE_NS                             (0x40097000u)
21459   /** Peripheral SPI6 base pointer */
21460   #define SPI6                                     ((SPI_Type *)SPI6_BASE)
21461   /** Peripheral SPI6 base pointer */
21462   #define SPI6_NS                                  ((SPI_Type *)SPI6_BASE_NS)
21463   /** Peripheral SPI7 base address */
21464   #define SPI7_BASE                                (0x50098000u)
21465   /** Peripheral SPI7 base address */
21466   #define SPI7_BASE_NS                             (0x40098000u)
21467   /** Peripheral SPI7 base pointer */
21468   #define SPI7                                     ((SPI_Type *)SPI7_BASE)
21469   /** Peripheral SPI7 base pointer */
21470   #define SPI7_NS                                  ((SPI_Type *)SPI7_BASE_NS)
21471   /** Peripheral SPI8 base address */
21472   #define SPI8_BASE                                (0x5009F000u)
21473   /** Peripheral SPI8 base address */
21474   #define SPI8_BASE_NS                             (0x4009F000u)
21475   /** Peripheral SPI8 base pointer */
21476   #define SPI8                                     ((SPI_Type *)SPI8_BASE)
21477   /** Peripheral SPI8 base pointer */
21478   #define SPI8_NS                                  ((SPI_Type *)SPI8_BASE_NS)
21479   /** Array initializer of SPI peripheral base addresses */
21480   #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE }
21481   /** Array initializer of SPI peripheral base pointers */
21482   #define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 }
21483   /** Array initializer of SPI peripheral base addresses */
21484   #define SPI_BASE_ADDRS_NS                        { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS }
21485   /** Array initializer of SPI peripheral base pointers */
21486   #define SPI_BASE_PTRS_NS                         { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS }
21487 #else
21488   /** Peripheral SPI0 base address */
21489   #define SPI0_BASE                                (0x40086000u)
21490   /** Peripheral SPI0 base pointer */
21491   #define SPI0                                     ((SPI_Type *)SPI0_BASE)
21492   /** Peripheral SPI1 base address */
21493   #define SPI1_BASE                                (0x40087000u)
21494   /** Peripheral SPI1 base pointer */
21495   #define SPI1                                     ((SPI_Type *)SPI1_BASE)
21496   /** Peripheral SPI2 base address */
21497   #define SPI2_BASE                                (0x40088000u)
21498   /** Peripheral SPI2 base pointer */
21499   #define SPI2                                     ((SPI_Type *)SPI2_BASE)
21500   /** Peripheral SPI3 base address */
21501   #define SPI3_BASE                                (0x40089000u)
21502   /** Peripheral SPI3 base pointer */
21503   #define SPI3                                     ((SPI_Type *)SPI3_BASE)
21504   /** Peripheral SPI4 base address */
21505   #define SPI4_BASE                                (0x4008A000u)
21506   /** Peripheral SPI4 base pointer */
21507   #define SPI4                                     ((SPI_Type *)SPI4_BASE)
21508   /** Peripheral SPI5 base address */
21509   #define SPI5_BASE                                (0x40096000u)
21510   /** Peripheral SPI5 base pointer */
21511   #define SPI5                                     ((SPI_Type *)SPI5_BASE)
21512   /** Peripheral SPI6 base address */
21513   #define SPI6_BASE                                (0x40097000u)
21514   /** Peripheral SPI6 base pointer */
21515   #define SPI6                                     ((SPI_Type *)SPI6_BASE)
21516   /** Peripheral SPI7 base address */
21517   #define SPI7_BASE                                (0x40098000u)
21518   /** Peripheral SPI7 base pointer */
21519   #define SPI7                                     ((SPI_Type *)SPI7_BASE)
21520   /** Peripheral SPI8 base address */
21521   #define SPI8_BASE                                (0x4009F000u)
21522   /** Peripheral SPI8 base pointer */
21523   #define SPI8                                     ((SPI_Type *)SPI8_BASE)
21524   /** Array initializer of SPI peripheral base addresses */
21525   #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE }
21526   /** Array initializer of SPI peripheral base pointers */
21527   #define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 }
21528 #endif
21529 /** Interrupt vectors for the SPI peripheral type */
21530 #define SPI_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn }
21531 
21532 /*!
21533  * @}
21534  */ /* end of group SPI_Peripheral_Access_Layer */
21535 
21536 
21537 /* ----------------------------------------------------------------------------
21538    -- SYSCON Peripheral Access Layer
21539    ---------------------------------------------------------------------------- */
21540 
21541 /*!
21542  * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
21543  * @{
21544  */
21545 
21546 /** SYSCON - Register Layout Typedef */
21547 typedef struct {
21548   __IO uint32_t MEMORYREMAP;                       /**< Memory Remap control register, offset: 0x0 */
21549        uint8_t RESERVED_0[12];
21550   __IO uint32_t AHBMATPRIO;                        /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */
21551        uint8_t RESERVED_1[36];
21552   __IO uint32_t CPU0STCKCAL;                       /**< System tick calibration for secure part of CPU0, offset: 0x38 */
21553   __IO uint32_t CPU0NSTCKCAL;                      /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */
21554   __IO uint32_t CPU1STCKCAL;                       /**< System tick calibration for CPU1, offset: 0x40 */
21555        uint8_t RESERVED_2[4];
21556   __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x48 */
21557        uint8_t RESERVED_3[180];
21558   union {                                          /* offset: 0x100 */
21559     struct {                                         /* offset: 0x100 */
21560       __IO uint32_t PRESETCTRL0;                       /**< Peripheral reset control 0, offset: 0x100 */
21561       __IO uint32_t PRESETCTRL1;                       /**< Peripheral reset control 1, offset: 0x104 */
21562       __IO uint32_t PRESETCTRL2;                       /**< Peripheral reset control 2, offset: 0x108 */
21563     } PRESETCTRL;
21564     __IO uint32_t PRESETCTRLX[3];                    /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */
21565   };
21566        uint8_t RESERVED_4[20];
21567   __IO uint32_t PRESETCTRLSET[3];                  /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */
21568        uint8_t RESERVED_5[20];
21569   __IO uint32_t PRESETCTRLCLR[3];                  /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */
21570        uint8_t RESERVED_6[20];
21571   __O  uint32_t SWR_RESET;                         /**< generate a software_reset, offset: 0x160 */
21572        uint8_t RESERVED_7[156];
21573   union {                                          /* offset: 0x200 */
21574     struct {                                         /* offset: 0x200 */
21575       __IO uint32_t AHBCLKCTRL0;                       /**< AHB Clock control 0, offset: 0x200 */
21576       __IO uint32_t AHBCLKCTRL1;                       /**< AHB Clock control 1, offset: 0x204 */
21577       __IO uint32_t AHBCLKCTRL2;                       /**< AHB Clock control 2, offset: 0x208 */
21578     } AHBCLKCTRL;
21579     __IO uint32_t AHBCLKCTRLX[3];                    /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */
21580   };
21581        uint8_t RESERVED_8[20];
21582   __IO uint32_t AHBCLKCTRLSET[3];                  /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */
21583        uint8_t RESERVED_9[20];
21584   __IO uint32_t AHBCLKCTRLCLR[3];                  /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */
21585        uint8_t RESERVED_10[20];
21586   union {                                          /* offset: 0x260 */
21587     struct {                                         /* offset: 0x260 */
21588       __IO uint32_t SYSTICKCLKSEL0;                    /**< System Tick Timer for CPU0 source select, offset: 0x260 */
21589       __IO uint32_t SYSTICKCLKSEL1;                    /**< System Tick Timer for CPU1 source select, offset: 0x264 */
21590     } SYSTICKCLKSEL;
21591     __IO uint32_t SYSTICKCLKSELX[2];                 /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */
21592   };
21593   __IO uint32_t TRACECLKSEL;                       /**< Trace clock source select, offset: 0x268 */
21594   union {                                          /* offset: 0x26C */
21595     struct {                                         /* offset: 0x26C */
21596       __IO uint32_t CTIMERCLKSEL0;                     /**< CTimer 0 clock source select, offset: 0x26C */
21597       __IO uint32_t CTIMERCLKSEL1;                     /**< CTimer 1 clock source select, offset: 0x270 */
21598       __IO uint32_t CTIMERCLKSEL2;                     /**< CTimer 2 clock source select, offset: 0x274 */
21599       __IO uint32_t CTIMERCLKSEL3;                     /**< CTimer 3 clock source select, offset: 0x278 */
21600       __IO uint32_t CTIMERCLKSEL4;                     /**< CTimer 4 clock source select, offset: 0x27C */
21601     } CTIMERCLKSEL;
21602     __IO uint32_t CTIMERCLKSELX[5];                  /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */
21603   };
21604   __IO uint32_t MAINCLKSELA;                       /**< Main clock A source select, offset: 0x280 */
21605   __IO uint32_t MAINCLKSELB;                       /**< Main clock source select, offset: 0x284 */
21606   __IO uint32_t CLKOUTSEL;                         /**< CLKOUT clock source select, offset: 0x288 */
21607        uint8_t RESERVED_11[4];
21608   __IO uint32_t PLL0CLKSEL;                        /**< PLL0 clock source select, offset: 0x290 */
21609   __IO uint32_t PLL1CLKSEL;                        /**< PLL1 clock source select, offset: 0x294 */
21610        uint8_t RESERVED_12[12];
21611   __IO uint32_t ADCCLKSEL;                         /**< ADC clock source select, offset: 0x2A4 */
21612   __IO uint32_t USB0CLKSEL;                        /**< FS USB clock source select, offset: 0x2A8 */
21613        uint8_t RESERVED_13[4];
21614   union {                                          /* offset: 0x2B0 */
21615     struct {                                         /* offset: 0x2B0 */
21616       __IO uint32_t FCCLKSEL0;                         /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */
21617       __IO uint32_t FCCLKSEL1;                         /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */
21618       __IO uint32_t FCCLKSEL2;                         /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */
21619       __IO uint32_t FCCLKSEL3;                         /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */
21620       __IO uint32_t FCCLKSEL4;                         /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */
21621       __IO uint32_t FCCLKSEL5;                         /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */
21622       __IO uint32_t FCCLKSEL6;                         /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */
21623       __IO uint32_t FCCLKSEL7;                         /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */
21624     } FCCLKSEL;
21625     __IO uint32_t FCCLKSELX[8];                      /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */
21626   };
21627   __IO uint32_t HSLSPICLKSEL;                      /**< HS LSPI clock source select, offset: 0x2D0 */
21628        uint8_t RESERVED_14[12];
21629   __IO uint32_t MCLKCLKSEL;                        /**< MCLK clock source select, offset: 0x2E0 */
21630        uint8_t RESERVED_15[12];
21631   __IO uint32_t SCTCLKSEL;                         /**< SCTimer/PWM clock source select, offset: 0x2F0 */
21632        uint8_t RESERVED_16[4];
21633   __IO uint32_t SDIOCLKSEL;                        /**< SDIO clock source select, offset: 0x2F8 */
21634        uint8_t RESERVED_17[4];
21635   __IO uint32_t SYSTICKCLKDIV0;                    /**< System Tick Timer divider for CPU0, offset: 0x300 */
21636   __IO uint32_t SYSTICKCLKDIV1;                    /**< System Tick Timer divider for CPU1, offset: 0x304 */
21637   __IO uint32_t TRACECLKDIV;                       /**< TRACE clock divider, offset: 0x308 */
21638        uint8_t RESERVED_18[20];
21639   union {                                          /* offset: 0x320 */
21640     struct {                                         /* offset: 0x320 */
21641       __IO uint32_t FLEXFRG0CTRL;                      /**< Fractional rate divider for flexcomm 0, offset: 0x320 */
21642       __IO uint32_t FLEXFRG1CTRL;                      /**< Fractional rate divider for flexcomm 1, offset: 0x324 */
21643       __IO uint32_t FLEXFRG2CTRL;                      /**< Fractional rate divider for flexcomm 2, offset: 0x328 */
21644       __IO uint32_t FLEXFRG3CTRL;                      /**< Fractional rate divider for flexcomm 3, offset: 0x32C */
21645       __IO uint32_t FLEXFRG4CTRL;                      /**< Fractional rate divider for flexcomm 4, offset: 0x330 */
21646       __IO uint32_t FLEXFRG5CTRL;                      /**< Fractional rate divider for flexcomm 5, offset: 0x334 */
21647       __IO uint32_t FLEXFRG6CTRL;                      /**< Fractional rate divider for flexcomm 6, offset: 0x338 */
21648       __IO uint32_t FLEXFRG7CTRL;                      /**< Fractional rate divider for flexcomm 7, offset: 0x33C */
21649     } FLEXFRGCTRL;
21650     __IO uint32_t FLEXFRGXCTRL[8];                   /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */
21651   };
21652        uint8_t RESERVED_19[64];
21653   __IO uint32_t AHBCLKDIV;                         /**< System clock divider, offset: 0x380 */
21654   __IO uint32_t CLKOUTDIV;                         /**< CLKOUT clock divider, offset: 0x384 */
21655   __IO uint32_t FROHFDIV;                          /**< FRO_HF (96MHz) clock divider, offset: 0x388 */
21656   __IO uint32_t WDTCLKDIV;                         /**< WDT clock divider, offset: 0x38C */
21657        uint8_t RESERVED_20[4];
21658   __IO uint32_t ADCCLKDIV;                         /**< ADC clock divider, offset: 0x394 */
21659   __IO uint32_t USB0CLKDIV;                        /**< USB0 Clock divider, offset: 0x398 */
21660        uint8_t RESERVED_21[16];
21661   __IO uint32_t MCLKDIV;                           /**< I2S MCLK clock divider, offset: 0x3AC */
21662        uint8_t RESERVED_22[4];
21663   __IO uint32_t SCTCLKDIV;                         /**< SCT/PWM clock divider, offset: 0x3B4 */
21664        uint8_t RESERVED_23[4];
21665   __IO uint32_t SDIOCLKDIV;                        /**< SDIO clock divider, offset: 0x3BC */
21666        uint8_t RESERVED_24[4];
21667   __IO uint32_t PLL0CLKDIV;                        /**< PLL0 clock divider, offset: 0x3C4 */
21668        uint8_t RESERVED_25[52];
21669   __IO uint32_t CLOCKGENUPDATELOCKOUT;             /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */
21670   __IO uint32_t FMCCR;                             /**< FMC configuration register, offset: 0x400 */
21671        uint8_t RESERVED_26[8];
21672   __IO uint32_t USB0NEEDCLKCTRL;                   /**< USB0 need clock control, offset: 0x40C */
21673   __I  uint32_t USB0NEEDCLKSTAT;                   /**< USB0 need clock status, offset: 0x410 */
21674        uint8_t RESERVED_27[8];
21675   __O  uint32_t FMCFLUSH;                          /**< FMCflush control, offset: 0x41C */
21676   __IO uint32_t MCLKIO;                            /**< MCLK control, offset: 0x420 */
21677   __IO uint32_t USB1NEEDCLKCTRL;                   /**< USB1 need clock control, offset: 0x424 */
21678   __I  uint32_t USB1NEEDCLKSTAT;                   /**< USB1 need clock status, offset: 0x428 */
21679        uint8_t RESERVED_28[52];
21680   __IO uint32_t SDIOCLKCTRL;                       /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
21681        uint8_t RESERVED_29[252];
21682   __IO uint32_t PLL1CTRL;                          /**< PLL1 550m control, offset: 0x560 */
21683   __I  uint32_t PLL1STAT;                          /**< PLL1 550m status, offset: 0x564 */
21684   __IO uint32_t PLL1NDEC;                          /**< PLL1 550m N divider, offset: 0x568 */
21685   __IO uint32_t PLL1MDEC;                          /**< PLL1 550m M divider, offset: 0x56C */
21686   __IO uint32_t PLL1PDEC;                          /**< PLL1 550m P divider, offset: 0x570 */
21687        uint8_t RESERVED_30[12];
21688   __IO uint32_t PLL0CTRL;                          /**< PLL0 550m control, offset: 0x580 */
21689   __I  uint32_t PLL0STAT;                          /**< PLL0 550m status, offset: 0x584 */
21690   __IO uint32_t PLL0NDEC;                          /**< PLL0 550m N divider, offset: 0x588 */
21691   __IO uint32_t PLL0PDEC;                          /**< PLL0 550m P divider, offset: 0x58C */
21692   __IO uint32_t PLL0SSCG0;                         /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */
21693   __IO uint32_t PLL0SSCG1;                         /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */
21694        uint8_t RESERVED_31[364];
21695   __IO uint32_t FUNCRETENTIONCTRL;                 /**< Functional retention control register, offset: 0x704 */
21696        uint8_t RESERVED_32[248];
21697   __IO uint32_t CPUCTRL;                           /**< CPU Control for multiple processors, offset: 0x800 */
21698   __IO uint32_t CPBOOT;                            /**< Coprocessor Boot Address, offset: 0x804 */
21699        uint8_t RESERVED_33[4];
21700   __I  uint32_t CPSTAT;                            /**< CPU Status, offset: 0x80C */
21701        uint8_t RESERVED_34[520];
21702   __IO uint32_t CLOCK_CTRL;                        /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */
21703        uint8_t RESERVED_35[244];
21704   __IO uint32_t COMP_INT_CTRL;                     /**< Comparator Interrupt control, offset: 0xB10 */
21705   __I  uint32_t COMP_INT_STATUS;                   /**< Comparator Interrupt status, offset: 0xB14 */
21706        uint8_t RESERVED_36[748];
21707   __IO uint32_t AUTOCLKGATEOVERRIDE;               /**< Control automatic clock gating, offset: 0xE04 */
21708   __IO uint32_t GPIOPSYNC;                         /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */
21709        uint8_t RESERVED_37[404];
21710   __IO uint32_t DEBUG_LOCK_EN;                     /**< Control write access to security registers., offset: 0xFA0 */
21711   __IO uint32_t DEBUG_FEATURES;                    /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */
21712   __IO uint32_t DEBUG_FEATURES_DP;                 /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */
21713        uint8_t RESERVED_38[16];
21714   __O  uint32_t KEY_BLOCK;                         /**< block quiddikey/PUF all index., offset: 0xFBC */
21715   __IO uint32_t DEBUG_AUTH_BEACON;                 /**< Debug authentication BEACON register, offset: 0xFC0 */
21716        uint8_t RESERVED_39[16];
21717   __IO uint32_t CPUCFG;                            /**< CPUs configuration register, offset: 0xFD4 */
21718        uint8_t RESERVED_40[32];
21719   __I  uint32_t DEVICE_ID0;                        /**< Device ID, offset: 0xFF8 */
21720   __I  uint32_t DIEID;                             /**< Chip revision ID and Number, offset: 0xFFC */
21721 } SYSCON_Type;
21722 
21723 /* ----------------------------------------------------------------------------
21724    -- SYSCON Register Masks
21725    ---------------------------------------------------------------------------- */
21726 
21727 /*!
21728  * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
21729  * @{
21730  */
21731 
21732 /*! @name MEMORYREMAP - Memory Remap control register */
21733 /*! @{ */
21734 
21735 #define SYSCON_MEMORYREMAP_MAP_MASK              (0x3U)
21736 #define SYSCON_MEMORYREMAP_MAP_SHIFT             (0U)
21737 /*! MAP - Select the location of the vector table :.
21738  *  0b00..Vector Table in ROM.
21739  *  0b01..Vector Table in RAM.
21740  *  0b10..Vector Table in Flash.
21741  *  0b11..Vector Table in Flash.
21742  */
21743 #define SYSCON_MEMORYREMAP_MAP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK)
21744 /*! @} */
21745 
21746 /*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */
21747 /*! @{ */
21748 
21749 #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK     (0x3U)
21750 #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT    (0U)
21751 /*! PRI_CPU0_CBUS - CPU0 C-AHB bus.
21752  */
21753 #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK)
21754 
21755 #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK     (0xCU)
21756 #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT    (2U)
21757 /*! PRI_CPU0_SBUS - CPU0 S-AHB bus.
21758  */
21759 #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK)
21760 
21761 #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK     (0x30U)
21762 #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT    (4U)
21763 /*! PRI_CPU1_CBUS - CPU1 C-AHB bus.
21764  */
21765 #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK)
21766 
21767 #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK     (0xC0U)
21768 #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT    (6U)
21769 /*! PRI_CPU1_SBUS - CPU1 S-AHB bus.
21770  */
21771 #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK)
21772 
21773 #define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK        (0x300U)
21774 #define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT       (8U)
21775 /*! PRI_USB_FS - USB-FS.(USB0)
21776  */
21777 #define SYSCON_AHBMATPRIO_PRI_USB_FS(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK)
21778 
21779 #define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK         (0xC00U)
21780 #define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT        (10U)
21781 /*! PRI_SDMA0 - DMA0 controller priority.
21782  */
21783 #define SYSCON_AHBMATPRIO_PRI_SDMA0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK)
21784 
21785 #define SYSCON_AHBMATPRIO_PRI_SDIO_MASK          (0x30000U)
21786 #define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT         (16U)
21787 /*! PRI_SDIO - SDIO.
21788  */
21789 #define SYSCON_AHBMATPRIO_PRI_SDIO(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
21790 
21791 #define SYSCON_AHBMATPRIO_PRI_PQ_MASK            (0xC0000U)
21792 #define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT           (18U)
21793 /*! PRI_PQ - PQ (HW Accelerator).
21794  */
21795 #define SYSCON_AHBMATPRIO_PRI_PQ(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK)
21796 
21797 #define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK      (0x300000U)
21798 #define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT     (20U)
21799 /*! PRI_HASH_AES - HASH_AES.
21800  */
21801 #define SYSCON_AHBMATPRIO_PRI_HASH_AES(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK)
21802 
21803 #define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK        (0xC00000U)
21804 #define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT       (22U)
21805 /*! PRI_USB_HS - USB-HS.(USB1)
21806  */
21807 #define SYSCON_AHBMATPRIO_PRI_USB_HS(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK)
21808 
21809 #define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK         (0x3000000U)
21810 #define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT        (24U)
21811 /*! PRI_SDMA1 - DMA1 controller priority.
21812  */
21813 #define SYSCON_AHBMATPRIO_PRI_SDMA1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK)
21814 /*! @} */
21815 
21816 /*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */
21817 /*! @{ */
21818 
21819 #define SYSCON_CPU0STCKCAL_TENMS_MASK            (0xFFFFFFU)
21820 #define SYSCON_CPU0STCKCAL_TENMS_SHIFT           (0U)
21821 /*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value
21822  *    reads as zero, the calibration value is not known.
21823  */
21824 #define SYSCON_CPU0STCKCAL_TENMS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK)
21825 
21826 #define SYSCON_CPU0STCKCAL_SKEW_MASK             (0x1000000U)
21827 #define SYSCON_CPU0STCKCAL_SKEW_SHIFT            (24U)
21828 /*! SKEW - Initial value for the Systick timer.
21829  */
21830 #define SYSCON_CPU0STCKCAL_SKEW(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK)
21831 
21832 #define SYSCON_CPU0STCKCAL_NOREF_MASK            (0x2000000U)
21833 #define SYSCON_CPU0STCKCAL_NOREF_SHIFT           (25U)
21834 /*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference
21835  *    clock provided; 1 = no reference clock provided.
21836  */
21837 #define SYSCON_CPU0STCKCAL_NOREF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK)
21838 /*! @} */
21839 
21840 /*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */
21841 /*! @{ */
21842 
21843 #define SYSCON_CPU0NSTCKCAL_TENMS_MASK           (0xFFFFFFU)
21844 #define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT          (0U)
21845 /*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the
21846  *    value reads as zero, the calibration value is not known.
21847  */
21848 #define SYSCON_CPU0NSTCKCAL_TENMS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK)
21849 
21850 #define SYSCON_CPU0NSTCKCAL_SKEW_MASK            (0x1000000U)
21851 #define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT           (24U)
21852 /*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given.
21853  */
21854 #define SYSCON_CPU0NSTCKCAL_SKEW(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK)
21855 
21856 #define SYSCON_CPU0NSTCKCAL_NOREF_MASK           (0x2000000U)
21857 #define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT          (25U)
21858 /*! NOREF - Initial value for the Systick timer.
21859  */
21860 #define SYSCON_CPU0NSTCKCAL_NOREF(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK)
21861 /*! @} */
21862 
21863 /*! @name CPU1STCKCAL - System tick calibration for CPU1 */
21864 /*! @{ */
21865 
21866 #define SYSCON_CPU1STCKCAL_TENMS_MASK            (0xFFFFFFU)
21867 #define SYSCON_CPU1STCKCAL_TENMS_SHIFT           (0U)
21868 /*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value
21869  *    reads as zero, the calibration value is not known.
21870  */
21871 #define SYSCON_CPU1STCKCAL_TENMS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK)
21872 
21873 #define SYSCON_CPU1STCKCAL_SKEW_MASK             (0x1000000U)
21874 #define SYSCON_CPU1STCKCAL_SKEW_SHIFT            (24U)
21875 /*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given.
21876  */
21877 #define SYSCON_CPU1STCKCAL_SKEW(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK)
21878 
21879 #define SYSCON_CPU1STCKCAL_NOREF_MASK            (0x2000000U)
21880 #define SYSCON_CPU1STCKCAL_NOREF_SHIFT           (25U)
21881 /*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference
21882  *    clock provided; 1 = no reference clock provided.
21883  */
21884 #define SYSCON_CPU1STCKCAL_NOREF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK)
21885 /*! @} */
21886 
21887 /*! @name NMISRC - NMI Source Select */
21888 /*! @{ */
21889 
21890 #define SYSCON_NMISRC_IRQCPU0_MASK               (0x3FU)
21891 #define SYSCON_NMISRC_IRQCPU0_SHIFT              (0U)
21892 /*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0.
21893  */
21894 #define SYSCON_NMISRC_IRQCPU0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK)
21895 
21896 #define SYSCON_NMISRC_IRQCPU1_MASK               (0x3F00U)
21897 #define SYSCON_NMISRC_IRQCPU1_SHIFT              (8U)
21898 /*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1.
21899  */
21900 #define SYSCON_NMISRC_IRQCPU1(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK)
21901 
21902 #define SYSCON_NMISRC_NMIENCPU1_MASK             (0x40000000U)
21903 #define SYSCON_NMISRC_NMIENCPU1_SHIFT            (30U)
21904 /*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1.
21905  */
21906 #define SYSCON_NMISRC_NMIENCPU1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK)
21907 
21908 #define SYSCON_NMISRC_NMIENCPU0_MASK             (0x80000000U)
21909 #define SYSCON_NMISRC_NMIENCPU0_SHIFT            (31U)
21910 /*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.
21911  */
21912 #define SYSCON_NMISRC_NMIENCPU0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK)
21913 /*! @} */
21914 
21915 /*! @name PRESETCTRL0 - Peripheral reset control 0 */
21916 /*! @{ */
21917 
21918 #define SYSCON_PRESETCTRL0_ROM_RST_MASK          (0x2U)
21919 #define SYSCON_PRESETCTRL0_ROM_RST_SHIFT         (1U)
21920 /*! ROM_RST - ROM reset control.
21921  *  0b1..Bloc is reset.
21922  *  0b0..Bloc is not reset.
21923  */
21924 #define SYSCON_PRESETCTRL0_ROM_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK)
21925 
21926 #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK   (0x8U)
21927 #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT  (3U)
21928 /*! SRAM_CTRL1_RST - SRAM Controller 1 reset control.
21929  *  0b1..Bloc is reset.
21930  *  0b0..Bloc is not reset.
21931  */
21932 #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK)
21933 
21934 #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK   (0x10U)
21935 #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT  (4U)
21936 /*! SRAM_CTRL2_RST - SRAM Controller 2 reset control.
21937  *  0b1..Bloc is reset.
21938  *  0b0..Bloc is not reset.
21939  */
21940 #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK)
21941 
21942 #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK   (0x20U)
21943 #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT  (5U)
21944 /*! SRAM_CTRL3_RST - SRAM Controller 3 reset control.
21945  *  0b1..Bloc is reset.
21946  *  0b0..Bloc is not reset.
21947  */
21948 #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK)
21949 
21950 #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK   (0x40U)
21951 #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT  (6U)
21952 /*! SRAM_CTRL4_RST - SRAM Controller 4 reset control.
21953  *  0b1..Bloc is reset.
21954  *  0b0..Bloc is not reset.
21955  */
21956 #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK)
21957 
21958 #define SYSCON_PRESETCTRL0_FLASH_RST_MASK        (0x80U)
21959 #define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT       (7U)
21960 /*! FLASH_RST - Flash controller reset control.
21961  *  0b1..Bloc is reset.
21962  *  0b0..Bloc is not reset.
21963  */
21964 #define SYSCON_PRESETCTRL0_FLASH_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK)
21965 
21966 #define SYSCON_PRESETCTRL0_FMC_RST_MASK          (0x100U)
21967 #define SYSCON_PRESETCTRL0_FMC_RST_SHIFT         (8U)
21968 /*! FMC_RST - FMC controller reset control.
21969  *  0b1..Bloc is reset.
21970  *  0b0..Bloc is not reset.
21971  */
21972 #define SYSCON_PRESETCTRL0_FMC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK)
21973 
21974 #define SYSCON_PRESETCTRL0_MUX_RST_MASK          (0x800U)
21975 #define SYSCON_PRESETCTRL0_MUX_RST_SHIFT         (11U)
21976 /*! MUX_RST - Input Mux reset control.
21977  *  0b1..Bloc is reset.
21978  *  0b0..Bloc is not reset.
21979  */
21980 #define SYSCON_PRESETCTRL0_MUX_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK)
21981 
21982 #define SYSCON_PRESETCTRL0_IOCON_RST_MASK        (0x2000U)
21983 #define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT       (13U)
21984 /*! IOCON_RST - I/O controller reset control.
21985  *  0b1..Bloc is reset.
21986  *  0b0..Bloc is not reset.
21987  */
21988 #define SYSCON_PRESETCTRL0_IOCON_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK)
21989 
21990 #define SYSCON_PRESETCTRL0_GPIO0_RST_MASK        (0x4000U)
21991 #define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT       (14U)
21992 /*! GPIO0_RST - GPIO0 reset control.
21993  *  0b1..Bloc is reset.
21994  *  0b0..Bloc is not reset.
21995  */
21996 #define SYSCON_PRESETCTRL0_GPIO0_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK)
21997 
21998 #define SYSCON_PRESETCTRL0_GPIO1_RST_MASK        (0x8000U)
21999 #define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT       (15U)
22000 /*! GPIO1_RST - GPIO1 reset control.
22001  *  0b1..Bloc is reset.
22002  *  0b0..Bloc is not reset.
22003  */
22004 #define SYSCON_PRESETCTRL0_GPIO1_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK)
22005 
22006 #define SYSCON_PRESETCTRL0_GPIO2_RST_MASK        (0x10000U)
22007 #define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT       (16U)
22008 /*! GPIO2_RST - GPIO2 reset control.
22009  *  0b1..Bloc is reset.
22010  *  0b0..Bloc is not reset.
22011  */
22012 #define SYSCON_PRESETCTRL0_GPIO2_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK)
22013 
22014 #define SYSCON_PRESETCTRL0_GPIO3_RST_MASK        (0x20000U)
22015 #define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT       (17U)
22016 /*! GPIO3_RST - GPIO3 reset control.
22017  *  0b1..Bloc is reset.
22018  *  0b0..Bloc is not reset.
22019  */
22020 #define SYSCON_PRESETCTRL0_GPIO3_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK)
22021 
22022 #define SYSCON_PRESETCTRL0_PINT_RST_MASK         (0x40000U)
22023 #define SYSCON_PRESETCTRL0_PINT_RST_SHIFT        (18U)
22024 /*! PINT_RST - Pin interrupt (PINT) reset control.
22025  *  0b1..Bloc is reset.
22026  *  0b0..Bloc is not reset.
22027  */
22028 #define SYSCON_PRESETCTRL0_PINT_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK)
22029 
22030 #define SYSCON_PRESETCTRL0_GINT_RST_MASK         (0x80000U)
22031 #define SYSCON_PRESETCTRL0_GINT_RST_SHIFT        (19U)
22032 /*! GINT_RST - Group interrupt (GINT) reset control.
22033  *  0b1..Bloc is reset.
22034  *  0b0..Bloc is not reset.
22035  */
22036 #define SYSCON_PRESETCTRL0_GINT_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK)
22037 
22038 #define SYSCON_PRESETCTRL0_DMA0_RST_MASK         (0x100000U)
22039 #define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT        (20U)
22040 /*! DMA0_RST - DMA0 reset control.
22041  *  0b1..Bloc is reset.
22042  *  0b0..Bloc is not reset.
22043  */
22044 #define SYSCON_PRESETCTRL0_DMA0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK)
22045 
22046 #define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK       (0x200000U)
22047 #define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT      (21U)
22048 /*! CRCGEN_RST - CRCGEN reset control.
22049  *  0b1..Bloc is reset.
22050  *  0b0..Bloc is not reset.
22051  */
22052 #define SYSCON_PRESETCTRL0_CRCGEN_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK)
22053 
22054 #define SYSCON_PRESETCTRL0_WWDT_RST_MASK         (0x400000U)
22055 #define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT        (22U)
22056 /*! WWDT_RST - Watchdog Timer reset control.
22057  *  0b1..Bloc is reset.
22058  *  0b0..Bloc is not reset.
22059  */
22060 #define SYSCON_PRESETCTRL0_WWDT_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK)
22061 
22062 #define SYSCON_PRESETCTRL0_RTC_RST_MASK          (0x800000U)
22063 #define SYSCON_PRESETCTRL0_RTC_RST_SHIFT         (23U)
22064 /*! RTC_RST - Real Time Clock (RTC) reset control.
22065  *  0b1..Bloc is reset.
22066  *  0b0..Bloc is not reset.
22067  */
22068 #define SYSCON_PRESETCTRL0_RTC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK)
22069 
22070 #define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK      (0x4000000U)
22071 #define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT     (26U)
22072 /*! MAILBOX_RST - Inter CPU communication Mailbox reset control.
22073  *  0b1..Bloc is reset.
22074  *  0b0..Bloc is not reset.
22075  */
22076 #define SYSCON_PRESETCTRL0_MAILBOX_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK)
22077 
22078 #define SYSCON_PRESETCTRL0_ADC_RST_MASK          (0x8000000U)
22079 #define SYSCON_PRESETCTRL0_ADC_RST_SHIFT         (27U)
22080 /*! ADC_RST - ADC reset control.
22081  *  0b1..Bloc is reset.
22082  *  0b0..Bloc is not reset.
22083  */
22084 #define SYSCON_PRESETCTRL0_ADC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK)
22085 /*! @} */
22086 
22087 /*! @name PRESETCTRL1 - Peripheral reset control 1 */
22088 /*! @{ */
22089 
22090 #define SYSCON_PRESETCTRL1_MRT_RST_MASK          (0x1U)
22091 #define SYSCON_PRESETCTRL1_MRT_RST_SHIFT         (0U)
22092 /*! MRT_RST - MRT reset control.
22093  *  0b1..Bloc is reset.
22094  *  0b0..Bloc is not reset.
22095  */
22096 #define SYSCON_PRESETCTRL1_MRT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK)
22097 
22098 #define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK      (0x2U)
22099 #define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT     (1U)
22100 /*! OSTIMER_RST - OS Event Timer reset control.
22101  *  0b1..Bloc is reset.
22102  *  0b0..Bloc is not reset.
22103  */
22104 #define SYSCON_PRESETCTRL1_OSTIMER_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK)
22105 
22106 #define SYSCON_PRESETCTRL1_SCT_RST_MASK          (0x4U)
22107 #define SYSCON_PRESETCTRL1_SCT_RST_SHIFT         (2U)
22108 /*! SCT_RST - SCT reset control.
22109  *  0b1..Bloc is reset.
22110  *  0b0..Bloc is not reset.
22111  */
22112 #define SYSCON_PRESETCTRL1_SCT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK)
22113 
22114 #define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK       (0x40U)
22115 #define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT      (6U)
22116 /*! SCTIPU_RST - SCTIPU reset control.
22117  *  0b1..Bloc is reset.
22118  *  0b0..Bloc is not reset.
22119  */
22120 #define SYSCON_PRESETCTRL1_SCTIPU_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK)
22121 
22122 #define SYSCON_PRESETCTRL1_UTICK_RST_MASK        (0x400U)
22123 #define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT       (10U)
22124 /*! UTICK_RST - UTICK reset control.
22125  *  0b1..Bloc is reset.
22126  *  0b0..Bloc is not reset.
22127  */
22128 #define SYSCON_PRESETCTRL1_UTICK_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK)
22129 
22130 #define SYSCON_PRESETCTRL1_FC0_RST_MASK          (0x800U)
22131 #define SYSCON_PRESETCTRL1_FC0_RST_SHIFT         (11U)
22132 /*! FC0_RST - FC0 reset control.
22133  *  0b1..Bloc is reset.
22134  *  0b0..Bloc is not reset.
22135  */
22136 #define SYSCON_PRESETCTRL1_FC0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK)
22137 
22138 #define SYSCON_PRESETCTRL1_FC1_RST_MASK          (0x1000U)
22139 #define SYSCON_PRESETCTRL1_FC1_RST_SHIFT         (12U)
22140 /*! FC1_RST - FC1 reset control.
22141  *  0b1..Bloc is reset.
22142  *  0b0..Bloc is not reset.
22143  */
22144 #define SYSCON_PRESETCTRL1_FC1_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK)
22145 
22146 #define SYSCON_PRESETCTRL1_FC2_RST_MASK          (0x2000U)
22147 #define SYSCON_PRESETCTRL1_FC2_RST_SHIFT         (13U)
22148 /*! FC2_RST - FC2 reset control.
22149  *  0b1..Bloc is reset.
22150  *  0b0..Bloc is not reset.
22151  */
22152 #define SYSCON_PRESETCTRL1_FC2_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK)
22153 
22154 #define SYSCON_PRESETCTRL1_FC3_RST_MASK          (0x4000U)
22155 #define SYSCON_PRESETCTRL1_FC3_RST_SHIFT         (14U)
22156 /*! FC3_RST - FC3 reset control.
22157  *  0b1..Bloc is reset.
22158  *  0b0..Bloc is not reset.
22159  */
22160 #define SYSCON_PRESETCTRL1_FC3_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK)
22161 
22162 #define SYSCON_PRESETCTRL1_FC4_RST_MASK          (0x8000U)
22163 #define SYSCON_PRESETCTRL1_FC4_RST_SHIFT         (15U)
22164 /*! FC4_RST - FC4 reset control.
22165  *  0b1..Bloc is reset.
22166  *  0b0..Bloc is not reset.
22167  */
22168 #define SYSCON_PRESETCTRL1_FC4_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK)
22169 
22170 #define SYSCON_PRESETCTRL1_FC5_RST_MASK          (0x10000U)
22171 #define SYSCON_PRESETCTRL1_FC5_RST_SHIFT         (16U)
22172 /*! FC5_RST - FC5 reset control.
22173  *  0b1..Bloc is reset.
22174  *  0b0..Bloc is not reset.
22175  */
22176 #define SYSCON_PRESETCTRL1_FC5_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK)
22177 
22178 #define SYSCON_PRESETCTRL1_FC6_RST_MASK          (0x20000U)
22179 #define SYSCON_PRESETCTRL1_FC6_RST_SHIFT         (17U)
22180 /*! FC6_RST - FC6 reset control.
22181  *  0b1..Bloc is reset.
22182  *  0b0..Bloc is not reset.
22183  */
22184 #define SYSCON_PRESETCTRL1_FC6_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK)
22185 
22186 #define SYSCON_PRESETCTRL1_FC7_RST_MASK          (0x40000U)
22187 #define SYSCON_PRESETCTRL1_FC7_RST_SHIFT         (18U)
22188 /*! FC7_RST - FC7 reset control.
22189  *  0b1..Bloc is reset.
22190  *  0b0..Bloc is not reset.
22191  */
22192 #define SYSCON_PRESETCTRL1_FC7_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK)
22193 
22194 #define SYSCON_PRESETCTRL1_TIMER2_RST_MASK       (0x400000U)
22195 #define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT      (22U)
22196 /*! TIMER2_RST - Timer 2 reset control.
22197  *  0b1..Bloc is reset.
22198  *  0b0..Bloc is not reset.
22199  */
22200 #define SYSCON_PRESETCTRL1_TIMER2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK)
22201 
22202 #define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK     (0x2000000U)
22203 #define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT    (25U)
22204 /*! USB0_DEV_RST - USB0 DEV reset control.
22205  *  0b1..Bloc is reset.
22206  *  0b0..Bloc is not reset.
22207  */
22208 #define SYSCON_PRESETCTRL1_USB0_DEV_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK)
22209 
22210 #define SYSCON_PRESETCTRL1_TIMER0_RST_MASK       (0x4000000U)
22211 #define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT      (26U)
22212 /*! TIMER0_RST - Timer 0 reset control.
22213  *  0b1..Bloc is reset.
22214  *  0b0..Bloc is not reset.
22215  */
22216 #define SYSCON_PRESETCTRL1_TIMER0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK)
22217 
22218 #define SYSCON_PRESETCTRL1_TIMER1_RST_MASK       (0x8000000U)
22219 #define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT      (27U)
22220 /*! TIMER1_RST - Timer 1 reset control.
22221  *  0b1..Bloc is reset.
22222  *  0b0..Bloc is not reset.
22223  */
22224 #define SYSCON_PRESETCTRL1_TIMER1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK)
22225 /*! @} */
22226 
22227 /*! @name PRESETCTRL2 - Peripheral reset control 2 */
22228 /*! @{ */
22229 
22230 #define SYSCON_PRESETCTRL2_DMA1_RST_MASK         (0x2U)
22231 #define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT        (1U)
22232 /*! DMA1_RST - DMA1 reset control.
22233  *  0b1..Bloc is reset.
22234  *  0b0..Bloc is not reset.
22235  */
22236 #define SYSCON_PRESETCTRL2_DMA1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK)
22237 
22238 #define SYSCON_PRESETCTRL2_COMP_RST_MASK         (0x4U)
22239 #define SYSCON_PRESETCTRL2_COMP_RST_SHIFT        (2U)
22240 /*! COMP_RST - Comparator reset control.
22241  *  0b1..Bloc is reset.
22242  *  0b0..Bloc is not reset.
22243  */
22244 #define SYSCON_PRESETCTRL2_COMP_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK)
22245 
22246 #define SYSCON_PRESETCTRL2_SDIO_RST_MASK         (0x8U)
22247 #define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT        (3U)
22248 /*! SDIO_RST - SDIO reset control.
22249  *  0b1..Bloc is reset.
22250  *  0b0..Bloc is not reset.
22251  */
22252 #define SYSCON_PRESETCTRL2_SDIO_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK)
22253 
22254 #define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK    (0x10U)
22255 #define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT   (4U)
22256 /*! USB1_HOST_RST - USB1 Host reset control.
22257  *  0b1..Bloc is reset.
22258  *  0b0..Bloc is not reset.
22259  */
22260 #define SYSCON_PRESETCTRL2_USB1_HOST_RST(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK)
22261 
22262 #define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK     (0x20U)
22263 #define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT    (5U)
22264 /*! USB1_DEV_RST - USB1 dev reset control.
22265  *  0b1..Bloc is reset.
22266  *  0b0..Bloc is not reset.
22267  */
22268 #define SYSCON_PRESETCTRL2_USB1_DEV_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK)
22269 
22270 #define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK     (0x40U)
22271 #define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT    (6U)
22272 /*! USB1_RAM_RST - USB1 RAM reset control.
22273  *  0b1..Bloc is reset.
22274  *  0b0..Bloc is not reset.
22275  */
22276 #define SYSCON_PRESETCTRL2_USB1_RAM_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK)
22277 
22278 #define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK     (0x80U)
22279 #define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT    (7U)
22280 /*! USB1_PHY_RST - USB1 PHY reset control.
22281  *  0b1..Bloc is reset.
22282  *  0b0..Bloc is not reset.
22283  */
22284 #define SYSCON_PRESETCTRL2_USB1_PHY_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK)
22285 
22286 #define SYSCON_PRESETCTRL2_FREQME_RST_MASK       (0x100U)
22287 #define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT      (8U)
22288 /*! FREQME_RST - Frequency meter reset control.
22289  *  0b1..Bloc is reset.
22290  *  0b0..Bloc is not reset.
22291  */
22292 #define SYSCON_PRESETCTRL2_FREQME_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK)
22293 
22294 #define SYSCON_PRESETCTRL2_RNG_RST_MASK          (0x2000U)
22295 #define SYSCON_PRESETCTRL2_RNG_RST_SHIFT         (13U)
22296 /*! RNG_RST - RNG reset control.
22297  *  0b1..Bloc is reset.
22298  *  0b0..Bloc is not reset.
22299  */
22300 #define SYSCON_PRESETCTRL2_RNG_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK)
22301 
22302 #define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK       (0x8000U)
22303 #define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT      (15U)
22304 /*! SYSCTL_RST - SYSCTL Block reset.
22305  *  0b1..Bloc is reset.
22306  *  0b0..Bloc is not reset.
22307  */
22308 #define SYSCON_PRESETCTRL2_SYSCTL_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK)
22309 
22310 #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK   (0x10000U)
22311 #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT  (16U)
22312 /*! USB0_HOSTM_RST - USB0 Host Master reset control.
22313  *  0b1..Bloc is reset.
22314  *  0b0..Bloc is not reset.
22315  */
22316 #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK)
22317 
22318 #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK   (0x20000U)
22319 #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT  (17U)
22320 /*! USB0_HOSTS_RST - USB0 Host Slave reset control.
22321  *  0b1..Bloc is reset.
22322  *  0b0..Bloc is not reset.
22323  */
22324 #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK)
22325 
22326 #define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK     (0x40000U)
22327 #define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT    (18U)
22328 /*! HASH_AES_RST - HASH_AES reset control.
22329  *  0b1..Bloc is reset.
22330  *  0b0..Bloc is not reset.
22331  */
22332 #define SYSCON_PRESETCTRL2_HASH_AES_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK)
22333 
22334 #define SYSCON_PRESETCTRL2_PQ_RST_MASK           (0x80000U)
22335 #define SYSCON_PRESETCTRL2_PQ_RST_SHIFT          (19U)
22336 /*! PQ_RST - Power Quad reset control.
22337  *  0b1..Bloc is reset.
22338  *  0b0..Bloc is not reset.
22339  */
22340 #define SYSCON_PRESETCTRL2_PQ_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK)
22341 
22342 #define SYSCON_PRESETCTRL2_PLULUT_RST_MASK       (0x100000U)
22343 #define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT      (20U)
22344 /*! PLULUT_RST - PLU LUT reset control.
22345  *  0b1..Bloc is reset.
22346  *  0b0..Bloc is not reset.
22347  */
22348 #define SYSCON_PRESETCTRL2_PLULUT_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK)
22349 
22350 #define SYSCON_PRESETCTRL2_TIMER3_RST_MASK       (0x200000U)
22351 #define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT      (21U)
22352 /*! TIMER3_RST - Timer 3 reset control.
22353  *  0b1..Bloc is reset.
22354  *  0b0..Bloc is not reset.
22355  */
22356 #define SYSCON_PRESETCTRL2_TIMER3_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK)
22357 
22358 #define SYSCON_PRESETCTRL2_TIMER4_RST_MASK       (0x400000U)
22359 #define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT      (22U)
22360 /*! TIMER4_RST - Timer 4 reset control.
22361  *  0b1..Bloc is reset.
22362  *  0b0..Bloc is not reset.
22363  */
22364 #define SYSCON_PRESETCTRL2_TIMER4_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK)
22365 
22366 #define SYSCON_PRESETCTRL2_PUF_RST_MASK          (0x800000U)
22367 #define SYSCON_PRESETCTRL2_PUF_RST_SHIFT         (23U)
22368 /*! PUF_RST - PUF reset control reset control.
22369  *  0b1..Bloc is reset.
22370  *  0b0..Bloc is not reset.
22371  */
22372 #define SYSCON_PRESETCTRL2_PUF_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK)
22373 
22374 #define SYSCON_PRESETCTRL2_CASPER_RST_MASK       (0x1000000U)
22375 #define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT      (24U)
22376 /*! CASPER_RST - Casper reset control.
22377  *  0b1..Bloc is reset.
22378  *  0b0..Bloc is not reset.
22379  */
22380 #define SYSCON_PRESETCTRL2_CASPER_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK)
22381 
22382 #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK  (0x8000000U)
22383 #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U)
22384 /*! ANALOG_CTRL_RST - analog control reset control.
22385  *  0b1..Bloc is reset.
22386  *  0b0..Bloc is not reset.
22387  */
22388 #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK)
22389 
22390 #define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK      (0x10000000U)
22391 #define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT     (28U)
22392 /*! HS_LSPI_RST - HS LSPI reset control.
22393  *  0b1..Bloc is reset.
22394  *  0b0..Bloc is not reset.
22395  */
22396 #define SYSCON_PRESETCTRL2_HS_LSPI_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK)
22397 
22398 #define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK     (0x20000000U)
22399 #define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT    (29U)
22400 /*! GPIO_SEC_RST - GPIO secure reset control.
22401  *  0b1..Bloc is reset.
22402  *  0b0..Bloc is not reset.
22403  */
22404 #define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK)
22405 
22406 #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U)
22407 #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U)
22408 /*! GPIO_SEC_INT_RST - GPIO secure int reset control.
22409  *  0b1..Bloc is reset.
22410  *  0b0..Bloc is not reset.
22411  */
22412 #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK)
22413 /*! @} */
22414 
22415 /*! @name PRESETCTRLX - Peripheral reset control register */
22416 /*! @{ */
22417 
22418 #define SYSCON_PRESETCTRLX_DATA_MASK             (0xFFFFFFFFU)
22419 #define SYSCON_PRESETCTRLX_DATA_SHIFT            (0U)
22420 /*! DATA - Data array value
22421  */
22422 #define SYSCON_PRESETCTRLX_DATA(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK)
22423 /*! @} */
22424 
22425 /* The count of SYSCON_PRESETCTRLX */
22426 #define SYSCON_PRESETCTRLX_COUNT                 (3U)
22427 
22428 /*! @name PRESETCTRLSET - Peripheral reset control set register */
22429 /*! @{ */
22430 
22431 #define SYSCON_PRESETCTRLSET_DATA_MASK           (0xFFFFFFFFU)
22432 #define SYSCON_PRESETCTRLSET_DATA_SHIFT          (0U)
22433 /*! DATA - Data array value
22434  */
22435 #define SYSCON_PRESETCTRLSET_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK)
22436 /*! @} */
22437 
22438 /* The count of SYSCON_PRESETCTRLSET */
22439 #define SYSCON_PRESETCTRLSET_COUNT               (3U)
22440 
22441 /*! @name PRESETCTRLCLR - Peripheral reset control clear register */
22442 /*! @{ */
22443 
22444 #define SYSCON_PRESETCTRLCLR_DATA_MASK           (0xFFFFFFFFU)
22445 #define SYSCON_PRESETCTRLCLR_DATA_SHIFT          (0U)
22446 /*! DATA - Data array value
22447  */
22448 #define SYSCON_PRESETCTRLCLR_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK)
22449 /*! @} */
22450 
22451 /* The count of SYSCON_PRESETCTRLCLR */
22452 #define SYSCON_PRESETCTRLCLR_COUNT               (3U)
22453 
22454 /*! @name SWR_RESET - generate a software_reset */
22455 /*! @{ */
22456 
22457 #define SYSCON_SWR_RESET_SWR_RESET_MASK          (0xFFFFFFFFU)
22458 #define SYSCON_SWR_RESET_SWR_RESET_SHIFT         (0U)
22459 /*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset.
22460  *  0b01011010000000000000000000000001..Generate a software reset.
22461  *  0b00000000000000000000000000000000..Bloc is not reset.
22462  */
22463 #define SYSCON_SWR_RESET_SWR_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK)
22464 /*! @} */
22465 
22466 /*! @name AHBCLKCTRL0 - AHB Clock control 0 */
22467 /*! @{ */
22468 
22469 #define SYSCON_AHBCLKCTRL0_ROM_MASK              (0x2U)
22470 #define SYSCON_AHBCLKCTRL0_ROM_SHIFT             (1U)
22471 /*! ROM - Enables the clock for the ROM.
22472  *  0b1..Enable Clock.
22473  *  0b0..Disable Clock.
22474  */
22475 #define SYSCON_AHBCLKCTRL0_ROM(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK)
22476 
22477 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK       (0x8U)
22478 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT      (3U)
22479 /*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1.
22480  *  0b1..Enable Clock.
22481  *  0b0..Disable Clock.
22482  */
22483 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK)
22484 
22485 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK       (0x10U)
22486 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT      (4U)
22487 /*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2.
22488  *  0b1..Enable Clock.
22489  *  0b0..Disable Clock.
22490  */
22491 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK)
22492 
22493 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK       (0x20U)
22494 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT      (5U)
22495 /*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3.
22496  *  0b1..Enable Clock.
22497  *  0b0..Disable Clock.
22498  */
22499 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK)
22500 
22501 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK       (0x40U)
22502 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT      (6U)
22503 /*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4.
22504  *  0b1..Enable Clock.
22505  *  0b0..Disable Clock.
22506  */
22507 #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK)
22508 
22509 #define SYSCON_AHBCLKCTRL0_FLASH_MASK            (0x80U)
22510 #define SYSCON_AHBCLKCTRL0_FLASH_SHIFT           (7U)
22511 /*! FLASH - Enables the clock for the Flash controller.
22512  *  0b1..Enable Clock.
22513  *  0b0..Disable Clock.
22514  */
22515 #define SYSCON_AHBCLKCTRL0_FLASH(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK)
22516 
22517 #define SYSCON_AHBCLKCTRL0_FMC_MASK              (0x100U)
22518 #define SYSCON_AHBCLKCTRL0_FMC_SHIFT             (8U)
22519 /*! FMC - Enables the clock for the FMC controller.
22520  *  0b1..Enable Clock.
22521  *  0b0..Disable Clock.
22522  */
22523 #define SYSCON_AHBCLKCTRL0_FMC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK)
22524 
22525 #define SYSCON_AHBCLKCTRL0_MUX_MASK              (0x800U)
22526 #define SYSCON_AHBCLKCTRL0_MUX_SHIFT             (11U)
22527 /*! MUX - Enables the clock for the Input Mux.
22528  *  0b1..Enable Clock.
22529  *  0b0..Disable Clock.
22530  */
22531 #define SYSCON_AHBCLKCTRL0_MUX(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK)
22532 
22533 #define SYSCON_AHBCLKCTRL0_IOCON_MASK            (0x2000U)
22534 #define SYSCON_AHBCLKCTRL0_IOCON_SHIFT           (13U)
22535 /*! IOCON - Enables the clock for the I/O controller.
22536  *  0b1..Enable Clock.
22537  *  0b0..Disable Clock.
22538  */
22539 #define SYSCON_AHBCLKCTRL0_IOCON(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK)
22540 
22541 #define SYSCON_AHBCLKCTRL0_GPIO0_MASK            (0x4000U)
22542 #define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT           (14U)
22543 /*! GPIO0 - Enables the clock for the GPIO0.
22544  *  0b1..Enable Clock.
22545  *  0b0..Disable Clock.
22546  */
22547 #define SYSCON_AHBCLKCTRL0_GPIO0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK)
22548 
22549 #define SYSCON_AHBCLKCTRL0_GPIO1_MASK            (0x8000U)
22550 #define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT           (15U)
22551 /*! GPIO1 - Enables the clock for the GPIO1.
22552  *  0b1..Enable Clock.
22553  *  0b0..Disable Clock.
22554  */
22555 #define SYSCON_AHBCLKCTRL0_GPIO1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK)
22556 
22557 #define SYSCON_AHBCLKCTRL0_GPIO2_MASK            (0x10000U)
22558 #define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT           (16U)
22559 /*! GPIO2 - Enables the clock for the GPIO2.
22560  *  0b1..Enable Clock.
22561  *  0b0..Disable Clock.
22562  */
22563 #define SYSCON_AHBCLKCTRL0_GPIO2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK)
22564 
22565 #define SYSCON_AHBCLKCTRL0_GPIO3_MASK            (0x20000U)
22566 #define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT           (17U)
22567 /*! GPIO3 - Enables the clock for the GPIO3.
22568  *  0b1..Enable Clock.
22569  *  0b0..Disable Clock.
22570  */
22571 #define SYSCON_AHBCLKCTRL0_GPIO3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK)
22572 
22573 #define SYSCON_AHBCLKCTRL0_PINT_MASK             (0x40000U)
22574 #define SYSCON_AHBCLKCTRL0_PINT_SHIFT            (18U)
22575 /*! PINT - Enables the clock for the Pin interrupt (PINT).
22576  *  0b1..Enable Clock.
22577  *  0b0..Disable Clock.
22578  */
22579 #define SYSCON_AHBCLKCTRL0_PINT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK)
22580 
22581 #define SYSCON_AHBCLKCTRL0_GINT_MASK             (0x80000U)
22582 #define SYSCON_AHBCLKCTRL0_GINT_SHIFT            (19U)
22583 /*! GINT - Enables the clock for the Group interrupt (GINT).
22584  *  0b1..Enable Clock.
22585  *  0b0..Disable Clock.
22586  */
22587 #define SYSCON_AHBCLKCTRL0_GINT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK)
22588 
22589 #define SYSCON_AHBCLKCTRL0_DMA0_MASK             (0x100000U)
22590 #define SYSCON_AHBCLKCTRL0_DMA0_SHIFT            (20U)
22591 /*! DMA0 - Enables the clock for the DMA0.
22592  *  0b1..Enable Clock.
22593  *  0b0..Disable Clock.
22594  */
22595 #define SYSCON_AHBCLKCTRL0_DMA0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK)
22596 
22597 #define SYSCON_AHBCLKCTRL0_CRCGEN_MASK           (0x200000U)
22598 #define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT          (21U)
22599 /*! CRCGEN - Enables the clock for the CRCGEN.
22600  *  0b1..Enable Clock.
22601  *  0b0..Disable Clock.
22602  */
22603 #define SYSCON_AHBCLKCTRL0_CRCGEN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK)
22604 
22605 #define SYSCON_AHBCLKCTRL0_WWDT_MASK             (0x400000U)
22606 #define SYSCON_AHBCLKCTRL0_WWDT_SHIFT            (22U)
22607 /*! WWDT - Enables the clock for the Watchdog Timer.
22608  *  0b1..Enable Clock.
22609  *  0b0..Disable Clock.
22610  */
22611 #define SYSCON_AHBCLKCTRL0_WWDT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK)
22612 
22613 #define SYSCON_AHBCLKCTRL0_RTC_MASK              (0x800000U)
22614 #define SYSCON_AHBCLKCTRL0_RTC_SHIFT             (23U)
22615 /*! RTC - Enables the clock for the Real Time Clock (RTC).
22616  *  0b1..Enable Clock.
22617  *  0b0..Disable Clock.
22618  */
22619 #define SYSCON_AHBCLKCTRL0_RTC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK)
22620 
22621 #define SYSCON_AHBCLKCTRL0_MAILBOX_MASK          (0x4000000U)
22622 #define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT         (26U)
22623 /*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox.
22624  *  0b1..Enable Clock.
22625  *  0b0..Disable Clock.
22626  */
22627 #define SYSCON_AHBCLKCTRL0_MAILBOX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK)
22628 
22629 #define SYSCON_AHBCLKCTRL0_ADC_MASK              (0x8000000U)
22630 #define SYSCON_AHBCLKCTRL0_ADC_SHIFT             (27U)
22631 /*! ADC - Enables the clock for the ADC.
22632  *  0b1..Enable Clock.
22633  *  0b0..Disable Clock.
22634  */
22635 #define SYSCON_AHBCLKCTRL0_ADC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK)
22636 /*! @} */
22637 
22638 /*! @name AHBCLKCTRL1 - AHB Clock control 1 */
22639 /*! @{ */
22640 
22641 #define SYSCON_AHBCLKCTRL1_MRT_MASK              (0x1U)
22642 #define SYSCON_AHBCLKCTRL1_MRT_SHIFT             (0U)
22643 /*! MRT - Enables the clock for the MRT.
22644  *  0b1..Enable Clock.
22645  *  0b0..Disable Clock.
22646  */
22647 #define SYSCON_AHBCLKCTRL1_MRT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK)
22648 
22649 #define SYSCON_AHBCLKCTRL1_OSTIMER_MASK          (0x2U)
22650 #define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT         (1U)
22651 /*! OSTIMER - Enables the clock for the OS Event Timer.
22652  *  0b1..Enable Clock.
22653  *  0b0..Disable Clock.
22654  */
22655 #define SYSCON_AHBCLKCTRL1_OSTIMER(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK)
22656 
22657 #define SYSCON_AHBCLKCTRL1_SCT_MASK              (0x4U)
22658 #define SYSCON_AHBCLKCTRL1_SCT_SHIFT             (2U)
22659 /*! SCT - Enables the clock for the SCT.
22660  *  0b1..Enable Clock.
22661  *  0b0..Disable Clock.
22662  */
22663 #define SYSCON_AHBCLKCTRL1_SCT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK)
22664 
22665 #define SYSCON_AHBCLKCTRL1_UTICK_MASK            (0x400U)
22666 #define SYSCON_AHBCLKCTRL1_UTICK_SHIFT           (10U)
22667 /*! UTICK - Enables the clock for the UTICK.
22668  *  0b1..Enable Clock.
22669  *  0b0..Disable Clock.
22670  */
22671 #define SYSCON_AHBCLKCTRL1_UTICK(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK)
22672 
22673 #define SYSCON_AHBCLKCTRL1_FC0_MASK              (0x800U)
22674 #define SYSCON_AHBCLKCTRL1_FC0_SHIFT             (11U)
22675 /*! FC0 - Enables the clock for the FC0.
22676  *  0b1..Enable Clock.
22677  *  0b0..Disable Clock.
22678  */
22679 #define SYSCON_AHBCLKCTRL1_FC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK)
22680 
22681 #define SYSCON_AHBCLKCTRL1_FC1_MASK              (0x1000U)
22682 #define SYSCON_AHBCLKCTRL1_FC1_SHIFT             (12U)
22683 /*! FC1 - Enables the clock for the FC1.
22684  *  0b1..Enable Clock.
22685  *  0b0..Disable Clock.
22686  */
22687 #define SYSCON_AHBCLKCTRL1_FC1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK)
22688 
22689 #define SYSCON_AHBCLKCTRL1_FC2_MASK              (0x2000U)
22690 #define SYSCON_AHBCLKCTRL1_FC2_SHIFT             (13U)
22691 /*! FC2 - Enables the clock for the FC2.
22692  *  0b1..Enable Clock.
22693  *  0b0..Disable Clock.
22694  */
22695 #define SYSCON_AHBCLKCTRL1_FC2(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK)
22696 
22697 #define SYSCON_AHBCLKCTRL1_FC3_MASK              (0x4000U)
22698 #define SYSCON_AHBCLKCTRL1_FC3_SHIFT             (14U)
22699 /*! FC3 - Enables the clock for the FC3.
22700  *  0b1..Enable Clock.
22701  *  0b0..Disable Clock.
22702  */
22703 #define SYSCON_AHBCLKCTRL1_FC3(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK)
22704 
22705 #define SYSCON_AHBCLKCTRL1_FC4_MASK              (0x8000U)
22706 #define SYSCON_AHBCLKCTRL1_FC4_SHIFT             (15U)
22707 /*! FC4 - Enables the clock for the FC4.
22708  *  0b1..Enable Clock.
22709  *  0b0..Disable Clock.
22710  */
22711 #define SYSCON_AHBCLKCTRL1_FC4(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK)
22712 
22713 #define SYSCON_AHBCLKCTRL1_FC5_MASK              (0x10000U)
22714 #define SYSCON_AHBCLKCTRL1_FC5_SHIFT             (16U)
22715 /*! FC5 - Enables the clock for the FC5.
22716  *  0b1..Enable Clock.
22717  *  0b0..Disable Clock.
22718  */
22719 #define SYSCON_AHBCLKCTRL1_FC5(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK)
22720 
22721 #define SYSCON_AHBCLKCTRL1_FC6_MASK              (0x20000U)
22722 #define SYSCON_AHBCLKCTRL1_FC6_SHIFT             (17U)
22723 /*! FC6 - Enables the clock for the FC6.
22724  *  0b1..Enable Clock.
22725  *  0b0..Disable Clock.
22726  */
22727 #define SYSCON_AHBCLKCTRL1_FC6(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK)
22728 
22729 #define SYSCON_AHBCLKCTRL1_FC7_MASK              (0x40000U)
22730 #define SYSCON_AHBCLKCTRL1_FC7_SHIFT             (18U)
22731 /*! FC7 - Enables the clock for the FC7.
22732  *  0b1..Enable Clock.
22733  *  0b0..Disable Clock.
22734  */
22735 #define SYSCON_AHBCLKCTRL1_FC7(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK)
22736 
22737 #define SYSCON_AHBCLKCTRL1_TIMER2_MASK           (0x400000U)
22738 #define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT          (22U)
22739 /*! TIMER2 - Enables the clock for the Timer 2.
22740  *  0b1..Enable Clock.
22741  *  0b0..Disable Clock.
22742  */
22743 #define SYSCON_AHBCLKCTRL1_TIMER2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK)
22744 
22745 #define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK         (0x2000000U)
22746 #define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT        (25U)
22747 /*! USB0_DEV - Enables the clock for the USB0 DEV.
22748  *  0b1..Enable Clock.
22749  *  0b0..Disable Clock.
22750  */
22751 #define SYSCON_AHBCLKCTRL1_USB0_DEV(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK)
22752 
22753 #define SYSCON_AHBCLKCTRL1_TIMER0_MASK           (0x4000000U)
22754 #define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT          (26U)
22755 /*! TIMER0 - Enables the clock for the Timer 0.
22756  *  0b1..Enable Clock.
22757  *  0b0..Disable Clock.
22758  */
22759 #define SYSCON_AHBCLKCTRL1_TIMER0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK)
22760 
22761 #define SYSCON_AHBCLKCTRL1_TIMER1_MASK           (0x8000000U)
22762 #define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT          (27U)
22763 /*! TIMER1 - Enables the clock for the Timer 1.
22764  *  0b1..Enable Clock.
22765  *  0b0..Disable Clock.
22766  */
22767 #define SYSCON_AHBCLKCTRL1_TIMER1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK)
22768 /*! @} */
22769 
22770 /*! @name AHBCLKCTRL2 - AHB Clock control 2 */
22771 /*! @{ */
22772 
22773 #define SYSCON_AHBCLKCTRL2_DMA1_MASK             (0x2U)
22774 #define SYSCON_AHBCLKCTRL2_DMA1_SHIFT            (1U)
22775 /*! DMA1 - Enables the clock for the DMA1.
22776  *  0b1..Enable Clock.
22777  *  0b0..Disable Clock.
22778  */
22779 #define SYSCON_AHBCLKCTRL2_DMA1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK)
22780 
22781 #define SYSCON_AHBCLKCTRL2_COMP_MASK             (0x4U)
22782 #define SYSCON_AHBCLKCTRL2_COMP_SHIFT            (2U)
22783 /*! COMP - Enables the clock for the Comparator.
22784  *  0b1..Enable Clock.
22785  *  0b0..Disable Clock.
22786  */
22787 #define SYSCON_AHBCLKCTRL2_COMP(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK)
22788 
22789 #define SYSCON_AHBCLKCTRL2_SDIO_MASK             (0x8U)
22790 #define SYSCON_AHBCLKCTRL2_SDIO_SHIFT            (3U)
22791 /*! SDIO - Enables the clock for the SDIO.
22792  *  0b1..Enable Clock.
22793  *  0b0..Disable Clock.
22794  */
22795 #define SYSCON_AHBCLKCTRL2_SDIO(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK)
22796 
22797 #define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK        (0x10U)
22798 #define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT       (4U)
22799 /*! USB1_HOST - Enables the clock for the USB1 Host.
22800  *  0b1..Enable Clock.
22801  *  0b0..Disable Clock.
22802  */
22803 #define SYSCON_AHBCLKCTRL2_USB1_HOST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK)
22804 
22805 #define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK         (0x20U)
22806 #define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT        (5U)
22807 /*! USB1_DEV - Enables the clock for the USB1 dev.
22808  *  0b1..Enable Clock.
22809  *  0b0..Disable Clock.
22810  */
22811 #define SYSCON_AHBCLKCTRL2_USB1_DEV(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK)
22812 
22813 #define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK         (0x40U)
22814 #define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT        (6U)
22815 /*! USB1_RAM - Enables the clock for the USB1 RAM.
22816  *  0b1..Enable Clock.
22817  *  0b0..Disable Clock.
22818  */
22819 #define SYSCON_AHBCLKCTRL2_USB1_RAM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK)
22820 
22821 #define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK         (0x80U)
22822 #define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT        (7U)
22823 /*! USB1_PHY - Enables the clock for the USB1 PHY.
22824  *  0b1..Enable Clock.
22825  *  0b0..Disable Clock.
22826  */
22827 #define SYSCON_AHBCLKCTRL2_USB1_PHY(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK)
22828 
22829 #define SYSCON_AHBCLKCTRL2_FREQME_MASK           (0x100U)
22830 #define SYSCON_AHBCLKCTRL2_FREQME_SHIFT          (8U)
22831 /*! FREQME - Enables the clock for the Frequency meter.
22832  *  0b1..Enable Clock.
22833  *  0b0..Disable Clock.
22834  */
22835 #define SYSCON_AHBCLKCTRL2_FREQME(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK)
22836 
22837 #define SYSCON_AHBCLKCTRL2_RNG_MASK              (0x2000U)
22838 #define SYSCON_AHBCLKCTRL2_RNG_SHIFT             (13U)
22839 /*! RNG - Enables the clock for the RNG.
22840  *  0b1..Enable Clock.
22841  *  0b0..Disable Clock.
22842  */
22843 #define SYSCON_AHBCLKCTRL2_RNG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK)
22844 
22845 #define SYSCON_AHBCLKCTRL2_SYSCTL_MASK           (0x8000U)
22846 #define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT          (15U)
22847 /*! SYSCTL - SYSCTL block clock.
22848  *  0b1..Enable Clock.
22849  *  0b0..Disable Clock.
22850  */
22851 #define SYSCON_AHBCLKCTRL2_SYSCTL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK)
22852 
22853 #define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK       (0x10000U)
22854 #define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT      (16U)
22855 /*! USB0_HOSTM - Enables the clock for the USB0 Host Master.
22856  *  0b1..Enable Clock.
22857  *  0b0..Disable Clock.
22858  */
22859 #define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK)
22860 
22861 #define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK       (0x20000U)
22862 #define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT      (17U)
22863 /*! USB0_HOSTS - Enables the clock for the USB0 Host Slave.
22864  *  0b1..Enable Clock.
22865  *  0b0..Disable Clock.
22866  */
22867 #define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK)
22868 
22869 #define SYSCON_AHBCLKCTRL2_HASH_AES_MASK         (0x40000U)
22870 #define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT        (18U)
22871 /*! HASH_AES - Enables the clock for the HASH_AES.
22872  *  0b1..Enable Clock.
22873  *  0b0..Disable Clock.
22874  */
22875 #define SYSCON_AHBCLKCTRL2_HASH_AES(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK)
22876 
22877 #define SYSCON_AHBCLKCTRL2_PQ_MASK               (0x80000U)
22878 #define SYSCON_AHBCLKCTRL2_PQ_SHIFT              (19U)
22879 /*! PQ - Enables the clock for the Power Quad.
22880  *  0b1..Enable Clock.
22881  *  0b0..Disable Clock.
22882  */
22883 #define SYSCON_AHBCLKCTRL2_PQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK)
22884 
22885 #define SYSCON_AHBCLKCTRL2_PLULUT_MASK           (0x100000U)
22886 #define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT          (20U)
22887 /*! PLULUT - Enables the clock for the PLU LUT.
22888  *  0b1..Enable Clock.
22889  *  0b0..Disable Clock.
22890  */
22891 #define SYSCON_AHBCLKCTRL2_PLULUT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK)
22892 
22893 #define SYSCON_AHBCLKCTRL2_TIMER3_MASK           (0x200000U)
22894 #define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT          (21U)
22895 /*! TIMER3 - Enables the clock for the Timer 3.
22896  *  0b1..Enable Clock.
22897  *  0b0..Disable Clock.
22898  */
22899 #define SYSCON_AHBCLKCTRL2_TIMER3(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK)
22900 
22901 #define SYSCON_AHBCLKCTRL2_TIMER4_MASK           (0x400000U)
22902 #define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT          (22U)
22903 /*! TIMER4 - Enables the clock for the Timer 4.
22904  *  0b1..Enable Clock.
22905  *  0b0..Disable Clock.
22906  */
22907 #define SYSCON_AHBCLKCTRL2_TIMER4(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK)
22908 
22909 #define SYSCON_AHBCLKCTRL2_PUF_MASK              (0x800000U)
22910 #define SYSCON_AHBCLKCTRL2_PUF_SHIFT             (23U)
22911 /*! PUF - Enables the clock for the PUF reset control.
22912  *  0b1..Enable Clock.
22913  *  0b0..Disable Clock.
22914  */
22915 #define SYSCON_AHBCLKCTRL2_PUF(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK)
22916 
22917 #define SYSCON_AHBCLKCTRL2_CASPER_MASK           (0x1000000U)
22918 #define SYSCON_AHBCLKCTRL2_CASPER_SHIFT          (24U)
22919 /*! CASPER - Enables the clock for the Casper.
22920  *  0b1..Enable Clock.
22921  *  0b0..Disable Clock.
22922  */
22923 #define SYSCON_AHBCLKCTRL2_CASPER(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK)
22924 
22925 #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK      (0x8000000U)
22926 #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT     (27U)
22927 /*! ANALOG_CTRL - Enables the clock for the analog control.
22928  *  0b1..Enable Clock.
22929  *  0b0..Disable Clock.
22930  */
22931 #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK)
22932 
22933 #define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK          (0x10000000U)
22934 #define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT         (28U)
22935 /*! HS_LSPI - Enables the clock for the HS LSPI.
22936  *  0b1..Enable Clock.
22937  *  0b0..Disable Clock.
22938  */
22939 #define SYSCON_AHBCLKCTRL2_HS_LSPI(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK)
22940 
22941 #define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK         (0x20000000U)
22942 #define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT        (29U)
22943 /*! GPIO_SEC - Enables the clock for the GPIO secure.
22944  *  0b1..Enable Clock.
22945  *  0b0..Disable Clock.
22946  */
22947 #define SYSCON_AHBCLKCTRL2_GPIO_SEC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK)
22948 
22949 #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK     (0x40000000U)
22950 #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT    (30U)
22951 /*! GPIO_SEC_INT - Enables the clock for the GPIO secure int.
22952  *  0b1..Enable Clock.
22953  *  0b0..Disable Clock.
22954  */
22955 #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK)
22956 /*! @} */
22957 
22958 /*! @name AHBCLKCTRLX - Peripheral reset control register */
22959 /*! @{ */
22960 
22961 #define SYSCON_AHBCLKCTRLX_DATA_MASK             (0xFFFFFFFFU)
22962 #define SYSCON_AHBCLKCTRLX_DATA_SHIFT            (0U)
22963 /*! DATA - Data array value
22964  */
22965 #define SYSCON_AHBCLKCTRLX_DATA(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK)
22966 /*! @} */
22967 
22968 /* The count of SYSCON_AHBCLKCTRLX */
22969 #define SYSCON_AHBCLKCTRLX_COUNT                 (3U)
22970 
22971 /*! @name AHBCLKCTRLSET - Peripheral reset control register */
22972 /*! @{ */
22973 
22974 #define SYSCON_AHBCLKCTRLSET_DATA_MASK           (0xFFFFFFFFU)
22975 #define SYSCON_AHBCLKCTRLSET_DATA_SHIFT          (0U)
22976 /*! DATA - Data array value
22977  */
22978 #define SYSCON_AHBCLKCTRLSET_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK)
22979 /*! @} */
22980 
22981 /* The count of SYSCON_AHBCLKCTRLSET */
22982 #define SYSCON_AHBCLKCTRLSET_COUNT               (3U)
22983 
22984 /*! @name AHBCLKCTRLCLR - Peripheral reset control register */
22985 /*! @{ */
22986 
22987 #define SYSCON_AHBCLKCTRLCLR_DATA_MASK           (0xFFFFFFFFU)
22988 #define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT          (0U)
22989 /*! DATA - Data array value
22990  */
22991 #define SYSCON_AHBCLKCTRLCLR_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK)
22992 /*! @} */
22993 
22994 /* The count of SYSCON_AHBCLKCTRLCLR */
22995 #define SYSCON_AHBCLKCTRLCLR_COUNT               (3U)
22996 
22997 /*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */
22998 /*! @{ */
22999 
23000 #define SYSCON_SYSTICKCLKSEL0_SEL_MASK           (0x7U)
23001 #define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT          (0U)
23002 /*! SEL - System Tick Timer for CPU0 source select.
23003  *  0b000..System Tick 0 divided clock.
23004  *  0b001..FRO 1MHz clock.
23005  *  0b010..Oscillator 32 kHz clock.
23006  *  0b011..No clock.
23007  *  0b100..No clock.
23008  *  0b101..No clock.
23009  *  0b110..No clock.
23010  *  0b111..No clock.
23011  */
23012 #define SYSCON_SYSTICKCLKSEL0_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK)
23013 /*! @} */
23014 
23015 /*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */
23016 /*! @{ */
23017 
23018 #define SYSCON_SYSTICKCLKSEL1_SEL_MASK           (0x7U)
23019 #define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT          (0U)
23020 /*! SEL - System Tick Timer for CPU1 source select.
23021  *  0b000..System Tick 1 divided clock.
23022  *  0b001..FRO 1MHz clock.
23023  *  0b010..Oscillator 32 kHz clock.
23024  *  0b011..No clock.
23025  *  0b100..No clock.
23026  *  0b101..No clock.
23027  *  0b110..No clock.
23028  *  0b111..No clock.
23029  */
23030 #define SYSCON_SYSTICKCLKSEL1_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK)
23031 /*! @} */
23032 
23033 /*! @name SYSTICKCLKSELX - Peripheral reset control register */
23034 /*! @{ */
23035 
23036 #define SYSCON_SYSTICKCLKSELX_DATA_MASK          (0xFFFFFFFFU)
23037 #define SYSCON_SYSTICKCLKSELX_DATA_SHIFT         (0U)
23038 /*! DATA - Data array value
23039  */
23040 #define SYSCON_SYSTICKCLKSELX_DATA(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK)
23041 /*! @} */
23042 
23043 /* The count of SYSCON_SYSTICKCLKSELX */
23044 #define SYSCON_SYSTICKCLKSELX_COUNT              (2U)
23045 
23046 /*! @name TRACECLKSEL - Trace clock source select */
23047 /*! @{ */
23048 
23049 #define SYSCON_TRACECLKSEL_SEL_MASK              (0x7U)
23050 #define SYSCON_TRACECLKSEL_SEL_SHIFT             (0U)
23051 /*! SEL - Trace clock source select.
23052  *  0b000..Trace divided clock.
23053  *  0b001..FRO 1MHz clock.
23054  *  0b010..Oscillator 32 kHz clock.
23055  *  0b011..No clock.
23056  *  0b100..No clock.
23057  *  0b101..No clock.
23058  *  0b110..No clock.
23059  *  0b111..No clock.
23060  */
23061 #define SYSCON_TRACECLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK)
23062 /*! @} */
23063 
23064 /*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */
23065 /*! @{ */
23066 
23067 #define SYSCON_CTIMERCLKSEL0_SEL_MASK            (0x7U)
23068 #define SYSCON_CTIMERCLKSEL0_SEL_SHIFT           (0U)
23069 /*! SEL - CTimer 0 clock source select.
23070  *  0b000..Main clock.
23071  *  0b001..PLL0 clock.
23072  *  0b010..No clock.
23073  *  0b011..FRO 96 MHz clock.
23074  *  0b100..FRO 1MHz clock.
23075  *  0b101..MCLK clock.
23076  *  0b110..Oscillator 32kHz clock.
23077  *  0b111..No clock.
23078  */
23079 #define SYSCON_CTIMERCLKSEL0_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK)
23080 /*! @} */
23081 
23082 /*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */
23083 /*! @{ */
23084 
23085 #define SYSCON_CTIMERCLKSEL1_SEL_MASK            (0x7U)
23086 #define SYSCON_CTIMERCLKSEL1_SEL_SHIFT           (0U)
23087 /*! SEL - CTimer 1 clock source select.
23088  *  0b000..Main clock.
23089  *  0b001..PLL0 clock.
23090  *  0b010..No clock.
23091  *  0b011..FRO 96 MHz clock.
23092  *  0b100..FRO 1MHz clock.
23093  *  0b101..MCLK clock.
23094  *  0b110..Oscillator 32kHz clock.
23095  *  0b111..No clock.
23096  */
23097 #define SYSCON_CTIMERCLKSEL1_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK)
23098 /*! @} */
23099 
23100 /*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */
23101 /*! @{ */
23102 
23103 #define SYSCON_CTIMERCLKSEL2_SEL_MASK            (0x7U)
23104 #define SYSCON_CTIMERCLKSEL2_SEL_SHIFT           (0U)
23105 /*! SEL - CTimer 2 clock source select.
23106  *  0b000..Main clock.
23107  *  0b001..PLL0 clock.
23108  *  0b010..No clock.
23109  *  0b011..FRO 96 MHz clock.
23110  *  0b100..FRO 1MHz clock.
23111  *  0b101..MCLK clock.
23112  *  0b110..Oscillator 32kHz clock.
23113  *  0b111..No clock.
23114  */
23115 #define SYSCON_CTIMERCLKSEL2_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK)
23116 /*! @} */
23117 
23118 /*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */
23119 /*! @{ */
23120 
23121 #define SYSCON_CTIMERCLKSEL3_SEL_MASK            (0x7U)
23122 #define SYSCON_CTIMERCLKSEL3_SEL_SHIFT           (0U)
23123 /*! SEL - CTimer 3 clock source select.
23124  *  0b000..Main clock.
23125  *  0b001..PLL0 clock.
23126  *  0b010..No clock.
23127  *  0b011..FRO 96 MHz clock.
23128  *  0b100..FRO 1MHz clock.
23129  *  0b101..MCLK clock.
23130  *  0b110..Oscillator 32kHz clock.
23131  *  0b111..No clock.
23132  */
23133 #define SYSCON_CTIMERCLKSEL3_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK)
23134 /*! @} */
23135 
23136 /*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */
23137 /*! @{ */
23138 
23139 #define SYSCON_CTIMERCLKSEL4_SEL_MASK            (0x7U)
23140 #define SYSCON_CTIMERCLKSEL4_SEL_SHIFT           (0U)
23141 /*! SEL - CTimer 4 clock source select.
23142  *  0b000..Main clock.
23143  *  0b001..PLL0 clock.
23144  *  0b010..No clock.
23145  *  0b011..FRO 96 MHz clock.
23146  *  0b100..FRO 1MHz clock.
23147  *  0b101..MCLK clock.
23148  *  0b110..Oscillator 32kHz clock.
23149  *  0b111..No clock.
23150  */
23151 #define SYSCON_CTIMERCLKSEL4_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK)
23152 /*! @} */
23153 
23154 /*! @name CTIMERCLKSELX - Peripheral reset control register */
23155 /*! @{ */
23156 
23157 #define SYSCON_CTIMERCLKSELX_DATA_MASK           (0xFFFFFFFFU)
23158 #define SYSCON_CTIMERCLKSELX_DATA_SHIFT          (0U)
23159 /*! DATA - Data array value
23160  */
23161 #define SYSCON_CTIMERCLKSELX_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK)
23162 /*! @} */
23163 
23164 /* The count of SYSCON_CTIMERCLKSELX */
23165 #define SYSCON_CTIMERCLKSELX_COUNT               (5U)
23166 
23167 /*! @name MAINCLKSELA - Main clock A source select */
23168 /*! @{ */
23169 
23170 #define SYSCON_MAINCLKSELA_SEL_MASK              (0x7U)
23171 #define SYSCON_MAINCLKSELA_SEL_SHIFT             (0U)
23172 /*! SEL - Main clock A source select.
23173  *  0b000..FRO 12 MHz clock.
23174  *  0b001..CLKIN clock.
23175  *  0b010..FRO 1MHz clock.
23176  *  0b011..FRO 96 MHz clock.
23177  *  0b100..Reserved.
23178  *  0b101..Reserved.
23179  *  0b110..Reserved.
23180  *  0b111..Reserved.
23181  */
23182 #define SYSCON_MAINCLKSELA_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
23183 /*! @} */
23184 
23185 /*! @name MAINCLKSELB - Main clock source select */
23186 /*! @{ */
23187 
23188 #define SYSCON_MAINCLKSELB_SEL_MASK              (0x7U)
23189 #define SYSCON_MAINCLKSELB_SEL_SHIFT             (0U)
23190 /*! SEL - Main clock source select.
23191  *  0b000..Main Clock A.
23192  *  0b001..PLL0 clock.
23193  *  0b010..PLL1 clock.
23194  *  0b011..Oscillator 32 kHz clock.
23195  *  0b100..Reserved.
23196  *  0b101..Reserved.
23197  *  0b110..Reserved.
23198  *  0b111..Reserved.
23199  */
23200 #define SYSCON_MAINCLKSELB_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
23201 /*! @} */
23202 
23203 /*! @name CLKOUTSEL - CLKOUT clock source select */
23204 /*! @{ */
23205 
23206 #define SYSCON_CLKOUTSEL_SEL_MASK                (0x7U)
23207 #define SYSCON_CLKOUTSEL_SEL_SHIFT               (0U)
23208 /*! SEL - CLKOUT clock source select.
23209  *  0b000..Main clock.
23210  *  0b001..PLL0 clock.
23211  *  0b010..CLKIN clock.
23212  *  0b011..FRO 96 MHz clock.
23213  *  0b100..FRO 1MHz clock.
23214  *  0b101..PLL1 clock.
23215  *  0b110..Oscillator 32kHz clock.
23216  *  0b111..No clock.
23217  */
23218 #define SYSCON_CLKOUTSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK)
23219 /*! @} */
23220 
23221 /*! @name PLL0CLKSEL - PLL0 clock source select */
23222 /*! @{ */
23223 
23224 #define SYSCON_PLL0CLKSEL_SEL_MASK               (0x7U)
23225 #define SYSCON_PLL0CLKSEL_SEL_SHIFT              (0U)
23226 /*! SEL - PLL0 clock source select.
23227  *  0b000..FRO 12 MHz clock.
23228  *  0b001..CLKIN clock.
23229  *  0b010..FRO 1MHz clock.
23230  *  0b011..Oscillator 32kHz clock.
23231  *  0b100..No clock.
23232  *  0b101..No clock.
23233  *  0b110..No clock.
23234  *  0b111..No clock.
23235  */
23236 #define SYSCON_PLL0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK)
23237 /*! @} */
23238 
23239 /*! @name PLL1CLKSEL - PLL1 clock source select */
23240 /*! @{ */
23241 
23242 #define SYSCON_PLL1CLKSEL_SEL_MASK               (0x7U)
23243 #define SYSCON_PLL1CLKSEL_SEL_SHIFT              (0U)
23244 /*! SEL - PLL1 clock source select.
23245  *  0b000..FRO 12 MHz clock.
23246  *  0b001..CLKIN clock.
23247  *  0b010..FRO 1MHz clock.
23248  *  0b011..Oscillator 32kHz clock.
23249  *  0b100..No clock.
23250  *  0b101..No clock.
23251  *  0b110..No clock.
23252  *  0b111..No clock.
23253  */
23254 #define SYSCON_PLL1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK)
23255 /*! @} */
23256 
23257 /*! @name ADCCLKSEL - ADC clock source select */
23258 /*! @{ */
23259 
23260 #define SYSCON_ADCCLKSEL_SEL_MASK                (0x7U)
23261 #define SYSCON_ADCCLKSEL_SEL_SHIFT               (0U)
23262 /*! SEL - ADC clock source select.
23263  *  0b000..Main clock.
23264  *  0b001..PLL0 clock.
23265  *  0b010..FRO 96 MHz clock.
23266  *  0b011..Reserved.
23267  *  0b100..No clock.
23268  *  0b101..No clock.
23269  *  0b110..No clock.
23270  *  0b111..No clock.
23271  */
23272 #define SYSCON_ADCCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
23273 /*! @} */
23274 
23275 /*! @name USB0CLKSEL - FS USB clock source select */
23276 /*! @{ */
23277 
23278 #define SYSCON_USB0CLKSEL_SEL_MASK               (0x7U)
23279 #define SYSCON_USB0CLKSEL_SEL_SHIFT              (0U)
23280 /*! SEL - FS USB clock source select.
23281  *  0b000..Main clock.
23282  *  0b001..PLL0 clock.
23283  *  0b010..No clock.
23284  *  0b011..FRO 96 MHz clock.
23285  *  0b100..No clock.
23286  *  0b101..PLL1 clock.
23287  *  0b110..No clock.
23288  *  0b111..No clock.
23289  */
23290 #define SYSCON_USB0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
23291 /*! @} */
23292 
23293 /*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */
23294 /*! @{ */
23295 
23296 #define SYSCON_FCCLKSEL0_SEL_MASK                (0x7U)
23297 #define SYSCON_FCCLKSEL0_SEL_SHIFT               (0U)
23298 /*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider.
23299  *  0b000..Main clock.
23300  *  0b001..system PLL divided clock.
23301  *  0b010..FRO 12 MHz clock.
23302  *  0b011..FRO 96 MHz clock.
23303  *  0b100..FRO 1MHz clock.
23304  *  0b101..MCLK clock.
23305  *  0b110..Oscillator 32 kHz clock.
23306  *  0b111..No clock.
23307  */
23308 #define SYSCON_FCCLKSEL0_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK)
23309 /*! @} */
23310 
23311 /*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */
23312 /*! @{ */
23313 
23314 #define SYSCON_FCCLKSEL1_SEL_MASK                (0x7U)
23315 #define SYSCON_FCCLKSEL1_SEL_SHIFT               (0U)
23316 /*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider.
23317  *  0b000..Main clock.
23318  *  0b001..system PLL divided clock.
23319  *  0b010..FRO 12 MHz clock.
23320  *  0b011..FRO 96 MHz clock.
23321  *  0b100..FRO 1MHz clock.
23322  *  0b101..MCLK clock.
23323  *  0b110..Oscillator 32 kHz clock.
23324  *  0b111..No clock.
23325  */
23326 #define SYSCON_FCCLKSEL1_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK)
23327 /*! @} */
23328 
23329 /*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */
23330 /*! @{ */
23331 
23332 #define SYSCON_FCCLKSEL2_SEL_MASK                (0x7U)
23333 #define SYSCON_FCCLKSEL2_SEL_SHIFT               (0U)
23334 /*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider.
23335  *  0b000..Main clock.
23336  *  0b001..system PLL divided clock.
23337  *  0b010..FRO 12 MHz clock.
23338  *  0b011..FRO 96 MHz clock.
23339  *  0b100..FRO 1MHz clock.
23340  *  0b101..MCLK clock.
23341  *  0b110..Oscillator 32 kHz clock.
23342  *  0b111..No clock.
23343  */
23344 #define SYSCON_FCCLKSEL2_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK)
23345 /*! @} */
23346 
23347 /*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */
23348 /*! @{ */
23349 
23350 #define SYSCON_FCCLKSEL3_SEL_MASK                (0x7U)
23351 #define SYSCON_FCCLKSEL3_SEL_SHIFT               (0U)
23352 /*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider.
23353  *  0b000..Main clock.
23354  *  0b001..system PLL divided clock.
23355  *  0b010..FRO 12 MHz clock.
23356  *  0b011..FRO 96 MHz clock.
23357  *  0b100..FRO 1MHz clock.
23358  *  0b101..MCLK clock.
23359  *  0b110..Oscillator 32 kHz clock.
23360  *  0b111..No clock.
23361  */
23362 #define SYSCON_FCCLKSEL3_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK)
23363 /*! @} */
23364 
23365 /*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */
23366 /*! @{ */
23367 
23368 #define SYSCON_FCCLKSEL4_SEL_MASK                (0x7U)
23369 #define SYSCON_FCCLKSEL4_SEL_SHIFT               (0U)
23370 /*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider.
23371  *  0b000..Main clock.
23372  *  0b001..system PLL divided clock.
23373  *  0b010..FRO 12 MHz clock.
23374  *  0b011..FRO 96 MHz clock.
23375  *  0b100..FRO 1MHz clock.
23376  *  0b101..MCLK clock.
23377  *  0b110..Oscillator 32 kHz clock.
23378  *  0b111..No clock.
23379  */
23380 #define SYSCON_FCCLKSEL4_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK)
23381 /*! @} */
23382 
23383 /*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */
23384 /*! @{ */
23385 
23386 #define SYSCON_FCCLKSEL5_SEL_MASK                (0x7U)
23387 #define SYSCON_FCCLKSEL5_SEL_SHIFT               (0U)
23388 /*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider.
23389  *  0b000..Main clock.
23390  *  0b001..system PLL divided clock.
23391  *  0b010..FRO 12 MHz clock.
23392  *  0b011..FRO 96 MHz clock.
23393  *  0b100..FRO 1MHz clock.
23394  *  0b101..MCLK clock.
23395  *  0b110..Oscillator 32 kHz clock.
23396  *  0b111..No clock.
23397  */
23398 #define SYSCON_FCCLKSEL5_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK)
23399 /*! @} */
23400 
23401 /*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */
23402 /*! @{ */
23403 
23404 #define SYSCON_FCCLKSEL6_SEL_MASK                (0x7U)
23405 #define SYSCON_FCCLKSEL6_SEL_SHIFT               (0U)
23406 /*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider.
23407  *  0b000..Main clock.
23408  *  0b001..system PLL divided clock.
23409  *  0b010..FRO 12 MHz clock.
23410  *  0b011..FRO 96 MHz clock.
23411  *  0b100..FRO 1MHz clock.
23412  *  0b101..MCLK clock.
23413  *  0b110..Oscillator 32 kHz clock.
23414  *  0b111..No clock.
23415  */
23416 #define SYSCON_FCCLKSEL6_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK)
23417 /*! @} */
23418 
23419 /*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */
23420 /*! @{ */
23421 
23422 #define SYSCON_FCCLKSEL7_SEL_MASK                (0x7U)
23423 #define SYSCON_FCCLKSEL7_SEL_SHIFT               (0U)
23424 /*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider.
23425  *  0b000..Main clock.
23426  *  0b001..system PLL divided clock.
23427  *  0b010..FRO 12 MHz clock.
23428  *  0b011..FRO 96 MHz clock.
23429  *  0b100..FRO 1MHz clock.
23430  *  0b101..MCLK clock.
23431  *  0b110..Oscillator 32 kHz clock.
23432  *  0b111..No clock.
23433  */
23434 #define SYSCON_FCCLKSEL7_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK)
23435 /*! @} */
23436 
23437 /*! @name FCCLKSELX - Peripheral reset control register */
23438 /*! @{ */
23439 
23440 #define SYSCON_FCCLKSELX_DATA_MASK               (0xFFFFFFFFU)
23441 #define SYSCON_FCCLKSELX_DATA_SHIFT              (0U)
23442 /*! DATA - Data array value
23443  */
23444 #define SYSCON_FCCLKSELX_DATA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK)
23445 /*! @} */
23446 
23447 /* The count of SYSCON_FCCLKSELX */
23448 #define SYSCON_FCCLKSELX_COUNT                   (8U)
23449 
23450 /*! @name HSLSPICLKSEL - HS LSPI clock source select */
23451 /*! @{ */
23452 
23453 #define SYSCON_HSLSPICLKSEL_SEL_MASK             (0x7U)
23454 #define SYSCON_HSLSPICLKSEL_SEL_SHIFT            (0U)
23455 /*! SEL - HS LSPI clock source select.
23456  *  0b000..Main clock.
23457  *  0b001..system PLL divided clock.
23458  *  0b010..FRO 12 MHz clock.
23459  *  0b011..FRO 96 MHz clock.
23460  *  0b100..FRO 1MHz clock.
23461  *  0b101..No clock.
23462  *  0b110..Oscillator 32 kHz clock.
23463  *  0b111..No clock.
23464  */
23465 #define SYSCON_HSLSPICLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK)
23466 /*! @} */
23467 
23468 /*! @name MCLKCLKSEL - MCLK clock source select */
23469 /*! @{ */
23470 
23471 #define SYSCON_MCLKCLKSEL_SEL_MASK               (0x7U)
23472 #define SYSCON_MCLKCLKSEL_SEL_SHIFT              (0U)
23473 /*! SEL - MCLK clock source select.
23474  *  0b000..FRO 96 MHz clock.
23475  *  0b001..PLL0 clock.
23476  *  0b010..Reserved.
23477  *  0b011..Reserved.
23478  *  0b100..No clock.
23479  *  0b101..No clock.
23480  *  0b110..No clock.
23481  *  0b111..No clock.
23482  */
23483 #define SYSCON_MCLKCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
23484 /*! @} */
23485 
23486 /*! @name SCTCLKSEL - SCTimer/PWM clock source select */
23487 /*! @{ */
23488 
23489 #define SYSCON_SCTCLKSEL_SEL_MASK                (0x7U)
23490 #define SYSCON_SCTCLKSEL_SEL_SHIFT               (0U)
23491 /*! SEL - SCTimer/PWM clock source select.
23492  *  0b000..Main clock.
23493  *  0b001..PLL0 clock.
23494  *  0b010..CLKIN clock.
23495  *  0b011..FRO 96 MHz clock.
23496  *  0b100..No clock.
23497  *  0b101..MCLK clock.
23498  *  0b110..No clock.
23499  *  0b111..No clock.
23500  */
23501 #define SYSCON_SCTCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
23502 /*! @} */
23503 
23504 /*! @name SDIOCLKSEL - SDIO clock source select */
23505 /*! @{ */
23506 
23507 #define SYSCON_SDIOCLKSEL_SEL_MASK               (0x7U)
23508 #define SYSCON_SDIOCLKSEL_SEL_SHIFT              (0U)
23509 /*! SEL - SDIO clock source select.
23510  *  0b000..Main clock.
23511  *  0b001..PLL0 clock.
23512  *  0b010..No clock.
23513  *  0b011..FRO 96 MHz clock.
23514  *  0b100..No clock.
23515  *  0b101..PLL1 clock.
23516  *  0b110..No clock.
23517  *  0b111..No clock.
23518  */
23519 #define SYSCON_SDIOCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
23520 /*! @} */
23521 
23522 /*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */
23523 /*! @{ */
23524 
23525 #define SYSCON_SYSTICKCLKDIV0_DIV_MASK           (0xFFU)
23526 #define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT          (0U)
23527 /*! DIV - Clock divider value.
23528  */
23529 #define SYSCON_SYSTICKCLKDIV0_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK)
23530 
23531 #define SYSCON_SYSTICKCLKDIV0_RESET_MASK         (0x20000000U)
23532 #define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT        (29U)
23533 /*! RESET - Resets the divider counter.
23534  *  0b1..Divider is reset.
23535  *  0b0..Divider is not reset.
23536  */
23537 #define SYSCON_SYSTICKCLKDIV0_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK)
23538 
23539 #define SYSCON_SYSTICKCLKDIV0_HALT_MASK          (0x40000000U)
23540 #define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT         (30U)
23541 /*! HALT - Halts the divider counter.
23542  *  0b1..Divider clock is stoped.
23543  *  0b0..Divider clock is running.
23544  */
23545 #define SYSCON_SYSTICKCLKDIV0_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK)
23546 
23547 #define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK       (0x80000000U)
23548 #define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT      (31U)
23549 /*! REQFLAG - Divider status flag.
23550  *  0b1..Clock frequency is not stable.
23551  *  0b0..Divider clock is stable.
23552  */
23553 #define SYSCON_SYSTICKCLKDIV0_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK)
23554 /*! @} */
23555 
23556 /*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */
23557 /*! @{ */
23558 
23559 #define SYSCON_SYSTICKCLKDIV1_DIV_MASK           (0xFFU)
23560 #define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT          (0U)
23561 /*! DIV - Clock divider value.
23562  */
23563 #define SYSCON_SYSTICKCLKDIV1_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK)
23564 
23565 #define SYSCON_SYSTICKCLKDIV1_RESET_MASK         (0x20000000U)
23566 #define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT        (29U)
23567 /*! RESET - Resets the divider counter.
23568  *  0b1..Divider is reset.
23569  *  0b0..Divider is not reset.
23570  */
23571 #define SYSCON_SYSTICKCLKDIV1_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK)
23572 
23573 #define SYSCON_SYSTICKCLKDIV1_HALT_MASK          (0x40000000U)
23574 #define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT         (30U)
23575 /*! HALT - Halts the divider counter.
23576  *  0b1..Divider clock is stoped.
23577  *  0b0..Divider clock is running.
23578  */
23579 #define SYSCON_SYSTICKCLKDIV1_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK)
23580 
23581 #define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK       (0x80000000U)
23582 #define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT      (31U)
23583 /*! REQFLAG - Divider status flag.
23584  *  0b1..Clock frequency is not stable.
23585  *  0b0..Divider clock is stable.
23586  */
23587 #define SYSCON_SYSTICKCLKDIV1_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK)
23588 /*! @} */
23589 
23590 /*! @name TRACECLKDIV - TRACE clock divider */
23591 /*! @{ */
23592 
23593 #define SYSCON_TRACECLKDIV_DIV_MASK              (0xFFU)
23594 #define SYSCON_TRACECLKDIV_DIV_SHIFT             (0U)
23595 /*! DIV - Clock divider value.
23596  */
23597 #define SYSCON_TRACECLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK)
23598 
23599 #define SYSCON_TRACECLKDIV_RESET_MASK            (0x20000000U)
23600 #define SYSCON_TRACECLKDIV_RESET_SHIFT           (29U)
23601 /*! RESET - Resets the divider counter.
23602  *  0b1..Divider is reset.
23603  *  0b0..Divider is not reset.
23604  */
23605 #define SYSCON_TRACECLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK)
23606 
23607 #define SYSCON_TRACECLKDIV_HALT_MASK             (0x40000000U)
23608 #define SYSCON_TRACECLKDIV_HALT_SHIFT            (30U)
23609 /*! HALT - Halts the divider counter.
23610  *  0b1..Divider clock is stoped.
23611  *  0b0..Divider clock is running.
23612  */
23613 #define SYSCON_TRACECLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK)
23614 
23615 #define SYSCON_TRACECLKDIV_REQFLAG_MASK          (0x80000000U)
23616 #define SYSCON_TRACECLKDIV_REQFLAG_SHIFT         (31U)
23617 /*! REQFLAG - Divider status flag.
23618  *  0b1..Clock frequency is not stable.
23619  *  0b0..Divider clock is stable.
23620  */
23621 #define SYSCON_TRACECLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK)
23622 /*! @} */
23623 
23624 /*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */
23625 /*! @{ */
23626 
23627 #define SYSCON_FLEXFRG0CTRL_DIV_MASK             (0xFFU)
23628 #define SYSCON_FLEXFRG0CTRL_DIV_SHIFT            (0U)
23629 /*! DIV - Denominator of the fractional rate divider.
23630  */
23631 #define SYSCON_FLEXFRG0CTRL_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK)
23632 
23633 #define SYSCON_FLEXFRG0CTRL_MULT_MASK            (0xFF00U)
23634 #define SYSCON_FLEXFRG0CTRL_MULT_SHIFT           (8U)
23635 /*! MULT - Numerator of the fractional rate divider.
23636  */
23637 #define SYSCON_FLEXFRG0CTRL_MULT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK)
23638 /*! @} */
23639 
23640 /*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */
23641 /*! @{ */
23642 
23643 #define SYSCON_FLEXFRG1CTRL_DIV_MASK             (0xFFU)
23644 #define SYSCON_FLEXFRG1CTRL_DIV_SHIFT            (0U)
23645 /*! DIV - Denominator of the fractional rate divider.
23646  */
23647 #define SYSCON_FLEXFRG1CTRL_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK)
23648 
23649 #define SYSCON_FLEXFRG1CTRL_MULT_MASK            (0xFF00U)
23650 #define SYSCON_FLEXFRG1CTRL_MULT_SHIFT           (8U)
23651 /*! MULT - Numerator of the fractional rate divider.
23652  */
23653 #define SYSCON_FLEXFRG1CTRL_MULT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK)
23654 /*! @} */
23655 
23656 /*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */
23657 /*! @{ */
23658 
23659 #define SYSCON_FLEXFRG2CTRL_DIV_MASK             (0xFFU)
23660 #define SYSCON_FLEXFRG2CTRL_DIV_SHIFT            (0U)
23661 /*! DIV - Denominator of the fractional rate divider.
23662  */
23663 #define SYSCON_FLEXFRG2CTRL_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK)
23664 
23665 #define SYSCON_FLEXFRG2CTRL_MULT_MASK            (0xFF00U)
23666 #define SYSCON_FLEXFRG2CTRL_MULT_SHIFT           (8U)
23667 /*! MULT - Numerator of the fractional rate divider.
23668  */
23669 #define SYSCON_FLEXFRG2CTRL_MULT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK)
23670 /*! @} */
23671 
23672 /*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */
23673 /*! @{ */
23674 
23675 #define SYSCON_FLEXFRG3CTRL_DIV_MASK             (0xFFU)
23676 #define SYSCON_FLEXFRG3CTRL_DIV_SHIFT            (0U)
23677 /*! DIV - Denominator of the fractional rate divider.
23678  */
23679 #define SYSCON_FLEXFRG3CTRL_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK)
23680 
23681 #define SYSCON_FLEXFRG3CTRL_MULT_MASK            (0xFF00U)
23682 #define SYSCON_FLEXFRG3CTRL_MULT_SHIFT           (8U)
23683 /*! MULT - Numerator of the fractional rate divider.
23684  */
23685 #define SYSCON_FLEXFRG3CTRL_MULT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK)
23686 /*! @} */
23687 
23688 /*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */
23689 /*! @{ */
23690 
23691 #define SYSCON_FLEXFRG4CTRL_DIV_MASK             (0xFFU)
23692 #define SYSCON_FLEXFRG4CTRL_DIV_SHIFT            (0U)
23693 /*! DIV - Denominator of the fractional rate divider.
23694  */
23695 #define SYSCON_FLEXFRG4CTRL_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK)
23696 
23697 #define SYSCON_FLEXFRG4CTRL_MULT_MASK            (0xFF00U)
23698 #define SYSCON_FLEXFRG4CTRL_MULT_SHIFT           (8U)
23699 /*! MULT - Numerator of the fractional rate divider.
23700  */
23701 #define SYSCON_FLEXFRG4CTRL_MULT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK)
23702 /*! @} */
23703 
23704 /*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */
23705 /*! @{ */
23706 
23707 #define SYSCON_FLEXFRG5CTRL_DIV_MASK             (0xFFU)
23708 #define SYSCON_FLEXFRG5CTRL_DIV_SHIFT            (0U)
23709 /*! DIV - Denominator of the fractional rate divider.
23710  */
23711 #define SYSCON_FLEXFRG5CTRL_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK)
23712 
23713 #define SYSCON_FLEXFRG5CTRL_MULT_MASK            (0xFF00U)
23714 #define SYSCON_FLEXFRG5CTRL_MULT_SHIFT           (8U)
23715 /*! MULT - Numerator of the fractional rate divider.
23716  */
23717 #define SYSCON_FLEXFRG5CTRL_MULT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK)
23718 /*! @} */
23719 
23720 /*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */
23721 /*! @{ */
23722 
23723 #define SYSCON_FLEXFRG6CTRL_DIV_MASK             (0xFFU)
23724 #define SYSCON_FLEXFRG6CTRL_DIV_SHIFT            (0U)
23725 /*! DIV - Denominator of the fractional rate divider.
23726  */
23727 #define SYSCON_FLEXFRG6CTRL_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK)
23728 
23729 #define SYSCON_FLEXFRG6CTRL_MULT_MASK            (0xFF00U)
23730 #define SYSCON_FLEXFRG6CTRL_MULT_SHIFT           (8U)
23731 /*! MULT - Numerator of the fractional rate divider.
23732  */
23733 #define SYSCON_FLEXFRG6CTRL_MULT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK)
23734 /*! @} */
23735 
23736 /*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */
23737 /*! @{ */
23738 
23739 #define SYSCON_FLEXFRG7CTRL_DIV_MASK             (0xFFU)
23740 #define SYSCON_FLEXFRG7CTRL_DIV_SHIFT            (0U)
23741 /*! DIV - Denominator of the fractional rate divider.
23742  */
23743 #define SYSCON_FLEXFRG7CTRL_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK)
23744 
23745 #define SYSCON_FLEXFRG7CTRL_MULT_MASK            (0xFF00U)
23746 #define SYSCON_FLEXFRG7CTRL_MULT_SHIFT           (8U)
23747 /*! MULT - Numerator of the fractional rate divider.
23748  */
23749 #define SYSCON_FLEXFRG7CTRL_MULT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK)
23750 /*! @} */
23751 
23752 /*! @name FLEXFRGXCTRL - Peripheral reset control register */
23753 /*! @{ */
23754 
23755 #define SYSCON_FLEXFRGXCTRL_DATA_MASK            (0xFFFFFFFFU)
23756 #define SYSCON_FLEXFRGXCTRL_DATA_SHIFT           (0U)
23757 /*! DATA - Data array value
23758  */
23759 #define SYSCON_FLEXFRGXCTRL_DATA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK)
23760 /*! @} */
23761 
23762 /* The count of SYSCON_FLEXFRGXCTRL */
23763 #define SYSCON_FLEXFRGXCTRL_COUNT                (8U)
23764 
23765 /*! @name AHBCLKDIV - System clock divider */
23766 /*! @{ */
23767 
23768 #define SYSCON_AHBCLKDIV_DIV_MASK                (0xFFU)
23769 #define SYSCON_AHBCLKDIV_DIV_SHIFT               (0U)
23770 /*! DIV - Clock divider value.
23771  */
23772 #define SYSCON_AHBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
23773 
23774 #define SYSCON_AHBCLKDIV_RESET_MASK              (0x20000000U)
23775 #define SYSCON_AHBCLKDIV_RESET_SHIFT             (29U)
23776 /*! RESET - Resets the divider counter.
23777  *  0b1..Divider is reset.
23778  *  0b0..Divider is not reset.
23779  */
23780 #define SYSCON_AHBCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK)
23781 
23782 #define SYSCON_AHBCLKDIV_HALT_MASK               (0x40000000U)
23783 #define SYSCON_AHBCLKDIV_HALT_SHIFT              (30U)
23784 /*! HALT - Halts the divider counter.
23785  *  0b1..Divider clock is stoped.
23786  *  0b0..Divider clock is running.
23787  */
23788 #define SYSCON_AHBCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK)
23789 
23790 #define SYSCON_AHBCLKDIV_REQFLAG_MASK            (0x80000000U)
23791 #define SYSCON_AHBCLKDIV_REQFLAG_SHIFT           (31U)
23792 /*! REQFLAG - Divider status flag.
23793  *  0b1..Clock frequency is not stable.
23794  *  0b0..Divider clock is stable.
23795  */
23796 #define SYSCON_AHBCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
23797 /*! @} */
23798 
23799 /*! @name CLKOUTDIV - CLKOUT clock divider */
23800 /*! @{ */
23801 
23802 #define SYSCON_CLKOUTDIV_DIV_MASK                (0xFFU)
23803 #define SYSCON_CLKOUTDIV_DIV_SHIFT               (0U)
23804 /*! DIV - Clock divider value.
23805  */
23806 #define SYSCON_CLKOUTDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
23807 
23808 #define SYSCON_CLKOUTDIV_RESET_MASK              (0x20000000U)
23809 #define SYSCON_CLKOUTDIV_RESET_SHIFT             (29U)
23810 /*! RESET - Resets the divider counter.
23811  *  0b1..Divider is reset.
23812  *  0b0..Divider is not reset.
23813  */
23814 #define SYSCON_CLKOUTDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
23815 
23816 #define SYSCON_CLKOUTDIV_HALT_MASK               (0x40000000U)
23817 #define SYSCON_CLKOUTDIV_HALT_SHIFT              (30U)
23818 /*! HALT - Halts the divider counter.
23819  *  0b1..Divider clock is stoped.
23820  *  0b0..Divider clock is running.
23821  */
23822 #define SYSCON_CLKOUTDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
23823 
23824 #define SYSCON_CLKOUTDIV_REQFLAG_MASK            (0x80000000U)
23825 #define SYSCON_CLKOUTDIV_REQFLAG_SHIFT           (31U)
23826 /*! REQFLAG - Divider status flag.
23827  *  0b1..Clock frequency is not stable.
23828  *  0b0..Divider clock is stable.
23829  */
23830 #define SYSCON_CLKOUTDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
23831 /*! @} */
23832 
23833 /*! @name FROHFDIV - FRO_HF (96MHz) clock divider */
23834 /*! @{ */
23835 
23836 #define SYSCON_FROHFDIV_DIV_MASK                 (0xFFU)
23837 #define SYSCON_FROHFDIV_DIV_SHIFT                (0U)
23838 /*! DIV - Clock divider value.
23839  */
23840 #define SYSCON_FROHFDIV_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)
23841 
23842 #define SYSCON_FROHFDIV_RESET_MASK               (0x20000000U)
23843 #define SYSCON_FROHFDIV_RESET_SHIFT              (29U)
23844 /*! RESET - Resets the divider counter.
23845  *  0b1..Divider is reset.
23846  *  0b0..Divider is not reset.
23847  */
23848 #define SYSCON_FROHFDIV_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)
23849 
23850 #define SYSCON_FROHFDIV_HALT_MASK                (0x40000000U)
23851 #define SYSCON_FROHFDIV_HALT_SHIFT               (30U)
23852 /*! HALT - Halts the divider counter.
23853  *  0b1..Divider clock is stoped.
23854  *  0b0..Divider clock is running.
23855  */
23856 #define SYSCON_FROHFDIV_HALT(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)
23857 
23858 #define SYSCON_FROHFDIV_REQFLAG_MASK             (0x80000000U)
23859 #define SYSCON_FROHFDIV_REQFLAG_SHIFT            (31U)
23860 /*! REQFLAG - Divider status flag.
23861  *  0b1..Clock frequency is not stable.
23862  *  0b0..Divider clock is stable.
23863  */
23864 #define SYSCON_FROHFDIV_REQFLAG(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK)
23865 /*! @} */
23866 
23867 /*! @name WDTCLKDIV - WDT clock divider */
23868 /*! @{ */
23869 
23870 #define SYSCON_WDTCLKDIV_DIV_MASK                (0x3FU)
23871 #define SYSCON_WDTCLKDIV_DIV_SHIFT               (0U)
23872 /*! DIV - Clock divider value.
23873  */
23874 #define SYSCON_WDTCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK)
23875 
23876 #define SYSCON_WDTCLKDIV_RESET_MASK              (0x20000000U)
23877 #define SYSCON_WDTCLKDIV_RESET_SHIFT             (29U)
23878 /*! RESET - Resets the divider counter.
23879  *  0b1..Divider is reset.
23880  *  0b0..Divider is not reset.
23881  */
23882 #define SYSCON_WDTCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK)
23883 
23884 #define SYSCON_WDTCLKDIV_HALT_MASK               (0x40000000U)
23885 #define SYSCON_WDTCLKDIV_HALT_SHIFT              (30U)
23886 /*! HALT - Halts the divider counter.
23887  *  0b1..Divider clock is stoped.
23888  *  0b0..Divider clock is running.
23889  */
23890 #define SYSCON_WDTCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK)
23891 
23892 #define SYSCON_WDTCLKDIV_REQFLAG_MASK            (0x80000000U)
23893 #define SYSCON_WDTCLKDIV_REQFLAG_SHIFT           (31U)
23894 /*! REQFLAG - Divider status flag.
23895  *  0b1..Clock frequency is not stable.
23896  *  0b0..Divider clock is stable.
23897  */
23898 #define SYSCON_WDTCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK)
23899 /*! @} */
23900 
23901 /*! @name ADCCLKDIV - ADC clock divider */
23902 /*! @{ */
23903 
23904 #define SYSCON_ADCCLKDIV_DIV_MASK                (0x7U)
23905 #define SYSCON_ADCCLKDIV_DIV_SHIFT               (0U)
23906 /*! DIV - Clock divider value.
23907  */
23908 #define SYSCON_ADCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
23909 
23910 #define SYSCON_ADCCLKDIV_RESET_MASK              (0x20000000U)
23911 #define SYSCON_ADCCLKDIV_RESET_SHIFT             (29U)
23912 /*! RESET - Resets the divider counter.
23913  *  0b1..Divider is reset.
23914  *  0b0..Divider is not reset.
23915  */
23916 #define SYSCON_ADCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
23917 
23918 #define SYSCON_ADCCLKDIV_HALT_MASK               (0x40000000U)
23919 #define SYSCON_ADCCLKDIV_HALT_SHIFT              (30U)
23920 /*! HALT - Halts the divider counter.
23921  *  0b1..Divider clock is stoped.
23922  *  0b0..Divider clock is running.
23923  */
23924 #define SYSCON_ADCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
23925 
23926 #define SYSCON_ADCCLKDIV_REQFLAG_MASK            (0x80000000U)
23927 #define SYSCON_ADCCLKDIV_REQFLAG_SHIFT           (31U)
23928 /*! REQFLAG - Divider status flag.
23929  *  0b1..Clock frequency is not stable.
23930  *  0b0..Divider clock is stable.
23931  */
23932 #define SYSCON_ADCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
23933 /*! @} */
23934 
23935 /*! @name USB0CLKDIV - USB0 Clock divider */
23936 /*! @{ */
23937 
23938 #define SYSCON_USB0CLKDIV_DIV_MASK               (0xFFU)
23939 #define SYSCON_USB0CLKDIV_DIV_SHIFT              (0U)
23940 /*! DIV - Clock divider value.
23941  */
23942 #define SYSCON_USB0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
23943 
23944 #define SYSCON_USB0CLKDIV_RESET_MASK             (0x20000000U)
23945 #define SYSCON_USB0CLKDIV_RESET_SHIFT            (29U)
23946 /*! RESET - Resets the divider counter.
23947  *  0b1..Divider is reset.
23948  *  0b0..Divider is not reset.
23949  */
23950 #define SYSCON_USB0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
23951 
23952 #define SYSCON_USB0CLKDIV_HALT_MASK              (0x40000000U)
23953 #define SYSCON_USB0CLKDIV_HALT_SHIFT             (30U)
23954 /*! HALT - Halts the divider counter.
23955  *  0b1..Divider clock is stoped.
23956  *  0b0..Divider clock is running.
23957  */
23958 #define SYSCON_USB0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
23959 
23960 #define SYSCON_USB0CLKDIV_REQFLAG_MASK           (0x80000000U)
23961 #define SYSCON_USB0CLKDIV_REQFLAG_SHIFT          (31U)
23962 /*! REQFLAG - Divider status flag.
23963  *  0b1..Clock frequency is not stable.
23964  *  0b0..Divider clock is stable.
23965  */
23966 #define SYSCON_USB0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
23967 /*! @} */
23968 
23969 /*! @name MCLKDIV - I2S MCLK clock divider */
23970 /*! @{ */
23971 
23972 #define SYSCON_MCLKDIV_DIV_MASK                  (0xFFU)
23973 #define SYSCON_MCLKDIV_DIV_SHIFT                 (0U)
23974 /*! DIV - Clock divider value.
23975  */
23976 #define SYSCON_MCLKDIV_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
23977 
23978 #define SYSCON_MCLKDIV_RESET_MASK                (0x20000000U)
23979 #define SYSCON_MCLKDIV_RESET_SHIFT               (29U)
23980 /*! RESET - Resets the divider counter.
23981  *  0b1..Divider is reset.
23982  *  0b0..Divider is not reset.
23983  */
23984 #define SYSCON_MCLKDIV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
23985 
23986 #define SYSCON_MCLKDIV_HALT_MASK                 (0x40000000U)
23987 #define SYSCON_MCLKDIV_HALT_SHIFT                (30U)
23988 /*! HALT - Halts the divider counter.
23989  *  0b1..Divider clock is stoped.
23990  *  0b0..Divider clock is running.
23991  */
23992 #define SYSCON_MCLKDIV_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
23993 
23994 #define SYSCON_MCLKDIV_REQFLAG_MASK              (0x80000000U)
23995 #define SYSCON_MCLKDIV_REQFLAG_SHIFT             (31U)
23996 /*! REQFLAG - Divider status flag.
23997  *  0b1..Clock frequency is not stable.
23998  *  0b0..Divider clock is stable.
23999  */
24000 #define SYSCON_MCLKDIV_REQFLAG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
24001 /*! @} */
24002 
24003 /*! @name SCTCLKDIV - SCT/PWM clock divider */
24004 /*! @{ */
24005 
24006 #define SYSCON_SCTCLKDIV_DIV_MASK                (0xFFU)
24007 #define SYSCON_SCTCLKDIV_DIV_SHIFT               (0U)
24008 /*! DIV - Clock divider value.
24009  */
24010 #define SYSCON_SCTCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
24011 
24012 #define SYSCON_SCTCLKDIV_RESET_MASK              (0x20000000U)
24013 #define SYSCON_SCTCLKDIV_RESET_SHIFT             (29U)
24014 /*! RESET - Resets the divider counter.
24015  *  0b1..Divider is reset.
24016  *  0b0..Divider is not reset.
24017  */
24018 #define SYSCON_SCTCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
24019 
24020 #define SYSCON_SCTCLKDIV_HALT_MASK               (0x40000000U)
24021 #define SYSCON_SCTCLKDIV_HALT_SHIFT              (30U)
24022 /*! HALT - Halts the divider counter.
24023  *  0b1..Divider clock is stoped.
24024  *  0b0..Divider clock is running.
24025  */
24026 #define SYSCON_SCTCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
24027 
24028 #define SYSCON_SCTCLKDIV_REQFLAG_MASK            (0x80000000U)
24029 #define SYSCON_SCTCLKDIV_REQFLAG_SHIFT           (31U)
24030 /*! REQFLAG - Divider status flag.
24031  *  0b1..Clock frequency is not stable.
24032  *  0b0..Divider clock is stable.
24033  */
24034 #define SYSCON_SCTCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
24035 /*! @} */
24036 
24037 /*! @name SDIOCLKDIV - SDIO clock divider */
24038 /*! @{ */
24039 
24040 #define SYSCON_SDIOCLKDIV_DIV_MASK               (0xFFU)
24041 #define SYSCON_SDIOCLKDIV_DIV_SHIFT              (0U)
24042 /*! DIV - Clock divider value.
24043  */
24044 #define SYSCON_SDIOCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
24045 
24046 #define SYSCON_SDIOCLKDIV_RESET_MASK             (0x20000000U)
24047 #define SYSCON_SDIOCLKDIV_RESET_SHIFT            (29U)
24048 /*! RESET - Resets the divider counter.
24049  *  0b1..Divider is reset.
24050  *  0b0..Divider is not reset.
24051  */
24052 #define SYSCON_SDIOCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
24053 
24054 #define SYSCON_SDIOCLKDIV_HALT_MASK              (0x40000000U)
24055 #define SYSCON_SDIOCLKDIV_HALT_SHIFT             (30U)
24056 /*! HALT - Halts the divider counter.
24057  *  0b1..Divider clock is stoped.
24058  *  0b0..Divider clock is running.
24059  */
24060 #define SYSCON_SDIOCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
24061 
24062 #define SYSCON_SDIOCLKDIV_REQFLAG_MASK           (0x80000000U)
24063 #define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT          (31U)
24064 /*! REQFLAG - Divider status flag.
24065  *  0b1..Clock frequency is not stable.
24066  *  0b0..Divider clock is stable.
24067  */
24068 #define SYSCON_SDIOCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
24069 /*! @} */
24070 
24071 /*! @name PLL0CLKDIV - PLL0 clock divider */
24072 /*! @{ */
24073 
24074 #define SYSCON_PLL0CLKDIV_DIV_MASK               (0xFFU)
24075 #define SYSCON_PLL0CLKDIV_DIV_SHIFT              (0U)
24076 /*! DIV - Clock divider value.
24077  */
24078 #define SYSCON_PLL0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK)
24079 
24080 #define SYSCON_PLL0CLKDIV_RESET_MASK             (0x20000000U)
24081 #define SYSCON_PLL0CLKDIV_RESET_SHIFT            (29U)
24082 /*! RESET - Resets the divider counter.
24083  *  0b1..Divider is reset.
24084  *  0b0..Divider is not reset.
24085  */
24086 #define SYSCON_PLL0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK)
24087 
24088 #define SYSCON_PLL0CLKDIV_HALT_MASK              (0x40000000U)
24089 #define SYSCON_PLL0CLKDIV_HALT_SHIFT             (30U)
24090 /*! HALT - Halts the divider counter.
24091  *  0b1..Divider clock is stoped.
24092  *  0b0..Divider clock is running.
24093  */
24094 #define SYSCON_PLL0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK)
24095 
24096 #define SYSCON_PLL0CLKDIV_REQFLAG_MASK           (0x80000000U)
24097 #define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT          (31U)
24098 /*! REQFLAG - Divider status flag.
24099  *  0b1..Clock frequency is not stable.
24100  *  0b0..Divider clock is stable.
24101  */
24102 #define SYSCON_PLL0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK)
24103 /*! @} */
24104 
24105 /*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */
24106 /*! @{ */
24107 
24108 #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU)
24109 #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U)
24110 /*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL).
24111  *  0b00000000000000000000000000000001..update all clock configuration.
24112  *  0b00000000000000000000000000000000..all hardware clock configruration are freeze.
24113  */
24114 #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK)
24115 /*! @} */
24116 
24117 /*! @name FMCCR - FMC configuration register */
24118 /*! @{ */
24119 
24120 #define SYSCON_FMCCR_FETCHCFG_MASK               (0x3U)
24121 #define SYSCON_FMCCR_FETCHCFG_SHIFT              (0U)
24122 /*! FETCHCFG - Instruction fetch configuration.
24123  *  0b00..Instruction fetches from flash are not buffered.
24124  *  0b01..One buffer is used for all instruction fetches.
24125  *  0b10..All buffers may be used for instruction fetches.
24126  */
24127 #define SYSCON_FMCCR_FETCHCFG(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK)
24128 
24129 #define SYSCON_FMCCR_DATACFG_MASK                (0xCU)
24130 #define SYSCON_FMCCR_DATACFG_SHIFT               (2U)
24131 /*! DATACFG - Data read configuration.
24132  *  0b00..Data accesses from flash are not buffered.
24133  *  0b01..One buffer is used for all data accesses.
24134  *  0b10..All buffers can be used for data accesses.
24135  */
24136 #define SYSCON_FMCCR_DATACFG(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK)
24137 
24138 #define SYSCON_FMCCR_ACCEL_MASK                  (0x10U)
24139 #define SYSCON_FMCCR_ACCEL_SHIFT                 (4U)
24140 /*! ACCEL - Acceleration enable.
24141  *  0b0..Flash acceleration is disabled.
24142  *  0b1..Flash acceleration is enabled.
24143  */
24144 #define SYSCON_FMCCR_ACCEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK)
24145 
24146 #define SYSCON_FMCCR_PREFEN_MASK                 (0x20U)
24147 #define SYSCON_FMCCR_PREFEN_SHIFT                (5U)
24148 /*! PREFEN - Prefetch enable.
24149  *  0b0..No instruction prefetch is performed.
24150  *  0b1..Instruction prefetch is enabled.
24151  */
24152 #define SYSCON_FMCCR_PREFEN(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK)
24153 
24154 #define SYSCON_FMCCR_PREFOVR_MASK                (0x40U)
24155 #define SYSCON_FMCCR_PREFOVR_SHIFT               (6U)
24156 /*! PREFOVR - Prefetch override.
24157  *  0b0..Any previously initiated prefetch will be completed.
24158  *  0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current
24159  *       execution address will be prefetched if not already buffered.
24160  */
24161 #define SYSCON_FMCCR_PREFOVR(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK)
24162 
24163 #define SYSCON_FMCCR_FLASHTIM_MASK               (0xF000U)
24164 #define SYSCON_FMCCR_FLASHTIM_SHIFT              (12U)
24165 /*! FLASHTIM - Flash memory access time.
24166  *  0b0000..1 system clock flash access time (for system clock rates up to 11 MHz).
24167  *  0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz).
24168  *  0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz).
24169  *  0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz).
24170  *  0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz).
24171  *  0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz).
24172  *  0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz).
24173  *  0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz).
24174  *  0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz).
24175  *  0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz).
24176  *  0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz).
24177  *  0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz).
24178  */
24179 #define SYSCON_FMCCR_FLASHTIM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK)
24180 /*! @} */
24181 
24182 /*! @name USB0NEEDCLKCTRL - USB0 need clock control */
24183 /*! @{ */
24184 
24185 #define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U)
24186 #define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U)
24187 /*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:.
24188  *  0b0..Under hardware control.
24189  *  0b1..Forced high.
24190  */
24191 #define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK)
24192 
24193 #define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U)
24194 #define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U)
24195 /*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.
24196  *  0b0..Falling edge of device USB0_NEEDCLK triggers wake-up.
24197  *  0b1..Rising edge of device USB0_NEEDCLK triggers wake-up.
24198  */
24199 #define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK)
24200 
24201 #define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U)
24202 #define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U)
24203 /*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:.
24204  *  0b0..Under hardware control.
24205  *  0b1..Forced high.
24206  */
24207 #define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK)
24208 
24209 #define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U)
24210 #define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U)
24211 /*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.
24212  *  0b0..Falling edge of device USB0_NEEDCLK triggers wake-up.
24213  *  0b1..Rising edge of device USB0_NEEDCLK triggers wake-up.
24214  */
24215 #define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK)
24216 /*! @} */
24217 
24218 /*! @name USB0NEEDCLKSTAT - USB0 need clock status */
24219 /*! @{ */
24220 
24221 #define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK  (0x1U)
24222 #define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U)
24223 /*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:.
24224  *  0b1..USB0 Device clock is high.
24225  *  0b0..USB0 Device clock is low.
24226  */
24227 #define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK)
24228 
24229 #define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U)
24230 #define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U)
24231 /*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:.
24232  *  0b1..USB0 Host clock is high.
24233  *  0b0..USB0 Host clock is low.
24234  */
24235 #define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK)
24236 /*! @} */
24237 
24238 /*! @name FMCFLUSH - FMCflush control */
24239 /*! @{ */
24240 
24241 #define SYSCON_FMCFLUSH_FLUSH_MASK               (0x1U)
24242 #define SYSCON_FMCFLUSH_FLUSH_SHIFT              (0U)
24243 /*! FLUSH - Flush control
24244  *  0b1..Flush the FMC buffer contents.
24245  *  0b0..No action is performed.
24246  */
24247 #define SYSCON_FMCFLUSH_FLUSH(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK)
24248 /*! @} */
24249 
24250 /*! @name MCLKIO - MCLK control */
24251 /*! @{ */
24252 
24253 #define SYSCON_MCLKIO_MCLKIO_MASK                (0x1U)
24254 #define SYSCON_MCLKIO_MCLKIO_SHIFT               (0U)
24255 /*! MCLKIO - MCLK control.
24256  *  0b0..input mode.
24257  *  0b1..output mode.
24258  */
24259 #define SYSCON_MCLKIO_MCLKIO(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK)
24260 /*! @} */
24261 
24262 /*! @name USB1NEEDCLKCTRL - USB1 need clock control */
24263 /*! @{ */
24264 
24265 #define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U)
24266 #define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U)
24267 /*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control:
24268  *  0b0..HOST_NEEDCLK is under hardware control.
24269  *  0b1..HOST_NEEDCLK is forced high.
24270  */
24271 #define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK)
24272 
24273 #define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U)
24274 #define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U)
24275 /*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt:
24276  *  0b0..Falling edge of DEV_NEEDCLK triggers wake-up.
24277  *  0b1..Rising edge of DEV_NEEDCLK triggers wake-up.
24278  */
24279 #define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK)
24280 
24281 #define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U)
24282 #define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U)
24283 /*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control:
24284  *  0b0..HOST_NEEDCLK is under hardware control.
24285  *  0b1..HOST_NEEDCLK is forced high.
24286  */
24287 #define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK)
24288 
24289 #define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U)
24290 #define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U)
24291 /*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt.
24292  *  0b0..Falling edge of HOST_NEEDCLK triggers wake-up.
24293  *  0b1..Rising edge of HOST_NEEDCLK triggers wake-up.
24294  */
24295 #define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK)
24296 
24297 #define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)
24298 #define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
24299 /*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic.
24300  *  0b0..Forces USB1_PHY to wake-up.
24301  *  0b1..Normal USB1_PHY behavior.
24302  */
24303 #define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK)
24304 /*! @} */
24305 
24306 /*! @name USB1NEEDCLKSTAT - USB1 need clock status */
24307 /*! @{ */
24308 
24309 #define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK  (0x1U)
24310 #define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U)
24311 /*! DEV_NEEDCLK - USB1 Device need_clock signal status:.
24312  *  0b1..DEV_NEEDCLK is high.
24313  *  0b0..DEV_NEEDCLK is low.
24314  */
24315 #define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK)
24316 
24317 #define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U)
24318 #define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U)
24319 /*! HOST_NEEDCLK - USB1 Host need_clock signal status:.
24320  *  0b1..HOST_NEEDCLK is high.
24321  *  0b0..HOST_NEEDCLK is low.
24322  */
24323 #define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK)
24324 /*! @} */
24325 
24326 /*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
24327 /*! @{ */
24328 
24329 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK   (0x3U)
24330 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT  (0U)
24331 /*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
24332  *  0b00..0 degree shift.
24333  *  0b01..90 degree shift.
24334  *  0b10..180 degree shift.
24335  *  0b11..270 degree shift.
24336  */
24337 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
24338 
24339 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
24340 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
24341 /*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
24342  *  0b00..0 degree shift.
24343  *  0b01..90 degree shift.
24344  *  0b10..180 degree shift.
24345  *  0b11..270 degree shift.
24346  */
24347 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
24348 
24349 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK     (0x80U)
24350 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT    (7U)
24351 /*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.
24352  *  0b0..Bypassed.
24353  *  0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled.
24354  */
24355 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
24356 
24357 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK   (0x1F0000U)
24358 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT  (16U)
24359 /*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
24360  */
24361 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
24362 
24363 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
24364 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
24365 /*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
24366  *  0b1..Enable drive delay.
24367  *  0b0..Disable drive delay.
24368  */
24369 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
24370 
24371 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
24372 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
24373 /*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
24374  */
24375 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
24376 
24377 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
24378 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
24379 /*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
24380  *  0b1..Enables sample delay.
24381  *  0b0..Disables sample delay.
24382  */
24383 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
24384 /*! @} */
24385 
24386 /*! @name PLL1CTRL - PLL1 550m control */
24387 /*! @{ */
24388 
24389 #define SYSCON_PLL1CTRL_SELR_MASK                (0xFU)
24390 #define SYSCON_PLL1CTRL_SELR_SHIFT               (0U)
24391 /*! SELR - Bandwidth select R value.
24392  */
24393 #define SYSCON_PLL1CTRL_SELR(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK)
24394 
24395 #define SYSCON_PLL1CTRL_SELI_MASK                (0x3F0U)
24396 #define SYSCON_PLL1CTRL_SELI_SHIFT               (4U)
24397 /*! SELI - Bandwidth select I value.
24398  */
24399 #define SYSCON_PLL1CTRL_SELI(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK)
24400 
24401 #define SYSCON_PLL1CTRL_SELP_MASK                (0x7C00U)
24402 #define SYSCON_PLL1CTRL_SELP_SHIFT               (10U)
24403 /*! SELP - Bandwidth select P value.
24404  */
24405 #define SYSCON_PLL1CTRL_SELP(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK)
24406 
24407 #define SYSCON_PLL1CTRL_BYPASSPLL_MASK           (0x8000U)
24408 #define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT          (15U)
24409 /*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default).
24410  *  0b1..PLL input clock is sent directly to the PLL output.
24411  *  0b0..use PLL.
24412  */
24413 #define SYSCON_PLL1CTRL_BYPASSPLL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK)
24414 
24415 #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK      (0x10000U)
24416 #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT     (16U)
24417 /*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider.
24418  *  0b1..bypass of the divide-by-2 divider in the post-divider.
24419  *  0b0..use the divide-by-2 divider in the post-divider.
24420  */
24421 #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)
24422 
24423 #define SYSCON_PLL1CTRL_LIMUPOFF_MASK            (0x20000U)
24424 #define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT           (17U)
24425 /*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications.
24426  */
24427 #define SYSCON_PLL1CTRL_LIMUPOFF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK)
24428 
24429 #define SYSCON_PLL1CTRL_BWDIRECT_MASK            (0x40000U)
24430 #define SYSCON_PLL1CTRL_BWDIRECT_SHIFT           (18U)
24431 /*! BWDIRECT - control of the bandwidth of the PLL.
24432  *  0b1..modify the bandwidth of the PLL directly.
24433  *  0b0..the bandwidth is changed synchronously with the feedback-divider.
24434  */
24435 #define SYSCON_PLL1CTRL_BWDIRECT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK)
24436 
24437 #define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK        (0x80000U)
24438 #define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT       (19U)
24439 /*! BYPASSPREDIV - bypass of the pre-divider.
24440  *  0b1..bypass of the pre-divider.
24441  *  0b0..use the pre-divider.
24442  */
24443 #define SYSCON_PLL1CTRL_BYPASSPREDIV(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK)
24444 
24445 #define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK       (0x100000U)
24446 #define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT      (20U)
24447 /*! BYPASSPOSTDIV - bypass of the post-divider.
24448  *  0b1..bypass of the post-divider.
24449  *  0b0..use the post-divider.
24450  */
24451 #define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK)
24452 
24453 #define SYSCON_PLL1CTRL_CLKEN_MASK               (0x200000U)
24454 #define SYSCON_PLL1CTRL_CLKEN_SHIFT              (21U)
24455 /*! CLKEN - enable the output clock.
24456  *  0b1..Enable the output clock.
24457  *  0b0..Disable the output clock.
24458  */
24459 #define SYSCON_PLL1CTRL_CLKEN(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK)
24460 
24461 #define SYSCON_PLL1CTRL_FRMEN_MASK               (0x400000U)
24462 #define SYSCON_PLL1CTRL_FRMEN_SHIFT              (22U)
24463 /*! FRMEN - 1: free running mode.
24464  */
24465 #define SYSCON_PLL1CTRL_FRMEN(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK)
24466 
24467 #define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK        (0x800000U)
24468 #define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT       (23U)
24469 /*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable.
24470  */
24471 #define SYSCON_PLL1CTRL_FRMCLKSTABLE(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK)
24472 
24473 #define SYSCON_PLL1CTRL_SKEWEN_MASK              (0x1000000U)
24474 #define SYSCON_PLL1CTRL_SKEWEN_SHIFT             (24U)
24475 /*! SKEWEN - Skew mode.
24476  *  0b1..skewmode is enable.
24477  *  0b0..skewmode is disable.
24478  */
24479 #define SYSCON_PLL1CTRL_SKEWEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK)
24480 /*! @} */
24481 
24482 /*! @name PLL1STAT - PLL1 550m status */
24483 /*! @{ */
24484 
24485 #define SYSCON_PLL1STAT_LOCK_MASK                (0x1U)
24486 #define SYSCON_PLL1STAT_LOCK_SHIFT               (0U)
24487 /*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz.
24488  */
24489 #define SYSCON_PLL1STAT_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK)
24490 
24491 #define SYSCON_PLL1STAT_PREDIVACK_MASK           (0x2U)
24492 #define SYSCON_PLL1STAT_PREDIVACK_SHIFT          (1U)
24493 /*! PREDIVACK - pre-divider ratio change acknowledge.
24494  */
24495 #define SYSCON_PLL1STAT_PREDIVACK(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK)
24496 
24497 #define SYSCON_PLL1STAT_FEEDDIVACK_MASK          (0x4U)
24498 #define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT         (2U)
24499 /*! FEEDDIVACK - feedback divider ratio change acknowledge.
24500  */
24501 #define SYSCON_PLL1STAT_FEEDDIVACK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK)
24502 
24503 #define SYSCON_PLL1STAT_POSTDIVACK_MASK          (0x8U)
24504 #define SYSCON_PLL1STAT_POSTDIVACK_SHIFT         (3U)
24505 /*! POSTDIVACK - post-divider ratio change acknowledge.
24506  */
24507 #define SYSCON_PLL1STAT_POSTDIVACK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK)
24508 
24509 #define SYSCON_PLL1STAT_FRMDET_MASK              (0x10U)
24510 #define SYSCON_PLL1STAT_FRMDET_SHIFT             (4U)
24511 /*! FRMDET - free running detector output (active high).
24512  */
24513 #define SYSCON_PLL1STAT_FRMDET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK)
24514 /*! @} */
24515 
24516 /*! @name PLL1NDEC - PLL1 550m N divider */
24517 /*! @{ */
24518 
24519 #define SYSCON_PLL1NDEC_NDIV_MASK                (0xFFU)
24520 #define SYSCON_PLL1NDEC_NDIV_SHIFT               (0U)
24521 /*! NDIV - pre-divider divider ratio (N-divider).
24522  */
24523 #define SYSCON_PLL1NDEC_NDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK)
24524 
24525 #define SYSCON_PLL1NDEC_NREQ_MASK                (0x100U)
24526 #define SYSCON_PLL1NDEC_NREQ_SHIFT               (8U)
24527 /*! NREQ - pre-divider ratio change request.
24528  */
24529 #define SYSCON_PLL1NDEC_NREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK)
24530 /*! @} */
24531 
24532 /*! @name PLL1MDEC - PLL1 550m M divider */
24533 /*! @{ */
24534 
24535 #define SYSCON_PLL1MDEC_MDIV_MASK                (0xFFFFU)
24536 #define SYSCON_PLL1MDEC_MDIV_SHIFT               (0U)
24537 /*! MDIV - feedback divider divider ratio (M-divider).
24538  */
24539 #define SYSCON_PLL1MDEC_MDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK)
24540 
24541 #define SYSCON_PLL1MDEC_MREQ_MASK                (0x10000U)
24542 #define SYSCON_PLL1MDEC_MREQ_SHIFT               (16U)
24543 /*! MREQ - feedback ratio change request.
24544  */
24545 #define SYSCON_PLL1MDEC_MREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK)
24546 /*! @} */
24547 
24548 /*! @name PLL1PDEC - PLL1 550m P divider */
24549 /*! @{ */
24550 
24551 #define SYSCON_PLL1PDEC_PDIV_MASK                (0x1FU)
24552 #define SYSCON_PLL1PDEC_PDIV_SHIFT               (0U)
24553 /*! PDIV - post-divider divider ratio (P-divider)
24554  */
24555 #define SYSCON_PLL1PDEC_PDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK)
24556 
24557 #define SYSCON_PLL1PDEC_PREQ_MASK                (0x20U)
24558 #define SYSCON_PLL1PDEC_PREQ_SHIFT               (5U)
24559 /*! PREQ - feedback ratio change request.
24560  */
24561 #define SYSCON_PLL1PDEC_PREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK)
24562 /*! @} */
24563 
24564 /*! @name PLL0CTRL - PLL0 550m control */
24565 /*! @{ */
24566 
24567 #define SYSCON_PLL0CTRL_SELR_MASK                (0xFU)
24568 #define SYSCON_PLL0CTRL_SELR_SHIFT               (0U)
24569 /*! SELR - Bandwidth select R value.
24570  */
24571 #define SYSCON_PLL0CTRL_SELR(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK)
24572 
24573 #define SYSCON_PLL0CTRL_SELI_MASK                (0x3F0U)
24574 #define SYSCON_PLL0CTRL_SELI_SHIFT               (4U)
24575 /*! SELI - Bandwidth select I value.
24576  */
24577 #define SYSCON_PLL0CTRL_SELI(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK)
24578 
24579 #define SYSCON_PLL0CTRL_SELP_MASK                (0x7C00U)
24580 #define SYSCON_PLL0CTRL_SELP_SHIFT               (10U)
24581 /*! SELP - Bandwidth select P value.
24582  */
24583 #define SYSCON_PLL0CTRL_SELP(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK)
24584 
24585 #define SYSCON_PLL0CTRL_BYPASSPLL_MASK           (0x8000U)
24586 #define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT          (15U)
24587 /*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default).
24588  *  0b1..Bypass PLL input clock is sent directly to the PLL output.
24589  *  0b0..use PLL.
24590  */
24591 #define SYSCON_PLL0CTRL_BYPASSPLL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK)
24592 
24593 #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK      (0x10000U)
24594 #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT     (16U)
24595 /*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider.
24596  *  0b1..bypass of the divide-by-2 divider in the post-divider.
24597  *  0b0..use the divide-by-2 divider in the post-divider.
24598  */
24599 #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
24600 
24601 #define SYSCON_PLL0CTRL_LIMUPOFF_MASK            (0x20000U)
24602 #define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT           (17U)
24603 /*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications.
24604  */
24605 #define SYSCON_PLL0CTRL_LIMUPOFF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK)
24606 
24607 #define SYSCON_PLL0CTRL_BWDIRECT_MASK            (0x40000U)
24608 #define SYSCON_PLL0CTRL_BWDIRECT_SHIFT           (18U)
24609 /*! BWDIRECT - Control of the bandwidth of the PLL.
24610  *  0b1..modify the bandwidth of the PLL directly.
24611  *  0b0..the bandwidth is changed synchronously with the feedback-divider.
24612  */
24613 #define SYSCON_PLL0CTRL_BWDIRECT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK)
24614 
24615 #define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK        (0x80000U)
24616 #define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT       (19U)
24617 /*! BYPASSPREDIV - bypass of the pre-divider.
24618  *  0b1..bypass of the pre-divider.
24619  *  0b0..use the pre-divider.
24620  */
24621 #define SYSCON_PLL0CTRL_BYPASSPREDIV(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK)
24622 
24623 #define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK       (0x100000U)
24624 #define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT      (20U)
24625 /*! BYPASSPOSTDIV - bypass of the post-divider.
24626  *  0b1..bypass of the post-divider.
24627  *  0b0..use the post-divider.
24628  */
24629 #define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK)
24630 
24631 #define SYSCON_PLL0CTRL_CLKEN_MASK               (0x200000U)
24632 #define SYSCON_PLL0CTRL_CLKEN_SHIFT              (21U)
24633 /*! CLKEN - enable the output clock.
24634  *  0b1..enable the output clock.
24635  *  0b0..disable the output clock.
24636  */
24637 #define SYSCON_PLL0CTRL_CLKEN(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK)
24638 
24639 #define SYSCON_PLL0CTRL_FRMEN_MASK               (0x400000U)
24640 #define SYSCON_PLL0CTRL_FRMEN_SHIFT              (22U)
24641 /*! FRMEN - free running mode.
24642  *  0b1..free running mode is enable.
24643  *  0b0..free running mode is disable.
24644  */
24645 #define SYSCON_PLL0CTRL_FRMEN(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK)
24646 
24647 #define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK        (0x800000U)
24648 #define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT       (23U)
24649 /*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable.
24650  */
24651 #define SYSCON_PLL0CTRL_FRMCLKSTABLE(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK)
24652 
24653 #define SYSCON_PLL0CTRL_SKEWEN_MASK              (0x1000000U)
24654 #define SYSCON_PLL0CTRL_SKEWEN_SHIFT             (24U)
24655 /*! SKEWEN - skew mode.
24656  *  0b1..skew mode is enable.
24657  *  0b0..skew mode is disable.
24658  */
24659 #define SYSCON_PLL0CTRL_SKEWEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK)
24660 /*! @} */
24661 
24662 /*! @name PLL0STAT - PLL0 550m status */
24663 /*! @{ */
24664 
24665 #define SYSCON_PLL0STAT_LOCK_MASK                (0x1U)
24666 #define SYSCON_PLL0STAT_LOCK_SHIFT               (0U)
24667 /*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz.
24668  */
24669 #define SYSCON_PLL0STAT_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK)
24670 
24671 #define SYSCON_PLL0STAT_PREDIVACK_MASK           (0x2U)
24672 #define SYSCON_PLL0STAT_PREDIVACK_SHIFT          (1U)
24673 /*! PREDIVACK - pre-divider ratio change acknowledge.
24674  */
24675 #define SYSCON_PLL0STAT_PREDIVACK(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK)
24676 
24677 #define SYSCON_PLL0STAT_FEEDDIVACK_MASK          (0x4U)
24678 #define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT         (2U)
24679 /*! FEEDDIVACK - feedback divider ratio change acknowledge.
24680  */
24681 #define SYSCON_PLL0STAT_FEEDDIVACK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK)
24682 
24683 #define SYSCON_PLL0STAT_POSTDIVACK_MASK          (0x8U)
24684 #define SYSCON_PLL0STAT_POSTDIVACK_SHIFT         (3U)
24685 /*! POSTDIVACK - post-divider ratio change acknowledge.
24686  */
24687 #define SYSCON_PLL0STAT_POSTDIVACK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK)
24688 
24689 #define SYSCON_PLL0STAT_FRMDET_MASK              (0x10U)
24690 #define SYSCON_PLL0STAT_FRMDET_SHIFT             (4U)
24691 /*! FRMDET - free running detector output (active high).
24692  */
24693 #define SYSCON_PLL0STAT_FRMDET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK)
24694 /*! @} */
24695 
24696 /*! @name PLL0NDEC - PLL0 550m N divider */
24697 /*! @{ */
24698 
24699 #define SYSCON_PLL0NDEC_NDIV_MASK                (0xFFU)
24700 #define SYSCON_PLL0NDEC_NDIV_SHIFT               (0U)
24701 /*! NDIV - pre-divider divider ratio (N-divider).
24702  */
24703 #define SYSCON_PLL0NDEC_NDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK)
24704 
24705 #define SYSCON_PLL0NDEC_NREQ_MASK                (0x100U)
24706 #define SYSCON_PLL0NDEC_NREQ_SHIFT               (8U)
24707 /*! NREQ - pre-divider ratio change request.
24708  */
24709 #define SYSCON_PLL0NDEC_NREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK)
24710 /*! @} */
24711 
24712 /*! @name PLL0PDEC - PLL0 550m P divider */
24713 /*! @{ */
24714 
24715 #define SYSCON_PLL0PDEC_PDIV_MASK                (0x1FU)
24716 #define SYSCON_PLL0PDEC_PDIV_SHIFT               (0U)
24717 /*! PDIV - post-divider divider ratio (P-divider)
24718  */
24719 #define SYSCON_PLL0PDEC_PDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK)
24720 
24721 #define SYSCON_PLL0PDEC_PREQ_MASK                (0x20U)
24722 #define SYSCON_PLL0PDEC_PREQ_SHIFT               (5U)
24723 /*! PREQ - feedback ratio change request.
24724  */
24725 #define SYSCON_PLL0PDEC_PREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK)
24726 /*! @} */
24727 
24728 /*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */
24729 /*! @{ */
24730 
24731 #define SYSCON_PLL0SSCG0_MD_LBS_MASK             (0xFFFFFFFFU)
24732 #define SYSCON_PLL0SSCG0_MD_LBS_SHIFT            (0U)
24733 /*! MD_LBS - input word of the wrapper bit 31 to 0.
24734  */
24735 #define SYSCON_PLL0SSCG0_MD_LBS(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK)
24736 /*! @} */
24737 
24738 /*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */
24739 /*! @{ */
24740 
24741 #define SYSCON_PLL0SSCG1_MD_MBS_MASK             (0x1U)
24742 #define SYSCON_PLL0SSCG1_MD_MBS_SHIFT            (0U)
24743 /*! MD_MBS - input word of the wrapper bit 32.
24744  */
24745 #define SYSCON_PLL0SSCG1_MD_MBS(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK)
24746 
24747 #define SYSCON_PLL0SSCG1_MD_REQ_MASK             (0x2U)
24748 #define SYSCON_PLL0SSCG1_MD_REQ_SHIFT            (1U)
24749 /*! MD_REQ - md change request.
24750  */
24751 #define SYSCON_PLL0SSCG1_MD_REQ(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK)
24752 
24753 #define SYSCON_PLL0SSCG1_MF_MASK                 (0x1CU)
24754 #define SYSCON_PLL0SSCG1_MF_SHIFT                (2U)
24755 /*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3.
24756  */
24757 #define SYSCON_PLL0SSCG1_MF(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)
24758 
24759 #define SYSCON_PLL0SSCG1_MR_MASK                 (0xE0U)
24760 #define SYSCON_PLL0SSCG1_MR_SHIFT                (5U)
24761 /*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec)
24762  *    mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1.
24763  */
24764 #define SYSCON_PLL0SSCG1_MR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK)
24765 
24766 #define SYSCON_PLL0SSCG1_MC_MASK                 (0x300U)
24767 #define SYSCON_PLL0SSCG1_MC_SHIFT                (8U)
24768 /*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a
24769  *    triangular modulation at the output of the PLL, giving a flat frequency spectrum.
24770  */
24771 #define SYSCON_PLL0SSCG1_MC(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK)
24772 
24773 #define SYSCON_PLL0SSCG1_MDIV_EXT_MASK           (0x3FFFC00U)
24774 #define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT          (10U)
24775 /*! MDIV_EXT - to select an external mdiv value.
24776  */
24777 #define SYSCON_PLL0SSCG1_MDIV_EXT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK)
24778 
24779 #define SYSCON_PLL0SSCG1_MREQ_MASK               (0x4000000U)
24780 #define SYSCON_PLL0SSCG1_MREQ_SHIFT              (26U)
24781 /*! MREQ - to select an external mreq value.
24782  */
24783 #define SYSCON_PLL0SSCG1_MREQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK)
24784 
24785 #define SYSCON_PLL0SSCG1_DITHER_MASK             (0x8000000U)
24786 #define SYSCON_PLL0SSCG1_DITHER_SHIFT            (27U)
24787 /*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way
24788  *    (white noise), in order to decrease the probability that the modulated waveform will occur
24789  *    with the same phase on a particular point on the screen.
24790  */
24791 #define SYSCON_PLL0SSCG1_DITHER(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK)
24792 
24793 #define SYSCON_PLL0SSCG1_SEL_EXT_MASK            (0x10000000U)
24794 #define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT           (28U)
24795 /*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext.
24796  */
24797 #define SYSCON_PLL0SSCG1_SEL_EXT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
24798 /*! @} */
24799 
24800 /*! @name FUNCRETENTIONCTRL - Functional retention control register */
24801 /*! @{ */
24802 
24803 #define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U)
24804 #define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U)
24805 /*! FUNCRETENA - functional retention in power down only.
24806  *  0b1..enable functional retention.
24807  *  0b0..disable functional retention.
24808  */
24809 #define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK)
24810 
24811 #define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK  (0x3FFEU)
24812 #define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U)
24813 /*! RET_START - Start address divided by 4 inside SRAMX bank.
24814  */
24815 #define SYSCON_FUNCRETENTIONCTRL_RET_START(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK)
24816 
24817 #define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK  (0xFFC000U)
24818 #define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U)
24819 /*! RET_LENTH - lenth of Scan chains to save.
24820  */
24821 #define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)
24822 /*! @} */
24823 
24824 /*! @name CPUCTRL - CPU Control for multiple processors */
24825 /*! @{ */
24826 
24827 #define SYSCON_CPUCTRL_CPU1CLKEN_MASK            (0x8U)
24828 #define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT           (3U)
24829 /*! CPU1CLKEN - CPU1 clock enable.
24830  *  0b1..The CPU1 clock is enabled.
24831  *  0b0..The CPU1 clock is not enabled.
24832  */
24833 #define SYSCON_CPUCTRL_CPU1CLKEN(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK)
24834 
24835 #define SYSCON_CPUCTRL_CPU1RSTEN_MASK            (0x20U)
24836 #define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT           (5U)
24837 /*! CPU1RSTEN - CPU1 reset.
24838  *  0b1..The CPU1 is being reset.
24839  *  0b0..The CPU1 is not being reset.
24840  */
24841 #define SYSCON_CPUCTRL_CPU1RSTEN(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK)
24842 /*! @} */
24843 
24844 /*! @name CPBOOT - Coprocessor Boot Address */
24845 /*! @{ */
24846 
24847 #define SYSCON_CPBOOT_CPBOOT_MASK                (0xFFFFFFFFU)
24848 #define SYSCON_CPBOOT_CPBOOT_SHIFT               (0U)
24849 /*! CPBOOT - Coprocessor Boot Address for CPU1.
24850  */
24851 #define SYSCON_CPBOOT_CPBOOT(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK)
24852 /*! @} */
24853 
24854 /*! @name CPSTAT - CPU Status */
24855 /*! @{ */
24856 
24857 #define SYSCON_CPSTAT_CPU0SLEEPING_MASK          (0x1U)
24858 #define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT         (0U)
24859 /*! CPU0SLEEPING - The CPU0 sleeping state.
24860  *  0b1..the CPU is sleeping.
24861  *  0b0..the CPU is not sleeping.
24862  */
24863 #define SYSCON_CPSTAT_CPU0SLEEPING(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK)
24864 
24865 #define SYSCON_CPSTAT_CPU1SLEEPING_MASK          (0x2U)
24866 #define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT         (1U)
24867 /*! CPU1SLEEPING - The CPU1 sleeping state.
24868  *  0b1..the CPU is sleeping.
24869  *  0b0..the CPU is not sleeping.
24870  */
24871 #define SYSCON_CPSTAT_CPU1SLEEPING(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK)
24872 
24873 #define SYSCON_CPSTAT_CPU0LOCKUP_MASK            (0x4U)
24874 #define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT           (2U)
24875 /*! CPU0LOCKUP - The CPU0 lockup state.
24876  *  0b1..the CPU is in lockup.
24877  *  0b0..the CPU is not in lockup.
24878  */
24879 #define SYSCON_CPSTAT_CPU0LOCKUP(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK)
24880 
24881 #define SYSCON_CPSTAT_CPU1LOCKUP_MASK            (0x8U)
24882 #define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT           (3U)
24883 /*! CPU1LOCKUP - The CPU1 lockup state.
24884  *  0b1..the CPU is in lockup.
24885  *  0b0..the CPU is not in lockup.
24886  */
24887 #define SYSCON_CPSTAT_CPU1LOCKUP(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK)
24888 /*! @} */
24889 
24890 /*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */
24891 /*! @{ */
24892 
24893 #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U)
24894 #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U)
24895 /*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module.
24896  *  0b1..The clock is enabled.
24897  *  0b0..The clock is not enabled.
24898  */
24899 #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK)
24900 
24901 #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U)
24902 #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U)
24903 /*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK.
24904  *  0b1..The clock is enabled.
24905  *  0b0..The clock is not enabled.
24906  */
24907 #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK)
24908 
24909 #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U)
24910 #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U)
24911 /*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module.
24912  *  0b1..The clock is enabled.
24913  *  0b0..The clock is not enabled.
24914  */
24915 #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK)
24916 
24917 #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK  (0x10U)
24918 #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U)
24919 /*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module.
24920  *  0b1..The clock is enabled.
24921  *  0b0..The clock is not enabled.
24922  */
24923 #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK)
24924 
24925 #define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK         (0x20U)
24926 #define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT        (5U)
24927 /*! CLKIN_ENA - Enable clock_in clock for clock module.
24928  *  0b1..The clock is enabled.
24929  *  0b0..The clock is not enabled.
24930  */
24931 #define SYSCON_CLOCK_CTRL_CLKIN_ENA(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK)
24932 
24933 #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK   (0x40U)
24934 #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT  (6U)
24935 /*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen.
24936  *  0b1..The clock is enabled.
24937  *  0b0..The clock is not enabled.
24938  */
24939 #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK)
24940 
24941 #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U)
24942 #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U)
24943 /*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz.
24944  *  0b1..The clock is enabled.
24945  *  0b0..The clock is not enabled.
24946  */
24947 #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK)
24948 
24949 #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK    (0x100U)
24950 #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT   (8U)
24951 /*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration.
24952  *  0b1..The clock is enabled.
24953  *  0b0..The clock is not enabled.
24954  */
24955 #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK)
24956 
24957 #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U)
24958 #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U)
24959 /*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching.
24960  *  0b1..The clock is enabled.
24961  *  0b0..The clock is not enabled.
24962  */
24963 #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK)
24964 /*! @} */
24965 
24966 /*! @name COMP_INT_CTRL - Comparator Interrupt control */
24967 /*! @{ */
24968 
24969 #define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK     (0x1U)
24970 #define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT    (0U)
24971 /*! INT_ENABLE - Analog Comparator interrupt enable control:.
24972  *  0b1..interrupt enable.
24973  *  0b0..interrupt disable.
24974  */
24975 #define SYSCON_COMP_INT_CTRL_INT_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK)
24976 
24977 #define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK      (0x2U)
24978 #define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT     (1U)
24979 /*! INT_CLEAR - Analog Comparator interrupt clear.
24980  *  0b0..No effect.
24981  *  0b1..Clear the interrupt. Self-cleared bit.
24982  */
24983 #define SYSCON_COMP_INT_CTRL_INT_CLEAR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK)
24984 
24985 #define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK       (0x1CU)
24986 #define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT      (2U)
24987 /*! INT_CTRL - Comparator interrupt type selector:.
24988  *  0b000..The analog comparator interrupt edge sensitive is disabled.
24989  *  0b010..analog comparator interrupt is rising edge sensitive.
24990  *  0b100..analog comparator interrupt is falling edge sensitive.
24991  *  0b110..analog comparator interrupt is rising and falling edge sensitive.
24992  *  0b001..The analog comparator interrupt level sensitive is disabled.
24993  *  0b011..Analog Comparator interrupt is high level sensitive.
24994  *  0b101..Analog Comparator interrupt is low level sensitive.
24995  *  0b111..The analog comparator interrupt level sensitive is disabled.
24996  */
24997 #define SYSCON_COMP_INT_CTRL_INT_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK)
24998 
24999 #define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK     (0x20U)
25000 #define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT    (5U)
25001 /*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection.
25002  *  0b0..Select Analog Comparator filtered output as input for interrupt detection.
25003  *  0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when
25004  *       Analog comparator is used as wake up source in Power down mode.
25005  */
25006 #define SYSCON_COMP_INT_CTRL_INT_SOURCE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK)
25007 /*! @} */
25008 
25009 /*! @name COMP_INT_STATUS - Comparator Interrupt status */
25010 /*! @{ */
25011 
25012 #define SYSCON_COMP_INT_STATUS_STATUS_MASK       (0x1U)
25013 #define SYSCON_COMP_INT_STATUS_STATUS_SHIFT      (0U)
25014 /*! STATUS - Interrupt status BEFORE Interrupt Enable.
25015  *  0b0..no interrupt pending.
25016  *  0b1..interrupt pending.
25017  */
25018 #define SYSCON_COMP_INT_STATUS_STATUS(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK)
25019 
25020 #define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK   (0x2U)
25021 #define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT  (1U)
25022 /*! INT_STATUS - Interrupt status AFTER Interrupt Enable.
25023  *  0b0..no interrupt pending.
25024  *  0b1..interrupt pending.
25025  */
25026 #define SYSCON_COMP_INT_STATUS_INT_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK)
25027 
25028 #define SYSCON_COMP_INT_STATUS_VAL_MASK          (0x4U)
25029 #define SYSCON_COMP_INT_STATUS_VAL_SHIFT         (2U)
25030 /*! VAL - comparator analog output.
25031  *  0b1..P+ is greater than P-.
25032  *  0b0..P+ is smaller than P-.
25033  */
25034 #define SYSCON_COMP_INT_STATUS_VAL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK)
25035 /*! @} */
25036 
25037 /*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */
25038 /*! @{ */
25039 
25040 #define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK      (0x1U)
25041 #define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT     (0U)
25042 /*! ROM - Control automatic clock gating of ROM controller.
25043  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25044  *  0b0..Automatic clock gating is not overridden.
25045  */
25046 #define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK)
25047 
25048 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U)
25049 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U)
25050 /*! RAMX_CTRL - Control automatic clock gating of RAMX controller.
25051  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25052  *  0b0..Automatic clock gating is not overridden.
25053  */
25054 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK)
25055 
25056 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U)
25057 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U)
25058 /*! RAM0_CTRL - Control automatic clock gating of RAM0 controller.
25059  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25060  *  0b0..Automatic clock gating is not overridden.
25061  */
25062 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK)
25063 
25064 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U)
25065 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U)
25066 /*! RAM1_CTRL - Control automatic clock gating of RAM1 controller.
25067  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25068  *  0b0..Automatic clock gating is not overridden.
25069  */
25070 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK)
25071 
25072 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U)
25073 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U)
25074 /*! RAM2_CTRL - Control automatic clock gating of RAM2 controller.
25075  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25076  *  0b0..Automatic clock gating is not overridden.
25077  */
25078 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK)
25079 
25080 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U)
25081 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U)
25082 /*! RAM3_CTRL - Control automatic clock gating of RAM3 controller.
25083  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25084  *  0b0..Automatic clock gating is not overridden.
25085  */
25086 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK)
25087 
25088 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U)
25089 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U)
25090 /*! RAM4_CTRL - Control automatic clock gating of RAM4 controller.
25091  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25092  *  0b0..Automatic clock gating is not overridden.
25093  */
25094 #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK)
25095 
25096 #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U)
25097 #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U)
25098 /*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0.
25099  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25100  *  0b0..Automatic clock gating is not overridden.
25101  */
25102 #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK)
25103 
25104 #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U)
25105 #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U)
25106 /*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1.
25107  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25108  *  0b0..Automatic clock gating is not overridden.
25109  */
25110 #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK)
25111 
25112 #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK   (0x800U)
25113 #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT  (11U)
25114 /*! CRCGEN - Control automatic clock gating of CRCGEN controller.
25115  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25116  *  0b0..Automatic clock gating is not overridden.
25117  */
25118 #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK)
25119 
25120 #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK    (0x1000U)
25121 #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT   (12U)
25122 /*! SDMA0 - Control automatic clock gating of DMA0 controller.
25123  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25124  *  0b0..Automatic clock gating is not overridden.
25125  */
25126 #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK)
25127 
25128 #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK    (0x2000U)
25129 #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT   (13U)
25130 /*! SDMA1 - Control automatic clock gating of DMA1 controller.
25131  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25132  *  0b0..Automatic clock gating is not overridden.
25133  */
25134 #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK)
25135 
25136 #define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK     (0x4000U)
25137 #define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT    (14U)
25138 /*! USB0 - Control automatic clock gating of USB controller.
25139  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25140  *  0b0..Automatic clock gating is not overridden.
25141  */
25142 #define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK)
25143 
25144 #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK   (0x8000U)
25145 #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT  (15U)
25146 /*! SYSCON - Control automatic clock gating of synchronous system controller registers bank.
25147  *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
25148  *  0b0..Automatic clock gating is not overridden.
25149  */
25150 #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK)
25151 
25152 #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U)
25153 #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U)
25154 /*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect.
25155  *  0b1100000011011110..Bit Fields 0 - 15 of this register are updated
25156  *  0b0000000000000000..Bit Fields 0 - 15 of this register are not updated
25157  */
25158 #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK)
25159 /*! @} */
25160 
25161 /*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */
25162 /*! @{ */
25163 
25164 #define SYSCON_GPIOPSYNC_PSYNC_MASK              (0x1U)
25165 #define SYSCON_GPIOPSYNC_PSYNC_SHIFT             (0U)
25166 /*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module.
25167  *  0b1..bypass of the first stage of synchonization inside GPIO_INT module.
25168  *  0b0..use the first stage of synchonization inside GPIO_INT module.
25169  */
25170 #define SYSCON_GPIOPSYNC_PSYNC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK)
25171 /*! @} */
25172 
25173 /*! @name DEBUG_LOCK_EN - Control write access to security registers. */
25174 /*! @{ */
25175 
25176 #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK       (0xFU)
25177 #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT      (0U)
25178 /*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0,
25179  *    CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers.
25180  *  0b1010..1010: Enable write access to all 6 registers.
25181  *  0b0000..Any other value than b1010: disable write access to all 6 registers.
25182  */
25183 #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK)
25184 /*! @} */
25185 
25186 /*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */
25187 /*! @{ */
25188 
25189 #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK    (0x3U)
25190 #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT   (0U)
25191 /*! CPU0_DBGEN - CPU0 Invasive debug control:.
25192  *  0b10..10: Invasive debug is enabled.
25193  *  0b01..Any other value than b10: invasive debug is disable.
25194  */
25195 #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK)
25196 
25197 #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK    (0xCU)
25198 #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT   (2U)
25199 /*! CPU0_NIDEN - CPU0 Non Invasive debug control:.
25200  *  0b10..10: Invasive debug is enabled.
25201  *  0b01..Any other value than b10: invasive debug is disable.
25202  */
25203 #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK)
25204 
25205 #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK   (0x30U)
25206 #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT  (4U)
25207 /*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:.
25208  *  0b10..10: Invasive debug is enabled.
25209  *  0b01..Any other value than b10: invasive debug is disable.
25210  */
25211 #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK)
25212 
25213 #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK  (0xC0U)
25214 #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U)
25215 /*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:.
25216  *  0b10..10: Invasive debug is enabled.
25217  *  0b01..Any other value than b10: invasive debug is disable.
25218  */
25219 #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK)
25220 
25221 #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK    (0x300U)
25222 #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT   (8U)
25223 /*! CPU1_DBGEN - CPU1 Invasive debug control:.
25224  *  0b10..10: Invasive debug is enabled.
25225  *  0b01..Any other value than b10: invasive debug is disable.
25226  */
25227 #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK)
25228 
25229 #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK    (0xC00U)
25230 #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT   (10U)
25231 /*! CPU1_NIDEN - CPU1 Non Invasive debug control:.
25232  *  0b10..10: Invasive debug is enabled.
25233  *  0b01..Any other value than b10: invasive debug is disable.
25234  */
25235 #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK)
25236 /*! @} */
25237 
25238 /*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */
25239 /*! @{ */
25240 
25241 #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U)
25242 #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U)
25243 /*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:.
25244  *  0b10..10: Invasive debug is enabled.
25245  *  0b01..Any other value than b10: invasive debug is disable.
25246  */
25247 #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK)
25248 
25249 #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU)
25250 #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U)
25251 /*! CPU0_NIDEN - CPU0 Non Invasive debug control:.
25252  *  0b10..10: Invasive debug is enabled.
25253  *  0b01..Any other value than b10: invasive debug is disable.
25254  */
25255 #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK)
25256 
25257 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U)
25258 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U)
25259 /*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:.
25260  *  0b10..10: Invasive debug is enabled.
25261  *  0b01..Any other value than b10: invasive debug is disable.
25262  */
25263 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK)
25264 
25265 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U)
25266 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U)
25267 /*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:.
25268  *  0b10..10: Invasive debug is enabled.
25269  *  0b01..Any other value than b10: invasive debug is disable.
25270  */
25271 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK)
25272 
25273 #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U)
25274 #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U)
25275 /*! CPU1_DBGEN - CPU1 Invasive debug control:.
25276  *  0b10..10: Invasive debug is enabled.
25277  *  0b01..Any other value than b10: invasive debug is disable.
25278  */
25279 #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK)
25280 
25281 #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U)
25282 #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U)
25283 /*! CPU1_NIDEN - CPU1 Non Invasive debug control:.
25284  *  0b10..10: Invasive debug is enabled.
25285  *  0b01..Any other value than b10: invasive debug is disable.
25286  */
25287 #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK)
25288 /*! @} */
25289 
25290 /*! @name KEY_BLOCK - block quiddikey/PUF all index. */
25291 /*! @{ */
25292 
25293 #define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK          (0xFFFFFFFFU)
25294 #define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT         (0U)
25295 /*! KEY_BLOCK - Write a value to block quiddikey/PUF all index.
25296  */
25297 #define SYSCON_KEY_BLOCK_KEY_BLOCK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK)
25298 /*! @} */
25299 
25300 /*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */
25301 /*! @{ */
25302 
25303 #define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK     (0xFFFFFFFFU)
25304 #define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT    (0U)
25305 /*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential
25306  *    Beacon and Authentication Beacon) to application code.
25307  */
25308 #define SYSCON_DEBUG_AUTH_BEACON_BEACON(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK)
25309 /*! @} */
25310 
25311 /*! @name CPUCFG - CPUs configuration register */
25312 /*! @{ */
25313 
25314 #define SYSCON_CPUCFG_CPU1ENABLE_MASK            (0x4U)
25315 #define SYSCON_CPUCFG_CPU1ENABLE_SHIFT           (2U)
25316 /*! CPU1ENABLE - Enable CPU1.
25317  *  0b0..CPU1 is disable (Processor in reset).
25318  *  0b1..CPU1 is enable.
25319  */
25320 #define SYSCON_CPUCFG_CPU1ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK)
25321 /*! @} */
25322 
25323 /*! @name DEVICE_ID0 - Device ID */
25324 /*! @{ */
25325 
25326 #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK     (0xF00000U)
25327 #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT    (20U)
25328 /*! ROM_REV_MINOR - ROM revision.
25329  */
25330 #define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK)
25331 /*! @} */
25332 
25333 /*! @name DIEID - Chip revision ID and Number */
25334 /*! @{ */
25335 
25336 #define SYSCON_DIEID_REV_ID_MASK                 (0xFU)
25337 #define SYSCON_DIEID_REV_ID_SHIFT                (0U)
25338 /*! REV_ID - Chip Metal Revision ID.
25339  */
25340 #define SYSCON_DIEID_REV_ID(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK)
25341 
25342 #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK      (0xFFFFF0U)
25343 #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT     (4U)
25344 /*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B.
25345  */
25346 #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK)
25347 /*! @} */
25348 
25349 
25350 /*!
25351  * @}
25352  */ /* end of group SYSCON_Register_Masks */
25353 
25354 
25355 /* SYSCON - Peripheral instance base addresses */
25356 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
25357   /** Peripheral SYSCON base address */
25358   #define SYSCON_BASE                              (0x50000000u)
25359   /** Peripheral SYSCON base address */
25360   #define SYSCON_BASE_NS                           (0x40000000u)
25361   /** Peripheral SYSCON base pointer */
25362   #define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
25363   /** Peripheral SYSCON base pointer */
25364   #define SYSCON_NS                                ((SYSCON_Type *)SYSCON_BASE_NS)
25365   /** Array initializer of SYSCON peripheral base addresses */
25366   #define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
25367   /** Array initializer of SYSCON peripheral base pointers */
25368   #define SYSCON_BASE_PTRS                         { SYSCON }
25369   /** Array initializer of SYSCON peripheral base addresses */
25370   #define SYSCON_BASE_ADDRS_NS                     { SYSCON_BASE_NS }
25371   /** Array initializer of SYSCON peripheral base pointers */
25372   #define SYSCON_BASE_PTRS_NS                      { SYSCON_NS }
25373 #else
25374   /** Peripheral SYSCON base address */
25375   #define SYSCON_BASE                              (0x40000000u)
25376   /** Peripheral SYSCON base pointer */
25377   #define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
25378   /** Array initializer of SYSCON peripheral base addresses */
25379   #define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
25380   /** Array initializer of SYSCON peripheral base pointers */
25381   #define SYSCON_BASE_PTRS                         { SYSCON }
25382 #endif
25383 
25384 /*!
25385  * @}
25386  */ /* end of group SYSCON_Peripheral_Access_Layer */
25387 
25388 
25389 /* ----------------------------------------------------------------------------
25390    -- SYSCTL Peripheral Access Layer
25391    ---------------------------------------------------------------------------- */
25392 
25393 /*!
25394  * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer
25395  * @{
25396  */
25397 
25398 /** SYSCTL - Register Layout Typedef */
25399 typedef struct {
25400   __IO uint32_t UPDATELCKOUT;                      /**< update lock out control, offset: 0x0 */
25401        uint8_t RESERVED_0[60];
25402   __IO uint32_t FCCTRLSEL[8];                      /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */
25403        uint8_t RESERVED_1[32];
25404   __IO uint32_t SHAREDCTRLSET[2];                  /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */
25405        uint8_t RESERVED_2[120];
25406   __I  uint32_t USB_HS_STATUS;                     /**< Status register for USB HS, offset: 0x100 */
25407 } SYSCTL_Type;
25408 
25409 /* ----------------------------------------------------------------------------
25410    -- SYSCTL Register Masks
25411    ---------------------------------------------------------------------------- */
25412 
25413 /*!
25414  * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks
25415  * @{
25416  */
25417 
25418 /*! @name UPDATELCKOUT - update lock out control */
25419 /*! @{ */
25420 
25421 #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK    (0x1U)
25422 #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT   (0U)
25423 /*! UPDATELCKOUT - All Registers
25424  *  0b0..Normal Mode. Can be written to.
25425  *  0b1..Protected Mode. Cannot be written to.
25426  */
25427 #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK)
25428 /*! @} */
25429 
25430 /*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */
25431 /*! @{ */
25432 
25433 #define SYSCTL_FCCTRLSEL_SCKINSEL_MASK           (0x3U)
25434 #define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT          (0U)
25435 /*! SCKINSEL - Selects the source for SCK going into this Flexcomm.
25436  *  0b00..Selects the dedicated FCn_SCK function for this Flexcomm.
25437  *  0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0).
25438  *  0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1).
25439  *  0b11..Reserved.
25440  */
25441 #define SYSCTL_FCCTRLSEL_SCKINSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK)
25442 
25443 #define SYSCTL_FCCTRLSEL_WSINSEL_MASK            (0x300U)
25444 #define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT           (8U)
25445 /*! WSINSEL - Selects the source for WS going into this Flexcomm.
25446  *  0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm.
25447  *  0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0).
25448  *  0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1).
25449  *  0b11..Reserved.
25450  */
25451 #define SYSCTL_FCCTRLSEL_WSINSEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK)
25452 
25453 #define SYSCTL_FCCTRLSEL_DATAINSEL_MASK          (0x30000U)
25454 #define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT         (16U)
25455 /*! DATAINSEL - Selects the source for DATA input to this Flexcomm.
25456  *  0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm.
25457  *  0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0).
25458  *  0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1).
25459  *  0b11..Reserved.
25460  */
25461 #define SYSCTL_FCCTRLSEL_DATAINSEL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK)
25462 
25463 #define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK         (0x3000000U)
25464 #define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT        (24U)
25465 /*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm.
25466  *  0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm.
25467  *  0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0).
25468  *  0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1).
25469  *  0b11..Reserved.
25470  */
25471 #define SYSCTL_FCCTRLSEL_DATAOUTSEL(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK)
25472 /*! @} */
25473 
25474 /* The count of SYSCTL_FCCTRLSEL */
25475 #define SYSCTL_FCCTRLSEL_COUNT                   (8U)
25476 
25477 /*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */
25478 /*! @{ */
25479 
25480 #define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK   (0x7U)
25481 #define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT  (0U)
25482 /*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set.
25483  *  0b000..SCK for this shared signal set comes from Flexcomm 0.
25484  *  0b001..SCK for this shared signal set comes from Flexcomm 1.
25485  *  0b010..SCK for this shared signal set comes from Flexcomm 2.
25486  *  0b011..SCK for this shared signal set comes from Flexcomm 3.
25487  *  0b100..SCK for this shared signal set comes from Flexcomm 4.
25488  *  0b101..SCK for this shared signal set comes from Flexcomm 5.
25489  *  0b110..SCK for this shared signal set comes from Flexcomm 6.
25490  *  0b111..SCK for this shared signal set comes from Flexcomm 7.
25491  */
25492 #define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK)
25493 
25494 #define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK    (0x70U)
25495 #define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT   (4U)
25496 /*! SHAREDWSSEL - Selects the source for WS of this shared signal set.
25497  *  0b000..WS for this shared signal set comes from Flexcomm 0.
25498  *  0b001..WS for this shared signal set comes from Flexcomm 1.
25499  *  0b010..WS for this shared signal set comes from Flexcomm 2.
25500  *  0b011..WS for this shared signal set comes from Flexcomm 3.
25501  *  0b100..WS for this shared signal set comes from Flexcomm 4.
25502  *  0b101..WS for this shared signal set comes from Flexcomm 5.
25503  *  0b110..WS for this shared signal set comes from Flexcomm 6.
25504  *  0b111..WS for this shared signal set comes from Flexcomm 7.
25505  */
25506 #define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK)
25507 
25508 #define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK  (0x700U)
25509 #define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U)
25510 /*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set.
25511  *  0b000..DATA input for this shared signal set comes from Flexcomm 0.
25512  *  0b001..DATA input for this shared signal set comes from Flexcomm 1.
25513  *  0b010..DATA input for this shared signal set comes from Flexcomm 2.
25514  *  0b011..DATA input for this shared signal set comes from Flexcomm 3.
25515  *  0b100..DATA input for this shared signal set comes from Flexcomm 4.
25516  *  0b101..DATA input for this shared signal set comes from Flexcomm 5.
25517  *  0b110..DATA input for this shared signal set comes from Flexcomm 6.
25518  *  0b111..DATA input for this shared signal set comes from Flexcomm 7.
25519  */
25520 #define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK)
25521 
25522 #define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK   (0x10000U)
25523 #define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT  (16U)
25524 /*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set.
25525  *  0b0..Data output from FC0 does not contribute to this shared set.
25526  *  0b1..Data output from FC0 does contribute to this shared set.
25527  */
25528 #define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK)
25529 
25530 #define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK   (0x20000U)
25531 #define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT  (17U)
25532 /*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set.
25533  *  0b0..Data output from FC1 does not contribute to this shared set.
25534  *  0b1..Data output from FC1 does contribute to this shared set.
25535  */
25536 #define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK)
25537 
25538 #define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK   (0x40000U)
25539 #define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT  (18U)
25540 /*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set.
25541  *  0b0..Data output from FC2 does not contribute to this shared set.
25542  *  0b1..Data output from FC2 does contribute to this shared set.
25543  */
25544 #define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK)
25545 
25546 #define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK   (0x100000U)
25547 #define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT  (20U)
25548 /*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set.
25549  *  0b0..Data output from FC4 does not contribute to this shared set.
25550  *  0b1..Data output from FC4 does contribute to this shared set.
25551  */
25552 #define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK)
25553 
25554 #define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK   (0x200000U)
25555 #define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT  (21U)
25556 /*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set.
25557  *  0b0..Data output from FC5 does not contribute to this shared set.
25558  *  0b1..Data output from FC5 does contribute to this shared set.
25559  */
25560 #define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK)
25561 
25562 #define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK   (0x400000U)
25563 #define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT  (22U)
25564 /*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set.
25565  *  0b0..Data output from FC6 does not contribute to this shared set.
25566  *  0b1..Data output from FC6 does contribute to this shared set.
25567  */
25568 #define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK)
25569 
25570 #define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK   (0x800000U)
25571 #define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT  (23U)
25572 /*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set.
25573  *  0b0..Data output from FC7 does not contribute to this shared set.
25574  *  0b1..Data output from FC7 does contribute to this shared set.
25575  */
25576 #define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK)
25577 /*! @} */
25578 
25579 /* The count of SYSCTL_SHAREDCTRLSET */
25580 #define SYSCTL_SHAREDCTRLSET_COUNT               (2U)
25581 
25582 /*! @name USB_HS_STATUS - Status register for USB HS */
25583 /*! @{ */
25584 
25585 #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK   (0x1U)
25586 #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT  (0U)
25587 /*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply.
25588  *  0b0..3v3 supply is good.
25589  *  0b1..3v3 supply is too low.
25590  */
25591 #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK)
25592 /*! @} */
25593 
25594 
25595 /*!
25596  * @}
25597  */ /* end of group SYSCTL_Register_Masks */
25598 
25599 
25600 /* SYSCTL - Peripheral instance base addresses */
25601 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
25602   /** Peripheral SYSCTL base address */
25603   #define SYSCTL_BASE                              (0x50023000u)
25604   /** Peripheral SYSCTL base address */
25605   #define SYSCTL_BASE_NS                           (0x40023000u)
25606   /** Peripheral SYSCTL base pointer */
25607   #define SYSCTL                                   ((SYSCTL_Type *)SYSCTL_BASE)
25608   /** Peripheral SYSCTL base pointer */
25609   #define SYSCTL_NS                                ((SYSCTL_Type *)SYSCTL_BASE_NS)
25610   /** Array initializer of SYSCTL peripheral base addresses */
25611   #define SYSCTL_BASE_ADDRS                        { SYSCTL_BASE }
25612   /** Array initializer of SYSCTL peripheral base pointers */
25613   #define SYSCTL_BASE_PTRS                         { SYSCTL }
25614   /** Array initializer of SYSCTL peripheral base addresses */
25615   #define SYSCTL_BASE_ADDRS_NS                     { SYSCTL_BASE_NS }
25616   /** Array initializer of SYSCTL peripheral base pointers */
25617   #define SYSCTL_BASE_PTRS_NS                      { SYSCTL_NS }
25618 #else
25619   /** Peripheral SYSCTL base address */
25620   #define SYSCTL_BASE                              (0x40023000u)
25621   /** Peripheral SYSCTL base pointer */
25622   #define SYSCTL                                   ((SYSCTL_Type *)SYSCTL_BASE)
25623   /** Array initializer of SYSCTL peripheral base addresses */
25624   #define SYSCTL_BASE_ADDRS                        { SYSCTL_BASE }
25625   /** Array initializer of SYSCTL peripheral base pointers */
25626   #define SYSCTL_BASE_PTRS                         { SYSCTL }
25627 #endif
25628 
25629 /*!
25630  * @}
25631  */ /* end of group SYSCTL_Peripheral_Access_Layer */
25632 
25633 
25634 /* ----------------------------------------------------------------------------
25635    -- USART Peripheral Access Layer
25636    ---------------------------------------------------------------------------- */
25637 
25638 /*!
25639  * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
25640  * @{
25641  */
25642 
25643 /** USART - Register Layout Typedef */
25644 typedef struct {
25645   __IO uint32_t CFG;                               /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
25646   __IO uint32_t CTL;                               /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
25647   __IO uint32_t STAT;                              /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
25648   __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
25649   __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
25650        uint8_t RESERVED_0[12];
25651   __IO uint32_t BRG;                               /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
25652   __I  uint32_t INTSTAT;                           /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
25653   __IO uint32_t OSR;                               /**< Oversample selection register for asynchronous communication., offset: 0x28 */
25654   __IO uint32_t ADDR;                              /**< Address register for automatic address matching., offset: 0x2C */
25655        uint8_t RESERVED_1[3536];
25656   __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
25657   __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
25658   __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
25659        uint8_t RESERVED_2[4];
25660   __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
25661   __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
25662   __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
25663        uint8_t RESERVED_3[4];
25664   __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
25665        uint8_t RESERVED_4[12];
25666   __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
25667        uint8_t RESERVED_5[12];
25668   __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
25669        uint8_t RESERVED_6[4];
25670   __I  uint32_t FIFOSIZE;                          /**< FIFO size register, offset: 0xE48 */
25671        uint8_t RESERVED_7[432];
25672   __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
25673 } USART_Type;
25674 
25675 /* ----------------------------------------------------------------------------
25676    -- USART Register Masks
25677    ---------------------------------------------------------------------------- */
25678 
25679 /*!
25680  * @addtogroup USART_Register_Masks USART Register Masks
25681  * @{
25682  */
25683 
25684 /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
25685 /*! @{ */
25686 
25687 #define USART_CFG_ENABLE_MASK                    (0x1U)
25688 #define USART_CFG_ENABLE_SHIFT                   (0U)
25689 /*! ENABLE - USART Enable.
25690  *  0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0,
25691  *       all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control
25692  *       bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the
25693  *       transmitter has been reset and is therefore available.
25694  *  0b1..Enabled. The USART is enabled for operation.
25695  */
25696 #define USART_CFG_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
25697 
25698 #define USART_CFG_DATALEN_MASK                   (0xCU)
25699 #define USART_CFG_DATALEN_SHIFT                  (2U)
25700 /*! DATALEN - Selects the data size for the USART.
25701  *  0b00..7 bit Data length.
25702  *  0b01..8 bit Data length.
25703  *  0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
25704  *  0b11..Reserved.
25705  */
25706 #define USART_CFG_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
25707 
25708 #define USART_CFG_PARITYSEL_MASK                 (0x30U)
25709 #define USART_CFG_PARITYSEL_SHIFT                (4U)
25710 /*! PARITYSEL - Selects what type of parity is used by the USART.
25711  *  0b00..No parity.
25712  *  0b01..Reserved.
25713  *  0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even,
25714  *        and the number of 1s in a received character is expected to be even.
25715  *  0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd,
25716  *        and the number of 1s in a received character is expected to be odd.
25717  */
25718 #define USART_CFG_PARITYSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
25719 
25720 #define USART_CFG_STOPLEN_MASK                   (0x40U)
25721 #define USART_CFG_STOPLEN_SHIFT                  (6U)
25722 /*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
25723  *  0b0..1 stop bit.
25724  *  0b1..2 stop bits. This setting should only be used for asynchronous communication.
25725  */
25726 #define USART_CFG_STOPLEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
25727 
25728 #define USART_CFG_MODE32K_MASK                   (0x80U)
25729 #define USART_CFG_MODE32K_SHIFT                  (7U)
25730 /*! MODE32K - Selects standard or 32 kHz clocking mode.
25731  *  0b0..Disabled. USART uses standard clocking.
25732  *  0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.
25733  */
25734 #define USART_CFG_MODE32K(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
25735 
25736 #define USART_CFG_LINMODE_MASK                   (0x100U)
25737 #define USART_CFG_LINMODE_SHIFT                  (8U)
25738 /*! LINMODE - LIN break mode enable.
25739  *  0b0..Disabled. Break detect and generate is configured for normal operation.
25740  *  0b1..Enabled. Break detect and generate is configured for LIN bus operation.
25741  */
25742 #define USART_CFG_LINMODE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
25743 
25744 #define USART_CFG_CTSEN_MASK                     (0x200U)
25745 #define USART_CFG_CTSEN_SHIFT                    (9U)
25746 /*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input
25747  *    pin, or from the USART's own RTS if loopback mode is enabled.
25748  *  0b0..No flow control. The transmitter does not receive any automatic flow control signal.
25749  *  0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
25750  */
25751 #define USART_CFG_CTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
25752 
25753 #define USART_CFG_SYNCEN_MASK                    (0x800U)
25754 #define USART_CFG_SYNCEN_SHIFT                   (11U)
25755 /*! SYNCEN - Selects synchronous or asynchronous operation.
25756  *  0b0..Asynchronous mode.
25757  *  0b1..Synchronous mode.
25758  */
25759 #define USART_CFG_SYNCEN(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
25760 
25761 #define USART_CFG_CLKPOL_MASK                    (0x1000U)
25762 #define USART_CFG_CLKPOL_SHIFT                   (12U)
25763 /*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode.
25764  *  0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK.
25765  *  0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK.
25766  */
25767 #define USART_CFG_CLKPOL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
25768 
25769 #define USART_CFG_SYNCMST_MASK                   (0x4000U)
25770 #define USART_CFG_SYNCMST_SHIFT                  (14U)
25771 /*! SYNCMST - Synchronous mode Master select.
25772  *  0b0..Slave. When synchronous mode is enabled, the USART is a slave.
25773  *  0b1..Master. When synchronous mode is enabled, the USART is a master.
25774  */
25775 #define USART_CFG_SYNCMST(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
25776 
25777 #define USART_CFG_LOOP_MASK                      (0x8000U)
25778 #define USART_CFG_LOOP_SHIFT                     (15U)
25779 /*! LOOP - Selects data loopback mode.
25780  *  0b0..Normal operation.
25781  *  0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial
25782  *       data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD
25783  *       and Un_RTS activity will also appear on external pins if these functions are configured to appear on device
25784  *       pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
25785  */
25786 #define USART_CFG_LOOP(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
25787 
25788 #define USART_CFG_OETA_MASK                      (0x40000U)
25789 #define USART_CFG_OETA_SHIFT                     (18U)
25790 /*! OETA - Output Enable Turnaround time enable for RS-485 operation.
25791  *  0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
25792  *  0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the
25793  *       end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins
25794  *       before it is deasserted.
25795  */
25796 #define USART_CFG_OETA(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
25797 
25798 #define USART_CFG_AUTOADDR_MASK                  (0x80000U)
25799 #define USART_CFG_AUTOADDR_SHIFT                 (19U)
25800 /*! AUTOADDR - Automatic Address matching enable.
25801  *  0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the
25802  *       possibility of versatile addressing (e.g. respond to more than one address).
25803  *  0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in
25804  *       the ADDR register as the address to match.
25805  */
25806 #define USART_CFG_AUTOADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
25807 
25808 #define USART_CFG_OESEL_MASK                     (0x100000U)
25809 #define USART_CFG_OESEL_SHIFT                    (20U)
25810 /*! OESEL - Output Enable Select.
25811  *  0b0..Standard. The RTS signal is used as the standard flow control function.
25812  *  0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.
25813  */
25814 #define USART_CFG_OESEL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
25815 
25816 #define USART_CFG_OEPOL_MASK                     (0x200000U)
25817 #define USART_CFG_OEPOL_SHIFT                    (21U)
25818 /*! OEPOL - Output Enable Polarity.
25819  *  0b0..Low. If selected by OESEL, the output enable is active low.
25820  *  0b1..High. If selected by OESEL, the output enable is active high.
25821  */
25822 #define USART_CFG_OEPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
25823 
25824 #define USART_CFG_RXPOL_MASK                     (0x400000U)
25825 #define USART_CFG_RXPOL_SHIFT                    (22U)
25826 /*! RXPOL - Receive data polarity.
25827  *  0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start
25828  *       bit is 0, data is not inverted, and the stop bit is 1.
25829  *  0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is
25830  *       0, start bit is 1, data is inverted, and the stop bit is 0.
25831  */
25832 #define USART_CFG_RXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
25833 
25834 #define USART_CFG_TXPOL_MASK                     (0x800000U)
25835 #define USART_CFG_TXPOL_SHIFT                    (23U)
25836 /*! TXPOL - Transmit data polarity.
25837  *  0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is
25838  *       0, data is not inverted, and the stop bit is 1.
25839  *  0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value
25840  *       is 0, start bit is 1, data is inverted, and the stop bit is 0.
25841  */
25842 #define USART_CFG_TXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
25843 /*! @} */
25844 
25845 /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
25846 /*! @{ */
25847 
25848 #define USART_CTL_TXBRKEN_MASK                   (0x2U)
25849 #define USART_CTL_TXBRKEN_SHIFT                  (1U)
25850 /*! TXBRKEN - Break Enable.
25851  *  0b0..Normal operation.
25852  *  0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit
25853  *       is cleared. A break may be sent without danger of corrupting any currently transmitting character if the
25854  *       transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled
25855  *       (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
25856  */
25857 #define USART_CTL_TXBRKEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
25858 
25859 #define USART_CTL_ADDRDET_MASK                   (0x4U)
25860 #define USART_CTL_ADDRDET_SHIFT                  (2U)
25861 /*! ADDRDET - Enable address detect mode.
25862  *  0b0..Disabled. The USART presents all incoming data.
25863  *  0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data
25864  *       (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally,
25865  *       generating a received data interrupt. Software can then check the data to see if this is an address that
25866  *       should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled
25867  *       normally.
25868  */
25869 #define USART_CTL_ADDRDET(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
25870 
25871 #define USART_CTL_TXDIS_MASK                     (0x40U)
25872 #define USART_CTL_TXDIS_SHIFT                    (6U)
25873 /*! TXDIS - Transmit Disable.
25874  *  0b0..Not disabled. USART transmitter is not disabled.
25875  *  0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This
25876  *       feature can be used to facilitate software flow control.
25877  */
25878 #define USART_CTL_TXDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
25879 
25880 #define USART_CTL_CC_MASK                        (0x100U)
25881 #define USART_CTL_CC_SHIFT                       (8U)
25882 /*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
25883  *  0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to
25884  *       complete a character that is being received.
25885  *  0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on
25886  *       Un_RxD independently from transmission on Un_TXD).
25887  */
25888 #define USART_CTL_CC(x)                          (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
25889 
25890 #define USART_CTL_CLRCCONRX_MASK                 (0x200U)
25891 #define USART_CTL_CLRCCONRX_SHIFT                (9U)
25892 /*! CLRCCONRX - Clear Continuous Clock.
25893  *  0b0..No effect. No effect on the CC bit.
25894  *  0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
25895  */
25896 #define USART_CTL_CLRCCONRX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
25897 
25898 #define USART_CTL_AUTOBAUD_MASK                  (0x10000U)
25899 #define USART_CTL_AUTOBAUD_SHIFT                 (16U)
25900 /*! AUTOBAUD - Autobaud enable.
25901  *  0b0..Disabled. USART is in normal operating mode.
25902  *  0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The
25903  *       first start bit of RX is measured and used the update the BRG register to match the received data rate.
25904  *       AUTOBAUD is cleared once this process is complete, or if there is an AERR.
25905  */
25906 #define USART_CTL_AUTOBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
25907 /*! @} */
25908 
25909 /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
25910 /*! @{ */
25911 
25912 #define USART_STAT_RXIDLE_MASK                   (0x2U)
25913 #define USART_STAT_RXIDLE_SHIFT                  (1U)
25914 /*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of
25915  *    receiving data. When 1, indicates that the receiver is not currently in the process of receiving
25916  *    data.
25917  */
25918 #define USART_STAT_RXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
25919 
25920 #define USART_STAT_TXIDLE_MASK                   (0x8U)
25921 #define USART_STAT_TXIDLE_SHIFT                  (3U)
25922 /*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of
25923  *    sending data.When 1, indicate that the transmitter is not currently in the process of sending
25924  *    data.
25925  */
25926 #define USART_STAT_TXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
25927 
25928 #define USART_STAT_CTS_MASK                      (0x10U)
25929 #define USART_STAT_CTS_SHIFT                     (4U)
25930 /*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the
25931  *    CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode
25932  *    is enabled.
25933  */
25934 #define USART_STAT_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
25935 
25936 #define USART_STAT_DELTACTS_MASK                 (0x20U)
25937 #define USART_STAT_DELTACTS_SHIFT                (5U)
25938 /*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
25939  */
25940 #define USART_STAT_DELTACTS(x)                   (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
25941 
25942 #define USART_STAT_TXDISSTAT_MASK                (0x40U)
25943 #define USART_STAT_TXDISSTAT_SHIFT               (6U)
25944 /*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART
25945  *    transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
25946  */
25947 #define USART_STAT_TXDISSTAT(x)                  (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
25948 
25949 #define USART_STAT_RXBRK_MASK                    (0x400U)
25950 #define USART_STAT_RXBRK_SHIFT                   (10U)
25951 /*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection
25952  *    logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also
25953  *    be set when this condition occurs because the stop bit(s) for the character would be missing.
25954  *    RXBRK is cleared when the Un_RXD pin goes high.
25955  */
25956 #define USART_STAT_RXBRK(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
25957 
25958 #define USART_STAT_DELTARXBRK_MASK               (0x800U)
25959 #define USART_STAT_DELTARXBRK_SHIFT              (11U)
25960 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
25961  */
25962 #define USART_STAT_DELTARXBRK(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
25963 
25964 #define USART_STAT_START_MASK                    (0x1000U)
25965 #define USART_STAT_START_SHIFT                   (12U)
25966 /*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily
25967  *    to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected.
25968  *    Cleared by software.
25969  */
25970 #define USART_STAT_START(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
25971 
25972 #define USART_STAT_FRAMERRINT_MASK               (0x2000U)
25973 #define USART_STAT_FRAMERRINT_SHIFT              (13U)
25974 /*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a
25975  *    missing stop bit at the expected location. This could be an indication of a baud rate or
25976  *    configuration mismatch with the transmitting source.
25977  */
25978 #define USART_STAT_FRAMERRINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
25979 
25980 #define USART_STAT_PARITYERRINT_MASK             (0x4000U)
25981 #define USART_STAT_PARITYERRINT_SHIFT            (14U)
25982 /*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
25983  */
25984 #define USART_STAT_PARITYERRINT(x)               (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
25985 
25986 #define USART_STAT_RXNOISEINT_MASK               (0x8000U)
25987 #define USART_STAT_RXNOISEINT_SHIFT              (15U)
25988 /*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to
25989  *    determine the value of each received data bit, except in synchronous mode. This acts as a
25990  *    noise filter if one sample disagrees. This flag is set when a received data bit contains one
25991  *    disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or
25992  *    loss of synchronization during data reception.
25993  */
25994 #define USART_STAT_RXNOISEINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
25995 
25996 #define USART_STAT_ABERR_MASK                    (0x10000U)
25997 #define USART_STAT_ABERR_SHIFT                   (16U)
25998 /*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the
25999  *    end of the start bit that is being measured, essentially an auto baud time-out.
26000  */
26001 #define USART_STAT_ABERR(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
26002 /*! @} */
26003 
26004 /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
26005 /*! @{ */
26006 
26007 #define USART_INTENSET_TXIDLEEN_MASK             (0x8U)
26008 #define USART_INTENSET_TXIDLEEN_SHIFT            (3U)
26009 /*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
26010  */
26011 #define USART_INTENSET_TXIDLEEN(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
26012 
26013 #define USART_INTENSET_DELTACTSEN_MASK           (0x20U)
26014 #define USART_INTENSET_DELTACTSEN_SHIFT          (5U)
26015 /*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input.
26016  */
26017 #define USART_INTENSET_DELTACTSEN(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
26018 
26019 #define USART_INTENSET_TXDISEN_MASK              (0x40U)
26020 #define USART_INTENSET_TXDISEN_SHIFT             (6U)
26021 /*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by
26022  *    the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
26023  */
26024 #define USART_INTENSET_TXDISEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
26025 
26026 #define USART_INTENSET_DELTARXBRKEN_MASK         (0x800U)
26027 #define USART_INTENSET_DELTARXBRKEN_SHIFT        (11U)
26028 /*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection
26029  *    of a received break condition (break condition asserted or deasserted).
26030  */
26031 #define USART_INTENSET_DELTARXBRKEN(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
26032 
26033 #define USART_INTENSET_STARTEN_MASK              (0x1000U)
26034 #define USART_INTENSET_STARTEN_SHIFT             (12U)
26035 /*! STARTEN - When 1, enables an interrupt when a received start bit has been detected.
26036  */
26037 #define USART_INTENSET_STARTEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
26038 
26039 #define USART_INTENSET_FRAMERREN_MASK            (0x2000U)
26040 #define USART_INTENSET_FRAMERREN_SHIFT           (13U)
26041 /*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected.
26042  */
26043 #define USART_INTENSET_FRAMERREN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
26044 
26045 #define USART_INTENSET_PARITYERREN_MASK          (0x4000U)
26046 #define USART_INTENSET_PARITYERREN_SHIFT         (14U)
26047 /*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected.
26048  */
26049 #define USART_INTENSET_PARITYERREN(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
26050 
26051 #define USART_INTENSET_RXNOISEEN_MASK            (0x8000U)
26052 #define USART_INTENSET_RXNOISEEN_SHIFT           (15U)
26053 /*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354.
26054  */
26055 #define USART_INTENSET_RXNOISEEN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
26056 
26057 #define USART_INTENSET_ABERREN_MASK              (0x10000U)
26058 #define USART_INTENSET_ABERREN_SHIFT             (16U)
26059 /*! ABERREN - When 1, enables an interrupt when an auto baud error occurs.
26060  */
26061 #define USART_INTENSET_ABERREN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
26062 /*! @} */
26063 
26064 /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
26065 /*! @{ */
26066 
26067 #define USART_INTENCLR_TXIDLECLR_MASK            (0x8U)
26068 #define USART_INTENCLR_TXIDLECLR_SHIFT           (3U)
26069 /*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register.
26070  */
26071 #define USART_INTENCLR_TXIDLECLR(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
26072 
26073 #define USART_INTENCLR_DELTACTSCLR_MASK          (0x20U)
26074 #define USART_INTENCLR_DELTACTSCLR_SHIFT         (5U)
26075 /*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register.
26076  */
26077 #define USART_INTENCLR_DELTACTSCLR(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
26078 
26079 #define USART_INTENCLR_TXDISCLR_MASK             (0x40U)
26080 #define USART_INTENCLR_TXDISCLR_SHIFT            (6U)
26081 /*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register.
26082  */
26083 #define USART_INTENCLR_TXDISCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
26084 
26085 #define USART_INTENCLR_DELTARXBRKCLR_MASK        (0x800U)
26086 #define USART_INTENCLR_DELTARXBRKCLR_SHIFT       (11U)
26087 /*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register.
26088  */
26089 #define USART_INTENCLR_DELTARXBRKCLR(x)          (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
26090 
26091 #define USART_INTENCLR_STARTCLR_MASK             (0x1000U)
26092 #define USART_INTENCLR_STARTCLR_SHIFT            (12U)
26093 /*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register.
26094  */
26095 #define USART_INTENCLR_STARTCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
26096 
26097 #define USART_INTENCLR_FRAMERRCLR_MASK           (0x2000U)
26098 #define USART_INTENCLR_FRAMERRCLR_SHIFT          (13U)
26099 /*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
26100  */
26101 #define USART_INTENCLR_FRAMERRCLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
26102 
26103 #define USART_INTENCLR_PARITYERRCLR_MASK         (0x4000U)
26104 #define USART_INTENCLR_PARITYERRCLR_SHIFT        (14U)
26105 /*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
26106  */
26107 #define USART_INTENCLR_PARITYERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
26108 
26109 #define USART_INTENCLR_RXNOISECLR_MASK           (0x8000U)
26110 #define USART_INTENCLR_RXNOISECLR_SHIFT          (15U)
26111 /*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register.
26112  */
26113 #define USART_INTENCLR_RXNOISECLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
26114 
26115 #define USART_INTENCLR_ABERRCLR_MASK             (0x10000U)
26116 #define USART_INTENCLR_ABERRCLR_SHIFT            (16U)
26117 /*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
26118  */
26119 #define USART_INTENCLR_ABERRCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
26120 /*! @} */
26121 
26122 /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
26123 /*! @{ */
26124 
26125 #define USART_BRG_BRGVAL_MASK                    (0xFFFFU)
26126 #define USART_BRG_BRGVAL_SHIFT                   (0U)
26127 /*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on
26128  *    the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is
26129  *    divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART
26130  *    function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
26131  */
26132 #define USART_BRG_BRGVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
26133 /*! @} */
26134 
26135 /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
26136 /*! @{ */
26137 
26138 #define USART_INTSTAT_TXIDLE_MASK                (0x8U)
26139 #define USART_INTSTAT_TXIDLE_SHIFT               (3U)
26140 /*! TXIDLE - Transmitter Idle status.
26141  */
26142 #define USART_INTSTAT_TXIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
26143 
26144 #define USART_INTSTAT_DELTACTS_MASK              (0x20U)
26145 #define USART_INTSTAT_DELTACTS_SHIFT             (5U)
26146 /*! DELTACTS - This bit is set when a change in the state of the CTS input is detected.
26147  */
26148 #define USART_INTSTAT_DELTACTS(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
26149 
26150 #define USART_INTSTAT_TXDISINT_MASK              (0x40U)
26151 #define USART_INTSTAT_TXDISINT_SHIFT             (6U)
26152 /*! TXDISINT - Transmitter Disabled Interrupt flag.
26153  */
26154 #define USART_INTSTAT_TXDISINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
26155 
26156 #define USART_INTSTAT_DELTARXBRK_MASK            (0x800U)
26157 #define USART_INTSTAT_DELTARXBRK_SHIFT           (11U)
26158 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs.
26159  */
26160 #define USART_INTSTAT_DELTARXBRK(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
26161 
26162 #define USART_INTSTAT_START_MASK                 (0x1000U)
26163 #define USART_INTSTAT_START_SHIFT                (12U)
26164 /*! START - This bit is set when a start is detected on the receiver input.
26165  */
26166 #define USART_INTSTAT_START(x)                   (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
26167 
26168 #define USART_INTSTAT_FRAMERRINT_MASK            (0x2000U)
26169 #define USART_INTSTAT_FRAMERRINT_SHIFT           (13U)
26170 /*! FRAMERRINT - Framing Error interrupt flag.
26171  */
26172 #define USART_INTSTAT_FRAMERRINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
26173 
26174 #define USART_INTSTAT_PARITYERRINT_MASK          (0x4000U)
26175 #define USART_INTSTAT_PARITYERRINT_SHIFT         (14U)
26176 /*! PARITYERRINT - Parity Error interrupt flag.
26177  */
26178 #define USART_INTSTAT_PARITYERRINT(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
26179 
26180 #define USART_INTSTAT_RXNOISEINT_MASK            (0x8000U)
26181 #define USART_INTSTAT_RXNOISEINT_SHIFT           (15U)
26182 /*! RXNOISEINT - Received Noise interrupt flag.
26183  */
26184 #define USART_INTSTAT_RXNOISEINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
26185 
26186 #define USART_INTSTAT_ABERRINT_MASK              (0x10000U)
26187 #define USART_INTSTAT_ABERRINT_SHIFT             (16U)
26188 /*! ABERRINT - Auto baud Error Interrupt flag.
26189  */
26190 #define USART_INTSTAT_ABERRINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
26191 /*! @} */
26192 
26193 /*! @name OSR - Oversample selection register for asynchronous communication. */
26194 /*! @{ */
26195 
26196 #define USART_OSR_OSRVAL_MASK                    (0xFU)
26197 #define USART_OSR_OSRVAL_SHIFT                   (0U)
26198 /*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to
26199  *    transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive
26200  *    each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.
26201  */
26202 #define USART_OSR_OSRVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
26203 /*! @} */
26204 
26205 /*! @name ADDR - Address register for automatic address matching. */
26206 /*! @{ */
26207 
26208 #define USART_ADDR_ADDRESS_MASK                  (0xFFU)
26209 #define USART_ADDR_ADDRESS_SHIFT                 (0U)
26210 /*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is
26211  *    enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
26212  */
26213 #define USART_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
26214 /*! @} */
26215 
26216 /*! @name FIFOCFG - FIFO configuration and enable register. */
26217 /*! @{ */
26218 
26219 #define USART_FIFOCFG_ENABLETX_MASK              (0x1U)
26220 #define USART_FIFOCFG_ENABLETX_SHIFT             (0U)
26221 /*! ENABLETX - Enable the transmit FIFO.
26222  *  0b0..The transmit FIFO is not enabled.
26223  *  0b1..The transmit FIFO is enabled.
26224  */
26225 #define USART_FIFOCFG_ENABLETX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
26226 
26227 #define USART_FIFOCFG_ENABLERX_MASK              (0x2U)
26228 #define USART_FIFOCFG_ENABLERX_SHIFT             (1U)
26229 /*! ENABLERX - Enable the receive FIFO.
26230  *  0b0..The receive FIFO is not enabled.
26231  *  0b1..The receive FIFO is enabled.
26232  */
26233 #define USART_FIFOCFG_ENABLERX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
26234 
26235 #define USART_FIFOCFG_SIZE_MASK                  (0x30U)
26236 #define USART_FIFOCFG_SIZE_SHIFT                 (4U)
26237 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
26238  *    entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
26239  */
26240 #define USART_FIFOCFG_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
26241 
26242 #define USART_FIFOCFG_DMATX_MASK                 (0x1000U)
26243 #define USART_FIFOCFG_DMATX_SHIFT                (12U)
26244 /*! DMATX - DMA configuration for transmit.
26245  *  0b0..DMA is not used for the transmit function.
26246  *  0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
26247  */
26248 #define USART_FIFOCFG_DMATX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
26249 
26250 #define USART_FIFOCFG_DMARX_MASK                 (0x2000U)
26251 #define USART_FIFOCFG_DMARX_SHIFT                (13U)
26252 /*! DMARX - DMA configuration for receive.
26253  *  0b0..DMA is not used for the receive function.
26254  *  0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
26255  */
26256 #define USART_FIFOCFG_DMARX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
26257 
26258 #define USART_FIFOCFG_WAKETX_MASK                (0x4000U)
26259 #define USART_FIFOCFG_WAKETX_SHIFT               (14U)
26260 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
26261  *    modes (up to power-down, as long as the peripheral function works in that power mode) without
26262  *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
26263  *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
26264  *    Wake-up control register.
26265  *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
26266  *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
26267  *       FIFOTRIG, even when the TXLVL interrupt is not enabled.
26268  */
26269 #define USART_FIFOCFG_WAKETX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
26270 
26271 #define USART_FIFOCFG_WAKERX_MASK                (0x8000U)
26272 #define USART_FIFOCFG_WAKERX_SHIFT               (15U)
26273 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
26274  *    modes (up to power-down, as long as the peripheral function works in that power mode) without
26275  *    enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
26276  *    CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
26277  *    Wake-up control register.
26278  *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
26279  *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
26280  *       FIFOTRIG, even when the RXLVL interrupt is not enabled.
26281  */
26282 #define USART_FIFOCFG_WAKERX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
26283 
26284 #define USART_FIFOCFG_EMPTYTX_MASK               (0x10000U)
26285 #define USART_FIFOCFG_EMPTYTX_SHIFT              (16U)
26286 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
26287  */
26288 #define USART_FIFOCFG_EMPTYTX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
26289 
26290 #define USART_FIFOCFG_EMPTYRX_MASK               (0x20000U)
26291 #define USART_FIFOCFG_EMPTYRX_SHIFT              (17U)
26292 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
26293  */
26294 #define USART_FIFOCFG_EMPTYRX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
26295 /*! @} */
26296 
26297 /*! @name FIFOSTAT - FIFO status register. */
26298 /*! @{ */
26299 
26300 #define USART_FIFOSTAT_TXERR_MASK                (0x1U)
26301 #define USART_FIFOSTAT_TXERR_SHIFT               (0U)
26302 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
26303  *    caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
26304  *    needed. Cleared by writing a 1 to this bit.
26305  */
26306 #define USART_FIFOSTAT_TXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
26307 
26308 #define USART_FIFOSTAT_RXERR_MASK                (0x2U)
26309 #define USART_FIFOSTAT_RXERR_SHIFT               (1U)
26310 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
26311  *    not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
26312  */
26313 #define USART_FIFOSTAT_RXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
26314 
26315 #define USART_FIFOSTAT_PERINT_MASK               (0x8U)
26316 #define USART_FIFOSTAT_PERINT_SHIFT              (3U)
26317 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
26318  *    an interrupt. The details can be found by reading the peripheral's STAT register.
26319  */
26320 #define USART_FIFOSTAT_PERINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
26321 
26322 #define USART_FIFOSTAT_TXEMPTY_MASK              (0x10U)
26323 #define USART_FIFOSTAT_TXEMPTY_SHIFT             (4U)
26324 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
26325  */
26326 #define USART_FIFOSTAT_TXEMPTY(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
26327 
26328 #define USART_FIFOSTAT_TXNOTFULL_MASK            (0x20U)
26329 #define USART_FIFOSTAT_TXNOTFULL_SHIFT           (5U)
26330 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
26331  *    written. When 0, the transmit FIFO is full and another write would cause it to overflow.
26332  */
26333 #define USART_FIFOSTAT_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
26334 
26335 #define USART_FIFOSTAT_RXNOTEMPTY_MASK           (0x40U)
26336 #define USART_FIFOSTAT_RXNOTEMPTY_SHIFT          (6U)
26337 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
26338  */
26339 #define USART_FIFOSTAT_RXNOTEMPTY(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
26340 
26341 #define USART_FIFOSTAT_RXFULL_MASK               (0x80U)
26342 #define USART_FIFOSTAT_RXFULL_SHIFT              (7U)
26343 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
26344  *    prevent the peripheral from causing an overflow.
26345  */
26346 #define USART_FIFOSTAT_RXFULL(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
26347 
26348 #define USART_FIFOSTAT_TXLVL_MASK                (0x1F00U)
26349 #define USART_FIFOSTAT_TXLVL_SHIFT               (8U)
26350 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
26351  *    and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
26352  *    the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
26353  *    0.
26354  */
26355 #define USART_FIFOSTAT_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
26356 
26357 #define USART_FIFOSTAT_RXLVL_MASK                (0x1F0000U)
26358 #define USART_FIFOSTAT_RXLVL_SHIFT               (16U)
26359 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
26360  *    RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
26361  *    point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
26362  *    1.
26363  */
26364 #define USART_FIFOSTAT_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
26365 /*! @} */
26366 
26367 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
26368 /*! @{ */
26369 
26370 #define USART_FIFOTRIG_TXLVLENA_MASK             (0x1U)
26371 #define USART_FIFOTRIG_TXLVLENA_SHIFT            (0U)
26372 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
26373  *    in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
26374  *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
26375  *  0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
26376  */
26377 #define USART_FIFOTRIG_TXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
26378 
26379 #define USART_FIFOTRIG_RXLVLENA_MASK             (0x2U)
26380 #define USART_FIFOTRIG_RXLVLENA_SHIFT            (1U)
26381 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
26382  *    in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
26383  *  0b0..Receive FIFO level does not generate a FIFO level trigger.
26384  *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
26385  */
26386 #define USART_FIFOTRIG_RXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
26387 
26388 #define USART_FIFOTRIG_TXLVL_MASK                (0xF00U)
26389 #define USART_FIFOTRIG_TXLVL_SHIFT               (8U)
26390 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
26391  *    to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
26392  *    the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
26393  *    becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
26394  *    FIFO level decreases to 15 entries (is no longer full).
26395  */
26396 #define USART_FIFOTRIG_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
26397 
26398 #define USART_FIFOTRIG_RXLVL_MASK                (0xF0000U)
26399 #define USART_FIFOTRIG_RXLVL_SHIFT               (16U)
26400 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
26401  *    is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
26402  *    can wake up the device just enough to perform DMA, then return to the reduced power mode. See
26403  *    Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
26404  *    longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
26405  *    FIFO has received 16 entries (has become full).
26406  */
26407 #define USART_FIFOTRIG_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
26408 /*! @} */
26409 
26410 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
26411 /*! @{ */
26412 
26413 #define USART_FIFOINTENSET_TXERR_MASK            (0x1U)
26414 #define USART_FIFOINTENSET_TXERR_SHIFT           (0U)
26415 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
26416  *  0b0..No interrupt will be generated for a transmit error.
26417  *  0b1..An interrupt will be generated when a transmit error occurs.
26418  */
26419 #define USART_FIFOINTENSET_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
26420 
26421 #define USART_FIFOINTENSET_RXERR_MASK            (0x2U)
26422 #define USART_FIFOINTENSET_RXERR_SHIFT           (1U)
26423 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
26424  *  0b0..No interrupt will be generated for a receive error.
26425  *  0b1..An interrupt will be generated when a receive error occurs.
26426  */
26427 #define USART_FIFOINTENSET_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
26428 
26429 #define USART_FIFOINTENSET_TXLVL_MASK            (0x4U)
26430 #define USART_FIFOINTENSET_TXLVL_SHIFT           (2U)
26431 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
26432  *    specified by the TXLVL field in the FIFOTRIG register.
26433  *  0b0..No interrupt will be generated based on the TX FIFO level.
26434  *  0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
26435  *       to the level specified by TXLVL in the FIFOTRIG register.
26436  */
26437 #define USART_FIFOINTENSET_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
26438 
26439 #define USART_FIFOINTENSET_RXLVL_MASK            (0x8U)
26440 #define USART_FIFOINTENSET_RXLVL_SHIFT           (3U)
26441 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
26442  *    specified by the TXLVL field in the FIFOTRIG register.
26443  *  0b0..No interrupt will be generated based on the RX FIFO level.
26444  *  0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
26445  *       increases to the level specified by RXLVL in the FIFOTRIG register.
26446  */
26447 #define USART_FIFOINTENSET_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
26448 /*! @} */
26449 
26450 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
26451 /*! @{ */
26452 
26453 #define USART_FIFOINTENCLR_TXERR_MASK            (0x1U)
26454 #define USART_FIFOINTENCLR_TXERR_SHIFT           (0U)
26455 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
26456  */
26457 #define USART_FIFOINTENCLR_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
26458 
26459 #define USART_FIFOINTENCLR_RXERR_MASK            (0x2U)
26460 #define USART_FIFOINTENCLR_RXERR_SHIFT           (1U)
26461 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
26462  */
26463 #define USART_FIFOINTENCLR_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
26464 
26465 #define USART_FIFOINTENCLR_TXLVL_MASK            (0x4U)
26466 #define USART_FIFOINTENCLR_TXLVL_SHIFT           (2U)
26467 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
26468  */
26469 #define USART_FIFOINTENCLR_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
26470 
26471 #define USART_FIFOINTENCLR_RXLVL_MASK            (0x8U)
26472 #define USART_FIFOINTENCLR_RXLVL_SHIFT           (3U)
26473 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
26474  */
26475 #define USART_FIFOINTENCLR_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
26476 /*! @} */
26477 
26478 /*! @name FIFOINTSTAT - FIFO interrupt status register. */
26479 /*! @{ */
26480 
26481 #define USART_FIFOINTSTAT_TXERR_MASK             (0x1U)
26482 #define USART_FIFOINTSTAT_TXERR_SHIFT            (0U)
26483 /*! TXERR - TX FIFO error.
26484  */
26485 #define USART_FIFOINTSTAT_TXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
26486 
26487 #define USART_FIFOINTSTAT_RXERR_MASK             (0x2U)
26488 #define USART_FIFOINTSTAT_RXERR_SHIFT            (1U)
26489 /*! RXERR - RX FIFO error.
26490  */
26491 #define USART_FIFOINTSTAT_RXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
26492 
26493 #define USART_FIFOINTSTAT_TXLVL_MASK             (0x4U)
26494 #define USART_FIFOINTSTAT_TXLVL_SHIFT            (2U)
26495 /*! TXLVL - Transmit FIFO level interrupt.
26496  */
26497 #define USART_FIFOINTSTAT_TXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
26498 
26499 #define USART_FIFOINTSTAT_RXLVL_MASK             (0x8U)
26500 #define USART_FIFOINTSTAT_RXLVL_SHIFT            (3U)
26501 /*! RXLVL - Receive FIFO level interrupt.
26502  */
26503 #define USART_FIFOINTSTAT_RXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
26504 
26505 #define USART_FIFOINTSTAT_PERINT_MASK            (0x10U)
26506 #define USART_FIFOINTSTAT_PERINT_SHIFT           (4U)
26507 /*! PERINT - Peripheral interrupt.
26508  */
26509 #define USART_FIFOINTSTAT_PERINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
26510 /*! @} */
26511 
26512 /*! @name FIFOWR - FIFO write data. */
26513 /*! @{ */
26514 
26515 #define USART_FIFOWR_TXDATA_MASK                 (0x1FFU)
26516 #define USART_FIFOWR_TXDATA_SHIFT                (0U)
26517 /*! TXDATA - Transmit data to the FIFO.
26518  */
26519 #define USART_FIFOWR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
26520 /*! @} */
26521 
26522 /*! @name FIFORD - FIFO read data. */
26523 /*! @{ */
26524 
26525 #define USART_FIFORD_RXDATA_MASK                 (0x1FFU)
26526 #define USART_FIFORD_RXDATA_SHIFT                (0U)
26527 /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
26528  */
26529 #define USART_FIFORD_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
26530 
26531 #define USART_FIFORD_FRAMERR_MASK                (0x2000U)
26532 #define USART_FIFORD_FRAMERR_SHIFT               (13U)
26533 /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
26534  *    with from the FIFO, and indicates that the character was received with a missing stop bit at
26535  *    the expected location. This could be an indication of a baud rate or configuration mismatch
26536  *    with the transmitting source.
26537  */
26538 #define USART_FIFORD_FRAMERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
26539 
26540 #define USART_FIFORD_PARITYERR_MASK              (0x4000U)
26541 #define USART_FIFORD_PARITYERR_SHIFT             (14U)
26542 /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
26543  *    with from the FIFO. This bit will be set when a parity error is detected in a received
26544  *    character.
26545  */
26546 #define USART_FIFORD_PARITYERR(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
26547 
26548 #define USART_FIFORD_RXNOISE_MASK                (0x8000U)
26549 #define USART_FIFORD_RXNOISE_SHIFT               (15U)
26550 /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
26551  */
26552 #define USART_FIFORD_RXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
26553 /*! @} */
26554 
26555 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
26556 /*! @{ */
26557 
26558 #define USART_FIFORDNOPOP_RXDATA_MASK            (0x1FFU)
26559 #define USART_FIFORDNOPOP_RXDATA_SHIFT           (0U)
26560 /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
26561  */
26562 #define USART_FIFORDNOPOP_RXDATA(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
26563 
26564 #define USART_FIFORDNOPOP_FRAMERR_MASK           (0x2000U)
26565 #define USART_FIFORDNOPOP_FRAMERR_SHIFT          (13U)
26566 /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
26567  *    with from the FIFO, and indicates that the character was received with a missing stop bit at
26568  *    the expected location. This could be an indication of a baud rate or configuration mismatch
26569  *    with the transmitting source.
26570  */
26571 #define USART_FIFORDNOPOP_FRAMERR(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
26572 
26573 #define USART_FIFORDNOPOP_PARITYERR_MASK         (0x4000U)
26574 #define USART_FIFORDNOPOP_PARITYERR_SHIFT        (14U)
26575 /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
26576  *    with from the FIFO. This bit will be set when a parity error is detected in a received
26577  *    character.
26578  */
26579 #define USART_FIFORDNOPOP_PARITYERR(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
26580 
26581 #define USART_FIFORDNOPOP_RXNOISE_MASK           (0x8000U)
26582 #define USART_FIFORDNOPOP_RXNOISE_SHIFT          (15U)
26583 /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
26584  */
26585 #define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
26586 /*! @} */
26587 
26588 /*! @name FIFOSIZE - FIFO size register */
26589 /*! @{ */
26590 
26591 #define USART_FIFOSIZE_FIFOSIZE_MASK             (0x1FU)
26592 #define USART_FIFOSIZE_FIFOSIZE_SHIFT            (0U)
26593 /*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries.
26594  */
26595 #define USART_FIFOSIZE_FIFOSIZE(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK)
26596 /*! @} */
26597 
26598 /*! @name ID - Peripheral identification register. */
26599 /*! @{ */
26600 
26601 #define USART_ID_APERTURE_MASK                   (0xFFU)
26602 #define USART_ID_APERTURE_SHIFT                  (0U)
26603 /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
26604  */
26605 #define USART_ID_APERTURE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
26606 
26607 #define USART_ID_MINOR_REV_MASK                  (0xF00U)
26608 #define USART_ID_MINOR_REV_SHIFT                 (8U)
26609 /*! MINOR_REV - Minor revision of module implementation.
26610  */
26611 #define USART_ID_MINOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
26612 
26613 #define USART_ID_MAJOR_REV_MASK                  (0xF000U)
26614 #define USART_ID_MAJOR_REV_SHIFT                 (12U)
26615 /*! MAJOR_REV - Major revision of module implementation.
26616  */
26617 #define USART_ID_MAJOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
26618 
26619 #define USART_ID_ID_MASK                         (0xFFFF0000U)
26620 #define USART_ID_ID_SHIFT                        (16U)
26621 /*! ID - Module identifier for the selected function.
26622  */
26623 #define USART_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
26624 /*! @} */
26625 
26626 
26627 /*!
26628  * @}
26629  */ /* end of group USART_Register_Masks */
26630 
26631 
26632 /* USART - Peripheral instance base addresses */
26633 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
26634   /** Peripheral USART0 base address */
26635   #define USART0_BASE                              (0x50086000u)
26636   /** Peripheral USART0 base address */
26637   #define USART0_BASE_NS                           (0x40086000u)
26638   /** Peripheral USART0 base pointer */
26639   #define USART0                                   ((USART_Type *)USART0_BASE)
26640   /** Peripheral USART0 base pointer */
26641   #define USART0_NS                                ((USART_Type *)USART0_BASE_NS)
26642   /** Peripheral USART1 base address */
26643   #define USART1_BASE                              (0x50087000u)
26644   /** Peripheral USART1 base address */
26645   #define USART1_BASE_NS                           (0x40087000u)
26646   /** Peripheral USART1 base pointer */
26647   #define USART1                                   ((USART_Type *)USART1_BASE)
26648   /** Peripheral USART1 base pointer */
26649   #define USART1_NS                                ((USART_Type *)USART1_BASE_NS)
26650   /** Peripheral USART2 base address */
26651   #define USART2_BASE                              (0x50088000u)
26652   /** Peripheral USART2 base address */
26653   #define USART2_BASE_NS                           (0x40088000u)
26654   /** Peripheral USART2 base pointer */
26655   #define USART2                                   ((USART_Type *)USART2_BASE)
26656   /** Peripheral USART2 base pointer */
26657   #define USART2_NS                                ((USART_Type *)USART2_BASE_NS)
26658   /** Peripheral USART3 base address */
26659   #define USART3_BASE                              (0x50089000u)
26660   /** Peripheral USART3 base address */
26661   #define USART3_BASE_NS                           (0x40089000u)
26662   /** Peripheral USART3 base pointer */
26663   #define USART3                                   ((USART_Type *)USART3_BASE)
26664   /** Peripheral USART3 base pointer */
26665   #define USART3_NS                                ((USART_Type *)USART3_BASE_NS)
26666   /** Peripheral USART4 base address */
26667   #define USART4_BASE                              (0x5008A000u)
26668   /** Peripheral USART4 base address */
26669   #define USART4_BASE_NS                           (0x4008A000u)
26670   /** Peripheral USART4 base pointer */
26671   #define USART4                                   ((USART_Type *)USART4_BASE)
26672   /** Peripheral USART4 base pointer */
26673   #define USART4_NS                                ((USART_Type *)USART4_BASE_NS)
26674   /** Peripheral USART5 base address */
26675   #define USART5_BASE                              (0x50096000u)
26676   /** Peripheral USART5 base address */
26677   #define USART5_BASE_NS                           (0x40096000u)
26678   /** Peripheral USART5 base pointer */
26679   #define USART5                                   ((USART_Type *)USART5_BASE)
26680   /** Peripheral USART5 base pointer */
26681   #define USART5_NS                                ((USART_Type *)USART5_BASE_NS)
26682   /** Peripheral USART6 base address */
26683   #define USART6_BASE                              (0x50097000u)
26684   /** Peripheral USART6 base address */
26685   #define USART6_BASE_NS                           (0x40097000u)
26686   /** Peripheral USART6 base pointer */
26687   #define USART6                                   ((USART_Type *)USART6_BASE)
26688   /** Peripheral USART6 base pointer */
26689   #define USART6_NS                                ((USART_Type *)USART6_BASE_NS)
26690   /** Peripheral USART7 base address */
26691   #define USART7_BASE                              (0x50098000u)
26692   /** Peripheral USART7 base address */
26693   #define USART7_BASE_NS                           (0x40098000u)
26694   /** Peripheral USART7 base pointer */
26695   #define USART7                                   ((USART_Type *)USART7_BASE)
26696   /** Peripheral USART7 base pointer */
26697   #define USART7_NS                                ((USART_Type *)USART7_BASE_NS)
26698   /** Array initializer of USART peripheral base addresses */
26699   #define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }
26700   /** Array initializer of USART peripheral base pointers */
26701   #define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }
26702   /** Array initializer of USART peripheral base addresses */
26703   #define USART_BASE_ADDRS_NS                      { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS }
26704   /** Array initializer of USART peripheral base pointers */
26705   #define USART_BASE_PTRS_NS                       { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS }
26706 #else
26707   /** Peripheral USART0 base address */
26708   #define USART0_BASE                              (0x40086000u)
26709   /** Peripheral USART0 base pointer */
26710   #define USART0                                   ((USART_Type *)USART0_BASE)
26711   /** Peripheral USART1 base address */
26712   #define USART1_BASE                              (0x40087000u)
26713   /** Peripheral USART1 base pointer */
26714   #define USART1                                   ((USART_Type *)USART1_BASE)
26715   /** Peripheral USART2 base address */
26716   #define USART2_BASE                              (0x40088000u)
26717   /** Peripheral USART2 base pointer */
26718   #define USART2                                   ((USART_Type *)USART2_BASE)
26719   /** Peripheral USART3 base address */
26720   #define USART3_BASE                              (0x40089000u)
26721   /** Peripheral USART3 base pointer */
26722   #define USART3                                   ((USART_Type *)USART3_BASE)
26723   /** Peripheral USART4 base address */
26724   #define USART4_BASE                              (0x4008A000u)
26725   /** Peripheral USART4 base pointer */
26726   #define USART4                                   ((USART_Type *)USART4_BASE)
26727   /** Peripheral USART5 base address */
26728   #define USART5_BASE                              (0x40096000u)
26729   /** Peripheral USART5 base pointer */
26730   #define USART5                                   ((USART_Type *)USART5_BASE)
26731   /** Peripheral USART6 base address */
26732   #define USART6_BASE                              (0x40097000u)
26733   /** Peripheral USART6 base pointer */
26734   #define USART6                                   ((USART_Type *)USART6_BASE)
26735   /** Peripheral USART7 base address */
26736   #define USART7_BASE                              (0x40098000u)
26737   /** Peripheral USART7 base pointer */
26738   #define USART7                                   ((USART_Type *)USART7_BASE)
26739   /** Array initializer of USART peripheral base addresses */
26740   #define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }
26741   /** Array initializer of USART peripheral base pointers */
26742   #define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }
26743 #endif
26744 /** Interrupt vectors for the USART peripheral type */
26745 #define USART_IRQS                               { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
26746 
26747 /*!
26748  * @}
26749  */ /* end of group USART_Peripheral_Access_Layer */
26750 
26751 
26752 /* ----------------------------------------------------------------------------
26753    -- USB Peripheral Access Layer
26754    ---------------------------------------------------------------------------- */
26755 
26756 /*!
26757  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
26758  * @{
26759  */
26760 
26761 /** USB - Register Layout Typedef */
26762 typedef struct {
26763   __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
26764   __IO uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
26765   __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
26766   __IO uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
26767   __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
26768   __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
26769   __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
26770   __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
26771   __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
26772   __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
26773   __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
26774        uint8_t RESERVED_0[8];
26775   __IO uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
26776 } USB_Type;
26777 
26778 /* ----------------------------------------------------------------------------
26779    -- USB Register Masks
26780    ---------------------------------------------------------------------------- */
26781 
26782 /*!
26783  * @addtogroup USB_Register_Masks USB Register Masks
26784  * @{
26785  */
26786 
26787 /*! @name DEVCMDSTAT - USB Device Command/Status register */
26788 /*! @{ */
26789 
26790 #define USB_DEVCMDSTAT_DEV_ADDR_MASK             (0x7FU)
26791 #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT            (0U)
26792 /*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit
26793  *    is set, the device will respond on packets for function address DEV_ADDR. When receiving a
26794  *    SetAddress Control Request from the USB host, software must program the new address before
26795  *    completing the status phase of the SetAddress Control Request.
26796  */
26797 #define USB_DEVCMDSTAT_DEV_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
26798 
26799 #define USB_DEVCMDSTAT_DEV_EN_MASK               (0x80U)
26800 #define USB_DEVCMDSTAT_DEV_EN_SHIFT              (7U)
26801 /*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.
26802  */
26803 #define USB_DEVCMDSTAT_DEV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
26804 
26805 #define USB_DEVCMDSTAT_SETUP_MASK                (0x100U)
26806 #define USB_DEVCMDSTAT_SETUP_SHIFT               (8U)
26807 /*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this
26808  *    bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW
26809  *    must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the
26810  *    CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.
26811  */
26812 #define USB_DEVCMDSTAT_SETUP(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
26813 
26814 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK        (0x200U)
26815 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT       (9U)
26816 /*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:
26817  *  0b0..USB_NEEDCLK has normal function.
26818  *  0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.
26819  */
26820 #define USB_DEVCMDSTAT_FORCE_NEEDCLK(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
26821 
26822 #define USB_DEVCMDSTAT_LPM_SUP_MASK              (0x800U)
26823 #define USB_DEVCMDSTAT_LPM_SUP_SHIFT             (11U)
26824 /*! LPM_SUP - LPM Supported:
26825  *  0b0..LPM not supported.
26826  *  0b1..LPM supported.
26827  */
26828 #define USB_DEVCMDSTAT_LPM_SUP(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
26829 
26830 #define USB_DEVCMDSTAT_INTONNAK_AO_MASK          (0x1000U)
26831 #define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT         (12U)
26832 /*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP
26833  *  0b0..Only acknowledged packets generate an interrupt
26834  *  0b1..Both acknowledged and NAKed packets generate interrupts.
26835  */
26836 #define USB_DEVCMDSTAT_INTONNAK_AO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
26837 
26838 #define USB_DEVCMDSTAT_INTONNAK_AI_MASK          (0x2000U)
26839 #define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT         (13U)
26840 /*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP
26841  *  0b0..Only acknowledged packets generate an interrupt
26842  *  0b1..Both acknowledged and NAKed packets generate interrupts.
26843  */
26844 #define USB_DEVCMDSTAT_INTONNAK_AI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
26845 
26846 #define USB_DEVCMDSTAT_INTONNAK_CO_MASK          (0x4000U)
26847 #define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT         (14U)
26848 /*! INTONNAK_CO - Interrupt on NAK for control OUT EP
26849  *  0b0..Only acknowledged packets generate an interrupt
26850  *  0b1..Both acknowledged and NAKed packets generate interrupts.
26851  */
26852 #define USB_DEVCMDSTAT_INTONNAK_CO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
26853 
26854 #define USB_DEVCMDSTAT_INTONNAK_CI_MASK          (0x8000U)
26855 #define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT         (15U)
26856 /*! INTONNAK_CI - Interrupt on NAK for control IN EP
26857  *  0b0..Only acknowledged packets generate an interrupt
26858  *  0b1..Both acknowledged and NAKed packets generate interrupts.
26859  */
26860 #define USB_DEVCMDSTAT_INTONNAK_CI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
26861 
26862 #define USB_DEVCMDSTAT_DCON_MASK                 (0x10000U)
26863 #define USB_DEVCMDSTAT_DCON_SHIFT                (16U)
26864 /*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device
26865  *    must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and
26866  *    the VBUSDEBOUNCED bit is one.
26867  */
26868 #define USB_DEVCMDSTAT_DCON(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
26869 
26870 #define USB_DEVCMDSTAT_DSUS_MASK                 (0x20000U)
26871 #define USB_DEVCMDSTAT_DSUS_SHIFT                (17U)
26872 /*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set
26873  *    to 1 when the device hasn't seen any activity on its upstream port for more than 3
26874  *    milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and
26875  *    the software writes a 0 to it, the device will generate a remote wake-up. This will only happen
26876  *    when the device is connected (Connect bit = 1). When the device is not connected or not
26877  *    suspended, a writing a 0 has no effect. Writing a 1 never has an effect.
26878  */
26879 #define USB_DEVCMDSTAT_DSUS(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
26880 
26881 #define USB_DEVCMDSTAT_LPM_SUS_MASK              (0x80000U)
26882 #define USB_DEVCMDSTAT_LPM_SUS_SHIFT             (19U)
26883 /*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is
26884  *    set to 1 by HW when the device has acknowledged the LPM request from the USB host and the
26885  *    Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend
26886  *    bit = 1) and the software writes a zero to this bit, the device will generate a remote
26887  *    walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this
26888  *    bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the
26889  *    LPM_SUPP bit is equal to one.
26890  */
26891 #define USB_DEVCMDSTAT_LPM_SUS(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
26892 
26893 #define USB_DEVCMDSTAT_LPM_REWP_MASK             (0x100000U)
26894 #define USB_DEVCMDSTAT_LPM_REWP_SHIFT            (20U)
26895 /*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake
26896  *    bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the
26897  *    host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset
26898  *    is received. Software can use this bit to check if the remote wake-up feature is enabled by the
26899  *    host for the LPM transaction.
26900  */
26901 #define USB_DEVCMDSTAT_LPM_REWP(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
26902 
26903 #define USB_DEVCMDSTAT_DCON_C_MASK               (0x1000000U)
26904 #define USB_DEVCMDSTAT_DCON_C_SHIFT              (24U)
26905 /*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up
26906  *    resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.
26907  */
26908 #define USB_DEVCMDSTAT_DCON_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
26909 
26910 #define USB_DEVCMDSTAT_DSUS_C_MASK               (0x2000000U)
26911 #define USB_DEVCMDSTAT_DSUS_C_SHIFT              (25U)
26912 /*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit
26913  *    toggles. The suspend bit can toggle because: - The device goes in the suspended state - The
26914  *    device is disconnected - The device receives resume signaling on its upstream port. The bit is
26915  *    reset by writing a one to it.
26916  */
26917 #define USB_DEVCMDSTAT_DSUS_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
26918 
26919 #define USB_DEVCMDSTAT_DRES_C_MASK               (0x4000000U)
26920 #define USB_DEVCMDSTAT_DRES_C_SHIFT              (26U)
26921 /*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On
26922  *    a bus reset the device will automatically go to the default state (unconfigured and responding
26923  *    to address 0). The bit is reset by writing a one to it.
26924  */
26925 #define USB_DEVCMDSTAT_DRES_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
26926 
26927 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK        (0x10000000U)
26928 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT       (28U)
26929 /*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when
26930  *    Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and
26931  *    the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.
26932  */
26933 #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
26934 /*! @} */
26935 
26936 /*! @name INFO - USB Info register */
26937 /*! @{ */
26938 
26939 #define USB_INFO_FRAME_NR_MASK                   (0x7FFU)
26940 #define USB_INFO_FRAME_NR_SHIFT                  (0U)
26941 /*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF.
26942  *    In case no SOF was received by the device at the beginning of a frame, the frame number
26943  *    returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC
26944  *    error, the frame number returned will be the corrupted frame number as received by the device.
26945  */
26946 #define USB_INFO_FRAME_NR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
26947 
26948 #define USB_INFO_ERR_CODE_MASK                   (0x7800U)
26949 #define USB_INFO_ERR_CODE_SHIFT                  (11U)
26950 /*! ERR_CODE - The error code which last occurred:
26951  *  0b0000..No error
26952  *  0b0001..PID encoding error
26953  *  0b0010..PID unknown
26954  *  0b0011..Packet unexpected
26955  *  0b0100..Token CRC error
26956  *  0b0101..Data CRC error
26957  *  0b0110..Time out
26958  *  0b0111..Babble
26959  *  0b1000..Truncated EOP
26960  *  0b1001..Sent/Received NAK
26961  *  0b1010..Sent Stall
26962  *  0b1011..Overrun
26963  *  0b1100..Sent empty packet
26964  *  0b1101..Bitstuff error
26965  *  0b1110..Sync error
26966  *  0b1111..Wrong data toggle
26967  */
26968 #define USB_INFO_ERR_CODE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
26969 
26970 #define USB_INFO_MINREV_MASK                     (0xFF0000U)
26971 #define USB_INFO_MINREV_SHIFT                    (16U)
26972 /*! MINREV - Minor Revision.
26973  */
26974 #define USB_INFO_MINREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
26975 
26976 #define USB_INFO_MAJREV_MASK                     (0xFF000000U)
26977 #define USB_INFO_MAJREV_SHIFT                    (24U)
26978 /*! MAJREV - Major Revision.
26979  */
26980 #define USB_INFO_MAJREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
26981 /*! @} */
26982 
26983 /*! @name EPLISTSTART - USB EP Command/Status List start address */
26984 /*! @{ */
26985 
26986 #define USB_EPLISTSTART_EP_LIST_MASK             (0xFFFFFF00U)
26987 #define USB_EPLISTSTART_EP_LIST_SHIFT            (8U)
26988 /*! EP_LIST - Start address of the USB EP Command/Status List.
26989  */
26990 #define USB_EPLISTSTART_EP_LIST(x)               (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
26991 /*! @} */
26992 
26993 /*! @name DATABUFSTART - USB Data buffer start address */
26994 /*! @{ */
26995 
26996 #define USB_DATABUFSTART_DA_BUF_MASK             (0xFFC00000U)
26997 #define USB_DATABUFSTART_DA_BUF_SHIFT            (22U)
26998 /*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located.
26999  */
27000 #define USB_DATABUFSTART_DA_BUF(x)               (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
27001 /*! @} */
27002 
27003 /*! @name LPM - USB Link Power Management register */
27004 /*! @{ */
27005 
27006 #define USB_LPM_HIRD_HW_MASK                     (0xFU)
27007 #define USB_LPM_HIRD_HW_SHIFT                    (0U)
27008 /*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token
27009  */
27010 #define USB_LPM_HIRD_HW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
27011 
27012 #define USB_LPM_HIRD_SW_MASK                     (0xF0U)
27013 #define USB_LPM_HIRD_SW_SHIFT                    (4U)
27014 /*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB
27015  *    device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.
27016  */
27017 #define USB_LPM_HIRD_SW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
27018 
27019 #define USB_LPM_DATA_PENDING_MASK                (0x100U)
27020 #define USB_LPM_DATA_PENDING_SHIFT               (8U)
27021 /*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
27022  *    return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and
27023  *    this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has
27024  *    still data pending and LPM is supported, it must set this bit to 1.
27025  */
27026 #define USB_LPM_DATA_PENDING(x)                  (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
27027 /*! @} */
27028 
27029 /*! @name EPSKIP - USB Endpoint skip */
27030 /*! @{ */
27031 
27032 #define USB_EPSKIP_SKIP_MASK                     (0x3FFU)
27033 #define USB_EPSKIP_SKIP_SHIFT                    (0U)
27034 /*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
27035  *    deactivate the buffer assigned to this endpoint and return control back to software. When HW has
27036  *    deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An
27037  *    interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering,
27038  *    HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.
27039  */
27040 #define USB_EPSKIP_SKIP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
27041 /*! @} */
27042 
27043 /*! @name EPINUSE - USB Endpoint Buffer in use */
27044 /*! @{ */
27045 
27046 #define USB_EPINUSE_BUF_MASK                     (0x3FCU)
27047 #define USB_EPINUSE_BUF_SHIFT                    (2U)
27048 /*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer
27049  *    0. 1: HW is accessing buffer 1.
27050  */
27051 #define USB_EPINUSE_BUF(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
27052 /*! @} */
27053 
27054 /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
27055 /*! @{ */
27056 
27057 #define USB_EPBUFCFG_BUF_SB_MASK                 (0x3FCU)
27058 #define USB_EPBUFCFG_BUF_SB_SHIFT                (2U)
27059 /*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1:
27060  *    Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding
27061  *    EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle
27062  *    the EPINUSE bit when it clears the Active bit for the buffer.
27063  */
27064 #define USB_EPBUFCFG_BUF_SB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
27065 /*! @} */
27066 
27067 /*! @name INTSTAT - USB interrupt status register */
27068 /*! @{ */
27069 
27070 #define USB_INTSTAT_EP0OUT_MASK                  (0x1U)
27071 #define USB_INTSTAT_EP0OUT_SHIFT                 (0U)
27072 /*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set
27073  *    if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is
27074  *    successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a
27075  *    NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a
27076  *    one to it.
27077  */
27078 #define USB_INTSTAT_EP0OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
27079 
27080 #define USB_INTSTAT_EP0IN_MASK                   (0x2U)
27081 #define USB_INTSTAT_EP0IN_SHIFT                  (1U)
27082 /*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if
27083  *    NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this
27084  *    bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can
27085  *    clear this bit by writing a one to it.
27086  */
27087 #define USB_INTSTAT_EP0IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
27088 
27089 #define USB_INTSTAT_EP1OUT_MASK                  (0x4U)
27090 #define USB_INTSTAT_EP1OUT_SHIFT                 (2U)
27091 /*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the
27092  *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
27093  *    transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
27094  *    set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by
27095  *    writing a one to it.
27096  */
27097 #define USB_INTSTAT_EP1OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
27098 
27099 #define USB_INTSTAT_EP1IN_MASK                   (0x8U)
27100 #define USB_INTSTAT_EP1IN_SHIFT                  (3U)
27101 /*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the
27102  *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
27103  *    to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
27104  *    set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing
27105  *    a one to it.
27106  */
27107 #define USB_INTSTAT_EP1IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
27108 
27109 #define USB_INTSTAT_EP2OUT_MASK                  (0x10U)
27110 #define USB_INTSTAT_EP2OUT_SHIFT                 (4U)
27111 /*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the
27112  *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
27113  *    transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
27114  *    set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by
27115  *    writing a one to it.
27116  */
27117 #define USB_INTSTAT_EP2OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
27118 
27119 #define USB_INTSTAT_EP2IN_MASK                   (0x20U)
27120 #define USB_INTSTAT_EP2IN_SHIFT                  (5U)
27121 /*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the
27122  *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
27123  *    to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
27124  *    set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing
27125  *    a one to it.
27126  */
27127 #define USB_INTSTAT_EP2IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
27128 
27129 #define USB_INTSTAT_EP3OUT_MASK                  (0x40U)
27130 #define USB_INTSTAT_EP3OUT_SHIFT                 (6U)
27131 /*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the
27132  *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
27133  *    transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
27134  *    set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by
27135  *    writing a one to it.
27136  */
27137 #define USB_INTSTAT_EP3OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
27138 
27139 #define USB_INTSTAT_EP3IN_MASK                   (0x80U)
27140 #define USB_INTSTAT_EP3IN_SHIFT                  (7U)
27141 /*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the
27142  *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
27143  *    to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
27144  *    set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing
27145  *    a one to it.
27146  */
27147 #define USB_INTSTAT_EP3IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
27148 
27149 #define USB_INTSTAT_EP4OUT_MASK                  (0x100U)
27150 #define USB_INTSTAT_EP4OUT_SHIFT                 (8U)
27151 /*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the
27152  *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
27153  *    transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
27154  *    set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by
27155  *    writing a one to it.
27156  */
27157 #define USB_INTSTAT_EP4OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
27158 
27159 #define USB_INTSTAT_EP4IN_MASK                   (0x200U)
27160 #define USB_INTSTAT_EP4IN_SHIFT                  (9U)
27161 /*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the
27162  *    corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
27163  *    to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
27164  *    set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing
27165  *    a one to it.
27166  */
27167 #define USB_INTSTAT_EP4IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
27168 
27169 #define USB_INTSTAT_FRAME_INT_MASK               (0x40000000U)
27170 #define USB_INTSTAT_FRAME_INT_SHIFT              (30U)
27171 /*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit
27172  *    and the DCON bit are set. This bit can be used by software when handling isochronous
27173  *    endpoints. Software can clear this bit by writing a one to it.
27174  */
27175 #define USB_INTSTAT_FRAME_INT(x)                 (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
27176 
27177 #define USB_INTSTAT_DEV_INT_MASK                 (0x80000000U)
27178 #define USB_INTSTAT_DEV_INT_SHIFT                (31U)
27179 /*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device
27180  *    Status Change register are set. Software can clear this bit by writing a one to it.
27181  */
27182 #define USB_INTSTAT_DEV_INT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
27183 /*! @} */
27184 
27185 /*! @name INTEN - USB interrupt enable register */
27186 /*! @{ */
27187 
27188 #define USB_INTEN_EP_INT_EN_MASK                 (0x3FFU)
27189 #define USB_INTEN_EP_INT_EN_SHIFT                (0U)
27190 /*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
27191  *    interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
27192  *    bit.
27193  */
27194 #define USB_INTEN_EP_INT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
27195 
27196 #define USB_INTEN_FRAME_INT_EN_MASK              (0x40000000U)
27197 #define USB_INTEN_FRAME_INT_EN_SHIFT             (30U)
27198 /*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
27199  *    interrupt is generated on the interrupt line indicated by the corresponding USB interrupt
27200  *    routing bit.
27201  */
27202 #define USB_INTEN_FRAME_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
27203 
27204 #define USB_INTEN_DEV_INT_EN_MASK                (0x80000000U)
27205 #define USB_INTEN_DEV_INT_EN_SHIFT               (31U)
27206 /*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
27207  *    interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
27208  *    bit.
27209  */
27210 #define USB_INTEN_DEV_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
27211 /*! @} */
27212 
27213 /*! @name INTSETSTAT - USB set interrupt status register */
27214 /*! @{ */
27215 
27216 #define USB_INTSETSTAT_EP_SET_INT_MASK           (0x3FFU)
27217 #define USB_INTSETSTAT_EP_SET_INT_SHIFT          (0U)
27218 /*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
27219  *    status bit is set. When this register is read, the same value as the USB interrupt status register
27220  *    is returned.
27221  */
27222 #define USB_INTSETSTAT_EP_SET_INT(x)             (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
27223 
27224 #define USB_INTSETSTAT_FRAME_SET_INT_MASK        (0x40000000U)
27225 #define USB_INTSETSTAT_FRAME_SET_INT_SHIFT       (30U)
27226 /*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
27227  *    status bit is set. When this register is read, the same value as the USB interrupt status
27228  *    register is returned.
27229  */
27230 #define USB_INTSETSTAT_FRAME_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
27231 
27232 #define USB_INTSETSTAT_DEV_SET_INT_MASK          (0x80000000U)
27233 #define USB_INTSETSTAT_DEV_SET_INT_SHIFT         (31U)
27234 /*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
27235  *    status bit is set. When this register is read, the same value as the USB interrupt status
27236  *    register is returned.
27237  */
27238 #define USB_INTSETSTAT_DEV_SET_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
27239 /*! @} */
27240 
27241 /*! @name EPTOGGLE - USB Endpoint toggle register */
27242 /*! @{ */
27243 
27244 #define USB_EPTOGGLE_TOGGLE_MASK                 (0x3FFU)
27245 #define USB_EPTOGGLE_TOGGLE_SHIFT                (0U)
27246 /*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
27247  */
27248 #define USB_EPTOGGLE_TOGGLE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
27249 /*! @} */
27250 
27251 
27252 /*!
27253  * @}
27254  */ /* end of group USB_Register_Masks */
27255 
27256 
27257 /* USB - Peripheral instance base addresses */
27258 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
27259   /** Peripheral USB0 base address */
27260   #define USB0_BASE                                (0x50084000u)
27261   /** Peripheral USB0 base address */
27262   #define USB0_BASE_NS                             (0x40084000u)
27263   /** Peripheral USB0 base pointer */
27264   #define USB0                                     ((USB_Type *)USB0_BASE)
27265   /** Peripheral USB0 base pointer */
27266   #define USB0_NS                                  ((USB_Type *)USB0_BASE_NS)
27267   /** Array initializer of USB peripheral base addresses */
27268   #define USB_BASE_ADDRS                           { USB0_BASE }
27269   /** Array initializer of USB peripheral base pointers */
27270   #define USB_BASE_PTRS                            { USB0 }
27271   /** Array initializer of USB peripheral base addresses */
27272   #define USB_BASE_ADDRS_NS                        { USB0_BASE_NS }
27273   /** Array initializer of USB peripheral base pointers */
27274   #define USB_BASE_PTRS_NS                         { USB0_NS }
27275 #else
27276   /** Peripheral USB0 base address */
27277   #define USB0_BASE                                (0x40084000u)
27278   /** Peripheral USB0 base pointer */
27279   #define USB0                                     ((USB_Type *)USB0_BASE)
27280   /** Array initializer of USB peripheral base addresses */
27281   #define USB_BASE_ADDRS                           { USB0_BASE }
27282   /** Array initializer of USB peripheral base pointers */
27283   #define USB_BASE_PTRS                            { USB0 }
27284 #endif
27285 /** Interrupt vectors for the USB peripheral type */
27286 #define USB_IRQS                                 { USB0_IRQn }
27287 #define USB_NEEDCLK_IRQS                         { USB0_NEEDCLK_IRQn }
27288 
27289 /*!
27290  * @}
27291  */ /* end of group USB_Peripheral_Access_Layer */
27292 
27293 
27294 /* ----------------------------------------------------------------------------
27295    -- USBFSH Peripheral Access Layer
27296    ---------------------------------------------------------------------------- */
27297 
27298 /*!
27299  * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
27300  * @{
27301  */
27302 
27303 /** USBFSH - Register Layout Typedef */
27304 typedef struct {
27305   __I  uint32_t HCREVISION;                        /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
27306   __IO uint32_t HCCONTROL;                         /**< Defines the operating modes of the HC, offset: 0x4 */
27307   __IO uint32_t HCCOMMANDSTATUS;                   /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
27308   __IO uint32_t HCINTERRUPTSTATUS;                 /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
27309   __IO uint32_t HCINTERRUPTENABLE;                 /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
27310   __IO uint32_t HCINTERRUPTDISABLE;                /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
27311   __IO uint32_t HCHCCA;                            /**< Contains the physical address of the host controller communication area, offset: 0x18 */
27312   __I  uint32_t HCPERIODCURRENTED;                 /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
27313   __IO uint32_t HCCONTROLHEADED;                   /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
27314   __IO uint32_t HCCONTROLCURRENTED;                /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
27315   __IO uint32_t HCBULKHEADED;                      /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
27316   __IO uint32_t HCBULKCURRENTED;                   /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
27317   __I  uint32_t HCDONEHEAD;                        /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
27318   __IO uint32_t HCFMINTERVAL;                      /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
27319   __I  uint32_t HCFMREMAINING;                     /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
27320   __I  uint32_t HCFMNUMBER;                        /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
27321   __IO uint32_t HCPERIODICSTART;                   /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
27322   __IO uint32_t HCLSTHRESHOLD;                     /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
27323   __IO uint32_t HCRHDESCRIPTORA;                   /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
27324   __IO uint32_t HCRHDESCRIPTORB;                   /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
27325   __IO uint32_t HCRHSTATUS;                        /**< This register is divided into two parts, offset: 0x50 */
27326   __IO uint32_t HCRHPORTSTATUS;                    /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
27327        uint8_t RESERVED_0[4];
27328   __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
27329 } USBFSH_Type;
27330 
27331 /* ----------------------------------------------------------------------------
27332    -- USBFSH Register Masks
27333    ---------------------------------------------------------------------------- */
27334 
27335 /*!
27336  * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
27337  * @{
27338  */
27339 
27340 /*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
27341 /*! @{ */
27342 
27343 #define USBFSH_HCREVISION_REV_MASK               (0xFFU)
27344 #define USBFSH_HCREVISION_REV_SHIFT              (0U)
27345 /*! REV - Revision.
27346  */
27347 #define USBFSH_HCREVISION_REV(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
27348 /*! @} */
27349 
27350 /*! @name HCCONTROL - Defines the operating modes of the HC */
27351 /*! @{ */
27352 
27353 #define USBFSH_HCCONTROL_CBSR_MASK               (0x3U)
27354 #define USBFSH_HCCONTROL_CBSR_SHIFT              (0U)
27355 /*! CBSR - ControlBulkServiceRatio.
27356  */
27357 #define USBFSH_HCCONTROL_CBSR(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
27358 
27359 #define USBFSH_HCCONTROL_PLE_MASK                (0x4U)
27360 #define USBFSH_HCCONTROL_PLE_SHIFT               (2U)
27361 /*! PLE - PeriodicListEnable.
27362  */
27363 #define USBFSH_HCCONTROL_PLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
27364 
27365 #define USBFSH_HCCONTROL_IE_MASK                 (0x8U)
27366 #define USBFSH_HCCONTROL_IE_SHIFT                (3U)
27367 /*! IE - IsochronousEnable.
27368  */
27369 #define USBFSH_HCCONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
27370 
27371 #define USBFSH_HCCONTROL_CLE_MASK                (0x10U)
27372 #define USBFSH_HCCONTROL_CLE_SHIFT               (4U)
27373 /*! CLE - ControlListEnable.
27374  */
27375 #define USBFSH_HCCONTROL_CLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
27376 
27377 #define USBFSH_HCCONTROL_BLE_MASK                (0x20U)
27378 #define USBFSH_HCCONTROL_BLE_SHIFT               (5U)
27379 /*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame.
27380  */
27381 #define USBFSH_HCCONTROL_BLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
27382 
27383 #define USBFSH_HCCONTROL_HCFS_MASK               (0xC0U)
27384 #define USBFSH_HCCONTROL_HCFS_SHIFT              (6U)
27385 /*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL
27386  *    11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin
27387  *    1 ms later.
27388  */
27389 #define USBFSH_HCCONTROL_HCFS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
27390 
27391 #define USBFSH_HCCONTROL_IR_MASK                 (0x100U)
27392 #define USBFSH_HCCONTROL_IR_SHIFT                (8U)
27393 /*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus.
27394  */
27395 #define USBFSH_HCCONTROL_IR(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
27396 
27397 #define USBFSH_HCCONTROL_RWC_MASK                (0x200U)
27398 #define USBFSH_HCCONTROL_RWC_SHIFT               (9U)
27399 /*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling.
27400  */
27401 #define USBFSH_HCCONTROL_RWC(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
27402 
27403 #define USBFSH_HCCONTROL_RWE_MASK                (0x400U)
27404 #define USBFSH_HCCONTROL_RWE_SHIFT               (10U)
27405 /*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature
27406  *    upon the detection of upstream resume signaling.
27407  */
27408 #define USBFSH_HCCONTROL_RWE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
27409 /*! @} */
27410 
27411 /*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
27412 /*! @{ */
27413 
27414 #define USBFSH_HCCOMMANDSTATUS_HCR_MASK          (0x1U)
27415 #define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT         (0U)
27416 /*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC.
27417  */
27418 #define USBFSH_HCCOMMANDSTATUS_HCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
27419 
27420 #define USBFSH_HCCOMMANDSTATUS_CLF_MASK          (0x2U)
27421 #define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT         (1U)
27422 /*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.
27423  */
27424 #define USBFSH_HCCOMMANDSTATUS_CLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
27425 
27426 #define USBFSH_HCCOMMANDSTATUS_BLF_MASK          (0x4U)
27427 #define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT         (2U)
27428 /*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list.
27429  */
27430 #define USBFSH_HCCOMMANDSTATUS_BLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
27431 
27432 #define USBFSH_HCCOMMANDSTATUS_OCR_MASK          (0x8U)
27433 #define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT         (3U)
27434 /*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC.
27435  */
27436 #define USBFSH_HCCOMMANDSTATUS_OCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
27437 
27438 #define USBFSH_HCCOMMANDSTATUS_SOC_MASK          (0xC0U)
27439 #define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT         (6U)
27440 /*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error.
27441  */
27442 #define USBFSH_HCCOMMANDSTATUS_SOC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
27443 /*! @} */
27444 
27445 /*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
27446 /*! @{ */
27447 
27448 #define USBFSH_HCINTERRUPTSTATUS_SO_MASK         (0x1U)
27449 #define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT        (0U)
27450 /*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and
27451  *    after the update of HccaFrameNumber.
27452  */
27453 #define USBFSH_HCINTERRUPTSTATUS_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
27454 
27455 #define USBFSH_HCINTERRUPTSTATUS_WDH_MASK        (0x2U)
27456 #define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT       (1U)
27457 /*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead.
27458  */
27459 #define USBFSH_HCINTERRUPTSTATUS_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
27460 
27461 #define USBFSH_HCINTERRUPTSTATUS_SF_MASK         (0x4U)
27462 #define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT        (2U)
27463 /*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber.
27464  */
27465 #define USBFSH_HCINTERRUPTSTATUS_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
27466 
27467 #define USBFSH_HCINTERRUPTSTATUS_RD_MASK         (0x8U)
27468 #define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT        (3U)
27469 /*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling.
27470  */
27471 #define USBFSH_HCINTERRUPTSTATUS_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
27472 
27473 #define USBFSH_HCINTERRUPTSTATUS_UE_MASK         (0x10U)
27474 #define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT        (4U)
27475 /*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB.
27476  */
27477 #define USBFSH_HCINTERRUPTSTATUS_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
27478 
27479 #define USBFSH_HCINTERRUPTSTATUS_FNO_MASK        (0x20U)
27480 #define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT       (5U)
27481 /*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value,
27482  *    from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated.
27483  */
27484 #define USBFSH_HCINTERRUPTSTATUS_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
27485 
27486 #define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK       (0x40U)
27487 #define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT      (6U)
27488 /*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any
27489  *    of HcRhPortStatus[NumberofDownstreamPort] has changed.
27490  */
27491 #define USBFSH_HCINTERRUPTSTATUS_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
27492 
27493 #define USBFSH_HCINTERRUPTSTATUS_OC_MASK         (0xFFFFFC00U)
27494 #define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT        (10U)
27495 /*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.
27496  */
27497 #define USBFSH_HCINTERRUPTSTATUS_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
27498 /*! @} */
27499 
27500 /*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
27501 /*! @{ */
27502 
27503 #define USBFSH_HCINTERRUPTENABLE_SO_MASK         (0x1U)
27504 #define USBFSH_HCINTERRUPTENABLE_SO_SHIFT        (0U)
27505 /*! SO - Scheduling Overrun interrupt.
27506  */
27507 #define USBFSH_HCINTERRUPTENABLE_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
27508 
27509 #define USBFSH_HCINTERRUPTENABLE_WDH_MASK        (0x2U)
27510 #define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT       (1U)
27511 /*! WDH - HcDoneHead Writeback interrupt.
27512  */
27513 #define USBFSH_HCINTERRUPTENABLE_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
27514 
27515 #define USBFSH_HCINTERRUPTENABLE_SF_MASK         (0x4U)
27516 #define USBFSH_HCINTERRUPTENABLE_SF_SHIFT        (2U)
27517 /*! SF - Start of Frame interrupt.
27518  */
27519 #define USBFSH_HCINTERRUPTENABLE_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
27520 
27521 #define USBFSH_HCINTERRUPTENABLE_RD_MASK         (0x8U)
27522 #define USBFSH_HCINTERRUPTENABLE_RD_SHIFT        (3U)
27523 /*! RD - Resume Detect interrupt.
27524  */
27525 #define USBFSH_HCINTERRUPTENABLE_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
27526 
27527 #define USBFSH_HCINTERRUPTENABLE_UE_MASK         (0x10U)
27528 #define USBFSH_HCINTERRUPTENABLE_UE_SHIFT        (4U)
27529 /*! UE - Unrecoverable Error interrupt.
27530  */
27531 #define USBFSH_HCINTERRUPTENABLE_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
27532 
27533 #define USBFSH_HCINTERRUPTENABLE_FNO_MASK        (0x20U)
27534 #define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT       (5U)
27535 /*! FNO - Frame Number Overflow interrupt.
27536  */
27537 #define USBFSH_HCINTERRUPTENABLE_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
27538 
27539 #define USBFSH_HCINTERRUPTENABLE_RHSC_MASK       (0x40U)
27540 #define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT      (6U)
27541 /*! RHSC - Root Hub Status Change interrupt.
27542  */
27543 #define USBFSH_HCINTERRUPTENABLE_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
27544 
27545 #define USBFSH_HCINTERRUPTENABLE_OC_MASK         (0x40000000U)
27546 #define USBFSH_HCINTERRUPTENABLE_OC_SHIFT        (30U)
27547 /*! OC - Ownership Change interrupt.
27548  */
27549 #define USBFSH_HCINTERRUPTENABLE_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
27550 
27551 #define USBFSH_HCINTERRUPTENABLE_MIE_MASK        (0x80000000U)
27552 #define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT       (31U)
27553 /*! MIE - Master Interrupt Enable.
27554  */
27555 #define USBFSH_HCINTERRUPTENABLE_MIE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
27556 /*! @} */
27557 
27558 /*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
27559 /*! @{ */
27560 
27561 #define USBFSH_HCINTERRUPTDISABLE_SO_MASK        (0x1U)
27562 #define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT       (0U)
27563 /*! SO - Scheduling Overrun interrupt.
27564  */
27565 #define USBFSH_HCINTERRUPTDISABLE_SO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
27566 
27567 #define USBFSH_HCINTERRUPTDISABLE_WDH_MASK       (0x2U)
27568 #define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT      (1U)
27569 /*! WDH - HcDoneHead Writeback interrupt.
27570  */
27571 #define USBFSH_HCINTERRUPTDISABLE_WDH(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
27572 
27573 #define USBFSH_HCINTERRUPTDISABLE_SF_MASK        (0x4U)
27574 #define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT       (2U)
27575 /*! SF - Start of Frame interrupt.
27576  */
27577 #define USBFSH_HCINTERRUPTDISABLE_SF(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
27578 
27579 #define USBFSH_HCINTERRUPTDISABLE_RD_MASK        (0x8U)
27580 #define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT       (3U)
27581 /*! RD - Resume Detect interrupt.
27582  */
27583 #define USBFSH_HCINTERRUPTDISABLE_RD(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
27584 
27585 #define USBFSH_HCINTERRUPTDISABLE_UE_MASK        (0x10U)
27586 #define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT       (4U)
27587 /*! UE - Unrecoverable Error interrupt.
27588  */
27589 #define USBFSH_HCINTERRUPTDISABLE_UE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
27590 
27591 #define USBFSH_HCINTERRUPTDISABLE_FNO_MASK       (0x20U)
27592 #define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT      (5U)
27593 /*! FNO - Frame Number Overflow interrupt.
27594  */
27595 #define USBFSH_HCINTERRUPTDISABLE_FNO(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
27596 
27597 #define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK      (0x40U)
27598 #define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT     (6U)
27599 /*! RHSC - Root Hub Status Change interrupt.
27600  */
27601 #define USBFSH_HCINTERRUPTDISABLE_RHSC(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
27602 
27603 #define USBFSH_HCINTERRUPTDISABLE_OC_MASK        (0x40000000U)
27604 #define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT       (30U)
27605 /*! OC - Ownership Change interrupt.
27606  */
27607 #define USBFSH_HCINTERRUPTDISABLE_OC(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
27608 
27609 #define USBFSH_HCINTERRUPTDISABLE_MIE_MASK       (0x80000000U)
27610 #define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT      (31U)
27611 /*! MIE - A 0 written to this field is ignored by HC.
27612  */
27613 #define USBFSH_HCINTERRUPTDISABLE_MIE(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
27614 /*! @} */
27615 
27616 /*! @name HCHCCA - Contains the physical address of the host controller communication area */
27617 /*! @{ */
27618 
27619 #define USBFSH_HCHCCA_HCCA_MASK                  (0xFFFFFF00U)
27620 #define USBFSH_HCHCCA_HCCA_SHIFT                 (8U)
27621 /*! HCCA - Base address of the Host Controller Communication Area.
27622  */
27623 #define USBFSH_HCHCCA_HCCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
27624 /*! @} */
27625 
27626 /*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
27627 /*! @{ */
27628 
27629 #define USBFSH_HCPERIODCURRENTED_PCED_MASK       (0xFFFFFFF0U)
27630 #define USBFSH_HCPERIODCURRENTED_PCED_SHIFT      (4U)
27631 /*! PCED - The content of this register is updated by HC after a periodic ED is processed.
27632  */
27633 #define USBFSH_HCPERIODCURRENTED_PCED(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
27634 /*! @} */
27635 
27636 /*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
27637 /*! @{ */
27638 
27639 #define USBFSH_HCCONTROLHEADED_CHED_MASK         (0xFFFFFFF0U)
27640 #define USBFSH_HCCONTROLHEADED_CHED_SHIFT        (4U)
27641 /*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer.
27642  */
27643 #define USBFSH_HCCONTROLHEADED_CHED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
27644 /*! @} */
27645 
27646 /*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
27647 /*! @{ */
27648 
27649 #define USBFSH_HCCONTROLCURRENTED_CCED_MASK      (0xFFFFFFF0U)
27650 #define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT     (4U)
27651 /*! CCED - ControlCurrentED.
27652  */
27653 #define USBFSH_HCCONTROLCURRENTED_CCED(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
27654 /*! @} */
27655 
27656 /*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
27657 /*! @{ */
27658 
27659 #define USBFSH_HCBULKHEADED_BHED_MASK            (0xFFFFFFF0U)
27660 #define USBFSH_HCBULKHEADED_BHED_SHIFT           (4U)
27661 /*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer.
27662  */
27663 #define USBFSH_HCBULKHEADED_BHED(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
27664 /*! @} */
27665 
27666 /*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
27667 /*! @{ */
27668 
27669 #define USBFSH_HCBULKCURRENTED_BCED_MASK         (0xFFFFFFF0U)
27670 #define USBFSH_HCBULKCURRENTED_BCED_SHIFT        (4U)
27671 /*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one.
27672  */
27673 #define USBFSH_HCBULKCURRENTED_BCED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
27674 /*! @} */
27675 
27676 /*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
27677 /*! @{ */
27678 
27679 #define USBFSH_HCDONEHEAD_DH_MASK                (0xFFFFFFF0U)
27680 #define USBFSH_HCDONEHEAD_DH_SHIFT               (4U)
27681 /*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD.
27682  */
27683 #define USBFSH_HCDONEHEAD_DH(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
27684 /*! @} */
27685 
27686 /*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
27687 /*! @{ */
27688 
27689 #define USBFSH_HCFMINTERVAL_FI_MASK              (0x3FFFU)
27690 #define USBFSH_HCFMINTERVAL_FI_SHIFT             (0U)
27691 /*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times.
27692  */
27693 #define USBFSH_HCFMINTERVAL_FI(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
27694 
27695 #define USBFSH_HCFMINTERVAL_FSMPS_MASK           (0x7FFF0000U)
27696 #define USBFSH_HCFMINTERVAL_FSMPS_SHIFT          (16U)
27697 /*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data
27698  *    Packet Counter at the beginning of each frame.
27699  */
27700 #define USBFSH_HCFMINTERVAL_FSMPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
27701 
27702 #define USBFSH_HCFMINTERVAL_FIT_MASK             (0x80000000U)
27703 #define USBFSH_HCFMINTERVAL_FIT_SHIFT            (31U)
27704 /*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval.
27705  */
27706 #define USBFSH_HCFMINTERVAL_FIT(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
27707 /*! @} */
27708 
27709 /*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
27710 /*! @{ */
27711 
27712 #define USBFSH_HCFMREMAINING_FR_MASK             (0x3FFFU)
27713 #define USBFSH_HCFMREMAINING_FR_SHIFT            (0U)
27714 /*! FR - FrameRemaining This counter is decremented at each bit time.
27715  */
27716 #define USBFSH_HCFMREMAINING_FR(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
27717 
27718 #define USBFSH_HCFMREMAINING_FRT_MASK            (0x80000000U)
27719 #define USBFSH_HCFMREMAINING_FRT_SHIFT           (31U)
27720 /*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval
27721  *    whenever FrameRemaining reaches 0.
27722  */
27723 #define USBFSH_HCFMREMAINING_FRT(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
27724 /*! @} */
27725 
27726 /*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
27727 /*! @{ */
27728 
27729 #define USBFSH_HCFMNUMBER_FN_MASK                (0xFFFFU)
27730 #define USBFSH_HCFMNUMBER_FN_SHIFT               (0U)
27731 /*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded.
27732  */
27733 #define USBFSH_HCFMNUMBER_FN(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
27734 /*! @} */
27735 
27736 /*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
27737 /*! @{ */
27738 
27739 #define USBFSH_HCPERIODICSTART_PS_MASK           (0x3FFFU)
27740 #define USBFSH_HCPERIODICSTART_PS_SHIFT          (0U)
27741 /*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization.
27742  */
27743 #define USBFSH_HCPERIODICSTART_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
27744 /*! @} */
27745 
27746 /*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
27747 /*! @{ */
27748 
27749 #define USBFSH_HCLSTHRESHOLD_LST_MASK            (0xFFFU)
27750 #define USBFSH_HCLSTHRESHOLD_LST_SHIFT           (0U)
27751 /*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field
27752  *    prior to initiating a Low Speed transaction.
27753  */
27754 #define USBFSH_HCLSTHRESHOLD_LST(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
27755 /*! @} */
27756 
27757 /*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
27758 /*! @{ */
27759 
27760 #define USBFSH_HCRHDESCRIPTORA_NDP_MASK          (0xFFU)
27761 #define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT         (0U)
27762 /*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub.
27763  */
27764 #define USBFSH_HCRHDESCRIPTORA_NDP(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
27765 
27766 #define USBFSH_HCRHDESCRIPTORA_PSM_MASK          (0x100U)
27767 #define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT         (8U)
27768 /*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled.
27769  */
27770 #define USBFSH_HCRHDESCRIPTORA_PSM(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
27771 
27772 #define USBFSH_HCRHDESCRIPTORA_NPS_MASK          (0x200U)
27773 #define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT         (9U)
27774 /*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered.
27775  */
27776 #define USBFSH_HCRHDESCRIPTORA_NPS(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
27777 
27778 #define USBFSH_HCRHDESCRIPTORA_DT_MASK           (0x400U)
27779 #define USBFSH_HCRHDESCRIPTORA_DT_SHIFT          (10U)
27780 /*! DT - DeviceType This bit specifies that the root hub is not a compound device.
27781  */
27782 #define USBFSH_HCRHDESCRIPTORA_DT(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
27783 
27784 #define USBFSH_HCRHDESCRIPTORA_OCPM_MASK         (0x800U)
27785 #define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT        (11U)
27786 /*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported.
27787  */
27788 #define USBFSH_HCRHDESCRIPTORA_OCPM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
27789 
27790 #define USBFSH_HCRHDESCRIPTORA_NOCP_MASK         (0x1000U)
27791 #define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT        (12U)
27792 /*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported.
27793  */
27794 #define USBFSH_HCRHDESCRIPTORA_NOCP(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
27795 
27796 #define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK       (0xFF000000U)
27797 #define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT      (24U)
27798 /*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before
27799  *    accessing a powered-on port of the root hub.
27800  */
27801 #define USBFSH_HCRHDESCRIPTORA_POTPGT(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
27802 /*! @} */
27803 
27804 /*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
27805 /*! @{ */
27806 
27807 #define USBFSH_HCRHDESCRIPTORB_DR_MASK           (0xFFFFU)
27808 #define USBFSH_HCRHDESCRIPTORB_DR_SHIFT          (0U)
27809 /*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub.
27810  */
27811 #define USBFSH_HCRHDESCRIPTORB_DR(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
27812 
27813 #define USBFSH_HCRHDESCRIPTORB_PPCM_MASK         (0xFFFF0000U)
27814 #define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT        (16U)
27815 /*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control
27816  *    command when PowerSwitchingMode is set.
27817  */
27818 #define USBFSH_HCRHDESCRIPTORB_PPCM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
27819 /*! @} */
27820 
27821 /*! @name HCRHSTATUS - This register is divided into two parts */
27822 /*! @{ */
27823 
27824 #define USBFSH_HCRHSTATUS_LPS_MASK               (0x1U)
27825 #define USBFSH_HCRHSTATUS_LPS_SHIFT              (0U)
27826 /*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature;
27827  *    thus, this bit is always read as 0.
27828  */
27829 #define USBFSH_HCRHSTATUS_LPS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
27830 
27831 #define USBFSH_HCRHSTATUS_OCI_MASK               (0x2U)
27832 #define USBFSH_HCRHSTATUS_OCI_SHIFT              (1U)
27833 /*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented.
27834  */
27835 #define USBFSH_HCRHSTATUS_OCI(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
27836 
27837 #define USBFSH_HCRHSTATUS_DRWE_MASK              (0x8000U)
27838 #define USBFSH_HCRHSTATUS_DRWE_SHIFT             (15U)
27839 /*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume
27840  *    event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected
27841  *    interrupt.
27842  */
27843 #define USBFSH_HCRHSTATUS_DRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
27844 
27845 #define USBFSH_HCRHSTATUS_LPSC_MASK              (0x10000U)
27846 #define USBFSH_HCRHSTATUS_LPSC_SHIFT             (16U)
27847 /*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature.
27848  */
27849 #define USBFSH_HCRHSTATUS_LPSC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
27850 
27851 #define USBFSH_HCRHSTATUS_OCIC_MASK              (0x20000U)
27852 #define USBFSH_HCRHSTATUS_OCIC_SHIFT             (17U)
27853 /*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register.
27854  */
27855 #define USBFSH_HCRHSTATUS_OCIC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
27856 
27857 #define USBFSH_HCRHSTATUS_CRWE_MASK              (0x80000000U)
27858 #define USBFSH_HCRHSTATUS_CRWE_SHIFT             (31U)
27859 /*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable.
27860  */
27861 #define USBFSH_HCRHSTATUS_CRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
27862 /*! @} */
27863 
27864 /*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
27865 /*! @{ */
27866 
27867 #define USBFSH_HCRHPORTSTATUS_CCS_MASK           (0x1U)
27868 #define USBFSH_HCRHPORTSTATUS_CCS_SHIFT          (0U)
27869 /*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port.
27870  */
27871 #define USBFSH_HCRHPORTSTATUS_CCS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
27872 
27873 #define USBFSH_HCRHPORTSTATUS_PES_MASK           (0x2U)
27874 #define USBFSH_HCRHPORTSTATUS_PES_SHIFT          (1U)
27875 /*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled.
27876  */
27877 #define USBFSH_HCRHPORTSTATUS_PES(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
27878 
27879 #define USBFSH_HCRHPORTSTATUS_PSS_MASK           (0x4U)
27880 #define USBFSH_HCRHPORTSTATUS_PSS_SHIFT          (2U)
27881 /*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence.
27882  */
27883 #define USBFSH_HCRHPORTSTATUS_PSS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
27884 
27885 #define USBFSH_HCRHPORTSTATUS_POCI_MASK          (0x8U)
27886 #define USBFSH_HCRHPORTSTATUS_POCI_SHIFT         (3U)
27887 /*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in
27888  *    such a way that overcurrent conditions are reported on a per-port basis.
27889  */
27890 #define USBFSH_HCRHPORTSTATUS_POCI(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
27891 
27892 #define USBFSH_HCRHPORTSTATUS_PRS_MASK           (0x10U)
27893 #define USBFSH_HCRHPORTSTATUS_PRS_SHIFT          (4U)
27894 /*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted.
27895  */
27896 #define USBFSH_HCRHPORTSTATUS_PRS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
27897 
27898 #define USBFSH_HCRHPORTSTATUS_PPS_MASK           (0x100U)
27899 #define USBFSH_HCRHPORTSTATUS_PPS_SHIFT          (8U)
27900 /*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type
27901  *    of power switching implemented.
27902  */
27903 #define USBFSH_HCRHPORTSTATUS_PPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
27904 
27905 #define USBFSH_HCRHPORTSTATUS_LSDA_MASK          (0x200U)
27906 #define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT         (9U)
27907 /*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port.
27908  */
27909 #define USBFSH_HCRHPORTSTATUS_LSDA(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
27910 
27911 #define USBFSH_HCRHPORTSTATUS_CSC_MASK           (0x10000U)
27912 #define USBFSH_HCRHPORTSTATUS_CSC_SHIFT          (16U)
27913 /*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs.
27914  */
27915 #define USBFSH_HCRHPORTSTATUS_CSC(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
27916 
27917 #define USBFSH_HCRHPORTSTATUS_PESC_MASK          (0x20000U)
27918 #define USBFSH_HCRHPORTSTATUS_PESC_SHIFT         (17U)
27919 /*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared.
27920  */
27921 #define USBFSH_HCRHPORTSTATUS_PESC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
27922 
27923 #define USBFSH_HCRHPORTSTATUS_PSSC_MASK          (0x40000U)
27924 #define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT         (18U)
27925 /*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed.
27926  */
27927 #define USBFSH_HCRHPORTSTATUS_PSSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
27928 
27929 #define USBFSH_HCRHPORTSTATUS_OCIC_MASK          (0x80000U)
27930 #define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT         (19U)
27931 /*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis.
27932  */
27933 #define USBFSH_HCRHPORTSTATUS_OCIC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
27934 
27935 #define USBFSH_HCRHPORTSTATUS_PRSC_MASK          (0x100000U)
27936 #define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT         (20U)
27937 /*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal.
27938  */
27939 #define USBFSH_HCRHPORTSTATUS_PRSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
27940 /*! @} */
27941 
27942 /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
27943 /*! @{ */
27944 
27945 #define USBFSH_PORTMODE_ID_MASK                  (0x1U)
27946 #define USBFSH_PORTMODE_ID_SHIFT                 (0U)
27947 /*! ID - Port ID pin value.
27948  */
27949 #define USBFSH_PORTMODE_ID(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
27950 
27951 #define USBFSH_PORTMODE_ID_EN_MASK               (0x100U)
27952 #define USBFSH_PORTMODE_ID_EN_SHIFT              (8U)
27953 /*! ID_EN - Port ID pin pull-up enable.
27954  */
27955 #define USBFSH_PORTMODE_ID_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
27956 
27957 #define USBFSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
27958 #define USBFSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
27959 /*! DEV_ENABLE - 1: device 0: host.
27960  */
27961 #define USBFSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
27962 /*! @} */
27963 
27964 
27965 /*!
27966  * @}
27967  */ /* end of group USBFSH_Register_Masks */
27968 
27969 
27970 /* USBFSH - Peripheral instance base addresses */
27971 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
27972   /** Peripheral USBFSH base address */
27973   #define USBFSH_BASE                              (0x500A2000u)
27974   /** Peripheral USBFSH base address */
27975   #define USBFSH_BASE_NS                           (0x400A2000u)
27976   /** Peripheral USBFSH base pointer */
27977   #define USBFSH                                   ((USBFSH_Type *)USBFSH_BASE)
27978   /** Peripheral USBFSH base pointer */
27979   #define USBFSH_NS                                ((USBFSH_Type *)USBFSH_BASE_NS)
27980   /** Array initializer of USBFSH peripheral base addresses */
27981   #define USBFSH_BASE_ADDRS                        { USBFSH_BASE }
27982   /** Array initializer of USBFSH peripheral base pointers */
27983   #define USBFSH_BASE_PTRS                         { USBFSH }
27984   /** Array initializer of USBFSH peripheral base addresses */
27985   #define USBFSH_BASE_ADDRS_NS                     { USBFSH_BASE_NS }
27986   /** Array initializer of USBFSH peripheral base pointers */
27987   #define USBFSH_BASE_PTRS_NS                      { USBFSH_NS }
27988 #else
27989   /** Peripheral USBFSH base address */
27990   #define USBFSH_BASE                              (0x400A2000u)
27991   /** Peripheral USBFSH base pointer */
27992   #define USBFSH                                   ((USBFSH_Type *)USBFSH_BASE)
27993   /** Array initializer of USBFSH peripheral base addresses */
27994   #define USBFSH_BASE_ADDRS                        { USBFSH_BASE }
27995   /** Array initializer of USBFSH peripheral base pointers */
27996   #define USBFSH_BASE_PTRS                         { USBFSH }
27997 #endif
27998 /** Interrupt vectors for the USBFSH peripheral type */
27999 #define USBFSH_IRQS                              { USB0_IRQn }
28000 #define USBFSH_NEEDCLK_IRQS                      { USB0_NEEDCLK_IRQn }
28001 
28002 /*!
28003  * @}
28004  */ /* end of group USBFSH_Peripheral_Access_Layer */
28005 
28006 
28007 /* ----------------------------------------------------------------------------
28008    -- USBHSD Peripheral Access Layer
28009    ---------------------------------------------------------------------------- */
28010 
28011 /*!
28012  * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
28013  * @{
28014  */
28015 
28016 /** USBHSD - Register Layout Typedef */
28017 typedef struct {
28018   __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
28019   __I  uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
28020   __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
28021   __IO uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
28022   __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
28023   __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
28024   __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
28025   __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
28026   __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
28027   __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
28028   __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
28029        uint8_t RESERVED_0[8];
28030   __I  uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
28031 } USBHSD_Type;
28032 
28033 /* ----------------------------------------------------------------------------
28034    -- USBHSD Register Masks
28035    ---------------------------------------------------------------------------- */
28036 
28037 /*!
28038  * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
28039  * @{
28040  */
28041 
28042 /*! @name DEVCMDSTAT - USB Device Command/Status register */
28043 /*! @{ */
28044 
28045 #define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK          (0x7FU)
28046 #define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT         (0U)
28047 /*! DEV_ADDR - USB device address.
28048  */
28049 #define USBHSD_DEVCMDSTAT_DEV_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
28050 
28051 #define USBHSD_DEVCMDSTAT_DEV_EN_MASK            (0x80U)
28052 #define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT           (7U)
28053 /*! DEV_EN - USB device enable.
28054  */
28055 #define USBHSD_DEVCMDSTAT_DEV_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
28056 
28057 #define USBHSD_DEVCMDSTAT_SETUP_MASK             (0x100U)
28058 #define USBHSD_DEVCMDSTAT_SETUP_SHIFT            (8U)
28059 /*! SETUP - SETUP token received.
28060  */
28061 #define USBHSD_DEVCMDSTAT_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
28062 
28063 #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK     (0x200U)
28064 #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT    (9U)
28065 /*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:.
28066  */
28067 #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
28068 
28069 #define USBHSD_DEVCMDSTAT_LPM_SUP_MASK           (0x800U)
28070 #define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT          (11U)
28071 /*! LPM_SUP - LPM Supported:.
28072  */
28073 #define USBHSD_DEVCMDSTAT_LPM_SUP(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
28074 
28075 #define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK       (0x1000U)
28076 #define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT      (12U)
28077 /*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:.
28078  */
28079 #define USBHSD_DEVCMDSTAT_INTONNAK_AO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
28080 
28081 #define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK       (0x2000U)
28082 #define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT      (13U)
28083 /*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:.
28084  */
28085 #define USBHSD_DEVCMDSTAT_INTONNAK_AI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
28086 
28087 #define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK       (0x4000U)
28088 #define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT      (14U)
28089 /*! INTONNAK_CO - Interrupt on NAK for control OUT EP:.
28090  */
28091 #define USBHSD_DEVCMDSTAT_INTONNAK_CO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
28092 
28093 #define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK       (0x8000U)
28094 #define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT      (15U)
28095 /*! INTONNAK_CI - Interrupt on NAK for control IN EP:.
28096  */
28097 #define USBHSD_DEVCMDSTAT_INTONNAK_CI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
28098 
28099 #define USBHSD_DEVCMDSTAT_DCON_MASK              (0x10000U)
28100 #define USBHSD_DEVCMDSTAT_DCON_SHIFT             (16U)
28101 /*! DCON - Device status - connect.
28102  */
28103 #define USBHSD_DEVCMDSTAT_DCON(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
28104 
28105 #define USBHSD_DEVCMDSTAT_DSUS_MASK              (0x20000U)
28106 #define USBHSD_DEVCMDSTAT_DSUS_SHIFT             (17U)
28107 /*! DSUS - Device status - suspend.
28108  */
28109 #define USBHSD_DEVCMDSTAT_DSUS(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
28110 
28111 #define USBHSD_DEVCMDSTAT_LPM_SUS_MASK           (0x80000U)
28112 #define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT          (19U)
28113 /*! LPM_SUS - Device status - LPM Suspend.
28114  */
28115 #define USBHSD_DEVCMDSTAT_LPM_SUS(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
28116 
28117 #define USBHSD_DEVCMDSTAT_LPM_REWP_MASK          (0x100000U)
28118 #define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT         (20U)
28119 /*! LPM_REWP - LPM Remote Wake-up Enabled by USB host.
28120  */
28121 #define USBHSD_DEVCMDSTAT_LPM_REWP(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
28122 
28123 #define USBHSD_DEVCMDSTAT_Speed_MASK             (0xC00000U)
28124 #define USBHSD_DEVCMDSTAT_Speed_SHIFT            (22U)
28125 /*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b:
28126  *    full-speed 10b: high-speed 11b: super-speed (reserved for future use).
28127  */
28128 #define USBHSD_DEVCMDSTAT_Speed(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
28129 
28130 #define USBHSD_DEVCMDSTAT_DCON_C_MASK            (0x1000000U)
28131 #define USBHSD_DEVCMDSTAT_DCON_C_SHIFT           (24U)
28132 /*! DCON_C - Device status - connect change.
28133  */
28134 #define USBHSD_DEVCMDSTAT_DCON_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
28135 
28136 #define USBHSD_DEVCMDSTAT_DSUS_C_MASK            (0x2000000U)
28137 #define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT           (25U)
28138 /*! DSUS_C - Device status - suspend change.
28139  */
28140 #define USBHSD_DEVCMDSTAT_DSUS_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
28141 
28142 #define USBHSD_DEVCMDSTAT_DRES_C_MASK            (0x4000000U)
28143 #define USBHSD_DEVCMDSTAT_DRES_C_SHIFT           (26U)
28144 /*! DRES_C - Device status - reset change.
28145  */
28146 #define USBHSD_DEVCMDSTAT_DRES_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
28147 
28148 #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK    (0x10000000U)
28149 #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT   (28U)
28150 /*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not.
28151  */
28152 #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
28153 
28154 #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK     (0xE0000000U)
28155 #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT    (29U)
28156 /*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification.
28157  *  0b000..Test mode disabled.
28158  *  0b001..Test_J.
28159  *  0b010..Test_K.
28160  *  0b011..Test_SE0_NAK.
28161  *  0b100..Test_Packet.
28162  *  0b101..Test_Force_Enable.
28163  */
28164 #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
28165 /*! @} */
28166 
28167 /*! @name INFO - USB Info register */
28168 /*! @{ */
28169 
28170 #define USBHSD_INFO_FRAME_NR_MASK                (0x7FFU)
28171 #define USBHSD_INFO_FRAME_NR_SHIFT               (0U)
28172 /*! FRAME_NR - Frame number.
28173  */
28174 #define USBHSD_INFO_FRAME_NR(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
28175 
28176 #define USBHSD_INFO_ERR_CODE_MASK                (0x7800U)
28177 #define USBHSD_INFO_ERR_CODE_SHIFT               (11U)
28178 /*! ERR_CODE - The error code which last occurred:.
28179  */
28180 #define USBHSD_INFO_ERR_CODE(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
28181 
28182 #define USBHSD_INFO_MINREV_MASK                  (0xFF0000U)
28183 #define USBHSD_INFO_MINREV_SHIFT                 (16U)
28184 /*! MINREV - Minor revision.
28185  */
28186 #define USBHSD_INFO_MINREV(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK)
28187 
28188 #define USBHSD_INFO_MAJREV_MASK                  (0xFF000000U)
28189 #define USBHSD_INFO_MAJREV_SHIFT                 (24U)
28190 /*! MAJREV - Major revision.
28191  */
28192 #define USBHSD_INFO_MAJREV(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK)
28193 /*! @} */
28194 
28195 /*! @name EPLISTSTART - USB EP Command/Status List start address */
28196 /*! @{ */
28197 
28198 #define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK      (0xFFF00U)
28199 #define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT     (8U)
28200 /*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address.
28201  */
28202 #define USBHSD_EPLISTSTART_EP_LIST_PRG(x)        (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
28203 
28204 #define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK    (0xFFF00000U)
28205 #define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT   (20U)
28206 /*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address.
28207  */
28208 #define USBHSD_EPLISTSTART_EP_LIST_FIXED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
28209 /*! @} */
28210 
28211 /*! @name DATABUFSTART - USB Data buffer start address */
28212 /*! @{ */
28213 
28214 #define USBHSD_DATABUFSTART_DA_BUF_MASK          (0xFFFFFFFFU)
28215 #define USBHSD_DATABUFSTART_DA_BUF_SHIFT         (0U)
28216 /*! DA_BUF - Start address of the memory page where all endpoint data buffers are located.
28217  */
28218 #define USBHSD_DATABUFSTART_DA_BUF(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
28219 /*! @} */
28220 
28221 /*! @name LPM - USB Link Power Management register */
28222 /*! @{ */
28223 
28224 #define USBHSD_LPM_HIRD_HW_MASK                  (0xFU)
28225 #define USBHSD_LPM_HIRD_HW_SHIFT                 (0U)
28226 /*! HIRD_HW - Host Initiated Resume Duration - HW.
28227  */
28228 #define USBHSD_LPM_HIRD_HW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
28229 
28230 #define USBHSD_LPM_HIRD_SW_MASK                  (0xF0U)
28231 #define USBHSD_LPM_HIRD_SW_SHIFT                 (4U)
28232 /*! HIRD_SW - Host Initiated Resume Duration - SW.
28233  */
28234 #define USBHSD_LPM_HIRD_SW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
28235 
28236 #define USBHSD_LPM_DATA_PENDING_MASK             (0x100U)
28237 #define USBHSD_LPM_DATA_PENDING_SHIFT            (8U)
28238 /*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
28239  *    return a NYET handshake on every LPM token it receives.
28240  */
28241 #define USBHSD_LPM_DATA_PENDING(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
28242 /*! @} */
28243 
28244 /*! @name EPSKIP - USB Endpoint skip */
28245 /*! @{ */
28246 
28247 #define USBHSD_EPSKIP_SKIP_MASK                  (0xFFFU)
28248 #define USBHSD_EPSKIP_SKIP_SHIFT                 (0U)
28249 /*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
28250  *    deactivate the buffer assigned to this endpoint and return control back to software.
28251  */
28252 #define USBHSD_EPSKIP_SKIP(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
28253 /*! @} */
28254 
28255 /*! @name EPINUSE - USB Endpoint Buffer in use */
28256 /*! @{ */
28257 
28258 #define USBHSD_EPINUSE_BUF_MASK                  (0xFFCU)
28259 #define USBHSD_EPINUSE_BUF_SHIFT                 (2U)
28260 /*! BUF - Buffer in use: This register has one bit per physical endpoint.
28261  */
28262 #define USBHSD_EPINUSE_BUF(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
28263 /*! @} */
28264 
28265 /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
28266 /*! @{ */
28267 
28268 #define USBHSD_EPBUFCFG_BUF_SB_MASK              (0xFFCU)
28269 #define USBHSD_EPBUFCFG_BUF_SB_SHIFT             (2U)
28270 /*! BUF_SB - Buffer usage: This register has one bit per physical endpoint.
28271  */
28272 #define USBHSD_EPBUFCFG_BUF_SB(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
28273 /*! @} */
28274 
28275 /*! @name INTSTAT - USB interrupt status register */
28276 /*! @{ */
28277 
28278 #define USBHSD_INTSTAT_EP0OUT_MASK               (0x1U)
28279 #define USBHSD_INTSTAT_EP0OUT_SHIFT              (0U)
28280 /*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction.
28281  */
28282 #define USBHSD_INTSTAT_EP0OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
28283 
28284 #define USBHSD_INTSTAT_EP0IN_MASK                (0x2U)
28285 #define USBHSD_INTSTAT_EP0IN_SHIFT               (1U)
28286 /*! EP0IN - Interrupt status register bit for the Control EP0 IN direction.
28287  */
28288 #define USBHSD_INTSTAT_EP0IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
28289 
28290 #define USBHSD_INTSTAT_EP1OUT_MASK               (0x4U)
28291 #define USBHSD_INTSTAT_EP1OUT_SHIFT              (2U)
28292 /*! EP1OUT - Interrupt status register bit for the EP1 OUT direction.
28293  */
28294 #define USBHSD_INTSTAT_EP1OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
28295 
28296 #define USBHSD_INTSTAT_EP1IN_MASK                (0x8U)
28297 #define USBHSD_INTSTAT_EP1IN_SHIFT               (3U)
28298 /*! EP1IN - Interrupt status register bit for the EP1 IN direction.
28299  */
28300 #define USBHSD_INTSTAT_EP1IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
28301 
28302 #define USBHSD_INTSTAT_EP2OUT_MASK               (0x10U)
28303 #define USBHSD_INTSTAT_EP2OUT_SHIFT              (4U)
28304 /*! EP2OUT - Interrupt status register bit for the EP2 OUT direction.
28305  */
28306 #define USBHSD_INTSTAT_EP2OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
28307 
28308 #define USBHSD_INTSTAT_EP2IN_MASK                (0x20U)
28309 #define USBHSD_INTSTAT_EP2IN_SHIFT               (5U)
28310 /*! EP2IN - Interrupt status register bit for the EP2 IN direction.
28311  */
28312 #define USBHSD_INTSTAT_EP2IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
28313 
28314 #define USBHSD_INTSTAT_EP3OUT_MASK               (0x40U)
28315 #define USBHSD_INTSTAT_EP3OUT_SHIFT              (6U)
28316 /*! EP3OUT - Interrupt status register bit for the EP3 OUT direction.
28317  */
28318 #define USBHSD_INTSTAT_EP3OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
28319 
28320 #define USBHSD_INTSTAT_EP3IN_MASK                (0x80U)
28321 #define USBHSD_INTSTAT_EP3IN_SHIFT               (7U)
28322 /*! EP3IN - Interrupt status register bit for the EP3 IN direction.
28323  */
28324 #define USBHSD_INTSTAT_EP3IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
28325 
28326 #define USBHSD_INTSTAT_EP4OUT_MASK               (0x100U)
28327 #define USBHSD_INTSTAT_EP4OUT_SHIFT              (8U)
28328 /*! EP4OUT - Interrupt status register bit for the EP4 OUT direction.
28329  */
28330 #define USBHSD_INTSTAT_EP4OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
28331 
28332 #define USBHSD_INTSTAT_EP4IN_MASK                (0x200U)
28333 #define USBHSD_INTSTAT_EP4IN_SHIFT               (9U)
28334 /*! EP4IN - Interrupt status register bit for the EP4 IN direction.
28335  */
28336 #define USBHSD_INTSTAT_EP4IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
28337 
28338 #define USBHSD_INTSTAT_EP5OUT_MASK               (0x400U)
28339 #define USBHSD_INTSTAT_EP5OUT_SHIFT              (10U)
28340 /*! EP5OUT - Interrupt status register bit for the EP5 OUT direction.
28341  */
28342 #define USBHSD_INTSTAT_EP5OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
28343 
28344 #define USBHSD_INTSTAT_EP5IN_MASK                (0x800U)
28345 #define USBHSD_INTSTAT_EP5IN_SHIFT               (11U)
28346 /*! EP5IN - Interrupt status register bit for the EP5 IN direction.
28347  */
28348 #define USBHSD_INTSTAT_EP5IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
28349 
28350 #define USBHSD_INTSTAT_FRAME_INT_MASK            (0x40000000U)
28351 #define USBHSD_INTSTAT_FRAME_INT_SHIFT           (30U)
28352 /*! FRAME_INT - Frame interrupt.
28353  */
28354 #define USBHSD_INTSTAT_FRAME_INT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
28355 
28356 #define USBHSD_INTSTAT_DEV_INT_MASK              (0x80000000U)
28357 #define USBHSD_INTSTAT_DEV_INT_SHIFT             (31U)
28358 /*! DEV_INT - Device status interrupt.
28359  */
28360 #define USBHSD_INTSTAT_DEV_INT(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
28361 /*! @} */
28362 
28363 /*! @name INTEN - USB interrupt enable register */
28364 /*! @{ */
28365 
28366 #define USBHSD_INTEN_EP_INT_EN_MASK              (0xFFFU)
28367 #define USBHSD_INTEN_EP_INT_EN_SHIFT             (0U)
28368 /*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
28369  *    interrupt is generated on the interrupt line.
28370  */
28371 #define USBHSD_INTEN_EP_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
28372 
28373 #define USBHSD_INTEN_FRAME_INT_EN_MASK           (0x40000000U)
28374 #define USBHSD_INTEN_FRAME_INT_EN_SHIFT          (30U)
28375 /*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
28376  *    interrupt is generated on the interrupt line.
28377  */
28378 #define USBHSD_INTEN_FRAME_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
28379 
28380 #define USBHSD_INTEN_DEV_INT_EN_MASK             (0x80000000U)
28381 #define USBHSD_INTEN_DEV_INT_EN_SHIFT            (31U)
28382 /*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
28383  *    interrupt is generated on the interrupt line.
28384  */
28385 #define USBHSD_INTEN_DEV_INT_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
28386 /*! @} */
28387 
28388 /*! @name INTSETSTAT - USB set interrupt status register */
28389 /*! @{ */
28390 
28391 #define USBHSD_INTSETSTAT_EP_SET_INT_MASK        (0xFFFU)
28392 #define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT       (0U)
28393 /*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
28394  */
28395 #define USBHSD_INTSETSTAT_EP_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
28396 
28397 #define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK     (0x40000000U)
28398 #define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT    (30U)
28399 /*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
28400  */
28401 #define USBHSD_INTSETSTAT_FRAME_SET_INT(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
28402 
28403 #define USBHSD_INTSETSTAT_DEV_SET_INT_MASK       (0x80000000U)
28404 #define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT      (31U)
28405 /*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
28406  */
28407 #define USBHSD_INTSETSTAT_DEV_SET_INT(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
28408 /*! @} */
28409 
28410 /*! @name EPTOGGLE - USB Endpoint toggle register */
28411 /*! @{ */
28412 
28413 #define USBHSD_EPTOGGLE_TOGGLE_MASK              (0x3FFFFFFFU)
28414 #define USBHSD_EPTOGGLE_TOGGLE_SHIFT             (0U)
28415 /*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
28416  */
28417 #define USBHSD_EPTOGGLE_TOGGLE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
28418 /*! @} */
28419 
28420 
28421 /*!
28422  * @}
28423  */ /* end of group USBHSD_Register_Masks */
28424 
28425 
28426 /* USBHSD - Peripheral instance base addresses */
28427 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
28428   /** Peripheral USBHSD base address */
28429   #define USBHSD_BASE                              (0x50094000u)
28430   /** Peripheral USBHSD base address */
28431   #define USBHSD_BASE_NS                           (0x40094000u)
28432   /** Peripheral USBHSD base pointer */
28433   #define USBHSD                                   ((USBHSD_Type *)USBHSD_BASE)
28434   /** Peripheral USBHSD base pointer */
28435   #define USBHSD_NS                                ((USBHSD_Type *)USBHSD_BASE_NS)
28436   /** Array initializer of USBHSD peripheral base addresses */
28437   #define USBHSD_BASE_ADDRS                        { USBHSD_BASE }
28438   /** Array initializer of USBHSD peripheral base pointers */
28439   #define USBHSD_BASE_PTRS                         { USBHSD }
28440   /** Array initializer of USBHSD peripheral base addresses */
28441   #define USBHSD_BASE_ADDRS_NS                     { USBHSD_BASE_NS }
28442   /** Array initializer of USBHSD peripheral base pointers */
28443   #define USBHSD_BASE_PTRS_NS                      { USBHSD_NS }
28444 #else
28445   /** Peripheral USBHSD base address */
28446   #define USBHSD_BASE                              (0x40094000u)
28447   /** Peripheral USBHSD base pointer */
28448   #define USBHSD                                   ((USBHSD_Type *)USBHSD_BASE)
28449   /** Array initializer of USBHSD peripheral base addresses */
28450   #define USBHSD_BASE_ADDRS                        { USBHSD_BASE }
28451   /** Array initializer of USBHSD peripheral base pointers */
28452   #define USBHSD_BASE_PTRS                         { USBHSD }
28453 #endif
28454 /** Interrupt vectors for the USBHSD peripheral type */
28455 #define USBHSD_IRQS                              { USB1_IRQn }
28456 #define USBHSD_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
28457 
28458 /*!
28459  * @}
28460  */ /* end of group USBHSD_Peripheral_Access_Layer */
28461 
28462 
28463 /* ----------------------------------------------------------------------------
28464    -- USBHSH Peripheral Access Layer
28465    ---------------------------------------------------------------------------- */
28466 
28467 /*!
28468  * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
28469  * @{
28470  */
28471 
28472 /** USBHSH - Register Layout Typedef */
28473 typedef struct {
28474   __I  uint32_t CAPLENGTH_CHIPID;                  /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
28475   __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x4 */
28476        uint8_t RESERVED_0[4];
28477   __IO uint32_t FLADJ_FRINDEX;                     /**< Frame Length Adjustment, offset: 0xC */
28478   __IO uint32_t ATLPTD;                            /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
28479   __IO uint32_t ISOPTD;                            /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
28480   __IO uint32_t INTPTD;                            /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
28481   __IO uint32_t DATAPAYLOAD;                       /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
28482   __IO uint32_t USBCMD;                            /**< USB Command register, offset: 0x20 */
28483   __IO uint32_t USBSTS;                            /**< USB Interrupt Status register, offset: 0x24 */
28484   __IO uint32_t USBINTR;                           /**< USB Interrupt Enable register, offset: 0x28 */
28485   __IO uint32_t PORTSC1;                           /**< Port Status and Control register, offset: 0x2C */
28486   __IO uint32_t ATLPTDD;                           /**< Done map for each ATL PTD, offset: 0x30 */
28487   __IO uint32_t ATLPTDS;                           /**< Skip map for each ATL PTD, offset: 0x34 */
28488   __IO uint32_t ISOPTDD;                           /**< Done map for each ISO PTD, offset: 0x38 */
28489   __IO uint32_t ISOPTDS;                           /**< Skip map for each ISO PTD, offset: 0x3C */
28490   __IO uint32_t INTPTDD;                           /**< Done map for each INT PTD, offset: 0x40 */
28491   __IO uint32_t INTPTDS;                           /**< Skip map for each INT PTD, offset: 0x44 */
28492   __IO uint32_t LASTPTD;                           /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
28493        uint8_t RESERVED_1[4];
28494   __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
28495 } USBHSH_Type;
28496 
28497 /* ----------------------------------------------------------------------------
28498    -- USBHSH Register Masks
28499    ---------------------------------------------------------------------------- */
28500 
28501 /*!
28502  * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
28503  * @{
28504  */
28505 
28506 /*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
28507 /*! @{ */
28508 
28509 #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK   (0xFFU)
28510 #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT  (0U)
28511 /*! CAPLENGTH - Capability Length: This is used as an offset.
28512  */
28513 #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
28514 
28515 #define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK      (0xFFFF0000U)
28516 #define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT     (16U)
28517 /*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major
28518  *    revision [23:16] = Minor revision Major revisions used: 0x01: USB2.
28519  */
28520 #define USBHSH_CAPLENGTH_CHIPID_CHIPID(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
28521 /*! @} */
28522 
28523 /*! @name HCSPARAMS - Host Controller Structural Parameters */
28524 /*! @{ */
28525 
28526 #define USBHSH_HCSPARAMS_N_PORTS_MASK            (0xFU)
28527 #define USBHSH_HCSPARAMS_N_PORTS_SHIFT           (0U)
28528 /*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller.
28529  */
28530 #define USBHSH_HCSPARAMS_N_PORTS(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
28531 
28532 #define USBHSH_HCSPARAMS_PPC_MASK                (0x10U)
28533 #define USBHSH_HCSPARAMS_PPC_SHIFT               (4U)
28534 /*! PPC - This field indicates whether the host controller implementation includes port power control.
28535  */
28536 #define USBHSH_HCSPARAMS_PPC(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
28537 
28538 #define USBHSH_HCSPARAMS_P_INDICATOR_MASK        (0x10000U)
28539 #define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT       (16U)
28540 /*! P_INDICATOR - This bit indicates whether the ports support port indicator control.
28541  */
28542 #define USBHSH_HCSPARAMS_P_INDICATOR(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
28543 /*! @} */
28544 
28545 /*! @name FLADJ_FRINDEX - Frame Length Adjustment */
28546 /*! @{ */
28547 
28548 #define USBHSH_FLADJ_FRINDEX_FLADJ_MASK          (0x3FU)
28549 #define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT         (0U)
28550 /*! FLADJ - Frame Length Timing Value.
28551  */
28552 #define USBHSH_FLADJ_FRINDEX_FLADJ(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
28553 
28554 #define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK        (0x3FFF0000U)
28555 #define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT       (16U)
28556 /*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet.
28557  */
28558 #define USBHSH_FLADJ_FRINDEX_FRINDEX(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
28559 /*! @} */
28560 
28561 /*! @name ATLPTD - Memory base address where ATL PTD0 is stored */
28562 /*! @{ */
28563 
28564 #define USBHSH_ATLPTD_ATL_CUR_MASK               (0x1F0U)
28565 #define USBHSH_ATLPTD_ATL_CUR_SHIFT              (4U)
28566 /*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list.
28567  */
28568 #define USBHSH_ATLPTD_ATL_CUR(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK)
28569 
28570 #define USBHSH_ATLPTD_ATL_BASE_MASK              (0xFFFFFE00U)
28571 #define USBHSH_ATLPTD_ATL_BASE_SHIFT             (9U)
28572 /*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list.
28573  */
28574 #define USBHSH_ATLPTD_ATL_BASE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK)
28575 /*! @} */
28576 
28577 /*! @name ISOPTD - Memory base address where ISO PTD0 is stored */
28578 /*! @{ */
28579 
28580 #define USBHSH_ISOPTD_ISO_FIRST_MASK             (0x3E0U)
28581 #define USBHSH_ISOPTD_ISO_FIRST_SHIFT            (5U)
28582 /*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list.
28583  */
28584 #define USBHSH_ISOPTD_ISO_FIRST(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK)
28585 
28586 #define USBHSH_ISOPTD_ISO_BASE_MASK              (0xFFFFFC00U)
28587 #define USBHSH_ISOPTD_ISO_BASE_SHIFT             (10U)
28588 /*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list.
28589  */
28590 #define USBHSH_ISOPTD_ISO_BASE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK)
28591 /*! @} */
28592 
28593 /*! @name INTPTD - Memory base address where INT PTD0 is stored */
28594 /*! @{ */
28595 
28596 #define USBHSH_INTPTD_INT_FIRST_MASK             (0x3E0U)
28597 #define USBHSH_INTPTD_INT_FIRST_SHIFT            (5U)
28598 /*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list.
28599  */
28600 #define USBHSH_INTPTD_INT_FIRST(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK)
28601 
28602 #define USBHSH_INTPTD_INT_BASE_MASK              (0xFFFFFC00U)
28603 #define USBHSH_INTPTD_INT_BASE_SHIFT             (10U)
28604 /*! INT_BASE - Base address to be used by the hardware to find the start of the INT list.
28605  */
28606 #define USBHSH_INTPTD_INT_BASE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK)
28607 /*! @} */
28608 
28609 /*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */
28610 /*! @{ */
28611 
28612 #define USBHSH_DATAPAYLOAD_DAT_BASE_MASK         (0xFFFF0000U)
28613 #define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT        (16U)
28614 /*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section.
28615  */
28616 #define USBHSH_DATAPAYLOAD_DAT_BASE(x)           (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK)
28617 /*! @} */
28618 
28619 /*! @name USBCMD - USB Command register */
28620 /*! @{ */
28621 
28622 #define USBHSH_USBCMD_RS_MASK                    (0x1U)
28623 #define USBHSH_USBCMD_RS_SHIFT                   (0U)
28624 /*! RS - Run/Stop: 1b = Run.
28625  */
28626 #define USBHSH_USBCMD_RS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
28627 
28628 #define USBHSH_USBCMD_HCRESET_MASK               (0x2U)
28629 #define USBHSH_USBCMD_HCRESET_SHIFT              (1U)
28630 /*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller.
28631  */
28632 #define USBHSH_USBCMD_HCRESET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
28633 
28634 #define USBHSH_USBCMD_FLS_MASK                   (0xCU)
28635 #define USBHSH_USBCMD_FLS_SHIFT                  (2U)
28636 /*! FLS - Frame List Size: This field specifies the size of the frame list.
28637  */
28638 #define USBHSH_USBCMD_FLS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
28639 
28640 #define USBHSH_USBCMD_LHCR_MASK                  (0x80U)
28641 #define USBHSH_USBCMD_LHCR_SHIFT                 (7U)
28642 /*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host
28643  *    controller without affecting the state of the ports.
28644  */
28645 #define USBHSH_USBCMD_LHCR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
28646 
28647 #define USBHSH_USBCMD_ATL_EN_MASK                (0x100U)
28648 #define USBHSH_USBCMD_ATL_EN_SHIFT               (8U)
28649 /*! ATL_EN - ATL List enabled.
28650  */
28651 #define USBHSH_USBCMD_ATL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
28652 
28653 #define USBHSH_USBCMD_ISO_EN_MASK                (0x200U)
28654 #define USBHSH_USBCMD_ISO_EN_SHIFT               (9U)
28655 /*! ISO_EN - ISO List enabled.
28656  */
28657 #define USBHSH_USBCMD_ISO_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
28658 
28659 #define USBHSH_USBCMD_INT_EN_MASK                (0x400U)
28660 #define USBHSH_USBCMD_INT_EN_SHIFT               (10U)
28661 /*! INT_EN - INT List enabled.
28662  */
28663 #define USBHSH_USBCMD_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
28664 /*! @} */
28665 
28666 /*! @name USBSTS - USB Interrupt Status register */
28667 /*! @{ */
28668 
28669 #define USBHSH_USBSTS_PCD_MASK                   (0x4U)
28670 #define USBHSH_USBSTS_PCD_SHIFT                  (2U)
28671 /*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a
28672  *    change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a
28673  *    result of a J-K transition detected on a suspended port.
28674  */
28675 #define USBHSH_USBSTS_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
28676 
28677 #define USBHSH_USBSTS_FLR_MASK                   (0x8U)
28678 #define USBHSH_USBSTS_FLR_SHIFT                  (3U)
28679 /*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list
28680  *    index rolls over its maximum value to 0.
28681  */
28682 #define USBHSH_USBSTS_FLR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
28683 
28684 #define USBHSH_USBSTS_ATL_IRQ_MASK               (0x10000U)
28685 #define USBHSH_USBSTS_ATL_IRQ_SHIFT              (16U)
28686 /*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed.
28687  */
28688 #define USBHSH_USBSTS_ATL_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
28689 
28690 #define USBHSH_USBSTS_ISO_IRQ_MASK               (0x20000U)
28691 #define USBHSH_USBSTS_ISO_IRQ_SHIFT              (17U)
28692 /*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed.
28693  */
28694 #define USBHSH_USBSTS_ISO_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
28695 
28696 #define USBHSH_USBSTS_INT_IRQ_MASK               (0x40000U)
28697 #define USBHSH_USBSTS_INT_IRQ_SHIFT              (18U)
28698 /*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed.
28699  */
28700 #define USBHSH_USBSTS_INT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
28701 
28702 #define USBHSH_USBSTS_SOF_IRQ_MASK               (0x80000U)
28703 #define USBHSH_USBSTS_SOF_IRQ_SHIFT              (19U)
28704 /*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set.
28705  */
28706 #define USBHSH_USBSTS_SOF_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
28707 /*! @} */
28708 
28709 /*! @name USBINTR - USB Interrupt Enable register */
28710 /*! @{ */
28711 
28712 #define USBHSH_USBINTR_PCDE_MASK                 (0x4U)
28713 #define USBHSH_USBINTR_PCDE_SHIFT                (2U)
28714 /*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable.
28715  */
28716 #define USBHSH_USBINTR_PCDE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
28717 
28718 #define USBHSH_USBINTR_FLRE_MASK                 (0x8U)
28719 #define USBHSH_USBINTR_FLRE_SHIFT                (3U)
28720 /*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable.
28721  */
28722 #define USBHSH_USBINTR_FLRE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
28723 
28724 #define USBHSH_USBINTR_ATL_IRQ_E_MASK            (0x10000U)
28725 #define USBHSH_USBINTR_ATL_IRQ_E_SHIFT           (16U)
28726 /*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable.
28727  */
28728 #define USBHSH_USBINTR_ATL_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
28729 
28730 #define USBHSH_USBINTR_ISO_IRQ_E_MASK            (0x20000U)
28731 #define USBHSH_USBINTR_ISO_IRQ_E_SHIFT           (17U)
28732 /*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable.
28733  */
28734 #define USBHSH_USBINTR_ISO_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
28735 
28736 #define USBHSH_USBINTR_INT_IRQ_E_MASK            (0x40000U)
28737 #define USBHSH_USBINTR_INT_IRQ_E_SHIFT           (18U)
28738 /*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable.
28739  */
28740 #define USBHSH_USBINTR_INT_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
28741 
28742 #define USBHSH_USBINTR_SOF_E_MASK                (0x80000U)
28743 #define USBHSH_USBINTR_SOF_E_SHIFT               (19U)
28744 /*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable.
28745  */
28746 #define USBHSH_USBINTR_SOF_E(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
28747 /*! @} */
28748 
28749 /*! @name PORTSC1 - Port Status and Control register */
28750 /*! @{ */
28751 
28752 #define USBHSH_PORTSC1_CCS_MASK                  (0x1U)
28753 #define USBHSH_PORTSC1_CCS_SHIFT                 (0U)
28754 /*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port.
28755  */
28756 #define USBHSH_PORTSC1_CCS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
28757 
28758 #define USBHSH_PORTSC1_CSC_MASK                  (0x2U)
28759 #define USBHSH_PORTSC1_CSC_SHIFT                 (1U)
28760 /*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed.
28761  */
28762 #define USBHSH_PORTSC1_CSC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
28763 
28764 #define USBHSH_PORTSC1_PED_MASK                  (0x4U)
28765 #define USBHSH_PORTSC1_PED_SHIFT                 (2U)
28766 /*! PED - Port Enabled/Disabled.
28767  */
28768 #define USBHSH_PORTSC1_PED(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
28769 
28770 #define USBHSH_PORTSC1_PEDC_MASK                 (0x8U)
28771 #define USBHSH_PORTSC1_PEDC_SHIFT                (3U)
28772 /*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed.
28773  */
28774 #define USBHSH_PORTSC1_PEDC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
28775 
28776 #define USBHSH_PORTSC1_OCA_MASK                  (0x10U)
28777 #define USBHSH_PORTSC1_OCA_SHIFT                 (4U)
28778 /*! OCA - Over-current active: Logic 1 means that this port has an over-current condition.
28779  */
28780 #define USBHSH_PORTSC1_OCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
28781 
28782 #define USBHSH_PORTSC1_OCC_MASK                  (0x20U)
28783 #define USBHSH_PORTSC1_OCC_SHIFT                 (5U)
28784 /*! OCC - Over-current change: Logic 1 means that the value of OCA has changed.
28785  */
28786 #define USBHSH_PORTSC1_OCC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
28787 
28788 #define USBHSH_PORTSC1_FPR_MASK                  (0x40U)
28789 #define USBHSH_PORTSC1_FPR_SHIFT                 (6U)
28790 /*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port.
28791  */
28792 #define USBHSH_PORTSC1_FPR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
28793 
28794 #define USBHSH_PORTSC1_SUSP_MASK                 (0x80U)
28795 #define USBHSH_PORTSC1_SUSP_SHIFT                (7U)
28796 /*! SUSP - Suspend: Logic 1 means port is in the suspend state.
28797  */
28798 #define USBHSH_PORTSC1_SUSP(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
28799 
28800 #define USBHSH_PORTSC1_PR_MASK                   (0x100U)
28801 #define USBHSH_PORTSC1_PR_SHIFT                  (8U)
28802 /*! PR - Port Reset: Logic 1 means the port is in the reset state.
28803  */
28804 #define USBHSH_PORTSC1_PR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
28805 
28806 #define USBHSH_PORTSC1_LS_MASK                   (0xC00U)
28807 #define USBHSH_PORTSC1_LS_SHIFT                  (10U)
28808 /*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines.
28809  */
28810 #define USBHSH_PORTSC1_LS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
28811 
28812 #define USBHSH_PORTSC1_PP_MASK                   (0x1000U)
28813 #define USBHSH_PORTSC1_PP_SHIFT                  (12U)
28814 /*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register.
28815  */
28816 #define USBHSH_PORTSC1_PP(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
28817 
28818 #define USBHSH_PORTSC1_PIC_MASK                  (0xC000U)
28819 #define USBHSH_PORTSC1_PIC_SHIFT                 (14U)
28820 /*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the
28821  *    HCSPARAMS register is logic 0.
28822  */
28823 #define USBHSH_PORTSC1_PIC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
28824 
28825 #define USBHSH_PORTSC1_PTC_MASK                  (0xF0000U)
28826 #define USBHSH_PORTSC1_PTC_SHIFT                 (16U)
28827 /*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value.
28828  */
28829 #define USBHSH_PORTSC1_PTC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
28830 
28831 #define USBHSH_PORTSC1_PSPD_MASK                 (0x300000U)
28832 #define USBHSH_PORTSC1_PSPD_SHIFT                (20U)
28833 /*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved.
28834  */
28835 #define USBHSH_PORTSC1_PSPD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
28836 
28837 #define USBHSH_PORTSC1_WOO_MASK                  (0x400000U)
28838 #define USBHSH_PORTSC1_WOO_SHIFT                 (22U)
28839 /*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to
28840  *    overcurrent conditions as wake-up events.
28841  */
28842 #define USBHSH_PORTSC1_WOO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
28843 /*! @} */
28844 
28845 /*! @name ATLPTDD - Done map for each ATL PTD */
28846 /*! @{ */
28847 
28848 #define USBHSH_ATLPTDD_ATL_DONE_MASK             (0xFFFFFFFFU)
28849 #define USBHSH_ATLPTDD_ATL_DONE_SHIFT            (0U)
28850 /*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
28851  */
28852 #define USBHSH_ATLPTDD_ATL_DONE(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK)
28853 /*! @} */
28854 
28855 /*! @name ATLPTDS - Skip map for each ATL PTD */
28856 /*! @{ */
28857 
28858 #define USBHSH_ATLPTDS_ATL_SKIP_MASK             (0xFFFFFFFFU)
28859 #define USBHSH_ATLPTDS_ATL_SKIP_SHIFT            (0U)
28860 /*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
28861  *    skipped, independent of the V bit setting.
28862  */
28863 #define USBHSH_ATLPTDS_ATL_SKIP(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK)
28864 /*! @} */
28865 
28866 /*! @name ISOPTDD - Done map for each ISO PTD */
28867 /*! @{ */
28868 
28869 #define USBHSH_ISOPTDD_ISO_DONE_MASK             (0xFFFFFFFFU)
28870 #define USBHSH_ISOPTDD_ISO_DONE_SHIFT            (0U)
28871 /*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
28872  */
28873 #define USBHSH_ISOPTDD_ISO_DONE(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK)
28874 /*! @} */
28875 
28876 /*! @name ISOPTDS - Skip map for each ISO PTD */
28877 /*! @{ */
28878 
28879 #define USBHSH_ISOPTDS_ISO_SKIP_MASK             (0xFFFFFFFFU)
28880 #define USBHSH_ISOPTDS_ISO_SKIP_SHIFT            (0U)
28881 /*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
28882  */
28883 #define USBHSH_ISOPTDS_ISO_SKIP(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK)
28884 /*! @} */
28885 
28886 /*! @name INTPTDD - Done map for each INT PTD */
28887 /*! @{ */
28888 
28889 #define USBHSH_INTPTDD_INT_DONE_MASK             (0xFFFFFFFFU)
28890 #define USBHSH_INTPTDD_INT_DONE_SHIFT            (0U)
28891 /*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
28892  */
28893 #define USBHSH_INTPTDD_INT_DONE(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK)
28894 /*! @} */
28895 
28896 /*! @name INTPTDS - Skip map for each INT PTD */
28897 /*! @{ */
28898 
28899 #define USBHSH_INTPTDS_INT_SKIP_MASK             (0xFFFFFFFFU)
28900 #define USBHSH_INTPTDS_INT_SKIP_SHIFT            (0U)
28901 /*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
28902  *    skipped, independent of the V bit setting.
28903  */
28904 #define USBHSH_INTPTDS_INT_SKIP(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK)
28905 /*! @} */
28906 
28907 /*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */
28908 /*! @{ */
28909 
28910 #define USBHSH_LASTPTD_ATL_LAST_MASK             (0x1FU)
28911 #define USBHSH_LASTPTD_ATL_LAST_SHIFT            (0U)
28912 /*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed.
28913  */
28914 #define USBHSH_LASTPTD_ATL_LAST(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK)
28915 
28916 #define USBHSH_LASTPTD_ISO_LAST_MASK             (0x1F00U)
28917 #define USBHSH_LASTPTD_ISO_LAST_SHIFT            (8U)
28918 /*! ISO_LAST - This indicates the last PTD in the ISO list.
28919  */
28920 #define USBHSH_LASTPTD_ISO_LAST(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK)
28921 
28922 #define USBHSH_LASTPTD_INT_LAST_MASK             (0x1F0000U)
28923 #define USBHSH_LASTPTD_INT_LAST_SHIFT            (16U)
28924 /*! INT_LAST - This indicates the last PTD in the INT list.
28925  */
28926 #define USBHSH_LASTPTD_INT_LAST(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK)
28927 /*! @} */
28928 
28929 /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
28930 /*! @{ */
28931 
28932 #define USBHSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
28933 #define USBHSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
28934 /*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device.
28935  */
28936 #define USBHSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
28937 
28938 #define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK       (0x40000U)
28939 #define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT      (18U)
28940 /*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware.
28941  */
28942 #define USBHSH_PORTMODE_SW_CTRL_PDCOM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
28943 
28944 #define USBHSH_PORTMODE_SW_PDCOM_MASK            (0x80000U)
28945 #define USBHSH_PORTMODE_SW_PDCOM_SHIFT           (19U)
28946 /*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b.
28947  */
28948 #define USBHSH_PORTMODE_SW_PDCOM(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
28949 /*! @} */
28950 
28951 
28952 /*!
28953  * @}
28954  */ /* end of group USBHSH_Register_Masks */
28955 
28956 
28957 /* USBHSH - Peripheral instance base addresses */
28958 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
28959   /** Peripheral USBHSH base address */
28960   #define USBHSH_BASE                              (0x500A3000u)
28961   /** Peripheral USBHSH base address */
28962   #define USBHSH_BASE_NS                           (0x400A3000u)
28963   /** Peripheral USBHSH base pointer */
28964   #define USBHSH                                   ((USBHSH_Type *)USBHSH_BASE)
28965   /** Peripheral USBHSH base pointer */
28966   #define USBHSH_NS                                ((USBHSH_Type *)USBHSH_BASE_NS)
28967   /** Array initializer of USBHSH peripheral base addresses */
28968   #define USBHSH_BASE_ADDRS                        { USBHSH_BASE }
28969   /** Array initializer of USBHSH peripheral base pointers */
28970   #define USBHSH_BASE_PTRS                         { USBHSH }
28971   /** Array initializer of USBHSH peripheral base addresses */
28972   #define USBHSH_BASE_ADDRS_NS                     { USBHSH_BASE_NS }
28973   /** Array initializer of USBHSH peripheral base pointers */
28974   #define USBHSH_BASE_PTRS_NS                      { USBHSH_NS }
28975 #else
28976   /** Peripheral USBHSH base address */
28977   #define USBHSH_BASE                              (0x400A3000u)
28978   /** Peripheral USBHSH base pointer */
28979   #define USBHSH                                   ((USBHSH_Type *)USBHSH_BASE)
28980   /** Array initializer of USBHSH peripheral base addresses */
28981   #define USBHSH_BASE_ADDRS                        { USBHSH_BASE }
28982   /** Array initializer of USBHSH peripheral base pointers */
28983   #define USBHSH_BASE_PTRS                         { USBHSH }
28984 #endif
28985 /** Interrupt vectors for the USBHSH peripheral type */
28986 #define USBHSH_IRQS                              { USB1_IRQn }
28987 #define USBHSH_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
28988 
28989 /*!
28990  * @}
28991  */ /* end of group USBHSH_Peripheral_Access_Layer */
28992 
28993 
28994 /* ----------------------------------------------------------------------------
28995    -- USBPHY Peripheral Access Layer
28996    ---------------------------------------------------------------------------- */
28997 
28998 /*!
28999  * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
29000  * @{
29001  */
29002 
29003 /** USBPHY - Register Layout Typedef */
29004 typedef struct {
29005   __IO uint32_t PWD;                               /**< USB PHY Power-Down Register, offset: 0x0 */
29006   __IO uint32_t PWD_SET;                           /**< USB PHY Power-Down Register, offset: 0x4 */
29007   __IO uint32_t PWD_CLR;                           /**< USB PHY Power-Down Register, offset: 0x8 */
29008   __IO uint32_t PWD_TOG;                           /**< USB PHY Power-Down Register, offset: 0xC */
29009   __IO uint32_t TX;                                /**< USB PHY Transmitter Control Register, offset: 0x10 */
29010   __IO uint32_t TX_SET;                            /**< USB PHY Transmitter Control Register, offset: 0x14 */
29011   __IO uint32_t TX_CLR;                            /**< USB PHY Transmitter Control Register, offset: 0x18 */
29012   __IO uint32_t TX_TOG;                            /**< USB PHY Transmitter Control Register, offset: 0x1C */
29013   __IO uint32_t RX;                                /**< USB PHY Receiver Control Register, offset: 0x20 */
29014   __IO uint32_t RX_SET;                            /**< USB PHY Receiver Control Register, offset: 0x24 */
29015   __IO uint32_t RX_CLR;                            /**< USB PHY Receiver Control Register, offset: 0x28 */
29016   __IO uint32_t RX_TOG;                            /**< USB PHY Receiver Control Register, offset: 0x2C */
29017   __IO uint32_t CTRL;                              /**< USB PHY General Control Register, offset: 0x30 */
29018   __IO uint32_t CTRL_SET;                          /**< USB PHY General Control Register, offset: 0x34 */
29019   __IO uint32_t CTRL_CLR;                          /**< USB PHY General Control Register, offset: 0x38 */
29020   __IO uint32_t CTRL_TOG;                          /**< USB PHY General Control Register, offset: 0x3C */
29021   __I  uint32_t STATUS;                            /**< USB PHY Status Register, offset: 0x40 */
29022        uint8_t RESERVED_0[92];
29023   __IO uint32_t PLL_SIC;                           /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
29024   __IO uint32_t PLL_SIC_SET;                       /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
29025   __IO uint32_t PLL_SIC_CLR;                       /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
29026   __IO uint32_t PLL_SIC_TOG;                       /**< USB PHY PLL Control/Status Register, offset: 0xAC */
29027        uint8_t RESERVED_1[16];
29028   __IO uint32_t USB1_VBUS_DETECT;                  /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
29029   __IO uint32_t USB1_VBUS_DETECT_SET;              /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
29030   __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
29031   __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
29032        uint8_t RESERVED_2[48];
29033   __IO uint32_t ANACTRLr;                          /**< USB PHY Analog Control Register, offset: 0x100, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'ANACTRL' */
29034   __IO uint32_t ANACTRL_SET;                       /**< USB PHY Analog Control Register, offset: 0x104 */
29035   __IO uint32_t ANACTRL_CLR;                       /**< USB PHY Analog Control Register, offset: 0x108 */
29036   __IO uint32_t ANACTRL_TOG;                       /**< USB PHY Analog Control Register, offset: 0x10C */
29037 } USBPHY_Type;
29038 
29039 /* ----------------------------------------------------------------------------
29040    -- USBPHY Register Masks
29041    ---------------------------------------------------------------------------- */
29042 
29043 /*!
29044  * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
29045  * @{
29046  */
29047 
29048 /*! @name PWD - USB PHY Power-Down Register */
29049 /*! @{ */
29050 
29051 #define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
29052 #define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
29053 /*! TXPWDFS
29054  *  0b0..Normal operation.
29055  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
29056  */
29057 #define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
29058 
29059 #define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
29060 #define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
29061 /*! TXPWDIBIAS
29062  *  0b0..Normal operation.
29063  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
29064  */
29065 #define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
29066 
29067 #define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
29068 #define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
29069 /*! TXPWDV2I
29070  *  0b0..Normal operation.
29071  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
29072  */
29073 #define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
29074 
29075 #define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
29076 #define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
29077 /*! RXPWDENV
29078  *  0b0..Normal operation.
29079  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
29080  */
29081 #define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
29082 
29083 #define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
29084 #define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
29085 /*! RXPWD1PT1
29086  *  0b0..Normal operation.
29087  *  0b1..Power-down the USB full-speed differential receiver.
29088  */
29089 #define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
29090 
29091 #define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
29092 #define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
29093 /*! RXPWDDIFF
29094  *  0b0..Normal operation.
29095  *  0b1..Power-down the USB high-speed differential receive
29096  */
29097 #define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
29098 
29099 #define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
29100 #define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
29101 /*! RXPWDRX
29102  *  0b0..Normal operation.
29103  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
29104  */
29105 #define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
29106 /*! @} */
29107 
29108 /*! @name PWD_SET - USB PHY Power-Down Register */
29109 /*! @{ */
29110 
29111 #define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
29112 #define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
29113 /*! TXPWDFS
29114  *  0b0..Normal operation.
29115  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
29116  */
29117 #define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
29118 
29119 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
29120 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
29121 /*! TXPWDIBIAS
29122  *  0b0..Normal operation.
29123  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
29124  */
29125 #define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
29126 
29127 #define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
29128 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
29129 /*! TXPWDV2I
29130  *  0b0..Normal operation.
29131  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
29132  */
29133 #define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
29134 
29135 #define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
29136 #define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
29137 /*! RXPWDENV
29138  *  0b0..Normal operation.
29139  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
29140  */
29141 #define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
29142 
29143 #define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
29144 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
29145 /*! RXPWD1PT1
29146  *  0b0..Normal operation.
29147  *  0b1..Power-down the USB full-speed differential receiver.
29148  */
29149 #define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
29150 
29151 #define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
29152 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
29153 /*! RXPWDDIFF
29154  *  0b0..Normal operation.
29155  *  0b1..Power-down the USB high-speed differential receive
29156  */
29157 #define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
29158 
29159 #define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
29160 #define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
29161 /*! RXPWDRX
29162  *  0b0..Normal operation.
29163  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
29164  */
29165 #define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
29166 /*! @} */
29167 
29168 /*! @name PWD_CLR - USB PHY Power-Down Register */
29169 /*! @{ */
29170 
29171 #define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
29172 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
29173 /*! TXPWDFS
29174  *  0b0..Normal operation.
29175  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
29176  */
29177 #define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
29178 
29179 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
29180 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
29181 /*! TXPWDIBIAS
29182  *  0b0..Normal operation.
29183  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
29184  */
29185 #define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
29186 
29187 #define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
29188 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
29189 /*! TXPWDV2I
29190  *  0b0..Normal operation.
29191  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
29192  */
29193 #define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
29194 
29195 #define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
29196 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
29197 /*! RXPWDENV
29198  *  0b0..Normal operation.
29199  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
29200  */
29201 #define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
29202 
29203 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
29204 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
29205 /*! RXPWD1PT1
29206  *  0b0..Normal operation.
29207  *  0b1..Power-down the USB full-speed differential receiver.
29208  */
29209 #define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
29210 
29211 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
29212 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
29213 /*! RXPWDDIFF
29214  *  0b0..Normal operation.
29215  *  0b1..Power-down the USB high-speed differential receive
29216  */
29217 #define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
29218 
29219 #define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
29220 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
29221 /*! RXPWDRX
29222  *  0b0..Normal operation.
29223  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
29224  */
29225 #define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
29226 /*! @} */
29227 
29228 /*! @name PWD_TOG - USB PHY Power-Down Register */
29229 /*! @{ */
29230 
29231 #define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
29232 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
29233 /*! TXPWDFS
29234  *  0b0..Normal operation.
29235  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
29236  */
29237 #define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
29238 
29239 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
29240 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
29241 /*! TXPWDIBIAS
29242  *  0b0..Normal operation.
29243  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
29244  */
29245 #define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
29246 
29247 #define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
29248 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
29249 /*! TXPWDV2I
29250  *  0b0..Normal operation.
29251  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
29252  */
29253 #define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
29254 
29255 #define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
29256 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
29257 /*! RXPWDENV
29258  *  0b0..Normal operation.
29259  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
29260  */
29261 #define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
29262 
29263 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
29264 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
29265 /*! RXPWD1PT1
29266  *  0b0..Normal operation.
29267  *  0b1..Power-down the USB full-speed differential receiver.
29268  */
29269 #define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
29270 
29271 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
29272 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
29273 /*! RXPWDDIFF
29274  *  0b0..Normal operation.
29275  *  0b1..Power-down the USB high-speed differential receive
29276  */
29277 #define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
29278 
29279 #define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
29280 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
29281 /*! RXPWDRX
29282  *  0b0..Normal operation.
29283  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
29284  */
29285 #define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
29286 /*! @} */
29287 
29288 /*! @name TX - USB PHY Transmitter Control Register */
29289 /*! @{ */
29290 
29291 #define USBPHY_TX_D_CAL_MASK                     (0xFU)
29292 #define USBPHY_TX_D_CAL_SHIFT                    (0U)
29293 /*! D_CAL
29294  *  0b0000..Maximum current, approximately 19% above nominal.
29295  *  0b0111..Nominal
29296  *  0b1111..Minimum current, approximately 19% below nominal.
29297  */
29298 #define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
29299 
29300 #define USBPHY_TX_TXCAL45DM_MASK                 (0xF00U)
29301 #define USBPHY_TX_TXCAL45DM_SHIFT                (8U)
29302 #define USBPHY_TX_TXCAL45DM(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
29303 
29304 #define USBPHY_TX_TXENCAL45DN_MASK               (0x2000U)
29305 #define USBPHY_TX_TXENCAL45DN_SHIFT              (13U)
29306 #define USBPHY_TX_TXENCAL45DN(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK)
29307 
29308 #define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
29309 #define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
29310 #define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
29311 
29312 #define USBPHY_TX_TXENCAL45DP_MASK               (0x200000U)
29313 #define USBPHY_TX_TXENCAL45DP_SHIFT              (21U)
29314 #define USBPHY_TX_TXENCAL45DP(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK)
29315 /*! @} */
29316 
29317 /*! @name TX_SET - USB PHY Transmitter Control Register */
29318 /*! @{ */
29319 
29320 #define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
29321 #define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
29322 /*! D_CAL
29323  *  0b0000..Maximum current, approximately 19% above nominal.
29324  *  0b0111..Nominal
29325  *  0b1111..Minimum current, approximately 19% below nominal.
29326  */
29327 #define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
29328 
29329 #define USBPHY_TX_SET_TXCAL45DM_MASK             (0xF00U)
29330 #define USBPHY_TX_SET_TXCAL45DM_SHIFT            (8U)
29331 #define USBPHY_TX_SET_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
29332 
29333 #define USBPHY_TX_SET_TXENCAL45DN_MASK           (0x2000U)
29334 #define USBPHY_TX_SET_TXENCAL45DN_SHIFT          (13U)
29335 #define USBPHY_TX_SET_TXENCAL45DN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK)
29336 
29337 #define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
29338 #define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
29339 #define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
29340 
29341 #define USBPHY_TX_SET_TXENCAL45DP_MASK           (0x200000U)
29342 #define USBPHY_TX_SET_TXENCAL45DP_SHIFT          (21U)
29343 #define USBPHY_TX_SET_TXENCAL45DP(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK)
29344 /*! @} */
29345 
29346 /*! @name TX_CLR - USB PHY Transmitter Control Register */
29347 /*! @{ */
29348 
29349 #define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
29350 #define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
29351 /*! D_CAL
29352  *  0b0000..Maximum current, approximately 19% above nominal.
29353  *  0b0111..Nominal
29354  *  0b1111..Minimum current, approximately 19% below nominal.
29355  */
29356 #define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
29357 
29358 #define USBPHY_TX_CLR_TXCAL45DM_MASK             (0xF00U)
29359 #define USBPHY_TX_CLR_TXCAL45DM_SHIFT            (8U)
29360 #define USBPHY_TX_CLR_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
29361 
29362 #define USBPHY_TX_CLR_TXENCAL45DN_MASK           (0x2000U)
29363 #define USBPHY_TX_CLR_TXENCAL45DN_SHIFT          (13U)
29364 #define USBPHY_TX_CLR_TXENCAL45DN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK)
29365 
29366 #define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
29367 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
29368 #define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
29369 
29370 #define USBPHY_TX_CLR_TXENCAL45DP_MASK           (0x200000U)
29371 #define USBPHY_TX_CLR_TXENCAL45DP_SHIFT          (21U)
29372 #define USBPHY_TX_CLR_TXENCAL45DP(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK)
29373 /*! @} */
29374 
29375 /*! @name TX_TOG - USB PHY Transmitter Control Register */
29376 /*! @{ */
29377 
29378 #define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
29379 #define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
29380 /*! D_CAL
29381  *  0b0000..Maximum current, approximately 19% above nominal.
29382  *  0b0111..Nominal
29383  *  0b1111..Minimum current, approximately 19% below nominal.
29384  */
29385 #define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
29386 
29387 #define USBPHY_TX_TOG_TXCAL45DM_MASK             (0xF00U)
29388 #define USBPHY_TX_TOG_TXCAL45DM_SHIFT            (8U)
29389 #define USBPHY_TX_TOG_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
29390 
29391 #define USBPHY_TX_TOG_TXENCAL45DN_MASK           (0x2000U)
29392 #define USBPHY_TX_TOG_TXENCAL45DN_SHIFT          (13U)
29393 #define USBPHY_TX_TOG_TXENCAL45DN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK)
29394 
29395 #define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
29396 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
29397 #define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
29398 
29399 #define USBPHY_TX_TOG_TXENCAL45DP_MASK           (0x200000U)
29400 #define USBPHY_TX_TOG_TXENCAL45DP_SHIFT          (21U)
29401 #define USBPHY_TX_TOG_TXENCAL45DP(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK)
29402 /*! @} */
29403 
29404 /*! @name RX - USB PHY Receiver Control Register */
29405 /*! @{ */
29406 
29407 #define USBPHY_RX_ENVADJ_MASK                    (0x7U)
29408 #define USBPHY_RX_ENVADJ_SHIFT                   (0U)
29409 /*! ENVADJ
29410  *  0b000..Trip-Level Voltage is 0.1000 V
29411  *  0b001..Trip-Level Voltage is 0.1125 V
29412  *  0b010..Trip-Level Voltage is 0.1250 V
29413  *  0b011..Trip-Level Voltage is 0.0875 V
29414  *  0b100..reserved
29415  *  0b101..reserved
29416  *  0b110..reserved
29417  *  0b111..reserved
29418  */
29419 #define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
29420 
29421 #define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
29422 #define USBPHY_RX_DISCONADJ_SHIFT                (4U)
29423 /*! DISCONADJ
29424  *  0b000..Trip-Level Voltage is 0.56875 V
29425  *  0b001..Trip-Level Voltage is 0.55000 V
29426  *  0b010..Trip-Level Voltage is 0.58125 V
29427  *  0b011..Trip-Level Voltage is 0.60000 V
29428  *  0b100..reserved
29429  *  0b101..reserved
29430  *  0b110..reserved
29431  *  0b111..reserved
29432  */
29433 #define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
29434 
29435 #define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
29436 #define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
29437 /*! RXDBYPASS
29438  *  0b0..Normal operation.
29439  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
29440  */
29441 #define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
29442 /*! @} */
29443 
29444 /*! @name RX_SET - USB PHY Receiver Control Register */
29445 /*! @{ */
29446 
29447 #define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
29448 #define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
29449 /*! ENVADJ
29450  *  0b000..Trip-Level Voltage is 0.1000 V
29451  *  0b001..Trip-Level Voltage is 0.1125 V
29452  *  0b010..Trip-Level Voltage is 0.1250 V
29453  *  0b011..Trip-Level Voltage is 0.0875 V
29454  *  0b100..reserved
29455  *  0b101..reserved
29456  *  0b110..reserved
29457  *  0b111..reserved
29458  */
29459 #define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
29460 
29461 #define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
29462 #define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
29463 /*! DISCONADJ
29464  *  0b000..Trip-Level Voltage is 0.56875 V
29465  *  0b001..Trip-Level Voltage is 0.55000 V
29466  *  0b010..Trip-Level Voltage is 0.58125 V
29467  *  0b011..Trip-Level Voltage is 0.60000 V
29468  *  0b100..reserved
29469  *  0b101..reserved
29470  *  0b110..reserved
29471  *  0b111..reserved
29472  */
29473 #define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
29474 
29475 #define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
29476 #define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
29477 /*! RXDBYPASS
29478  *  0b0..Normal operation.
29479  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
29480  */
29481 #define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
29482 /*! @} */
29483 
29484 /*! @name RX_CLR - USB PHY Receiver Control Register */
29485 /*! @{ */
29486 
29487 #define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
29488 #define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
29489 /*! ENVADJ
29490  *  0b000..Trip-Level Voltage is 0.1000 V
29491  *  0b001..Trip-Level Voltage is 0.1125 V
29492  *  0b010..Trip-Level Voltage is 0.1250 V
29493  *  0b011..Trip-Level Voltage is 0.0875 V
29494  *  0b100..reserved
29495  *  0b101..reserved
29496  *  0b110..reserved
29497  *  0b111..reserved
29498  */
29499 #define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
29500 
29501 #define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
29502 #define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
29503 /*! DISCONADJ
29504  *  0b000..Trip-Level Voltage is 0.56875 V
29505  *  0b001..Trip-Level Voltage is 0.55000 V
29506  *  0b010..Trip-Level Voltage is 0.58125 V
29507  *  0b011..Trip-Level Voltage is 0.60000 V
29508  *  0b100..reserved
29509  *  0b101..reserved
29510  *  0b110..reserved
29511  *  0b111..reserved
29512  */
29513 #define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
29514 
29515 #define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
29516 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
29517 /*! RXDBYPASS
29518  *  0b0..Normal operation.
29519  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
29520  */
29521 #define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
29522 /*! @} */
29523 
29524 /*! @name RX_TOG - USB PHY Receiver Control Register */
29525 /*! @{ */
29526 
29527 #define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
29528 #define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
29529 /*! ENVADJ
29530  *  0b000..Trip-Level Voltage is 0.1000 V
29531  *  0b001..Trip-Level Voltage is 0.1125 V
29532  *  0b010..Trip-Level Voltage is 0.1250 V
29533  *  0b011..Trip-Level Voltage is 0.0875 V
29534  *  0b100..reserved
29535  *  0b101..reserved
29536  *  0b110..reserved
29537  *  0b111..reserved
29538  */
29539 #define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
29540 
29541 #define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
29542 #define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
29543 /*! DISCONADJ
29544  *  0b000..Trip-Level Voltage is 0.56875 V
29545  *  0b001..Trip-Level Voltage is 0.55000 V
29546  *  0b010..Trip-Level Voltage is 0.58125 V
29547  *  0b011..Trip-Level Voltage is 0.60000 V
29548  *  0b100..reserved
29549  *  0b101..reserved
29550  *  0b110..reserved
29551  *  0b111..reserved
29552  */
29553 #define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
29554 
29555 #define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
29556 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
29557 /*! RXDBYPASS
29558  *  0b0..Normal operation.
29559  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
29560  */
29561 #define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
29562 /*! @} */
29563 
29564 /*! @name CTRL - USB PHY General Control Register */
29565 /*! @{ */
29566 
29567 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
29568 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
29569 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
29570 
29571 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         (0x4U)
29572 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        (2U)
29573 #define USBPHY_CTRL_ENIRQHOSTDISCON(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
29574 
29575 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
29576 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
29577 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
29578 
29579 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK          (0x10U)
29580 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT         (4U)
29581 /*! ENDEVPLUGINDET
29582  *  0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
29583  *  0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
29584  */
29585 #define USBPHY_CTRL_ENDEVPLUGINDET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
29586 
29587 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      (0x20U)
29588 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     (5U)
29589 #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
29590 
29591 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         (0x100U)
29592 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        (8U)
29593 #define USBPHY_CTRL_RESUMEIRQSTICKY(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
29594 
29595 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       (0x200U)
29596 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      (9U)
29597 #define USBPHY_CTRL_ENIRQRESUMEDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
29598 
29599 #define USBPHY_CTRL_RESUME_IRQ_MASK              (0x400U)
29600 #define USBPHY_CTRL_RESUME_IRQ_SHIFT             (10U)
29601 #define USBPHY_CTRL_RESUME_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
29602 
29603 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
29604 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
29605 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
29606 
29607 #define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
29608 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
29609 #define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
29610 
29611 #define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
29612 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
29613 #define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
29614 
29615 #define USBPHY_CTRL_ENIRQWAKEUP_MASK             (0x10000U)
29616 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            (16U)
29617 #define USBPHY_CTRL_ENIRQWAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
29618 
29619 #define USBPHY_CTRL_WAKEUP_IRQ_MASK              (0x20000U)
29620 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             (17U)
29621 #define USBPHY_CTRL_WAKEUP_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
29622 
29623 #define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
29624 #define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
29625 #define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
29626 
29627 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
29628 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
29629 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
29630 
29631 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
29632 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
29633 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
29634 
29635 #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK          (0x200000U)
29636 #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT         (21U)
29637 #define USBPHY_CTRL_ENDPDMCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
29638 
29639 #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK          (0x800000U)
29640 #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT         (23U)
29641 #define USBPHY_CTRL_ENVBUSCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
29642 
29643 #define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK    (0x2000000U)
29644 #define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT   (25U)
29645 #define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK)
29646 
29647 #define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK       (0x4000000U)
29648 #define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT      (26U)
29649 #define USBPHY_CTRL_ENAUTOSET_USBCLKS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK)
29650 
29651 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
29652 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
29653 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
29654 
29655 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
29656 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
29657 #define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
29658 
29659 #define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
29660 #define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
29661 #define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
29662 
29663 #define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
29664 #define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
29665 #define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
29666 /*! @} */
29667 
29668 /*! @name CTRL_SET - USB PHY General Control Register */
29669 /*! @{ */
29670 
29671 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
29672 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
29673 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
29674 
29675 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     (0x4U)
29676 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    (2U)
29677 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
29678 
29679 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
29680 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
29681 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
29682 
29683 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK      (0x10U)
29684 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT     (4U)
29685 /*! ENDEVPLUGINDET
29686  *  0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
29687  *  0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
29688  */
29689 #define USBPHY_CTRL_SET_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
29690 
29691 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  (0x20U)
29692 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
29693 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
29694 
29695 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     (0x100U)
29696 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    (8U)
29697 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
29698 
29699 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   (0x200U)
29700 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  (9U)
29701 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
29702 
29703 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK          (0x400U)
29704 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         (10U)
29705 #define USBPHY_CTRL_SET_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
29706 
29707 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
29708 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
29709 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
29710 
29711 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
29712 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
29713 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
29714 
29715 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
29716 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
29717 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
29718 
29719 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         (0x10000U)
29720 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        (16U)
29721 #define USBPHY_CTRL_SET_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
29722 
29723 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          (0x20000U)
29724 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         (17U)
29725 #define USBPHY_CTRL_SET_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
29726 
29727 #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
29728 #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
29729 #define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
29730 
29731 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
29732 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
29733 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
29734 
29735 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
29736 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
29737 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
29738 
29739 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK      (0x200000U)
29740 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT     (21U)
29741 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
29742 
29743 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK      (0x800000U)
29744 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT     (23U)
29745 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
29746 
29747 #define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U)
29748 #define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U)
29749 #define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK)
29750 
29751 #define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK   (0x4000000U)
29752 #define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT  (26U)
29753 #define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK)
29754 
29755 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
29756 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
29757 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
29758 
29759 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
29760 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
29761 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
29762 
29763 #define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
29764 #define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
29765 #define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
29766 
29767 #define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
29768 #define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
29769 #define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
29770 /*! @} */
29771 
29772 /*! @name CTRL_CLR - USB PHY General Control Register */
29773 /*! @{ */
29774 
29775 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
29776 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
29777 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
29778 
29779 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     (0x4U)
29780 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    (2U)
29781 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
29782 
29783 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
29784 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
29785 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
29786 
29787 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK      (0x10U)
29788 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT     (4U)
29789 /*! ENDEVPLUGINDET
29790  *  0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
29791  *  0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
29792  */
29793 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
29794 
29795 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  (0x20U)
29796 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
29797 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
29798 
29799 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     (0x100U)
29800 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    (8U)
29801 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
29802 
29803 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   (0x200U)
29804 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  (9U)
29805 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
29806 
29807 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          (0x400U)
29808 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         (10U)
29809 #define USBPHY_CTRL_CLR_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
29810 
29811 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
29812 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
29813 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
29814 
29815 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
29816 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
29817 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
29818 
29819 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
29820 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
29821 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
29822 
29823 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         (0x10000U)
29824 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        (16U)
29825 #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
29826 
29827 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          (0x20000U)
29828 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         (17U)
29829 #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
29830 
29831 #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
29832 #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
29833 #define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
29834 
29835 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
29836 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
29837 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
29838 
29839 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
29840 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
29841 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
29842 
29843 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK      (0x200000U)
29844 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT     (21U)
29845 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
29846 
29847 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK      (0x800000U)
29848 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT     (23U)
29849 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
29850 
29851 #define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U)
29852 #define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U)
29853 #define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK)
29854 
29855 #define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK   (0x4000000U)
29856 #define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT  (26U)
29857 #define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK)
29858 
29859 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
29860 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
29861 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
29862 
29863 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
29864 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
29865 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
29866 
29867 #define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
29868 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
29869 #define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
29870 
29871 #define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
29872 #define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
29873 #define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
29874 /*! @} */
29875 
29876 /*! @name CTRL_TOG - USB PHY General Control Register */
29877 /*! @{ */
29878 
29879 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
29880 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
29881 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
29882 
29883 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     (0x4U)
29884 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    (2U)
29885 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
29886 
29887 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
29888 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
29889 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
29890 
29891 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK      (0x10U)
29892 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT     (4U)
29893 /*! ENDEVPLUGINDET
29894  *  0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
29895  *  0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
29896  */
29897 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
29898 
29899 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  (0x20U)
29900 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
29901 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
29902 
29903 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     (0x100U)
29904 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    (8U)
29905 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
29906 
29907 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   (0x200U)
29908 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  (9U)
29909 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
29910 
29911 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          (0x400U)
29912 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         (10U)
29913 #define USBPHY_CTRL_TOG_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
29914 
29915 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
29916 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
29917 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
29918 
29919 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
29920 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
29921 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
29922 
29923 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
29924 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
29925 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
29926 
29927 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         (0x10000U)
29928 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        (16U)
29929 #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
29930 
29931 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          (0x20000U)
29932 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         (17U)
29933 #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
29934 
29935 #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
29936 #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
29937 #define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
29938 
29939 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
29940 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
29941 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
29942 
29943 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
29944 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
29945 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
29946 
29947 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK      (0x200000U)
29948 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT     (21U)
29949 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
29950 
29951 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK      (0x800000U)
29952 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT     (23U)
29953 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
29954 
29955 #define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U)
29956 #define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U)
29957 #define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK)
29958 
29959 #define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK   (0x4000000U)
29960 #define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT  (26U)
29961 #define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK)
29962 
29963 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
29964 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
29965 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
29966 
29967 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
29968 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
29969 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
29970 
29971 #define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
29972 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
29973 #define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
29974 
29975 #define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
29976 #define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
29977 #define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
29978 /*! @} */
29979 
29980 /*! @name STATUS - USB PHY Status Register */
29981 /*! @{ */
29982 
29983 #define USBPHY_STATUS_OK_STATUS_3V_MASK          (0x1U)
29984 #define USBPHY_STATUS_OK_STATUS_3V_SHIFT         (0U)
29985 #define USBPHY_STATUS_OK_STATUS_3V(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK)
29986 
29987 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
29988 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
29989 /*! HOSTDISCONDETECT_STATUS
29990  *  0b0..USB cable disconnect has not been detected at the local host
29991  *  0b1..USB cable disconnect has been detected at the local host
29992  */
29993 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
29994 
29995 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
29996 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
29997 /*! DEVPLUGIN_STATUS
29998  *  0b0..No attachment to a USB host is detected
29999  *  0b1..Cable attachment to a USB host is detected
30000  */
30001 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
30002 
30003 #define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
30004 #define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
30005 #define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
30006 /*! @} */
30007 
30008 /*! @name PLL_SIC - USB PHY PLL Control/Status Register */
30009 /*! @{ */
30010 
30011 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK      (0x40U)
30012 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT     (6U)
30013 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
30014 
30015 #define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
30016 #define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
30017 #define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
30018 
30019 #define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
30020 #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
30021 #define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
30022 
30023 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK      (0x80000U)
30024 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT     (19U)
30025 /*! REFBIAS_PWD_SEL
30026  *  0b0..Selects PLL_POWER to control the reference bias
30027  *  0b1..Selects REFBIAS_PWD to control the reference bias
30028  */
30029 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
30030 
30031 #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK          (0x100000U)
30032 #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT         (20U)
30033 #define USBPHY_PLL_SIC_REFBIAS_PWD(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
30034 
30035 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK       (0x200000U)
30036 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT      (21U)
30037 #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
30038 
30039 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x1C00000U)
30040 #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (22U)
30041 /*! PLL_DIV_SEL
30042  *  0b000..Divide by 13
30043  *  0b001..Divide by 15
30044  *  0b010..Divide by 16
30045  *  0b011..Divide by 20
30046  *  0b100..Divide by 22
30047  *  0b101..Divide by 25
30048  *  0b110..Divide by 30
30049  *  0b111..Divide by 240
30050  */
30051 #define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
30052 
30053 #define USBPHY_PLL_SIC_PLL_PREDIV_MASK           (0x40000000U)
30054 #define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT          (30U)
30055 #define USBPHY_PLL_SIC_PLL_PREDIV(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK)
30056 
30057 #define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
30058 #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
30059 /*! PLL_LOCK
30060  *  0b0..PLL is not currently locked
30061  *  0b1..PLL is currently locked
30062  */
30063 #define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
30064 /*! @} */
30065 
30066 /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
30067 /*! @{ */
30068 
30069 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK  (0x40U)
30070 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
30071 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
30072 
30073 #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
30074 #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
30075 #define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
30076 
30077 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
30078 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
30079 #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
30080 
30081 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK  (0x80000U)
30082 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
30083 /*! REFBIAS_PWD_SEL
30084  *  0b0..Selects PLL_POWER to control the reference bias
30085  *  0b1..Selects REFBIAS_PWD to control the reference bias
30086  */
30087 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
30088 
30089 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK      (0x100000U)
30090 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT     (20U)
30091 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
30092 
30093 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK   (0x200000U)
30094 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT  (21U)
30095 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
30096 
30097 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x1C00000U)
30098 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (22U)
30099 /*! PLL_DIV_SEL
30100  *  0b000..Divide by 13
30101  *  0b001..Divide by 15
30102  *  0b010..Divide by 16
30103  *  0b011..Divide by 20
30104  *  0b100..Divide by 22
30105  *  0b101..Divide by 25
30106  *  0b110..Divide by 30
30107  *  0b111..Divide by 240
30108  */
30109 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
30110 
30111 #define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK       (0x40000000U)
30112 #define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT      (30U)
30113 #define USBPHY_PLL_SIC_SET_PLL_PREDIV(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK)
30114 
30115 #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
30116 #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
30117 /*! PLL_LOCK
30118  *  0b0..PLL is not currently locked
30119  *  0b1..PLL is currently locked
30120  */
30121 #define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
30122 /*! @} */
30123 
30124 /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
30125 /*! @{ */
30126 
30127 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK  (0x40U)
30128 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
30129 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
30130 
30131 #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
30132 #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
30133 #define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
30134 
30135 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
30136 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
30137 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
30138 
30139 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK  (0x80000U)
30140 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
30141 /*! REFBIAS_PWD_SEL
30142  *  0b0..Selects PLL_POWER to control the reference bias
30143  *  0b1..Selects REFBIAS_PWD to control the reference bias
30144  */
30145 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
30146 
30147 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK      (0x100000U)
30148 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT     (20U)
30149 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
30150 
30151 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK   (0x200000U)
30152 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT  (21U)
30153 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
30154 
30155 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x1C00000U)
30156 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (22U)
30157 /*! PLL_DIV_SEL
30158  *  0b000..Divide by 13
30159  *  0b001..Divide by 15
30160  *  0b010..Divide by 16
30161  *  0b011..Divide by 20
30162  *  0b100..Divide by 22
30163  *  0b101..Divide by 25
30164  *  0b110..Divide by 30
30165  *  0b111..Divide by 240
30166  */
30167 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
30168 
30169 #define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK       (0x40000000U)
30170 #define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT      (30U)
30171 #define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK)
30172 
30173 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
30174 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
30175 /*! PLL_LOCK
30176  *  0b0..PLL is not currently locked
30177  *  0b1..PLL is currently locked
30178  */
30179 #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
30180 /*! @} */
30181 
30182 /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
30183 /*! @{ */
30184 
30185 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK  (0x40U)
30186 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
30187 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
30188 
30189 #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
30190 #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
30191 #define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
30192 
30193 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
30194 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
30195 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
30196 
30197 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK  (0x80000U)
30198 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
30199 /*! REFBIAS_PWD_SEL
30200  *  0b0..Selects PLL_POWER to control the reference bias
30201  *  0b1..Selects REFBIAS_PWD to control the reference bias
30202  */
30203 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
30204 
30205 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK      (0x100000U)
30206 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT     (20U)
30207 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
30208 
30209 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK   (0x200000U)
30210 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT  (21U)
30211 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
30212 
30213 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x1C00000U)
30214 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (22U)
30215 /*! PLL_DIV_SEL
30216  *  0b000..Divide by 13
30217  *  0b001..Divide by 15
30218  *  0b010..Divide by 16
30219  *  0b011..Divide by 20
30220  *  0b100..Divide by 22
30221  *  0b101..Divide by 25
30222  *  0b110..Divide by 30
30223  *  0b111..Divide by 240
30224  */
30225 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
30226 
30227 #define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK       (0x40000000U)
30228 #define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT      (30U)
30229 #define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK)
30230 
30231 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
30232 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
30233 /*! PLL_LOCK
30234  *  0b0..PLL is not currently locked
30235  *  0b1..PLL is currently locked
30236  */
30237 #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
30238 /*! @} */
30239 
30240 /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
30241 /*! @{ */
30242 
30243 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
30244 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
30245 /*! VBUSVALID_THRESH
30246  *  0b000..4.0V
30247  *  0b001..4.1V
30248  *  0b010..4.2V
30249  *  0b011..4.3V
30250  *  0b100..4.4V(Default)
30251  *  0b101..4.5V
30252  *  0b110..4.6V
30253  *  0b111..4.7V
30254  */
30255 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
30256 
30257 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
30258 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
30259 /*! VBUS_OVERRIDE_EN
30260  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
30261  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
30262  */
30263 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
30264 
30265 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
30266 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
30267 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
30268 
30269 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
30270 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
30271 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
30272 
30273 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
30274 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
30275 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
30276 
30277 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
30278 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
30279 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
30280 
30281 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
30282 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
30283 /*! VBUSVALID_SEL
30284  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
30285  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
30286  */
30287 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
30288 
30289 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
30290 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
30291 /*! VBUS_SOURCE_SEL
30292  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
30293  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
30294  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
30295  *  0b11..Reserved, do not use
30296  */
30297 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
30298 
30299 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U)
30300 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U)
30301 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)
30302 
30303 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U)
30304 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U)
30305 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)
30306 
30307 #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
30308 #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U)
30309 /*! EXT_ID_OVERRIDE_EN
30310  *  0b0..Select the Muxed value chosen using ID_OVERRIDE_EN.
30311  *  0b1..Select the external ID value.
30312  */
30313 #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK)
30314 
30315 #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
30316 #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
30317 /*! EXT_VBUS_OVERRIDE_EN
30318  *  0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN.
30319  *  0b1..Select the external VBUS VALID value.
30320  */
30321 #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK)
30322 
30323 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
30324 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
30325 /*! VBUSVALID_TO_SESSVALID
30326  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
30327  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
30328  */
30329 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
30330 
30331 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U)
30332 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U)
30333 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK)
30334 
30335 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK  (0x700000U)
30336 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
30337 /*! PWRUP_CMPS
30338  *  0b000..Powers down the VBUS_VALID comparator
30339  *  0b111..Enables the VBUS_VALID comparator (default)
30340  */
30341 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
30342 
30343 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
30344 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
30345 /*! DISCHARGE_VBUS
30346  *  0b0..VBUS discharge resistor is disabled (Default)
30347  *  0b1..VBUS discharge resistor is enabled
30348  */
30349 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
30350 /*! @} */
30351 
30352 /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
30353 /*! @{ */
30354 
30355 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
30356 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
30357 /*! VBUSVALID_THRESH
30358  *  0b000..4.0V
30359  *  0b001..4.1V
30360  *  0b010..4.2V
30361  *  0b011..4.3V
30362  *  0b100..4.4V(Default)
30363  *  0b101..4.5V
30364  *  0b110..4.6V
30365  *  0b111..4.7V
30366  */
30367 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
30368 
30369 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
30370 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
30371 /*! VBUS_OVERRIDE_EN
30372  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
30373  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
30374  */
30375 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
30376 
30377 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
30378 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
30379 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
30380 
30381 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
30382 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
30383 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
30384 
30385 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
30386 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
30387 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
30388 
30389 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
30390 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
30391 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
30392 
30393 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
30394 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
30395 /*! VBUSVALID_SEL
30396  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
30397  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
30398  */
30399 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
30400 
30401 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
30402 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
30403 /*! VBUS_SOURCE_SEL
30404  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
30405  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
30406  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
30407  *  0b11..Reserved, do not use
30408  */
30409 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
30410 
30411 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U)
30412 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U)
30413 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)
30414 
30415 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U)
30416 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U)
30417 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)
30418 
30419 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
30420 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U)
30421 /*! EXT_ID_OVERRIDE_EN
30422  *  0b0..Select the Muxed value chosen using ID_OVERRIDE_EN.
30423  *  0b1..Select the external ID value.
30424  */
30425 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK)
30426 
30427 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
30428 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
30429 /*! EXT_VBUS_OVERRIDE_EN
30430  *  0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN.
30431  *  0b1..Select the external VBUS VALID value.
30432  */
30433 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK)
30434 
30435 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
30436 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
30437 /*! VBUSVALID_TO_SESSVALID
30438  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
30439  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
30440  */
30441 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
30442 
30443 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U)
30444 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U)
30445 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK)
30446 
30447 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U)
30448 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
30449 /*! PWRUP_CMPS
30450  *  0b000..Powers down the VBUS_VALID comparator
30451  *  0b111..Enables the VBUS_VALID comparator (default)
30452  */
30453 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
30454 
30455 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
30456 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
30457 /*! DISCHARGE_VBUS
30458  *  0b0..VBUS discharge resistor is disabled (Default)
30459  *  0b1..VBUS discharge resistor is enabled
30460  */
30461 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
30462 /*! @} */
30463 
30464 /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
30465 /*! @{ */
30466 
30467 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
30468 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
30469 /*! VBUSVALID_THRESH
30470  *  0b000..4.0V
30471  *  0b001..4.1V
30472  *  0b010..4.2V
30473  *  0b011..4.3V
30474  *  0b100..4.4V(Default)
30475  *  0b101..4.5V
30476  *  0b110..4.6V
30477  *  0b111..4.7V
30478  */
30479 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
30480 
30481 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
30482 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
30483 /*! VBUS_OVERRIDE_EN
30484  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
30485  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
30486  */
30487 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
30488 
30489 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
30490 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
30491 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
30492 
30493 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
30494 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
30495 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
30496 
30497 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
30498 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
30499 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
30500 
30501 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
30502 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
30503 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
30504 
30505 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
30506 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
30507 /*! VBUSVALID_SEL
30508  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
30509  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
30510  */
30511 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
30512 
30513 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
30514 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
30515 /*! VBUS_SOURCE_SEL
30516  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
30517  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
30518  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
30519  *  0b11..Reserved, do not use
30520  */
30521 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
30522 
30523 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U)
30524 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U)
30525 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)
30526 
30527 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U)
30528 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U)
30529 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)
30530 
30531 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
30532 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U)
30533 /*! EXT_ID_OVERRIDE_EN
30534  *  0b0..Select the Muxed value chosen using ID_OVERRIDE_EN.
30535  *  0b1..Select the external ID value.
30536  */
30537 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK)
30538 
30539 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
30540 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
30541 /*! EXT_VBUS_OVERRIDE_EN
30542  *  0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN.
30543  *  0b1..Select the external VBUS VALID value.
30544  */
30545 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK)
30546 
30547 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
30548 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
30549 /*! VBUSVALID_TO_SESSVALID
30550  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
30551  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
30552  */
30553 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
30554 
30555 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U)
30556 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U)
30557 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK)
30558 
30559 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U)
30560 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
30561 /*! PWRUP_CMPS
30562  *  0b000..Powers down the VBUS_VALID comparator
30563  *  0b111..Enables the VBUS_VALID comparator (default)
30564  */
30565 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
30566 
30567 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
30568 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
30569 /*! DISCHARGE_VBUS
30570  *  0b0..VBUS discharge resistor is disabled (Default)
30571  *  0b1..VBUS discharge resistor is enabled
30572  */
30573 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
30574 /*! @} */
30575 
30576 /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
30577 /*! @{ */
30578 
30579 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
30580 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
30581 /*! VBUSVALID_THRESH
30582  *  0b000..4.0V
30583  *  0b001..4.1V
30584  *  0b010..4.2V
30585  *  0b011..4.3V
30586  *  0b100..4.4V(Default)
30587  *  0b101..4.5V
30588  *  0b110..4.6V
30589  *  0b111..4.7V
30590  */
30591 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
30592 
30593 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
30594 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
30595 /*! VBUS_OVERRIDE_EN
30596  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
30597  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
30598  */
30599 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
30600 
30601 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
30602 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
30603 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
30604 
30605 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
30606 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
30607 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
30608 
30609 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
30610 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
30611 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
30612 
30613 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
30614 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
30615 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
30616 
30617 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
30618 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
30619 /*! VBUSVALID_SEL
30620  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
30621  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
30622  */
30623 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
30624 
30625 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
30626 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
30627 /*! VBUS_SOURCE_SEL
30628  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
30629  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
30630  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
30631  *  0b11..Reserved, do not use
30632  */
30633 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
30634 
30635 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U)
30636 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U)
30637 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)
30638 
30639 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U)
30640 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U)
30641 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)
30642 
30643 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
30644 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U)
30645 /*! EXT_ID_OVERRIDE_EN
30646  *  0b0..Select the muxed value chosen using ID_OVERRIDE_EN.
30647  *  0b1..Select the external ID value.
30648  */
30649 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK)
30650 
30651 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
30652 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
30653 /*! EXT_VBUS_OVERRIDE_EN
30654  *  0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN.
30655  *  0b1..Select the external VBUS VALID value.
30656  */
30657 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK)
30658 
30659 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
30660 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
30661 /*! VBUSVALID_TO_SESSVALID
30662  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
30663  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
30664  */
30665 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
30666 
30667 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U)
30668 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U)
30669 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK)
30670 
30671 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U)
30672 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
30673 /*! PWRUP_CMPS
30674  *  0b000..Powers down the VBUS_VALID comparator
30675  *  0b111..Enables the VBUS_VALID comparator (default)
30676  */
30677 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
30678 
30679 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
30680 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
30681 /*! DISCHARGE_VBUS
30682  *  0b0..VBUS discharge resistor is disabled (Default)
30683  *  0b1..VBUS discharge resistor is enabled
30684  */
30685 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
30686 /*! @} */
30687 
30688 /*! @name ANACTRL - USB PHY Analog Control Register */
30689 /*! @{ */
30690 
30691 #define USBPHY_ANACTRL_LVI_EN_MASK               (0x2U)
30692 #define USBPHY_ANACTRL_LVI_EN_SHIFT              (1U)
30693 #define USBPHY_ANACTRL_LVI_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK)
30694 
30695 #define USBPHY_ANACTRL_PFD_CLK_SEL_MASK          (0xCU)
30696 #define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT         (2U)
30697 #define USBPHY_ANACTRL_PFD_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
30698 
30699 #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
30700 #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
30701 /*! DEV_PULLDOWN
30702  *  0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
30703  *  0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
30704  */
30705 #define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
30706 /*! @} */
30707 
30708 /*! @name ANACTRL_SET - USB PHY Analog Control Register */
30709 /*! @{ */
30710 
30711 #define USBPHY_ANACTRL_SET_LVI_EN_MASK           (0x2U)
30712 #define USBPHY_ANACTRL_SET_LVI_EN_SHIFT          (1U)
30713 #define USBPHY_ANACTRL_SET_LVI_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK)
30714 
30715 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK      (0xCU)
30716 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT     (2U)
30717 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
30718 
30719 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
30720 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
30721 /*! DEV_PULLDOWN
30722  *  0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
30723  *  0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
30724  */
30725 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
30726 /*! @} */
30727 
30728 /*! @name ANACTRL_CLR - USB PHY Analog Control Register */
30729 /*! @{ */
30730 
30731 #define USBPHY_ANACTRL_CLR_LVI_EN_MASK           (0x2U)
30732 #define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT          (1U)
30733 #define USBPHY_ANACTRL_CLR_LVI_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK)
30734 
30735 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK      (0xCU)
30736 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT     (2U)
30737 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
30738 
30739 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
30740 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
30741 /*! DEV_PULLDOWN
30742  *  0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
30743  *  0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
30744  */
30745 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
30746 /*! @} */
30747 
30748 /*! @name ANACTRL_TOG - USB PHY Analog Control Register */
30749 /*! @{ */
30750 
30751 #define USBPHY_ANACTRL_TOG_LVI_EN_MASK           (0x2U)
30752 #define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT          (1U)
30753 #define USBPHY_ANACTRL_TOG_LVI_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK)
30754 
30755 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK      (0xCU)
30756 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT     (2U)
30757 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
30758 
30759 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
30760 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
30761 /*! DEV_PULLDOWN
30762  *  0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
30763  *  0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
30764  */
30765 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
30766 /*! @} */
30767 
30768 
30769 /*!
30770  * @}
30771  */ /* end of group USBPHY_Register_Masks */
30772 
30773 
30774 /* USBPHY - Peripheral instance base addresses */
30775 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
30776   /** Peripheral USBPHY base address */
30777   #define USBPHY_BASE                              (0x50038000u)
30778   /** Peripheral USBPHY base address */
30779   #define USBPHY_BASE_NS                           (0x40038000u)
30780   /** Peripheral USBPHY base pointer */
30781   #define USBPHY                                   ((USBPHY_Type *)USBPHY_BASE)
30782   /** Peripheral USBPHY base pointer */
30783   #define USBPHY_NS                                ((USBPHY_Type *)USBPHY_BASE_NS)
30784   /** Array initializer of USBPHY peripheral base addresses */
30785   #define USBPHY_BASE_ADDRS                        { USBPHY_BASE }
30786   /** Array initializer of USBPHY peripheral base pointers */
30787   #define USBPHY_BASE_PTRS                         { USBPHY }
30788   /** Array initializer of USBPHY peripheral base addresses */
30789   #define USBPHY_BASE_ADDRS_NS                     { USBPHY_BASE_NS }
30790   /** Array initializer of USBPHY peripheral base pointers */
30791   #define USBPHY_BASE_PTRS_NS                      { USBPHY_NS }
30792 #else
30793   /** Peripheral USBPHY base address */
30794   #define USBPHY_BASE                              (0x40038000u)
30795   /** Peripheral USBPHY base pointer */
30796   #define USBPHY                                   ((USBPHY_Type *)USBPHY_BASE)
30797   /** Array initializer of USBPHY peripheral base addresses */
30798   #define USBPHY_BASE_ADDRS                        { USBPHY_BASE }
30799   /** Array initializer of USBPHY peripheral base pointers */
30800   #define USBPHY_BASE_PTRS                         { USBPHY }
30801 #endif
30802 /** Interrupt vectors for the USBPHY peripheral type */
30803 #define USBPHY_IRQS                              { USB1_PHY_IRQn }
30804 
30805 /*!
30806  * @}
30807  */ /* end of group USBPHY_Peripheral_Access_Layer */
30808 
30809 
30810 /* ----------------------------------------------------------------------------
30811    -- UTICK Peripheral Access Layer
30812    ---------------------------------------------------------------------------- */
30813 
30814 /*!
30815  * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
30816  * @{
30817  */
30818 
30819 /** UTICK - Register Layout Typedef */
30820 typedef struct {
30821   __IO uint32_t CTRL;                              /**< Control register., offset: 0x0 */
30822   __IO uint32_t STAT;                              /**< Status register., offset: 0x4 */
30823   __IO uint32_t CFG;                               /**< Capture configuration register., offset: 0x8 */
30824   __O  uint32_t CAPCLR;                            /**< Capture clear register., offset: 0xC */
30825   __I  uint32_t CAP[4];                            /**< Capture register ., array offset: 0x10, array step: 0x4 */
30826 } UTICK_Type;
30827 
30828 /* ----------------------------------------------------------------------------
30829    -- UTICK Register Masks
30830    ---------------------------------------------------------------------------- */
30831 
30832 /*!
30833  * @addtogroup UTICK_Register_Masks UTICK Register Masks
30834  * @{
30835  */
30836 
30837 /*! @name CTRL - Control register. */
30838 /*! @{ */
30839 
30840 #define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
30841 #define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
30842 /*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer
30843  *    clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.
30844  */
30845 #define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
30846 
30847 #define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
30848 #define UTICK_CTRL_REPEAT_SHIFT                  (31U)
30849 /*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.
30850  */
30851 #define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
30852 /*! @} */
30853 
30854 /*! @name STAT - Status register. */
30855 /*! @{ */
30856 
30857 #define UTICK_STAT_INTR_MASK                     (0x1U)
30858 #define UTICK_STAT_INTR_SHIFT                    (0U)
30859 /*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any
30860  *    value to this register clears this flag.
30861  */
30862 #define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
30863 
30864 #define UTICK_STAT_ACTIVE_MASK                   (0x2U)
30865 #define UTICK_STAT_ACTIVE_SHIFT                  (1U)
30866 /*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.
30867  */
30868 #define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
30869 /*! @} */
30870 
30871 /*! @name CFG - Capture configuration register. */
30872 /*! @{ */
30873 
30874 #define UTICK_CFG_CAPEN0_MASK                    (0x1U)
30875 #define UTICK_CFG_CAPEN0_SHIFT                   (0U)
30876 /*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled.
30877  */
30878 #define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
30879 
30880 #define UTICK_CFG_CAPEN1_MASK                    (0x2U)
30881 #define UTICK_CFG_CAPEN1_SHIFT                   (1U)
30882 /*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled.
30883  */
30884 #define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
30885 
30886 #define UTICK_CFG_CAPEN2_MASK                    (0x4U)
30887 #define UTICK_CFG_CAPEN2_SHIFT                   (2U)
30888 /*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled.
30889  */
30890 #define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
30891 
30892 #define UTICK_CFG_CAPEN3_MASK                    (0x8U)
30893 #define UTICK_CFG_CAPEN3_SHIFT                   (3U)
30894 /*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled.
30895  */
30896 #define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
30897 
30898 #define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
30899 #define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
30900 /*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture.
30901  */
30902 #define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
30903 
30904 #define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
30905 #define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
30906 /*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture.
30907  */
30908 #define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
30909 
30910 #define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
30911 #define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
30912 /*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture.
30913  */
30914 #define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
30915 
30916 #define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
30917 #define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
30918 /*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture.
30919  */
30920 #define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
30921 /*! @} */
30922 
30923 /*! @name CAPCLR - Capture clear register. */
30924 /*! @{ */
30925 
30926 #define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
30927 #define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
30928 /*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value.
30929  */
30930 #define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
30931 
30932 #define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
30933 #define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
30934 /*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value.
30935  */
30936 #define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
30937 
30938 #define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
30939 #define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
30940 /*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value.
30941  */
30942 #define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
30943 
30944 #define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
30945 #define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
30946 /*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value.
30947  */
30948 #define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
30949 /*! @} */
30950 
30951 /*! @name CAP - Capture register . */
30952 /*! @{ */
30953 
30954 #define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
30955 #define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
30956 /*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower
30957  *    than the actual value of the Micro-tick Timer at the moment of the capture event.
30958  */
30959 #define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
30960 
30961 #define UTICK_CAP_VALID_MASK                     (0x80000000U)
30962 #define UTICK_CAP_VALID_SHIFT                    (31U)
30963 /*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related
30964  *    UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
30965  */
30966 #define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
30967 /*! @} */
30968 
30969 /* The count of UTICK_CAP */
30970 #define UTICK_CAP_COUNT                          (4U)
30971 
30972 
30973 /*!
30974  * @}
30975  */ /* end of group UTICK_Register_Masks */
30976 
30977 
30978 /* UTICK - Peripheral instance base addresses */
30979 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
30980   /** Peripheral UTICK0 base address */
30981   #define UTICK0_BASE                              (0x5000E000u)
30982   /** Peripheral UTICK0 base address */
30983   #define UTICK0_BASE_NS                           (0x4000E000u)
30984   /** Peripheral UTICK0 base pointer */
30985   #define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
30986   /** Peripheral UTICK0 base pointer */
30987   #define UTICK0_NS                                ((UTICK_Type *)UTICK0_BASE_NS)
30988   /** Array initializer of UTICK peripheral base addresses */
30989   #define UTICK_BASE_ADDRS                         { UTICK0_BASE }
30990   /** Array initializer of UTICK peripheral base pointers */
30991   #define UTICK_BASE_PTRS                          { UTICK0 }
30992   /** Array initializer of UTICK peripheral base addresses */
30993   #define UTICK_BASE_ADDRS_NS                      { UTICK0_BASE_NS }
30994   /** Array initializer of UTICK peripheral base pointers */
30995   #define UTICK_BASE_PTRS_NS                       { UTICK0_NS }
30996 #else
30997   /** Peripheral UTICK0 base address */
30998   #define UTICK0_BASE                              (0x4000E000u)
30999   /** Peripheral UTICK0 base pointer */
31000   #define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
31001   /** Array initializer of UTICK peripheral base addresses */
31002   #define UTICK_BASE_ADDRS                         { UTICK0_BASE }
31003   /** Array initializer of UTICK peripheral base pointers */
31004   #define UTICK_BASE_PTRS                          { UTICK0 }
31005 #endif
31006 /** Interrupt vectors for the UTICK peripheral type */
31007 #define UTICK_IRQS                               { UTICK0_IRQn }
31008 
31009 /*!
31010  * @}
31011  */ /* end of group UTICK_Peripheral_Access_Layer */
31012 
31013 
31014 /* ----------------------------------------------------------------------------
31015    -- WWDT Peripheral Access Layer
31016    ---------------------------------------------------------------------------- */
31017 
31018 /*!
31019  * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
31020  * @{
31021  */
31022 
31023 /** WWDT - Register Layout Typedef */
31024 typedef struct {
31025   __IO uint32_t MOD;                               /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
31026   __IO uint32_t TC;                                /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
31027   __O  uint32_t FEED;                              /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
31028   __I  uint32_t TV;                                /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
31029        uint8_t RESERVED_0[4];
31030   __IO uint32_t WARNINT;                           /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
31031   __IO uint32_t WINDOW;                            /**< Watchdog Window compare value., offset: 0x18 */
31032 } WWDT_Type;
31033 
31034 /* ----------------------------------------------------------------------------
31035    -- WWDT Register Masks
31036    ---------------------------------------------------------------------------- */
31037 
31038 /*!
31039  * @addtogroup WWDT_Register_Masks WWDT Register Masks
31040  * @{
31041  */
31042 
31043 /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
31044 /*! @{ */
31045 
31046 #define WWDT_MOD_WDEN_MASK                       (0x1U)
31047 #define WWDT_MOD_WDEN_SHIFT                      (0U)
31048 /*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the
31049  *    watchdog timer will run permanently.
31050  *  0b0..Stop. The watchdog timer is stopped.
31051  *  0b1..Run. The watchdog timer is running.
31052  */
31053 #define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
31054 
31055 #define WWDT_MOD_WDRESET_MASK                    (0x2U)
31056 #define WWDT_MOD_WDRESET_SHIFT                   (1U)
31057 /*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
31058  *  0b0..Interrupt. A watchdog time-out will not cause a chip reset.
31059  *  0b1..Reset. A watchdog time-out will cause a chip reset.
31060  */
31061 #define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
31062 
31063 #define WWDT_MOD_WDTOF_MASK                      (0x4U)
31064 #define WWDT_MOD_WDTOF_SHIFT                     (2U)
31065 /*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by
31066  *    events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a
31067  *    chip reset if WDRESET = 1.
31068  */
31069 #define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
31070 
31071 #define WWDT_MOD_WDINT_MASK                      (0x8U)
31072 #define WWDT_MOD_WDINT_SHIFT                     (3U)
31073 /*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT.
31074  *    Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the
31075  *    WARNINT value is equal to the value of the TV register. This can occur if the value of
31076  *    WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.
31077  */
31078 #define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
31079 
31080 #define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
31081 #define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
31082 /*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
31083  *  0b0..Flexible. The watchdog time-out value (TC) can be changed at any time.
31084  *  0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.
31085  */
31086 #define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
31087 /*! @} */
31088 
31089 /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
31090 /*! @{ */
31091 
31092 #define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
31093 #define WWDT_TC_COUNT_SHIFT                      (0U)
31094 /*! COUNT - Watchdog time-out value.
31095  */
31096 #define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
31097 /*! @} */
31098 
31099 /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
31100 /*! @{ */
31101 
31102 #define WWDT_FEED_FEED_MASK                      (0xFFU)
31103 #define WWDT_FEED_FEED_SHIFT                     (0U)
31104 /*! FEED - Feed value should be 0xAA followed by 0x55.
31105  */
31106 #define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
31107 /*! @} */
31108 
31109 /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
31110 /*! @{ */
31111 
31112 #define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
31113 #define WWDT_TV_COUNT_SHIFT                      (0U)
31114 /*! COUNT - Counter timer value.
31115  */
31116 #define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
31117 /*! @} */
31118 
31119 /*! @name WARNINT - Watchdog Warning Interrupt compare value. */
31120 /*! @{ */
31121 
31122 #define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
31123 #define WWDT_WARNINT_WARNINT_SHIFT               (0U)
31124 /*! WARNINT - Watchdog warning interrupt compare value.
31125  */
31126 #define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
31127 /*! @} */
31128 
31129 /*! @name WINDOW - Watchdog Window compare value. */
31130 /*! @{ */
31131 
31132 #define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
31133 #define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
31134 /*! WINDOW - Watchdog window value.
31135  */
31136 #define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
31137 /*! @} */
31138 
31139 
31140 /*!
31141  * @}
31142  */ /* end of group WWDT_Register_Masks */
31143 
31144 
31145 /* WWDT - Peripheral instance base addresses */
31146 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
31147   /** Peripheral WWDT base address */
31148   #define WWDT_BASE                                (0x5000C000u)
31149   /** Peripheral WWDT base address */
31150   #define WWDT_BASE_NS                             (0x4000C000u)
31151   /** Peripheral WWDT base pointer */
31152   #define WWDT                                     ((WWDT_Type *)WWDT_BASE)
31153   /** Peripheral WWDT base pointer */
31154   #define WWDT_NS                                  ((WWDT_Type *)WWDT_BASE_NS)
31155   /** Array initializer of WWDT peripheral base addresses */
31156   #define WWDT_BASE_ADDRS                          { WWDT_BASE }
31157   /** Array initializer of WWDT peripheral base pointers */
31158   #define WWDT_BASE_PTRS                           { WWDT }
31159   /** Array initializer of WWDT peripheral base addresses */
31160   #define WWDT_BASE_ADDRS_NS                       { WWDT_BASE_NS }
31161   /** Array initializer of WWDT peripheral base pointers */
31162   #define WWDT_BASE_PTRS_NS                        { WWDT_NS }
31163 #else
31164   /** Peripheral WWDT base address */
31165   #define WWDT_BASE                                (0x4000C000u)
31166   /** Peripheral WWDT base pointer */
31167   #define WWDT                                     ((WWDT_Type *)WWDT_BASE)
31168   /** Array initializer of WWDT peripheral base addresses */
31169   #define WWDT_BASE_ADDRS                          { WWDT_BASE }
31170   /** Array initializer of WWDT peripheral base pointers */
31171   #define WWDT_BASE_PTRS                           { WWDT }
31172 #endif
31173 /** Interrupt vectors for the WWDT peripheral type */
31174 #define WWDT_IRQS                                { WDT_BOD_IRQn }
31175 
31176 /*!
31177  * @}
31178  */ /* end of group WWDT_Peripheral_Access_Layer */
31179 
31180 
31181 /*
31182 ** End of section using anonymous unions
31183 */
31184 
31185 #if defined(__ARMCC_VERSION)
31186   #if (__ARMCC_VERSION >= 6010050)
31187     #pragma clang diagnostic pop
31188   #else
31189     #pragma pop
31190   #endif
31191 #elif defined(__GNUC__)
31192   /* leave anonymous unions enabled */
31193 #elif defined(__IAR_SYSTEMS_ICC__)
31194   #pragma language=default
31195 #else
31196   #error Not supported compiler type
31197 #endif
31198 
31199 /*!
31200  * @}
31201  */ /* end of group Peripheral_access_layer */
31202 
31203 
31204 /* ----------------------------------------------------------------------------
31205    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
31206    ---------------------------------------------------------------------------- */
31207 
31208 /*!
31209  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
31210  * @{
31211  */
31212 
31213 #if defined(__ARMCC_VERSION)
31214   #if (__ARMCC_VERSION >= 6010050)
31215     #pragma clang system_header
31216   #endif
31217 #elif defined(__IAR_SYSTEMS_ICC__)
31218   #pragma system_include
31219 #endif
31220 
31221 /**
31222  * @brief Mask and left-shift a bit field value for use in a register bit range.
31223  * @param field Name of the register bit field.
31224  * @param value Value of the bit field.
31225  * @return Masked and shifted value.
31226  */
31227 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
31228 /**
31229  * @brief Mask and right-shift a register value to extract a bit field value.
31230  * @param field Name of the register bit field.
31231  * @param value Value of the register.
31232  * @return Masked and shifted bit field value.
31233  */
31234 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
31235 
31236 /*!
31237  * @}
31238  */ /* end of group Bit_Field_Generic_Macros */
31239 
31240 
31241 /* ----------------------------------------------------------------------------
31242    -- SDK Compatibility
31243    ---------------------------------------------------------------------------- */
31244 
31245 /*!
31246  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
31247  * @{
31248  */
31249 
31250 /** High Speed SPI (Flexcomm 8) interrupt name */
31251 #define LSPI_HS_IRQn                                FLEXCOMM8_IRQn
31252 
31253 /*!
31254  * @brief Get the chip value.
31255  *
31256  * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version.
31257  */
Chip_GetVersion(void)31258 static inline uint32_t Chip_GetVersion(void)
31259 {
31260     uint32_t deviceRevision;
31261 
31262     deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK;
31263 
31264     if(0UL == deviceRevision) /* A0 device revision is 0 */
31265     {
31266         return 0x0;
31267     }
31268     else if(1UL == deviceRevision) /* A1 device revision is 1 */
31269     {
31270         return 0x1;
31271     }
31272     else
31273     {
31274         return 0xFF;
31275     }
31276 }
31277 
31278 
31279 /*!
31280  * @}
31281  */ /* end of group SDK_Compatibility_Symbols */
31282 
31283 
31284 #endif  /* _LPC55S69_CM33_CORE1_H_ */
31285 
31286