1 /* 2 ** ################################################################### 3 ** Version: rev. 1.1, 2019-05-16 4 ** Build: b231017 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2023 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2018-08-22) 18 ** Initial version based on v0.2UM 19 ** - rev. 1.1 (2019-05-16) 20 ** Initial A1 version based on v1.3UM 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _LPC55S69_cm33_core0_FEATURES_H_ 26 #define _LPC55S69_cm33_core0_FEATURES_H_ 27 28 /* SOC module features */ 29 30 /* @brief CASPER availability on the SoC. */ 31 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 32 /* @brief CRC availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CRC_COUNT (1) 34 /* @brief CTIMER availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 36 /* @brief DMA availability on the SoC. */ 37 #define FSL_FEATURE_SOC_DMA_COUNT (2) 38 /* @brief FLASH availability on the SoC. */ 39 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 40 /* @brief FLEXCOMM availability on the SoC. */ 41 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 42 /* @brief GINT availability on the SoC. */ 43 #define FSL_FEATURE_SOC_GINT_COUNT (2) 44 /* @brief GPIO availability on the SoC. */ 45 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 46 /* @brief SECGPIO availability on the SoC. */ 47 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 48 /* @brief HASHCRYPT availability on the SoC. */ 49 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 50 /* @brief I2C availability on the SoC. */ 51 #define FSL_FEATURE_SOC_I2C_COUNT (8) 52 /* @brief I2S availability on the SoC. */ 53 #define FSL_FEATURE_SOC_I2S_COUNT (8) 54 /* @brief INPUTMUX availability on the SoC. */ 55 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 56 /* @brief IOCON availability on the SoC. */ 57 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 58 /* @brief LPADC availability on the SoC. */ 59 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 60 /* @brief MAILBOX availability on the SoC. */ 61 #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) 62 /* @brief MPU availability on the SoC. */ 63 #define FSL_FEATURE_SOC_MPU_COUNT (1) 64 /* @brief MRT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_MRT_COUNT (1) 66 /* @brief OSTIMER availability on the SoC. */ 67 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 68 /* @brief PINT availability on the SoC. */ 69 #define FSL_FEATURE_SOC_PINT_COUNT (1) 70 /* @brief SECPINT availability on the SoC. */ 71 #define FSL_FEATURE_SOC_SECPINT_COUNT (1) 72 /* @brief PMC availability on the SoC. */ 73 #define FSL_FEATURE_SOC_PMC_COUNT (1) 74 /* @brief POWERQUAD availability on the SoC. */ 75 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 76 /* @brief PUF availability on the SoC. */ 77 #define FSL_FEATURE_SOC_PUF_COUNT (1) 78 /* @brief LPC_RNG1 availability on the SoC. */ 79 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) 80 /* @brief RTC availability on the SoC. */ 81 #define FSL_FEATURE_SOC_RTC_COUNT (1) 82 /* @brief SCT availability on the SoC. */ 83 #define FSL_FEATURE_SOC_SCT_COUNT (1) 84 /* @brief SDIF availability on the SoC. */ 85 #define FSL_FEATURE_SOC_SDIF_COUNT (1) 86 /* @brief SPI availability on the SoC. */ 87 #define FSL_FEATURE_SOC_SPI_COUNT (9) 88 /* @brief SYSCON availability on the SoC. */ 89 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 90 /* @brief SYSCTL1 availability on the SoC. */ 91 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 92 /* @brief USART availability on the SoC. */ 93 #define FSL_FEATURE_SOC_USART_COUNT (8) 94 /* @brief USB availability on the SoC. */ 95 #define FSL_FEATURE_SOC_USB_COUNT (1) 96 /* @brief USBFSH availability on the SoC. */ 97 #define FSL_FEATURE_SOC_USBFSH_COUNT (1) 98 /* @brief USBHSD availability on the SoC. */ 99 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 100 /* @brief USBHSH availability on the SoC. */ 101 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 102 /* @brief USBPHY availability on the SoC. */ 103 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 104 /* @brief UTICK availability on the SoC. */ 105 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 106 /* @brief WWDT availability on the SoC. */ 107 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 108 109 /* LPADC module features */ 110 111 /* @brief FIFO availability on the SoC. */ 112 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 113 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 114 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 115 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 116 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 117 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 118 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 119 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 120 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 121 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 122 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 123 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 124 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 125 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 126 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 127 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 128 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 129 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 130 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 131 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 132 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 133 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 134 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 135 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 136 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 137 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 138 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 139 /* @brief Has offset trim (register OFSTRIM). */ 140 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 141 /* @brief OFSTRIM availability on the SoC. */ 142 #define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) 143 /* @brief Has Trigger status register. */ 144 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 145 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 146 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 147 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 148 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 149 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 150 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 151 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 152 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 153 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 154 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 155 /* @brief Conversion averaged bitfiled width. */ 156 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 157 /* @brief Has B side channels. */ 158 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 159 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 160 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) 161 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 162 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) 163 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 164 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) 165 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 166 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 167 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 168 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) 169 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 170 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) 171 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 172 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) 173 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 174 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) 175 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 176 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) 177 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 178 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) 179 /* @brief Has internal temperature sensor. */ 180 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 181 /* @brief Chip Rev 0A Temperature sensor parameter A (slope). */ 182 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_0A (770.0f) 183 /* @brief Chip Rev 0A Temperature sensor parameter B (offset). */ 184 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_0A (289.4f) 185 /* @brief Chip Rev 0A Temperature sensor parameter Alpha. */ 186 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_0A (9.5f) 187 /* @brief Chip Rev 1B Temperature sensor parameter A (slope). */ 188 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_1B (804.0f) 189 /* @brief Chip Rev 1B Temperature sensor parameter B (offset). */ 190 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_1B (280.0f) 191 /* @brief Chip Rev 1B Temperature sensor parameter Alpha. */ 192 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_1B (8.5f) 193 /* @brief the buffer size of temperature sensor. */ 194 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) 195 196 /* ANALOGCTRL module features */ 197 198 /* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ 199 #define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) 200 /* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ 201 #define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) 202 /* @brief Has auxiliary bias(register AUX_BIAS). */ 203 #define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) 204 205 /* CASPER module features */ 206 207 /* @brief Base address of the CASPER dedicated RAM */ 208 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) 209 /* @brief SW interleaving of the CASPER dedicated RAM */ 210 #define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) 211 /* @brief CASPER dedicated RAM offset */ 212 #define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) 213 214 /* CTIMER module features */ 215 216 /* @brief CTIMER has no capture channel. */ 217 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 218 /* @brief CTIMER has no capture 2 interrupt. */ 219 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 220 /* @brief CTIMER capture 3 interrupt. */ 221 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 222 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 223 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 224 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 225 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 226 /* @brief CTIMER Has register MSR */ 227 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 228 229 /* DMA module features */ 230 231 /* @brief Number of channels */ 232 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) 233 /* @brief Align size of DMA descriptor */ 234 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 235 /* @brief DMA head link descriptor table align size */ 236 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 237 238 /* FLEXCOMM module features */ 239 240 /* @brief FLEXCOMM0 USART INDEX 0 */ 241 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 242 /* @brief FLEXCOMM0 SPI INDEX 0 */ 243 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 244 /* @brief FLEXCOMM0 I2C INDEX 0 */ 245 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 246 /* @brief FLEXCOMM0 I2S INDEX 0 */ 247 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 248 /* @brief FLEXCOMM1 USART INDEX 1 */ 249 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 250 /* @brief FLEXCOMM1 SPI INDEX 1 */ 251 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 252 /* @brief FLEXCOMM1 I2C INDEX 1 */ 253 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 254 /* @brief FLEXCOMM1 I2S INDEX 1 */ 255 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 256 /* @brief FLEXCOMM2 USART INDEX 2 */ 257 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 258 /* @brief FLEXCOMM2 SPI INDEX 2 */ 259 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 260 /* @brief FLEXCOMM2 I2C INDEX 2 */ 261 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 262 /* @brief FLEXCOMM2 I2S INDEX 2 */ 263 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 264 /* @brief FLEXCOMM3 USART INDEX 3 */ 265 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 266 /* @brief FLEXCOMM3 SPI INDEX 3 */ 267 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 268 /* @brief FLEXCOMM3 I2C INDEX 3 */ 269 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 270 /* @brief FLEXCOMM3 I2S INDEX 3 */ 271 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 272 /* @brief FLEXCOMM4 USART INDEX 4 */ 273 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 274 /* @brief FLEXCOMM4 SPI INDEX 4 */ 275 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 276 /* @brief FLEXCOMM4 I2C INDEX 4 */ 277 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 278 /* @brief FLEXCOMM4 I2S INDEX 4 */ 279 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 280 /* @brief FLEXCOMM5 USART INDEX 5 */ 281 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 282 /* @brief FLEXCOMM5 SPI INDEX 5 */ 283 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 284 /* @brief FLEXCOMM5 I2C INDEX 5 */ 285 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 286 /* @brief FLEXCOMM5 I2S INDEX 5 */ 287 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 288 /* @brief FLEXCOMM6 USART INDEX 6 */ 289 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 290 /* @brief FLEXCOMM6 SPI INDEX 6 */ 291 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 292 /* @brief FLEXCOMM6 I2C INDEX 6 */ 293 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 294 /* @brief FLEXCOMM6 I2S INDEX 6 */ 295 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 296 /* @brief FLEXCOMM7 USART INDEX 7 */ 297 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 298 /* @brief FLEXCOMM7 SPI INDEX 7 */ 299 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 300 /* @brief FLEXCOMM7 I2C INDEX 7 */ 301 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 302 /* @brief FLEXCOMM7 I2S INDEX 7 */ 303 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 304 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 305 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 306 /* @brief I2S has DMIC interconnection */ 307 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) 308 309 /* GINT module features */ 310 311 /* @brief The count of th port which are supported in GINT. */ 312 #define FSL_FEATURE_GINT_PORT_COUNT (2) 313 314 /* HASHCRYPT module features */ 315 316 /* @brief the address of alias offset */ 317 #define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) 318 319 /* I2S module features */ 320 321 /* @brief I2S support dual channel transfer. */ 322 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) 323 /* @brief I2S has DMIC interconnection */ 324 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) 325 326 /* INPUTMUX module features */ 327 328 /* @brief Inputmux has DMA Request Enable */ 329 #define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (0) 330 /* @brief Inputmux has channel mux control */ 331 #define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) 332 333 /* IOCON module features */ 334 335 /* @brief Func bit field width */ 336 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 337 338 /* MAILBOX module features */ 339 340 /* @brief Mailbox side for current core */ 341 #define FSL_FEATURE_MAILBOX_SIDE_A (1) 342 343 /* MRT module features */ 344 345 /* @brief number of channels. */ 346 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 347 348 /* PINT module features */ 349 350 /* @brief Number of connected outputs */ 351 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 352 353 /* PLU module features */ 354 355 /* @brief Has WAKEINT_CTRL register. */ 356 #define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) 357 358 /* PMC module features */ 359 360 /* @brief UTICK does not support PD configure. */ 361 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 362 /* @brief WDT OSC does not support PD configure. */ 363 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 364 365 /* POWERLIB module features */ 366 367 /* @brief Powerlib API is different with other LPC series devices. */ 368 #define FSL_FEATURE_POWERLIB_EXTEND (1) 369 370 /* POWERQUAD module features */ 371 372 /* @brief Sine and Cossine fix errata */ 373 #define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) 374 375 /* PUF module features */ 376 377 /* @brief Number of PUF key slots available on device. */ 378 #define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) 379 /* @brief the shift status value */ 380 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) 381 /* @brief Puf Activation Code Address. */ 382 #define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (648704) 383 /* @brief Puf Activation Code Size. */ 384 #define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1192) 385 386 /* RTC module features */ 387 388 /* @brief Has SUBSEC Register (register SUBSEC) */ 389 #define FSL_FEATURE_RTC_HAS_SUBSEC (1) 390 391 /* SCT module features */ 392 393 /* @brief Number of events */ 394 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 395 /* @brief Number of states */ 396 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 397 /* @brief Number of match capture */ 398 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 399 /* @brief Number of outputs */ 400 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 401 402 /* SDIF module features */ 403 404 /* @brief FIFO depth, every location is a WORD */ 405 #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) 406 /* @brief Max DMA buffer size */ 407 #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) 408 /* @brief Max source clock in HZ */ 409 #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) 410 /* @brief support 2 cards */ 411 #define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) 412 413 /* SECPINT module features */ 414 415 /* @brief Number of connected outputs */ 416 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) 417 418 /* SPI module features */ 419 420 /* @brief SSEL pin count. */ 421 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 422 423 /* SYSCON module features */ 424 425 /* @brief Flash page size in bytes */ 426 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) 427 /* @brief Flash sector size in bytes */ 428 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) 429 /* @brief Flash size in bytes */ 430 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120) 431 /* @brief Has Power Down mode */ 432 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) 433 /* @brief CCM_ANALOG availability on the SoC. */ 434 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 435 /* @brief Starter register discontinuous. */ 436 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 437 438 /* SYSCTL1 module features */ 439 440 /* No feature definitions */ 441 442 /* USB module features */ 443 444 /* @brief Size of the USB dedicated RAM */ 445 #define FSL_FEATURE_USB_USB_RAM (0x00004000) 446 /* @brief Base address of the USB dedicated RAM */ 447 #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) 448 /* @brief USB version */ 449 #define FSL_FEATURE_USB_VERSION (200) 450 /* @brief Number of the endpoint in USB FS */ 451 #define FSL_FEATURE_USB_EP_NUM (5) 452 453 /* USBFSH module features */ 454 455 /* @brief Size of the USB dedicated RAM */ 456 #define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) 457 /* @brief Base address of the USB dedicated RAM */ 458 #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) 459 /* @brief USBFSH version */ 460 #define FSL_FEATURE_USBFSH_VERSION (200) 461 462 /* USBHSD module features */ 463 464 /* @brief Size of the USB dedicated RAM */ 465 #define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) 466 /* @brief Base address of the USB dedicated RAM */ 467 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) 468 /* @brief USBHSD version */ 469 #define FSL_FEATURE_USBHSD_VERSION (300) 470 /* @brief Number of the endpoint in USB HS */ 471 #define FSL_FEATURE_USBHSD_EP_NUM (6) 472 473 /* USBHSH module features */ 474 475 /* @brief Size of the USB dedicated RAM */ 476 #define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) 477 /* @brief Base address of the USB dedicated RAM */ 478 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) 479 /* @brief USBHSH version */ 480 #define FSL_FEATURE_USBHSH_VERSION (300) 481 482 /* USBPHY module features */ 483 484 /* @brief Size of the USB dedicated RAM */ 485 #define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) 486 /* @brief Base address of the USB dedicated RAM */ 487 #define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) 488 /* @brief USBHSD version */ 489 #define FSL_FEATURE_USBPHY_VERSION (300) 490 /* @brief Number of the endpoint in USB HS */ 491 #define FSL_FEATURE_USBPHY_EP_NUM (6) 492 493 /* WWDT module features */ 494 495 /* @brief Has no RESET register. */ 496 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 497 /* @brief WWDT does not support oscillator lock. */ 498 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) 499 500 #endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ 501 502
