1 /* 2 ** ################################################################### 3 ** Version: rev. 1.1, 2021-08-04 4 ** Build: b240322 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2021-04-12) 18 ** Initial version based on RM DraftF 19 ** - rev. 1.1 (2021-08-04) 20 ** Initial version based on RM DraftG 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _LPC55S36_FEATURES_H_ 26 #define _LPC55S36_FEATURES_H_ 27 28 /* SOC module features */ 29 30 #if defined(CPU_LPC55S36JBD100) 31 /* @brief AOI availability on the SoC. */ 32 #define FSL_FEATURE_SOC_AOI_COUNT (2) 33 /* @brief CACHE64_CTRL availability on the SoC. */ 34 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) 35 /* @brief CACHE64_POLSEL availability on the SoC. */ 36 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) 37 /* @brief LPC_CAN availability on the SoC. */ 38 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) 39 /* @brief CDOG availability on the SoC. */ 40 #define FSL_FEATURE_SOC_CDOG_COUNT (1) 41 /* @brief CRC availability on the SoC. */ 42 #define FSL_FEATURE_SOC_CRC_COUNT (1) 43 /* @brief CTIMER availability on the SoC. */ 44 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 45 /* @brief DMA availability on the SoC. */ 46 #define FSL_FEATURE_SOC_DMA_COUNT (2) 47 /* @brief DMIC availability on the SoC. */ 48 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 49 /* @brief ELS availability on the SoC. */ 50 #define FSL_FEATURE_SOC_ELS_COUNT (1) 51 /* @brief ENC availability on the SoC. */ 52 #define FSL_FEATURE_SOC_ENC_COUNT (2) 53 /* @brief FLASH availability on the SoC. */ 54 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 55 /* @brief FLEXCOMM availability on the SoC. */ 56 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 57 /* @brief FLEXSPI availability on the SoC. */ 58 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 59 /* @brief FREQME availability on the SoC. */ 60 #define FSL_FEATURE_SOC_FREQME_COUNT (1) 61 /* @brief GINT availability on the SoC. */ 62 #define FSL_FEATURE_SOC_GINT_COUNT (2) 63 /* @brief GPIO availability on the SoC. */ 64 #define FSL_FEATURE_SOC_GPIO_COUNT (2) 65 /* @brief I2C availability on the SoC. */ 66 #define FSL_FEATURE_SOC_I2C_COUNT (8) 67 /* @brief I3C availability on the SoC. */ 68 #define FSL_FEATURE_SOC_I3C_COUNT (1) 69 /* @brief I2S availability on the SoC. */ 70 #define FSL_FEATURE_SOC_I2S_COUNT (8) 71 /* @brief INPUTMUX availability on the SoC. */ 72 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 73 /* @brief IOCON availability on the SoC. */ 74 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 75 /* @brief ITRC availability on the SoC. */ 76 #define FSL_FEATURE_SOC_ITRC_COUNT (1) 77 /* @brief LPADC availability on the SoC. */ 78 #define FSL_FEATURE_SOC_LPADC_COUNT (2) 79 /* @brief LPCMP availability on the SoC. */ 80 #define FSL_FEATURE_SOC_LPCMP_COUNT (3) 81 /* @brief LPDAC availability on the SoC. */ 82 #define FSL_FEATURE_SOC_LPDAC_COUNT (3) 83 /* @brief MAILBOX availability on the SoC. */ 84 #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) 85 /* @brief MRT availability on the SoC. */ 86 #define FSL_FEATURE_SOC_MRT_COUNT (1) 87 /* @brief OPAMP availability on the SoC. */ 88 #define FSL_FEATURE_SOC_OPAMP_COUNT (3) 89 /* @brief OSTIMER availability on the SoC. */ 90 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 91 /* @brief PINT availability on the SoC. */ 92 #define FSL_FEATURE_SOC_PINT_COUNT (2) 93 /* @brief PKC availability on the SoC. */ 94 #define FSL_FEATURE_SOC_PKC_COUNT (1) 95 /* @brief PMC availability on the SoC. */ 96 #define FSL_FEATURE_SOC_PMC_COUNT (1) 97 /* @brief POWERQUAD availability on the SoC. */ 98 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 99 /* @brief PWM availability on the SoC. */ 100 #define FSL_FEATURE_SOC_PWM_COUNT (2) 101 /* @brief PUF availability on the SoC. */ 102 #define FSL_FEATURE_SOC_PUF_COUNT (1) 103 /* @brief RTC availability on the SoC. */ 104 #define FSL_FEATURE_SOC_RTC_COUNT (1) 105 /* @brief SCT availability on the SoC. */ 106 #define FSL_FEATURE_SOC_SCT_COUNT (1) 107 /* @brief SPI availability on the SoC. */ 108 #define FSL_FEATURE_SOC_SPI_COUNT (9) 109 /* @brief SYSCON availability on the SoC. */ 110 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 111 /* @brief USART availability on the SoC. */ 112 #define FSL_FEATURE_SOC_USART_COUNT (8) 113 /* @brief USB availability on the SoC. */ 114 #define FSL_FEATURE_SOC_USB_COUNT (1) 115 /* @brief USBFSH availability on the SoC. */ 116 #define FSL_FEATURE_SOC_USBFSH_COUNT (1) 117 /* @brief UTICK availability on the SoC. */ 118 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 119 /* @brief VREF availability on the SoC. */ 120 #define FSL_FEATURE_SOC_VREF_COUNT (1) 121 /* @brief WWDT availability on the SoC. */ 122 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 123 #elif defined(CPU_LPC55S36JHI48) 124 /* @brief AOI availability on the SoC. */ 125 #define FSL_FEATURE_SOC_AOI_COUNT (2) 126 /* @brief CACHE64_CTRL availability on the SoC. */ 127 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) 128 /* @brief CACHE64_POLSEL availability on the SoC. */ 129 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) 130 /* @brief LPC_CAN availability on the SoC. */ 131 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) 132 /* @brief CDOG availability on the SoC. */ 133 #define FSL_FEATURE_SOC_CDOG_COUNT (1) 134 /* @brief CRC availability on the SoC. */ 135 #define FSL_FEATURE_SOC_CRC_COUNT (1) 136 /* @brief CTIMER availability on the SoC. */ 137 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 138 /* @brief DMA availability on the SoC. */ 139 #define FSL_FEATURE_SOC_DMA_COUNT (2) 140 /* @brief DMIC availability on the SoC. */ 141 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 142 /* @brief ELS availability on the SoC. */ 143 #define FSL_FEATURE_SOC_ELS_COUNT (1) 144 /* @brief ENC availability on the SoC. */ 145 #define FSL_FEATURE_SOC_ENC_COUNT (2) 146 /* @brief FLASH availability on the SoC. */ 147 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 148 /* @brief FLEXCOMM availability on the SoC. */ 149 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 150 /* @brief FLEXSPI availability on the SoC. */ 151 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 152 /* @brief FREQME availability on the SoC. */ 153 #define FSL_FEATURE_SOC_FREQME_COUNT (1) 154 /* @brief GINT availability on the SoC. */ 155 #define FSL_FEATURE_SOC_GINT_COUNT (2) 156 /* @brief GPIO availability on the SoC. */ 157 #define FSL_FEATURE_SOC_GPIO_COUNT (2) 158 /* @brief I2C availability on the SoC. */ 159 #define FSL_FEATURE_SOC_I2C_COUNT (8) 160 /* @brief I3C availability on the SoC. */ 161 #define FSL_FEATURE_SOC_I3C_COUNT (1) 162 /* @brief I2S availability on the SoC. */ 163 #define FSL_FEATURE_SOC_I2S_COUNT (8) 164 /* @brief INPUTMUX availability on the SoC. */ 165 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 166 /* @brief IOCON availability on the SoC. */ 167 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 168 /* @brief ITRC availability on the SoC. */ 169 #define FSL_FEATURE_SOC_ITRC_COUNT (1) 170 /* @brief LPADC availability on the SoC. */ 171 #define FSL_FEATURE_SOC_LPADC_COUNT (2) 172 /* @brief LPCMP availability on the SoC. */ 173 #define FSL_FEATURE_SOC_LPCMP_COUNT (3) 174 /* @brief LPDAC availability on the SoC. */ 175 #define FSL_FEATURE_SOC_LPDAC_COUNT (3) 176 /* @brief MAILBOX availability on the SoC. */ 177 #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) 178 /* @brief MRT availability on the SoC. */ 179 #define FSL_FEATURE_SOC_MRT_COUNT (1) 180 /* @brief OPAMP availability on the SoC. */ 181 #define FSL_FEATURE_SOC_OPAMP_COUNT (3) 182 /* @brief OSTIMER availability on the SoC. */ 183 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 184 /* @brief PINT availability on the SoC. */ 185 #define FSL_FEATURE_SOC_PINT_COUNT (2) 186 /* @brief PKC availability on the SoC. */ 187 #define FSL_FEATURE_SOC_PKC_COUNT (1) 188 /* @brief PMC availability on the SoC. */ 189 #define FSL_FEATURE_SOC_PMC_COUNT (1) 190 /* @brief POWERQUAD availability on the SoC. */ 191 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 192 /* @brief PWM availability on the SoC. */ 193 #define FSL_FEATURE_SOC_PWM_COUNT (2) 194 /* @brief PUF availability on the SoC. */ 195 #define FSL_FEATURE_SOC_PUF_COUNT (1) 196 /* @brief RTC availability on the SoC. */ 197 #define FSL_FEATURE_SOC_RTC_COUNT (1) 198 /* @brief SCT availability on the SoC. */ 199 #define FSL_FEATURE_SOC_SCT_COUNT (1) 200 /* @brief SPI availability on the SoC. */ 201 #define FSL_FEATURE_SOC_SPI_COUNT (9) 202 /* @brief SYSCON availability on the SoC. */ 203 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 204 /* @brief USART availability on the SoC. */ 205 #define FSL_FEATURE_SOC_USART_COUNT (8) 206 /* @brief UTICK availability on the SoC. */ 207 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 208 /* @brief VREF availability on the SoC. */ 209 #define FSL_FEATURE_SOC_VREF_COUNT (1) 210 /* @brief WWDT availability on the SoC. */ 211 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 212 #endif 213 214 /* LPADC module features */ 215 216 /* @brief FIFO availability on the SoC. */ 217 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 218 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 219 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 220 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 221 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 222 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 223 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 224 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 225 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 226 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 227 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 228 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 229 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 230 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 231 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 232 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 233 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 234 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 235 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 236 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 237 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 238 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 239 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 240 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 241 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 242 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 243 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 244 /* @brief Has offset trim (register OFSTRIM). */ 245 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 246 /* @brief OFSTRIM availability on the SoC. */ 247 #define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) 248 /* @brief Has Trigger status register. */ 249 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 250 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 251 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 252 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 253 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 254 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 255 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) 256 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 257 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) 258 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 259 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 260 /* @brief Conversion averaged bitfiled width. */ 261 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 262 /* @brief Has B side channels. */ 263 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 264 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 265 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) 266 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 267 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) 268 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 269 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) 270 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 271 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 272 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 273 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) 274 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 275 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) 276 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 277 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) 278 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 279 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) 280 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 281 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) 282 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 283 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) 284 /* @brief Has internal temperature sensor. */ 285 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 286 /* @brief Temperature sensor parameter A (slope). */ 287 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (768.0f) 288 /* @brief Temperature sensor parameter B (offset). */ 289 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (292.7f) 290 /* @brief Temperature sensor parameter Alpha. */ 291 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.7f) 292 /* @brief Temperature sensor need calibration. */ 293 #define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1) 294 /* @brief the address of temperature sensor parameter A (slope) in Flash. */ 295 #define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U) 296 /* @brief the address of temperature sensor parameter B (offset) in Flash. */ 297 #define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU) 298 /* @brief the buffer size of temperature sensor. */ 299 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) 300 301 /* ANACTRL module features */ 302 303 /* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ 304 #define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) 305 /* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ 306 #define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1) 307 /* @brief Has auxiliary bias(register AUX_BIAS). */ 308 #define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) 309 /* @brief Has FREQ_ME_CTRL reigster. */ 310 #define FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL (1) 311 312 /* AOI module features */ 313 314 /* @brief Maximum value of input mux. */ 315 #define FSL_FEATURE_AOI_MODULE_INPUTS (4) 316 /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ 317 #define FSL_FEATURE_AOI_EVENT_COUNT (4) 318 319 /* CACHE64_CTRL module features */ 320 321 /* @brief Cache Line size in byte. */ 322 #define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) 323 324 /* CACHE64_POLSEL module features */ 325 326 /* No feature definitions */ 327 328 /* CAN module features */ 329 330 /* @brief Support CANFD or not */ 331 #define FSL_FEATURE_CAN_SUPPORT_CANFD (1) 332 333 /* CDOG module features */ 334 335 /* No feature definitions */ 336 337 /* CRC module features */ 338 339 /* @brief Has data register with name CRC */ 340 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 341 342 /* CTIMER module features */ 343 344 /* @brief CTIMER has no capture channel. */ 345 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 346 /* @brief CTIMER has no capture 2 interrupt. */ 347 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 348 /* @brief CTIMER capture 3 interrupt. */ 349 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 350 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 351 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 352 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 353 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 354 /* @brief CTIMER Has register MSR */ 355 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 356 357 /* LPDAC module features */ 358 359 /* @brief FIFO size. */ 360 #define FSL_FEATURE_LPDAC_FIFO_SIZE (16) 361 /* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ 362 #define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) 363 /* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ 364 #define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) 365 /* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ 366 #define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) 367 /* @brief VREF source number. */ 368 #define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) 369 /* @brief Has internal reference current options. */ 370 #define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) 371 /* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ 372 #define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) 373 374 /* DMA module features */ 375 376 /* @brief Number of channels */ 377 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) \ 378 (((x) == DMA0) ? (52) : \ 379 (((x) == DMA1) ? (16) : (-1))) 380 /* @brief Max channels */ 381 #define FSL_FEATURE_DMA_MAX_CHANNELS (52) 382 /* @brief All channels */ 383 #define FSL_FEATURE_DMA_ALL_CHANNELS (68U) 384 /* @brief Align size of DMA0 descriptor */ 385 #define FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE (1024) 386 /* @brief Align size of DMA1 descriptor */ 387 #define FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE (256) 388 /* @brief Align size of DMA descriptor */ 389 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(x) \ 390 (((x) == DMA0) ? (1024) : \ 391 (((x) == DMA1) ? (256) : (-1))) 392 /* @brief DMA head link descriptor table align size */ 393 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 394 395 /* DMIC module features */ 396 397 /* @brief Number of channels */ 398 #define FSL_FEATURE_DMIC_CHANNEL_NUM (2) 399 /* @brief DMIC channel support stereo data */ 400 #define FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6 (0) 401 /* @brief DMIC does not support bypass channel clock */ 402 #define FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS (1) 403 /* @brief DMIC channel FIFO register support sign extended */ 404 #define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1) 405 /* @brief DMIC has no IOCFG register */ 406 #define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1) 407 /* @brief DMIC has decimator reset function */ 408 #define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1) 409 /* @brief DMIC has global channel synchronization function */ 410 #define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (1) 411 412 /* ENC module features */ 413 414 /* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ 415 #define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0) 416 /* @brief Has register CTRL3. */ 417 #define FSL_FEATURE_ENC_HAS_CTRL3 (1) 418 /* @brief Has register LASTEDGE or LASTEDGEH. */ 419 #define FSL_FEATURE_ENC_HAS_LASTEDGE (1) 420 /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ 421 #define FSL_FEATURE_ENC_HAS_POSDPER (1) 422 /* @brief Has bitfiled FILT[FILT_PRSC]. */ 423 #define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) 424 425 /* FLEXCOMM module features */ 426 427 /* @brief FLEXCOMM0 USART INDEX 0 */ 428 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 429 /* @brief FLEXCOMM0 SPI INDEX 0 */ 430 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 431 /* @brief FLEXCOMM0 I2C INDEX 0 */ 432 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 433 /* @brief FLEXCOMM0 I2S INDEX 0 */ 434 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 435 /* @brief FLEXCOMM1 USART INDEX 1 */ 436 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 437 /* @brief FLEXCOMM1 SPI INDEX 1 */ 438 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 439 /* @brief FLEXCOMM1 I2C INDEX 1 */ 440 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 441 /* @brief FLEXCOMM1 I2S INDEX 1 */ 442 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 443 /* @brief FLEXCOMM2 USART INDEX 2 */ 444 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 445 /* @brief FLEXCOMM2 SPI INDEX 2 */ 446 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 447 /* @brief FLEXCOMM2 I2C INDEX 2 */ 448 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 449 /* @brief FLEXCOMM2 I2S INDEX 2 */ 450 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 451 /* @brief FLEXCOMM3 USART INDEX 3 */ 452 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 453 /* @brief FLEXCOMM3 SPI INDEX 3 */ 454 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 455 /* @brief FLEXCOMM3 I2C INDEX 3 */ 456 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 457 /* @brief FLEXCOMM3 I2S INDEX 3 */ 458 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 459 /* @brief FLEXCOMM4 USART INDEX 4 */ 460 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 461 /* @brief FLEXCOMM4 SPI INDEX 4 */ 462 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 463 /* @brief FLEXCOMM4 I2C INDEX 4 */ 464 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 465 /* @brief FLEXCOMM4 I2S INDEX 4 */ 466 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 467 /* @brief FLEXCOMM5 USART INDEX 5 */ 468 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 469 /* @brief FLEXCOMM5 SPI INDEX 5 */ 470 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 471 /* @brief FLEXCOMM5 I2C INDEX 5 */ 472 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 473 /* @brief FLEXCOMM5 I2S INDEX 5 */ 474 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 475 /* @brief FLEXCOMM6 USART INDEX 6 */ 476 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 477 /* @brief FLEXCOMM6 SPI INDEX 6 */ 478 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 479 /* @brief FLEXCOMM6 I2C INDEX 6 */ 480 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 481 /* @brief FLEXCOMM6 I2S INDEX 6 */ 482 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 483 /* @brief FLEXCOMM7 USART INDEX 7 */ 484 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 485 /* @brief FLEXCOMM7 SPI INDEX 7 */ 486 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 487 /* @brief FLEXCOMM7 I2C INDEX 7 */ 488 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 489 /* @brief FLEXCOMM7 I2S INDEX 7 */ 490 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 491 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 492 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 493 /* @brief I2S has DMIC interconnection */ 494 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ 495 (((x) == FLEXCOMM0) ? (0) : \ 496 (((x) == FLEXCOMM1) ? (0) : \ 497 (((x) == FLEXCOMM2) ? (0) : \ 498 (((x) == FLEXCOMM3) ? (0) : \ 499 (((x) == FLEXCOMM4) ? (0) : \ 500 (((x) == FLEXCOMM5) ? (0) : \ 501 (((x) == FLEXCOMM6) ? (0) : \ 502 (((x) == FLEXCOMM7) ? (1) : \ 503 (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) 504 /* @brief I2S support dual channel transfer */ 505 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ 506 (((x) == FLEXCOMM0) ? (0) : \ 507 (((x) == FLEXCOMM1) ? (0) : \ 508 (((x) == FLEXCOMM2) ? (0) : \ 509 (((x) == FLEXCOMM3) ? (0) : \ 510 (((x) == FLEXCOMM4) ? (0) : \ 511 (((x) == FLEXCOMM5) ? (0) : \ 512 (((x) == FLEXCOMM6) ? (1) : \ 513 (((x) == FLEXCOMM7) ? (1) : \ 514 (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) 515 516 /* FLEXSPI module features */ 517 518 /* @brief FlexSPI AHB buffer count */ 519 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) 520 /* @brief FlexSPI has no MCR0 ARDFEN bit */ 521 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) 522 /* @brief FlexSPI has no MCR0 ATDFEN bit */ 523 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) 524 /* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ 525 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) 526 /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ 527 #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) 528 /* @brief FlexSPI has no IPCR1 IPAREN bit */ 529 #define FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN (1) 530 /* @brief FlexSPI has no AHBCR APAREN bit */ 531 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN (1) 532 /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ 533 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) 534 /* @brief FlexSPI has no FLSHCR4 WMENB bit */ 535 #define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) 536 /* @brief FlexSPI has no STS2 BSLVLOCK bit */ 537 #define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (1) 538 /* @brief FlexSPI has no STS2 BREFLOCK bit */ 539 #define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (1) 540 /* @brief FlexSPI supports Port A only, do not support Port B. */ 541 #define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (1) 542 /* @brief FlexSPI LUTKEY is read only. */ 543 #define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (1) 544 /* @brief There is AHBBUSERROREN bit in INTEN register. */ 545 #define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) 546 /* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ 547 #define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) 548 /* @brief FLEXSPI has no IP parallel mode. */ 549 #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) 550 /* @brief FLEXSPI has no AHB parallel mode. */ 551 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) 552 /* @brief FLEXSPI support address shift. */ 553 #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) 554 /* @brief FlexSPI AHB RX buffer size (byte) */ 555 #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) 556 557 /* GINT module features */ 558 559 /* @brief The count of th port which are supported in GINT. */ 560 #define FSL_FEATURE_GINT_PORT_COUNT (2) 561 562 /* I2S module features */ 563 564 /* @brief I2S support dual channel transfer. */ 565 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 566 /* @brief I2S has DMIC interconnection. */ 567 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) 568 569 /* I3C module features */ 570 571 /* @brief Has TERM bitfile in MERRWARN register. */ 572 #define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) 573 /* @brief SOC has no reset driver. */ 574 #define FSL_FEATURE_I3C_HAS_NO_RESET (0) 575 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ 576 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) 577 /* @brief Register SCONFIG do not have IDRAND bitfield. */ 578 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) 579 /* @brief Register SCONFIG has HDROK bitfield. */ 580 #define FSL_FEATURE_I3C_HAS_HDROK (0) 581 /* @brief SOC doesn't support slave IBI/MR/HJ. */ 582 #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) 583 584 /* INPUTMUX module features */ 585 586 /* @brief Inputmux has DMA Request Enable */ 587 #define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) 588 /* @brief Inputmux has channel mux control */ 589 #define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) 590 591 /* IOCON module features */ 592 593 /* @brief Func bit field width */ 594 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 595 596 /* MRT module features */ 597 598 /* @brief number of channels. */ 599 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 600 601 /* PINT module features */ 602 603 /* @brief Number of connected outputs */ 604 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 605 /* @brief Number of connected outputs */ 606 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) 607 608 /* PMC module features */ 609 610 /* @brief UTICK does not support PD configure. */ 611 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 612 /* @brief WDT OSC does not support PD configure. */ 613 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 614 615 /* POWERQUAD module features */ 616 617 /* @brief Sine and Cossine fix errata */ 618 #define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) 619 620 /* PUF module features */ 621 622 /* @brief the shift status value */ 623 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) 624 /* @brief Puf Activation Code Address. */ 625 #define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (255488) 626 /* @brief Puf Activation Code Size. */ 627 #define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (996) 628 629 /* PWM module features */ 630 631 /* @brief If (e)FlexPWM has module A channels (outputs). */ 632 #define FSL_FEATURE_PWM_HAS_CHANNELA (1) 633 /* @brief If (e)FlexPWM has module B channels (outputs). */ 634 #define FSL_FEATURE_PWM_HAS_CHANNELB (1) 635 /* @brief If (e)FlexPWM has module X channels (outputs). */ 636 #define FSL_FEATURE_PWM_HAS_CHANNELX (1) 637 /* @brief If (e)FlexPWM has fractional feature. */ 638 #define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) 639 /* @brief If (e)FlexPWM has mux trigger source select bit field. */ 640 #define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) 641 /* @brief Number of submodules in each (e)FlexPWM module. */ 642 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) 643 /* @brief Number of fault channel in each (e)FlexPWM module. */ 644 #define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) 645 /* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ 646 #define FSL_FEATURE_PWM_HAS_NO_WAITEN (0) 647 /* @brief If (e)FlexPWM has phase delay feature. */ 648 #define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) 649 /* @brief If (e)FlexPWM has input filter capture feature. */ 650 #define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) 651 /* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ 652 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) 653 /* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ 654 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) 655 /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ 656 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) 657 658 /* RTC module features */ 659 660 /* @brief Has Tamper Direction Register support. */ 661 #define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) 662 /* @brief Has Tamper Queue Status and Control Register support. */ 663 #define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (1) 664 /* @brief Has RTC subsystem. */ 665 #define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) 666 /* @brief Has Reset in system level. */ 667 #define FSL_FEATURE_RTC_HAS_RESET (1) 668 /* @brief Has RTC Tamper 23 Filter Configuration Register support. */ 669 #define FSL_FEATURE_RTC_HAS_FILTER23_CFG (1) 670 /* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ 671 #define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) 672 /* @brief Has CLK_SEL bitfile in CTRL register. */ 673 #define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (0) 674 /* @brief Has CLKO_DIS bitfile in CTRL register. */ 675 #define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (0) 676 /* @brief Has No Tamper in RTC. */ 677 #define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (0) 678 /* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ 679 #define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (0) 680 /* @brief Has RST_SRC bitfile in STATUS register. */ 681 #define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (0) 682 /* @brief Has GP_DATA_REG register. */ 683 #define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (0) 684 /* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ 685 #define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (0) 686 687 /* SCT module features */ 688 689 /* @brief Number of events */ 690 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 691 /* @brief Number of states */ 692 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 693 /* @brief Number of match capture */ 694 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 695 /* @brief Number of outputs */ 696 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 697 698 /* SPI module features */ 699 700 /* @brief SSEL pin count. */ 701 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 702 703 /* SYSCON module features */ 704 705 /* @brief Flash page size in bytes */ 706 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) 707 /* @brief Flash sector size in bytes */ 708 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) 709 /* @brief Flash size in bytes */ 710 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (251904) 711 712 /* SYSCTL module features */ 713 714 /* @brief SYSCTRL has Code Gray feature. */ 715 #define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) 716 717 /* USART module features */ 718 719 /* @brief Has FIFO Receive Timeout Configuration (register FIFORXTIMEOUTCFG). */ 720 #define FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG (1) 721 722 /* USB module features */ 723 724 #if defined(CPU_LPC55S36JBD100) 725 /* @brief USB version */ 726 #define FSL_FEATURE_USB_VERSION (200) 727 /* @brief Number of the endpoint in USB FS */ 728 #define FSL_FEATURE_USB_EP_NUM (5) 729 #endif /* defined(CPU_LPC55S36JBD100) */ 730 731 /* USBFSH module features */ 732 733 #if defined(CPU_LPC55S36JBD100) 734 /* @brief USBFSH version */ 735 #define FSL_FEATURE_USBFSH_VERSION (200) 736 #endif /* defined(CPU_LPC55S36JBD100) */ 737 738 /* VREF module features */ 739 740 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 741 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (0) 742 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 743 #define FSL_FEATURE_VREF_HAS_COMPENSATION (0) 744 /* @brief If high/low buffer mode supported */ 745 #define FSL_FEATURE_VREF_MODE_LV_TYPE (0) 746 /* @brief Module has also low reference (registers VREFL/VREFH) */ 747 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 748 /* @brief Has VREF_TRM4. */ 749 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 750 751 /* WWDT module features */ 752 753 /* @brief Has no RESET register. */ 754 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 755 756 #endif /* _LPC55S36_FEATURES_H_ */ 757 758
