1 /* 2 ** ################################################################### 3 ** Version: rev. 1.1, 2019-05-16 4 ** Build: b220725 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2018-08-22) 20 ** Initial version based on v0.2UM 21 ** - rev. 1.1 (2019-05-16) 22 ** Initial A1 version based on v1.3UM 23 ** 24 ** ################################################################### 25 */ 26 27 #ifndef _LPC55S28_FEATURES_H_ 28 #define _LPC55S28_FEATURES_H_ 29 30 /* SOC module features */ 31 32 /* @brief CASPER availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 34 /* @brief CRC availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CRC_COUNT (1) 36 /* @brief CTIMER availability on the SoC. */ 37 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 38 /* @brief DMA availability on the SoC. */ 39 #define FSL_FEATURE_SOC_DMA_COUNT (2) 40 /* @brief FLASH availability on the SoC. */ 41 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 42 /* @brief FLEXCOMM availability on the SoC. */ 43 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 44 /* @brief GINT availability on the SoC. */ 45 #define FSL_FEATURE_SOC_GINT_COUNT (2) 46 /* @brief GPIO availability on the SoC. */ 47 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 48 /* @brief SECGPIO availability on the SoC. */ 49 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 50 /* @brief HASHCRYPT availability on the SoC. */ 51 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 52 /* @brief I2C availability on the SoC. */ 53 #define FSL_FEATURE_SOC_I2C_COUNT (8) 54 /* @brief I2S availability on the SoC. */ 55 #define FSL_FEATURE_SOC_I2S_COUNT (8) 56 /* @brief INPUTMUX availability on the SoC. */ 57 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 58 /* @brief IOCON availability on the SoC. */ 59 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 60 /* @brief LPADC availability on the SoC. */ 61 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 62 /* @brief MPU availability on the SoC. */ 63 #define FSL_FEATURE_SOC_MPU_COUNT (1) 64 /* @brief MRT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_MRT_COUNT (1) 66 /* @brief OSTIMER availability on the SoC. */ 67 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 68 /* @brief PINT availability on the SoC. */ 69 #define FSL_FEATURE_SOC_PINT_COUNT (1) 70 /* @brief SECPINT availability on the SoC. */ 71 #define FSL_FEATURE_SOC_SECPINT_COUNT (1) 72 /* @brief PMC availability on the SoC. */ 73 #define FSL_FEATURE_SOC_PMC_COUNT (1) 74 /* @brief PUF availability on the SoC. */ 75 #define FSL_FEATURE_SOC_PUF_COUNT (1) 76 /* @brief LPC_RNG1 availability on the SoC. */ 77 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) 78 /* @brief RTC availability on the SoC. */ 79 #define FSL_FEATURE_SOC_RTC_COUNT (1) 80 /* @brief SCT availability on the SoC. */ 81 #define FSL_FEATURE_SOC_SCT_COUNT (1) 82 /* @brief SDIF availability on the SoC. */ 83 #define FSL_FEATURE_SOC_SDIF_COUNT (1) 84 /* @brief SPI availability on the SoC. */ 85 #define FSL_FEATURE_SOC_SPI_COUNT (9) 86 /* @brief SYSCON availability on the SoC. */ 87 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 88 /* @brief SYSCTL1 availability on the SoC. */ 89 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 90 /* @brief USART availability on the SoC. */ 91 #define FSL_FEATURE_SOC_USART_COUNT (8) 92 /* @brief USB availability on the SoC. */ 93 #define FSL_FEATURE_SOC_USB_COUNT (1) 94 /* @brief USBFSH availability on the SoC. */ 95 #define FSL_FEATURE_SOC_USBFSH_COUNT (1) 96 /* @brief USBHSD availability on the SoC. */ 97 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 98 /* @brief USBHSH availability on the SoC. */ 99 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 100 /* @brief USBPHY availability on the SoC. */ 101 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 102 /* @brief UTICK availability on the SoC. */ 103 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 104 /* @brief WWDT availability on the SoC. */ 105 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 106 107 /* LPADC module features */ 108 109 /* @brief FIFO availability on the SoC. */ 110 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 111 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 112 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 113 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 114 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 115 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 116 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 117 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 118 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 119 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 120 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 121 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 122 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 123 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 124 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 125 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 126 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 127 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 128 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 129 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 130 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 131 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 132 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 133 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 134 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 135 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 136 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 137 /* @brief Has offset trim (register OFSTRIM). */ 138 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 139 /* @brief Has Trigger status register. */ 140 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 141 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 142 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 143 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 144 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 145 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 146 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 147 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 148 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 149 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 150 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 151 /* @brief Conversion averaged bitfiled width. */ 152 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 153 /* @brief Has internal temperature sensor. */ 154 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 155 /* @brief Temperature sensor parameter A (slope). */ 156 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f) 157 /* @brief Temperature sensor parameter B (offset). */ 158 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f) 159 /* @brief Temperature sensor parameter Alpha. */ 160 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f) 161 /* @brief the buffer size of temperature sensor. */ 162 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) 163 164 /* ANALOGCTRL module features */ 165 166 /* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ 167 #define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) 168 /* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ 169 #define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) 170 /* @brief Has auxiliary bias(register AUX_BIAS). */ 171 #define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) 172 173 /* CASPER module features */ 174 175 /* @brief Base address of the CASPER dedicated RAM */ 176 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) 177 /* @brief SW interleaving of the CASPER dedicated RAM */ 178 #define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) 179 /* @brief CASPER dedicated RAM offset */ 180 #define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) 181 182 /* CTIMER module features */ 183 184 /* @brief CTIMER has no capture channel. */ 185 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 186 /* @brief CTIMER has no capture 2 interrupt. */ 187 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 188 /* @brief CTIMER capture 3 interrupt. */ 189 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 190 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 191 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 192 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 193 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 194 /* @brief CTIMER Has register MSR */ 195 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 196 197 /* DMA module features */ 198 199 /* @brief Number of channels */ 200 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) 201 /* @brief Align size of DMA descriptor */ 202 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 203 /* @brief DMA head link descriptor table align size */ 204 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 205 206 /* FLEXCOMM module features */ 207 208 /* @brief FLEXCOMM0 USART INDEX 0 */ 209 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 210 /* @brief FLEXCOMM0 SPI INDEX 0 */ 211 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 212 /* @brief FLEXCOMM0 I2C INDEX 0 */ 213 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 214 /* @brief FLEXCOMM0 I2S INDEX 0 */ 215 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 216 /* @brief FLEXCOMM1 USART INDEX 1 */ 217 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 218 /* @brief FLEXCOMM1 SPI INDEX 1 */ 219 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 220 /* @brief FLEXCOMM1 I2C INDEX 1 */ 221 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 222 /* @brief FLEXCOMM1 I2S INDEX 1 */ 223 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 224 /* @brief FLEXCOMM2 USART INDEX 2 */ 225 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 226 /* @brief FLEXCOMM2 SPI INDEX 2 */ 227 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 228 /* @brief FLEXCOMM2 I2C INDEX 2 */ 229 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 230 /* @brief FLEXCOMM2 I2S INDEX 2 */ 231 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 232 /* @brief FLEXCOMM3 USART INDEX 3 */ 233 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 234 /* @brief FLEXCOMM3 SPI INDEX 3 */ 235 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 236 /* @brief FLEXCOMM3 I2C INDEX 3 */ 237 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 238 /* @brief FLEXCOMM3 I2S INDEX 3 */ 239 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 240 /* @brief FLEXCOMM4 USART INDEX 4 */ 241 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 242 /* @brief FLEXCOMM4 SPI INDEX 4 */ 243 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 244 /* @brief FLEXCOMM4 I2C INDEX 4 */ 245 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 246 /* @brief FLEXCOMM4 I2S INDEX 4 */ 247 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 248 /* @brief FLEXCOMM5 USART INDEX 5 */ 249 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 250 /* @brief FLEXCOMM5 SPI INDEX 5 */ 251 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 252 /* @brief FLEXCOMM5 I2C INDEX 5 */ 253 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 254 /* @brief FLEXCOMM5 I2S INDEX 5 */ 255 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 256 /* @brief FLEXCOMM6 USART INDEX 6 */ 257 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 258 /* @brief FLEXCOMM6 SPI INDEX 6 */ 259 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 260 /* @brief FLEXCOMM6 I2C INDEX 6 */ 261 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 262 /* @brief FLEXCOMM6 I2S INDEX 6 */ 263 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 264 /* @brief FLEXCOMM7 USART INDEX 7 */ 265 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 266 /* @brief FLEXCOMM7 SPI INDEX 7 */ 267 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 268 /* @brief FLEXCOMM7 I2C INDEX 7 */ 269 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 270 /* @brief FLEXCOMM7 I2S INDEX 7 */ 271 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 272 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 273 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 274 /* @brief I2S has DMIC interconnection */ 275 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) 276 277 /* GINT module features */ 278 279 /* @brief The count of th port which are supported in GINT. */ 280 #define FSL_FEATURE_GINT_PORT_COUNT (2) 281 282 /* HASHCRYPT module features */ 283 284 /* @brief the address of alias offset */ 285 #define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) 286 287 /* I2S module features */ 288 289 /* @brief I2S support dual channel transfer. */ 290 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) 291 /* @brief I2S has DMIC interconnection */ 292 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) 293 294 /* IOCON module features */ 295 296 /* @brief Func bit field width */ 297 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 298 299 /* MRT module features */ 300 301 /* @brief number of channels. */ 302 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 303 304 /* PINT module features */ 305 306 /* @brief Number of connected outputs */ 307 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 308 309 /* PLU module features */ 310 311 /* @brief Has WAKEINT_CTRL register. */ 312 #define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) 313 314 /* PMC module features */ 315 316 /* @brief UTICK does not support PD configure. */ 317 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 318 /* @brief WDT OSC does not support PD configure. */ 319 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 320 321 /* POWERLIB module features */ 322 323 /* @brief Powerlib API is different with other LPC series devices. */ 324 #define FSL_FEATURE_POWERLIB_EXTEND (1) 325 326 /* PUF module features */ 327 328 /* @brief Number of PUF key slots available on device. */ 329 #define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) 330 /* @brief the shift status value */ 331 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) 332 333 /* RTC module features */ 334 335 /* No feature definitions */ 336 337 /* SCT module features */ 338 339 /* @brief Number of events */ 340 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 341 /* @brief Number of states */ 342 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 343 /* @brief Number of match capture */ 344 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 345 /* @brief Number of outputs */ 346 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 347 348 /* SDIF module features */ 349 350 /* @brief FIFO depth, every location is a WORD */ 351 #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) 352 /* @brief Max DMA buffer size */ 353 #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) 354 /* @brief Max source clock in HZ */ 355 #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) 356 /* @brief support 2 cards */ 357 #define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) 358 359 /* SECPINT module features */ 360 361 /* @brief Number of connected outputs */ 362 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) 363 364 /* SPI module features */ 365 366 /* @brief SSEL pin count. */ 367 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 368 369 /* SYSCON module features */ 370 371 /* @brief Flash page size in bytes */ 372 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) 373 /* @brief Flash sector size in bytes */ 374 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) 375 /* @brief Flash size in bytes */ 376 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) 377 /* @brief Has Power Down mode */ 378 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) 379 /* @brief CCM_ANALOG availability on the SoC. */ 380 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 381 /* @brief Starter register discontinuous. */ 382 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 383 384 /* SYSCTL1 module features */ 385 386 /* No feature definitions */ 387 388 /* USB module features */ 389 390 /* @brief Size of the USB dedicated RAM */ 391 #define FSL_FEATURE_USB_USB_RAM (0x00004000) 392 /* @brief Base address of the USB dedicated RAM */ 393 #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) 394 /* @brief USB version */ 395 #define FSL_FEATURE_USB_VERSION (200) 396 /* @brief Number of the endpoint in USB FS */ 397 #define FSL_FEATURE_USB_EP_NUM (5) 398 399 /* USBFSH module features */ 400 401 /* @brief Size of the USB dedicated RAM */ 402 #define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) 403 /* @brief Base address of the USB dedicated RAM */ 404 #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) 405 /* @brief USBFSH version */ 406 #define FSL_FEATURE_USBFSH_VERSION (200) 407 408 /* USBHSD module features */ 409 410 /* @brief Size of the USB dedicated RAM */ 411 #define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) 412 /* @brief Base address of the USB dedicated RAM */ 413 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) 414 /* @brief USBHSD version */ 415 #define FSL_FEATURE_USBHSD_VERSION (300) 416 /* @brief Number of the endpoint in USB HS */ 417 #define FSL_FEATURE_USBHSD_EP_NUM (6) 418 419 /* USBHSH module features */ 420 421 /* @brief Size of the USB dedicated RAM */ 422 #define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) 423 /* @brief Base address of the USB dedicated RAM */ 424 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) 425 /* @brief USBHSH version */ 426 #define FSL_FEATURE_USBHSH_VERSION (300) 427 428 /* USBPHY module features */ 429 430 /* @brief Size of the USB dedicated RAM */ 431 #define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) 432 /* @brief Base address of the USB dedicated RAM */ 433 #define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) 434 /* @brief USBHSD version */ 435 #define FSL_FEATURE_USBPHY_VERSION (300) 436 /* @brief Number of the endpoint in USB HS */ 437 #define FSL_FEATURE_USBPHY_EP_NUM (6) 438 439 /* WWDT module features */ 440 441 /* @brief Has no RESET register. */ 442 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 443 /* @brief WWDT does not support oscillator lock. */ 444 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) 445 446 #endif /* _LPC55S28_FEATURES_H_ */ 447 448
