1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2020-04-09 4 ** Build: b231016 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2023 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2020-04-09) 18 ** Initial version based on Niobe4mini 19 ** 20 ** ################################################################### 21 */ 22 23 #ifndef _LPC55S06_FEATURES_H_ 24 #define _LPC55S06_FEATURES_H_ 25 26 /* SOC module features */ 27 28 #if defined(CPU_LPC55S06JBD64) 29 /* @brief LPC_CAN availability on the SoC. */ 30 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) 31 /* @brief CASPER availability on the SoC. */ 32 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 33 /* @brief CDOG availability on the SoC. */ 34 #define FSL_FEATURE_SOC_CDOG_COUNT (1) 35 /* @brief CRC availability on the SoC. */ 36 #define FSL_FEATURE_SOC_CRC_COUNT (1) 37 /* @brief CTIMER availability on the SoC. */ 38 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 39 /* @brief DMA availability on the SoC. */ 40 #define FSL_FEATURE_SOC_DMA_COUNT (2) 41 /* @brief FLASH availability on the SoC. */ 42 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 43 /* @brief FLEXCOMM availability on the SoC. */ 44 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 45 /* @brief GINT availability on the SoC. */ 46 #define FSL_FEATURE_SOC_GINT_COUNT (2) 47 /* @brief GPIO availability on the SoC. */ 48 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 49 /* @brief SECGPIO availability on the SoC. */ 50 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 51 /* @brief HASHCRYPT availability on the SoC. */ 52 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 53 /* @brief I2C availability on the SoC. */ 54 #define FSL_FEATURE_SOC_I2C_COUNT (8) 55 /* @brief I2S availability on the SoC. */ 56 #define FSL_FEATURE_SOC_I2S_COUNT (8) 57 /* @brief INPUTMUX availability on the SoC. */ 58 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 59 /* @brief IOCON availability on the SoC. */ 60 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 61 /* @brief LPADC availability on the SoC. */ 62 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 63 /* @brief MPU availability on the SoC. */ 64 #define FSL_FEATURE_SOC_MPU_COUNT (1) 65 /* @brief MRT availability on the SoC. */ 66 #define FSL_FEATURE_SOC_MRT_COUNT (1) 67 /* @brief OSTIMER availability on the SoC. */ 68 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 69 /* @brief PINT availability on the SoC. */ 70 #define FSL_FEATURE_SOC_PINT_COUNT (1) 71 /* @brief SECPINT availability on the SoC. */ 72 #define FSL_FEATURE_SOC_SECPINT_COUNT (1) 73 /* @brief PMC availability on the SoC. */ 74 #define FSL_FEATURE_SOC_PMC_COUNT (1) 75 /* @brief PUF availability on the SoC. */ 76 #define FSL_FEATURE_SOC_PUF_COUNT (1) 77 /* @brief PUF_SRAM_CTRL availability on the SoC. */ 78 #define FSL_FEATURE_SOC_PUF_SRAM_CTRL_COUNT (1) 79 /* @brief LPC_RNG1 availability on the SoC. */ 80 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) 81 /* @brief RTC availability on the SoC. */ 82 #define FSL_FEATURE_SOC_RTC_COUNT (1) 83 /* @brief SCT availability on the SoC. */ 84 #define FSL_FEATURE_SOC_SCT_COUNT (1) 85 /* @brief SPI availability on the SoC. */ 86 #define FSL_FEATURE_SOC_SPI_COUNT (7) 87 /* @brief SYSCON availability on the SoC. */ 88 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 89 /* @brief SYSCTL1 availability on the SoC. */ 90 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 91 /* @brief USART availability on the SoC. */ 92 #define FSL_FEATURE_SOC_USART_COUNT (8) 93 /* @brief UTICK availability on the SoC. */ 94 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 95 /* @brief WWDT availability on the SoC. */ 96 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 97 #elif defined(CPU_LPC55S06JHI48) 98 /* @brief LPC_CAN availability on the SoC. */ 99 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) 100 /* @brief CASPER availability on the SoC. */ 101 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 102 /* @brief CDOG availability on the SoC. */ 103 #define FSL_FEATURE_SOC_CDOG_COUNT (1) 104 /* @brief CRC availability on the SoC. */ 105 #define FSL_FEATURE_SOC_CRC_COUNT (1) 106 /* @brief CTIMER availability on the SoC. */ 107 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 108 /* @brief DMA availability on the SoC. */ 109 #define FSL_FEATURE_SOC_DMA_COUNT (2) 110 /* @brief FLASH availability on the SoC. */ 111 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 112 /* @brief FLEXCOMM availability on the SoC. */ 113 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8) 114 /* @brief GINT availability on the SoC. */ 115 #define FSL_FEATURE_SOC_GINT_COUNT (2) 116 /* @brief GPIO availability on the SoC. */ 117 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 118 /* @brief SECGPIO availability on the SoC. */ 119 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 120 /* @brief HASHCRYPT availability on the SoC. */ 121 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 122 /* @brief I2C availability on the SoC. */ 123 #define FSL_FEATURE_SOC_I2C_COUNT (7) 124 /* @brief I2S availability on the SoC. */ 125 #define FSL_FEATURE_SOC_I2S_COUNT (4) 126 /* @brief INPUTMUX availability on the SoC. */ 127 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 128 /* @brief IOCON availability on the SoC. */ 129 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 130 /* @brief LPADC availability on the SoC. */ 131 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 132 /* @brief MPU availability on the SoC. */ 133 #define FSL_FEATURE_SOC_MPU_COUNT (1) 134 /* @brief MRT availability on the SoC. */ 135 #define FSL_FEATURE_SOC_MRT_COUNT (1) 136 /* @brief OSTIMER availability on the SoC. */ 137 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 138 /* @brief PINT availability on the SoC. */ 139 #define FSL_FEATURE_SOC_PINT_COUNT (1) 140 /* @brief SECPINT availability on the SoC. */ 141 #define FSL_FEATURE_SOC_SECPINT_COUNT (1) 142 /* @brief PMC availability on the SoC. */ 143 #define FSL_FEATURE_SOC_PMC_COUNT (1) 144 /* @brief PUF availability on the SoC. */ 145 #define FSL_FEATURE_SOC_PUF_COUNT (1) 146 /* @brief PUF_SRAM_CTRL availability on the SoC. */ 147 #define FSL_FEATURE_SOC_PUF_SRAM_CTRL_COUNT (1) 148 /* @brief LPC_RNG1 availability on the SoC. */ 149 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) 150 /* @brief RTC availability on the SoC. */ 151 #define FSL_FEATURE_SOC_RTC_COUNT (1) 152 /* @brief SCT availability on the SoC. */ 153 #define FSL_FEATURE_SOC_SCT_COUNT (1) 154 /* @brief SPI availability on the SoC. */ 155 #define FSL_FEATURE_SOC_SPI_COUNT (4) 156 /* @brief SYSCON availability on the SoC. */ 157 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 158 /* @brief SYSCTL1 availability on the SoC. */ 159 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 160 /* @brief USART availability on the SoC. */ 161 #define FSL_FEATURE_SOC_USART_COUNT (7) 162 /* @brief UTICK availability on the SoC. */ 163 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 164 /* @brief WWDT availability on the SoC. */ 165 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 166 #endif 167 168 /* LPADC module features */ 169 170 /* @brief FIFO availability on the SoC. */ 171 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 172 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 173 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 174 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 175 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 176 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 177 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 178 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 179 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 180 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 181 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 182 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 183 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 184 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 185 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 186 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 187 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 188 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 189 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 190 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 191 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 192 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 193 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 194 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 195 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 196 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 197 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 198 /* @brief Has offset trim (register OFSTRIM). */ 199 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 200 /* @brief OFSTRIM availability on the SoC. */ 201 #define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) 202 /* @brief Has Trigger status register. */ 203 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 204 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 205 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 206 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 207 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 208 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 209 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 210 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 211 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 212 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 213 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 214 /* @brief Conversion averaged bitfiled width. */ 215 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 216 /* @brief Has B side channels. */ 217 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 218 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 219 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) 220 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 221 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) 222 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 223 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) 224 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 225 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 226 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 227 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) 228 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 229 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) 230 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 231 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) 232 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 233 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) 234 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 235 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) 236 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 237 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) 238 /* @brief Has internal temperature sensor. */ 239 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 240 /* @brief Temperature sensor parameter A (slope). */ 241 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (799.0f) 242 /* @brief Temperature sensor parameter B (offset). */ 243 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (280.0f) 244 /* @brief Temperature sensor parameter Alpha. */ 245 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (8.5f) 246 /* @brief Temperature sensor need calibration. */ 247 #define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1) 248 /* @brief the address of temperature sensor parameter A (slope) in Flash. */ 249 #define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U) 250 /* @brief the address of temperature sensor parameter B (offset) in Flash. */ 251 #define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU) 252 /* @brief the buffer size of temperature sensor. */ 253 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) 254 255 /* ANALOGCTRL module features */ 256 257 /* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ 258 #define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) 259 /* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ 260 #define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1) 261 /* @brief Has auxiliary bias(register AUX_BIAS). */ 262 #define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) 263 264 /* CAN module features */ 265 266 /* @brief Support CANFD or not */ 267 #define FSL_FEATURE_CAN_SUPPORT_CANFD (1) 268 269 /* CASPER module features */ 270 271 /* @brief Base address of the CASPER dedicated RAM */ 272 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) 273 /* @brief HW interleaving of the CASPER dedicated RAM */ 274 #define FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE (1) 275 276 /* CDOG module features */ 277 278 /* No feature definitions */ 279 280 /* CTIMER module features */ 281 282 /* @brief CTIMER has no capture channel. */ 283 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 284 /* @brief CTIMER has no capture 2 interrupt. */ 285 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 286 /* @brief CTIMER capture 3 interrupt. */ 287 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 288 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 289 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 290 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 291 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 292 /* @brief CTIMER Has register MSR */ 293 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 294 295 /* DMA module features */ 296 297 /* @brief Number of channels */ 298 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) 299 /* @brief Align size of DMA descriptor */ 300 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 301 /* @brief DMA head link descriptor table align size */ 302 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 303 304 /* FLEXCOMM module features */ 305 306 #if defined(CPU_LPC55S06JBD64) 307 /* @brief FLEXCOMM0 USART INDEX 0 */ 308 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 309 /* @brief FLEXCOMM0 SPI INDEX 0 */ 310 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 311 /* @brief FLEXCOMM0 I2C INDEX 0 */ 312 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 313 /* @brief FLEXCOMM0 I2S INDEX 0 */ 314 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 315 /* @brief FLEXCOMM1 USART INDEX 1 */ 316 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 317 /* @brief FLEXCOMM1 SPI INDEX 1 */ 318 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 319 /* @brief FLEXCOMM1 I2C INDEX 1 */ 320 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 321 /* @brief FLEXCOMM1 I2S INDEX 1 */ 322 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 323 /* @brief FLEXCOMM2 USART INDEX 2 */ 324 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 325 /* @brief FLEXCOMM2 I2C INDEX 2 */ 326 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 327 /* @brief FLEXCOMM2 I2S INDEX 2 */ 328 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 329 /* @brief FLEXCOMM3 USART INDEX 3 */ 330 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 331 /* @brief FLEXCOMM3 SPI INDEX 3 */ 332 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 333 /* @brief FLEXCOMM3 I2C INDEX 3 */ 334 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 335 /* @brief FLEXCOMM3 I2S INDEX 3 */ 336 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 337 /* @brief FLEXCOMM4 USART INDEX 4 */ 338 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 339 /* @brief FLEXCOMM4 SPI INDEX 4 */ 340 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 341 /* @brief FLEXCOMM4 I2C INDEX 4 */ 342 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 343 /* @brief FLEXCOMM4 I2S INDEX 4 */ 344 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 345 /* @brief FLEXCOMM5 USART INDEX 5 */ 346 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 347 /* @brief FLEXCOMM5 I2C INDEX 5 */ 348 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 349 /* @brief FLEXCOMM5 I2S INDEX 5 */ 350 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 351 /* @brief FLEXCOMM6 USART INDEX 6 */ 352 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 353 /* @brief FLEXCOMM6 SPI INDEX 6 */ 354 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 355 /* @brief FLEXCOMM6 I2C INDEX 6 */ 356 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 357 /* @brief FLEXCOMM6 I2S INDEX 6 */ 358 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 359 /* @brief FLEXCOMM7 USART INDEX 7 */ 360 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 361 /* @brief FLEXCOMM7 SPI INDEX 7 */ 362 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 363 /* @brief FLEXCOMM7 I2C INDEX 7 */ 364 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 365 /* @brief FLEXCOMM7 I2S INDEX 7 */ 366 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 367 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 368 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 369 /* @brief I2S has DMIC interconnection */ 370 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) 371 /* @brief I2S support dual channel transfer */ 372 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ 373 (((x) == FLEXCOMM0) ? (0) : \ 374 (((x) == FLEXCOMM1) ? (0) : \ 375 (((x) == FLEXCOMM2) ? (0) : \ 376 (((x) == FLEXCOMM3) ? (0) : \ 377 (((x) == FLEXCOMM4) ? (0) : \ 378 (((x) == FLEXCOMM5) ? (0) : \ 379 (((x) == FLEXCOMM6) ? (1) : \ 380 (((x) == FLEXCOMM7) ? (1) : \ 381 (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) 382 #elif defined(CPU_LPC55S06JHI48) 383 /* @brief FLEXCOMM0 USART INDEX 0 */ 384 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 385 /* @brief FLEXCOMM0 SPI INDEX 0 */ 386 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 387 /* @brief FLEXCOMM0 I2C INDEX 0 */ 388 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 389 /* @brief FLEXCOMM0 I2S INDEX 0 */ 390 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 391 /* @brief FLEXCOMM1 USART INDEX 1 */ 392 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 393 /* @brief FLEXCOMM1 I2C INDEX 1 */ 394 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 395 /* @brief FLEXCOMM2 USART INDEX 2 */ 396 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 397 /* @brief FLEXCOMM2 I2C INDEX 2 */ 398 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 399 /* @brief FLEXCOMM3 USART INDEX 3 */ 400 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 401 /* @brief FLEXCOMM3 SPI INDEX 3 */ 402 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 403 /* @brief FLEXCOMM3 I2C INDEX 3 */ 404 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 405 /* @brief FLEXCOMM3 I2S INDEX 3 */ 406 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 407 /* @brief FLEXCOMM4 USART INDEX 4 */ 408 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 409 /* @brief FLEXCOMM4 I2C INDEX 4 */ 410 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 411 /* @brief FLEXCOMM4 I2S INDEX 4 */ 412 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 413 /* @brief FLEXCOMM5 USART INDEX 5 */ 414 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 415 /* @brief FLEXCOMM5 I2C INDEX 5 */ 416 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 417 /* @brief FLEXCOMM6 USART INDEX 6 */ 418 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 419 /* @brief FLEXCOMM6 SPI INDEX 6 */ 420 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 421 /* @brief FLEXCOMM6 I2C INDEX 6 */ 422 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 423 /* @brief FLEXCOMM6 I2S INDEX 6 */ 424 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 425 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 426 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 427 /* @brief I2S has DMIC interconnection */ 428 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) 429 /* @brief I2S support dual channel transfer */ 430 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ 431 (((x) == FLEXCOMM0) ? (0) : \ 432 (((x) == FLEXCOMM1) ? (0) : \ 433 (((x) == FLEXCOMM2) ? (0) : \ 434 (((x) == FLEXCOMM3) ? (0) : \ 435 (((x) == FLEXCOMM4) ? (0) : \ 436 (((x) == FLEXCOMM5) ? (0) : \ 437 (((x) == FLEXCOMM6) ? (1) : \ 438 (((x) == FLEXCOMM8) ? (0) : (-1))))))))) 439 #endif /* defined(CPU_LPC55S06JBD64) */ 440 441 /* GINT module features */ 442 443 /* @brief The count of th port which are supported in GINT. */ 444 #define FSL_FEATURE_GINT_PORT_COUNT (2) 445 446 /* HASHCRYPT module features */ 447 448 /* @brief the address of alias offset */ 449 #define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) 450 /* @brief hashcrypt has reload feature */ 451 #define FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE (1) 452 453 /* I2S module features */ 454 455 /* @brief I2S6 and I2S7 support dual channel transfer. */ 456 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 457 /* @brief I2S has DMIC interconnection */ 458 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) 459 460 /* INPUTMUX module features */ 461 462 /* @brief Inputmux has DMA Request Enable */ 463 #define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (0) 464 /* @brief Inputmux has channel mux control */ 465 #define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) 466 467 /* IOCON module features */ 468 469 /* @brief Func bit field width */ 470 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 471 472 /* MRT module features */ 473 474 /* @brief number of channels. */ 475 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 476 477 /* PINT module features */ 478 479 /* @brief Number of connected outputs */ 480 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 481 482 /* PLU module features */ 483 484 /* @brief Has WAKEINT_CTRL register. */ 485 #define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) 486 487 /* PMC module features */ 488 489 /* @brief UTICK does not support PD configure. */ 490 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 491 /* @brief WDT OSC does not support PD configure. */ 492 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 493 494 /* POWERLIB module features */ 495 496 /* @brief Powerlib API is different with other LPC series devices. */ 497 #define FSL_FEATURE_POWERLIB_EXTEND (1) 498 499 /* PUF module features */ 500 501 /* @brief Number of PUF key slots available on device. */ 502 #define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) 503 /* @brief the shift status value */ 504 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) 505 /* @brief PUF has dedicated SRAM control */ 506 #define FSL_FEATURE_PUF_HAS_SRAM_CTRL (1) 507 /* @brief Puf Activation Code Address. */ 508 #define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (255488) 509 /* @brief Puf Activation Code Size. */ 510 #define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1192) 511 512 /* RTC module features */ 513 514 /* @brief Has SUBSEC Register (register SUBSEC) */ 515 #define FSL_FEATURE_RTC_HAS_SUBSEC (1) 516 517 /* SCT module features */ 518 519 /* @brief Number of events */ 520 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 521 /* @brief Number of states */ 522 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 523 /* @brief Number of match capture */ 524 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 525 /* @brief Number of outputs */ 526 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 527 528 /* SECPINT module features */ 529 530 /* @brief Number of connected outputs */ 531 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) 532 533 /* SPI module features */ 534 535 /* @brief SSEL pin count. */ 536 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 537 538 /* SYSCON module features */ 539 540 /* @brief Flash page size in bytes */ 541 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) 542 /* @brief Flash sector size in bytes */ 543 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) 544 /* @brief Flash size in bytes */ 545 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (249856) 546 /* @brief Has Power Down mode */ 547 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) 548 /* @brief CCM_ANALOG availability on the SoC. */ 549 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 550 /* @brief Starter register discontinuous. */ 551 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 552 553 /* SYSCTL1 module features */ 554 555 /* @brief SYSCTRL has Code Gray feature. */ 556 #define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) 557 558 /* WWDT module features */ 559 560 /* @brief Has no RESET register. */ 561 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 562 /* @brief WWDT does not support oscillator lock. */ 563 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) 564 565 #endif /* _LPC55S06_FEATURES_H_ */ 566 567
