1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2020-04-09 4 ** Build: b220725 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2020-04-09) 20 ** Initial version based on Niobe4mini 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _LPC55S04_FEATURES_H_ 26 #define _LPC55S04_FEATURES_H_ 27 28 /* SOC module features */ 29 30 #if defined(CPU_LPC55S04JBD64) 31 /* @brief LPC_CAN availability on the SoC. */ 32 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) 33 /* @brief CASPER availability on the SoC. */ 34 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 35 /* @brief CRC availability on the SoC. */ 36 #define FSL_FEATURE_SOC_CRC_COUNT (1) 37 /* @brief CTIMER availability on the SoC. */ 38 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 39 /* @brief CDOG availability on the SoC. */ 40 #define FSL_FEATURE_SOC_CDOG_COUNT (1) 41 /* @brief DMA availability on the SoC. */ 42 #define FSL_FEATURE_SOC_DMA_COUNT (2) 43 /* @brief FLASH availability on the SoC. */ 44 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 45 /* @brief FLEXCOMM availability on the SoC. */ 46 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 47 /* @brief GINT availability on the SoC. */ 48 #define FSL_FEATURE_SOC_GINT_COUNT (2) 49 /* @brief GPIO availability on the SoC. */ 50 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 51 /* @brief SECGPIO availability on the SoC. */ 52 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 53 /* @brief HASHCRYPT availability on the SoC. */ 54 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 55 /* @brief I2C availability on the SoC. */ 56 #define FSL_FEATURE_SOC_I2C_COUNT (8) 57 /* @brief I2S availability on the SoC. */ 58 #define FSL_FEATURE_SOC_I2S_COUNT (8) 59 /* @brief INPUTMUX availability on the SoC. */ 60 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 61 /* @brief IOCON availability on the SoC. */ 62 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 63 /* @brief LPADC availability on the SoC. */ 64 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 65 /* @brief MPU availability on the SoC. */ 66 #define FSL_FEATURE_SOC_MPU_COUNT (1) 67 /* @brief MRT availability on the SoC. */ 68 #define FSL_FEATURE_SOC_MRT_COUNT (1) 69 /* @brief OSTIMER availability on the SoC. */ 70 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 71 /* @brief PINT availability on the SoC. */ 72 #define FSL_FEATURE_SOC_PINT_COUNT (1) 73 /* @brief SECPINT availability on the SoC. */ 74 #define FSL_FEATURE_SOC_SECPINT_COUNT (1) 75 /* @brief PMC availability on the SoC. */ 76 #define FSL_FEATURE_SOC_PMC_COUNT (1) 77 /* @brief PUF availability on the SoC. */ 78 #define FSL_FEATURE_SOC_PUF_COUNT (1) 79 /* @brief PUF_SRAM_CTRL availability on the SoC. */ 80 #define FSL_FEATURE_SOC_PUF_SRAM_CTRL_COUNT (1) 81 /* @brief LPC_RNG1 availability on the SoC. */ 82 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) 83 /* @brief RTC availability on the SoC. */ 84 #define FSL_FEATURE_SOC_RTC_COUNT (1) 85 /* @brief SCT availability on the SoC. */ 86 #define FSL_FEATURE_SOC_SCT_COUNT (1) 87 /* @brief SPI availability on the SoC. */ 88 #define FSL_FEATURE_SOC_SPI_COUNT (7) 89 /* @brief SYSCON availability on the SoC. */ 90 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 91 /* @brief SYSCTL1 availability on the SoC. */ 92 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 93 /* @brief USART availability on the SoC. */ 94 #define FSL_FEATURE_SOC_USART_COUNT (8) 95 /* @brief UTICK availability on the SoC. */ 96 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 97 /* @brief WWDT availability on the SoC. */ 98 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 99 #elif defined(CPU_LPC55S04JHI48) 100 /* @brief LPC_CAN availability on the SoC. */ 101 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) 102 /* @brief CASPER availability on the SoC. */ 103 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 104 /* @brief CRC availability on the SoC. */ 105 #define FSL_FEATURE_SOC_CRC_COUNT (1) 106 /* @brief CTIMER availability on the SoC. */ 107 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 108 /* @brief CDOG availability on the SoC. */ 109 #define FSL_FEATURE_SOC_CDOG_COUNT (1) 110 /* @brief DMA availability on the SoC. */ 111 #define FSL_FEATURE_SOC_DMA_COUNT (2) 112 /* @brief FLASH availability on the SoC. */ 113 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 114 /* @brief FLEXCOMM availability on the SoC. */ 115 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8) 116 /* @brief GINT availability on the SoC. */ 117 #define FSL_FEATURE_SOC_GINT_COUNT (2) 118 /* @brief GPIO availability on the SoC. */ 119 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 120 /* @brief SECGPIO availability on the SoC. */ 121 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 122 /* @brief HASHCRYPT availability on the SoC. */ 123 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 124 /* @brief I2C availability on the SoC. */ 125 #define FSL_FEATURE_SOC_I2C_COUNT (7) 126 /* @brief I2S availability on the SoC. */ 127 #define FSL_FEATURE_SOC_I2S_COUNT (4) 128 /* @brief INPUTMUX availability on the SoC. */ 129 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 130 /* @brief IOCON availability on the SoC. */ 131 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 132 /* @brief LPADC availability on the SoC. */ 133 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 134 /* @brief MPU availability on the SoC. */ 135 #define FSL_FEATURE_SOC_MPU_COUNT (1) 136 /* @brief MRT availability on the SoC. */ 137 #define FSL_FEATURE_SOC_MRT_COUNT (1) 138 /* @brief OSTIMER availability on the SoC. */ 139 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 140 /* @brief PINT availability on the SoC. */ 141 #define FSL_FEATURE_SOC_PINT_COUNT (1) 142 /* @brief SECPINT availability on the SoC. */ 143 #define FSL_FEATURE_SOC_SECPINT_COUNT (1) 144 /* @brief PMC availability on the SoC. */ 145 #define FSL_FEATURE_SOC_PMC_COUNT (1) 146 /* @brief PUF availability on the SoC. */ 147 #define FSL_FEATURE_SOC_PUF_COUNT (1) 148 /* @brief PUF_SRAM_CTRL availability on the SoC. */ 149 #define FSL_FEATURE_SOC_PUF_SRAM_CTRL_COUNT (1) 150 /* @brief LPC_RNG1 availability on the SoC. */ 151 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) 152 /* @brief RTC availability on the SoC. */ 153 #define FSL_FEATURE_SOC_RTC_COUNT (1) 154 /* @brief SCT availability on the SoC. */ 155 #define FSL_FEATURE_SOC_SCT_COUNT (1) 156 /* @brief SPI availability on the SoC. */ 157 #define FSL_FEATURE_SOC_SPI_COUNT (4) 158 /* @brief SYSCON availability on the SoC. */ 159 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 160 /* @brief SYSCTL1 availability on the SoC. */ 161 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 162 /* @brief USART availability on the SoC. */ 163 #define FSL_FEATURE_SOC_USART_COUNT (7) 164 /* @brief UTICK availability on the SoC. */ 165 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 166 /* @brief WWDT availability on the SoC. */ 167 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 168 #endif 169 170 /* LPADC module features */ 171 172 /* @brief FIFO availability on the SoC. */ 173 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 174 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 175 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 176 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 177 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 178 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 179 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 180 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 181 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 182 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 183 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 184 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 185 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 186 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 187 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 188 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 189 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 190 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 191 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 192 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 193 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 194 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 195 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 196 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 197 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 198 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 199 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 200 /* @brief Has offset trim (register OFSTRIM). */ 201 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 202 /* @brief Has Trigger status register. */ 203 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 204 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 205 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 206 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 207 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 208 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 209 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 210 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 211 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 212 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 213 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 214 /* @brief Conversion averaged bitfiled width. */ 215 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 216 /* @brief Has internal temperature sensor. */ 217 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 218 /* @brief Temperature sensor parameter A (slope). */ 219 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (799.0f) 220 /* @brief Temperature sensor parameter B (offset). */ 221 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (280.0f) 222 /* @brief Temperature sensor parameter Alpha. */ 223 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (8.5f) 224 /* @brief Temperature sensor need calibration. */ 225 #define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1) 226 /* @brief the address of temperature sensor parameter A (slope) in Flash. */ 227 #define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U) 228 /* @brief the address of temperature sensor parameter B (offset) in Flash. */ 229 #define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU) 230 /* @brief the buffer size of temperature sensor. */ 231 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) 232 233 /* ANALOGCTRL module features */ 234 235 /* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ 236 #define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) 237 /* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ 238 #define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1) 239 /* @brief Has auxiliary bias(register AUX_BIAS). */ 240 #define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) 241 242 /* CAN module features */ 243 244 /* @brief Support CANFD or not */ 245 #define FSL_FEATURE_CAN_SUPPORT_CANFD (1) 246 247 /* CASPER module features */ 248 249 /* @brief Base address of the CASPER dedicated RAM */ 250 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) 251 /* @brief HW interleaving of the CASPER dedicated RAM */ 252 #define FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE (1) 253 254 /* CTIMER module features */ 255 256 /* @brief CTIMER has no capture channel. */ 257 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 258 /* @brief CTIMER has no capture 2 interrupt. */ 259 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 260 /* @brief CTIMER capture 3 interrupt. */ 261 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 262 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 263 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 264 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 265 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 266 /* @brief CTIMER Has register MSR */ 267 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 268 269 /* DMA module features */ 270 271 /* @brief Number of channels */ 272 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) 273 /* @brief Align size of DMA descriptor */ 274 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 275 /* @brief DMA head link descriptor table align size */ 276 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 277 278 /* FLEXCOMM module features */ 279 280 #if defined(CPU_LPC55S04JBD64) 281 /* @brief FLEXCOMM0 USART INDEX 0 */ 282 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 283 /* @brief FLEXCOMM0 SPI INDEX 0 */ 284 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 285 /* @brief FLEXCOMM0 I2C INDEX 0 */ 286 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 287 /* @brief FLEXCOMM0 I2S INDEX 0 */ 288 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 289 /* @brief FLEXCOMM1 USART INDEX 1 */ 290 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 291 /* @brief FLEXCOMM1 SPI INDEX 1 */ 292 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 293 /* @brief FLEXCOMM1 I2C INDEX 1 */ 294 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 295 /* @brief FLEXCOMM1 I2S INDEX 1 */ 296 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 297 /* @brief FLEXCOMM2 USART INDEX 2 */ 298 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 299 /* @brief FLEXCOMM2 I2C INDEX 2 */ 300 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 301 /* @brief FLEXCOMM2 I2S INDEX 2 */ 302 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 303 /* @brief FLEXCOMM3 USART INDEX 3 */ 304 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 305 /* @brief FLEXCOMM3 SPI INDEX 3 */ 306 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 307 /* @brief FLEXCOMM3 I2C INDEX 3 */ 308 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 309 /* @brief FLEXCOMM3 I2S INDEX 3 */ 310 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 311 /* @brief FLEXCOMM4 USART INDEX 4 */ 312 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 313 /* @brief FLEXCOMM4 SPI INDEX 4 */ 314 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 315 /* @brief FLEXCOMM4 I2C INDEX 4 */ 316 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 317 /* @brief FLEXCOMM4 I2S INDEX 4 */ 318 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 319 /* @brief FLEXCOMM5 USART INDEX 5 */ 320 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 321 /* @brief FLEXCOMM5 I2C INDEX 5 */ 322 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 323 /* @brief FLEXCOMM5 I2S INDEX 5 */ 324 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 325 /* @brief FLEXCOMM6 USART INDEX 6 */ 326 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 327 /* @brief FLEXCOMM6 SPI INDEX 6 */ 328 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 329 /* @brief FLEXCOMM6 I2C INDEX 6 */ 330 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 331 /* @brief FLEXCOMM6 I2S INDEX 6 */ 332 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 333 /* @brief FLEXCOMM7 USART INDEX 7 */ 334 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 335 /* @brief FLEXCOMM7 SPI INDEX 7 */ 336 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 337 /* @brief FLEXCOMM7 I2C INDEX 7 */ 338 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 339 /* @brief FLEXCOMM7 I2S INDEX 7 */ 340 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 341 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 342 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 343 /* @brief I2S has DMIC interconnection */ 344 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) 345 /* @brief I2S support dual channel transfer */ 346 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ 347 (((x) == FLEXCOMM0) ? (0) : \ 348 (((x) == FLEXCOMM1) ? (0) : \ 349 (((x) == FLEXCOMM2) ? (0) : \ 350 (((x) == FLEXCOMM3) ? (0) : \ 351 (((x) == FLEXCOMM4) ? (0) : \ 352 (((x) == FLEXCOMM5) ? (0) : \ 353 (((x) == FLEXCOMM6) ? (1) : \ 354 (((x) == FLEXCOMM7) ? (1) : \ 355 (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) 356 #elif defined(CPU_LPC55S04JHI48) 357 /* @brief FLEXCOMM0 USART INDEX 0 */ 358 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 359 /* @brief FLEXCOMM0 SPI INDEX 0 */ 360 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 361 /* @brief FLEXCOMM0 I2C INDEX 0 */ 362 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 363 /* @brief FLEXCOMM0 I2S INDEX 0 */ 364 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 365 /* @brief FLEXCOMM1 USART INDEX 1 */ 366 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 367 /* @brief FLEXCOMM1 I2C INDEX 1 */ 368 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 369 /* @brief FLEXCOMM2 USART INDEX 2 */ 370 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 371 /* @brief FLEXCOMM2 I2C INDEX 2 */ 372 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 373 /* @brief FLEXCOMM3 USART INDEX 3 */ 374 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 375 /* @brief FLEXCOMM3 SPI INDEX 3 */ 376 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 377 /* @brief FLEXCOMM3 I2C INDEX 3 */ 378 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 379 /* @brief FLEXCOMM3 I2S INDEX 3 */ 380 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 381 /* @brief FLEXCOMM4 USART INDEX 4 */ 382 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 383 /* @brief FLEXCOMM4 I2C INDEX 4 */ 384 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 385 /* @brief FLEXCOMM4 I2S INDEX 4 */ 386 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 387 /* @brief FLEXCOMM5 USART INDEX 5 */ 388 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 389 /* @brief FLEXCOMM5 I2C INDEX 5 */ 390 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 391 /* @brief FLEXCOMM6 USART INDEX 6 */ 392 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 393 /* @brief FLEXCOMM6 SPI INDEX 6 */ 394 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 395 /* @brief FLEXCOMM6 I2C INDEX 6 */ 396 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 397 /* @brief FLEXCOMM6 I2S INDEX 6 */ 398 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 399 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 400 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 401 /* @brief I2S has DMIC interconnection */ 402 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) 403 /* @brief I2S support dual channel transfer */ 404 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ 405 (((x) == FLEXCOMM0) ? (0) : \ 406 (((x) == FLEXCOMM1) ? (0) : \ 407 (((x) == FLEXCOMM2) ? (0) : \ 408 (((x) == FLEXCOMM3) ? (0) : \ 409 (((x) == FLEXCOMM4) ? (0) : \ 410 (((x) == FLEXCOMM5) ? (0) : \ 411 (((x) == FLEXCOMM6) ? (1) : \ 412 (((x) == FLEXCOMM8) ? (0) : (-1))))))))) 413 #endif /* defined(CPU_LPC55S04JBD64) */ 414 415 /* GINT module features */ 416 417 /* @brief The count of th port which are supported in GINT. */ 418 #define FSL_FEATURE_GINT_PORT_COUNT (2) 419 420 /* HASHCRYPT module features */ 421 422 /* @brief the address of alias offset */ 423 #define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) 424 /* @brief hashcrypt has reload feature */ 425 #define FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE (1) 426 427 /* I2S module features */ 428 429 /* @brief I2S6 and I2S7 support dual channel transfer. */ 430 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 431 /* @brief I2S has DMIC interconnection */ 432 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) 433 434 /* IOCON module features */ 435 436 /* @brief Func bit field width */ 437 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 438 439 /* MRT module features */ 440 441 /* @brief number of channels. */ 442 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 443 444 /* PINT module features */ 445 446 /* @brief Number of connected outputs */ 447 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 448 449 /* PLU module features */ 450 451 /* @brief Has WAKEINT_CTRL register. */ 452 #define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) 453 454 /* PMC module features */ 455 456 /* @brief UTICK does not support PD configure. */ 457 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 458 /* @brief WDT OSC does not support PD configure. */ 459 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 460 461 /* POWERLIB module features */ 462 463 /* @brief Powerlib API is different with other LPC series devices. */ 464 #define FSL_FEATURE_POWERLIB_EXTEND (1) 465 466 /* PUF module features */ 467 468 /* @brief Number of PUF key slots available on device. */ 469 #define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) 470 /* @brief the shift status value */ 471 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) 472 /* @brief PUF has dedicated SRAM control */ 473 #define FSL_FEATURE_PUF_HAS_SRAM_CTRL (1) 474 475 /* RTC module features */ 476 477 /* No feature definitions */ 478 479 /* SCT module features */ 480 481 /* @brief Number of events */ 482 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 483 /* @brief Number of states */ 484 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 485 /* @brief Number of match capture */ 486 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 487 /* @brief Number of outputs */ 488 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 489 490 /* SECPINT module features */ 491 492 /* @brief Number of connected outputs */ 493 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) 494 495 /* SPI module features */ 496 497 /* @brief SSEL pin count. */ 498 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 499 500 /* SYSCON module features */ 501 502 /* @brief Flash page size in bytes */ 503 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) 504 /* @brief Flash sector size in bytes */ 505 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) 506 /* @brief Flash size in bytes */ 507 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (131072) 508 /* @brief Has Power Down mode */ 509 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) 510 /* @brief CCM_ANALOG availability on the SoC. */ 511 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 512 /* @brief Starter register discontinuous. */ 513 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 514 515 /* SYSCTL1 module features */ 516 517 /* @brief SYSCTRL has Code Gray feature. */ 518 #define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) 519 520 /* WWDT module features */ 521 522 /* @brief Has no RESET register. */ 523 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 524 /* @brief WWDT does not support oscillator lock. */ 525 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) 526 527 #endif /* _LPC55S04_FEATURES_H_ */ 528 529
