1 /* 2 ** ################################################################### 3 ** Version: rev. 1.1, 2021-08-04 4 ** Build: b240322 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2021-04-12) 18 ** Initial version based on RM DraftF 19 ** - rev. 1.1 (2021-08-04) 20 ** Initial version based on RM DraftG 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _LPC5534_FEATURES_H_ 26 #define _LPC5534_FEATURES_H_ 27 28 /* SOC module features */ 29 30 #if defined(CPU_LPC5534JBD100) 31 /* @brief AOI availability on the SoC. */ 32 #define FSL_FEATURE_SOC_AOI_COUNT (2) 33 /* @brief CACHE64_CTRL availability on the SoC. */ 34 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) 35 /* @brief CACHE64_POLSEL availability on the SoC. */ 36 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) 37 /* @brief LPC_CAN availability on the SoC. */ 38 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) 39 /* @brief CDOG availability on the SoC. */ 40 #define FSL_FEATURE_SOC_CDOG_COUNT (1) 41 /* @brief CRC availability on the SoC. */ 42 #define FSL_FEATURE_SOC_CRC_COUNT (1) 43 /* @brief CTIMER availability on the SoC. */ 44 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 45 /* @brief DMA availability on the SoC. */ 46 #define FSL_FEATURE_SOC_DMA_COUNT (2) 47 /* @brief DMIC availability on the SoC. */ 48 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 49 /* @brief ENC availability on the SoC. */ 50 #define FSL_FEATURE_SOC_ENC_COUNT (2) 51 /* @brief FLASH availability on the SoC. */ 52 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 53 /* @brief FLEXCOMM availability on the SoC. */ 54 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 55 /* @brief FLEXSPI availability on the SoC. */ 56 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 57 /* @brief FREQME availability on the SoC. */ 58 #define FSL_FEATURE_SOC_FREQME_COUNT (1) 59 /* @brief GINT availability on the SoC. */ 60 #define FSL_FEATURE_SOC_GINT_COUNT (2) 61 /* @brief GPIO availability on the SoC. */ 62 #define FSL_FEATURE_SOC_GPIO_COUNT (2) 63 /* @brief I2C availability on the SoC. */ 64 #define FSL_FEATURE_SOC_I2C_COUNT (8) 65 /* @brief I3C availability on the SoC. */ 66 #define FSL_FEATURE_SOC_I3C_COUNT (1) 67 /* @brief I2S availability on the SoC. */ 68 #define FSL_FEATURE_SOC_I2S_COUNT (8) 69 /* @brief INPUTMUX availability on the SoC. */ 70 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 71 /* @brief IOCON availability on the SoC. */ 72 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 73 /* @brief LPADC availability on the SoC. */ 74 #define FSL_FEATURE_SOC_LPADC_COUNT (2) 75 /* @brief LPCMP availability on the SoC. */ 76 #define FSL_FEATURE_SOC_LPCMP_COUNT (3) 77 /* @brief LPDAC availability on the SoC. */ 78 #define FSL_FEATURE_SOC_LPDAC_COUNT (3) 79 /* @brief MRT availability on the SoC. */ 80 #define FSL_FEATURE_SOC_MRT_COUNT (1) 81 /* @brief OPAMP availability on the SoC. */ 82 #define FSL_FEATURE_SOC_OPAMP_COUNT (3) 83 /* @brief OSTIMER availability on the SoC. */ 84 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 85 /* @brief PINT availability on the SoC. */ 86 #define FSL_FEATURE_SOC_PINT_COUNT (2) 87 /* @brief PMC availability on the SoC. */ 88 #define FSL_FEATURE_SOC_PMC_COUNT (1) 89 /* @brief POWERQUAD availability on the SoC. */ 90 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 91 /* @brief PWM availability on the SoC. */ 92 #define FSL_FEATURE_SOC_PWM_COUNT (2) 93 /* @brief RTC availability on the SoC. */ 94 #define FSL_FEATURE_SOC_RTC_COUNT (1) 95 /* @brief SCT availability on the SoC. */ 96 #define FSL_FEATURE_SOC_SCT_COUNT (1) 97 /* @brief SPI availability on the SoC. */ 98 #define FSL_FEATURE_SOC_SPI_COUNT (9) 99 /* @brief SYSCON availability on the SoC. */ 100 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 101 /* @brief USART availability on the SoC. */ 102 #define FSL_FEATURE_SOC_USART_COUNT (8) 103 /* @brief USB availability on the SoC. */ 104 #define FSL_FEATURE_SOC_USB_COUNT (1) 105 /* @brief USBFSH availability on the SoC. */ 106 #define FSL_FEATURE_SOC_USBFSH_COUNT (1) 107 /* @brief UTICK availability on the SoC. */ 108 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 109 /* @brief VREF availability on the SoC. */ 110 #define FSL_FEATURE_SOC_VREF_COUNT (1) 111 /* @brief WWDT availability on the SoC. */ 112 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 113 #elif defined(CPU_LPC5534JBD64) || defined(CPU_LPC5534JHI48) 114 /* @brief AOI availability on the SoC. */ 115 #define FSL_FEATURE_SOC_AOI_COUNT (2) 116 /* @brief CACHE64_CTRL availability on the SoC. */ 117 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) 118 /* @brief CACHE64_POLSEL availability on the SoC. */ 119 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) 120 /* @brief LPC_CAN availability on the SoC. */ 121 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) 122 /* @brief CDOG availability on the SoC. */ 123 #define FSL_FEATURE_SOC_CDOG_COUNT (1) 124 /* @brief CRC availability on the SoC. */ 125 #define FSL_FEATURE_SOC_CRC_COUNT (1) 126 /* @brief CTIMER availability on the SoC. */ 127 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 128 /* @brief DMA availability on the SoC. */ 129 #define FSL_FEATURE_SOC_DMA_COUNT (2) 130 /* @brief DMIC availability on the SoC. */ 131 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 132 /* @brief ENC availability on the SoC. */ 133 #define FSL_FEATURE_SOC_ENC_COUNT (2) 134 /* @brief FLASH availability on the SoC. */ 135 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 136 /* @brief FLEXCOMM availability on the SoC. */ 137 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 138 /* @brief FLEXSPI availability on the SoC. */ 139 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 140 /* @brief FREQME availability on the SoC. */ 141 #define FSL_FEATURE_SOC_FREQME_COUNT (1) 142 /* @brief GINT availability on the SoC. */ 143 #define FSL_FEATURE_SOC_GINT_COUNT (2) 144 /* @brief GPIO availability on the SoC. */ 145 #define FSL_FEATURE_SOC_GPIO_COUNT (2) 146 /* @brief I2C availability on the SoC. */ 147 #define FSL_FEATURE_SOC_I2C_COUNT (8) 148 /* @brief I3C availability on the SoC. */ 149 #define FSL_FEATURE_SOC_I3C_COUNT (1) 150 /* @brief I2S availability on the SoC. */ 151 #define FSL_FEATURE_SOC_I2S_COUNT (8) 152 /* @brief INPUTMUX availability on the SoC. */ 153 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 154 /* @brief IOCON availability on the SoC. */ 155 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 156 /* @brief LPADC availability on the SoC. */ 157 #define FSL_FEATURE_SOC_LPADC_COUNT (2) 158 /* @brief LPCMP availability on the SoC. */ 159 #define FSL_FEATURE_SOC_LPCMP_COUNT (3) 160 /* @brief LPDAC availability on the SoC. */ 161 #define FSL_FEATURE_SOC_LPDAC_COUNT (3) 162 /* @brief MRT availability on the SoC. */ 163 #define FSL_FEATURE_SOC_MRT_COUNT (1) 164 /* @brief OPAMP availability on the SoC. */ 165 #define FSL_FEATURE_SOC_OPAMP_COUNT (3) 166 /* @brief OSTIMER availability on the SoC. */ 167 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 168 /* @brief PINT availability on the SoC. */ 169 #define FSL_FEATURE_SOC_PINT_COUNT (2) 170 /* @brief PMC availability on the SoC. */ 171 #define FSL_FEATURE_SOC_PMC_COUNT (1) 172 /* @brief POWERQUAD availability on the SoC. */ 173 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 174 /* @brief PWM availability on the SoC. */ 175 #define FSL_FEATURE_SOC_PWM_COUNT (2) 176 /* @brief RTC availability on the SoC. */ 177 #define FSL_FEATURE_SOC_RTC_COUNT (1) 178 /* @brief SCT availability on the SoC. */ 179 #define FSL_FEATURE_SOC_SCT_COUNT (1) 180 /* @brief SPI availability on the SoC. */ 181 #define FSL_FEATURE_SOC_SPI_COUNT (9) 182 /* @brief SYSCON availability on the SoC. */ 183 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 184 /* @brief USART availability on the SoC. */ 185 #define FSL_FEATURE_SOC_USART_COUNT (8) 186 /* @brief UTICK availability on the SoC. */ 187 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 188 /* @brief VREF availability on the SoC. */ 189 #define FSL_FEATURE_SOC_VREF_COUNT (1) 190 /* @brief WWDT availability on the SoC. */ 191 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 192 #endif 193 194 /* LPADC module features */ 195 196 /* @brief FIFO availability on the SoC. */ 197 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 198 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 199 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 200 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 201 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 202 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 203 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 204 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 205 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 206 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 207 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 208 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 209 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 210 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 211 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 212 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 213 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 214 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 215 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 216 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 217 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 218 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 219 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 220 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 221 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 222 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 223 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 224 /* @brief Has offset trim (register OFSTRIM). */ 225 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 226 /* @brief OFSTRIM availability on the SoC. */ 227 #define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) 228 /* @brief Has Trigger status register. */ 229 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 230 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 231 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 232 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 233 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 234 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 235 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) 236 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 237 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) 238 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 239 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 240 /* @brief Conversion averaged bitfiled width. */ 241 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 242 /* @brief Has B side channels. */ 243 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 244 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 245 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) 246 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 247 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) 248 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 249 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) 250 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 251 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 252 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 253 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) 254 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 255 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) 256 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 257 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) 258 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 259 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) 260 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 261 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) 262 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 263 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) 264 /* @brief Has internal temperature sensor. */ 265 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 266 /* @brief Temperature sensor parameter A (slope). */ 267 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (768.0f) 268 /* @brief Temperature sensor parameter B (offset). */ 269 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (292.7f) 270 /* @brief Temperature sensor parameter Alpha. */ 271 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.7f) 272 /* @brief Temperature sensor need calibration. */ 273 #define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1) 274 /* @brief the address of temperature sensor parameter A (slope) in Flash. */ 275 #define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U) 276 /* @brief the address of temperature sensor parameter B (offset) in Flash. */ 277 #define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU) 278 /* @brief the buffer size of temperature sensor. */ 279 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) 280 281 /* ANACTRL module features */ 282 283 /* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ 284 #define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) 285 /* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ 286 #define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1) 287 /* @brief Has auxiliary bias(register AUX_BIAS). */ 288 #define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) 289 /* @brief Has FREQ_ME_CTRL reigster. */ 290 #define FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL (1) 291 292 /* AOI module features */ 293 294 /* @brief Maximum value of input mux. */ 295 #define FSL_FEATURE_AOI_MODULE_INPUTS (4) 296 /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ 297 #define FSL_FEATURE_AOI_EVENT_COUNT (4) 298 299 /* CACHE64_CTRL module features */ 300 301 /* @brief Cache Line size in byte. */ 302 #define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) 303 304 /* CACHE64_POLSEL module features */ 305 306 /* No feature definitions */ 307 308 /* CAN module features */ 309 310 /* @brief Support CANFD or not */ 311 #define FSL_FEATURE_CAN_SUPPORT_CANFD (1) 312 313 /* CDOG module features */ 314 315 /* No feature definitions */ 316 317 /* CRC module features */ 318 319 /* @brief Has data register with name CRC */ 320 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 321 322 /* CTIMER module features */ 323 324 /* @brief CTIMER has no capture channel. */ 325 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 326 /* @brief CTIMER has no capture 2 interrupt. */ 327 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 328 /* @brief CTIMER capture 3 interrupt. */ 329 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 330 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 331 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 332 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 333 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 334 /* @brief CTIMER Has register MSR */ 335 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 336 337 /* LPDAC module features */ 338 339 /* @brief FIFO size. */ 340 #define FSL_FEATURE_LPDAC_FIFO_SIZE (16) 341 /* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ 342 #define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) 343 /* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ 344 #define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) 345 /* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ 346 #define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) 347 /* @brief VREF source number. */ 348 #define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) 349 /* @brief Has internal reference current options. */ 350 #define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) 351 /* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ 352 #define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) 353 354 /* DMA module features */ 355 356 /* @brief Number of channels */ 357 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) \ 358 (((x) == DMA0) ? (52) : \ 359 (((x) == DMA1) ? (16) : (-1))) 360 /* @brief Max channels */ 361 #define FSL_FEATURE_DMA_MAX_CHANNELS (52) 362 /* @brief All channels */ 363 #define FSL_FEATURE_DMA_ALL_CHANNELS (68U) 364 /* @brief Align size of DMA0 descriptor */ 365 #define FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE (1024) 366 /* @brief Align size of DMA1 descriptor */ 367 #define FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE (256) 368 /* @brief Align size of DMA descriptor */ 369 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(x) \ 370 (((x) == DMA0) ? (1024) : \ 371 (((x) == DMA1) ? (256) : (-1))) 372 /* @brief DMA head link descriptor table align size */ 373 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 374 375 /* DMIC module features */ 376 377 /* @brief Number of channels */ 378 #define FSL_FEATURE_DMIC_CHANNEL_NUM (2) 379 /* @brief DMIC channel support stereo data */ 380 #define FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6 (0) 381 /* @brief DMIC does not support bypass channel clock */ 382 #define FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS (1) 383 /* @brief DMIC channel FIFO register support sign extended */ 384 #define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1) 385 /* @brief DMIC has no IOCFG register */ 386 #define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1) 387 /* @brief DMIC has decimator reset function */ 388 #define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1) 389 /* @brief DMIC has global channel synchronization function */ 390 #define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (1) 391 392 /* ENC module features */ 393 394 /* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ 395 #define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0) 396 /* @brief Has register CTRL3. */ 397 #define FSL_FEATURE_ENC_HAS_CTRL3 (1) 398 /* @brief Has register LASTEDGE or LASTEDGEH. */ 399 #define FSL_FEATURE_ENC_HAS_LASTEDGE (1) 400 /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ 401 #define FSL_FEATURE_ENC_HAS_POSDPER (1) 402 /* @brief Has bitfiled FILT[FILT_PRSC]. */ 403 #define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) 404 405 /* FLEXCOMM module features */ 406 407 /* @brief FLEXCOMM0 USART INDEX 0 */ 408 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 409 /* @brief FLEXCOMM0 SPI INDEX 0 */ 410 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 411 /* @brief FLEXCOMM0 I2C INDEX 0 */ 412 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 413 /* @brief FLEXCOMM0 I2S INDEX 0 */ 414 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 415 /* @brief FLEXCOMM1 USART INDEX 1 */ 416 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 417 /* @brief FLEXCOMM1 SPI INDEX 1 */ 418 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 419 /* @brief FLEXCOMM1 I2C INDEX 1 */ 420 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 421 /* @brief FLEXCOMM1 I2S INDEX 1 */ 422 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 423 /* @brief FLEXCOMM2 USART INDEX 2 */ 424 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 425 /* @brief FLEXCOMM2 SPI INDEX 2 */ 426 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 427 /* @brief FLEXCOMM2 I2C INDEX 2 */ 428 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 429 /* @brief FLEXCOMM2 I2S INDEX 2 */ 430 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 431 /* @brief FLEXCOMM3 USART INDEX 3 */ 432 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 433 /* @brief FLEXCOMM3 SPI INDEX 3 */ 434 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 435 /* @brief FLEXCOMM3 I2C INDEX 3 */ 436 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 437 /* @brief FLEXCOMM3 I2S INDEX 3 */ 438 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 439 /* @brief FLEXCOMM4 USART INDEX 4 */ 440 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 441 /* @brief FLEXCOMM4 SPI INDEX 4 */ 442 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 443 /* @brief FLEXCOMM4 I2C INDEX 4 */ 444 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 445 /* @brief FLEXCOMM4 I2S INDEX 4 */ 446 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 447 /* @brief FLEXCOMM5 USART INDEX 5 */ 448 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 449 /* @brief FLEXCOMM5 SPI INDEX 5 */ 450 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 451 /* @brief FLEXCOMM5 I2C INDEX 5 */ 452 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 453 /* @brief FLEXCOMM5 I2S INDEX 5 */ 454 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 455 /* @brief FLEXCOMM6 USART INDEX 6 */ 456 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 457 /* @brief FLEXCOMM6 SPI INDEX 6 */ 458 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 459 /* @brief FLEXCOMM6 I2C INDEX 6 */ 460 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 461 /* @brief FLEXCOMM6 I2S INDEX 6 */ 462 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 463 /* @brief FLEXCOMM7 USART INDEX 7 */ 464 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 465 /* @brief FLEXCOMM7 SPI INDEX 7 */ 466 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 467 /* @brief FLEXCOMM7 I2C INDEX 7 */ 468 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 469 /* @brief FLEXCOMM7 I2S INDEX 7 */ 470 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 471 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 472 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 473 /* @brief I2S has DMIC interconnection */ 474 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ 475 (((x) == FLEXCOMM0) ? (0) : \ 476 (((x) == FLEXCOMM1) ? (0) : \ 477 (((x) == FLEXCOMM2) ? (0) : \ 478 (((x) == FLEXCOMM3) ? (0) : \ 479 (((x) == FLEXCOMM4) ? (0) : \ 480 (((x) == FLEXCOMM5) ? (0) : \ 481 (((x) == FLEXCOMM6) ? (0) : \ 482 (((x) == FLEXCOMM7) ? (1) : \ 483 (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) 484 /* @brief I2S support dual channel transfer */ 485 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ 486 (((x) == FLEXCOMM0) ? (0) : \ 487 (((x) == FLEXCOMM1) ? (0) : \ 488 (((x) == FLEXCOMM2) ? (0) : \ 489 (((x) == FLEXCOMM3) ? (0) : \ 490 (((x) == FLEXCOMM4) ? (0) : \ 491 (((x) == FLEXCOMM5) ? (0) : \ 492 (((x) == FLEXCOMM6) ? (1) : \ 493 (((x) == FLEXCOMM7) ? (1) : \ 494 (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) 495 496 /* FLEXSPI module features */ 497 498 /* @brief FlexSPI AHB buffer count */ 499 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) 500 /* @brief FlexSPI has no MCR0 ARDFEN bit */ 501 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) 502 /* @brief FlexSPI has no MCR0 ATDFEN bit */ 503 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) 504 /* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ 505 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) 506 /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ 507 #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) 508 /* @brief FlexSPI has no IPCR1 IPAREN bit */ 509 #define FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN (1) 510 /* @brief FlexSPI has no AHBCR APAREN bit */ 511 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN (1) 512 /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ 513 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) 514 /* @brief FlexSPI has no FLSHCR4 WMENB bit */ 515 #define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) 516 /* @brief FlexSPI has no STS2 BSLVLOCK bit */ 517 #define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (1) 518 /* @brief FlexSPI has no STS2 BREFLOCK bit */ 519 #define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (1) 520 /* @brief FlexSPI supports Port A only, do not support Port B. */ 521 #define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (1) 522 /* @brief FlexSPI LUTKEY is read only. */ 523 #define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (1) 524 /* @brief There is AHBBUSERROREN bit in INTEN register. */ 525 #define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) 526 /* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ 527 #define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) 528 /* @brief FLEXSPI has no IP parallel mode. */ 529 #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) 530 /* @brief FLEXSPI has no AHB parallel mode. */ 531 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) 532 /* @brief FLEXSPI support address shift. */ 533 #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) 534 /* @brief FlexSPI AHB RX buffer size (byte) */ 535 #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) 536 537 /* GINT module features */ 538 539 /* @brief The count of th port which are supported in GINT. */ 540 #define FSL_FEATURE_GINT_PORT_COUNT (2) 541 542 /* I2S module features */ 543 544 /* @brief I2S support dual channel transfer. */ 545 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 546 /* @brief I2S has DMIC interconnection. */ 547 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) 548 549 /* I3C module features */ 550 551 /* @brief Has TERM bitfile in MERRWARN register. */ 552 #define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) 553 /* @brief SOC has no reset driver. */ 554 #define FSL_FEATURE_I3C_HAS_NO_RESET (0) 555 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ 556 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) 557 /* @brief Register SCONFIG do not have IDRAND bitfield. */ 558 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) 559 /* @brief Register SCONFIG has HDROK bitfield. */ 560 #define FSL_FEATURE_I3C_HAS_HDROK (0) 561 /* @brief SOC doesn't support slave IBI/MR/HJ. */ 562 #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) 563 564 /* INPUTMUX module features */ 565 566 /* @brief Inputmux has DMA Request Enable */ 567 #define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) 568 /* @brief Inputmux has channel mux control */ 569 #define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) 570 571 /* IOCON module features */ 572 573 /* @brief Func bit field width */ 574 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 575 576 /* MRT module features */ 577 578 /* @brief number of channels. */ 579 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 580 581 /* PINT module features */ 582 583 /* @brief Number of connected outputs */ 584 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 585 /* @brief Number of connected outputs */ 586 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) 587 588 /* PMC module features */ 589 590 /* @brief UTICK does not support PD configure. */ 591 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 592 /* @brief WDT OSC does not support PD configure. */ 593 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 594 595 /* POWERQUAD module features */ 596 597 /* @brief Sine and Cossine fix errata */ 598 #define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) 599 600 /* PWM module features */ 601 602 /* @brief If (e)FlexPWM has module A channels (outputs). */ 603 #define FSL_FEATURE_PWM_HAS_CHANNELA (1) 604 /* @brief If (e)FlexPWM has module B channels (outputs). */ 605 #define FSL_FEATURE_PWM_HAS_CHANNELB (1) 606 /* @brief If (e)FlexPWM has module X channels (outputs). */ 607 #define FSL_FEATURE_PWM_HAS_CHANNELX (1) 608 /* @brief If (e)FlexPWM has fractional feature. */ 609 #define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) 610 /* @brief If (e)FlexPWM has mux trigger source select bit field. */ 611 #define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) 612 /* @brief Number of submodules in each (e)FlexPWM module. */ 613 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) 614 /* @brief Number of fault channel in each (e)FlexPWM module. */ 615 #define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) 616 /* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ 617 #define FSL_FEATURE_PWM_HAS_NO_WAITEN (0) 618 /* @brief If (e)FlexPWM has phase delay feature. */ 619 #define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) 620 /* @brief If (e)FlexPWM has input filter capture feature. */ 621 #define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) 622 /* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ 623 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) 624 /* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ 625 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) 626 /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ 627 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) 628 629 /* RTC module features */ 630 631 /* @brief Has Tamper Direction Register support. */ 632 #define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) 633 /* @brief Has Tamper Queue Status and Control Register support. */ 634 #define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (1) 635 /* @brief Has RTC subsystem. */ 636 #define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) 637 /* @brief Has Reset in system level. */ 638 #define FSL_FEATURE_RTC_HAS_RESET (1) 639 /* @brief Has RTC Tamper 23 Filter Configuration Register support. */ 640 #define FSL_FEATURE_RTC_HAS_FILTER23_CFG (1) 641 /* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ 642 #define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) 643 /* @brief Has CLK_SEL bitfile in CTRL register. */ 644 #define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (0) 645 /* @brief Has CLKO_DIS bitfile in CTRL register. */ 646 #define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (0) 647 /* @brief Has No Tamper in RTC. */ 648 #define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (0) 649 /* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ 650 #define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (0) 651 /* @brief Has RST_SRC bitfile in STATUS register. */ 652 #define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (0) 653 /* @brief Has GP_DATA_REG register. */ 654 #define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (0) 655 /* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ 656 #define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (0) 657 658 /* SCT module features */ 659 660 /* @brief Number of events */ 661 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 662 /* @brief Number of states */ 663 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 664 /* @brief Number of match capture */ 665 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 666 /* @brief Number of outputs */ 667 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 668 669 /* SPI module features */ 670 671 /* @brief SSEL pin count. */ 672 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 673 674 /* SYSCON module features */ 675 676 /* @brief Flash page size in bytes */ 677 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) 678 /* @brief Flash sector size in bytes */ 679 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) 680 /* @brief Flash size in bytes */ 681 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (131072) 682 683 /* SYSCTL module features */ 684 685 /* @brief SYSCTRL has Code Gray feature. */ 686 #define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) 687 688 /* USART module features */ 689 690 /* @brief Has FIFO Receive Timeout Configuration (register FIFORXTIMEOUTCFG). */ 691 #define FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG (1) 692 693 /* USB module features */ 694 695 #if defined(CPU_LPC5534JBD100) 696 /* @brief USB version */ 697 #define FSL_FEATURE_USB_VERSION (200) 698 /* @brief Number of the endpoint in USB FS */ 699 #define FSL_FEATURE_USB_EP_NUM (5) 700 #endif /* defined(CPU_LPC5534JBD100) */ 701 702 /* USBFSH module features */ 703 704 #if defined(CPU_LPC5534JBD100) 705 /* @brief USBFSH version */ 706 #define FSL_FEATURE_USBFSH_VERSION (200) 707 #endif /* defined(CPU_LPC5534JBD100) */ 708 709 /* VREF module features */ 710 711 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 712 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (0) 713 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 714 #define FSL_FEATURE_VREF_HAS_COMPENSATION (0) 715 /* @brief If high/low buffer mode supported */ 716 #define FSL_FEATURE_VREF_MODE_LV_TYPE (0) 717 /* @brief Module has also low reference (registers VREFL/VREFH) */ 718 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 719 /* @brief Has VREF_TRM4. */ 720 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 721 722 /* WWDT module features */ 723 724 /* @brief Has no RESET register. */ 725 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 726 727 #endif /* _LPC5534_FEATURES_H_ */ 728 729
