1 /* 2 ** ################################################################### 3 ** Version: rev. 1.1, 2019-05-16 4 ** Build: b231017 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2023 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2018-08-22) 18 ** Initial version based on v0.2UM 19 ** - rev. 1.1 (2019-05-16) 20 ** Initial A1 version based on v1.3UM 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _LPC5528_FEATURES_H_ 26 #define _LPC5528_FEATURES_H_ 27 28 /* SOC module features */ 29 30 /* @brief CRC availability on the SoC. */ 31 #define FSL_FEATURE_SOC_CRC_COUNT (1) 32 /* @brief CTIMER availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 34 /* @brief DMA availability on the SoC. */ 35 #define FSL_FEATURE_SOC_DMA_COUNT (2) 36 /* @brief FLASH availability on the SoC. */ 37 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 38 /* @brief FLEXCOMM availability on the SoC. */ 39 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 40 /* @brief GINT availability on the SoC. */ 41 #define FSL_FEATURE_SOC_GINT_COUNT (2) 42 /* @brief GPIO availability on the SoC. */ 43 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 44 /* @brief SECGPIO availability on the SoC. */ 45 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 46 /* @brief I2C availability on the SoC. */ 47 #define FSL_FEATURE_SOC_I2C_COUNT (8) 48 /* @brief I2S availability on the SoC. */ 49 #define FSL_FEATURE_SOC_I2S_COUNT (8) 50 /* @brief INPUTMUX availability on the SoC. */ 51 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 52 /* @brief IOCON availability on the SoC. */ 53 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 54 /* @brief LPADC availability on the SoC. */ 55 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 56 /* @brief MPU availability on the SoC. */ 57 #define FSL_FEATURE_SOC_MPU_COUNT (1) 58 /* @brief MRT availability on the SoC. */ 59 #define FSL_FEATURE_SOC_MRT_COUNT (1) 60 /* @brief OSTIMER availability on the SoC. */ 61 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 62 /* @brief PINT availability on the SoC. */ 63 #define FSL_FEATURE_SOC_PINT_COUNT (1) 64 /* @brief SECPINT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_SECPINT_COUNT (1) 66 /* @brief PMC availability on the SoC. */ 67 #define FSL_FEATURE_SOC_PMC_COUNT (1) 68 /* @brief LPC_RNG1 availability on the SoC. */ 69 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) 70 /* @brief RTC availability on the SoC. */ 71 #define FSL_FEATURE_SOC_RTC_COUNT (1) 72 /* @brief SCT availability on the SoC. */ 73 #define FSL_FEATURE_SOC_SCT_COUNT (1) 74 /* @brief SDIF availability on the SoC. */ 75 #define FSL_FEATURE_SOC_SDIF_COUNT (1) 76 /* @brief SPI availability on the SoC. */ 77 #define FSL_FEATURE_SOC_SPI_COUNT (9) 78 /* @brief SYSCON availability on the SoC. */ 79 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 80 /* @brief SYSCTL1 availability on the SoC. */ 81 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 82 /* @brief USART availability on the SoC. */ 83 #define FSL_FEATURE_SOC_USART_COUNT (8) 84 /* @brief USB availability on the SoC. */ 85 #define FSL_FEATURE_SOC_USB_COUNT (1) 86 /* @brief USBFSH availability on the SoC. */ 87 #define FSL_FEATURE_SOC_USBFSH_COUNT (1) 88 /* @brief USBHSD availability on the SoC. */ 89 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 90 /* @brief USBHSH availability on the SoC. */ 91 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 92 /* @brief USBPHY availability on the SoC. */ 93 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 94 /* @brief UTICK availability on the SoC. */ 95 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 96 /* @brief WWDT availability on the SoC. */ 97 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 98 99 /* LPADC module features */ 100 101 /* @brief FIFO availability on the SoC. */ 102 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 103 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 104 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 105 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 106 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 107 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 108 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 109 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 110 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 111 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 112 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 113 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 114 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 115 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 116 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 117 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 118 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 119 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 120 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 121 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 122 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 123 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 124 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 125 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 126 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 127 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 128 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 129 /* @brief Has offset trim (register OFSTRIM). */ 130 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 131 /* @brief OFSTRIM availability on the SoC. */ 132 #define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) 133 /* @brief Has Trigger status register. */ 134 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 135 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 136 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 137 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 138 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 139 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 140 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 141 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 142 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 143 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 144 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 145 /* @brief Conversion averaged bitfiled width. */ 146 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 147 /* @brief Has B side channels. */ 148 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 149 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 150 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) 151 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 152 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) 153 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 154 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) 155 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 156 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 157 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 158 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) 159 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 160 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) 161 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 162 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) 163 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 164 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) 165 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 166 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) 167 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 168 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) 169 /* @brief Has internal temperature sensor. */ 170 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 171 /* @brief Chip Rev 0A Temperature sensor parameter A (slope). */ 172 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_0A (770.0f) 173 /* @brief Chip Rev 0A Temperature sensor parameter B (offset). */ 174 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_0A (289.4f) 175 /* @brief Chip Rev 0A Temperature sensor parameter Alpha. */ 176 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_0A (9.5f) 177 /* @brief Chip Rev 1B Temperature sensor parameter A (slope). */ 178 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_1B (804.0f) 179 /* @brief Chip Rev 1B Temperature sensor parameter B (offset). */ 180 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_1B (280.0f) 181 /* @brief Chip Rev 1B Temperature sensor parameter Alpha. */ 182 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_1B (8.5f) 183 /* @brief the buffer size of temperature sensor. */ 184 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) 185 186 /* ANALOGCTRL module features */ 187 188 /* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ 189 #define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) 190 /* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ 191 #define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) 192 /* @brief Has auxiliary bias(register AUX_BIAS). */ 193 #define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) 194 195 /* CTIMER module features */ 196 197 /* @brief CTIMER has no capture channel. */ 198 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 199 /* @brief CTIMER has no capture 2 interrupt. */ 200 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 201 /* @brief CTIMER capture 3 interrupt. */ 202 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 203 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 204 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 205 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 206 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 207 /* @brief CTIMER Has register MSR */ 208 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 209 210 /* DMA module features */ 211 212 /* @brief Number of channels */ 213 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) 214 /* @brief Align size of DMA descriptor */ 215 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 216 /* @brief DMA head link descriptor table align size */ 217 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 218 219 /* FLEXCOMM module features */ 220 221 /* @brief FLEXCOMM0 USART INDEX 0 */ 222 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 223 /* @brief FLEXCOMM0 SPI INDEX 0 */ 224 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 225 /* @brief FLEXCOMM0 I2C INDEX 0 */ 226 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 227 /* @brief FLEXCOMM0 I2S INDEX 0 */ 228 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 229 /* @brief FLEXCOMM1 USART INDEX 1 */ 230 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 231 /* @brief FLEXCOMM1 SPI INDEX 1 */ 232 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 233 /* @brief FLEXCOMM1 I2C INDEX 1 */ 234 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 235 /* @brief FLEXCOMM1 I2S INDEX 1 */ 236 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 237 /* @brief FLEXCOMM2 USART INDEX 2 */ 238 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 239 /* @brief FLEXCOMM2 SPI INDEX 2 */ 240 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 241 /* @brief FLEXCOMM2 I2C INDEX 2 */ 242 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 243 /* @brief FLEXCOMM2 I2S INDEX 2 */ 244 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 245 /* @brief FLEXCOMM3 USART INDEX 3 */ 246 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 247 /* @brief FLEXCOMM3 SPI INDEX 3 */ 248 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 249 /* @brief FLEXCOMM3 I2C INDEX 3 */ 250 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 251 /* @brief FLEXCOMM3 I2S INDEX 3 */ 252 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 253 /* @brief FLEXCOMM4 USART INDEX 4 */ 254 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 255 /* @brief FLEXCOMM4 SPI INDEX 4 */ 256 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 257 /* @brief FLEXCOMM4 I2C INDEX 4 */ 258 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 259 /* @brief FLEXCOMM4 I2S INDEX 4 */ 260 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 261 /* @brief FLEXCOMM5 USART INDEX 5 */ 262 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 263 /* @brief FLEXCOMM5 SPI INDEX 5 */ 264 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 265 /* @brief FLEXCOMM5 I2C INDEX 5 */ 266 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 267 /* @brief FLEXCOMM5 I2S INDEX 5 */ 268 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 269 /* @brief FLEXCOMM6 USART INDEX 6 */ 270 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 271 /* @brief FLEXCOMM6 SPI INDEX 6 */ 272 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 273 /* @brief FLEXCOMM6 I2C INDEX 6 */ 274 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 275 /* @brief FLEXCOMM6 I2S INDEX 6 */ 276 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 277 /* @brief FLEXCOMM7 USART INDEX 7 */ 278 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 279 /* @brief FLEXCOMM7 SPI INDEX 7 */ 280 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 281 /* @brief FLEXCOMM7 I2C INDEX 7 */ 282 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 283 /* @brief FLEXCOMM7 I2S INDEX 7 */ 284 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 285 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 286 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 287 /* @brief I2S has DMIC interconnection */ 288 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) 289 290 /* GINT module features */ 291 292 /* @brief The count of th port which are supported in GINT. */ 293 #define FSL_FEATURE_GINT_PORT_COUNT (2) 294 295 /* I2S module features */ 296 297 /* @brief I2S support dual channel transfer. */ 298 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) 299 /* @brief I2S has DMIC interconnection */ 300 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) 301 302 /* INPUTMUX module features */ 303 304 /* @brief Inputmux has DMA Request Enable */ 305 #define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (0) 306 /* @brief Inputmux has channel mux control */ 307 #define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) 308 309 /* IOCON module features */ 310 311 /* @brief Func bit field width */ 312 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 313 314 /* MRT module features */ 315 316 /* @brief number of channels. */ 317 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 318 319 /* PINT module features */ 320 321 /* @brief Number of connected outputs */ 322 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 323 324 /* PLU module features */ 325 326 /* @brief Has WAKEINT_CTRL register. */ 327 #define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) 328 329 /* PMC module features */ 330 331 /* @brief UTICK does not support PD configure. */ 332 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 333 /* @brief WDT OSC does not support PD configure. */ 334 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 335 336 /* POWERLIB module features */ 337 338 /* @brief Powerlib API is different with other LPC series devices. */ 339 #define FSL_FEATURE_POWERLIB_EXTEND (1) 340 341 /* RTC module features */ 342 343 /* @brief Has SUBSEC Register (register SUBSEC) */ 344 #define FSL_FEATURE_RTC_HAS_SUBSEC (1) 345 346 /* SCT module features */ 347 348 /* @brief Number of events */ 349 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 350 /* @brief Number of states */ 351 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 352 /* @brief Number of match capture */ 353 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 354 /* @brief Number of outputs */ 355 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 356 357 /* SDIF module features */ 358 359 /* @brief FIFO depth, every location is a WORD */ 360 #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) 361 /* @brief Max DMA buffer size */ 362 #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) 363 /* @brief Max source clock in HZ */ 364 #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) 365 /* @brief support 2 cards */ 366 #define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) 367 368 /* SECPINT module features */ 369 370 /* @brief Number of connected outputs */ 371 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) 372 373 /* SPI module features */ 374 375 /* @brief SSEL pin count. */ 376 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 377 378 /* SYSCON module features */ 379 380 /* @brief Flash page size in bytes */ 381 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) 382 /* @brief Flash sector size in bytes */ 383 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) 384 /* @brief Flash size in bytes */ 385 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) 386 /* @brief Has Power Down mode */ 387 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) 388 /* @brief CCM_ANALOG availability on the SoC. */ 389 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 390 /* @brief Starter register discontinuous. */ 391 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 392 393 /* SYSCTL1 module features */ 394 395 /* No feature definitions */ 396 397 /* USB module features */ 398 399 /* @brief Size of the USB dedicated RAM */ 400 #define FSL_FEATURE_USB_USB_RAM (0x00004000) 401 /* @brief Base address of the USB dedicated RAM */ 402 #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) 403 /* @brief USB version */ 404 #define FSL_FEATURE_USB_VERSION (200) 405 /* @brief Number of the endpoint in USB FS */ 406 #define FSL_FEATURE_USB_EP_NUM (5) 407 408 /* USBFSH module features */ 409 410 /* @brief Size of the USB dedicated RAM */ 411 #define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) 412 /* @brief Base address of the USB dedicated RAM */ 413 #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) 414 /* @brief USBFSH version */ 415 #define FSL_FEATURE_USBFSH_VERSION (200) 416 417 /* USBHSD module features */ 418 419 /* @brief Size of the USB dedicated RAM */ 420 #define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) 421 /* @brief Base address of the USB dedicated RAM */ 422 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) 423 /* @brief USBHSD version */ 424 #define FSL_FEATURE_USBHSD_VERSION (300) 425 /* @brief Number of the endpoint in USB HS */ 426 #define FSL_FEATURE_USBHSD_EP_NUM (6) 427 428 /* USBHSH module features */ 429 430 /* @brief Size of the USB dedicated RAM */ 431 #define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) 432 /* @brief Base address of the USB dedicated RAM */ 433 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) 434 /* @brief USBHSH version */ 435 #define FSL_FEATURE_USBHSH_VERSION (300) 436 437 /* USBPHY module features */ 438 439 /* @brief Size of the USB dedicated RAM */ 440 #define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) 441 /* @brief Base address of the USB dedicated RAM */ 442 #define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) 443 /* @brief USBHSD version */ 444 #define FSL_FEATURE_USBPHY_VERSION (300) 445 /* @brief Number of the endpoint in USB HS */ 446 #define FSL_FEATURE_USBPHY_EP_NUM (6) 447 448 /* WWDT module features */ 449 450 /* @brief Has no RESET register. */ 451 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 452 /* @brief WWDT does not support oscillator lock. */ 453 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) 454 455 #endif /* _LPC5528_FEATURES_H_ */ 456 457
