1 /* 2 ** ################################################################### 3 ** Version: rev. 1.1, 2019-05-16 4 ** Build: b220725 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2018-08-22) 20 ** Initial version based on v0.2UM 21 ** - rev. 1.1 (2019-05-16) 22 ** Initial A1 version based on v1.3UM 23 ** 24 ** ################################################################### 25 */ 26 27 #ifndef _LPC5526_FEATURES_H_ 28 #define _LPC5526_FEATURES_H_ 29 30 /* SOC module features */ 31 32 /* @brief CRC availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CRC_COUNT (1) 34 /* @brief CTIMER availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 36 /* @brief DMA availability on the SoC. */ 37 #define FSL_FEATURE_SOC_DMA_COUNT (2) 38 /* @brief FLASH availability on the SoC. */ 39 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 40 /* @brief FLEXCOMM availability on the SoC. */ 41 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 42 /* @brief GINT availability on the SoC. */ 43 #define FSL_FEATURE_SOC_GINT_COUNT (2) 44 /* @brief GPIO availability on the SoC. */ 45 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 46 /* @brief SECGPIO availability on the SoC. */ 47 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 48 /* @brief I2C availability on the SoC. */ 49 #define FSL_FEATURE_SOC_I2C_COUNT (8) 50 /* @brief I2S availability on the SoC. */ 51 #define FSL_FEATURE_SOC_I2S_COUNT (8) 52 /* @brief INPUTMUX availability on the SoC. */ 53 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 54 /* @brief IOCON availability on the SoC. */ 55 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 56 /* @brief LPADC availability on the SoC. */ 57 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 58 /* @brief MPU availability on the SoC. */ 59 #define FSL_FEATURE_SOC_MPU_COUNT (1) 60 /* @brief MRT availability on the SoC. */ 61 #define FSL_FEATURE_SOC_MRT_COUNT (1) 62 /* @brief OSTIMER availability on the SoC. */ 63 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 64 /* @brief PINT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_PINT_COUNT (1) 66 /* @brief SECPINT availability on the SoC. */ 67 #define FSL_FEATURE_SOC_SECPINT_COUNT (1) 68 /* @brief PMC availability on the SoC. */ 69 #define FSL_FEATURE_SOC_PMC_COUNT (1) 70 /* @brief LPC_RNG1 availability on the SoC. */ 71 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) 72 /* @brief RTC availability on the SoC. */ 73 #define FSL_FEATURE_SOC_RTC_COUNT (1) 74 /* @brief SCT availability on the SoC. */ 75 #define FSL_FEATURE_SOC_SCT_COUNT (1) 76 /* @brief SDIF availability on the SoC. */ 77 #define FSL_FEATURE_SOC_SDIF_COUNT (1) 78 /* @brief SPI availability on the SoC. */ 79 #define FSL_FEATURE_SOC_SPI_COUNT (9) 80 /* @brief SYSCON availability on the SoC. */ 81 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 82 /* @brief SYSCTL1 availability on the SoC. */ 83 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 84 /* @brief USART availability on the SoC. */ 85 #define FSL_FEATURE_SOC_USART_COUNT (8) 86 /* @brief USB availability on the SoC. */ 87 #define FSL_FEATURE_SOC_USB_COUNT (1) 88 /* @brief USBFSH availability on the SoC. */ 89 #define FSL_FEATURE_SOC_USBFSH_COUNT (1) 90 /* @brief USBHSD availability on the SoC. */ 91 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 92 /* @brief USBHSH availability on the SoC. */ 93 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 94 /* @brief USBPHY availability on the SoC. */ 95 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 96 /* @brief UTICK availability on the SoC. */ 97 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 98 /* @brief WWDT availability on the SoC. */ 99 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 100 101 /* LPADC module features */ 102 103 /* @brief FIFO availability on the SoC. */ 104 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 105 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 106 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 107 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 108 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 109 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 110 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 111 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 112 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 113 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 114 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 115 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 116 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 117 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 118 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 119 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 120 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 121 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 122 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 123 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 124 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 125 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 126 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 127 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 128 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 129 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 130 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 131 /* @brief Has offset trim (register OFSTRIM). */ 132 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 133 /* @brief Has Trigger status register. */ 134 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 135 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 136 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 137 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 138 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 139 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 140 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 141 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 142 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 143 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 144 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 145 /* @brief Conversion averaged bitfiled width. */ 146 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 147 /* @brief Has internal temperature sensor. */ 148 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 149 /* @brief Temperature sensor parameter A (slope). */ 150 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f) 151 /* @brief Temperature sensor parameter B (offset). */ 152 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f) 153 /* @brief Temperature sensor parameter Alpha. */ 154 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f) 155 /* @brief the buffer size of temperature sensor. */ 156 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) 157 158 /* ANALOGCTRL module features */ 159 160 /* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ 161 #define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) 162 /* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ 163 #define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) 164 /* @brief Has auxiliary bias(register AUX_BIAS). */ 165 #define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) 166 167 /* CTIMER module features */ 168 169 /* @brief CTIMER has no capture channel. */ 170 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 171 /* @brief CTIMER has no capture 2 interrupt. */ 172 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 173 /* @brief CTIMER capture 3 interrupt. */ 174 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 175 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 176 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 177 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 178 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 179 /* @brief CTIMER Has register MSR */ 180 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 181 182 /* DMA module features */ 183 184 /* @brief Number of channels */ 185 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) 186 /* @brief Align size of DMA descriptor */ 187 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 188 /* @brief DMA head link descriptor table align size */ 189 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 190 191 /* FLEXCOMM module features */ 192 193 /* @brief FLEXCOMM0 USART INDEX 0 */ 194 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 195 /* @brief FLEXCOMM0 SPI INDEX 0 */ 196 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 197 /* @brief FLEXCOMM0 I2C INDEX 0 */ 198 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 199 /* @brief FLEXCOMM0 I2S INDEX 0 */ 200 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 201 /* @brief FLEXCOMM1 USART INDEX 1 */ 202 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 203 /* @brief FLEXCOMM1 SPI INDEX 1 */ 204 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 205 /* @brief FLEXCOMM1 I2C INDEX 1 */ 206 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 207 /* @brief FLEXCOMM1 I2S INDEX 1 */ 208 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 209 /* @brief FLEXCOMM2 USART INDEX 2 */ 210 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 211 /* @brief FLEXCOMM2 SPI INDEX 2 */ 212 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 213 /* @brief FLEXCOMM2 I2C INDEX 2 */ 214 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 215 /* @brief FLEXCOMM2 I2S INDEX 2 */ 216 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 217 /* @brief FLEXCOMM3 USART INDEX 3 */ 218 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 219 /* @brief FLEXCOMM3 SPI INDEX 3 */ 220 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 221 /* @brief FLEXCOMM3 I2C INDEX 3 */ 222 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 223 /* @brief FLEXCOMM3 I2S INDEX 3 */ 224 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 225 /* @brief FLEXCOMM4 USART INDEX 4 */ 226 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 227 /* @brief FLEXCOMM4 SPI INDEX 4 */ 228 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 229 /* @brief FLEXCOMM4 I2C INDEX 4 */ 230 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 231 /* @brief FLEXCOMM4 I2S INDEX 4 */ 232 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 233 /* @brief FLEXCOMM5 USART INDEX 5 */ 234 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 235 /* @brief FLEXCOMM5 SPI INDEX 5 */ 236 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 237 /* @brief FLEXCOMM5 I2C INDEX 5 */ 238 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 239 /* @brief FLEXCOMM5 I2S INDEX 5 */ 240 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 241 /* @brief FLEXCOMM6 USART INDEX 6 */ 242 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 243 /* @brief FLEXCOMM6 SPI INDEX 6 */ 244 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 245 /* @brief FLEXCOMM6 I2C INDEX 6 */ 246 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 247 /* @brief FLEXCOMM6 I2S INDEX 6 */ 248 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 249 /* @brief FLEXCOMM7 USART INDEX 7 */ 250 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 251 /* @brief FLEXCOMM7 SPI INDEX 7 */ 252 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 253 /* @brief FLEXCOMM7 I2C INDEX 7 */ 254 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 255 /* @brief FLEXCOMM7 I2S INDEX 7 */ 256 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 257 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 258 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 259 /* @brief I2S has DMIC interconnection */ 260 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) 261 262 /* GINT module features */ 263 264 /* @brief The count of th port which are supported in GINT. */ 265 #define FSL_FEATURE_GINT_PORT_COUNT (2) 266 267 /* I2S module features */ 268 269 /* @brief I2S support dual channel transfer. */ 270 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) 271 /* @brief I2S has DMIC interconnection */ 272 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) 273 274 /* IOCON module features */ 275 276 /* @brief Func bit field width */ 277 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 278 279 /* MRT module features */ 280 281 /* @brief number of channels. */ 282 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 283 284 /* PINT module features */ 285 286 /* @brief Number of connected outputs */ 287 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 288 289 /* PLU module features */ 290 291 /* @brief Has WAKEINT_CTRL register. */ 292 #define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) 293 294 /* PMC module features */ 295 296 /* @brief UTICK does not support PD configure. */ 297 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 298 /* @brief WDT OSC does not support PD configure. */ 299 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 300 301 /* POWERLIB module features */ 302 303 /* @brief Powerlib API is different with other LPC series devices. */ 304 #define FSL_FEATURE_POWERLIB_EXTEND (1) 305 306 /* RTC module features */ 307 308 /* No feature definitions */ 309 310 /* SCT module features */ 311 312 /* @brief Number of events */ 313 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 314 /* @brief Number of states */ 315 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 316 /* @brief Number of match capture */ 317 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 318 /* @brief Number of outputs */ 319 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 320 321 /* SDIF module features */ 322 323 /* @brief FIFO depth, every location is a WORD */ 324 #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) 325 /* @brief Max DMA buffer size */ 326 #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) 327 /* @brief Max source clock in HZ */ 328 #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) 329 /* @brief support 2 cards */ 330 #define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) 331 332 /* SECPINT module features */ 333 334 /* @brief Number of connected outputs */ 335 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) 336 337 /* SPI module features */ 338 339 /* @brief SSEL pin count. */ 340 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 341 342 /* SYSCON module features */ 343 344 /* @brief Flash page size in bytes */ 345 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) 346 /* @brief Flash sector size in bytes */ 347 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) 348 /* @brief Flash size in bytes */ 349 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) 350 /* @brief Has Power Down mode */ 351 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) 352 /* @brief CCM_ANALOG availability on the SoC. */ 353 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 354 /* @brief Starter register discontinuous. */ 355 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 356 357 /* SYSCTL1 module features */ 358 359 /* No feature definitions */ 360 361 /* USB module features */ 362 363 /* @brief Size of the USB dedicated RAM */ 364 #define FSL_FEATURE_USB_USB_RAM (0x00004000) 365 /* @brief Base address of the USB dedicated RAM */ 366 #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) 367 /* @brief USB version */ 368 #define FSL_FEATURE_USB_VERSION (200) 369 /* @brief Number of the endpoint in USB FS */ 370 #define FSL_FEATURE_USB_EP_NUM (5) 371 372 /* USBFSH module features */ 373 374 /* @brief Size of the USB dedicated RAM */ 375 #define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) 376 /* @brief Base address of the USB dedicated RAM */ 377 #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) 378 /* @brief USBFSH version */ 379 #define FSL_FEATURE_USBFSH_VERSION (200) 380 381 /* USBHSD module features */ 382 383 /* @brief Size of the USB dedicated RAM */ 384 #define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) 385 /* @brief Base address of the USB dedicated RAM */ 386 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) 387 /* @brief USBHSD version */ 388 #define FSL_FEATURE_USBHSD_VERSION (300) 389 /* @brief Number of the endpoint in USB HS */ 390 #define FSL_FEATURE_USBHSD_EP_NUM (6) 391 392 /* USBHSH module features */ 393 394 /* @brief Size of the USB dedicated RAM */ 395 #define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) 396 /* @brief Base address of the USB dedicated RAM */ 397 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) 398 /* @brief USBHSH version */ 399 #define FSL_FEATURE_USBHSH_VERSION (300) 400 401 /* USBPHY module features */ 402 403 /* @brief Size of the USB dedicated RAM */ 404 #define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) 405 /* @brief Base address of the USB dedicated RAM */ 406 #define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) 407 /* @brief USBHSD version */ 408 #define FSL_FEATURE_USBPHY_VERSION (300) 409 /* @brief Number of the endpoint in USB HS */ 410 #define FSL_FEATURE_USBPHY_EP_NUM (6) 411 412 /* WWDT module features */ 413 414 /* @brief Has no RESET register. */ 415 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 416 /* @brief WWDT does not support oscillator lock. */ 417 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) 418 419 #endif /* _LPC5526_FEATURES_H_ */ 420 421
