1# SPDX-License-Identifier: BSD-3-Clause 2 3config XT_WAITI_DELAY 4 bool 5 default n 6 help 7 LX6 Xtensa platforms may require additional delay to flush loads 8 and stores before entering WAITI. 9 10config HOST_PTABLE 11 bool 12 default n 13 14config XT_BOOT_LOADER 15 bool 16 default n 17 18config XT_HAVE_RESET_VECTOR_ROM 19 bool 20 default n 21 help 22 Select if your platform has the reset vector 23 in ROM. 24 25config XT_IRQ_MAP 26 bool 27 default n 28 29config DMA_GW 30 bool 31 default n 32 33config MEM_WND 34 bool 35 default n 36 37config INTEL_IOMUX 38 bool 39 default n 40 41config DMA_HW_LLI 42 bool 43 default n 44 help 45 Hardware linked list is DMA feature, which allows 46 to automatically reload the next programmed linked list 47 item from memory without stopping the transfer. Without 48 it the transfer stops after every lli read and FW needs 49 to manually setup the next transfer. 50 51 Any platforms with hardware linked list support 52 should set this. 53 54config DMA_SUSPEND_DRAIN 55 bool 56 default n 57 help 58 Some platforms cannot just simple disable DMA 59 channel during the transfer, because it will 60 hang the whole DMA controller. Instead we can 61 suspend the channel and drain the FIFO in order 62 to stop the channel as soon as possible. 63 64 Any platforms without the ability to disable 65 the DMA channel right away should set this. 66 67config DMA_FIFO_PARTITION 68 bool 69 default n 70 help 71 Some platforms require to manually set DMA 72 FIFO partitions before starting any transfer. 73 74 Any platforms without automatic FIFO partitions 75 should set this. 76 77config XT_INTERRUPT_LEVEL_1 78 bool 79 default n 80 help 81 Select if the platform supports any interrupts of level 1. 82 Disabling this option allows for less memory consumption. 83 84config XT_INTERRUPT_LEVEL_2 85 bool 86 default n 87 help 88 Select if the platform supports any interrupts of level 2. 89 Disabling this option allows for less memory consumption. 90 91config XT_INTERRUPT_LEVEL_3 92 bool 93 default n 94 help 95 Select if the platform supports any interrupts of level 3. 96 Disabling this option allows for less memory consumption. 97 98config XT_INTERRUPT_LEVEL_4 99 bool 100 default n 101 help 102 Select if the platform supports any interrupts of level 4. 103 Disabling this option allows for less memory consumption. 104 105config XT_INTERRUPT_LEVEL_5 106 bool 107 default n 108 help 109 Select if the platform supports any interrupts of level 5. 110 Disabling this option allows for less memory consumption. 111 112config COMPILER_WORKAROUND_CACHE_ATTR 113 bool 114 default n 115 help 116 Select this to activate use of functions instead of macros 117 to decide whether an address is cacheable or not. 118 There is a weird optimization bug with gcc10x and gcc8.1 119 (with -O2 flags) on IMX platforms. See PR #4605. 120 121rsource "src/Kconfig" 122 123# See zephyr/modules/Kconfig 124if !ZEPHYR_SOF_MODULE 125 rsource "Kconfig.xtos-build" 126endif 127 128if ZEPHYR_SOF_MODULE 129 rsource "Kconfig.zephyr-log" 130endif 131 132menu "Debug" 133 134config DEBUG 135 bool "Enable debug build" 136 default n 137 help 138 Select for debug build 139 140config GDB_DEBUG 141 bool "GDB Stub" 142 default n 143 help 144 Select for GDB debugging 145 146config DEBUG_MEMORY_USAGE_SCAN 147 bool "Memory usage scan" 148 default y 149 help 150 It enables memory usage scan at demand in runtime. 151 This feature does not affect standard memory operations, 152 especially allocation and deallocation. 153 154config DEBUG_LOCKS 155 bool "Spinlock debug" 156 default n 157 help 158 It adds additional information to the spinlocks about 159 the current user of the lock. Also executes panic 160 on deadlock. 161 162config DEBUG_LOCKS_VERBOSE 163 bool "Spinlock verbose debug" 164 depends on DEBUG_LOCKS 165 default n 166 help 167 In addition to DEBUG_LOCKS it also adds spinlock traces 168 every time the lock is acquired. 169 170config DEBUG_IPC_COUNTERS 171 bool "IPC counters" 172 depends on CAVS 173 depends on DEBUG 174 default n 175 help 176 Select for enabling tracing IPC counter in SRAM_REG mailbox 177 178config SCHEDULE_LOG_CYCLE_STATISTICS 179 bool "Log cycles per tick statistics for each task separately" 180 default y 181 help 182 Log DSP cycle usage statistics about once per second (1ms * 183 1024) for each task separately. The printed data is task's 184 meta information, average number of cycles/tick, and maximum 185 number of cycles/tick during the previous 1024 tick period. 186 187config PERFORMANCE_COUNTERS 188 bool "Performance counters" 189 default n 190 help 191 Enables tracing of simple performance measurements. 192 A basic use case is to measure number of platform & cpu clock ticks 193 passed between two checkpoints (init() and stamp()), for example 194 total time spent on running low latency scheduler tasks. 195 Platforms that gate cpu clock in wait-for-interrupt calls may also 196 use the stamp() macro periodically to find out how long the cpu 197 was in active/sleep state between the calls and estimate the cpu load. 198 199config DSP_RESIDENCY_COUNTERS 200 bool "DSP residency counters" 201 default n 202 help 203 Enables simple DSP residency counters in SRAM_REG mailbox. 204 R0, R1, R2 are abstract states which can be used differently 205 based on platform implementation. 206 207if !ZEPHYR_SOF_MODULE 208 rsource "Kconfig.xtos-dbg" 209endif 210 211endmenu 212
