1# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
2# SPDX-License-Identifier: Apache-2.0
3
4config RISCV_ISA_RV32I
5	bool
6	help
7	  RV32I Base Integer Instruction Set - 32bit
8
9config RISCV_ISA_RV32E
10	bool
11	help
12	  RV32E Base Integer Instruction Set (Embedded) - 32bit
13
14config RISCV_ISA_RV64I
15	bool
16	default y if 64BIT
17	help
18	  RV64I Base Integer Instruction Set - 64bit
19
20config RISCV_ISA_RV128I
21	bool
22	help
23	  RV128I Base Integer Instruction Set - 128bit
24
25config RISCV_ISA_EXT_M
26	bool
27	help
28	  (M) - Standard Extension for Integer Multiplication and Division
29
30	  Standard integer multiplication and division instruction extension,
31	  which is named "M" and contains instructions that multiply or divide
32	  values held in two integer registers.
33
34config RISCV_ISA_EXT_A
35	bool
36	imply RISCV_ISA_EXT_ZAAMO
37	imply RISCV_ISA_EXT_ZLRSC
38	help
39	  (A) - Standard Extension for Atomic Instructions
40
41	  The standard atomic instruction extension is denoted by instruction
42	  subset name "A", and contains instructions that atomically
43	  read-modify-write memory to support synchronization between multiple
44	  RISC-V threads running in the same memory space.
45
46config RISCV_ISA_EXT_F
47	bool
48	help
49	  (F) - Standard Extension for Single-Precision Floating-Point
50
51	  Standard instruction-set extension for single-precision
52	  floating-point, which is named "F" and adds single-precision
53	  floating-point computational instructions compliant with the IEEE
54	  754-2008 arithmetic standard.
55
56config RISCV_ISA_EXT_D
57	bool
58	depends on RISCV_ISA_EXT_F
59	help
60	  (D) - Standard Extension for Double-Precision Floating-Point
61
62	  Standard double-precision floating-point instruction-set extension,
63	  which is named "D" and adds double-precision floating-point
64	  computational instructions compliant with the IEEE 754-2008
65	  arithmetic standard.
66
67config RISCV_ISA_EXT_G
68	bool
69	select RISCV_ISA_EXT_M
70	select RISCV_ISA_EXT_A
71	select RISCV_ISA_EXT_F
72	select RISCV_ISA_EXT_D
73	select RISCV_ISA_EXT_ZICSR
74	select RISCV_ISA_EXT_ZIFENCEI
75	help
76	  (IMAFDZicsr_Zifencei) IMAFDZicsr_Zifencei extensions
77
78config RISCV_ISA_EXT_Q
79	bool
80	depends on RISCV_ISA_RV64I
81	depends on RISCV_ISA_EXT_F
82	depends on RISCV_ISA_EXT_D
83	help
84	  (Q) - Standard Extension for Quad-Precision Floating-Point
85
86	  Standard extension for 128-bit binary floating-point instructions
87	  compliant with the IEEE 754-2008 arithmetic standard. The 128-bit or
88	  quad-precision binary floatingpoint instruction subset is named "Q".
89
90config RISCV_ISA_EXT_C
91	bool
92	help
93	  (C) - Standard Extension for Compressed Instructions
94
95	  RISC-V standard compressed instruction set extension, named "C",
96	  which reduces static and dynamic code size by adding short 16-bit
97	  instruction encodings for common operations.
98
99config RISCV_ISA_EXT_ZICSR
100	bool
101	help
102	  (Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions
103
104	  The "Zicsr" extension introduces support for the full set of CSR
105	  instructions that operate on CSRs registers.
106
107config RISCV_ISA_EXT_ZIFENCEI
108	bool
109	help
110	  (Zifencei) - Standard Extension for Instruction-Fetch Fence
111
112	  The "Zifencei" extension includes the FENCE.I instruction that
113	  provides explicit synchronization between writes to instruction
114	  memory and instruction fetches on the same hart.
115
116config RISCV_ISA_EXT_ZAAMO
117	bool
118	help
119	  (Zaamo) - Atomic memory operation subset of the A extension
120
121	  The Zaamo extension enables support for AMO*.W/D-style instructions.
122
123config RISCV_ISA_EXT_ZLRSC
124	bool
125	help
126	  (Zlrsc) - Load-Reserved/Store-Conditional subset of the A extension
127
128	  The Zlrsc extension enables support for LR.W/D and SC.W/D-style instructions.
129
130config RISCV_ISA_EXT_ZBA
131	bool
132	help
133	  (Zba) - Zba BitManip Extension
134
135	  The Zba instructions can be used to accelerate the generation of
136	  addresses that index into arrays of basic types (halfword, word,
137	  doubleword) using both unsigned word-sized and XLEN-sized indices: a
138	  shifted index is added to a base address.
139
140config RISCV_ISA_EXT_ZBB
141	bool
142	help
143	  (Zbb) - Zbb BitManip Extension (Basic bit-manipulation)
144
145	  The Zbb instructions can be used for basic bit-manipulation (logical
146	  with negate, count leading / trailing zero bits, count population,
147	  etc...).
148
149config RISCV_ISA_EXT_ZBC
150	bool
151	help
152	  (Zbc) - Zbc BitManip Extension (Carry-less multiplication)
153
154	  The Zbc instructions can be used for carry-less multiplication that
155	  is the multiplication in the polynomial ring over GF(2).
156
157config RISCV_ISA_EXT_ZBS
158	bool
159	help
160	  (Zbs) - Zbs BitManip Extension (Single-bit instructions)
161
162	  The Zbs instructions can be used for single-bit instructions that
163	  provide a mechanism to set, clear, invert, or extract a single bit in
164	  a register.
165