1 /*
2 ** ###################################################################
3 **     Version:             rev. 1.0, 2019-04-22
4 **     Build:               b240301
5 **
6 **     Abstract:
7 **         Chip specific module features.
8 **
9 **     Copyright 2016 Freescale Semiconductor, Inc.
10 **     Copyright 2016-2024 NXP
11 **     SPDX-License-Identifier: BSD-3-Clause
12 **
13 **     http:                 www.nxp.com
14 **     mail:                 support@nxp.com
15 **
16 **     Revisions:
17 **     - rev. 1.0 (2019-04-22)
18 **         Initial version.
19 **
20 ** ###################################################################
21 */
22 
23 #ifndef _K32L3A60_cm0plus_FEATURES_H_
24 #define _K32L3A60_cm0plus_FEATURES_H_
25 
26 /* SOC module features */
27 
28 /* @brief CAU3 availability on the SoC. */
29 #define FSL_FEATURE_SOC_CAU3_COUNT (1)
30 /* @brief CRC availability on the SoC. */
31 #define FSL_FEATURE_SOC_CRC_COUNT (1)
32 /* @brief DMAMUX availability on the SoC. */
33 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
34 /* @brief EDMA availability on the SoC. */
35 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
36 /* @brief EMVSIM availability on the SoC. */
37 #define FSL_FEATURE_SOC_EMVSIM_COUNT (1)
38 /* @brief EWM availability on the SoC. */
39 #define FSL_FEATURE_SOC_EWM_COUNT (1)
40 /* @brief FB availability on the SoC. */
41 #define FSL_FEATURE_SOC_FB_COUNT (1)
42 /* @brief FGPIO availability on the SoC. */
43 #define FSL_FEATURE_SOC_FGPIO_COUNT (1)
44 /* @brief FLASH availability on the SoC. */
45 #define FSL_FEATURE_SOC_FLASH_COUNT (1)
46 /* @brief FLEXIO availability on the SoC. */
47 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
48 /* @brief GPIO availability on the SoC. */
49 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
50 /* @brief I2S availability on the SoC. */
51 #define FSL_FEATURE_SOC_I2S_COUNT (1)
52 /* @brief INTMUX availability on the SoC. */
53 #define FSL_FEATURE_SOC_INTMUX_COUNT (1)
54 /* @brief LLWU availability on the SoC. */
55 #define FSL_FEATURE_SOC_LLWU_COUNT (2)
56 /* @brief LPADC availability on the SoC. */
57 #define FSL_FEATURE_SOC_LPADC_COUNT (1)
58 /* @brief LPCMP availability on the SoC. */
59 #define FSL_FEATURE_SOC_LPCMP_COUNT (2)
60 /* @brief LPDAC availability on the SoC. */
61 #define FSL_FEATURE_SOC_LPDAC_COUNT (1)
62 /* @brief LPI2C availability on the SoC. */
63 #define FSL_FEATURE_SOC_LPI2C_COUNT (4)
64 /* @brief LPIT availability on the SoC. */
65 #define FSL_FEATURE_SOC_LPIT_COUNT (2)
66 /* @brief LPSPI availability on the SoC. */
67 #define FSL_FEATURE_SOC_LPSPI_COUNT (4)
68 /* @brief LPTMR availability on the SoC. */
69 #define FSL_FEATURE_SOC_LPTMR_COUNT (3)
70 /* @brief LPUART availability on the SoC. */
71 #define FSL_FEATURE_SOC_LPUART_COUNT (4)
72 /* @brief MCM availability on the SoC. */
73 #define FSL_FEATURE_SOC_MCM_COUNT (1)
74 /* @brief MMDVSQ availability on the SoC. */
75 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (1)
76 /* @brief MSCM availability on the SoC. */
77 #define FSL_FEATURE_SOC_MSCM_COUNT (1)
78 /* @brief MTB availability on the SoC. */
79 #define FSL_FEATURE_SOC_MTB_COUNT (1)
80 /* @brief MTBDWT availability on the SoC. */
81 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
82 /* @brief MU availability on the SoC. */
83 #define FSL_FEATURE_SOC_MU_COUNT (1)
84 /* @brief PCC availability on the SoC. */
85 #define FSL_FEATURE_SOC_PCC_COUNT (2)
86 /* @brief PORT availability on the SoC. */
87 #define FSL_FEATURE_SOC_PORT_COUNT (5)
88 /* @brief ROM availability on the SoC. */
89 #define FSL_FEATURE_SOC_ROM_COUNT (1)
90 /* @brief RTC availability on the SoC. */
91 #define FSL_FEATURE_SOC_RTC_COUNT (1)
92 /* @brief SCG availability on the SoC. */
93 #define FSL_FEATURE_SOC_SCG_COUNT (1)
94 /* @brief SEMA42 availability on the SoC. */
95 #define FSL_FEATURE_SOC_SEMA42_COUNT (2)
96 /* @brief SIM availability on the SoC. */
97 #define FSL_FEATURE_SOC_SIM_COUNT (1)
98 /* @brief SMC availability on the SoC. */
99 #define FSL_FEATURE_SOC_SMC_COUNT (2)
100 /* @brief SPM availability on the SoC. */
101 #define FSL_FEATURE_SOC_SPM_COUNT (1)
102 /* @brief TPM availability on the SoC. */
103 #define FSL_FEATURE_SOC_TPM_COUNT (4)
104 /* @brief TRGMUX availability on the SoC. */
105 #define FSL_FEATURE_SOC_TRGMUX_COUNT (2)
106 /* @brief TRNG availability on the SoC. */
107 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
108 /* @brief TSTMR availability on the SoC. */
109 #define FSL_FEATURE_SOC_TSTMR_COUNT (1)
110 /* @brief USB availability on the SoC. */
111 #define FSL_FEATURE_SOC_USB_COUNT (1)
112 /* @brief USBVREG availability on the SoC. */
113 #define FSL_FEATURE_SOC_USBVREG_COUNT (1)
114 /* @brief USDHC availability on the SoC. */
115 #define FSL_FEATURE_SOC_USDHC_COUNT (1)
116 /* @brief VREF availability on the SoC. */
117 #define FSL_FEATURE_SOC_VREF_COUNT (1)
118 /* @brief WDOG availability on the SoC. */
119 #define FSL_FEATURE_SOC_WDOG_COUNT (2)
120 /* @brief XRDC availability on the SoC. */
121 #define FSL_FEATURE_SOC_XRDC_COUNT (1)
122 
123 /* interrupt module features */
124 
125 /* @brief Lowest interrupt request number. */
126 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
127 /* @brief Highest interrupt request number. */
128 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
129 
130 /* CRC module features */
131 
132 /* @brief Has data register with name CRC */
133 #define FSL_FEATURE_CRC_HAS_CRC_REG (0)
134 
135 /* EDMA module features */
136 
137 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
138 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (8)
139 /* @brief Total number of DMA channels on all modules. */
140 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (8)
141 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
142 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
143 /* @brief Has DMA_Error interrupt vector. */
144 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
145 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
146 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8)
147 /* @brief Channel IRQ entry shared offset. */
148 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (4)
149 /* @brief If 8 bytes transfer supported. */
150 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0)
151 /* @brief If 16 bytes transfer supported. */
152 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
153 /* @brief If 32 bytes transfer supported. */
154 #define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1)
155 
156 /* DMAMUX module features */
157 
158 /* @brief Number of DMA channels (related to number of register CHCFGn). */
159 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8)
160 /* @brief Total number of DMA channels on all modules. */
161 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16)
162 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
163 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
164 /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
165 #define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
166 /* @brief Register CHCFGn width. */
167 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32)
168 
169 /* EWM module features */
170 
171 /* @brief Has clock select (register CLKCTRL). */
172 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
173 /* @brief Has clock prescaler (register CLKPRESCALER). */
174 #define FSL_FEATURE_EWM_HAS_PRESCALER (1)
175 
176 /* FB module features */
177 
178 /* No feature definitions */
179 
180 /* FGPIO module features */
181 
182 /* No feature definitions */
183 
184 /* FLEXIO module features */
185 
186 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
187 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
188 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */
189 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
190 /* @brief Has pin input output related registers */
191 #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0)
192 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
193 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
194 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
195 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
196 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
197 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
198 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
199 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
200 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
201 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
202 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
203 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
204 /* @brief Reset value of the FLEXIO_VERID register */
205 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
206 /* @brief Reset value of the FLEXIO_PARAM register */
207 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808)
208 /* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */
209 #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2)
210 /* @brief Flexio DMA request base channel */
211 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
212 
213 /* FLASH module features */
214 
215 /* @brief Current core ID. */
216 #define FSL_FEATURE_FLASH_CURRENT_CORE_ID (1)
217 /* @brief Is of type FTFA. */
218 #define FSL_FEATURE_FLASH_IS_FTFA (0)
219 /* @brief Is of type FTFE. */
220 #define FSL_FEATURE_FLASH_IS_FTFE (1)
221 /* @brief Is of type FTFL. */
222 #define FSL_FEATURE_FLASH_IS_FTFL (0)
223 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
224 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
225 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
226 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
227 /* @brief Has EEPROM region protection (register FEPROT). */
228 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
229 /* @brief Has data flash region protection (register FDPROT). */
230 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
231 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
232 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
233 /* @brief Has flash cache control in FMC module. */
234 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
235 /* @brief Has flash cache control in MCM module. */
236 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
237 /* @brief Has flash cache control in MSCM module. */
238 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (1)
239 /* @brief Has prefetch speculation control in flash, such as kv5x. */
240 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
241 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for others. */
242 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (1)
243 /* @brief P-Flash start address. */
244 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x01000000)
245 /* @brief P-Flash block count. */
246 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
247 /* @brief P-Flash block size. */
248 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
249 /* @brief P-Flash sector size. */
250 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
251 /* @brief P-Flash write unit size. */
252 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
253 /* @brief P-Flash data path width. */
254 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
255 /* @brief P-Flash block swap feature. */
256 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
257 /* @brief P-Flash protection region count. */
258 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (16)
259 /* @brief Has multiple flash. */
260 #define FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH (1)
261 /* @brief Flash memory count. */
262 #define FSL_FEATURE_FLASH_MEMORY_COUNT (2)
263 /* @brief P-Flash start address. */
264 #define FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS (0x00000000)
265 /* @brief P-Flash block count. */
266 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT (2)
267 /* @brief P-Flash block size. */
268 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE (524288)
269 /* @brief P-Flash sector size. */
270 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE (4096)
271 /* @brief P-Flash write unit size. */
272 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE (8)
273 /* @brief P-Flash data path width. */
274 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_DATA_PATH_WIDTH (16)
275 /* @brief P-Flash protection region count. */
276 #define FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT (64)
277 /* @brief P-Flash block swap feature. */
278 #define FSL_FEATURE_FLASH_HAS_1_PFLASH_BLOCK_SWAP (1)
279 /* @brief Has FlexNVM memory. */
280 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
281 /* @brief Has FlexNVM alias. */
282 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
283 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
284 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
285 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
286 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
287 /* @brief FlexNVM block count. */
288 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
289 /* @brief FlexNVM block size. */
290 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
291 /* @brief FlexNVM sector size. */
292 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
293 /* @brief FlexNVM write unit size. */
294 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
295 /* @brief FlexNVM data path width. */
296 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
297 /* @brief Has FlexRAM memory. */
298 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
299 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
300 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x48000000)
301 /* @brief FlexRAM size. */
302 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
303 /* @brief Has 0x00 Read 1s Block command. */
304 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
305 /* @brief Flash 1 has 0x00 Read 1s Block command. */
306 #define FSL_FEATURE_FLASH_HAS_1_READ_1S_BLOCK_CMD (1)
307 /* @brief Has 0x01 Read 1s Section command. */
308 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
309 /* @brief Has 0x02 Program Check command. */
310 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
311 /* @brief Has 0x03 Read Resource command. */
312 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (0)
313 /* @brief Has 0x06 Program Longword command. */
314 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
315 /* @brief Has 0x07 Program Phrase command. */
316 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
317 /* @brief Has 0x08 Erase Flash Block command. */
318 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
319 /* @brief Flash 1 has 0x08 Erase Flash Block command. */
320 #define FSL_FEATURE_FLASH_HAS_1_ERASE_FLASH_BLOCK_CMD (1)
321 /* @brief Has 0x09 Erase Flash Sector command. */
322 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
323 /* @brief Has 0x0B Program Section command. */
324 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
325 /* @brief Has 0x0C Generate CRC signature for selected program flash sectors. */
326 #define FSL_FEATURE_FLASH_HAS_GENERATE_CRC_CMD (1)
327 /* @brief Has 0x40 Read 1s All Blocks command. */
328 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
329 /* @brief Has 0x41 Read Once command. */
330 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
331 /* @brief Has 0x43 Program Once command. */
332 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
333 /* @brief Has 0x44 Erase All Blocks command. */
334 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
335 /* @brief Has 0x45 Verify Backdoor Access Key command. */
336 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
337 /* @brief Has 0x46 Swap Control command. */
338 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
339 /* @brief Flash 1 has 0x46 Swap Control command. */
340 #define FSL_FEATURE_FLASH_HAS_1_SWAP_CONTROL_CMD (1)
341 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
342 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
343 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
344 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
345 /* @brief Has 0x4B Erase All Execute-only Segments command. */
346 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
347 /* @brief Has 0x80 Program Partition command. */
348 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
349 /* @brief Has 0x81 Set FlexRAM Function command. */
350 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
351 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
352 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
353 /* @brief P-Flash Erase sector command address alignment. */
354 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
355 /* @brief P-Flash Erase sector command address alignment. */
356 #define FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT (16)
357 /* @brief P-Flash Program/Verify section command address alignment. */
358 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
359 /* @brief P-Flash Program/Verify section command address alignment. */
360 #define FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT (16)
361 /* @brief P-Flash Read resource command address alignment. */
362 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
363 /* @brief P-Flash Program check command address alignment. */
364 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
365 /* @brief P-Flash Program check command address alignment. */
366 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
367 /* @brief P-Flash 1 Program check command address alignment. */
368 #define FSL_FEATURE_FLASH_PFLASH_1_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
369 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
370 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
371 /* @brief FlexNVM Erase sector command address alignment. */
372 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
373 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
374 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
375 /* @brief FlexNVM Read resource command address alignment. */
376 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
377 /* @brief FlexNVM Program check command address alignment. */
378 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
379 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
380 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
381 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
382 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
383 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
384 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
385 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
386 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
387 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
388 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
389 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
390 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
391 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
392 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
393 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
394 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
395 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
396 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
397 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
398 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
399 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
400 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
401 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
402 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
403 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
404 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
405 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
406 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
407 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
408 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
409 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
410 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
411 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
412 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
413 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
414 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
415 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
416 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
417 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
418 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
419 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
420 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
421 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
422 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
423 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
424 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
425 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
426 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
427 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
428 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
429 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
430 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
431 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
432 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
433 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
434 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
435 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
436 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
437 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
438 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
439 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
440 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
441 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
442 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
443 
444 /* GPIO module features */
445 
446 /* @brief Has GPIO attribute checker register (GACR). */
447 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
448 
449 /* SAI module features */
450 
451 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */
452 #define FSL_FEATURE_SAI_HAS_FIFO (1)
453 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
454 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8)
455 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
456 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2)
457 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
458 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
459 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
460 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
461 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
462 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
463 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
464 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
465 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
466 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
467 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
468 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
469 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
470 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
471 /* @brief Interrupt source number */
472 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
473 /* @brief Has register of MCR. */
474 #define FSL_FEATURE_SAI_HAS_MCR (0)
475 /* @brief Has bit field MICS of the MCR register. */
476 #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
477 /* @brief Has register of MDR */
478 #define FSL_FEATURE_SAI_HAS_MDR (0)
479 /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
480 #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
481 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
482 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
483 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
484 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
485 /* @brief Support synchronous with another SAI. */
486 #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0)
487 
488 /* INTMUX module features */
489 
490 /* @brief Number of INTMUX channels (related to number of register CHn_CSR). */
491 #define FSL_FEATURE_INTMUX_CHANNEL_COUNT (8)
492 /* @brief Number of INTMUX IRQ source. */
493 #define FSL_FEATURE_INTMUX_IRQ_COUNT (32)
494 /* @brief The start IRQ index of first INTMUX source IRQ. */
495 #define FSL_FEATURE_INTMUX_IRQ_START_INDEX (32)
496 /* @brief The direction of INTMUX. OUT, route the CM4 subsystem IRQ to System. */
497 #define FSL_FEATURE_INTMUX_DIRECTION_OUT (0)
498 /* @brief The total number of level1 interrupt vectors. */
499 #define FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS (32)
500 
501 /* LLWU module features */
502 
503 /* @brief Maximum number of pins connected to LLWU device. */
504 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32)
505 /* @brief Maximum number of internal modules connected to LLWU device. */
506 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
507 /* @brief Number of digital filters. */
508 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
509 /* @brief Has MF register. */
510 #define FSL_FEATURE_LLWU_HAS_MF (0)
511 /* @brief Has PF register. */
512 #define FSL_FEATURE_LLWU_HAS_PF (1)
513 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
514 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
515 /* @brief Has no internal module wakeup flag register. */
516 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (1)
517 /* @brief Has external pin 0 connected to LLWU device. */
518 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
519 /* @brief Index of port of external pin. */
520 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX)
521 /* @brief Number of external pin port on specified port. */
522 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
523 /* @brief Has external pin 1 connected to LLWU device. */
524 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
525 /* @brief Index of port of external pin. */
526 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX)
527 /* @brief Number of external pin port on specified port. */
528 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
529 /* @brief Has external pin 2 connected to LLWU device. */
530 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
531 /* @brief Index of port of external pin. */
532 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX)
533 /* @brief Number of external pin port on specified port. */
534 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (22)
535 /* @brief Has external pin 3 connected to LLWU device. */
536 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
537 /* @brief Index of port of external pin. */
538 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
539 /* @brief Number of external pin port on specified port. */
540 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (30)
541 /* @brief Has external pin 4 connected to LLWU device. */
542 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
543 /* @brief Index of port of external pin. */
544 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOB_IDX)
545 /* @brief Number of external pin port on specified port. */
546 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (1)
547 /* @brief Has external pin 5 connected to LLWU device. */
548 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
549 /* @brief Index of port of external pin. */
550 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
551 /* @brief Number of external pin port on specified port. */
552 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (2)
553 /* @brief Has external pin 6 connected to LLWU device. */
554 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
555 /* @brief Index of port of external pin. */
556 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOB_IDX)
557 /* @brief Number of external pin port on specified port. */
558 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (4)
559 /* @brief Has external pin 7 connected to LLWU device. */
560 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
561 /* @brief Index of port of external pin. */
562 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOB_IDX)
563 /* @brief Number of external pin port on specified port. */
564 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (6)
565 /* @brief Has external pin 8 connected to LLWU device. */
566 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
567 /* @brief Index of port of external pin. */
568 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
569 /* @brief Number of external pin port on specified port. */
570 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (7)
571 /* @brief Has external pin 9 connected to LLWU device. */
572 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
573 /* @brief Index of port of external pin. */
574 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX)
575 /* @brief Number of external pin port on specified port. */
576 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (8)
577 /* @brief Has external pin 10 connected to LLWU device. */
578 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
579 /* @brief Index of port of external pin. */
580 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX)
581 /* @brief Number of external pin port on specified port. */
582 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (16)
583 /* @brief Has external pin 11 connected to LLWU device. */
584 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
585 /* @brief Index of port of external pin. */
586 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX)
587 /* @brief Number of external pin port on specified port. */
588 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (20)
589 /* @brief Has external pin 12 connected to LLWU device. */
590 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
591 /* @brief Index of port of external pin. */
592 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX)
593 /* @brief Number of external pin port on specified port. */
594 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (22)
595 /* @brief Has external pin 13 connected to LLWU device. */
596 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
597 /* @brief Index of port of external pin. */
598 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX)
599 /* @brief Number of external pin port on specified port. */
600 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (25)
601 /* @brief Has external pin 14 connected to LLWU device. */
602 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
603 /* @brief Index of port of external pin. */
604 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX)
605 /* @brief Number of external pin port on specified port. */
606 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (28)
607 /* @brief Has external pin 15 connected to LLWU device. */
608 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
609 /* @brief Index of port of external pin. */
610 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
611 /* @brief Number of external pin port on specified port. */
612 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
613 /* @brief Has external pin 16 connected to LLWU device. */
614 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
615 /* @brief Index of port of external pin. */
616 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOC_IDX)
617 /* @brief Number of external pin port on specified port. */
618 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (9)
619 /* @brief Has external pin 17 connected to LLWU device. */
620 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
621 /* @brief Index of port of external pin. */
622 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOC_IDX)
623 /* @brief Number of external pin port on specified port. */
624 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (11)
625 /* @brief Has external pin 18 connected to LLWU device. */
626 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
627 /* @brief Index of port of external pin. */
628 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOC_IDX)
629 /* @brief Number of external pin port on specified port. */
630 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (12)
631 /* @brief Has external pin 19 connected to LLWU device. */
632 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1)
633 /* @brief Index of port of external pin. */
634 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOD_IDX)
635 /* @brief Number of external pin port on specified port. */
636 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (8)
637 /* @brief Has external pin 20 connected to LLWU device. */
638 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1)
639 /* @brief Index of port of external pin. */
640 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOD_IDX)
641 /* @brief Number of external pin port on specified port. */
642 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (10)
643 /* @brief Has external pin 21 connected to LLWU device. */
644 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
645 /* @brief Index of port of external pin. */
646 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
647 /* @brief Number of external pin port on specified port. */
648 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (1)
649 /* @brief Has external pin 22 connected to LLWU device. */
650 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
651 /* @brief Index of port of external pin. */
652 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOE_IDX)
653 /* @brief Number of external pin port on specified port. */
654 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (3)
655 /* @brief Has external pin 23 connected to LLWU device. */
656 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
657 /* @brief Index of port of external pin. */
658 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOE_IDX)
659 /* @brief Number of external pin port on specified port. */
660 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (8)
661 /* @brief Has external pin 24 connected to LLWU device. */
662 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
663 /* @brief Index of port of external pin. */
664 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOE_IDX)
665 /* @brief Number of external pin port on specified port. */
666 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (9)
667 /* @brief Has external pin 25 connected to LLWU device. */
668 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
669 /* @brief Index of port of external pin. */
670 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOE_IDX)
671 /* @brief Number of external pin port on specified port. */
672 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (10)
673 /* @brief Has external pin 26 connected to LLWU device. */
674 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (1)
675 /* @brief Index of port of external pin. */
676 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (GPIOE_IDX)
677 /* @brief Number of external pin port on specified port. */
678 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (12)
679 /* @brief Has external pin 27 connected to LLWU device. */
680 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
681 /* @brief Index of port of external pin. */
682 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
683 /* @brief Number of external pin port on specified port. */
684 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
685 /* @brief Has external pin 28 connected to LLWU device. */
686 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
687 /* @brief Index of port of external pin. */
688 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
689 /* @brief Number of external pin port on specified port. */
690 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
691 /* @brief Has external pin 29 connected to LLWU device. */
692 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
693 /* @brief Index of port of external pin. */
694 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
695 /* @brief Number of external pin port on specified port. */
696 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
697 /* @brief Has external pin 30 connected to LLWU device. */
698 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
699 /* @brief Index of port of external pin. */
700 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
701 /* @brief Number of external pin port on specified port. */
702 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
703 /* @brief Has external pin 31 connected to LLWU device. */
704 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
705 /* @brief Index of port of external pin. */
706 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
707 /* @brief Number of external pin port on specified port. */
708 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
709 /* @brief Has internal module 0 connected to LLWU device. */
710 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
711 /* @brief Has internal module 1 connected to LLWU device. */
712 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
713 /* @brief Has internal module 2 connected to LLWU device. */
714 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
715 /* @brief Has internal module 3 connected to LLWU device. */
716 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
717 /* @brief Has internal module 4 connected to LLWU device. */
718 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
719 /* @brief Has internal module 5 connected to LLWU device. */
720 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
721 /* @brief Has internal module 6 connected to LLWU device. */
722 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1)
723 /* @brief Has internal module 7 connected to LLWU device. */
724 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
725 /* @brief Has LLWU_VERID. */
726 #define FSL_FEATURE_LLWU_HAS_VERID (1)
727 /* @brief Has LLWU_PARAM. */
728 #define FSL_FEATURE_LLWU_HAS_PARAM (1)
729 /* @brief LLWU register bit width. */
730 #define FSL_FEATURE_LLWU_REG_BITWIDTH (32)
731 /* @brief Has DMA Enable register LLWU_DE. */
732 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (1)
733 
734 /* LPADC module features */
735 
736 /* @brief FIFO availability on the SoC. */
737 #define FSL_FEATURE_LPADC_FIFO_COUNT (1)
738 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
739 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
740 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */
741 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
742 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
743 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
744 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
745 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0)
746 /* @brief Has conversion resolution select  (bitfield CMDLn[MODE]). */
747 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0)
748 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
749 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
750 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
751 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0)
752 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
753 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0)
754 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
755 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0)
756 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
757 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0)
758 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */
759 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (1)
760 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
761 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (1)
762 /* @brief Has calibration (bitfield CFG[CALOFS]). */
763 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (1)
764 /* @brief Has offset trim (register OFSTRIM). */
765 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
766 /* @brief OFSTRIM availability on the SoC. */
767 #define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1)
768 /* @brief Has Trigger status register. */
769 #define FSL_FEATURE_LPADC_HAS_TSTAT (0)
770 /* @brief Has power select (bitfield CFG[PWRSEL]). */
771 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
772 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
773 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
774 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
775 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
776 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
777 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
778 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
779 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
780 /* @brief Conversion averaged bitfiled width. */
781 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
782 /* @brief Has B side channels. */
783 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1)
784 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */
785 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (0)
786 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */
787 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (0)
788 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */
789 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (0)
790 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */
791 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (0)
792 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */
793 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (0)
794 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */
795 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (0)
796 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */
797 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (0)
798 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */
799 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (0)
800 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */
801 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (0)
802 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
803 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (1)
804 
805 /* LPCMP module features */
806 
807 /* @brief Has CCR1 FUNC_CLK_SEL bitfield. */
808 #define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (0)
809 /* @brief Has IER RRF_IE bitfield. */
810 #define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (0)
811 /* @brief Has CSR RRF bitfield. */
812 #define FSL_FEATURE_LPCMP_HAS_CSR_RRF (0)
813 /* @brief Has Round Robin mode (related to existence of registers RRCR0). */
814 #define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (0)
815 /* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */
816 #define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (0)
817 /* @brief Has no CCR0 CMP_STOP_EN bitfield. */
818 #define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (0)
819 
820 /* LPDAC module features */
821 
822 /* @brief FIFO size. */
823 #define FSL_FEATURE_LPDAC_FIFO_SIZE (16)
824 
825 /* LPI2C module features */
826 
827 /* @brief Has separate DMA RX and TX requests. */
828 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
829 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
830 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
831 
832 /* LPIT module features */
833 
834 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
835 #define FSL_FEATURE_LPIT_TIMER_COUNT (4)
836 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
837 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0)
838 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
839 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1)
840 
841 /* LPSPI module features */
842 
843 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
844 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4)
845 /* @brief Has separate DMA RX and TX requests. */
846 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
847 /* @brief Has CCR1 (related to existence of registers CCR1). */
848 #define FSL_FEATURE_LPSPI_HAS_CCR1 (0)
849 /* @brief Has no PCSCFG bit in CFGR1 register */
850 #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0)
851 /* @brief Has no WIDTH bits in TCR register */
852 #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0)
853 
854 /* LPTMR module features */
855 
856 /* @brief Has shared interrupt handler with another LPTMR module. */
857 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
858 /* @brief Whether LPTMR counter is 32 bits width. */
859 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
860 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
861 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
862 /* @brief Do not has prescaler clock source 0. */
863 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0)
864 /* @brief Do not has prescaler clock source 1. */
865 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
866 /* @brief Do not has prescaler clock source 2. */
867 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0)
868 /* @brief Do not has prescaler clock source 3. */
869 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0)
870 
871 /* LPUART module features */
872 
873 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
874 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
875 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
876 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
877 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
878 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
879 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
880 #define FSL_FEATURE_LPUART_HAS_FIFO (1)
881 /* @brief Has 32-bit register MODIR */
882 #define FSL_FEATURE_LPUART_HAS_MODIR (1)
883 /* @brief Hardware flow control (RTS, CTS) is supported. */
884 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
885 /* @brief Infrared (modulation) is supported. */
886 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
887 /* @brief 2 bits long stop bit is available. */
888 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
889 /* @brief If 10-bit mode is supported. */
890 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
891 /* @brief If 7-bit mode is supported. */
892 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
893 /* @brief Baud rate fine adjustment is available. */
894 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
895 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
896 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
897 /* @brief Baud rate oversampling is available. */
898 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
899 /* @brief Baud rate oversampling is available. */
900 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
901 /* @brief Peripheral type. */
902 #define FSL_FEATURE_LPUART_IS_SCI (1)
903 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
904 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8)
905 /* @brief Supports two match addresses to filter incoming frames. */
906 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
907 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
908 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
909 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
910 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
911 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
912 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
913 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
914 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
915 /* @brief Has improved smart card (ISO7816 protocol) support. */
916 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
917 /* @brief Has local operation network (CEA709.1-B protocol) support. */
918 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
919 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
920 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
921 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
922 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
923 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
924 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
925 /* @brief Has separate DMA RX and TX requests. */
926 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
927 /* @brief Has separate RX and TX interrupts. */
928 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
929 /* @brief Has LPAURT_PARAM. */
930 #define FSL_FEATURE_LPUART_HAS_PARAM (1)
931 /* @brief Has LPUART_VERID. */
932 #define FSL_FEATURE_LPUART_HAS_VERID (1)
933 /* @brief Has LPUART_GLOBAL. */
934 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
935 /* @brief Has LPUART_PINCFG. */
936 #define FSL_FEATURE_LPUART_HAS_PINCFG (1)
937 /* @brief Has register MODEM Control. */
938 #define FSL_FEATURE_LPUART_HAS_MCR (0)
939 /* @brief Has register Half Duplex Control. */
940 #define FSL_FEATURE_LPUART_HAS_HDCR (0)
941 /* @brief Has register Timeout. */
942 #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0)
943 
944 /* MCM module features */
945 
946 /* @brief Has L1 cache. */
947 #define FSL_FEATURE_HAS_L1CACHE (1)
948 
949 /* MSCM module features */
950 
951 /* @brief Number of configuration information for processors. */
952 #define FSL_FEATURE_MSCM_HAS_CP_COUNT (2)
953 /* @brief Has data cache. */
954 #define FSL_FEATURE_MSCM_HAS_DATACACHE (0)
955 
956 /* MU module features */
957 
958 /* @brief MU side for current core */
959 #define FSL_FEATURE_MU_SIDE_B (1)
960 /* @brief MU Has register CCR */
961 #define FSL_FEATURE_MU_HAS_CCR (1)
962 /* @brief MU Has register SR[RS], BSR[ARS] */
963 #define FSL_FEATURE_MU_HAS_SR_RS (0)
964 /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
965 #define FSL_FEATURE_MU_HAS_RESET_INT (1)
966 /* @brief MU Has register SR[MURIP] */
967 #define FSL_FEATURE_MU_HAS_SR_MURIP (1)
968 /* @brief MU Has register SR[HRIP] */
969 #define FSL_FEATURE_MU_HAS_SR_HRIP (1)
970 /* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
971 #define FSL_FEATURE_MU_NO_CLKE (0)
972 /* @brief MU does not support NMI, CR[NMI]. */
973 #define FSL_FEATURE_MU_NO_NMI (0)
974 /* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
975 #define FSL_FEATURE_MU_NO_RSTH (0)
976 /* @brief MU does not supports MU reset, CR[MUR]. */
977 #define FSL_FEATURE_MU_NO_MUR (0)
978 /* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
979 #define FSL_FEATURE_MU_NO_HR (0)
980 /* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
981 #define FSL_FEATURE_MU_HAS_HRM (1)
982 /* @brief MU does not support check the other core power mode. SR[PM] or BSR[APM]. */
983 #define FSL_FEATURE_MU_NO_PM (0)
984 /* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */
985 #define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (1)
986 /* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */
987 #define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (1)
988 
989 /* PCC module features */
990 
991 /* @brief Has CLOCK GATE CONTROL bit (e.g PCC_CGC) */
992 #define FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL (1)
993 
994 /* PORT module features */
995 
996 /* @brief Has control lock (register bit PCR[LK]). */
997 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
998 /* @brief Has open drain control (register bit PCR[ODE]). */
999 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
1000 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
1001 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
1002 /* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */
1003 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
1004 /* @brief Has pull resistor selection available. */
1005 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
1006 /* @brief Has pull resistor enable (register bit PCR[PE]). */
1007 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
1008 /* @brief Has slew rate control (register bit PCR[SRE]). */
1009 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
1010 /* @brief Has passive filter (register bit field PCR[PFE]). */
1011 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
1012 /* @brief Has drive strength control (register bit PCR[DSE]). */
1013 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
1014 /* @brief Defines width of PCR[MUX] field. */
1015 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
1016 /* @brief Has dedicated interrupt vector. */
1017 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
1018 /* @brief Has independent interrupt control(register ICR). */
1019 #define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0)
1020 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
1021 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1)
1022 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
1023 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1)
1024 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
1025 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1)
1026 
1027 /* RTC module features */
1028 
1029 /* @brief Has wakeup pin. */
1030 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
1031 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
1032 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
1033 /* @brief Has low power features (registers MER, MCLR and MCHR). */
1034 #define FSL_FEATURE_RTC_HAS_MONOTONIC (1)
1035 /* @brief Has read/write access control (registers WAR and RAR). */
1036 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
1037 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
1038 #define FSL_FEATURE_RTC_HAS_SECURITY (1)
1039 /* @brief Has RTC_CLKIN available. */
1040 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
1041 /* @brief Has prescaler adjust for LPO. */
1042 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1)
1043 /* @brief Has Clock Pin Enable field. */
1044 #define FSL_FEATURE_RTC_HAS_CPE (1)
1045 /* @brief Has Timer Seconds Interrupt Configuration field. */
1046 #define FSL_FEATURE_RTC_HAS_TSIC (1)
1047 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
1048 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
1049 /* @brief Has Tamper Interrupt Register (register TIR). */
1050 #define FSL_FEATURE_RTC_HAS_TIR (1)
1051 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
1052 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (1)
1053 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
1054 #define FSL_FEATURE_RTC_HAS_TIR_SIE (1)
1055 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
1056 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (1)
1057 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
1058 #define FSL_FEATURE_RTC_HAS_SR_TIDF (1)
1059 /* @brief Has Tamper Detect Register (register TDR). */
1060 #define FSL_FEATURE_RTC_HAS_TDR (1)
1061 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
1062 #define FSL_FEATURE_RTC_HAS_TDR_TPF (1)
1063 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
1064 #define FSL_FEATURE_RTC_HAS_TDR_STF (1)
1065 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
1066 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (1)
1067 /* @brief Has Tamper Time Seconds Register (register TTSR). */
1068 #define FSL_FEATURE_RTC_HAS_TTSR (1)
1069 /* @brief Has Pin Configuration Register (register PCR). */
1070 #define FSL_FEATURE_RTC_HAS_PCR (1)
1071 /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */
1072 #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0)
1073 
1074 /* SCG module features */
1075 
1076 /* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */
1077 #define FSL_FEATURE_SCG_HAS_DIVPLAT (0)
1078 /* @brief Has bus clock divider SCG_CSR[DIVBUS]. */
1079 #define FSL_FEATURE_SCG_HAS_DIVBUS (1)
1080 /* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */
1081 #define FSL_FEATURE_SCG_HAS_DIVEXT (1)
1082 /* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */
1083 #define FSL_FEATURE_SCG_HAS_OSC_SCXP (0)
1084 /* @brief Has SOSCCSR[SOSCERCLKEN]. */
1085 #define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0)
1086 /* @brief Has OSC freq range SOSCCFG[RANGE]. */
1087 #define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0)
1088 /* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */
1089 #define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1)
1090 /* @brief Has SCG_SOSCDIV[SOSCDIV1]. */
1091 #define FSL_FEATURE_SCG_HAS_SOSCDIV1 (0)
1092 /* @brief Has SCG_SOSCDIV[SOSCDIV3]. */
1093 #define FSL_FEATURE_SCG_HAS_SOSCDIV3 (0)
1094 /* @brief Has SCG_SIRCDIV[SIRCDIV1]. */
1095 #define FSL_FEATURE_SCG_HAS_SIRCDIV1 (1)
1096 /* @brief Has SCG_SIRCDIV[SIRCDIV3]. */
1097 #define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1)
1098 /* @brief Has SCG_SIRCCSR[LPOPO]. */
1099 #define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0)
1100 /* @brief Has SCG_FIRCDIV[FIRCDIV1]. */
1101 #define FSL_FEATURE_SCG_HAS_FIRCDIV1 (1)
1102 /* @brief Has SCG_FIRCDIV[FIRCDIV3]. */
1103 #define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1)
1104 /* @brief Has SCG_FIRCCSR[FIRCLPEN]. */
1105 #define FSL_FEATURE_SCG_HAS_FIRCLPEN (1)
1106 /* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */
1107 #define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1)
1108 /* @brief Has SCG_SPLLDIV[SPLLDIV1]. */
1109 #define FSL_FEATURE_SCG_HAS_SPLLDIV1 (0)
1110 /* @brief Has SCG_SPLLDIV[SPLLDIV3]. */
1111 #define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0)
1112 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */
1113 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0)
1114 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */
1115 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0)
1116 /* @brief Has SCG_SPLLCFG[PLLS]. */
1117 #define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0)
1118 /* @brief Has SCG_SPLLCFG[BYPASS]. */
1119 #define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0)
1120 /* @brief Has SCG_SPLLCFG[PFDSEL]. */
1121 #define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0)
1122 /* @brief Has SCG_SPLLCSR[SPLLCM]. */
1123 #define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0)
1124 /* @brief Has SCG_LPFLLDIV[FLLDIV1]. */
1125 #define FSL_FEATURE_SCG_HAS_FLLDIV1 (1)
1126 /* @brief Has SCG_LPFLLDIV[FLLDIV3]. */
1127 #define FSL_FEATURE_SCG_HAS_FLLDIV3 (1)
1128 /* @brief Has low power FLL, SCG_LPFLLCSR. */
1129 #define FSL_FEATURE_SCG_HAS_LPFLL (1)
1130 /* @brief Has system PLL, SCG_SPLLCSR. */
1131 #define FSL_FEATURE_SCG_HAS_SPLL (0)
1132 /* @brief Has system PLL PFD, SCG_SPLLPFD. */
1133 #define FSL_FEATURE_SCG_HAS_SPLLPFD (0)
1134 /* @brief Has auxiliary PLL, SCG_APLLCSR. */
1135 #define FSL_FEATURE_SCG_HAS_APLL (0)
1136 /* @brief Has RTC OSC control, SCG_ROSCCSR. */
1137 #define FSL_FEATURE_SCG_HAS_ROSC (1)
1138 /* @brief Has RTC OSC clock source. */
1139 #define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1)
1140 /* @brief Has RTC OSC clock out select. */
1141 #define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1)
1142 /* @brief Has EXTERNAL clock out select. */
1143 #define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (1)
1144 /* @brief Has no System OSC configuration register, SCG_SOSCCFG. */
1145 #define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1)
1146 /* @brief Has no SCG_SOSCCSR[SOSCEN]. */
1147 #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (1)
1148 /* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */
1149 #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (1)
1150 /* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */
1151 #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (1)
1152 /* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */
1153 #define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (0)
1154 /* @brief Has FIRC trim source USB0 Start of Frame. */
1155 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0)
1156 /* @brief Has FIRC trim source USB1 Start of Frame. */
1157 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0)
1158 /* @brief Has FIRC trim source system OSC. */
1159 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (0)
1160 /* @brief Has FIRC trim source RTC OSC. */
1161 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1)
1162 
1163 /* SEMA42 module features */
1164 
1165 /* @brief Gate counts */
1166 #define FSL_FEATURE_SEMA42_GATE_COUNT (16)
1167 
1168 /* SIM module features */
1169 
1170 /* @brief Has USB FS divider. */
1171 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1172 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1173 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1174 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1175 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
1176 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1177 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1178 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1179 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0)
1180 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1181 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0)
1182 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1183 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
1184 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1185 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
1186 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1187 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1188 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1189 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1190 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1191 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1192 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1193 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1194 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1195 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1196 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1197 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1198 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1199 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
1200 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1201 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
1202 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1203 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1204 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1205 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1206 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1207 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
1208 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1209 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1210 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1211 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1212 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1213 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1214 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1215 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1216 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1217 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1218 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1219 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1220 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1221 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1222 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1223 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
1224 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1225 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
1226 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1227 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
1228 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1229 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
1230 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1231 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
1232 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1233 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
1234 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1235 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
1236 /* @brief Has FTM module(s) configuration. */
1237 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
1238 /* @brief Number of FTM modules. */
1239 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
1240 /* @brief Number of FTM triggers with selectable source. */
1241 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
1242 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1243 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
1244 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1245 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1246 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1247 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1248 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1249 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1250 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1251 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1252 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1253 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1254 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1255 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
1256 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1257 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
1258 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1259 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
1260 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1261 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1262 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1263 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1264 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1265 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1266 /* @brief Has TPM module(s) configuration. */
1267 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1268 /* @brief The highest TPM module index. */
1269 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1270 /* @brief Has TPM module with index 0. */
1271 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1272 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1273 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
1274 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1275 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1276 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1277 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1278 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1279 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
1280 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1281 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1282 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1283 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1284 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1285 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1286 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1287 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
1288 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1289 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
1290 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1291 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1292 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1293 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1294 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1295 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1296 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1297 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1298 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1299 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1300 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1301 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1302 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1303 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
1304 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1305 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1306 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1307 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1308 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1309 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1310 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1311 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1312 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1313 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1314 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1315 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1316 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1317 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1318 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1319 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1320 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1321 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
1322 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1323 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (0)
1324 /* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */
1325 #define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0)
1326 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
1327 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0)
1328 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
1329 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
1330 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
1331 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1332 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
1333 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1334 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1335 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
1336 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1337 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
1338 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1339 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1340 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1341 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
1342 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1343 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
1344 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1345 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1346 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1347 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
1348 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1349 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1350 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1351 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0)
1352 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1353 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0)
1354 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1355 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1356 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1357 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1358 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1359 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1360 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1361 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1362 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1363 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1364 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1365 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1366 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1367 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1368 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1369 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1370 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1371 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
1372 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1373 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1374 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1375 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1376 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1377 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1378 /* @brief Has device die ID (register bit field SDID[DIEID]). */
1379 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1380 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1381 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1382 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1383 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1384 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1385 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1386 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1387 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1388 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1389 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
1390 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1391 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1392 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1393 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1394 /* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */
1395 #define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (1)
1396 /* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */
1397 #define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (1)
1398 /* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */
1399 #define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (1)
1400 /* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */
1401 #define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (1)
1402 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1403 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0)
1404 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1405 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
1406 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1407 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1)
1408 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1409 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1410 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1411 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1412 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1413 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1414 /* @brief Has miscellanious control register (register MCR). */
1415 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1416 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
1417 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1418 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1419 #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1420 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1421 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1422 /* @brief Has MISCCTRL reg. */
1423 #define FSL_FEATURE_SIM_HAS_MISCCTRL (0)
1424 /* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */
1425 #define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0)
1426 /* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */
1427 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0)
1428 /* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */
1429 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0)
1430 /* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */
1431 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0)
1432 /* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */
1433 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0)
1434 /* @brief Has SECKEY0 reg. */
1435 #define FSL_FEATURE_SIM_HAS_SECKEY0 (0)
1436 /* @brief Has SECKEY bit (e.g SIM_SECKEY0). */
1437 #define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0)
1438 /* @brief Has SECKEY1 reg. */
1439 #define FSL_FEATURE_SIM_HAS_SECKEY1 (0)
1440 /* @brief Has SECKEY bit (e.g SIM_SECKEY1). */
1441 #define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0)
1442 /* @brief Has SECKEY2 reg. */
1443 #define FSL_FEATURE_SIM_HAS_SECKEY2 (0)
1444 /* @brief Has SECKEY bit (e.g SIM_SECKEY2). */
1445 #define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0)
1446 /* @brief Has SECKEY3 reg. */
1447 #define FSL_FEATURE_SIM_HAS_SECKEY3 (0)
1448 /* @brief Has SECKEY bit (e.g SIM_SECKEY3). */
1449 #define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0)
1450 /* @brief Has no SDID reg. */
1451 #define FSL_FEATURE_SIM_HAS_NO_SDID (0)
1452 /* @brief Has no UID reg. */
1453 #define FSL_FEATURE_SIM_HAS_NO_UID (0)
1454 /* @brief Has RFADDRL and RFADDRH registers. */
1455 #define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (0)
1456 /* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */
1457 #define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (1)
1458 /* @brief Has UIDH registers. */
1459 #define FSL_FEATURE_SIM_HAS_UIDH (1)
1460 /* @brief Has UIDM registers. */
1461 #define FSL_FEATURE_SIM_HAS_UIDM (1)
1462 
1463 /* SMC module features */
1464 
1465 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1466 #define FSL_FEATURE_SMC_HAS_PSTOPO (0)
1467 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1468 #define FSL_FEATURE_SMC_HAS_LPOPO (0)
1469 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1470 #define FSL_FEATURE_SMC_HAS_PORPO (0)
1471 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1472 #define FSL_FEATURE_SMC_HAS_LPWUI (0)
1473 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1474 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
1475 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1476 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
1477 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1478 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
1479 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1480 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
1481 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1482 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
1483 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1484 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
1485 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
1486 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
1487 /* @brief Has stop submode. */
1488 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
1489 /* @brief Has stop submode 0(VLLS0). */
1490 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1491 /* @brief Has stop submode 2(VLLS2). */
1492 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
1493 /* @brief Has SMC_PARAM. */
1494 #define FSL_FEATURE_SMC_HAS_PARAM (1)
1495 /* @brief Has SMC_VERID. */
1496 #define FSL_FEATURE_SMC_HAS_VERID (1)
1497 /* @brief Has SMC_CSRE. */
1498 #define FSL_FEATURE_SMC_HAS_CSRE (0)
1499 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
1500 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (0)
1501 /* @brief Has tamper reset (register bit SRS[TAMPER]). */
1502 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
1503 /* @brief Has security violation reset (register bit SRS[SECVIO]). */
1504 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
1505 /* @brief Has security violation reset (register bit SRS[VBAT]). */
1506 #define FSL_FEATURE_SMC_HAS_SRS_VBAT (0)
1507 /* @brief Has security violation reset (register bit SRS[CORE0]). */
1508 #define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1)
1509 /* @brief Has security violation reset (register bit SRS[CORE1]). */
1510 #define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1)
1511 /* @brief Has security violation reset (register bit SRIE[VBAT]). */
1512 #define FSL_FEATURE_SMC_HAS_SRIE_VBAT (0)
1513 /* @brief Has security violation reset (register bit SRIE[CORE0]). */
1514 #define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (1)
1515 /* @brief Has security violation reset (register bit SRIE[CORE1]). */
1516 #define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (1)
1517 /* @brief Width of SMC registers. */
1518 #define FSL_FEATURE_SMC_REG_WIDTH (32)
1519 
1520 /* SysTick module features */
1521 
1522 /* @brief Systick has external reference clock. */
1523 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
1524 /* @brief Systick external reference clock is core clock divided by this value. */
1525 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
1526 
1527 /* TPM module features */
1528 
1529 /* @brief Number of channels. */
1530 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
1531     (((x) == TPM0) ? (6) : \
1532     (((x) == TPM1) ? (2) : \
1533     (((x) == TPM2) ? (6) : \
1534     (((x) == TPM3) ? (2) : (-1)))))
1535 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
1536 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
1537 /* @brief Has TPM_PARAM. */
1538 #define FSL_FEATURE_TPM_HAS_PARAM (1)
1539 /* @brief Has TPM_VERID. */
1540 #define FSL_FEATURE_TPM_HAS_VERID (1)
1541 /* @brief Has TPM_GLOBAL. */
1542 #define FSL_FEATURE_TPM_HAS_GLOBAL (1)
1543 /* @brief Has TPM_TRIG. */
1544 #define FSL_FEATURE_TPM_HAS_TRIG (1)
1545 /* @brief Whether TRIG register has effect. */
1546 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \
1547     (((x) == TPM0) ? (1) : \
1548     (((x) == TPM1) ? (0) : \
1549     (((x) == TPM2) ? (1) : \
1550     (((x) == TPM3) ? (0) : (-1)))))
1551 /* @brief Has counter pause on trigger. */
1552 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
1553 /* @brief Has external trigger selection. */
1554 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
1555 /* @brief Has TPM_COMBINE register. */
1556 #define FSL_FEATURE_TPM_HAS_COMBINE (1)
1557 /* @brief Whether COMBINE register has effect. */
1558 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
1559 /* @brief Has TPM_POL. */
1560 #define FSL_FEATURE_TPM_HAS_POL (1)
1561 /* @brief Whether POL register has effect. */
1562 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \
1563     (((x) == TPM0) ? (1) : \
1564     (((x) == TPM1) ? (0) : \
1565     (((x) == TPM2) ? (1) : \
1566     (((x) == TPM3) ? (0) : (-1)))))
1567 /* @brief Has TPM_FILTER register. */
1568 #define FSL_FEATURE_TPM_HAS_FILTER (1)
1569 /* @brief Whether FILTER register has effect. */
1570 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
1571 /* @brief Has TPM_QDCTRL register. */
1572 #define FSL_FEATURE_TPM_HAS_QDCTRL (1)
1573 /* @brief Whether QDCTRL register has effect. */
1574 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
1575 /* @brief Has pause level select. */
1576 #define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (1)
1577 /* @brief Whether 32 bits counter has effect. */
1578 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0)
1579 
1580 /* TRGMUX module features */
1581 
1582 /* No feature definitions */
1583 
1584 /* TRNG module features */
1585 
1586 /* No feature definitions */
1587 
1588 /* USB module features */
1589 
1590 /* @brief KHCI module instance count */
1591 #define FSL_FEATURE_USB_KHCI_COUNT (1)
1592 /* @brief HOST mode enabled */
1593 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
1594 /* @brief OTG mode enabled */
1595 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
1596 /* @brief Size of the USB dedicated RAM */
1597 #define FSL_FEATURE_USB_KHCI_USB_RAM (2048)
1598 /* @brief Base address of the USB dedicated RAM */
1599 #define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1208025088)
1600 /* @brief Has KEEP_ALIVE_CTRL register */
1601 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1)
1602 /* @brief Mode control of the USB Keep Alive */
1603 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
1604 /* @brief Has the Dynamic SOF threshold compare support */
1605 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1)
1606 /* @brief Has the VBUS detect support */
1607 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1)
1608 /* @brief Has the IRC48M module clock support */
1609 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
1610 /* @brief Number of endpoints supported */
1611 #define FSL_FEATURE_USB_ENDPT_COUNT (16)
1612 /* @brief Has STALL_IL/OL_DIS registers */
1613 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1)
1614 /* @brief Has STALL_IH/OH_DIS registers */
1615 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1)
1616 
1617 /* USDHC module features */
1618 
1619 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
1620 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
1621 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
1622 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
1623 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
1624 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (0)
1625 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
1626 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (0)
1627 /* @brief USDHC has reset control */
1628 #define FSL_FEATURE_USDHC_HAS_RESET (0)
1629 /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
1630 #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0)
1631 /* @brief If USDHC instance support 8 bit width */
1632 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1)
1633 /* @brief If USDHC instance support HS400 mode */
1634 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0)
1635 /* @brief If USDHC instance support 1v8 signal */
1636 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1)
1637 /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */
1638 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1)
1639 /* @brief Has no VSELECT bit in VEND_SPEC register */
1640 #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0)
1641 /* @brief Has no VS18 bit in HOST_CTRL_CAP register */
1642 #define FSL_FEATURE_USDHC_HAS_NO_VS18 (0)
1643 
1644 /* VREF module features */
1645 
1646 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */
1647 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
1648 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
1649 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
1650 /* @brief If high/low buffer mode supported */
1651 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
1652 /* @brief Module has also low reference (registers VREFL/VREFH) */
1653 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
1654 /* @brief Has VREF_TRM4. */
1655 #define FSL_FEATURE_VREF_HAS_TRM4 (1)
1656 
1657 /* WDOG module features */
1658 
1659 /* @brief Watchdog is available. */
1660 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
1661 /* @brief WDOG_CNT can be 32-bit written. */
1662 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1)
1663 
1664 /* XRDC module features */
1665 
1666 /* @brief Does not have global valid (register bit CR[GVLD]). */
1667 #define FSL_FEATURE_XRDC_HAS_NO_CR_GVLD (1)
1668 /* @brief Has domain ID of faulted access (register bit FDID[FDID]). */
1669 #define FSL_FEATURE_XRDC_HAS_FDID (1)
1670 /* @brief Has special 4-state model option (register bit PID[SP4SM]). */
1671 #define FSL_FEATURE_XRDC_PID_SP4SM (1)
1672 /* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */
1673 #define FSL_FEATURE_XRDC_NO_MDA_LPID (1)
1674 /* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */
1675 #define FSL_FEATURE_XRDC_NO_MDA_LPE (1)
1676 /* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */
1677 #define FSL_FEATURE_XRDC_NO_PDAC_SE (1)
1678 /* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */
1679 #define FSL_FEATURE_XRDC_NO_PDAC_SNUM (1)
1680 /* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */
1681 #define FSL_FEATURE_XRDC_HAS_PDAC_EALO (1)
1682 /* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */
1683 #define FSL_FEATURE_XRDC_HAS_PDAC_EAL (1)
1684 /* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */
1685 #define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (1)
1686 /* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */
1687 #define FSL_FEATURE_XRDC_NO_MRGD_SE (1)
1688 /* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */
1689 #define FSL_FEATURE_XRDC_NO_MRGD_SNUM (1)
1690 /* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */
1691 #define FSL_FEATURE_XRDC_NO_MRGD_DXACP (1)
1692 /* @brief Does not have region size configuration (register bit MRGD_W2[SZ]). */
1693 #define FSL_FEATURE_XRDC_NO_MRGD_SZ (1)
1694 /* @brief Does not have subregion disable option (register bit MRGD_W2[SRD]). */
1695 #define FSL_FEATURE_XRDC_NO_MRGD_SRD (1)
1696 /* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */
1697 #define FSL_FEATURE_XRDC_HAS_MRGD_EALO (1)
1698 /* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */
1699 #define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (1)
1700 /* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */
1701 #define FSL_FEATURE_XRDC_HAS_MRGD_EAL (1)
1702 /* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */
1703 #define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (1)
1704 /* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */
1705 #define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (1)
1706 /* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */
1707 #define FSL_FEATURE_XRDC_HAS_MRGD_CR (1)
1708 /* @brief Has ASSSET lock option (register bit MRGD_W4[LKAS1]/[LKAS2]). */
1709 #define FSL_FEATURE_XRDC_HAS_MRGD_LKAS (1)
1710 /* @brief Has programmable access flags (register bit MRGD_W4[ACCSET1]/[ACCSET2]). */
1711 #define FSL_FEATURE_XRDC_HAS_MRGD_ACCSET (1)
1712 /* @brief Has lock option in MRGD_W4 register (register bit MRGD_W4[LK2]). */
1713 #define FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2 (1)
1714 /* @brief Has valid option in MRGD_W4 register (register bit MRGD_W4[VLD]). */
1715 #define FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD (1)
1716 /* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */
1717 #define FSL_FEATURE_XRDC_DOMAIN_COUNT (3)
1718 
1719 #endif /* _K32L3A60_cm0plus_FEATURES_H_ */
1720 
1721