1/*
2 * Copyright (c) 2018-2023 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *     http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "region_defs.h"
18
19LR_CODE BL2_CODE_START {
20    ER_CODE BL2_CODE_START BL2_CODE_SIZE {
21        *.o (RESET +First)
22        * (+RO)
23    }
24
25    /* eFlash driver code that gets copied from Flash to SRAM */
26    ER_CODE_SRAM BL2_CODE_SRAM_BASE {
27        *libflash_drivers* (+RO)
28    }
29
30    /* Base address of bootloader data area */
31    BL2_DATA_START S_DATA_START {
32    }
33
34#ifdef CODE_SHARING
35    /* The code sharing between bootloader and runtime firmware requires to
36     * share the global variables.
37     */
38    TFM_SHARED_SYMBOLS +0 ALIGN 32 SHARED_SYMBOL_AREA_SIZE {
39       *platform.* (+RW)
40       *(.rodata.memset_func)
41    }
42#endif
43
44    TFM_SHARED_DATA +0 ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE {
45    }
46
47    ER_DATA +0 {
48        * (+ZI +RW)
49    }
50
51    /* MSP */
52    ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE {
53    }
54
55    ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE {
56    }
57
58    /* This empty, zero long execution region is here to mark the limit address
59     * of the last execution region that is allocated in SRAM.
60     */
61    SRAM_WATERMARK +0 EMPTY 0x0 {
62    }
63
64    /* Make sure that the sections allocated in the SRAM does not exceed the
65     * size of the SRAM available.
66     */
67    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= BL2_DATA_START + BL2_DATA_SIZE)
68}
69