1 /*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file CanEXCEL_Ip_HwAccess.c
9 *
10 * @addtogroup CanEXCEL
11 * @{
12 */
13
14 #include "CanEXCEL_Ip_HwAccess.h"
15 /*==================================================================================================
16 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
17 ==================================================================================================*/
18
19 /*==================================================================================================
20 * LOCAL MACROS
21 ==================================================================================================*/
22 /* CAN FD extended data length DLC encoding */
23 #define FLEXCAN_IP_DLC_VALUE_12_BYTES 9U
24 #define FLEXCAN_IP_DLC_VALUE_16_BYTES 10U
25 #define FLEXCAN_IP_DLC_VALUE_20_BYTES 11U
26 #define FLEXCAN_IP_DLC_VALUE_24_BYTES 12U
27 #define FLEXCAN_IP_DLC_VALUE_32_BYTES 13U
28 #define FLEXCAN_IP_DLC_VALUE_48_BYTES 14U
29 #define FLEXCAN_IP_DLC_VALUE_64_BYTES 15U
30
31 /*==================================================================================================
32 * GLOBAL VARIABLES
33 ==================================================================================================*/
34 static volatile uint32 Canexcel_Ip_au32ImaskBuff[CANXL_GRP_CONTROL_INSTANCE_COUNT][CANXL_GRP_CONTROL_MSGIMASKARRAY_COUNT];
35 static volatile uint32 Canexcel_Ip_au32DescHostInt[CANXL_GRP_CONTROL_INSTANCE_COUNT];
36 static volatile uint8 Canexcel_Ip_au8RxFifoInt[CANXL_GRP_CONTROL_INSTANCE_COUNT];
37 /*FUNCTION**********************************************************************
38 *
39 * Function Name : CanXL_SetErrIntCmd
40 * Description : Enable the error interrupts.
41 * This function will enable Error interrupt.
42 *
43 *END**************************************************************************/
CanXL_SetErrIntCmd(CANXL_SIC_Type * base,canxl_int_type_t errType,boolean enable)44 void CanXL_SetErrIntCmd(CANXL_SIC_Type * base, canxl_int_type_t errType, boolean enable)
45 {
46 uint32 temp = (uint32)errType;
47 if (enable)
48 {
49 base->SYSIE |= temp;
50 }
51 else
52 {
53 base->SYSIE &= (~temp);
54 }
55 }
56 /*FUNCTION**********************************************************************
57 *
58 * Function Name: CAN_ComputeDLCValue
59 * Description : Computes the DLC field value, given a payload size (in bytes).
60 * This is compatible only for Classical CAN Format (FDF=0) and CAN FD Format (FDF=1
61 * and XLF=0), for CAN XL Format (FDF=1 and XLF=1) is size is DLC+1 value
62 *END**************************************************************************/
CAN_ComputeDLCValue(uint8 payloadSize)63 uint8 CAN_ComputeDLCValue(uint8 payloadSize)
64 {
65 uint32 ret = 0xFFU; /* 0, 1, 2, 3, 4, 5, 6, 7, 8, */
66 static const uint8 payload_code[65] = {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
67 /* 9 to 12 payload have DLC Code 12 Bytes */
68 FLEXCAN_IP_DLC_VALUE_12_BYTES, FLEXCAN_IP_DLC_VALUE_12_BYTES, FLEXCAN_IP_DLC_VALUE_12_BYTES, FLEXCAN_IP_DLC_VALUE_12_BYTES,
69 /* 13 to 16 payload have DLC Code 16 Bytes */
70 FLEXCAN_IP_DLC_VALUE_16_BYTES, FLEXCAN_IP_DLC_VALUE_16_BYTES, FLEXCAN_IP_DLC_VALUE_16_BYTES, FLEXCAN_IP_DLC_VALUE_16_BYTES,
71 /* 17 to 20 payload have DLC Code 20 Bytes */
72 FLEXCAN_IP_DLC_VALUE_20_BYTES, FLEXCAN_IP_DLC_VALUE_20_BYTES, FLEXCAN_IP_DLC_VALUE_20_BYTES, FLEXCAN_IP_DLC_VALUE_20_BYTES,
73 /* 21 to 24 payload have DLC Code 24 Bytes */
74 FLEXCAN_IP_DLC_VALUE_24_BYTES, FLEXCAN_IP_DLC_VALUE_24_BYTES, FLEXCAN_IP_DLC_VALUE_24_BYTES, FLEXCAN_IP_DLC_VALUE_24_BYTES,
75 /* 25 to 32 payload have DLC Code 32 Bytes */
76 FLEXCAN_IP_DLC_VALUE_32_BYTES, FLEXCAN_IP_DLC_VALUE_32_BYTES, FLEXCAN_IP_DLC_VALUE_32_BYTES, FLEXCAN_IP_DLC_VALUE_32_BYTES,
77 FLEXCAN_IP_DLC_VALUE_32_BYTES, FLEXCAN_IP_DLC_VALUE_32_BYTES, FLEXCAN_IP_DLC_VALUE_32_BYTES, FLEXCAN_IP_DLC_VALUE_32_BYTES,
78 /* 33 to 48 payload have DLC Code 48 Bytes */
79 FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES,
80 FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES,
81 FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES,
82 FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES, FLEXCAN_IP_DLC_VALUE_48_BYTES,
83 /* 49 to 64 payload have DLC Code 64 Bytes */
84 FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES,
85 FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES,
86 FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES,
87 FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES, FLEXCAN_IP_DLC_VALUE_64_BYTES
88 };
89
90 if (payloadSize <= 64U)
91 {
92 ret = payload_code[payloadSize];
93 }
94 else
95 {
96 /* The argument is not a valid payload size will return 0xFF*/
97 }
98 return (uint8)ret;
99 }
100
CanXL_SetDLCValue(CANXL_SIC_Type * base,uint16 payloadSize)101 uint16 CanXL_SetDLCValue(CANXL_SIC_Type * base, uint16 payloadSize)
102 {
103 if(CANXL_SIC_BCFG2_XLEN_MASK == (base->BCFG1 & CANXL_SIC_BCFG2_XLEN_MASK))
104 {
105 return (payloadSize-1);
106 }
107 else
108 {
109 return CAN_ComputeDLCValue(payloadSize);
110 }
111 }
112
CAN_ComputePayloadSize(uint8 dlcValue)113 static uint8 CAN_ComputePayloadSize(uint8 dlcValue)
114 {
115 uint8 ret = 8U;
116
117 if (dlcValue <= 8U)
118 {
119 ret = dlcValue;
120 }
121 else
122 {
123 switch (dlcValue)
124 {
125 case FLEXCAN_IP_DLC_VALUE_12_BYTES:
126 ret = 12U;
127 break;
128 case FLEXCAN_IP_DLC_VALUE_16_BYTES:
129 ret = 16U;
130 break;
131 case FLEXCAN_IP_DLC_VALUE_20_BYTES:
132 ret = 20U;
133 break;
134 case FLEXCAN_IP_DLC_VALUE_24_BYTES:
135 ret = 24U;
136 break;
137 case FLEXCAN_IP_DLC_VALUE_32_BYTES:
138 ret = 32U;
139 break;
140 case FLEXCAN_IP_DLC_VALUE_48_BYTES:
141 ret = 48U;
142 break;
143 case FLEXCAN_IP_DLC_VALUE_64_BYTES:
144 ret = 64U;
145 break;
146 default:
147 /* The argument is not a valid DLC size */
148 break;
149 }
150 }
151 return ret;
152 }
153
CanXL_SoftReset(CANXL_SIC_Type * base)154 Canexcel_Ip_StatusType CanXL_SoftReset(CANXL_SIC_Type * base)
155 {
156 uint32 timeStart = 0U;
157 uint32 timeElapsed = 0U;
158 Canexcel_Ip_StatusType returnResult = CANEXCEL_STATUS_SUCCESS;
159 uint32 uS2Ticks = OsIf_MicrosToTicks(CANEXCEL_IP_TIMEOUT_DURATION, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
160 base->SYSMC = CANXL_SIC_SYSMC_SOFRST_MASK;
161 while ((base->SYSMC & CANXL_SIC_SYSMC_SOFRST_MASK) == CANXL_SIC_SYSMC_SOFRST_MASK)
162 {
163 timeElapsed += OsIf_GetElapsed(&timeStart, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
164 if (timeElapsed >= uS2Ticks)
165 {
166 returnResult = CANEXCEL_STATUS_TIMEOUT;
167 break;
168 }
169 }
170 return returnResult;
171 }
172
173 /*FUNCTION**********************************************************************
174 *
175 * Function Name : CanXL_ClearRAM
176 * Description : Clears CANEXCEL memory positions that require initialization.
177 *
178 *END**************************************************************************/
CanXL_ClearRAM(CANEXCEL_StructType * CANXL,uint8 instance)179 void CanXL_ClearRAM(CANEXCEL_StructType * CANXL, uint8 instance)
180 {
181 uint16 idx;
182 CANXL_MSG_DESCRIPTORS_Type * base_Msg_Desc = CANXL->EXL_MSGD[instance];
183 for(idx=0u; idx < CANXL_MSG_DESCRIPTORS_MSGDSC_COUNT; idx++)
184 {
185 base_Msg_Desc->MSGDSC[idx].CTRL.RXCTRL = 0U;
186 base_Msg_Desc->MSGDSC[idx].CFG1.MDFLT1FD = 0U;
187 base_Msg_Desc->MSGDSC[idx].CFG2.MDFLT2FD = 0U;
188 base_Msg_Desc->MSGDSC[idx].LSTPNT.RXLSTPTR = 0U;
189 for(uint8 i=0;i<16u;i++)
190 {
191 /* Initialize the msg descriptor reserved space */
192 base_Msg_Desc->MSGDSC[idx].RESERVED_0[i] = 0U;
193 }
194 }
195 /* Clear the filter bank check the size in device reg as FILTER_BANK_SIZE */
196 uint32 * ptr = (uint32 *)&CANXL->EXL_FILTER[instance]->AFCFG0;
197 for(idx = 0u; idx <= FILTER_BANK_SIZE/4; idx++ )
198 {
199 * ptr = 0U;
200 ptr++;
201 }
202 /* Clear and initilize RXFIFO memory */
203 CANXL_RXFIFO_Type * base_RxFifo = CANXL->EXL_RXFIFO[instance];
204 base_RxFifo->RXFFCTR = 0U;
205 for(idx = 0u; idx < CANXL_RXFIFO_RXFFPOINTERAR_COUNT; idx++)
206 {
207 base_RxFifo->RXFMBP[idx] = 0U;
208 }
209 base_RxFifo->SECAM = 0U;
210 base_RxFifo->SECAV = 0U;
211 base_RxFifo->AFCFG = 0U;
212 base_RxFifo->VAMRCFG = 0U;
213 base_RxFifo->SAMRCFG = 0U;
214 base_RxFifo->AAMRCFG = 0U;
215 base_RxFifo->ACPTIDMR = 0U;
216 for(idx = 0u; idx < CANXL_RXFIFO_VCANACPTFLTAR_COUNT; idx++)
217 {
218 base_RxFifo->VAFLT[idx] = 0U;
219 }
220 for(idx = 0u; idx < CANXL_RXFIFO_SDUACPTFLTAR_COUNT; idx++)
221 {
222 base_RxFifo->SAFLT[idx] = 0U;
223 }
224 for(idx = 0u; idx < CANXL_RXFIFO_ADDRACPTFLTAR_COUNT; idx++)
225 {
226 base_RxFifo->ADDRACPTFLTAR[idx].AAFLTL = 0U;
227 base_RxFifo->ADDRACPTFLTAR[idx].AAFLTH = 0U;
228 }
229 for(idx = 0u; idx < CANXL_RXFIFO_IDACPTFLTAR_COUNT; idx++)
230 {
231 base_RxFifo->IDACPTFLTAR[idx].IDAFLTL = 0U;
232 base_RxFifo->IDACPTFLTAR[idx].IDAFLTH = 0U;
233 }
234 }
235
236 /*FUNCTION**********************************************************************
237 *
238 * Function Name : CANXL_EnterFreezeMode
239 * Description : Enter the freeze mode.
240 *
241 *END**************************************************************************/
CanXL_EnterFreezeMode(CANXL_SIC_Type * base)242 Canexcel_Ip_StatusType CanXL_EnterFreezeMode(CANXL_SIC_Type * base)
243 {
244 uint32 timeStart = 0U;
245 uint32 timeElapsed = 0U;
246 uint32 uS2Ticks = OsIf_MicrosToTicks(CANEXCEL_IP_TIMEOUT_DURATION, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
247 Canexcel_Ip_StatusType returnResult = CANEXCEL_STATUS_SUCCESS;
248 boolean lowPower = FALSE;
249
250 /* Start critical section: implementation depends on integrator */
251 if(((base->SYSS & CANXL_SIC_SYSS_FRZACKF_MASK) == CANXL_SIC_SYSS_FRZACKF_MASK) && ((base->SYSMC & CANXL_SIC_SYSMC_FRZREQ_MASK) == 0U))
252 {
253 if((base->SYSS & CANXL_SIC_SYSS_LPMACKF_MASK) && ((base->SYSMC & CANXL_SIC_SYSMC_LPMREQ_MASK) == CANXL_SIC_SYSMC_LPMREQ_MASK))
254 {
255 lowPower = TRUE;
256 /* Exit low Power Mode to allow Freeze Enter Mode */
257 base->SYSS |= CANXL_SIC_SYSS_LPMACKF_MASK;
258 base->SYSMC &= ~CANXL_SIC_SYSMC_LPMREQ_MASK;
259 timeStart = OsIf_GetCounter(CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
260 while(0U == (base->SYSS & CANXL_SIC_SYSS_LPMACKF_MASK))
261 {
262 timeElapsed += OsIf_GetElapsed(&timeStart, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
263 if (timeElapsed >= uS2Ticks)
264 {
265 returnResult = CANEXCEL_STATUS_TIMEOUT;
266 break;
267 }
268 }
269 }
270 /* Request Freeze Enter Mode */
271 base->SYSS |= CANXL_SIC_SYSS_FRZACKF_MASK;
272 base->SYSMC |= CANXL_SIC_SYSMC_FRZREQ_MASK;
273 }
274 if(CANEXCEL_STATUS_SUCCESS == returnResult)
275 {
276 timeStart = OsIf_GetCounter(CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
277 while (0U == (base->SYSS & CANXL_SIC_SYSS_FRZACKF_MASK))
278 {
279 timeElapsed += OsIf_GetElapsed(&timeStart, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
280 if (timeElapsed >= uS2Ticks)
281 {
282 returnResult = CANEXCEL_STATUS_TIMEOUT;
283 break;
284 }
285 }
286 }
287
288 if((CANEXCEL_STATUS_SUCCESS == returnResult) && TRUE == lowPower)
289 {
290 base->SYSS = CANXL_SIC_SYSS_LPMACKF_MASK;
291 base->SYSMC |= CANXL_SIC_SYSMC_LPMREQ_MASK;
292 timeStart = OsIf_GetCounter(CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
293 while(0U == (base->SYSS & CANXL_SIC_SYSS_LPMACKF_MASK))
294 {
295 timeElapsed += OsIf_GetElapsed(&timeStart, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
296 if (timeElapsed >= uS2Ticks)
297 {
298 returnResult = CANEXCEL_STATUS_TIMEOUT;
299 break;
300 }
301 }
302 }
303 return returnResult;
304 }
305
306 /*FUNCTION**********************************************************************
307 *
308 * Function Name : CANXL_ExitFreezeMode
309 * Description : Exit the freeze mode.
310 *
311 *END**************************************************************************/
CanXL_ExitFreezeMode(CANXL_SIC_Type * base)312 Canexcel_Ip_StatusType CanXL_ExitFreezeMode(CANXL_SIC_Type * base)
313 {
314 uint32 timeStart = 0U;
315 uint32 timeElapsed = 0U;
316 uint32 uS2Ticks = OsIf_MicrosToTicks(CANEXCEL_IP_TIMEOUT_DURATION, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
317 Canexcel_Ip_StatusType returnResult = CANEXCEL_STATUS_SUCCESS;
318 boolean lowPower = FALSE;
319 if((base->SYSS & CANXL_SIC_SYSS_FRZACKF_MASK) != 0U)
320 {
321 if(base->SYSS & CANXL_SIC_SYSS_LPMACKF_MASK)
322 {
323 lowPower = TRUE;
324 base->SYSS = CANXL_SIC_SYSS_LPMACKF_MASK;
325 /* Exit low Power Mode to allow Freeze Exit Mode */
326 base->SYSMC &= ~CANXL_SIC_SYSMC_LPMREQ_MASK;
327 timeStart = OsIf_GetCounter(CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
328 while(0U == (base->SYSS & CANXL_SIC_SYSS_LPMACKF_MASK))
329 {
330 timeElapsed += OsIf_GetElapsed(&timeStart, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
331 if (timeElapsed >= uS2Ticks)
332 {
333 returnResult = CANEXCEL_STATUS_TIMEOUT;
334 break;
335 }
336 }
337 }
338 }
339 if(CANEXCEL_STATUS_SUCCESS == returnResult)
340 {
341 base->SYSS = CANXL_SIC_SYSS_FRZACKF_MASK;
342 /* Request exit Freeze Mode */
343 base->SYSMC &= ~CANXL_SIC_SYSMC_FRZREQ_MASK;
344 timeStart = OsIf_GetCounter(CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
345 while (0U == (base->SYSS & CANXL_SIC_SYSS_FRZACKF_MASK))
346 {
347 timeElapsed += OsIf_GetElapsed(&timeStart, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
348 if (timeElapsed >= uS2Ticks)
349 {
350 returnResult = CANEXCEL_STATUS_TIMEOUT;
351 break;
352 }
353 }
354 }
355 if((CANEXCEL_STATUS_SUCCESS == returnResult) && (TRUE == lowPower))
356 {
357 base->SYSS = CANXL_SIC_SYSS_LPMACKF_MASK;
358 base->SYSMC |= CANXL_SIC_SYSMC_LPMREQ_MASK;
359 while(0U == (base->SYSS & CANXL_SIC_SYSS_LPMACKF_MASK))
360 {
361 timeElapsed += OsIf_GetElapsed(&timeStart, CANEXCEL_IP_SERVICE_TIMEOUT_TYPE);
362 if (timeElapsed >= uS2Ticks)
363 {
364 returnResult = CANEXCEL_STATUS_TIMEOUT;
365 break;
366 }
367 }
368 }
369 return returnResult;
370 }
371
CanXL_GetDescControlStatus(CANXL_DSC_CONTROL_Type * base,uint8 descNo)372 Canexcel_Ip_DesCntStatus CanXL_GetDescControlStatus(CANXL_DSC_CONTROL_Type * base, uint8 descNo)
373 {
374 switch((base->DSCMBCTRLAR[descNo].STA.DCSTA & (CANXL_DSC_CONTROL_DCSTA_HWLOCK_MASK | CANXL_DSC_CONTROL_DCSTA_SYSLOCK_MASK))>>CANXL_DSC_CONTROL_DCSTA_HWLOCK_SHIFT)
375 {
376 case 0U:
377 return CANEXCEL_DESCNTSTATUS_UNLOCKED;
378 case 1U:
379 return CANEXCEL_DESCNTSTATUS_LOCKED_HW;
380 case 2U:
381 return CANEXCEL_DESCNTSTATUS_LOCKED_SYS;
382 case 3:
383 return CANEXCEL_DESCNTSTATUS_INVALID;
384 default:
385 return CANEXCEL_DESCNTSTATUS_INVALID;
386 }
387 }
388
389 /*FUNCTION**********************************************************************
390 *
391 * Function Name : CanXL_SetOperationMode
392 * Description : Enable a FlexCAN operation mode.
393 * This function will enable one of the modes listed in flexcan_operation_modes_t.
394 *
395 *END**************************************************************************/
CanXL_SetOperationMode(CANXL_SIC_Type * base,Canexcel_Ip_ModesType mode)396 void CanXL_SetOperationMode(CANXL_SIC_Type * base, Canexcel_Ip_ModesType mode)
397 {
398 switch (mode)
399 {
400 case CANEXCEL_NORMAL_MODE:
401 base->BCFG2 = (base->BCFG2 & ~CANXL_SIC_BCFG2_LOM_MASK) | CANXL_SIC_BCFG2_LOM(0U);
402 base->BCFG2 = (base->BCFG2 & ~CANXL_SIC_BCFG2_LPB_MASK) | CANXL_SIC_BCFG2_LPB(0U);
403 break;
404 case CANEXCEL_LISTEN_ONLY_MODE:
405 base->BCFG2 = (base->BCFG2 & ~CANXL_SIC_BCFG2_LOM_MASK) | CANXL_SIC_BCFG2_LOM(1U);;
406 break;
407 case CANEXCEL_LOOPBACK_MODE:
408 base->BCFG2 = (base->BCFG2 & ~CANXL_SIC_BCFG2_LPB_MASK) | CANXL_SIC_BCFG2_LPB(1U);
409 base->BCFG2 = (base->BCFG2 & ~CANXL_SIC_BCFG2_LOM_MASK) | CANXL_SIC_BCFG2_LOM(0U);
410 base->BCFG2 = (base->BCFG2 & ~CANXL_SIC_BCFG2_TMSE_MASK);
411 /* Enable Self Reception */
412 CanXL_SetSelfReception(base, TRUE);
413 break;
414 default:
415 /* Should not get here */
416 break;
417 }
418 }
419
420
CanXL_SetTxMsgBuffData(const Canexcel_Ip_DataInfoType * info,const uint8 * data,uint8 * MB)421 void CanXL_SetTxMsgBuffData(const Canexcel_Ip_DataInfoType * info, const uint8 * data, uint8 * MB)
422 {
423 volatile uint32 * Mb_Data_32 = (volatile uint32 *)MB;
424 const uint32 * MsgData_32 = (const uint32*)data;
425 uint16 idx;
426 for(idx = 0u; idx< (info->dataLength & ~3U); idx +=4u )
427 {
428 * Mb_Data_32 = * MsgData_32;
429 Mb_Data_32++;
430 MsgData_32++;
431 }
432 for ( ; idx < info->dataLength; idx++)
433 {
434 MB[idx] = data[idx];
435 }
436
437 if(info->frame == CANEXCEL_FD_FRAME)
438 {
439 uint8 dlcValue = CAN_ComputeDLCValue(info->dataLength);
440 uint8 calcValue = CAN_ComputePayloadSize(dlcValue);
441 for(idx = info->dataLength; idx<calcValue; idx++)
442 {
443 MB[idx] = info->fd_padding;
444 }
445 }
446 }
447
CanXL_ConfigInterrupts(uint8 Instance)448 void CanXL_ConfigInterrupts(uint8 Instance)
449 {
450 Canexcel_Ip_au32DescHostInt[Instance] = CANXL_SIC_SYSMDHICFG_TXDCFGHI0_0_MASK | CANXL_SIC_SYSMDHICFG_TXDCFGHI0_1_MASK | CANXL_SIC_SYSMDHICFG_TXDCFGHI0_2_MASK | CANXL_SIC_SYSMDHICFG_TXDCFGHI0_3_MASK |
451 CANXL_SIC_SYSMDHICFG_RXDCFGHI0_0_MASK | CANXL_SIC_SYSMDHICFG_RXDCFGHI0_1_MASK | CANXL_SIC_SYSMDHICFG_RXDCFGHI0_2_MASK | CANXL_SIC_SYSMDHICFG_RXDCFGHI0_3_MASK;
452 }
453
CanXL_EnableInterrupts(CANXL_SIC_Type * base,uint8 Instance)454 void CanXL_EnableInterrupts(CANXL_SIC_Type * base, uint8 Instance)
455 {
456 base->SYSMDHICFG = Canexcel_Ip_au32DescHostInt[Instance];
457 /*uint8 ImaskCnt = 0U;
458 for (ImaskCnt = 0U; ImaskCnt < CANXL_GRP_CONTROL_MSGIMASKARRAY_COUNT; ImaskCnt++)
459 {
460 base->MSGIMASK[ImaskCnt] = Canexcel_Ip_au32ImaskBuff[Instance][ImaskCnt];
461 }*/
462 }
463
CanXL_DisableInterrupts(CANXL_SIC_Type * base,uint8 Instance)464 void CanXL_DisableInterrupts(CANXL_SIC_Type * base, uint8 Instance)
465 {
466 Canexcel_Ip_au32DescHostInt[Instance] = base->SYSMDHICFG;
467 base->SYSMDHICFG = 0U;
468 /*uint8 ImaskCnt = 0U;
469 for (ImaskCnt = 0U; ImaskCnt < GRP_CONTROL_MSGIMASKARRAY_COUNT; ImaskCnt++)
470 {
471 base->MSGIMASK[ImaskCnt] = 0U;
472 }*/
473 }
474 /*FUNCTION**********************************************************************
475 *
476 * Function Name : CanXL_ResetImaskBuff (uses in Canexcel_Ip_Init function only)
477 * Description : Reset Imask Buffers.
478 *
479 *END**************************************************************************/
CanXL_ResetImaskBuff(CANXL_GRP_CONTROL_Type * base,uint8 Instance)480 void CanXL_ResetImaskBuff(CANXL_GRP_CONTROL_Type * base,uint8 Instance)
481 {
482 uint8 ImaskCnt = 0U;
483 for (ImaskCnt = 0U; ImaskCnt < CANXL_GRP_CONTROL_MSGIMASKARRAY_COUNT; ImaskCnt++)
484 {
485 base->MSGIMASK[ImaskCnt] = 0U;
486 }
487 }
488
489 /*FUNCTION**********************************************************************
490 *
491 * Function Name : CanXL_ConfigCtrlOptions
492 * Description : configure controller depending on options
493 * note: Protocol exception should not be enabled with XL frame support.
494 *
495 *END**************************************************************************/
CanXL_ConfigCtrlOptions(CANXL_SIC_Type * base,uint32 u32Options)496 Canexcel_Ip_StatusType CanXL_ConfigCtrlOptions(CANXL_SIC_Type * base, uint32 u32Options)
497 {
498 Canexcel_Ip_StatusType status = CANEXCEL_STATUS_SUCCESS;
499 if ((base->BCFG2 & CANXL_SIC_BCFG2_XLEN_MASK) && ((u32Options & CANXL_IP_PROTOCOL_EXCEPTION_U32) != 0U))
500 {
501 status = CANEXCEL_STATUS_ERROR;
502 }
503 else
504 {
505 /* Set protocol Exception, PEXCE must be cleared when BCFG2[XLEN] is set. */
506 if ((u32Options & CANXL_IP_PROTOCOL_EXCEPTION_U32) != 0U)
507 {
508 /* 1b - Protocol exception feature enabled */
509 base->BCFG2 |= CANXL_SIC_BCFG2_PEXCE_MASK;
510 }
511 else
512 {
513 /* 0b - Protocol exception feature disabled */
514 base->BCFG2 &= (~CANXL_SIC_BCFG2_PEXCE_MASK);
515 }
516 }
517 if ((u32Options & CANXL_IP_ROM_U32) != 0U)
518 {
519 base->BCFG2 |= CANXL_SIC_BCFG2_ROM_MASK;
520 }
521 else
522 {
523 base->BCFG2 &= (~CANXL_SIC_BCFG2_ROM_MASK);
524 }
525 if ((u32Options & CANXL_IP_TX_ERROR_RESPONSE_U32) != 0U)
526 {
527 base->BCFG2 |= CANXL_SIC_BCFG2_TFER_MASK;
528 }
529 else
530 {
531 base->BCFG2 &= (~CANXL_SIC_BCFG2_TFER_MASK);
532 }
533 if ((u32Options & CANXL_IP_BUSOFF_RECOVERY_U32) != 0U)
534 {
535 /* 0b - Automatic bus-off recovery is enabled */
536 base->BCFG1 &= (~CANXL_SIC_BCFG1_ABRDIS_MASK);
537 }
538 else
539 {
540 /* 1b - Automatic bus-off recovery is disabled */
541 base->BCFG1 |= CANXL_SIC_BCFG1_ABRDIS_MASK;
542 }
543 if ((u32Options & CANXL_IP_EDGE_FILTER_U32) != 0U)
544 {
545 /* 0b - Edge Filter is enabled */
546 base->BCFG1 &= (~CANXL_SIC_BCFG1_ABRDIS_MASK);
547 }
548 else
549 {
550 /* 1b - Edge Filter is disabled */
551 base->BCFG1 |= CANXL_SIC_BCFG1_ABRDIS_MASK;
552 }
553 return status;
554 }
555
CanXL_ConfigAccAddr(CANXL_RXFIFO_Type * base,Canexcel_Ip_RxFifoFilterID_ADDR * filter,uint8 filtIdx)556 void CanXL_ConfigAccAddr(CANXL_RXFIFO_Type * base, Canexcel_Ip_RxFifoFilterID_ADDR * filter, uint8 filtIdx)
557 {
558 uint32 mask = 1UL << filtIdx%32U;
559 if(filter->filterType == CANEXCEL_IP_RX_FIFO_RANGE_FILTER)
560 {
561 /* Enable Range Filter operation */
562 base->AAMRCFG |= mask;
563 }
564 else
565 { /* Enable Mask Filter operation */
566 base->AAMRCFG &= (~mask);
567 }
568 base->ADDRACPTFLTAR[filtIdx].AAFLTH = filter->idAddrFilterH;
569 base->ADDRACPTFLTAR[filtIdx].AAFLTL = filter->idAddrFilterL;
570 }
571
CanXL_ConfigIDFilter(CANXL_RXFIFO_Type * base,Canexcel_Ip_RxFifoFilterID_ADDR * filter,uint8 filtIdx)572 void CanXL_ConfigIDFilter(CANXL_RXFIFO_Type * base, Canexcel_Ip_RxFifoFilterID_ADDR * filter, uint8 filtIdx)
573 {
574 uint32 mask = 1UL << filtIdx%32U;
575 if(filter->filterType == CANEXCEL_IP_RX_FIFO_RANGE_FILTER)
576 {
577 /* Enable Range Filter operation */
578 base->ACPTIDMR |= mask;
579 }
580 else
581 { /* Enable Mask Filter operation */
582 base->ACPTIDMR &= (~mask);
583 }
584 base->IDACPTFLTAR[filtIdx].IDAFLTH = filter->idAddrFilterH;
585 base->IDACPTFLTAR[filtIdx].IDAFLTL = filter->idAddrFilterL;
586 }
587
CanXL_ConfigSDUFilter(CANXL_RXFIFO_Type * base,Canexcel_Ip_RxFifoFilterSDU_CAN * filter,uint8 filtIdx)588 void CanXL_ConfigSDUFilter(CANXL_RXFIFO_Type * base, Canexcel_Ip_RxFifoFilterSDU_CAN * filter, uint8 filtIdx)
589 {
590 uint32 mask = 1UL << filtIdx%32U;
591 if(filter->filterType == CANEXCEL_IP_RX_FIFO_RANGE_FILTER)
592 {
593 /* Enable Range Filter operation */
594 base->SAMRCFG |= mask;
595 }
596 else
597 { /* Enable Mask Filter operation */
598 base->SAMRCFG &= (~mask);
599 }
600 /* Div the register selection to 2, this register is composed form a pair of SDU filter */
601 base->SAFLT[filtIdx>>2U] = 0U;
602 if(filtIdx % 2 == 0U)
603 {
604 base->SAFLT[filtIdx>>2U] |= CANXL_RXFIFO_SAFLT_SDUa_H(filter->sduVcanFilterH) | CANXL_RXFIFO_SAFLT_SDUa_L(filter->sduVcanFilterL);
605 }
606 else
607 {
608 base->SAFLT[filtIdx>>2U] |= CANXL_RXFIFO_SAFLT_SDUb_H(filter->sduVcanFilterH) | CANXL_RXFIFO_SAFLT_SDUb_L(filter->sduVcanFilterL);
609 }
610 }
611
CanXL_ConfigVCANFilter(CANXL_RXFIFO_Type * base,Canexcel_Ip_RxFifoFilterSDU_CAN * filter,uint8 filtIdx)612 void CanXL_ConfigVCANFilter(CANXL_RXFIFO_Type * base, Canexcel_Ip_RxFifoFilterSDU_CAN * filter, uint8 filtIdx)
613 {
614 uint32 mask = 1UL << filtIdx%32U;
615 if(filter->filterType == CANEXCEL_IP_RX_FIFO_RANGE_FILTER)
616 {
617 /* Enable Range Filter operation */
618 base->VAMRCFG |= mask;
619 }
620 else
621 { /* Enable Mask Filter operation */
622 base->VAMRCFG &= (~mask);
623 }
624 /* Div the register selection to 2, this register is composed form a pair of SDU filter */
625 base->VAFLT[filtIdx>>2U] = 0U;
626 if(filtIdx % 2 == 0U)
627 {
628 base->VAFLT[filtIdx>>2U] |= CANXL_RXFIFO_VAFLT_VCANa_H(filter->sduVcanFilterH) | CANXL_RXFIFO_VAFLT_VCANa_L(filter->sduVcanFilterL);
629 }
630 else
631 {
632 base->VAFLT[filtIdx>>2U] |= CANXL_RXFIFO_VAFLT_VCANb_H(filter->sduVcanFilterH) | CANXL_RXFIFO_VAFLT_VCANb_L(filter->sduVcanFilterL);
633 }
634 }
635
636 /** @} */
637
638
