1 /***************************************************************************//**
2 * \file system_psoc6_cm4.c
3 * \version 2.95.1
4 *
5 * The device system-source file.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 #include <stdbool.h>
26 #include "system_psoc6.h"
27 #include "cy_device.h"
28 #include "cy_device_headers.h"
29 #include "cy_syslib.h"
30 #include "cy_sysclk.h"
31 #include "cy_wdt.h"
32
33 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
34 #include "cy_ipc_sema.h"
35 #include "cy_ipc_pipe.h"
36 #include "cy_ipc_drv.h"
37
38 #if defined(CY_DEVICE_PSOC6ABLE2)
39 #include "cy_flash.h"
40 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
41 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
42
43 #if defined(CY_DEVICE_SECURE)
44 #include "cy_pra.h"
45 #endif /* defined(CY_DEVICE_SECURE) */
46
47
48 /*******************************************************************************
49 * SystemCoreClockUpdate()
50 *******************************************************************************/
51
52 /** Default HFClk frequency in Hz */
53 #define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
54
55 /** Default PeriClk frequency in Hz */
56 #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
57
58 /** Default FastClk system core frequency in Hz */
59 #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
60
61 uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
62
63 uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
64
65 uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
66
67 /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
68 uint32_t cy_BleEcoClockFreqHz = 0UL;
69
70 /* SCB->CPACR */
71 #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
72
73 /** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
74 uint32_t cy_AhbFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
75
76 /*******************************************************************************
77 * SystemInit()
78 *******************************************************************************/
79
80 /* CLK_FLL_CONFIG default values */
81 #define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
82 #define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
83 #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
84 #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
85
86 /* IPC_STRUCT7->DATA configuration */
87 #define CY_STARTUP_CM0_DP_STATE (0x2uL)
88 #define CY_STARTUP_IPC7_DP_OFFSET (28u)
89
90
91 /*******************************************************************************
92 * SystemCoreClockUpdate (void)
93 *******************************************************************************/
94
95 /* Do not use these definitions directly in your application */
96 #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
97 #define CY_DELAY_1K_THRESHOLD (1000u)
98 #define CY_DELAY_1M_THRESHOLD (1000000u)
99
100 uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
101
102 uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
103
104
SystemInit(void)105 void SystemInit(void)
106 {
107 Cy_PDL_Init(CY_DEVICE_CFG);
108
109 #ifdef __CM0P_PRESENT
110 #if (__CM0P_PRESENT == 0)
111 /* Restore FLL registers to the default state as they are not restored by the ROM code */
112 uint32_t copy = SRSS->CLK_FLL_CONFIG;
113 copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
114 SRSS->CLK_FLL_CONFIG = copy;
115
116 copy = SRSS->CLK_ROOT_SELECT[0u];
117 copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
118 SRSS->CLK_ROOT_SELECT[0u] = copy;
119
120 SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
121 SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
122 SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
123 SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
124
125 /* Unlock and disable WDT */
126 Cy_WDT_Unlock();
127 Cy_WDT_Disable();
128 #endif /* (__CM0P_PRESENT == 0) */
129 #endif /* __CM0P_PRESENT */
130
131 Cy_SystemInit();
132 SystemCoreClockUpdate();
133
134 #ifdef __CM0P_PRESENT
135 #if (__CM0P_PRESENT == 0)
136 /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
137 REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
138 CY_STARTUP_IPC7_DP_OFFSET);
139
140 /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
141 REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
142 #endif /* (__CM0P_PRESENT == 0) */
143 #endif /* __CM0P_PRESENT */
144
145 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
146
147 #ifdef __CM0P_PRESENT
148 #if (__CM0P_PRESENT == 0)
149 /* Allocate and initialize semaphores for the system operations. */
150 static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
151 (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
152 #else
153 (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
154 #endif /* (__CM0P_PRESENT) */
155 #else
156 (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
157 #endif /* __CM0P_PRESENT */
158
159
160 /********************************************************************************
161 *
162 * Initializes the system pipes. The system pipes are used by BLE and Flash.
163 *
164 * If the default startup file is not used, or SystemInit() is not called in your
165 * project, call the following three functions prior to executing any flash or
166 * EmEEPROM write or erase operation:
167 * -# Cy_IPC_Sema_Init()
168 * -# Cy_IPC_Pipe_Config()
169 * -# Cy_IPC_Pipe_Init()
170 * -# Cy_Flash_Init()
171 *
172 *******************************************************************************/
173 /* Create an array of endpoint structures */
174 static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
175
176 Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
177
178 static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
179
180 static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
181 {
182 /* .ep0ConfigData */
183 {
184 /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
185 /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
186 /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
187 /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
188 /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
189 },
190 /* .ep1ConfigData */
191 {
192 /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
193 /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
194 /* .ipcNotifierMuxNumber */ 0u,
195 /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
196 /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
197 },
198 /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
199 /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
200 /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
201 };
202
203 Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
204
205 #if defined(CY_DEVICE_PSOC6ABLE2)
206 Cy_Flash_Init();
207 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
208
209 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
210
211 #if defined(CY_DEVICE_SECURE)
212 /* Initialize Protected Register Access driver */
213 Cy_PRA_Init();
214 #endif /* defined(CY_DEVICE_SECURE) */
215 }
216
217
218 /*******************************************************************************
219 * Function Name: Cy_SystemInit
220 ****************************************************************************//**
221 *
222 * The function is called during device startup. Once project compiled as part of
223 * the PSoC Creator project, the Cy_SystemInit() function is generated by the
224 * PSoC Creator.
225 *
226 * The function generated by PSoC Creator performs all of the necessary device
227 * configuration based on the design settings. This includes settings from the
228 * Design Wide Resources (DWR) such as Clocks and Pins as well as any component
229 * configuration that is necessary.
230 *
231 *******************************************************************************/
Cy_SystemInit(void)232 __WEAK void Cy_SystemInit(void)
233 {
234 /* Empty weak function. The actual implementation to be in the PSoC Creator
235 * generated strong function.
236 */
237 }
238
239
SystemCoreClockUpdate(void)240 void SystemCoreClockUpdate (void)
241 {
242 uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
243
244 if (0UL != locHf0Clock)
245 {
246 cy_Hfclk0FreqHz = locHf0Clock;
247 cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
248 SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
249
250 /* Sets clock frequency for Delay API */
251 cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
252 cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
253
254 /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
255 cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
256 }
257 }
258
259
260 /*******************************************************************************
261 * Function Name: Cy_SystemInitFpuEnable
262 ****************************************************************************//**
263 *
264 * Enables the FPU if it is used. The function is called from the startup file.
265 *
266 *******************************************************************************/
Cy_SystemInitFpuEnable(void)267 void Cy_SystemInitFpuEnable(void)
268 {
269 #if defined (__FPU_USED) && (__FPU_USED == 1U)
270 uint32_t interruptState;
271 interruptState = __get_PRIMASK();
272 __disable_irq();
273 SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
274 __DSB();
275 __ISB();
276 __set_PRIMASK(interruptState);
277 #endif /* (__FPU_USED) && (__FPU_USED == 1U) */
278 }
279
280
281 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
282 /*******************************************************************************
283 * Function Name: Cy_SysIpcPipeIsrCm4
284 ****************************************************************************//**
285 *
286 * This is the interrupt service routine for the system pipe.
287 *
288 *******************************************************************************/
Cy_SysIpcPipeIsrCm4(void)289 void Cy_SysIpcPipeIsrCm4(void)
290 {
291 Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
292 }
293 #endif
294
295
296 /*******************************************************************************
297 * Function Name: Cy_MemorySymbols
298 ****************************************************************************//**
299 *
300 * The intention of the function is to declare boundaries of the memories for the
301 * MDK compilers. For the rest of the supported compilers, this is done using
302 * linker configuration files. The following symbols used by the cymcuelftool.
303 *
304 *******************************************************************************/
305 #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
Cy_MemorySymbols(void)306 __asm void Cy_MemorySymbols(void)
307 {
308 /* Flash */
309 EXPORT __cy_memory_0_start
310 EXPORT __cy_memory_0_length
311 EXPORT __cy_memory_0_row_size
312
313 /* Working Flash */
314 EXPORT __cy_memory_1_start
315 EXPORT __cy_memory_1_length
316 EXPORT __cy_memory_1_row_size
317
318 /* Supervisory Flash */
319 EXPORT __cy_memory_2_start
320 EXPORT __cy_memory_2_length
321 EXPORT __cy_memory_2_row_size
322
323 /* XIP */
324 EXPORT __cy_memory_3_start
325 EXPORT __cy_memory_3_length
326 EXPORT __cy_memory_3_row_size
327
328 /* eFuse */
329 EXPORT __cy_memory_4_start
330 EXPORT __cy_memory_4_length
331 EXPORT __cy_memory_4_row_size
332
333 /* Flash */
334 __cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
335 __cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
336 __cy_memory_0_row_size EQU 0x200
337
338 /* Flash region for EEPROM emulation */
339 __cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
340 __cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
341 __cy_memory_1_row_size EQU 0x200
342
343 /* Supervisory Flash */
344 __cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
345 __cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
346 __cy_memory_2_row_size EQU 0x200
347
348 /* XIP */
349 __cy_memory_3_start EQU __cpp(CY_XIP_BASE)
350 __cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
351 __cy_memory_3_row_size EQU 0x200
352
353 /* eFuse */
354 __cy_memory_4_start EQU __cpp(0x90700000)
355 __cy_memory_4_length EQU __cpp(0x100000)
356 __cy_memory_4_row_size EQU __cpp(1)
357 }
358 #endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
359
360
361 /* [] END OF FILE */
362
