1/**************************************************************************//** 2 * @file startup_psoc6_03_cm4.S 3 * @brief CMSIS Core Device Startup File for 4 * ARMCM4 Device Series 5 * @version V5.00 6 * @date 02. March 2016 7 ******************************************************************************/ 8/* 9 * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 /* Address of the NMI handler */ 27 #define CY_NMI_HANLDER_ADDR 0x0000000D 28 29 /* The CPU VTOR register */ 30 #define CY_CPU_VTOR_ADDR 0xE000ED08 31 32 /* Copy flash vectors and data section to RAM */ 33 #define __STARTUP_COPY_MULTIPLE 34 35 /* Clear single BSS section */ 36 #define __STARTUP_CLEAR_BSS 37 38 .syntax unified 39 .arch armv7-m 40 41 .section .stack 42 .align 3 43#ifdef __STACK_SIZE 44 .equ Stack_Size, __STACK_SIZE 45#else 46 .equ Stack_Size, 0x00001000 47#endif 48 .globl __StackTop 49 .globl __StackLimit 50__StackLimit: 51 .space Stack_Size 52 .size __StackLimit, . - __StackLimit 53__StackTop: 54 .size __StackTop, . - __StackTop 55 56 .section .heap 57 .align 3 58#ifdef __HEAP_SIZE 59 .equ Heap_Size, __HEAP_SIZE 60#else 61 .equ Heap_Size, 0x00000400 62#endif 63 .globl __HeapBase 64 .globl __HeapLimit 65__HeapBase: 66 .if Heap_Size 67 .space Heap_Size 68 .endif 69 .size __HeapBase, . - __HeapBase 70__HeapLimit: 71 .size __HeapLimit, . - __HeapLimit 72 73 .section .vectors 74 .align 2 75 .globl __Vectors 76__Vectors: 77 .long __StackTop /* Top of Stack */ 78 .long Reset_Handler /* Reset Handler */ 79 .long CY_NMI_HANLDER_ADDR /* NMI Handler */ 80 .long HardFault_Handler /* Hard Fault Handler */ 81 .long MemManage_Handler /* MPU Fault Handler */ 82 .long BusFault_Handler /* Bus Fault Handler */ 83 .long UsageFault_Handler /* Usage Fault Handler */ 84 .long 0 /* Reserved */ 85 .long 0 /* Reserved */ 86 .long 0 /* Reserved */ 87 .long 0 /* Reserved */ 88 .long SVC_Handler /* SVCall Handler */ 89 .long DebugMon_Handler /* Debug Monitor Handler */ 90 .long 0 /* Reserved */ 91 .long PendSV_Handler /* PendSV Handler */ 92 .long SysTick_Handler /* SysTick Handler */ 93 94 /* External interrupts Description */ 95 .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ 96 .long 0 /* Reserved */ 97 .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ 98 .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ 99 .long 0 /* Reserved */ 100 .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ 101 .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ 102 .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ 103 .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ 104 .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ 105 .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ 106 .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ 107 .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ 108 .long 0 /* Reserved */ 109 .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ 110 .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ 111 .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ 112 .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ 113 .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ 114 .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 115 .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 116 .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ 117 .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 118 .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ 119 .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ 120 .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ 121 .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ 122 .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ 123 .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ 124 .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ 125 .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ 126 .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ 127 .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ 128 .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ 129 .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ 130 .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ 131 .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ 132 .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ 133 .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ 134 .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ 135 .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ 136 .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ 137 .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ 138 .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ 139 .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ 140 .long 0 /* Reserved */ 141 .long 0 /* Reserved */ 142 .long 0 /* Reserved */ 143 .long 0 /* Reserved */ 144 .long 0 /* Reserved */ 145 .long 0 /* Reserved */ 146 .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ 147 .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ 148 .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ 149 .long 0 /* Reserved */ 150 .long 0 /* Reserved */ 151 .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ 152 .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ 153 .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ 154 .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ 155 .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ 156 .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ 157 .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ 158 .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ 159 .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ 160 .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ 161 .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ 162 .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ 163 .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ 164 .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ 165 .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ 166 .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ 167 .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ 168 .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ 169 .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ 170 .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ 171 .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ 172 .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ 173 .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ 174 .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ 175 .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ 176 .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ 177 .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ 178 .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ 179 .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ 180 .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ 181 .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ 182 .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ 183 .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ 184 .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ 185 .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ 186 .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ 187 .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ 188 .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ 189 .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ 190 .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ 191 .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ 192 .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ 193 .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ 194 .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ 195 .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ 196 .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ 197 .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ 198 .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ 199 .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ 200 .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ 201 .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ 202 .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ 203 .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ 204 .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ 205 .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ 206 .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ 207 .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ 208 .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ 209 .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ 210 .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ 211 .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ 212 .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ 213 .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ 214 .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ 215 .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ 216 .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ 217 .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ 218 .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ 219 .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ 220 .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ 221 .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ 222 .long 0 /* Reserved */ 223 .long 0 /* Reserved */ 224 .long 0 /* Reserved */ 225 .long 0 /* Reserved */ 226 .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ 227 .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ 228 .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ 229 .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ 230 .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ 231 .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ 232 .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ 233 .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ 234 .long 0 /* Reserved */ 235 .long 0 /* Reserved */ 236 .long 0 /* Reserved */ 237 .long 0 /* Reserved */ 238 .long 0 /* Reserved */ 239 .long 0 /* Reserved */ 240 .long 0 /* Reserved */ 241 .long 0 /* Reserved */ 242 .long 0 /* Reserved */ 243 .long 0 /* Reserved */ 244 .long 0 /* Reserved */ 245 .long 0 /* Reserved */ 246 .long 0 /* Reserved */ 247 .long 0 /* Reserved */ 248 .long 0 /* Reserved */ 249 .long 0 /* Reserved */ 250 .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ 251 .long 0 /* Reserved */ 252 .long 0 /* Reserved */ 253 .long 0 /* Reserved */ 254 .long 0 /* Reserved */ 255 .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ 256 .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ 257 .long usb_interrupt_med_IRQHandler /* USB Interrupt */ 258 .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ 259 .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ 260 .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ 261 .long 0 /* Reserved */ 262 .long 0 /* Reserved */ 263 .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ 264 .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ 265 .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ 266 .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ 267 .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ 268 .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ 269 270 271 .size __Vectors, . - __Vectors 272 .equ __VectorsSize, . - __Vectors 273 274 .section .ram_vectors 275 .align 2 276 .globl __ramVectors 277__ramVectors: 278 .space __VectorsSize 279 .size __ramVectors, . - __ramVectors 280 281 282 .text 283 .thumb 284 .thumb_func 285 .align 2 286 287 /* 288 * Device startup customization 289 * 290 * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 291 * because this function is executed as the first instruction in the ResetHandler. 292 * The PDL is also not initialized to use the proper register offsets. 293 * The user of this function is responsible for initializing the PDL and resources before using them. 294 */ 295 .weak Cy_OnResetUser 296 .func Cy_OnResetUser, Cy_OnResetUser 297 .type Cy_OnResetUser, %function 298 299Cy_OnResetUser: 300 bx lr 301 .size Cy_OnResetUser, . - Cy_OnResetUser 302 .endfunc 303 304 /* OS-specific low-level initialization */ 305 .weak cy_toolchain_init 306 .func cy_toolchain_init, cy_toolchain_init 307 .type cy_toolchain_init, %function 308 309cy_toolchain_init: 310 bx lr 311 .size cy_toolchain_init, . - cy_toolchain_init 312 .endfunc 313 314 /* Reset handler */ 315 .weak Reset_Handler 316 .type Reset_Handler, %function 317 318Reset_Handler: 319 bl Cy_OnResetUser 320 cpsid i 321 322/* Firstly it copies data from read only memory to RAM. There are two schemes 323 * to copy. One can copy more than one sections. Another can only copy 324 * one section. The former scheme needs more instructions and read-only 325 * data to implement than the latter. 326 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ 327 328#ifdef __STARTUP_COPY_MULTIPLE 329/* Multiple sections scheme. 330 * 331 * Between symbol address __copy_table_start__ and __copy_table_end__, 332 * there are array of triplets, each of which specify: 333 * offset 0: LMA of start of a section to copy from 334 * offset 4: VMA of start of a section to copy to 335 * offset 8: size of the section to copy. Must be multiply of 4 336 * 337 * All addresses must be aligned to 4 bytes boundary. 338 */ 339 ldr r4, =__copy_table_start__ 340 ldr r5, =__copy_table_end__ 341 342.L_loop0: 343 cmp r4, r5 344 bge .L_loop0_done 345 ldr r1, [r4] 346 ldr r2, [r4, #4] 347 ldr r3, [r4, #8] 348 349.L_loop0_0: 350 subs r3, #4 351 ittt ge 352 ldrge r0, [r1, r3] 353 strge r0, [r2, r3] 354 bge .L_loop0_0 355 356 adds r4, #12 357 b .L_loop0 358 359.L_loop0_done: 360#else 361/* Single section scheme. 362 * 363 * The ranges of copy from/to are specified by following symbols 364 * __etext: LMA of start of the section to copy from. Usually end of text 365 * __data_start__: VMA of start of the section to copy to 366 * __data_end__: VMA of end of the section to copy to 367 * 368 * All addresses must be aligned to 4 bytes boundary. 369 */ 370 ldr r1, =__etext 371 ldr r2, =__data_start__ 372 ldr r3, =__data_end__ 373 374.L_loop1: 375 cmp r2, r3 376 ittt lt 377 ldrlt r0, [r1], #4 378 strlt r0, [r2], #4 379 blt .L_loop1 380#endif /*__STARTUP_COPY_MULTIPLE */ 381 382/* This part of work usually is done in C library startup code. Otherwise, 383 * define this macro to enable it in this startup. 384 * 385 * There are two schemes too. One can clear multiple BSS sections. Another 386 * can only clear one section. The former is more size expensive than the 387 * latter. 388 * 389 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. 390 * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. 391 */ 392#ifdef __STARTUP_CLEAR_BSS_MULTIPLE 393/* Multiple sections scheme. 394 * 395 * Between symbol address __copy_table_start__ and __copy_table_end__, 396 * there are array of tuples specifying: 397 * offset 0: Start of a BSS section 398 * offset 4: Size of this BSS section. Must be multiply of 4 399 */ 400 ldr r3, =__zero_table_start__ 401 ldr r4, =__zero_table_end__ 402 403.L_loop2: 404 cmp r3, r4 405 bge .L_loop2_done 406 ldr r1, [r3] 407 ldr r2, [r3, #4] 408 movs r0, 0 409 410.L_loop2_0: 411 subs r2, #4 412 itt ge 413 strge r0, [r1, r2] 414 bge .L_loop2_0 415 416 adds r3, #8 417 b .L_loop2 418.L_loop2_done: 419#elif defined (__STARTUP_CLEAR_BSS) 420/* Single BSS section scheme. 421 * 422 * The BSS section is specified by following symbols 423 * __bss_start__: start of the BSS section. 424 * __bss_end__: end of the BSS section. 425 * 426 * Both addresses must be aligned to 4 bytes boundary. 427 */ 428 ldr r1, =__bss_start__ 429 ldr r2, =__bss_end__ 430 431 movs r0, 0 432.L_loop3: 433 cmp r1, r2 434 itt lt 435 strlt r0, [r1], #4 436 blt .L_loop3 437#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ 438 439 /* Update Vector Table Offset Register. */ 440 ldr r0, =__ramVectors 441 ldr r1, =CY_CPU_VTOR_ADDR 442 str r0, [r1] 443 dsb 0xF 444 445 /* Enable the FPU if used */ 446 bl Cy_SystemInitFpuEnable 447 448#ifndef __NO_SYSTEM_INIT 449 bl SystemInit 450#endif 451 452 /* OS-specific low-level initialization */ 453 bl cy_toolchain_init 454 455 /* Call C/C++ static constructors */ 456 bl __libc_init_array 457 458 /* Execute main application */ 459 bl main 460 461 /* Call C/C++ static destructors */ 462 bl __libc_fini_array 463 464 /* Should never get here */ 465 b . 466 467 .pool 468 .size Reset_Handler, . - Reset_Handler 469 470 .align 1 471 .thumb_func 472 .weak Default_Handler 473 .type Default_Handler, %function 474 475Default_Handler: 476 b . 477 .size Default_Handler, . - Default_Handler 478 479 480 .weak Cy_SysLib_FaultHandler 481 .type Cy_SysLib_FaultHandler, %function 482 483Cy_SysLib_FaultHandler: 484 b . 485 .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler 486 .type Fault_Handler, %function 487 488Fault_Handler: 489 /* Storing LR content for Creator call stack trace */ 490 push {LR} 491 movs r0, #4 492 mov r1, LR 493 tst r0, r1 494 beq .L_MSP 495 mrs r0, PSP 496 b .L_API_call 497.L_MSP: 498 mrs r0, MSP 499 /* Compensation of stack pointer address due to pushing 4 bytes of LR */ 500 adds r0, r0, #4 501.L_API_call: 502 bl Cy_SysLib_FaultHandler 503 b . 504 .size Fault_Handler, . - Fault_Handler 505 506.macro def_fault_Handler fault_handler_name 507 .weak \fault_handler_name 508 .set \fault_handler_name, Fault_Handler 509 .endm 510 511/* Macro to define default handlers. Default handler 512 * will be weak symbol and just dead loops. They can be 513 * overwritten by other handlers */ 514 .macro def_irq_handler handler_name 515 .weak \handler_name 516 .set \handler_name, Default_Handler 517 .endm 518 519 def_irq_handler NMI_Handler 520 521 def_fault_Handler HardFault_Handler 522 def_fault_Handler MemManage_Handler 523 def_fault_Handler BusFault_Handler 524 def_fault_Handler UsageFault_Handler 525 526 def_irq_handler SVC_Handler 527 def_irq_handler DebugMon_Handler 528 def_irq_handler PendSV_Handler 529 def_irq_handler SysTick_Handler 530 531 def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ 532 def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ 533 def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ 534 def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ 535 def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ 536 def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ 537 def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ 538 def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ 539 def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ 540 def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ 541 def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ 542 def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ 543 def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ 544 def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ 545 def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ 546 def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ 547 def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 548 def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 549 def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ 550 def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 551 def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ 552 def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ 553 def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ 554 def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ 555 def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ 556 def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ 557 def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ 558 def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ 559 def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ 560 def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ 561 def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ 562 def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ 563 def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ 564 def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ 565 def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ 566 def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ 567 def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ 568 def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ 569 def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ 570 def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ 571 def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ 572 def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ 573 def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ 574 def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ 575 def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ 576 def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ 577 def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ 578 def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ 579 def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ 580 def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ 581 def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ 582 def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ 583 def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ 584 def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ 585 def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ 586 def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ 587 def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ 588 def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ 589 def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ 590 def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ 591 def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ 592 def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ 593 def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ 594 def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ 595 def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ 596 def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ 597 def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ 598 def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ 599 def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ 600 def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ 601 def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ 602 def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ 603 def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ 604 def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ 605 def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ 606 def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ 607 def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ 608 def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ 609 def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ 610 def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ 611 def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ 612 def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ 613 def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ 614 def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ 615 def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ 616 def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ 617 def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ 618 def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ 619 def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ 620 def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ 621 def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ 622 def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ 623 def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ 624 def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ 625 def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ 626 def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ 627 def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ 628 def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ 629 def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ 630 def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ 631 def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ 632 def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ 633 def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ 634 def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ 635 def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ 636 def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ 637 def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ 638 def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ 639 def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ 640 def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ 641 def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ 642 def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ 643 def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ 644 def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ 645 def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ 646 def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ 647 def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ 648 def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ 649 def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ 650 def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ 651 def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ 652 def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ 653 def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ 654 def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ 655 def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ 656 def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ 657 def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ 658 def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ 659 def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ 660 def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ 661 def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ 662 def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ 663 def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ 664 def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ 665 def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ 666 def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ 667 def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ 668 669 .end 670 671 672/* [] END OF FILE */ 673
