1/**************************************************************************//** 2 * @file startup_psoc6_01_cm4.S 3 * @brief CMSIS Core Device Startup File for 4 * ARMCM4 Device Series 5 * @version V5.00 6 * @date 02. March 2016 7 ******************************************************************************/ 8/* 9 * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 /* Address of the NMI handler */ 27 #define CY_NMI_HANLDER_ADDR 0x0000000D 28 29 /* The CPU VTOR register */ 30 #define CY_CPU_VTOR_ADDR 0xE000ED08 31 32 /* Copy flash vectors and data section to RAM */ 33 #define __STARTUP_COPY_MULTIPLE 34 35 /* Clear single BSS section */ 36 #define __STARTUP_CLEAR_BSS 37 38 .syntax unified 39 .arch armv7-m 40 41 .section .stack 42 .align 3 43#ifdef __STACK_SIZE 44 .equ Stack_Size, __STACK_SIZE 45#else 46 .equ Stack_Size, 0x00001000 47#endif 48 .globl __StackTop 49 .globl __StackLimit 50__StackLimit: 51 .space Stack_Size 52 .size __StackLimit, . - __StackLimit 53__StackTop: 54 .size __StackTop, . - __StackTop 55 56 .section .heap 57 .align 3 58#ifdef __HEAP_SIZE 59 .equ Heap_Size, __HEAP_SIZE 60#else 61 .equ Heap_Size, 0x00000400 62#endif 63 .globl __HeapBase 64 .globl __HeapLimit 65__HeapBase: 66 .if Heap_Size 67 .space Heap_Size 68 .endif 69 .size __HeapBase, . - __HeapBase 70__HeapLimit: 71 .size __HeapLimit, . - __HeapLimit 72 73 .section .vectors 74 .align 2 75 .globl __Vectors 76__Vectors: 77 .long __StackTop /* Top of Stack */ 78 .long Reset_Handler /* Reset Handler */ 79 .long CY_NMI_HANLDER_ADDR /* NMI Handler */ 80 .long HardFault_Handler /* Hard Fault Handler */ 81 .long MemManage_Handler /* MPU Fault Handler */ 82 .long BusFault_Handler /* Bus Fault Handler */ 83 .long UsageFault_Handler /* Usage Fault Handler */ 84 .long 0 /* Reserved */ 85 .long 0 /* Reserved */ 86 .long 0 /* Reserved */ 87 .long 0 /* Reserved */ 88 .long SVC_Handler /* SVCall Handler */ 89 .long DebugMon_Handler /* Debug Monitor Handler */ 90 .long 0 /* Reserved */ 91 .long PendSV_Handler /* PendSV Handler */ 92 .long SysTick_Handler /* SysTick Handler */ 93 94 /* External interrupts Description */ 95 .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ 96 .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ 97 .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ 98 .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ 99 .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ 100 .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ 101 .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ 102 .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ 103 .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ 104 .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ 105 .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ 106 .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ 107 .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ 108 .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ 109 .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ 110 .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ 111 .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ 112 .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ 113 .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ 114 .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 115 .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 116 .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ 117 .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 118 .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ 119 .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ 120 .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ 121 .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ 122 .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ 123 .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ 124 .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ 125 .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ 126 .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ 127 .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ 128 .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ 129 .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ 130 .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ 131 .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ 132 .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ 133 .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ 134 .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ 135 .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ 136 .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ 137 .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ 138 .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ 139 .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ 140 .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ 141 .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ 142 .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ 143 .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ 144 .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ 145 .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ 146 .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ 147 .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ 148 .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ 149 .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ 150 .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ 151 .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ 152 .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ 153 .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ 154 .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ 155 .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ 156 .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ 157 .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ 158 .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ 159 .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ 160 .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ 161 .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ 162 .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ 163 .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ 164 .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ 165 .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ 166 .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ 167 .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ 168 .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ 169 .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ 170 .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ 171 .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ 172 .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ 173 .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ 174 .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ 175 .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ 176 .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ 177 .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ 178 .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ 179 .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ 180 .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ 181 .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ 182 .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ 183 .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ 184 .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ 185 .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ 186 .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ 187 .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ 188 .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ 189 .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ 190 .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ 191 .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ 192 .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ 193 .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ 194 .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ 195 .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ 196 .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ 197 .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ 198 .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ 199 .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ 200 .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ 201 .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ 202 .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ 203 .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ 204 .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ 205 .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ 206 .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ 207 .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ 208 .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ 209 .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ 210 .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ 211 .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ 212 .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ 213 .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ 214 .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ 215 .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ 216 .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ 217 .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ 218 .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ 219 .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ 220 .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ 221 .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ 222 .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ 223 .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ 224 .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ 225 .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ 226 .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ 227 .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ 228 .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ 229 .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ 230 .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ 231 .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ 232 .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ 233 .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ 234 .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ 235 .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ 236 .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ 237 .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ 238 .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ 239 .long usb_interrupt_med_IRQHandler /* USB Interrupt */ 240 .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ 241 .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ 242 243 244 .size __Vectors, . - __Vectors 245 .equ __VectorsSize, . - __Vectors 246 247 .section .ram_vectors 248 .align 2 249 .globl __ramVectors 250__ramVectors: 251 .space __VectorsSize 252 .size __ramVectors, . - __ramVectors 253 254 255 .text 256 .thumb 257 .thumb_func 258 .align 2 259 260 /* 261 * Device startup customization 262 * 263 * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 264 * because this function is executed as the first instruction in the ResetHandler. 265 * The PDL is also not initialized to use the proper register offsets. 266 * The user of this function is responsible for initializing the PDL and resources before using them. 267 */ 268 .weak Cy_OnResetUser 269 .func Cy_OnResetUser, Cy_OnResetUser 270 .type Cy_OnResetUser, %function 271 272Cy_OnResetUser: 273 bx lr 274 .size Cy_OnResetUser, . - Cy_OnResetUser 275 .endfunc 276 277 /* OS-specific low-level initialization */ 278 .weak cy_toolchain_init 279 .func cy_toolchain_init, cy_toolchain_init 280 .type cy_toolchain_init, %function 281 282cy_toolchain_init: 283 bx lr 284 .size cy_toolchain_init, . - cy_toolchain_init 285 .endfunc 286 287 /* Reset handler */ 288 .weak Reset_Handler 289 .type Reset_Handler, %function 290 291Reset_Handler: 292 bl Cy_OnResetUser 293 cpsid i 294 295/* Firstly it copies data from read only memory to RAM. There are two schemes 296 * to copy. One can copy more than one sections. Another can only copy 297 * one section. The former scheme needs more instructions and read-only 298 * data to implement than the latter. 299 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ 300 301#ifdef __STARTUP_COPY_MULTIPLE 302/* Multiple sections scheme. 303 * 304 * Between symbol address __copy_table_start__ and __copy_table_end__, 305 * there are array of triplets, each of which specify: 306 * offset 0: LMA of start of a section to copy from 307 * offset 4: VMA of start of a section to copy to 308 * offset 8: size of the section to copy. Must be multiply of 4 309 * 310 * All addresses must be aligned to 4 bytes boundary. 311 */ 312 ldr r4, =__copy_table_start__ 313 ldr r5, =__copy_table_end__ 314 315.L_loop0: 316 cmp r4, r5 317 bge .L_loop0_done 318 ldr r1, [r4] 319 ldr r2, [r4, #4] 320 ldr r3, [r4, #8] 321 322.L_loop0_0: 323 subs r3, #4 324 ittt ge 325 ldrge r0, [r1, r3] 326 strge r0, [r2, r3] 327 bge .L_loop0_0 328 329 adds r4, #12 330 b .L_loop0 331 332.L_loop0_done: 333#else 334/* Single section scheme. 335 * 336 * The ranges of copy from/to are specified by following symbols 337 * __etext: LMA of start of the section to copy from. Usually end of text 338 * __data_start__: VMA of start of the section to copy to 339 * __data_end__: VMA of end of the section to copy to 340 * 341 * All addresses must be aligned to 4 bytes boundary. 342 */ 343 ldr r1, =__etext 344 ldr r2, =__data_start__ 345 ldr r3, =__data_end__ 346 347.L_loop1: 348 cmp r2, r3 349 ittt lt 350 ldrlt r0, [r1], #4 351 strlt r0, [r2], #4 352 blt .L_loop1 353#endif /*__STARTUP_COPY_MULTIPLE */ 354 355/* This part of work usually is done in C library startup code. Otherwise, 356 * define this macro to enable it in this startup. 357 * 358 * There are two schemes too. One can clear multiple BSS sections. Another 359 * can only clear one section. The former is more size expensive than the 360 * latter. 361 * 362 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. 363 * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. 364 */ 365#ifdef __STARTUP_CLEAR_BSS_MULTIPLE 366/* Multiple sections scheme. 367 * 368 * Between symbol address __copy_table_start__ and __copy_table_end__, 369 * there are array of tuples specifying: 370 * offset 0: Start of a BSS section 371 * offset 4: Size of this BSS section. Must be multiply of 4 372 */ 373 ldr r3, =__zero_table_start__ 374 ldr r4, =__zero_table_end__ 375 376.L_loop2: 377 cmp r3, r4 378 bge .L_loop2_done 379 ldr r1, [r3] 380 ldr r2, [r3, #4] 381 movs r0, 0 382 383.L_loop2_0: 384 subs r2, #4 385 itt ge 386 strge r0, [r1, r2] 387 bge .L_loop2_0 388 389 adds r3, #8 390 b .L_loop2 391.L_loop2_done: 392#elif defined (__STARTUP_CLEAR_BSS) 393/* Single BSS section scheme. 394 * 395 * The BSS section is specified by following symbols 396 * __bss_start__: start of the BSS section. 397 * __bss_end__: end of the BSS section. 398 * 399 * Both addresses must be aligned to 4 bytes boundary. 400 */ 401 ldr r1, =__bss_start__ 402 ldr r2, =__bss_end__ 403 404 movs r0, 0 405.L_loop3: 406 cmp r1, r2 407 itt lt 408 strlt r0, [r1], #4 409 blt .L_loop3 410#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ 411 412 /* Update Vector Table Offset Register. */ 413 ldr r0, =__ramVectors 414 ldr r1, =CY_CPU_VTOR_ADDR 415 str r0, [r1] 416 dsb 0xF 417 418 /* Enable the FPU if used */ 419 bl Cy_SystemInitFpuEnable 420 421#ifndef __NO_SYSTEM_INIT 422 bl SystemInit 423#endif 424 425 /* OS-specific low-level initialization */ 426 bl cy_toolchain_init 427 428 /* Call C/C++ static constructors */ 429 bl __libc_init_array 430 431 /* Execute main application */ 432 bl main 433 434 /* Call C/C++ static destructors */ 435 bl __libc_fini_array 436 437 /* Should never get here */ 438 b . 439 440 .pool 441 .size Reset_Handler, . - Reset_Handler 442 443 .align 1 444 .thumb_func 445 .weak Default_Handler 446 .type Default_Handler, %function 447 448Default_Handler: 449 b . 450 .size Default_Handler, . - Default_Handler 451 452 453 .weak Cy_SysLib_FaultHandler 454 .type Cy_SysLib_FaultHandler, %function 455 456Cy_SysLib_FaultHandler: 457 b . 458 .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler 459 .type Fault_Handler, %function 460 461Fault_Handler: 462 /* Storing LR content for Creator call stack trace */ 463 push {LR} 464 movs r0, #4 465 mov r1, LR 466 tst r0, r1 467 beq .L_MSP 468 mrs r0, PSP 469 b .L_API_call 470.L_MSP: 471 mrs r0, MSP 472 /* Compensation of stack pointer address due to pushing 4 bytes of LR */ 473 adds r0, r0, #4 474.L_API_call: 475 bl Cy_SysLib_FaultHandler 476 b . 477 .size Fault_Handler, . - Fault_Handler 478 479.macro def_fault_Handler fault_handler_name 480 .weak \fault_handler_name 481 .set \fault_handler_name, Fault_Handler 482 .endm 483 484/* Macro to define default handlers. Default handler 485 * will be weak symbol and just dead loops. They can be 486 * overwritten by other handlers */ 487 .macro def_irq_handler handler_name 488 .weak \handler_name 489 .set \handler_name, Default_Handler 490 .endm 491 492 def_irq_handler NMI_Handler 493 494 def_fault_Handler HardFault_Handler 495 def_fault_Handler MemManage_Handler 496 def_fault_Handler BusFault_Handler 497 def_fault_Handler UsageFault_Handler 498 499 def_irq_handler SVC_Handler 500 def_irq_handler DebugMon_Handler 501 def_irq_handler PendSV_Handler 502 def_irq_handler SysTick_Handler 503 504 def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ 505 def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ 506 def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ 507 def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ 508 def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ 509 def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ 510 def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ 511 def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ 512 def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ 513 def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ 514 def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ 515 def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ 516 def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ 517 def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ 518 def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ 519 def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ 520 def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ 521 def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ 522 def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ 523 def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 524 def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 525 def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ 526 def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 527 def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ 528 def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ 529 def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ 530 def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ 531 def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ 532 def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ 533 def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ 534 def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ 535 def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ 536 def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ 537 def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ 538 def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ 539 def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ 540 def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ 541 def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ 542 def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ 543 def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ 544 def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ 545 def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ 546 def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ 547 def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ 548 def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ 549 def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ 550 def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ 551 def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ 552 def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ 553 def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ 554 def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ 555 def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ 556 def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ 557 def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ 558 def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ 559 def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ 560 def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ 561 def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ 562 def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ 563 def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ 564 def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ 565 def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ 566 def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ 567 def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ 568 def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ 569 def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ 570 def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ 571 def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ 572 def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ 573 def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ 574 def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ 575 def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ 576 def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ 577 def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ 578 def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ 579 def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ 580 def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ 581 def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ 582 def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ 583 def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ 584 def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ 585 def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ 586 def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ 587 def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ 588 def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ 589 def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ 590 def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ 591 def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ 592 def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ 593 def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ 594 def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ 595 def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ 596 def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ 597 def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ 598 def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ 599 def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ 600 def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ 601 def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ 602 def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ 603 def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ 604 def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ 605 def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ 606 def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ 607 def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ 608 def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ 609 def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ 610 def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ 611 def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ 612 def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ 613 def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ 614 def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ 615 def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ 616 def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ 617 def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ 618 def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ 619 def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ 620 def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ 621 def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ 622 def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ 623 def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ 624 def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ 625 def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ 626 def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ 627 def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ 628 def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ 629 def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ 630 def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ 631 def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ 632 def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ 633 def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ 634 def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ 635 def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ 636 def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ 637 def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ 638 def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ 639 def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ 640 def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ 641 def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ 642 def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ 643 def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ 644 def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ 645 def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ 646 def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ 647 def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ 648 def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ 649 def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ 650 def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ 651 652 .end 653 654 655/* [] END OF FILE */ 656
