1/**************************************************************************//** 2 * @file startup_psoc6_03_cm4.S 3 * @brief CMSIS Core Device Startup File for 4 * ARMCM4 Device Series 5 * @version V5.00 6 * @date 02. March 2016 7 ******************************************************************************/ 8/* 9 * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 /* Address of the NMI handler */ 27 #define CY_NMI_HANLDER_ADDR 0x0000000D 28 29 /* The CPU VTOR register */ 30 #define CY_CPU_VTOR_ADDR 0xE000ED08 31 32 .syntax unified 33 .section __STACK , __stack 34 .align 3 35 36#ifdef __STACK_SIZE 37 .equ Stack_Size, __STACK_SIZE 38#else 39 .equ Stack_Size, 0x00001000 40#endif 41 .globl __StackTop 42 .globl __StackLimit 43 44__StackLimit: 45 .space Stack_Size 46 .equ __StackTop, . - Stack_Size 47 48 .section __HEAP, __heap 49 .align 3 50#ifdef __HEAP_SIZE 51 .equ Heap_Size, __HEAP_SIZE 52#else 53 .equ Heap_Size, 0x00000400 54#endif 55 .globl __HeapBase 56__HeapBase: 57 .if Heap_Size 58 .space Heap_Size 59 .endif 60 61 .section __VECT, ___Vectors 62 .align 2 63 .globl ___Vectors 64___Vectors: 65 .long __StackTop /* Top of Stack */ 66 .long Reset_Handler /* Reset Handler */ 67 .long CY_NMI_HANLDER_ADDR /* NMI Handler */ 68 .long HardFault_Handler /* Hard Fault Handler */ 69 .long MemManage_Handler /* MPU Fault Handler */ 70 .long BusFault_Handler /* Bus Fault Handler */ 71 .long UsageFault_Handler /* Usage Fault Handler */ 72 .long 0 /* Reserved */ 73 .long 0 /* Reserved */ 74 .long 0 /* Reserved */ 75 .long 0 /* Reserved */ 76 .long SVC_Handler /* SVCall Handler */ 77 .long DebugMon_Handler /* Debug Monitor Handler */ 78 .long 0 /* Reserved */ 79 .long PendSV_Handler /* PendSV Handler */ 80 .long SysTick_Handler /* SysTick Handler */ 81 82 /* External interrupts Description */ 83 .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ 84 .long 0 /* Reserved */ 85 .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ 86 .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ 87 .long 0 /* Reserved */ 88 .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ 89 .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ 90 .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ 91 .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ 92 .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ 93 .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ 94 .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ 95 .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ 96 .long 0 /* Reserved */ 97 .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ 98 .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ 99 .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ 100 .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ 101 .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ 102 .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 103 .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 104 .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ 105 .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 106 .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ 107 .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ 108 .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ 109 .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ 110 .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ 111 .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ 112 .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ 113 .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ 114 .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ 115 .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ 116 .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ 117 .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ 118 .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ 119 .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ 120 .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ 121 .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ 122 .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ 123 .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ 124 .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ 125 .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ 126 .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ 127 .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ 128 .long 0 /* Reserved */ 129 .long 0 /* Reserved */ 130 .long 0 /* Reserved */ 131 .long 0 /* Reserved */ 132 .long 0 /* Reserved */ 133 .long 0 /* Reserved */ 134 .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ 135 .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ 136 .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ 137 .long 0 /* Reserved */ 138 .long 0 /* Reserved */ 139 .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ 140 .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ 141 .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ 142 .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ 143 .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ 144 .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ 145 .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ 146 .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ 147 .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ 148 .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ 149 .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ 150 .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ 151 .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ 152 .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ 153 .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ 154 .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ 155 .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ 156 .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ 157 .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ 158 .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ 159 .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ 160 .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ 161 .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ 162 .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ 163 .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ 164 .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ 165 .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ 166 .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ 167 .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ 168 .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ 169 .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ 170 .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ 171 .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ 172 .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ 173 .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ 174 .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ 175 .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ 176 .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ 177 .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ 178 .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ 179 .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ 180 .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ 181 .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ 182 .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ 183 .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ 184 .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ 185 .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ 186 .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ 187 .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ 188 .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ 189 .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ 190 .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ 191 .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ 192 .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ 193 .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ 194 .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ 195 .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ 196 .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ 197 .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ 198 .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ 199 .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ 200 .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ 201 .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ 202 .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ 203 .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ 204 .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ 205 .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ 206 .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ 207 .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ 208 .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ 209 .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ 210 .long 0 /* Reserved */ 211 .long 0 /* Reserved */ 212 .long 0 /* Reserved */ 213 .long 0 /* Reserved */ 214 .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ 215 .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ 216 .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ 217 .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ 218 .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ 219 .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ 220 .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ 221 .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ 222 .long 0 /* Reserved */ 223 .long 0 /* Reserved */ 224 .long 0 /* Reserved */ 225 .long 0 /* Reserved */ 226 .long 0 /* Reserved */ 227 .long 0 /* Reserved */ 228 .long 0 /* Reserved */ 229 .long 0 /* Reserved */ 230 .long 0 /* Reserved */ 231 .long 0 /* Reserved */ 232 .long 0 /* Reserved */ 233 .long 0 /* Reserved */ 234 .long 0 /* Reserved */ 235 .long 0 /* Reserved */ 236 .long 0 /* Reserved */ 237 .long 0 /* Reserved */ 238 .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ 239 .long 0 /* Reserved */ 240 .long 0 /* Reserved */ 241 .long 0 /* Reserved */ 242 .long 0 /* Reserved */ 243 .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ 244 .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ 245 .long usb_interrupt_med_IRQHandler /* USB Interrupt */ 246 .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ 247 .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ 248 .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ 249 .long 0 /* Reserved */ 250 .long 0 /* Reserved */ 251 .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ 252 .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ 253 .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ 254 .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ 255 .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ 256 .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ 257 258 .equ __VectorsSize, . - ___Vectors 259 260 .section __RAMVECTORS, ___ramVectors 261 .align 2 262 .globl ___ramVectors 263 264___ramVectors: 265 .space __VectorsSize 266 267 268 .text 269 .thumb_func 270 .align 2 271 /* Reset handler */ 272 .globl Reset_Handler 273 274Reset_Handler: 275 bl Cy_OnResetUser 276 cpsid i 277 278/* Single section scheme. 279 * 280 * The ranges of copy from/to are specified by following symbols 281 * __etext: LMA of start of the section to copy from. Usually end of text 282 * __data_start__: VMA of start of the section to copy to 283 * __data_end__: VMA of end of the section to copy to 284 * 285 * All addresses must be aligned to 4 bytes boundary. 286 */ 287 ldr r0, =___ramVectors 288 ldr r1, =___Vectors 289 ldr r2, =__VectorsSize 290 bl _memcpy 291 292 ldr r0, =segment$start$__DATA 293 ldr r1, =segment$end$__TEXT 294 ldr r2, =section$start$__DATA$__zerofill 295 sub r2, r0 296 bl _memcpy 297 298 ldr r0, =section$start$__DATA$__zerofill 299 eor r1, r1 300 ldr r2, =section$end$__DATA$__zerofill 301 sub r2, r0 302 bl _memset 303 304 /* Update Vector Table Offset Register. */ 305 ldr r0, =___ramVectors 306 ldr r1, =CY_CPU_VTOR_ADDR 307 str r0, [r1] 308 dsb 0xF 309 310 /* Enable the FPU if used */ 311 bl _Cy_SystemInitFpuEnable 312 313 bl _HeapInit 314#ifndef __NO_SYSTEM_INIT 315 bl _SystemInit 316#endif 317 318 bl _main 319 320 /* Should never get here */ 321 b . 322 323 .pool 324 325 .text 326 .thumb 327 .thumb_func 328 .align 2 329 330 /* Device startup customization */ 331 .weak_definition Cy_OnResetUser 332 .global Cy_OnResetUser, Cy_OnResetUser 333Cy_OnResetUser: 334 bx lr 335 336 .text 337 .align 1 338 .thumb_func 339 .weak_reference Default_Handler 340 341Default_Handler: 342 b . 343 344 .text 345 .thumb_func 346 .align 2 347 .weak_definition Cy_SysLib_FaultHandler 348 349Cy_SysLib_FaultHandler: 350 b . 351 352 .text 353 .thumb_func 354 .align 2 355 356Fault_Handler: 357 /* Storing LR content for Creator call stack trace */ 358 push {LR} 359 movs r0, #4 360 mov r1, LR 361 tst r0, r1 362 beq .L_MSP 363 mrs r0, PSP 364 b .L_API_call 365.L_MSP: 366 mrs r0, MSP 367 /* Compensation of stack pointer address due to pushing 4 bytes of LR */ 368 adds r0, r0, #4 369 nop 370.L_API_call: 371 bl Cy_SysLib_FaultHandler 372 b . 373 374.macro def_fault_Handler fault_handler_name 375 .weak_definition \fault_handler_name 376 .set \fault_handler_name, Fault_Handler 377 .endm 378 379/* Macro to define default handlers. Default handler 380 * will be weak symbol and just dead loops. They can be 381 * overwritten by other handlers */ 382 .macro def_irq_handler handler_name 383 .weak_definition \handler_name 384 .set \handler_name, Default_Handler 385 .endm 386 387 def_irq_handler NMI_Handler 388 389 def_fault_Handler HardFault_Handler 390 def_fault_Handler MemManage_Handler 391 def_fault_Handler BusFault_Handler 392 def_fault_Handler UsageFault_Handler 393 394 def_irq_handler SVC_Handler 395 def_irq_handler DebugMon_Handler 396 def_irq_handler PendSV_Handler 397 def_irq_handler SysTick_Handler 398 399 def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ 400 def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ 401 def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ 402 def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ 403 def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ 404 def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ 405 def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ 406 def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ 407 def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ 408 def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ 409 def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ 410 def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ 411 def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ 412 def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ 413 def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ 414 def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ 415 def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 416 def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 417 def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ 418 def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 419 def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ 420 def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ 421 def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ 422 def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ 423 def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ 424 def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ 425 def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ 426 def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ 427 def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ 428 def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ 429 def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ 430 def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ 431 def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ 432 def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ 433 def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ 434 def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ 435 def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ 436 def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ 437 def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ 438 def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ 439 def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ 440 def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ 441 def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ 442 def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ 443 def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ 444 def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ 445 def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ 446 def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ 447 def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ 448 def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ 449 def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ 450 def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ 451 def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ 452 def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ 453 def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ 454 def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ 455 def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ 456 def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ 457 def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ 458 def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ 459 def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ 460 def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ 461 def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ 462 def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ 463 def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ 464 def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ 465 def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ 466 def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ 467 def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ 468 def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ 469 def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ 470 def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ 471 def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ 472 def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ 473 def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ 474 def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ 475 def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ 476 def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ 477 def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ 478 def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ 479 def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ 480 def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ 481 def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ 482 def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ 483 def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ 484 def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ 485 def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ 486 def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ 487 def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ 488 def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ 489 def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ 490 def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ 491 def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ 492 def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ 493 def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ 494 def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ 495 def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ 496 def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ 497 def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ 498 def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ 499 def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ 500 def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ 501 def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ 502 def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ 503 def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ 504 def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ 505 def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ 506 def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ 507 def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ 508 def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ 509 def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ 510 def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ 511 def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ 512 def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ 513 def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ 514 def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ 515 def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ 516 def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ 517 def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ 518 def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ 519 def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ 520 def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ 521 def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ 522 def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ 523 def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ 524 def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ 525 def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ 526 def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ 527 def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ 528 def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ 529 def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ 530 def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ 531 def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ 532 def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ 533 def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ 534 def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ 535 def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ 536 537 .end 538 539 540/* [] END OF FILE */ 541
