1/**************************************************************************//**
2 * @file     startup_cm0plus.S
3 * @brief    CMSIS-Core(M) Device Startup File for Cortex-M0plus Device
4 * @version  V2.2.0
5 * @date     26. May 2021
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#define CPUSS_RAM0_CTL0     0x40201300
26#define CPUSS_RAM1_CTL0     0x40201380
27#define CPUSS_RAM2_CTL0     0x402013a0
28
29
30                .syntax  unified
31                .arch    armv6-m
32
33                .section .vectors
34                .align   2
35                .globl   __Vectors
36                .globl   __Vectors_End
37                .globl   __Vectors_Size
38                .global  CM0P_CpuIntr2_Handler
39                .global  CM0P_CpuIntr3_Handler
40                .global  CM0P_CpuIntr4_Handler
41                .global  CM0P_CpuIntr5_Handler
42                .global  CM0P_CpuIntr6_Handler
43                .global  CM0P_CpuIntr7_Handler
44
45__Vectors:
46                .long    __StackTop                         /*     Top of Stack */
47                .long    Reset_Handler                      /*     Reset Handler */
48                .long    NMI_Handler                        /* -14 NMI Handler */
49                .long    HardFault_Handler                  /* -13 Hard Fault Handler */
50                .long    0                                  /*     Reserved */
51                .long    0                                  /*     Reserved */
52                .long    0                                  /*     Reserved */
53                .long    0                                  /*     Reserved */
54                .long    0                                  /*     Reserved */
55                .long    0                                  /*     Reserved */
56                .long    0                                  /*     Reserved */
57                .long    SVC_Handler                        /*  -5 SVCall Handler */
58                .long    0                                  /*     Reserved */
59                .long    0                                  /*     Reserved */
60                .long    PendSV_Handler                     /*  -2 PendSV Handler */
61                .long    SysTick_Handler                    /*  -1 SysTick Handler */
62
63                /* Interrupts */
64                .long    Default_Intr_Handler               /* CPU User Interrupt #0 */
65                .long    Default_Intr_Handler               /* CPU User Interrupt #1 */
66                .long    CM0P_CpuIntr2_Handler              /* CPU User Interrupt #2 */
67                .long    CM0P_CpuIntr3_Handler              /* CPU User Interrupt #3 */
68                .long    CM0P_CpuIntr4_Handler              /* CPU User Interrupt #4 */
69                .long    CM0P_CpuIntr5_Handler              /* CPU User Interrupt #5 */
70                .long    CM0P_CpuIntr6_Handler              /* CPU User Interrupt #6 */
71                .long    CM0P_CpuIntr7_Handler              /* CPU User Interrupt #7 */
72                .long    Default_Intr_Handler               /* Internal SW Interrupt #0 */
73                .long    Default_Intr_Handler               /* Internal SW Interrupt #1 */
74                .long    Default_Intr_Handler               /* Internal SW Interrupt #2 */
75                .long    Default_Intr_Handler               /* Internal SW Interrupt #3 */
76                .long    Default_Intr_Handler               /* Internal SW Interrupt #4 */
77                .long    Default_Intr_Handler               /* Internal SW Interrupt #5 */
78                .long    Default_Intr_Handler               /* Internal SW Interrupt #6 */
79                .long    Default_Intr_Handler               /* Internal SW Interrupt #7 */
80
81__Vectors_End:
82                .equ     __Vectors_Size, __Vectors_End - __Vectors
83                .size    __Vectors, . - __Vectors
84
85                .section .ram_vectors
86                .align 2
87                .globl __ramVectors
88__ramVectors:
89                .space  __Vectors_Size
90                .size   __ramVectors, . - __ramVectors
91
92                .thumb
93                .section .text
94                .align   2
95
96                .thumb_func
97                .type    Reset_Handler, %function
98                .globl   Reset_Handler
99                .extern  __cmsis_start
100                .fnstart
101Reset_Handler:
102                /* CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
103                 * Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet
104                 * Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
105                 * or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
106                 */
107                movs r0, #1
108                lsls r0, r0, #19
109                ldr  r1, =CPUSS_RAM0_CTL0
110                ldr  r2, [r1]
111                orrs r2, r0
112                str  r2, [r1]
113                ldr  r1, =CPUSS_RAM1_CTL0
114                ldr  r2, [r1]
115                orrs r2, r0
116                str  r2, [r1]
117                ldr  r1, =CPUSS_RAM2_CTL0
118                ldr  r2, [r1]
119                orrs r2, r0
120                str  r2, [r1]
121
122                /* Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration,
123                 * because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device
124                 * Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted)
125                 */
126                ldr     r0, =__StackTop-0x100
127                ldr     r1, =__StackTop
128                movs    r2, #0
129                movs    r3, #0
130loopstackclean:
131                stmia   r0!, {r2, r3}
132                cmp     r0, r1
133                bcc.n   loopstackclean
134
135                bl       SystemInit
136
137                bl       CyMain
138
139                .fnend
140                .size    Reset_Handler, . - Reset_Handler
141
142                .thumb_func
143                .type    Default_Handler, %function
144                .weak    Default_Handler
145Default_Handler:
146                b        .
147                .size    Default_Handler, . - Default_Handler
148                .weak    Cy_SysLib_FaultHandler
149                .type    Cy_SysLib_FaultHandler, %function
150
151Cy_SysLib_FaultHandler:
152                b    .
153                .size    Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
154                .type Fault_Handler, %function
155
156Fault_Handler:
157/*              Storing LR content for Creator call stack trace */
158                push {LR}
159                movs r0, #4
160                mov r1, LR
161                tst r0, r1
162                beq .L_MSP
163                mrs r0, PSP
164                b .L_API_call
165.L_MSP:
166                mrs r0, MSP
167/*              Compensation of stack pointer address due to pushing 4 bytes of LR */
168                adds r0, r0, #4
169.L_API_call:
170                bl Cy_SysLib_FaultHandler
171                b   .
172                .size    Fault_Handler, . - Fault_Handler
173
174                .macro    Def_Fault_Handler    fault_handler_name
175                .weak    \fault_handler_name
176                .set    \fault_handler_name, Fault_Handler
177                .endm
178
179/*              Macro to define default exception/interrupt handlers.
180 *              Default handler are weak symbols with an endless loop.
181 *              They can be overwritten by real handlers.
182 */
183                .macro   Def_Irq_Handler  Handler_Name
184                .weak    \Handler_Name
185                .set     \Handler_Name, Default_Handler
186                .endm
187
188/*              Default exception/interrupt handlers */
189                Def_Irq_Handler  NMI_Handler
190
191                Def_Fault_Handler    HardFault_Handler
192
193                Def_Irq_Handler  SVC_Handler
194                Def_Irq_Handler  PendSV_Handler
195                Def_Irq_Handler  SysTick_Handler
196                Def_Irq_Handler  Default_Intr_Handler
197
198                .end
199
200/* [] END OF FILE */
201