1/**************************************************************************//**
2 * @file     startup_psoc6_03_cm0plus.S
3 * @brief    CMSIS Core Device Startup File for
4 *           ARMCM0plus Device Series
5 * @version  V5.00
6 * @date     02. March 2016
7 ******************************************************************************/
8/*
9 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
10 *
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26    /* Address of the NMI handler */
27    #define CY_NMI_HANLDER_ADDR         0x0000000D
28
29    /* The CPU VTOR register */
30    #define CY_CPU_VTOR_ADDR            0xE000ED08
31
32    .syntax    unified
33
34    .section __STACK, __stack
35    .align    3
36#ifdef __STACK_SIZE
37    .equ    Stack_Size, __STACK_SIZE
38#else
39    .equ    Stack_Size, 0x00001000
40#endif
41    .globl    __StackTop
42    .globl    __StackLimit
43
44__StackLimit:
45    .space    Stack_Size
46    .equ    __StackTop, . - Stack_Size
47
48    .section __HEAP, __heap
49    .align    3
50#ifdef __HEAP_SIZE
51    .equ    Heap_Size, __HEAP_SIZE
52#else
53    .equ    Heap_Size, 0x00000400
54#endif
55    .globl    __HeapBase
56__HeapBase:
57    .if    Heap_Size
58    .space    Heap_Size
59    .endif
60
61    .section __VECT, ___Vectors
62    .align 2
63    .globl    ___Vectors
64___Vectors:
65    .long    __StackTop            /* Top of Stack */
66    .long    Reset_Handler         /* Reset Handler */
67    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
68    .long    HardFault_Handler     /* Hard Fault Handler */
69    .long    0                     /* Reserved */
70    .long    0                     /* Reserved */
71    .long    0                     /* Reserved */
72    .long    0                     /* Reserved */
73    .long    0                     /* Reserved */
74    .long    0                     /* Reserved */
75    .long    0                     /* Reserved */
76    .long    SVC_Handler           /* SVCall Handler */
77    .long    0                     /* Reserved */
78    .long    0                     /* Reserved */
79    .long    PendSV_Handler        /* PendSV Handler */
80    .long    SysTick_Handler       /* SysTick Handler */
81
82     /* External interrupts                             Description */
83    .long    NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
84    .long    NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
85    .long    NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
86    .long    NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
87    .long    NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
88    .long    NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
89    .long    NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
90    .long    NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
91    .long    Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
92    .long    Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
93    .long    Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
94    .long    Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
95    .long    Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
96    .long    Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
97    .long    Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
98    .long    Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
99
100    .equ    __VectorsSize, . - ___Vectors
101
102    .section __RAMVECTORS, ___ramVectors
103    .align 2
104    .globl ___ramVectors
105
106___ramVectors:
107    .space  __VectorsSize
108
109
110    .text
111    .thumb_func
112    .align 2
113    /* Reset handler */
114    .globl Reset_Handler
115
116Reset_Handler:
117    bl Cy_OnResetUser
118    cpsid i
119
120/*  Single section scheme.
121 *
122 *  The ranges of copy from/to are specified by following symbols
123 *    __etext: LMA of start of the section to copy from. Usually end of text
124 *    __data_start__: VMA of start of the section to copy to
125 *    __data_end__: VMA of end of the section to copy to
126 *
127 *  All addresses must be aligned to 4 bytes boundary.
128 */
129    ldr    r0, =___ramVectors
130    ldr    r1, =___Vectors
131    ldr    r2, =__VectorsSize
132    bl     _memcpy
133
134    ldr    r0, =segment$start$__DATA
135    ldr    r1, =segment$end$__TEXT
136    ldr    r2, =section$start$__DATA$__zerofill
137    sub    r2, r0
138    bl     _memcpy
139
140    ldr    r0, =section$start$__DATA$__zerofill
141    eor    r1, r1
142    ldr    r2, =section$end$__DATA$__zerofill
143    sub    r2, r0
144    bl     _memset
145
146    /* Update Vector Table Offset Register. */
147    ldr r0, =___ramVectors
148    ldr r1, =CY_CPU_VTOR_ADDR
149    str r0, [r1]
150    dsb 0xF
151
152    bl _HeapInit
153#ifndef __NO_SYSTEM_INIT
154    bl  _SystemInit
155#endif
156
157    bl  _main
158
159    /* Should never get here */
160    b   .
161
162    .pool
163
164    .text
165    .thumb
166    .thumb_func
167    .align 2
168
169    /* Device startup customization */
170    .weak_definition   Cy_OnResetUser
171    .global Cy_OnResetUser, Cy_OnResetUser
172Cy_OnResetUser:
173    bx lr
174
175    .text
176    .align    1
177    .thumb_func
178    .weak_reference    Default_Handler
179
180Default_Handler:
181    b    .
182
183    .text
184    .thumb_func
185    .align  2
186    .weak_definition    Cy_SysLib_FaultHandler
187
188Cy_SysLib_FaultHandler:
189    b    .
190
191    .text
192    .thumb_func
193    .align  2
194
195Fault_Handler:
196    /* Storing LR content for Creator call stack trace */
197    push {LR}
198    movs r0, #4
199    mov r1, LR
200    tst r0, r1
201    beq .L_MSP
202    mrs r0, PSP
203    b .L_API_call
204.L_MSP:
205    mrs r0, MSP
206    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
207    adds r0, r0, #4
208    nop
209.L_API_call:
210    bl Cy_SysLib_FaultHandler
211    b   .
212
213.macro    def_fault_Handler    fault_handler_name
214    .weak_definition    \fault_handler_name
215    .set    \fault_handler_name, Fault_Handler
216    .endm
217
218/*    Macro to define default handlers. Default handler
219 *    will be weak symbol and just dead loops. They can be
220 *    overwritten by other handlers */
221    .macro    def_irq_handler    handler_name
222    .weak_definition    \handler_name
223    .set    \handler_name, Default_Handler
224    .endm
225
226    def_irq_handler    NMI_Handler
227
228    def_fault_Handler  HardFault_Handler
229
230    def_irq_handler    SVC_Handler
231    def_irq_handler    PendSV_Handler
232    def_irq_handler    SysTick_Handler
233
234    def_irq_handler  NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
235    def_irq_handler  NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
236    def_irq_handler  NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
237    def_irq_handler  NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
238    def_irq_handler  NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
239    def_irq_handler  NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
240    def_irq_handler  NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
241    def_irq_handler  NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
242    def_irq_handler  Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
243    def_irq_handler  Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
244    def_irq_handler  Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
245    def_irq_handler  Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
246    def_irq_handler  Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
247    def_irq_handler  Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
248    def_irq_handler  Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
249    def_irq_handler  Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
250
251    .end
252
253
254/* [] END OF FILE */
255