1/**************************************************************************//** 2 * @file startup_psoc6_01_cm0plus.S 3 * @brief CMSIS Core Device Startup File for 4 * ARMCM0plus Device Series 5 * @version V5.00 6 * @date 02. March 2016 7 ******************************************************************************/ 8/* 9 * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 /* Address of the NMI handler */ 27 #define CY_NMI_HANLDER_ADDR 0x0000000D 28 29 /* The CPU VTOR register */ 30 #define CY_CPU_VTOR_ADDR 0xE000ED08 31 32 .syntax unified 33 34 .section __STACK, __stack 35 .align 3 36#ifdef __STACK_SIZE 37 .equ Stack_Size, __STACK_SIZE 38#else 39 .equ Stack_Size, 0x00001000 40#endif 41 .globl __StackTop 42 .globl __StackLimit 43 44__StackLimit: 45 .space Stack_Size 46 .equ __StackTop, . - Stack_Size 47 48 .section __HEAP, __heap 49 .align 3 50#ifdef __HEAP_SIZE 51 .equ Heap_Size, __HEAP_SIZE 52#else 53 .equ Heap_Size, 0x00000400 54#endif 55 .globl __HeapBase 56__HeapBase: 57 .if Heap_Size 58 .space Heap_Size 59 .endif 60 61 .section __VECT, ___Vectors 62 .align 2 63 .globl ___Vectors 64___Vectors: 65 .long __StackTop /* Top of Stack */ 66 .long Reset_Handler /* Reset Handler */ 67 .long CY_NMI_HANLDER_ADDR /* NMI Handler */ 68 .long HardFault_Handler /* Hard Fault Handler */ 69 .long 0 /* Reserved */ 70 .long 0 /* Reserved */ 71 .long 0 /* Reserved */ 72 .long 0 /* Reserved */ 73 .long 0 /* Reserved */ 74 .long 0 /* Reserved */ 75 .long 0 /* Reserved */ 76 .long SVC_Handler /* SVCall Handler */ 77 .long 0 /* Reserved */ 78 .long 0 /* Reserved */ 79 .long PendSV_Handler /* PendSV Handler */ 80 .long SysTick_Handler /* SysTick Handler */ 81 82 /* External interrupts Description */ 83 .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ 84 .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ 85 .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ 86 .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ 87 .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ 88 .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ 89 .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ 90 .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ 91 .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ 92 .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ 93 .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ 94 .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ 95 .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ 96 .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ 97 .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ 98 .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ 99 .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ 100 .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ 101 .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ 102 .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ 103 .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ 104 .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ 105 .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ 106 .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ 107 .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ 108 .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ 109 .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ 110 .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ 111 .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ 112 .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ 113 .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ 114 .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ 115 116 .equ __VectorsSize, . - ___Vectors 117 118 .section __RAMVECTORS, ___ramVectors 119 .align 2 120 .globl ___ramVectors 121 122___ramVectors: 123 .space __VectorsSize 124 125 126 .text 127 .thumb_func 128 .align 2 129 /* Reset handler */ 130 .globl Reset_Handler 131 132Reset_Handler: 133 bl Cy_OnResetUser 134 cpsid i 135 136/* Single section scheme. 137 * 138 * The ranges of copy from/to are specified by following symbols 139 * __etext: LMA of start of the section to copy from. Usually end of text 140 * __data_start__: VMA of start of the section to copy to 141 * __data_end__: VMA of end of the section to copy to 142 * 143 * All addresses must be aligned to 4 bytes boundary. 144 */ 145 ldr r0, =___ramVectors 146 ldr r1, =___Vectors 147 ldr r2, =__VectorsSize 148 bl _memcpy 149 150 ldr r0, =segment$start$__DATA 151 ldr r1, =segment$end$__TEXT 152 ldr r2, =section$start$__DATA$__zerofill 153 sub r2, r0 154 bl _memcpy 155 156 ldr r0, =section$start$__DATA$__zerofill 157 eor r1, r1 158 ldr r2, =section$end$__DATA$__zerofill 159 sub r2, r0 160 bl _memset 161 162 /* Update Vector Table Offset Register. */ 163 ldr r0, =___ramVectors 164 ldr r1, =CY_CPU_VTOR_ADDR 165 str r0, [r1] 166 dsb 0xF 167 168 bl _HeapInit 169#ifndef __NO_SYSTEM_INIT 170 bl _SystemInit 171#endif 172 173 bl _main 174 175 /* Should never get here */ 176 b . 177 178 .pool 179 180 .text 181 .thumb 182 .thumb_func 183 .align 2 184 185 /* Device startup customization */ 186 .weak_definition Cy_OnResetUser 187 .global Cy_OnResetUser, Cy_OnResetUser 188Cy_OnResetUser: 189 bx lr 190 191 .text 192 .align 1 193 .thumb_func 194 .weak_reference Default_Handler 195 196Default_Handler: 197 b . 198 199 .text 200 .thumb_func 201 .align 2 202 .weak_definition Cy_SysLib_FaultHandler 203 204Cy_SysLib_FaultHandler: 205 b . 206 207 .text 208 .thumb_func 209 .align 2 210 211Fault_Handler: 212 /* Storing LR content for Creator call stack trace */ 213 push {LR} 214 movs r0, #4 215 mov r1, LR 216 tst r0, r1 217 beq .L_MSP 218 mrs r0, PSP 219 b .L_API_call 220.L_MSP: 221 mrs r0, MSP 222 /* Compensation of stack pointer address due to pushing 4 bytes of LR */ 223 adds r0, r0, #4 224 nop 225.L_API_call: 226 bl Cy_SysLib_FaultHandler 227 b . 228 229.macro def_fault_Handler fault_handler_name 230 .weak_definition \fault_handler_name 231 .set \fault_handler_name, Fault_Handler 232 .endm 233 234/* Macro to define default handlers. Default handler 235 * will be weak symbol and just dead loops. They can be 236 * overwritten by other handlers */ 237 .macro def_irq_handler handler_name 238 .weak_definition \handler_name 239 .set \handler_name, Default_Handler 240 .endm 241 242 def_irq_handler NMI_Handler 243 244 def_fault_Handler HardFault_Handler 245 246 def_irq_handler SVC_Handler 247 def_irq_handler PendSV_Handler 248 def_irq_handler SysTick_Handler 249 250 def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ 251 def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ 252 def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ 253 def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ 254 def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ 255 def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ 256 def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ 257 def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ 258 def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ 259 def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ 260 def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ 261 def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ 262 def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ 263 def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ 264 def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ 265 def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ 266 def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ 267 def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ 268 def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ 269 def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ 270 def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ 271 def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ 272 def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ 273 def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ 274 def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ 275 def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ 276 def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ 277 def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ 278 def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ 279 def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ 280 def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ 281 def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ 282 283 .end 284 285 286/* [] END OF FILE */ 287