1# Parameters: 2# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] 3#---------------------------------------------------------------------------------------------- 4cpu0.CFGITCMSZ=11 5cpu0.CFGDTCMSZ=11 6mps3_board.visualisation.disable-visualisation=1 7# (bool , init-time) default = '0' : Enable/disable visualisation 8cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support 9cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included 10cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. 11#cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] 12#cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls 13#cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] 14#cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] 15#cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] 16#cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] 17#cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. 18#cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] 19#cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] 20#cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included 21#cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] 22#cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] 23#idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : 24#cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write 25#cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write 26#cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write 27#cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included 28#cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included 29mps3_board.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic 30mps3_board.sse300.iotss3_systemcontrol.INITSVTOR_RST=0x70000000 31#---------------------------------------------------------------------------------------------- 32
