1 /* 2 * Copyright (c) 2016-2020 Nordic Semiconductor ASA 3 * Copyright (c) 2016 Vinayak Kariappa Chettimada 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #if defined(CONFIG_BT_CTLR_DEBUG_PINS) || \ 9 defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) 10 #if defined(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP) || \ 11 defined(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP_NS) || \ 12 defined(CONFIG_BOARD_NRF5340DK_NRF5340_CPUNET) 13 #define DEBUG_PORT NRF_P1 14 #define DEBUG_PIN_IDX0 0 15 #define DEBUG_PIN_IDX1 1 16 #define DEBUG_PIN_IDX2 4 17 #define DEBUG_PIN_IDX3 5 18 #define DEBUG_PIN_IDX4 6 19 #define DEBUG_PIN_IDX5 7 20 #define DEBUG_PIN_IDX6 8 21 #define DEBUG_PIN_IDX7 9 22 #define DEBUG_PIN_IDX8 10 23 #define DEBUG_PIN_IDX9 11 24 #define DEBUG_PIN0 BIT(DEBUG_PIN_IDX0) 25 #define DEBUG_PIN1 BIT(DEBUG_PIN_IDX1) 26 #define DEBUG_PIN2 BIT(DEBUG_PIN_IDX2) 27 #define DEBUG_PIN3 BIT(DEBUG_PIN_IDX3) 28 #define DEBUG_PIN4 BIT(DEBUG_PIN_IDX4) 29 #define DEBUG_PIN5 BIT(DEBUG_PIN_IDX5) 30 #define DEBUG_PIN6 BIT(DEBUG_PIN_IDX6) 31 #define DEBUG_PIN7 BIT(DEBUG_PIN_IDX7) 32 #define DEBUG_PIN8 BIT(DEBUG_PIN_IDX8) 33 #define DEBUG_PIN9 BIT(DEBUG_PIN_IDX9) 34 #if defined(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP) || \ 35 (defined(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP_NS) && defined(CONFIG_BUILD_WITH_TFM)) 36 #include <soc_secure.h> 37 #define DEBUG_SETUP() \ 38 do { \ 39 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX0, NRF_GPIO_PIN_SEL_NETWORK); \ 40 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX1, NRF_GPIO_PIN_SEL_NETWORK); \ 41 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX2, NRF_GPIO_PIN_SEL_NETWORK); \ 42 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX3, NRF_GPIO_PIN_SEL_NETWORK); \ 43 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX4, NRF_GPIO_PIN_SEL_NETWORK); \ 44 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX5, NRF_GPIO_PIN_SEL_NETWORK); \ 45 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX6, NRF_GPIO_PIN_SEL_NETWORK); \ 46 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX7, NRF_GPIO_PIN_SEL_NETWORK); \ 47 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX8, NRF_GPIO_PIN_SEL_NETWORK); \ 48 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX9, NRF_GPIO_PIN_SEL_NETWORK); \ 49 } while (0) 50 #endif /* CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP */ 51 #elif defined(CONFIG_BOARD_NRF52840DK_NRF52840) || \ 52 defined(CONFIG_BOARD_NRF52833DK_NRF52833) 53 #define DEBUG_PORT NRF_P1 54 #define DEBUG_PIN0 BIT(1) 55 #define DEBUG_PIN1 BIT(2) 56 #define DEBUG_PIN2 BIT(3) 57 #define DEBUG_PIN3 BIT(4) 58 #define DEBUG_PIN4 BIT(5) 59 #define DEBUG_PIN5 BIT(6) 60 #define DEBUG_PIN6 BIT(7) 61 #define DEBUG_PIN7 BIT(8) 62 #define DEBUG_PIN8 BIT(10) 63 #define DEBUG_PIN9 BIT(11) 64 #elif defined(CONFIG_BOARD_NRF52DK_NRF52832) || \ 65 defined(CONFIG_BOARD_NRF52DK_NRF52810) 66 #define DEBUG_PORT NRF_GPIO 67 #define DEBUG_PIN0 BIT(11) 68 #define DEBUG_PIN1 BIT(12) 69 #define DEBUG_PIN2 BIT(13) 70 #define DEBUG_PIN3 BIT(14) 71 #define DEBUG_PIN4 BIT(15) 72 #define DEBUG_PIN5 BIT(16) 73 #define DEBUG_PIN6 BIT(17) 74 #define DEBUG_PIN7 BIT(18) 75 #define DEBUG_PIN8 BIT(19) 76 #define DEBUG_PIN9 BIT(20) 77 #elif defined(CONFIG_BOARD_NRF51DK_NRF51422) 78 #define DEBUG_PORT NRF_GPIO 79 #define DEBUG_PIN0 BIT(12) 80 #define DEBUG_PIN1 BIT(13) 81 #define DEBUG_PIN2 BIT(14) 82 #define DEBUG_PIN3 BIT(15) 83 #define DEBUG_PIN4 BIT(16) 84 #define DEBUG_PIN5 BIT(17) 85 #define DEBUG_PIN6 BIT(18) 86 #define DEBUG_PIN7 BIT(19) 87 #define DEBUG_PIN8 BIT(20) 88 #define DEBUG_PIN9 BIT(23) 89 #else 90 #error BT_CTLR_DEBUG_PINS not supported on this board. 91 #endif 92 93 #define DEBUG_PIN_MASK (DEBUG_PIN0 | DEBUG_PIN1 | DEBUG_PIN2 | DEBUG_PIN3 | \ 94 DEBUG_PIN4 | DEBUG_PIN5 | DEBUG_PIN6 | DEBUG_PIN7 | \ 95 DEBUG_PIN8 | DEBUG_PIN9) 96 #define DEBUG_CLOSE_MASK (DEBUG_PIN3 | DEBUG_PIN4 | DEBUG_PIN5 | DEBUG_PIN6) 97 98 /* below are some interesting macros referenced by controller 99 * which can be defined to SoC's GPIO toggle to observe/debug the 100 * controller's runtime behavior. 101 */ 102 #define DEBUG_INIT() \ 103 do { \ 104 DEBUG_PORT->DIRSET = DEBUG_PIN_MASK; \ 105 DEBUG_PORT->OUTCLR = DEBUG_PIN_MASK; \ 106 } while (0) 107 108 #define DEBUG_CPU_SLEEP(flag) \ 109 do { \ 110 if (flag) { \ 111 DEBUG_PORT->OUTSET = DEBUG_PIN0; \ 112 DEBUG_PORT->OUTCLR = DEBUG_PIN0; \ 113 } else { \ 114 DEBUG_PORT->OUTCLR = DEBUG_PIN0; \ 115 DEBUG_PORT->OUTSET = DEBUG_PIN0; \ 116 } \ 117 } while (0) 118 119 #define DEBUG_TICKER_ISR(flag) \ 120 do { \ 121 if (flag) { \ 122 DEBUG_PORT->OUTCLR = DEBUG_PIN1; \ 123 DEBUG_PORT->OUTSET = DEBUG_PIN1; \ 124 } else { \ 125 DEBUG_PORT->OUTSET = DEBUG_PIN1; \ 126 DEBUG_PORT->OUTCLR = DEBUG_PIN1; \ 127 } \ 128 } while (0) 129 130 #define DEBUG_TICKER_TASK(flag) \ 131 do { \ 132 if (flag) { \ 133 DEBUG_PORT->OUTCLR = DEBUG_PIN1; \ 134 DEBUG_PORT->OUTSET = DEBUG_PIN1; \ 135 } else { \ 136 DEBUG_PORT->OUTSET = DEBUG_PIN1; \ 137 DEBUG_PORT->OUTCLR = DEBUG_PIN1; \ 138 } \ 139 } while (0) 140 141 #define DEBUG_TICKER_JOB(flag) \ 142 do { \ 143 if (flag) { \ 144 DEBUG_PORT->OUTCLR = DEBUG_PIN2; \ 145 DEBUG_PORT->OUTSET = DEBUG_PIN2; \ 146 } else { \ 147 DEBUG_PORT->OUTSET = DEBUG_PIN2; \ 148 DEBUG_PORT->OUTCLR = DEBUG_PIN2; \ 149 } \ 150 } while (0) 151 152 #define DEBUG_RADIO_ISR(flag) \ 153 do { \ 154 if (flag) { \ 155 DEBUG_PORT->OUTCLR = DEBUG_PIN7; \ 156 DEBUG_PORT->OUTSET = DEBUG_PIN7; \ 157 } else { \ 158 DEBUG_PORT->OUTSET = DEBUG_PIN7; \ 159 DEBUG_PORT->OUTCLR = DEBUG_PIN7; \ 160 } \ 161 } while (0) 162 163 #define DEBUG_RADIO_XTAL(flag) \ 164 do { \ 165 if (flag) { \ 166 DEBUG_PORT->OUTCLR = DEBUG_PIN8; \ 167 DEBUG_PORT->OUTSET = DEBUG_PIN8; \ 168 } else { \ 169 DEBUG_PORT->OUTSET = DEBUG_PIN8; \ 170 DEBUG_PORT->OUTCLR = DEBUG_PIN8; \ 171 } \ 172 } while (0) 173 174 #define DEBUG_RADIO_ACTIVE(flag) \ 175 do { \ 176 if (flag) { \ 177 DEBUG_PORT->OUTCLR = DEBUG_PIN9; \ 178 DEBUG_PORT->OUTSET = DEBUG_PIN9; \ 179 } else { \ 180 DEBUG_PORT->OUTSET = DEBUG_PIN9; \ 181 DEBUG_PORT->OUTCLR = DEBUG_PIN9; \ 182 } \ 183 } while (0) 184 185 #define DEBUG_RADIO_CLOSE(flag) \ 186 do { \ 187 if (flag) { \ 188 DEBUG_PORT->OUTCLR = 0x00000000; \ 189 DEBUG_PORT->OUTSET = 0x00000000; \ 190 } else { \ 191 DEBUG_PORT->OUTCLR = DEBUG_CLOSE_MASK; \ 192 } \ 193 } while (0) 194 195 #define DEBUG_RADIO_PREPARE_A(flag) \ 196 do { \ 197 if (flag) { \ 198 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 199 DEBUG_PORT->OUTSET = DEBUG_PIN3; \ 200 } else { \ 201 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 202 DEBUG_PORT->OUTSET = DEBUG_PIN3; \ 203 } \ 204 } while (0) 205 206 #define DEBUG_RADIO_START_A(flag) \ 207 do { \ 208 if (flag) { \ 209 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 210 DEBUG_PORT->OUTSET = DEBUG_PIN3; \ 211 } else { \ 212 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 213 DEBUG_PORT->OUTSET = DEBUG_PIN3; \ 214 } \ 215 } while (0) 216 217 #define DEBUG_RADIO_CLOSE_A(flag) \ 218 do { \ 219 if (flag) { \ 220 DEBUG_PORT->OUTCLR = 0x00000000; \ 221 DEBUG_PORT->OUTSET = 0x00000000; \ 222 } else { \ 223 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 224 } \ 225 } while (0) 226 227 #define DEBUG_RADIO_PREPARE_S(flag) \ 228 do { \ 229 if (flag) { \ 230 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 231 DEBUG_PORT->OUTSET = DEBUG_PIN4; \ 232 } else { \ 233 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 234 DEBUG_PORT->OUTSET = DEBUG_PIN4; \ 235 } \ 236 } while (0) 237 238 #define DEBUG_RADIO_START_S(flag) \ 239 do { \ 240 if (flag) { \ 241 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 242 DEBUG_PORT->OUTSET = DEBUG_PIN4; \ 243 } else { \ 244 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 245 DEBUG_PORT->OUTSET = DEBUG_PIN4; \ 246 } \ 247 } while (0) 248 249 #define DEBUG_RADIO_CLOSE_S(flag) \ 250 do { \ 251 if (flag) { \ 252 DEBUG_PORT->OUTCLR = 0x00000000; \ 253 DEBUG_PORT->OUTSET = 0x00000000; \ 254 } else { \ 255 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 256 } \ 257 } while (0) 258 259 #define DEBUG_RADIO_PREPARE_O(flag) \ 260 do { \ 261 if (flag) { \ 262 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 263 DEBUG_PORT->OUTSET = DEBUG_PIN5; \ 264 } else { \ 265 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 266 DEBUG_PORT->OUTSET = DEBUG_PIN5; \ 267 } \ 268 } while (0) 269 270 #define DEBUG_RADIO_START_O(flag) \ 271 do { \ 272 if (flag) { \ 273 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 274 DEBUG_PORT->OUTSET = DEBUG_PIN5; \ 275 } else { \ 276 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 277 DEBUG_PORT->OUTSET = DEBUG_PIN5; \ 278 } \ 279 } while (0) 280 281 #define DEBUG_RADIO_CLOSE_O(flag) \ 282 do { \ 283 if (flag) { \ 284 DEBUG_PORT->OUTCLR = 0x00000000; \ 285 DEBUG_PORT->OUTSET = 0x00000000; \ 286 } else { \ 287 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 288 } \ 289 } while (0) 290 291 #define DEBUG_RADIO_PREPARE_M(flag) \ 292 do { \ 293 if (flag) { \ 294 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 295 DEBUG_PORT->OUTSET = DEBUG_PIN6; \ 296 } else { \ 297 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 298 DEBUG_PORT->OUTSET = DEBUG_PIN6; \ 299 } \ 300 } while (0) 301 302 #define DEBUG_RADIO_START_M(flag) \ 303 do { \ 304 if (flag) { \ 305 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 306 DEBUG_PORT->OUTSET = DEBUG_PIN6; \ 307 } else { \ 308 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 309 DEBUG_PORT->OUTSET = DEBUG_PIN6; \ 310 } \ 311 } while (0) 312 313 #define DEBUG_RADIO_CLOSE_M(flag) \ 314 do { \ 315 if (flag) { \ 316 DEBUG_PORT->OUTCLR = 0x00000000; \ 317 DEBUG_PORT->OUTSET = 0x00000000; \ 318 } else { \ 319 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 320 } \ 321 } while (0) 322 323 #else 324 #define DEBUG_INIT() 325 #define DEBUG_CPU_SLEEP(flag) 326 #define DEBUG_TICKER_ISR(flag) 327 #define DEBUG_TICKER_TASK(flag) 328 #define DEBUG_TICKER_JOB(flag) 329 #define DEBUG_RADIO_ISR(flag) 330 #define DEBUG_RADIO_HCTO(flag) 331 #define DEBUG_RADIO_XTAL(flag) 332 #define DEBUG_RADIO_ACTIVE(flag) 333 #define DEBUG_RADIO_CLOSE(flag) 334 #define DEBUG_RADIO_PREPARE_A(flag) 335 #define DEBUG_RADIO_START_A(flag) 336 #define DEBUG_RADIO_CLOSE_A(flag) 337 #define DEBUG_RADIO_PREPARE_S(flag) 338 #define DEBUG_RADIO_START_S(flag) 339 #define DEBUG_RADIO_CLOSE_S(flag) 340 #define DEBUG_RADIO_PREPARE_O(flag) 341 #define DEBUG_RADIO_START_O(flag) 342 #define DEBUG_RADIO_CLOSE_O(flag) 343 #define DEBUG_RADIO_PREPARE_M(flag) 344 #define DEBUG_RADIO_START_M(flag) 345 #define DEBUG_RADIO_CLOSE_M(flag) 346 #endif /* CONFIG_BT_CTLR_DEBUG_PINS */ 347 348 #if defined(CONFIG_BT_CTLR_DEBUG_PINS) || \ 349 defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) 350 #define DEBUG_COEX_PORT NRF_P1 351 #define DEBUG_COEX_PIN_GRANT BIT(12) 352 #define DEBUG_COEX_PIN_IRQ BIT(13) 353 #define DEBUG_COEX_PIN_MASK (DEBUG_COEX_PIN_IRQ | DEBUG_COEX_PIN_GRANT) 354 #define DEBUG_COEX_INIT() \ 355 do { \ 356 DEBUG_COEX_PORT->DIRSET = DEBUG_COEX_PIN_MASK; \ 357 DEBUG_COEX_PORT->OUTCLR = DEBUG_COEX_PIN_MASK; \ 358 } while (0) 359 360 #define DEBUG_COEX_GRANT(flag) \ 361 do { \ 362 if (flag) { \ 363 DEBUG_COEX_PORT->OUTSET = DEBUG_COEX_PIN_GRANT; \ 364 } else { \ 365 DEBUG_COEX_PORT->OUTCLR = DEBUG_COEX_PIN_GRANT; \ 366 } \ 367 } while (0) 368 369 370 #define DEBUG_COEX_IRQ(flag) \ 371 do { \ 372 if (flag) { \ 373 DEBUG_COEX_PORT->OUTSET = DEBUG_COEX_PIN_IRQ; \ 374 } else { \ 375 DEBUG_COEX_PORT->OUTCLR = DEBUG_COEX_PIN_IRQ; \ 376 } \ 377 } while (0) 378 #else 379 #define DEBUG_COEX_INIT() 380 #define DEBUG_COEX_GRANT(flag) 381 #define DEBUG_COEX_IRQ(flag) 382 #endif /* CONFIG_BT_CTLR_DEBUG_PINS */ 383
