1 /*******************************************************************************
2  * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * MPFS HAL Embedded Software
7  *
8  */
9 
10 /*******************************************************************************
11  * @file mss_nwc_init.h
12  * @author Microchip-FPGA Embedded Systems Solutions
13  * @brief defines for mss_nwc_init.c
14  *
15  */
16 
17 /*=========================================================================*//**
18   @page MPFS MSS NWC configuration
19   ==============================================================================
20   @section intro_sec Introduction
21   ==============================================================================
22   The MPFS microcontroller subsystem (MSS) includes a number of hard core
23   components physically located in the north west corner of the MSS on the die.
24 
25   ==============================================================================
26   @section Items located in the north west corner
27   ==============================================================================
28   MSS PLL
29   SGMII
30   DDR phy
31   MSSIO
32 
33   ==============================================================================
34   @section Flow diagram
35   ==============================================================================
36   todo: remove, added line here as test *****
37   Simplified flow diagram
38                               +-----------------+
39                               |     start       |
40                               |  NWC setup      |
41                               +-------+---------+
42                                       v
43                               +-----------------+
44                               |   set SCB access|
45                               |   Parameters    |
46                               +-------+---------+
47                                       |
48                               +-------v---------+
49                               | Release APB NWC |
50                               | Turn on APB clk |
51                               +-------+---------+
52                                       |
53                               +-------v---------+
54                               | Set Dynamic     |
55                               | enable bits     |
56                               +-------++--------+
57                                       |
58                               +-------v---------+
59                               | Setup signals   |
60                               | DCE,CORE_UP,    |
61                               | Flash_Valid,    |
62                               | MSS_IO_EN       |
63                               +-------+---------+
64                                       |
65                               +-------v---------+
66                               | Setup SGMII     |
67                               |                 |
68                               +-------+---------+
69                                       |
70                               +-------v---------+
71                               | Setup DDR       |
72                               |                 |
73                               +-------+---------+
74                                       |
75                               +-------v---------+
76                               | Setup MSSIO     |
77                               |                 |
78                               +-------+---------+
79                                       |
80                               +-------v---------+
81                               |    Finished     |
82                               +-----------------+
83 
84  *//*=========================================================================*/
85 #ifndef __MSS_NWC_INIT_H_
86 #define __MSS_NWC_INIT_H_ 1
87 
88 
89 #include <stddef.h>
90 #include <stdint.h>
91 
92 
93 #ifdef __cplusplus
94 extern "C" {
95 #endif
96 
97 
98 /***************************************************************************//**
99   MSS_SCB_ACCESS_CONFIG_ON_RESET
100 
101   SCB access settings on reset.
102   Bits 15:8 Sets how long SCB request is held active after SCB bus granted.
103   Allows SCB bus master-ship to maintained across multiple SCB access
104   cycles
105   Bits 7:0 Set the timeout for an SCB access in CPU cycles.
106 
107   Note: These settings are used even after we change the MSS clock from SCB
108   80MHz default setting. todo: This needs to be confirmed as OK, there will be
109   no potential timing issues:
110   Min 143 Hclk cycles for simulation set-up, making 160
111   todo: review setting
112   */
113 
114 #define MSS_SCB_ACCESS_CONFIG   ((160UL<<8U)|(0x80U))
115 
116 
117 /***************************************************************************//**
118   mss_nwc_init()
119   Called on start-up, initializes clocks, sgmii, ddr, mssio
120  */
121 uint8_t
122 mss_nwc_init
123 (
124     void
125 );
126 
127 
128 /***************************************************************************//**
129   mtime_delay(x) delay function, passes microseconds
130   waits x microseconds
131   Assumption 1 is we have ensured clock is 1MHz
132   Assumption 2 is we have not setup tick timer when using this function. It is
133   only used by the startup code.
134 
135   Example:
136   @code
137 
138       mtime_delay(100UL);
139 
140   @endcode
141 
142  */
143 void
144 mtime_delay
145 (
146     uint32_t microseconds
147 );
148 
149 
150 #ifdef __cplusplus
151 }
152 #endif
153 
154 #endif /* __MSS_DDRC_H_ */
155 
156 
157