1 /**************************************************************************//**
2 * @file cmsis_armclang_r.h
3 * @brief CMSIS compiler armclang (Arm Compiler 6) header file
4 * @version V6.0.0
5 * @date 04. December 2024
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef __CMSIS_ARMCLANG_R_H
26 #define __CMSIS_ARMCLANG_R_H
27
28 #pragma clang system_header /* treat file as system include file */
29
30 #ifndef __CMSIS_ARMCLANG_H
31 #error "This file must not be included directly"
32 #endif
33
34
35 /* ########################### Core Function Access ########################### */
36 /** \ingroup CMSIS_Core_FunctionInterface
37 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
38 @{
39 */
40
41 /** \brief Get CPSR Register
42 \return CPSR Register value
43 */
__get_CPSR(void)44 __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
45 {
46 uint32_t result;
47 __ASM volatile("MRS %0, cpsr" : "=r" (result) );
48 return(result);
49 }
50
51 /** \brief Set CPSR Register
52 \param [in] cpsr CPSR value to set
53 */
__set_CPSR(uint32_t cpsr)54 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
55 {
56 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
57 }
58
59 /** \brief Get Mode
60 \return Processor Mode
61 */
__get_mode(void)62 __STATIC_FORCEINLINE uint32_t __get_mode(void)
63 {
64 return (__get_CPSR() & 0x1FU);
65 }
66
67 /** \brief Set Mode
68 \param [in] mode Mode value to set
69 */
__set_mode(uint32_t mode)70 __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
71 {
72 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
73 }
74
75 /** \brief Get Stack Pointer
76 \return Stack Pointer value
77 */
__get_SP(void)78 __STATIC_FORCEINLINE uint32_t __get_SP(void)
79 {
80 uint32_t result;
81 __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
82 return result;
83 }
84
85 /** \brief Set Stack Pointer
86 \param [in] stack Stack Pointer value to set
87 */
__set_SP(uint32_t stack)88 __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
89 {
90 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
91 }
92
93 /** \brief Get USR/SYS Stack Pointer
94 \return USR/SYS Stack Pointer value
95 */
__get_SP_usr(void)96 __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
97 {
98 uint32_t cpsr;
99 uint32_t result;
100 __ASM volatile(
101 "MRS %0, cpsr \n"
102 "CPS #0x1F \n" // no effect in USR mode
103 "MOV %1, sp \n"
104 "MSR cpsr_c, %0 \n" // no effect in USR mode
105 "ISB" : "=r"(cpsr), "=r"(result) : : "memory"
106 );
107 return result;
108 }
109
110 /** \brief Set USR/SYS Stack Pointer
111 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
112 */
__set_SP_usr(uint32_t topOfProcStack)113 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
114 {
115 uint32_t cpsr;
116 __ASM volatile(
117 "MRS %0, cpsr \n"
118 "CPS #0x1F \n" // no effect in USR mode
119 "MOV sp, %1 \n"
120 "MSR cpsr_c, %0 \n" // no effect in USR mode
121 "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
122 );
123 }
124
125 /** \brief Get FPEXC
126 \return Floating Point Exception Control register value
127 */
__get_FPEXC(void)128 __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
129 {
130 #if (__FPU_PRESENT == 1)
131 uint32_t result;
132 __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
133 return(result);
134 #else
135 return(0);
136 #endif
137 }
138
139 /** \brief Set FPEXC
140 \param [in] fpexc Floating Point Exception Control value to set
141 */
__set_FPEXC(uint32_t fpexc)142 __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
143 {
144 #if (__FPU_PRESENT == 1)
145 __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
146 #endif
147 }
148
149 /** @} end of CMSIS_Core_RegAccFunctions */
150
151
152 /*
153 * Include common core functions to access Coprocessor 15 registers
154 */
155
156 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
157 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
158 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
159 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
160
161 #endif /* __CMSIS_ARMCLANG_R_H */
162
