1 /*
2 * Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
3 * Copyright (c) 2018 Intel Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/ztest.h>
9 #include <zephyr/interrupt_util.h>
10
11 /*
12 * Run the nested interrupt test for the supported platforms only.
13 */
14 #if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_ARC) || \
15 defined(CONFIG_GIC) || defined(CONFIG_NRFX_CLIC)
16 #define TEST_NESTED_ISR
17 #endif
18
19 #define DURATION 5
20
21 #define ISR0_TOKEN 0xDEADBEEF
22 #define ISR1_TOKEN 0xCAFEBABE
23
24 /*
25 * This test uses two IRQ lines selected within the range of available IRQs on
26 * the target SoC. These IRQs are platform and interrupt controller-specific,
27 * and must be specified for every supported platform.
28 *
29 * In terms of priority, the IRQ1 is triggered from the ISR of the IRQ0;
30 * therefore, the priority of IRQ1 must be greater than that of the IRQ0.
31 */
32 #if defined(CONFIG_CPU_CORTEX_M)
33 /*
34 * For Cortex-M NVIC, unused and available IRQs are automatically detected when
35 * the test is run.
36 *
37 * The IRQ priorities start at 1 because the priority 0 is reserved for the
38 * SVCall exception and Zero-Latency IRQs (see `_EXCEPTION_RESERVED_PRIO`).
39 */
40 #define IRQ0_PRIO 2
41 #define IRQ1_PRIO 1
42 #elif defined(CONFIG_GIC)
43 /*
44 * For the platforms that use the ARM GIC, use the SGI (software generated
45 * interrupt) lines 14 and 15 for testing.
46 */
47 #define IRQ0_LINE 14
48 #define IRQ1_LINE 15
49
50 /*
51 * Choose lower prio for IRQ0 and higher priority for IRQ1
52 * Minimum legal value of GICC BPR is '3' ie <gggg.ssss>
53 * Hence choosing default priority and highest possible priority
54 * '0x0' as the priorities so that the preemption rule applies
55 * generically to all GIC versions and security states.
56 */
57 #define IRQ0_PRIO IRQ_DEFAULT_PRIORITY
58 #define IRQ1_PRIO 0x0
59 #elif defined(CONFIG_SOC_SERIES_NRF54LX) && defined(CONFIG_RISCV_CORE_NORDIC_VPR)
60 #define IRQ0_LINE 16
61 #define IRQ1_LINE 17
62
63 #define IRQ0_PRIO 1
64 #define IRQ1_PRIO 2
65 #elif defined(CONFIG_SOC_NRF54H20_CPUPPR)
66 #define IRQ0_LINE 14
67 #define IRQ1_LINE 15
68
69 #define IRQ0_PRIO 1
70 #define IRQ1_PRIO 2
71 #else
72 /*
73 * For all the other platforms, use the last two available IRQ lines for
74 * testing.
75 */
76 #define IRQ0_LINE (CONFIG_NUM_IRQS - 1)
77 #define IRQ1_LINE (CONFIG_NUM_IRQS - 2)
78
79 #define IRQ0_PRIO 1
80 #define IRQ1_PRIO 0
81 #endif
82
83 #ifdef TEST_NESTED_ISR
84 static uint32_t irq_line_0;
85 static uint32_t irq_line_1;
86
87 static uint32_t isr0_result;
88 static uint32_t isr1_result;
89
isr1(const void * param)90 void isr1(const void *param)
91 {
92 ARG_UNUSED(param);
93
94 printk("isr1: Enter\n");
95
96 /* Set verification token */
97 isr1_result = ISR1_TOKEN;
98
99 printk("isr1: Leave\n");
100 }
101
isr0(const void * param)102 void isr0(const void *param)
103 {
104 ARG_UNUSED(param);
105
106 printk("isr0: Enter\n");
107
108 /* Set verification token */
109 isr0_result = ISR0_TOKEN;
110
111 /* Trigger nested IRQ 1 */
112 trigger_irq(irq_line_1);
113
114 /* Wait for interrupt */
115 k_busy_wait(MS_TO_US(DURATION));
116
117 /* Validate nested ISR result token */
118 zassert_equal(isr1_result, ISR1_TOKEN, "isr1 did not execute");
119
120 printk("isr0: Leave\n");
121 }
122
123 /**
124 * @brief Test interrupt nesting
125 *
126 * @ingroup kernel_interrupt_tests
127 *
128 * This routine tests the interrupt nesting feature, which allows an ISR to be
129 * preempted in mid-execution if a higher priority interrupt is signaled. The
130 * lower priority ISR resumes execution once the higher priority ISR has
131 * completed its processing.
132 *
133 * The expected control flow for this test is as follows:
134 *
135 * 1. [thread] Trigger IRQ 0 (lower priority)
136 * 2. [isr0] Set ISR 0 result token and trigger IRQ 1 (higher priority)
137 * 3. [isr1] Set ISR 1 result token and return
138 * 4. [isr0] Validate ISR 1 result token and return
139 * 5. [thread] Validate ISR 0 result token
140 */
ZTEST(interrupt_feature,test_nested_isr)141 ZTEST(interrupt_feature, test_nested_isr)
142 {
143 /* Resolve test IRQ line numbers */
144 #if defined(CONFIG_CPU_CORTEX_M)
145 irq_line_0 = get_available_nvic_line(CONFIG_NUM_IRQS);
146 irq_line_1 = get_available_nvic_line(irq_line_0);
147 #else
148 irq_line_0 = IRQ0_LINE;
149 irq_line_1 = IRQ1_LINE;
150 #endif
151
152 /* Connect and enable test IRQs */
153 arch_irq_connect_dynamic(irq_line_0, IRQ0_PRIO, isr0, NULL, 0);
154 arch_irq_connect_dynamic(irq_line_1, IRQ1_PRIO, isr1, NULL, 0);
155
156 irq_enable(irq_line_0);
157 irq_enable(irq_line_1);
158
159 /* Trigger test IRQ 0 */
160 trigger_irq(irq_line_0);
161
162 /* Wait for interrupt */
163 k_busy_wait(MS_TO_US(DURATION));
164
165 /* Validate ISR result token */
166 zassert_equal(isr0_result, ISR0_TOKEN, "isr0 did not execute");
167 }
168 #else
ZTEST(interrupt_feature,test_nested_isr)169 ZTEST(interrupt_feature, test_nested_isr)
170 {
171 ztest_test_skip();
172 }
173 #endif /* TEST_NESTED_ISR */
174
