1#  Copyright (C) 2020 Synopsys, Inc.
2#  SPDX-License-Identifier: Apache-2.0
3#
4
5# Configure JTAG cable
6# SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
7# it uses channel B for JTAG, instead of channel A.
8adapter driver ftdi
9
10# Only specify FTDI serial number if it is specified via
11# "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script
12if { [info exists _ZEPHYR_BOARD_SERIAL] } {
13       ftdi_serial $_ZEPHYR_BOARD_SERIAL
14}
15
16ftdi_vid_pid 0x0403 0x6010
17ftdi_layout_init 0x0088 0x008b
18ftdi_channel 1
19
20
21adapter speed 10000
22
23# ARCs supports only JTAG.
24transport select jtag
25
26
27#
28# HS Development Kit SoC.
29#
30# Contains quad-core ARC HS38.
31#
32
33source [find cpu/arc/hs.tcl]
34
35set _coreid 0
36set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
37
38# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
39# OpenOCD is concerned EM and HS are identical.
40set _CHIPNAME arc-em
41
42# OpenOCD discovers JTAG TAPs in reverse order.
43
44set _TARGETNAME4 $_CHIPNAME.cpu4
45jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
46set _TARGETNAME3 $_CHIPNAME.cpu3
47jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
48set _TARGETNAME2 $_CHIPNAME.cpu2
49jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
50set _TARGETNAME1 $_CHIPNAME.cpu1
51jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
52
53################################
54# ARC HS38 core 2
55################################
56
57target create $_TARGETNAME2 arcv2 -chain-position $_TARGETNAME2
58$_TARGETNAME2 configure -coreid $_coreid
59$_TARGETNAME2 configure -dbgbase $_dbgbase
60$_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
61set _coreid [expr $_coreid + 1]
62set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
63arc_hs_init_regs
64
65# Enable L2 cache support for core 2.
66$_TARGETNAME2 arc cache l2 auto 1
67
68################################
69# ARC HS38 core 1
70################################
71
72target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
73$_TARGETNAME1 configure -coreid $_coreid
74$_TARGETNAME1 configure -dbgbase $_dbgbase
75$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
76set _coreid [expr $_coreid + 1]
77set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
78arc_hs_init_regs
79
80# Enable L2 cache support for core 1.
81$_TARGETNAME1 arc cache l2 auto 1
82
83target smp $_TARGETNAME1 $_TARGETNAME2
84
85# vi:ft=tcl
86