1 /*
2 * Copyright (c) 2009-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
21 * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
22 */
23
24 #include "stm32u5xx.h"
25
26 /*----------------------------------------------------------------------------
27 External References
28 *----------------------------------------------------------------------------*/
29 extern uint32_t __INITIAL_SP;
30 extern uint32_t __STACK_LIMIT;
31
32 extern __NO_RETURN void __PROGRAM_START(void);
33
34 /*----------------------------------------------------------------------------
35 Internal References
36 *----------------------------------------------------------------------------*/
37 __NO_RETURN void Reset_Handler (void);
38
39 /*----------------------------------------------------------------------------
40 Exception / Interrupt Handler
41 *----------------------------------------------------------------------------*/
42 #define DEFAULT_IRQ_HANDLER(handler_name) \
43 __NO_RETURN void __WEAK handler_name(void); \
44 void handler_name(void) { \
45 while(1); \
46 }
47
48 /* Exceptions */
49 DEFAULT_IRQ_HANDLER(NMI_Handler)
50 DEFAULT_IRQ_HANDLER(HardFault_Handler)
51 DEFAULT_IRQ_HANDLER(MemManage_Handler)
52 DEFAULT_IRQ_HANDLER(BusFault_Handler)
53 DEFAULT_IRQ_HANDLER(UsageFault_Handler)
54 DEFAULT_IRQ_HANDLER(SecureFault_Handler)
55 DEFAULT_IRQ_HANDLER(SVC_Handler)
56 DEFAULT_IRQ_HANDLER(DebugMon_Handler)
57 DEFAULT_IRQ_HANDLER(PendSV_Handler)
58 DEFAULT_IRQ_HANDLER(SysTick_Handler)
59
60 DEFAULT_IRQ_HANDLER(WWDG_IRQHandler)
61 DEFAULT_IRQ_HANDLER(PVD_AVD_IRQHandler)
62 DEFAULT_IRQ_HANDLER(RTC_IRQHandler)
63 DEFAULT_IRQ_HANDLER(RTC_IRQHandler_S)
64 DEFAULT_IRQ_HANDLER(TAMP_IRQHandler)
65 DEFAULT_IRQ_HANDLER(RAMCFG_IRQHandler)
66 DEFAULT_IRQ_HANDLER(FLASH_IRQHandler)
67 DEFAULT_IRQ_HANDLER(FLASH_IRQHandler_S)
68 DEFAULT_IRQ_HANDLER(GTZC_IRQHandler)
69 DEFAULT_IRQ_HANDLER(RCC_IRQHandler)
70 DEFAULT_IRQ_HANDLER(RCC_IRQHandler_S)
71 DEFAULT_IRQ_HANDLER(EXTI0_IRQHandler)
72 DEFAULT_IRQ_HANDLER(EXTI1_IRQHandler)
73 DEFAULT_IRQ_HANDLER(EXTI2_IRQHandler)
74 DEFAULT_IRQ_HANDLER(EXTI3_IRQHandler)
75 DEFAULT_IRQ_HANDLER(EXTI4_IRQHandler)
76 DEFAULT_IRQ_HANDLER(EXTI5_IRQHandler)
77 DEFAULT_IRQ_HANDLER(EXTI6_IRQHandler)
78 DEFAULT_IRQ_HANDLER(EXTI7_IRQHandler)
79 DEFAULT_IRQ_HANDLER(EXTI8_IRQHandler)
80 DEFAULT_IRQ_HANDLER(EXTI9_IRQHandler)
81 DEFAULT_IRQ_HANDLER(EXTI10_IRQHandler)
82 DEFAULT_IRQ_HANDLER(EXTI11_IRQHandler)
83 DEFAULT_IRQ_HANDLER(EXTI12_IRQHandler)
84 DEFAULT_IRQ_HANDLER(EXTI13_IRQHandler)
85 DEFAULT_IRQ_HANDLER(EXTI14_IRQHandler)
86 DEFAULT_IRQ_HANDLER(EXTI15_IRQHandler)
87 DEFAULT_IRQ_HANDLER(IWDG_IRQHandler)
88 #ifdef STM32U585xx
89 DEFAULT_IRQ_HANDLER(SAES_IRQHandler)
90 #endif
91 DEFAULT_IRQ_HANDLER(GPDMA1_Channel0_IRQHandler)
92 DEFAULT_IRQ_HANDLER(GPDMA1_Channel1_IRQHandler)
93 DEFAULT_IRQ_HANDLER(GPDMA1_Channel2_IRQHandler)
94 DEFAULT_IRQ_HANDLER(GPDMA1_Channel3_IRQHandler)
95 DEFAULT_IRQ_HANDLER(GPDMA1_Channel4_IRQHandler)
96 DEFAULT_IRQ_HANDLER(GPDMA1_Channel5_IRQHandler)
97 DEFAULT_IRQ_HANDLER(GPDMA1_Channel6_IRQHandler)
98 DEFAULT_IRQ_HANDLER(GPDMA1_Channel7_IRQHandler)
99 DEFAULT_IRQ_HANDLER(ADC1_IRQHandler)
100 DEFAULT_IRQ_HANDLER(DAC1_IRQHandler)
101 DEFAULT_IRQ_HANDLER(FDCAN1_IT0_IRQHandler)
102 DEFAULT_IRQ_HANDLER(FDCAN1_IT1_IRQHandler)
103 DEFAULT_IRQ_HANDLER(TIM1_BRK_IRQHandler)
104 DEFAULT_IRQ_HANDLER(TIM1_UP_IRQHandler)
105 DEFAULT_IRQ_HANDLER(TIM1_TRG_COM_IRQHandler)
106 DEFAULT_IRQ_HANDLER(TIM1_CC_IRQHandler)
107 DEFAULT_IRQ_HANDLER(TIM2_IRQHandler)
108 DEFAULT_IRQ_HANDLER(TIM3_IRQHandler)
109 DEFAULT_IRQ_HANDLER(TIM4_IRQHandler)
110 DEFAULT_IRQ_HANDLER(TIM5_IRQHandler)
111 DEFAULT_IRQ_HANDLER(TIM6_IRQHandler)
112 DEFAULT_IRQ_HANDLER(TIM7_IRQHandler)
113 DEFAULT_IRQ_HANDLER(TIM8_BRK_IRQHandler)
114 DEFAULT_IRQ_HANDLER(TIM8_UP_IRQHandler)
115 DEFAULT_IRQ_HANDLER(TIM8_TRG_COM_IRQHandler)
116 DEFAULT_IRQ_HANDLER(TIM8_CC_IRQHandler)
117 DEFAULT_IRQ_HANDLER(I2C1_EV_IRQHandler)
118 DEFAULT_IRQ_HANDLER(I2C1_ER_IRQHandler)
119 DEFAULT_IRQ_HANDLER(I2C2_EV_IRQHandler)
120 DEFAULT_IRQ_HANDLER(I2C2_ER_IRQHandler)
121 DEFAULT_IRQ_HANDLER(SPI1_IRQHandler)
122 DEFAULT_IRQ_HANDLER(SPI2_IRQHandler)
123 DEFAULT_IRQ_HANDLER(USART1_IRQHandler)
124 DEFAULT_IRQ_HANDLER(USART2_IRQHandler)
125 DEFAULT_IRQ_HANDLER(USART3_IRQHandler)
126 DEFAULT_IRQ_HANDLER(UART4_IRQHandler)
127 DEFAULT_IRQ_HANDLER(UART5_IRQHandler)
128 DEFAULT_IRQ_HANDLER(LPUART1_IRQHandler)
129 DEFAULT_IRQ_HANDLER(LPTIM1_IRQHandler)
130 DEFAULT_IRQ_HANDLER(LPTIM2_IRQHandler)
131 DEFAULT_IRQ_HANDLER(TIM15_IRQHandler)
132 DEFAULT_IRQ_HANDLER(TIM16_IRQHandler)
133 DEFAULT_IRQ_HANDLER(TIM17_IRQHandler)
134 DEFAULT_IRQ_HANDLER(COMP_IRQHandler)
135 DEFAULT_IRQ_HANDLER(OTG_FS_IRQHandler)
136 DEFAULT_IRQ_HANDLER(CRS_IRQHandler)
137 DEFAULT_IRQ_HANDLER(FMC_IRQHandler)
138 DEFAULT_IRQ_HANDLER(OCTOSPI1_IRQHandler)
139 DEFAULT_IRQ_HANDLER(PWR_S3WU_IRQHandler)
140 DEFAULT_IRQ_HANDLER(SDMMC1_IRQHandler)
141 DEFAULT_IRQ_HANDLER(SDMMC2_IRQHandler)
142
143 DEFAULT_IRQ_HANDLER(DMA2_Channel1_IRQHandler)
144 DEFAULT_IRQ_HANDLER(GPDMA1_Channel8_IRQHandler)
145 DEFAULT_IRQ_HANDLER(GPDMA1_Channel9_IRQHandler)
146 DEFAULT_IRQ_HANDLER(GPDMA1_Channel10_IRQHandler)
147 DEFAULT_IRQ_HANDLER(GPDMA1_Channel11_IRQHandler)
148 DEFAULT_IRQ_HANDLER(GPDMA1_Channel12_IRQHandler)
149 DEFAULT_IRQ_HANDLER(GPDMA1_Channel13_IRQHandler)
150 DEFAULT_IRQ_HANDLER(GPDMA1_Channel14_IRQHandler)
151 DEFAULT_IRQ_HANDLER(GPDMA1_Channel15_IRQHandler)
152 DEFAULT_IRQ_HANDLER(I2C3_EV_IRQHandler)
153 DEFAULT_IRQ_HANDLER(I2C3_ER_IRQHandler)
154 DEFAULT_IRQ_HANDLER(SAI1_IRQHandler)
155 DEFAULT_IRQ_HANDLER(SAI2_IRQHandler)
156 DEFAULT_IRQ_HANDLER(TSC_IRQHandler)
157 #ifdef STM32U585xx
158 DEFAULT_IRQ_HANDLER(AES_IRQHandler)
159 #endif
160 DEFAULT_IRQ_HANDLER(RNG_IRQHandler)
161 DEFAULT_IRQ_HANDLER(FPU_IRQHandler)
162 DEFAULT_IRQ_HANDLER(HASH_IRQHandler)
163 #ifdef STM32U585xx
164 DEFAULT_IRQ_HANDLER(PKA_IRQHandler)
165 #endif
166 DEFAULT_IRQ_HANDLER(LPTIM3_IRQHandler)
167 DEFAULT_IRQ_HANDLER(SPI3_IRQHandler)
168 DEFAULT_IRQ_HANDLER(I2C4_ER_IRQHandler)
169 DEFAULT_IRQ_HANDLER(I2C4_EV_IRQHandler)
170 DEFAULT_IRQ_HANDLER(MDF1_FLT0_IRQHandler)
171 DEFAULT_IRQ_HANDLER(MDF1_FLT1_IRQHandler)
172 DEFAULT_IRQ_HANDLER(MDF1_FLT2_IRQHandler)
173 DEFAULT_IRQ_HANDLER(MDF1_FLT3_IRQHandler)
174 DEFAULT_IRQ_HANDLER(UCPD1_IRQHandler)
175 DEFAULT_IRQ_HANDLER(ICACHE_IRQHandler)
176 #ifdef STM32U585xx
177 DEFAULT_IRQ_HANDLER(OTFDEC1_IRQHandler)
178 DEFAULT_IRQ_HANDLER(OTFDEC2_IRQHandler)
179 #endif
180 DEFAULT_IRQ_HANDLER(LPTIM4_IRQHandler)
181 DEFAULT_IRQ_HANDLER(DCACHE1_IRQHandler)
182 DEFAULT_IRQ_HANDLER(ADF1_IRQHandler)
183 DEFAULT_IRQ_HANDLER(ADC4_IRQHandler)
184 DEFAULT_IRQ_HANDLER(LPDMA1_Channel0_IRQHandler)
185 DEFAULT_IRQ_HANDLER(LPDMA1_Channel1_IRQHandler)
186 DEFAULT_IRQ_HANDLER(LPDMA1_Channel2_IRQHandler)
187 DEFAULT_IRQ_HANDLER(LPDMA1_Channel3_IRQHandler)
188 DEFAULT_IRQ_HANDLER(DMA2D_IRQHandler)
189 DEFAULT_IRQ_HANDLER(DCMI_PSSI_IRQHandler)
190 DEFAULT_IRQ_HANDLER(OCTOSPI2_IRQHandler)
191 DEFAULT_IRQ_HANDLER(MDF1_FLT4_IRQHandler)
192 DEFAULT_IRQ_HANDLER(MDF1_FLT5_IRQHandler)
193 DEFAULT_IRQ_HANDLER(CORDIC_IRQHandler)
194 DEFAULT_IRQ_HANDLER(FMAC_IRQHandler)
195
196 /*----------------------------------------------------------------------------
197 Exception / Interrupt Vector table
198 *----------------------------------------------------------------------------*/
199
200 #if defined ( __GNUC__ )
201 #pragma GCC diagnostic push
202 #pragma GCC diagnostic ignored "-Wpedantic"
203 #endif
204
205 extern const VECTOR_TABLE_Type __VECTOR_TABLE[];
206 const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
207 (VECTOR_TABLE_Type)(&__INITIAL_SP),/* Initial Stack Pointer */
208 Reset_Handler, /* Reset Handler */
209 NMI_Handler, /* -14: NMI Handler */
210 HardFault_Handler, /* -13: Hard Fault Handler */
211 MemManage_Handler, /* -12: MPU Fault Handler */
212 BusFault_Handler, /* -11: Bus Fault Handler */
213 UsageFault_Handler, /* -10: Usage Fault Handler */
214 SecureFault_Handler, /* -9: Secure Fault Handler */
215 0, /* Reserved */
216 0, /* Reserved */
217 0, /* Reserved */
218 SVC_Handler, /* -5: SVCall Handler */
219 DebugMon_Handler, /* -4: Debug Monitor Handler */
220 0, /* Reserved */
221 PendSV_Handler, /* -2: PendSV Handler */
222 SysTick_Handler, /* -1: SysTick Handler */
223 WWDG_IRQHandler, /* 0: Window WatchDog */
224 PVD_AVD_IRQHandler, /* 1: PVD/AVD through EXTI Line detection Interrupt */
225 RTC_IRQHandler, /* 2: RTC non-secure interrupt */
226 RTC_IRQHandler_S, /* 3: RTC secure interrupt */
227 TAMP_IRQHandler, /* 4: Tamper non-secure interrupt */
228 RAMCFG_IRQHandler, /* 5: RAMCFG global */
229 FLASH_IRQHandler, /* 6: FLASH non-secure global interrupt */
230 FLASH_IRQHandler_S, /* 7: FLASH secure global interrupt */
231 GTZC_IRQHandler, /* 8: Global TrustZone Controller interrupt */
232 RCC_IRQHandler, /* 9: RRCC non-secure global interrupts */
233 RCC_IRQHandler_S, /* 10: RRCC secure global interrupts */
234 EXTI0_IRQHandler, /* 11: REXTI Line0 */
235 EXTI1_IRQHandler, /* 12: REXTI Line1 */
236 EXTI2_IRQHandler, /* 13: REXTI Line2 */
237 EXTI3_IRQHandler, /* 14: REXTI Line3 */
238 EXTI4_IRQHandler, /* 15: REXTI Line4 */
239 EXTI5_IRQHandler, /* 16: REXTI Line5 */
240 EXTI6_IRQHandler, /* 17: REXTI Line6 */
241 EXTI7_IRQHandler, /* 18: REXTI Line7 */
242 EXTI8_IRQHandler, /* 19: REXTI Line8 */
243 EXTI9_IRQHandler, /* 20: REXTI Line9 */
244 EXTI10_IRQHandler, /* 21: EXTI Line10 */
245 EXTI11_IRQHandler, /* 22: EXTI Line11 */
246 EXTI12_IRQHandler, /* 23: EXTI Line12 */
247 EXTI13_IRQHandler, /* 24: EXTI Line13 */
248 EXTI14_IRQHandler, /* 25: EXTI Line14 */
249 EXTI15_IRQHandler, /* 26: EXTI Line15 */
250 IWDG_IRQHandler, /* 27: IWDG global interrupt */
251 #ifdef STM32U585xx
252 SAES_IRQHandler, /* 28:Secure AES global interrupt */
253 #else
254 0, /* 28: Reserved */
255 #endif
256 GPDMA1_Channel0_IRQHandler, /* 29: GPDMA1 Channel 0 global interrupt */
257 GPDMA1_Channel1_IRQHandler, /* 30: GPDMA1 Channel 1 global interrupt */
258 GPDMA1_Channel2_IRQHandler, /* 31: GPDMA1 Channel 2 global interrupt */
259 GPDMA1_Channel3_IRQHandler, /* 32: GPDMA1 Channel 3 global interrupt */
260 GPDMA1_Channel4_IRQHandler, /* 33: GPDMA1 Channel 4 global interrupt */
261 GPDMA1_Channel5_IRQHandler, /* 34: GPDMA1 Channel 5 global interrupt */
262 GPDMA1_Channel6_IRQHandler, /* 35: GPDMA1 Channel 6 global interrupt */
263 GPDMA1_Channel7_IRQHandler, /* 36: GPDMA1 Channel 7 global interrupt */
264 ADC1_IRQHandler, /* 37: ADC1 global interrupt */
265 DAC1_IRQHandler, /* 38: DAC1 global interrupt */
266 FDCAN1_IT0_IRQHandler, /* 39: FDCAN1 Interrupt 0 */
267 FDCAN1_IT1_IRQHandler, /* 40: FDCAN1 Interrupt 1 */
268 TIM1_BRK_IRQHandler, /* 41: TIM1 Break */
269 TIM1_UP_IRQHandler, /* 42: TIM1 Update */
270 TIM1_TRG_COM_IRQHandler, /* 43: TIM1 Trigger and Commutation */
271 TIM1_CC_IRQHandler, /* 44: TIM1 Capture Compare */
272 TIM2_IRQHandler, /* 45: TIM2 */
273 TIM3_IRQHandler, /* 46: TIM3 */
274 TIM4_IRQHandler, /* 47: TIM4 */
275 TIM5_IRQHandler, /* 48: TIM5 */
276 TIM6_IRQHandler, /* 49: TIM6 */
277 TIM7_IRQHandler, /* 50: TIM7 */
278 TIM8_BRK_IRQHandler, /* 51: TIM8 Break */
279 TIM8_UP_IRQHandler, /* 52: TIM8 Update */
280 TIM8_TRG_COM_IRQHandler, /* 53: TIM8 Trigger and Commutation */
281 TIM8_CC_IRQHandler, /* 54: TIM8 Capture Compare */
282 I2C1_EV_IRQHandler, /* 55: I2C1 Event */
283 I2C1_ER_IRQHandler, /* 56: I2C1 Error */
284 I2C2_EV_IRQHandler, /* 57: I2C2 Event */
285 I2C2_ER_IRQHandler, /* 58: I2C2 Error */
286 SPI1_IRQHandler, /* 59: SPI1 */
287 SPI2_IRQHandler, /* 60: SPI2 */
288 USART1_IRQHandler, /* 61: USART1 */
289 USART2_IRQHandler, /* 62: USART2 */
290 USART3_IRQHandler, /* 63: USART3 */
291 UART4_IRQHandler, /* 64: UART4 */
292 UART5_IRQHandler, /* 65: UART5 */
293 LPUART1_IRQHandler, /* 66: LP UART1 */
294 LPTIM1_IRQHandler, /* 67: LP TIM1 */
295 LPTIM2_IRQHandler, /* 68: LP TIM2 */
296 TIM15_IRQHandler, /* 69: TIM15 */
297 TIM16_IRQHandler, /* 70: TIM16 */
298 TIM17_IRQHandler, /* 71: TIM17 */
299 COMP_IRQHandler, /* 72: COMP1&2 */
300 OTG_FS_IRQHandler, /* 73: USB OTG FS global interrupt */
301 CRS_IRQHandler, /* 74: CRS */
302 FMC_IRQHandler, /* 75: FMC */
303 OCTOSPI1_IRQHandler, /* 76: OctoSPI1 global interrupt */
304 PWR_S3WU_IRQHandler, /* 77: PWR wake up from Stop3 interrupt */
305 SDMMC1_IRQHandler, /* 78: SDMMC1 global interrupt */
306 SDMMC2_IRQHandler, /* 79: SDMMC2 global interrupt*/
307 GPDMA1_Channel8_IRQHandler, /* 80: GPDMA1 Channel 8 global interrupt*/
308 GPDMA1_Channel9_IRQHandler, /* 81: GPDMA1 Channel 9 global interrupt*/
309 GPDMA1_Channel10_IRQHandler, /* 82: GPDMA1 Channel 10 global interrupt*/
310 GPDMA1_Channel11_IRQHandler, /* 83: GPDMA1 Channel 11 global interrupt*/
311 GPDMA1_Channel12_IRQHandler, /* 84: GPDMA1 Channel 12 global interrupt*/
312 GPDMA1_Channel13_IRQHandler, /* 85: GPDMA1 Channel 13 global interrupt*/
313 GPDMA1_Channel14_IRQHandler, /* 86: GPDMA1 Channel 14 global interrupt*/
314 GPDMA1_Channel15_IRQHandler, /* 87: GPDMA1 Channel 15 global interrupt*/
315 I2C3_EV_IRQHandler, /* 88: I2C3 event */
316 I2C3_ER_IRQHandler, /* 89: I2C3 error */
317 SAI1_IRQHandler, /* 90: Serial Audio Interface 1 global interrupt */
318 SAI2_IRQHandler, /* 91: Serial Audio Interface 2 global interrupt */
319 TSC_IRQHandler, /* 92: Touch Sense Controller global interrupt */
320 #ifdef STM32U585xx
321 AES_IRQHandler, /* 93: AES global interrupt */
322 #else
323 0, /* 93: Reserved */
324 #endif
325 RNG_IRQHandler, /* 94: RNG global interrupt */
326 FPU_IRQHandler, /* 95: FPU */
327 HASH_IRQHandler, /* 96: HASH global interrupt */
328 #ifdef STM32U585xx
329 PKA_IRQHandler, /* 97: PKA global interrupt */
330 #else
331 0, /* 97: Reserved */
332 #endif
333 LPTIM3_IRQHandler, /* 98: LP TIM3 */
334 SPI3_IRQHandler, /* 99: SPI3 */
335 I2C4_ER_IRQHandler, /* 100: I2C4 error */
336 I2C4_EV_IRQHandler, /* 101: I2C4 event */
337 MDF1_FLT0_IRQHandler, /* 102: MDF1 Filter 0 global interrupt */
338 MDF1_FLT1_IRQHandler, /* 103: MDF1 Filter 1 global interrupt */
339 MDF1_FLT2_IRQHandler, /* 104: MDF1 Filter 2 global interrupt */
340 MDF1_FLT3_IRQHandler, /* 105: MDF1 Filter 3 global interrupt */
341 UCPD1_IRQHandler, /* 106: UCPD1 global interrupt */
342 ICACHE_IRQHandler, /* 107: Instruction cache global interrupt*/
343 #ifdef STM32U585xx
344 OTFDEC1_IRQHandler, /* 108: OTFDEC1 global interrupt */
345 OTFDEC2_IRQHandler, /* 108: OTFDEC2 global interrupt */
346 #else
347 0, /* 108: Reserved */
348 0, /* 109: Reserved */
349 #endif
350 LPTIM4_IRQHandler, /* 110: LPTIM4 global interrupt */
351 DCACHE1_IRQHandler, /* 111: Data cache global interrupt */
352 ADF1_IRQHandler, /* 112: ADF interrupt */
353 ADC4_IRQHandler, /* 113: ADC4 (12bits) global interrupt */
354 LPDMA1_Channel0_IRQHandler, /* 114: LPDMA1 SmartRun Channel 0 global interrupt */
355 LPDMA1_Channel1_IRQHandler, /* 115: LPDMA1 SmartRun Channel 0 global interrupt */
356 LPDMA1_Channel2_IRQHandler, /* 116: LPDMA1 SmartRun Channel 0 global interrupt */
357 LPDMA1_Channel3_IRQHandler, /* 117: LPDMA1 SmartRun Channel 0 global interrupt */
358 DMA2D_IRQHandler, /* 118: DMA2D global interrupt */
359 DCMI_PSSI_IRQHandler, /* 119: DCMI/PSSI global interrupt */
360 OCTOSPI2_IRQHandler, /* 120: OCTOSPI2 global interrupt */
361 MDF1_FLT4_IRQHandler, /* 121: MDF1 Filter 4 global interrupt */
362 MDF1_FLT5_IRQHandler, /* 122: MDF1 Filter 5 global interrupt */
363 CORDIC_IRQHandler, /* 123: CORDIC global interrupt */
364 FMAC_IRQHandler, /* 124: FMAC global interrupt */
365 };
366 #if defined ( __GNUC__ )
367 #pragma GCC diagnostic pop
368 #endif
369
370 /*----------------------------------------------------------------------------
371 Reset Handler called on controller reset
372 *----------------------------------------------------------------------------*/
Reset_Handler(void)373 void Reset_Handler(void)
374 {
375 __set_PSP((uint32_t)(&__INITIAL_SP));
376
377 __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
378 __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
379
380 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
381 __IO uint32_t tmp;
382
383 /* disable IRQ is removed */
384 /*__disable_irq();*/
385 /* Tamp IRQ prio is set to highest , and IRQ is enabled */
386 NVIC_SetPriority(TAMP_IRQn, 0);
387 NVIC_EnableIRQ(TAMP_IRQn);
388
389 SCB->VTOR = (uint32_t) &__VECTOR_TABLE[0];
390 /* Lock Secure Vector Table */
391 /* Enable SYSCFG interface clock */
392 RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN;
393 /* Delay after an RCC peripheral clock enabling */
394 tmp = RCC->APB3ENR;
395 (void)tmp;
396 SYSCFG->CSLCKR |= SYSCFG_CSLCKR_LOCKSVTAIRCR;
397 #endif
398 SystemInit(); /* CMSIS System Initialization */
399 __PROGRAM_START(); /* Enter PreMain (C library entry point) */
400 }
401
